1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "asm/assembler.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "code/compiledIC.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "gc/shared/gc_globals.hpp"
39 #include "nativeInst_aarch64.hpp"
40 #include "oops/objArrayKlass.hpp"
41 #include "runtime/frame.inline.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "runtime/stubRoutines.hpp"
44 #include "utilities/powerOfTwo.hpp"
45 #include "vmreg_aarch64.inline.hpp"
46
47
48 #ifndef PRODUCT
49 #define COMMENT(x) do { __ block_comment(x); } while (0)
50 #else
51 #define COMMENT(x)
52 #endif
53
54 NEEDS_CLEANUP // remove this definitions ?
55 const Register SYNC_header = r0; // synchronization header
56 const Register SHIFT_count = r0; // where count for shift operations must be
57
58 #define __ _masm->
59
60
61 static void select_different_registers(Register preserve,
62 Register extra,
63 Register &tmp1,
64 Register &tmp2) {
65 if (tmp1 == preserve) {
66 assert_different_registers(tmp1, tmp2, extra);
67 tmp1 = extra;
68 } else if (tmp2 == preserve) {
69 assert_different_registers(tmp1, tmp2, extra);
70 tmp2 = extra;
71 }
72 assert_different_registers(preserve, tmp1, tmp2);
73 }
74
75
76
77 static void select_different_registers(Register preserve,
78 Register extra,
79 Register &tmp1,
80 Register &tmp2,
81 Register &tmp3) {
82 if (tmp1 == preserve) {
83 assert_different_registers(tmp1, tmp2, tmp3, extra);
84 tmp1 = extra;
85 } else if (tmp2 == preserve) {
86 assert_different_registers(tmp1, tmp2, tmp3, extra);
87 tmp2 = extra;
88 } else if (tmp3 == preserve) {
89 assert_different_registers(tmp1, tmp2, tmp3, extra);
90 tmp3 = extra;
91 }
92 assert_different_registers(preserve, tmp1, tmp2, tmp3);
93 }
94
95
96 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
97
98
99 LIR_Opr LIR_Assembler::receiverOpr() {
100 return FrameMap::receiver_opr;
101 }
102
103 LIR_Opr LIR_Assembler::osrBufferPointer() {
104 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
105 }
106
107 //--------------fpu register translations-----------------------
108
109
110 address LIR_Assembler::float_constant(float f) {
111 address const_addr = __ float_constant(f);
112 if (const_addr == nullptr) {
113 bailout("const section overflow");
114 return __ code()->consts()->start();
115 } else {
116 return const_addr;
117 }
118 }
119
120
121 address LIR_Assembler::double_constant(double d) {
122 address const_addr = __ double_constant(d);
123 if (const_addr == nullptr) {
124 bailout("const section overflow");
125 return __ code()->consts()->start();
126 } else {
127 return const_addr;
128 }
129 }
130
131 address LIR_Assembler::int_constant(jlong n) {
132 address const_addr = __ long_constant(n);
133 if (const_addr == nullptr) {
134 bailout("const section overflow");
135 return __ code()->consts()->start();
136 } else {
137 return const_addr;
138 }
139 }
140
141 void LIR_Assembler::breakpoint() { Unimplemented(); }
142
143 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
144
145 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
146
147 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
148 //-------------------------------------------
149
150 static Register as_reg(LIR_Opr op) {
151 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
152 }
153
154 static jlong as_long(LIR_Opr data) {
155 jlong result;
156 switch (data->type()) {
157 case T_INT:
158 result = (data->as_jint());
159 break;
160 case T_LONG:
161 result = (data->as_jlong());
162 break;
163 default:
164 ShouldNotReachHere();
165 result = 0; // unreachable
166 }
167 return result;
168 }
169
170 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
171 Register base = addr->base()->as_pointer_register();
172 LIR_Opr opr = addr->index();
173 if (opr->is_cpu_register()) {
174 Register index;
175 if (opr->is_single_cpu())
176 index = opr->as_register();
177 else
178 index = opr->as_register_lo();
179 assert(addr->disp() == 0, "must be");
180 switch(opr->type()) {
181 case T_INT:
182 return Address(base, index, Address::sxtw(addr->scale()));
183 case T_LONG:
184 return Address(base, index, Address::lsl(addr->scale()));
185 default:
186 ShouldNotReachHere();
187 }
188 } else {
189 assert(addr->scale() == 0,
190 "expected for immediate operand, was: %d", addr->scale());
191 ptrdiff_t offset = ptrdiff_t(addr->disp());
192 // NOTE: Does not handle any 16 byte vector access.
193 const uint type_size = type2aelembytes(addr->type(), true);
194 return __ legitimize_address(Address(base, offset), type_size, tmp);
195 }
196 return Address();
197 }
198
199 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
200 ShouldNotReachHere();
201 return Address();
202 }
203
204 Address LIR_Assembler::as_Address(LIR_Address* addr) {
205 return as_Address(addr, rscratch1);
206 }
207
208 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
209 return as_Address(addr, rscratch1); // Ouch
210 // FIXME: This needs to be much more clever. See x86.
211 }
212
213 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
214 // not encodable as a base + (immediate) offset, generate an explicit address
215 // calculation to hold the address in a temporary register.
216 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
217 precond(size == 4 || size == 8);
218 Address addr = frame_map()->address_for_slot(index, adjust);
219 precond(addr.getMode() == Address::base_plus_offset);
220 precond(addr.base() == sp);
221 precond(addr.offset() > 0);
222 uint mask = size - 1;
223 assert((addr.offset() & mask) == 0, "scaled offsets only");
224 return __ legitimize_address(addr, size, tmp);
225 }
226
227 void LIR_Assembler::osr_entry() {
228 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
229 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
230 ValueStack* entry_state = osr_entry->state();
231 int number_of_locks = entry_state->locks_size();
232
233 // we jump here if osr happens with the interpreter
234 // state set up to continue at the beginning of the
235 // loop that triggered osr - in particular, we have
236 // the following registers setup:
237 //
238 // r2: osr buffer
239 //
240
241 // build frame
242 ciMethod* m = compilation()->method();
243 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
244
245 // OSR buffer is
246 //
247 // locals[nlocals-1..0]
248 // monitors[0..number_of_locks]
249 //
250 // locals is a direct copy of the interpreter frame so in the osr buffer
251 // so first slot in the local array is the last local from the interpreter
252 // and last slot is local[0] (receiver) from the interpreter
253 //
254 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
255 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
256 // in the interpreter frame (the method lock if a sync method)
257
258 // Initialize monitors in the compiled activation.
259 // r2: pointer to osr buffer
260 //
261 // All other registers are dead at this point and the locals will be
262 // copied into place by code emitted in the IR.
263
264 Register OSR_buf = osrBufferPointer()->as_pointer_register();
265 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
266 int monitor_offset = BytesPerWord * method()->max_locals() +
267 (2 * BytesPerWord) * (number_of_locks - 1);
268 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
269 // the OSR buffer using 2 word entries: first the lock and then
270 // the oop.
271 for (int i = 0; i < number_of_locks; i++) {
272 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
273 #ifdef ASSERT
274 // verify the interpreter's monitor has a non-null object
275 {
276 Label L;
277 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
278 __ cbnz(rscratch1, L);
279 __ stop("locked object is null");
280 __ bind(L);
281 }
282 #endif
283 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
284 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
285 __ str(r19, frame_map()->address_for_monitor_lock(i));
286 __ str(r20, frame_map()->address_for_monitor_object(i));
287 }
288 }
289 }
290
291
292 // inline cache check; done before the frame is built.
293 int LIR_Assembler::check_icache() {
294 return __ ic_check(CodeEntryAlignment);
295 }
296
297 void LIR_Assembler::clinit_barrier(ciMethod* method) {
298 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
299 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
300
301 Label L_skip_barrier;
302
303 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
304 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
305 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
306 __ bind(L_skip_barrier);
307 }
308
309 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
310 if (o == nullptr) {
311 __ mov(reg, zr);
312 } else {
313 __ movoop(reg, o);
314 }
315 }
316
317 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
318 address target = nullptr;
319 relocInfo::relocType reloc_type = relocInfo::none;
320
321 switch (patching_id(info)) {
322 case PatchingStub::access_field_id:
323 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
324 reloc_type = relocInfo::section_word_type;
325 break;
326 case PatchingStub::load_klass_id:
327 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
328 reloc_type = relocInfo::metadata_type;
329 break;
330 case PatchingStub::load_mirror_id:
331 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
332 reloc_type = relocInfo::oop_type;
333 break;
334 case PatchingStub::load_appendix_id:
335 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
336 reloc_type = relocInfo::oop_type;
337 break;
338 default: ShouldNotReachHere();
339 }
340
341 __ far_call(RuntimeAddress(target));
342 add_call_info_here(info);
343 }
344
345 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
346 deoptimize_trap(info);
347 }
348
349
350 // This specifies the rsp decrement needed to build the frame
351 int LIR_Assembler::initial_frame_size_in_bytes() const {
352 // if rounding, must let FrameMap know!
353
354 return in_bytes(frame_map()->framesize_in_bytes());
355 }
356
357
358 int LIR_Assembler::emit_exception_handler() {
359 // generate code for exception handler
360 address handler_base = __ start_a_stub(exception_handler_size());
361 if (handler_base == nullptr) {
362 // not enough space left for the handler
363 bailout("exception handler overflow");
364 return -1;
365 }
366
367 int offset = code_offset();
368
369 // the exception oop and pc are in r0, and r3
370 // no other registers need to be preserved, so invalidate them
371 __ invalidate_registers(false, true, true, false, true, true);
372
373 // check that there is really an exception
374 __ verify_not_null_oop(r0);
375
376 // search an exception handler (r0: exception oop, r3: throwing pc)
377 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
378 __ should_not_reach_here();
379 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
380 __ end_a_stub();
381
382 return offset;
383 }
384
385
386 // Emit the code to remove the frame from the stack in the exception
387 // unwind path.
388 int LIR_Assembler::emit_unwind_handler() {
389 #ifndef PRODUCT
390 if (CommentedAssembly) {
391 _masm->block_comment("Unwind handler");
392 }
393 #endif
394
395 int offset = code_offset();
396
397 // Fetch the exception from TLS and clear out exception related thread state
398 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
399 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
400 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
401
402 __ bind(_unwind_handler_entry);
403 __ verify_not_null_oop(r0);
404 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
405 __ mov(r19, r0); // Preserve the exception
406 }
407
408 // Perform needed unlocking
409 MonitorExitStub* stub = nullptr;
410 if (method()->is_synchronized()) {
411 monitor_address(0, FrameMap::r0_opr);
412 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
413 if (LockingMode == LM_MONITOR) {
414 __ b(*stub->entry());
415 } else {
416 __ unlock_object(r5, r4, r0, r6, *stub->entry());
417 }
418 __ bind(*stub->continuation());
419 }
420
421 if (compilation()->env()->dtrace_method_probes()) {
422 __ mov(c_rarg0, rthread);
423 __ mov_metadata(c_rarg1, method()->constant_encoding());
424 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
425 }
426
427 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
428 __ mov(r0, r19); // Restore the exception
429 }
430
431 // remove the activation and dispatch to the unwind handler
432 __ block_comment("remove_frame and dispatch to the unwind handler");
433 __ remove_frame(initial_frame_size_in_bytes());
434 __ far_jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
435
436 // Emit the slow path assembly
437 if (stub != nullptr) {
438 stub->emit_code(this);
439 }
440
441 return offset;
442 }
443
444
445 int LIR_Assembler::emit_deopt_handler() {
446 // generate code for exception handler
447 address handler_base = __ start_a_stub(deopt_handler_size());
448 if (handler_base == nullptr) {
449 // not enough space left for the handler
450 bailout("deopt handler overflow");
451 return -1;
452 }
453
454 int offset = code_offset();
455
456 __ adr(lr, pc());
457 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
458 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
459 __ end_a_stub();
460
461 return offset;
462 }
463
464 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
465 _masm->code_section()->relocate(adr, relocInfo::poll_type);
466 int pc_offset = code_offset();
467 flush_debug_info(pc_offset);
468 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
469 if (info->exception_handlers() != nullptr) {
470 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
471 }
472 }
473
474 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
475 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
476
477 // Pop the stack before the safepoint code
478 __ remove_frame(initial_frame_size_in_bytes());
479
480 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
481 __ reserved_stack_check();
482 }
483
484 code_stub->set_safepoint_offset(__ offset());
485 __ relocate(relocInfo::poll_return_type);
486 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
487 __ ret(lr);
488 }
489
490 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
491 guarantee(info != nullptr, "Shouldn't be null");
492 __ get_polling_page(rscratch1, relocInfo::poll_type);
493 add_debug_info_for_branch(info); // This isn't just debug info:
494 // it's the oop map
495 __ read_polling_page(rscratch1, relocInfo::poll_type);
496 return __ offset();
497 }
498
499
500 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
501 if (from_reg == r31_sp)
502 from_reg = sp;
503 if (to_reg == r31_sp)
504 to_reg = sp;
505 __ mov(to_reg, from_reg);
506 }
507
508 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
509
510
511 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
512 assert(src->is_constant(), "should not call otherwise");
513 assert(dest->is_register(), "should not call otherwise");
514 LIR_Const* c = src->as_constant_ptr();
515
516 switch (c->type()) {
517 case T_INT: {
518 assert(patch_code == lir_patch_none, "no patching handled here");
519 __ movw(dest->as_register(), c->as_jint());
520 break;
521 }
522
523 case T_ADDRESS: {
524 assert(patch_code == lir_patch_none, "no patching handled here");
525 __ mov(dest->as_register(), c->as_jint());
526 break;
527 }
528
529 case T_LONG: {
530 assert(patch_code == lir_patch_none, "no patching handled here");
531 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
532 break;
533 }
534
535 case T_OBJECT: {
536 if (patch_code == lir_patch_none) {
537 jobject2reg(c->as_jobject(), dest->as_register());
538 } else {
539 jobject2reg_with_patching(dest->as_register(), info);
540 }
541 break;
542 }
543
544 case T_METADATA: {
545 if (patch_code != lir_patch_none) {
546 klass2reg_with_patching(dest->as_register(), info);
547 } else {
548 __ mov_metadata(dest->as_register(), c->as_metadata());
549 }
550 break;
551 }
552
553 case T_FLOAT: {
554 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
555 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
556 } else {
557 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
558 __ ldrs(dest->as_float_reg(), Address(rscratch1));
559 }
560 break;
561 }
562
563 case T_DOUBLE: {
564 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
565 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
566 } else {
567 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
568 __ ldrd(dest->as_double_reg(), Address(rscratch1));
569 }
570 break;
571 }
572
573 default:
574 ShouldNotReachHere();
575 }
576 }
577
578 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
579 LIR_Const* c = src->as_constant_ptr();
580 switch (c->type()) {
581 case T_OBJECT:
582 {
583 if (! c->as_jobject())
584 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
585 else {
586 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
587 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
588 }
589 }
590 break;
591 case T_ADDRESS:
592 {
593 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
594 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
595 }
596 case T_INT:
597 case T_FLOAT:
598 {
599 Register reg = zr;
600 if (c->as_jint_bits() == 0)
601 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
602 else {
603 __ movw(rscratch1, c->as_jint_bits());
604 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
605 }
606 }
607 break;
608 case T_LONG:
609 case T_DOUBLE:
610 {
611 Register reg = zr;
612 if (c->as_jlong_bits() == 0)
613 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
614 lo_word_offset_in_bytes));
615 else {
616 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
617 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
618 lo_word_offset_in_bytes));
619 }
620 }
621 break;
622 default:
623 ShouldNotReachHere();
624 }
625 }
626
627 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
628 assert(src->is_constant(), "should not call otherwise");
629 LIR_Const* c = src->as_constant_ptr();
630 LIR_Address* to_addr = dest->as_address_ptr();
631
632 void (Assembler::* insn)(Register Rt, const Address &adr);
633
634 switch (type) {
635 case T_ADDRESS:
636 assert(c->as_jint() == 0, "should be");
637 insn = &Assembler::str;
638 break;
639 case T_LONG:
640 assert(c->as_jlong() == 0, "should be");
641 insn = &Assembler::str;
642 break;
643 case T_INT:
644 assert(c->as_jint() == 0, "should be");
645 insn = &Assembler::strw;
646 break;
647 case T_OBJECT:
648 case T_ARRAY:
649 assert(c->as_jobject() == nullptr, "should be");
650 if (UseCompressedOops && !wide) {
651 insn = &Assembler::strw;
652 } else {
653 insn = &Assembler::str;
654 }
655 break;
656 case T_CHAR:
657 case T_SHORT:
658 assert(c->as_jint() == 0, "should be");
659 insn = &Assembler::strh;
660 break;
661 case T_BOOLEAN:
662 case T_BYTE:
663 assert(c->as_jint() == 0, "should be");
664 insn = &Assembler::strb;
665 break;
666 default:
667 ShouldNotReachHere();
668 insn = &Assembler::str; // unreachable
669 }
670
671 if (info) add_debug_info_for_null_check_here(info);
672 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
673 }
674
675 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
676 assert(src->is_register(), "should not call otherwise");
677 assert(dest->is_register(), "should not call otherwise");
678
679 // move between cpu-registers
680 if (dest->is_single_cpu()) {
681 if (src->type() == T_LONG) {
682 // Can do LONG -> OBJECT
683 move_regs(src->as_register_lo(), dest->as_register());
684 return;
685 }
686 assert(src->is_single_cpu(), "must match");
687 if (src->type() == T_OBJECT) {
688 __ verify_oop(src->as_register());
689 }
690 move_regs(src->as_register(), dest->as_register());
691
692 } else if (dest->is_double_cpu()) {
693 if (is_reference_type(src->type())) {
694 // Surprising to me but we can see move of a long to t_object
695 __ verify_oop(src->as_register());
696 move_regs(src->as_register(), dest->as_register_lo());
697 return;
698 }
699 assert(src->is_double_cpu(), "must match");
700 Register f_lo = src->as_register_lo();
701 Register f_hi = src->as_register_hi();
702 Register t_lo = dest->as_register_lo();
703 Register t_hi = dest->as_register_hi();
704 assert(f_hi == f_lo, "must be same");
705 assert(t_hi == t_lo, "must be same");
706 move_regs(f_lo, t_lo);
707
708 } else if (dest->is_single_fpu()) {
709 __ fmovs(dest->as_float_reg(), src->as_float_reg());
710
711 } else if (dest->is_double_fpu()) {
712 __ fmovd(dest->as_double_reg(), src->as_double_reg());
713
714 } else {
715 ShouldNotReachHere();
716 }
717 }
718
719 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
720 precond(src->is_register() && dest->is_stack());
721
722 uint const c_sz32 = sizeof(uint32_t);
723 uint const c_sz64 = sizeof(uint64_t);
724
725 if (src->is_single_cpu()) {
726 int index = dest->single_stack_ix();
727 if (is_reference_type(type)) {
728 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
729 __ verify_oop(src->as_register());
730 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
731 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
732 } else {
733 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
734 }
735
736 } else if (src->is_double_cpu()) {
737 int index = dest->double_stack_ix();
738 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
739 __ str(src->as_register_lo(), dest_addr_LO);
740
741 } else if (src->is_single_fpu()) {
742 int index = dest->single_stack_ix();
743 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
744
745 } else if (src->is_double_fpu()) {
746 int index = dest->double_stack_ix();
747 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
748
749 } else {
750 ShouldNotReachHere();
751 }
752 }
753
754
755 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
756 LIR_Address* to_addr = dest->as_address_ptr();
757 PatchingStub* patch = nullptr;
758 Register compressed_src = rscratch1;
759
760 if (patch_code != lir_patch_none) {
761 deoptimize_trap(info);
762 return;
763 }
764
765 if (is_reference_type(type)) {
766 __ verify_oop(src->as_register());
767
768 if (UseCompressedOops && !wide) {
769 __ encode_heap_oop(compressed_src, src->as_register());
770 } else {
771 compressed_src = src->as_register();
772 }
773 }
774
775 int null_check_here = code_offset();
776 switch (type) {
777 case T_FLOAT: {
778 __ strs(src->as_float_reg(), as_Address(to_addr));
779 break;
780 }
781
782 case T_DOUBLE: {
783 __ strd(src->as_double_reg(), as_Address(to_addr));
784 break;
785 }
786
787 case T_ARRAY: // fall through
788 case T_OBJECT: // fall through
789 if (UseCompressedOops && !wide) {
790 __ strw(compressed_src, as_Address(to_addr, rscratch2));
791 } else {
792 __ str(compressed_src, as_Address(to_addr));
793 }
794 break;
795 case T_METADATA:
796 // We get here to store a method pointer to the stack to pass to
797 // a dtrace runtime call. This can't work on 64 bit with
798 // compressed klass ptrs: T_METADATA can be a compressed klass
799 // ptr or a 64 bit method pointer.
800 ShouldNotReachHere();
801 __ str(src->as_register(), as_Address(to_addr));
802 break;
803 case T_ADDRESS:
804 __ str(src->as_register(), as_Address(to_addr));
805 break;
806 case T_INT:
807 __ strw(src->as_register(), as_Address(to_addr));
808 break;
809
810 case T_LONG: {
811 __ str(src->as_register_lo(), as_Address_lo(to_addr));
812 break;
813 }
814
815 case T_BYTE: // fall through
816 case T_BOOLEAN: {
817 __ strb(src->as_register(), as_Address(to_addr));
818 break;
819 }
820
821 case T_CHAR: // fall through
822 case T_SHORT:
823 __ strh(src->as_register(), as_Address(to_addr));
824 break;
825
826 default:
827 ShouldNotReachHere();
828 }
829 if (info != nullptr) {
830 add_debug_info_for_null_check(null_check_here, info);
831 }
832 }
833
834
835 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
836 precond(src->is_stack() && dest->is_register());
837
838 uint const c_sz32 = sizeof(uint32_t);
839 uint const c_sz64 = sizeof(uint64_t);
840
841 if (dest->is_single_cpu()) {
842 int index = src->single_stack_ix();
843 if (is_reference_type(type)) {
844 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
845 __ verify_oop(dest->as_register());
846 } else if (type == T_METADATA || type == T_ADDRESS) {
847 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
848 } else {
849 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
850 }
851
852 } else if (dest->is_double_cpu()) {
853 int index = src->double_stack_ix();
854 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
855 __ ldr(dest->as_register_lo(), src_addr_LO);
856
857 } else if (dest->is_single_fpu()) {
858 int index = src->single_stack_ix();
859 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
860
861 } else if (dest->is_double_fpu()) {
862 int index = src->double_stack_ix();
863 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
864
865 } else {
866 ShouldNotReachHere();
867 }
868 }
869
870
871 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
872 address target = nullptr;
873 relocInfo::relocType reloc_type = relocInfo::none;
874
875 switch (patching_id(info)) {
876 case PatchingStub::access_field_id:
877 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
878 reloc_type = relocInfo::section_word_type;
879 break;
880 case PatchingStub::load_klass_id:
881 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
882 reloc_type = relocInfo::metadata_type;
883 break;
884 case PatchingStub::load_mirror_id:
885 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
886 reloc_type = relocInfo::oop_type;
887 break;
888 case PatchingStub::load_appendix_id:
889 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
890 reloc_type = relocInfo::oop_type;
891 break;
892 default: ShouldNotReachHere();
893 }
894
895 __ far_call(RuntimeAddress(target));
896 add_call_info_here(info);
897 }
898
899 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
900
901 LIR_Opr temp;
902 if (type == T_LONG || type == T_DOUBLE)
903 temp = FrameMap::rscratch1_long_opr;
904 else
905 temp = FrameMap::rscratch1_opr;
906
907 stack2reg(src, temp, src->type());
908 reg2stack(temp, dest, dest->type());
909 }
910
911
912 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
913 LIR_Address* addr = src->as_address_ptr();
914 LIR_Address* from_addr = src->as_address_ptr();
915
916 if (addr->base()->type() == T_OBJECT) {
917 __ verify_oop(addr->base()->as_pointer_register());
918 }
919
920 if (patch_code != lir_patch_none) {
921 deoptimize_trap(info);
922 return;
923 }
924
925 if (info != nullptr) {
926 add_debug_info_for_null_check_here(info);
927 }
928 int null_check_here = code_offset();
929 switch (type) {
930 case T_FLOAT: {
931 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
932 break;
933 }
934
935 case T_DOUBLE: {
936 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
937 break;
938 }
939
940 case T_ARRAY: // fall through
941 case T_OBJECT: // fall through
942 if (UseCompressedOops && !wide) {
943 __ ldrw(dest->as_register(), as_Address(from_addr));
944 } else {
945 __ ldr(dest->as_register(), as_Address(from_addr));
946 }
947 break;
948 case T_METADATA:
949 // We get here to store a method pointer to the stack to pass to
950 // a dtrace runtime call. This can't work on 64 bit with
951 // compressed klass ptrs: T_METADATA can be a compressed klass
952 // ptr or a 64 bit method pointer.
953 ShouldNotReachHere();
954 __ ldr(dest->as_register(), as_Address(from_addr));
955 break;
956 case T_ADDRESS:
957 __ ldr(dest->as_register(), as_Address(from_addr));
958 break;
959 case T_INT:
960 __ ldrw(dest->as_register(), as_Address(from_addr));
961 break;
962
963 case T_LONG: {
964 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
965 break;
966 }
967
968 case T_BYTE:
969 __ ldrsb(dest->as_register(), as_Address(from_addr));
970 break;
971 case T_BOOLEAN: {
972 __ ldrb(dest->as_register(), as_Address(from_addr));
973 break;
974 }
975
976 case T_CHAR:
977 __ ldrh(dest->as_register(), as_Address(from_addr));
978 break;
979 case T_SHORT:
980 __ ldrsh(dest->as_register(), as_Address(from_addr));
981 break;
982
983 default:
984 ShouldNotReachHere();
985 }
986
987 if (is_reference_type(type)) {
988 if (UseCompressedOops && !wide) {
989 __ decode_heap_oop(dest->as_register());
990 }
991
992 __ verify_oop(dest->as_register());
993 }
994 }
995
996
997 int LIR_Assembler::array_element_size(BasicType type) const {
998 int elem_size = type2aelembytes(type);
999 return exact_log2(elem_size);
1000 }
1001
1002
1003 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1004 switch (op->code()) {
1005 case lir_idiv:
1006 case lir_irem:
1007 arithmetic_idiv(op->code(),
1008 op->in_opr1(),
1009 op->in_opr2(),
1010 op->in_opr3(),
1011 op->result_opr(),
1012 op->info());
1013 break;
1014 case lir_fmad:
1015 __ fmaddd(op->result_opr()->as_double_reg(),
1016 op->in_opr1()->as_double_reg(),
1017 op->in_opr2()->as_double_reg(),
1018 op->in_opr3()->as_double_reg());
1019 break;
1020 case lir_fmaf:
1021 __ fmadds(op->result_opr()->as_float_reg(),
1022 op->in_opr1()->as_float_reg(),
1023 op->in_opr2()->as_float_reg(),
1024 op->in_opr3()->as_float_reg());
1025 break;
1026 default: ShouldNotReachHere(); break;
1027 }
1028 }
1029
1030 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1031 #ifdef ASSERT
1032 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1033 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1034 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1035 #endif
1036
1037 if (op->cond() == lir_cond_always) {
1038 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1039 __ b(*(op->label()));
1040 } else {
1041 Assembler::Condition acond;
1042 if (op->code() == lir_cond_float_branch) {
1043 bool is_unordered = (op->ublock() == op->block());
1044 // Assembler::EQ does not permit unordered branches, so we add
1045 // another branch here. Likewise, Assembler::NE does not permit
1046 // ordered branches.
1047 if ((is_unordered && op->cond() == lir_cond_equal)
1048 || (!is_unordered && op->cond() == lir_cond_notEqual))
1049 __ br(Assembler::VS, *(op->ublock()->label()));
1050 switch(op->cond()) {
1051 case lir_cond_equal: acond = Assembler::EQ; break;
1052 case lir_cond_notEqual: acond = Assembler::NE; break;
1053 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1054 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1055 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1056 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1057 default: ShouldNotReachHere();
1058 acond = Assembler::EQ; // unreachable
1059 }
1060 } else {
1061 switch (op->cond()) {
1062 case lir_cond_equal: acond = Assembler::EQ; break;
1063 case lir_cond_notEqual: acond = Assembler::NE; break;
1064 case lir_cond_less: acond = Assembler::LT; break;
1065 case lir_cond_lessEqual: acond = Assembler::LE; break;
1066 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1067 case lir_cond_greater: acond = Assembler::GT; break;
1068 case lir_cond_belowEqual: acond = Assembler::LS; break;
1069 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1070 default: ShouldNotReachHere();
1071 acond = Assembler::EQ; // unreachable
1072 }
1073 }
1074 __ br(acond,*(op->label()));
1075 }
1076 }
1077
1078
1079
1080 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1081 LIR_Opr src = op->in_opr();
1082 LIR_Opr dest = op->result_opr();
1083
1084 switch (op->bytecode()) {
1085 case Bytecodes::_i2f:
1086 {
1087 __ scvtfws(dest->as_float_reg(), src->as_register());
1088 break;
1089 }
1090 case Bytecodes::_i2d:
1091 {
1092 __ scvtfwd(dest->as_double_reg(), src->as_register());
1093 break;
1094 }
1095 case Bytecodes::_l2d:
1096 {
1097 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1098 break;
1099 }
1100 case Bytecodes::_l2f:
1101 {
1102 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1103 break;
1104 }
1105 case Bytecodes::_f2d:
1106 {
1107 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1108 break;
1109 }
1110 case Bytecodes::_d2f:
1111 {
1112 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1113 break;
1114 }
1115 case Bytecodes::_i2c:
1116 {
1117 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1118 break;
1119 }
1120 case Bytecodes::_i2l:
1121 {
1122 __ sxtw(dest->as_register_lo(), src->as_register());
1123 break;
1124 }
1125 case Bytecodes::_i2s:
1126 {
1127 __ sxth(dest->as_register(), src->as_register());
1128 break;
1129 }
1130 case Bytecodes::_i2b:
1131 {
1132 __ sxtb(dest->as_register(), src->as_register());
1133 break;
1134 }
1135 case Bytecodes::_l2i:
1136 {
1137 _masm->block_comment("FIXME: This could be a no-op");
1138 __ uxtw(dest->as_register(), src->as_register_lo());
1139 break;
1140 }
1141 case Bytecodes::_d2l:
1142 {
1143 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1144 break;
1145 }
1146 case Bytecodes::_f2i:
1147 {
1148 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1149 break;
1150 }
1151 case Bytecodes::_f2l:
1152 {
1153 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1154 break;
1155 }
1156 case Bytecodes::_d2i:
1157 {
1158 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1159 break;
1160 }
1161 default: ShouldNotReachHere();
1162 }
1163 }
1164
1165 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1166 if (op->init_check()) {
1167 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1168 __ ldarb(rscratch1, rscratch1);
1169 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1170 add_debug_info_for_null_check_here(op->stub()->info());
1171 __ br(Assembler::NE, *op->stub()->entry());
1172 }
1173 __ allocate_object(op->obj()->as_register(),
1174 op->tmp1()->as_register(),
1175 op->tmp2()->as_register(),
1176 op->header_size(),
1177 op->object_size(),
1178 op->klass()->as_register(),
1179 *op->stub()->entry());
1180 __ bind(*op->stub()->continuation());
1181 }
1182
1183 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1184 Register len = op->len()->as_register();
1185 __ uxtw(len, len);
1186
1187 if (UseSlowPath ||
1188 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1189 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1190 __ b(*op->stub()->entry());
1191 } else {
1192 Register tmp1 = op->tmp1()->as_register();
1193 Register tmp2 = op->tmp2()->as_register();
1194 Register tmp3 = op->tmp3()->as_register();
1195 if (len == tmp1) {
1196 tmp1 = tmp3;
1197 } else if (len == tmp2) {
1198 tmp2 = tmp3;
1199 } else if (len == tmp3) {
1200 // everything is ok
1201 } else {
1202 __ mov(tmp3, len);
1203 }
1204 __ allocate_array(op->obj()->as_register(),
1205 len,
1206 tmp1,
1207 tmp2,
1208 arrayOopDesc::base_offset_in_bytes(op->type()),
1209 array_element_size(op->type()),
1210 op->klass()->as_register(),
1211 *op->stub()->entry(),
1212 op->zero_array());
1213 }
1214 __ bind(*op->stub()->continuation());
1215 }
1216
1217 void LIR_Assembler::type_profile_helper(Register mdo,
1218 ciMethodData *md, ciProfileData *data,
1219 Register recv, Label* update_done) {
1220
1221 // Given a profile data offset, generate an Address which points to
1222 // the corresponding slot in mdo->data().
1223 // Clobbers rscratch2.
1224 auto slot_at = [=](ByteSize offset) -> Address {
1225 return __ form_address(rscratch2, mdo,
1226 md->byte_offset_of_slot(data, offset),
1227 LogBytesPerWord);
1228 };
1229
1230 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1231 Label next_test;
1232 // See if the receiver is receiver[n].
1233 __ ldr(rscratch1, slot_at(ReceiverTypeData::receiver_offset(i)));
1234 __ cmp(recv, rscratch1);
1235 __ br(Assembler::NE, next_test);
1236 __ addptr(slot_at(ReceiverTypeData::receiver_count_offset(i)),
1237 DataLayout::counter_increment);
1238 __ b(*update_done);
1239 __ bind(next_test);
1240 }
1241
1242 // Didn't find receiver; find next empty slot and fill it in
1243 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1244 Label next_test;
1245 Address recv_addr(slot_at(ReceiverTypeData::receiver_offset(i)));
1246 __ ldr(rscratch1, recv_addr);
1247 __ cbnz(rscratch1, next_test);
1248 __ str(recv, recv_addr);
1249 __ mov(rscratch1, DataLayout::counter_increment);
1250 __ str(rscratch1, slot_at(ReceiverTypeData::receiver_count_offset(i)));
1251 __ b(*update_done);
1252 __ bind(next_test);
1253 }
1254 }
1255
1256 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1257 // we always need a stub for the failure case.
1258 CodeStub* stub = op->stub();
1259 Register obj = op->object()->as_register();
1260 Register k_RInfo = op->tmp1()->as_register();
1261 Register klass_RInfo = op->tmp2()->as_register();
1262 Register dst = op->result_opr()->as_register();
1263 ciKlass* k = op->klass();
1264 Register Rtmp1 = noreg;
1265
1266 // check if it needs to be profiled
1267 ciMethodData* md;
1268 ciProfileData* data;
1269
1270 const bool should_profile = op->should_profile();
1271
1272 if (should_profile) {
1273 ciMethod* method = op->profiled_method();
1274 assert(method != nullptr, "Should have method");
1275 int bci = op->profiled_bci();
1276 md = method->method_data_or_null();
1277 assert(md != nullptr, "Sanity");
1278 data = md->bci_to_data(bci);
1279 assert(data != nullptr, "need data for type check");
1280 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1281 }
1282 Label* success_target = success;
1283 Label* failure_target = failure;
1284
1285 if (obj == k_RInfo) {
1286 k_RInfo = dst;
1287 } else if (obj == klass_RInfo) {
1288 klass_RInfo = dst;
1289 }
1290 if (k->is_loaded() && !UseCompressedClassPointers) {
1291 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1292 } else {
1293 Rtmp1 = op->tmp3()->as_register();
1294 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1295 }
1296
1297 assert_different_registers(obj, k_RInfo, klass_RInfo);
1298
1299 if (should_profile) {
1300 Register mdo = klass_RInfo;
1301 __ mov_metadata(mdo, md->constant_encoding());
1302 Label not_null;
1303 __ cbnz(obj, not_null);
1304 // Object is null; update MDO and exit
1305 Address data_addr
1306 = __ form_address(rscratch2, mdo,
1307 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1308 0);
1309 __ ldrb(rscratch1, data_addr);
1310 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1311 __ strb(rscratch1, data_addr);
1312 __ b(*obj_is_null);
1313 __ bind(not_null);
1314
1315 Label update_done;
1316 Register recv = k_RInfo;
1317 __ load_klass(recv, obj);
1318 type_profile_helper(mdo, md, data, recv, &update_done);
1319 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1320 __ addptr(counter_addr, DataLayout::counter_increment);
1321
1322 __ bind(update_done);
1323 } else {
1324 __ cbz(obj, *obj_is_null);
1325 }
1326
1327 if (!k->is_loaded()) {
1328 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1329 } else {
1330 __ mov_metadata(k_RInfo, k->constant_encoding());
1331 }
1332 __ verify_oop(obj);
1333
1334 if (op->fast_check()) {
1335 // get object class
1336 // not a safepoint as obj null check happens earlier
1337 __ load_klass(rscratch1, obj);
1338 __ cmp( rscratch1, k_RInfo);
1339
1340 __ br(Assembler::NE, *failure_target);
1341 // successful cast, fall through to profile or jump
1342 } else {
1343 // get object class
1344 // not a safepoint as obj null check happens earlier
1345 __ load_klass(klass_RInfo, obj);
1346 if (k->is_loaded()) {
1347 // See if we get an immediate positive hit
1348 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1349 __ cmp(k_RInfo, rscratch1);
1350 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1351 __ br(Assembler::NE, *failure_target);
1352 // successful cast, fall through to profile or jump
1353 } else {
1354 // See if we get an immediate positive hit
1355 __ br(Assembler::EQ, *success_target);
1356 // check for self
1357 __ cmp(klass_RInfo, k_RInfo);
1358 __ br(Assembler::EQ, *success_target);
1359
1360 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1361 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1362 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1363 // result is a boolean
1364 __ cbzw(klass_RInfo, *failure_target);
1365 // successful cast, fall through to profile or jump
1366 }
1367 } else {
1368 // perform the fast part of the checking logic
1369 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1370 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1371 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1372 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1373 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1374 // result is a boolean
1375 __ cbz(k_RInfo, *failure_target);
1376 // successful cast, fall through to profile or jump
1377 }
1378 }
1379 __ b(*success);
1380 }
1381
1382
1383 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1384 const bool should_profile = op->should_profile();
1385
1386 LIR_Code code = op->code();
1387 if (code == lir_store_check) {
1388 Register value = op->object()->as_register();
1389 Register array = op->array()->as_register();
1390 Register k_RInfo = op->tmp1()->as_register();
1391 Register klass_RInfo = op->tmp2()->as_register();
1392 Register Rtmp1 = op->tmp3()->as_register();
1393
1394 CodeStub* stub = op->stub();
1395
1396 // check if it needs to be profiled
1397 ciMethodData* md;
1398 ciProfileData* data;
1399
1400 if (should_profile) {
1401 ciMethod* method = op->profiled_method();
1402 assert(method != nullptr, "Should have method");
1403 int bci = op->profiled_bci();
1404 md = method->method_data_or_null();
1405 assert(md != nullptr, "Sanity");
1406 data = md->bci_to_data(bci);
1407 assert(data != nullptr, "need data for type check");
1408 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1409 }
1410 Label done;
1411 Label* success_target = &done;
1412 Label* failure_target = stub->entry();
1413
1414 if (should_profile) {
1415 Label not_null;
1416 Register mdo = klass_RInfo;
1417 __ mov_metadata(mdo, md->constant_encoding());
1418 __ cbnz(value, not_null);
1419 // Object is null; update MDO and exit
1420 Address data_addr
1421 = __ form_address(rscratch2, mdo,
1422 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1423 __ ldrb(rscratch1, data_addr);
1424 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1425 __ strb(rscratch1, data_addr);
1426 __ b(done);
1427 __ bind(not_null);
1428
1429 Label update_done;
1430 Register recv = k_RInfo;
1431 __ load_klass(recv, value);
1432 type_profile_helper(mdo, md, data, recv, &update_done);
1433 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1434 __ addptr(counter_addr, DataLayout::counter_increment);
1435 __ bind(update_done);
1436 } else {
1437 __ cbz(value, done);
1438 }
1439
1440 add_debug_info_for_null_check_here(op->info_for_exception());
1441 __ load_klass(k_RInfo, array);
1442 __ load_klass(klass_RInfo, value);
1443
1444 // get instance klass (it's already uncompressed)
1445 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1446 // perform the fast part of the checking logic
1447 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1448 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1449 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1450 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1451 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1452 // result is a boolean
1453 __ cbzw(k_RInfo, *failure_target);
1454 // fall through to the success case
1455
1456 __ bind(done);
1457 } else if (code == lir_checkcast) {
1458 Register obj = op->object()->as_register();
1459 Register dst = op->result_opr()->as_register();
1460 Label success;
1461 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1462 __ bind(success);
1463 if (dst != obj) {
1464 __ mov(dst, obj);
1465 }
1466 } else if (code == lir_instanceof) {
1467 Register obj = op->object()->as_register();
1468 Register dst = op->result_opr()->as_register();
1469 Label success, failure, done;
1470 emit_typecheck_helper(op, &success, &failure, &failure);
1471 __ bind(failure);
1472 __ mov(dst, zr);
1473 __ b(done);
1474 __ bind(success);
1475 __ mov(dst, 1);
1476 __ bind(done);
1477 } else {
1478 ShouldNotReachHere();
1479 }
1480 }
1481
1482 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1483 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1484 __ cset(rscratch1, Assembler::NE);
1485 __ membar(__ AnyAny);
1486 }
1487
1488 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1489 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1490 __ cset(rscratch1, Assembler::NE);
1491 __ membar(__ AnyAny);
1492 }
1493
1494
1495 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1496 Register addr;
1497 if (op->addr()->is_register()) {
1498 addr = as_reg(op->addr());
1499 } else {
1500 assert(op->addr()->is_address(), "what else?");
1501 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1502 assert(addr_ptr->disp() == 0, "need 0 disp");
1503 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1504 addr = as_reg(addr_ptr->base());
1505 }
1506 Register newval = as_reg(op->new_value());
1507 Register cmpval = as_reg(op->cmp_value());
1508
1509 if (op->code() == lir_cas_obj) {
1510 if (UseCompressedOops) {
1511 Register t1 = op->tmp1()->as_register();
1512 assert(op->tmp1()->is_valid(), "must be");
1513 __ encode_heap_oop(t1, cmpval);
1514 cmpval = t1;
1515 __ encode_heap_oop(rscratch2, newval);
1516 newval = rscratch2;
1517 casw(addr, newval, cmpval);
1518 } else {
1519 casl(addr, newval, cmpval);
1520 }
1521 } else if (op->code() == lir_cas_int) {
1522 casw(addr, newval, cmpval);
1523 } else {
1524 casl(addr, newval, cmpval);
1525 }
1526 }
1527
1528
1529 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1530 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1531 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1532
1533 Assembler::Condition acond, ncond;
1534 switch (condition) {
1535 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1536 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1537 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1538 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1539 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1540 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1541 case lir_cond_belowEqual:
1542 case lir_cond_aboveEqual:
1543 default: ShouldNotReachHere();
1544 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1545 }
1546
1547 assert(result->is_single_cpu() || result->is_double_cpu(),
1548 "expect single register for result");
1549 if (opr1->is_constant() && opr2->is_constant()
1550 && opr1->type() == T_INT && opr2->type() == T_INT) {
1551 jint val1 = opr1->as_jint();
1552 jint val2 = opr2->as_jint();
1553 if (val1 == 0 && val2 == 1) {
1554 __ cset(result->as_register(), ncond);
1555 return;
1556 } else if (val1 == 1 && val2 == 0) {
1557 __ cset(result->as_register(), acond);
1558 return;
1559 }
1560 }
1561
1562 if (opr1->is_constant() && opr2->is_constant()
1563 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1564 jlong val1 = opr1->as_jlong();
1565 jlong val2 = opr2->as_jlong();
1566 if (val1 == 0 && val2 == 1) {
1567 __ cset(result->as_register_lo(), ncond);
1568 return;
1569 } else if (val1 == 1 && val2 == 0) {
1570 __ cset(result->as_register_lo(), acond);
1571 return;
1572 }
1573 }
1574
1575 if (opr1->is_stack()) {
1576 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1577 opr1 = FrameMap::rscratch1_opr;
1578 } else if (opr1->is_constant()) {
1579 LIR_Opr tmp
1580 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1581 const2reg(opr1, tmp, lir_patch_none, nullptr);
1582 opr1 = tmp;
1583 }
1584
1585 if (opr2->is_stack()) {
1586 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1587 opr2 = FrameMap::rscratch2_opr;
1588 } else if (opr2->is_constant()) {
1589 LIR_Opr tmp
1590 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1591 const2reg(opr2, tmp, lir_patch_none, nullptr);
1592 opr2 = tmp;
1593 }
1594
1595 if (result->type() == T_LONG)
1596 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1597 else
1598 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1599 }
1600
1601 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1602 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1603
1604 if (left->is_single_cpu()) {
1605 Register lreg = left->as_register();
1606 Register dreg = as_reg(dest);
1607
1608 if (right->is_single_cpu()) {
1609 // cpu register - cpu register
1610
1611 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1612 "should be");
1613 Register rreg = right->as_register();
1614 switch (code) {
1615 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1616 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1617 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1618 default: ShouldNotReachHere();
1619 }
1620
1621 } else if (right->is_double_cpu()) {
1622 Register rreg = right->as_register_lo();
1623 // single_cpu + double_cpu: can happen with obj+long
1624 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1625 switch (code) {
1626 case lir_add: __ add(dreg, lreg, rreg); break;
1627 case lir_sub: __ sub(dreg, lreg, rreg); break;
1628 default: ShouldNotReachHere();
1629 }
1630 } else if (right->is_constant()) {
1631 // cpu register - constant
1632 jlong c;
1633
1634 // FIXME. This is fugly: we really need to factor all this logic.
1635 switch(right->type()) {
1636 case T_LONG:
1637 c = right->as_constant_ptr()->as_jlong();
1638 break;
1639 case T_INT:
1640 case T_ADDRESS:
1641 c = right->as_constant_ptr()->as_jint();
1642 break;
1643 default:
1644 ShouldNotReachHere();
1645 c = 0; // unreachable
1646 break;
1647 }
1648
1649 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1650 if (c == 0 && dreg == lreg) {
1651 COMMENT("effective nop elided");
1652 return;
1653 }
1654 switch(left->type()) {
1655 case T_INT:
1656 switch (code) {
1657 case lir_add: __ addw(dreg, lreg, c); break;
1658 case lir_sub: __ subw(dreg, lreg, c); break;
1659 default: ShouldNotReachHere();
1660 }
1661 break;
1662 case T_OBJECT:
1663 case T_ADDRESS:
1664 switch (code) {
1665 case lir_add: __ add(dreg, lreg, c); break;
1666 case lir_sub: __ sub(dreg, lreg, c); break;
1667 default: ShouldNotReachHere();
1668 }
1669 break;
1670 default:
1671 ShouldNotReachHere();
1672 }
1673 } else {
1674 ShouldNotReachHere();
1675 }
1676
1677 } else if (left->is_double_cpu()) {
1678 Register lreg_lo = left->as_register_lo();
1679
1680 if (right->is_double_cpu()) {
1681 // cpu register - cpu register
1682 Register rreg_lo = right->as_register_lo();
1683 switch (code) {
1684 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1685 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1686 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1687 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1688 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1689 default:
1690 ShouldNotReachHere();
1691 }
1692
1693 } else if (right->is_constant()) {
1694 jlong c = right->as_constant_ptr()->as_jlong();
1695 Register dreg = as_reg(dest);
1696 switch (code) {
1697 case lir_add:
1698 case lir_sub:
1699 if (c == 0 && dreg == lreg_lo) {
1700 COMMENT("effective nop elided");
1701 return;
1702 }
1703 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1704 break;
1705 case lir_div:
1706 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1707 if (c == 1) {
1708 // move lreg_lo to dreg if divisor is 1
1709 __ mov(dreg, lreg_lo);
1710 } else {
1711 unsigned int shift = log2i_exact(c);
1712 // use rscratch1 as intermediate result register
1713 __ asr(rscratch1, lreg_lo, 63);
1714 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1715 __ asr(dreg, rscratch1, shift);
1716 }
1717 break;
1718 case lir_rem:
1719 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1720 if (c == 1) {
1721 // move 0 to dreg if divisor is 1
1722 __ mov(dreg, zr);
1723 } else {
1724 // use rscratch1 as intermediate result register
1725 __ negs(rscratch1, lreg_lo);
1726 __ andr(dreg, lreg_lo, c - 1);
1727 __ andr(rscratch1, rscratch1, c - 1);
1728 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1729 }
1730 break;
1731 default:
1732 ShouldNotReachHere();
1733 }
1734 } else {
1735 ShouldNotReachHere();
1736 }
1737 } else if (left->is_single_fpu()) {
1738 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1739 switch (code) {
1740 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1741 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1742 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1743 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1744 default:
1745 ShouldNotReachHere();
1746 }
1747 } else if (left->is_double_fpu()) {
1748 if (right->is_double_fpu()) {
1749 // fpu register - fpu register
1750 switch (code) {
1751 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1752 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1753 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1754 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1755 default:
1756 ShouldNotReachHere();
1757 }
1758 } else {
1759 if (right->is_constant()) {
1760 ShouldNotReachHere();
1761 }
1762 ShouldNotReachHere();
1763 }
1764 } else if (left->is_single_stack() || left->is_address()) {
1765 assert(left == dest, "left and dest must be equal");
1766 ShouldNotReachHere();
1767 } else {
1768 ShouldNotReachHere();
1769 }
1770 }
1771
1772 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1773 switch(code) {
1774 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1775 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1776 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1777 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1778 default : ShouldNotReachHere();
1779 }
1780 }
1781
1782 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1783
1784 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1785 Register Rleft = left->is_single_cpu() ? left->as_register() :
1786 left->as_register_lo();
1787 if (dst->is_single_cpu()) {
1788 Register Rdst = dst->as_register();
1789 if (right->is_constant()) {
1790 switch (code) {
1791 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1792 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1793 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1794 default: ShouldNotReachHere(); break;
1795 }
1796 } else {
1797 Register Rright = right->is_single_cpu() ? right->as_register() :
1798 right->as_register_lo();
1799 switch (code) {
1800 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1801 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1802 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1803 default: ShouldNotReachHere(); break;
1804 }
1805 }
1806 } else {
1807 Register Rdst = dst->as_register_lo();
1808 if (right->is_constant()) {
1809 switch (code) {
1810 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1811 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1812 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1813 default: ShouldNotReachHere(); break;
1814 }
1815 } else {
1816 Register Rright = right->is_single_cpu() ? right->as_register() :
1817 right->as_register_lo();
1818 switch (code) {
1819 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1820 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1821 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1822 default: ShouldNotReachHere(); break;
1823 }
1824 }
1825 }
1826 }
1827
1828
1829
1830 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1831
1832 // opcode check
1833 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1834 bool is_irem = (code == lir_irem);
1835
1836 // operand check
1837 assert(left->is_single_cpu(), "left must be register");
1838 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1839 assert(result->is_single_cpu(), "result must be register");
1840 Register lreg = left->as_register();
1841 Register dreg = result->as_register();
1842
1843 // power-of-2 constant check and codegen
1844 if (right->is_constant()) {
1845 int c = right->as_constant_ptr()->as_jint();
1846 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1847 if (is_irem) {
1848 if (c == 1) {
1849 // move 0 to dreg if divisor is 1
1850 __ movw(dreg, zr);
1851 } else {
1852 // use rscratch1 as intermediate result register
1853 __ negsw(rscratch1, lreg);
1854 __ andw(dreg, lreg, c - 1);
1855 __ andw(rscratch1, rscratch1, c - 1);
1856 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1857 }
1858 } else {
1859 if (c == 1) {
1860 // move lreg to dreg if divisor is 1
1861 __ movw(dreg, lreg);
1862 } else {
1863 unsigned int shift = exact_log2(c);
1864 // use rscratch1 as intermediate result register
1865 __ asrw(rscratch1, lreg, 31);
1866 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1867 __ asrw(dreg, rscratch1, shift);
1868 }
1869 }
1870 } else {
1871 Register rreg = right->as_register();
1872 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1873 }
1874 }
1875
1876
1877 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1878 if (opr1->is_constant() && opr2->is_single_cpu()) {
1879 // tableswitch
1880 Register reg = as_reg(opr2);
1881 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1882 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1883 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1884 Register reg1 = as_reg(opr1);
1885 if (opr2->is_single_cpu()) {
1886 // cpu register - cpu register
1887 Register reg2 = opr2->as_register();
1888 if (is_reference_type(opr1->type())) {
1889 __ cmpoop(reg1, reg2);
1890 } else {
1891 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1892 __ cmpw(reg1, reg2);
1893 }
1894 return;
1895 }
1896 if (opr2->is_double_cpu()) {
1897 // cpu register - cpu register
1898 Register reg2 = opr2->as_register_lo();
1899 __ cmp(reg1, reg2);
1900 return;
1901 }
1902
1903 if (opr2->is_constant()) {
1904 bool is_32bit = false; // width of register operand
1905 jlong imm;
1906
1907 switch(opr2->type()) {
1908 case T_INT:
1909 imm = opr2->as_constant_ptr()->as_jint();
1910 is_32bit = true;
1911 break;
1912 case T_LONG:
1913 imm = opr2->as_constant_ptr()->as_jlong();
1914 break;
1915 case T_ADDRESS:
1916 imm = opr2->as_constant_ptr()->as_jint();
1917 break;
1918 case T_METADATA:
1919 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1920 break;
1921 case T_OBJECT:
1922 case T_ARRAY:
1923 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1924 __ cmpoop(reg1, rscratch1);
1925 return;
1926 default:
1927 ShouldNotReachHere();
1928 imm = 0; // unreachable
1929 break;
1930 }
1931
1932 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1933 if (is_32bit)
1934 __ cmpw(reg1, imm);
1935 else
1936 __ subs(zr, reg1, imm);
1937 return;
1938 } else {
1939 __ mov(rscratch1, imm);
1940 if (is_32bit)
1941 __ cmpw(reg1, rscratch1);
1942 else
1943 __ cmp(reg1, rscratch1);
1944 return;
1945 }
1946 } else
1947 ShouldNotReachHere();
1948 } else if (opr1->is_single_fpu()) {
1949 FloatRegister reg1 = opr1->as_float_reg();
1950 assert(opr2->is_single_fpu(), "expect single float register");
1951 FloatRegister reg2 = opr2->as_float_reg();
1952 __ fcmps(reg1, reg2);
1953 } else if (opr1->is_double_fpu()) {
1954 FloatRegister reg1 = opr1->as_double_reg();
1955 assert(opr2->is_double_fpu(), "expect double float register");
1956 FloatRegister reg2 = opr2->as_double_reg();
1957 __ fcmpd(reg1, reg2);
1958 } else {
1959 ShouldNotReachHere();
1960 }
1961 }
1962
1963 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1964 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1965 bool is_unordered_less = (code == lir_ucmp_fd2i);
1966 if (left->is_single_fpu()) {
1967 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1968 } else if (left->is_double_fpu()) {
1969 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1970 } else {
1971 ShouldNotReachHere();
1972 }
1973 } else if (code == lir_cmp_l2i) {
1974 Label done;
1975 __ cmp(left->as_register_lo(), right->as_register_lo());
1976 __ mov(dst->as_register(), (uint64_t)-1L);
1977 __ br(Assembler::LT, done);
1978 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
1979 __ bind(done);
1980 } else {
1981 ShouldNotReachHere();
1982 }
1983 }
1984
1985
1986 void LIR_Assembler::align_call(LIR_Code code) { }
1987
1988
1989 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
1990 address call = __ trampoline_call(Address(op->addr(), rtype));
1991 if (call == nullptr) {
1992 bailout("trampoline stub overflow");
1993 return;
1994 }
1995 add_call_info(code_offset(), op->info());
1996 __ post_call_nop();
1997 }
1998
1999
2000 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2001 address call = __ ic_call(op->addr());
2002 if (call == nullptr) {
2003 bailout("trampoline stub overflow");
2004 return;
2005 }
2006 add_call_info(code_offset(), op->info());
2007 __ post_call_nop();
2008 }
2009
2010 void LIR_Assembler::emit_static_call_stub() {
2011 address call_pc = __ pc();
2012 address stub = __ start_a_stub(call_stub_size());
2013 if (stub == nullptr) {
2014 bailout("static call stub overflow");
2015 return;
2016 }
2017
2018 int start = __ offset();
2019
2020 __ relocate(static_stub_Relocation::spec(call_pc));
2021 __ emit_static_call_stub();
2022
2023 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2024 <= call_stub_size(), "stub too big");
2025 __ end_a_stub();
2026 }
2027
2028
2029 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2030 assert(exceptionOop->as_register() == r0, "must match");
2031 assert(exceptionPC->as_register() == r3, "must match");
2032
2033 // exception object is not added to oop map by LinearScan
2034 // (LinearScan assumes that no oops are in fixed registers)
2035 info->add_register_oop(exceptionOop);
2036 C1StubId unwind_id;
2037
2038 // get current pc information
2039 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2040 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2041 // As no instructions have been generated yet for this LIR node it's
2042 // possible that an oop map already exists for the current offset.
2043 // In that case insert an dummy NOP here to ensure all oop map PCs
2044 // are unique. See JDK-8237483.
2045 __ nop();
2046 }
2047 int pc_for_athrow_offset = __ offset();
2048 InternalAddress pc_for_athrow(__ pc());
2049 __ adr(exceptionPC->as_register(), pc_for_athrow);
2050 add_call_info(pc_for_athrow_offset, info); // for exception handler
2051
2052 __ verify_not_null_oop(r0);
2053 // search an exception handler (r0: exception oop, r3: throwing pc)
2054 if (compilation()->has_fpu_code()) {
2055 unwind_id = C1StubId::handle_exception_id;
2056 } else {
2057 unwind_id = C1StubId::handle_exception_nofpu_id;
2058 }
2059 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2060
2061 // FIXME: enough room for two byte trap ????
2062 __ nop();
2063 }
2064
2065
2066 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2067 assert(exceptionOop->as_register() == r0, "must match");
2068
2069 __ b(_unwind_handler_entry);
2070 }
2071
2072
2073 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2074 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2075 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2076
2077 switch (left->type()) {
2078 case T_INT: {
2079 switch (code) {
2080 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2081 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2082 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2083 default:
2084 ShouldNotReachHere();
2085 break;
2086 }
2087 break;
2088 case T_LONG:
2089 case T_ADDRESS:
2090 case T_OBJECT:
2091 switch (code) {
2092 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2093 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2094 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2095 default:
2096 ShouldNotReachHere();
2097 break;
2098 }
2099 break;
2100 default:
2101 ShouldNotReachHere();
2102 break;
2103 }
2104 }
2105 }
2106
2107
2108 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2109 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2110 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2111
2112 switch (left->type()) {
2113 case T_INT: {
2114 switch (code) {
2115 case lir_shl: __ lslw (dreg, lreg, count); break;
2116 case lir_shr: __ asrw (dreg, lreg, count); break;
2117 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2118 default:
2119 ShouldNotReachHere();
2120 break;
2121 }
2122 break;
2123 case T_LONG:
2124 case T_ADDRESS:
2125 case T_OBJECT:
2126 switch (code) {
2127 case lir_shl: __ lsl (dreg, lreg, count); break;
2128 case lir_shr: __ asr (dreg, lreg, count); break;
2129 case lir_ushr: __ lsr (dreg, lreg, count); break;
2130 default:
2131 ShouldNotReachHere();
2132 break;
2133 }
2134 break;
2135 default:
2136 ShouldNotReachHere();
2137 break;
2138 }
2139 }
2140 }
2141
2142
2143 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2144 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2145 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2146 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2147 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2148 }
2149
2150
2151 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2152 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2153 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2154 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2155 __ mov (rscratch1, c);
2156 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2157 }
2158
2159
2160 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2161 ShouldNotReachHere();
2162 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2163 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2164 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2165 __ lea(rscratch1, __ constant_oop_address(o));
2166 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2167 }
2168
2169
2170 // This code replaces a call to arraycopy; no exception may
2171 // be thrown in this code, they must be thrown in the System.arraycopy
2172 // activation frame; we could save some checks if this would not be the case
2173 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2174 ciArrayKlass* default_type = op->expected_type();
2175 Register src = op->src()->as_register();
2176 Register dst = op->dst()->as_register();
2177 Register src_pos = op->src_pos()->as_register();
2178 Register dst_pos = op->dst_pos()->as_register();
2179 Register length = op->length()->as_register();
2180 Register tmp = op->tmp()->as_register();
2181
2182 CodeStub* stub = op->stub();
2183 int flags = op->flags();
2184 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2185 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2186
2187 // if we don't know anything, just go through the generic arraycopy
2188 if (default_type == nullptr // || basic_type == T_OBJECT
2189 ) {
2190 Label done;
2191 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2192
2193 // Save the arguments in case the generic arraycopy fails and we
2194 // have to fall back to the JNI stub
2195 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2196 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2197 __ str(src, Address(sp, 4*BytesPerWord));
2198
2199 address copyfunc_addr = StubRoutines::generic_arraycopy();
2200 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2201
2202 // The arguments are in java calling convention so we shift them
2203 // to C convention
2204 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2205 __ mov(c_rarg0, j_rarg0);
2206 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2207 __ mov(c_rarg1, j_rarg1);
2208 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2209 __ mov(c_rarg2, j_rarg2);
2210 assert_different_registers(c_rarg3, j_rarg4);
2211 __ mov(c_rarg3, j_rarg3);
2212 __ mov(c_rarg4, j_rarg4);
2213 #ifndef PRODUCT
2214 if (PrintC1Statistics) {
2215 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2216 }
2217 #endif
2218 __ far_call(RuntimeAddress(copyfunc_addr));
2219
2220 __ cbz(r0, *stub->continuation());
2221
2222 // Reload values from the stack so they are where the stub
2223 // expects them.
2224 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2225 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2226 __ ldr(src, Address(sp, 4*BytesPerWord));
2227
2228 // r0 is -1^K where K == partial copied count
2229 __ eonw(rscratch1, r0, zr);
2230 // adjust length down and src/end pos up by partial copied count
2231 __ subw(length, length, rscratch1);
2232 __ addw(src_pos, src_pos, rscratch1);
2233 __ addw(dst_pos, dst_pos, rscratch1);
2234 __ b(*stub->entry());
2235
2236 __ bind(*stub->continuation());
2237 return;
2238 }
2239
2240 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2241
2242 int elem_size = type2aelembytes(basic_type);
2243 int scale = exact_log2(elem_size);
2244
2245 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2246 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2247
2248 // test for null
2249 if (flags & LIR_OpArrayCopy::src_null_check) {
2250 __ cbz(src, *stub->entry());
2251 }
2252 if (flags & LIR_OpArrayCopy::dst_null_check) {
2253 __ cbz(dst, *stub->entry());
2254 }
2255
2256 // If the compiler was not able to prove that exact type of the source or the destination
2257 // of the arraycopy is an array type, check at runtime if the source or the destination is
2258 // an instance type.
2259 if (flags & LIR_OpArrayCopy::type_check) {
2260 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2261 __ load_klass(tmp, dst);
2262 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2263 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2264 __ br(Assembler::GE, *stub->entry());
2265 }
2266
2267 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2268 __ load_klass(tmp, src);
2269 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2270 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2271 __ br(Assembler::GE, *stub->entry());
2272 }
2273 }
2274
2275 // check if negative
2276 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2277 __ cmpw(src_pos, 0);
2278 __ br(Assembler::LT, *stub->entry());
2279 }
2280 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2281 __ cmpw(dst_pos, 0);
2282 __ br(Assembler::LT, *stub->entry());
2283 }
2284
2285 if (flags & LIR_OpArrayCopy::length_positive_check) {
2286 __ cmpw(length, 0);
2287 __ br(Assembler::LT, *stub->entry());
2288 }
2289
2290 if (flags & LIR_OpArrayCopy::src_range_check) {
2291 __ addw(tmp, src_pos, length);
2292 __ ldrw(rscratch1, src_length_addr);
2293 __ cmpw(tmp, rscratch1);
2294 __ br(Assembler::HI, *stub->entry());
2295 }
2296 if (flags & LIR_OpArrayCopy::dst_range_check) {
2297 __ addw(tmp, dst_pos, length);
2298 __ ldrw(rscratch1, dst_length_addr);
2299 __ cmpw(tmp, rscratch1);
2300 __ br(Assembler::HI, *stub->entry());
2301 }
2302
2303 if (flags & LIR_OpArrayCopy::type_check) {
2304 // We don't know the array types are compatible
2305 if (basic_type != T_OBJECT) {
2306 // Simple test for basic type arrays
2307 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2308 __ br(Assembler::NE, *stub->entry());
2309 } else {
2310 // For object arrays, if src is a sub class of dst then we can
2311 // safely do the copy.
2312 Label cont, slow;
2313
2314 #define PUSH(r1, r2) \
2315 stp(r1, r2, __ pre(sp, -2 * wordSize));
2316
2317 #define POP(r1, r2) \
2318 ldp(r1, r2, __ post(sp, 2 * wordSize));
2319
2320 __ PUSH(src, dst);
2321
2322 __ load_klass(src, src);
2323 __ load_klass(dst, dst);
2324
2325 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2326
2327 __ PUSH(src, dst);
2328 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
2329 __ POP(src, dst);
2330
2331 __ cbnz(src, cont);
2332
2333 __ bind(slow);
2334 __ POP(src, dst);
2335
2336 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2337 if (copyfunc_addr != nullptr) { // use stub if available
2338 // src is not a sub class of dst so we have to do a
2339 // per-element check.
2340
2341 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2342 if ((flags & mask) != mask) {
2343 // Check that at least both of them object arrays.
2344 assert(flags & mask, "one of the two should be known to be an object array");
2345
2346 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2347 __ load_klass(tmp, src);
2348 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2349 __ load_klass(tmp, dst);
2350 }
2351 int lh_offset = in_bytes(Klass::layout_helper_offset());
2352 Address klass_lh_addr(tmp, lh_offset);
2353 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2354 __ ldrw(rscratch1, klass_lh_addr);
2355 __ mov(rscratch2, objArray_lh);
2356 __ eorw(rscratch1, rscratch1, rscratch2);
2357 __ cbnzw(rscratch1, *stub->entry());
2358 }
2359
2360 // Spill because stubs can use any register they like and it's
2361 // easier to restore just those that we care about.
2362 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2363 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2364 __ str(src, Address(sp, 4*BytesPerWord));
2365
2366 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2367 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2368 assert_different_registers(c_rarg0, dst, dst_pos, length);
2369 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2370 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2371 assert_different_registers(c_rarg1, dst, length);
2372 __ uxtw(c_rarg2, length);
2373 assert_different_registers(c_rarg2, dst);
2374
2375 __ load_klass(c_rarg4, dst);
2376 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2377 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2378 __ far_call(RuntimeAddress(copyfunc_addr));
2379
2380 #ifndef PRODUCT
2381 if (PrintC1Statistics) {
2382 Label failed;
2383 __ cbnz(r0, failed);
2384 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2385 __ bind(failed);
2386 }
2387 #endif
2388
2389 __ cbz(r0, *stub->continuation());
2390
2391 #ifndef PRODUCT
2392 if (PrintC1Statistics) {
2393 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2394 }
2395 #endif
2396 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2397
2398 // Restore previously spilled arguments
2399 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2400 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2401 __ ldr(src, Address(sp, 4*BytesPerWord));
2402
2403 // return value is -1^K where K is partial copied count
2404 __ eonw(rscratch1, r0, zr);
2405 // adjust length down and src/end pos up by partial copied count
2406 __ subw(length, length, rscratch1);
2407 __ addw(src_pos, src_pos, rscratch1);
2408 __ addw(dst_pos, dst_pos, rscratch1);
2409 }
2410
2411 __ b(*stub->entry());
2412
2413 __ bind(cont);
2414 __ POP(src, dst);
2415 }
2416 }
2417
2418 #ifdef ASSERT
2419 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2420 // Sanity check the known type with the incoming class. For the
2421 // primitive case the types must match exactly with src.klass and
2422 // dst.klass each exactly matching the default type. For the
2423 // object array case, if no type check is needed then either the
2424 // dst type is exactly the expected type and the src type is a
2425 // subtype which we can't check or src is the same array as dst
2426 // but not necessarily exactly of type default_type.
2427 Label known_ok, halt;
2428 __ mov_metadata(tmp, default_type->constant_encoding());
2429
2430 if (basic_type != T_OBJECT) {
2431 __ cmp_klass(dst, tmp, rscratch1);
2432 __ br(Assembler::NE, halt);
2433 __ cmp_klass(src, tmp, rscratch1);
2434 __ br(Assembler::EQ, known_ok);
2435 } else {
2436 __ cmp_klass(dst, tmp, rscratch1);
2437 __ br(Assembler::EQ, known_ok);
2438 __ cmp(src, dst);
2439 __ br(Assembler::EQ, known_ok);
2440 }
2441 __ bind(halt);
2442 __ stop("incorrect type information in arraycopy");
2443 __ bind(known_ok);
2444 }
2445 #endif
2446
2447 #ifndef PRODUCT
2448 if (PrintC1Statistics) {
2449 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2450 }
2451 #endif
2452
2453 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2454 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2455 assert_different_registers(c_rarg0, dst, dst_pos, length);
2456 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2457 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2458 assert_different_registers(c_rarg1, dst, length);
2459 __ uxtw(c_rarg2, length);
2460 assert_different_registers(c_rarg2, dst);
2461
2462 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2463 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2464 const char *name;
2465 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2466
2467 CodeBlob *cb = CodeCache::find_blob(entry);
2468 if (cb) {
2469 __ far_call(RuntimeAddress(entry));
2470 } else {
2471 __ call_VM_leaf(entry, 3);
2472 }
2473
2474 if (stub != nullptr) {
2475 __ bind(*stub->continuation());
2476 }
2477 }
2478
2479
2480
2481
2482 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2483 Register obj = op->obj_opr()->as_register(); // may not be an oop
2484 Register hdr = op->hdr_opr()->as_register();
2485 Register lock = op->lock_opr()->as_register();
2486 Register temp = op->scratch_opr()->as_register();
2487 if (LockingMode == LM_MONITOR) {
2488 if (op->info() != nullptr) {
2489 add_debug_info_for_null_check_here(op->info());
2490 __ null_check(obj, -1);
2491 }
2492 __ b(*op->stub()->entry());
2493 } else if (op->code() == lir_lock) {
2494 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2495 // add debug info for NullPointerException only if one is possible
2496 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2497 if (op->info() != nullptr) {
2498 add_debug_info_for_null_check(null_check_offset, op->info());
2499 }
2500 // done
2501 } else if (op->code() == lir_unlock) {
2502 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2503 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2504 } else {
2505 Unimplemented();
2506 }
2507 __ bind(*op->stub()->continuation());
2508 }
2509
2510 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2511 Register obj = op->obj()->as_pointer_register();
2512 Register result = op->result_opr()->as_pointer_register();
2513
2514 CodeEmitInfo* info = op->info();
2515 if (info != nullptr) {
2516 add_debug_info_for_null_check_here(info);
2517 }
2518
2519 __ load_klass(result, obj);
2520 }
2521
2522 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2523 ciMethod* method = op->profiled_method();
2524 int bci = op->profiled_bci();
2525 ciMethod* callee = op->profiled_callee();
2526
2527 // Update counter for all call types
2528 ciMethodData* md = method->method_data_or_null();
2529 assert(md != nullptr, "Sanity");
2530 ciProfileData* data = md->bci_to_data(bci);
2531 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2532 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2533 Register mdo = op->mdo()->as_register();
2534 __ mov_metadata(mdo, md->constant_encoding());
2535 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2536 // Perform additional virtual call profiling for invokevirtual and
2537 // invokeinterface bytecodes
2538 if (op->should_profile_receiver_type()) {
2539 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2540 Register recv = op->recv()->as_register();
2541 assert_different_registers(mdo, recv);
2542 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2543 ciKlass* known_klass = op->known_holder();
2544 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2545 // We know the type that will be seen at this call site; we can
2546 // statically update the MethodData* rather than needing to do
2547 // dynamic tests on the receiver type
2548
2549 // NOTE: we should probably put a lock around this search to
2550 // avoid collisions by concurrent compilations
2551 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2552 uint i;
2553 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2554 ciKlass* receiver = vc_data->receiver(i);
2555 if (known_klass->equals(receiver)) {
2556 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2557 __ addptr(data_addr, DataLayout::counter_increment);
2558 return;
2559 }
2560 }
2561
2562 // Receiver type not found in profile data; select an empty slot
2563
2564 // Note that this is less efficient than it should be because it
2565 // always does a write to the receiver part of the
2566 // VirtualCallData rather than just the first time
2567 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2568 ciKlass* receiver = vc_data->receiver(i);
2569 if (receiver == nullptr) {
2570 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2571 Address recv_addr =
2572 __ form_address(rscratch2, mdo,
2573 md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)),
2574 LogBytesPerWord);
2575 __ str(rscratch1, recv_addr);
2576 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2577 __ addptr(data_addr, DataLayout::counter_increment);
2578 return;
2579 }
2580 }
2581 } else {
2582 __ load_klass(recv, recv);
2583 Label update_done;
2584 type_profile_helper(mdo, md, data, recv, &update_done);
2585 // Receiver did not match any saved receiver and there is no empty row for it.
2586 // Increment total counter to indicate polymorphic case.
2587 __ addptr(counter_addr, DataLayout::counter_increment);
2588
2589 __ bind(update_done);
2590 }
2591 } else {
2592 // Static call
2593 __ addptr(counter_addr, DataLayout::counter_increment);
2594 }
2595 }
2596
2597
2598 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2599 Unimplemented();
2600 }
2601
2602
2603 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2604 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2605 }
2606
2607 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2608 assert(op->crc()->is_single_cpu(), "crc must be register");
2609 assert(op->val()->is_single_cpu(), "byte value must be register");
2610 assert(op->result_opr()->is_single_cpu(), "result must be register");
2611 Register crc = op->crc()->as_register();
2612 Register val = op->val()->as_register();
2613 Register res = op->result_opr()->as_register();
2614
2615 assert_different_registers(val, crc, res);
2616 uint64_t offset;
2617 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2618 __ add(res, res, offset);
2619
2620 __ mvnw(crc, crc); // ~crc
2621 __ update_byte_crc32(crc, val, res);
2622 __ mvnw(res, crc); // ~crc
2623 }
2624
2625 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2626 COMMENT("emit_profile_type {");
2627 Register obj = op->obj()->as_register();
2628 Register tmp = op->tmp()->as_pointer_register();
2629 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2630 ciKlass* exact_klass = op->exact_klass();
2631 intptr_t current_klass = op->current_klass();
2632 bool not_null = op->not_null();
2633 bool no_conflict = op->no_conflict();
2634
2635 Label update, next, none;
2636
2637 bool do_null = !not_null;
2638 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2639 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2640
2641 assert(do_null || do_update, "why are we here?");
2642 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2643 assert(mdo_addr.base() != rscratch1, "wrong register");
2644
2645 __ verify_oop(obj);
2646
2647 if (tmp != obj) {
2648 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2649 __ mov(tmp, obj);
2650 } else {
2651 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2652 }
2653 if (do_null) {
2654 __ cbnz(tmp, update);
2655 if (!TypeEntries::was_null_seen(current_klass)) {
2656 __ ldr(rscratch2, mdo_addr);
2657 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2658 __ str(rscratch2, mdo_addr);
2659 }
2660 if (do_update) {
2661 #ifndef ASSERT
2662 __ b(next);
2663 }
2664 #else
2665 __ b(next);
2666 }
2667 } else {
2668 __ cbnz(tmp, update);
2669 __ stop("unexpected null obj");
2670 #endif
2671 }
2672
2673 __ bind(update);
2674
2675 if (do_update) {
2676 #ifdef ASSERT
2677 if (exact_klass != nullptr) {
2678 Label ok;
2679 __ load_klass(tmp, tmp);
2680 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2681 __ eor(rscratch1, tmp, rscratch1);
2682 __ cbz(rscratch1, ok);
2683 __ stop("exact klass and actual klass differ");
2684 __ bind(ok);
2685 }
2686 #endif
2687 if (!no_conflict) {
2688 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2689 if (exact_klass != nullptr) {
2690 __ mov_metadata(tmp, exact_klass->constant_encoding());
2691 } else {
2692 __ load_klass(tmp, tmp);
2693 }
2694
2695 __ ldr(rscratch2, mdo_addr);
2696 __ eor(tmp, tmp, rscratch2);
2697 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2698 // klass seen before, nothing to do. The unknown bit may have been
2699 // set already but no need to check.
2700 __ cbz(rscratch1, next);
2701
2702 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2703
2704 if (TypeEntries::is_type_none(current_klass)) {
2705 __ cbz(rscratch2, none);
2706 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2707 __ br(Assembler::EQ, none);
2708 // There is a chance that the checks above
2709 // fail if another thread has just set the
2710 // profiling to this obj's klass
2711 __ dmb(Assembler::ISHLD);
2712 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2713 __ ldr(rscratch2, mdo_addr);
2714 __ eor(tmp, tmp, rscratch2);
2715 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2716 __ cbz(rscratch1, next);
2717 }
2718 } else {
2719 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2720 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2721
2722 __ ldr(tmp, mdo_addr);
2723 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2724 }
2725
2726 // different than before. Cannot keep accurate profile.
2727 __ ldr(rscratch2, mdo_addr);
2728 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2729 __ str(rscratch2, mdo_addr);
2730
2731 if (TypeEntries::is_type_none(current_klass)) {
2732 __ b(next);
2733
2734 __ bind(none);
2735 // first time here. Set profile type.
2736 __ str(tmp, mdo_addr);
2737 #ifdef ASSERT
2738 __ andr(tmp, tmp, TypeEntries::type_mask);
2739 __ verify_klass_ptr(tmp);
2740 #endif
2741 }
2742 } else {
2743 // There's a single possible klass at this profile point
2744 assert(exact_klass != nullptr, "should be");
2745 if (TypeEntries::is_type_none(current_klass)) {
2746 __ mov_metadata(tmp, exact_klass->constant_encoding());
2747 __ ldr(rscratch2, mdo_addr);
2748 __ eor(tmp, tmp, rscratch2);
2749 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2750 __ cbz(rscratch1, next);
2751 #ifdef ASSERT
2752 {
2753 Label ok;
2754 __ ldr(rscratch1, mdo_addr);
2755 __ cbz(rscratch1, ok);
2756 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2757 __ br(Assembler::EQ, ok);
2758 // may have been set by another thread
2759 __ dmb(Assembler::ISHLD);
2760 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2761 __ ldr(rscratch2, mdo_addr);
2762 __ eor(rscratch2, rscratch1, rscratch2);
2763 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2764 __ cbz(rscratch2, ok);
2765
2766 __ stop("unexpected profiling mismatch");
2767 __ bind(ok);
2768 }
2769 #endif
2770 // first time here. Set profile type.
2771 __ str(tmp, mdo_addr);
2772 #ifdef ASSERT
2773 __ andr(tmp, tmp, TypeEntries::type_mask);
2774 __ verify_klass_ptr(tmp);
2775 #endif
2776 } else {
2777 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2778 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2779
2780 __ ldr(tmp, mdo_addr);
2781 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2782
2783 __ orr(tmp, tmp, TypeEntries::type_unknown);
2784 __ str(tmp, mdo_addr);
2785 // FIXME: Write barrier needed here?
2786 }
2787 }
2788
2789 __ bind(next);
2790 }
2791 COMMENT("} emit_profile_type");
2792 }
2793
2794
2795 void LIR_Assembler::align_backward_branch_target() {
2796 }
2797
2798
2799 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2800 // tmp must be unused
2801 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2802
2803 if (left->is_single_cpu()) {
2804 assert(dest->is_single_cpu(), "expect single result reg");
2805 __ negw(dest->as_register(), left->as_register());
2806 } else if (left->is_double_cpu()) {
2807 assert(dest->is_double_cpu(), "expect double result reg");
2808 __ neg(dest->as_register_lo(), left->as_register_lo());
2809 } else if (left->is_single_fpu()) {
2810 assert(dest->is_single_fpu(), "expect single float result reg");
2811 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2812 } else {
2813 assert(left->is_double_fpu(), "expect double float operand reg");
2814 assert(dest->is_double_fpu(), "expect double float result reg");
2815 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2816 }
2817 }
2818
2819
2820 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2821 if (patch_code != lir_patch_none) {
2822 deoptimize_trap(info);
2823 return;
2824 }
2825
2826 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2827 }
2828
2829
2830 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2831 assert(!tmp->is_valid(), "don't need temporary");
2832
2833 CodeBlob *cb = CodeCache::find_blob(dest);
2834 if (cb) {
2835 __ far_call(RuntimeAddress(dest));
2836 } else {
2837 __ mov(rscratch1, RuntimeAddress(dest));
2838 __ blr(rscratch1);
2839 }
2840
2841 if (info != nullptr) {
2842 add_call_info_here(info);
2843 }
2844 __ post_call_nop();
2845 }
2846
2847 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2848 if (dest->is_address() || src->is_address()) {
2849 move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
2850 } else {
2851 ShouldNotReachHere();
2852 }
2853 }
2854
2855 #ifdef ASSERT
2856 // emit run-time assertion
2857 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2858 assert(op->code() == lir_assert, "must be");
2859
2860 if (op->in_opr1()->is_valid()) {
2861 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2862 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2863 } else {
2864 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2865 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2866 }
2867
2868 Label ok;
2869 if (op->condition() != lir_cond_always) {
2870 Assembler::Condition acond = Assembler::AL;
2871 switch (op->condition()) {
2872 case lir_cond_equal: acond = Assembler::EQ; break;
2873 case lir_cond_notEqual: acond = Assembler::NE; break;
2874 case lir_cond_less: acond = Assembler::LT; break;
2875 case lir_cond_lessEqual: acond = Assembler::LE; break;
2876 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2877 case lir_cond_greater: acond = Assembler::GT; break;
2878 case lir_cond_belowEqual: acond = Assembler::LS; break;
2879 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2880 default: ShouldNotReachHere();
2881 }
2882 __ br(acond, ok);
2883 }
2884 if (op->halt()) {
2885 const char* str = __ code_string(op->msg());
2886 __ stop(str);
2887 } else {
2888 breakpoint();
2889 }
2890 __ bind(ok);
2891 }
2892 #endif
2893
2894 #ifndef PRODUCT
2895 #define COMMENT(x) do { __ block_comment(x); } while (0)
2896 #else
2897 #define COMMENT(x)
2898 #endif
2899
2900 void LIR_Assembler::membar() {
2901 COMMENT("membar");
2902 __ membar(MacroAssembler::AnyAny);
2903 }
2904
2905 void LIR_Assembler::membar_acquire() {
2906 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2907 }
2908
2909 void LIR_Assembler::membar_release() {
2910 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2911 }
2912
2913 void LIR_Assembler::membar_loadload() {
2914 __ membar(Assembler::LoadLoad);
2915 }
2916
2917 void LIR_Assembler::membar_storestore() {
2918 __ membar(MacroAssembler::StoreStore);
2919 }
2920
2921 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2922
2923 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2924
2925 void LIR_Assembler::on_spin_wait() {
2926 __ spin_wait();
2927 }
2928
2929 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2930 __ mov(result_reg->as_register(), rthread);
2931 }
2932
2933
2934 void LIR_Assembler::peephole(LIR_List *lir) {
2935 #if 0
2936 if (tableswitch_count >= max_tableswitches)
2937 return;
2938
2939 /*
2940 This finite-state automaton recognizes sequences of compare-and-
2941 branch instructions. We will turn them into a tableswitch. You
2942 could argue that C1 really shouldn't be doing this sort of
2943 optimization, but without it the code is really horrible.
2944 */
2945
2946 enum { start_s, cmp1_s, beq_s, cmp_s } state;
2947 int first_key, last_key = -2147483648;
2948 int next_key = 0;
2949 int start_insn = -1;
2950 int last_insn = -1;
2951 Register reg = noreg;
2952 LIR_Opr reg_opr;
2953 state = start_s;
2954
2955 LIR_OpList* inst = lir->instructions_list();
2956 for (int i = 0; i < inst->length(); i++) {
2957 LIR_Op* op = inst->at(i);
2958 switch (state) {
2959 case start_s:
2960 first_key = -1;
2961 start_insn = i;
2962 switch (op->code()) {
2963 case lir_cmp:
2964 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2965 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2966 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2967 && opr2->is_constant()
2968 && opr2->type() == T_INT) {
2969 reg_opr = opr1;
2970 reg = opr1->as_register();
2971 first_key = opr2->as_constant_ptr()->as_jint();
2972 next_key = first_key + 1;
2973 state = cmp_s;
2974 goto next_state;
2975 }
2976 break;
2977 }
2978 break;
2979 case cmp_s:
2980 switch (op->code()) {
2981 case lir_branch:
2982 if (op->as_OpBranch()->cond() == lir_cond_equal) {
2983 state = beq_s;
2984 last_insn = i;
2985 goto next_state;
2986 }
2987 }
2988 state = start_s;
2989 break;
2990 case beq_s:
2991 switch (op->code()) {
2992 case lir_cmp: {
2993 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2994 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2995 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2996 && opr1->as_register() == reg
2997 && opr2->is_constant()
2998 && opr2->type() == T_INT
2999 && opr2->as_constant_ptr()->as_jint() == next_key) {
3000 last_key = next_key;
3001 next_key++;
3002 state = cmp_s;
3003 goto next_state;
3004 }
3005 }
3006 }
3007 last_key = next_key;
3008 state = start_s;
3009 break;
3010 default:
3011 assert(false, "impossible state");
3012 }
3013 if (state == start_s) {
3014 if (first_key < last_key - 5L && reg != noreg) {
3015 {
3016 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3017 // reg->encoding(),
3018 // start_insn, first_key, last_key);
3019 // for (int i = 0; i < inst->length(); i++) {
3020 // inst->at(i)->print();
3021 // tty->print("\n");
3022 // }
3023 // tty->print("\n");
3024 }
3025
3026 struct tableswitch *sw = &switches[tableswitch_count];
3027 sw->_insn_index = start_insn, sw->_first_key = first_key,
3028 sw->_last_key = last_key, sw->_reg = reg;
3029 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3030 {
3031 // Insert the new table of branches
3032 int offset = last_insn;
3033 for (int n = first_key; n < last_key; n++) {
3034 inst->insert_before
3035 (last_insn + 1,
3036 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3037 inst->at(offset)->as_OpBranch()->label()));
3038 offset -= 2, i++;
3039 }
3040 }
3041 // Delete all the old compare-and-branch instructions
3042 for (int n = first_key; n < last_key; n++) {
3043 inst->remove_at(start_insn);
3044 inst->remove_at(start_insn);
3045 }
3046 // Insert the tableswitch instruction
3047 inst->insert_before(start_insn,
3048 new LIR_Op2(lir_cmp, lir_cond_always,
3049 LIR_OprFact::intConst(tableswitch_count),
3050 reg_opr));
3051 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3052 tableswitch_count++;
3053 }
3054 reg = noreg;
3055 last_key = -2147483648;
3056 }
3057 next_state:
3058 ;
3059 }
3060 #endif
3061 }
3062
3063 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3064 Address addr = as_Address(src->as_address_ptr());
3065 BasicType type = src->type();
3066 bool is_oop = is_reference_type(type);
3067
3068 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3069 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3070
3071 switch(type) {
3072 case T_INT:
3073 xchg = &MacroAssembler::atomic_xchgalw;
3074 add = &MacroAssembler::atomic_addalw;
3075 break;
3076 case T_LONG:
3077 xchg = &MacroAssembler::atomic_xchgal;
3078 add = &MacroAssembler::atomic_addal;
3079 break;
3080 case T_OBJECT:
3081 case T_ARRAY:
3082 if (UseCompressedOops) {
3083 xchg = &MacroAssembler::atomic_xchgalw;
3084 add = &MacroAssembler::atomic_addalw;
3085 } else {
3086 xchg = &MacroAssembler::atomic_xchgal;
3087 add = &MacroAssembler::atomic_addal;
3088 }
3089 break;
3090 default:
3091 ShouldNotReachHere();
3092 xchg = &MacroAssembler::atomic_xchgal;
3093 add = &MacroAssembler::atomic_addal; // unreachable
3094 }
3095
3096 switch (code) {
3097 case lir_xadd:
3098 {
3099 RegisterOrConstant inc;
3100 Register tmp = as_reg(tmp_op);
3101 Register dst = as_reg(dest);
3102 if (data->is_constant()) {
3103 inc = RegisterOrConstant(as_long(data));
3104 assert_different_registers(dst, addr.base(), tmp,
3105 rscratch1, rscratch2);
3106 } else {
3107 inc = RegisterOrConstant(as_reg(data));
3108 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3109 rscratch1, rscratch2);
3110 }
3111 __ lea(tmp, addr);
3112 (_masm->*add)(dst, inc, tmp);
3113 break;
3114 }
3115 case lir_xchg:
3116 {
3117 Register tmp = tmp_op->as_register();
3118 Register obj = as_reg(data);
3119 Register dst = as_reg(dest);
3120 if (is_oop && UseCompressedOops) {
3121 __ encode_heap_oop(rscratch2, obj);
3122 obj = rscratch2;
3123 }
3124 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3125 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3126 __ lea(tmp, addr);
3127 (_masm->*xchg)(dst, obj, tmp);
3128 if (is_oop && UseCompressedOops) {
3129 __ decode_heap_oop(dst);
3130 }
3131 }
3132 break;
3133 default:
3134 ShouldNotReachHere();
3135 }
3136 __ membar(__ AnyAny);
3137 }
3138
3139 #undef __