1 /*
2 * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "code/compiledIC.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/gc_globals.hpp"
40 #include "nativeInst_aarch64.hpp"
41 #include "oops/objArrayKlass.hpp"
42 #include "runtime/frame.inline.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "utilities/powerOfTwo.hpp"
46 #include "vmreg_aarch64.inline.hpp"
47
48
49 #ifndef PRODUCT
50 #define COMMENT(x) do { __ block_comment(x); } while (0)
51 #else
52 #define COMMENT(x)
53 #endif
54
55 NEEDS_CLEANUP // remove this definitions ?
56 const Register SYNC_header = r0; // synchronization header
57 const Register SHIFT_count = r0; // where count for shift operations must be
58
59 #define __ _masm->
60
61
62 static void select_different_registers(Register preserve,
63 Register extra,
64 Register &tmp1,
65 Register &tmp2) {
66 if (tmp1 == preserve) {
67 assert_different_registers(tmp1, tmp2, extra);
68 tmp1 = extra;
69 } else if (tmp2 == preserve) {
70 assert_different_registers(tmp1, tmp2, extra);
71 tmp2 = extra;
72 }
73 assert_different_registers(preserve, tmp1, tmp2);
74 }
75
76
77
78 static void select_different_registers(Register preserve,
79 Register extra,
80 Register &tmp1,
81 Register &tmp2,
82 Register &tmp3) {
83 if (tmp1 == preserve) {
84 assert_different_registers(tmp1, tmp2, tmp3, extra);
85 tmp1 = extra;
86 } else if (tmp2 == preserve) {
87 assert_different_registers(tmp1, tmp2, tmp3, extra);
88 tmp2 = extra;
89 } else if (tmp3 == preserve) {
90 assert_different_registers(tmp1, tmp2, tmp3, extra);
91 tmp3 = extra;
92 }
93 assert_different_registers(preserve, tmp1, tmp2, tmp3);
94 }
95
96
97 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
98
99
100 LIR_Opr LIR_Assembler::receiverOpr() {
101 return FrameMap::receiver_opr;
102 }
103
104 LIR_Opr LIR_Assembler::osrBufferPointer() {
105 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
106 }
107
108 //--------------fpu register translations-----------------------
109
110
111 address LIR_Assembler::float_constant(float f) {
112 address const_addr = __ float_constant(f);
113 if (const_addr == nullptr) {
114 bailout("const section overflow");
115 return __ code()->consts()->start();
116 } else {
117 return const_addr;
118 }
119 }
120
121
122 address LIR_Assembler::double_constant(double d) {
123 address const_addr = __ double_constant(d);
124 if (const_addr == nullptr) {
125 bailout("const section overflow");
126 return __ code()->consts()->start();
127 } else {
128 return const_addr;
129 }
130 }
131
132 address LIR_Assembler::int_constant(jlong n) {
133 address const_addr = __ long_constant(n);
134 if (const_addr == nullptr) {
135 bailout("const section overflow");
136 return __ code()->consts()->start();
137 } else {
138 return const_addr;
139 }
140 }
141
142 void LIR_Assembler::breakpoint() { Unimplemented(); }
143
144 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
145
146 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
147
148 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
149 //-------------------------------------------
150
151 static Register as_reg(LIR_Opr op) {
152 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
153 }
154
155 static jlong as_long(LIR_Opr data) {
156 jlong result;
157 switch (data->type()) {
158 case T_INT:
159 result = (data->as_jint());
160 break;
161 case T_LONG:
162 result = (data->as_jlong());
163 break;
164 default:
165 ShouldNotReachHere();
166 result = 0; // unreachable
167 }
168 return result;
169 }
170
171 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
172 Register base = addr->base()->as_pointer_register();
173 LIR_Opr opr = addr->index();
174 if (opr->is_cpu_register()) {
175 Register index;
176 if (opr->is_single_cpu())
177 index = opr->as_register();
178 else
179 index = opr->as_register_lo();
180 assert(addr->disp() == 0, "must be");
181 switch(opr->type()) {
182 case T_INT:
183 return Address(base, index, Address::sxtw(addr->scale()));
184 case T_LONG:
185 return Address(base, index, Address::lsl(addr->scale()));
186 default:
187 ShouldNotReachHere();
188 }
189 } else {
190 assert(addr->scale() == 0,
191 "expected for immediate operand, was: %d", addr->scale());
192 ptrdiff_t offset = ptrdiff_t(addr->disp());
193 // NOTE: Does not handle any 16 byte vector access.
194 const uint type_size = type2aelembytes(addr->type(), true);
195 return __ legitimize_address(Address(base, offset), type_size, tmp);
196 }
197 return Address();
198 }
199
200 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
201 ShouldNotReachHere();
202 return Address();
203 }
204
205 Address LIR_Assembler::as_Address(LIR_Address* addr) {
206 return as_Address(addr, rscratch1);
207 }
208
209 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
210 return as_Address(addr, rscratch1); // Ouch
211 // FIXME: This needs to be much more clever. See x86.
212 }
213
214 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
215 // not encodable as a base + (immediate) offset, generate an explicit address
216 // calculation to hold the address in a temporary register.
217 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
218 precond(size == 4 || size == 8);
219 Address addr = frame_map()->address_for_slot(index, adjust);
220 precond(addr.getMode() == Address::base_plus_offset);
221 precond(addr.base() == sp);
222 precond(addr.offset() > 0);
223 uint mask = size - 1;
224 assert((addr.offset() & mask) == 0, "scaled offsets only");
225 return __ legitimize_address(addr, size, tmp);
226 }
227
228 void LIR_Assembler::osr_entry() {
229 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
230 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
231 ValueStack* entry_state = osr_entry->state();
232 int number_of_locks = entry_state->locks_size();
233
234 // we jump here if osr happens with the interpreter
235 // state set up to continue at the beginning of the
236 // loop that triggered osr - in particular, we have
237 // the following registers setup:
238 //
239 // r2: osr buffer
240 //
241
242 // build frame
243 ciMethod* m = compilation()->method();
244 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
245
246 // OSR buffer is
247 //
248 // locals[nlocals-1..0]
249 // monitors[0..number_of_locks]
250 //
251 // locals is a direct copy of the interpreter frame so in the osr buffer
252 // so first slot in the local array is the last local from the interpreter
253 // and last slot is local[0] (receiver) from the interpreter
254 //
255 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
256 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
257 // in the interpreter frame (the method lock if a sync method)
258
259 // Initialize monitors in the compiled activation.
260 // r2: pointer to osr buffer
261 //
262 // All other registers are dead at this point and the locals will be
263 // copied into place by code emitted in the IR.
264
265 Register OSR_buf = osrBufferPointer()->as_pointer_register();
266 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
267 int monitor_offset = BytesPerWord * method()->max_locals() +
268 (2 * BytesPerWord) * (number_of_locks - 1);
269 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
270 // the OSR buffer using 2 word entries: first the lock and then
271 // the oop.
272 for (int i = 0; i < number_of_locks; i++) {
273 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
274 #ifdef ASSERT
275 // verify the interpreter's monitor has a non-null object
276 {
277 Label L;
278 __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
279 __ cbnz(rscratch1, L);
280 __ stop("locked object is null");
281 __ bind(L);
282 }
283 #endif
284 __ ldr(r19, Address(OSR_buf, slot_offset));
285 __ ldr(r20, Address(OSR_buf, slot_offset + BytesPerWord));
286 __ str(r19, frame_map()->address_for_monitor_lock(i));
287 __ str(r20, frame_map()->address_for_monitor_object(i));
288 }
289 }
290 }
291
292
293 // inline cache check; done before the frame is built.
294 int LIR_Assembler::check_icache() {
295 return __ ic_check(CodeEntryAlignment);
296 }
297
298 void LIR_Assembler::clinit_barrier(ciMethod* method) {
299 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
300 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
301
302 Label L_skip_barrier;
303
304 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
305 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
306 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
307 __ bind(L_skip_barrier);
308 }
309
310 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
311 if (o == nullptr) {
312 __ mov(reg, zr);
313 } else {
314 __ movoop(reg, o);
315 }
316 }
317
318 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
319 address target = nullptr;
320 relocInfo::relocType reloc_type = relocInfo::none;
321
322 switch (patching_id(info)) {
323 case PatchingStub::access_field_id:
324 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
325 reloc_type = relocInfo::section_word_type;
326 break;
327 case PatchingStub::load_klass_id:
328 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
329 reloc_type = relocInfo::metadata_type;
330 break;
331 case PatchingStub::load_mirror_id:
332 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
333 reloc_type = relocInfo::oop_type;
334 break;
335 case PatchingStub::load_appendix_id:
336 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
337 reloc_type = relocInfo::oop_type;
338 break;
339 default: ShouldNotReachHere();
340 }
341
342 __ far_call(RuntimeAddress(target));
343 add_call_info_here(info);
344 }
345
346 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
347 deoptimize_trap(info);
348 }
349
350
351 // This specifies the rsp decrement needed to build the frame
352 int LIR_Assembler::initial_frame_size_in_bytes() const {
353 // if rounding, must let FrameMap know!
354
355 return in_bytes(frame_map()->framesize_in_bytes());
356 }
357
358
359 int LIR_Assembler::emit_exception_handler() {
360 // generate code for exception handler
361 address handler_base = __ start_a_stub(exception_handler_size());
362 if (handler_base == nullptr) {
363 // not enough space left for the handler
364 bailout("exception handler overflow");
365 return -1;
366 }
367
368 int offset = code_offset();
369
370 // the exception oop and pc are in r0, and r3
371 // no other registers need to be preserved, so invalidate them
372 __ invalidate_registers(false, true, true, false, true, true);
373
374 // check that there is really an exception
375 __ verify_not_null_oop(r0);
376
377 // search an exception handler (r0: exception oop, r3: throwing pc)
378 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
379 __ should_not_reach_here();
380 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
381 __ end_a_stub();
382
383 return offset;
384 }
385
386
387 // Emit the code to remove the frame from the stack in the exception
388 // unwind path.
389 int LIR_Assembler::emit_unwind_handler() {
390 #ifndef PRODUCT
391 if (CommentedAssembly) {
392 _masm->block_comment("Unwind handler");
393 }
394 #endif
395
396 int offset = code_offset();
397
398 // Fetch the exception from TLS and clear out exception related thread state
399 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
400 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
401 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
402
403 __ bind(_unwind_handler_entry);
404 __ verify_not_null_oop(r0);
405 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
406 __ mov(r19, r0); // Preserve the exception
407 }
408
409 // Perform needed unlocking
410 MonitorExitStub* stub = nullptr;
411 if (method()->is_synchronized()) {
412 monitor_address(0, FrameMap::r0_opr);
413 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
414 if (LockingMode == LM_MONITOR) {
415 __ b(*stub->entry());
416 } else {
417 __ unlock_object(r5, r4, r0, r6, *stub->entry());
418 }
419 __ bind(*stub->continuation());
420 }
421
422 if (compilation()->env()->dtrace_method_probes()) {
423 __ mov(c_rarg0, rthread);
424 __ mov_metadata(c_rarg1, method()->constant_encoding());
425 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
426 }
427
428 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
429 __ mov(r0, r19); // Restore the exception
430 }
431
432 // remove the activation and dispatch to the unwind handler
433 __ block_comment("remove_frame and dispatch to the unwind handler");
434 __ remove_frame(initial_frame_size_in_bytes());
435 __ far_jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
436
437 // Emit the slow path assembly
438 if (stub != nullptr) {
439 stub->emit_code(this);
440 }
441
442 return offset;
443 }
444
445
446 int LIR_Assembler::emit_deopt_handler() {
447 // generate code for exception handler
448 address handler_base = __ start_a_stub(deopt_handler_size());
449 if (handler_base == nullptr) {
450 // not enough space left for the handler
451 bailout("deopt handler overflow");
452 return -1;
453 }
454
455 int offset = code_offset();
456
457 __ adr(lr, pc());
458 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
459 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
460 __ end_a_stub();
461
462 return offset;
463 }
464
465 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
466 _masm->code_section()->relocate(adr, relocInfo::poll_type);
467 int pc_offset = code_offset();
468 flush_debug_info(pc_offset);
469 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
470 if (info->exception_handlers() != nullptr) {
471 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
472 }
473 }
474
475 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
476 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
477
478 // Pop the stack before the safepoint code
479 __ remove_frame(initial_frame_size_in_bytes());
480
481 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
482 __ reserved_stack_check();
483 }
484
485 code_stub->set_safepoint_offset(__ offset());
486 __ relocate(relocInfo::poll_return_type);
487 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
488 __ ret(lr);
489 }
490
491 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
492 guarantee(info != nullptr, "Shouldn't be null");
493 __ get_polling_page(rscratch1, relocInfo::poll_type);
494 add_debug_info_for_branch(info); // This isn't just debug info:
495 // it's the oop map
496 __ read_polling_page(rscratch1, relocInfo::poll_type);
497 return __ offset();
498 }
499
500
501 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
502 if (from_reg == r31_sp)
503 from_reg = sp;
504 if (to_reg == r31_sp)
505 to_reg = sp;
506 __ mov(to_reg, from_reg);
507 }
508
509 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
510
511
512 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
513 assert(src->is_constant(), "should not call otherwise");
514 assert(dest->is_register(), "should not call otherwise");
515 LIR_Const* c = src->as_constant_ptr();
516
517 switch (c->type()) {
518 case T_INT: {
519 assert(patch_code == lir_patch_none, "no patching handled here");
520 __ movw(dest->as_register(), c->as_jint());
521 break;
522 }
523
524 case T_ADDRESS: {
525 assert(patch_code == lir_patch_none, "no patching handled here");
526 __ mov(dest->as_register(), c->as_jint());
527 break;
528 }
529
530 case T_LONG: {
531 assert(patch_code == lir_patch_none, "no patching handled here");
532 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
533 break;
534 }
535
536 case T_OBJECT: {
537 if (patch_code == lir_patch_none) {
538 jobject2reg(c->as_jobject(), dest->as_register());
539 } else {
540 jobject2reg_with_patching(dest->as_register(), info);
541 }
542 break;
543 }
544
545 case T_METADATA: {
546 if (patch_code != lir_patch_none) {
547 klass2reg_with_patching(dest->as_register(), info);
548 } else {
549 __ mov_metadata(dest->as_register(), c->as_metadata());
550 }
551 break;
552 }
553
554 case T_FLOAT: {
555 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
556 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
557 } else {
558 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
559 __ ldrs(dest->as_float_reg(), Address(rscratch1));
560 }
561 break;
562 }
563
564 case T_DOUBLE: {
565 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
566 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
567 } else {
568 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
569 __ ldrd(dest->as_double_reg(), Address(rscratch1));
570 }
571 break;
572 }
573
574 default:
575 ShouldNotReachHere();
576 }
577 }
578
579 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
580 LIR_Const* c = src->as_constant_ptr();
581 switch (c->type()) {
582 case T_OBJECT:
583 {
584 if (! c->as_jobject())
585 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
586 else {
587 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
588 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
589 }
590 }
591 break;
592 case T_ADDRESS:
593 {
594 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
595 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
596 }
597 case T_INT:
598 case T_FLOAT:
599 {
600 Register reg = zr;
601 if (c->as_jint_bits() == 0)
602 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
603 else {
604 __ movw(rscratch1, c->as_jint_bits());
605 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
606 }
607 }
608 break;
609 case T_LONG:
610 case T_DOUBLE:
611 {
612 Register reg = zr;
613 if (c->as_jlong_bits() == 0)
614 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
615 lo_word_offset_in_bytes));
616 else {
617 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
618 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
619 lo_word_offset_in_bytes));
620 }
621 }
622 break;
623 default:
624 ShouldNotReachHere();
625 }
626 }
627
628 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
629 assert(src->is_constant(), "should not call otherwise");
630 LIR_Const* c = src->as_constant_ptr();
631 LIR_Address* to_addr = dest->as_address_ptr();
632
633 void (Assembler::* insn)(Register Rt, const Address &adr);
634
635 switch (type) {
636 case T_ADDRESS:
637 assert(c->as_jint() == 0, "should be");
638 insn = &Assembler::str;
639 break;
640 case T_LONG:
641 assert(c->as_jlong() == 0, "should be");
642 insn = &Assembler::str;
643 break;
644 case T_INT:
645 assert(c->as_jint() == 0, "should be");
646 insn = &Assembler::strw;
647 break;
648 case T_OBJECT:
649 case T_ARRAY:
650 assert(c->as_jobject() == nullptr, "should be");
651 if (UseCompressedOops && !wide) {
652 insn = &Assembler::strw;
653 } else {
654 insn = &Assembler::str;
655 }
656 break;
657 case T_CHAR:
658 case T_SHORT:
659 assert(c->as_jint() == 0, "should be");
660 insn = &Assembler::strh;
661 break;
662 case T_BOOLEAN:
663 case T_BYTE:
664 assert(c->as_jint() == 0, "should be");
665 insn = &Assembler::strb;
666 break;
667 default:
668 ShouldNotReachHere();
669 insn = &Assembler::str; // unreachable
670 }
671
672 if (info) add_debug_info_for_null_check_here(info);
673 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
674 }
675
676 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
677 assert(src->is_register(), "should not call otherwise");
678 assert(dest->is_register(), "should not call otherwise");
679
680 // move between cpu-registers
681 if (dest->is_single_cpu()) {
682 if (src->type() == T_LONG) {
683 // Can do LONG -> OBJECT
684 move_regs(src->as_register_lo(), dest->as_register());
685 return;
686 }
687 assert(src->is_single_cpu(), "must match");
688 if (src->type() == T_OBJECT) {
689 __ verify_oop(src->as_register());
690 }
691 move_regs(src->as_register(), dest->as_register());
692
693 } else if (dest->is_double_cpu()) {
694 if (is_reference_type(src->type())) {
695 // Surprising to me but we can see move of a long to t_object
696 __ verify_oop(src->as_register());
697 move_regs(src->as_register(), dest->as_register_lo());
698 return;
699 }
700 assert(src->is_double_cpu(), "must match");
701 Register f_lo = src->as_register_lo();
702 Register f_hi = src->as_register_hi();
703 Register t_lo = dest->as_register_lo();
704 Register t_hi = dest->as_register_hi();
705 assert(f_hi == f_lo, "must be same");
706 assert(t_hi == t_lo, "must be same");
707 move_regs(f_lo, t_lo);
708
709 } else if (dest->is_single_fpu()) {
710 __ fmovs(dest->as_float_reg(), src->as_float_reg());
711
712 } else if (dest->is_double_fpu()) {
713 __ fmovd(dest->as_double_reg(), src->as_double_reg());
714
715 } else {
716 ShouldNotReachHere();
717 }
718 }
719
720 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
721 precond(src->is_register() && dest->is_stack());
722
723 uint const c_sz32 = sizeof(uint32_t);
724 uint const c_sz64 = sizeof(uint64_t);
725
726 if (src->is_single_cpu()) {
727 int index = dest->single_stack_ix();
728 if (is_reference_type(type)) {
729 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
730 __ verify_oop(src->as_register());
731 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
732 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
733 } else {
734 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
735 }
736
737 } else if (src->is_double_cpu()) {
738 int index = dest->double_stack_ix();
739 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
740 __ str(src->as_register_lo(), dest_addr_LO);
741
742 } else if (src->is_single_fpu()) {
743 int index = dest->single_stack_ix();
744 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
745
746 } else if (src->is_double_fpu()) {
747 int index = dest->double_stack_ix();
748 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
749
750 } else {
751 ShouldNotReachHere();
752 }
753 }
754
755
756 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
757 LIR_Address* to_addr = dest->as_address_ptr();
758 PatchingStub* patch = nullptr;
759 Register compressed_src = rscratch1;
760
761 if (patch_code != lir_patch_none) {
762 deoptimize_trap(info);
763 return;
764 }
765
766 if (is_reference_type(type)) {
767 __ verify_oop(src->as_register());
768
769 if (UseCompressedOops && !wide) {
770 __ encode_heap_oop(compressed_src, src->as_register());
771 } else {
772 compressed_src = src->as_register();
773 }
774 }
775
776 int null_check_here = code_offset();
777 switch (type) {
778 case T_FLOAT: {
779 __ strs(src->as_float_reg(), as_Address(to_addr));
780 break;
781 }
782
783 case T_DOUBLE: {
784 __ strd(src->as_double_reg(), as_Address(to_addr));
785 break;
786 }
787
788 case T_ARRAY: // fall through
789 case T_OBJECT: // fall through
790 if (UseCompressedOops && !wide) {
791 __ strw(compressed_src, as_Address(to_addr, rscratch2));
792 } else {
793 __ str(compressed_src, as_Address(to_addr));
794 }
795 break;
796 case T_METADATA:
797 // We get here to store a method pointer to the stack to pass to
798 // a dtrace runtime call. This can't work on 64 bit with
799 // compressed klass ptrs: T_METADATA can be a compressed klass
800 // ptr or a 64 bit method pointer.
801 ShouldNotReachHere();
802 __ str(src->as_register(), as_Address(to_addr));
803 break;
804 case T_ADDRESS:
805 __ str(src->as_register(), as_Address(to_addr));
806 break;
807 case T_INT:
808 __ strw(src->as_register(), as_Address(to_addr));
809 break;
810
811 case T_LONG: {
812 __ str(src->as_register_lo(), as_Address_lo(to_addr));
813 break;
814 }
815
816 case T_BYTE: // fall through
817 case T_BOOLEAN: {
818 __ strb(src->as_register(), as_Address(to_addr));
819 break;
820 }
821
822 case T_CHAR: // fall through
823 case T_SHORT:
824 __ strh(src->as_register(), as_Address(to_addr));
825 break;
826
827 default:
828 ShouldNotReachHere();
829 }
830 if (info != nullptr) {
831 add_debug_info_for_null_check(null_check_here, info);
832 }
833 }
834
835
836 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
837 precond(src->is_stack() && dest->is_register());
838
839 uint const c_sz32 = sizeof(uint32_t);
840 uint const c_sz64 = sizeof(uint64_t);
841
842 if (dest->is_single_cpu()) {
843 int index = src->single_stack_ix();
844 if (is_reference_type(type)) {
845 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
846 __ verify_oop(dest->as_register());
847 } else if (type == T_METADATA || type == T_ADDRESS) {
848 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
849 } else {
850 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
851 }
852
853 } else if (dest->is_double_cpu()) {
854 int index = src->double_stack_ix();
855 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
856 __ ldr(dest->as_register_lo(), src_addr_LO);
857
858 } else if (dest->is_single_fpu()) {
859 int index = src->single_stack_ix();
860 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
861
862 } else if (dest->is_double_fpu()) {
863 int index = src->double_stack_ix();
864 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
865
866 } else {
867 ShouldNotReachHere();
868 }
869 }
870
871
872 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
873 address target = nullptr;
874 relocInfo::relocType reloc_type = relocInfo::none;
875
876 switch (patching_id(info)) {
877 case PatchingStub::access_field_id:
878 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
879 reloc_type = relocInfo::section_word_type;
880 break;
881 case PatchingStub::load_klass_id:
882 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
883 reloc_type = relocInfo::metadata_type;
884 break;
885 case PatchingStub::load_mirror_id:
886 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
887 reloc_type = relocInfo::oop_type;
888 break;
889 case PatchingStub::load_appendix_id:
890 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
891 reloc_type = relocInfo::oop_type;
892 break;
893 default: ShouldNotReachHere();
894 }
895
896 __ far_call(RuntimeAddress(target));
897 add_call_info_here(info);
898 }
899
900 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
901
902 LIR_Opr temp;
903 if (type == T_LONG || type == T_DOUBLE)
904 temp = FrameMap::rscratch1_long_opr;
905 else
906 temp = FrameMap::rscratch1_opr;
907
908 stack2reg(src, temp, src->type());
909 reg2stack(temp, dest, dest->type(), false);
910 }
911
912
913 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
914 LIR_Address* addr = src->as_address_ptr();
915 LIR_Address* from_addr = src->as_address_ptr();
916
917 if (addr->base()->type() == T_OBJECT) {
918 __ verify_oop(addr->base()->as_pointer_register());
919 }
920
921 if (patch_code != lir_patch_none) {
922 deoptimize_trap(info);
923 return;
924 }
925
926 if (info != nullptr) {
927 add_debug_info_for_null_check_here(info);
928 }
929 int null_check_here = code_offset();
930 switch (type) {
931 case T_FLOAT: {
932 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
933 break;
934 }
935
936 case T_DOUBLE: {
937 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
938 break;
939 }
940
941 case T_ARRAY: // fall through
942 case T_OBJECT: // fall through
943 if (UseCompressedOops && !wide) {
944 __ ldrw(dest->as_register(), as_Address(from_addr));
945 } else {
946 __ ldr(dest->as_register(), as_Address(from_addr));
947 }
948 break;
949 case T_METADATA:
950 // We get here to store a method pointer to the stack to pass to
951 // a dtrace runtime call. This can't work on 64 bit with
952 // compressed klass ptrs: T_METADATA can be a compressed klass
953 // ptr or a 64 bit method pointer.
954 ShouldNotReachHere();
955 __ ldr(dest->as_register(), as_Address(from_addr));
956 break;
957 case T_ADDRESS:
958 __ ldr(dest->as_register(), as_Address(from_addr));
959 break;
960 case T_INT:
961 __ ldrw(dest->as_register(), as_Address(from_addr));
962 break;
963
964 case T_LONG: {
965 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
966 break;
967 }
968
969 case T_BYTE:
970 __ ldrsb(dest->as_register(), as_Address(from_addr));
971 break;
972 case T_BOOLEAN: {
973 __ ldrb(dest->as_register(), as_Address(from_addr));
974 break;
975 }
976
977 case T_CHAR:
978 __ ldrh(dest->as_register(), as_Address(from_addr));
979 break;
980 case T_SHORT:
981 __ ldrsh(dest->as_register(), as_Address(from_addr));
982 break;
983
984 default:
985 ShouldNotReachHere();
986 }
987
988 if (is_reference_type(type)) {
989 if (UseCompressedOops && !wide) {
990 __ decode_heap_oop(dest->as_register());
991 }
992
993 if (!(UseZGC && !ZGenerational)) {
994 // Load barrier has not yet been applied, so ZGC can't verify the oop here
995 __ verify_oop(dest->as_register());
996 }
997 }
998 }
999
1000
1001 int LIR_Assembler::array_element_size(BasicType type) const {
1002 int elem_size = type2aelembytes(type);
1003 return exact_log2(elem_size);
1004 }
1005
1006
1007 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1008 switch (op->code()) {
1009 case lir_idiv:
1010 case lir_irem:
1011 arithmetic_idiv(op->code(),
1012 op->in_opr1(),
1013 op->in_opr2(),
1014 op->in_opr3(),
1015 op->result_opr(),
1016 op->info());
1017 break;
1018 case lir_fmad:
1019 __ fmaddd(op->result_opr()->as_double_reg(),
1020 op->in_opr1()->as_double_reg(),
1021 op->in_opr2()->as_double_reg(),
1022 op->in_opr3()->as_double_reg());
1023 break;
1024 case lir_fmaf:
1025 __ fmadds(op->result_opr()->as_float_reg(),
1026 op->in_opr1()->as_float_reg(),
1027 op->in_opr2()->as_float_reg(),
1028 op->in_opr3()->as_float_reg());
1029 break;
1030 default: ShouldNotReachHere(); break;
1031 }
1032 }
1033
1034 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1035 #ifdef ASSERT
1036 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1037 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1038 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1039 #endif
1040
1041 if (op->cond() == lir_cond_always) {
1042 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1043 __ b(*(op->label()));
1044 } else {
1045 Assembler::Condition acond;
1046 if (op->code() == lir_cond_float_branch) {
1047 bool is_unordered = (op->ublock() == op->block());
1048 // Assembler::EQ does not permit unordered branches, so we add
1049 // another branch here. Likewise, Assembler::NE does not permit
1050 // ordered branches.
1051 if ((is_unordered && op->cond() == lir_cond_equal)
1052 || (!is_unordered && op->cond() == lir_cond_notEqual))
1053 __ br(Assembler::VS, *(op->ublock()->label()));
1054 switch(op->cond()) {
1055 case lir_cond_equal: acond = Assembler::EQ; break;
1056 case lir_cond_notEqual: acond = Assembler::NE; break;
1057 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1058 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1059 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1060 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1061 default: ShouldNotReachHere();
1062 acond = Assembler::EQ; // unreachable
1063 }
1064 } else {
1065 switch (op->cond()) {
1066 case lir_cond_equal: acond = Assembler::EQ; break;
1067 case lir_cond_notEqual: acond = Assembler::NE; break;
1068 case lir_cond_less: acond = Assembler::LT; break;
1069 case lir_cond_lessEqual: acond = Assembler::LE; break;
1070 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1071 case lir_cond_greater: acond = Assembler::GT; break;
1072 case lir_cond_belowEqual: acond = Assembler::LS; break;
1073 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1074 default: ShouldNotReachHere();
1075 acond = Assembler::EQ; // unreachable
1076 }
1077 }
1078 __ br(acond,*(op->label()));
1079 }
1080 }
1081
1082
1083
1084 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1085 LIR_Opr src = op->in_opr();
1086 LIR_Opr dest = op->result_opr();
1087
1088 switch (op->bytecode()) {
1089 case Bytecodes::_i2f:
1090 {
1091 __ scvtfws(dest->as_float_reg(), src->as_register());
1092 break;
1093 }
1094 case Bytecodes::_i2d:
1095 {
1096 __ scvtfwd(dest->as_double_reg(), src->as_register());
1097 break;
1098 }
1099 case Bytecodes::_l2d:
1100 {
1101 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1102 break;
1103 }
1104 case Bytecodes::_l2f:
1105 {
1106 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1107 break;
1108 }
1109 case Bytecodes::_f2d:
1110 {
1111 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1112 break;
1113 }
1114 case Bytecodes::_d2f:
1115 {
1116 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1117 break;
1118 }
1119 case Bytecodes::_i2c:
1120 {
1121 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1122 break;
1123 }
1124 case Bytecodes::_i2l:
1125 {
1126 __ sxtw(dest->as_register_lo(), src->as_register());
1127 break;
1128 }
1129 case Bytecodes::_i2s:
1130 {
1131 __ sxth(dest->as_register(), src->as_register());
1132 break;
1133 }
1134 case Bytecodes::_i2b:
1135 {
1136 __ sxtb(dest->as_register(), src->as_register());
1137 break;
1138 }
1139 case Bytecodes::_l2i:
1140 {
1141 _masm->block_comment("FIXME: This could be a no-op");
1142 __ uxtw(dest->as_register(), src->as_register_lo());
1143 break;
1144 }
1145 case Bytecodes::_d2l:
1146 {
1147 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1148 break;
1149 }
1150 case Bytecodes::_f2i:
1151 {
1152 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1153 break;
1154 }
1155 case Bytecodes::_f2l:
1156 {
1157 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1158 break;
1159 }
1160 case Bytecodes::_d2i:
1161 {
1162 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1163 break;
1164 }
1165 default: ShouldNotReachHere();
1166 }
1167 }
1168
1169 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1170 if (op->init_check()) {
1171 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1172 __ ldarb(rscratch1, rscratch1);
1173 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1174 add_debug_info_for_null_check_here(op->stub()->info());
1175 __ br(Assembler::NE, *op->stub()->entry());
1176 }
1177 __ allocate_object(op->obj()->as_register(),
1178 op->tmp1()->as_register(),
1179 op->tmp2()->as_register(),
1180 op->header_size(),
1181 op->object_size(),
1182 op->klass()->as_register(),
1183 *op->stub()->entry());
1184 __ bind(*op->stub()->continuation());
1185 }
1186
1187 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1188 Register len = op->len()->as_register();
1189 __ uxtw(len, len);
1190
1191 if (UseSlowPath ||
1192 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1193 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1194 __ b(*op->stub()->entry());
1195 } else {
1196 Register tmp1 = op->tmp1()->as_register();
1197 Register tmp2 = op->tmp2()->as_register();
1198 Register tmp3 = op->tmp3()->as_register();
1199 if (len == tmp1) {
1200 tmp1 = tmp3;
1201 } else if (len == tmp2) {
1202 tmp2 = tmp3;
1203 } else if (len == tmp3) {
1204 // everything is ok
1205 } else {
1206 __ mov(tmp3, len);
1207 }
1208 __ allocate_array(op->obj()->as_register(),
1209 len,
1210 tmp1,
1211 tmp2,
1212 arrayOopDesc::base_offset_in_bytes(op->type()),
1213 array_element_size(op->type()),
1214 op->klass()->as_register(),
1215 *op->stub()->entry(),
1216 op->zero_array());
1217 }
1218 __ bind(*op->stub()->continuation());
1219 }
1220
1221 void LIR_Assembler::type_profile_helper(Register mdo,
1222 ciMethodData *md, ciProfileData *data,
1223 Register recv, Label* update_done) {
1224 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1225 Label next_test;
1226 // See if the receiver is receiver[n].
1227 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1228 __ ldr(rscratch1, Address(rscratch2));
1229 __ cmp(recv, rscratch1);
1230 __ br(Assembler::NE, next_test);
1231 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1232 __ addptr(data_addr, DataLayout::counter_increment);
1233 __ b(*update_done);
1234 __ bind(next_test);
1235 }
1236
1237 // Didn't find receiver; find next empty slot and fill it in
1238 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1239 Label next_test;
1240 __ lea(rscratch2,
1241 Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1242 Address recv_addr(rscratch2);
1243 __ ldr(rscratch1, recv_addr);
1244 __ cbnz(rscratch1, next_test);
1245 __ str(recv, recv_addr);
1246 __ mov(rscratch1, DataLayout::counter_increment);
1247 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1248 __ str(rscratch1, Address(rscratch2));
1249 __ b(*update_done);
1250 __ bind(next_test);
1251 }
1252 }
1253
1254 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1255 // we always need a stub for the failure case.
1256 CodeStub* stub = op->stub();
1257 Register obj = op->object()->as_register();
1258 Register k_RInfo = op->tmp1()->as_register();
1259 Register klass_RInfo = op->tmp2()->as_register();
1260 Register dst = op->result_opr()->as_register();
1261 ciKlass* k = op->klass();
1262 Register Rtmp1 = noreg;
1263
1264 // check if it needs to be profiled
1265 ciMethodData* md;
1266 ciProfileData* data;
1267
1268 const bool should_profile = op->should_profile();
1269
1270 if (should_profile) {
1271 ciMethod* method = op->profiled_method();
1272 assert(method != nullptr, "Should have method");
1273 int bci = op->profiled_bci();
1274 md = method->method_data_or_null();
1275 assert(md != nullptr, "Sanity");
1276 data = md->bci_to_data(bci);
1277 assert(data != nullptr, "need data for type check");
1278 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1279 }
1280 Label* success_target = success;
1281 Label* failure_target = failure;
1282
1283 if (obj == k_RInfo) {
1284 k_RInfo = dst;
1285 } else if (obj == klass_RInfo) {
1286 klass_RInfo = dst;
1287 }
1288 if (k->is_loaded() && !UseCompressedClassPointers) {
1289 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1290 } else {
1291 Rtmp1 = op->tmp3()->as_register();
1292 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1293 }
1294
1295 assert_different_registers(obj, k_RInfo, klass_RInfo);
1296
1297 if (should_profile) {
1298 Register mdo = klass_RInfo;
1299 __ mov_metadata(mdo, md->constant_encoding());
1300 Label not_null;
1301 __ cbnz(obj, not_null);
1302 // Object is null; update MDO and exit
1303 Address data_addr
1304 = __ form_address(rscratch2, mdo,
1305 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1306 0);
1307 __ ldrb(rscratch1, data_addr);
1308 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1309 __ strb(rscratch1, data_addr);
1310 __ b(*obj_is_null);
1311 __ bind(not_null);
1312
1313 Label update_done;
1314 Register recv = k_RInfo;
1315 __ load_klass(recv, obj);
1316 type_profile_helper(mdo, md, data, recv, &update_done);
1317 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1318 __ addptr(counter_addr, DataLayout::counter_increment);
1319
1320 __ bind(update_done);
1321 } else {
1322 __ cbz(obj, *obj_is_null);
1323 }
1324
1325 if (!k->is_loaded()) {
1326 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1327 } else {
1328 __ mov_metadata(k_RInfo, k->constant_encoding());
1329 }
1330 __ verify_oop(obj);
1331
1332 if (op->fast_check()) {
1333 // get object class
1334 // not a safepoint as obj null check happens earlier
1335 __ load_klass(rscratch1, obj);
1336 __ cmp( rscratch1, k_RInfo);
1337
1338 __ br(Assembler::NE, *failure_target);
1339 // successful cast, fall through to profile or jump
1340 } else {
1341 // get object class
1342 // not a safepoint as obj null check happens earlier
1343 __ load_klass(klass_RInfo, obj);
1344 if (k->is_loaded()) {
1345 // See if we get an immediate positive hit
1346 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1347 __ cmp(k_RInfo, rscratch1);
1348 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1349 __ br(Assembler::NE, *failure_target);
1350 // successful cast, fall through to profile or jump
1351 } else {
1352 // See if we get an immediate positive hit
1353 __ br(Assembler::EQ, *success_target);
1354 // check for self
1355 __ cmp(klass_RInfo, k_RInfo);
1356 __ br(Assembler::EQ, *success_target);
1357
1358 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1359 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1360 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1361 // result is a boolean
1362 __ cbzw(klass_RInfo, *failure_target);
1363 // successful cast, fall through to profile or jump
1364 }
1365 } else {
1366 // perform the fast part of the checking logic
1367 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1368 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1369 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1370 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1371 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1372 // result is a boolean
1373 __ cbz(k_RInfo, *failure_target);
1374 // successful cast, fall through to profile or jump
1375 }
1376 }
1377 __ b(*success);
1378 }
1379
1380
1381 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1382 const bool should_profile = op->should_profile();
1383
1384 LIR_Code code = op->code();
1385 if (code == lir_store_check) {
1386 Register value = op->object()->as_register();
1387 Register array = op->array()->as_register();
1388 Register k_RInfo = op->tmp1()->as_register();
1389 Register klass_RInfo = op->tmp2()->as_register();
1390 Register Rtmp1 = op->tmp3()->as_register();
1391
1392 CodeStub* stub = op->stub();
1393
1394 // check if it needs to be profiled
1395 ciMethodData* md;
1396 ciProfileData* data;
1397
1398 if (should_profile) {
1399 ciMethod* method = op->profiled_method();
1400 assert(method != nullptr, "Should have method");
1401 int bci = op->profiled_bci();
1402 md = method->method_data_or_null();
1403 assert(md != nullptr, "Sanity");
1404 data = md->bci_to_data(bci);
1405 assert(data != nullptr, "need data for type check");
1406 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1407 }
1408 Label done;
1409 Label* success_target = &done;
1410 Label* failure_target = stub->entry();
1411
1412 if (should_profile) {
1413 Label not_null;
1414 Register mdo = klass_RInfo;
1415 __ mov_metadata(mdo, md->constant_encoding());
1416 __ cbnz(value, not_null);
1417 // Object is null; update MDO and exit
1418 Address data_addr
1419 = __ form_address(rscratch2, mdo,
1420 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1421 0);
1422 __ ldrb(rscratch1, data_addr);
1423 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1424 __ strb(rscratch1, data_addr);
1425 __ b(done);
1426 __ bind(not_null);
1427
1428 Label update_done;
1429 Register recv = k_RInfo;
1430 __ load_klass(recv, value);
1431 type_profile_helper(mdo, md, data, recv, &update_done);
1432 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1433 __ addptr(counter_addr, DataLayout::counter_increment);
1434 __ bind(update_done);
1435 } else {
1436 __ cbz(value, done);
1437 }
1438
1439 add_debug_info_for_null_check_here(op->info_for_exception());
1440 __ load_klass(k_RInfo, array);
1441 __ load_klass(klass_RInfo, value);
1442
1443 // get instance klass (it's already uncompressed)
1444 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1445 // perform the fast part of the checking logic
1446 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1447 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1448 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1449 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1450 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1451 // result is a boolean
1452 __ cbzw(k_RInfo, *failure_target);
1453 // fall through to the success case
1454
1455 __ bind(done);
1456 } else if (code == lir_checkcast) {
1457 Register obj = op->object()->as_register();
1458 Register dst = op->result_opr()->as_register();
1459 Label success;
1460 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1461 __ bind(success);
1462 if (dst != obj) {
1463 __ mov(dst, obj);
1464 }
1465 } else if (code == lir_instanceof) {
1466 Register obj = op->object()->as_register();
1467 Register dst = op->result_opr()->as_register();
1468 Label success, failure, done;
1469 emit_typecheck_helper(op, &success, &failure, &failure);
1470 __ bind(failure);
1471 __ mov(dst, zr);
1472 __ b(done);
1473 __ bind(success);
1474 __ mov(dst, 1);
1475 __ bind(done);
1476 } else {
1477 ShouldNotReachHere();
1478 }
1479 }
1480
1481 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1482 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1483 __ cset(rscratch1, Assembler::NE);
1484 __ membar(__ AnyAny);
1485 }
1486
1487 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1488 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1489 __ cset(rscratch1, Assembler::NE);
1490 __ membar(__ AnyAny);
1491 }
1492
1493
1494 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1495 Register addr;
1496 if (op->addr()->is_register()) {
1497 addr = as_reg(op->addr());
1498 } else {
1499 assert(op->addr()->is_address(), "what else?");
1500 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1501 assert(addr_ptr->disp() == 0, "need 0 disp");
1502 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1503 addr = as_reg(addr_ptr->base());
1504 }
1505 Register newval = as_reg(op->new_value());
1506 Register cmpval = as_reg(op->cmp_value());
1507
1508 if (op->code() == lir_cas_obj) {
1509 if (UseCompressedOops) {
1510 Register t1 = op->tmp1()->as_register();
1511 assert(op->tmp1()->is_valid(), "must be");
1512 __ encode_heap_oop(t1, cmpval);
1513 cmpval = t1;
1514 __ encode_heap_oop(rscratch2, newval);
1515 newval = rscratch2;
1516 casw(addr, newval, cmpval);
1517 } else {
1518 casl(addr, newval, cmpval);
1519 }
1520 } else if (op->code() == lir_cas_int) {
1521 casw(addr, newval, cmpval);
1522 } else {
1523 casl(addr, newval, cmpval);
1524 }
1525 }
1526
1527
1528 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1529 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1530 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1531
1532 Assembler::Condition acond, ncond;
1533 switch (condition) {
1534 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1535 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1536 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1537 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1538 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1539 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1540 case lir_cond_belowEqual:
1541 case lir_cond_aboveEqual:
1542 default: ShouldNotReachHere();
1543 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1544 }
1545
1546 assert(result->is_single_cpu() || result->is_double_cpu(),
1547 "expect single register for result");
1548 if (opr1->is_constant() && opr2->is_constant()
1549 && opr1->type() == T_INT && opr2->type() == T_INT) {
1550 jint val1 = opr1->as_jint();
1551 jint val2 = opr2->as_jint();
1552 if (val1 == 0 && val2 == 1) {
1553 __ cset(result->as_register(), ncond);
1554 return;
1555 } else if (val1 == 1 && val2 == 0) {
1556 __ cset(result->as_register(), acond);
1557 return;
1558 }
1559 }
1560
1561 if (opr1->is_constant() && opr2->is_constant()
1562 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1563 jlong val1 = opr1->as_jlong();
1564 jlong val2 = opr2->as_jlong();
1565 if (val1 == 0 && val2 == 1) {
1566 __ cset(result->as_register_lo(), ncond);
1567 return;
1568 } else if (val1 == 1 && val2 == 0) {
1569 __ cset(result->as_register_lo(), acond);
1570 return;
1571 }
1572 }
1573
1574 if (opr1->is_stack()) {
1575 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1576 opr1 = FrameMap::rscratch1_opr;
1577 } else if (opr1->is_constant()) {
1578 LIR_Opr tmp
1579 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1580 const2reg(opr1, tmp, lir_patch_none, nullptr);
1581 opr1 = tmp;
1582 }
1583
1584 if (opr2->is_stack()) {
1585 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1586 opr2 = FrameMap::rscratch2_opr;
1587 } else if (opr2->is_constant()) {
1588 LIR_Opr tmp
1589 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1590 const2reg(opr2, tmp, lir_patch_none, nullptr);
1591 opr2 = tmp;
1592 }
1593
1594 if (result->type() == T_LONG)
1595 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1596 else
1597 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1598 }
1599
1600 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1601 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1602
1603 if (left->is_single_cpu()) {
1604 Register lreg = left->as_register();
1605 Register dreg = as_reg(dest);
1606
1607 if (right->is_single_cpu()) {
1608 // cpu register - cpu register
1609
1610 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1611 "should be");
1612 Register rreg = right->as_register();
1613 switch (code) {
1614 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1615 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1616 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1617 default: ShouldNotReachHere();
1618 }
1619
1620 } else if (right->is_double_cpu()) {
1621 Register rreg = right->as_register_lo();
1622 // single_cpu + double_cpu: can happen with obj+long
1623 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1624 switch (code) {
1625 case lir_add: __ add(dreg, lreg, rreg); break;
1626 case lir_sub: __ sub(dreg, lreg, rreg); break;
1627 default: ShouldNotReachHere();
1628 }
1629 } else if (right->is_constant()) {
1630 // cpu register - constant
1631 jlong c;
1632
1633 // FIXME. This is fugly: we really need to factor all this logic.
1634 switch(right->type()) {
1635 case T_LONG:
1636 c = right->as_constant_ptr()->as_jlong();
1637 break;
1638 case T_INT:
1639 case T_ADDRESS:
1640 c = right->as_constant_ptr()->as_jint();
1641 break;
1642 default:
1643 ShouldNotReachHere();
1644 c = 0; // unreachable
1645 break;
1646 }
1647
1648 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1649 if (c == 0 && dreg == lreg) {
1650 COMMENT("effective nop elided");
1651 return;
1652 }
1653 switch(left->type()) {
1654 case T_INT:
1655 switch (code) {
1656 case lir_add: __ addw(dreg, lreg, c); break;
1657 case lir_sub: __ subw(dreg, lreg, c); break;
1658 default: ShouldNotReachHere();
1659 }
1660 break;
1661 case T_OBJECT:
1662 case T_ADDRESS:
1663 switch (code) {
1664 case lir_add: __ add(dreg, lreg, c); break;
1665 case lir_sub: __ sub(dreg, lreg, c); break;
1666 default: ShouldNotReachHere();
1667 }
1668 break;
1669 default:
1670 ShouldNotReachHere();
1671 }
1672 } else {
1673 ShouldNotReachHere();
1674 }
1675
1676 } else if (left->is_double_cpu()) {
1677 Register lreg_lo = left->as_register_lo();
1678
1679 if (right->is_double_cpu()) {
1680 // cpu register - cpu register
1681 Register rreg_lo = right->as_register_lo();
1682 switch (code) {
1683 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1684 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1685 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1686 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1687 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1688 default:
1689 ShouldNotReachHere();
1690 }
1691
1692 } else if (right->is_constant()) {
1693 jlong c = right->as_constant_ptr()->as_jlong();
1694 Register dreg = as_reg(dest);
1695 switch (code) {
1696 case lir_add:
1697 case lir_sub:
1698 if (c == 0 && dreg == lreg_lo) {
1699 COMMENT("effective nop elided");
1700 return;
1701 }
1702 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1703 break;
1704 case lir_div:
1705 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1706 if (c == 1) {
1707 // move lreg_lo to dreg if divisor is 1
1708 __ mov(dreg, lreg_lo);
1709 } else {
1710 unsigned int shift = log2i_exact(c);
1711 // use rscratch1 as intermediate result register
1712 __ asr(rscratch1, lreg_lo, 63);
1713 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1714 __ asr(dreg, rscratch1, shift);
1715 }
1716 break;
1717 case lir_rem:
1718 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1719 if (c == 1) {
1720 // move 0 to dreg if divisor is 1
1721 __ mov(dreg, zr);
1722 } else {
1723 // use rscratch1 as intermediate result register
1724 __ negs(rscratch1, lreg_lo);
1725 __ andr(dreg, lreg_lo, c - 1);
1726 __ andr(rscratch1, rscratch1, c - 1);
1727 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1728 }
1729 break;
1730 default:
1731 ShouldNotReachHere();
1732 }
1733 } else {
1734 ShouldNotReachHere();
1735 }
1736 } else if (left->is_single_fpu()) {
1737 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1738 switch (code) {
1739 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1740 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1741 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1742 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1743 default:
1744 ShouldNotReachHere();
1745 }
1746 } else if (left->is_double_fpu()) {
1747 if (right->is_double_fpu()) {
1748 // fpu register - fpu register
1749 switch (code) {
1750 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1751 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1752 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1753 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1754 default:
1755 ShouldNotReachHere();
1756 }
1757 } else {
1758 if (right->is_constant()) {
1759 ShouldNotReachHere();
1760 }
1761 ShouldNotReachHere();
1762 }
1763 } else if (left->is_single_stack() || left->is_address()) {
1764 assert(left == dest, "left and dest must be equal");
1765 ShouldNotReachHere();
1766 } else {
1767 ShouldNotReachHere();
1768 }
1769 }
1770
1771 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1772
1773
1774 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1775 switch(code) {
1776 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1777 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1778 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1779 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1780 default : ShouldNotReachHere();
1781 }
1782 }
1783
1784 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1785
1786 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1787 Register Rleft = left->is_single_cpu() ? left->as_register() :
1788 left->as_register_lo();
1789 if (dst->is_single_cpu()) {
1790 Register Rdst = dst->as_register();
1791 if (right->is_constant()) {
1792 switch (code) {
1793 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1794 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1795 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1796 default: ShouldNotReachHere(); break;
1797 }
1798 } else {
1799 Register Rright = right->is_single_cpu() ? right->as_register() :
1800 right->as_register_lo();
1801 switch (code) {
1802 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1803 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1804 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1805 default: ShouldNotReachHere(); break;
1806 }
1807 }
1808 } else {
1809 Register Rdst = dst->as_register_lo();
1810 if (right->is_constant()) {
1811 switch (code) {
1812 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1813 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1814 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1815 default: ShouldNotReachHere(); break;
1816 }
1817 } else {
1818 Register Rright = right->is_single_cpu() ? right->as_register() :
1819 right->as_register_lo();
1820 switch (code) {
1821 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1822 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1823 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1824 default: ShouldNotReachHere(); break;
1825 }
1826 }
1827 }
1828 }
1829
1830
1831
1832 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1833
1834 // opcode check
1835 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1836 bool is_irem = (code == lir_irem);
1837
1838 // operand check
1839 assert(left->is_single_cpu(), "left must be register");
1840 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1841 assert(result->is_single_cpu(), "result must be register");
1842 Register lreg = left->as_register();
1843 Register dreg = result->as_register();
1844
1845 // power-of-2 constant check and codegen
1846 if (right->is_constant()) {
1847 int c = right->as_constant_ptr()->as_jint();
1848 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1849 if (is_irem) {
1850 if (c == 1) {
1851 // move 0 to dreg if divisor is 1
1852 __ movw(dreg, zr);
1853 } else {
1854 // use rscratch1 as intermediate result register
1855 __ negsw(rscratch1, lreg);
1856 __ andw(dreg, lreg, c - 1);
1857 __ andw(rscratch1, rscratch1, c - 1);
1858 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1859 }
1860 } else {
1861 if (c == 1) {
1862 // move lreg to dreg if divisor is 1
1863 __ movw(dreg, lreg);
1864 } else {
1865 unsigned int shift = exact_log2(c);
1866 // use rscratch1 as intermediate result register
1867 __ asrw(rscratch1, lreg, 31);
1868 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1869 __ asrw(dreg, rscratch1, shift);
1870 }
1871 }
1872 } else {
1873 Register rreg = right->as_register();
1874 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1875 }
1876 }
1877
1878
1879 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1880 if (opr1->is_constant() && opr2->is_single_cpu()) {
1881 // tableswitch
1882 Register reg = as_reg(opr2);
1883 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1884 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1885 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1886 Register reg1 = as_reg(opr1);
1887 if (opr2->is_single_cpu()) {
1888 // cpu register - cpu register
1889 Register reg2 = opr2->as_register();
1890 if (is_reference_type(opr1->type())) {
1891 __ cmpoop(reg1, reg2);
1892 } else {
1893 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1894 __ cmpw(reg1, reg2);
1895 }
1896 return;
1897 }
1898 if (opr2->is_double_cpu()) {
1899 // cpu register - cpu register
1900 Register reg2 = opr2->as_register_lo();
1901 __ cmp(reg1, reg2);
1902 return;
1903 }
1904
1905 if (opr2->is_constant()) {
1906 bool is_32bit = false; // width of register operand
1907 jlong imm;
1908
1909 switch(opr2->type()) {
1910 case T_INT:
1911 imm = opr2->as_constant_ptr()->as_jint();
1912 is_32bit = true;
1913 break;
1914 case T_LONG:
1915 imm = opr2->as_constant_ptr()->as_jlong();
1916 break;
1917 case T_ADDRESS:
1918 imm = opr2->as_constant_ptr()->as_jint();
1919 break;
1920 case T_METADATA:
1921 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1922 break;
1923 case T_OBJECT:
1924 case T_ARRAY:
1925 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1926 __ cmpoop(reg1, rscratch1);
1927 return;
1928 default:
1929 ShouldNotReachHere();
1930 imm = 0; // unreachable
1931 break;
1932 }
1933
1934 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1935 if (is_32bit)
1936 __ cmpw(reg1, imm);
1937 else
1938 __ subs(zr, reg1, imm);
1939 return;
1940 } else {
1941 __ mov(rscratch1, imm);
1942 if (is_32bit)
1943 __ cmpw(reg1, rscratch1);
1944 else
1945 __ cmp(reg1, rscratch1);
1946 return;
1947 }
1948 } else
1949 ShouldNotReachHere();
1950 } else if (opr1->is_single_fpu()) {
1951 FloatRegister reg1 = opr1->as_float_reg();
1952 assert(opr2->is_single_fpu(), "expect single float register");
1953 FloatRegister reg2 = opr2->as_float_reg();
1954 __ fcmps(reg1, reg2);
1955 } else if (opr1->is_double_fpu()) {
1956 FloatRegister reg1 = opr1->as_double_reg();
1957 assert(opr2->is_double_fpu(), "expect double float register");
1958 FloatRegister reg2 = opr2->as_double_reg();
1959 __ fcmpd(reg1, reg2);
1960 } else {
1961 ShouldNotReachHere();
1962 }
1963 }
1964
1965 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1966 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1967 bool is_unordered_less = (code == lir_ucmp_fd2i);
1968 if (left->is_single_fpu()) {
1969 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1970 } else if (left->is_double_fpu()) {
1971 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1972 } else {
1973 ShouldNotReachHere();
1974 }
1975 } else if (code == lir_cmp_l2i) {
1976 Label done;
1977 __ cmp(left->as_register_lo(), right->as_register_lo());
1978 __ mov(dst->as_register(), (uint64_t)-1L);
1979 __ br(Assembler::LT, done);
1980 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
1981 __ bind(done);
1982 } else {
1983 ShouldNotReachHere();
1984 }
1985 }
1986
1987
1988 void LIR_Assembler::align_call(LIR_Code code) { }
1989
1990
1991 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
1992 address call = __ trampoline_call(Address(op->addr(), rtype));
1993 if (call == nullptr) {
1994 bailout("trampoline stub overflow");
1995 return;
1996 }
1997 add_call_info(code_offset(), op->info());
1998 __ post_call_nop();
1999 }
2000
2001
2002 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2003 address call = __ ic_call(op->addr());
2004 if (call == nullptr) {
2005 bailout("trampoline stub overflow");
2006 return;
2007 }
2008 add_call_info(code_offset(), op->info());
2009 __ post_call_nop();
2010 }
2011
2012 void LIR_Assembler::emit_static_call_stub() {
2013 address call_pc = __ pc();
2014 address stub = __ start_a_stub(call_stub_size());
2015 if (stub == nullptr) {
2016 bailout("static call stub overflow");
2017 return;
2018 }
2019
2020 int start = __ offset();
2021
2022 __ relocate(static_stub_Relocation::spec(call_pc));
2023 __ emit_static_call_stub();
2024
2025 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2026 <= call_stub_size(), "stub too big");
2027 __ end_a_stub();
2028 }
2029
2030
2031 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2032 assert(exceptionOop->as_register() == r0, "must match");
2033 assert(exceptionPC->as_register() == r3, "must match");
2034
2035 // exception object is not added to oop map by LinearScan
2036 // (LinearScan assumes that no oops are in fixed registers)
2037 info->add_register_oop(exceptionOop);
2038 C1StubId unwind_id;
2039
2040 // get current pc information
2041 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2042 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2043 // As no instructions have been generated yet for this LIR node it's
2044 // possible that an oop map already exists for the current offset.
2045 // In that case insert an dummy NOP here to ensure all oop map PCs
2046 // are unique. See JDK-8237483.
2047 __ nop();
2048 }
2049 int pc_for_athrow_offset = __ offset();
2050 InternalAddress pc_for_athrow(__ pc());
2051 __ adr(exceptionPC->as_register(), pc_for_athrow);
2052 add_call_info(pc_for_athrow_offset, info); // for exception handler
2053
2054 __ verify_not_null_oop(r0);
2055 // search an exception handler (r0: exception oop, r3: throwing pc)
2056 if (compilation()->has_fpu_code()) {
2057 unwind_id = C1StubId::handle_exception_id;
2058 } else {
2059 unwind_id = C1StubId::handle_exception_nofpu_id;
2060 }
2061 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2062
2063 // FIXME: enough room for two byte trap ????
2064 __ nop();
2065 }
2066
2067
2068 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2069 assert(exceptionOop->as_register() == r0, "must match");
2070
2071 __ b(_unwind_handler_entry);
2072 }
2073
2074
2075 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2076 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2077 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2078
2079 switch (left->type()) {
2080 case T_INT: {
2081 switch (code) {
2082 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2083 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2084 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2085 default:
2086 ShouldNotReachHere();
2087 break;
2088 }
2089 break;
2090 case T_LONG:
2091 case T_ADDRESS:
2092 case T_OBJECT:
2093 switch (code) {
2094 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2095 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2096 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2097 default:
2098 ShouldNotReachHere();
2099 break;
2100 }
2101 break;
2102 default:
2103 ShouldNotReachHere();
2104 break;
2105 }
2106 }
2107 }
2108
2109
2110 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2111 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2112 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2113
2114 switch (left->type()) {
2115 case T_INT: {
2116 switch (code) {
2117 case lir_shl: __ lslw (dreg, lreg, count); break;
2118 case lir_shr: __ asrw (dreg, lreg, count); break;
2119 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2120 default:
2121 ShouldNotReachHere();
2122 break;
2123 }
2124 break;
2125 case T_LONG:
2126 case T_ADDRESS:
2127 case T_OBJECT:
2128 switch (code) {
2129 case lir_shl: __ lsl (dreg, lreg, count); break;
2130 case lir_shr: __ asr (dreg, lreg, count); break;
2131 case lir_ushr: __ lsr (dreg, lreg, count); break;
2132 default:
2133 ShouldNotReachHere();
2134 break;
2135 }
2136 break;
2137 default:
2138 ShouldNotReachHere();
2139 break;
2140 }
2141 }
2142 }
2143
2144
2145 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2146 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2147 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2148 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2149 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2150 }
2151
2152
2153 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2154 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2155 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2156 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2157 __ mov (rscratch1, c);
2158 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2159 }
2160
2161
2162 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2163 ShouldNotReachHere();
2164 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2165 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2166 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2167 __ lea(rscratch1, __ constant_oop_address(o));
2168 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2169 }
2170
2171
2172 // This code replaces a call to arraycopy; no exception may
2173 // be thrown in this code, they must be thrown in the System.arraycopy
2174 // activation frame; we could save some checks if this would not be the case
2175 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2176 ciArrayKlass* default_type = op->expected_type();
2177 Register src = op->src()->as_register();
2178 Register dst = op->dst()->as_register();
2179 Register src_pos = op->src_pos()->as_register();
2180 Register dst_pos = op->dst_pos()->as_register();
2181 Register length = op->length()->as_register();
2182 Register tmp = op->tmp()->as_register();
2183
2184 CodeStub* stub = op->stub();
2185 int flags = op->flags();
2186 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2187 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2188
2189 // if we don't know anything, just go through the generic arraycopy
2190 if (default_type == nullptr // || basic_type == T_OBJECT
2191 ) {
2192 Label done;
2193 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2194
2195 // Save the arguments in case the generic arraycopy fails and we
2196 // have to fall back to the JNI stub
2197 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2198 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2199 __ str(src, Address(sp, 4*BytesPerWord));
2200
2201 address copyfunc_addr = StubRoutines::generic_arraycopy();
2202 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2203
2204 // The arguments are in java calling convention so we shift them
2205 // to C convention
2206 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2207 __ mov(c_rarg0, j_rarg0);
2208 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2209 __ mov(c_rarg1, j_rarg1);
2210 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2211 __ mov(c_rarg2, j_rarg2);
2212 assert_different_registers(c_rarg3, j_rarg4);
2213 __ mov(c_rarg3, j_rarg3);
2214 __ mov(c_rarg4, j_rarg4);
2215 #ifndef PRODUCT
2216 if (PrintC1Statistics) {
2217 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2218 }
2219 #endif
2220 __ far_call(RuntimeAddress(copyfunc_addr));
2221
2222 __ cbz(r0, *stub->continuation());
2223
2224 // Reload values from the stack so they are where the stub
2225 // expects them.
2226 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2227 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2228 __ ldr(src, Address(sp, 4*BytesPerWord));
2229
2230 // r0 is -1^K where K == partial copied count
2231 __ eonw(rscratch1, r0, zr);
2232 // adjust length down and src/end pos up by partial copied count
2233 __ subw(length, length, rscratch1);
2234 __ addw(src_pos, src_pos, rscratch1);
2235 __ addw(dst_pos, dst_pos, rscratch1);
2236 __ b(*stub->entry());
2237
2238 __ bind(*stub->continuation());
2239 return;
2240 }
2241
2242 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2243
2244 int elem_size = type2aelembytes(basic_type);
2245 int scale = exact_log2(elem_size);
2246
2247 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2248 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2249 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2250 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2251
2252 // test for null
2253 if (flags & LIR_OpArrayCopy::src_null_check) {
2254 __ cbz(src, *stub->entry());
2255 }
2256 if (flags & LIR_OpArrayCopy::dst_null_check) {
2257 __ cbz(dst, *stub->entry());
2258 }
2259
2260 // If the compiler was not able to prove that exact type of the source or the destination
2261 // of the arraycopy is an array type, check at runtime if the source or the destination is
2262 // an instance type.
2263 if (flags & LIR_OpArrayCopy::type_check) {
2264 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2265 __ load_klass(tmp, dst);
2266 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2267 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2268 __ br(Assembler::GE, *stub->entry());
2269 }
2270
2271 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2272 __ load_klass(tmp, src);
2273 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2274 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2275 __ br(Assembler::GE, *stub->entry());
2276 }
2277 }
2278
2279 // check if negative
2280 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2281 __ cmpw(src_pos, 0);
2282 __ br(Assembler::LT, *stub->entry());
2283 }
2284 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2285 __ cmpw(dst_pos, 0);
2286 __ br(Assembler::LT, *stub->entry());
2287 }
2288
2289 if (flags & LIR_OpArrayCopy::length_positive_check) {
2290 __ cmpw(length, 0);
2291 __ br(Assembler::LT, *stub->entry());
2292 }
2293
2294 if (flags & LIR_OpArrayCopy::src_range_check) {
2295 __ addw(tmp, src_pos, length);
2296 __ ldrw(rscratch1, src_length_addr);
2297 __ cmpw(tmp, rscratch1);
2298 __ br(Assembler::HI, *stub->entry());
2299 }
2300 if (flags & LIR_OpArrayCopy::dst_range_check) {
2301 __ addw(tmp, dst_pos, length);
2302 __ ldrw(rscratch1, dst_length_addr);
2303 __ cmpw(tmp, rscratch1);
2304 __ br(Assembler::HI, *stub->entry());
2305 }
2306
2307 if (flags & LIR_OpArrayCopy::type_check) {
2308 // We don't know the array types are compatible
2309 if (basic_type != T_OBJECT) {
2310 // Simple test for basic type arrays
2311 if (UseCompressedClassPointers) {
2312 __ ldrw(tmp, src_klass_addr);
2313 __ ldrw(rscratch1, dst_klass_addr);
2314 __ cmpw(tmp, rscratch1);
2315 } else {
2316 __ ldr(tmp, src_klass_addr);
2317 __ ldr(rscratch1, dst_klass_addr);
2318 __ cmp(tmp, rscratch1);
2319 }
2320 __ br(Assembler::NE, *stub->entry());
2321 } else {
2322 // For object arrays, if src is a sub class of dst then we can
2323 // safely do the copy.
2324 Label cont, slow;
2325
2326 #define PUSH(r1, r2) \
2327 stp(r1, r2, __ pre(sp, -2 * wordSize));
2328
2329 #define POP(r1, r2) \
2330 ldp(r1, r2, __ post(sp, 2 * wordSize));
2331
2332 __ PUSH(src, dst);
2333
2334 __ load_klass(src, src);
2335 __ load_klass(dst, dst);
2336
2337 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2338
2339 __ PUSH(src, dst);
2340 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
2341 __ POP(src, dst);
2342
2343 __ cbnz(src, cont);
2344
2345 __ bind(slow);
2346 __ POP(src, dst);
2347
2348 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2349 if (copyfunc_addr != nullptr) { // use stub if available
2350 // src is not a sub class of dst so we have to do a
2351 // per-element check.
2352
2353 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2354 if ((flags & mask) != mask) {
2355 // Check that at least both of them object arrays.
2356 assert(flags & mask, "one of the two should be known to be an object array");
2357
2358 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2359 __ load_klass(tmp, src);
2360 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2361 __ load_klass(tmp, dst);
2362 }
2363 int lh_offset = in_bytes(Klass::layout_helper_offset());
2364 Address klass_lh_addr(tmp, lh_offset);
2365 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2366 __ ldrw(rscratch1, klass_lh_addr);
2367 __ mov(rscratch2, objArray_lh);
2368 __ eorw(rscratch1, rscratch1, rscratch2);
2369 __ cbnzw(rscratch1, *stub->entry());
2370 }
2371
2372 // Spill because stubs can use any register they like and it's
2373 // easier to restore just those that we care about.
2374 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2375 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2376 __ str(src, Address(sp, 4*BytesPerWord));
2377
2378 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2379 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2380 assert_different_registers(c_rarg0, dst, dst_pos, length);
2381 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2382 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2383 assert_different_registers(c_rarg1, dst, length);
2384 __ uxtw(c_rarg2, length);
2385 assert_different_registers(c_rarg2, dst);
2386
2387 __ load_klass(c_rarg4, dst);
2388 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2389 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2390 __ far_call(RuntimeAddress(copyfunc_addr));
2391
2392 #ifndef PRODUCT
2393 if (PrintC1Statistics) {
2394 Label failed;
2395 __ cbnz(r0, failed);
2396 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2397 __ bind(failed);
2398 }
2399 #endif
2400
2401 __ cbz(r0, *stub->continuation());
2402
2403 #ifndef PRODUCT
2404 if (PrintC1Statistics) {
2405 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2406 }
2407 #endif
2408 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2409
2410 // Restore previously spilled arguments
2411 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2412 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2413 __ ldr(src, Address(sp, 4*BytesPerWord));
2414
2415 // return value is -1^K where K is partial copied count
2416 __ eonw(rscratch1, r0, zr);
2417 // adjust length down and src/end pos up by partial copied count
2418 __ subw(length, length, rscratch1);
2419 __ addw(src_pos, src_pos, rscratch1);
2420 __ addw(dst_pos, dst_pos, rscratch1);
2421 }
2422
2423 __ b(*stub->entry());
2424
2425 __ bind(cont);
2426 __ POP(src, dst);
2427 }
2428 }
2429
2430 #ifdef ASSERT
2431 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2432 // Sanity check the known type with the incoming class. For the
2433 // primitive case the types must match exactly with src.klass and
2434 // dst.klass each exactly matching the default type. For the
2435 // object array case, if no type check is needed then either the
2436 // dst type is exactly the expected type and the src type is a
2437 // subtype which we can't check or src is the same array as dst
2438 // but not necessarily exactly of type default_type.
2439 Label known_ok, halt;
2440 __ mov_metadata(tmp, default_type->constant_encoding());
2441 if (UseCompressedClassPointers) {
2442 __ encode_klass_not_null(tmp);
2443 }
2444
2445 if (basic_type != T_OBJECT) {
2446
2447 if (UseCompressedClassPointers) {
2448 __ ldrw(rscratch1, dst_klass_addr);
2449 __ cmpw(tmp, rscratch1);
2450 } else {
2451 __ ldr(rscratch1, dst_klass_addr);
2452 __ cmp(tmp, rscratch1);
2453 }
2454 __ br(Assembler::NE, halt);
2455 if (UseCompressedClassPointers) {
2456 __ ldrw(rscratch1, src_klass_addr);
2457 __ cmpw(tmp, rscratch1);
2458 } else {
2459 __ ldr(rscratch1, src_klass_addr);
2460 __ cmp(tmp, rscratch1);
2461 }
2462 __ br(Assembler::EQ, known_ok);
2463 } else {
2464 if (UseCompressedClassPointers) {
2465 __ ldrw(rscratch1, dst_klass_addr);
2466 __ cmpw(tmp, rscratch1);
2467 } else {
2468 __ ldr(rscratch1, dst_klass_addr);
2469 __ cmp(tmp, rscratch1);
2470 }
2471 __ br(Assembler::EQ, known_ok);
2472 __ cmp(src, dst);
2473 __ br(Assembler::EQ, known_ok);
2474 }
2475 __ bind(halt);
2476 __ stop("incorrect type information in arraycopy");
2477 __ bind(known_ok);
2478 }
2479 #endif
2480
2481 #ifndef PRODUCT
2482 if (PrintC1Statistics) {
2483 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2484 }
2485 #endif
2486
2487 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2488 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2489 assert_different_registers(c_rarg0, dst, dst_pos, length);
2490 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2491 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2492 assert_different_registers(c_rarg1, dst, length);
2493 __ uxtw(c_rarg2, length);
2494 assert_different_registers(c_rarg2, dst);
2495
2496 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2497 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2498 const char *name;
2499 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2500
2501 CodeBlob *cb = CodeCache::find_blob(entry);
2502 if (cb) {
2503 __ far_call(RuntimeAddress(entry));
2504 } else {
2505 __ call_VM_leaf(entry, 3);
2506 }
2507
2508 if (stub != nullptr) {
2509 __ bind(*stub->continuation());
2510 }
2511 }
2512
2513
2514
2515
2516 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2517 Register obj = op->obj_opr()->as_register(); // may not be an oop
2518 Register hdr = op->hdr_opr()->as_register();
2519 Register lock = op->lock_opr()->as_register();
2520 Register temp = op->scratch_opr()->as_register();
2521 if (LockingMode == LM_MONITOR) {
2522 if (op->info() != nullptr) {
2523 add_debug_info_for_null_check_here(op->info());
2524 __ null_check(obj, -1);
2525 }
2526 __ b(*op->stub()->entry());
2527 } else if (op->code() == lir_lock) {
2528 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2529 // add debug info for NullPointerException only if one is possible
2530 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2531 if (op->info() != nullptr) {
2532 add_debug_info_for_null_check(null_check_offset, op->info());
2533 }
2534 // done
2535 } else if (op->code() == lir_unlock) {
2536 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2537 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2538 } else {
2539 Unimplemented();
2540 }
2541 __ bind(*op->stub()->continuation());
2542 }
2543
2544 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2545 Register obj = op->obj()->as_pointer_register();
2546 Register result = op->result_opr()->as_pointer_register();
2547
2548 CodeEmitInfo* info = op->info();
2549 if (info != nullptr) {
2550 add_debug_info_for_null_check_here(info);
2551 }
2552
2553 if (UseCompressedClassPointers) {
2554 __ ldrw(result, Address (obj, oopDesc::klass_offset_in_bytes()));
2555 __ decode_klass_not_null(result);
2556 } else {
2557 __ ldr(result, Address (obj, oopDesc::klass_offset_in_bytes()));
2558 }
2559 }
2560
2561 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2562 ciMethod* method = op->profiled_method();
2563 int bci = op->profiled_bci();
2564 ciMethod* callee = op->profiled_callee();
2565
2566 // Update counter for all call types
2567 ciMethodData* md = method->method_data_or_null();
2568 assert(md != nullptr, "Sanity");
2569 ciProfileData* data = md->bci_to_data(bci);
2570 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2571 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2572 Register mdo = op->mdo()->as_register();
2573 __ mov_metadata(mdo, md->constant_encoding());
2574 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2575 // Perform additional virtual call profiling for invokevirtual and
2576 // invokeinterface bytecodes
2577 if (op->should_profile_receiver_type()) {
2578 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2579 Register recv = op->recv()->as_register();
2580 assert_different_registers(mdo, recv);
2581 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2582 ciKlass* known_klass = op->known_holder();
2583 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2584 // We know the type that will be seen at this call site; we can
2585 // statically update the MethodData* rather than needing to do
2586 // dynamic tests on the receiver type
2587
2588 // NOTE: we should probably put a lock around this search to
2589 // avoid collisions by concurrent compilations
2590 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2591 uint i;
2592 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2593 ciKlass* receiver = vc_data->receiver(i);
2594 if (known_klass->equals(receiver)) {
2595 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2596 __ addptr(data_addr, DataLayout::counter_increment);
2597 return;
2598 }
2599 }
2600
2601 // Receiver type not found in profile data; select an empty slot
2602
2603 // Note that this is less efficient than it should be because it
2604 // always does a write to the receiver part of the
2605 // VirtualCallData rather than just the first time
2606 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2607 ciKlass* receiver = vc_data->receiver(i);
2608 if (receiver == nullptr) {
2609 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2610 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2611 __ lea(rscratch2, recv_addr);
2612 __ str(rscratch1, Address(rscratch2));
2613 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2614 __ addptr(data_addr, DataLayout::counter_increment);
2615 return;
2616 }
2617 }
2618 } else {
2619 __ load_klass(recv, recv);
2620 Label update_done;
2621 type_profile_helper(mdo, md, data, recv, &update_done);
2622 // Receiver did not match any saved receiver and there is no empty row for it.
2623 // Increment total counter to indicate polymorphic case.
2624 __ addptr(counter_addr, DataLayout::counter_increment);
2625
2626 __ bind(update_done);
2627 }
2628 } else {
2629 // Static call
2630 __ addptr(counter_addr, DataLayout::counter_increment);
2631 }
2632 }
2633
2634
2635 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2636 Unimplemented();
2637 }
2638
2639
2640 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2641 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2642 }
2643
2644 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2645 assert(op->crc()->is_single_cpu(), "crc must be register");
2646 assert(op->val()->is_single_cpu(), "byte value must be register");
2647 assert(op->result_opr()->is_single_cpu(), "result must be register");
2648 Register crc = op->crc()->as_register();
2649 Register val = op->val()->as_register();
2650 Register res = op->result_opr()->as_register();
2651
2652 assert_different_registers(val, crc, res);
2653 uint64_t offset;
2654 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2655 __ add(res, res, offset);
2656
2657 __ mvnw(crc, crc); // ~crc
2658 __ update_byte_crc32(crc, val, res);
2659 __ mvnw(res, crc); // ~crc
2660 }
2661
2662 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2663 COMMENT("emit_profile_type {");
2664 Register obj = op->obj()->as_register();
2665 Register tmp = op->tmp()->as_pointer_register();
2666 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2667 ciKlass* exact_klass = op->exact_klass();
2668 intptr_t current_klass = op->current_klass();
2669 bool not_null = op->not_null();
2670 bool no_conflict = op->no_conflict();
2671
2672 Label update, next, none;
2673
2674 bool do_null = !not_null;
2675 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2676 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2677
2678 assert(do_null || do_update, "why are we here?");
2679 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2680 assert(mdo_addr.base() != rscratch1, "wrong register");
2681
2682 __ verify_oop(obj);
2683
2684 if (tmp != obj) {
2685 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2686 __ mov(tmp, obj);
2687 } else {
2688 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2689 }
2690 if (do_null) {
2691 __ cbnz(tmp, update);
2692 if (!TypeEntries::was_null_seen(current_klass)) {
2693 __ ldr(rscratch2, mdo_addr);
2694 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2695 __ str(rscratch2, mdo_addr);
2696 }
2697 if (do_update) {
2698 #ifndef ASSERT
2699 __ b(next);
2700 }
2701 #else
2702 __ b(next);
2703 }
2704 } else {
2705 __ cbnz(tmp, update);
2706 __ stop("unexpected null obj");
2707 #endif
2708 }
2709
2710 __ bind(update);
2711
2712 if (do_update) {
2713 #ifdef ASSERT
2714 if (exact_klass != nullptr) {
2715 Label ok;
2716 __ load_klass(tmp, tmp);
2717 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2718 __ eor(rscratch1, tmp, rscratch1);
2719 __ cbz(rscratch1, ok);
2720 __ stop("exact klass and actual klass differ");
2721 __ bind(ok);
2722 }
2723 #endif
2724 if (!no_conflict) {
2725 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2726 if (exact_klass != nullptr) {
2727 __ mov_metadata(tmp, exact_klass->constant_encoding());
2728 } else {
2729 __ load_klass(tmp, tmp);
2730 }
2731
2732 __ ldr(rscratch2, mdo_addr);
2733 __ eor(tmp, tmp, rscratch2);
2734 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2735 // klass seen before, nothing to do. The unknown bit may have been
2736 // set already but no need to check.
2737 __ cbz(rscratch1, next);
2738
2739 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2740
2741 if (TypeEntries::is_type_none(current_klass)) {
2742 __ cbz(rscratch2, none);
2743 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2744 __ br(Assembler::EQ, none);
2745 // There is a chance that the checks above
2746 // fail if another thread has just set the
2747 // profiling to this obj's klass
2748 __ dmb(Assembler::ISHLD);
2749 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2750 __ ldr(rscratch2, mdo_addr);
2751 __ eor(tmp, tmp, rscratch2);
2752 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2753 __ cbz(rscratch1, next);
2754 }
2755 } else {
2756 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2757 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2758
2759 __ ldr(tmp, mdo_addr);
2760 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2761 }
2762
2763 // different than before. Cannot keep accurate profile.
2764 __ ldr(rscratch2, mdo_addr);
2765 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2766 __ str(rscratch2, mdo_addr);
2767
2768 if (TypeEntries::is_type_none(current_klass)) {
2769 __ b(next);
2770
2771 __ bind(none);
2772 // first time here. Set profile type.
2773 __ str(tmp, mdo_addr);
2774 #ifdef ASSERT
2775 __ andr(tmp, tmp, TypeEntries::type_mask);
2776 __ verify_klass_ptr(tmp);
2777 #endif
2778 }
2779 } else {
2780 // There's a single possible klass at this profile point
2781 assert(exact_klass != nullptr, "should be");
2782 if (TypeEntries::is_type_none(current_klass)) {
2783 __ mov_metadata(tmp, exact_klass->constant_encoding());
2784 __ ldr(rscratch2, mdo_addr);
2785 __ eor(tmp, tmp, rscratch2);
2786 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2787 __ cbz(rscratch1, next);
2788 #ifdef ASSERT
2789 {
2790 Label ok;
2791 __ ldr(rscratch1, mdo_addr);
2792 __ cbz(rscratch1, ok);
2793 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2794 __ br(Assembler::EQ, ok);
2795 // may have been set by another thread
2796 __ dmb(Assembler::ISHLD);
2797 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2798 __ ldr(rscratch2, mdo_addr);
2799 __ eor(rscratch2, rscratch1, rscratch2);
2800 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2801 __ cbz(rscratch2, ok);
2802
2803 __ stop("unexpected profiling mismatch");
2804 __ bind(ok);
2805 }
2806 #endif
2807 // first time here. Set profile type.
2808 __ str(tmp, mdo_addr);
2809 #ifdef ASSERT
2810 __ andr(tmp, tmp, TypeEntries::type_mask);
2811 __ verify_klass_ptr(tmp);
2812 #endif
2813 } else {
2814 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2815 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2816
2817 __ ldr(tmp, mdo_addr);
2818 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2819
2820 __ orr(tmp, tmp, TypeEntries::type_unknown);
2821 __ str(tmp, mdo_addr);
2822 // FIXME: Write barrier needed here?
2823 }
2824 }
2825
2826 __ bind(next);
2827 }
2828 COMMENT("} emit_profile_type");
2829 }
2830
2831
2832 void LIR_Assembler::align_backward_branch_target() {
2833 }
2834
2835
2836 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2837 // tmp must be unused
2838 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2839
2840 if (left->is_single_cpu()) {
2841 assert(dest->is_single_cpu(), "expect single result reg");
2842 __ negw(dest->as_register(), left->as_register());
2843 } else if (left->is_double_cpu()) {
2844 assert(dest->is_double_cpu(), "expect double result reg");
2845 __ neg(dest->as_register_lo(), left->as_register_lo());
2846 } else if (left->is_single_fpu()) {
2847 assert(dest->is_single_fpu(), "expect single float result reg");
2848 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2849 } else {
2850 assert(left->is_double_fpu(), "expect double float operand reg");
2851 assert(dest->is_double_fpu(), "expect double float result reg");
2852 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2853 }
2854 }
2855
2856
2857 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2858 if (patch_code != lir_patch_none) {
2859 deoptimize_trap(info);
2860 return;
2861 }
2862
2863 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2864 }
2865
2866
2867 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2868 assert(!tmp->is_valid(), "don't need temporary");
2869
2870 CodeBlob *cb = CodeCache::find_blob(dest);
2871 if (cb) {
2872 __ far_call(RuntimeAddress(dest));
2873 } else {
2874 __ mov(rscratch1, RuntimeAddress(dest));
2875 __ blr(rscratch1);
2876 }
2877
2878 if (info != nullptr) {
2879 add_call_info_here(info);
2880 }
2881 __ post_call_nop();
2882 }
2883
2884 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2885 if (dest->is_address() || src->is_address()) {
2886 move_op(src, dest, type, lir_patch_none, info,
2887 /*pop_fpu_stack*/false, /*wide*/false);
2888 } else {
2889 ShouldNotReachHere();
2890 }
2891 }
2892
2893 #ifdef ASSERT
2894 // emit run-time assertion
2895 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2896 assert(op->code() == lir_assert, "must be");
2897
2898 if (op->in_opr1()->is_valid()) {
2899 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2900 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2901 } else {
2902 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2903 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2904 }
2905
2906 Label ok;
2907 if (op->condition() != lir_cond_always) {
2908 Assembler::Condition acond = Assembler::AL;
2909 switch (op->condition()) {
2910 case lir_cond_equal: acond = Assembler::EQ; break;
2911 case lir_cond_notEqual: acond = Assembler::NE; break;
2912 case lir_cond_less: acond = Assembler::LT; break;
2913 case lir_cond_lessEqual: acond = Assembler::LE; break;
2914 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2915 case lir_cond_greater: acond = Assembler::GT; break;
2916 case lir_cond_belowEqual: acond = Assembler::LS; break;
2917 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2918 default: ShouldNotReachHere();
2919 }
2920 __ br(acond, ok);
2921 }
2922 if (op->halt()) {
2923 const char* str = __ code_string(op->msg());
2924 __ stop(str);
2925 } else {
2926 breakpoint();
2927 }
2928 __ bind(ok);
2929 }
2930 #endif
2931
2932 #ifndef PRODUCT
2933 #define COMMENT(x) do { __ block_comment(x); } while (0)
2934 #else
2935 #define COMMENT(x)
2936 #endif
2937
2938 void LIR_Assembler::membar() {
2939 COMMENT("membar");
2940 __ membar(MacroAssembler::AnyAny);
2941 }
2942
2943 void LIR_Assembler::membar_acquire() {
2944 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2945 }
2946
2947 void LIR_Assembler::membar_release() {
2948 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2949 }
2950
2951 void LIR_Assembler::membar_loadload() {
2952 __ membar(Assembler::LoadLoad);
2953 }
2954
2955 void LIR_Assembler::membar_storestore() {
2956 __ membar(MacroAssembler::StoreStore);
2957 }
2958
2959 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2960
2961 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2962
2963 void LIR_Assembler::on_spin_wait() {
2964 __ spin_wait();
2965 }
2966
2967 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2968 __ mov(result_reg->as_register(), rthread);
2969 }
2970
2971
2972 void LIR_Assembler::peephole(LIR_List *lir) {
2973 #if 0
2974 if (tableswitch_count >= max_tableswitches)
2975 return;
2976
2977 /*
2978 This finite-state automaton recognizes sequences of compare-and-
2979 branch instructions. We will turn them into a tableswitch. You
2980 could argue that C1 really shouldn't be doing this sort of
2981 optimization, but without it the code is really horrible.
2982 */
2983
2984 enum { start_s, cmp1_s, beq_s, cmp_s } state;
2985 int first_key, last_key = -2147483648;
2986 int next_key = 0;
2987 int start_insn = -1;
2988 int last_insn = -1;
2989 Register reg = noreg;
2990 LIR_Opr reg_opr;
2991 state = start_s;
2992
2993 LIR_OpList* inst = lir->instructions_list();
2994 for (int i = 0; i < inst->length(); i++) {
2995 LIR_Op* op = inst->at(i);
2996 switch (state) {
2997 case start_s:
2998 first_key = -1;
2999 start_insn = i;
3000 switch (op->code()) {
3001 case lir_cmp:
3002 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3003 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3004 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3005 && opr2->is_constant()
3006 && opr2->type() == T_INT) {
3007 reg_opr = opr1;
3008 reg = opr1->as_register();
3009 first_key = opr2->as_constant_ptr()->as_jint();
3010 next_key = first_key + 1;
3011 state = cmp_s;
3012 goto next_state;
3013 }
3014 break;
3015 }
3016 break;
3017 case cmp_s:
3018 switch (op->code()) {
3019 case lir_branch:
3020 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3021 state = beq_s;
3022 last_insn = i;
3023 goto next_state;
3024 }
3025 }
3026 state = start_s;
3027 break;
3028 case beq_s:
3029 switch (op->code()) {
3030 case lir_cmp: {
3031 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3032 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3033 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3034 && opr1->as_register() == reg
3035 && opr2->is_constant()
3036 && opr2->type() == T_INT
3037 && opr2->as_constant_ptr()->as_jint() == next_key) {
3038 last_key = next_key;
3039 next_key++;
3040 state = cmp_s;
3041 goto next_state;
3042 }
3043 }
3044 }
3045 last_key = next_key;
3046 state = start_s;
3047 break;
3048 default:
3049 assert(false, "impossible state");
3050 }
3051 if (state == start_s) {
3052 if (first_key < last_key - 5L && reg != noreg) {
3053 {
3054 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3055 // reg->encoding(),
3056 // start_insn, first_key, last_key);
3057 // for (int i = 0; i < inst->length(); i++) {
3058 // inst->at(i)->print();
3059 // tty->print("\n");
3060 // }
3061 // tty->print("\n");
3062 }
3063
3064 struct tableswitch *sw = &switches[tableswitch_count];
3065 sw->_insn_index = start_insn, sw->_first_key = first_key,
3066 sw->_last_key = last_key, sw->_reg = reg;
3067 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3068 {
3069 // Insert the new table of branches
3070 int offset = last_insn;
3071 for (int n = first_key; n < last_key; n++) {
3072 inst->insert_before
3073 (last_insn + 1,
3074 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3075 inst->at(offset)->as_OpBranch()->label()));
3076 offset -= 2, i++;
3077 }
3078 }
3079 // Delete all the old compare-and-branch instructions
3080 for (int n = first_key; n < last_key; n++) {
3081 inst->remove_at(start_insn);
3082 inst->remove_at(start_insn);
3083 }
3084 // Insert the tableswitch instruction
3085 inst->insert_before(start_insn,
3086 new LIR_Op2(lir_cmp, lir_cond_always,
3087 LIR_OprFact::intConst(tableswitch_count),
3088 reg_opr));
3089 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3090 tableswitch_count++;
3091 }
3092 reg = noreg;
3093 last_key = -2147483648;
3094 }
3095 next_state:
3096 ;
3097 }
3098 #endif
3099 }
3100
3101 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3102 Address addr = as_Address(src->as_address_ptr());
3103 BasicType type = src->type();
3104 bool is_oop = is_reference_type(type);
3105
3106 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3107 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3108
3109 switch(type) {
3110 case T_INT:
3111 xchg = &MacroAssembler::atomic_xchgalw;
3112 add = &MacroAssembler::atomic_addalw;
3113 break;
3114 case T_LONG:
3115 xchg = &MacroAssembler::atomic_xchgal;
3116 add = &MacroAssembler::atomic_addal;
3117 break;
3118 case T_OBJECT:
3119 case T_ARRAY:
3120 if (UseCompressedOops) {
3121 xchg = &MacroAssembler::atomic_xchgalw;
3122 add = &MacroAssembler::atomic_addalw;
3123 } else {
3124 xchg = &MacroAssembler::atomic_xchgal;
3125 add = &MacroAssembler::atomic_addal;
3126 }
3127 break;
3128 default:
3129 ShouldNotReachHere();
3130 xchg = &MacroAssembler::atomic_xchgal;
3131 add = &MacroAssembler::atomic_addal; // unreachable
3132 }
3133
3134 switch (code) {
3135 case lir_xadd:
3136 {
3137 RegisterOrConstant inc;
3138 Register tmp = as_reg(tmp_op);
3139 Register dst = as_reg(dest);
3140 if (data->is_constant()) {
3141 inc = RegisterOrConstant(as_long(data));
3142 assert_different_registers(dst, addr.base(), tmp,
3143 rscratch1, rscratch2);
3144 } else {
3145 inc = RegisterOrConstant(as_reg(data));
3146 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3147 rscratch1, rscratch2);
3148 }
3149 __ lea(tmp, addr);
3150 (_masm->*add)(dst, inc, tmp);
3151 break;
3152 }
3153 case lir_xchg:
3154 {
3155 Register tmp = tmp_op->as_register();
3156 Register obj = as_reg(data);
3157 Register dst = as_reg(dest);
3158 if (is_oop && UseCompressedOops) {
3159 __ encode_heap_oop(rscratch2, obj);
3160 obj = rscratch2;
3161 }
3162 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3163 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3164 __ lea(tmp, addr);
3165 (_masm->*xchg)(dst, obj, tmp);
3166 if (is_oop && UseCompressedOops) {
3167 __ decode_heap_oop(dst);
3168 }
3169 }
3170 break;
3171 default:
3172 ShouldNotReachHere();
3173 }
3174 __ membar(__ AnyAny);
3175 }
3176
3177 #undef __