1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "asm/assembler.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "ci/ciUtilities.hpp"
37 #include "code/SCCache.hpp"
38 #include "code/compiledIC.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/gc_globals.hpp"
41 #include "nativeInst_aarch64.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/sharedRuntime.hpp"
45 #include "runtime/stubRoutines.hpp"
46 #include "utilities/powerOfTwo.hpp"
47 #include "vmreg_aarch64.inline.hpp"
48
49
50 #ifndef PRODUCT
51 #define COMMENT(x) do { __ block_comment(x); } while (0)
52 #else
53 #define COMMENT(x)
54 #endif
55
56 NEEDS_CLEANUP // remove this definitions ?
57 const Register SYNC_header = r0; // synchronization header
58 const Register SHIFT_count = r0; // where count for shift operations must be
59
60 #define __ _masm->
61
62
63 static void select_different_registers(Register preserve,
64 Register extra,
65 Register &tmp1,
66 Register &tmp2) {
67 if (tmp1 == preserve) {
68 assert_different_registers(tmp1, tmp2, extra);
69 tmp1 = extra;
70 } else if (tmp2 == preserve) {
71 assert_different_registers(tmp1, tmp2, extra);
72 tmp2 = extra;
73 }
74 assert_different_registers(preserve, tmp1, tmp2);
75 }
76
77
78
79 static void select_different_registers(Register preserve,
80 Register extra,
81 Register &tmp1,
82 Register &tmp2,
83 Register &tmp3) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, tmp3, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, tmp3, extra);
89 tmp2 = extra;
90 } else if (tmp3 == preserve) {
91 assert_different_registers(tmp1, tmp2, tmp3, extra);
92 tmp3 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2, tmp3);
95 }
96
97
98 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
99
100
101 LIR_Opr LIR_Assembler::receiverOpr() {
102 return FrameMap::receiver_opr;
103 }
104
105 LIR_Opr LIR_Assembler::osrBufferPointer() {
106 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
107 }
108
109 //--------------fpu register translations-----------------------
110
111
112 address LIR_Assembler::float_constant(float f) {
113 address const_addr = __ float_constant(f);
114 if (const_addr == nullptr) {
115 bailout("const section overflow");
116 return __ code()->consts()->start();
117 } else {
118 return const_addr;
119 }
120 }
121
122
123 address LIR_Assembler::double_constant(double d) {
124 address const_addr = __ double_constant(d);
125 if (const_addr == nullptr) {
126 bailout("const section overflow");
127 return __ code()->consts()->start();
128 } else {
129 return const_addr;
130 }
131 }
132
133 address LIR_Assembler::int_constant(jlong n) {
134 address const_addr = __ long_constant(n);
135 if (const_addr == nullptr) {
136 bailout("const section overflow");
137 return __ code()->consts()->start();
138 } else {
139 return const_addr;
140 }
141 }
142
143 void LIR_Assembler::breakpoint() { Unimplemented(); }
144
145 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
146
147 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
148
149 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
150 //-------------------------------------------
151
152 static Register as_reg(LIR_Opr op) {
153 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
154 }
155
156 static jlong as_long(LIR_Opr data) {
157 jlong result;
158 switch (data->type()) {
159 case T_INT:
160 result = (data->as_jint());
161 break;
162 case T_LONG:
163 result = (data->as_jlong());
164 break;
165 default:
166 ShouldNotReachHere();
167 result = 0; // unreachable
168 }
169 return result;
170 }
171
172 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
173 Register base = addr->base()->as_pointer_register();
174 LIR_Opr opr = addr->index();
175 if (opr->is_cpu_register()) {
176 Register index;
177 if (opr->is_single_cpu())
178 index = opr->as_register();
179 else
180 index = opr->as_register_lo();
181 assert(addr->disp() == 0, "must be");
182 switch(opr->type()) {
183 case T_INT:
184 return Address(base, index, Address::sxtw(addr->scale()));
185 case T_LONG:
186 return Address(base, index, Address::lsl(addr->scale()));
187 default:
188 ShouldNotReachHere();
189 }
190 } else {
191 assert(addr->scale() == 0,
192 "expected for immediate operand, was: %d", addr->scale());
193 ptrdiff_t offset = ptrdiff_t(addr->disp());
194 // NOTE: Does not handle any 16 byte vector access.
195 const uint type_size = type2aelembytes(addr->type(), true);
196 return __ legitimize_address(Address(base, offset), type_size, tmp);
197 }
198 return Address();
199 }
200
201 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
202 ShouldNotReachHere();
203 return Address();
204 }
205
206 Address LIR_Assembler::as_Address(LIR_Address* addr) {
207 return as_Address(addr, rscratch1);
208 }
209
210 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
211 return as_Address(addr, rscratch1); // Ouch
212 // FIXME: This needs to be much more clever. See x86.
213 }
214
215 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
216 // not encodable as a base + (immediate) offset, generate an explicit address
217 // calculation to hold the address in a temporary register.
218 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
219 precond(size == 4 || size == 8);
220 Address addr = frame_map()->address_for_slot(index, adjust);
221 precond(addr.getMode() == Address::base_plus_offset);
222 precond(addr.base() == sp);
223 precond(addr.offset() > 0);
224 uint mask = size - 1;
225 assert((addr.offset() & mask) == 0, "scaled offsets only");
226 return __ legitimize_address(addr, size, tmp);
227 }
228
229 void LIR_Assembler::osr_entry() {
230 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
231 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
232 ValueStack* entry_state = osr_entry->state();
233 int number_of_locks = entry_state->locks_size();
234
235 // we jump here if osr happens with the interpreter
236 // state set up to continue at the beginning of the
237 // loop that triggered osr - in particular, we have
238 // the following registers setup:
239 //
240 // r2: osr buffer
241 //
242
243 // build frame
244 ciMethod* m = compilation()->method();
245 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
246
247 // OSR buffer is
248 //
249 // locals[nlocals-1..0]
250 // monitors[0..number_of_locks]
251 //
252 // locals is a direct copy of the interpreter frame so in the osr buffer
253 // so first slot in the local array is the last local from the interpreter
254 // and last slot is local[0] (receiver) from the interpreter
255 //
256 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
257 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
258 // in the interpreter frame (the method lock if a sync method)
259
260 // Initialize monitors in the compiled activation.
261 // r2: pointer to osr buffer
262 //
263 // All other registers are dead at this point and the locals will be
264 // copied into place by code emitted in the IR.
265
266 Register OSR_buf = osrBufferPointer()->as_pointer_register();
267 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
268 int monitor_offset = BytesPerWord * method()->max_locals() +
269 (2 * BytesPerWord) * (number_of_locks - 1);
270 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
271 // the OSR buffer using 2 word entries: first the lock and then
272 // the oop.
273 for (int i = 0; i < number_of_locks; i++) {
274 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
275 #ifdef ASSERT
276 // verify the interpreter's monitor has a non-null object
277 {
278 Label L;
279 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
280 __ cbnz(rscratch1, L);
281 __ stop("locked object is null");
282 __ bind(L);
283 }
284 #endif
285 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
286 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
287 __ str(r19, frame_map()->address_for_monitor_lock(i));
288 __ str(r20, frame_map()->address_for_monitor_object(i));
289 }
290 }
291 }
292
293
294 // inline cache check; done before the frame is built.
295 int LIR_Assembler::check_icache() {
296 return __ ic_check(CodeEntryAlignment);
297 }
298
299 void LIR_Assembler::clinit_barrier(ciMethod* method) {
300 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
301 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
302
303 Label L_skip_barrier;
304
305 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
306 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
307 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
308 __ bind(L_skip_barrier);
309 }
310
311 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
312 if (o == nullptr) {
313 __ mov(reg, zr);
314 } else {
315 __ movoop(reg, o);
316 }
317 }
318
319 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
320 address target = nullptr;
321 relocInfo::relocType reloc_type = relocInfo::none;
322
323 switch (patching_id(info)) {
324 case PatchingStub::access_field_id:
325 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
326 reloc_type = relocInfo::section_word_type;
327 break;
328 case PatchingStub::load_klass_id:
329 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
330 reloc_type = relocInfo::metadata_type;
331 break;
332 case PatchingStub::load_mirror_id:
333 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
334 reloc_type = relocInfo::oop_type;
335 break;
336 case PatchingStub::load_appendix_id:
337 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
338 reloc_type = relocInfo::oop_type;
339 break;
340 default: ShouldNotReachHere();
341 }
342
343 __ far_call(RuntimeAddress(target));
344 add_call_info_here(info);
345 }
346
347 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
348 deoptimize_trap(info);
349 }
350
351
352 // This specifies the rsp decrement needed to build the frame
353 int LIR_Assembler::initial_frame_size_in_bytes() const {
354 // if rounding, must let FrameMap know!
355
356 return in_bytes(frame_map()->framesize_in_bytes());
357 }
358
359
360 int LIR_Assembler::emit_exception_handler() {
361 // generate code for exception handler
362 address handler_base = __ start_a_stub(exception_handler_size());
363 if (handler_base == nullptr) {
364 // not enough space left for the handler
365 bailout("exception handler overflow");
366 return -1;
367 }
368
369 int offset = code_offset();
370
371 // the exception oop and pc are in r0, and r3
372 // no other registers need to be preserved, so invalidate them
373 __ invalidate_registers(false, true, true, false, true, true);
374
375 // check that there is really an exception
376 __ verify_not_null_oop(r0);
377
378 // search an exception handler (r0: exception oop, r3: throwing pc)
379 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
380 __ should_not_reach_here();
381 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
382 __ end_a_stub();
383
384 return offset;
385 }
386
387
388 // Emit the code to remove the frame from the stack in the exception
389 // unwind path.
390 int LIR_Assembler::emit_unwind_handler() {
391 #ifndef PRODUCT
392 if (CommentedAssembly) {
393 _masm->block_comment("Unwind handler");
394 }
395 #endif
396
397 int offset = code_offset();
398
399 // Fetch the exception from TLS and clear out exception related thread state
400 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
401 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
402 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
403
404 __ bind(_unwind_handler_entry);
405 __ verify_not_null_oop(r0);
406 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
407 __ mov(r19, r0); // Preserve the exception
408 }
409
410 // Perform needed unlocking
411 MonitorExitStub* stub = nullptr;
412 if (method()->is_synchronized()) {
413 monitor_address(0, FrameMap::r0_opr);
414 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
415 if (LockingMode == LM_MONITOR) {
416 __ b(*stub->entry());
417 } else {
418 __ unlock_object(r5, r4, r0, r6, *stub->entry());
419 }
420 __ bind(*stub->continuation());
421 }
422
423 if (compilation()->env()->dtrace_method_probes()) {
424 __ mov(c_rarg0, rthread);
425 __ mov_metadata(c_rarg1, method()->constant_encoding());
426 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
427 }
428
429 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
430 __ mov(r0, r19); // Restore the exception
431 }
432
433 // remove the activation and dispatch to the unwind handler
434 __ block_comment("remove_frame and dispatch to the unwind handler");
435 __ remove_frame(initial_frame_size_in_bytes());
436 __ far_jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
437
438 // Emit the slow path assembly
439 if (stub != nullptr) {
440 stub->emit_code(this);
441 }
442
443 return offset;
444 }
445
446
447 int LIR_Assembler::emit_deopt_handler() {
448 // generate code for exception handler
449 address handler_base = __ start_a_stub(deopt_handler_size());
450 if (handler_base == nullptr) {
451 // not enough space left for the handler
452 bailout("deopt handler overflow");
453 return -1;
454 }
455
456 int offset = code_offset();
457
458 __ adr(lr, pc());
459 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
460 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
461 __ end_a_stub();
462
463 return offset;
464 }
465
466 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
467 _masm->code_section()->relocate(adr, relocInfo::poll_type);
468 int pc_offset = code_offset();
469 flush_debug_info(pc_offset);
470 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
471 if (info->exception_handlers() != nullptr) {
472 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
473 }
474 }
475
476 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
477 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
478
479 // Pop the stack before the safepoint code
480 __ remove_frame(initial_frame_size_in_bytes());
481
482 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
483 __ reserved_stack_check();
484 }
485
486 code_stub->set_safepoint_offset(__ offset());
487 __ relocate(relocInfo::poll_return_type);
488 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
489 __ ret(lr);
490 }
491
492 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
493 guarantee(info != nullptr, "Shouldn't be null");
494 __ get_polling_page(rscratch1, relocInfo::poll_type);
495 add_debug_info_for_branch(info); // This isn't just debug info:
496 // it's the oop map
497 __ read_polling_page(rscratch1, relocInfo::poll_type);
498 return __ offset();
499 }
500
501
502 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
503 if (from_reg == r31_sp)
504 from_reg = sp;
505 if (to_reg == r31_sp)
506 to_reg = sp;
507 __ mov(to_reg, from_reg);
508 }
509
510 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
511
512
513 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
514 assert(src->is_constant(), "should not call otherwise");
515 assert(dest->is_register(), "should not call otherwise");
516 LIR_Const* c = src->as_constant_ptr();
517
518 switch (c->type()) {
519 case T_INT: {
520 assert(patch_code == lir_patch_none, "no patching handled here");
521 __ movw(dest->as_register(), c->as_jint());
522 break;
523 }
524
525 case T_ADDRESS: {
526 assert(patch_code == lir_patch_none, "no patching handled here");
527 __ mov(dest->as_register(), c->as_jint());
528 break;
529 }
530
531 case T_LONG: {
532 assert(patch_code == lir_patch_none, "no patching handled here");
533 if (SCCache::is_on_for_write()) {
534 // SCA needs relocation info for card table base
535 address b = c->as_pointer();
536 if (is_card_table_address(b)) {
537 __ lea(dest->as_register_lo(), ExternalAddress(b));
538 break;
539 }
540 if (AOTRuntimeConstants::contains(b)) {
541 __ load_aotrc_address(dest->as_register_lo(), b);
542 break;
543 }
544 }
545 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
546 break;
547 }
548
549 case T_OBJECT: {
550 if (patch_code == lir_patch_none) {
551 jobject2reg(c->as_jobject(), dest->as_register());
552 } else {
553 jobject2reg_with_patching(dest->as_register(), info);
554 }
555 break;
556 }
557
558 case T_METADATA: {
559 if (patch_code != lir_patch_none) {
560 klass2reg_with_patching(dest->as_register(), info);
561 } else {
562 __ mov_metadata(dest->as_register(), c->as_metadata());
563 }
564 break;
565 }
566
567 case T_FLOAT: {
568 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
569 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
570 } else {
571 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
572 __ ldrs(dest->as_float_reg(), Address(rscratch1));
573 }
574 break;
575 }
576
577 case T_DOUBLE: {
578 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
579 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
580 } else {
581 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
582 __ ldrd(dest->as_double_reg(), Address(rscratch1));
583 }
584 break;
585 }
586
587 default:
588 ShouldNotReachHere();
589 }
590 }
591
592 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
593 LIR_Const* c = src->as_constant_ptr();
594 switch (c->type()) {
595 case T_OBJECT:
596 {
597 if (! c->as_jobject())
598 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
599 else {
600 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
601 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
602 }
603 }
604 break;
605 case T_ADDRESS:
606 {
607 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
608 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
609 }
610 case T_INT:
611 case T_FLOAT:
612 {
613 Register reg = zr;
614 if (c->as_jint_bits() == 0)
615 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
616 else {
617 __ movw(rscratch1, c->as_jint_bits());
618 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
619 }
620 }
621 break;
622 case T_LONG:
623 case T_DOUBLE:
624 {
625 Register reg = zr;
626 if (c->as_jlong_bits() == 0)
627 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
628 lo_word_offset_in_bytes));
629 else {
630 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
631 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
632 lo_word_offset_in_bytes));
633 }
634 }
635 break;
636 default:
637 ShouldNotReachHere();
638 }
639 }
640
641 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
642 assert(src->is_constant(), "should not call otherwise");
643 LIR_Const* c = src->as_constant_ptr();
644 LIR_Address* to_addr = dest->as_address_ptr();
645
646 void (Assembler::* insn)(Register Rt, const Address &adr);
647
648 switch (type) {
649 case T_ADDRESS:
650 assert(c->as_jint() == 0, "should be");
651 insn = &Assembler::str;
652 break;
653 case T_LONG:
654 assert(c->as_jlong() == 0, "should be");
655 insn = &Assembler::str;
656 break;
657 case T_INT:
658 assert(c->as_jint() == 0, "should be");
659 insn = &Assembler::strw;
660 break;
661 case T_OBJECT:
662 case T_ARRAY:
663 assert(c->as_jobject() == nullptr, "should be");
664 if (UseCompressedOops && !wide) {
665 insn = &Assembler::strw;
666 } else {
667 insn = &Assembler::str;
668 }
669 break;
670 case T_CHAR:
671 case T_SHORT:
672 assert(c->as_jint() == 0, "should be");
673 insn = &Assembler::strh;
674 break;
675 case T_BOOLEAN:
676 case T_BYTE:
677 assert(c->as_jint() == 0, "should be");
678 insn = &Assembler::strb;
679 break;
680 default:
681 ShouldNotReachHere();
682 insn = &Assembler::str; // unreachable
683 }
684
685 if (info) add_debug_info_for_null_check_here(info);
686 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
687 }
688
689 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
690 assert(src->is_register(), "should not call otherwise");
691 assert(dest->is_register(), "should not call otherwise");
692
693 // move between cpu-registers
694 if (dest->is_single_cpu()) {
695 if (src->type() == T_LONG) {
696 // Can do LONG -> OBJECT
697 move_regs(src->as_register_lo(), dest->as_register());
698 return;
699 }
700 assert(src->is_single_cpu(), "must match");
701 if (src->type() == T_OBJECT) {
702 __ verify_oop(src->as_register());
703 }
704 move_regs(src->as_register(), dest->as_register());
705
706 } else if (dest->is_double_cpu()) {
707 if (is_reference_type(src->type())) {
708 // Surprising to me but we can see move of a long to t_object
709 __ verify_oop(src->as_register());
710 move_regs(src->as_register(), dest->as_register_lo());
711 return;
712 }
713 assert(src->is_double_cpu(), "must match");
714 Register f_lo = src->as_register_lo();
715 Register f_hi = src->as_register_hi();
716 Register t_lo = dest->as_register_lo();
717 Register t_hi = dest->as_register_hi();
718 assert(f_hi == f_lo, "must be same");
719 assert(t_hi == t_lo, "must be same");
720 move_regs(f_lo, t_lo);
721
722 } else if (dest->is_single_fpu()) {
723 __ fmovs(dest->as_float_reg(), src->as_float_reg());
724
725 } else if (dest->is_double_fpu()) {
726 __ fmovd(dest->as_double_reg(), src->as_double_reg());
727
728 } else {
729 ShouldNotReachHere();
730 }
731 }
732
733 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
734 precond(src->is_register() && dest->is_stack());
735
736 uint const c_sz32 = sizeof(uint32_t);
737 uint const c_sz64 = sizeof(uint64_t);
738
739 if (src->is_single_cpu()) {
740 int index = dest->single_stack_ix();
741 if (is_reference_type(type)) {
742 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
743 __ verify_oop(src->as_register());
744 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
745 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
746 } else {
747 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
748 }
749
750 } else if (src->is_double_cpu()) {
751 int index = dest->double_stack_ix();
752 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
753 __ str(src->as_register_lo(), dest_addr_LO);
754
755 } else if (src->is_single_fpu()) {
756 int index = dest->single_stack_ix();
757 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
758
759 } else if (src->is_double_fpu()) {
760 int index = dest->double_stack_ix();
761 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
762
763 } else {
764 ShouldNotReachHere();
765 }
766 }
767
768
769 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
770 LIR_Address* to_addr = dest->as_address_ptr();
771 PatchingStub* patch = nullptr;
772 Register compressed_src = rscratch1;
773
774 if (patch_code != lir_patch_none) {
775 deoptimize_trap(info);
776 return;
777 }
778
779 if (is_reference_type(type)) {
780 __ verify_oop(src->as_register());
781
782 if (UseCompressedOops && !wide) {
783 __ encode_heap_oop(compressed_src, src->as_register());
784 } else {
785 compressed_src = src->as_register();
786 }
787 }
788
789 int null_check_here = code_offset();
790 switch (type) {
791 case T_FLOAT: {
792 __ strs(src->as_float_reg(), as_Address(to_addr));
793 break;
794 }
795
796 case T_DOUBLE: {
797 __ strd(src->as_double_reg(), as_Address(to_addr));
798 break;
799 }
800
801 case T_ARRAY: // fall through
802 case T_OBJECT: // fall through
803 if (UseCompressedOops && !wide) {
804 __ strw(compressed_src, as_Address(to_addr, rscratch2));
805 } else {
806 __ str(compressed_src, as_Address(to_addr));
807 }
808 break;
809 case T_METADATA:
810 // We get here to store a method pointer to the stack to pass to
811 // a dtrace runtime call. This can't work on 64 bit with
812 // compressed klass ptrs: T_METADATA can be a compressed klass
813 // ptr or a 64 bit method pointer.
814 ShouldNotReachHere();
815 __ str(src->as_register(), as_Address(to_addr));
816 break;
817 case T_ADDRESS:
818 __ str(src->as_register(), as_Address(to_addr));
819 break;
820 case T_INT:
821 __ strw(src->as_register(), as_Address(to_addr));
822 break;
823
824 case T_LONG: {
825 __ str(src->as_register_lo(), as_Address_lo(to_addr));
826 break;
827 }
828
829 case T_BYTE: // fall through
830 case T_BOOLEAN: {
831 __ strb(src->as_register(), as_Address(to_addr));
832 break;
833 }
834
835 case T_CHAR: // fall through
836 case T_SHORT:
837 __ strh(src->as_register(), as_Address(to_addr));
838 break;
839
840 default:
841 ShouldNotReachHere();
842 }
843 if (info != nullptr) {
844 add_debug_info_for_null_check(null_check_here, info);
845 }
846 }
847
848
849 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
850 precond(src->is_stack() && dest->is_register());
851
852 uint const c_sz32 = sizeof(uint32_t);
853 uint const c_sz64 = sizeof(uint64_t);
854
855 if (dest->is_single_cpu()) {
856 int index = src->single_stack_ix();
857 if (is_reference_type(type)) {
858 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
859 __ verify_oop(dest->as_register());
860 } else if (type == T_METADATA || type == T_ADDRESS) {
861 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
862 } else {
863 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
864 }
865
866 } else if (dest->is_double_cpu()) {
867 int index = src->double_stack_ix();
868 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
869 __ ldr(dest->as_register_lo(), src_addr_LO);
870
871 } else if (dest->is_single_fpu()) {
872 int index = src->single_stack_ix();
873 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
874
875 } else if (dest->is_double_fpu()) {
876 int index = src->double_stack_ix();
877 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
878
879 } else {
880 ShouldNotReachHere();
881 }
882 }
883
884
885 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
886 address target = nullptr;
887 relocInfo::relocType reloc_type = relocInfo::none;
888
889 switch (patching_id(info)) {
890 case PatchingStub::access_field_id:
891 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
892 reloc_type = relocInfo::section_word_type;
893 break;
894 case PatchingStub::load_klass_id:
895 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
896 reloc_type = relocInfo::metadata_type;
897 break;
898 case PatchingStub::load_mirror_id:
899 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
900 reloc_type = relocInfo::oop_type;
901 break;
902 case PatchingStub::load_appendix_id:
903 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
904 reloc_type = relocInfo::oop_type;
905 break;
906 default: ShouldNotReachHere();
907 }
908
909 __ far_call(RuntimeAddress(target));
910 add_call_info_here(info);
911 }
912
913 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
914
915 LIR_Opr temp;
916 if (type == T_LONG || type == T_DOUBLE)
917 temp = FrameMap::rscratch1_long_opr;
918 else
919 temp = FrameMap::rscratch1_opr;
920
921 stack2reg(src, temp, src->type());
922 reg2stack(temp, dest, dest->type(), false);
923 }
924
925
926 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
927 LIR_Address* addr = src->as_address_ptr();
928 LIR_Address* from_addr = src->as_address_ptr();
929
930 if (addr->base()->type() == T_OBJECT) {
931 __ verify_oop(addr->base()->as_pointer_register());
932 }
933
934 if (patch_code != lir_patch_none) {
935 deoptimize_trap(info);
936 return;
937 }
938
939 if (info != nullptr) {
940 add_debug_info_for_null_check_here(info);
941 }
942 int null_check_here = code_offset();
943 switch (type) {
944 case T_FLOAT: {
945 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
946 break;
947 }
948
949 case T_DOUBLE: {
950 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
951 break;
952 }
953
954 case T_ARRAY: // fall through
955 case T_OBJECT: // fall through
956 if (UseCompressedOops && !wide) {
957 __ ldrw(dest->as_register(), as_Address(from_addr));
958 } else {
959 __ ldr(dest->as_register(), as_Address(from_addr));
960 }
961 break;
962 case T_METADATA:
963 // We get here to store a method pointer to the stack to pass to
964 // a dtrace runtime call. This can't work on 64 bit with
965 // compressed klass ptrs: T_METADATA can be a compressed klass
966 // ptr or a 64 bit method pointer.
967 ShouldNotReachHere();
968 __ ldr(dest->as_register(), as_Address(from_addr));
969 break;
970 case T_ADDRESS:
971 __ ldr(dest->as_register(), as_Address(from_addr));
972 break;
973 case T_INT:
974 __ ldrw(dest->as_register(), as_Address(from_addr));
975 break;
976
977 case T_LONG: {
978 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
979 break;
980 }
981
982 case T_BYTE:
983 __ ldrsb(dest->as_register(), as_Address(from_addr));
984 break;
985 case T_BOOLEAN: {
986 __ ldrb(dest->as_register(), as_Address(from_addr));
987 break;
988 }
989
990 case T_CHAR:
991 __ ldrh(dest->as_register(), as_Address(from_addr));
992 break;
993 case T_SHORT:
994 __ ldrsh(dest->as_register(), as_Address(from_addr));
995 break;
996
997 default:
998 ShouldNotReachHere();
999 }
1000
1001 if (is_reference_type(type)) {
1002 if (UseCompressedOops && !wide) {
1003 __ decode_heap_oop(dest->as_register());
1004 }
1005
1006 __ verify_oop(dest->as_register());
1007 }
1008 }
1009
1010
1011 int LIR_Assembler::array_element_size(BasicType type) const {
1012 int elem_size = type2aelembytes(type);
1013 return exact_log2(elem_size);
1014 }
1015
1016
1017 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1018 switch (op->code()) {
1019 case lir_idiv:
1020 case lir_irem:
1021 arithmetic_idiv(op->code(),
1022 op->in_opr1(),
1023 op->in_opr2(),
1024 op->in_opr3(),
1025 op->result_opr(),
1026 op->info());
1027 break;
1028 case lir_fmad:
1029 __ fmaddd(op->result_opr()->as_double_reg(),
1030 op->in_opr1()->as_double_reg(),
1031 op->in_opr2()->as_double_reg(),
1032 op->in_opr3()->as_double_reg());
1033 break;
1034 case lir_fmaf:
1035 __ fmadds(op->result_opr()->as_float_reg(),
1036 op->in_opr1()->as_float_reg(),
1037 op->in_opr2()->as_float_reg(),
1038 op->in_opr3()->as_float_reg());
1039 break;
1040 default: ShouldNotReachHere(); break;
1041 }
1042 }
1043
1044 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1045 #ifdef ASSERT
1046 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1047 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1048 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1049 #endif
1050
1051 if (op->cond() == lir_cond_always) {
1052 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1053 __ b(*(op->label()));
1054 } else {
1055 Assembler::Condition acond;
1056 if (op->code() == lir_cond_float_branch) {
1057 bool is_unordered = (op->ublock() == op->block());
1058 // Assembler::EQ does not permit unordered branches, so we add
1059 // another branch here. Likewise, Assembler::NE does not permit
1060 // ordered branches.
1061 if ((is_unordered && op->cond() == lir_cond_equal)
1062 || (!is_unordered && op->cond() == lir_cond_notEqual))
1063 __ br(Assembler::VS, *(op->ublock()->label()));
1064 switch(op->cond()) {
1065 case lir_cond_equal: acond = Assembler::EQ; break;
1066 case lir_cond_notEqual: acond = Assembler::NE; break;
1067 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1068 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1069 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1070 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1071 default: ShouldNotReachHere();
1072 acond = Assembler::EQ; // unreachable
1073 }
1074 } else {
1075 switch (op->cond()) {
1076 case lir_cond_equal: acond = Assembler::EQ; break;
1077 case lir_cond_notEqual: acond = Assembler::NE; break;
1078 case lir_cond_less: acond = Assembler::LT; break;
1079 case lir_cond_lessEqual: acond = Assembler::LE; break;
1080 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1081 case lir_cond_greater: acond = Assembler::GT; break;
1082 case lir_cond_belowEqual: acond = Assembler::LS; break;
1083 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1084 default: ShouldNotReachHere();
1085 acond = Assembler::EQ; // unreachable
1086 }
1087 }
1088 __ br(acond,*(op->label()));
1089 }
1090 }
1091
1092
1093
1094 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1095 LIR_Opr src = op->in_opr();
1096 LIR_Opr dest = op->result_opr();
1097
1098 switch (op->bytecode()) {
1099 case Bytecodes::_i2f:
1100 {
1101 __ scvtfws(dest->as_float_reg(), src->as_register());
1102 break;
1103 }
1104 case Bytecodes::_i2d:
1105 {
1106 __ scvtfwd(dest->as_double_reg(), src->as_register());
1107 break;
1108 }
1109 case Bytecodes::_l2d:
1110 {
1111 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1112 break;
1113 }
1114 case Bytecodes::_l2f:
1115 {
1116 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1117 break;
1118 }
1119 case Bytecodes::_f2d:
1120 {
1121 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1122 break;
1123 }
1124 case Bytecodes::_d2f:
1125 {
1126 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1127 break;
1128 }
1129 case Bytecodes::_i2c:
1130 {
1131 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1132 break;
1133 }
1134 case Bytecodes::_i2l:
1135 {
1136 __ sxtw(dest->as_register_lo(), src->as_register());
1137 break;
1138 }
1139 case Bytecodes::_i2s:
1140 {
1141 __ sxth(dest->as_register(), src->as_register());
1142 break;
1143 }
1144 case Bytecodes::_i2b:
1145 {
1146 __ sxtb(dest->as_register(), src->as_register());
1147 break;
1148 }
1149 case Bytecodes::_l2i:
1150 {
1151 _masm->block_comment("FIXME: This could be a no-op");
1152 __ uxtw(dest->as_register(), src->as_register_lo());
1153 break;
1154 }
1155 case Bytecodes::_d2l:
1156 {
1157 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1158 break;
1159 }
1160 case Bytecodes::_f2i:
1161 {
1162 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1163 break;
1164 }
1165 case Bytecodes::_f2l:
1166 {
1167 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1168 break;
1169 }
1170 case Bytecodes::_d2i:
1171 {
1172 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1173 break;
1174 }
1175 default: ShouldNotReachHere();
1176 }
1177 }
1178
1179 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1180 if (op->init_check()) {
1181 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1182 __ ldarb(rscratch1, rscratch1);
1183 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1184 add_debug_info_for_null_check_here(op->stub()->info());
1185 __ br(Assembler::NE, *op->stub()->entry());
1186 }
1187 __ allocate_object(op->obj()->as_register(),
1188 op->tmp1()->as_register(),
1189 op->tmp2()->as_register(),
1190 op->header_size(),
1191 op->object_size(),
1192 op->klass()->as_register(),
1193 *op->stub()->entry());
1194 __ bind(*op->stub()->continuation());
1195 }
1196
1197 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1198 Register len = op->len()->as_register();
1199 __ uxtw(len, len);
1200
1201 if (UseSlowPath ||
1202 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1203 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1204 __ b(*op->stub()->entry());
1205 } else {
1206 Register tmp1 = op->tmp1()->as_register();
1207 Register tmp2 = op->tmp2()->as_register();
1208 Register tmp3 = op->tmp3()->as_register();
1209 if (len == tmp1) {
1210 tmp1 = tmp3;
1211 } else if (len == tmp2) {
1212 tmp2 = tmp3;
1213 } else if (len == tmp3) {
1214 // everything is ok
1215 } else {
1216 __ mov(tmp3, len);
1217 }
1218 __ allocate_array(op->obj()->as_register(),
1219 len,
1220 tmp1,
1221 tmp2,
1222 arrayOopDesc::base_offset_in_bytes(op->type()),
1223 array_element_size(op->type()),
1224 op->klass()->as_register(),
1225 *op->stub()->entry(),
1226 op->zero_array());
1227 }
1228 __ bind(*op->stub()->continuation());
1229 }
1230
1231 void LIR_Assembler::type_profile_helper(Register mdo,
1232 ciMethodData *md, ciProfileData *data,
1233 Register recv, Label* update_done) {
1234
1235 // Given a profile data offset, generate an Address which points to
1236 // the corresponding slot in mdo->data().
1237 // Clobbers rscratch2.
1238 auto slot_at = [=](ByteSize offset) -> Address {
1239 return __ form_address(rscratch2, mdo,
1240 md->byte_offset_of_slot(data, offset),
1241 LogBytesPerWord);
1242 };
1243
1244 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1245 Label next_test;
1246 // See if the receiver is receiver[n].
1247 __ ldr(rscratch1, slot_at(ReceiverTypeData::receiver_offset(i)));
1248 __ cmp(recv, rscratch1);
1249 __ br(Assembler::NE, next_test);
1250 __ addptr(slot_at(ReceiverTypeData::receiver_count_offset(i)),
1251 DataLayout::counter_increment);
1252 __ b(*update_done);
1253 __ bind(next_test);
1254 }
1255
1256 // Didn't find receiver; find next empty slot and fill it in
1257 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1258 Label next_test;
1259 Address recv_addr(slot_at(ReceiverTypeData::receiver_offset(i)));
1260 __ ldr(rscratch1, recv_addr);
1261 __ cbnz(rscratch1, next_test);
1262 __ str(recv, recv_addr);
1263 __ mov(rscratch1, DataLayout::counter_increment);
1264 __ str(rscratch1, slot_at(ReceiverTypeData::receiver_count_offset(i)));
1265 __ b(*update_done);
1266 __ bind(next_test);
1267 }
1268 }
1269
1270 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1271 // we always need a stub for the failure case.
1272 CodeStub* stub = op->stub();
1273 Register obj = op->object()->as_register();
1274 Register k_RInfo = op->tmp1()->as_register();
1275 Register klass_RInfo = op->tmp2()->as_register();
1276 Register dst = op->result_opr()->as_register();
1277 ciKlass* k = op->klass();
1278 Register Rtmp1 = noreg;
1279
1280 // check if it needs to be profiled
1281 ciMethodData* md;
1282 ciProfileData* data;
1283
1284 const bool should_profile = op->should_profile();
1285
1286 if (should_profile) {
1287 ciMethod* method = op->profiled_method();
1288 assert(method != nullptr, "Should have method");
1289 int bci = op->profiled_bci();
1290 md = method->method_data_or_null();
1291 assert(md != nullptr, "Sanity");
1292 data = md->bci_to_data(bci);
1293 assert(data != nullptr, "need data for type check");
1294 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1295 }
1296 Label* success_target = success;
1297 Label* failure_target = failure;
1298
1299 if (obj == k_RInfo) {
1300 k_RInfo = dst;
1301 } else if (obj == klass_RInfo) {
1302 klass_RInfo = dst;
1303 }
1304 if (k->is_loaded() && !UseCompressedClassPointers) {
1305 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1306 } else {
1307 Rtmp1 = op->tmp3()->as_register();
1308 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1309 }
1310
1311 assert_different_registers(obj, k_RInfo, klass_RInfo);
1312
1313 if (should_profile) {
1314 Register mdo = klass_RInfo;
1315 __ mov_metadata(mdo, md->constant_encoding());
1316 Label not_null;
1317 __ cbnz(obj, not_null);
1318 // Object is null; update MDO and exit
1319 Address data_addr
1320 = __ form_address(rscratch2, mdo,
1321 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1322 0);
1323 __ ldrb(rscratch1, data_addr);
1324 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1325 __ strb(rscratch1, data_addr);
1326 __ b(*obj_is_null);
1327 __ bind(not_null);
1328
1329 Label update_done;
1330 Register recv = k_RInfo;
1331 __ load_klass(recv, obj);
1332 type_profile_helper(mdo, md, data, recv, &update_done);
1333 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1334 __ addptr(counter_addr, DataLayout::counter_increment);
1335
1336 __ bind(update_done);
1337 } else {
1338 __ cbz(obj, *obj_is_null);
1339 }
1340
1341 if (!k->is_loaded()) {
1342 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1343 } else {
1344 __ mov_metadata(k_RInfo, k->constant_encoding());
1345 }
1346 __ verify_oop(obj);
1347
1348 if (op->fast_check()) {
1349 // get object class
1350 // not a safepoint as obj null check happens earlier
1351 __ load_klass(rscratch1, obj);
1352 __ cmp( rscratch1, k_RInfo);
1353
1354 __ br(Assembler::NE, *failure_target);
1355 // successful cast, fall through to profile or jump
1356 } else {
1357 // get object class
1358 // not a safepoint as obj null check happens earlier
1359 __ load_klass(klass_RInfo, obj);
1360 if (k->is_loaded()) {
1361 // See if we get an immediate positive hit
1362 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1363 __ cmp(k_RInfo, rscratch1);
1364 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1365 __ br(Assembler::NE, *failure_target);
1366 // successful cast, fall through to profile or jump
1367 } else {
1368 // See if we get an immediate positive hit
1369 __ br(Assembler::EQ, *success_target);
1370 // check for self
1371 __ cmp(klass_RInfo, k_RInfo);
1372 __ br(Assembler::EQ, *success_target);
1373
1374 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1375 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1376 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1377 // result is a boolean
1378 __ cbzw(klass_RInfo, *failure_target);
1379 // successful cast, fall through to profile or jump
1380 }
1381 } else {
1382 // perform the fast part of the checking logic
1383 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1384 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1385 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1386 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1387 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1388 // result is a boolean
1389 __ cbz(k_RInfo, *failure_target);
1390 // successful cast, fall through to profile or jump
1391 }
1392 }
1393 __ b(*success);
1394 }
1395
1396
1397 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1398 const bool should_profile = op->should_profile();
1399
1400 LIR_Code code = op->code();
1401 if (code == lir_store_check) {
1402 Register value = op->object()->as_register();
1403 Register array = op->array()->as_register();
1404 Register k_RInfo = op->tmp1()->as_register();
1405 Register klass_RInfo = op->tmp2()->as_register();
1406 Register Rtmp1 = op->tmp3()->as_register();
1407
1408 CodeStub* stub = op->stub();
1409
1410 // check if it needs to be profiled
1411 ciMethodData* md;
1412 ciProfileData* data;
1413
1414 if (should_profile) {
1415 ciMethod* method = op->profiled_method();
1416 assert(method != nullptr, "Should have method");
1417 int bci = op->profiled_bci();
1418 md = method->method_data_or_null();
1419 assert(md != nullptr, "Sanity");
1420 data = md->bci_to_data(bci);
1421 assert(data != nullptr, "need data for type check");
1422 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1423 }
1424 Label done;
1425 Label* success_target = &done;
1426 Label* failure_target = stub->entry();
1427
1428 if (should_profile) {
1429 Label not_null;
1430 Register mdo = klass_RInfo;
1431 __ mov_metadata(mdo, md->constant_encoding());
1432 __ cbnz(value, not_null);
1433 // Object is null; update MDO and exit
1434 Address data_addr
1435 = __ form_address(rscratch2, mdo,
1436 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1437 __ ldrb(rscratch1, data_addr);
1438 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1439 __ strb(rscratch1, data_addr);
1440 __ b(done);
1441 __ bind(not_null);
1442
1443 Label update_done;
1444 Register recv = k_RInfo;
1445 __ load_klass(recv, value);
1446 type_profile_helper(mdo, md, data, recv, &update_done);
1447 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1448 __ addptr(counter_addr, DataLayout::counter_increment);
1449 __ bind(update_done);
1450 } else {
1451 __ cbz(value, done);
1452 }
1453
1454 add_debug_info_for_null_check_here(op->info_for_exception());
1455 __ load_klass(k_RInfo, array);
1456 __ load_klass(klass_RInfo, value);
1457
1458 // get instance klass (it's already uncompressed)
1459 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1460 // perform the fast part of the checking logic
1461 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1462 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1463 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1464 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1465 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1466 // result is a boolean
1467 __ cbzw(k_RInfo, *failure_target);
1468 // fall through to the success case
1469
1470 __ bind(done);
1471 } else if (code == lir_checkcast) {
1472 Register obj = op->object()->as_register();
1473 Register dst = op->result_opr()->as_register();
1474 Label success;
1475 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1476 __ bind(success);
1477 if (dst != obj) {
1478 __ mov(dst, obj);
1479 }
1480 } else if (code == lir_instanceof) {
1481 Register obj = op->object()->as_register();
1482 Register dst = op->result_opr()->as_register();
1483 Label success, failure, done;
1484 emit_typecheck_helper(op, &success, &failure, &failure);
1485 __ bind(failure);
1486 __ mov(dst, zr);
1487 __ b(done);
1488 __ bind(success);
1489 __ mov(dst, 1);
1490 __ bind(done);
1491 } else {
1492 ShouldNotReachHere();
1493 }
1494 }
1495
1496 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1497 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1498 __ cset(rscratch1, Assembler::NE);
1499 __ membar(__ AnyAny);
1500 }
1501
1502 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1503 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1504 __ cset(rscratch1, Assembler::NE);
1505 __ membar(__ AnyAny);
1506 }
1507
1508
1509 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1510 Register addr;
1511 if (op->addr()->is_register()) {
1512 addr = as_reg(op->addr());
1513 } else {
1514 assert(op->addr()->is_address(), "what else?");
1515 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1516 assert(addr_ptr->disp() == 0, "need 0 disp");
1517 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1518 addr = as_reg(addr_ptr->base());
1519 }
1520 Register newval = as_reg(op->new_value());
1521 Register cmpval = as_reg(op->cmp_value());
1522
1523 if (op->code() == lir_cas_obj) {
1524 if (UseCompressedOops) {
1525 Register t1 = op->tmp1()->as_register();
1526 assert(op->tmp1()->is_valid(), "must be");
1527 __ encode_heap_oop(t1, cmpval);
1528 cmpval = t1;
1529 __ encode_heap_oop(rscratch2, newval);
1530 newval = rscratch2;
1531 casw(addr, newval, cmpval);
1532 } else {
1533 casl(addr, newval, cmpval);
1534 }
1535 } else if (op->code() == lir_cas_int) {
1536 casw(addr, newval, cmpval);
1537 } else {
1538 casl(addr, newval, cmpval);
1539 }
1540 }
1541
1542
1543 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1544 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1545 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1546
1547 Assembler::Condition acond, ncond;
1548 switch (condition) {
1549 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1550 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1551 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1552 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1553 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1554 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1555 case lir_cond_belowEqual:
1556 case lir_cond_aboveEqual:
1557 default: ShouldNotReachHere();
1558 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1559 }
1560
1561 assert(result->is_single_cpu() || result->is_double_cpu(),
1562 "expect single register for result");
1563 if (opr1->is_constant() && opr2->is_constant()
1564 && opr1->type() == T_INT && opr2->type() == T_INT) {
1565 jint val1 = opr1->as_jint();
1566 jint val2 = opr2->as_jint();
1567 if (val1 == 0 && val2 == 1) {
1568 __ cset(result->as_register(), ncond);
1569 return;
1570 } else if (val1 == 1 && val2 == 0) {
1571 __ cset(result->as_register(), acond);
1572 return;
1573 }
1574 }
1575
1576 if (opr1->is_constant() && opr2->is_constant()
1577 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1578 jlong val1 = opr1->as_jlong();
1579 jlong val2 = opr2->as_jlong();
1580 if (val1 == 0 && val2 == 1) {
1581 __ cset(result->as_register_lo(), ncond);
1582 return;
1583 } else if (val1 == 1 && val2 == 0) {
1584 __ cset(result->as_register_lo(), acond);
1585 return;
1586 }
1587 }
1588
1589 if (opr1->is_stack()) {
1590 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1591 opr1 = FrameMap::rscratch1_opr;
1592 } else if (opr1->is_constant()) {
1593 LIR_Opr tmp
1594 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1595 const2reg(opr1, tmp, lir_patch_none, nullptr);
1596 opr1 = tmp;
1597 }
1598
1599 if (opr2->is_stack()) {
1600 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1601 opr2 = FrameMap::rscratch2_opr;
1602 } else if (opr2->is_constant()) {
1603 LIR_Opr tmp
1604 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1605 const2reg(opr2, tmp, lir_patch_none, nullptr);
1606 opr2 = tmp;
1607 }
1608
1609 if (result->type() == T_LONG)
1610 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1611 else
1612 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1613 }
1614
1615 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1616 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1617
1618 if (left->is_single_cpu()) {
1619 Register lreg = left->as_register();
1620 Register dreg = as_reg(dest);
1621
1622 if (right->is_single_cpu()) {
1623 // cpu register - cpu register
1624
1625 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1626 "should be");
1627 Register rreg = right->as_register();
1628 switch (code) {
1629 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1630 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1631 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1632 default: ShouldNotReachHere();
1633 }
1634
1635 } else if (right->is_double_cpu()) {
1636 Register rreg = right->as_register_lo();
1637 // single_cpu + double_cpu: can happen with obj+long
1638 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1639 switch (code) {
1640 case lir_add: __ add(dreg, lreg, rreg); break;
1641 case lir_sub: __ sub(dreg, lreg, rreg); break;
1642 default: ShouldNotReachHere();
1643 }
1644 } else if (right->is_constant()) {
1645 // cpu register - constant
1646 jlong c;
1647
1648 // FIXME. This is fugly: we really need to factor all this logic.
1649 switch(right->type()) {
1650 case T_LONG:
1651 c = right->as_constant_ptr()->as_jlong();
1652 break;
1653 case T_INT:
1654 case T_ADDRESS:
1655 c = right->as_constant_ptr()->as_jint();
1656 break;
1657 default:
1658 ShouldNotReachHere();
1659 c = 0; // unreachable
1660 break;
1661 }
1662
1663 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1664 if (c == 0 && dreg == lreg) {
1665 COMMENT("effective nop elided");
1666 return;
1667 }
1668 switch(left->type()) {
1669 case T_INT:
1670 switch (code) {
1671 case lir_add: __ addw(dreg, lreg, c); break;
1672 case lir_sub: __ subw(dreg, lreg, c); break;
1673 default: ShouldNotReachHere();
1674 }
1675 break;
1676 case T_OBJECT:
1677 case T_ADDRESS:
1678 switch (code) {
1679 case lir_add: __ add(dreg, lreg, c); break;
1680 case lir_sub: __ sub(dreg, lreg, c); break;
1681 default: ShouldNotReachHere();
1682 }
1683 break;
1684 default:
1685 ShouldNotReachHere();
1686 }
1687 } else {
1688 ShouldNotReachHere();
1689 }
1690
1691 } else if (left->is_double_cpu()) {
1692 Register lreg_lo = left->as_register_lo();
1693
1694 if (right->is_double_cpu()) {
1695 // cpu register - cpu register
1696 Register rreg_lo = right->as_register_lo();
1697 switch (code) {
1698 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1699 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1700 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1701 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1702 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1703 default:
1704 ShouldNotReachHere();
1705 }
1706
1707 } else if (right->is_constant()) {
1708 jlong c = right->as_constant_ptr()->as_jlong();
1709 Register dreg = as_reg(dest);
1710 switch (code) {
1711 case lir_add:
1712 case lir_sub:
1713 if (c == 0 && dreg == lreg_lo) {
1714 COMMENT("effective nop elided");
1715 return;
1716 }
1717 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1718 break;
1719 case lir_div:
1720 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1721 if (c == 1) {
1722 // move lreg_lo to dreg if divisor is 1
1723 __ mov(dreg, lreg_lo);
1724 } else {
1725 unsigned int shift = log2i_exact(c);
1726 // use rscratch1 as intermediate result register
1727 __ asr(rscratch1, lreg_lo, 63);
1728 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1729 __ asr(dreg, rscratch1, shift);
1730 }
1731 break;
1732 case lir_rem:
1733 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1734 if (c == 1) {
1735 // move 0 to dreg if divisor is 1
1736 __ mov(dreg, zr);
1737 } else {
1738 // use rscratch1 as intermediate result register
1739 __ negs(rscratch1, lreg_lo);
1740 __ andr(dreg, lreg_lo, c - 1);
1741 __ andr(rscratch1, rscratch1, c - 1);
1742 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1743 }
1744 break;
1745 default:
1746 ShouldNotReachHere();
1747 }
1748 } else {
1749 ShouldNotReachHere();
1750 }
1751 } else if (left->is_single_fpu()) {
1752 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1753 switch (code) {
1754 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1755 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1756 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1757 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1758 default:
1759 ShouldNotReachHere();
1760 }
1761 } else if (left->is_double_fpu()) {
1762 if (right->is_double_fpu()) {
1763 // fpu register - fpu register
1764 switch (code) {
1765 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1766 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1767 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1768 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1769 default:
1770 ShouldNotReachHere();
1771 }
1772 } else {
1773 if (right->is_constant()) {
1774 ShouldNotReachHere();
1775 }
1776 ShouldNotReachHere();
1777 }
1778 } else if (left->is_single_stack() || left->is_address()) {
1779 assert(left == dest, "left and dest must be equal");
1780 ShouldNotReachHere();
1781 } else {
1782 ShouldNotReachHere();
1783 }
1784 }
1785
1786 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1787
1788
1789 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1790 switch(code) {
1791 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1792 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1793 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1794 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1795 default : ShouldNotReachHere();
1796 }
1797 }
1798
1799 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1800
1801 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1802 Register Rleft = left->is_single_cpu() ? left->as_register() :
1803 left->as_register_lo();
1804 if (dst->is_single_cpu()) {
1805 Register Rdst = dst->as_register();
1806 if (right->is_constant()) {
1807 switch (code) {
1808 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1809 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1810 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1811 default: ShouldNotReachHere(); break;
1812 }
1813 } else {
1814 Register Rright = right->is_single_cpu() ? right->as_register() :
1815 right->as_register_lo();
1816 switch (code) {
1817 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1818 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1819 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1820 default: ShouldNotReachHere(); break;
1821 }
1822 }
1823 } else {
1824 Register Rdst = dst->as_register_lo();
1825 if (right->is_constant()) {
1826 switch (code) {
1827 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1828 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1829 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1830 default: ShouldNotReachHere(); break;
1831 }
1832 } else {
1833 Register Rright = right->is_single_cpu() ? right->as_register() :
1834 right->as_register_lo();
1835 switch (code) {
1836 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1837 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1838 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1839 default: ShouldNotReachHere(); break;
1840 }
1841 }
1842 }
1843 }
1844
1845
1846
1847 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1848
1849 // opcode check
1850 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1851 bool is_irem = (code == lir_irem);
1852
1853 // operand check
1854 assert(left->is_single_cpu(), "left must be register");
1855 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1856 assert(result->is_single_cpu(), "result must be register");
1857 Register lreg = left->as_register();
1858 Register dreg = result->as_register();
1859
1860 // power-of-2 constant check and codegen
1861 if (right->is_constant()) {
1862 int c = right->as_constant_ptr()->as_jint();
1863 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1864 if (is_irem) {
1865 if (c == 1) {
1866 // move 0 to dreg if divisor is 1
1867 __ movw(dreg, zr);
1868 } else {
1869 // use rscratch1 as intermediate result register
1870 __ negsw(rscratch1, lreg);
1871 __ andw(dreg, lreg, c - 1);
1872 __ andw(rscratch1, rscratch1, c - 1);
1873 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1874 }
1875 } else {
1876 if (c == 1) {
1877 // move lreg to dreg if divisor is 1
1878 __ movw(dreg, lreg);
1879 } else {
1880 unsigned int shift = exact_log2(c);
1881 // use rscratch1 as intermediate result register
1882 __ asrw(rscratch1, lreg, 31);
1883 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1884 __ asrw(dreg, rscratch1, shift);
1885 }
1886 }
1887 } else {
1888 Register rreg = right->as_register();
1889 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1890 }
1891 }
1892
1893
1894 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1895 if (opr1->is_constant() && opr2->is_single_cpu()) {
1896 // tableswitch
1897 Register reg = as_reg(opr2);
1898 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1899 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1900 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1901 Register reg1 = as_reg(opr1);
1902 if (opr2->is_single_cpu()) {
1903 // cpu register - cpu register
1904 Register reg2 = opr2->as_register();
1905 if (is_reference_type(opr1->type())) {
1906 __ cmpoop(reg1, reg2);
1907 } else {
1908 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1909 __ cmpw(reg1, reg2);
1910 }
1911 return;
1912 }
1913 if (opr2->is_double_cpu()) {
1914 // cpu register - cpu register
1915 Register reg2 = opr2->as_register_lo();
1916 __ cmp(reg1, reg2);
1917 return;
1918 }
1919
1920 if (opr2->is_constant()) {
1921 bool is_32bit = false; // width of register operand
1922 jlong imm;
1923
1924 switch(opr2->type()) {
1925 case T_INT:
1926 imm = opr2->as_constant_ptr()->as_jint();
1927 is_32bit = true;
1928 break;
1929 case T_LONG:
1930 imm = opr2->as_constant_ptr()->as_jlong();
1931 break;
1932 case T_ADDRESS:
1933 imm = opr2->as_constant_ptr()->as_jint();
1934 break;
1935 case T_METADATA:
1936 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1937 break;
1938 case T_OBJECT:
1939 case T_ARRAY:
1940 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1941 __ cmpoop(reg1, rscratch1);
1942 return;
1943 default:
1944 ShouldNotReachHere();
1945 imm = 0; // unreachable
1946 break;
1947 }
1948
1949 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1950 if (is_32bit)
1951 __ cmpw(reg1, imm);
1952 else
1953 __ subs(zr, reg1, imm);
1954 return;
1955 } else {
1956 __ mov(rscratch1, imm);
1957 if (is_32bit)
1958 __ cmpw(reg1, rscratch1);
1959 else
1960 __ cmp(reg1, rscratch1);
1961 return;
1962 }
1963 } else
1964 ShouldNotReachHere();
1965 } else if (opr1->is_single_fpu()) {
1966 FloatRegister reg1 = opr1->as_float_reg();
1967 assert(opr2->is_single_fpu(), "expect single float register");
1968 FloatRegister reg2 = opr2->as_float_reg();
1969 __ fcmps(reg1, reg2);
1970 } else if (opr1->is_double_fpu()) {
1971 FloatRegister reg1 = opr1->as_double_reg();
1972 assert(opr2->is_double_fpu(), "expect double float register");
1973 FloatRegister reg2 = opr2->as_double_reg();
1974 __ fcmpd(reg1, reg2);
1975 } else {
1976 ShouldNotReachHere();
1977 }
1978 }
1979
1980 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1981 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1982 bool is_unordered_less = (code == lir_ucmp_fd2i);
1983 if (left->is_single_fpu()) {
1984 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1985 } else if (left->is_double_fpu()) {
1986 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1987 } else {
1988 ShouldNotReachHere();
1989 }
1990 } else if (code == lir_cmp_l2i) {
1991 Label done;
1992 __ cmp(left->as_register_lo(), right->as_register_lo());
1993 __ mov(dst->as_register(), (uint64_t)-1L);
1994 __ br(Assembler::LT, done);
1995 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
1996 __ bind(done);
1997 } else {
1998 ShouldNotReachHere();
1999 }
2000 }
2001
2002
2003 void LIR_Assembler::align_call(LIR_Code code) { }
2004
2005
2006 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2007 address call = __ trampoline_call(Address(op->addr(), rtype));
2008 if (call == nullptr) {
2009 bailout("trampoline stub overflow");
2010 return;
2011 }
2012 add_call_info(code_offset(), op->info());
2013 __ post_call_nop();
2014 }
2015
2016
2017 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2018 address call = __ ic_call(op->addr());
2019 if (call == nullptr) {
2020 bailout("trampoline stub overflow");
2021 return;
2022 }
2023 add_call_info(code_offset(), op->info());
2024 __ post_call_nop();
2025 }
2026
2027 void LIR_Assembler::emit_static_call_stub() {
2028 address call_pc = __ pc();
2029 address stub = __ start_a_stub(call_stub_size());
2030 if (stub == nullptr) {
2031 bailout("static call stub overflow");
2032 return;
2033 }
2034
2035 int start = __ offset();
2036
2037 __ relocate(static_stub_Relocation::spec(call_pc));
2038 __ emit_static_call_stub();
2039
2040 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2041 <= call_stub_size(), "stub too big");
2042 __ end_a_stub();
2043 }
2044
2045
2046 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2047 assert(exceptionOop->as_register() == r0, "must match");
2048 assert(exceptionPC->as_register() == r3, "must match");
2049
2050 // exception object is not added to oop map by LinearScan
2051 // (LinearScan assumes that no oops are in fixed registers)
2052 info->add_register_oop(exceptionOop);
2053 C1StubId unwind_id;
2054
2055 // get current pc information
2056 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2057 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2058 // As no instructions have been generated yet for this LIR node it's
2059 // possible that an oop map already exists for the current offset.
2060 // In that case insert an dummy NOP here to ensure all oop map PCs
2061 // are unique. See JDK-8237483.
2062 __ nop();
2063 }
2064 int pc_for_athrow_offset = __ offset();
2065 InternalAddress pc_for_athrow(__ pc());
2066 __ adr(exceptionPC->as_register(), pc_for_athrow);
2067 add_call_info(pc_for_athrow_offset, info); // for exception handler
2068
2069 __ verify_not_null_oop(r0);
2070 // search an exception handler (r0: exception oop, r3: throwing pc)
2071 if (compilation()->has_fpu_code()) {
2072 unwind_id = C1StubId::handle_exception_id;
2073 } else {
2074 unwind_id = C1StubId::handle_exception_nofpu_id;
2075 }
2076 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2077
2078 // FIXME: enough room for two byte trap ????
2079 __ nop();
2080 }
2081
2082
2083 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2084 assert(exceptionOop->as_register() == r0, "must match");
2085
2086 __ b(_unwind_handler_entry);
2087 }
2088
2089
2090 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2091 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2092 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2093
2094 switch (left->type()) {
2095 case T_INT: {
2096 switch (code) {
2097 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2098 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2099 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2100 default:
2101 ShouldNotReachHere();
2102 break;
2103 }
2104 break;
2105 case T_LONG:
2106 case T_ADDRESS:
2107 case T_OBJECT:
2108 switch (code) {
2109 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2110 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2111 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2112 default:
2113 ShouldNotReachHere();
2114 break;
2115 }
2116 break;
2117 default:
2118 ShouldNotReachHere();
2119 break;
2120 }
2121 }
2122 }
2123
2124
2125 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2126 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2127 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2128
2129 switch (left->type()) {
2130 case T_INT: {
2131 switch (code) {
2132 case lir_shl: __ lslw (dreg, lreg, count); break;
2133 case lir_shr: __ asrw (dreg, lreg, count); break;
2134 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2135 default:
2136 ShouldNotReachHere();
2137 break;
2138 }
2139 break;
2140 case T_LONG:
2141 case T_ADDRESS:
2142 case T_OBJECT:
2143 switch (code) {
2144 case lir_shl: __ lsl (dreg, lreg, count); break;
2145 case lir_shr: __ asr (dreg, lreg, count); break;
2146 case lir_ushr: __ lsr (dreg, lreg, count); break;
2147 default:
2148 ShouldNotReachHere();
2149 break;
2150 }
2151 break;
2152 default:
2153 ShouldNotReachHere();
2154 break;
2155 }
2156 }
2157 }
2158
2159
2160 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2161 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2162 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2163 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2164 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2165 }
2166
2167
2168 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2169 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2170 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2171 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2172 __ mov (rscratch1, c);
2173 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2174 }
2175
2176
2177 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2178 ShouldNotReachHere();
2179 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2180 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2181 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2182 __ lea(rscratch1, __ constant_oop_address(o));
2183 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2184 }
2185
2186
2187 // This code replaces a call to arraycopy; no exception may
2188 // be thrown in this code, they must be thrown in the System.arraycopy
2189 // activation frame; we could save some checks if this would not be the case
2190 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2191 ciArrayKlass* default_type = op->expected_type();
2192 Register src = op->src()->as_register();
2193 Register dst = op->dst()->as_register();
2194 Register src_pos = op->src_pos()->as_register();
2195 Register dst_pos = op->dst_pos()->as_register();
2196 Register length = op->length()->as_register();
2197 Register tmp = op->tmp()->as_register();
2198
2199 CodeStub* stub = op->stub();
2200 int flags = op->flags();
2201 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2202 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2203
2204 // if we don't know anything, just go through the generic arraycopy
2205 if (default_type == nullptr // || basic_type == T_OBJECT
2206 ) {
2207 Label done;
2208 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2209
2210 // Save the arguments in case the generic arraycopy fails and we
2211 // have to fall back to the JNI stub
2212 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2213 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2214 __ str(src, Address(sp, 4*BytesPerWord));
2215
2216 address copyfunc_addr = StubRoutines::generic_arraycopy();
2217 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2218
2219 // The arguments are in java calling convention so we shift them
2220 // to C convention
2221 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2222 __ mov(c_rarg0, j_rarg0);
2223 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2224 __ mov(c_rarg1, j_rarg1);
2225 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2226 __ mov(c_rarg2, j_rarg2);
2227 assert_different_registers(c_rarg3, j_rarg4);
2228 __ mov(c_rarg3, j_rarg3);
2229 __ mov(c_rarg4, j_rarg4);
2230 #ifndef PRODUCT
2231 if (PrintC1Statistics) {
2232 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2233 }
2234 #endif
2235 __ far_call(RuntimeAddress(copyfunc_addr));
2236
2237 __ cbz(r0, *stub->continuation());
2238
2239 // Reload values from the stack so they are where the stub
2240 // expects them.
2241 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2242 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2243 __ ldr(src, Address(sp, 4*BytesPerWord));
2244
2245 // r0 is -1^K where K == partial copied count
2246 __ eonw(rscratch1, r0, zr);
2247 // adjust length down and src/end pos up by partial copied count
2248 __ subw(length, length, rscratch1);
2249 __ addw(src_pos, src_pos, rscratch1);
2250 __ addw(dst_pos, dst_pos, rscratch1);
2251 __ b(*stub->entry());
2252
2253 __ bind(*stub->continuation());
2254 return;
2255 }
2256
2257 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2258
2259 int elem_size = type2aelembytes(basic_type);
2260 int scale = exact_log2(elem_size);
2261
2262 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2263 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2264
2265 // test for null
2266 if (flags & LIR_OpArrayCopy::src_null_check) {
2267 __ cbz(src, *stub->entry());
2268 }
2269 if (flags & LIR_OpArrayCopy::dst_null_check) {
2270 __ cbz(dst, *stub->entry());
2271 }
2272
2273 // If the compiler was not able to prove that exact type of the source or the destination
2274 // of the arraycopy is an array type, check at runtime if the source or the destination is
2275 // an instance type.
2276 if (flags & LIR_OpArrayCopy::type_check) {
2277 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2278 __ load_klass(tmp, dst);
2279 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2280 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2281 __ br(Assembler::GE, *stub->entry());
2282 }
2283
2284 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2285 __ load_klass(tmp, src);
2286 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2287 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2288 __ br(Assembler::GE, *stub->entry());
2289 }
2290 }
2291
2292 // check if negative
2293 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2294 __ cmpw(src_pos, 0);
2295 __ br(Assembler::LT, *stub->entry());
2296 }
2297 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2298 __ cmpw(dst_pos, 0);
2299 __ br(Assembler::LT, *stub->entry());
2300 }
2301
2302 if (flags & LIR_OpArrayCopy::length_positive_check) {
2303 __ cmpw(length, 0);
2304 __ br(Assembler::LT, *stub->entry());
2305 }
2306
2307 if (flags & LIR_OpArrayCopy::src_range_check) {
2308 __ addw(tmp, src_pos, length);
2309 __ ldrw(rscratch1, src_length_addr);
2310 __ cmpw(tmp, rscratch1);
2311 __ br(Assembler::HI, *stub->entry());
2312 }
2313 if (flags & LIR_OpArrayCopy::dst_range_check) {
2314 __ addw(tmp, dst_pos, length);
2315 __ ldrw(rscratch1, dst_length_addr);
2316 __ cmpw(tmp, rscratch1);
2317 __ br(Assembler::HI, *stub->entry());
2318 }
2319
2320 if (flags & LIR_OpArrayCopy::type_check) {
2321 // We don't know the array types are compatible
2322 if (basic_type != T_OBJECT) {
2323 // Simple test for basic type arrays
2324 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2325 __ br(Assembler::NE, *stub->entry());
2326 } else {
2327 // For object arrays, if src is a sub class of dst then we can
2328 // safely do the copy.
2329 Label cont, slow;
2330
2331 #define PUSH(r1, r2) \
2332 stp(r1, r2, __ pre(sp, -2 * wordSize));
2333
2334 #define POP(r1, r2) \
2335 ldp(r1, r2, __ post(sp, 2 * wordSize));
2336
2337 __ PUSH(src, dst);
2338
2339 __ load_klass(src, src);
2340 __ load_klass(dst, dst);
2341
2342 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2343
2344 __ PUSH(src, dst);
2345 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
2346 __ POP(src, dst);
2347
2348 __ cbnz(src, cont);
2349
2350 __ bind(slow);
2351 __ POP(src, dst);
2352
2353 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2354 if (copyfunc_addr != nullptr) { // use stub if available
2355 // src is not a sub class of dst so we have to do a
2356 // per-element check.
2357
2358 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2359 if ((flags & mask) != mask) {
2360 // Check that at least both of them object arrays.
2361 assert(flags & mask, "one of the two should be known to be an object array");
2362
2363 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2364 __ load_klass(tmp, src);
2365 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2366 __ load_klass(tmp, dst);
2367 }
2368 int lh_offset = in_bytes(Klass::layout_helper_offset());
2369 Address klass_lh_addr(tmp, lh_offset);
2370 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2371 __ ldrw(rscratch1, klass_lh_addr);
2372 __ mov(rscratch2, objArray_lh);
2373 __ eorw(rscratch1, rscratch1, rscratch2);
2374 __ cbnzw(rscratch1, *stub->entry());
2375 }
2376
2377 // Spill because stubs can use any register they like and it's
2378 // easier to restore just those that we care about.
2379 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2380 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2381 __ str(src, Address(sp, 4*BytesPerWord));
2382
2383 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2384 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2385 assert_different_registers(c_rarg0, dst, dst_pos, length);
2386 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2387 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2388 assert_different_registers(c_rarg1, dst, length);
2389 __ uxtw(c_rarg2, length);
2390 assert_different_registers(c_rarg2, dst);
2391
2392 __ load_klass(c_rarg4, dst);
2393 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2394 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2395 __ far_call(RuntimeAddress(copyfunc_addr));
2396
2397 #ifndef PRODUCT
2398 if (PrintC1Statistics) {
2399 Label failed;
2400 __ cbnz(r0, failed);
2401 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2402 __ bind(failed);
2403 }
2404 #endif
2405
2406 __ cbz(r0, *stub->continuation());
2407
2408 #ifndef PRODUCT
2409 if (PrintC1Statistics) {
2410 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2411 }
2412 #endif
2413 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2414
2415 // Restore previously spilled arguments
2416 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2417 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2418 __ ldr(src, Address(sp, 4*BytesPerWord));
2419
2420 // return value is -1^K where K is partial copied count
2421 __ eonw(rscratch1, r0, zr);
2422 // adjust length down and src/end pos up by partial copied count
2423 __ subw(length, length, rscratch1);
2424 __ addw(src_pos, src_pos, rscratch1);
2425 __ addw(dst_pos, dst_pos, rscratch1);
2426 }
2427
2428 __ b(*stub->entry());
2429
2430 __ bind(cont);
2431 __ POP(src, dst);
2432 }
2433 }
2434
2435 #ifdef ASSERT
2436 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2437 // Sanity check the known type with the incoming class. For the
2438 // primitive case the types must match exactly with src.klass and
2439 // dst.klass each exactly matching the default type. For the
2440 // object array case, if no type check is needed then either the
2441 // dst type is exactly the expected type and the src type is a
2442 // subtype which we can't check or src is the same array as dst
2443 // but not necessarily exactly of type default_type.
2444 Label known_ok, halt;
2445 __ mov_metadata(tmp, default_type->constant_encoding());
2446
2447 if (basic_type != T_OBJECT) {
2448 __ cmp_klass(dst, tmp, rscratch1);
2449 __ br(Assembler::NE, halt);
2450 __ cmp_klass(src, tmp, rscratch1);
2451 __ br(Assembler::EQ, known_ok);
2452 } else {
2453 __ cmp_klass(dst, tmp, rscratch1);
2454 __ br(Assembler::EQ, known_ok);
2455 __ cmp(src, dst);
2456 __ br(Assembler::EQ, known_ok);
2457 }
2458 __ bind(halt);
2459 __ stop("incorrect type information in arraycopy");
2460 __ bind(known_ok);
2461 }
2462 #endif
2463
2464 #ifndef PRODUCT
2465 if (PrintC1Statistics) {
2466 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2467 }
2468 #endif
2469
2470 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2471 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2472 assert_different_registers(c_rarg0, dst, dst_pos, length);
2473 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2474 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2475 assert_different_registers(c_rarg1, dst, length);
2476 __ uxtw(c_rarg2, length);
2477 assert_different_registers(c_rarg2, dst);
2478
2479 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2480 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2481 const char *name;
2482 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2483
2484 CodeBlob *cb = CodeCache::find_blob(entry);
2485 if (cb) {
2486 __ far_call(RuntimeAddress(entry));
2487 } else {
2488 __ call_VM_leaf(entry, 3);
2489 }
2490
2491 if (stub != nullptr) {
2492 __ bind(*stub->continuation());
2493 }
2494 }
2495
2496
2497
2498
2499 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2500 Register obj = op->obj_opr()->as_register(); // may not be an oop
2501 Register hdr = op->hdr_opr()->as_register();
2502 Register lock = op->lock_opr()->as_register();
2503 Register temp = op->scratch_opr()->as_register();
2504 if (LockingMode == LM_MONITOR) {
2505 if (op->info() != nullptr) {
2506 add_debug_info_for_null_check_here(op->info());
2507 __ null_check(obj, -1);
2508 }
2509 __ b(*op->stub()->entry());
2510 } else if (op->code() == lir_lock) {
2511 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2512 // add debug info for NullPointerException only if one is possible
2513 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2514 if (op->info() != nullptr) {
2515 add_debug_info_for_null_check(null_check_offset, op->info());
2516 }
2517 // done
2518 } else if (op->code() == lir_unlock) {
2519 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2520 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2521 } else {
2522 Unimplemented();
2523 }
2524 __ bind(*op->stub()->continuation());
2525 }
2526
2527 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2528 Register obj = op->obj()->as_pointer_register();
2529 Register result = op->result_opr()->as_pointer_register();
2530
2531 CodeEmitInfo* info = op->info();
2532 if (info != nullptr) {
2533 add_debug_info_for_null_check_here(info);
2534 }
2535
2536 __ load_klass(result, obj);
2537 }
2538
2539 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2540 ciMethod* method = op->profiled_method();
2541 int bci = op->profiled_bci();
2542 ciMethod* callee = op->profiled_callee();
2543
2544 // Update counter for all call types
2545 ciMethodData* md = method->method_data_or_null();
2546 assert(md != nullptr, "Sanity");
2547 ciProfileData* data = md->bci_to_data(bci);
2548 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2549 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2550 Register mdo = op->mdo()->as_register();
2551 __ mov_metadata(mdo, md->constant_encoding());
2552 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2553 // Perform additional virtual call profiling for invokevirtual and
2554 // invokeinterface bytecodes
2555 if (op->should_profile_receiver_type()) {
2556 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2557 Register recv = op->recv()->as_register();
2558 assert_different_registers(mdo, recv);
2559 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2560 ciKlass* known_klass = op->known_holder();
2561 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2562 // We know the type that will be seen at this call site; we can
2563 // statically update the MethodData* rather than needing to do
2564 // dynamic tests on the receiver type
2565
2566 // NOTE: we should probably put a lock around this search to
2567 // avoid collisions by concurrent compilations
2568 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2569 uint i;
2570 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2571 ciKlass* receiver = vc_data->receiver(i);
2572 if (known_klass->equals(receiver)) {
2573 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2574 __ addptr(data_addr, DataLayout::counter_increment);
2575 return;
2576 }
2577 }
2578
2579 // Receiver type not found in profile data; select an empty slot
2580
2581 // Note that this is less efficient than it should be because it
2582 // always does a write to the receiver part of the
2583 // VirtualCallData rather than just the first time
2584 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2585 ciKlass* receiver = vc_data->receiver(i);
2586 if (receiver == nullptr) {
2587 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2588 Address recv_addr =
2589 __ form_address(rscratch2, mdo,
2590 md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)),
2591 LogBytesPerWord);
2592 __ str(rscratch1, recv_addr);
2593 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2594 __ addptr(data_addr, DataLayout::counter_increment);
2595 return;
2596 }
2597 }
2598 } else {
2599 __ load_klass(recv, recv);
2600 Label update_done;
2601 type_profile_helper(mdo, md, data, recv, &update_done);
2602 // Receiver did not match any saved receiver and there is no empty row for it.
2603 // Increment total counter to indicate polymorphic case.
2604 __ addptr(counter_addr, DataLayout::counter_increment);
2605
2606 __ bind(update_done);
2607 }
2608 } else {
2609 // Static call
2610 __ addptr(counter_addr, DataLayout::counter_increment);
2611 }
2612 }
2613
2614
2615 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2616 Unimplemented();
2617 }
2618
2619
2620 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2621 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2622 }
2623
2624 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2625 assert(op->crc()->is_single_cpu(), "crc must be register");
2626 assert(op->val()->is_single_cpu(), "byte value must be register");
2627 assert(op->result_opr()->is_single_cpu(), "result must be register");
2628 Register crc = op->crc()->as_register();
2629 Register val = op->val()->as_register();
2630 Register res = op->result_opr()->as_register();
2631
2632 assert_different_registers(val, crc, res);
2633 uint64_t offset;
2634 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2635 __ add(res, res, offset);
2636
2637 __ mvnw(crc, crc); // ~crc
2638 __ update_byte_crc32(crc, val, res);
2639 __ mvnw(res, crc); // ~crc
2640 }
2641
2642 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2643 COMMENT("emit_profile_type {");
2644 Register obj = op->obj()->as_register();
2645 Register tmp = op->tmp()->as_pointer_register();
2646 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2647 ciKlass* exact_klass = op->exact_klass();
2648 intptr_t current_klass = op->current_klass();
2649 bool not_null = op->not_null();
2650 bool no_conflict = op->no_conflict();
2651
2652 Label update, next, none;
2653
2654 bool do_null = !not_null;
2655 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2656 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2657
2658 assert(do_null || do_update, "why are we here?");
2659 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2660 assert(mdo_addr.base() != rscratch1, "wrong register");
2661
2662 __ verify_oop(obj);
2663
2664 if (tmp != obj) {
2665 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2666 __ mov(tmp, obj);
2667 } else {
2668 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2669 }
2670 if (do_null) {
2671 __ cbnz(tmp, update);
2672 if (!TypeEntries::was_null_seen(current_klass)) {
2673 __ ldr(rscratch2, mdo_addr);
2674 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2675 __ str(rscratch2, mdo_addr);
2676 }
2677 if (do_update) {
2678 #ifndef ASSERT
2679 __ b(next);
2680 }
2681 #else
2682 __ b(next);
2683 }
2684 } else {
2685 __ cbnz(tmp, update);
2686 __ stop("unexpected null obj");
2687 #endif
2688 }
2689
2690 __ bind(update);
2691
2692 if (do_update) {
2693 #ifdef ASSERT
2694 if (exact_klass != nullptr) {
2695 Label ok;
2696 __ load_klass(tmp, tmp);
2697 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2698 __ eor(rscratch1, tmp, rscratch1);
2699 __ cbz(rscratch1, ok);
2700 __ stop("exact klass and actual klass differ");
2701 __ bind(ok);
2702 }
2703 #endif
2704 if (!no_conflict) {
2705 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2706 if (exact_klass != nullptr) {
2707 __ mov_metadata(tmp, exact_klass->constant_encoding());
2708 } else {
2709 __ load_klass(tmp, tmp);
2710 }
2711
2712 __ ldr(rscratch2, mdo_addr);
2713 __ eor(tmp, tmp, rscratch2);
2714 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2715 // klass seen before, nothing to do. The unknown bit may have been
2716 // set already but no need to check.
2717 __ cbz(rscratch1, next);
2718
2719 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2720
2721 if (TypeEntries::is_type_none(current_klass)) {
2722 __ cbz(rscratch2, none);
2723 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2724 __ br(Assembler::EQ, none);
2725 // There is a chance that the checks above
2726 // fail if another thread has just set the
2727 // profiling to this obj's klass
2728 __ dmb(Assembler::ISHLD);
2729 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2730 __ ldr(rscratch2, mdo_addr);
2731 __ eor(tmp, tmp, rscratch2);
2732 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2733 __ cbz(rscratch1, next);
2734 }
2735 } else {
2736 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2737 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2738
2739 __ ldr(tmp, mdo_addr);
2740 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2741 }
2742
2743 // different than before. Cannot keep accurate profile.
2744 __ ldr(rscratch2, mdo_addr);
2745 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2746 __ str(rscratch2, mdo_addr);
2747
2748 if (TypeEntries::is_type_none(current_klass)) {
2749 __ b(next);
2750
2751 __ bind(none);
2752 // first time here. Set profile type.
2753 __ str(tmp, mdo_addr);
2754 #ifdef ASSERT
2755 __ andr(tmp, tmp, TypeEntries::type_mask);
2756 __ verify_klass_ptr(tmp);
2757 #endif
2758 }
2759 } else {
2760 // There's a single possible klass at this profile point
2761 assert(exact_klass != nullptr, "should be");
2762 if (TypeEntries::is_type_none(current_klass)) {
2763 __ mov_metadata(tmp, exact_klass->constant_encoding());
2764 __ ldr(rscratch2, mdo_addr);
2765 __ eor(tmp, tmp, rscratch2);
2766 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2767 __ cbz(rscratch1, next);
2768 #ifdef ASSERT
2769 {
2770 Label ok;
2771 __ ldr(rscratch1, mdo_addr);
2772 __ cbz(rscratch1, ok);
2773 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2774 __ br(Assembler::EQ, ok);
2775 // may have been set by another thread
2776 __ dmb(Assembler::ISHLD);
2777 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2778 __ ldr(rscratch2, mdo_addr);
2779 __ eor(rscratch2, rscratch1, rscratch2);
2780 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2781 __ cbz(rscratch2, ok);
2782
2783 __ stop("unexpected profiling mismatch");
2784 __ bind(ok);
2785 }
2786 #endif
2787 // first time here. Set profile type.
2788 __ str(tmp, mdo_addr);
2789 #ifdef ASSERT
2790 __ andr(tmp, tmp, TypeEntries::type_mask);
2791 __ verify_klass_ptr(tmp);
2792 #endif
2793 } else {
2794 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2795 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2796
2797 __ ldr(tmp, mdo_addr);
2798 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2799
2800 __ orr(tmp, tmp, TypeEntries::type_unknown);
2801 __ str(tmp, mdo_addr);
2802 // FIXME: Write barrier needed here?
2803 }
2804 }
2805
2806 __ bind(next);
2807 }
2808 COMMENT("} emit_profile_type");
2809 }
2810
2811
2812 void LIR_Assembler::align_backward_branch_target() {
2813 }
2814
2815
2816 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2817 // tmp must be unused
2818 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2819
2820 if (left->is_single_cpu()) {
2821 assert(dest->is_single_cpu(), "expect single result reg");
2822 __ negw(dest->as_register(), left->as_register());
2823 } else if (left->is_double_cpu()) {
2824 assert(dest->is_double_cpu(), "expect double result reg");
2825 __ neg(dest->as_register_lo(), left->as_register_lo());
2826 } else if (left->is_single_fpu()) {
2827 assert(dest->is_single_fpu(), "expect single float result reg");
2828 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2829 } else {
2830 assert(left->is_double_fpu(), "expect double float operand reg");
2831 assert(dest->is_double_fpu(), "expect double float result reg");
2832 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2833 }
2834 }
2835
2836
2837 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2838 if (patch_code != lir_patch_none) {
2839 deoptimize_trap(info);
2840 return;
2841 }
2842
2843 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2844 }
2845
2846
2847 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2848 assert(!tmp->is_valid(), "don't need temporary");
2849
2850 CodeBlob *cb = CodeCache::find_blob(dest);
2851 if (cb) {
2852 __ far_call(RuntimeAddress(dest));
2853 } else {
2854 __ mov(rscratch1, RuntimeAddress(dest));
2855 __ blr(rscratch1);
2856 }
2857
2858 if (info != nullptr) {
2859 add_call_info_here(info);
2860 }
2861 __ post_call_nop();
2862 }
2863
2864 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2865 if (dest->is_address() || src->is_address()) {
2866 move_op(src, dest, type, lir_patch_none, info,
2867 /*pop_fpu_stack*/false, /*wide*/false);
2868 } else {
2869 ShouldNotReachHere();
2870 }
2871 }
2872
2873 #ifdef ASSERT
2874 // emit run-time assertion
2875 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2876 assert(op->code() == lir_assert, "must be");
2877
2878 if (op->in_opr1()->is_valid()) {
2879 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2880 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2881 } else {
2882 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2883 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2884 }
2885
2886 Label ok;
2887 if (op->condition() != lir_cond_always) {
2888 Assembler::Condition acond = Assembler::AL;
2889 switch (op->condition()) {
2890 case lir_cond_equal: acond = Assembler::EQ; break;
2891 case lir_cond_notEqual: acond = Assembler::NE; break;
2892 case lir_cond_less: acond = Assembler::LT; break;
2893 case lir_cond_lessEqual: acond = Assembler::LE; break;
2894 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2895 case lir_cond_greater: acond = Assembler::GT; break;
2896 case lir_cond_belowEqual: acond = Assembler::LS; break;
2897 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2898 default: ShouldNotReachHere();
2899 }
2900 __ br(acond, ok);
2901 }
2902 if (op->halt()) {
2903 const char* str = __ code_string(op->msg());
2904 __ stop(str);
2905 } else {
2906 breakpoint();
2907 }
2908 __ bind(ok);
2909 }
2910 #endif
2911
2912 #ifndef PRODUCT
2913 #define COMMENT(x) do { __ block_comment(x); } while (0)
2914 #else
2915 #define COMMENT(x)
2916 #endif
2917
2918 void LIR_Assembler::membar() {
2919 COMMENT("membar");
2920 __ membar(MacroAssembler::AnyAny);
2921 }
2922
2923 void LIR_Assembler::membar_acquire() {
2924 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2925 }
2926
2927 void LIR_Assembler::membar_release() {
2928 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2929 }
2930
2931 void LIR_Assembler::membar_loadload() {
2932 __ membar(Assembler::LoadLoad);
2933 }
2934
2935 void LIR_Assembler::membar_storestore() {
2936 __ membar(MacroAssembler::StoreStore);
2937 }
2938
2939 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2940
2941 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2942
2943 void LIR_Assembler::on_spin_wait() {
2944 __ spin_wait();
2945 }
2946
2947 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2948 __ mov(result_reg->as_register(), rthread);
2949 }
2950
2951
2952 void LIR_Assembler::peephole(LIR_List *lir) {
2953 #if 0
2954 if (tableswitch_count >= max_tableswitches)
2955 return;
2956
2957 /*
2958 This finite-state automaton recognizes sequences of compare-and-
2959 branch instructions. We will turn them into a tableswitch. You
2960 could argue that C1 really shouldn't be doing this sort of
2961 optimization, but without it the code is really horrible.
2962 */
2963
2964 enum { start_s, cmp1_s, beq_s, cmp_s } state;
2965 int first_key, last_key = -2147483648;
2966 int next_key = 0;
2967 int start_insn = -1;
2968 int last_insn = -1;
2969 Register reg = noreg;
2970 LIR_Opr reg_opr;
2971 state = start_s;
2972
2973 LIR_OpList* inst = lir->instructions_list();
2974 for (int i = 0; i < inst->length(); i++) {
2975 LIR_Op* op = inst->at(i);
2976 switch (state) {
2977 case start_s:
2978 first_key = -1;
2979 start_insn = i;
2980 switch (op->code()) {
2981 case lir_cmp:
2982 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2983 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2984 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2985 && opr2->is_constant()
2986 && opr2->type() == T_INT) {
2987 reg_opr = opr1;
2988 reg = opr1->as_register();
2989 first_key = opr2->as_constant_ptr()->as_jint();
2990 next_key = first_key + 1;
2991 state = cmp_s;
2992 goto next_state;
2993 }
2994 break;
2995 }
2996 break;
2997 case cmp_s:
2998 switch (op->code()) {
2999 case lir_branch:
3000 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3001 state = beq_s;
3002 last_insn = i;
3003 goto next_state;
3004 }
3005 }
3006 state = start_s;
3007 break;
3008 case beq_s:
3009 switch (op->code()) {
3010 case lir_cmp: {
3011 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3012 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3013 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3014 && opr1->as_register() == reg
3015 && opr2->is_constant()
3016 && opr2->type() == T_INT
3017 && opr2->as_constant_ptr()->as_jint() == next_key) {
3018 last_key = next_key;
3019 next_key++;
3020 state = cmp_s;
3021 goto next_state;
3022 }
3023 }
3024 }
3025 last_key = next_key;
3026 state = start_s;
3027 break;
3028 default:
3029 assert(false, "impossible state");
3030 }
3031 if (state == start_s) {
3032 if (first_key < last_key - 5L && reg != noreg) {
3033 {
3034 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3035 // reg->encoding(),
3036 // start_insn, first_key, last_key);
3037 // for (int i = 0; i < inst->length(); i++) {
3038 // inst->at(i)->print();
3039 // tty->print("\n");
3040 // }
3041 // tty->print("\n");
3042 }
3043
3044 struct tableswitch *sw = &switches[tableswitch_count];
3045 sw->_insn_index = start_insn, sw->_first_key = first_key,
3046 sw->_last_key = last_key, sw->_reg = reg;
3047 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3048 {
3049 // Insert the new table of branches
3050 int offset = last_insn;
3051 for (int n = first_key; n < last_key; n++) {
3052 inst->insert_before
3053 (last_insn + 1,
3054 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3055 inst->at(offset)->as_OpBranch()->label()));
3056 offset -= 2, i++;
3057 }
3058 }
3059 // Delete all the old compare-and-branch instructions
3060 for (int n = first_key; n < last_key; n++) {
3061 inst->remove_at(start_insn);
3062 inst->remove_at(start_insn);
3063 }
3064 // Insert the tableswitch instruction
3065 inst->insert_before(start_insn,
3066 new LIR_Op2(lir_cmp, lir_cond_always,
3067 LIR_OprFact::intConst(tableswitch_count),
3068 reg_opr));
3069 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3070 tableswitch_count++;
3071 }
3072 reg = noreg;
3073 last_key = -2147483648;
3074 }
3075 next_state:
3076 ;
3077 }
3078 #endif
3079 }
3080
3081 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3082 Address addr = as_Address(src->as_address_ptr());
3083 BasicType type = src->type();
3084 bool is_oop = is_reference_type(type);
3085
3086 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3087 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3088
3089 switch(type) {
3090 case T_INT:
3091 xchg = &MacroAssembler::atomic_xchgalw;
3092 add = &MacroAssembler::atomic_addalw;
3093 break;
3094 case T_LONG:
3095 xchg = &MacroAssembler::atomic_xchgal;
3096 add = &MacroAssembler::atomic_addal;
3097 break;
3098 case T_OBJECT:
3099 case T_ARRAY:
3100 if (UseCompressedOops) {
3101 xchg = &MacroAssembler::atomic_xchgalw;
3102 add = &MacroAssembler::atomic_addalw;
3103 } else {
3104 xchg = &MacroAssembler::atomic_xchgal;
3105 add = &MacroAssembler::atomic_addal;
3106 }
3107 break;
3108 default:
3109 ShouldNotReachHere();
3110 xchg = &MacroAssembler::atomic_xchgal;
3111 add = &MacroAssembler::atomic_addal; // unreachable
3112 }
3113
3114 switch (code) {
3115 case lir_xadd:
3116 {
3117 RegisterOrConstant inc;
3118 Register tmp = as_reg(tmp_op);
3119 Register dst = as_reg(dest);
3120 if (data->is_constant()) {
3121 inc = RegisterOrConstant(as_long(data));
3122 assert_different_registers(dst, addr.base(), tmp,
3123 rscratch1, rscratch2);
3124 } else {
3125 inc = RegisterOrConstant(as_reg(data));
3126 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3127 rscratch1, rscratch2);
3128 }
3129 __ lea(tmp, addr);
3130 (_masm->*add)(dst, inc, tmp);
3131 break;
3132 }
3133 case lir_xchg:
3134 {
3135 Register tmp = tmp_op->as_register();
3136 Register obj = as_reg(data);
3137 Register dst = as_reg(dest);
3138 if (is_oop && UseCompressedOops) {
3139 __ encode_heap_oop(rscratch2, obj);
3140 obj = rscratch2;
3141 }
3142 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3143 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3144 __ lea(tmp, addr);
3145 (_masm->*xchg)(dst, obj, tmp);
3146 if (is_oop && UseCompressedOops) {
3147 __ decode_heap_oop(dst);
3148 }
3149 }
3150 break;
3151 default:
3152 ShouldNotReachHere();
3153 }
3154 __ membar(__ AnyAny);
3155 }
3156
3157 #undef __