1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "asm/assembler.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "code/aotCodeCache.hpp"
37 #include "code/compiledIC.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/gc_globals.hpp"
40 #include "nativeInst_aarch64.hpp"
41 #include "oops/objArrayKlass.hpp"
42 #include "runtime/frame.inline.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "runtime/threadIdentifier.hpp"
46 #include "utilities/powerOfTwo.hpp"
47 #include "vmreg_aarch64.inline.hpp"
48
49
50 #ifndef PRODUCT
51 #define COMMENT(x) do { __ block_comment(x); } while (0)
52 #else
53 #define COMMENT(x)
54 #endif
55
56 NEEDS_CLEANUP // remove this definitions ?
57 const Register SYNC_header = r0; // synchronization header
58 const Register SHIFT_count = r0; // where count for shift operations must be
59
60 #define __ _masm->
61
62
63 static void select_different_registers(Register preserve,
64 Register extra,
65 Register &tmp1,
66 Register &tmp2) {
67 if (tmp1 == preserve) {
68 assert_different_registers(tmp1, tmp2, extra);
69 tmp1 = extra;
70 } else if (tmp2 == preserve) {
71 assert_different_registers(tmp1, tmp2, extra);
72 tmp2 = extra;
73 }
74 assert_different_registers(preserve, tmp1, tmp2);
75 }
76
77
78
79 static void select_different_registers(Register preserve,
80 Register extra,
81 Register &tmp1,
82 Register &tmp2,
83 Register &tmp3) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, tmp3, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, tmp3, extra);
89 tmp2 = extra;
90 } else if (tmp3 == preserve) {
91 assert_different_registers(tmp1, tmp2, tmp3, extra);
92 tmp3 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2, tmp3);
95 }
96
97
98 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
99
100
101 LIR_Opr LIR_Assembler::receiverOpr() {
102 return FrameMap::receiver_opr;
103 }
104
105 LIR_Opr LIR_Assembler::osrBufferPointer() {
106 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
107 }
108
109 //--------------fpu register translations-----------------------
110
111
112 address LIR_Assembler::float_constant(float f) {
113 address const_addr = __ float_constant(f);
114 if (const_addr == nullptr) {
115 bailout("const section overflow");
116 return __ code()->consts()->start();
117 } else {
118 return const_addr;
119 }
120 }
121
122
123 address LIR_Assembler::double_constant(double d) {
124 address const_addr = __ double_constant(d);
125 if (const_addr == nullptr) {
126 bailout("const section overflow");
127 return __ code()->consts()->start();
128 } else {
129 return const_addr;
130 }
131 }
132
133 address LIR_Assembler::int_constant(jlong n) {
134 address const_addr = __ long_constant(n);
135 if (const_addr == nullptr) {
136 bailout("const section overflow");
137 return __ code()->consts()->start();
138 } else {
139 return const_addr;
140 }
141 }
142
143 void LIR_Assembler::breakpoint() { Unimplemented(); }
144
145 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
146
147 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
148
149 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
150 //-------------------------------------------
151
152 static Register as_reg(LIR_Opr op) {
153 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
154 }
155
156 static jlong as_long(LIR_Opr data) {
157 jlong result;
158 switch (data->type()) {
159 case T_INT:
160 result = (data->as_jint());
161 break;
162 case T_LONG:
163 result = (data->as_jlong());
164 break;
165 default:
166 ShouldNotReachHere();
167 result = 0; // unreachable
168 }
169 return result;
170 }
171
172 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
173 Register base = addr->base()->as_pointer_register();
174 LIR_Opr opr = addr->index();
175 if (opr->is_cpu_register()) {
176 Register index;
177 if (opr->is_single_cpu())
178 index = opr->as_register();
179 else
180 index = opr->as_register_lo();
181 assert(addr->disp() == 0, "must be");
182 switch(opr->type()) {
183 case T_INT:
184 return Address(base, index, Address::sxtw(addr->scale()));
185 case T_LONG:
186 return Address(base, index, Address::lsl(addr->scale()));
187 default:
188 ShouldNotReachHere();
189 }
190 } else {
191 assert(addr->scale() == 0,
192 "expected for immediate operand, was: %d", addr->scale());
193 ptrdiff_t offset = ptrdiff_t(addr->disp());
194 // NOTE: Does not handle any 16 byte vector access.
195 const uint type_size = type2aelembytes(addr->type(), true);
196 return __ legitimize_address(Address(base, offset), type_size, tmp);
197 }
198 return Address();
199 }
200
201 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
202 ShouldNotReachHere();
203 return Address();
204 }
205
206 Address LIR_Assembler::as_Address(LIR_Address* addr) {
207 return as_Address(addr, rscratch1);
208 }
209
210 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
211 return as_Address(addr, rscratch1); // Ouch
212 // FIXME: This needs to be much more clever. See x86.
213 }
214
215 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
216 // not encodable as a base + (immediate) offset, generate an explicit address
217 // calculation to hold the address in a temporary register.
218 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
219 precond(size == 4 || size == 8);
220 Address addr = frame_map()->address_for_slot(index, adjust);
221 precond(addr.getMode() == Address::base_plus_offset);
222 precond(addr.base() == sp);
223 precond(addr.offset() > 0);
224 uint mask = size - 1;
225 assert((addr.offset() & mask) == 0, "scaled offsets only");
226 return __ legitimize_address(addr, size, tmp);
227 }
228
229 void LIR_Assembler::osr_entry() {
230 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
231 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
232 ValueStack* entry_state = osr_entry->state();
233 int number_of_locks = entry_state->locks_size();
234
235 // we jump here if osr happens with the interpreter
236 // state set up to continue at the beginning of the
237 // loop that triggered osr - in particular, we have
238 // the following registers setup:
239 //
240 // r2: osr buffer
241 //
242
243 // build frame
244 ciMethod* m = compilation()->method();
245 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
246
247 // OSR buffer is
248 //
249 // locals[nlocals-1..0]
250 // monitors[0..number_of_locks]
251 //
252 // locals is a direct copy of the interpreter frame so in the osr buffer
253 // so first slot in the local array is the last local from the interpreter
254 // and last slot is local[0] (receiver) from the interpreter
255 //
256 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
257 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
258 // in the interpreter frame (the method lock if a sync method)
259
260 // Initialize monitors in the compiled activation.
261 // r2: pointer to osr buffer
262 //
263 // All other registers are dead at this point and the locals will be
264 // copied into place by code emitted in the IR.
265
266 Register OSR_buf = osrBufferPointer()->as_pointer_register();
267 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
268 int monitor_offset = BytesPerWord * method()->max_locals() +
269 (2 * BytesPerWord) * (number_of_locks - 1);
270 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
271 // the OSR buffer using 2 word entries: first the lock and then
272 // the oop.
273 for (int i = 0; i < number_of_locks; i++) {
274 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
275 #ifdef ASSERT
276 // verify the interpreter's monitor has a non-null object
277 {
278 Label L;
279 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
280 __ cbnz(rscratch1, L);
281 __ stop("locked object is null");
282 __ bind(L);
283 }
284 #endif
285 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
286 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
287 __ str(r19, frame_map()->address_for_monitor_lock(i));
288 __ str(r20, frame_map()->address_for_monitor_object(i));
289 }
290 }
291 }
292
293
294 // inline cache check; done before the frame is built.
295 int LIR_Assembler::check_icache() {
296 return __ ic_check(CodeEntryAlignment);
297 }
298
299 void LIR_Assembler::clinit_barrier(ciMethod* method) {
300 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
301 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
302
303 Label L_skip_barrier;
304
305 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
306 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
307 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
308 __ bind(L_skip_barrier);
309 }
310
311 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
312 if (o == nullptr) {
313 __ mov(reg, zr);
314 } else {
315 __ movoop(reg, o);
316 }
317 }
318
319 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
320 address target = nullptr;
321 relocInfo::relocType reloc_type = relocInfo::none;
322
323 switch (patching_id(info)) {
324 case PatchingStub::access_field_id:
325 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
326 reloc_type = relocInfo::section_word_type;
327 break;
328 case PatchingStub::load_klass_id:
329 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
330 reloc_type = relocInfo::metadata_type;
331 break;
332 case PatchingStub::load_mirror_id:
333 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
334 reloc_type = relocInfo::oop_type;
335 break;
336 case PatchingStub::load_appendix_id:
337 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
338 reloc_type = relocInfo::oop_type;
339 break;
340 default: ShouldNotReachHere();
341 }
342
343 __ far_call(RuntimeAddress(target));
344 add_call_info_here(info);
345 }
346
347 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
348 deoptimize_trap(info);
349 }
350
351
352 // This specifies the rsp decrement needed to build the frame
353 int LIR_Assembler::initial_frame_size_in_bytes() const {
354 // if rounding, must let FrameMap know!
355
356 return in_bytes(frame_map()->framesize_in_bytes());
357 }
358
359
360 int LIR_Assembler::emit_exception_handler() {
361 // generate code for exception handler
362 address handler_base = __ start_a_stub(exception_handler_size());
363 if (handler_base == nullptr) {
364 // not enough space left for the handler
365 bailout("exception handler overflow");
366 return -1;
367 }
368
369 int offset = code_offset();
370
371 // the exception oop and pc are in r0, and r3
372 // no other registers need to be preserved, so invalidate them
373 __ invalidate_registers(false, true, true, false, true, true);
374
375 // check that there is really an exception
376 __ verify_not_null_oop(r0);
377
378 // search an exception handler (r0: exception oop, r3: throwing pc)
379 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id)));
380 __ should_not_reach_here();
381 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
382 __ end_a_stub();
383
384 return offset;
385 }
386
387
388 // Emit the code to remove the frame from the stack in the exception
389 // unwind path.
390 int LIR_Assembler::emit_unwind_handler() {
391 #ifndef PRODUCT
392 if (CommentedAssembly) {
393 _masm->block_comment("Unwind handler");
394 }
395 #endif
396
397 int offset = code_offset();
398
399 // Fetch the exception from TLS and clear out exception related thread state
400 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
401 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
402 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
403
404 __ bind(_unwind_handler_entry);
405 __ verify_not_null_oop(r0);
406 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
407 __ mov(r19, r0); // Preserve the exception
408 }
409
410 // Perform needed unlocking
411 MonitorExitStub* stub = nullptr;
412 if (method()->is_synchronized()) {
413 monitor_address(0, FrameMap::r0_opr);
414 stub = new MonitorExitStub(FrameMap::r0_opr, 0);
415 __ unlock_object(r5, r4, r0, r6, *stub->entry());
416 __ bind(*stub->continuation());
417 }
418
419 if (compilation()->env()->dtrace_method_probes()) {
420 __ mov(c_rarg0, rthread);
421 __ mov_metadata(c_rarg1, method()->constant_encoding());
422 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
423 }
424
425 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
426 __ mov(r0, r19); // Restore the exception
427 }
428
429 // remove the activation and dispatch to the unwind handler
430 __ block_comment("remove_frame and dispatch to the unwind handler");
431 __ remove_frame(initial_frame_size_in_bytes());
432 __ far_jump(RuntimeAddress(Runtime1::entry_for(StubId::c1_unwind_exception_id)));
433
434 // Emit the slow path assembly
435 if (stub != nullptr) {
436 stub->emit_code(this);
437 }
438
439 return offset;
440 }
441
442
443 int LIR_Assembler::emit_deopt_handler() {
444 // generate code for exception handler
445 address handler_base = __ start_a_stub(deopt_handler_size());
446 if (handler_base == nullptr) {
447 // not enough space left for the handler
448 bailout("deopt handler overflow");
449 return -1;
450 }
451
452 int offset = code_offset();
453
454 Label start;
455 __ bind(start);
456
457 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
458
459 int entry_offset = __ offset();
460 __ b(start);
461
462 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
463 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
464 "out of bounds read in post-call NOP check");
465 __ end_a_stub();
466
467 return entry_offset;
468 }
469
470 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
471 _masm->code_section()->relocate(adr, relocInfo::poll_type);
472 int pc_offset = code_offset();
473 flush_debug_info(pc_offset);
474 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
475 if (info->exception_handlers() != nullptr) {
476 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
477 }
478 }
479
480 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
481 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
482
483 // Pop the stack before the safepoint code
484 __ remove_frame(initial_frame_size_in_bytes());
485
486 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
487 __ reserved_stack_check();
488 }
489
490 code_stub->set_safepoint_offset(__ offset());
491 __ relocate(relocInfo::poll_return_type);
492 __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
493 __ ret(lr);
494 }
495
496 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
497 guarantee(info != nullptr, "Shouldn't be null");
498 __ get_polling_page(rscratch1, relocInfo::poll_type);
499 add_debug_info_for_branch(info); // This isn't just debug info:
500 // it's the oop map
501 __ read_polling_page(rscratch1, relocInfo::poll_type);
502 return __ offset();
503 }
504
505
506 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
507 if (from_reg == r31_sp)
508 from_reg = sp;
509 if (to_reg == r31_sp)
510 to_reg = sp;
511 __ mov(to_reg, from_reg);
512 }
513
514 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
515
516
517 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
518 assert(src->is_constant(), "should not call otherwise");
519 assert(dest->is_register(), "should not call otherwise");
520 LIR_Const* c = src->as_constant_ptr();
521
522 switch (c->type()) {
523 case T_INT: {
524 assert(patch_code == lir_patch_none, "no patching handled here");
525 __ movw(dest->as_register(), c->as_jint());
526 break;
527 }
528
529 case T_ADDRESS: {
530 assert(patch_code == lir_patch_none, "no patching handled here");
531 __ mov(dest->as_register(), c->as_jint());
532 break;
533 }
534
535 case T_LONG: {
536 assert(patch_code == lir_patch_none, "no patching handled here");
537 #if INCLUDE_CDS
538 if (AOTCodeCache::is_on_for_dump()) {
539 address b = c->as_pointer();
540 if (b == (address)ThreadIdentifier::unsafe_offset()) {
541 __ lea(dest->as_register_lo(), ExternalAddress(b));
542 break;
543 }
544 if (AOTRuntimeConstants::contains(b)) {
545 __ load_aotrc_address(dest->as_register_lo(), b);
546 break;
547 }
548 }
549 #endif
550 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
551 break;
552 }
553
554 case T_OBJECT: {
555 if (patch_code == lir_patch_none) {
556 jobject2reg(c->as_jobject(), dest->as_register());
557 } else {
558 jobject2reg_with_patching(dest->as_register(), info);
559 }
560 break;
561 }
562
563 case T_METADATA: {
564 if (patch_code != lir_patch_none) {
565 klass2reg_with_patching(dest->as_register(), info);
566 } else {
567 __ mov_metadata(dest->as_register(), c->as_metadata());
568 }
569 break;
570 }
571
572 case T_FLOAT: {
573 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
574 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
575 } else {
576 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
577 __ ldrs(dest->as_float_reg(), Address(rscratch1));
578 }
579 break;
580 }
581
582 case T_DOUBLE: {
583 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
584 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
585 } else {
586 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
587 __ ldrd(dest->as_double_reg(), Address(rscratch1));
588 }
589 break;
590 }
591
592 default:
593 ShouldNotReachHere();
594 }
595 }
596
597 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
598 LIR_Const* c = src->as_constant_ptr();
599 switch (c->type()) {
600 case T_OBJECT:
601 {
602 if (! c->as_jobject())
603 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
604 else {
605 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
606 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
607 }
608 }
609 break;
610 case T_ADDRESS:
611 {
612 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
613 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
614 }
615 case T_INT:
616 case T_FLOAT:
617 {
618 Register reg = zr;
619 if (c->as_jint_bits() == 0)
620 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
621 else {
622 __ movw(rscratch1, c->as_jint_bits());
623 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
624 }
625 }
626 break;
627 case T_LONG:
628 case T_DOUBLE:
629 {
630 Register reg = zr;
631 if (c->as_jlong_bits() == 0)
632 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
633 lo_word_offset_in_bytes));
634 else {
635 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
636 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
637 lo_word_offset_in_bytes));
638 }
639 }
640 break;
641 default:
642 ShouldNotReachHere();
643 }
644 }
645
646 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
647 assert(src->is_constant(), "should not call otherwise");
648 LIR_Const* c = src->as_constant_ptr();
649 LIR_Address* to_addr = dest->as_address_ptr();
650
651 void (Assembler::* insn)(Register Rt, const Address &adr);
652
653 switch (type) {
654 case T_ADDRESS:
655 assert(c->as_jint() == 0, "should be");
656 insn = &Assembler::str;
657 break;
658 case T_LONG:
659 assert(c->as_jlong() == 0, "should be");
660 insn = &Assembler::str;
661 break;
662 case T_INT:
663 assert(c->as_jint() == 0, "should be");
664 insn = &Assembler::strw;
665 break;
666 case T_OBJECT:
667 case T_ARRAY:
668 assert(c->as_jobject() == nullptr, "should be");
669 if (UseCompressedOops && !wide) {
670 insn = &Assembler::strw;
671 } else {
672 insn = &Assembler::str;
673 }
674 break;
675 case T_CHAR:
676 case T_SHORT:
677 assert(c->as_jint() == 0, "should be");
678 insn = &Assembler::strh;
679 break;
680 case T_BOOLEAN:
681 case T_BYTE:
682 assert(c->as_jint() == 0, "should be");
683 insn = &Assembler::strb;
684 break;
685 default:
686 ShouldNotReachHere();
687 insn = &Assembler::str; // unreachable
688 }
689
690 if (info) add_debug_info_for_null_check_here(info);
691 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
692 }
693
694 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
695 assert(src->is_register(), "should not call otherwise");
696 assert(dest->is_register(), "should not call otherwise");
697
698 // move between cpu-registers
699 if (dest->is_single_cpu()) {
700 if (src->type() == T_LONG) {
701 // Can do LONG -> OBJECT
702 move_regs(src->as_register_lo(), dest->as_register());
703 return;
704 }
705 assert(src->is_single_cpu(), "must match");
706 if (src->type() == T_OBJECT) {
707 __ verify_oop(src->as_register());
708 }
709 move_regs(src->as_register(), dest->as_register());
710
711 } else if (dest->is_double_cpu()) {
712 if (is_reference_type(src->type())) {
713 // Surprising to me but we can see move of a long to t_object
714 __ verify_oop(src->as_register());
715 move_regs(src->as_register(), dest->as_register_lo());
716 return;
717 }
718 assert(src->is_double_cpu(), "must match");
719 Register f_lo = src->as_register_lo();
720 Register f_hi = src->as_register_hi();
721 Register t_lo = dest->as_register_lo();
722 Register t_hi = dest->as_register_hi();
723 assert(f_hi == f_lo, "must be same");
724 assert(t_hi == t_lo, "must be same");
725 move_regs(f_lo, t_lo);
726
727 } else if (dest->is_single_fpu()) {
728 __ fmovs(dest->as_float_reg(), src->as_float_reg());
729
730 } else if (dest->is_double_fpu()) {
731 __ fmovd(dest->as_double_reg(), src->as_double_reg());
732
733 } else {
734 ShouldNotReachHere();
735 }
736 }
737
738 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
739 precond(src->is_register() && dest->is_stack());
740
741 uint const c_sz32 = sizeof(uint32_t);
742 uint const c_sz64 = sizeof(uint64_t);
743
744 if (src->is_single_cpu()) {
745 int index = dest->single_stack_ix();
746 if (is_reference_type(type)) {
747 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
748 __ verify_oop(src->as_register());
749 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
750 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
751 } else {
752 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
753 }
754
755 } else if (src->is_double_cpu()) {
756 int index = dest->double_stack_ix();
757 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
758 __ str(src->as_register_lo(), dest_addr_LO);
759
760 } else if (src->is_single_fpu()) {
761 int index = dest->single_stack_ix();
762 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
763
764 } else if (src->is_double_fpu()) {
765 int index = dest->double_stack_ix();
766 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
767
768 } else {
769 ShouldNotReachHere();
770 }
771 }
772
773
774 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
775 LIR_Address* to_addr = dest->as_address_ptr();
776 PatchingStub* patch = nullptr;
777 Register compressed_src = rscratch1;
778
779 if (patch_code != lir_patch_none) {
780 deoptimize_trap(info);
781 return;
782 }
783
784 if (is_reference_type(type)) {
785 __ verify_oop(src->as_register());
786
787 if (UseCompressedOops && !wide) {
788 __ encode_heap_oop(compressed_src, src->as_register());
789 } else {
790 compressed_src = src->as_register();
791 }
792 }
793
794 int null_check_here = code_offset();
795 switch (type) {
796 case T_FLOAT: {
797 __ strs(src->as_float_reg(), as_Address(to_addr));
798 break;
799 }
800
801 case T_DOUBLE: {
802 __ strd(src->as_double_reg(), as_Address(to_addr));
803 break;
804 }
805
806 case T_ARRAY: // fall through
807 case T_OBJECT: // fall through
808 if (UseCompressedOops && !wide) {
809 __ strw(compressed_src, as_Address(to_addr, rscratch2));
810 } else {
811 __ str(compressed_src, as_Address(to_addr));
812 }
813 break;
814 case T_METADATA:
815 // We get here to store a method pointer to the stack to pass to
816 // a dtrace runtime call. This can't work on 64 bit with
817 // compressed klass ptrs: T_METADATA can be a compressed klass
818 // ptr or a 64 bit method pointer.
819 ShouldNotReachHere();
820 __ str(src->as_register(), as_Address(to_addr));
821 break;
822 case T_ADDRESS:
823 __ str(src->as_register(), as_Address(to_addr));
824 break;
825 case T_INT:
826 __ strw(src->as_register(), as_Address(to_addr));
827 break;
828
829 case T_LONG: {
830 __ str(src->as_register_lo(), as_Address_lo(to_addr));
831 break;
832 }
833
834 case T_BYTE: // fall through
835 case T_BOOLEAN: {
836 __ strb(src->as_register(), as_Address(to_addr));
837 break;
838 }
839
840 case T_CHAR: // fall through
841 case T_SHORT:
842 __ strh(src->as_register(), as_Address(to_addr));
843 break;
844
845 default:
846 ShouldNotReachHere();
847 }
848 if (info != nullptr) {
849 add_debug_info_for_null_check(null_check_here, info);
850 }
851 }
852
853
854 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
855 precond(src->is_stack() && dest->is_register());
856
857 uint const c_sz32 = sizeof(uint32_t);
858 uint const c_sz64 = sizeof(uint64_t);
859
860 if (dest->is_single_cpu()) {
861 int index = src->single_stack_ix();
862 if (is_reference_type(type)) {
863 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
864 __ verify_oop(dest->as_register());
865 } else if (type == T_METADATA || type == T_ADDRESS) {
866 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
867 } else {
868 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
869 }
870
871 } else if (dest->is_double_cpu()) {
872 int index = src->double_stack_ix();
873 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
874 __ ldr(dest->as_register_lo(), src_addr_LO);
875
876 } else if (dest->is_single_fpu()) {
877 int index = src->single_stack_ix();
878 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
879
880 } else if (dest->is_double_fpu()) {
881 int index = src->double_stack_ix();
882 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
883
884 } else {
885 ShouldNotReachHere();
886 }
887 }
888
889
890 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
891 address target = nullptr;
892 relocInfo::relocType reloc_type = relocInfo::none;
893
894 switch (patching_id(info)) {
895 case PatchingStub::access_field_id:
896 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
897 reloc_type = relocInfo::section_word_type;
898 break;
899 case PatchingStub::load_klass_id:
900 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
901 reloc_type = relocInfo::metadata_type;
902 break;
903 case PatchingStub::load_mirror_id:
904 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
905 reloc_type = relocInfo::oop_type;
906 break;
907 case PatchingStub::load_appendix_id:
908 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
909 reloc_type = relocInfo::oop_type;
910 break;
911 default: ShouldNotReachHere();
912 }
913
914 __ far_call(RuntimeAddress(target));
915 add_call_info_here(info);
916 }
917
918 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
919
920 LIR_Opr temp;
921 if (type == T_LONG || type == T_DOUBLE)
922 temp = FrameMap::rscratch1_long_opr;
923 else
924 temp = FrameMap::rscratch1_opr;
925
926 stack2reg(src, temp, src->type());
927 reg2stack(temp, dest, dest->type());
928 }
929
930
931 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
932 LIR_Address* addr = src->as_address_ptr();
933 LIR_Address* from_addr = src->as_address_ptr();
934
935 if (addr->base()->type() == T_OBJECT) {
936 __ verify_oop(addr->base()->as_pointer_register());
937 }
938
939 if (patch_code != lir_patch_none) {
940 deoptimize_trap(info);
941 return;
942 }
943
944 if (info != nullptr) {
945 add_debug_info_for_null_check_here(info);
946 }
947 int null_check_here = code_offset();
948 switch (type) {
949 case T_FLOAT: {
950 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
951 break;
952 }
953
954 case T_DOUBLE: {
955 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
956 break;
957 }
958
959 case T_ARRAY: // fall through
960 case T_OBJECT: // fall through
961 if (UseCompressedOops && !wide) {
962 __ ldrw(dest->as_register(), as_Address(from_addr));
963 } else {
964 __ ldr(dest->as_register(), as_Address(from_addr));
965 }
966 break;
967 case T_METADATA:
968 // We get here to store a method pointer to the stack to pass to
969 // a dtrace runtime call. This can't work on 64 bit with
970 // compressed klass ptrs: T_METADATA can be a compressed klass
971 // ptr or a 64 bit method pointer.
972 ShouldNotReachHere();
973 __ ldr(dest->as_register(), as_Address(from_addr));
974 break;
975 case T_ADDRESS:
976 __ ldr(dest->as_register(), as_Address(from_addr));
977 break;
978 case T_INT:
979 __ ldrw(dest->as_register(), as_Address(from_addr));
980 break;
981
982 case T_LONG: {
983 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
984 break;
985 }
986
987 case T_BYTE:
988 __ ldrsb(dest->as_register(), as_Address(from_addr));
989 break;
990 case T_BOOLEAN: {
991 __ ldrb(dest->as_register(), as_Address(from_addr));
992 break;
993 }
994
995 case T_CHAR:
996 __ ldrh(dest->as_register(), as_Address(from_addr));
997 break;
998 case T_SHORT:
999 __ ldrsh(dest->as_register(), as_Address(from_addr));
1000 break;
1001
1002 default:
1003 ShouldNotReachHere();
1004 }
1005
1006 if (is_reference_type(type)) {
1007 if (UseCompressedOops && !wide) {
1008 __ decode_heap_oop(dest->as_register());
1009 }
1010
1011 __ verify_oop(dest->as_register());
1012 }
1013 }
1014
1015
1016 int LIR_Assembler::array_element_size(BasicType type) const {
1017 int elem_size = type2aelembytes(type);
1018 return exact_log2(elem_size);
1019 }
1020
1021
1022 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1023 switch (op->code()) {
1024 case lir_idiv:
1025 case lir_irem:
1026 arithmetic_idiv(op->code(),
1027 op->in_opr1(),
1028 op->in_opr2(),
1029 op->in_opr3(),
1030 op->result_opr(),
1031 op->info());
1032 break;
1033 case lir_fmad:
1034 __ fmaddd(op->result_opr()->as_double_reg(),
1035 op->in_opr1()->as_double_reg(),
1036 op->in_opr2()->as_double_reg(),
1037 op->in_opr3()->as_double_reg());
1038 break;
1039 case lir_fmaf:
1040 __ fmadds(op->result_opr()->as_float_reg(),
1041 op->in_opr1()->as_float_reg(),
1042 op->in_opr2()->as_float_reg(),
1043 op->in_opr3()->as_float_reg());
1044 break;
1045 default: ShouldNotReachHere(); break;
1046 }
1047 }
1048
1049 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1050 #ifdef ASSERT
1051 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1052 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1053 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1054 #endif
1055
1056 if (op->cond() == lir_cond_always) {
1057 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1058 __ b(*(op->label()));
1059 } else {
1060 Assembler::Condition acond;
1061 if (op->code() == lir_cond_float_branch) {
1062 bool is_unordered = (op->ublock() == op->block());
1063 // Assembler::EQ does not permit unordered branches, so we add
1064 // another branch here. Likewise, Assembler::NE does not permit
1065 // ordered branches.
1066 if ((is_unordered && op->cond() == lir_cond_equal)
1067 || (!is_unordered && op->cond() == lir_cond_notEqual))
1068 __ br(Assembler::VS, *(op->ublock()->label()));
1069 switch(op->cond()) {
1070 case lir_cond_equal: acond = Assembler::EQ; break;
1071 case lir_cond_notEqual: acond = Assembler::NE; break;
1072 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1073 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1074 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1075 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1076 default: ShouldNotReachHere();
1077 acond = Assembler::EQ; // unreachable
1078 }
1079 } else {
1080 switch (op->cond()) {
1081 case lir_cond_equal: acond = Assembler::EQ; break;
1082 case lir_cond_notEqual: acond = Assembler::NE; break;
1083 case lir_cond_less: acond = Assembler::LT; break;
1084 case lir_cond_lessEqual: acond = Assembler::LE; break;
1085 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1086 case lir_cond_greater: acond = Assembler::GT; break;
1087 case lir_cond_belowEqual: acond = Assembler::LS; break;
1088 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1089 default: ShouldNotReachHere();
1090 acond = Assembler::EQ; // unreachable
1091 }
1092 }
1093 __ br(acond,*(op->label()));
1094 }
1095 }
1096
1097
1098
1099 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1100 LIR_Opr src = op->in_opr();
1101 LIR_Opr dest = op->result_opr();
1102
1103 switch (op->bytecode()) {
1104 case Bytecodes::_i2f:
1105 {
1106 __ scvtfws(dest->as_float_reg(), src->as_register());
1107 break;
1108 }
1109 case Bytecodes::_i2d:
1110 {
1111 __ scvtfwd(dest->as_double_reg(), src->as_register());
1112 break;
1113 }
1114 case Bytecodes::_l2d:
1115 {
1116 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1117 break;
1118 }
1119 case Bytecodes::_l2f:
1120 {
1121 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1122 break;
1123 }
1124 case Bytecodes::_f2d:
1125 {
1126 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1127 break;
1128 }
1129 case Bytecodes::_d2f:
1130 {
1131 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1132 break;
1133 }
1134 case Bytecodes::_i2c:
1135 {
1136 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1137 break;
1138 }
1139 case Bytecodes::_i2l:
1140 {
1141 __ sxtw(dest->as_register_lo(), src->as_register());
1142 break;
1143 }
1144 case Bytecodes::_i2s:
1145 {
1146 __ sxth(dest->as_register(), src->as_register());
1147 break;
1148 }
1149 case Bytecodes::_i2b:
1150 {
1151 __ sxtb(dest->as_register(), src->as_register());
1152 break;
1153 }
1154 case Bytecodes::_l2i:
1155 {
1156 _masm->block_comment("FIXME: This could be a no-op");
1157 __ uxtw(dest->as_register(), src->as_register_lo());
1158 break;
1159 }
1160 case Bytecodes::_d2l:
1161 {
1162 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1163 break;
1164 }
1165 case Bytecodes::_f2i:
1166 {
1167 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1168 break;
1169 }
1170 case Bytecodes::_f2l:
1171 {
1172 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1173 break;
1174 }
1175 case Bytecodes::_d2i:
1176 {
1177 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1178 break;
1179 }
1180 default: ShouldNotReachHere();
1181 }
1182 }
1183
1184 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1185 if (op->init_check()) {
1186 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1187 __ ldarb(rscratch1, rscratch1);
1188 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1189 add_debug_info_for_null_check_here(op->stub()->info());
1190 __ br(Assembler::NE, *op->stub()->entry());
1191 }
1192 __ allocate_object(op->obj()->as_register(),
1193 op->tmp1()->as_register(),
1194 op->tmp2()->as_register(),
1195 op->header_size(),
1196 op->object_size(),
1197 op->klass()->as_register(),
1198 *op->stub()->entry());
1199 __ bind(*op->stub()->continuation());
1200 }
1201
1202 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1203 Register len = op->len()->as_register();
1204 __ uxtw(len, len);
1205
1206 if (UseSlowPath ||
1207 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1208 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1209 __ b(*op->stub()->entry());
1210 } else {
1211 Register tmp1 = op->tmp1()->as_register();
1212 Register tmp2 = op->tmp2()->as_register();
1213 Register tmp3 = op->tmp3()->as_register();
1214 if (len == tmp1) {
1215 tmp1 = tmp3;
1216 } else if (len == tmp2) {
1217 tmp2 = tmp3;
1218 } else if (len == tmp3) {
1219 // everything is ok
1220 } else {
1221 __ mov(tmp3, len);
1222 }
1223 __ allocate_array(op->obj()->as_register(),
1224 len,
1225 tmp1,
1226 tmp2,
1227 arrayOopDesc::base_offset_in_bytes(op->type()),
1228 array_element_size(op->type()),
1229 op->klass()->as_register(),
1230 *op->stub()->entry(),
1231 op->zero_array());
1232 }
1233 __ bind(*op->stub()->continuation());
1234 }
1235
1236 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md,
1237 ciProfileData *data, Register recv) {
1238
1239 int mdp_offset = md->byte_offset_of_slot(data, in_ByteSize(0));
1240 __ profile_receiver_type(recv, mdo, mdp_offset);
1241 }
1242
1243 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1244 // we always need a stub for the failure case.
1245 CodeStub* stub = op->stub();
1246 Register obj = op->object()->as_register();
1247 Register k_RInfo = op->tmp1()->as_register();
1248 Register klass_RInfo = op->tmp2()->as_register();
1249 Register dst = op->result_opr()->as_register();
1250 ciKlass* k = op->klass();
1251 Register Rtmp1 = noreg;
1252
1253 // check if it needs to be profiled
1254 ciMethodData* md;
1255 ciProfileData* data;
1256
1257 const bool should_profile = op->should_profile();
1258
1259 if (should_profile) {
1260 ciMethod* method = op->profiled_method();
1261 assert(method != nullptr, "Should have method");
1262 int bci = op->profiled_bci();
1263 md = method->method_data_or_null();
1264 assert(md != nullptr, "Sanity");
1265 data = md->bci_to_data(bci);
1266 assert(data != nullptr, "need data for type check");
1267 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1268 }
1269 Label* success_target = success;
1270 Label* failure_target = failure;
1271
1272 if (obj == k_RInfo) {
1273 k_RInfo = dst;
1274 } else if (obj == klass_RInfo) {
1275 klass_RInfo = dst;
1276 }
1277 if (k->is_loaded() && !UseCompressedClassPointers) {
1278 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1279 } else {
1280 Rtmp1 = op->tmp3()->as_register();
1281 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1282 }
1283
1284 assert_different_registers(obj, k_RInfo, klass_RInfo);
1285
1286 if (should_profile) {
1287 Register mdo = klass_RInfo;
1288 __ mov_metadata(mdo, md->constant_encoding());
1289 Label not_null;
1290 __ cbnz(obj, not_null);
1291 // Object is null; update MDO and exit
1292 Address data_addr
1293 = __ form_address(rscratch2, mdo,
1294 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1295 0);
1296 __ ldrb(rscratch1, data_addr);
1297 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1298 __ strb(rscratch1, data_addr);
1299 __ b(*obj_is_null);
1300 __ bind(not_null);
1301
1302 Register recv = k_RInfo;
1303 __ load_klass(recv, obj);
1304 type_profile_helper(mdo, md, data, recv);
1305 } else {
1306 __ cbz(obj, *obj_is_null);
1307 }
1308
1309 if (!k->is_loaded()) {
1310 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1311 } else {
1312 __ mov_metadata(k_RInfo, k->constant_encoding());
1313 }
1314 __ verify_oop(obj);
1315
1316 if (op->fast_check()) {
1317 // get object class
1318 // not a safepoint as obj null check happens earlier
1319 __ load_klass(rscratch1, obj);
1320 __ cmp( rscratch1, k_RInfo);
1321
1322 __ br(Assembler::NE, *failure_target);
1323 // successful cast, fall through to profile or jump
1324 } else {
1325 // get object class
1326 // not a safepoint as obj null check happens earlier
1327 __ load_klass(klass_RInfo, obj);
1328 if (k->is_loaded()) {
1329 // See if we get an immediate positive hit
1330 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1331 __ cmp(k_RInfo, rscratch1);
1332 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1333 __ br(Assembler::NE, *failure_target);
1334 // successful cast, fall through to profile or jump
1335 } else {
1336 // See if we get an immediate positive hit
1337 __ br(Assembler::EQ, *success_target);
1338 // check for self
1339 __ cmp(klass_RInfo, k_RInfo);
1340 __ br(Assembler::EQ, *success_target);
1341
1342 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1343 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1344 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1345 // result is a boolean
1346 __ cbzw(klass_RInfo, *failure_target);
1347 // successful cast, fall through to profile or jump
1348 }
1349 } else {
1350 // perform the fast part of the checking logic
1351 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1352 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1353 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1354 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1355 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1356 // result is a boolean
1357 __ cbz(k_RInfo, *failure_target);
1358 // successful cast, fall through to profile or jump
1359 }
1360 }
1361 __ b(*success);
1362 }
1363
1364
1365 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1366 const bool should_profile = op->should_profile();
1367
1368 LIR_Code code = op->code();
1369 if (code == lir_store_check) {
1370 Register value = op->object()->as_register();
1371 Register array = op->array()->as_register();
1372 Register k_RInfo = op->tmp1()->as_register();
1373 Register klass_RInfo = op->tmp2()->as_register();
1374 Register Rtmp1 = op->tmp3()->as_register();
1375
1376 CodeStub* stub = op->stub();
1377
1378 // check if it needs to be profiled
1379 ciMethodData* md;
1380 ciProfileData* data;
1381
1382 if (should_profile) {
1383 ciMethod* method = op->profiled_method();
1384 assert(method != nullptr, "Should have method");
1385 int bci = op->profiled_bci();
1386 md = method->method_data_or_null();
1387 assert(md != nullptr, "Sanity");
1388 data = md->bci_to_data(bci);
1389 assert(data != nullptr, "need data for type check");
1390 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1391 }
1392 Label done;
1393 Label* success_target = &done;
1394 Label* failure_target = stub->entry();
1395
1396 if (should_profile) {
1397 Label not_null;
1398 Register mdo = klass_RInfo;
1399 __ mov_metadata(mdo, md->constant_encoding());
1400 __ cbnz(value, not_null);
1401 // Object is null; update MDO and exit
1402 Address data_addr
1403 = __ form_address(rscratch2, mdo,
1404 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1405 __ ldrb(rscratch1, data_addr);
1406 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1407 __ strb(rscratch1, data_addr);
1408 __ b(done);
1409 __ bind(not_null);
1410
1411 Register recv = k_RInfo;
1412 __ load_klass(recv, value);
1413 type_profile_helper(mdo, md, data, recv);
1414 } else {
1415 __ cbz(value, done);
1416 }
1417
1418 add_debug_info_for_null_check_here(op->info_for_exception());
1419 __ load_klass(k_RInfo, array);
1420 __ load_klass(klass_RInfo, value);
1421
1422 // get instance klass (it's already uncompressed)
1423 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1424 // perform the fast part of the checking logic
1425 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1426 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1427 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1428 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1429 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1430 // result is a boolean
1431 __ cbzw(k_RInfo, *failure_target);
1432 // fall through to the success case
1433
1434 __ bind(done);
1435 } else if (code == lir_checkcast) {
1436 Register obj = op->object()->as_register();
1437 Register dst = op->result_opr()->as_register();
1438 Label success;
1439 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1440 __ bind(success);
1441 if (dst != obj) {
1442 __ mov(dst, obj);
1443 }
1444 } else if (code == lir_instanceof) {
1445 Register obj = op->object()->as_register();
1446 Register dst = op->result_opr()->as_register();
1447 Label success, failure, done;
1448 emit_typecheck_helper(op, &success, &failure, &failure);
1449 __ bind(failure);
1450 __ mov(dst, zr);
1451 __ b(done);
1452 __ bind(success);
1453 __ mov(dst, 1);
1454 __ bind(done);
1455 } else {
1456 ShouldNotReachHere();
1457 }
1458 }
1459
1460 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1461 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1462 __ cset(rscratch1, Assembler::NE);
1463 __ membar(__ AnyAny);
1464 }
1465
1466 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1467 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1468 __ cset(rscratch1, Assembler::NE);
1469 __ membar(__ AnyAny);
1470 }
1471
1472
1473 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1474 Register addr;
1475 if (op->addr()->is_register()) {
1476 addr = as_reg(op->addr());
1477 } else {
1478 assert(op->addr()->is_address(), "what else?");
1479 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1480 assert(addr_ptr->disp() == 0, "need 0 disp");
1481 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1482 addr = as_reg(addr_ptr->base());
1483 }
1484 Register newval = as_reg(op->new_value());
1485 Register cmpval = as_reg(op->cmp_value());
1486
1487 if (op->code() == lir_cas_obj) {
1488 if (UseCompressedOops) {
1489 Register t1 = op->tmp1()->as_register();
1490 assert(op->tmp1()->is_valid(), "must be");
1491 __ encode_heap_oop(t1, cmpval);
1492 cmpval = t1;
1493 __ encode_heap_oop(rscratch2, newval);
1494 newval = rscratch2;
1495 casw(addr, newval, cmpval);
1496 } else {
1497 casl(addr, newval, cmpval);
1498 }
1499 } else if (op->code() == lir_cas_int) {
1500 casw(addr, newval, cmpval);
1501 } else {
1502 casl(addr, newval, cmpval);
1503 }
1504 }
1505
1506
1507 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1508 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1509 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1510
1511 Assembler::Condition acond, ncond;
1512 switch (condition) {
1513 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1514 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1515 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1516 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1517 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1518 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1519 case lir_cond_belowEqual:
1520 case lir_cond_aboveEqual:
1521 default: ShouldNotReachHere();
1522 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1523 }
1524
1525 assert(result->is_single_cpu() || result->is_double_cpu(),
1526 "expect single register for result");
1527 if (opr1->is_constant() && opr2->is_constant()
1528 && opr1->type() == T_INT && opr2->type() == T_INT) {
1529 jint val1 = opr1->as_jint();
1530 jint val2 = opr2->as_jint();
1531 if (val1 == 0 && val2 == 1) {
1532 __ cset(result->as_register(), ncond);
1533 return;
1534 } else if (val1 == 1 && val2 == 0) {
1535 __ cset(result->as_register(), acond);
1536 return;
1537 }
1538 }
1539
1540 if (opr1->is_constant() && opr2->is_constant()
1541 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1542 jlong val1 = opr1->as_jlong();
1543 jlong val2 = opr2->as_jlong();
1544 if (val1 == 0 && val2 == 1) {
1545 __ cset(result->as_register_lo(), ncond);
1546 return;
1547 } else if (val1 == 1 && val2 == 0) {
1548 __ cset(result->as_register_lo(), acond);
1549 return;
1550 }
1551 }
1552
1553 if (opr1->is_stack()) {
1554 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1555 opr1 = FrameMap::rscratch1_opr;
1556 } else if (opr1->is_constant()) {
1557 LIR_Opr tmp
1558 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1559 const2reg(opr1, tmp, lir_patch_none, nullptr);
1560 opr1 = tmp;
1561 }
1562
1563 if (opr2->is_stack()) {
1564 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1565 opr2 = FrameMap::rscratch2_opr;
1566 } else if (opr2->is_constant()) {
1567 LIR_Opr tmp
1568 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1569 const2reg(opr2, tmp, lir_patch_none, nullptr);
1570 opr2 = tmp;
1571 }
1572
1573 if (result->type() == T_LONG)
1574 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1575 else
1576 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1577 }
1578
1579 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1580 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1581
1582 if (left->is_single_cpu()) {
1583 Register lreg = left->as_register();
1584 Register dreg = as_reg(dest);
1585
1586 if (right->is_single_cpu()) {
1587 // cpu register - cpu register
1588
1589 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1590 "should be");
1591 Register rreg = right->as_register();
1592 switch (code) {
1593 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1594 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1595 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1596 default: ShouldNotReachHere();
1597 }
1598
1599 } else if (right->is_double_cpu()) {
1600 Register rreg = right->as_register_lo();
1601 // single_cpu + double_cpu: can happen with obj+long
1602 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1603 switch (code) {
1604 case lir_add: __ add(dreg, lreg, rreg); break;
1605 case lir_sub: __ sub(dreg, lreg, rreg); break;
1606 default: ShouldNotReachHere();
1607 }
1608 } else if (right->is_constant()) {
1609 // cpu register - constant
1610 jlong c;
1611
1612 // FIXME. This is fugly: we really need to factor all this logic.
1613 switch(right->type()) {
1614 case T_LONG:
1615 c = right->as_constant_ptr()->as_jlong();
1616 break;
1617 case T_INT:
1618 case T_ADDRESS:
1619 c = right->as_constant_ptr()->as_jint();
1620 break;
1621 default:
1622 ShouldNotReachHere();
1623 c = 0; // unreachable
1624 break;
1625 }
1626
1627 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1628 if (c == 0 && dreg == lreg) {
1629 COMMENT("effective nop elided");
1630 return;
1631 }
1632 switch(left->type()) {
1633 case T_INT:
1634 switch (code) {
1635 case lir_add: __ addw(dreg, lreg, c); break;
1636 case lir_sub: __ subw(dreg, lreg, c); break;
1637 default: ShouldNotReachHere();
1638 }
1639 break;
1640 case T_OBJECT:
1641 case T_ADDRESS:
1642 switch (code) {
1643 case lir_add: __ add(dreg, lreg, c); break;
1644 case lir_sub: __ sub(dreg, lreg, c); break;
1645 default: ShouldNotReachHere();
1646 }
1647 break;
1648 default:
1649 ShouldNotReachHere();
1650 }
1651 } else {
1652 ShouldNotReachHere();
1653 }
1654
1655 } else if (left->is_double_cpu()) {
1656 Register lreg_lo = left->as_register_lo();
1657
1658 if (right->is_double_cpu()) {
1659 // cpu register - cpu register
1660 Register rreg_lo = right->as_register_lo();
1661 switch (code) {
1662 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1663 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1664 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1665 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1666 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1667 default:
1668 ShouldNotReachHere();
1669 }
1670
1671 } else if (right->is_constant()) {
1672 jlong c = right->as_constant_ptr()->as_jlong();
1673 Register dreg = as_reg(dest);
1674 switch (code) {
1675 case lir_add:
1676 case lir_sub:
1677 if (c == 0 && dreg == lreg_lo) {
1678 COMMENT("effective nop elided");
1679 return;
1680 }
1681 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1682 break;
1683 case lir_div:
1684 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1685 if (c == 1) {
1686 // move lreg_lo to dreg if divisor is 1
1687 __ mov(dreg, lreg_lo);
1688 } else {
1689 unsigned int shift = log2i_exact(c);
1690 // use rscratch1 as intermediate result register
1691 __ asr(rscratch1, lreg_lo, 63);
1692 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1693 __ asr(dreg, rscratch1, shift);
1694 }
1695 break;
1696 case lir_rem:
1697 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1698 if (c == 1) {
1699 // move 0 to dreg if divisor is 1
1700 __ mov(dreg, zr);
1701 } else {
1702 // use rscratch1 as intermediate result register
1703 __ negs(rscratch1, lreg_lo);
1704 __ andr(dreg, lreg_lo, c - 1);
1705 __ andr(rscratch1, rscratch1, c - 1);
1706 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1707 }
1708 break;
1709 default:
1710 ShouldNotReachHere();
1711 }
1712 } else {
1713 ShouldNotReachHere();
1714 }
1715 } else if (left->is_single_fpu()) {
1716 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1717 switch (code) {
1718 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1719 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1720 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1721 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1722 default:
1723 ShouldNotReachHere();
1724 }
1725 } else if (left->is_double_fpu()) {
1726 if (right->is_double_fpu()) {
1727 // fpu register - fpu register
1728 switch (code) {
1729 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1730 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1731 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1732 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1733 default:
1734 ShouldNotReachHere();
1735 }
1736 } else {
1737 if (right->is_constant()) {
1738 ShouldNotReachHere();
1739 }
1740 ShouldNotReachHere();
1741 }
1742 } else if (left->is_single_stack() || left->is_address()) {
1743 assert(left == dest, "left and dest must be equal");
1744 ShouldNotReachHere();
1745 } else {
1746 ShouldNotReachHere();
1747 }
1748 }
1749
1750 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1751 switch(code) {
1752 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1753 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1754 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1755 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1756 default : ShouldNotReachHere();
1757 }
1758 }
1759
1760 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1761
1762 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1763 Register Rleft = left->is_single_cpu() ? left->as_register() :
1764 left->as_register_lo();
1765 if (dst->is_single_cpu()) {
1766 Register Rdst = dst->as_register();
1767 if (right->is_constant()) {
1768 switch (code) {
1769 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1770 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1771 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1772 default: ShouldNotReachHere(); break;
1773 }
1774 } else {
1775 Register Rright = right->is_single_cpu() ? right->as_register() :
1776 right->as_register_lo();
1777 switch (code) {
1778 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1779 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1780 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1781 default: ShouldNotReachHere(); break;
1782 }
1783 }
1784 } else {
1785 Register Rdst = dst->as_register_lo();
1786 if (right->is_constant()) {
1787 switch (code) {
1788 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1789 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1790 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1791 default: ShouldNotReachHere(); break;
1792 }
1793 } else {
1794 Register Rright = right->is_single_cpu() ? right->as_register() :
1795 right->as_register_lo();
1796 switch (code) {
1797 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1798 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1799 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1800 default: ShouldNotReachHere(); break;
1801 }
1802 }
1803 }
1804 }
1805
1806
1807
1808 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1809
1810 // opcode check
1811 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1812 bool is_irem = (code == lir_irem);
1813
1814 // operand check
1815 assert(left->is_single_cpu(), "left must be register");
1816 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1817 assert(result->is_single_cpu(), "result must be register");
1818 Register lreg = left->as_register();
1819 Register dreg = result->as_register();
1820
1821 // power-of-2 constant check and codegen
1822 if (right->is_constant()) {
1823 int c = right->as_constant_ptr()->as_jint();
1824 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1825 if (is_irem) {
1826 if (c == 1) {
1827 // move 0 to dreg if divisor is 1
1828 __ movw(dreg, zr);
1829 } else {
1830 // use rscratch1 as intermediate result register
1831 __ negsw(rscratch1, lreg);
1832 __ andw(dreg, lreg, c - 1);
1833 __ andw(rscratch1, rscratch1, c - 1);
1834 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1835 }
1836 } else {
1837 if (c == 1) {
1838 // move lreg to dreg if divisor is 1
1839 __ movw(dreg, lreg);
1840 } else {
1841 unsigned int shift = exact_log2(c);
1842 // use rscratch1 as intermediate result register
1843 __ asrw(rscratch1, lreg, 31);
1844 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1845 __ asrw(dreg, rscratch1, shift);
1846 }
1847 }
1848 } else {
1849 Register rreg = right->as_register();
1850 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1851 }
1852 }
1853
1854
1855 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1856 if (opr1->is_constant() && opr2->is_single_cpu()) {
1857 // tableswitch
1858 Register reg = as_reg(opr2);
1859 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1860 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1861 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1862 Register reg1 = as_reg(opr1);
1863 if (opr2->is_single_cpu()) {
1864 // cpu register - cpu register
1865 Register reg2 = opr2->as_register();
1866 if (is_reference_type(opr1->type())) {
1867 __ cmpoop(reg1, reg2);
1868 } else {
1869 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1870 __ cmpw(reg1, reg2);
1871 }
1872 return;
1873 }
1874 if (opr2->is_double_cpu()) {
1875 // cpu register - cpu register
1876 Register reg2 = opr2->as_register_lo();
1877 __ cmp(reg1, reg2);
1878 return;
1879 }
1880
1881 if (opr2->is_constant()) {
1882 bool is_32bit = false; // width of register operand
1883 jlong imm;
1884
1885 switch(opr2->type()) {
1886 case T_INT:
1887 imm = opr2->as_constant_ptr()->as_jint();
1888 is_32bit = true;
1889 break;
1890 case T_LONG:
1891 imm = opr2->as_constant_ptr()->as_jlong();
1892 break;
1893 case T_ADDRESS:
1894 imm = opr2->as_constant_ptr()->as_jint();
1895 break;
1896 case T_METADATA:
1897 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1898 break;
1899 case T_OBJECT:
1900 case T_ARRAY:
1901 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1902 __ cmpoop(reg1, rscratch1);
1903 return;
1904 default:
1905 ShouldNotReachHere();
1906 imm = 0; // unreachable
1907 break;
1908 }
1909
1910 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1911 if (is_32bit)
1912 __ cmpw(reg1, imm);
1913 else
1914 __ subs(zr, reg1, imm);
1915 return;
1916 } else {
1917 __ mov(rscratch1, imm);
1918 if (is_32bit)
1919 __ cmpw(reg1, rscratch1);
1920 else
1921 __ cmp(reg1, rscratch1);
1922 return;
1923 }
1924 } else
1925 ShouldNotReachHere();
1926 } else if (opr1->is_single_fpu()) {
1927 FloatRegister reg1 = opr1->as_float_reg();
1928 assert(opr2->is_single_fpu(), "expect single float register");
1929 FloatRegister reg2 = opr2->as_float_reg();
1930 __ fcmps(reg1, reg2);
1931 } else if (opr1->is_double_fpu()) {
1932 FloatRegister reg1 = opr1->as_double_reg();
1933 assert(opr2->is_double_fpu(), "expect double float register");
1934 FloatRegister reg2 = opr2->as_double_reg();
1935 __ fcmpd(reg1, reg2);
1936 } else {
1937 ShouldNotReachHere();
1938 }
1939 }
1940
1941 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1942 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1943 bool is_unordered_less = (code == lir_ucmp_fd2i);
1944 if (left->is_single_fpu()) {
1945 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1946 } else if (left->is_double_fpu()) {
1947 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1948 } else {
1949 ShouldNotReachHere();
1950 }
1951 } else if (code == lir_cmp_l2i) {
1952 Label done;
1953 __ cmp(left->as_register_lo(), right->as_register_lo());
1954 __ mov(dst->as_register(), (uint64_t)-1L);
1955 __ br(Assembler::LT, done);
1956 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
1957 __ bind(done);
1958 } else {
1959 ShouldNotReachHere();
1960 }
1961 }
1962
1963
1964 void LIR_Assembler::align_call(LIR_Code code) { }
1965
1966
1967 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
1968 address call = __ trampoline_call(Address(op->addr(), rtype));
1969 if (call == nullptr) {
1970 bailout("trampoline stub overflow");
1971 return;
1972 }
1973 add_call_info(code_offset(), op->info());
1974 __ post_call_nop();
1975 }
1976
1977
1978 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
1979 address call = __ ic_call(op->addr());
1980 if (call == nullptr) {
1981 bailout("trampoline stub overflow");
1982 return;
1983 }
1984 add_call_info(code_offset(), op->info());
1985 __ post_call_nop();
1986 }
1987
1988 void LIR_Assembler::emit_static_call_stub() {
1989 address call_pc = __ pc();
1990 address stub = __ start_a_stub(call_stub_size());
1991 if (stub == nullptr) {
1992 bailout("static call stub overflow");
1993 return;
1994 }
1995
1996 int start = __ offset();
1997
1998 __ relocate(static_stub_Relocation::spec(call_pc));
1999 __ emit_static_call_stub();
2000
2001 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2002 <= call_stub_size(), "stub too big");
2003 __ end_a_stub();
2004 }
2005
2006
2007 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2008 assert(exceptionOop->as_register() == r0, "must match");
2009 assert(exceptionPC->as_register() == r3, "must match");
2010
2011 // exception object is not added to oop map by LinearScan
2012 // (LinearScan assumes that no oops are in fixed registers)
2013 info->add_register_oop(exceptionOop);
2014 StubId unwind_id;
2015
2016 // get current pc information
2017 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2018 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2019 // As no instructions have been generated yet for this LIR node it's
2020 // possible that an oop map already exists for the current offset.
2021 // In that case insert an dummy NOP here to ensure all oop map PCs
2022 // are unique. See JDK-8237483.
2023 __ nop();
2024 }
2025 int pc_for_athrow_offset = __ offset();
2026 InternalAddress pc_for_athrow(__ pc());
2027 __ adr(exceptionPC->as_register(), pc_for_athrow);
2028 add_call_info(pc_for_athrow_offset, info); // for exception handler
2029
2030 __ verify_not_null_oop(r0);
2031 // search an exception handler (r0: exception oop, r3: throwing pc)
2032 if (compilation()->has_fpu_code()) {
2033 unwind_id = StubId::c1_handle_exception_id;
2034 } else {
2035 unwind_id = StubId::c1_handle_exception_nofpu_id;
2036 }
2037 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2038
2039 // FIXME: enough room for two byte trap ????
2040 __ nop();
2041 }
2042
2043
2044 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2045 assert(exceptionOop->as_register() == r0, "must match");
2046
2047 __ b(_unwind_handler_entry);
2048 }
2049
2050
2051 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2052 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2053 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2054
2055 switch (left->type()) {
2056 case T_INT: {
2057 switch (code) {
2058 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2059 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2060 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2061 default:
2062 ShouldNotReachHere();
2063 break;
2064 }
2065 break;
2066 case T_LONG:
2067 case T_ADDRESS:
2068 case T_OBJECT:
2069 switch (code) {
2070 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2071 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2072 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2073 default:
2074 ShouldNotReachHere();
2075 break;
2076 }
2077 break;
2078 default:
2079 ShouldNotReachHere();
2080 break;
2081 }
2082 }
2083 }
2084
2085
2086 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2087 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2088 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2089
2090 switch (left->type()) {
2091 case T_INT: {
2092 switch (code) {
2093 case lir_shl: __ lslw (dreg, lreg, count); break;
2094 case lir_shr: __ asrw (dreg, lreg, count); break;
2095 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2096 default:
2097 ShouldNotReachHere();
2098 break;
2099 }
2100 break;
2101 case T_LONG:
2102 case T_ADDRESS:
2103 case T_OBJECT:
2104 switch (code) {
2105 case lir_shl: __ lsl (dreg, lreg, count); break;
2106 case lir_shr: __ asr (dreg, lreg, count); break;
2107 case lir_ushr: __ lsr (dreg, lreg, count); break;
2108 default:
2109 ShouldNotReachHere();
2110 break;
2111 }
2112 break;
2113 default:
2114 ShouldNotReachHere();
2115 break;
2116 }
2117 }
2118 }
2119
2120
2121 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2122 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2123 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2124 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2125 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2126 }
2127
2128
2129 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2130 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2131 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2132 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2133 __ mov (rscratch1, c);
2134 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2135 }
2136
2137
2138 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2139 ShouldNotReachHere();
2140 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2141 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2142 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2143 __ lea(rscratch1, __ constant_oop_address(o));
2144 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2145 }
2146
2147
2148 // This code replaces a call to arraycopy; no exception may
2149 // be thrown in this code, they must be thrown in the System.arraycopy
2150 // activation frame; we could save some checks if this would not be the case
2151 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2152 ciArrayKlass* default_type = op->expected_type();
2153 Register src = op->src()->as_register();
2154 Register dst = op->dst()->as_register();
2155 Register src_pos = op->src_pos()->as_register();
2156 Register dst_pos = op->dst_pos()->as_register();
2157 Register length = op->length()->as_register();
2158 Register tmp = op->tmp()->as_register();
2159
2160 CodeStub* stub = op->stub();
2161 int flags = op->flags();
2162 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2163 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2164
2165 // if we don't know anything, just go through the generic arraycopy
2166 if (default_type == nullptr // || basic_type == T_OBJECT
2167 ) {
2168 Label done;
2169 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2170
2171 // Save the arguments in case the generic arraycopy fails and we
2172 // have to fall back to the JNI stub
2173 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2174 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2175 __ str(src, Address(sp, 4*BytesPerWord));
2176
2177 address copyfunc_addr = StubRoutines::generic_arraycopy();
2178 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2179
2180 // The arguments are in java calling convention so we shift them
2181 // to C convention
2182 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2183 __ mov(c_rarg0, j_rarg0);
2184 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2185 __ mov(c_rarg1, j_rarg1);
2186 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2187 __ mov(c_rarg2, j_rarg2);
2188 assert_different_registers(c_rarg3, j_rarg4);
2189 __ mov(c_rarg3, j_rarg3);
2190 __ mov(c_rarg4, j_rarg4);
2191 #ifndef PRODUCT
2192 if (PrintC1Statistics) {
2193 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2194 }
2195 #endif
2196 __ far_call(RuntimeAddress(copyfunc_addr));
2197
2198 __ cbz(r0, *stub->continuation());
2199
2200 // Reload values from the stack so they are where the stub
2201 // expects them.
2202 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2203 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2204 __ ldr(src, Address(sp, 4*BytesPerWord));
2205
2206 // r0 is -1^K where K == partial copied count
2207 __ eonw(rscratch1, r0, zr);
2208 // adjust length down and src/end pos up by partial copied count
2209 __ subw(length, length, rscratch1);
2210 __ addw(src_pos, src_pos, rscratch1);
2211 __ addw(dst_pos, dst_pos, rscratch1);
2212 __ b(*stub->entry());
2213
2214 __ bind(*stub->continuation());
2215 return;
2216 }
2217
2218 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2219
2220 int elem_size = type2aelembytes(basic_type);
2221 int scale = exact_log2(elem_size);
2222
2223 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2224 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2225
2226 // test for null
2227 if (flags & LIR_OpArrayCopy::src_null_check) {
2228 __ cbz(src, *stub->entry());
2229 }
2230 if (flags & LIR_OpArrayCopy::dst_null_check) {
2231 __ cbz(dst, *stub->entry());
2232 }
2233
2234 // If the compiler was not able to prove that exact type of the source or the destination
2235 // of the arraycopy is an array type, check at runtime if the source or the destination is
2236 // an instance type.
2237 if (flags & LIR_OpArrayCopy::type_check) {
2238 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2239 __ load_klass(tmp, dst);
2240 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2241 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2242 __ br(Assembler::GE, *stub->entry());
2243 }
2244
2245 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2246 __ load_klass(tmp, src);
2247 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2248 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2249 __ br(Assembler::GE, *stub->entry());
2250 }
2251 }
2252
2253 // check if negative
2254 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2255 __ cmpw(src_pos, 0);
2256 __ br(Assembler::LT, *stub->entry());
2257 }
2258 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2259 __ cmpw(dst_pos, 0);
2260 __ br(Assembler::LT, *stub->entry());
2261 }
2262
2263 if (flags & LIR_OpArrayCopy::length_positive_check) {
2264 __ cmpw(length, 0);
2265 __ br(Assembler::LT, *stub->entry());
2266 }
2267
2268 if (flags & LIR_OpArrayCopy::src_range_check) {
2269 __ addw(tmp, src_pos, length);
2270 __ ldrw(rscratch1, src_length_addr);
2271 __ cmpw(tmp, rscratch1);
2272 __ br(Assembler::HI, *stub->entry());
2273 }
2274 if (flags & LIR_OpArrayCopy::dst_range_check) {
2275 __ addw(tmp, dst_pos, length);
2276 __ ldrw(rscratch1, dst_length_addr);
2277 __ cmpw(tmp, rscratch1);
2278 __ br(Assembler::HI, *stub->entry());
2279 }
2280
2281 if (flags & LIR_OpArrayCopy::type_check) {
2282 // We don't know the array types are compatible
2283 if (basic_type != T_OBJECT) {
2284 // Simple test for basic type arrays
2285 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2286 __ br(Assembler::NE, *stub->entry());
2287 } else {
2288 // For object arrays, if src is a sub class of dst then we can
2289 // safely do the copy.
2290 Label cont, slow;
2291
2292 #define PUSH(r1, r2) \
2293 stp(r1, r2, __ pre(sp, -2 * wordSize));
2294
2295 #define POP(r1, r2) \
2296 ldp(r1, r2, __ post(sp, 2 * wordSize));
2297
2298 __ PUSH(src, dst);
2299
2300 __ load_klass(src, src);
2301 __ load_klass(dst, dst);
2302
2303 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2304
2305 __ PUSH(src, dst);
2306 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
2307 __ POP(src, dst);
2308
2309 __ cbnz(src, cont);
2310
2311 __ bind(slow);
2312 __ POP(src, dst);
2313
2314 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2315 if (copyfunc_addr != nullptr) { // use stub if available
2316 // src is not a sub class of dst so we have to do a
2317 // per-element check.
2318
2319 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2320 if ((flags & mask) != mask) {
2321 // Check that at least both of them object arrays.
2322 assert(flags & mask, "one of the two should be known to be an object array");
2323
2324 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2325 __ load_klass(tmp, src);
2326 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2327 __ load_klass(tmp, dst);
2328 }
2329 int lh_offset = in_bytes(Klass::layout_helper_offset());
2330 Address klass_lh_addr(tmp, lh_offset);
2331 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2332 __ ldrw(rscratch1, klass_lh_addr);
2333 __ mov(rscratch2, objArray_lh);
2334 __ eorw(rscratch1, rscratch1, rscratch2);
2335 __ cbnzw(rscratch1, *stub->entry());
2336 }
2337
2338 // Spill because stubs can use any register they like and it's
2339 // easier to restore just those that we care about.
2340 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2341 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2342 __ str(src, Address(sp, 4*BytesPerWord));
2343
2344 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2345 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2346 assert_different_registers(c_rarg0, dst, dst_pos, length);
2347 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2348 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2349 assert_different_registers(c_rarg1, dst, length);
2350 __ uxtw(c_rarg2, length);
2351 assert_different_registers(c_rarg2, dst);
2352
2353 __ load_klass(c_rarg4, dst);
2354 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2355 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2356 __ far_call(RuntimeAddress(copyfunc_addr));
2357
2358 #ifndef PRODUCT
2359 if (PrintC1Statistics) {
2360 Label failed;
2361 __ cbnz(r0, failed);
2362 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2363 __ bind(failed);
2364 }
2365 #endif
2366
2367 __ cbz(r0, *stub->continuation());
2368
2369 #ifndef PRODUCT
2370 if (PrintC1Statistics) {
2371 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2372 }
2373 #endif
2374 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2375
2376 // Restore previously spilled arguments
2377 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2378 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2379 __ ldr(src, Address(sp, 4*BytesPerWord));
2380
2381 // return value is -1^K where K is partial copied count
2382 __ eonw(rscratch1, r0, zr);
2383 // adjust length down and src/end pos up by partial copied count
2384 __ subw(length, length, rscratch1);
2385 __ addw(src_pos, src_pos, rscratch1);
2386 __ addw(dst_pos, dst_pos, rscratch1);
2387 }
2388
2389 __ b(*stub->entry());
2390
2391 __ bind(cont);
2392 __ POP(src, dst);
2393 }
2394 }
2395
2396 #ifdef ASSERT
2397 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2398 // Sanity check the known type with the incoming class. For the
2399 // primitive case the types must match exactly with src.klass and
2400 // dst.klass each exactly matching the default type. For the
2401 // object array case, if no type check is needed then either the
2402 // dst type is exactly the expected type and the src type is a
2403 // subtype which we can't check or src is the same array as dst
2404 // but not necessarily exactly of type default_type.
2405 Label known_ok, halt;
2406 __ mov_metadata(tmp, default_type->constant_encoding());
2407
2408 if (basic_type != T_OBJECT) {
2409 __ cmp_klass(dst, tmp, rscratch1);
2410 __ br(Assembler::NE, halt);
2411 __ cmp_klass(src, tmp, rscratch1);
2412 __ br(Assembler::EQ, known_ok);
2413 } else {
2414 __ cmp_klass(dst, tmp, rscratch1);
2415 __ br(Assembler::EQ, known_ok);
2416 __ cmp(src, dst);
2417 __ br(Assembler::EQ, known_ok);
2418 }
2419 __ bind(halt);
2420 __ stop("incorrect type information in arraycopy");
2421 __ bind(known_ok);
2422 }
2423 #endif
2424
2425 #ifndef PRODUCT
2426 if (PrintC1Statistics) {
2427 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2428 }
2429 #endif
2430
2431 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2432 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2433 assert_different_registers(c_rarg0, dst, dst_pos, length);
2434 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2435 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2436 assert_different_registers(c_rarg1, dst, length);
2437 __ uxtw(c_rarg2, length);
2438 assert_different_registers(c_rarg2, dst);
2439
2440 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2441 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2442 const char *name;
2443 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2444
2445 CodeBlob *cb = CodeCache::find_blob(entry);
2446 if (cb) {
2447 __ far_call(RuntimeAddress(entry));
2448 } else {
2449 __ call_VM_leaf(entry, 3);
2450 }
2451
2452 if (stub != nullptr) {
2453 __ bind(*stub->continuation());
2454 }
2455 }
2456
2457
2458
2459
2460 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2461 Register obj = op->obj_opr()->as_register(); // may not be an oop
2462 Register hdr = op->hdr_opr()->as_register();
2463 Register lock = op->lock_opr()->as_register();
2464 Register temp = op->scratch_opr()->as_register();
2465 if (op->code() == lir_lock) {
2466 // add debug info for NullPointerException only if one is possible
2467 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2468 if (op->info() != nullptr) {
2469 add_debug_info_for_null_check(null_check_offset, op->info());
2470 }
2471 // done
2472 } else if (op->code() == lir_unlock) {
2473 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2474 } else {
2475 Unimplemented();
2476 }
2477 __ bind(*op->stub()->continuation());
2478 }
2479
2480 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2481 Register obj = op->obj()->as_pointer_register();
2482 Register result = op->result_opr()->as_pointer_register();
2483
2484 CodeEmitInfo* info = op->info();
2485 if (info != nullptr) {
2486 add_debug_info_for_null_check_here(info);
2487 }
2488
2489 __ load_klass(result, obj);
2490 }
2491
2492 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2493 ciMethod* method = op->profiled_method();
2494 int bci = op->profiled_bci();
2495 ciMethod* callee = op->profiled_callee();
2496
2497 // Update counter for all call types
2498 ciMethodData* md = method->method_data_or_null();
2499 assert(md != nullptr, "Sanity");
2500 ciProfileData* data = md->bci_to_data(bci);
2501 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2502 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2503 Register mdo = op->mdo()->as_register();
2504 __ mov_metadata(mdo, md->constant_encoding());
2505 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2506 // Perform additional virtual call profiling for invokevirtual and
2507 // invokeinterface bytecodes
2508 if (op->should_profile_receiver_type()) {
2509 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2510 Register recv = op->recv()->as_register();
2511 assert_different_registers(mdo, recv);
2512 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2513 ciKlass* known_klass = op->known_holder();
2514 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2515 // We know the type that will be seen at this call site; we can
2516 // statically update the MethodData* rather than needing to do
2517 // dynamic tests on the receiver type.
2518 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2519 for (uint i = 0; i < VirtualCallData::row_limit(); i++) {
2520 ciKlass* receiver = vc_data->receiver(i);
2521 if (known_klass->equals(receiver)) {
2522 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2523 __ addptr(data_addr, DataLayout::counter_increment);
2524 return;
2525 }
2526 }
2527 // Receiver type is not found in profile data.
2528 // Fall back to runtime helper to handle the rest at runtime.
2529 __ mov_metadata(recv, known_klass->constant_encoding());
2530 } else {
2531 __ load_klass(recv, recv);
2532 }
2533 type_profile_helper(mdo, md, data, recv);
2534 } else {
2535 // Static call
2536 __ addptr(counter_addr, DataLayout::counter_increment);
2537 }
2538 }
2539
2540
2541 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2542 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2543 }
2544
2545 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2546 assert(op->crc()->is_single_cpu(), "crc must be register");
2547 assert(op->val()->is_single_cpu(), "byte value must be register");
2548 assert(op->result_opr()->is_single_cpu(), "result must be register");
2549 Register crc = op->crc()->as_register();
2550 Register val = op->val()->as_register();
2551 Register res = op->result_opr()->as_register();
2552
2553 assert_different_registers(val, crc, res);
2554 uint64_t offset;
2555 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2556 __ add(res, res, offset);
2557
2558 __ mvnw(crc, crc); // ~crc
2559 __ update_byte_crc32(crc, val, res);
2560 __ mvnw(res, crc); // ~crc
2561 }
2562
2563 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2564 COMMENT("emit_profile_type {");
2565 Register obj = op->obj()->as_register();
2566 Register tmp = op->tmp()->as_pointer_register();
2567 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2568 ciKlass* exact_klass = op->exact_klass();
2569 intptr_t current_klass = op->current_klass();
2570 bool not_null = op->not_null();
2571 bool no_conflict = op->no_conflict();
2572
2573 Label update, next, none;
2574
2575 bool do_null = !not_null;
2576 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2577 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2578
2579 assert(do_null || do_update, "why are we here?");
2580 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2581 assert(mdo_addr.base() != rscratch1, "wrong register");
2582
2583 __ verify_oop(obj);
2584
2585 if (tmp != obj) {
2586 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2587 __ mov(tmp, obj);
2588 } else {
2589 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2590 }
2591 if (do_null) {
2592 __ cbnz(tmp, update);
2593 if (!TypeEntries::was_null_seen(current_klass)) {
2594 __ ldr(rscratch2, mdo_addr);
2595 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2596 __ str(rscratch2, mdo_addr);
2597 }
2598 if (do_update) {
2599 #ifndef ASSERT
2600 __ b(next);
2601 }
2602 #else
2603 __ b(next);
2604 }
2605 } else {
2606 __ cbnz(tmp, update);
2607 __ stop("unexpected null obj");
2608 #endif
2609 }
2610
2611 __ bind(update);
2612
2613 if (do_update) {
2614 #ifdef ASSERT
2615 if (exact_klass != nullptr) {
2616 Label ok;
2617 __ load_klass(tmp, tmp);
2618 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2619 __ eor(rscratch1, tmp, rscratch1);
2620 __ cbz(rscratch1, ok);
2621 __ stop("exact klass and actual klass differ");
2622 __ bind(ok);
2623 }
2624 #endif
2625 if (!no_conflict) {
2626 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2627 if (exact_klass != nullptr) {
2628 __ mov_metadata(tmp, exact_klass->constant_encoding());
2629 } else {
2630 __ load_klass(tmp, tmp);
2631 }
2632
2633 __ ldr(rscratch2, mdo_addr);
2634 __ eor(tmp, tmp, rscratch2);
2635 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2636 // klass seen before, nothing to do. The unknown bit may have been
2637 // set already but no need to check.
2638 __ cbz(rscratch1, next);
2639
2640 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2641
2642 if (TypeEntries::is_type_none(current_klass)) {
2643 __ cbz(rscratch2, none);
2644 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2645 __ br(Assembler::EQ, none);
2646 // There is a chance that the checks above
2647 // fail if another thread has just set the
2648 // profiling to this obj's klass
2649 __ dmb(Assembler::ISHLD);
2650 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2651 __ ldr(rscratch2, mdo_addr);
2652 __ eor(tmp, tmp, rscratch2);
2653 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2654 __ cbz(rscratch1, next);
2655 }
2656 } else {
2657 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2658 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2659
2660 __ ldr(tmp, mdo_addr);
2661 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2662 }
2663
2664 // different than before. Cannot keep accurate profile.
2665 __ ldr(rscratch2, mdo_addr);
2666 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2667 __ str(rscratch2, mdo_addr);
2668
2669 if (TypeEntries::is_type_none(current_klass)) {
2670 __ b(next);
2671
2672 __ bind(none);
2673 // first time here. Set profile type.
2674 __ str(tmp, mdo_addr);
2675 #ifdef ASSERT
2676 __ andr(tmp, tmp, TypeEntries::type_mask);
2677 __ verify_klass_ptr(tmp);
2678 #endif
2679 }
2680 } else {
2681 // There's a single possible klass at this profile point
2682 assert(exact_klass != nullptr, "should be");
2683 if (TypeEntries::is_type_none(current_klass)) {
2684 __ mov_metadata(tmp, exact_klass->constant_encoding());
2685 __ ldr(rscratch2, mdo_addr);
2686 __ eor(tmp, tmp, rscratch2);
2687 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2688 __ cbz(rscratch1, next);
2689 #ifdef ASSERT
2690 {
2691 Label ok;
2692 __ ldr(rscratch1, mdo_addr);
2693 __ cbz(rscratch1, ok);
2694 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2695 __ br(Assembler::EQ, ok);
2696 // may have been set by another thread
2697 __ dmb(Assembler::ISHLD);
2698 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2699 __ ldr(rscratch2, mdo_addr);
2700 __ eor(rscratch2, rscratch1, rscratch2);
2701 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2702 __ cbz(rscratch2, ok);
2703
2704 __ stop("unexpected profiling mismatch");
2705 __ bind(ok);
2706 }
2707 #endif
2708 // first time here. Set profile type.
2709 __ str(tmp, mdo_addr);
2710 #ifdef ASSERT
2711 __ andr(tmp, tmp, TypeEntries::type_mask);
2712 __ verify_klass_ptr(tmp);
2713 #endif
2714 } else {
2715 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2716 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2717
2718 __ ldr(tmp, mdo_addr);
2719 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2720
2721 __ orr(tmp, tmp, TypeEntries::type_unknown);
2722 __ str(tmp, mdo_addr);
2723 // FIXME: Write barrier needed here?
2724 }
2725 }
2726
2727 __ bind(next);
2728 }
2729 COMMENT("} emit_profile_type");
2730 }
2731
2732
2733 void LIR_Assembler::align_backward_branch_target() {
2734 }
2735
2736
2737 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2738 // tmp must be unused
2739 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2740
2741 if (left->is_single_cpu()) {
2742 assert(dest->is_single_cpu(), "expect single result reg");
2743 __ negw(dest->as_register(), left->as_register());
2744 } else if (left->is_double_cpu()) {
2745 assert(dest->is_double_cpu(), "expect double result reg");
2746 __ neg(dest->as_register_lo(), left->as_register_lo());
2747 } else if (left->is_single_fpu()) {
2748 assert(dest->is_single_fpu(), "expect single float result reg");
2749 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2750 } else {
2751 assert(left->is_double_fpu(), "expect double float operand reg");
2752 assert(dest->is_double_fpu(), "expect double float result reg");
2753 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2754 }
2755 }
2756
2757
2758 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2759 if (patch_code != lir_patch_none) {
2760 deoptimize_trap(info);
2761 return;
2762 }
2763
2764 __ lea(dest->as_pointer_register(), as_Address(addr->as_address_ptr()));
2765 }
2766
2767
2768 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2769 assert(!tmp->is_valid(), "don't need temporary");
2770
2771 CodeBlob *cb = CodeCache::find_blob(dest);
2772 if (cb) {
2773 __ far_call(RuntimeAddress(dest));
2774 } else {
2775 __ mov(rscratch1, RuntimeAddress(dest));
2776 __ blr(rscratch1);
2777 }
2778
2779 if (info != nullptr) {
2780 add_call_info_here(info);
2781 }
2782 __ post_call_nop();
2783 }
2784
2785 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2786 if (dest->is_address() || src->is_address()) {
2787 move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
2788 } else {
2789 ShouldNotReachHere();
2790 }
2791 }
2792
2793 #ifdef ASSERT
2794 // emit run-time assertion
2795 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2796 assert(op->code() == lir_assert, "must be");
2797
2798 if (op->in_opr1()->is_valid()) {
2799 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2800 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2801 } else {
2802 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2803 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2804 }
2805
2806 Label ok;
2807 if (op->condition() != lir_cond_always) {
2808 Assembler::Condition acond = Assembler::AL;
2809 switch (op->condition()) {
2810 case lir_cond_equal: acond = Assembler::EQ; break;
2811 case lir_cond_notEqual: acond = Assembler::NE; break;
2812 case lir_cond_less: acond = Assembler::LT; break;
2813 case lir_cond_lessEqual: acond = Assembler::LE; break;
2814 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2815 case lir_cond_greater: acond = Assembler::GT; break;
2816 case lir_cond_belowEqual: acond = Assembler::LS; break;
2817 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2818 default: ShouldNotReachHere();
2819 }
2820 __ br(acond, ok);
2821 }
2822 if (op->halt()) {
2823 const char* str = __ code_string(op->msg());
2824 __ stop(str);
2825 } else {
2826 breakpoint();
2827 }
2828 __ bind(ok);
2829 }
2830 #endif
2831
2832 #ifndef PRODUCT
2833 #define COMMENT(x) do { __ block_comment(x); } while (0)
2834 #else
2835 #define COMMENT(x)
2836 #endif
2837
2838 void LIR_Assembler::membar() {
2839 COMMENT("membar");
2840 __ membar(MacroAssembler::AnyAny);
2841 }
2842
2843 void LIR_Assembler::membar_acquire() {
2844 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2845 }
2846
2847 void LIR_Assembler::membar_release() {
2848 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2849 }
2850
2851 void LIR_Assembler::membar_loadload() {
2852 __ membar(Assembler::LoadLoad);
2853 }
2854
2855 void LIR_Assembler::membar_storestore() {
2856 __ membar(MacroAssembler::StoreStore);
2857 }
2858
2859 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2860
2861 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2862
2863 void LIR_Assembler::on_spin_wait() {
2864 __ spin_wait();
2865 }
2866
2867 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2868 __ mov(result_reg->as_register(), rthread);
2869 }
2870
2871
2872 void LIR_Assembler::peephole(LIR_List *lir) {
2873 #if 0
2874 if (tableswitch_count >= max_tableswitches)
2875 return;
2876
2877 /*
2878 This finite-state automaton recognizes sequences of compare-and-
2879 branch instructions. We will turn them into a tableswitch. You
2880 could argue that C1 really shouldn't be doing this sort of
2881 optimization, but without it the code is really horrible.
2882 */
2883
2884 enum { start_s, cmp1_s, beq_s, cmp_s } state;
2885 int first_key, last_key = -2147483648;
2886 int next_key = 0;
2887 int start_insn = -1;
2888 int last_insn = -1;
2889 Register reg = noreg;
2890 LIR_Opr reg_opr;
2891 state = start_s;
2892
2893 LIR_OpList* inst = lir->instructions_list();
2894 for (int i = 0; i < inst->length(); i++) {
2895 LIR_Op* op = inst->at(i);
2896 switch (state) {
2897 case start_s:
2898 first_key = -1;
2899 start_insn = i;
2900 switch (op->code()) {
2901 case lir_cmp:
2902 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2903 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2904 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2905 && opr2->is_constant()
2906 && opr2->type() == T_INT) {
2907 reg_opr = opr1;
2908 reg = opr1->as_register();
2909 first_key = opr2->as_constant_ptr()->as_jint();
2910 next_key = first_key + 1;
2911 state = cmp_s;
2912 goto next_state;
2913 }
2914 break;
2915 }
2916 break;
2917 case cmp_s:
2918 switch (op->code()) {
2919 case lir_branch:
2920 if (op->as_OpBranch()->cond() == lir_cond_equal) {
2921 state = beq_s;
2922 last_insn = i;
2923 goto next_state;
2924 }
2925 }
2926 state = start_s;
2927 break;
2928 case beq_s:
2929 switch (op->code()) {
2930 case lir_cmp: {
2931 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2932 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2933 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2934 && opr1->as_register() == reg
2935 && opr2->is_constant()
2936 && opr2->type() == T_INT
2937 && opr2->as_constant_ptr()->as_jint() == next_key) {
2938 last_key = next_key;
2939 next_key++;
2940 state = cmp_s;
2941 goto next_state;
2942 }
2943 }
2944 }
2945 last_key = next_key;
2946 state = start_s;
2947 break;
2948 default:
2949 assert(false, "impossible state");
2950 }
2951 if (state == start_s) {
2952 if (first_key < last_key - 5L && reg != noreg) {
2953 {
2954 // printf("found run register %d starting at insn %d low value %d high value %d\n",
2955 // reg->encoding(),
2956 // start_insn, first_key, last_key);
2957 // for (int i = 0; i < inst->length(); i++) {
2958 // inst->at(i)->print();
2959 // tty->print("\n");
2960 // }
2961 // tty->print("\n");
2962 }
2963
2964 struct tableswitch *sw = &switches[tableswitch_count];
2965 sw->_insn_index = start_insn, sw->_first_key = first_key,
2966 sw->_last_key = last_key, sw->_reg = reg;
2967 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
2968 {
2969 // Insert the new table of branches
2970 int offset = last_insn;
2971 for (int n = first_key; n < last_key; n++) {
2972 inst->insert_before
2973 (last_insn + 1,
2974 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
2975 inst->at(offset)->as_OpBranch()->label()));
2976 offset -= 2, i++;
2977 }
2978 }
2979 // Delete all the old compare-and-branch instructions
2980 for (int n = first_key; n < last_key; n++) {
2981 inst->remove_at(start_insn);
2982 inst->remove_at(start_insn);
2983 }
2984 // Insert the tableswitch instruction
2985 inst->insert_before(start_insn,
2986 new LIR_Op2(lir_cmp, lir_cond_always,
2987 LIR_OprFact::intConst(tableswitch_count),
2988 reg_opr));
2989 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
2990 tableswitch_count++;
2991 }
2992 reg = noreg;
2993 last_key = -2147483648;
2994 }
2995 next_state:
2996 ;
2997 }
2998 #endif
2999 }
3000
3001 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3002 Address addr = as_Address(src->as_address_ptr());
3003 BasicType type = src->type();
3004 bool is_oop = is_reference_type(type);
3005
3006 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3007 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3008
3009 switch(type) {
3010 case T_INT:
3011 xchg = &MacroAssembler::atomic_xchgalw;
3012 add = &MacroAssembler::atomic_addalw;
3013 break;
3014 case T_LONG:
3015 xchg = &MacroAssembler::atomic_xchgal;
3016 add = &MacroAssembler::atomic_addal;
3017 break;
3018 case T_OBJECT:
3019 case T_ARRAY:
3020 if (UseCompressedOops) {
3021 xchg = &MacroAssembler::atomic_xchgalw;
3022 add = &MacroAssembler::atomic_addalw;
3023 } else {
3024 xchg = &MacroAssembler::atomic_xchgal;
3025 add = &MacroAssembler::atomic_addal;
3026 }
3027 break;
3028 default:
3029 ShouldNotReachHere();
3030 xchg = &MacroAssembler::atomic_xchgal;
3031 add = &MacroAssembler::atomic_addal; // unreachable
3032 }
3033
3034 switch (code) {
3035 case lir_xadd:
3036 {
3037 RegisterOrConstant inc;
3038 Register tmp = as_reg(tmp_op);
3039 Register dst = as_reg(dest);
3040 if (data->is_constant()) {
3041 inc = RegisterOrConstant(as_long(data));
3042 assert_different_registers(dst, addr.base(), tmp,
3043 rscratch1, rscratch2);
3044 } else {
3045 inc = RegisterOrConstant(as_reg(data));
3046 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3047 rscratch1, rscratch2);
3048 }
3049 __ lea(tmp, addr);
3050 (_masm->*add)(dst, inc, tmp);
3051 break;
3052 }
3053 case lir_xchg:
3054 {
3055 Register tmp = tmp_op->as_register();
3056 Register obj = as_reg(data);
3057 Register dst = as_reg(dest);
3058 if (is_oop && UseCompressedOops) {
3059 __ encode_heap_oop(rscratch2, obj);
3060 obj = rscratch2;
3061 }
3062 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3063 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3064 __ lea(tmp, addr);
3065 (_masm->*xchg)(dst, obj, tmp);
3066 if (is_oop && UseCompressedOops) {
3067 __ decode_heap_oop(dst);
3068 }
3069 }
3070 break;
3071 default:
3072 ShouldNotReachHere();
3073 }
3074 if(!UseLSE) {
3075 __ membar(__ AnyAny);
3076 }
3077 }
3078
3079 #undef __