1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "asm/assembler.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "ci/ciUtilities.hpp"
37 #include "code/aotCodeCache.hpp"
38 #include "code/compiledIC.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/gc_globals.hpp"
41 #include "nativeInst_aarch64.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/sharedRuntime.hpp"
45 #include "runtime/stubRoutines.hpp"
46 #include "runtime/threadIdentifier.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_aarch64.inline.hpp"
49
50
51 #ifndef PRODUCT
52 #define COMMENT(x) do { __ block_comment(x); } while (0)
53 #else
54 #define COMMENT(x)
55 #endif
56
57 NEEDS_CLEANUP // remove this definitions ?
58 const Register SYNC_header = r0; // synchronization header
59 const Register SHIFT_count = r0; // where count for shift operations must be
60
61 #define __ _masm->
62
63
64 static void select_different_registers(Register preserve,
65 Register extra,
66 Register &tmp1,
67 Register &tmp2) {
68 if (tmp1 == preserve) {
69 assert_different_registers(tmp1, tmp2, extra);
70 tmp1 = extra;
71 } else if (tmp2 == preserve) {
72 assert_different_registers(tmp1, tmp2, extra);
73 tmp2 = extra;
74 }
75 assert_different_registers(preserve, tmp1, tmp2);
76 }
77
78
79
80 static void select_different_registers(Register preserve,
81 Register extra,
82 Register &tmp1,
83 Register &tmp2,
84 Register &tmp3) {
85 if (tmp1 == preserve) {
86 assert_different_registers(tmp1, tmp2, tmp3, extra);
87 tmp1 = extra;
88 } else if (tmp2 == preserve) {
89 assert_different_registers(tmp1, tmp2, tmp3, extra);
90 tmp2 = extra;
91 } else if (tmp3 == preserve) {
92 assert_different_registers(tmp1, tmp2, tmp3, extra);
93 tmp3 = extra;
94 }
95 assert_different_registers(preserve, tmp1, tmp2, tmp3);
96 }
97
98
99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
100
101
102 LIR_Opr LIR_Assembler::receiverOpr() {
103 return FrameMap::receiver_opr;
104 }
105
106 LIR_Opr LIR_Assembler::osrBufferPointer() {
107 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
108 }
109
110 //--------------fpu register translations-----------------------
111
112
113 address LIR_Assembler::float_constant(float f) {
114 address const_addr = __ float_constant(f);
115 if (const_addr == nullptr) {
116 bailout("const section overflow");
117 return __ code()->consts()->start();
118 } else {
119 return const_addr;
120 }
121 }
122
123
124 address LIR_Assembler::double_constant(double d) {
125 address const_addr = __ double_constant(d);
126 if (const_addr == nullptr) {
127 bailout("const section overflow");
128 return __ code()->consts()->start();
129 } else {
130 return const_addr;
131 }
132 }
133
134 address LIR_Assembler::int_constant(jlong n) {
135 address const_addr = __ long_constant(n);
136 if (const_addr == nullptr) {
137 bailout("const section overflow");
138 return __ code()->consts()->start();
139 } else {
140 return const_addr;
141 }
142 }
143
144 void LIR_Assembler::breakpoint() { Unimplemented(); }
145
146 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
147
148 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
149
150 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
151 //-------------------------------------------
152
153 static Register as_reg(LIR_Opr op) {
154 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
155 }
156
157 static jlong as_long(LIR_Opr data) {
158 jlong result;
159 switch (data->type()) {
160 case T_INT:
161 result = (data->as_jint());
162 break;
163 case T_LONG:
164 result = (data->as_jlong());
165 break;
166 default:
167 ShouldNotReachHere();
168 result = 0; // unreachable
169 }
170 return result;
171 }
172
173 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
174 Register base = addr->base()->as_pointer_register();
175 LIR_Opr opr = addr->index();
176 if (opr->is_cpu_register()) {
177 Register index;
178 if (opr->is_single_cpu())
179 index = opr->as_register();
180 else
181 index = opr->as_register_lo();
182 assert(addr->disp() == 0, "must be");
183 switch(opr->type()) {
184 case T_INT:
185 return Address(base, index, Address::sxtw(addr->scale()));
186 case T_LONG:
187 return Address(base, index, Address::lsl(addr->scale()));
188 default:
189 ShouldNotReachHere();
190 }
191 } else {
192 assert(addr->scale() == 0,
193 "expected for immediate operand, was: %d", addr->scale());
194 ptrdiff_t offset = ptrdiff_t(addr->disp());
195 // NOTE: Does not handle any 16 byte vector access.
196 const uint type_size = type2aelembytes(addr->type(), true);
197 return __ legitimize_address(Address(base, offset), type_size, tmp);
198 }
199 return Address();
200 }
201
202 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
203 ShouldNotReachHere();
204 return Address();
205 }
206
207 Address LIR_Assembler::as_Address(LIR_Address* addr) {
208 return as_Address(addr, rscratch1);
209 }
210
211 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
212 return as_Address(addr, rscratch1); // Ouch
213 // FIXME: This needs to be much more clever. See x86.
214 }
215
216 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
217 // not encodable as a base + (immediate) offset, generate an explicit address
218 // calculation to hold the address in a temporary register.
219 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
220 precond(size == 4 || size == 8);
221 Address addr = frame_map()->address_for_slot(index, adjust);
222 precond(addr.getMode() == Address::base_plus_offset);
223 precond(addr.base() == sp);
224 precond(addr.offset() > 0);
225 uint mask = size - 1;
226 assert((addr.offset() & mask) == 0, "scaled offsets only");
227 return __ legitimize_address(addr, size, tmp);
228 }
229
230 void LIR_Assembler::osr_entry() {
231 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
232 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
233 ValueStack* entry_state = osr_entry->state();
234 int number_of_locks = entry_state->locks_size();
235
236 // we jump here if osr happens with the interpreter
237 // state set up to continue at the beginning of the
238 // loop that triggered osr - in particular, we have
239 // the following registers setup:
240 //
241 // r2: osr buffer
242 //
243
244 // build frame
245 ciMethod* m = compilation()->method();
246 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
247
248 // OSR buffer is
249 //
250 // locals[nlocals-1..0]
251 // monitors[0..number_of_locks]
252 //
253 // locals is a direct copy of the interpreter frame so in the osr buffer
254 // so first slot in the local array is the last local from the interpreter
255 // and last slot is local[0] (receiver) from the interpreter
256 //
257 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
258 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
259 // in the interpreter frame (the method lock if a sync method)
260
261 // Initialize monitors in the compiled activation.
262 // r2: pointer to osr buffer
263 //
264 // All other registers are dead at this point and the locals will be
265 // copied into place by code emitted in the IR.
266
267 Register OSR_buf = osrBufferPointer()->as_pointer_register();
268 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
269 int monitor_offset = BytesPerWord * method()->max_locals() +
270 (2 * BytesPerWord) * (number_of_locks - 1);
271 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
272 // the OSR buffer using 2 word entries: first the lock and then
273 // the oop.
274 for (int i = 0; i < number_of_locks; i++) {
275 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
276 #ifdef ASSERT
277 // verify the interpreter's monitor has a non-null object
278 {
279 Label L;
280 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
281 __ cbnz(rscratch1, L);
282 __ stop("locked object is null");
283 __ bind(L);
284 }
285 #endif
286 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
287 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
288 __ str(r19, frame_map()->address_for_monitor_lock(i));
289 __ str(r20, frame_map()->address_for_monitor_object(i));
290 }
291 }
292 }
293
294
295 // inline cache check; done before the frame is built.
296 int LIR_Assembler::check_icache() {
297 return __ ic_check(CodeEntryAlignment);
298 }
299
300 void LIR_Assembler::clinit_barrier(ciMethod* method) {
301 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
302 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
303
304 Label L_skip_barrier;
305
306 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
307 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
308 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
309 __ bind(L_skip_barrier);
310 }
311
312 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
313 if (o == nullptr) {
314 __ mov(reg, zr);
315 } else {
316 __ movoop(reg, o);
317 }
318 }
319
320 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
321 address target = nullptr;
322 relocInfo::relocType reloc_type = relocInfo::none;
323
324 switch (patching_id(info)) {
325 case PatchingStub::access_field_id:
326 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
327 reloc_type = relocInfo::section_word_type;
328 break;
329 case PatchingStub::load_klass_id:
330 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
331 reloc_type = relocInfo::metadata_type;
332 break;
333 case PatchingStub::load_mirror_id:
334 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
335 reloc_type = relocInfo::oop_type;
336 break;
337 case PatchingStub::load_appendix_id:
338 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
339 reloc_type = relocInfo::oop_type;
340 break;
341 default: ShouldNotReachHere();
342 }
343
344 __ far_call(RuntimeAddress(target));
345 add_call_info_here(info);
346 }
347
348 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
349 deoptimize_trap(info);
350 }
351
352
353 // This specifies the rsp decrement needed to build the frame
354 int LIR_Assembler::initial_frame_size_in_bytes() const {
355 // if rounding, must let FrameMap know!
356
357 return in_bytes(frame_map()->framesize_in_bytes());
358 }
359
360
361 int LIR_Assembler::emit_exception_handler() {
362 // generate code for exception handler
363 address handler_base = __ start_a_stub(exception_handler_size());
364 if (handler_base == nullptr) {
365 // not enough space left for the handler
366 bailout("exception handler overflow");
367 return -1;
368 }
369
370 int offset = code_offset();
371
372 // the exception oop and pc are in r0, and r3
373 // no other registers need to be preserved, so invalidate them
374 __ invalidate_registers(false, true, true, false, true, true);
375
376 // check that there is really an exception
377 __ verify_not_null_oop(r0);
378
379 // search an exception handler (r0: exception oop, r3: throwing pc)
380 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id)));
381 __ should_not_reach_here();
382 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
383 __ end_a_stub();
384
385 return offset;
386 }
387
388
389 // Emit the code to remove the frame from the stack in the exception
390 // unwind path.
391 int LIR_Assembler::emit_unwind_handler() {
392 #ifndef PRODUCT
393 if (CommentedAssembly) {
394 _masm->block_comment("Unwind handler");
395 }
396 #endif
397
398 int offset = code_offset();
399
400 // Fetch the exception from TLS and clear out exception related thread state
401 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
402 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
403 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
404
405 __ bind(_unwind_handler_entry);
406 __ verify_not_null_oop(r0);
407 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
408 __ mov(r19, r0); // Preserve the exception
409 }
410
411 // Perform needed unlocking
412 MonitorExitStub* stub = nullptr;
413 if (method()->is_synchronized()) {
414 monitor_address(0, FrameMap::r0_opr);
415 stub = new MonitorExitStub(FrameMap::r0_opr, 0);
416 __ unlock_object(r5, r4, r0, r6, *stub->entry());
417 __ bind(*stub->continuation());
418 }
419
420 if (compilation()->env()->dtrace_method_probes()) {
421 __ mov(c_rarg0, rthread);
422 __ mov_metadata(c_rarg1, method()->constant_encoding());
423 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
424 }
425
426 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
427 __ mov(r0, r19); // Restore the exception
428 }
429
430 // remove the activation and dispatch to the unwind handler
431 __ block_comment("remove_frame and dispatch to the unwind handler");
432 __ remove_frame(initial_frame_size_in_bytes());
433 __ far_jump(RuntimeAddress(Runtime1::entry_for(StubId::c1_unwind_exception_id)));
434
435 // Emit the slow path assembly
436 if (stub != nullptr) {
437 stub->emit_code(this);
438 }
439
440 return offset;
441 }
442
443
444 int LIR_Assembler::emit_deopt_handler() {
445 // generate code for exception handler
446 address handler_base = __ start_a_stub(deopt_handler_size());
447 if (handler_base == nullptr) {
448 // not enough space left for the handler
449 bailout("deopt handler overflow");
450 return -1;
451 }
452
453 int offset = code_offset();
454
455 Label start;
456 __ bind(start);
457
458 __ far_call(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
459
460 int entry_offset = __ offset();
461 __ b(start);
462
463 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
464 assert(code_offset() - entry_offset >= NativePostCallNop::first_check_size,
465 "out of bounds read in post-call NOP check");
466 __ end_a_stub();
467
468 return entry_offset;
469 }
470
471 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
472 _masm->code_section()->relocate(adr, relocInfo::poll_type);
473 int pc_offset = code_offset();
474 flush_debug_info(pc_offset);
475 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
476 if (info->exception_handlers() != nullptr) {
477 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
478 }
479 }
480
481 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
482 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
483
484 // Pop the stack before the safepoint code
485 __ remove_frame(initial_frame_size_in_bytes());
486
487 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
488 __ reserved_stack_check();
489 }
490
491 code_stub->set_safepoint_offset(__ offset());
492 __ relocate(relocInfo::poll_return_type);
493 __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
494 __ ret(lr);
495 }
496
497 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
498 guarantee(info != nullptr, "Shouldn't be null");
499 __ get_polling_page(rscratch1, relocInfo::poll_type);
500 add_debug_info_for_branch(info); // This isn't just debug info:
501 // it's the oop map
502 __ read_polling_page(rscratch1, relocInfo::poll_type);
503 return __ offset();
504 }
505
506
507 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
508 if (from_reg == r31_sp)
509 from_reg = sp;
510 if (to_reg == r31_sp)
511 to_reg = sp;
512 __ mov(to_reg, from_reg);
513 }
514
515 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
516
517
518 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
519 assert(src->is_constant(), "should not call otherwise");
520 assert(dest->is_register(), "should not call otherwise");
521 LIR_Const* c = src->as_constant_ptr();
522
523 switch (c->type()) {
524 case T_INT: {
525 assert(patch_code == lir_patch_none, "no patching handled here");
526 __ movw(dest->as_register(), c->as_jint());
527 break;
528 }
529
530 case T_ADDRESS: {
531 assert(patch_code == lir_patch_none, "no patching handled here");
532 __ mov(dest->as_register(), c->as_jint());
533 break;
534 }
535
536 case T_LONG: {
537 assert(patch_code == lir_patch_none, "no patching handled here");
538 #if INCLUDE_CDS
539 if (AOTCodeCache::is_on_for_dump()) {
540 address b = c->as_pointer();
541 if (b == (address)ThreadIdentifier::unsafe_offset()) {
542 __ lea(dest->as_register_lo(), ExternalAddress(b));
543 break;
544 }
545 if (AOTRuntimeConstants::contains(b)) {
546 __ load_aotrc_address(dest->as_register_lo(), b);
547 break;
548 }
549 }
550 #endif
551 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
552 break;
553 }
554
555 case T_OBJECT: {
556 if (patch_code == lir_patch_none) {
557 jobject2reg(c->as_jobject(), dest->as_register());
558 } else {
559 jobject2reg_with_patching(dest->as_register(), info);
560 }
561 break;
562 }
563
564 case T_METADATA: {
565 if (patch_code != lir_patch_none) {
566 klass2reg_with_patching(dest->as_register(), info);
567 } else {
568 __ mov_metadata(dest->as_register(), c->as_metadata());
569 }
570 break;
571 }
572
573 case T_FLOAT: {
574 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
575 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
576 } else {
577 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
578 __ ldrs(dest->as_float_reg(), Address(rscratch1));
579 }
580 break;
581 }
582
583 case T_DOUBLE: {
584 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
585 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
586 } else {
587 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
588 __ ldrd(dest->as_double_reg(), Address(rscratch1));
589 }
590 break;
591 }
592
593 default:
594 ShouldNotReachHere();
595 }
596 }
597
598 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
599 LIR_Const* c = src->as_constant_ptr();
600 switch (c->type()) {
601 case T_OBJECT:
602 {
603 if (! c->as_jobject())
604 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
605 else {
606 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
607 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
608 }
609 }
610 break;
611 case T_ADDRESS:
612 {
613 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
614 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
615 }
616 case T_INT:
617 case T_FLOAT:
618 {
619 Register reg = zr;
620 if (c->as_jint_bits() == 0)
621 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
622 else {
623 __ movw(rscratch1, c->as_jint_bits());
624 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
625 }
626 }
627 break;
628 case T_LONG:
629 case T_DOUBLE:
630 {
631 Register reg = zr;
632 if (c->as_jlong_bits() == 0)
633 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
634 lo_word_offset_in_bytes));
635 else {
636 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
637 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
638 lo_word_offset_in_bytes));
639 }
640 }
641 break;
642 default:
643 ShouldNotReachHere();
644 }
645 }
646
647 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
648 assert(src->is_constant(), "should not call otherwise");
649 LIR_Const* c = src->as_constant_ptr();
650 LIR_Address* to_addr = dest->as_address_ptr();
651
652 void (Assembler::* insn)(Register Rt, const Address &adr);
653
654 switch (type) {
655 case T_ADDRESS:
656 assert(c->as_jint() == 0, "should be");
657 insn = &Assembler::str;
658 break;
659 case T_LONG:
660 assert(c->as_jlong() == 0, "should be");
661 insn = &Assembler::str;
662 break;
663 case T_INT:
664 assert(c->as_jint() == 0, "should be");
665 insn = &Assembler::strw;
666 break;
667 case T_OBJECT:
668 case T_ARRAY:
669 assert(c->as_jobject() == nullptr, "should be");
670 if (UseCompressedOops && !wide) {
671 insn = &Assembler::strw;
672 } else {
673 insn = &Assembler::str;
674 }
675 break;
676 case T_CHAR:
677 case T_SHORT:
678 assert(c->as_jint() == 0, "should be");
679 insn = &Assembler::strh;
680 break;
681 case T_BOOLEAN:
682 case T_BYTE:
683 assert(c->as_jint() == 0, "should be");
684 insn = &Assembler::strb;
685 break;
686 default:
687 ShouldNotReachHere();
688 insn = &Assembler::str; // unreachable
689 }
690
691 if (info) add_debug_info_for_null_check_here(info);
692 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
693 }
694
695 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
696 assert(src->is_register(), "should not call otherwise");
697 assert(dest->is_register(), "should not call otherwise");
698
699 // move between cpu-registers
700 if (dest->is_single_cpu()) {
701 if (src->type() == T_LONG) {
702 // Can do LONG -> OBJECT
703 move_regs(src->as_register_lo(), dest->as_register());
704 return;
705 }
706 assert(src->is_single_cpu(), "must match");
707 if (src->type() == T_OBJECT) {
708 __ verify_oop(src->as_register());
709 }
710 move_regs(src->as_register(), dest->as_register());
711
712 } else if (dest->is_double_cpu()) {
713 if (is_reference_type(src->type())) {
714 // Surprising to me but we can see move of a long to t_object
715 __ verify_oop(src->as_register());
716 move_regs(src->as_register(), dest->as_register_lo());
717 return;
718 }
719 assert(src->is_double_cpu(), "must match");
720 Register f_lo = src->as_register_lo();
721 Register f_hi = src->as_register_hi();
722 Register t_lo = dest->as_register_lo();
723 Register t_hi = dest->as_register_hi();
724 assert(f_hi == f_lo, "must be same");
725 assert(t_hi == t_lo, "must be same");
726 move_regs(f_lo, t_lo);
727
728 } else if (dest->is_single_fpu()) {
729 __ fmovs(dest->as_float_reg(), src->as_float_reg());
730
731 } else if (dest->is_double_fpu()) {
732 __ fmovd(dest->as_double_reg(), src->as_double_reg());
733
734 } else {
735 ShouldNotReachHere();
736 }
737 }
738
739 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
740 precond(src->is_register() && dest->is_stack());
741
742 uint const c_sz32 = sizeof(uint32_t);
743 uint const c_sz64 = sizeof(uint64_t);
744
745 if (src->is_single_cpu()) {
746 int index = dest->single_stack_ix();
747 if (is_reference_type(type)) {
748 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
749 __ verify_oop(src->as_register());
750 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
751 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
752 } else {
753 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
754 }
755
756 } else if (src->is_double_cpu()) {
757 int index = dest->double_stack_ix();
758 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
759 __ str(src->as_register_lo(), dest_addr_LO);
760
761 } else if (src->is_single_fpu()) {
762 int index = dest->single_stack_ix();
763 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
764
765 } else if (src->is_double_fpu()) {
766 int index = dest->double_stack_ix();
767 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
768
769 } else {
770 ShouldNotReachHere();
771 }
772 }
773
774
775 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
776 LIR_Address* to_addr = dest->as_address_ptr();
777 PatchingStub* patch = nullptr;
778 Register compressed_src = rscratch1;
779
780 if (patch_code != lir_patch_none) {
781 deoptimize_trap(info);
782 return;
783 }
784
785 if (is_reference_type(type)) {
786 __ verify_oop(src->as_register());
787
788 if (UseCompressedOops && !wide) {
789 __ encode_heap_oop(compressed_src, src->as_register());
790 } else {
791 compressed_src = src->as_register();
792 }
793 }
794
795 int null_check_here = code_offset();
796 switch (type) {
797 case T_FLOAT: {
798 __ strs(src->as_float_reg(), as_Address(to_addr));
799 break;
800 }
801
802 case T_DOUBLE: {
803 __ strd(src->as_double_reg(), as_Address(to_addr));
804 break;
805 }
806
807 case T_ARRAY: // fall through
808 case T_OBJECT: // fall through
809 if (UseCompressedOops && !wide) {
810 __ strw(compressed_src, as_Address(to_addr, rscratch2));
811 } else {
812 __ str(compressed_src, as_Address(to_addr));
813 }
814 break;
815 case T_METADATA:
816 // We get here to store a method pointer to the stack to pass to
817 // a dtrace runtime call. This can't work on 64 bit with
818 // compressed klass ptrs: T_METADATA can be a compressed klass
819 // ptr or a 64 bit method pointer.
820 ShouldNotReachHere();
821 __ str(src->as_register(), as_Address(to_addr));
822 break;
823 case T_ADDRESS:
824 __ str(src->as_register(), as_Address(to_addr));
825 break;
826 case T_INT:
827 __ strw(src->as_register(), as_Address(to_addr));
828 break;
829
830 case T_LONG: {
831 __ str(src->as_register_lo(), as_Address_lo(to_addr));
832 break;
833 }
834
835 case T_BYTE: // fall through
836 case T_BOOLEAN: {
837 __ strb(src->as_register(), as_Address(to_addr));
838 break;
839 }
840
841 case T_CHAR: // fall through
842 case T_SHORT:
843 __ strh(src->as_register(), as_Address(to_addr));
844 break;
845
846 default:
847 ShouldNotReachHere();
848 }
849 if (info != nullptr) {
850 add_debug_info_for_null_check(null_check_here, info);
851 }
852 }
853
854
855 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
856 precond(src->is_stack() && dest->is_register());
857
858 uint const c_sz32 = sizeof(uint32_t);
859 uint const c_sz64 = sizeof(uint64_t);
860
861 if (dest->is_single_cpu()) {
862 int index = src->single_stack_ix();
863 if (is_reference_type(type)) {
864 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
865 __ verify_oop(dest->as_register());
866 } else if (type == T_METADATA || type == T_ADDRESS) {
867 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
868 } else {
869 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
870 }
871
872 } else if (dest->is_double_cpu()) {
873 int index = src->double_stack_ix();
874 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
875 __ ldr(dest->as_register_lo(), src_addr_LO);
876
877 } else if (dest->is_single_fpu()) {
878 int index = src->single_stack_ix();
879 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
880
881 } else if (dest->is_double_fpu()) {
882 int index = src->double_stack_ix();
883 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
884
885 } else {
886 ShouldNotReachHere();
887 }
888 }
889
890
891 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
892 address target = nullptr;
893 relocInfo::relocType reloc_type = relocInfo::none;
894
895 switch (patching_id(info)) {
896 case PatchingStub::access_field_id:
897 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
898 reloc_type = relocInfo::section_word_type;
899 break;
900 case PatchingStub::load_klass_id:
901 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
902 reloc_type = relocInfo::metadata_type;
903 break;
904 case PatchingStub::load_mirror_id:
905 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
906 reloc_type = relocInfo::oop_type;
907 break;
908 case PatchingStub::load_appendix_id:
909 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
910 reloc_type = relocInfo::oop_type;
911 break;
912 default: ShouldNotReachHere();
913 }
914
915 __ far_call(RuntimeAddress(target));
916 add_call_info_here(info);
917 }
918
919 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
920
921 LIR_Opr temp;
922 if (type == T_LONG || type == T_DOUBLE)
923 temp = FrameMap::rscratch1_long_opr;
924 else
925 temp = FrameMap::rscratch1_opr;
926
927 stack2reg(src, temp, src->type());
928 reg2stack(temp, dest, dest->type());
929 }
930
931
932 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
933 LIR_Address* addr = src->as_address_ptr();
934 LIR_Address* from_addr = src->as_address_ptr();
935
936 if (addr->base()->type() == T_OBJECT) {
937 __ verify_oop(addr->base()->as_pointer_register());
938 }
939
940 if (patch_code != lir_patch_none) {
941 deoptimize_trap(info);
942 return;
943 }
944
945 if (info != nullptr) {
946 add_debug_info_for_null_check_here(info);
947 }
948 int null_check_here = code_offset();
949 switch (type) {
950 case T_FLOAT: {
951 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
952 break;
953 }
954
955 case T_DOUBLE: {
956 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
957 break;
958 }
959
960 case T_ARRAY: // fall through
961 case T_OBJECT: // fall through
962 if (UseCompressedOops && !wide) {
963 __ ldrw(dest->as_register(), as_Address(from_addr));
964 } else {
965 __ ldr(dest->as_register(), as_Address(from_addr));
966 }
967 break;
968 case T_METADATA:
969 // We get here to store a method pointer to the stack to pass to
970 // a dtrace runtime call. This can't work on 64 bit with
971 // compressed klass ptrs: T_METADATA can be a compressed klass
972 // ptr or a 64 bit method pointer.
973 ShouldNotReachHere();
974 __ ldr(dest->as_register(), as_Address(from_addr));
975 break;
976 case T_ADDRESS:
977 __ ldr(dest->as_register(), as_Address(from_addr));
978 break;
979 case T_INT:
980 __ ldrw(dest->as_register(), as_Address(from_addr));
981 break;
982
983 case T_LONG: {
984 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
985 break;
986 }
987
988 case T_BYTE:
989 __ ldrsb(dest->as_register(), as_Address(from_addr));
990 break;
991 case T_BOOLEAN: {
992 __ ldrb(dest->as_register(), as_Address(from_addr));
993 break;
994 }
995
996 case T_CHAR:
997 __ ldrh(dest->as_register(), as_Address(from_addr));
998 break;
999 case T_SHORT:
1000 __ ldrsh(dest->as_register(), as_Address(from_addr));
1001 break;
1002
1003 default:
1004 ShouldNotReachHere();
1005 }
1006
1007 if (is_reference_type(type)) {
1008 if (UseCompressedOops && !wide) {
1009 __ decode_heap_oop(dest->as_register());
1010 }
1011
1012 __ verify_oop(dest->as_register());
1013 }
1014 }
1015
1016
1017 int LIR_Assembler::array_element_size(BasicType type) const {
1018 int elem_size = type2aelembytes(type);
1019 return exact_log2(elem_size);
1020 }
1021
1022
1023 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1024 switch (op->code()) {
1025 case lir_idiv:
1026 case lir_irem:
1027 arithmetic_idiv(op->code(),
1028 op->in_opr1(),
1029 op->in_opr2(),
1030 op->in_opr3(),
1031 op->result_opr(),
1032 op->info());
1033 break;
1034 case lir_fmad:
1035 __ fmaddd(op->result_opr()->as_double_reg(),
1036 op->in_opr1()->as_double_reg(),
1037 op->in_opr2()->as_double_reg(),
1038 op->in_opr3()->as_double_reg());
1039 break;
1040 case lir_fmaf:
1041 __ fmadds(op->result_opr()->as_float_reg(),
1042 op->in_opr1()->as_float_reg(),
1043 op->in_opr2()->as_float_reg(),
1044 op->in_opr3()->as_float_reg());
1045 break;
1046 default: ShouldNotReachHere(); break;
1047 }
1048 }
1049
1050 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1051 #ifdef ASSERT
1052 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1053 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1054 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1055 #endif
1056
1057 if (op->cond() == lir_cond_always) {
1058 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1059 __ b(*(op->label()));
1060 } else {
1061 Assembler::Condition acond;
1062 if (op->code() == lir_cond_float_branch) {
1063 bool is_unordered = (op->ublock() == op->block());
1064 // Assembler::EQ does not permit unordered branches, so we add
1065 // another branch here. Likewise, Assembler::NE does not permit
1066 // ordered branches.
1067 if ((is_unordered && op->cond() == lir_cond_equal)
1068 || (!is_unordered && op->cond() == lir_cond_notEqual))
1069 __ br(Assembler::VS, *(op->ublock()->label()));
1070 switch(op->cond()) {
1071 case lir_cond_equal: acond = Assembler::EQ; break;
1072 case lir_cond_notEqual: acond = Assembler::NE; break;
1073 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1074 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1075 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1076 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1077 default: ShouldNotReachHere();
1078 acond = Assembler::EQ; // unreachable
1079 }
1080 } else {
1081 switch (op->cond()) {
1082 case lir_cond_equal: acond = Assembler::EQ; break;
1083 case lir_cond_notEqual: acond = Assembler::NE; break;
1084 case lir_cond_less: acond = Assembler::LT; break;
1085 case lir_cond_lessEqual: acond = Assembler::LE; break;
1086 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1087 case lir_cond_greater: acond = Assembler::GT; break;
1088 case lir_cond_belowEqual: acond = Assembler::LS; break;
1089 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1090 default: ShouldNotReachHere();
1091 acond = Assembler::EQ; // unreachable
1092 }
1093 }
1094 __ br(acond,*(op->label()));
1095 }
1096 }
1097
1098
1099
1100 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1101 LIR_Opr src = op->in_opr();
1102 LIR_Opr dest = op->result_opr();
1103
1104 switch (op->bytecode()) {
1105 case Bytecodes::_i2f:
1106 {
1107 __ scvtfws(dest->as_float_reg(), src->as_register());
1108 break;
1109 }
1110 case Bytecodes::_i2d:
1111 {
1112 __ scvtfwd(dest->as_double_reg(), src->as_register());
1113 break;
1114 }
1115 case Bytecodes::_l2d:
1116 {
1117 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1118 break;
1119 }
1120 case Bytecodes::_l2f:
1121 {
1122 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1123 break;
1124 }
1125 case Bytecodes::_f2d:
1126 {
1127 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1128 break;
1129 }
1130 case Bytecodes::_d2f:
1131 {
1132 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1133 break;
1134 }
1135 case Bytecodes::_i2c:
1136 {
1137 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1138 break;
1139 }
1140 case Bytecodes::_i2l:
1141 {
1142 __ sxtw(dest->as_register_lo(), src->as_register());
1143 break;
1144 }
1145 case Bytecodes::_i2s:
1146 {
1147 __ sxth(dest->as_register(), src->as_register());
1148 break;
1149 }
1150 case Bytecodes::_i2b:
1151 {
1152 __ sxtb(dest->as_register(), src->as_register());
1153 break;
1154 }
1155 case Bytecodes::_l2i:
1156 {
1157 _masm->block_comment("FIXME: This could be a no-op");
1158 __ uxtw(dest->as_register(), src->as_register_lo());
1159 break;
1160 }
1161 case Bytecodes::_d2l:
1162 {
1163 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1164 break;
1165 }
1166 case Bytecodes::_f2i:
1167 {
1168 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1169 break;
1170 }
1171 case Bytecodes::_f2l:
1172 {
1173 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1174 break;
1175 }
1176 case Bytecodes::_d2i:
1177 {
1178 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1179 break;
1180 }
1181 default: ShouldNotReachHere();
1182 }
1183 }
1184
1185 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1186 if (op->init_check()) {
1187 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1188 __ ldarb(rscratch1, rscratch1);
1189 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1190 add_debug_info_for_null_check_here(op->stub()->info());
1191 __ br(Assembler::NE, *op->stub()->entry());
1192 }
1193 __ allocate_object(op->obj()->as_register(),
1194 op->tmp1()->as_register(),
1195 op->tmp2()->as_register(),
1196 op->header_size(),
1197 op->object_size(),
1198 op->klass()->as_register(),
1199 *op->stub()->entry());
1200 __ bind(*op->stub()->continuation());
1201 }
1202
1203 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1204 Register len = op->len()->as_register();
1205 __ uxtw(len, len);
1206
1207 if (UseSlowPath ||
1208 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1209 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1210 __ b(*op->stub()->entry());
1211 } else {
1212 Register tmp1 = op->tmp1()->as_register();
1213 Register tmp2 = op->tmp2()->as_register();
1214 Register tmp3 = op->tmp3()->as_register();
1215 if (len == tmp1) {
1216 tmp1 = tmp3;
1217 } else if (len == tmp2) {
1218 tmp2 = tmp3;
1219 } else if (len == tmp3) {
1220 // everything is ok
1221 } else {
1222 __ mov(tmp3, len);
1223 }
1224 __ allocate_array(op->obj()->as_register(),
1225 len,
1226 tmp1,
1227 tmp2,
1228 arrayOopDesc::base_offset_in_bytes(op->type()),
1229 array_element_size(op->type()),
1230 op->klass()->as_register(),
1231 *op->stub()->entry(),
1232 op->zero_array());
1233 }
1234 __ bind(*op->stub()->continuation());
1235 }
1236
1237 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md,
1238 ciProfileData *data, Register recv) {
1239
1240 int mdp_offset = md->byte_offset_of_slot(data, in_ByteSize(0));
1241 __ profile_receiver_type(recv, mdo, mdp_offset);
1242 }
1243
1244 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1245 // we always need a stub for the failure case.
1246 CodeStub* stub = op->stub();
1247 Register obj = op->object()->as_register();
1248 Register k_RInfo = op->tmp1()->as_register();
1249 Register klass_RInfo = op->tmp2()->as_register();
1250 Register dst = op->result_opr()->as_register();
1251 ciKlass* k = op->klass();
1252 Register Rtmp1 = noreg;
1253
1254 // check if it needs to be profiled
1255 ciMethodData* md;
1256 ciProfileData* data;
1257
1258 const bool should_profile = op->should_profile();
1259
1260 if (should_profile) {
1261 ciMethod* method = op->profiled_method();
1262 assert(method != nullptr, "Should have method");
1263 int bci = op->profiled_bci();
1264 md = method->method_data_or_null();
1265 assert(md != nullptr, "Sanity");
1266 data = md->bci_to_data(bci);
1267 assert(data != nullptr, "need data for type check");
1268 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1269 }
1270 Label* success_target = success;
1271 Label* failure_target = failure;
1272
1273 if (obj == k_RInfo) {
1274 k_RInfo = dst;
1275 } else if (obj == klass_RInfo) {
1276 klass_RInfo = dst;
1277 }
1278 if (k->is_loaded() && !UseCompressedClassPointers) {
1279 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1280 } else {
1281 Rtmp1 = op->tmp3()->as_register();
1282 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1283 }
1284
1285 assert_different_registers(obj, k_RInfo, klass_RInfo);
1286
1287 if (should_profile) {
1288 Register mdo = klass_RInfo;
1289 __ mov_metadata(mdo, md->constant_encoding());
1290 Label not_null;
1291 __ cbnz(obj, not_null);
1292 // Object is null; update MDO and exit
1293 Address data_addr
1294 = __ form_address(rscratch2, mdo,
1295 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1296 0);
1297 __ ldrb(rscratch1, data_addr);
1298 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1299 __ strb(rscratch1, data_addr);
1300 __ b(*obj_is_null);
1301 __ bind(not_null);
1302
1303 Register recv = k_RInfo;
1304 __ load_klass(recv, obj);
1305 type_profile_helper(mdo, md, data, recv);
1306 } else {
1307 __ cbz(obj, *obj_is_null);
1308 }
1309
1310 if (!k->is_loaded()) {
1311 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1312 } else {
1313 __ mov_metadata(k_RInfo, k->constant_encoding());
1314 }
1315 __ verify_oop(obj);
1316
1317 if (op->fast_check()) {
1318 // get object class
1319 // not a safepoint as obj null check happens earlier
1320 __ load_klass(rscratch1, obj);
1321 __ cmp( rscratch1, k_RInfo);
1322
1323 __ br(Assembler::NE, *failure_target);
1324 // successful cast, fall through to profile or jump
1325 } else {
1326 // get object class
1327 // not a safepoint as obj null check happens earlier
1328 __ load_klass(klass_RInfo, obj);
1329 if (k->is_loaded()) {
1330 // See if we get an immediate positive hit
1331 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1332 __ cmp(k_RInfo, rscratch1);
1333 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1334 __ br(Assembler::NE, *failure_target);
1335 // successful cast, fall through to profile or jump
1336 } else {
1337 // See if we get an immediate positive hit
1338 __ br(Assembler::EQ, *success_target);
1339 // check for self
1340 __ cmp(klass_RInfo, k_RInfo);
1341 __ br(Assembler::EQ, *success_target);
1342
1343 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1344 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1345 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1346 // result is a boolean
1347 __ cbzw(klass_RInfo, *failure_target);
1348 // successful cast, fall through to profile or jump
1349 }
1350 } else {
1351 // perform the fast part of the checking logic
1352 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1353 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1354 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1355 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1356 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1357 // result is a boolean
1358 __ cbz(k_RInfo, *failure_target);
1359 // successful cast, fall through to profile or jump
1360 }
1361 }
1362 __ b(*success);
1363 }
1364
1365
1366 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1367 const bool should_profile = op->should_profile();
1368
1369 LIR_Code code = op->code();
1370 if (code == lir_store_check) {
1371 Register value = op->object()->as_register();
1372 Register array = op->array()->as_register();
1373 Register k_RInfo = op->tmp1()->as_register();
1374 Register klass_RInfo = op->tmp2()->as_register();
1375 Register Rtmp1 = op->tmp3()->as_register();
1376
1377 CodeStub* stub = op->stub();
1378
1379 // check if it needs to be profiled
1380 ciMethodData* md;
1381 ciProfileData* data;
1382
1383 if (should_profile) {
1384 ciMethod* method = op->profiled_method();
1385 assert(method != nullptr, "Should have method");
1386 int bci = op->profiled_bci();
1387 md = method->method_data_or_null();
1388 assert(md != nullptr, "Sanity");
1389 data = md->bci_to_data(bci);
1390 assert(data != nullptr, "need data for type check");
1391 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1392 }
1393 Label done;
1394 Label* success_target = &done;
1395 Label* failure_target = stub->entry();
1396
1397 if (should_profile) {
1398 Label not_null;
1399 Register mdo = klass_RInfo;
1400 __ mov_metadata(mdo, md->constant_encoding());
1401 __ cbnz(value, not_null);
1402 // Object is null; update MDO and exit
1403 Address data_addr
1404 = __ form_address(rscratch2, mdo,
1405 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1406 __ ldrb(rscratch1, data_addr);
1407 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1408 __ strb(rscratch1, data_addr);
1409 __ b(done);
1410 __ bind(not_null);
1411
1412 Register recv = k_RInfo;
1413 __ load_klass(recv, value);
1414 type_profile_helper(mdo, md, data, recv);
1415 } else {
1416 __ cbz(value, done);
1417 }
1418
1419 add_debug_info_for_null_check_here(op->info_for_exception());
1420 __ load_klass(k_RInfo, array);
1421 __ load_klass(klass_RInfo, value);
1422
1423 // get instance klass (it's already uncompressed)
1424 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1425 // perform the fast part of the checking logic
1426 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1427 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1428 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1429 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1430 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1431 // result is a boolean
1432 __ cbzw(k_RInfo, *failure_target);
1433 // fall through to the success case
1434
1435 __ bind(done);
1436 } else if (code == lir_checkcast) {
1437 Register obj = op->object()->as_register();
1438 Register dst = op->result_opr()->as_register();
1439 Label success;
1440 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1441 __ bind(success);
1442 if (dst != obj) {
1443 __ mov(dst, obj);
1444 }
1445 } else if (code == lir_instanceof) {
1446 Register obj = op->object()->as_register();
1447 Register dst = op->result_opr()->as_register();
1448 Label success, failure, done;
1449 emit_typecheck_helper(op, &success, &failure, &failure);
1450 __ bind(failure);
1451 __ mov(dst, zr);
1452 __ b(done);
1453 __ bind(success);
1454 __ mov(dst, 1);
1455 __ bind(done);
1456 } else {
1457 ShouldNotReachHere();
1458 }
1459 }
1460
1461 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1462 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1463 __ cset(rscratch1, Assembler::NE);
1464 __ membar(__ AnyAny);
1465 }
1466
1467 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1468 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1469 __ cset(rscratch1, Assembler::NE);
1470 __ membar(__ AnyAny);
1471 }
1472
1473
1474 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1475 Register addr;
1476 if (op->addr()->is_register()) {
1477 addr = as_reg(op->addr());
1478 } else {
1479 assert(op->addr()->is_address(), "what else?");
1480 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1481 assert(addr_ptr->disp() == 0, "need 0 disp");
1482 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1483 addr = as_reg(addr_ptr->base());
1484 }
1485 Register newval = as_reg(op->new_value());
1486 Register cmpval = as_reg(op->cmp_value());
1487
1488 if (op->code() == lir_cas_obj) {
1489 if (UseCompressedOops) {
1490 Register t1 = op->tmp1()->as_register();
1491 assert(op->tmp1()->is_valid(), "must be");
1492 __ encode_heap_oop(t1, cmpval);
1493 cmpval = t1;
1494 __ encode_heap_oop(rscratch2, newval);
1495 newval = rscratch2;
1496 casw(addr, newval, cmpval);
1497 } else {
1498 casl(addr, newval, cmpval);
1499 }
1500 } else if (op->code() == lir_cas_int) {
1501 casw(addr, newval, cmpval);
1502 } else {
1503 casl(addr, newval, cmpval);
1504 }
1505 }
1506
1507
1508 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1509 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1510 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1511
1512 Assembler::Condition acond, ncond;
1513 switch (condition) {
1514 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1515 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1516 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1517 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1518 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1519 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1520 case lir_cond_belowEqual:
1521 case lir_cond_aboveEqual:
1522 default: ShouldNotReachHere();
1523 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1524 }
1525
1526 assert(result->is_single_cpu() || result->is_double_cpu(),
1527 "expect single register for result");
1528 if (opr1->is_constant() && opr2->is_constant()
1529 && opr1->type() == T_INT && opr2->type() == T_INT) {
1530 jint val1 = opr1->as_jint();
1531 jint val2 = opr2->as_jint();
1532 if (val1 == 0 && val2 == 1) {
1533 __ cset(result->as_register(), ncond);
1534 return;
1535 } else if (val1 == 1 && val2 == 0) {
1536 __ cset(result->as_register(), acond);
1537 return;
1538 }
1539 }
1540
1541 if (opr1->is_constant() && opr2->is_constant()
1542 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1543 jlong val1 = opr1->as_jlong();
1544 jlong val2 = opr2->as_jlong();
1545 if (val1 == 0 && val2 == 1) {
1546 __ cset(result->as_register_lo(), ncond);
1547 return;
1548 } else if (val1 == 1 && val2 == 0) {
1549 __ cset(result->as_register_lo(), acond);
1550 return;
1551 }
1552 }
1553
1554 if (opr1->is_stack()) {
1555 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1556 opr1 = FrameMap::rscratch1_opr;
1557 } else if (opr1->is_constant()) {
1558 LIR_Opr tmp
1559 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1560 const2reg(opr1, tmp, lir_patch_none, nullptr);
1561 opr1 = tmp;
1562 }
1563
1564 if (opr2->is_stack()) {
1565 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1566 opr2 = FrameMap::rscratch2_opr;
1567 } else if (opr2->is_constant()) {
1568 LIR_Opr tmp
1569 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1570 const2reg(opr2, tmp, lir_patch_none, nullptr);
1571 opr2 = tmp;
1572 }
1573
1574 if (result->type() == T_LONG)
1575 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1576 else
1577 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1578 }
1579
1580 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1581 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1582
1583 if (left->is_single_cpu()) {
1584 Register lreg = left->as_register();
1585 Register dreg = as_reg(dest);
1586
1587 if (right->is_single_cpu()) {
1588 // cpu register - cpu register
1589
1590 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1591 "should be");
1592 Register rreg = right->as_register();
1593 switch (code) {
1594 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1595 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1596 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1597 default: ShouldNotReachHere();
1598 }
1599
1600 } else if (right->is_double_cpu()) {
1601 Register rreg = right->as_register_lo();
1602 // single_cpu + double_cpu: can happen with obj+long
1603 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1604 switch (code) {
1605 case lir_add: __ add(dreg, lreg, rreg); break;
1606 case lir_sub: __ sub(dreg, lreg, rreg); break;
1607 default: ShouldNotReachHere();
1608 }
1609 } else if (right->is_constant()) {
1610 // cpu register - constant
1611 jlong c;
1612
1613 // FIXME. This is fugly: we really need to factor all this logic.
1614 switch(right->type()) {
1615 case T_LONG:
1616 c = right->as_constant_ptr()->as_jlong();
1617 break;
1618 case T_INT:
1619 case T_ADDRESS:
1620 c = right->as_constant_ptr()->as_jint();
1621 break;
1622 default:
1623 ShouldNotReachHere();
1624 c = 0; // unreachable
1625 break;
1626 }
1627
1628 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1629 if (c == 0 && dreg == lreg) {
1630 COMMENT("effective nop elided");
1631 return;
1632 }
1633 switch(left->type()) {
1634 case T_INT:
1635 switch (code) {
1636 case lir_add: __ addw(dreg, lreg, c); break;
1637 case lir_sub: __ subw(dreg, lreg, c); break;
1638 default: ShouldNotReachHere();
1639 }
1640 break;
1641 case T_OBJECT:
1642 case T_ADDRESS:
1643 switch (code) {
1644 case lir_add: __ add(dreg, lreg, c); break;
1645 case lir_sub: __ sub(dreg, lreg, c); break;
1646 default: ShouldNotReachHere();
1647 }
1648 break;
1649 default:
1650 ShouldNotReachHere();
1651 }
1652 } else {
1653 ShouldNotReachHere();
1654 }
1655
1656 } else if (left->is_double_cpu()) {
1657 Register lreg_lo = left->as_register_lo();
1658
1659 if (right->is_double_cpu()) {
1660 // cpu register - cpu register
1661 Register rreg_lo = right->as_register_lo();
1662 switch (code) {
1663 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1664 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1665 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1666 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1667 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1668 default:
1669 ShouldNotReachHere();
1670 }
1671
1672 } else if (right->is_constant()) {
1673 jlong c = right->as_constant_ptr()->as_jlong();
1674 Register dreg = as_reg(dest);
1675 switch (code) {
1676 case lir_add:
1677 case lir_sub:
1678 if (c == 0 && dreg == lreg_lo) {
1679 COMMENT("effective nop elided");
1680 return;
1681 }
1682 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1683 break;
1684 case lir_div:
1685 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1686 if (c == 1) {
1687 // move lreg_lo to dreg if divisor is 1
1688 __ mov(dreg, lreg_lo);
1689 } else {
1690 unsigned int shift = log2i_exact(c);
1691 // use rscratch1 as intermediate result register
1692 __ asr(rscratch1, lreg_lo, 63);
1693 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1694 __ asr(dreg, rscratch1, shift);
1695 }
1696 break;
1697 case lir_rem:
1698 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1699 if (c == 1) {
1700 // move 0 to dreg if divisor is 1
1701 __ mov(dreg, zr);
1702 } else {
1703 // use rscratch1 as intermediate result register
1704 __ negs(rscratch1, lreg_lo);
1705 __ andr(dreg, lreg_lo, c - 1);
1706 __ andr(rscratch1, rscratch1, c - 1);
1707 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1708 }
1709 break;
1710 default:
1711 ShouldNotReachHere();
1712 }
1713 } else {
1714 ShouldNotReachHere();
1715 }
1716 } else if (left->is_single_fpu()) {
1717 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1718 switch (code) {
1719 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1720 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1721 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1722 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1723 default:
1724 ShouldNotReachHere();
1725 }
1726 } else if (left->is_double_fpu()) {
1727 if (right->is_double_fpu()) {
1728 // fpu register - fpu register
1729 switch (code) {
1730 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1731 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1732 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1733 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1734 default:
1735 ShouldNotReachHere();
1736 }
1737 } else {
1738 if (right->is_constant()) {
1739 ShouldNotReachHere();
1740 }
1741 ShouldNotReachHere();
1742 }
1743 } else if (left->is_single_stack() || left->is_address()) {
1744 assert(left == dest, "left and dest must be equal");
1745 ShouldNotReachHere();
1746 } else {
1747 ShouldNotReachHere();
1748 }
1749 }
1750
1751 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1752 switch(code) {
1753 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1754 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1755 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1756 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1757 default : ShouldNotReachHere();
1758 }
1759 }
1760
1761 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1762
1763 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1764 Register Rleft = left->is_single_cpu() ? left->as_register() :
1765 left->as_register_lo();
1766 if (dst->is_single_cpu()) {
1767 Register Rdst = dst->as_register();
1768 if (right->is_constant()) {
1769 switch (code) {
1770 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1771 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1772 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1773 default: ShouldNotReachHere(); break;
1774 }
1775 } else {
1776 Register Rright = right->is_single_cpu() ? right->as_register() :
1777 right->as_register_lo();
1778 switch (code) {
1779 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1780 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1781 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1782 default: ShouldNotReachHere(); break;
1783 }
1784 }
1785 } else {
1786 Register Rdst = dst->as_register_lo();
1787 if (right->is_constant()) {
1788 switch (code) {
1789 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1790 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1791 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1792 default: ShouldNotReachHere(); break;
1793 }
1794 } else {
1795 Register Rright = right->is_single_cpu() ? right->as_register() :
1796 right->as_register_lo();
1797 switch (code) {
1798 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1799 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1800 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1801 default: ShouldNotReachHere(); break;
1802 }
1803 }
1804 }
1805 }
1806
1807
1808
1809 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1810
1811 // opcode check
1812 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1813 bool is_irem = (code == lir_irem);
1814
1815 // operand check
1816 assert(left->is_single_cpu(), "left must be register");
1817 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1818 assert(result->is_single_cpu(), "result must be register");
1819 Register lreg = left->as_register();
1820 Register dreg = result->as_register();
1821
1822 // power-of-2 constant check and codegen
1823 if (right->is_constant()) {
1824 int c = right->as_constant_ptr()->as_jint();
1825 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1826 if (is_irem) {
1827 if (c == 1) {
1828 // move 0 to dreg if divisor is 1
1829 __ movw(dreg, zr);
1830 } else {
1831 // use rscratch1 as intermediate result register
1832 __ negsw(rscratch1, lreg);
1833 __ andw(dreg, lreg, c - 1);
1834 __ andw(rscratch1, rscratch1, c - 1);
1835 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1836 }
1837 } else {
1838 if (c == 1) {
1839 // move lreg to dreg if divisor is 1
1840 __ movw(dreg, lreg);
1841 } else {
1842 unsigned int shift = exact_log2(c);
1843 // use rscratch1 as intermediate result register
1844 __ asrw(rscratch1, lreg, 31);
1845 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1846 __ asrw(dreg, rscratch1, shift);
1847 }
1848 }
1849 } else {
1850 Register rreg = right->as_register();
1851 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1852 }
1853 }
1854
1855
1856 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1857 if (opr1->is_constant() && opr2->is_single_cpu()) {
1858 // tableswitch
1859 Register reg = as_reg(opr2);
1860 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1861 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1862 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1863 Register reg1 = as_reg(opr1);
1864 if (opr2->is_single_cpu()) {
1865 // cpu register - cpu register
1866 Register reg2 = opr2->as_register();
1867 if (is_reference_type(opr1->type())) {
1868 __ cmpoop(reg1, reg2);
1869 } else {
1870 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1871 __ cmpw(reg1, reg2);
1872 }
1873 return;
1874 }
1875 if (opr2->is_double_cpu()) {
1876 // cpu register - cpu register
1877 Register reg2 = opr2->as_register_lo();
1878 __ cmp(reg1, reg2);
1879 return;
1880 }
1881
1882 if (opr2->is_constant()) {
1883 bool is_32bit = false; // width of register operand
1884 jlong imm;
1885
1886 switch(opr2->type()) {
1887 case T_INT:
1888 imm = opr2->as_constant_ptr()->as_jint();
1889 is_32bit = true;
1890 break;
1891 case T_LONG:
1892 imm = opr2->as_constant_ptr()->as_jlong();
1893 break;
1894 case T_ADDRESS:
1895 imm = opr2->as_constant_ptr()->as_jint();
1896 break;
1897 case T_METADATA:
1898 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1899 break;
1900 case T_OBJECT:
1901 case T_ARRAY:
1902 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1903 __ cmpoop(reg1, rscratch1);
1904 return;
1905 default:
1906 ShouldNotReachHere();
1907 imm = 0; // unreachable
1908 break;
1909 }
1910
1911 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1912 if (is_32bit)
1913 __ cmpw(reg1, imm);
1914 else
1915 __ subs(zr, reg1, imm);
1916 return;
1917 } else {
1918 __ mov(rscratch1, imm);
1919 if (is_32bit)
1920 __ cmpw(reg1, rscratch1);
1921 else
1922 __ cmp(reg1, rscratch1);
1923 return;
1924 }
1925 } else
1926 ShouldNotReachHere();
1927 } else if (opr1->is_single_fpu()) {
1928 FloatRegister reg1 = opr1->as_float_reg();
1929 assert(opr2->is_single_fpu(), "expect single float register");
1930 FloatRegister reg2 = opr2->as_float_reg();
1931 __ fcmps(reg1, reg2);
1932 } else if (opr1->is_double_fpu()) {
1933 FloatRegister reg1 = opr1->as_double_reg();
1934 assert(opr2->is_double_fpu(), "expect double float register");
1935 FloatRegister reg2 = opr2->as_double_reg();
1936 __ fcmpd(reg1, reg2);
1937 } else {
1938 ShouldNotReachHere();
1939 }
1940 }
1941
1942 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1943 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1944 bool is_unordered_less = (code == lir_ucmp_fd2i);
1945 if (left->is_single_fpu()) {
1946 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1947 } else if (left->is_double_fpu()) {
1948 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1949 } else {
1950 ShouldNotReachHere();
1951 }
1952 } else if (code == lir_cmp_l2i) {
1953 Label done;
1954 __ cmp(left->as_register_lo(), right->as_register_lo());
1955 __ mov(dst->as_register(), (uint64_t)-1L);
1956 __ br(Assembler::LT, done);
1957 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
1958 __ bind(done);
1959 } else {
1960 ShouldNotReachHere();
1961 }
1962 }
1963
1964
1965 void LIR_Assembler::align_call(LIR_Code code) { }
1966
1967
1968 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
1969 address call = __ trampoline_call(Address(op->addr(), rtype));
1970 if (call == nullptr) {
1971 bailout("trampoline stub overflow");
1972 return;
1973 }
1974 add_call_info(code_offset(), op->info());
1975 __ post_call_nop();
1976 }
1977
1978
1979 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
1980 address call = __ ic_call(op->addr());
1981 if (call == nullptr) {
1982 bailout("trampoline stub overflow");
1983 return;
1984 }
1985 add_call_info(code_offset(), op->info());
1986 __ post_call_nop();
1987 }
1988
1989 void LIR_Assembler::emit_static_call_stub() {
1990 address call_pc = __ pc();
1991 address stub = __ start_a_stub(call_stub_size());
1992 if (stub == nullptr) {
1993 bailout("static call stub overflow");
1994 return;
1995 }
1996
1997 int start = __ offset();
1998
1999 __ relocate(static_stub_Relocation::spec(call_pc));
2000 __ emit_static_call_stub();
2001
2002 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2003 <= call_stub_size(), "stub too big");
2004 __ end_a_stub();
2005 }
2006
2007
2008 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2009 assert(exceptionOop->as_register() == r0, "must match");
2010 assert(exceptionPC->as_register() == r3, "must match");
2011
2012 // exception object is not added to oop map by LinearScan
2013 // (LinearScan assumes that no oops are in fixed registers)
2014 info->add_register_oop(exceptionOop);
2015 StubId unwind_id;
2016
2017 // get current pc information
2018 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2019 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2020 // As no instructions have been generated yet for this LIR node it's
2021 // possible that an oop map already exists for the current offset.
2022 // In that case insert an dummy NOP here to ensure all oop map PCs
2023 // are unique. See JDK-8237483.
2024 __ nop();
2025 }
2026 int pc_for_athrow_offset = __ offset();
2027 InternalAddress pc_for_athrow(__ pc());
2028 __ adr(exceptionPC->as_register(), pc_for_athrow);
2029 add_call_info(pc_for_athrow_offset, info); // for exception handler
2030
2031 __ verify_not_null_oop(r0);
2032 // search an exception handler (r0: exception oop, r3: throwing pc)
2033 if (compilation()->has_fpu_code()) {
2034 unwind_id = StubId::c1_handle_exception_id;
2035 } else {
2036 unwind_id = StubId::c1_handle_exception_nofpu_id;
2037 }
2038 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2039
2040 // FIXME: enough room for two byte trap ????
2041 __ nop();
2042 }
2043
2044
2045 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2046 assert(exceptionOop->as_register() == r0, "must match");
2047
2048 __ b(_unwind_handler_entry);
2049 }
2050
2051
2052 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2053 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2054 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2055
2056 switch (left->type()) {
2057 case T_INT: {
2058 switch (code) {
2059 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2060 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2061 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2062 default:
2063 ShouldNotReachHere();
2064 break;
2065 }
2066 break;
2067 case T_LONG:
2068 case T_ADDRESS:
2069 case T_OBJECT:
2070 switch (code) {
2071 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2072 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2073 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2074 default:
2075 ShouldNotReachHere();
2076 break;
2077 }
2078 break;
2079 default:
2080 ShouldNotReachHere();
2081 break;
2082 }
2083 }
2084 }
2085
2086
2087 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2088 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2089 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2090
2091 switch (left->type()) {
2092 case T_INT: {
2093 switch (code) {
2094 case lir_shl: __ lslw (dreg, lreg, count); break;
2095 case lir_shr: __ asrw (dreg, lreg, count); break;
2096 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2097 default:
2098 ShouldNotReachHere();
2099 break;
2100 }
2101 break;
2102 case T_LONG:
2103 case T_ADDRESS:
2104 case T_OBJECT:
2105 switch (code) {
2106 case lir_shl: __ lsl (dreg, lreg, count); break;
2107 case lir_shr: __ asr (dreg, lreg, count); break;
2108 case lir_ushr: __ lsr (dreg, lreg, count); break;
2109 default:
2110 ShouldNotReachHere();
2111 break;
2112 }
2113 break;
2114 default:
2115 ShouldNotReachHere();
2116 break;
2117 }
2118 }
2119 }
2120
2121
2122 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2123 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2124 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2125 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2126 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2127 }
2128
2129
2130 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2131 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2132 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2133 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2134 __ mov (rscratch1, c);
2135 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2136 }
2137
2138
2139 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2140 ShouldNotReachHere();
2141 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2142 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2143 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2144 __ lea(rscratch1, __ constant_oop_address(o));
2145 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2146 }
2147
2148
2149 // This code replaces a call to arraycopy; no exception may
2150 // be thrown in this code, they must be thrown in the System.arraycopy
2151 // activation frame; we could save some checks if this would not be the case
2152 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2153 ciArrayKlass* default_type = op->expected_type();
2154 Register src = op->src()->as_register();
2155 Register dst = op->dst()->as_register();
2156 Register src_pos = op->src_pos()->as_register();
2157 Register dst_pos = op->dst_pos()->as_register();
2158 Register length = op->length()->as_register();
2159 Register tmp = op->tmp()->as_register();
2160
2161 CodeStub* stub = op->stub();
2162 int flags = op->flags();
2163 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2164 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2165
2166 // if we don't know anything, just go through the generic arraycopy
2167 if (default_type == nullptr // || basic_type == T_OBJECT
2168 ) {
2169 Label done;
2170 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2171
2172 // Save the arguments in case the generic arraycopy fails and we
2173 // have to fall back to the JNI stub
2174 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2175 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2176 __ str(src, Address(sp, 4*BytesPerWord));
2177
2178 address copyfunc_addr = StubRoutines::generic_arraycopy();
2179 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2180
2181 // The arguments are in java calling convention so we shift them
2182 // to C convention
2183 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2184 __ mov(c_rarg0, j_rarg0);
2185 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2186 __ mov(c_rarg1, j_rarg1);
2187 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2188 __ mov(c_rarg2, j_rarg2);
2189 assert_different_registers(c_rarg3, j_rarg4);
2190 __ mov(c_rarg3, j_rarg3);
2191 __ mov(c_rarg4, j_rarg4);
2192 #ifndef PRODUCT
2193 if (PrintC1Statistics) {
2194 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2195 }
2196 #endif
2197 __ far_call(RuntimeAddress(copyfunc_addr));
2198
2199 __ cbz(r0, *stub->continuation());
2200
2201 // Reload values from the stack so they are where the stub
2202 // expects them.
2203 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2204 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2205 __ ldr(src, Address(sp, 4*BytesPerWord));
2206
2207 // r0 is -1^K where K == partial copied count
2208 __ eonw(rscratch1, r0, zr);
2209 // adjust length down and src/end pos up by partial copied count
2210 __ subw(length, length, rscratch1);
2211 __ addw(src_pos, src_pos, rscratch1);
2212 __ addw(dst_pos, dst_pos, rscratch1);
2213 __ b(*stub->entry());
2214
2215 __ bind(*stub->continuation());
2216 return;
2217 }
2218
2219 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2220
2221 int elem_size = type2aelembytes(basic_type);
2222 int scale = exact_log2(elem_size);
2223
2224 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2225 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2226
2227 // test for null
2228 if (flags & LIR_OpArrayCopy::src_null_check) {
2229 __ cbz(src, *stub->entry());
2230 }
2231 if (flags & LIR_OpArrayCopy::dst_null_check) {
2232 __ cbz(dst, *stub->entry());
2233 }
2234
2235 // If the compiler was not able to prove that exact type of the source or the destination
2236 // of the arraycopy is an array type, check at runtime if the source or the destination is
2237 // an instance type.
2238 if (flags & LIR_OpArrayCopy::type_check) {
2239 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2240 __ load_klass(tmp, dst);
2241 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2242 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2243 __ br(Assembler::GE, *stub->entry());
2244 }
2245
2246 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2247 __ load_klass(tmp, src);
2248 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2249 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2250 __ br(Assembler::GE, *stub->entry());
2251 }
2252 }
2253
2254 // check if negative
2255 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2256 __ cmpw(src_pos, 0);
2257 __ br(Assembler::LT, *stub->entry());
2258 }
2259 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2260 __ cmpw(dst_pos, 0);
2261 __ br(Assembler::LT, *stub->entry());
2262 }
2263
2264 if (flags & LIR_OpArrayCopy::length_positive_check) {
2265 __ cmpw(length, 0);
2266 __ br(Assembler::LT, *stub->entry());
2267 }
2268
2269 if (flags & LIR_OpArrayCopy::src_range_check) {
2270 __ addw(tmp, src_pos, length);
2271 __ ldrw(rscratch1, src_length_addr);
2272 __ cmpw(tmp, rscratch1);
2273 __ br(Assembler::HI, *stub->entry());
2274 }
2275 if (flags & LIR_OpArrayCopy::dst_range_check) {
2276 __ addw(tmp, dst_pos, length);
2277 __ ldrw(rscratch1, dst_length_addr);
2278 __ cmpw(tmp, rscratch1);
2279 __ br(Assembler::HI, *stub->entry());
2280 }
2281
2282 if (flags & LIR_OpArrayCopy::type_check) {
2283 // We don't know the array types are compatible
2284 if (basic_type != T_OBJECT) {
2285 // Simple test for basic type arrays
2286 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2287 __ br(Assembler::NE, *stub->entry());
2288 } else {
2289 // For object arrays, if src is a sub class of dst then we can
2290 // safely do the copy.
2291 Label cont, slow;
2292
2293 #define PUSH(r1, r2) \
2294 stp(r1, r2, __ pre(sp, -2 * wordSize));
2295
2296 #define POP(r1, r2) \
2297 ldp(r1, r2, __ post(sp, 2 * wordSize));
2298
2299 __ PUSH(src, dst);
2300
2301 __ load_klass(src, src);
2302 __ load_klass(dst, dst);
2303
2304 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2305
2306 __ PUSH(src, dst);
2307 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
2308 __ POP(src, dst);
2309
2310 __ cbnz(src, cont);
2311
2312 __ bind(slow);
2313 __ POP(src, dst);
2314
2315 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2316 if (copyfunc_addr != nullptr) { // use stub if available
2317 // src is not a sub class of dst so we have to do a
2318 // per-element check.
2319
2320 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2321 if ((flags & mask) != mask) {
2322 // Check that at least both of them object arrays.
2323 assert(flags & mask, "one of the two should be known to be an object array");
2324
2325 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2326 __ load_klass(tmp, src);
2327 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2328 __ load_klass(tmp, dst);
2329 }
2330 int lh_offset = in_bytes(Klass::layout_helper_offset());
2331 Address klass_lh_addr(tmp, lh_offset);
2332 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2333 __ ldrw(rscratch1, klass_lh_addr);
2334 __ mov(rscratch2, objArray_lh);
2335 __ eorw(rscratch1, rscratch1, rscratch2);
2336 __ cbnzw(rscratch1, *stub->entry());
2337 }
2338
2339 // Spill because stubs can use any register they like and it's
2340 // easier to restore just those that we care about.
2341 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2342 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2343 __ str(src, Address(sp, 4*BytesPerWord));
2344
2345 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2346 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2347 assert_different_registers(c_rarg0, dst, dst_pos, length);
2348 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2349 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2350 assert_different_registers(c_rarg1, dst, length);
2351 __ uxtw(c_rarg2, length);
2352 assert_different_registers(c_rarg2, dst);
2353
2354 __ load_klass(c_rarg4, dst);
2355 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2356 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2357 __ far_call(RuntimeAddress(copyfunc_addr));
2358
2359 #ifndef PRODUCT
2360 if (PrintC1Statistics) {
2361 Label failed;
2362 __ cbnz(r0, failed);
2363 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2364 __ bind(failed);
2365 }
2366 #endif
2367
2368 __ cbz(r0, *stub->continuation());
2369
2370 #ifndef PRODUCT
2371 if (PrintC1Statistics) {
2372 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2373 }
2374 #endif
2375 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2376
2377 // Restore previously spilled arguments
2378 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2379 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2380 __ ldr(src, Address(sp, 4*BytesPerWord));
2381
2382 // return value is -1^K where K is partial copied count
2383 __ eonw(rscratch1, r0, zr);
2384 // adjust length down and src/end pos up by partial copied count
2385 __ subw(length, length, rscratch1);
2386 __ addw(src_pos, src_pos, rscratch1);
2387 __ addw(dst_pos, dst_pos, rscratch1);
2388 }
2389
2390 __ b(*stub->entry());
2391
2392 __ bind(cont);
2393 __ POP(src, dst);
2394 }
2395 }
2396
2397 #ifdef ASSERT
2398 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2399 // Sanity check the known type with the incoming class. For the
2400 // primitive case the types must match exactly with src.klass and
2401 // dst.klass each exactly matching the default type. For the
2402 // object array case, if no type check is needed then either the
2403 // dst type is exactly the expected type and the src type is a
2404 // subtype which we can't check or src is the same array as dst
2405 // but not necessarily exactly of type default_type.
2406 Label known_ok, halt;
2407 __ mov_metadata(tmp, default_type->constant_encoding());
2408
2409 if (basic_type != T_OBJECT) {
2410 __ cmp_klass(dst, tmp, rscratch1);
2411 __ br(Assembler::NE, halt);
2412 __ cmp_klass(src, tmp, rscratch1);
2413 __ br(Assembler::EQ, known_ok);
2414 } else {
2415 __ cmp_klass(dst, tmp, rscratch1);
2416 __ br(Assembler::EQ, known_ok);
2417 __ cmp(src, dst);
2418 __ br(Assembler::EQ, known_ok);
2419 }
2420 __ bind(halt);
2421 __ stop("incorrect type information in arraycopy");
2422 __ bind(known_ok);
2423 }
2424 #endif
2425
2426 #ifndef PRODUCT
2427 if (PrintC1Statistics) {
2428 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2429 }
2430 #endif
2431
2432 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2433 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2434 assert_different_registers(c_rarg0, dst, dst_pos, length);
2435 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2436 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2437 assert_different_registers(c_rarg1, dst, length);
2438 __ uxtw(c_rarg2, length);
2439 assert_different_registers(c_rarg2, dst);
2440
2441 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2442 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2443 const char *name;
2444 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2445
2446 CodeBlob *cb = CodeCache::find_blob(entry);
2447 if (cb) {
2448 __ far_call(RuntimeAddress(entry));
2449 } else {
2450 __ call_VM_leaf(entry, 3);
2451 }
2452
2453 if (stub != nullptr) {
2454 __ bind(*stub->continuation());
2455 }
2456 }
2457
2458
2459
2460
2461 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2462 Register obj = op->obj_opr()->as_register(); // may not be an oop
2463 Register hdr = op->hdr_opr()->as_register();
2464 Register lock = op->lock_opr()->as_register();
2465 Register temp = op->scratch_opr()->as_register();
2466 if (op->code() == lir_lock) {
2467 // add debug info for NullPointerException only if one is possible
2468 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2469 if (op->info() != nullptr) {
2470 add_debug_info_for_null_check(null_check_offset, op->info());
2471 }
2472 // done
2473 } else if (op->code() == lir_unlock) {
2474 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2475 } else {
2476 Unimplemented();
2477 }
2478 __ bind(*op->stub()->continuation());
2479 }
2480
2481 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2482 Register obj = op->obj()->as_pointer_register();
2483 Register result = op->result_opr()->as_pointer_register();
2484
2485 CodeEmitInfo* info = op->info();
2486 if (info != nullptr) {
2487 add_debug_info_for_null_check_here(info);
2488 }
2489
2490 __ load_klass(result, obj);
2491 }
2492
2493 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2494 ciMethod* method = op->profiled_method();
2495 int bci = op->profiled_bci();
2496 ciMethod* callee = op->profiled_callee();
2497
2498 // Update counter for all call types
2499 ciMethodData* md = method->method_data_or_null();
2500 assert(md != nullptr, "Sanity");
2501 ciProfileData* data = md->bci_to_data(bci);
2502 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2503 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2504 Register mdo = op->mdo()->as_register();
2505 __ mov_metadata(mdo, md->constant_encoding());
2506 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2507 // Perform additional virtual call profiling for invokevirtual and
2508 // invokeinterface bytecodes
2509 if (op->should_profile_receiver_type()) {
2510 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2511 Register recv = op->recv()->as_register();
2512 assert_different_registers(mdo, recv);
2513 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2514 ciKlass* known_klass = op->known_holder();
2515 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2516 // We know the type that will be seen at this call site; we can
2517 // statically update the MethodData* rather than needing to do
2518 // dynamic tests on the receiver type.
2519 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2520 for (uint i = 0; i < VirtualCallData::row_limit(); i++) {
2521 ciKlass* receiver = vc_data->receiver(i);
2522 if (known_klass->equals(receiver)) {
2523 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2524 __ addptr(data_addr, DataLayout::counter_increment);
2525 return;
2526 }
2527 }
2528 // Receiver type is not found in profile data.
2529 // Fall back to runtime helper to handle the rest at runtime.
2530 __ mov_metadata(recv, known_klass->constant_encoding());
2531 } else {
2532 __ load_klass(recv, recv);
2533 }
2534 type_profile_helper(mdo, md, data, recv);
2535 } else {
2536 // Static call
2537 __ addptr(counter_addr, DataLayout::counter_increment);
2538 }
2539 }
2540
2541
2542 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2543 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2544 }
2545
2546 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2547 assert(op->crc()->is_single_cpu(), "crc must be register");
2548 assert(op->val()->is_single_cpu(), "byte value must be register");
2549 assert(op->result_opr()->is_single_cpu(), "result must be register");
2550 Register crc = op->crc()->as_register();
2551 Register val = op->val()->as_register();
2552 Register res = op->result_opr()->as_register();
2553
2554 assert_different_registers(val, crc, res);
2555 uint64_t offset;
2556 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2557 __ add(res, res, offset);
2558
2559 __ mvnw(crc, crc); // ~crc
2560 __ update_byte_crc32(crc, val, res);
2561 __ mvnw(res, crc); // ~crc
2562 }
2563
2564 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2565 COMMENT("emit_profile_type {");
2566 Register obj = op->obj()->as_register();
2567 Register tmp = op->tmp()->as_pointer_register();
2568 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2569 ciKlass* exact_klass = op->exact_klass();
2570 intptr_t current_klass = op->current_klass();
2571 bool not_null = op->not_null();
2572 bool no_conflict = op->no_conflict();
2573
2574 Label update, next, none;
2575
2576 bool do_null = !not_null;
2577 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2578 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2579
2580 assert(do_null || do_update, "why are we here?");
2581 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2582 assert(mdo_addr.base() != rscratch1, "wrong register");
2583
2584 __ verify_oop(obj);
2585
2586 if (tmp != obj) {
2587 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2588 __ mov(tmp, obj);
2589 } else {
2590 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2591 }
2592 if (do_null) {
2593 __ cbnz(tmp, update);
2594 if (!TypeEntries::was_null_seen(current_klass)) {
2595 __ ldr(rscratch2, mdo_addr);
2596 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2597 __ str(rscratch2, mdo_addr);
2598 }
2599 if (do_update) {
2600 #ifndef ASSERT
2601 __ b(next);
2602 }
2603 #else
2604 __ b(next);
2605 }
2606 } else {
2607 __ cbnz(tmp, update);
2608 __ stop("unexpected null obj");
2609 #endif
2610 }
2611
2612 __ bind(update);
2613
2614 if (do_update) {
2615 #ifdef ASSERT
2616 if (exact_klass != nullptr) {
2617 Label ok;
2618 __ load_klass(tmp, tmp);
2619 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2620 __ eor(rscratch1, tmp, rscratch1);
2621 __ cbz(rscratch1, ok);
2622 __ stop("exact klass and actual klass differ");
2623 __ bind(ok);
2624 }
2625 #endif
2626 if (!no_conflict) {
2627 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2628 if (exact_klass != nullptr) {
2629 __ mov_metadata(tmp, exact_klass->constant_encoding());
2630 } else {
2631 __ load_klass(tmp, tmp);
2632 }
2633
2634 __ ldr(rscratch2, mdo_addr);
2635 __ eor(tmp, tmp, rscratch2);
2636 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2637 // klass seen before, nothing to do. The unknown bit may have been
2638 // set already but no need to check.
2639 __ cbz(rscratch1, next);
2640
2641 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2642
2643 if (TypeEntries::is_type_none(current_klass)) {
2644 __ cbz(rscratch2, none);
2645 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2646 __ br(Assembler::EQ, none);
2647 // There is a chance that the checks above
2648 // fail if another thread has just set the
2649 // profiling to this obj's klass
2650 __ dmb(Assembler::ISHLD);
2651 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2652 __ ldr(rscratch2, mdo_addr);
2653 __ eor(tmp, tmp, rscratch2);
2654 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2655 __ cbz(rscratch1, next);
2656 }
2657 } else {
2658 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2659 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2660
2661 __ ldr(tmp, mdo_addr);
2662 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2663 }
2664
2665 // different than before. Cannot keep accurate profile.
2666 __ ldr(rscratch2, mdo_addr);
2667 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2668 __ str(rscratch2, mdo_addr);
2669
2670 if (TypeEntries::is_type_none(current_klass)) {
2671 __ b(next);
2672
2673 __ bind(none);
2674 // first time here. Set profile type.
2675 __ str(tmp, mdo_addr);
2676 #ifdef ASSERT
2677 __ andr(tmp, tmp, TypeEntries::type_mask);
2678 __ verify_klass_ptr(tmp);
2679 #endif
2680 }
2681 } else {
2682 // There's a single possible klass at this profile point
2683 assert(exact_klass != nullptr, "should be");
2684 if (TypeEntries::is_type_none(current_klass)) {
2685 __ mov_metadata(tmp, exact_klass->constant_encoding());
2686 __ ldr(rscratch2, mdo_addr);
2687 __ eor(tmp, tmp, rscratch2);
2688 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2689 __ cbz(rscratch1, next);
2690 #ifdef ASSERT
2691 {
2692 Label ok;
2693 __ ldr(rscratch1, mdo_addr);
2694 __ cbz(rscratch1, ok);
2695 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2696 __ br(Assembler::EQ, ok);
2697 // may have been set by another thread
2698 __ dmb(Assembler::ISHLD);
2699 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2700 __ ldr(rscratch2, mdo_addr);
2701 __ eor(rscratch2, rscratch1, rscratch2);
2702 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2703 __ cbz(rscratch2, ok);
2704
2705 __ stop("unexpected profiling mismatch");
2706 __ bind(ok);
2707 }
2708 #endif
2709 // first time here. Set profile type.
2710 __ str(tmp, mdo_addr);
2711 #ifdef ASSERT
2712 __ andr(tmp, tmp, TypeEntries::type_mask);
2713 __ verify_klass_ptr(tmp);
2714 #endif
2715 } else {
2716 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2717 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2718
2719 __ ldr(tmp, mdo_addr);
2720 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2721
2722 __ orr(tmp, tmp, TypeEntries::type_unknown);
2723 __ str(tmp, mdo_addr);
2724 // FIXME: Write barrier needed here?
2725 }
2726 }
2727
2728 __ bind(next);
2729 }
2730 COMMENT("} emit_profile_type");
2731 }
2732
2733
2734 void LIR_Assembler::align_backward_branch_target() {
2735 }
2736
2737
2738 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2739 // tmp must be unused
2740 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2741
2742 if (left->is_single_cpu()) {
2743 assert(dest->is_single_cpu(), "expect single result reg");
2744 __ negw(dest->as_register(), left->as_register());
2745 } else if (left->is_double_cpu()) {
2746 assert(dest->is_double_cpu(), "expect double result reg");
2747 __ neg(dest->as_register_lo(), left->as_register_lo());
2748 } else if (left->is_single_fpu()) {
2749 assert(dest->is_single_fpu(), "expect single float result reg");
2750 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2751 } else {
2752 assert(left->is_double_fpu(), "expect double float operand reg");
2753 assert(dest->is_double_fpu(), "expect double float result reg");
2754 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2755 }
2756 }
2757
2758
2759 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2760 if (patch_code != lir_patch_none) {
2761 deoptimize_trap(info);
2762 return;
2763 }
2764
2765 __ lea(dest->as_pointer_register(), as_Address(addr->as_address_ptr()));
2766 }
2767
2768
2769 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2770 assert(!tmp->is_valid(), "don't need temporary");
2771
2772 CodeBlob *cb = CodeCache::find_blob(dest);
2773 if (cb) {
2774 __ far_call(RuntimeAddress(dest));
2775 } else {
2776 __ mov(rscratch1, RuntimeAddress(dest));
2777 __ blr(rscratch1);
2778 }
2779
2780 if (info != nullptr) {
2781 add_call_info_here(info);
2782 }
2783 __ post_call_nop();
2784 }
2785
2786 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2787 if (dest->is_address() || src->is_address()) {
2788 move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
2789 } else {
2790 ShouldNotReachHere();
2791 }
2792 }
2793
2794 #ifdef ASSERT
2795 // emit run-time assertion
2796 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2797 assert(op->code() == lir_assert, "must be");
2798
2799 if (op->in_opr1()->is_valid()) {
2800 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2801 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2802 } else {
2803 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2804 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2805 }
2806
2807 Label ok;
2808 if (op->condition() != lir_cond_always) {
2809 Assembler::Condition acond = Assembler::AL;
2810 switch (op->condition()) {
2811 case lir_cond_equal: acond = Assembler::EQ; break;
2812 case lir_cond_notEqual: acond = Assembler::NE; break;
2813 case lir_cond_less: acond = Assembler::LT; break;
2814 case lir_cond_lessEqual: acond = Assembler::LE; break;
2815 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2816 case lir_cond_greater: acond = Assembler::GT; break;
2817 case lir_cond_belowEqual: acond = Assembler::LS; break;
2818 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2819 default: ShouldNotReachHere();
2820 }
2821 __ br(acond, ok);
2822 }
2823 if (op->halt()) {
2824 const char* str = __ code_string(op->msg());
2825 __ stop(str);
2826 } else {
2827 breakpoint();
2828 }
2829 __ bind(ok);
2830 }
2831 #endif
2832
2833 #ifndef PRODUCT
2834 #define COMMENT(x) do { __ block_comment(x); } while (0)
2835 #else
2836 #define COMMENT(x)
2837 #endif
2838
2839 void LIR_Assembler::membar() {
2840 COMMENT("membar");
2841 __ membar(MacroAssembler::AnyAny);
2842 }
2843
2844 void LIR_Assembler::membar_acquire() {
2845 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2846 }
2847
2848 void LIR_Assembler::membar_release() {
2849 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2850 }
2851
2852 void LIR_Assembler::membar_loadload() {
2853 __ membar(Assembler::LoadLoad);
2854 }
2855
2856 void LIR_Assembler::membar_storestore() {
2857 __ membar(MacroAssembler::StoreStore);
2858 }
2859
2860 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2861
2862 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2863
2864 void LIR_Assembler::on_spin_wait() {
2865 __ spin_wait();
2866 }
2867
2868 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2869 __ mov(result_reg->as_register(), rthread);
2870 }
2871
2872
2873 void LIR_Assembler::peephole(LIR_List *lir) {
2874 #if 0
2875 if (tableswitch_count >= max_tableswitches)
2876 return;
2877
2878 /*
2879 This finite-state automaton recognizes sequences of compare-and-
2880 branch instructions. We will turn them into a tableswitch. You
2881 could argue that C1 really shouldn't be doing this sort of
2882 optimization, but without it the code is really horrible.
2883 */
2884
2885 enum { start_s, cmp1_s, beq_s, cmp_s } state;
2886 int first_key, last_key = -2147483648;
2887 int next_key = 0;
2888 int start_insn = -1;
2889 int last_insn = -1;
2890 Register reg = noreg;
2891 LIR_Opr reg_opr;
2892 state = start_s;
2893
2894 LIR_OpList* inst = lir->instructions_list();
2895 for (int i = 0; i < inst->length(); i++) {
2896 LIR_Op* op = inst->at(i);
2897 switch (state) {
2898 case start_s:
2899 first_key = -1;
2900 start_insn = i;
2901 switch (op->code()) {
2902 case lir_cmp:
2903 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2904 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2905 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2906 && opr2->is_constant()
2907 && opr2->type() == T_INT) {
2908 reg_opr = opr1;
2909 reg = opr1->as_register();
2910 first_key = opr2->as_constant_ptr()->as_jint();
2911 next_key = first_key + 1;
2912 state = cmp_s;
2913 goto next_state;
2914 }
2915 break;
2916 }
2917 break;
2918 case cmp_s:
2919 switch (op->code()) {
2920 case lir_branch:
2921 if (op->as_OpBranch()->cond() == lir_cond_equal) {
2922 state = beq_s;
2923 last_insn = i;
2924 goto next_state;
2925 }
2926 }
2927 state = start_s;
2928 break;
2929 case beq_s:
2930 switch (op->code()) {
2931 case lir_cmp: {
2932 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2933 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2934 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2935 && opr1->as_register() == reg
2936 && opr2->is_constant()
2937 && opr2->type() == T_INT
2938 && opr2->as_constant_ptr()->as_jint() == next_key) {
2939 last_key = next_key;
2940 next_key++;
2941 state = cmp_s;
2942 goto next_state;
2943 }
2944 }
2945 }
2946 last_key = next_key;
2947 state = start_s;
2948 break;
2949 default:
2950 assert(false, "impossible state");
2951 }
2952 if (state == start_s) {
2953 if (first_key < last_key - 5L && reg != noreg) {
2954 {
2955 // printf("found run register %d starting at insn %d low value %d high value %d\n",
2956 // reg->encoding(),
2957 // start_insn, first_key, last_key);
2958 // for (int i = 0; i < inst->length(); i++) {
2959 // inst->at(i)->print();
2960 // tty->print("\n");
2961 // }
2962 // tty->print("\n");
2963 }
2964
2965 struct tableswitch *sw = &switches[tableswitch_count];
2966 sw->_insn_index = start_insn, sw->_first_key = first_key,
2967 sw->_last_key = last_key, sw->_reg = reg;
2968 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
2969 {
2970 // Insert the new table of branches
2971 int offset = last_insn;
2972 for (int n = first_key; n < last_key; n++) {
2973 inst->insert_before
2974 (last_insn + 1,
2975 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
2976 inst->at(offset)->as_OpBranch()->label()));
2977 offset -= 2, i++;
2978 }
2979 }
2980 // Delete all the old compare-and-branch instructions
2981 for (int n = first_key; n < last_key; n++) {
2982 inst->remove_at(start_insn);
2983 inst->remove_at(start_insn);
2984 }
2985 // Insert the tableswitch instruction
2986 inst->insert_before(start_insn,
2987 new LIR_Op2(lir_cmp, lir_cond_always,
2988 LIR_OprFact::intConst(tableswitch_count),
2989 reg_opr));
2990 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
2991 tableswitch_count++;
2992 }
2993 reg = noreg;
2994 last_key = -2147483648;
2995 }
2996 next_state:
2997 ;
2998 }
2999 #endif
3000 }
3001
3002 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3003 Address addr = as_Address(src->as_address_ptr());
3004 BasicType type = src->type();
3005 bool is_oop = is_reference_type(type);
3006
3007 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3008 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3009
3010 switch(type) {
3011 case T_INT:
3012 xchg = &MacroAssembler::atomic_xchgalw;
3013 add = &MacroAssembler::atomic_addalw;
3014 break;
3015 case T_LONG:
3016 xchg = &MacroAssembler::atomic_xchgal;
3017 add = &MacroAssembler::atomic_addal;
3018 break;
3019 case T_OBJECT:
3020 case T_ARRAY:
3021 if (UseCompressedOops) {
3022 xchg = &MacroAssembler::atomic_xchgalw;
3023 add = &MacroAssembler::atomic_addalw;
3024 } else {
3025 xchg = &MacroAssembler::atomic_xchgal;
3026 add = &MacroAssembler::atomic_addal;
3027 }
3028 break;
3029 default:
3030 ShouldNotReachHere();
3031 xchg = &MacroAssembler::atomic_xchgal;
3032 add = &MacroAssembler::atomic_addal; // unreachable
3033 }
3034
3035 switch (code) {
3036 case lir_xadd:
3037 {
3038 RegisterOrConstant inc;
3039 Register tmp = as_reg(tmp_op);
3040 Register dst = as_reg(dest);
3041 if (data->is_constant()) {
3042 inc = RegisterOrConstant(as_long(data));
3043 assert_different_registers(dst, addr.base(), tmp,
3044 rscratch1, rscratch2);
3045 } else {
3046 inc = RegisterOrConstant(as_reg(data));
3047 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3048 rscratch1, rscratch2);
3049 }
3050 __ lea(tmp, addr);
3051 (_masm->*add)(dst, inc, tmp);
3052 break;
3053 }
3054 case lir_xchg:
3055 {
3056 Register tmp = tmp_op->as_register();
3057 Register obj = as_reg(data);
3058 Register dst = as_reg(dest);
3059 if (is_oop && UseCompressedOops) {
3060 __ encode_heap_oop(rscratch2, obj);
3061 obj = rscratch2;
3062 }
3063 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3064 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3065 __ lea(tmp, addr);
3066 (_masm->*xchg)(dst, obj, tmp);
3067 if (is_oop && UseCompressedOops) {
3068 __ decode_heap_oop(dst);
3069 }
3070 }
3071 break;
3072 default:
3073 ShouldNotReachHere();
3074 }
3075 if(!UseLSE) {
3076 __ membar(__ AnyAny);
3077 }
3078 }
3079
3080 #undef __