1 /*
   2  * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "asm/macroAssembler.inline.hpp"
  27 #include "asm/assembler.hpp"
  28 #include "c1/c1_CodeStubs.hpp"
  29 #include "c1/c1_Compilation.hpp"
  30 #include "c1/c1_LIRAssembler.hpp"
  31 #include "c1/c1_MacroAssembler.hpp"
  32 #include "c1/c1_Runtime1.hpp"
  33 #include "c1/c1_ValueStack.hpp"
  34 #include "ci/ciArrayKlass.hpp"
  35 #include "ci/ciInstance.hpp"
  36 #include "ci/ciUtilities.hpp"
  37 #include "code/aotCodeCache.hpp"
  38 #include "code/compiledIC.hpp"
  39 #include "gc/shared/collectedHeap.hpp"
  40 #include "gc/shared/gc_globals.hpp"
  41 #include "nativeInst_aarch64.hpp"
  42 #include "oops/objArrayKlass.hpp"
  43 #include "runtime/frame.inline.hpp"
  44 #include "runtime/sharedRuntime.hpp"
  45 #include "runtime/stubRoutines.hpp"
  46 #include "runtime/threadIdentifier.hpp"
  47 #include "utilities/powerOfTwo.hpp"
  48 #include "vmreg_aarch64.inline.hpp"
  49 
  50 
  51 #ifndef PRODUCT
  52 #define COMMENT(x)   do { __ block_comment(x); } while (0)
  53 #else
  54 #define COMMENT(x)
  55 #endif
  56 
  57 NEEDS_CLEANUP // remove this definitions ?
  58 const Register SYNC_header = r0;   // synchronization header
  59 const Register SHIFT_count = r0;   // where count for shift operations must be
  60 
  61 #define __ _masm->
  62 
  63 
  64 static void select_different_registers(Register preserve,
  65                                        Register extra,
  66                                        Register &tmp1,
  67                                        Register &tmp2) {
  68   if (tmp1 == preserve) {
  69     assert_different_registers(tmp1, tmp2, extra);
  70     tmp1 = extra;
  71   } else if (tmp2 == preserve) {
  72     assert_different_registers(tmp1, tmp2, extra);
  73     tmp2 = extra;
  74   }
  75   assert_different_registers(preserve, tmp1, tmp2);
  76 }
  77 
  78 
  79 
  80 static void select_different_registers(Register preserve,
  81                                        Register extra,
  82                                        Register &tmp1,
  83                                        Register &tmp2,
  84                                        Register &tmp3) {
  85   if (tmp1 == preserve) {
  86     assert_different_registers(tmp1, tmp2, tmp3, extra);
  87     tmp1 = extra;
  88   } else if (tmp2 == preserve) {
  89     assert_different_registers(tmp1, tmp2, tmp3, extra);
  90     tmp2 = extra;
  91   } else if (tmp3 == preserve) {
  92     assert_different_registers(tmp1, tmp2, tmp3, extra);
  93     tmp3 = extra;
  94   }
  95   assert_different_registers(preserve, tmp1, tmp2, tmp3);
  96 }
  97 
  98 
  99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
 100 
 101 
 102 LIR_Opr LIR_Assembler::receiverOpr() {
 103   return FrameMap::receiver_opr;
 104 }
 105 
 106 LIR_Opr LIR_Assembler::osrBufferPointer() {
 107   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 108 }
 109 
 110 //--------------fpu register translations-----------------------
 111 
 112 
 113 address LIR_Assembler::float_constant(float f) {
 114   address const_addr = __ float_constant(f);
 115   if (const_addr == nullptr) {
 116     bailout("const section overflow");
 117     return __ code()->consts()->start();
 118   } else {
 119     return const_addr;
 120   }
 121 }
 122 
 123 
 124 address LIR_Assembler::double_constant(double d) {
 125   address const_addr = __ double_constant(d);
 126   if (const_addr == nullptr) {
 127     bailout("const section overflow");
 128     return __ code()->consts()->start();
 129   } else {
 130     return const_addr;
 131   }
 132 }
 133 
 134 address LIR_Assembler::int_constant(jlong n) {
 135   address const_addr = __ long_constant(n);
 136   if (const_addr == nullptr) {
 137     bailout("const section overflow");
 138     return __ code()->consts()->start();
 139   } else {
 140     return const_addr;
 141   }
 142 }
 143 
 144 void LIR_Assembler::breakpoint() { Unimplemented(); }
 145 
 146 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
 147 
 148 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
 149 
 150 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
 151 //-------------------------------------------
 152 
 153 static Register as_reg(LIR_Opr op) {
 154   return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
 155 }
 156 
 157 static jlong as_long(LIR_Opr data) {
 158   jlong result;
 159   switch (data->type()) {
 160   case T_INT:
 161     result = (data->as_jint());
 162     break;
 163   case T_LONG:
 164     result = (data->as_jlong());
 165     break;
 166   default:
 167     ShouldNotReachHere();
 168     result = 0;  // unreachable
 169   }
 170   return result;
 171 }
 172 
 173 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 174   Register base = addr->base()->as_pointer_register();
 175   LIR_Opr opr = addr->index();
 176   if (opr->is_cpu_register()) {
 177     Register index;
 178     if (opr->is_single_cpu())
 179       index = opr->as_register();
 180     else
 181       index = opr->as_register_lo();
 182     assert(addr->disp() == 0, "must be");
 183     switch(opr->type()) {
 184       case T_INT:
 185         return Address(base, index, Address::sxtw(addr->scale()));
 186       case T_LONG:
 187         return Address(base, index, Address::lsl(addr->scale()));
 188       default:
 189         ShouldNotReachHere();
 190       }
 191   } else {
 192     assert(addr->scale() == 0,
 193            "expected for immediate operand, was: %d", addr->scale());
 194     ptrdiff_t offset = ptrdiff_t(addr->disp());
 195     // NOTE: Does not handle any 16 byte vector access.
 196     const uint type_size = type2aelembytes(addr->type(), true);
 197     return __ legitimize_address(Address(base, offset), type_size, tmp);
 198   }
 199   return Address();
 200 }
 201 
 202 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 203   ShouldNotReachHere();
 204   return Address();
 205 }
 206 
 207 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 208   return as_Address(addr, rscratch1);
 209 }
 210 
 211 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 212   return as_Address(addr, rscratch1);  // Ouch
 213   // FIXME: This needs to be much more clever.  See x86.
 214 }
 215 
 216 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
 217 // not encodable as a base + (immediate) offset, generate an explicit address
 218 // calculation to hold the address in a temporary register.
 219 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
 220   precond(size == 4 || size == 8);
 221   Address addr = frame_map()->address_for_slot(index, adjust);
 222   precond(addr.getMode() == Address::base_plus_offset);
 223   precond(addr.base() == sp);
 224   precond(addr.offset() > 0);
 225   uint mask = size - 1;
 226   assert((addr.offset() & mask) == 0, "scaled offsets only");
 227   return __ legitimize_address(addr, size, tmp);
 228 }
 229 
 230 void LIR_Assembler::osr_entry() {
 231   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 232   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 233   ValueStack* entry_state = osr_entry->state();
 234   int number_of_locks = entry_state->locks_size();
 235 
 236   // we jump here if osr happens with the interpreter
 237   // state set up to continue at the beginning of the
 238   // loop that triggered osr - in particular, we have
 239   // the following registers setup:
 240   //
 241   // r2: osr buffer
 242   //
 243 
 244   // build frame
 245   ciMethod* m = compilation()->method();
 246   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 247 
 248   // OSR buffer is
 249   //
 250   // locals[nlocals-1..0]
 251   // monitors[0..number_of_locks]
 252   //
 253   // locals is a direct copy of the interpreter frame so in the osr buffer
 254   // so first slot in the local array is the last local from the interpreter
 255   // and last slot is local[0] (receiver) from the interpreter
 256   //
 257   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 258   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 259   // in the interpreter frame (the method lock if a sync method)
 260 
 261   // Initialize monitors in the compiled activation.
 262   //   r2: pointer to osr buffer
 263   //
 264   // All other registers are dead at this point and the locals will be
 265   // copied into place by code emitted in the IR.
 266 
 267   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 268   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 269     int monitor_offset = BytesPerWord * method()->max_locals() +
 270       (2 * BytesPerWord) * (number_of_locks - 1);
 271     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 272     // the OSR buffer using 2 word entries: first the lock and then
 273     // the oop.
 274     for (int i = 0; i < number_of_locks; i++) {
 275       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 276 #ifdef ASSERT
 277       // verify the interpreter's monitor has a non-null object
 278       {
 279         Label L;
 280         __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
 281         __ cbnz(rscratch1, L);
 282         __ stop("locked object is null");
 283         __ bind(L);
 284       }
 285 #endif
 286       __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
 287       __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
 288       __ str(r19, frame_map()->address_for_monitor_lock(i));
 289       __ str(r20, frame_map()->address_for_monitor_object(i));
 290     }
 291   }
 292 }
 293 
 294 
 295 // inline cache check; done before the frame is built.
 296 int LIR_Assembler::check_icache() {
 297   return __ ic_check(CodeEntryAlignment);
 298 }
 299 
 300 void LIR_Assembler::clinit_barrier(ciMethod* method) {
 301   assert(VM_Version::supports_fast_class_init_checks(), "sanity");
 302   assert(!method->holder()->is_not_initialized(), "initialization should have been started");
 303 
 304   Label L_skip_barrier;
 305 
 306   __ mov_metadata(rscratch2, method->holder()->constant_encoding());
 307   __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
 308   __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
 309   __ bind(L_skip_barrier);
 310 }
 311 
 312 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 313   if (o == nullptr) {
 314     __ mov(reg, zr);
 315   } else {
 316     __ movoop(reg, o);
 317   }
 318 }
 319 
 320 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
 321   address target = nullptr;
 322   relocInfo::relocType reloc_type = relocInfo::none;
 323 
 324   switch (patching_id(info)) {
 325   case PatchingStub::access_field_id:
 326     target = Runtime1::entry_for(C1StubId::access_field_patching_id);
 327     reloc_type = relocInfo::section_word_type;
 328     break;
 329   case PatchingStub::load_klass_id:
 330     target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
 331     reloc_type = relocInfo::metadata_type;
 332     break;
 333   case PatchingStub::load_mirror_id:
 334     target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
 335     reloc_type = relocInfo::oop_type;
 336     break;
 337   case PatchingStub::load_appendix_id:
 338     target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
 339     reloc_type = relocInfo::oop_type;
 340     break;
 341   default: ShouldNotReachHere();
 342   }
 343 
 344   __ far_call(RuntimeAddress(target));
 345   add_call_info_here(info);
 346 }
 347 
 348 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 349   deoptimize_trap(info);
 350 }
 351 
 352 
 353 // This specifies the rsp decrement needed to build the frame
 354 int LIR_Assembler::initial_frame_size_in_bytes() const {
 355   // if rounding, must let FrameMap know!
 356 
 357   return in_bytes(frame_map()->framesize_in_bytes());
 358 }
 359 
 360 
 361 int LIR_Assembler::emit_exception_handler() {
 362   // generate code for exception handler
 363   address handler_base = __ start_a_stub(exception_handler_size());
 364   if (handler_base == nullptr) {
 365     // not enough space left for the handler
 366     bailout("exception handler overflow");
 367     return -1;
 368   }
 369 
 370   int offset = code_offset();
 371 
 372   // the exception oop and pc are in r0, and r3
 373   // no other registers need to be preserved, so invalidate them
 374   __ invalidate_registers(false, true, true, false, true, true);
 375 
 376   // check that there is really an exception
 377   __ verify_not_null_oop(r0);
 378 
 379   // search an exception handler (r0: exception oop, r3: throwing pc)
 380   __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
 381   __ should_not_reach_here();
 382   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 383   __ end_a_stub();
 384 
 385   return offset;
 386 }
 387 
 388 
 389 // Emit the code to remove the frame from the stack in the exception
 390 // unwind path.
 391 int LIR_Assembler::emit_unwind_handler() {
 392 #ifndef PRODUCT
 393   if (CommentedAssembly) {
 394     _masm->block_comment("Unwind handler");
 395   }
 396 #endif
 397 
 398   int offset = code_offset();
 399 
 400   // Fetch the exception from TLS and clear out exception related thread state
 401   __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
 402   __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
 403   __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
 404 
 405   __ bind(_unwind_handler_entry);
 406   __ verify_not_null_oop(r0);
 407   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 408     __ mov(r19, r0);  // Preserve the exception
 409   }
 410 
 411   // Perform needed unlocking
 412   MonitorExitStub* stub = nullptr;
 413   if (method()->is_synchronized()) {
 414     monitor_address(0, FrameMap::r0_opr);
 415     stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
 416     if (LockingMode == LM_MONITOR) {
 417       __ b(*stub->entry());
 418     } else {
 419       __ unlock_object(r5, r4, r0, r6, *stub->entry());
 420     }
 421     __ bind(*stub->continuation());
 422   }
 423 
 424   if (compilation()->env()->dtrace_method_probes()) {
 425     __ mov(c_rarg0, rthread);
 426     __ mov_metadata(c_rarg1, method()->constant_encoding());
 427     __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
 428   }
 429 
 430   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 431     __ mov(r0, r19);  // Restore the exception
 432   }
 433 
 434   // remove the activation and dispatch to the unwind handler
 435   __ block_comment("remove_frame and dispatch to the unwind handler");
 436   __ remove_frame(initial_frame_size_in_bytes());
 437   __ far_jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
 438 
 439   // Emit the slow path assembly
 440   if (stub != nullptr) {
 441     stub->emit_code(this);
 442   }
 443 
 444   return offset;
 445 }
 446 
 447 
 448 int LIR_Assembler::emit_deopt_handler() {
 449   // generate code for exception handler
 450   address handler_base = __ start_a_stub(deopt_handler_size());
 451   if (handler_base == nullptr) {
 452     // not enough space left for the handler
 453     bailout("deopt handler overflow");
 454     return -1;
 455   }
 456 
 457   int offset = code_offset();
 458 
 459   __ adr(lr, pc());
 460   __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 461   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 462   __ end_a_stub();
 463 
 464   return offset;
 465 }
 466 
 467 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
 468   _masm->code_section()->relocate(adr, relocInfo::poll_type);
 469   int pc_offset = code_offset();
 470   flush_debug_info(pc_offset);
 471   info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
 472   if (info->exception_handlers() != nullptr) {
 473     compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
 474   }
 475 }
 476 
 477 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
 478   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
 479 
 480   // Pop the stack before the safepoint code
 481   __ remove_frame(initial_frame_size_in_bytes());
 482 
 483   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 484     __ reserved_stack_check();
 485   }
 486 
 487   code_stub->set_safepoint_offset(__ offset());
 488   __ relocate(relocInfo::poll_return_type);
 489   __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
 490   __ ret(lr);
 491 }
 492 
 493 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 494   guarantee(info != nullptr, "Shouldn't be null");
 495   __ get_polling_page(rscratch1, relocInfo::poll_type);
 496   add_debug_info_for_branch(info);  // This isn't just debug info:
 497                                     // it's the oop map
 498   __ read_polling_page(rscratch1, relocInfo::poll_type);
 499   return __ offset();
 500 }
 501 
 502 
 503 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 504   if (from_reg == r31_sp)
 505     from_reg = sp;
 506   if (to_reg == r31_sp)
 507     to_reg = sp;
 508   __ mov(to_reg, from_reg);
 509 }
 510 
 511 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
 512 
 513 
 514 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 515   assert(src->is_constant(), "should not call otherwise");
 516   assert(dest->is_register(), "should not call otherwise");
 517   LIR_Const* c = src->as_constant_ptr();
 518 
 519   switch (c->type()) {
 520     case T_INT: {
 521       assert(patch_code == lir_patch_none, "no patching handled here");
 522       __ movw(dest->as_register(), c->as_jint());
 523       break;
 524     }
 525 
 526     case T_ADDRESS: {
 527       assert(patch_code == lir_patch_none, "no patching handled here");
 528       __ mov(dest->as_register(), c->as_jint());
 529       break;
 530     }
 531 
 532     case T_LONG: {
 533       assert(patch_code == lir_patch_none, "no patching handled here");
 534       if (AOTCodeCache::is_on_for_dump()) {
 535         // AOT code needs relocation info for card table base
 536         address b = c->as_pointer();
 537         if (is_card_table_address(b)) {
 538           __ lea(dest->as_register_lo(), ExternalAddress(b));
 539           break;
 540         }
 541         if (b == (address)ThreadIdentifier::unsafe_offset()) {
 542           __ lea(dest->as_register_lo(), ExternalAddress(b));
 543           break;
 544         }
 545 #if INCLUDE_CDS
 546         if (AOTRuntimeConstants::contains(b)) {
 547           __ load_aotrc_address(dest->as_register_lo(), b);
 548           break;
 549         }
 550 #endif
 551       }
 552       __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
 553       break;
 554     }
 555 
 556     case T_OBJECT: {
 557         if (patch_code == lir_patch_none) {
 558           jobject2reg(c->as_jobject(), dest->as_register());
 559         } else {
 560           jobject2reg_with_patching(dest->as_register(), info);
 561         }
 562       break;
 563     }
 564 
 565     case T_METADATA: {
 566       if (patch_code != lir_patch_none) {
 567         klass2reg_with_patching(dest->as_register(), info);
 568       } else {
 569         __ mov_metadata(dest->as_register(), c->as_metadata());
 570       }
 571       break;
 572     }
 573 
 574     case T_FLOAT: {
 575       if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
 576         __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
 577       } else {
 578         __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
 579         __ ldrs(dest->as_float_reg(), Address(rscratch1));
 580       }
 581       break;
 582     }
 583 
 584     case T_DOUBLE: {
 585       if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
 586         __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
 587       } else {
 588         __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
 589         __ ldrd(dest->as_double_reg(), Address(rscratch1));
 590       }
 591       break;
 592     }
 593 
 594     default:
 595       ShouldNotReachHere();
 596   }
 597 }
 598 
 599 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 600   LIR_Const* c = src->as_constant_ptr();
 601   switch (c->type()) {
 602   case T_OBJECT:
 603     {
 604       if (! c->as_jobject())
 605         __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 606       else {
 607         const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
 608         reg2stack(FrameMap::rscratch1_opr, dest, c->type());
 609       }
 610     }
 611     break;
 612   case T_ADDRESS:
 613     {
 614       const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
 615       reg2stack(FrameMap::rscratch1_opr, dest, c->type());
 616     }
 617   case T_INT:
 618   case T_FLOAT:
 619     {
 620       Register reg = zr;
 621       if (c->as_jint_bits() == 0)
 622         __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 623       else {
 624         __ movw(rscratch1, c->as_jint_bits());
 625         __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
 626       }
 627     }
 628     break;
 629   case T_LONG:
 630   case T_DOUBLE:
 631     {
 632       Register reg = zr;
 633       if (c->as_jlong_bits() == 0)
 634         __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
 635                                                  lo_word_offset_in_bytes));
 636       else {
 637         __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
 638         __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
 639                                                         lo_word_offset_in_bytes));
 640       }
 641     }
 642     break;
 643   default:
 644     ShouldNotReachHere();
 645   }
 646 }
 647 
 648 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 649   assert(src->is_constant(), "should not call otherwise");
 650   LIR_Const* c = src->as_constant_ptr();
 651   LIR_Address* to_addr = dest->as_address_ptr();
 652 
 653   void (Assembler::* insn)(Register Rt, const Address &adr);
 654 
 655   switch (type) {
 656   case T_ADDRESS:
 657     assert(c->as_jint() == 0, "should be");
 658     insn = &Assembler::str;
 659     break;
 660   case T_LONG:
 661     assert(c->as_jlong() == 0, "should be");
 662     insn = &Assembler::str;
 663     break;
 664   case T_INT:
 665     assert(c->as_jint() == 0, "should be");
 666     insn = &Assembler::strw;
 667     break;
 668   case T_OBJECT:
 669   case T_ARRAY:
 670     assert(c->as_jobject() == nullptr, "should be");
 671     if (UseCompressedOops && !wide) {
 672       insn = &Assembler::strw;
 673     } else {
 674       insn = &Assembler::str;
 675     }
 676     break;
 677   case T_CHAR:
 678   case T_SHORT:
 679     assert(c->as_jint() == 0, "should be");
 680     insn = &Assembler::strh;
 681     break;
 682   case T_BOOLEAN:
 683   case T_BYTE:
 684     assert(c->as_jint() == 0, "should be");
 685     insn = &Assembler::strb;
 686     break;
 687   default:
 688     ShouldNotReachHere();
 689     insn = &Assembler::str;  // unreachable
 690   }
 691 
 692   if (info) add_debug_info_for_null_check_here(info);
 693   (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
 694 }
 695 
 696 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 697   assert(src->is_register(), "should not call otherwise");
 698   assert(dest->is_register(), "should not call otherwise");
 699 
 700   // move between cpu-registers
 701   if (dest->is_single_cpu()) {
 702     if (src->type() == T_LONG) {
 703       // Can do LONG -> OBJECT
 704       move_regs(src->as_register_lo(), dest->as_register());
 705       return;
 706     }
 707     assert(src->is_single_cpu(), "must match");
 708     if (src->type() == T_OBJECT) {
 709       __ verify_oop(src->as_register());
 710     }
 711     move_regs(src->as_register(), dest->as_register());
 712 
 713   } else if (dest->is_double_cpu()) {
 714     if (is_reference_type(src->type())) {
 715       // Surprising to me but we can see move of a long to t_object
 716       __ verify_oop(src->as_register());
 717       move_regs(src->as_register(), dest->as_register_lo());
 718       return;
 719     }
 720     assert(src->is_double_cpu(), "must match");
 721     Register f_lo = src->as_register_lo();
 722     Register f_hi = src->as_register_hi();
 723     Register t_lo = dest->as_register_lo();
 724     Register t_hi = dest->as_register_hi();
 725     assert(f_hi == f_lo, "must be same");
 726     assert(t_hi == t_lo, "must be same");
 727     move_regs(f_lo, t_lo);
 728 
 729   } else if (dest->is_single_fpu()) {
 730     __ fmovs(dest->as_float_reg(), src->as_float_reg());
 731 
 732   } else if (dest->is_double_fpu()) {
 733     __ fmovd(dest->as_double_reg(), src->as_double_reg());
 734 
 735   } else {
 736     ShouldNotReachHere();
 737   }
 738 }
 739 
 740 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
 741   precond(src->is_register() && dest->is_stack());
 742 
 743   uint const c_sz32 = sizeof(uint32_t);
 744   uint const c_sz64 = sizeof(uint64_t);
 745 
 746   if (src->is_single_cpu()) {
 747     int index = dest->single_stack_ix();
 748     if (is_reference_type(type)) {
 749       __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 750       __ verify_oop(src->as_register());
 751     } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
 752       __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 753     } else {
 754       __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
 755     }
 756 
 757   } else if (src->is_double_cpu()) {
 758     int index = dest->double_stack_ix();
 759     Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
 760     __ str(src->as_register_lo(), dest_addr_LO);
 761 
 762   } else if (src->is_single_fpu()) {
 763     int index = dest->single_stack_ix();
 764     __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
 765 
 766   } else if (src->is_double_fpu()) {
 767     int index = dest->double_stack_ix();
 768     __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
 769 
 770   } else {
 771     ShouldNotReachHere();
 772   }
 773 }
 774 
 775 
 776 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
 777   LIR_Address* to_addr = dest->as_address_ptr();
 778   PatchingStub* patch = nullptr;
 779   Register compressed_src = rscratch1;
 780 
 781   if (patch_code != lir_patch_none) {
 782     deoptimize_trap(info);
 783     return;
 784   }
 785 
 786   if (is_reference_type(type)) {
 787     __ verify_oop(src->as_register());
 788 
 789     if (UseCompressedOops && !wide) {
 790       __ encode_heap_oop(compressed_src, src->as_register());
 791     } else {
 792       compressed_src = src->as_register();
 793     }
 794   }
 795 
 796   int null_check_here = code_offset();
 797   switch (type) {
 798     case T_FLOAT: {
 799       __ strs(src->as_float_reg(), as_Address(to_addr));
 800       break;
 801     }
 802 
 803     case T_DOUBLE: {
 804       __ strd(src->as_double_reg(), as_Address(to_addr));
 805       break;
 806     }
 807 
 808     case T_ARRAY:   // fall through
 809     case T_OBJECT:  // fall through
 810       if (UseCompressedOops && !wide) {
 811         __ strw(compressed_src, as_Address(to_addr, rscratch2));
 812       } else {
 813          __ str(compressed_src, as_Address(to_addr));
 814       }
 815       break;
 816     case T_METADATA:
 817       // We get here to store a method pointer to the stack to pass to
 818       // a dtrace runtime call. This can't work on 64 bit with
 819       // compressed klass ptrs: T_METADATA can be a compressed klass
 820       // ptr or a 64 bit method pointer.
 821       ShouldNotReachHere();
 822       __ str(src->as_register(), as_Address(to_addr));
 823       break;
 824     case T_ADDRESS:
 825       __ str(src->as_register(), as_Address(to_addr));
 826       break;
 827     case T_INT:
 828       __ strw(src->as_register(), as_Address(to_addr));
 829       break;
 830 
 831     case T_LONG: {
 832       __ str(src->as_register_lo(), as_Address_lo(to_addr));
 833       break;
 834     }
 835 
 836     case T_BYTE:    // fall through
 837     case T_BOOLEAN: {
 838       __ strb(src->as_register(), as_Address(to_addr));
 839       break;
 840     }
 841 
 842     case T_CHAR:    // fall through
 843     case T_SHORT:
 844       __ strh(src->as_register(), as_Address(to_addr));
 845       break;
 846 
 847     default:
 848       ShouldNotReachHere();
 849   }
 850   if (info != nullptr) {
 851     add_debug_info_for_null_check(null_check_here, info);
 852   }
 853 }
 854 
 855 
 856 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
 857   precond(src->is_stack() && dest->is_register());
 858 
 859   uint const c_sz32 = sizeof(uint32_t);
 860   uint const c_sz64 = sizeof(uint64_t);
 861 
 862   if (dest->is_single_cpu()) {
 863     int index = src->single_stack_ix();
 864     if (is_reference_type(type)) {
 865       __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 866       __ verify_oop(dest->as_register());
 867     } else if (type == T_METADATA || type == T_ADDRESS) {
 868       __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 869     } else {
 870       __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
 871     }
 872 
 873   } else if (dest->is_double_cpu()) {
 874     int index = src->double_stack_ix();
 875     Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
 876     __ ldr(dest->as_register_lo(), src_addr_LO);
 877 
 878   } else if (dest->is_single_fpu()) {
 879     int index = src->single_stack_ix();
 880     __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
 881 
 882   } else if (dest->is_double_fpu()) {
 883     int index = src->double_stack_ix();
 884     __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
 885 
 886   } else {
 887     ShouldNotReachHere();
 888   }
 889 }
 890 
 891 
 892 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 893   address target = nullptr;
 894   relocInfo::relocType reloc_type = relocInfo::none;
 895 
 896   switch (patching_id(info)) {
 897   case PatchingStub::access_field_id:
 898     target = Runtime1::entry_for(C1StubId::access_field_patching_id);
 899     reloc_type = relocInfo::section_word_type;
 900     break;
 901   case PatchingStub::load_klass_id:
 902     target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
 903     reloc_type = relocInfo::metadata_type;
 904     break;
 905   case PatchingStub::load_mirror_id:
 906     target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
 907     reloc_type = relocInfo::oop_type;
 908     break;
 909   case PatchingStub::load_appendix_id:
 910     target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
 911     reloc_type = relocInfo::oop_type;
 912     break;
 913   default: ShouldNotReachHere();
 914   }
 915 
 916   __ far_call(RuntimeAddress(target));
 917   add_call_info_here(info);
 918 }
 919 
 920 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
 921 
 922   LIR_Opr temp;
 923   if (type == T_LONG || type == T_DOUBLE)
 924     temp = FrameMap::rscratch1_long_opr;
 925   else
 926     temp = FrameMap::rscratch1_opr;
 927 
 928   stack2reg(src, temp, src->type());
 929   reg2stack(temp, dest, dest->type());
 930 }
 931 
 932 
 933 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
 934   LIR_Address* addr = src->as_address_ptr();
 935   LIR_Address* from_addr = src->as_address_ptr();
 936 
 937   if (addr->base()->type() == T_OBJECT) {
 938     __ verify_oop(addr->base()->as_pointer_register());
 939   }
 940 
 941   if (patch_code != lir_patch_none) {
 942     deoptimize_trap(info);
 943     return;
 944   }
 945 
 946   if (info != nullptr) {
 947     add_debug_info_for_null_check_here(info);
 948   }
 949   int null_check_here = code_offset();
 950   switch (type) {
 951     case T_FLOAT: {
 952       __ ldrs(dest->as_float_reg(), as_Address(from_addr));
 953       break;
 954     }
 955 
 956     case T_DOUBLE: {
 957       __ ldrd(dest->as_double_reg(), as_Address(from_addr));
 958       break;
 959     }
 960 
 961     case T_ARRAY:   // fall through
 962     case T_OBJECT:  // fall through
 963       if (UseCompressedOops && !wide) {
 964         __ ldrw(dest->as_register(), as_Address(from_addr));
 965       } else {
 966         __ ldr(dest->as_register(), as_Address(from_addr));
 967       }
 968       break;
 969     case T_METADATA:
 970       // We get here to store a method pointer to the stack to pass to
 971       // a dtrace runtime call. This can't work on 64 bit with
 972       // compressed klass ptrs: T_METADATA can be a compressed klass
 973       // ptr or a 64 bit method pointer.
 974       ShouldNotReachHere();
 975       __ ldr(dest->as_register(), as_Address(from_addr));
 976       break;
 977     case T_ADDRESS:
 978       __ ldr(dest->as_register(), as_Address(from_addr));
 979       break;
 980     case T_INT:
 981       __ ldrw(dest->as_register(), as_Address(from_addr));
 982       break;
 983 
 984     case T_LONG: {
 985       __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
 986       break;
 987     }
 988 
 989     case T_BYTE:
 990       __ ldrsb(dest->as_register(), as_Address(from_addr));
 991       break;
 992     case T_BOOLEAN: {
 993       __ ldrb(dest->as_register(), as_Address(from_addr));
 994       break;
 995     }
 996 
 997     case T_CHAR:
 998       __ ldrh(dest->as_register(), as_Address(from_addr));
 999       break;
1000     case T_SHORT:
1001       __ ldrsh(dest->as_register(), as_Address(from_addr));
1002       break;
1003 
1004     default:
1005       ShouldNotReachHere();
1006   }
1007 
1008   if (is_reference_type(type)) {
1009     if (UseCompressedOops && !wide) {
1010       __ decode_heap_oop(dest->as_register());
1011     }
1012 
1013     __ verify_oop(dest->as_register());
1014   }
1015 }
1016 
1017 
1018 int LIR_Assembler::array_element_size(BasicType type) const {
1019   int elem_size = type2aelembytes(type);
1020   return exact_log2(elem_size);
1021 }
1022 
1023 
1024 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1025   switch (op->code()) {
1026   case lir_idiv:
1027   case lir_irem:
1028     arithmetic_idiv(op->code(),
1029                     op->in_opr1(),
1030                     op->in_opr2(),
1031                     op->in_opr3(),
1032                     op->result_opr(),
1033                     op->info());
1034     break;
1035   case lir_fmad:
1036     __ fmaddd(op->result_opr()->as_double_reg(),
1037               op->in_opr1()->as_double_reg(),
1038               op->in_opr2()->as_double_reg(),
1039               op->in_opr3()->as_double_reg());
1040     break;
1041   case lir_fmaf:
1042     __ fmadds(op->result_opr()->as_float_reg(),
1043               op->in_opr1()->as_float_reg(),
1044               op->in_opr2()->as_float_reg(),
1045               op->in_opr3()->as_float_reg());
1046     break;
1047   default:      ShouldNotReachHere(); break;
1048   }
1049 }
1050 
1051 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1052 #ifdef ASSERT
1053   assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1054   if (op->block() != nullptr)  _branch_target_blocks.append(op->block());
1055   if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1056 #endif
1057 
1058   if (op->cond() == lir_cond_always) {
1059     if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1060     __ b(*(op->label()));
1061   } else {
1062     Assembler::Condition acond;
1063     if (op->code() == lir_cond_float_branch) {
1064       bool is_unordered = (op->ublock() == op->block());
1065       // Assembler::EQ does not permit unordered branches, so we add
1066       // another branch here.  Likewise, Assembler::NE does not permit
1067       // ordered branches.
1068       if ((is_unordered && op->cond() == lir_cond_equal)
1069           || (!is_unordered && op->cond() == lir_cond_notEqual))
1070         __ br(Assembler::VS, *(op->ublock()->label()));
1071       switch(op->cond()) {
1072       case lir_cond_equal:        acond = Assembler::EQ; break;
1073       case lir_cond_notEqual:     acond = Assembler::NE; break;
1074       case lir_cond_less:         acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1075       case lir_cond_lessEqual:    acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1076       case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1077       case lir_cond_greater:      acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1078       default:                    ShouldNotReachHere();
1079         acond = Assembler::EQ;  // unreachable
1080       }
1081     } else {
1082       switch (op->cond()) {
1083         case lir_cond_equal:        acond = Assembler::EQ; break;
1084         case lir_cond_notEqual:     acond = Assembler::NE; break;
1085         case lir_cond_less:         acond = Assembler::LT; break;
1086         case lir_cond_lessEqual:    acond = Assembler::LE; break;
1087         case lir_cond_greaterEqual: acond = Assembler::GE; break;
1088         case lir_cond_greater:      acond = Assembler::GT; break;
1089         case lir_cond_belowEqual:   acond = Assembler::LS; break;
1090         case lir_cond_aboveEqual:   acond = Assembler::HS; break;
1091         default:                    ShouldNotReachHere();
1092           acond = Assembler::EQ;  // unreachable
1093       }
1094     }
1095     __ br(acond,*(op->label()));
1096   }
1097 }
1098 
1099 
1100 
1101 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1102   LIR_Opr src  = op->in_opr();
1103   LIR_Opr dest = op->result_opr();
1104 
1105   switch (op->bytecode()) {
1106     case Bytecodes::_i2f:
1107       {
1108         __ scvtfws(dest->as_float_reg(), src->as_register());
1109         break;
1110       }
1111     case Bytecodes::_i2d:
1112       {
1113         __ scvtfwd(dest->as_double_reg(), src->as_register());
1114         break;
1115       }
1116     case Bytecodes::_l2d:
1117       {
1118         __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1119         break;
1120       }
1121     case Bytecodes::_l2f:
1122       {
1123         __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1124         break;
1125       }
1126     case Bytecodes::_f2d:
1127       {
1128         __ fcvts(dest->as_double_reg(), src->as_float_reg());
1129         break;
1130       }
1131     case Bytecodes::_d2f:
1132       {
1133         __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1134         break;
1135       }
1136     case Bytecodes::_i2c:
1137       {
1138         __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1139         break;
1140       }
1141     case Bytecodes::_i2l:
1142       {
1143         __ sxtw(dest->as_register_lo(), src->as_register());
1144         break;
1145       }
1146     case Bytecodes::_i2s:
1147       {
1148         __ sxth(dest->as_register(), src->as_register());
1149         break;
1150       }
1151     case Bytecodes::_i2b:
1152       {
1153         __ sxtb(dest->as_register(), src->as_register());
1154         break;
1155       }
1156     case Bytecodes::_l2i:
1157       {
1158         _masm->block_comment("FIXME: This could be a no-op");
1159         __ uxtw(dest->as_register(), src->as_register_lo());
1160         break;
1161       }
1162     case Bytecodes::_d2l:
1163       {
1164         __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1165         break;
1166       }
1167     case Bytecodes::_f2i:
1168       {
1169         __ fcvtzsw(dest->as_register(), src->as_float_reg());
1170         break;
1171       }
1172     case Bytecodes::_f2l:
1173       {
1174         __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1175         break;
1176       }
1177     case Bytecodes::_d2i:
1178       {
1179         __ fcvtzdw(dest->as_register(), src->as_double_reg());
1180         break;
1181       }
1182     default: ShouldNotReachHere();
1183   }
1184 }
1185 
1186 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1187   if (op->init_check()) {
1188     __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1189     __ ldarb(rscratch1, rscratch1);
1190     __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1191     add_debug_info_for_null_check_here(op->stub()->info());
1192     __ br(Assembler::NE, *op->stub()->entry());
1193   }
1194   __ allocate_object(op->obj()->as_register(),
1195                      op->tmp1()->as_register(),
1196                      op->tmp2()->as_register(),
1197                      op->header_size(),
1198                      op->object_size(),
1199                      op->klass()->as_register(),
1200                      *op->stub()->entry());
1201   __ bind(*op->stub()->continuation());
1202 }
1203 
1204 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1205   Register len =  op->len()->as_register();
1206   __ uxtw(len, len);
1207 
1208   if (UseSlowPath ||
1209       (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1210       (!UseFastNewTypeArray   && !is_reference_type(op->type()))) {
1211     __ b(*op->stub()->entry());
1212   } else {
1213     Register tmp1 = op->tmp1()->as_register();
1214     Register tmp2 = op->tmp2()->as_register();
1215     Register tmp3 = op->tmp3()->as_register();
1216     if (len == tmp1) {
1217       tmp1 = tmp3;
1218     } else if (len == tmp2) {
1219       tmp2 = tmp3;
1220     } else if (len == tmp3) {
1221       // everything is ok
1222     } else {
1223       __ mov(tmp3, len);
1224     }
1225     __ allocate_array(op->obj()->as_register(),
1226                       len,
1227                       tmp1,
1228                       tmp2,
1229                       arrayOopDesc::base_offset_in_bytes(op->type()),
1230                       array_element_size(op->type()),
1231                       op->klass()->as_register(),
1232                       *op->stub()->entry(),
1233                       op->zero_array());
1234   }
1235   __ bind(*op->stub()->continuation());
1236 }
1237 
1238 void LIR_Assembler::type_profile_helper(Register mdo,
1239                                         ciMethodData *md, ciProfileData *data,
1240                                         Register recv, Label* update_done) {
1241 
1242   // Given a profile data offset, generate an Address which points to
1243   // the corresponding slot in mdo->data().
1244   // Clobbers rscratch2.
1245   auto slot_at = [=](ByteSize offset) -> Address {
1246     return __ form_address(rscratch2, mdo,
1247                            md->byte_offset_of_slot(data, offset),
1248                            LogBytesPerWord);
1249   };
1250 
1251   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1252     Label next_test;
1253     // See if the receiver is receiver[n].
1254     __ ldr(rscratch1, slot_at(ReceiverTypeData::receiver_offset(i)));
1255     __ cmp(recv, rscratch1);
1256     __ br(Assembler::NE, next_test);
1257     __ addptr(slot_at(ReceiverTypeData::receiver_count_offset(i)),
1258               DataLayout::counter_increment);
1259     __ b(*update_done);
1260     __ bind(next_test);
1261   }
1262 
1263   // Didn't find receiver; find next empty slot and fill it in
1264   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1265     Label next_test;
1266     Address recv_addr(slot_at(ReceiverTypeData::receiver_offset(i)));
1267     __ ldr(rscratch1, recv_addr);
1268     __ cbnz(rscratch1, next_test);
1269     __ str(recv, recv_addr);
1270     __ mov(rscratch1, DataLayout::counter_increment);
1271     __ str(rscratch1, slot_at(ReceiverTypeData::receiver_count_offset(i)));
1272     __ b(*update_done);
1273     __ bind(next_test);
1274   }
1275 }
1276 
1277 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1278   // we always need a stub for the failure case.
1279   CodeStub* stub = op->stub();
1280   Register obj = op->object()->as_register();
1281   Register k_RInfo = op->tmp1()->as_register();
1282   Register klass_RInfo = op->tmp2()->as_register();
1283   Register dst = op->result_opr()->as_register();
1284   ciKlass* k = op->klass();
1285   Register Rtmp1 = noreg;
1286 
1287   // check if it needs to be profiled
1288   ciMethodData* md;
1289   ciProfileData* data;
1290 
1291   const bool should_profile = op->should_profile();
1292 
1293   if (should_profile) {
1294     ciMethod* method = op->profiled_method();
1295     assert(method != nullptr, "Should have method");
1296     int bci = op->profiled_bci();
1297     md = method->method_data_or_null();
1298     assert(md != nullptr, "Sanity");
1299     data = md->bci_to_data(bci);
1300     assert(data != nullptr,                "need data for type check");
1301     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1302   }
1303   Label* success_target = success;
1304   Label* failure_target = failure;
1305 
1306   if (obj == k_RInfo) {
1307     k_RInfo = dst;
1308   } else if (obj == klass_RInfo) {
1309     klass_RInfo = dst;
1310   }
1311   if (k->is_loaded() && !UseCompressedClassPointers) {
1312     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1313   } else {
1314     Rtmp1 = op->tmp3()->as_register();
1315     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1316   }
1317 
1318   assert_different_registers(obj, k_RInfo, klass_RInfo);
1319 
1320   if (should_profile) {
1321     Register mdo  = klass_RInfo;
1322     __ mov_metadata(mdo, md->constant_encoding());
1323     Label not_null;
1324     __ cbnz(obj, not_null);
1325     // Object is null; update MDO and exit
1326     Address data_addr
1327       = __ form_address(rscratch2, mdo,
1328                         md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1329                         0);
1330     __ ldrb(rscratch1, data_addr);
1331     __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1332     __ strb(rscratch1, data_addr);
1333     __ b(*obj_is_null);
1334     __ bind(not_null);
1335 
1336     Label update_done;
1337     Register recv = k_RInfo;
1338     __ load_klass(recv, obj);
1339     type_profile_helper(mdo, md, data, recv, &update_done);
1340     Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1341     __ addptr(counter_addr, DataLayout::counter_increment);
1342 
1343     __ bind(update_done);
1344   } else {
1345     __ cbz(obj, *obj_is_null);
1346   }
1347 
1348   if (!k->is_loaded()) {
1349     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1350   } else {
1351     __ mov_metadata(k_RInfo, k->constant_encoding());
1352   }
1353   __ verify_oop(obj);
1354 
1355   if (op->fast_check()) {
1356     // get object class
1357     // not a safepoint as obj null check happens earlier
1358     __ load_klass(rscratch1, obj);
1359     __ cmp( rscratch1, k_RInfo);
1360 
1361     __ br(Assembler::NE, *failure_target);
1362     // successful cast, fall through to profile or jump
1363   } else {
1364     // get object class
1365     // not a safepoint as obj null check happens earlier
1366     __ load_klass(klass_RInfo, obj);
1367     if (k->is_loaded()) {
1368       // See if we get an immediate positive hit
1369       __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1370       __ cmp(k_RInfo, rscratch1);
1371       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1372         __ br(Assembler::NE, *failure_target);
1373         // successful cast, fall through to profile or jump
1374       } else {
1375         // See if we get an immediate positive hit
1376         __ br(Assembler::EQ, *success_target);
1377         // check for self
1378         __ cmp(klass_RInfo, k_RInfo);
1379         __ br(Assembler::EQ, *success_target);
1380 
1381         __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1382         __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1383         __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1384         // result is a boolean
1385         __ cbzw(klass_RInfo, *failure_target);
1386         // successful cast, fall through to profile or jump
1387       }
1388     } else {
1389       // perform the fast part of the checking logic
1390       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1391       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1392       __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1393       __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1394       __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1395       // result is a boolean
1396       __ cbz(k_RInfo, *failure_target);
1397       // successful cast, fall through to profile or jump
1398     }
1399   }
1400   __ b(*success);
1401 }
1402 
1403 
1404 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1405   const bool should_profile = op->should_profile();
1406 
1407   LIR_Code code = op->code();
1408   if (code == lir_store_check) {
1409     Register value = op->object()->as_register();
1410     Register array = op->array()->as_register();
1411     Register k_RInfo = op->tmp1()->as_register();
1412     Register klass_RInfo = op->tmp2()->as_register();
1413     Register Rtmp1 = op->tmp3()->as_register();
1414 
1415     CodeStub* stub = op->stub();
1416 
1417     // check if it needs to be profiled
1418     ciMethodData* md;
1419     ciProfileData* data;
1420 
1421     if (should_profile) {
1422       ciMethod* method = op->profiled_method();
1423       assert(method != nullptr, "Should have method");
1424       int bci = op->profiled_bci();
1425       md = method->method_data_or_null();
1426       assert(md != nullptr, "Sanity");
1427       data = md->bci_to_data(bci);
1428       assert(data != nullptr,                "need data for type check");
1429       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1430     }
1431     Label done;
1432     Label* success_target = &done;
1433     Label* failure_target = stub->entry();
1434 
1435     if (should_profile) {
1436       Label not_null;
1437       Register mdo  = klass_RInfo;
1438       __ mov_metadata(mdo, md->constant_encoding());
1439       __ cbnz(value, not_null);
1440       // Object is null; update MDO and exit
1441       Address data_addr
1442         = __ form_address(rscratch2, mdo,
1443                           md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1444       __ ldrb(rscratch1, data_addr);
1445       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1446       __ strb(rscratch1, data_addr);
1447       __ b(done);
1448       __ bind(not_null);
1449 
1450       Label update_done;
1451       Register recv = k_RInfo;
1452       __ load_klass(recv, value);
1453       type_profile_helper(mdo, md, data, recv, &update_done);
1454       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1455       __ addptr(counter_addr, DataLayout::counter_increment);
1456       __ bind(update_done);
1457     } else {
1458       __ cbz(value, done);
1459     }
1460 
1461     add_debug_info_for_null_check_here(op->info_for_exception());
1462     __ load_klass(k_RInfo, array);
1463     __ load_klass(klass_RInfo, value);
1464 
1465     // get instance klass (it's already uncompressed)
1466     __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1467     // perform the fast part of the checking logic
1468     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1469     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1470     __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1471     __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1472     __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1473     // result is a boolean
1474     __ cbzw(k_RInfo, *failure_target);
1475     // fall through to the success case
1476 
1477     __ bind(done);
1478   } else if (code == lir_checkcast) {
1479     Register obj = op->object()->as_register();
1480     Register dst = op->result_opr()->as_register();
1481     Label success;
1482     emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1483     __ bind(success);
1484     if (dst != obj) {
1485       __ mov(dst, obj);
1486     }
1487   } else if (code == lir_instanceof) {
1488     Register obj = op->object()->as_register();
1489     Register dst = op->result_opr()->as_register();
1490     Label success, failure, done;
1491     emit_typecheck_helper(op, &success, &failure, &failure);
1492     __ bind(failure);
1493     __ mov(dst, zr);
1494     __ b(done);
1495     __ bind(success);
1496     __ mov(dst, 1);
1497     __ bind(done);
1498   } else {
1499     ShouldNotReachHere();
1500   }
1501 }
1502 
1503 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1504   __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1505   __ cset(rscratch1, Assembler::NE);
1506   __ membar(__ AnyAny);
1507 }
1508 
1509 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1510   __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1511   __ cset(rscratch1, Assembler::NE);
1512   __ membar(__ AnyAny);
1513 }
1514 
1515 
1516 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1517   Register addr;
1518   if (op->addr()->is_register()) {
1519     addr = as_reg(op->addr());
1520   } else {
1521     assert(op->addr()->is_address(), "what else?");
1522     LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1523     assert(addr_ptr->disp() == 0, "need 0 disp");
1524     assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1525     addr = as_reg(addr_ptr->base());
1526   }
1527   Register newval = as_reg(op->new_value());
1528   Register cmpval = as_reg(op->cmp_value());
1529 
1530   if (op->code() == lir_cas_obj) {
1531     if (UseCompressedOops) {
1532       Register t1 = op->tmp1()->as_register();
1533       assert(op->tmp1()->is_valid(), "must be");
1534       __ encode_heap_oop(t1, cmpval);
1535       cmpval = t1;
1536       __ encode_heap_oop(rscratch2, newval);
1537       newval = rscratch2;
1538       casw(addr, newval, cmpval);
1539     } else {
1540       casl(addr, newval, cmpval);
1541     }
1542   } else if (op->code() == lir_cas_int) {
1543     casw(addr, newval, cmpval);
1544   } else {
1545     casl(addr, newval, cmpval);
1546   }
1547 }
1548 
1549 
1550 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1551                           LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1552   assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1553 
1554   Assembler::Condition acond, ncond;
1555   switch (condition) {
1556   case lir_cond_equal:        acond = Assembler::EQ; ncond = Assembler::NE; break;
1557   case lir_cond_notEqual:     acond = Assembler::NE; ncond = Assembler::EQ; break;
1558   case lir_cond_less:         acond = Assembler::LT; ncond = Assembler::GE; break;
1559   case lir_cond_lessEqual:    acond = Assembler::LE; ncond = Assembler::GT; break;
1560   case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1561   case lir_cond_greater:      acond = Assembler::GT; ncond = Assembler::LE; break;
1562   case lir_cond_belowEqual:
1563   case lir_cond_aboveEqual:
1564   default:                    ShouldNotReachHere();
1565     acond = Assembler::EQ; ncond = Assembler::NE;  // unreachable
1566   }
1567 
1568   assert(result->is_single_cpu() || result->is_double_cpu(),
1569          "expect single register for result");
1570   if (opr1->is_constant() && opr2->is_constant()
1571       && opr1->type() == T_INT && opr2->type() == T_INT) {
1572     jint val1 = opr1->as_jint();
1573     jint val2 = opr2->as_jint();
1574     if (val1 == 0 && val2 == 1) {
1575       __ cset(result->as_register(), ncond);
1576       return;
1577     } else if (val1 == 1 && val2 == 0) {
1578       __ cset(result->as_register(), acond);
1579       return;
1580     }
1581   }
1582 
1583   if (opr1->is_constant() && opr2->is_constant()
1584       && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1585     jlong val1 = opr1->as_jlong();
1586     jlong val2 = opr2->as_jlong();
1587     if (val1 == 0 && val2 == 1) {
1588       __ cset(result->as_register_lo(), ncond);
1589       return;
1590     } else if (val1 == 1 && val2 == 0) {
1591       __ cset(result->as_register_lo(), acond);
1592       return;
1593     }
1594   }
1595 
1596   if (opr1->is_stack()) {
1597     stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1598     opr1 = FrameMap::rscratch1_opr;
1599   } else if (opr1->is_constant()) {
1600     LIR_Opr tmp
1601       = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1602     const2reg(opr1, tmp, lir_patch_none, nullptr);
1603     opr1 = tmp;
1604   }
1605 
1606   if (opr2->is_stack()) {
1607     stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1608     opr2 = FrameMap::rscratch2_opr;
1609   } else if (opr2->is_constant()) {
1610     LIR_Opr tmp
1611       = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1612     const2reg(opr2, tmp, lir_patch_none, nullptr);
1613     opr2 = tmp;
1614   }
1615 
1616   if (result->type() == T_LONG)
1617     __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1618   else
1619     __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1620 }
1621 
1622 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1623   assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1624 
1625   if (left->is_single_cpu()) {
1626     Register lreg = left->as_register();
1627     Register dreg = as_reg(dest);
1628 
1629     if (right->is_single_cpu()) {
1630       // cpu register - cpu register
1631 
1632       assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1633              "should be");
1634       Register rreg = right->as_register();
1635       switch (code) {
1636       case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1637       case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1638       case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1639       default:      ShouldNotReachHere();
1640       }
1641 
1642     } else if (right->is_double_cpu()) {
1643       Register rreg = right->as_register_lo();
1644       // single_cpu + double_cpu: can happen with obj+long
1645       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1646       switch (code) {
1647       case lir_add: __ add(dreg, lreg, rreg); break;
1648       case lir_sub: __ sub(dreg, lreg, rreg); break;
1649       default: ShouldNotReachHere();
1650       }
1651     } else if (right->is_constant()) {
1652       // cpu register - constant
1653       jlong c;
1654 
1655       // FIXME.  This is fugly: we really need to factor all this logic.
1656       switch(right->type()) {
1657       case T_LONG:
1658         c = right->as_constant_ptr()->as_jlong();
1659         break;
1660       case T_INT:
1661       case T_ADDRESS:
1662         c = right->as_constant_ptr()->as_jint();
1663         break;
1664       default:
1665         ShouldNotReachHere();
1666         c = 0;  // unreachable
1667         break;
1668       }
1669 
1670       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1671       if (c == 0 && dreg == lreg) {
1672         COMMENT("effective nop elided");
1673         return;
1674       }
1675       switch(left->type()) {
1676       case T_INT:
1677         switch (code) {
1678         case lir_add: __ addw(dreg, lreg, c); break;
1679         case lir_sub: __ subw(dreg, lreg, c); break;
1680         default: ShouldNotReachHere();
1681         }
1682         break;
1683       case T_OBJECT:
1684       case T_ADDRESS:
1685         switch (code) {
1686         case lir_add: __ add(dreg, lreg, c); break;
1687         case lir_sub: __ sub(dreg, lreg, c); break;
1688         default: ShouldNotReachHere();
1689         }
1690         break;
1691       default:
1692         ShouldNotReachHere();
1693       }
1694     } else {
1695       ShouldNotReachHere();
1696     }
1697 
1698   } else if (left->is_double_cpu()) {
1699     Register lreg_lo = left->as_register_lo();
1700 
1701     if (right->is_double_cpu()) {
1702       // cpu register - cpu register
1703       Register rreg_lo = right->as_register_lo();
1704       switch (code) {
1705       case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1706       case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1707       case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1708       case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1709       case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1710       default:
1711         ShouldNotReachHere();
1712       }
1713 
1714     } else if (right->is_constant()) {
1715       jlong c = right->as_constant_ptr()->as_jlong();
1716       Register dreg = as_reg(dest);
1717       switch (code) {
1718         case lir_add:
1719         case lir_sub:
1720           if (c == 0 && dreg == lreg_lo) {
1721             COMMENT("effective nop elided");
1722             return;
1723           }
1724           code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1725           break;
1726         case lir_div:
1727           assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1728           if (c == 1) {
1729             // move lreg_lo to dreg if divisor is 1
1730             __ mov(dreg, lreg_lo);
1731           } else {
1732             unsigned int shift = log2i_exact(c);
1733             // use rscratch1 as intermediate result register
1734             __ asr(rscratch1, lreg_lo, 63);
1735             __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1736             __ asr(dreg, rscratch1, shift);
1737           }
1738           break;
1739         case lir_rem:
1740           assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1741           if (c == 1) {
1742             // move 0 to dreg if divisor is 1
1743             __ mov(dreg, zr);
1744           } else {
1745             // use rscratch1 as intermediate result register
1746             __ negs(rscratch1, lreg_lo);
1747             __ andr(dreg, lreg_lo, c - 1);
1748             __ andr(rscratch1, rscratch1, c - 1);
1749             __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1750           }
1751           break;
1752         default:
1753           ShouldNotReachHere();
1754       }
1755     } else {
1756       ShouldNotReachHere();
1757     }
1758   } else if (left->is_single_fpu()) {
1759     assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1760     switch (code) {
1761     case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1762     case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1763     case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1764     case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1765     default:
1766       ShouldNotReachHere();
1767     }
1768   } else if (left->is_double_fpu()) {
1769     if (right->is_double_fpu()) {
1770       // fpu register - fpu register
1771       switch (code) {
1772       case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1773       case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1774       case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1775       case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1776       default:
1777         ShouldNotReachHere();
1778       }
1779     } else {
1780       if (right->is_constant()) {
1781         ShouldNotReachHere();
1782       }
1783       ShouldNotReachHere();
1784     }
1785   } else if (left->is_single_stack() || left->is_address()) {
1786     assert(left == dest, "left and dest must be equal");
1787     ShouldNotReachHere();
1788   } else {
1789     ShouldNotReachHere();
1790   }
1791 }
1792 
1793 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1794   switch(code) {
1795   case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1796   case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1797   case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1798   case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1799   default      : ShouldNotReachHere();
1800   }
1801 }
1802 
1803 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1804 
1805   assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1806   Register Rleft = left->is_single_cpu() ? left->as_register() :
1807                                            left->as_register_lo();
1808    if (dst->is_single_cpu()) {
1809      Register Rdst = dst->as_register();
1810      if (right->is_constant()) {
1811        switch (code) {
1812          case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1813          case lir_logic_or:  __ orrw (Rdst, Rleft, right->as_jint()); break;
1814          case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1815          default: ShouldNotReachHere(); break;
1816        }
1817      } else {
1818        Register Rright = right->is_single_cpu() ? right->as_register() :
1819                                                   right->as_register_lo();
1820        switch (code) {
1821          case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1822          case lir_logic_or:  __ orrw (Rdst, Rleft, Rright); break;
1823          case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1824          default: ShouldNotReachHere(); break;
1825        }
1826      }
1827    } else {
1828      Register Rdst = dst->as_register_lo();
1829      if (right->is_constant()) {
1830        switch (code) {
1831          case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1832          case lir_logic_or:  __ orr (Rdst, Rleft, right->as_jlong()); break;
1833          case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1834          default: ShouldNotReachHere(); break;
1835        }
1836      } else {
1837        Register Rright = right->is_single_cpu() ? right->as_register() :
1838                                                   right->as_register_lo();
1839        switch (code) {
1840          case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1841          case lir_logic_or:  __ orr (Rdst, Rleft, Rright); break;
1842          case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1843          default: ShouldNotReachHere(); break;
1844        }
1845      }
1846    }
1847 }
1848 
1849 
1850 
1851 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1852 
1853   // opcode check
1854   assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1855   bool is_irem = (code == lir_irem);
1856 
1857   // operand check
1858   assert(left->is_single_cpu(),   "left must be register");
1859   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
1860   assert(result->is_single_cpu(), "result must be register");
1861   Register lreg = left->as_register();
1862   Register dreg = result->as_register();
1863 
1864   // power-of-2 constant check and codegen
1865   if (right->is_constant()) {
1866     int c = right->as_constant_ptr()->as_jint();
1867     assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1868     if (is_irem) {
1869       if (c == 1) {
1870         // move 0 to dreg if divisor is 1
1871         __ movw(dreg, zr);
1872       } else {
1873         // use rscratch1 as intermediate result register
1874         __ negsw(rscratch1, lreg);
1875         __ andw(dreg, lreg, c - 1);
1876         __ andw(rscratch1, rscratch1, c - 1);
1877         __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1878       }
1879     } else {
1880       if (c == 1) {
1881         // move lreg to dreg if divisor is 1
1882         __ movw(dreg, lreg);
1883       } else {
1884         unsigned int shift = exact_log2(c);
1885         // use rscratch1 as intermediate result register
1886         __ asrw(rscratch1, lreg, 31);
1887         __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1888         __ asrw(dreg, rscratch1, shift);
1889       }
1890     }
1891   } else {
1892     Register rreg = right->as_register();
1893     __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1894   }
1895 }
1896 
1897 
1898 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1899   if (opr1->is_constant() && opr2->is_single_cpu()) {
1900     // tableswitch
1901     Register reg = as_reg(opr2);
1902     struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1903     __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1904   } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1905     Register reg1 = as_reg(opr1);
1906     if (opr2->is_single_cpu()) {
1907       // cpu register - cpu register
1908       Register reg2 = opr2->as_register();
1909       if (is_reference_type(opr1->type())) {
1910         __ cmpoop(reg1, reg2);
1911       } else {
1912         assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1913         __ cmpw(reg1, reg2);
1914       }
1915       return;
1916     }
1917     if (opr2->is_double_cpu()) {
1918       // cpu register - cpu register
1919       Register reg2 = opr2->as_register_lo();
1920       __ cmp(reg1, reg2);
1921       return;
1922     }
1923 
1924     if (opr2->is_constant()) {
1925       bool is_32bit = false; // width of register operand
1926       jlong imm;
1927 
1928       switch(opr2->type()) {
1929       case T_INT:
1930         imm = opr2->as_constant_ptr()->as_jint();
1931         is_32bit = true;
1932         break;
1933       case T_LONG:
1934         imm = opr2->as_constant_ptr()->as_jlong();
1935         break;
1936       case T_ADDRESS:
1937         imm = opr2->as_constant_ptr()->as_jint();
1938         break;
1939       case T_METADATA:
1940         imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1941         break;
1942       case T_OBJECT:
1943       case T_ARRAY:
1944         jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1945         __ cmpoop(reg1, rscratch1);
1946         return;
1947       default:
1948         ShouldNotReachHere();
1949         imm = 0;  // unreachable
1950         break;
1951       }
1952 
1953       if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1954         if (is_32bit)
1955           __ cmpw(reg1, imm);
1956         else
1957           __ subs(zr, reg1, imm);
1958         return;
1959       } else {
1960         __ mov(rscratch1, imm);
1961         if (is_32bit)
1962           __ cmpw(reg1, rscratch1);
1963         else
1964           __ cmp(reg1, rscratch1);
1965         return;
1966       }
1967     } else
1968       ShouldNotReachHere();
1969   } else if (opr1->is_single_fpu()) {
1970     FloatRegister reg1 = opr1->as_float_reg();
1971     assert(opr2->is_single_fpu(), "expect single float register");
1972     FloatRegister reg2 = opr2->as_float_reg();
1973     __ fcmps(reg1, reg2);
1974   } else if (opr1->is_double_fpu()) {
1975     FloatRegister reg1 = opr1->as_double_reg();
1976     assert(opr2->is_double_fpu(), "expect double float register");
1977     FloatRegister reg2 = opr2->as_double_reg();
1978     __ fcmpd(reg1, reg2);
1979   } else {
1980     ShouldNotReachHere();
1981   }
1982 }
1983 
1984 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1985   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1986     bool is_unordered_less = (code == lir_ucmp_fd2i);
1987     if (left->is_single_fpu()) {
1988       __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1989     } else if (left->is_double_fpu()) {
1990       __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1991     } else {
1992       ShouldNotReachHere();
1993     }
1994   } else if (code == lir_cmp_l2i) {
1995     Label done;
1996     __ cmp(left->as_register_lo(), right->as_register_lo());
1997     __ mov(dst->as_register(), (uint64_t)-1L);
1998     __ br(Assembler::LT, done);
1999     __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2000     __ bind(done);
2001   } else {
2002     ShouldNotReachHere();
2003   }
2004 }
2005 
2006 
2007 void LIR_Assembler::align_call(LIR_Code code) {  }
2008 
2009 
2010 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2011   address call = __ trampoline_call(Address(op->addr(), rtype));
2012   if (call == nullptr) {
2013     bailout("trampoline stub overflow");
2014     return;
2015   }
2016   add_call_info(code_offset(), op->info());
2017   __ post_call_nop();
2018 }
2019 
2020 
2021 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2022   address call = __ ic_call(op->addr());
2023   if (call == nullptr) {
2024     bailout("trampoline stub overflow");
2025     return;
2026   }
2027   add_call_info(code_offset(), op->info());
2028   __ post_call_nop();
2029 }
2030 
2031 void LIR_Assembler::emit_static_call_stub() {
2032   address call_pc = __ pc();
2033   address stub = __ start_a_stub(call_stub_size());
2034   if (stub == nullptr) {
2035     bailout("static call stub overflow");
2036     return;
2037   }
2038 
2039   int start = __ offset();
2040 
2041   __ relocate(static_stub_Relocation::spec(call_pc));
2042   __ emit_static_call_stub();
2043 
2044   assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2045         <= call_stub_size(), "stub too big");
2046   __ end_a_stub();
2047 }
2048 
2049 
2050 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2051   assert(exceptionOop->as_register() == r0, "must match");
2052   assert(exceptionPC->as_register() == r3, "must match");
2053 
2054   // exception object is not added to oop map by LinearScan
2055   // (LinearScan assumes that no oops are in fixed registers)
2056   info->add_register_oop(exceptionOop);
2057   C1StubId unwind_id;
2058 
2059   // get current pc information
2060   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2061   if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2062     // As no instructions have been generated yet for this LIR node it's
2063     // possible that an oop map already exists for the current offset.
2064     // In that case insert an dummy NOP here to ensure all oop map PCs
2065     // are unique. See JDK-8237483.
2066     __ nop();
2067   }
2068   int pc_for_athrow_offset = __ offset();
2069   InternalAddress pc_for_athrow(__ pc());
2070   __ adr(exceptionPC->as_register(), pc_for_athrow);
2071   add_call_info(pc_for_athrow_offset, info); // for exception handler
2072 
2073   __ verify_not_null_oop(r0);
2074   // search an exception handler (r0: exception oop, r3: throwing pc)
2075   if (compilation()->has_fpu_code()) {
2076     unwind_id = C1StubId::handle_exception_id;
2077   } else {
2078     unwind_id = C1StubId::handle_exception_nofpu_id;
2079   }
2080   __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2081 
2082   // FIXME: enough room for two byte trap   ????
2083   __ nop();
2084 }
2085 
2086 
2087 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2088   assert(exceptionOop->as_register() == r0, "must match");
2089 
2090   __ b(_unwind_handler_entry);
2091 }
2092 
2093 
2094 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2095   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2096   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2097 
2098   switch (left->type()) {
2099     case T_INT: {
2100       switch (code) {
2101       case lir_shl:  __ lslvw (dreg, lreg, count->as_register()); break;
2102       case lir_shr:  __ asrvw (dreg, lreg, count->as_register()); break;
2103       case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2104       default:
2105         ShouldNotReachHere();
2106         break;
2107       }
2108       break;
2109     case T_LONG:
2110     case T_ADDRESS:
2111     case T_OBJECT:
2112       switch (code) {
2113       case lir_shl:  __ lslv (dreg, lreg, count->as_register()); break;
2114       case lir_shr:  __ asrv (dreg, lreg, count->as_register()); break;
2115       case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2116       default:
2117         ShouldNotReachHere();
2118         break;
2119       }
2120       break;
2121     default:
2122       ShouldNotReachHere();
2123       break;
2124     }
2125   }
2126 }
2127 
2128 
2129 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2130   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2131   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2132 
2133   switch (left->type()) {
2134     case T_INT: {
2135       switch (code) {
2136       case lir_shl:  __ lslw (dreg, lreg, count); break;
2137       case lir_shr:  __ asrw (dreg, lreg, count); break;
2138       case lir_ushr: __ lsrw (dreg, lreg, count); break;
2139       default:
2140         ShouldNotReachHere();
2141         break;
2142       }
2143       break;
2144     case T_LONG:
2145     case T_ADDRESS:
2146     case T_OBJECT:
2147       switch (code) {
2148       case lir_shl:  __ lsl (dreg, lreg, count); break;
2149       case lir_shr:  __ asr (dreg, lreg, count); break;
2150       case lir_ushr: __ lsr (dreg, lreg, count); break;
2151       default:
2152         ShouldNotReachHere();
2153         break;
2154       }
2155       break;
2156     default:
2157       ShouldNotReachHere();
2158       break;
2159     }
2160   }
2161 }
2162 
2163 
2164 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2165   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2166   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2167   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2168   __ str (r, Address(sp, offset_from_rsp_in_bytes));
2169 }
2170 
2171 
2172 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
2173   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2174   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2175   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2176   __ mov (rscratch1, c);
2177   __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2178 }
2179 
2180 
2181 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
2182   ShouldNotReachHere();
2183   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2184   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2185   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2186   __ lea(rscratch1, __ constant_oop_address(o));
2187   __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2188 }
2189 
2190 
2191 // This code replaces a call to arraycopy; no exception may
2192 // be thrown in this code, they must be thrown in the System.arraycopy
2193 // activation frame; we could save some checks if this would not be the case
2194 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2195   ciArrayKlass* default_type = op->expected_type();
2196   Register src = op->src()->as_register();
2197   Register dst = op->dst()->as_register();
2198   Register src_pos = op->src_pos()->as_register();
2199   Register dst_pos = op->dst_pos()->as_register();
2200   Register length  = op->length()->as_register();
2201   Register tmp = op->tmp()->as_register();
2202 
2203   CodeStub* stub = op->stub();
2204   int flags = op->flags();
2205   BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2206   if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2207 
2208   // if we don't know anything, just go through the generic arraycopy
2209   if (default_type == nullptr // || basic_type == T_OBJECT
2210       ) {
2211     Label done;
2212     assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2213 
2214     // Save the arguments in case the generic arraycopy fails and we
2215     // have to fall back to the JNI stub
2216     __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2217     __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2218     __ str(src,              Address(sp, 4*BytesPerWord));
2219 
2220     address copyfunc_addr = StubRoutines::generic_arraycopy();
2221     assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2222 
2223     // The arguments are in java calling convention so we shift them
2224     // to C convention
2225     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2226     __ mov(c_rarg0, j_rarg0);
2227     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2228     __ mov(c_rarg1, j_rarg1);
2229     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2230     __ mov(c_rarg2, j_rarg2);
2231     assert_different_registers(c_rarg3, j_rarg4);
2232     __ mov(c_rarg3, j_rarg3);
2233     __ mov(c_rarg4, j_rarg4);
2234 #ifndef PRODUCT
2235     if (PrintC1Statistics) {
2236       __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2237     }
2238 #endif
2239     __ far_call(RuntimeAddress(copyfunc_addr));
2240 
2241     __ cbz(r0, *stub->continuation());
2242 
2243     // Reload values from the stack so they are where the stub
2244     // expects them.
2245     __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2246     __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2247     __ ldr(src,              Address(sp, 4*BytesPerWord));
2248 
2249     // r0 is -1^K where K == partial copied count
2250     __ eonw(rscratch1, r0, zr);
2251     // adjust length down and src/end pos up by partial copied count
2252     __ subw(length, length, rscratch1);
2253     __ addw(src_pos, src_pos, rscratch1);
2254     __ addw(dst_pos, dst_pos, rscratch1);
2255     __ b(*stub->entry());
2256 
2257     __ bind(*stub->continuation());
2258     return;
2259   }
2260 
2261   assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2262 
2263   int elem_size = type2aelembytes(basic_type);
2264   int scale = exact_log2(elem_size);
2265 
2266   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2267   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2268 
2269   // test for null
2270   if (flags & LIR_OpArrayCopy::src_null_check) {
2271     __ cbz(src, *stub->entry());
2272   }
2273   if (flags & LIR_OpArrayCopy::dst_null_check) {
2274     __ cbz(dst, *stub->entry());
2275   }
2276 
2277   // If the compiler was not able to prove that exact type of the source or the destination
2278   // of the arraycopy is an array type, check at runtime if the source or the destination is
2279   // an instance type.
2280   if (flags & LIR_OpArrayCopy::type_check) {
2281     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2282       __ load_klass(tmp, dst);
2283       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2284       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2285       __ br(Assembler::GE, *stub->entry());
2286     }
2287 
2288     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2289       __ load_klass(tmp, src);
2290       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2291       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2292       __ br(Assembler::GE, *stub->entry());
2293     }
2294   }
2295 
2296   // check if negative
2297   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2298     __ cmpw(src_pos, 0);
2299     __ br(Assembler::LT, *stub->entry());
2300   }
2301   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2302     __ cmpw(dst_pos, 0);
2303     __ br(Assembler::LT, *stub->entry());
2304   }
2305 
2306   if (flags & LIR_OpArrayCopy::length_positive_check) {
2307     __ cmpw(length, 0);
2308     __ br(Assembler::LT, *stub->entry());
2309   }
2310 
2311   if (flags & LIR_OpArrayCopy::src_range_check) {
2312     __ addw(tmp, src_pos, length);
2313     __ ldrw(rscratch1, src_length_addr);
2314     __ cmpw(tmp, rscratch1);
2315     __ br(Assembler::HI, *stub->entry());
2316   }
2317   if (flags & LIR_OpArrayCopy::dst_range_check) {
2318     __ addw(tmp, dst_pos, length);
2319     __ ldrw(rscratch1, dst_length_addr);
2320     __ cmpw(tmp, rscratch1);
2321     __ br(Assembler::HI, *stub->entry());
2322   }
2323 
2324   if (flags & LIR_OpArrayCopy::type_check) {
2325     // We don't know the array types are compatible
2326     if (basic_type != T_OBJECT) {
2327       // Simple test for basic type arrays
2328       __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2329       __ br(Assembler::NE, *stub->entry());
2330     } else {
2331       // For object arrays, if src is a sub class of dst then we can
2332       // safely do the copy.
2333       Label cont, slow;
2334 
2335 #define PUSH(r1, r2)                                    \
2336       stp(r1, r2, __ pre(sp, -2 * wordSize));
2337 
2338 #define POP(r1, r2)                                     \
2339       ldp(r1, r2, __ post(sp, 2 * wordSize));
2340 
2341       __ PUSH(src, dst);
2342 
2343       __ load_klass(src, src);
2344       __ load_klass(dst, dst);
2345 
2346       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2347 
2348       __ PUSH(src, dst);
2349       __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
2350       __ POP(src, dst);
2351 
2352       __ cbnz(src, cont);
2353 
2354       __ bind(slow);
2355       __ POP(src, dst);
2356 
2357       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2358       if (copyfunc_addr != nullptr) { // use stub if available
2359         // src is not a sub class of dst so we have to do a
2360         // per-element check.
2361 
2362         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2363         if ((flags & mask) != mask) {
2364           // Check that at least both of them object arrays.
2365           assert(flags & mask, "one of the two should be known to be an object array");
2366 
2367           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2368             __ load_klass(tmp, src);
2369           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2370             __ load_klass(tmp, dst);
2371           }
2372           int lh_offset = in_bytes(Klass::layout_helper_offset());
2373           Address klass_lh_addr(tmp, lh_offset);
2374           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2375           __ ldrw(rscratch1, klass_lh_addr);
2376           __ mov(rscratch2, objArray_lh);
2377           __ eorw(rscratch1, rscratch1, rscratch2);
2378           __ cbnzw(rscratch1, *stub->entry());
2379         }
2380 
2381        // Spill because stubs can use any register they like and it's
2382        // easier to restore just those that we care about.
2383         __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2384         __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2385         __ str(src,              Address(sp, 4*BytesPerWord));
2386 
2387         __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2388         __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2389         assert_different_registers(c_rarg0, dst, dst_pos, length);
2390         __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2391         __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2392         assert_different_registers(c_rarg1, dst, length);
2393         __ uxtw(c_rarg2, length);
2394         assert_different_registers(c_rarg2, dst);
2395 
2396         __ load_klass(c_rarg4, dst);
2397         __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2398         __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2399         __ far_call(RuntimeAddress(copyfunc_addr));
2400 
2401 #ifndef PRODUCT
2402         if (PrintC1Statistics) {
2403           Label failed;
2404           __ cbnz(r0, failed);
2405           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2406           __ bind(failed);
2407         }
2408 #endif
2409 
2410         __ cbz(r0, *stub->continuation());
2411 
2412 #ifndef PRODUCT
2413         if (PrintC1Statistics) {
2414           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2415         }
2416 #endif
2417         assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2418 
2419         // Restore previously spilled arguments
2420         __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2421         __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2422         __ ldr(src,              Address(sp, 4*BytesPerWord));
2423 
2424         // return value is -1^K where K is partial copied count
2425         __ eonw(rscratch1, r0, zr);
2426         // adjust length down and src/end pos up by partial copied count
2427         __ subw(length, length, rscratch1);
2428         __ addw(src_pos, src_pos, rscratch1);
2429         __ addw(dst_pos, dst_pos, rscratch1);
2430       }
2431 
2432       __ b(*stub->entry());
2433 
2434       __ bind(cont);
2435       __ POP(src, dst);
2436     }
2437   }
2438 
2439 #ifdef ASSERT
2440   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2441     // Sanity check the known type with the incoming class.  For the
2442     // primitive case the types must match exactly with src.klass and
2443     // dst.klass each exactly matching the default type.  For the
2444     // object array case, if no type check is needed then either the
2445     // dst type is exactly the expected type and the src type is a
2446     // subtype which we can't check or src is the same array as dst
2447     // but not necessarily exactly of type default_type.
2448     Label known_ok, halt;
2449     __ mov_metadata(tmp, default_type->constant_encoding());
2450 
2451     if (basic_type != T_OBJECT) {
2452       __ cmp_klass(dst, tmp, rscratch1);
2453       __ br(Assembler::NE, halt);
2454       __ cmp_klass(src, tmp, rscratch1);
2455       __ br(Assembler::EQ, known_ok);
2456     } else {
2457       __ cmp_klass(dst, tmp, rscratch1);
2458       __ br(Assembler::EQ, known_ok);
2459       __ cmp(src, dst);
2460       __ br(Assembler::EQ, known_ok);
2461     }
2462     __ bind(halt);
2463     __ stop("incorrect type information in arraycopy");
2464     __ bind(known_ok);
2465   }
2466 #endif
2467 
2468 #ifndef PRODUCT
2469   if (PrintC1Statistics) {
2470     __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2471   }
2472 #endif
2473 
2474   __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2475   __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2476   assert_different_registers(c_rarg0, dst, dst_pos, length);
2477   __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2478   __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2479   assert_different_registers(c_rarg1, dst, length);
2480   __ uxtw(c_rarg2, length);
2481   assert_different_registers(c_rarg2, dst);
2482 
2483   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2484   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2485   const char *name;
2486   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2487 
2488  CodeBlob *cb = CodeCache::find_blob(entry);
2489  if (cb) {
2490    __ far_call(RuntimeAddress(entry));
2491  } else {
2492    __ call_VM_leaf(entry, 3);
2493  }
2494 
2495   if (stub != nullptr) {
2496     __ bind(*stub->continuation());
2497   }
2498 }
2499 
2500 
2501 
2502 
2503 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2504   Register obj = op->obj_opr()->as_register();  // may not be an oop
2505   Register hdr = op->hdr_opr()->as_register();
2506   Register lock = op->lock_opr()->as_register();
2507   Register temp = op->scratch_opr()->as_register();
2508   if (LockingMode == LM_MONITOR) {
2509     if (op->info() != nullptr) {
2510       add_debug_info_for_null_check_here(op->info());
2511       __ null_check(obj, -1);
2512     }
2513     __ b(*op->stub()->entry());
2514   } else if (op->code() == lir_lock) {
2515     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2516     // add debug info for NullPointerException only if one is possible
2517     int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2518     if (op->info() != nullptr) {
2519       add_debug_info_for_null_check(null_check_offset, op->info());
2520     }
2521     // done
2522   } else if (op->code() == lir_unlock) {
2523     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2524     __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2525   } else {
2526     Unimplemented();
2527   }
2528   __ bind(*op->stub()->continuation());
2529 }
2530 
2531 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2532   Register obj = op->obj()->as_pointer_register();
2533   Register result = op->result_opr()->as_pointer_register();
2534 
2535   CodeEmitInfo* info = op->info();
2536   if (info != nullptr) {
2537     add_debug_info_for_null_check_here(info);
2538   }
2539 
2540   __ load_klass(result, obj);
2541 }
2542 
2543 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2544   ciMethod* method = op->profiled_method();
2545   int bci          = op->profiled_bci();
2546   ciMethod* callee = op->profiled_callee();
2547 
2548   // Update counter for all call types
2549   ciMethodData* md = method->method_data_or_null();
2550   assert(md != nullptr, "Sanity");
2551   ciProfileData* data = md->bci_to_data(bci);
2552   assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2553   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2554   Register mdo  = op->mdo()->as_register();
2555   __ mov_metadata(mdo, md->constant_encoding());
2556   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2557   // Perform additional virtual call profiling for invokevirtual and
2558   // invokeinterface bytecodes
2559   if (op->should_profile_receiver_type()) {
2560     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2561     Register recv = op->recv()->as_register();
2562     assert_different_registers(mdo, recv);
2563     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2564     ciKlass* known_klass = op->known_holder();
2565     if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2566       // We know the type that will be seen at this call site; we can
2567       // statically update the MethodData* rather than needing to do
2568       // dynamic tests on the receiver type
2569 
2570       // NOTE: we should probably put a lock around this search to
2571       // avoid collisions by concurrent compilations
2572       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2573       uint i;
2574       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2575         ciKlass* receiver = vc_data->receiver(i);
2576         if (known_klass->equals(receiver)) {
2577           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2578           __ addptr(data_addr, DataLayout::counter_increment);
2579           return;
2580         }
2581       }
2582 
2583       // Receiver type not found in profile data; select an empty slot
2584 
2585       // Note that this is less efficient than it should be because it
2586       // always does a write to the receiver part of the
2587       // VirtualCallData rather than just the first time
2588       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2589         ciKlass* receiver = vc_data->receiver(i);
2590         if (receiver == nullptr) {
2591           __ mov_metadata(rscratch1, known_klass->constant_encoding());
2592           Address recv_addr =
2593             __ form_address(rscratch2, mdo,
2594                             md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)),
2595                             LogBytesPerWord);
2596           __ str(rscratch1, recv_addr);
2597           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2598           __ addptr(data_addr, DataLayout::counter_increment);
2599           return;
2600         }
2601       }
2602     } else {
2603       __ load_klass(recv, recv);
2604       Label update_done;
2605       type_profile_helper(mdo, md, data, recv, &update_done);
2606       // Receiver did not match any saved receiver and there is no empty row for it.
2607       // Increment total counter to indicate polymorphic case.
2608       __ addptr(counter_addr, DataLayout::counter_increment);
2609 
2610       __ bind(update_done);
2611     }
2612   } else {
2613     // Static call
2614     __ addptr(counter_addr, DataLayout::counter_increment);
2615   }
2616 }
2617 
2618 
2619 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2620   Unimplemented();
2621 }
2622 
2623 
2624 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2625   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2626 }
2627 
2628 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2629   assert(op->crc()->is_single_cpu(),  "crc must be register");
2630   assert(op->val()->is_single_cpu(),  "byte value must be register");
2631   assert(op->result_opr()->is_single_cpu(), "result must be register");
2632   Register crc = op->crc()->as_register();
2633   Register val = op->val()->as_register();
2634   Register res = op->result_opr()->as_register();
2635 
2636   assert_different_registers(val, crc, res);
2637   uint64_t offset;
2638   __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2639   __ add(res, res, offset);
2640 
2641   __ mvnw(crc, crc); // ~crc
2642   __ update_byte_crc32(crc, val, res);
2643   __ mvnw(res, crc); // ~crc
2644 }
2645 
2646 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2647   COMMENT("emit_profile_type {");
2648   Register obj = op->obj()->as_register();
2649   Register tmp = op->tmp()->as_pointer_register();
2650   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2651   ciKlass* exact_klass = op->exact_klass();
2652   intptr_t current_klass = op->current_klass();
2653   bool not_null = op->not_null();
2654   bool no_conflict = op->no_conflict();
2655 
2656   Label update, next, none;
2657 
2658   bool do_null = !not_null;
2659   bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2660   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2661 
2662   assert(do_null || do_update, "why are we here?");
2663   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2664   assert(mdo_addr.base() != rscratch1, "wrong register");
2665 
2666   __ verify_oop(obj);
2667 
2668   if (tmp != obj) {
2669     assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2670     __ mov(tmp, obj);
2671   } else {
2672     assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2673   }
2674   if (do_null) {
2675     __ cbnz(tmp, update);
2676     if (!TypeEntries::was_null_seen(current_klass)) {
2677       __ ldr(rscratch2, mdo_addr);
2678       __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2679       __ str(rscratch2, mdo_addr);
2680     }
2681     if (do_update) {
2682 #ifndef ASSERT
2683       __ b(next);
2684     }
2685 #else
2686       __ b(next);
2687     }
2688   } else {
2689     __ cbnz(tmp, update);
2690     __ stop("unexpected null obj");
2691 #endif
2692   }
2693 
2694   __ bind(update);
2695 
2696   if (do_update) {
2697 #ifdef ASSERT
2698     if (exact_klass != nullptr) {
2699       Label ok;
2700       __ load_klass(tmp, tmp);
2701       __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2702       __ eor(rscratch1, tmp, rscratch1);
2703       __ cbz(rscratch1, ok);
2704       __ stop("exact klass and actual klass differ");
2705       __ bind(ok);
2706     }
2707 #endif
2708     if (!no_conflict) {
2709       if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2710         if (exact_klass != nullptr) {
2711           __ mov_metadata(tmp, exact_klass->constant_encoding());
2712         } else {
2713           __ load_klass(tmp, tmp);
2714         }
2715 
2716         __ ldr(rscratch2, mdo_addr);
2717         __ eor(tmp, tmp, rscratch2);
2718         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2719         // klass seen before, nothing to do. The unknown bit may have been
2720         // set already but no need to check.
2721         __ cbz(rscratch1, next);
2722 
2723         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2724 
2725         if (TypeEntries::is_type_none(current_klass)) {
2726           __ cbz(rscratch2, none);
2727           __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2728           __ br(Assembler::EQ, none);
2729           // There is a chance that the checks above
2730           // fail if another thread has just set the
2731           // profiling to this obj's klass
2732           __ dmb(Assembler::ISHLD);
2733           __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2734           __ ldr(rscratch2, mdo_addr);
2735           __ eor(tmp, tmp, rscratch2);
2736           __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2737           __ cbz(rscratch1, next);
2738         }
2739       } else {
2740         assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2741                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2742 
2743         __ ldr(tmp, mdo_addr);
2744         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2745       }
2746 
2747       // different than before. Cannot keep accurate profile.
2748       __ ldr(rscratch2, mdo_addr);
2749       __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2750       __ str(rscratch2, mdo_addr);
2751 
2752       if (TypeEntries::is_type_none(current_klass)) {
2753         __ b(next);
2754 
2755         __ bind(none);
2756         // first time here. Set profile type.
2757         __ str(tmp, mdo_addr);
2758 #ifdef ASSERT
2759         __ andr(tmp, tmp, TypeEntries::type_mask);
2760         __ verify_klass_ptr(tmp);
2761 #endif
2762       }
2763     } else {
2764       // There's a single possible klass at this profile point
2765       assert(exact_klass != nullptr, "should be");
2766       if (TypeEntries::is_type_none(current_klass)) {
2767         __ mov_metadata(tmp, exact_klass->constant_encoding());
2768         __ ldr(rscratch2, mdo_addr);
2769         __ eor(tmp, tmp, rscratch2);
2770         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2771         __ cbz(rscratch1, next);
2772 #ifdef ASSERT
2773         {
2774           Label ok;
2775           __ ldr(rscratch1, mdo_addr);
2776           __ cbz(rscratch1, ok);
2777           __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2778           __ br(Assembler::EQ, ok);
2779           // may have been set by another thread
2780           __ dmb(Assembler::ISHLD);
2781           __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2782           __ ldr(rscratch2, mdo_addr);
2783           __ eor(rscratch2, rscratch1, rscratch2);
2784           __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2785           __ cbz(rscratch2, ok);
2786 
2787           __ stop("unexpected profiling mismatch");
2788           __ bind(ok);
2789         }
2790 #endif
2791         // first time here. Set profile type.
2792         __ str(tmp, mdo_addr);
2793 #ifdef ASSERT
2794         __ andr(tmp, tmp, TypeEntries::type_mask);
2795         __ verify_klass_ptr(tmp);
2796 #endif
2797       } else {
2798         assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2799                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2800 
2801         __ ldr(tmp, mdo_addr);
2802         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2803 
2804         __ orr(tmp, tmp, TypeEntries::type_unknown);
2805         __ str(tmp, mdo_addr);
2806         // FIXME: Write barrier needed here?
2807       }
2808     }
2809 
2810     __ bind(next);
2811   }
2812   COMMENT("} emit_profile_type");
2813 }
2814 
2815 
2816 void LIR_Assembler::align_backward_branch_target() {
2817 }
2818 
2819 
2820 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2821   // tmp must be unused
2822   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2823 
2824   if (left->is_single_cpu()) {
2825     assert(dest->is_single_cpu(), "expect single result reg");
2826     __ negw(dest->as_register(), left->as_register());
2827   } else if (left->is_double_cpu()) {
2828     assert(dest->is_double_cpu(), "expect double result reg");
2829     __ neg(dest->as_register_lo(), left->as_register_lo());
2830   } else if (left->is_single_fpu()) {
2831     assert(dest->is_single_fpu(), "expect single float result reg");
2832     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2833   } else {
2834     assert(left->is_double_fpu(), "expect double float operand reg");
2835     assert(dest->is_double_fpu(), "expect double float result reg");
2836     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2837   }
2838 }
2839 
2840 
2841 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2842   if (patch_code != lir_patch_none) {
2843     deoptimize_trap(info);
2844     return;
2845   }
2846 
2847   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2848 }
2849 
2850 
2851 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2852   assert(!tmp->is_valid(), "don't need temporary");
2853 
2854   CodeBlob *cb = CodeCache::find_blob(dest);
2855   if (cb) {
2856     __ far_call(RuntimeAddress(dest));
2857   } else {
2858     __ mov(rscratch1, RuntimeAddress(dest));
2859     __ blr(rscratch1);
2860   }
2861 
2862   if (info != nullptr) {
2863     add_call_info_here(info);
2864   }
2865   __ post_call_nop();
2866 }
2867 
2868 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2869   if (dest->is_address() || src->is_address()) {
2870     move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
2871   } else {
2872     ShouldNotReachHere();
2873   }
2874 }
2875 
2876 #ifdef ASSERT
2877 // emit run-time assertion
2878 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2879   assert(op->code() == lir_assert, "must be");
2880 
2881   if (op->in_opr1()->is_valid()) {
2882     assert(op->in_opr2()->is_valid(), "both operands must be valid");
2883     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2884   } else {
2885     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2886     assert(op->condition() == lir_cond_always, "no other conditions allowed");
2887   }
2888 
2889   Label ok;
2890   if (op->condition() != lir_cond_always) {
2891     Assembler::Condition acond = Assembler::AL;
2892     switch (op->condition()) {
2893       case lir_cond_equal:        acond = Assembler::EQ;  break;
2894       case lir_cond_notEqual:     acond = Assembler::NE;  break;
2895       case lir_cond_less:         acond = Assembler::LT;  break;
2896       case lir_cond_lessEqual:    acond = Assembler::LE;  break;
2897       case lir_cond_greaterEqual: acond = Assembler::GE;  break;
2898       case lir_cond_greater:      acond = Assembler::GT;  break;
2899       case lir_cond_belowEqual:   acond = Assembler::LS;  break;
2900       case lir_cond_aboveEqual:   acond = Assembler::HS;  break;
2901       default:                    ShouldNotReachHere();
2902     }
2903     __ br(acond, ok);
2904   }
2905   if (op->halt()) {
2906     const char* str = __ code_string(op->msg());
2907     __ stop(str);
2908   } else {
2909     breakpoint();
2910   }
2911   __ bind(ok);
2912 }
2913 #endif
2914 
2915 #ifndef PRODUCT
2916 #define COMMENT(x)   do { __ block_comment(x); } while (0)
2917 #else
2918 #define COMMENT(x)
2919 #endif
2920 
2921 void LIR_Assembler::membar() {
2922   COMMENT("membar");
2923   __ membar(MacroAssembler::AnyAny);
2924 }
2925 
2926 void LIR_Assembler::membar_acquire() {
2927   __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2928 }
2929 
2930 void LIR_Assembler::membar_release() {
2931   __ membar(Assembler::LoadStore|Assembler::StoreStore);
2932 }
2933 
2934 void LIR_Assembler::membar_loadload() {
2935   __ membar(Assembler::LoadLoad);
2936 }
2937 
2938 void LIR_Assembler::membar_storestore() {
2939   __ membar(MacroAssembler::StoreStore);
2940 }
2941 
2942 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2943 
2944 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2945 
2946 void LIR_Assembler::on_spin_wait() {
2947   __ spin_wait();
2948 }
2949 
2950 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2951   __ mov(result_reg->as_register(), rthread);
2952 }
2953 
2954 
2955 void LIR_Assembler::peephole(LIR_List *lir) {
2956 #if 0
2957   if (tableswitch_count >= max_tableswitches)
2958     return;
2959 
2960   /*
2961     This finite-state automaton recognizes sequences of compare-and-
2962     branch instructions.  We will turn them into a tableswitch.  You
2963     could argue that C1 really shouldn't be doing this sort of
2964     optimization, but without it the code is really horrible.
2965   */
2966 
2967   enum { start_s, cmp1_s, beq_s, cmp_s } state;
2968   int first_key, last_key = -2147483648;
2969   int next_key = 0;
2970   int start_insn = -1;
2971   int last_insn = -1;
2972   Register reg = noreg;
2973   LIR_Opr reg_opr;
2974   state = start_s;
2975 
2976   LIR_OpList* inst = lir->instructions_list();
2977   for (int i = 0; i < inst->length(); i++) {
2978     LIR_Op* op = inst->at(i);
2979     switch (state) {
2980     case start_s:
2981       first_key = -1;
2982       start_insn = i;
2983       switch (op->code()) {
2984       case lir_cmp:
2985         LIR_Opr opr1 = op->as_Op2()->in_opr1();
2986         LIR_Opr opr2 = op->as_Op2()->in_opr2();
2987         if (opr1->is_cpu_register() && opr1->is_single_cpu()
2988             && opr2->is_constant()
2989             && opr2->type() == T_INT) {
2990           reg_opr = opr1;
2991           reg = opr1->as_register();
2992           first_key = opr2->as_constant_ptr()->as_jint();
2993           next_key = first_key + 1;
2994           state = cmp_s;
2995           goto next_state;
2996         }
2997         break;
2998       }
2999       break;
3000     case cmp_s:
3001       switch (op->code()) {
3002       case lir_branch:
3003         if (op->as_OpBranch()->cond() == lir_cond_equal) {
3004           state = beq_s;
3005           last_insn = i;
3006           goto next_state;
3007         }
3008       }
3009       state = start_s;
3010       break;
3011     case beq_s:
3012       switch (op->code()) {
3013       case lir_cmp: {
3014         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3015         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3016         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3017             && opr1->as_register() == reg
3018             && opr2->is_constant()
3019             && opr2->type() == T_INT
3020             && opr2->as_constant_ptr()->as_jint() == next_key) {
3021           last_key = next_key;
3022           next_key++;
3023           state = cmp_s;
3024           goto next_state;
3025         }
3026       }
3027       }
3028       last_key = next_key;
3029       state = start_s;
3030       break;
3031     default:
3032       assert(false, "impossible state");
3033     }
3034     if (state == start_s) {
3035       if (first_key < last_key - 5L && reg != noreg) {
3036         {
3037           // printf("found run register %d starting at insn %d low value %d high value %d\n",
3038           //        reg->encoding(),
3039           //        start_insn, first_key, last_key);
3040           //   for (int i = 0; i < inst->length(); i++) {
3041           //     inst->at(i)->print();
3042           //     tty->print("\n");
3043           //   }
3044           //   tty->print("\n");
3045         }
3046 
3047         struct tableswitch *sw = &switches[tableswitch_count];
3048         sw->_insn_index = start_insn, sw->_first_key = first_key,
3049           sw->_last_key = last_key, sw->_reg = reg;
3050         inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3051         {
3052           // Insert the new table of branches
3053           int offset = last_insn;
3054           for (int n = first_key; n < last_key; n++) {
3055             inst->insert_before
3056               (last_insn + 1,
3057                new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3058                                 inst->at(offset)->as_OpBranch()->label()));
3059             offset -= 2, i++;
3060           }
3061         }
3062         // Delete all the old compare-and-branch instructions
3063         for (int n = first_key; n < last_key; n++) {
3064           inst->remove_at(start_insn);
3065           inst->remove_at(start_insn);
3066         }
3067         // Insert the tableswitch instruction
3068         inst->insert_before(start_insn,
3069                             new LIR_Op2(lir_cmp, lir_cond_always,
3070                                         LIR_OprFact::intConst(tableswitch_count),
3071                                         reg_opr));
3072         inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3073         tableswitch_count++;
3074       }
3075       reg = noreg;
3076       last_key = -2147483648;
3077     }
3078   next_state:
3079     ;
3080   }
3081 #endif
3082 }
3083 
3084 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3085   Address addr = as_Address(src->as_address_ptr());
3086   BasicType type = src->type();
3087   bool is_oop = is_reference_type(type);
3088 
3089   void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3090   void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3091 
3092   switch(type) {
3093   case T_INT:
3094     xchg = &MacroAssembler::atomic_xchgalw;
3095     add = &MacroAssembler::atomic_addalw;
3096     break;
3097   case T_LONG:
3098     xchg = &MacroAssembler::atomic_xchgal;
3099     add = &MacroAssembler::atomic_addal;
3100     break;
3101   case T_OBJECT:
3102   case T_ARRAY:
3103     if (UseCompressedOops) {
3104       xchg = &MacroAssembler::atomic_xchgalw;
3105       add = &MacroAssembler::atomic_addalw;
3106     } else {
3107       xchg = &MacroAssembler::atomic_xchgal;
3108       add = &MacroAssembler::atomic_addal;
3109     }
3110     break;
3111   default:
3112     ShouldNotReachHere();
3113     xchg = &MacroAssembler::atomic_xchgal;
3114     add = &MacroAssembler::atomic_addal; // unreachable
3115   }
3116 
3117   switch (code) {
3118   case lir_xadd:
3119     {
3120       RegisterOrConstant inc;
3121       Register tmp = as_reg(tmp_op);
3122       Register dst = as_reg(dest);
3123       if (data->is_constant()) {
3124         inc = RegisterOrConstant(as_long(data));
3125         assert_different_registers(dst, addr.base(), tmp,
3126                                    rscratch1, rscratch2);
3127       } else {
3128         inc = RegisterOrConstant(as_reg(data));
3129         assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3130                                    rscratch1, rscratch2);
3131       }
3132       __ lea(tmp, addr);
3133       (_masm->*add)(dst, inc, tmp);
3134       break;
3135     }
3136   case lir_xchg:
3137     {
3138       Register tmp = tmp_op->as_register();
3139       Register obj = as_reg(data);
3140       Register dst = as_reg(dest);
3141       if (is_oop && UseCompressedOops) {
3142         __ encode_heap_oop(rscratch2, obj);
3143         obj = rscratch2;
3144       }
3145       assert_different_registers(obj, addr.base(), tmp, rscratch1);
3146       assert_different_registers(dst, addr.base(), tmp, rscratch1);
3147       __ lea(tmp, addr);
3148       (_masm->*xchg)(dst, obj, tmp);
3149       if (is_oop && UseCompressedOops) {
3150         __ decode_heap_oop(dst);
3151       }
3152     }
3153     break;
3154   default:
3155     ShouldNotReachHere();
3156   }
3157   __ membar(__ AnyAny);
3158 }
3159 
3160 #undef __