1 /*
2 * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "ci/ciUtilities.hpp"
38 #include "code/SCCache.hpp"
39 #include "code/compiledIC.hpp"
40 #include "gc/shared/collectedHeap.hpp"
41 #include "gc/shared/gc_globals.hpp"
42 #include "nativeInst_aarch64.hpp"
43 #include "oops/objArrayKlass.hpp"
44 #include "runtime/frame.inline.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/stubRoutines.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_aarch64.inline.hpp"
49
50
51 #ifndef PRODUCT
52 #define COMMENT(x) do { __ block_comment(x); } while (0)
53 #else
54 #define COMMENT(x)
55 #endif
56
57 NEEDS_CLEANUP // remove this definitions ?
58 const Register SYNC_header = r0; // synchronization header
59 const Register SHIFT_count = r0; // where count for shift operations must be
60
61 #define __ _masm->
62
63
64 static void select_different_registers(Register preserve,
65 Register extra,
66 Register &tmp1,
67 Register &tmp2) {
68 if (tmp1 == preserve) {
69 assert_different_registers(tmp1, tmp2, extra);
70 tmp1 = extra;
71 } else if (tmp2 == preserve) {
72 assert_different_registers(tmp1, tmp2, extra);
73 tmp2 = extra;
74 }
75 assert_different_registers(preserve, tmp1, tmp2);
76 }
77
78
79
80 static void select_different_registers(Register preserve,
81 Register extra,
82 Register &tmp1,
83 Register &tmp2,
84 Register &tmp3) {
85 if (tmp1 == preserve) {
86 assert_different_registers(tmp1, tmp2, tmp3, extra);
87 tmp1 = extra;
88 } else if (tmp2 == preserve) {
89 assert_different_registers(tmp1, tmp2, tmp3, extra);
90 tmp2 = extra;
91 } else if (tmp3 == preserve) {
92 assert_different_registers(tmp1, tmp2, tmp3, extra);
93 tmp3 = extra;
94 }
95 assert_different_registers(preserve, tmp1, tmp2, tmp3);
96 }
97
98
99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
100
101
102 LIR_Opr LIR_Assembler::receiverOpr() {
103 return FrameMap::receiver_opr;
104 }
105
106 LIR_Opr LIR_Assembler::osrBufferPointer() {
107 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
108 }
109
110 //--------------fpu register translations-----------------------
111
112
113 address LIR_Assembler::float_constant(float f) {
114 address const_addr = __ float_constant(f);
115 if (const_addr == nullptr) {
116 bailout("const section overflow");
117 return __ code()->consts()->start();
118 } else {
119 return const_addr;
120 }
121 }
122
123
124 address LIR_Assembler::double_constant(double d) {
125 address const_addr = __ double_constant(d);
126 if (const_addr == nullptr) {
127 bailout("const section overflow");
128 return __ code()->consts()->start();
129 } else {
130 return const_addr;
131 }
132 }
133
134 address LIR_Assembler::int_constant(jlong n) {
135 address const_addr = __ long_constant(n);
136 if (const_addr == nullptr) {
137 bailout("const section overflow");
138 return __ code()->consts()->start();
139 } else {
140 return const_addr;
141 }
142 }
143
144 void LIR_Assembler::breakpoint() { Unimplemented(); }
145
146 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
147
148 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
149
150 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
151 //-------------------------------------------
152
153 static Register as_reg(LIR_Opr op) {
154 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
155 }
156
157 static jlong as_long(LIR_Opr data) {
158 jlong result;
159 switch (data->type()) {
160 case T_INT:
161 result = (data->as_jint());
162 break;
163 case T_LONG:
164 result = (data->as_jlong());
165 break;
166 default:
167 ShouldNotReachHere();
168 result = 0; // unreachable
169 }
170 return result;
171 }
172
173 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
174 Register base = addr->base()->as_pointer_register();
175 LIR_Opr opr = addr->index();
176 if (opr->is_cpu_register()) {
177 Register index;
178 if (opr->is_single_cpu())
179 index = opr->as_register();
180 else
181 index = opr->as_register_lo();
182 assert(addr->disp() == 0, "must be");
183 switch(opr->type()) {
184 case T_INT:
185 return Address(base, index, Address::sxtw(addr->scale()));
186 case T_LONG:
187 return Address(base, index, Address::lsl(addr->scale()));
188 default:
189 ShouldNotReachHere();
190 }
191 } else {
192 assert(addr->scale() == 0,
193 "expected for immediate operand, was: %d", addr->scale());
194 ptrdiff_t offset = ptrdiff_t(addr->disp());
195 // NOTE: Does not handle any 16 byte vector access.
196 const uint type_size = type2aelembytes(addr->type(), true);
197 return __ legitimize_address(Address(base, offset), type_size, tmp);
198 }
199 return Address();
200 }
201
202 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
203 ShouldNotReachHere();
204 return Address();
205 }
206
207 Address LIR_Assembler::as_Address(LIR_Address* addr) {
208 return as_Address(addr, rscratch1);
209 }
210
211 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
212 return as_Address(addr, rscratch1); // Ouch
213 // FIXME: This needs to be much more clever. See x86.
214 }
215
216 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
217 // not encodable as a base + (immediate) offset, generate an explicit address
218 // calculation to hold the address in a temporary register.
219 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
220 precond(size == 4 || size == 8);
221 Address addr = frame_map()->address_for_slot(index, adjust);
222 precond(addr.getMode() == Address::base_plus_offset);
223 precond(addr.base() == sp);
224 precond(addr.offset() > 0);
225 uint mask = size - 1;
226 assert((addr.offset() & mask) == 0, "scaled offsets only");
227 return __ legitimize_address(addr, size, tmp);
228 }
229
230 void LIR_Assembler::osr_entry() {
231 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
232 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
233 ValueStack* entry_state = osr_entry->state();
234 int number_of_locks = entry_state->locks_size();
235
236 // we jump here if osr happens with the interpreter
237 // state set up to continue at the beginning of the
238 // loop that triggered osr - in particular, we have
239 // the following registers setup:
240 //
241 // r2: osr buffer
242 //
243
244 // build frame
245 ciMethod* m = compilation()->method();
246 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
247
248 // OSR buffer is
249 //
250 // locals[nlocals-1..0]
251 // monitors[0..number_of_locks]
252 //
253 // locals is a direct copy of the interpreter frame so in the osr buffer
254 // so first slot in the local array is the last local from the interpreter
255 // and last slot is local[0] (receiver) from the interpreter
256 //
257 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
258 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
259 // in the interpreter frame (the method lock if a sync method)
260
261 // Initialize monitors in the compiled activation.
262 // r2: pointer to osr buffer
263 //
264 // All other registers are dead at this point and the locals will be
265 // copied into place by code emitted in the IR.
266
267 Register OSR_buf = osrBufferPointer()->as_pointer_register();
268 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
269 int monitor_offset = BytesPerWord * method()->max_locals() +
270 (2 * BytesPerWord) * (number_of_locks - 1);
271 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
272 // the OSR buffer using 2 word entries: first the lock and then
273 // the oop.
274 for (int i = 0; i < number_of_locks; i++) {
275 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
276 #ifdef ASSERT
277 // verify the interpreter's monitor has a non-null object
278 {
279 Label L;
280 __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
281 __ cbnz(rscratch1, L);
282 __ stop("locked object is null");
283 __ bind(L);
284 }
285 #endif
286 __ ldr(r19, Address(OSR_buf, slot_offset));
287 __ ldr(r20, Address(OSR_buf, slot_offset + BytesPerWord));
288 __ str(r19, frame_map()->address_for_monitor_lock(i));
289 __ str(r20, frame_map()->address_for_monitor_object(i));
290 }
291 }
292 }
293
294
295 // inline cache check; done before the frame is built.
296 int LIR_Assembler::check_icache() {
297 return __ ic_check(CodeEntryAlignment);
298 }
299
300 void LIR_Assembler::clinit_barrier(ciMethod* method) {
301 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
302 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
303
304 Label L_skip_barrier;
305
306 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
307 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
308 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
309 __ bind(L_skip_barrier);
310 }
311
312 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
313 if (o == nullptr) {
314 __ mov(reg, zr);
315 } else {
316 __ movoop(reg, o);
317 }
318 }
319
320 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
321 address target = nullptr;
322 relocInfo::relocType reloc_type = relocInfo::none;
323
324 switch (patching_id(info)) {
325 case PatchingStub::access_field_id:
326 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
327 reloc_type = relocInfo::section_word_type;
328 break;
329 case PatchingStub::load_klass_id:
330 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
331 reloc_type = relocInfo::metadata_type;
332 break;
333 case PatchingStub::load_mirror_id:
334 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
335 reloc_type = relocInfo::oop_type;
336 break;
337 case PatchingStub::load_appendix_id:
338 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
339 reloc_type = relocInfo::oop_type;
340 break;
341 default: ShouldNotReachHere();
342 }
343
344 __ far_call(RuntimeAddress(target));
345 add_call_info_here(info);
346 }
347
348 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
349 deoptimize_trap(info);
350 }
351
352
353 // This specifies the rsp decrement needed to build the frame
354 int LIR_Assembler::initial_frame_size_in_bytes() const {
355 // if rounding, must let FrameMap know!
356
357 return in_bytes(frame_map()->framesize_in_bytes());
358 }
359
360
361 int LIR_Assembler::emit_exception_handler() {
362 // generate code for exception handler
363 address handler_base = __ start_a_stub(exception_handler_size());
364 if (handler_base == nullptr) {
365 // not enough space left for the handler
366 bailout("exception handler overflow");
367 return -1;
368 }
369
370 int offset = code_offset();
371
372 // the exception oop and pc are in r0, and r3
373 // no other registers need to be preserved, so invalidate them
374 __ invalidate_registers(false, true, true, false, true, true);
375
376 // check that there is really an exception
377 __ verify_not_null_oop(r0);
378
379 // search an exception handler (r0: exception oop, r3: throwing pc)
380 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
381 __ should_not_reach_here();
382 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
383 __ end_a_stub();
384
385 return offset;
386 }
387
388
389 // Emit the code to remove the frame from the stack in the exception
390 // unwind path.
391 int LIR_Assembler::emit_unwind_handler() {
392 #ifndef PRODUCT
393 if (CommentedAssembly) {
394 _masm->block_comment("Unwind handler");
395 }
396 #endif
397
398 int offset = code_offset();
399
400 // Fetch the exception from TLS and clear out exception related thread state
401 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
402 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
403 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
404
405 __ bind(_unwind_handler_entry);
406 __ verify_not_null_oop(r0);
407 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
408 __ mov(r19, r0); // Preserve the exception
409 }
410
411 // Perform needed unlocking
412 MonitorExitStub* stub = nullptr;
413 if (method()->is_synchronized()) {
414 monitor_address(0, FrameMap::r0_opr);
415 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
416 if (LockingMode == LM_MONITOR) {
417 __ b(*stub->entry());
418 } else {
419 __ unlock_object(r5, r4, r0, r6, *stub->entry());
420 }
421 __ bind(*stub->continuation());
422 }
423
424 if (compilation()->env()->dtrace_method_probes()) {
425 __ mov(c_rarg0, rthread);
426 __ mov_metadata(c_rarg1, method()->constant_encoding());
427 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
428 }
429
430 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
431 __ mov(r0, r19); // Restore the exception
432 }
433
434 // remove the activation and dispatch to the unwind handler
435 __ block_comment("remove_frame and dispatch to the unwind handler");
436 __ remove_frame(initial_frame_size_in_bytes());
437 __ far_jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
438
439 // Emit the slow path assembly
440 if (stub != nullptr) {
441 stub->emit_code(this);
442 }
443
444 return offset;
445 }
446
447
448 int LIR_Assembler::emit_deopt_handler() {
449 // generate code for exception handler
450 address handler_base = __ start_a_stub(deopt_handler_size());
451 if (handler_base == nullptr) {
452 // not enough space left for the handler
453 bailout("deopt handler overflow");
454 return -1;
455 }
456
457 int offset = code_offset();
458
459 __ adr(lr, pc());
460 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
461 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
462 __ end_a_stub();
463
464 return offset;
465 }
466
467 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
468 _masm->code_section()->relocate(adr, relocInfo::poll_type);
469 int pc_offset = code_offset();
470 flush_debug_info(pc_offset);
471 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
472 if (info->exception_handlers() != nullptr) {
473 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
474 }
475 }
476
477 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
478 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
479
480 // Pop the stack before the safepoint code
481 __ remove_frame(initial_frame_size_in_bytes());
482
483 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
484 __ reserved_stack_check();
485 }
486
487 code_stub->set_safepoint_offset(__ offset());
488 __ relocate(relocInfo::poll_return_type);
489 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
490 __ ret(lr);
491 }
492
493 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
494 guarantee(info != nullptr, "Shouldn't be null");
495 __ get_polling_page(rscratch1, relocInfo::poll_type);
496 add_debug_info_for_branch(info); // This isn't just debug info:
497 // it's the oop map
498 __ read_polling_page(rscratch1, relocInfo::poll_type);
499 return __ offset();
500 }
501
502
503 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
504 if (from_reg == r31_sp)
505 from_reg = sp;
506 if (to_reg == r31_sp)
507 to_reg = sp;
508 __ mov(to_reg, from_reg);
509 }
510
511 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
512
513
514 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
515 assert(src->is_constant(), "should not call otherwise");
516 assert(dest->is_register(), "should not call otherwise");
517 LIR_Const* c = src->as_constant_ptr();
518
519 switch (c->type()) {
520 case T_INT: {
521 assert(patch_code == lir_patch_none, "no patching handled here");
522 __ movw(dest->as_register(), c->as_jint());
523 break;
524 }
525
526 case T_ADDRESS: {
527 assert(patch_code == lir_patch_none, "no patching handled here");
528 __ mov(dest->as_register(), c->as_jint());
529 break;
530 }
531
532 case T_LONG: {
533 assert(patch_code == lir_patch_none, "no patching handled here");
534 if (SCCache::is_on_for_write()) {
535 // SCA needs relocation info for card table base
536 address b = c->as_pointer();
537 if (is_card_table_address(b)) {
538 __ lea(dest->as_register_lo(), ExternalAddress(b));
539 break;
540 }
541 if (AOTRuntimeConstants::contains(b)) {
542 __ load_aotrc_address(dest->as_register_lo(), b);
543 break;
544 }
545 }
546 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
547 break;
548 }
549
550 case T_OBJECT: {
551 if (patch_code == lir_patch_none) {
552 jobject2reg(c->as_jobject(), dest->as_register());
553 } else {
554 jobject2reg_with_patching(dest->as_register(), info);
555 }
556 break;
557 }
558
559 case T_METADATA: {
560 if (patch_code != lir_patch_none) {
561 klass2reg_with_patching(dest->as_register(), info);
562 } else {
563 __ mov_metadata(dest->as_register(), c->as_metadata());
564 }
565 break;
566 }
567
568 case T_FLOAT: {
569 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
570 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
571 } else {
572 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
573 __ ldrs(dest->as_float_reg(), Address(rscratch1));
574 }
575 break;
576 }
577
578 case T_DOUBLE: {
579 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
580 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
581 } else {
582 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
583 __ ldrd(dest->as_double_reg(), Address(rscratch1));
584 }
585 break;
586 }
587
588 default:
589 ShouldNotReachHere();
590 }
591 }
592
593 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
594 LIR_Const* c = src->as_constant_ptr();
595 switch (c->type()) {
596 case T_OBJECT:
597 {
598 if (! c->as_jobject())
599 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
600 else {
601 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
602 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
603 }
604 }
605 break;
606 case T_ADDRESS:
607 {
608 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
609 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
610 }
611 case T_INT:
612 case T_FLOAT:
613 {
614 Register reg = zr;
615 if (c->as_jint_bits() == 0)
616 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
617 else {
618 __ movw(rscratch1, c->as_jint_bits());
619 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
620 }
621 }
622 break;
623 case T_LONG:
624 case T_DOUBLE:
625 {
626 Register reg = zr;
627 if (c->as_jlong_bits() == 0)
628 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
629 lo_word_offset_in_bytes));
630 else {
631 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
632 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
633 lo_word_offset_in_bytes));
634 }
635 }
636 break;
637 default:
638 ShouldNotReachHere();
639 }
640 }
641
642 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
643 assert(src->is_constant(), "should not call otherwise");
644 LIR_Const* c = src->as_constant_ptr();
645 LIR_Address* to_addr = dest->as_address_ptr();
646
647 void (Assembler::* insn)(Register Rt, const Address &adr);
648
649 switch (type) {
650 case T_ADDRESS:
651 assert(c->as_jint() == 0, "should be");
652 insn = &Assembler::str;
653 break;
654 case T_LONG:
655 assert(c->as_jlong() == 0, "should be");
656 insn = &Assembler::str;
657 break;
658 case T_INT:
659 assert(c->as_jint() == 0, "should be");
660 insn = &Assembler::strw;
661 break;
662 case T_OBJECT:
663 case T_ARRAY:
664 assert(c->as_jobject() == nullptr, "should be");
665 if (UseCompressedOops && !wide) {
666 insn = &Assembler::strw;
667 } else {
668 insn = &Assembler::str;
669 }
670 break;
671 case T_CHAR:
672 case T_SHORT:
673 assert(c->as_jint() == 0, "should be");
674 insn = &Assembler::strh;
675 break;
676 case T_BOOLEAN:
677 case T_BYTE:
678 assert(c->as_jint() == 0, "should be");
679 insn = &Assembler::strb;
680 break;
681 default:
682 ShouldNotReachHere();
683 insn = &Assembler::str; // unreachable
684 }
685
686 if (info) add_debug_info_for_null_check_here(info);
687 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
688 }
689
690 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
691 assert(src->is_register(), "should not call otherwise");
692 assert(dest->is_register(), "should not call otherwise");
693
694 // move between cpu-registers
695 if (dest->is_single_cpu()) {
696 if (src->type() == T_LONG) {
697 // Can do LONG -> OBJECT
698 move_regs(src->as_register_lo(), dest->as_register());
699 return;
700 }
701 assert(src->is_single_cpu(), "must match");
702 if (src->type() == T_OBJECT) {
703 __ verify_oop(src->as_register());
704 }
705 move_regs(src->as_register(), dest->as_register());
706
707 } else if (dest->is_double_cpu()) {
708 if (is_reference_type(src->type())) {
709 // Surprising to me but we can see move of a long to t_object
710 __ verify_oop(src->as_register());
711 move_regs(src->as_register(), dest->as_register_lo());
712 return;
713 }
714 assert(src->is_double_cpu(), "must match");
715 Register f_lo = src->as_register_lo();
716 Register f_hi = src->as_register_hi();
717 Register t_lo = dest->as_register_lo();
718 Register t_hi = dest->as_register_hi();
719 assert(f_hi == f_lo, "must be same");
720 assert(t_hi == t_lo, "must be same");
721 move_regs(f_lo, t_lo);
722
723 } else if (dest->is_single_fpu()) {
724 __ fmovs(dest->as_float_reg(), src->as_float_reg());
725
726 } else if (dest->is_double_fpu()) {
727 __ fmovd(dest->as_double_reg(), src->as_double_reg());
728
729 } else {
730 ShouldNotReachHere();
731 }
732 }
733
734 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
735 precond(src->is_register() && dest->is_stack());
736
737 uint const c_sz32 = sizeof(uint32_t);
738 uint const c_sz64 = sizeof(uint64_t);
739
740 if (src->is_single_cpu()) {
741 int index = dest->single_stack_ix();
742 if (is_reference_type(type)) {
743 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
744 __ verify_oop(src->as_register());
745 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
746 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
747 } else {
748 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
749 }
750
751 } else if (src->is_double_cpu()) {
752 int index = dest->double_stack_ix();
753 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
754 __ str(src->as_register_lo(), dest_addr_LO);
755
756 } else if (src->is_single_fpu()) {
757 int index = dest->single_stack_ix();
758 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
759
760 } else if (src->is_double_fpu()) {
761 int index = dest->double_stack_ix();
762 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
763
764 } else {
765 ShouldNotReachHere();
766 }
767 }
768
769
770 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
771 LIR_Address* to_addr = dest->as_address_ptr();
772 PatchingStub* patch = nullptr;
773 Register compressed_src = rscratch1;
774
775 if (patch_code != lir_patch_none) {
776 deoptimize_trap(info);
777 return;
778 }
779
780 if (is_reference_type(type)) {
781 __ verify_oop(src->as_register());
782
783 if (UseCompressedOops && !wide) {
784 __ encode_heap_oop(compressed_src, src->as_register());
785 } else {
786 compressed_src = src->as_register();
787 }
788 }
789
790 int null_check_here = code_offset();
791 switch (type) {
792 case T_FLOAT: {
793 __ strs(src->as_float_reg(), as_Address(to_addr));
794 break;
795 }
796
797 case T_DOUBLE: {
798 __ strd(src->as_double_reg(), as_Address(to_addr));
799 break;
800 }
801
802 case T_ARRAY: // fall through
803 case T_OBJECT: // fall through
804 if (UseCompressedOops && !wide) {
805 __ strw(compressed_src, as_Address(to_addr, rscratch2));
806 } else {
807 __ str(compressed_src, as_Address(to_addr));
808 }
809 break;
810 case T_METADATA:
811 // We get here to store a method pointer to the stack to pass to
812 // a dtrace runtime call. This can't work on 64 bit with
813 // compressed klass ptrs: T_METADATA can be a compressed klass
814 // ptr or a 64 bit method pointer.
815 ShouldNotReachHere();
816 __ str(src->as_register(), as_Address(to_addr));
817 break;
818 case T_ADDRESS:
819 __ str(src->as_register(), as_Address(to_addr));
820 break;
821 case T_INT:
822 __ strw(src->as_register(), as_Address(to_addr));
823 break;
824
825 case T_LONG: {
826 __ str(src->as_register_lo(), as_Address_lo(to_addr));
827 break;
828 }
829
830 case T_BYTE: // fall through
831 case T_BOOLEAN: {
832 __ strb(src->as_register(), as_Address(to_addr));
833 break;
834 }
835
836 case T_CHAR: // fall through
837 case T_SHORT:
838 __ strh(src->as_register(), as_Address(to_addr));
839 break;
840
841 default:
842 ShouldNotReachHere();
843 }
844 if (info != nullptr) {
845 add_debug_info_for_null_check(null_check_here, info);
846 }
847 }
848
849
850 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
851 precond(src->is_stack() && dest->is_register());
852
853 uint const c_sz32 = sizeof(uint32_t);
854 uint const c_sz64 = sizeof(uint64_t);
855
856 if (dest->is_single_cpu()) {
857 int index = src->single_stack_ix();
858 if (is_reference_type(type)) {
859 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
860 __ verify_oop(dest->as_register());
861 } else if (type == T_METADATA || type == T_ADDRESS) {
862 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
863 } else {
864 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
865 }
866
867 } else if (dest->is_double_cpu()) {
868 int index = src->double_stack_ix();
869 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
870 __ ldr(dest->as_register_lo(), src_addr_LO);
871
872 } else if (dest->is_single_fpu()) {
873 int index = src->single_stack_ix();
874 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
875
876 } else if (dest->is_double_fpu()) {
877 int index = src->double_stack_ix();
878 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
879
880 } else {
881 ShouldNotReachHere();
882 }
883 }
884
885
886 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
887 address target = nullptr;
888 relocInfo::relocType reloc_type = relocInfo::none;
889
890 switch (patching_id(info)) {
891 case PatchingStub::access_field_id:
892 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
893 reloc_type = relocInfo::section_word_type;
894 break;
895 case PatchingStub::load_klass_id:
896 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
897 reloc_type = relocInfo::metadata_type;
898 break;
899 case PatchingStub::load_mirror_id:
900 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
901 reloc_type = relocInfo::oop_type;
902 break;
903 case PatchingStub::load_appendix_id:
904 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
905 reloc_type = relocInfo::oop_type;
906 break;
907 default: ShouldNotReachHere();
908 }
909
910 __ far_call(RuntimeAddress(target));
911 add_call_info_here(info);
912 }
913
914 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
915
916 LIR_Opr temp;
917 if (type == T_LONG || type == T_DOUBLE)
918 temp = FrameMap::rscratch1_long_opr;
919 else
920 temp = FrameMap::rscratch1_opr;
921
922 stack2reg(src, temp, src->type());
923 reg2stack(temp, dest, dest->type(), false);
924 }
925
926
927 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
928 LIR_Address* addr = src->as_address_ptr();
929 LIR_Address* from_addr = src->as_address_ptr();
930
931 if (addr->base()->type() == T_OBJECT) {
932 __ verify_oop(addr->base()->as_pointer_register());
933 }
934
935 if (patch_code != lir_patch_none) {
936 deoptimize_trap(info);
937 return;
938 }
939
940 if (info != nullptr) {
941 add_debug_info_for_null_check_here(info);
942 }
943 int null_check_here = code_offset();
944 switch (type) {
945 case T_FLOAT: {
946 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
947 break;
948 }
949
950 case T_DOUBLE: {
951 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
952 break;
953 }
954
955 case T_ARRAY: // fall through
956 case T_OBJECT: // fall through
957 if (UseCompressedOops && !wide) {
958 __ ldrw(dest->as_register(), as_Address(from_addr));
959 } else {
960 __ ldr(dest->as_register(), as_Address(from_addr));
961 }
962 break;
963 case T_METADATA:
964 // We get here to store a method pointer to the stack to pass to
965 // a dtrace runtime call. This can't work on 64 bit with
966 // compressed klass ptrs: T_METADATA can be a compressed klass
967 // ptr or a 64 bit method pointer.
968 ShouldNotReachHere();
969 __ ldr(dest->as_register(), as_Address(from_addr));
970 break;
971 case T_ADDRESS:
972 __ ldr(dest->as_register(), as_Address(from_addr));
973 break;
974 case T_INT:
975 __ ldrw(dest->as_register(), as_Address(from_addr));
976 break;
977
978 case T_LONG: {
979 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
980 break;
981 }
982
983 case T_BYTE:
984 __ ldrsb(dest->as_register(), as_Address(from_addr));
985 break;
986 case T_BOOLEAN: {
987 __ ldrb(dest->as_register(), as_Address(from_addr));
988 break;
989 }
990
991 case T_CHAR:
992 __ ldrh(dest->as_register(), as_Address(from_addr));
993 break;
994 case T_SHORT:
995 __ ldrsh(dest->as_register(), as_Address(from_addr));
996 break;
997
998 default:
999 ShouldNotReachHere();
1000 }
1001
1002 if (is_reference_type(type)) {
1003 if (UseCompressedOops && !wide) {
1004 __ decode_heap_oop(dest->as_register());
1005 }
1006
1007 if (!(UseZGC && !ZGenerational)) {
1008 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1009 __ verify_oop(dest->as_register());
1010 }
1011 }
1012 }
1013
1014
1015 int LIR_Assembler::array_element_size(BasicType type) const {
1016 int elem_size = type2aelembytes(type);
1017 return exact_log2(elem_size);
1018 }
1019
1020
1021 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1022 switch (op->code()) {
1023 case lir_idiv:
1024 case lir_irem:
1025 arithmetic_idiv(op->code(),
1026 op->in_opr1(),
1027 op->in_opr2(),
1028 op->in_opr3(),
1029 op->result_opr(),
1030 op->info());
1031 break;
1032 case lir_fmad:
1033 __ fmaddd(op->result_opr()->as_double_reg(),
1034 op->in_opr1()->as_double_reg(),
1035 op->in_opr2()->as_double_reg(),
1036 op->in_opr3()->as_double_reg());
1037 break;
1038 case lir_fmaf:
1039 __ fmadds(op->result_opr()->as_float_reg(),
1040 op->in_opr1()->as_float_reg(),
1041 op->in_opr2()->as_float_reg(),
1042 op->in_opr3()->as_float_reg());
1043 break;
1044 default: ShouldNotReachHere(); break;
1045 }
1046 }
1047
1048 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1049 #ifdef ASSERT
1050 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1051 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1052 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1053 #endif
1054
1055 if (op->cond() == lir_cond_always) {
1056 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1057 __ b(*(op->label()));
1058 } else {
1059 Assembler::Condition acond;
1060 if (op->code() == lir_cond_float_branch) {
1061 bool is_unordered = (op->ublock() == op->block());
1062 // Assembler::EQ does not permit unordered branches, so we add
1063 // another branch here. Likewise, Assembler::NE does not permit
1064 // ordered branches.
1065 if ((is_unordered && op->cond() == lir_cond_equal)
1066 || (!is_unordered && op->cond() == lir_cond_notEqual))
1067 __ br(Assembler::VS, *(op->ublock()->label()));
1068 switch(op->cond()) {
1069 case lir_cond_equal: acond = Assembler::EQ; break;
1070 case lir_cond_notEqual: acond = Assembler::NE; break;
1071 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1072 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1073 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1074 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1075 default: ShouldNotReachHere();
1076 acond = Assembler::EQ; // unreachable
1077 }
1078 } else {
1079 switch (op->cond()) {
1080 case lir_cond_equal: acond = Assembler::EQ; break;
1081 case lir_cond_notEqual: acond = Assembler::NE; break;
1082 case lir_cond_less: acond = Assembler::LT; break;
1083 case lir_cond_lessEqual: acond = Assembler::LE; break;
1084 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1085 case lir_cond_greater: acond = Assembler::GT; break;
1086 case lir_cond_belowEqual: acond = Assembler::LS; break;
1087 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1088 default: ShouldNotReachHere();
1089 acond = Assembler::EQ; // unreachable
1090 }
1091 }
1092 __ br(acond,*(op->label()));
1093 }
1094 }
1095
1096
1097
1098 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1099 LIR_Opr src = op->in_opr();
1100 LIR_Opr dest = op->result_opr();
1101
1102 switch (op->bytecode()) {
1103 case Bytecodes::_i2f:
1104 {
1105 __ scvtfws(dest->as_float_reg(), src->as_register());
1106 break;
1107 }
1108 case Bytecodes::_i2d:
1109 {
1110 __ scvtfwd(dest->as_double_reg(), src->as_register());
1111 break;
1112 }
1113 case Bytecodes::_l2d:
1114 {
1115 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1116 break;
1117 }
1118 case Bytecodes::_l2f:
1119 {
1120 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1121 break;
1122 }
1123 case Bytecodes::_f2d:
1124 {
1125 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1126 break;
1127 }
1128 case Bytecodes::_d2f:
1129 {
1130 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1131 break;
1132 }
1133 case Bytecodes::_i2c:
1134 {
1135 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1136 break;
1137 }
1138 case Bytecodes::_i2l:
1139 {
1140 __ sxtw(dest->as_register_lo(), src->as_register());
1141 break;
1142 }
1143 case Bytecodes::_i2s:
1144 {
1145 __ sxth(dest->as_register(), src->as_register());
1146 break;
1147 }
1148 case Bytecodes::_i2b:
1149 {
1150 __ sxtb(dest->as_register(), src->as_register());
1151 break;
1152 }
1153 case Bytecodes::_l2i:
1154 {
1155 _masm->block_comment("FIXME: This could be a no-op");
1156 __ uxtw(dest->as_register(), src->as_register_lo());
1157 break;
1158 }
1159 case Bytecodes::_d2l:
1160 {
1161 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1162 break;
1163 }
1164 case Bytecodes::_f2i:
1165 {
1166 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1167 break;
1168 }
1169 case Bytecodes::_f2l:
1170 {
1171 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1172 break;
1173 }
1174 case Bytecodes::_d2i:
1175 {
1176 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1177 break;
1178 }
1179 default: ShouldNotReachHere();
1180 }
1181 }
1182
1183 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1184 if (op->init_check()) {
1185 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1186 __ ldarb(rscratch1, rscratch1);
1187 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1188 add_debug_info_for_null_check_here(op->stub()->info());
1189 __ br(Assembler::NE, *op->stub()->entry());
1190 }
1191 __ allocate_object(op->obj()->as_register(),
1192 op->tmp1()->as_register(),
1193 op->tmp2()->as_register(),
1194 op->header_size(),
1195 op->object_size(),
1196 op->klass()->as_register(),
1197 *op->stub()->entry());
1198 __ bind(*op->stub()->continuation());
1199 }
1200
1201 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1202 Register len = op->len()->as_register();
1203 __ uxtw(len, len);
1204
1205 if (UseSlowPath ||
1206 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1207 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1208 __ b(*op->stub()->entry());
1209 } else {
1210 Register tmp1 = op->tmp1()->as_register();
1211 Register tmp2 = op->tmp2()->as_register();
1212 Register tmp3 = op->tmp3()->as_register();
1213 if (len == tmp1) {
1214 tmp1 = tmp3;
1215 } else if (len == tmp2) {
1216 tmp2 = tmp3;
1217 } else if (len == tmp3) {
1218 // everything is ok
1219 } else {
1220 __ mov(tmp3, len);
1221 }
1222 __ allocate_array(op->obj()->as_register(),
1223 len,
1224 tmp1,
1225 tmp2,
1226 arrayOopDesc::base_offset_in_bytes(op->type()),
1227 array_element_size(op->type()),
1228 op->klass()->as_register(),
1229 *op->stub()->entry(),
1230 op->zero_array());
1231 }
1232 __ bind(*op->stub()->continuation());
1233 }
1234
1235 void LIR_Assembler::type_profile_helper(Register mdo,
1236 ciMethodData *md, ciProfileData *data,
1237 Register recv, Label* update_done) {
1238 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1239 Label next_test;
1240 // See if the receiver is receiver[n].
1241 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1242 __ ldr(rscratch1, Address(rscratch2));
1243 __ cmp(recv, rscratch1);
1244 __ br(Assembler::NE, next_test);
1245 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1246 __ addptr(data_addr, DataLayout::counter_increment);
1247 __ b(*update_done);
1248 __ bind(next_test);
1249 }
1250
1251 // Didn't find receiver; find next empty slot and fill it in
1252 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1253 Label next_test;
1254 __ lea(rscratch2,
1255 Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1256 Address recv_addr(rscratch2);
1257 __ ldr(rscratch1, recv_addr);
1258 __ cbnz(rscratch1, next_test);
1259 __ str(recv, recv_addr);
1260 __ mov(rscratch1, DataLayout::counter_increment);
1261 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1262 __ str(rscratch1, Address(rscratch2));
1263 __ b(*update_done);
1264 __ bind(next_test);
1265 }
1266 }
1267
1268 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1269 // we always need a stub for the failure case.
1270 CodeStub* stub = op->stub();
1271 Register obj = op->object()->as_register();
1272 Register k_RInfo = op->tmp1()->as_register();
1273 Register klass_RInfo = op->tmp2()->as_register();
1274 Register dst = op->result_opr()->as_register();
1275 ciKlass* k = op->klass();
1276 Register Rtmp1 = noreg;
1277
1278 // check if it needs to be profiled
1279 ciMethodData* md;
1280 ciProfileData* data;
1281
1282 const bool should_profile = op->should_profile();
1283
1284 if (should_profile) {
1285 ciMethod* method = op->profiled_method();
1286 assert(method != nullptr, "Should have method");
1287 int bci = op->profiled_bci();
1288 md = method->method_data_or_null();
1289 assert(md != nullptr, "Sanity");
1290 data = md->bci_to_data(bci);
1291 assert(data != nullptr, "need data for type check");
1292 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1293 }
1294 Label* success_target = success;
1295 Label* failure_target = failure;
1296
1297 if (obj == k_RInfo) {
1298 k_RInfo = dst;
1299 } else if (obj == klass_RInfo) {
1300 klass_RInfo = dst;
1301 }
1302 if (k->is_loaded() && !UseCompressedClassPointers) {
1303 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1304 } else {
1305 Rtmp1 = op->tmp3()->as_register();
1306 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1307 }
1308
1309 assert_different_registers(obj, k_RInfo, klass_RInfo);
1310
1311 if (should_profile) {
1312 Register mdo = klass_RInfo;
1313 __ mov_metadata(mdo, md->constant_encoding());
1314 Label not_null;
1315 __ cbnz(obj, not_null);
1316 // Object is null; update MDO and exit
1317 Address data_addr
1318 = __ form_address(rscratch2, mdo,
1319 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1320 0);
1321 __ ldrb(rscratch1, data_addr);
1322 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1323 __ strb(rscratch1, data_addr);
1324 __ b(*obj_is_null);
1325 __ bind(not_null);
1326
1327 Label update_done;
1328 Register recv = k_RInfo;
1329 __ load_klass(recv, obj);
1330 type_profile_helper(mdo, md, data, recv, &update_done);
1331 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1332 __ addptr(counter_addr, DataLayout::counter_increment);
1333
1334 __ bind(update_done);
1335 } else {
1336 __ cbz(obj, *obj_is_null);
1337 }
1338
1339 if (!k->is_loaded()) {
1340 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1341 } else {
1342 __ mov_metadata(k_RInfo, k->constant_encoding());
1343 }
1344 __ verify_oop(obj);
1345
1346 if (op->fast_check()) {
1347 // get object class
1348 // not a safepoint as obj null check happens earlier
1349 __ load_klass(rscratch1, obj);
1350 __ cmp( rscratch1, k_RInfo);
1351
1352 __ br(Assembler::NE, *failure_target);
1353 // successful cast, fall through to profile or jump
1354 } else {
1355 // get object class
1356 // not a safepoint as obj null check happens earlier
1357 __ load_klass(klass_RInfo, obj);
1358 if (k->is_loaded()) {
1359 // See if we get an immediate positive hit
1360 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1361 __ cmp(k_RInfo, rscratch1);
1362 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1363 __ br(Assembler::NE, *failure_target);
1364 // successful cast, fall through to profile or jump
1365 } else {
1366 // See if we get an immediate positive hit
1367 __ br(Assembler::EQ, *success_target);
1368 // check for self
1369 __ cmp(klass_RInfo, k_RInfo);
1370 __ br(Assembler::EQ, *success_target);
1371
1372 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1373 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1374 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1375 // result is a boolean
1376 __ cbzw(klass_RInfo, *failure_target);
1377 // successful cast, fall through to profile or jump
1378 }
1379 } else {
1380 // perform the fast part of the checking logic
1381 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1382 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1383 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1384 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1385 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1386 // result is a boolean
1387 __ cbz(k_RInfo, *failure_target);
1388 // successful cast, fall through to profile or jump
1389 }
1390 }
1391 __ b(*success);
1392 }
1393
1394
1395 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1396 const bool should_profile = op->should_profile();
1397
1398 LIR_Code code = op->code();
1399 if (code == lir_store_check) {
1400 Register value = op->object()->as_register();
1401 Register array = op->array()->as_register();
1402 Register k_RInfo = op->tmp1()->as_register();
1403 Register klass_RInfo = op->tmp2()->as_register();
1404 Register Rtmp1 = op->tmp3()->as_register();
1405
1406 CodeStub* stub = op->stub();
1407
1408 // check if it needs to be profiled
1409 ciMethodData* md;
1410 ciProfileData* data;
1411
1412 if (should_profile) {
1413 ciMethod* method = op->profiled_method();
1414 assert(method != nullptr, "Should have method");
1415 int bci = op->profiled_bci();
1416 md = method->method_data_or_null();
1417 assert(md != nullptr, "Sanity");
1418 data = md->bci_to_data(bci);
1419 assert(data != nullptr, "need data for type check");
1420 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1421 }
1422 Label done;
1423 Label* success_target = &done;
1424 Label* failure_target = stub->entry();
1425
1426 if (should_profile) {
1427 Label not_null;
1428 Register mdo = klass_RInfo;
1429 __ mov_metadata(mdo, md->constant_encoding());
1430 __ cbnz(value, not_null);
1431 // Object is null; update MDO and exit
1432 Address data_addr
1433 = __ form_address(rscratch2, mdo,
1434 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1435 0);
1436 __ ldrb(rscratch1, data_addr);
1437 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1438 __ strb(rscratch1, data_addr);
1439 __ b(done);
1440 __ bind(not_null);
1441
1442 Label update_done;
1443 Register recv = k_RInfo;
1444 __ load_klass(recv, value);
1445 type_profile_helper(mdo, md, data, recv, &update_done);
1446 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1447 __ addptr(counter_addr, DataLayout::counter_increment);
1448 __ bind(update_done);
1449 } else {
1450 __ cbz(value, done);
1451 }
1452
1453 add_debug_info_for_null_check_here(op->info_for_exception());
1454 __ load_klass(k_RInfo, array);
1455 __ load_klass(klass_RInfo, value);
1456
1457 // get instance klass (it's already uncompressed)
1458 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1459 // perform the fast part of the checking logic
1460 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1461 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1462 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1463 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1464 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1465 // result is a boolean
1466 __ cbzw(k_RInfo, *failure_target);
1467 // fall through to the success case
1468
1469 __ bind(done);
1470 } else if (code == lir_checkcast) {
1471 Register obj = op->object()->as_register();
1472 Register dst = op->result_opr()->as_register();
1473 Label success;
1474 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1475 __ bind(success);
1476 if (dst != obj) {
1477 __ mov(dst, obj);
1478 }
1479 } else if (code == lir_instanceof) {
1480 Register obj = op->object()->as_register();
1481 Register dst = op->result_opr()->as_register();
1482 Label success, failure, done;
1483 emit_typecheck_helper(op, &success, &failure, &failure);
1484 __ bind(failure);
1485 __ mov(dst, zr);
1486 __ b(done);
1487 __ bind(success);
1488 __ mov(dst, 1);
1489 __ bind(done);
1490 } else {
1491 ShouldNotReachHere();
1492 }
1493 }
1494
1495 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1496 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1497 __ cset(rscratch1, Assembler::NE);
1498 __ membar(__ AnyAny);
1499 }
1500
1501 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1502 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1503 __ cset(rscratch1, Assembler::NE);
1504 __ membar(__ AnyAny);
1505 }
1506
1507
1508 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1509 Register addr;
1510 if (op->addr()->is_register()) {
1511 addr = as_reg(op->addr());
1512 } else {
1513 assert(op->addr()->is_address(), "what else?");
1514 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1515 assert(addr_ptr->disp() == 0, "need 0 disp");
1516 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1517 addr = as_reg(addr_ptr->base());
1518 }
1519 Register newval = as_reg(op->new_value());
1520 Register cmpval = as_reg(op->cmp_value());
1521
1522 if (op->code() == lir_cas_obj) {
1523 if (UseCompressedOops) {
1524 Register t1 = op->tmp1()->as_register();
1525 assert(op->tmp1()->is_valid(), "must be");
1526 __ encode_heap_oop(t1, cmpval);
1527 cmpval = t1;
1528 __ encode_heap_oop(rscratch2, newval);
1529 newval = rscratch2;
1530 casw(addr, newval, cmpval);
1531 } else {
1532 casl(addr, newval, cmpval);
1533 }
1534 } else if (op->code() == lir_cas_int) {
1535 casw(addr, newval, cmpval);
1536 } else {
1537 casl(addr, newval, cmpval);
1538 }
1539 }
1540
1541
1542 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1543 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1544 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1545
1546 Assembler::Condition acond, ncond;
1547 switch (condition) {
1548 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1549 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1550 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1551 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1552 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1553 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1554 case lir_cond_belowEqual:
1555 case lir_cond_aboveEqual:
1556 default: ShouldNotReachHere();
1557 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1558 }
1559
1560 assert(result->is_single_cpu() || result->is_double_cpu(),
1561 "expect single register for result");
1562 if (opr1->is_constant() && opr2->is_constant()
1563 && opr1->type() == T_INT && opr2->type() == T_INT) {
1564 jint val1 = opr1->as_jint();
1565 jint val2 = opr2->as_jint();
1566 if (val1 == 0 && val2 == 1) {
1567 __ cset(result->as_register(), ncond);
1568 return;
1569 } else if (val1 == 1 && val2 == 0) {
1570 __ cset(result->as_register(), acond);
1571 return;
1572 }
1573 }
1574
1575 if (opr1->is_constant() && opr2->is_constant()
1576 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1577 jlong val1 = opr1->as_jlong();
1578 jlong val2 = opr2->as_jlong();
1579 if (val1 == 0 && val2 == 1) {
1580 __ cset(result->as_register_lo(), ncond);
1581 return;
1582 } else if (val1 == 1 && val2 == 0) {
1583 __ cset(result->as_register_lo(), acond);
1584 return;
1585 }
1586 }
1587
1588 if (opr1->is_stack()) {
1589 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1590 opr1 = FrameMap::rscratch1_opr;
1591 } else if (opr1->is_constant()) {
1592 LIR_Opr tmp
1593 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1594 const2reg(opr1, tmp, lir_patch_none, nullptr);
1595 opr1 = tmp;
1596 }
1597
1598 if (opr2->is_stack()) {
1599 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1600 opr2 = FrameMap::rscratch2_opr;
1601 } else if (opr2->is_constant()) {
1602 LIR_Opr tmp
1603 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1604 const2reg(opr2, tmp, lir_patch_none, nullptr);
1605 opr2 = tmp;
1606 }
1607
1608 if (result->type() == T_LONG)
1609 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1610 else
1611 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1612 }
1613
1614 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1615 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1616
1617 if (left->is_single_cpu()) {
1618 Register lreg = left->as_register();
1619 Register dreg = as_reg(dest);
1620
1621 if (right->is_single_cpu()) {
1622 // cpu register - cpu register
1623
1624 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1625 "should be");
1626 Register rreg = right->as_register();
1627 switch (code) {
1628 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1629 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1630 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1631 default: ShouldNotReachHere();
1632 }
1633
1634 } else if (right->is_double_cpu()) {
1635 Register rreg = right->as_register_lo();
1636 // single_cpu + double_cpu: can happen with obj+long
1637 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1638 switch (code) {
1639 case lir_add: __ add(dreg, lreg, rreg); break;
1640 case lir_sub: __ sub(dreg, lreg, rreg); break;
1641 default: ShouldNotReachHere();
1642 }
1643 } else if (right->is_constant()) {
1644 // cpu register - constant
1645 jlong c;
1646
1647 // FIXME. This is fugly: we really need to factor all this logic.
1648 switch(right->type()) {
1649 case T_LONG:
1650 c = right->as_constant_ptr()->as_jlong();
1651 break;
1652 case T_INT:
1653 case T_ADDRESS:
1654 c = right->as_constant_ptr()->as_jint();
1655 break;
1656 default:
1657 ShouldNotReachHere();
1658 c = 0; // unreachable
1659 break;
1660 }
1661
1662 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1663 if (c == 0 && dreg == lreg) {
1664 COMMENT("effective nop elided");
1665 return;
1666 }
1667 switch(left->type()) {
1668 case T_INT:
1669 switch (code) {
1670 case lir_add: __ addw(dreg, lreg, c); break;
1671 case lir_sub: __ subw(dreg, lreg, c); break;
1672 default: ShouldNotReachHere();
1673 }
1674 break;
1675 case T_OBJECT:
1676 case T_ADDRESS:
1677 switch (code) {
1678 case lir_add: __ add(dreg, lreg, c); break;
1679 case lir_sub: __ sub(dreg, lreg, c); break;
1680 default: ShouldNotReachHere();
1681 }
1682 break;
1683 default:
1684 ShouldNotReachHere();
1685 }
1686 } else {
1687 ShouldNotReachHere();
1688 }
1689
1690 } else if (left->is_double_cpu()) {
1691 Register lreg_lo = left->as_register_lo();
1692
1693 if (right->is_double_cpu()) {
1694 // cpu register - cpu register
1695 Register rreg_lo = right->as_register_lo();
1696 switch (code) {
1697 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1698 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1699 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1700 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1701 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1702 default:
1703 ShouldNotReachHere();
1704 }
1705
1706 } else if (right->is_constant()) {
1707 jlong c = right->as_constant_ptr()->as_jlong();
1708 Register dreg = as_reg(dest);
1709 switch (code) {
1710 case lir_add:
1711 case lir_sub:
1712 if (c == 0 && dreg == lreg_lo) {
1713 COMMENT("effective nop elided");
1714 return;
1715 }
1716 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1717 break;
1718 case lir_div:
1719 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1720 if (c == 1) {
1721 // move lreg_lo to dreg if divisor is 1
1722 __ mov(dreg, lreg_lo);
1723 } else {
1724 unsigned int shift = log2i_exact(c);
1725 // use rscratch1 as intermediate result register
1726 __ asr(rscratch1, lreg_lo, 63);
1727 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1728 __ asr(dreg, rscratch1, shift);
1729 }
1730 break;
1731 case lir_rem:
1732 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1733 if (c == 1) {
1734 // move 0 to dreg if divisor is 1
1735 __ mov(dreg, zr);
1736 } else {
1737 // use rscratch1 as intermediate result register
1738 __ negs(rscratch1, lreg_lo);
1739 __ andr(dreg, lreg_lo, c - 1);
1740 __ andr(rscratch1, rscratch1, c - 1);
1741 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1742 }
1743 break;
1744 default:
1745 ShouldNotReachHere();
1746 }
1747 } else {
1748 ShouldNotReachHere();
1749 }
1750 } else if (left->is_single_fpu()) {
1751 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1752 switch (code) {
1753 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1754 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1755 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1756 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1757 default:
1758 ShouldNotReachHere();
1759 }
1760 } else if (left->is_double_fpu()) {
1761 if (right->is_double_fpu()) {
1762 // fpu register - fpu register
1763 switch (code) {
1764 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1765 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1766 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1767 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1768 default:
1769 ShouldNotReachHere();
1770 }
1771 } else {
1772 if (right->is_constant()) {
1773 ShouldNotReachHere();
1774 }
1775 ShouldNotReachHere();
1776 }
1777 } else if (left->is_single_stack() || left->is_address()) {
1778 assert(left == dest, "left and dest must be equal");
1779 ShouldNotReachHere();
1780 } else {
1781 ShouldNotReachHere();
1782 }
1783 }
1784
1785 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1786
1787
1788 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1789 switch(code) {
1790 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1791 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1792 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1793 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1794 default : ShouldNotReachHere();
1795 }
1796 }
1797
1798 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1799
1800 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1801 Register Rleft = left->is_single_cpu() ? left->as_register() :
1802 left->as_register_lo();
1803 if (dst->is_single_cpu()) {
1804 Register Rdst = dst->as_register();
1805 if (right->is_constant()) {
1806 switch (code) {
1807 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1808 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1809 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1810 default: ShouldNotReachHere(); break;
1811 }
1812 } else {
1813 Register Rright = right->is_single_cpu() ? right->as_register() :
1814 right->as_register_lo();
1815 switch (code) {
1816 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1817 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1818 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1819 default: ShouldNotReachHere(); break;
1820 }
1821 }
1822 } else {
1823 Register Rdst = dst->as_register_lo();
1824 if (right->is_constant()) {
1825 switch (code) {
1826 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1827 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1828 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1829 default: ShouldNotReachHere(); break;
1830 }
1831 } else {
1832 Register Rright = right->is_single_cpu() ? right->as_register() :
1833 right->as_register_lo();
1834 switch (code) {
1835 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1836 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1837 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1838 default: ShouldNotReachHere(); break;
1839 }
1840 }
1841 }
1842 }
1843
1844
1845
1846 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1847
1848 // opcode check
1849 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1850 bool is_irem = (code == lir_irem);
1851
1852 // operand check
1853 assert(left->is_single_cpu(), "left must be register");
1854 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1855 assert(result->is_single_cpu(), "result must be register");
1856 Register lreg = left->as_register();
1857 Register dreg = result->as_register();
1858
1859 // power-of-2 constant check and codegen
1860 if (right->is_constant()) {
1861 int c = right->as_constant_ptr()->as_jint();
1862 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1863 if (is_irem) {
1864 if (c == 1) {
1865 // move 0 to dreg if divisor is 1
1866 __ movw(dreg, zr);
1867 } else {
1868 // use rscratch1 as intermediate result register
1869 __ negsw(rscratch1, lreg);
1870 __ andw(dreg, lreg, c - 1);
1871 __ andw(rscratch1, rscratch1, c - 1);
1872 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1873 }
1874 } else {
1875 if (c == 1) {
1876 // move lreg to dreg if divisor is 1
1877 __ movw(dreg, lreg);
1878 } else {
1879 unsigned int shift = exact_log2(c);
1880 // use rscratch1 as intermediate result register
1881 __ asrw(rscratch1, lreg, 31);
1882 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1883 __ asrw(dreg, rscratch1, shift);
1884 }
1885 }
1886 } else {
1887 Register rreg = right->as_register();
1888 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1889 }
1890 }
1891
1892
1893 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1894 if (opr1->is_constant() && opr2->is_single_cpu()) {
1895 // tableswitch
1896 Register reg = as_reg(opr2);
1897 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1898 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1899 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1900 Register reg1 = as_reg(opr1);
1901 if (opr2->is_single_cpu()) {
1902 // cpu register - cpu register
1903 Register reg2 = opr2->as_register();
1904 if (is_reference_type(opr1->type())) {
1905 __ cmpoop(reg1, reg2);
1906 } else {
1907 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1908 __ cmpw(reg1, reg2);
1909 }
1910 return;
1911 }
1912 if (opr2->is_double_cpu()) {
1913 // cpu register - cpu register
1914 Register reg2 = opr2->as_register_lo();
1915 __ cmp(reg1, reg2);
1916 return;
1917 }
1918
1919 if (opr2->is_constant()) {
1920 bool is_32bit = false; // width of register operand
1921 jlong imm;
1922
1923 switch(opr2->type()) {
1924 case T_INT:
1925 imm = opr2->as_constant_ptr()->as_jint();
1926 is_32bit = true;
1927 break;
1928 case T_LONG:
1929 imm = opr2->as_constant_ptr()->as_jlong();
1930 break;
1931 case T_ADDRESS:
1932 imm = opr2->as_constant_ptr()->as_jint();
1933 break;
1934 case T_METADATA:
1935 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1936 break;
1937 case T_OBJECT:
1938 case T_ARRAY:
1939 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1940 __ cmpoop(reg1, rscratch1);
1941 return;
1942 default:
1943 ShouldNotReachHere();
1944 imm = 0; // unreachable
1945 break;
1946 }
1947
1948 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1949 if (is_32bit)
1950 __ cmpw(reg1, imm);
1951 else
1952 __ subs(zr, reg1, imm);
1953 return;
1954 } else {
1955 __ mov(rscratch1, imm);
1956 if (is_32bit)
1957 __ cmpw(reg1, rscratch1);
1958 else
1959 __ cmp(reg1, rscratch1);
1960 return;
1961 }
1962 } else
1963 ShouldNotReachHere();
1964 } else if (opr1->is_single_fpu()) {
1965 FloatRegister reg1 = opr1->as_float_reg();
1966 assert(opr2->is_single_fpu(), "expect single float register");
1967 FloatRegister reg2 = opr2->as_float_reg();
1968 __ fcmps(reg1, reg2);
1969 } else if (opr1->is_double_fpu()) {
1970 FloatRegister reg1 = opr1->as_double_reg();
1971 assert(opr2->is_double_fpu(), "expect double float register");
1972 FloatRegister reg2 = opr2->as_double_reg();
1973 __ fcmpd(reg1, reg2);
1974 } else {
1975 ShouldNotReachHere();
1976 }
1977 }
1978
1979 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1980 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1981 bool is_unordered_less = (code == lir_ucmp_fd2i);
1982 if (left->is_single_fpu()) {
1983 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1984 } else if (left->is_double_fpu()) {
1985 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1986 } else {
1987 ShouldNotReachHere();
1988 }
1989 } else if (code == lir_cmp_l2i) {
1990 Label done;
1991 __ cmp(left->as_register_lo(), right->as_register_lo());
1992 __ mov(dst->as_register(), (uint64_t)-1L);
1993 __ br(Assembler::LT, done);
1994 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
1995 __ bind(done);
1996 } else {
1997 ShouldNotReachHere();
1998 }
1999 }
2000
2001
2002 void LIR_Assembler::align_call(LIR_Code code) { }
2003
2004
2005 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2006 address call = __ trampoline_call(Address(op->addr(), rtype));
2007 if (call == nullptr) {
2008 bailout("trampoline stub overflow");
2009 return;
2010 }
2011 add_call_info(code_offset(), op->info());
2012 __ post_call_nop();
2013 }
2014
2015
2016 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2017 address call = __ ic_call(op->addr());
2018 if (call == nullptr) {
2019 bailout("trampoline stub overflow");
2020 return;
2021 }
2022 add_call_info(code_offset(), op->info());
2023 __ post_call_nop();
2024 }
2025
2026 void LIR_Assembler::emit_static_call_stub() {
2027 address call_pc = __ pc();
2028 address stub = __ start_a_stub(call_stub_size());
2029 if (stub == nullptr) {
2030 bailout("static call stub overflow");
2031 return;
2032 }
2033
2034 int start = __ offset();
2035
2036 __ relocate(static_stub_Relocation::spec(call_pc));
2037 __ emit_static_call_stub();
2038
2039 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2040 <= call_stub_size(), "stub too big");
2041 __ end_a_stub();
2042 }
2043
2044
2045 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2046 assert(exceptionOop->as_register() == r0, "must match");
2047 assert(exceptionPC->as_register() == r3, "must match");
2048
2049 // exception object is not added to oop map by LinearScan
2050 // (LinearScan assumes that no oops are in fixed registers)
2051 info->add_register_oop(exceptionOop);
2052 C1StubId unwind_id;
2053
2054 // get current pc information
2055 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2056 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2057 // As no instructions have been generated yet for this LIR node it's
2058 // possible that an oop map already exists for the current offset.
2059 // In that case insert an dummy NOP here to ensure all oop map PCs
2060 // are unique. See JDK-8237483.
2061 __ nop();
2062 }
2063 int pc_for_athrow_offset = __ offset();
2064 InternalAddress pc_for_athrow(__ pc());
2065 __ adr(exceptionPC->as_register(), pc_for_athrow);
2066 add_call_info(pc_for_athrow_offset, info); // for exception handler
2067
2068 __ verify_not_null_oop(r0);
2069 // search an exception handler (r0: exception oop, r3: throwing pc)
2070 if (compilation()->has_fpu_code()) {
2071 unwind_id = C1StubId::handle_exception_id;
2072 } else {
2073 unwind_id = C1StubId::handle_exception_nofpu_id;
2074 }
2075 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2076
2077 // FIXME: enough room for two byte trap ????
2078 __ nop();
2079 }
2080
2081
2082 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2083 assert(exceptionOop->as_register() == r0, "must match");
2084
2085 __ b(_unwind_handler_entry);
2086 }
2087
2088
2089 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2090 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2091 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2092
2093 switch (left->type()) {
2094 case T_INT: {
2095 switch (code) {
2096 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2097 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2098 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2099 default:
2100 ShouldNotReachHere();
2101 break;
2102 }
2103 break;
2104 case T_LONG:
2105 case T_ADDRESS:
2106 case T_OBJECT:
2107 switch (code) {
2108 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2109 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2110 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2111 default:
2112 ShouldNotReachHere();
2113 break;
2114 }
2115 break;
2116 default:
2117 ShouldNotReachHere();
2118 break;
2119 }
2120 }
2121 }
2122
2123
2124 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2125 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2126 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2127
2128 switch (left->type()) {
2129 case T_INT: {
2130 switch (code) {
2131 case lir_shl: __ lslw (dreg, lreg, count); break;
2132 case lir_shr: __ asrw (dreg, lreg, count); break;
2133 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2134 default:
2135 ShouldNotReachHere();
2136 break;
2137 }
2138 break;
2139 case T_LONG:
2140 case T_ADDRESS:
2141 case T_OBJECT:
2142 switch (code) {
2143 case lir_shl: __ lsl (dreg, lreg, count); break;
2144 case lir_shr: __ asr (dreg, lreg, count); break;
2145 case lir_ushr: __ lsr (dreg, lreg, count); break;
2146 default:
2147 ShouldNotReachHere();
2148 break;
2149 }
2150 break;
2151 default:
2152 ShouldNotReachHere();
2153 break;
2154 }
2155 }
2156 }
2157
2158
2159 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2160 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2161 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2162 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2163 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2164 }
2165
2166
2167 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2168 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2169 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2170 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2171 __ mov (rscratch1, c);
2172 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2173 }
2174
2175
2176 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2177 ShouldNotReachHere();
2178 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2179 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2180 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2181 __ lea(rscratch1, __ constant_oop_address(o));
2182 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2183 }
2184
2185
2186 // This code replaces a call to arraycopy; no exception may
2187 // be thrown in this code, they must be thrown in the System.arraycopy
2188 // activation frame; we could save some checks if this would not be the case
2189 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2190 ciArrayKlass* default_type = op->expected_type();
2191 Register src = op->src()->as_register();
2192 Register dst = op->dst()->as_register();
2193 Register src_pos = op->src_pos()->as_register();
2194 Register dst_pos = op->dst_pos()->as_register();
2195 Register length = op->length()->as_register();
2196 Register tmp = op->tmp()->as_register();
2197
2198 CodeStub* stub = op->stub();
2199 int flags = op->flags();
2200 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2201 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2202
2203 // if we don't know anything, just go through the generic arraycopy
2204 if (default_type == nullptr // || basic_type == T_OBJECT
2205 ) {
2206 Label done;
2207 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2208
2209 // Save the arguments in case the generic arraycopy fails and we
2210 // have to fall back to the JNI stub
2211 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2212 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2213 __ str(src, Address(sp, 4*BytesPerWord));
2214
2215 address copyfunc_addr = StubRoutines::generic_arraycopy();
2216 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2217
2218 // The arguments are in java calling convention so we shift them
2219 // to C convention
2220 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2221 __ mov(c_rarg0, j_rarg0);
2222 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2223 __ mov(c_rarg1, j_rarg1);
2224 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2225 __ mov(c_rarg2, j_rarg2);
2226 assert_different_registers(c_rarg3, j_rarg4);
2227 __ mov(c_rarg3, j_rarg3);
2228 __ mov(c_rarg4, j_rarg4);
2229 #ifndef PRODUCT
2230 if (PrintC1Statistics) {
2231 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2232 }
2233 #endif
2234 __ far_call(RuntimeAddress(copyfunc_addr));
2235
2236 __ cbz(r0, *stub->continuation());
2237
2238 // Reload values from the stack so they are where the stub
2239 // expects them.
2240 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2241 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2242 __ ldr(src, Address(sp, 4*BytesPerWord));
2243
2244 // r0 is -1^K where K == partial copied count
2245 __ eonw(rscratch1, r0, zr);
2246 // adjust length down and src/end pos up by partial copied count
2247 __ subw(length, length, rscratch1);
2248 __ addw(src_pos, src_pos, rscratch1);
2249 __ addw(dst_pos, dst_pos, rscratch1);
2250 __ b(*stub->entry());
2251
2252 __ bind(*stub->continuation());
2253 return;
2254 }
2255
2256 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2257
2258 int elem_size = type2aelembytes(basic_type);
2259 int scale = exact_log2(elem_size);
2260
2261 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2262 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2263 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2264 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2265
2266 // test for null
2267 if (flags & LIR_OpArrayCopy::src_null_check) {
2268 __ cbz(src, *stub->entry());
2269 }
2270 if (flags & LIR_OpArrayCopy::dst_null_check) {
2271 __ cbz(dst, *stub->entry());
2272 }
2273
2274 // If the compiler was not able to prove that exact type of the source or the destination
2275 // of the arraycopy is an array type, check at runtime if the source or the destination is
2276 // an instance type.
2277 if (flags & LIR_OpArrayCopy::type_check) {
2278 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2279 __ load_klass(tmp, dst);
2280 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2281 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2282 __ br(Assembler::GE, *stub->entry());
2283 }
2284
2285 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2286 __ load_klass(tmp, src);
2287 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2288 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2289 __ br(Assembler::GE, *stub->entry());
2290 }
2291 }
2292
2293 // check if negative
2294 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2295 __ cmpw(src_pos, 0);
2296 __ br(Assembler::LT, *stub->entry());
2297 }
2298 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2299 __ cmpw(dst_pos, 0);
2300 __ br(Assembler::LT, *stub->entry());
2301 }
2302
2303 if (flags & LIR_OpArrayCopy::length_positive_check) {
2304 __ cmpw(length, 0);
2305 __ br(Assembler::LT, *stub->entry());
2306 }
2307
2308 if (flags & LIR_OpArrayCopy::src_range_check) {
2309 __ addw(tmp, src_pos, length);
2310 __ ldrw(rscratch1, src_length_addr);
2311 __ cmpw(tmp, rscratch1);
2312 __ br(Assembler::HI, *stub->entry());
2313 }
2314 if (flags & LIR_OpArrayCopy::dst_range_check) {
2315 __ addw(tmp, dst_pos, length);
2316 __ ldrw(rscratch1, dst_length_addr);
2317 __ cmpw(tmp, rscratch1);
2318 __ br(Assembler::HI, *stub->entry());
2319 }
2320
2321 if (flags & LIR_OpArrayCopy::type_check) {
2322 // We don't know the array types are compatible
2323 if (basic_type != T_OBJECT) {
2324 // Simple test for basic type arrays
2325 if (UseCompressedClassPointers) {
2326 __ ldrw(tmp, src_klass_addr);
2327 __ ldrw(rscratch1, dst_klass_addr);
2328 __ cmpw(tmp, rscratch1);
2329 } else {
2330 __ ldr(tmp, src_klass_addr);
2331 __ ldr(rscratch1, dst_klass_addr);
2332 __ cmp(tmp, rscratch1);
2333 }
2334 __ br(Assembler::NE, *stub->entry());
2335 } else {
2336 // For object arrays, if src is a sub class of dst then we can
2337 // safely do the copy.
2338 Label cont, slow;
2339
2340 #define PUSH(r1, r2) \
2341 stp(r1, r2, __ pre(sp, -2 * wordSize));
2342
2343 #define POP(r1, r2) \
2344 ldp(r1, r2, __ post(sp, 2 * wordSize));
2345
2346 __ PUSH(src, dst);
2347
2348 __ load_klass(src, src);
2349 __ load_klass(dst, dst);
2350
2351 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2352
2353 __ PUSH(src, dst);
2354 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
2355 __ POP(src, dst);
2356
2357 __ cbnz(src, cont);
2358
2359 __ bind(slow);
2360 __ POP(src, dst);
2361
2362 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2363 if (copyfunc_addr != nullptr) { // use stub if available
2364 // src is not a sub class of dst so we have to do a
2365 // per-element check.
2366
2367 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2368 if ((flags & mask) != mask) {
2369 // Check that at least both of them object arrays.
2370 assert(flags & mask, "one of the two should be known to be an object array");
2371
2372 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2373 __ load_klass(tmp, src);
2374 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2375 __ load_klass(tmp, dst);
2376 }
2377 int lh_offset = in_bytes(Klass::layout_helper_offset());
2378 Address klass_lh_addr(tmp, lh_offset);
2379 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2380 __ ldrw(rscratch1, klass_lh_addr);
2381 __ mov(rscratch2, objArray_lh);
2382 __ eorw(rscratch1, rscratch1, rscratch2);
2383 __ cbnzw(rscratch1, *stub->entry());
2384 }
2385
2386 // Spill because stubs can use any register they like and it's
2387 // easier to restore just those that we care about.
2388 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2389 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2390 __ str(src, Address(sp, 4*BytesPerWord));
2391
2392 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2393 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2394 assert_different_registers(c_rarg0, dst, dst_pos, length);
2395 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2396 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2397 assert_different_registers(c_rarg1, dst, length);
2398 __ uxtw(c_rarg2, length);
2399 assert_different_registers(c_rarg2, dst);
2400
2401 __ load_klass(c_rarg4, dst);
2402 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2403 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2404 __ far_call(RuntimeAddress(copyfunc_addr));
2405
2406 #ifndef PRODUCT
2407 if (PrintC1Statistics) {
2408 Label failed;
2409 __ cbnz(r0, failed);
2410 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2411 __ bind(failed);
2412 }
2413 #endif
2414
2415 __ cbz(r0, *stub->continuation());
2416
2417 #ifndef PRODUCT
2418 if (PrintC1Statistics) {
2419 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2420 }
2421 #endif
2422 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2423
2424 // Restore previously spilled arguments
2425 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2426 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2427 __ ldr(src, Address(sp, 4*BytesPerWord));
2428
2429 // return value is -1^K where K is partial copied count
2430 __ eonw(rscratch1, r0, zr);
2431 // adjust length down and src/end pos up by partial copied count
2432 __ subw(length, length, rscratch1);
2433 __ addw(src_pos, src_pos, rscratch1);
2434 __ addw(dst_pos, dst_pos, rscratch1);
2435 }
2436
2437 __ b(*stub->entry());
2438
2439 __ bind(cont);
2440 __ POP(src, dst);
2441 }
2442 }
2443
2444 #ifdef ASSERT
2445 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2446 // Sanity check the known type with the incoming class. For the
2447 // primitive case the types must match exactly with src.klass and
2448 // dst.klass each exactly matching the default type. For the
2449 // object array case, if no type check is needed then either the
2450 // dst type is exactly the expected type and the src type is a
2451 // subtype which we can't check or src is the same array as dst
2452 // but not necessarily exactly of type default_type.
2453 Label known_ok, halt;
2454 __ mov_metadata(tmp, default_type->constant_encoding());
2455 if (UseCompressedClassPointers) {
2456 __ encode_klass_not_null(tmp);
2457 }
2458
2459 if (basic_type != T_OBJECT) {
2460
2461 if (UseCompressedClassPointers) {
2462 __ ldrw(rscratch1, dst_klass_addr);
2463 __ cmpw(tmp, rscratch1);
2464 } else {
2465 __ ldr(rscratch1, dst_klass_addr);
2466 __ cmp(tmp, rscratch1);
2467 }
2468 __ br(Assembler::NE, halt);
2469 if (UseCompressedClassPointers) {
2470 __ ldrw(rscratch1, src_klass_addr);
2471 __ cmpw(tmp, rscratch1);
2472 } else {
2473 __ ldr(rscratch1, src_klass_addr);
2474 __ cmp(tmp, rscratch1);
2475 }
2476 __ br(Assembler::EQ, known_ok);
2477 } else {
2478 if (UseCompressedClassPointers) {
2479 __ ldrw(rscratch1, dst_klass_addr);
2480 __ cmpw(tmp, rscratch1);
2481 } else {
2482 __ ldr(rscratch1, dst_klass_addr);
2483 __ cmp(tmp, rscratch1);
2484 }
2485 __ br(Assembler::EQ, known_ok);
2486 __ cmp(src, dst);
2487 __ br(Assembler::EQ, known_ok);
2488 }
2489 __ bind(halt);
2490 __ stop("incorrect type information in arraycopy");
2491 __ bind(known_ok);
2492 }
2493 #endif
2494
2495 #ifndef PRODUCT
2496 if (PrintC1Statistics) {
2497 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2498 }
2499 #endif
2500
2501 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2502 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2503 assert_different_registers(c_rarg0, dst, dst_pos, length);
2504 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2505 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2506 assert_different_registers(c_rarg1, dst, length);
2507 __ uxtw(c_rarg2, length);
2508 assert_different_registers(c_rarg2, dst);
2509
2510 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2511 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2512 const char *name;
2513 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2514
2515 CodeBlob *cb = CodeCache::find_blob(entry);
2516 if (cb) {
2517 __ far_call(RuntimeAddress(entry));
2518 } else {
2519 __ call_VM_leaf(entry, 3);
2520 }
2521
2522 if (stub != nullptr) {
2523 __ bind(*stub->continuation());
2524 }
2525 }
2526
2527
2528
2529
2530 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2531 Register obj = op->obj_opr()->as_register(); // may not be an oop
2532 Register hdr = op->hdr_opr()->as_register();
2533 Register lock = op->lock_opr()->as_register();
2534 Register temp = op->scratch_opr()->as_register();
2535 if (LockingMode == LM_MONITOR) {
2536 if (op->info() != nullptr) {
2537 add_debug_info_for_null_check_here(op->info());
2538 __ null_check(obj, -1);
2539 }
2540 __ b(*op->stub()->entry());
2541 } else if (op->code() == lir_lock) {
2542 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2543 // add debug info for NullPointerException only if one is possible
2544 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2545 if (op->info() != nullptr) {
2546 add_debug_info_for_null_check(null_check_offset, op->info());
2547 }
2548 // done
2549 } else if (op->code() == lir_unlock) {
2550 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2551 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2552 } else {
2553 Unimplemented();
2554 }
2555 __ bind(*op->stub()->continuation());
2556 }
2557
2558 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2559 Register obj = op->obj()->as_pointer_register();
2560 Register result = op->result_opr()->as_pointer_register();
2561
2562 CodeEmitInfo* info = op->info();
2563 if (info != nullptr) {
2564 add_debug_info_for_null_check_here(info);
2565 }
2566
2567 if (UseCompressedClassPointers) {
2568 __ ldrw(result, Address (obj, oopDesc::klass_offset_in_bytes()));
2569 __ decode_klass_not_null(result);
2570 } else {
2571 __ ldr(result, Address (obj, oopDesc::klass_offset_in_bytes()));
2572 }
2573 }
2574
2575 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2576 ciMethod* method = op->profiled_method();
2577 int bci = op->profiled_bci();
2578 ciMethod* callee = op->profiled_callee();
2579
2580 // Update counter for all call types
2581 ciMethodData* md = method->method_data_or_null();
2582 assert(md != nullptr, "Sanity");
2583 ciProfileData* data = md->bci_to_data(bci);
2584 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2585 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2586 Register mdo = op->mdo()->as_register();
2587 __ mov_metadata(mdo, md->constant_encoding());
2588 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2589 // Perform additional virtual call profiling for invokevirtual and
2590 // invokeinterface bytecodes
2591 if (op->should_profile_receiver_type()) {
2592 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2593 Register recv = op->recv()->as_register();
2594 assert_different_registers(mdo, recv);
2595 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2596 ciKlass* known_klass = op->known_holder();
2597 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2598 // We know the type that will be seen at this call site; we can
2599 // statically update the MethodData* rather than needing to do
2600 // dynamic tests on the receiver type
2601
2602 // NOTE: we should probably put a lock around this search to
2603 // avoid collisions by concurrent compilations
2604 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2605 uint i;
2606 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2607 ciKlass* receiver = vc_data->receiver(i);
2608 if (known_klass->equals(receiver)) {
2609 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2610 __ addptr(data_addr, DataLayout::counter_increment);
2611 return;
2612 }
2613 }
2614
2615 // Receiver type not found in profile data; select an empty slot
2616
2617 // Note that this is less efficient than it should be because it
2618 // always does a write to the receiver part of the
2619 // VirtualCallData rather than just the first time
2620 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2621 ciKlass* receiver = vc_data->receiver(i);
2622 if (receiver == nullptr) {
2623 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2624 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2625 __ lea(rscratch2, recv_addr);
2626 __ str(rscratch1, Address(rscratch2));
2627 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2628 __ addptr(data_addr, DataLayout::counter_increment);
2629 return;
2630 }
2631 }
2632 } else {
2633 __ load_klass(recv, recv);
2634 Label update_done;
2635 type_profile_helper(mdo, md, data, recv, &update_done);
2636 // Receiver did not match any saved receiver and there is no empty row for it.
2637 // Increment total counter to indicate polymorphic case.
2638 __ addptr(counter_addr, DataLayout::counter_increment);
2639
2640 __ bind(update_done);
2641 }
2642 } else {
2643 // Static call
2644 __ addptr(counter_addr, DataLayout::counter_increment);
2645 }
2646 }
2647
2648
2649 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2650 Unimplemented();
2651 }
2652
2653
2654 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2655 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2656 }
2657
2658 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2659 assert(op->crc()->is_single_cpu(), "crc must be register");
2660 assert(op->val()->is_single_cpu(), "byte value must be register");
2661 assert(op->result_opr()->is_single_cpu(), "result must be register");
2662 Register crc = op->crc()->as_register();
2663 Register val = op->val()->as_register();
2664 Register res = op->result_opr()->as_register();
2665
2666 assert_different_registers(val, crc, res);
2667 uint64_t offset;
2668 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2669 __ add(res, res, offset);
2670
2671 __ mvnw(crc, crc); // ~crc
2672 __ update_byte_crc32(crc, val, res);
2673 __ mvnw(res, crc); // ~crc
2674 }
2675
2676 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2677 COMMENT("emit_profile_type {");
2678 Register obj = op->obj()->as_register();
2679 Register tmp = op->tmp()->as_pointer_register();
2680 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2681 ciKlass* exact_klass = op->exact_klass();
2682 intptr_t current_klass = op->current_klass();
2683 bool not_null = op->not_null();
2684 bool no_conflict = op->no_conflict();
2685
2686 Label update, next, none;
2687
2688 bool do_null = !not_null;
2689 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2690 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2691
2692 assert(do_null || do_update, "why are we here?");
2693 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2694 assert(mdo_addr.base() != rscratch1, "wrong register");
2695
2696 __ verify_oop(obj);
2697
2698 if (tmp != obj) {
2699 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2700 __ mov(tmp, obj);
2701 } else {
2702 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2703 }
2704 if (do_null) {
2705 __ cbnz(tmp, update);
2706 if (!TypeEntries::was_null_seen(current_klass)) {
2707 __ ldr(rscratch2, mdo_addr);
2708 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2709 __ str(rscratch2, mdo_addr);
2710 }
2711 if (do_update) {
2712 #ifndef ASSERT
2713 __ b(next);
2714 }
2715 #else
2716 __ b(next);
2717 }
2718 } else {
2719 __ cbnz(tmp, update);
2720 __ stop("unexpected null obj");
2721 #endif
2722 }
2723
2724 __ bind(update);
2725
2726 if (do_update) {
2727 #ifdef ASSERT
2728 if (exact_klass != nullptr) {
2729 Label ok;
2730 __ load_klass(tmp, tmp);
2731 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2732 __ eor(rscratch1, tmp, rscratch1);
2733 __ cbz(rscratch1, ok);
2734 __ stop("exact klass and actual klass differ");
2735 __ bind(ok);
2736 }
2737 #endif
2738 if (!no_conflict) {
2739 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2740 if (exact_klass != nullptr) {
2741 __ mov_metadata(tmp, exact_klass->constant_encoding());
2742 } else {
2743 __ load_klass(tmp, tmp);
2744 }
2745
2746 __ ldr(rscratch2, mdo_addr);
2747 __ eor(tmp, tmp, rscratch2);
2748 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2749 // klass seen before, nothing to do. The unknown bit may have been
2750 // set already but no need to check.
2751 __ cbz(rscratch1, next);
2752
2753 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2754
2755 if (TypeEntries::is_type_none(current_klass)) {
2756 __ cbz(rscratch2, none);
2757 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2758 __ br(Assembler::EQ, none);
2759 // There is a chance that the checks above
2760 // fail if another thread has just set the
2761 // profiling to this obj's klass
2762 __ dmb(Assembler::ISHLD);
2763 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2764 __ ldr(rscratch2, mdo_addr);
2765 __ eor(tmp, tmp, rscratch2);
2766 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2767 __ cbz(rscratch1, next);
2768 }
2769 } else {
2770 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2771 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2772
2773 __ ldr(tmp, mdo_addr);
2774 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2775 }
2776
2777 // different than before. Cannot keep accurate profile.
2778 __ ldr(rscratch2, mdo_addr);
2779 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2780 __ str(rscratch2, mdo_addr);
2781
2782 if (TypeEntries::is_type_none(current_klass)) {
2783 __ b(next);
2784
2785 __ bind(none);
2786 // first time here. Set profile type.
2787 __ str(tmp, mdo_addr);
2788 #ifdef ASSERT
2789 __ andr(tmp, tmp, TypeEntries::type_mask);
2790 __ verify_klass_ptr(tmp);
2791 #endif
2792 }
2793 } else {
2794 // There's a single possible klass at this profile point
2795 assert(exact_klass != nullptr, "should be");
2796 if (TypeEntries::is_type_none(current_klass)) {
2797 __ mov_metadata(tmp, exact_klass->constant_encoding());
2798 __ ldr(rscratch2, mdo_addr);
2799 __ eor(tmp, tmp, rscratch2);
2800 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2801 __ cbz(rscratch1, next);
2802 #ifdef ASSERT
2803 {
2804 Label ok;
2805 __ ldr(rscratch1, mdo_addr);
2806 __ cbz(rscratch1, ok);
2807 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2808 __ br(Assembler::EQ, ok);
2809 // may have been set by another thread
2810 __ dmb(Assembler::ISHLD);
2811 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2812 __ ldr(rscratch2, mdo_addr);
2813 __ eor(rscratch2, rscratch1, rscratch2);
2814 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2815 __ cbz(rscratch2, ok);
2816
2817 __ stop("unexpected profiling mismatch");
2818 __ bind(ok);
2819 }
2820 #endif
2821 // first time here. Set profile type.
2822 __ str(tmp, mdo_addr);
2823 #ifdef ASSERT
2824 __ andr(tmp, tmp, TypeEntries::type_mask);
2825 __ verify_klass_ptr(tmp);
2826 #endif
2827 } else {
2828 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2829 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2830
2831 __ ldr(tmp, mdo_addr);
2832 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2833
2834 __ orr(tmp, tmp, TypeEntries::type_unknown);
2835 __ str(tmp, mdo_addr);
2836 // FIXME: Write barrier needed here?
2837 }
2838 }
2839
2840 __ bind(next);
2841 }
2842 COMMENT("} emit_profile_type");
2843 }
2844
2845
2846 void LIR_Assembler::align_backward_branch_target() {
2847 }
2848
2849
2850 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2851 // tmp must be unused
2852 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2853
2854 if (left->is_single_cpu()) {
2855 assert(dest->is_single_cpu(), "expect single result reg");
2856 __ negw(dest->as_register(), left->as_register());
2857 } else if (left->is_double_cpu()) {
2858 assert(dest->is_double_cpu(), "expect double result reg");
2859 __ neg(dest->as_register_lo(), left->as_register_lo());
2860 } else if (left->is_single_fpu()) {
2861 assert(dest->is_single_fpu(), "expect single float result reg");
2862 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2863 } else {
2864 assert(left->is_double_fpu(), "expect double float operand reg");
2865 assert(dest->is_double_fpu(), "expect double float result reg");
2866 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2867 }
2868 }
2869
2870
2871 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2872 if (patch_code != lir_patch_none) {
2873 deoptimize_trap(info);
2874 return;
2875 }
2876
2877 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2878 }
2879
2880
2881 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2882 assert(!tmp->is_valid(), "don't need temporary");
2883
2884 CodeBlob *cb = CodeCache::find_blob(dest);
2885 if (cb) {
2886 __ far_call(RuntimeAddress(dest));
2887 } else {
2888 __ mov(rscratch1, RuntimeAddress(dest));
2889 __ blr(rscratch1);
2890 }
2891
2892 if (info != nullptr) {
2893 add_call_info_here(info);
2894 }
2895 __ post_call_nop();
2896 }
2897
2898 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2899 if (dest->is_address() || src->is_address()) {
2900 move_op(src, dest, type, lir_patch_none, info,
2901 /*pop_fpu_stack*/false, /*wide*/false);
2902 } else {
2903 ShouldNotReachHere();
2904 }
2905 }
2906
2907 #ifdef ASSERT
2908 // emit run-time assertion
2909 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2910 assert(op->code() == lir_assert, "must be");
2911
2912 if (op->in_opr1()->is_valid()) {
2913 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2914 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2915 } else {
2916 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2917 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2918 }
2919
2920 Label ok;
2921 if (op->condition() != lir_cond_always) {
2922 Assembler::Condition acond = Assembler::AL;
2923 switch (op->condition()) {
2924 case lir_cond_equal: acond = Assembler::EQ; break;
2925 case lir_cond_notEqual: acond = Assembler::NE; break;
2926 case lir_cond_less: acond = Assembler::LT; break;
2927 case lir_cond_lessEqual: acond = Assembler::LE; break;
2928 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2929 case lir_cond_greater: acond = Assembler::GT; break;
2930 case lir_cond_belowEqual: acond = Assembler::LS; break;
2931 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2932 default: ShouldNotReachHere();
2933 }
2934 __ br(acond, ok);
2935 }
2936 if (op->halt()) {
2937 const char* str = __ code_string(op->msg());
2938 __ stop(str);
2939 } else {
2940 breakpoint();
2941 }
2942 __ bind(ok);
2943 }
2944 #endif
2945
2946 #ifndef PRODUCT
2947 #define COMMENT(x) do { __ block_comment(x); } while (0)
2948 #else
2949 #define COMMENT(x)
2950 #endif
2951
2952 void LIR_Assembler::membar() {
2953 COMMENT("membar");
2954 __ membar(MacroAssembler::AnyAny);
2955 }
2956
2957 void LIR_Assembler::membar_acquire() {
2958 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2959 }
2960
2961 void LIR_Assembler::membar_release() {
2962 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2963 }
2964
2965 void LIR_Assembler::membar_loadload() {
2966 __ membar(Assembler::LoadLoad);
2967 }
2968
2969 void LIR_Assembler::membar_storestore() {
2970 __ membar(MacroAssembler::StoreStore);
2971 }
2972
2973 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2974
2975 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2976
2977 void LIR_Assembler::on_spin_wait() {
2978 __ spin_wait();
2979 }
2980
2981 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2982 __ mov(result_reg->as_register(), rthread);
2983 }
2984
2985
2986 void LIR_Assembler::peephole(LIR_List *lir) {
2987 #if 0
2988 if (tableswitch_count >= max_tableswitches)
2989 return;
2990
2991 /*
2992 This finite-state automaton recognizes sequences of compare-and-
2993 branch instructions. We will turn them into a tableswitch. You
2994 could argue that C1 really shouldn't be doing this sort of
2995 optimization, but without it the code is really horrible.
2996 */
2997
2998 enum { start_s, cmp1_s, beq_s, cmp_s } state;
2999 int first_key, last_key = -2147483648;
3000 int next_key = 0;
3001 int start_insn = -1;
3002 int last_insn = -1;
3003 Register reg = noreg;
3004 LIR_Opr reg_opr;
3005 state = start_s;
3006
3007 LIR_OpList* inst = lir->instructions_list();
3008 for (int i = 0; i < inst->length(); i++) {
3009 LIR_Op* op = inst->at(i);
3010 switch (state) {
3011 case start_s:
3012 first_key = -1;
3013 start_insn = i;
3014 switch (op->code()) {
3015 case lir_cmp:
3016 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3017 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3018 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3019 && opr2->is_constant()
3020 && opr2->type() == T_INT) {
3021 reg_opr = opr1;
3022 reg = opr1->as_register();
3023 first_key = opr2->as_constant_ptr()->as_jint();
3024 next_key = first_key + 1;
3025 state = cmp_s;
3026 goto next_state;
3027 }
3028 break;
3029 }
3030 break;
3031 case cmp_s:
3032 switch (op->code()) {
3033 case lir_branch:
3034 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3035 state = beq_s;
3036 last_insn = i;
3037 goto next_state;
3038 }
3039 }
3040 state = start_s;
3041 break;
3042 case beq_s:
3043 switch (op->code()) {
3044 case lir_cmp: {
3045 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3046 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3047 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3048 && opr1->as_register() == reg
3049 && opr2->is_constant()
3050 && opr2->type() == T_INT
3051 && opr2->as_constant_ptr()->as_jint() == next_key) {
3052 last_key = next_key;
3053 next_key++;
3054 state = cmp_s;
3055 goto next_state;
3056 }
3057 }
3058 }
3059 last_key = next_key;
3060 state = start_s;
3061 break;
3062 default:
3063 assert(false, "impossible state");
3064 }
3065 if (state == start_s) {
3066 if (first_key < last_key - 5L && reg != noreg) {
3067 {
3068 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3069 // reg->encoding(),
3070 // start_insn, first_key, last_key);
3071 // for (int i = 0; i < inst->length(); i++) {
3072 // inst->at(i)->print();
3073 // tty->print("\n");
3074 // }
3075 // tty->print("\n");
3076 }
3077
3078 struct tableswitch *sw = &switches[tableswitch_count];
3079 sw->_insn_index = start_insn, sw->_first_key = first_key,
3080 sw->_last_key = last_key, sw->_reg = reg;
3081 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3082 {
3083 // Insert the new table of branches
3084 int offset = last_insn;
3085 for (int n = first_key; n < last_key; n++) {
3086 inst->insert_before
3087 (last_insn + 1,
3088 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3089 inst->at(offset)->as_OpBranch()->label()));
3090 offset -= 2, i++;
3091 }
3092 }
3093 // Delete all the old compare-and-branch instructions
3094 for (int n = first_key; n < last_key; n++) {
3095 inst->remove_at(start_insn);
3096 inst->remove_at(start_insn);
3097 }
3098 // Insert the tableswitch instruction
3099 inst->insert_before(start_insn,
3100 new LIR_Op2(lir_cmp, lir_cond_always,
3101 LIR_OprFact::intConst(tableswitch_count),
3102 reg_opr));
3103 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3104 tableswitch_count++;
3105 }
3106 reg = noreg;
3107 last_key = -2147483648;
3108 }
3109 next_state:
3110 ;
3111 }
3112 #endif
3113 }
3114
3115 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3116 Address addr = as_Address(src->as_address_ptr());
3117 BasicType type = src->type();
3118 bool is_oop = is_reference_type(type);
3119
3120 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3121 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3122
3123 switch(type) {
3124 case T_INT:
3125 xchg = &MacroAssembler::atomic_xchgalw;
3126 add = &MacroAssembler::atomic_addalw;
3127 break;
3128 case T_LONG:
3129 xchg = &MacroAssembler::atomic_xchgal;
3130 add = &MacroAssembler::atomic_addal;
3131 break;
3132 case T_OBJECT:
3133 case T_ARRAY:
3134 if (UseCompressedOops) {
3135 xchg = &MacroAssembler::atomic_xchgalw;
3136 add = &MacroAssembler::atomic_addalw;
3137 } else {
3138 xchg = &MacroAssembler::atomic_xchgal;
3139 add = &MacroAssembler::atomic_addal;
3140 }
3141 break;
3142 default:
3143 ShouldNotReachHere();
3144 xchg = &MacroAssembler::atomic_xchgal;
3145 add = &MacroAssembler::atomic_addal; // unreachable
3146 }
3147
3148 switch (code) {
3149 case lir_xadd:
3150 {
3151 RegisterOrConstant inc;
3152 Register tmp = as_reg(tmp_op);
3153 Register dst = as_reg(dest);
3154 if (data->is_constant()) {
3155 inc = RegisterOrConstant(as_long(data));
3156 assert_different_registers(dst, addr.base(), tmp,
3157 rscratch1, rscratch2);
3158 } else {
3159 inc = RegisterOrConstant(as_reg(data));
3160 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3161 rscratch1, rscratch2);
3162 }
3163 __ lea(tmp, addr);
3164 (_masm->*add)(dst, inc, tmp);
3165 break;
3166 }
3167 case lir_xchg:
3168 {
3169 Register tmp = tmp_op->as_register();
3170 Register obj = as_reg(data);
3171 Register dst = as_reg(dest);
3172 if (is_oop && UseCompressedOops) {
3173 __ encode_heap_oop(rscratch2, obj);
3174 obj = rscratch2;
3175 }
3176 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3177 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3178 __ lea(tmp, addr);
3179 (_masm->*xchg)(dst, obj, tmp);
3180 if (is_oop && UseCompressedOops) {
3181 __ decode_heap_oop(dst);
3182 }
3183 }
3184 break;
3185 default:
3186 ShouldNotReachHere();
3187 }
3188 __ membar(__ AnyAny);
3189 }
3190
3191 #undef __