1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "asm/assembler.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "ci/ciUtilities.hpp"
37 #include "code/aotCodeCache.hpp"
38 #include "code/compiledIC.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/gc_globals.hpp"
41 #include "nativeInst_aarch64.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/sharedRuntime.hpp"
45 #include "runtime/stubRoutines.hpp"
46 #include "runtime/threadIdentifier.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_aarch64.inline.hpp"
49
50
51 #ifndef PRODUCT
52 #define COMMENT(x) do { __ block_comment(x); } while (0)
53 #else
54 #define COMMENT(x)
55 #endif
56
57 NEEDS_CLEANUP // remove this definitions ?
58 const Register SYNC_header = r0; // synchronization header
59 const Register SHIFT_count = r0; // where count for shift operations must be
60
61 #define __ _masm->
62
63
64 static void select_different_registers(Register preserve,
65 Register extra,
66 Register &tmp1,
67 Register &tmp2) {
68 if (tmp1 == preserve) {
69 assert_different_registers(tmp1, tmp2, extra);
70 tmp1 = extra;
71 } else if (tmp2 == preserve) {
72 assert_different_registers(tmp1, tmp2, extra);
73 tmp2 = extra;
74 }
75 assert_different_registers(preserve, tmp1, tmp2);
76 }
77
78
79
80 static void select_different_registers(Register preserve,
81 Register extra,
82 Register &tmp1,
83 Register &tmp2,
84 Register &tmp3) {
85 if (tmp1 == preserve) {
86 assert_different_registers(tmp1, tmp2, tmp3, extra);
87 tmp1 = extra;
88 } else if (tmp2 == preserve) {
89 assert_different_registers(tmp1, tmp2, tmp3, extra);
90 tmp2 = extra;
91 } else if (tmp3 == preserve) {
92 assert_different_registers(tmp1, tmp2, tmp3, extra);
93 tmp3 = extra;
94 }
95 assert_different_registers(preserve, tmp1, tmp2, tmp3);
96 }
97
98
99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
100
101
102 LIR_Opr LIR_Assembler::receiverOpr() {
103 return FrameMap::receiver_opr;
104 }
105
106 LIR_Opr LIR_Assembler::osrBufferPointer() {
107 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
108 }
109
110 //--------------fpu register translations-----------------------
111
112
113 address LIR_Assembler::float_constant(float f) {
114 address const_addr = __ float_constant(f);
115 if (const_addr == nullptr) {
116 bailout("const section overflow");
117 return __ code()->consts()->start();
118 } else {
119 return const_addr;
120 }
121 }
122
123
124 address LIR_Assembler::double_constant(double d) {
125 address const_addr = __ double_constant(d);
126 if (const_addr == nullptr) {
127 bailout("const section overflow");
128 return __ code()->consts()->start();
129 } else {
130 return const_addr;
131 }
132 }
133
134 address LIR_Assembler::int_constant(jlong n) {
135 address const_addr = __ long_constant(n);
136 if (const_addr == nullptr) {
137 bailout("const section overflow");
138 return __ code()->consts()->start();
139 } else {
140 return const_addr;
141 }
142 }
143
144 void LIR_Assembler::breakpoint() { Unimplemented(); }
145
146 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
147
148 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
149
150 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
151 //-------------------------------------------
152
153 static Register as_reg(LIR_Opr op) {
154 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
155 }
156
157 static jlong as_long(LIR_Opr data) {
158 jlong result;
159 switch (data->type()) {
160 case T_INT:
161 result = (data->as_jint());
162 break;
163 case T_LONG:
164 result = (data->as_jlong());
165 break;
166 default:
167 ShouldNotReachHere();
168 result = 0; // unreachable
169 }
170 return result;
171 }
172
173 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
174 Register base = addr->base()->as_pointer_register();
175 LIR_Opr opr = addr->index();
176 if (opr->is_cpu_register()) {
177 Register index;
178 if (opr->is_single_cpu())
179 index = opr->as_register();
180 else
181 index = opr->as_register_lo();
182 assert(addr->disp() == 0, "must be");
183 switch(opr->type()) {
184 case T_INT:
185 return Address(base, index, Address::sxtw(addr->scale()));
186 case T_LONG:
187 return Address(base, index, Address::lsl(addr->scale()));
188 default:
189 ShouldNotReachHere();
190 }
191 } else {
192 assert(addr->scale() == 0,
193 "expected for immediate operand, was: %d", addr->scale());
194 ptrdiff_t offset = ptrdiff_t(addr->disp());
195 // NOTE: Does not handle any 16 byte vector access.
196 const uint type_size = type2aelembytes(addr->type(), true);
197 return __ legitimize_address(Address(base, offset), type_size, tmp);
198 }
199 return Address();
200 }
201
202 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
203 ShouldNotReachHere();
204 return Address();
205 }
206
207 Address LIR_Assembler::as_Address(LIR_Address* addr) {
208 return as_Address(addr, rscratch1);
209 }
210
211 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
212 return as_Address(addr, rscratch1); // Ouch
213 // FIXME: This needs to be much more clever. See x86.
214 }
215
216 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
217 // not encodable as a base + (immediate) offset, generate an explicit address
218 // calculation to hold the address in a temporary register.
219 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
220 precond(size == 4 || size == 8);
221 Address addr = frame_map()->address_for_slot(index, adjust);
222 precond(addr.getMode() == Address::base_plus_offset);
223 precond(addr.base() == sp);
224 precond(addr.offset() > 0);
225 uint mask = size - 1;
226 assert((addr.offset() & mask) == 0, "scaled offsets only");
227 return __ legitimize_address(addr, size, tmp);
228 }
229
230 void LIR_Assembler::osr_entry() {
231 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
232 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
233 ValueStack* entry_state = osr_entry->state();
234 int number_of_locks = entry_state->locks_size();
235
236 // we jump here if osr happens with the interpreter
237 // state set up to continue at the beginning of the
238 // loop that triggered osr - in particular, we have
239 // the following registers setup:
240 //
241 // r2: osr buffer
242 //
243
244 // build frame
245 ciMethod* m = compilation()->method();
246 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
247
248 // OSR buffer is
249 //
250 // locals[nlocals-1..0]
251 // monitors[0..number_of_locks]
252 //
253 // locals is a direct copy of the interpreter frame so in the osr buffer
254 // so first slot in the local array is the last local from the interpreter
255 // and last slot is local[0] (receiver) from the interpreter
256 //
257 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
258 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
259 // in the interpreter frame (the method lock if a sync method)
260
261 // Initialize monitors in the compiled activation.
262 // r2: pointer to osr buffer
263 //
264 // All other registers are dead at this point and the locals will be
265 // copied into place by code emitted in the IR.
266
267 Register OSR_buf = osrBufferPointer()->as_pointer_register();
268 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
269 int monitor_offset = BytesPerWord * method()->max_locals() +
270 (2 * BytesPerWord) * (number_of_locks - 1);
271 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
272 // the OSR buffer using 2 word entries: first the lock and then
273 // the oop.
274 for (int i = 0; i < number_of_locks; i++) {
275 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
276 #ifdef ASSERT
277 // verify the interpreter's monitor has a non-null object
278 {
279 Label L;
280 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
281 __ cbnz(rscratch1, L);
282 __ stop("locked object is null");
283 __ bind(L);
284 }
285 #endif
286 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
287 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
288 __ str(r19, frame_map()->address_for_monitor_lock(i));
289 __ str(r20, frame_map()->address_for_monitor_object(i));
290 }
291 }
292 }
293
294
295 // inline cache check; done before the frame is built.
296 int LIR_Assembler::check_icache() {
297 return __ ic_check(CodeEntryAlignment);
298 }
299
300 void LIR_Assembler::clinit_barrier(ciMethod* method) {
301 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
302 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
303
304 Label L_skip_barrier;
305
306 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
307 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
308 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
309 __ bind(L_skip_barrier);
310 }
311
312 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
313 if (o == nullptr) {
314 __ mov(reg, zr);
315 } else {
316 __ movoop(reg, o);
317 }
318 }
319
320 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
321 address target = nullptr;
322 relocInfo::relocType reloc_type = relocInfo::none;
323
324 switch (patching_id(info)) {
325 case PatchingStub::access_field_id:
326 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
327 reloc_type = relocInfo::section_word_type;
328 break;
329 case PatchingStub::load_klass_id:
330 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
331 reloc_type = relocInfo::metadata_type;
332 break;
333 case PatchingStub::load_mirror_id:
334 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
335 reloc_type = relocInfo::oop_type;
336 break;
337 case PatchingStub::load_appendix_id:
338 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
339 reloc_type = relocInfo::oop_type;
340 break;
341 default: ShouldNotReachHere();
342 }
343
344 __ far_call(RuntimeAddress(target));
345 add_call_info_here(info);
346 }
347
348 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
349 deoptimize_trap(info);
350 }
351
352
353 // This specifies the rsp decrement needed to build the frame
354 int LIR_Assembler::initial_frame_size_in_bytes() const {
355 // if rounding, must let FrameMap know!
356
357 return in_bytes(frame_map()->framesize_in_bytes());
358 }
359
360
361 int LIR_Assembler::emit_exception_handler() {
362 // generate code for exception handler
363 address handler_base = __ start_a_stub(exception_handler_size());
364 if (handler_base == nullptr) {
365 // not enough space left for the handler
366 bailout("exception handler overflow");
367 return -1;
368 }
369
370 int offset = code_offset();
371
372 // the exception oop and pc are in r0, and r3
373 // no other registers need to be preserved, so invalidate them
374 __ invalidate_registers(false, true, true, false, true, true);
375
376 // check that there is really an exception
377 __ verify_not_null_oop(r0);
378
379 // search an exception handler (r0: exception oop, r3: throwing pc)
380 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_handle_exception_from_callee_id)));
381 __ should_not_reach_here();
382 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
383 __ end_a_stub();
384
385 return offset;
386 }
387
388
389 // Emit the code to remove the frame from the stack in the exception
390 // unwind path.
391 int LIR_Assembler::emit_unwind_handler() {
392 #ifndef PRODUCT
393 if (CommentedAssembly) {
394 _masm->block_comment("Unwind handler");
395 }
396 #endif
397
398 int offset = code_offset();
399
400 // Fetch the exception from TLS and clear out exception related thread state
401 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
402 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
403 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
404
405 __ bind(_unwind_handler_entry);
406 __ verify_not_null_oop(r0);
407 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
408 __ mov(r19, r0); // Preserve the exception
409 }
410
411 // Perform needed unlocking
412 MonitorExitStub* stub = nullptr;
413 if (method()->is_synchronized()) {
414 monitor_address(0, FrameMap::r0_opr);
415 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
416 __ unlock_object(r5, r4, r0, r6, *stub->entry());
417 __ bind(*stub->continuation());
418 }
419
420 if (compilation()->env()->dtrace_method_probes()) {
421 __ mov(c_rarg0, rthread);
422 __ mov_metadata(c_rarg1, method()->constant_encoding());
423 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
424 }
425
426 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
427 __ mov(r0, r19); // Restore the exception
428 }
429
430 // remove the activation and dispatch to the unwind handler
431 __ block_comment("remove_frame and dispatch to the unwind handler");
432 __ remove_frame(initial_frame_size_in_bytes());
433 __ far_jump(RuntimeAddress(Runtime1::entry_for(StubId::c1_unwind_exception_id)));
434
435 // Emit the slow path assembly
436 if (stub != nullptr) {
437 stub->emit_code(this);
438 }
439
440 return offset;
441 }
442
443
444 int LIR_Assembler::emit_deopt_handler() {
445 // generate code for exception handler
446 address handler_base = __ start_a_stub(deopt_handler_size());
447 if (handler_base == nullptr) {
448 // not enough space left for the handler
449 bailout("deopt handler overflow");
450 return -1;
451 }
452
453 int offset = code_offset();
454
455 __ adr(lr, pc());
456 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
457 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
458 __ end_a_stub();
459
460 return offset;
461 }
462
463 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
464 _masm->code_section()->relocate(adr, relocInfo::poll_type);
465 int pc_offset = code_offset();
466 flush_debug_info(pc_offset);
467 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
468 if (info->exception_handlers() != nullptr) {
469 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
470 }
471 }
472
473 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
474 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
475
476 // Pop the stack before the safepoint code
477 __ remove_frame(initial_frame_size_in_bytes());
478
479 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
480 __ reserved_stack_check();
481 }
482
483 code_stub->set_safepoint_offset(__ offset());
484 __ relocate(relocInfo::poll_return_type);
485 __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
486 __ ret(lr);
487 }
488
489 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
490 guarantee(info != nullptr, "Shouldn't be null");
491 __ get_polling_page(rscratch1, relocInfo::poll_type);
492 add_debug_info_for_branch(info); // This isn't just debug info:
493 // it's the oop map
494 __ read_polling_page(rscratch1, relocInfo::poll_type);
495 return __ offset();
496 }
497
498
499 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
500 if (from_reg == r31_sp)
501 from_reg = sp;
502 if (to_reg == r31_sp)
503 to_reg = sp;
504 __ mov(to_reg, from_reg);
505 }
506
507 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
508
509
510 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
511 assert(src->is_constant(), "should not call otherwise");
512 assert(dest->is_register(), "should not call otherwise");
513 LIR_Const* c = src->as_constant_ptr();
514
515 switch (c->type()) {
516 case T_INT: {
517 assert(patch_code == lir_patch_none, "no patching handled here");
518 __ movw(dest->as_register(), c->as_jint());
519 break;
520 }
521
522 case T_ADDRESS: {
523 assert(patch_code == lir_patch_none, "no patching handled here");
524 __ mov(dest->as_register(), c->as_jint());
525 break;
526 }
527
528 case T_LONG: {
529 assert(patch_code == lir_patch_none, "no patching handled here");
530 if (AOTCodeCache::is_on_for_dump()) {
531 // AOT code needs relocation info for card table base
532 address b = c->as_pointer();
533 if (is_card_table_address(b)) {
534 __ lea(dest->as_register_lo(), ExternalAddress(b));
535 break;
536 }
537 if (b == (address)ThreadIdentifier::unsafe_offset()) {
538 __ lea(dest->as_register_lo(), ExternalAddress(b));
539 break;
540 }
541 #if INCLUDE_CDS
542 if (AOTRuntimeConstants::contains(b)) {
543 __ load_aotrc_address(dest->as_register_lo(), b);
544 break;
545 }
546 #endif
547 }
548 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
549 break;
550 }
551
552 case T_OBJECT: {
553 if (patch_code == lir_patch_none) {
554 jobject2reg(c->as_jobject(), dest->as_register());
555 } else {
556 jobject2reg_with_patching(dest->as_register(), info);
557 }
558 break;
559 }
560
561 case T_METADATA: {
562 if (patch_code != lir_patch_none) {
563 klass2reg_with_patching(dest->as_register(), info);
564 } else {
565 __ mov_metadata(dest->as_register(), c->as_metadata());
566 }
567 break;
568 }
569
570 case T_FLOAT: {
571 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
572 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
573 } else {
574 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
575 __ ldrs(dest->as_float_reg(), Address(rscratch1));
576 }
577 break;
578 }
579
580 case T_DOUBLE: {
581 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
582 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
583 } else {
584 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
585 __ ldrd(dest->as_double_reg(), Address(rscratch1));
586 }
587 break;
588 }
589
590 default:
591 ShouldNotReachHere();
592 }
593 }
594
595 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
596 LIR_Const* c = src->as_constant_ptr();
597 switch (c->type()) {
598 case T_OBJECT:
599 {
600 if (! c->as_jobject())
601 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
602 else {
603 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
604 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
605 }
606 }
607 break;
608 case T_ADDRESS:
609 {
610 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
611 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
612 }
613 case T_INT:
614 case T_FLOAT:
615 {
616 Register reg = zr;
617 if (c->as_jint_bits() == 0)
618 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
619 else {
620 __ movw(rscratch1, c->as_jint_bits());
621 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
622 }
623 }
624 break;
625 case T_LONG:
626 case T_DOUBLE:
627 {
628 Register reg = zr;
629 if (c->as_jlong_bits() == 0)
630 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
631 lo_word_offset_in_bytes));
632 else {
633 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
634 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
635 lo_word_offset_in_bytes));
636 }
637 }
638 break;
639 default:
640 ShouldNotReachHere();
641 }
642 }
643
644 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
645 assert(src->is_constant(), "should not call otherwise");
646 LIR_Const* c = src->as_constant_ptr();
647 LIR_Address* to_addr = dest->as_address_ptr();
648
649 void (Assembler::* insn)(Register Rt, const Address &adr);
650
651 switch (type) {
652 case T_ADDRESS:
653 assert(c->as_jint() == 0, "should be");
654 insn = &Assembler::str;
655 break;
656 case T_LONG:
657 assert(c->as_jlong() == 0, "should be");
658 insn = &Assembler::str;
659 break;
660 case T_INT:
661 assert(c->as_jint() == 0, "should be");
662 insn = &Assembler::strw;
663 break;
664 case T_OBJECT:
665 case T_ARRAY:
666 assert(c->as_jobject() == nullptr, "should be");
667 if (UseCompressedOops && !wide) {
668 insn = &Assembler::strw;
669 } else {
670 insn = &Assembler::str;
671 }
672 break;
673 case T_CHAR:
674 case T_SHORT:
675 assert(c->as_jint() == 0, "should be");
676 insn = &Assembler::strh;
677 break;
678 case T_BOOLEAN:
679 case T_BYTE:
680 assert(c->as_jint() == 0, "should be");
681 insn = &Assembler::strb;
682 break;
683 default:
684 ShouldNotReachHere();
685 insn = &Assembler::str; // unreachable
686 }
687
688 if (info) add_debug_info_for_null_check_here(info);
689 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
690 }
691
692 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
693 assert(src->is_register(), "should not call otherwise");
694 assert(dest->is_register(), "should not call otherwise");
695
696 // move between cpu-registers
697 if (dest->is_single_cpu()) {
698 if (src->type() == T_LONG) {
699 // Can do LONG -> OBJECT
700 move_regs(src->as_register_lo(), dest->as_register());
701 return;
702 }
703 assert(src->is_single_cpu(), "must match");
704 if (src->type() == T_OBJECT) {
705 __ verify_oop(src->as_register());
706 }
707 move_regs(src->as_register(), dest->as_register());
708
709 } else if (dest->is_double_cpu()) {
710 if (is_reference_type(src->type())) {
711 // Surprising to me but we can see move of a long to t_object
712 __ verify_oop(src->as_register());
713 move_regs(src->as_register(), dest->as_register_lo());
714 return;
715 }
716 assert(src->is_double_cpu(), "must match");
717 Register f_lo = src->as_register_lo();
718 Register f_hi = src->as_register_hi();
719 Register t_lo = dest->as_register_lo();
720 Register t_hi = dest->as_register_hi();
721 assert(f_hi == f_lo, "must be same");
722 assert(t_hi == t_lo, "must be same");
723 move_regs(f_lo, t_lo);
724
725 } else if (dest->is_single_fpu()) {
726 __ fmovs(dest->as_float_reg(), src->as_float_reg());
727
728 } else if (dest->is_double_fpu()) {
729 __ fmovd(dest->as_double_reg(), src->as_double_reg());
730
731 } else {
732 ShouldNotReachHere();
733 }
734 }
735
736 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
737 precond(src->is_register() && dest->is_stack());
738
739 uint const c_sz32 = sizeof(uint32_t);
740 uint const c_sz64 = sizeof(uint64_t);
741
742 if (src->is_single_cpu()) {
743 int index = dest->single_stack_ix();
744 if (is_reference_type(type)) {
745 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
746 __ verify_oop(src->as_register());
747 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
748 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
749 } else {
750 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
751 }
752
753 } else if (src->is_double_cpu()) {
754 int index = dest->double_stack_ix();
755 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
756 __ str(src->as_register_lo(), dest_addr_LO);
757
758 } else if (src->is_single_fpu()) {
759 int index = dest->single_stack_ix();
760 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
761
762 } else if (src->is_double_fpu()) {
763 int index = dest->double_stack_ix();
764 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
765
766 } else {
767 ShouldNotReachHere();
768 }
769 }
770
771
772 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
773 LIR_Address* to_addr = dest->as_address_ptr();
774 PatchingStub* patch = nullptr;
775 Register compressed_src = rscratch1;
776
777 if (patch_code != lir_patch_none) {
778 deoptimize_trap(info);
779 return;
780 }
781
782 if (is_reference_type(type)) {
783 __ verify_oop(src->as_register());
784
785 if (UseCompressedOops && !wide) {
786 __ encode_heap_oop(compressed_src, src->as_register());
787 } else {
788 compressed_src = src->as_register();
789 }
790 }
791
792 int null_check_here = code_offset();
793 switch (type) {
794 case T_FLOAT: {
795 __ strs(src->as_float_reg(), as_Address(to_addr));
796 break;
797 }
798
799 case T_DOUBLE: {
800 __ strd(src->as_double_reg(), as_Address(to_addr));
801 break;
802 }
803
804 case T_ARRAY: // fall through
805 case T_OBJECT: // fall through
806 if (UseCompressedOops && !wide) {
807 __ strw(compressed_src, as_Address(to_addr, rscratch2));
808 } else {
809 __ str(compressed_src, as_Address(to_addr));
810 }
811 break;
812 case T_METADATA:
813 // We get here to store a method pointer to the stack to pass to
814 // a dtrace runtime call. This can't work on 64 bit with
815 // compressed klass ptrs: T_METADATA can be a compressed klass
816 // ptr or a 64 bit method pointer.
817 ShouldNotReachHere();
818 __ str(src->as_register(), as_Address(to_addr));
819 break;
820 case T_ADDRESS:
821 __ str(src->as_register(), as_Address(to_addr));
822 break;
823 case T_INT:
824 __ strw(src->as_register(), as_Address(to_addr));
825 break;
826
827 case T_LONG: {
828 __ str(src->as_register_lo(), as_Address_lo(to_addr));
829 break;
830 }
831
832 case T_BYTE: // fall through
833 case T_BOOLEAN: {
834 __ strb(src->as_register(), as_Address(to_addr));
835 break;
836 }
837
838 case T_CHAR: // fall through
839 case T_SHORT:
840 __ strh(src->as_register(), as_Address(to_addr));
841 break;
842
843 default:
844 ShouldNotReachHere();
845 }
846 if (info != nullptr) {
847 add_debug_info_for_null_check(null_check_here, info);
848 }
849 }
850
851
852 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
853 precond(src->is_stack() && dest->is_register());
854
855 uint const c_sz32 = sizeof(uint32_t);
856 uint const c_sz64 = sizeof(uint64_t);
857
858 if (dest->is_single_cpu()) {
859 int index = src->single_stack_ix();
860 if (is_reference_type(type)) {
861 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
862 __ verify_oop(dest->as_register());
863 } else if (type == T_METADATA || type == T_ADDRESS) {
864 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
865 } else {
866 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
867 }
868
869 } else if (dest->is_double_cpu()) {
870 int index = src->double_stack_ix();
871 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
872 __ ldr(dest->as_register_lo(), src_addr_LO);
873
874 } else if (dest->is_single_fpu()) {
875 int index = src->single_stack_ix();
876 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
877
878 } else if (dest->is_double_fpu()) {
879 int index = src->double_stack_ix();
880 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
881
882 } else {
883 ShouldNotReachHere();
884 }
885 }
886
887
888 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
889 address target = nullptr;
890 relocInfo::relocType reloc_type = relocInfo::none;
891
892 switch (patching_id(info)) {
893 case PatchingStub::access_field_id:
894 target = Runtime1::entry_for(StubId::c1_access_field_patching_id);
895 reloc_type = relocInfo::section_word_type;
896 break;
897 case PatchingStub::load_klass_id:
898 target = Runtime1::entry_for(StubId::c1_load_klass_patching_id);
899 reloc_type = relocInfo::metadata_type;
900 break;
901 case PatchingStub::load_mirror_id:
902 target = Runtime1::entry_for(StubId::c1_load_mirror_patching_id);
903 reloc_type = relocInfo::oop_type;
904 break;
905 case PatchingStub::load_appendix_id:
906 target = Runtime1::entry_for(StubId::c1_load_appendix_patching_id);
907 reloc_type = relocInfo::oop_type;
908 break;
909 default: ShouldNotReachHere();
910 }
911
912 __ far_call(RuntimeAddress(target));
913 add_call_info_here(info);
914 }
915
916 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
917
918 LIR_Opr temp;
919 if (type == T_LONG || type == T_DOUBLE)
920 temp = FrameMap::rscratch1_long_opr;
921 else
922 temp = FrameMap::rscratch1_opr;
923
924 stack2reg(src, temp, src->type());
925 reg2stack(temp, dest, dest->type());
926 }
927
928
929 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
930 LIR_Address* addr = src->as_address_ptr();
931 LIR_Address* from_addr = src->as_address_ptr();
932
933 if (addr->base()->type() == T_OBJECT) {
934 __ verify_oop(addr->base()->as_pointer_register());
935 }
936
937 if (patch_code != lir_patch_none) {
938 deoptimize_trap(info);
939 return;
940 }
941
942 if (info != nullptr) {
943 add_debug_info_for_null_check_here(info);
944 }
945 int null_check_here = code_offset();
946 switch (type) {
947 case T_FLOAT: {
948 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
949 break;
950 }
951
952 case T_DOUBLE: {
953 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
954 break;
955 }
956
957 case T_ARRAY: // fall through
958 case T_OBJECT: // fall through
959 if (UseCompressedOops && !wide) {
960 __ ldrw(dest->as_register(), as_Address(from_addr));
961 } else {
962 __ ldr(dest->as_register(), as_Address(from_addr));
963 }
964 break;
965 case T_METADATA:
966 // We get here to store a method pointer to the stack to pass to
967 // a dtrace runtime call. This can't work on 64 bit with
968 // compressed klass ptrs: T_METADATA can be a compressed klass
969 // ptr or a 64 bit method pointer.
970 ShouldNotReachHere();
971 __ ldr(dest->as_register(), as_Address(from_addr));
972 break;
973 case T_ADDRESS:
974 __ ldr(dest->as_register(), as_Address(from_addr));
975 break;
976 case T_INT:
977 __ ldrw(dest->as_register(), as_Address(from_addr));
978 break;
979
980 case T_LONG: {
981 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
982 break;
983 }
984
985 case T_BYTE:
986 __ ldrsb(dest->as_register(), as_Address(from_addr));
987 break;
988 case T_BOOLEAN: {
989 __ ldrb(dest->as_register(), as_Address(from_addr));
990 break;
991 }
992
993 case T_CHAR:
994 __ ldrh(dest->as_register(), as_Address(from_addr));
995 break;
996 case T_SHORT:
997 __ ldrsh(dest->as_register(), as_Address(from_addr));
998 break;
999
1000 default:
1001 ShouldNotReachHere();
1002 }
1003
1004 if (is_reference_type(type)) {
1005 if (UseCompressedOops && !wide) {
1006 __ decode_heap_oop(dest->as_register());
1007 }
1008
1009 __ verify_oop(dest->as_register());
1010 }
1011 }
1012
1013
1014 int LIR_Assembler::array_element_size(BasicType type) const {
1015 int elem_size = type2aelembytes(type);
1016 return exact_log2(elem_size);
1017 }
1018
1019
1020 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1021 switch (op->code()) {
1022 case lir_idiv:
1023 case lir_irem:
1024 arithmetic_idiv(op->code(),
1025 op->in_opr1(),
1026 op->in_opr2(),
1027 op->in_opr3(),
1028 op->result_opr(),
1029 op->info());
1030 break;
1031 case lir_fmad:
1032 __ fmaddd(op->result_opr()->as_double_reg(),
1033 op->in_opr1()->as_double_reg(),
1034 op->in_opr2()->as_double_reg(),
1035 op->in_opr3()->as_double_reg());
1036 break;
1037 case lir_fmaf:
1038 __ fmadds(op->result_opr()->as_float_reg(),
1039 op->in_opr1()->as_float_reg(),
1040 op->in_opr2()->as_float_reg(),
1041 op->in_opr3()->as_float_reg());
1042 break;
1043 default: ShouldNotReachHere(); break;
1044 }
1045 }
1046
1047 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1048 #ifdef ASSERT
1049 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1050 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1051 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1052 #endif
1053
1054 if (op->cond() == lir_cond_always) {
1055 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1056 __ b(*(op->label()));
1057 } else {
1058 Assembler::Condition acond;
1059 if (op->code() == lir_cond_float_branch) {
1060 bool is_unordered = (op->ublock() == op->block());
1061 // Assembler::EQ does not permit unordered branches, so we add
1062 // another branch here. Likewise, Assembler::NE does not permit
1063 // ordered branches.
1064 if ((is_unordered && op->cond() == lir_cond_equal)
1065 || (!is_unordered && op->cond() == lir_cond_notEqual))
1066 __ br(Assembler::VS, *(op->ublock()->label()));
1067 switch(op->cond()) {
1068 case lir_cond_equal: acond = Assembler::EQ; break;
1069 case lir_cond_notEqual: acond = Assembler::NE; break;
1070 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1071 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1072 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1073 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1074 default: ShouldNotReachHere();
1075 acond = Assembler::EQ; // unreachable
1076 }
1077 } else {
1078 switch (op->cond()) {
1079 case lir_cond_equal: acond = Assembler::EQ; break;
1080 case lir_cond_notEqual: acond = Assembler::NE; break;
1081 case lir_cond_less: acond = Assembler::LT; break;
1082 case lir_cond_lessEqual: acond = Assembler::LE; break;
1083 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1084 case lir_cond_greater: acond = Assembler::GT; break;
1085 case lir_cond_belowEqual: acond = Assembler::LS; break;
1086 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1087 default: ShouldNotReachHere();
1088 acond = Assembler::EQ; // unreachable
1089 }
1090 }
1091 __ br(acond,*(op->label()));
1092 }
1093 }
1094
1095
1096
1097 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1098 LIR_Opr src = op->in_opr();
1099 LIR_Opr dest = op->result_opr();
1100
1101 switch (op->bytecode()) {
1102 case Bytecodes::_i2f:
1103 {
1104 __ scvtfws(dest->as_float_reg(), src->as_register());
1105 break;
1106 }
1107 case Bytecodes::_i2d:
1108 {
1109 __ scvtfwd(dest->as_double_reg(), src->as_register());
1110 break;
1111 }
1112 case Bytecodes::_l2d:
1113 {
1114 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1115 break;
1116 }
1117 case Bytecodes::_l2f:
1118 {
1119 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1120 break;
1121 }
1122 case Bytecodes::_f2d:
1123 {
1124 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1125 break;
1126 }
1127 case Bytecodes::_d2f:
1128 {
1129 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1130 break;
1131 }
1132 case Bytecodes::_i2c:
1133 {
1134 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1135 break;
1136 }
1137 case Bytecodes::_i2l:
1138 {
1139 __ sxtw(dest->as_register_lo(), src->as_register());
1140 break;
1141 }
1142 case Bytecodes::_i2s:
1143 {
1144 __ sxth(dest->as_register(), src->as_register());
1145 break;
1146 }
1147 case Bytecodes::_i2b:
1148 {
1149 __ sxtb(dest->as_register(), src->as_register());
1150 break;
1151 }
1152 case Bytecodes::_l2i:
1153 {
1154 _masm->block_comment("FIXME: This could be a no-op");
1155 __ uxtw(dest->as_register(), src->as_register_lo());
1156 break;
1157 }
1158 case Bytecodes::_d2l:
1159 {
1160 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1161 break;
1162 }
1163 case Bytecodes::_f2i:
1164 {
1165 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1166 break;
1167 }
1168 case Bytecodes::_f2l:
1169 {
1170 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1171 break;
1172 }
1173 case Bytecodes::_d2i:
1174 {
1175 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1176 break;
1177 }
1178 default: ShouldNotReachHere();
1179 }
1180 }
1181
1182 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1183 if (op->init_check()) {
1184 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1185 __ ldarb(rscratch1, rscratch1);
1186 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1187 add_debug_info_for_null_check_here(op->stub()->info());
1188 __ br(Assembler::NE, *op->stub()->entry());
1189 }
1190 __ allocate_object(op->obj()->as_register(),
1191 op->tmp1()->as_register(),
1192 op->tmp2()->as_register(),
1193 op->header_size(),
1194 op->object_size(),
1195 op->klass()->as_register(),
1196 *op->stub()->entry());
1197 __ bind(*op->stub()->continuation());
1198 }
1199
1200 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1201 Register len = op->len()->as_register();
1202 __ uxtw(len, len);
1203
1204 if (UseSlowPath ||
1205 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1206 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1207 __ b(*op->stub()->entry());
1208 } else {
1209 Register tmp1 = op->tmp1()->as_register();
1210 Register tmp2 = op->tmp2()->as_register();
1211 Register tmp3 = op->tmp3()->as_register();
1212 if (len == tmp1) {
1213 tmp1 = tmp3;
1214 } else if (len == tmp2) {
1215 tmp2 = tmp3;
1216 } else if (len == tmp3) {
1217 // everything is ok
1218 } else {
1219 __ mov(tmp3, len);
1220 }
1221 __ allocate_array(op->obj()->as_register(),
1222 len,
1223 tmp1,
1224 tmp2,
1225 arrayOopDesc::base_offset_in_bytes(op->type()),
1226 array_element_size(op->type()),
1227 op->klass()->as_register(),
1228 *op->stub()->entry(),
1229 op->zero_array());
1230 }
1231 __ bind(*op->stub()->continuation());
1232 }
1233
1234 void LIR_Assembler::type_profile_helper(Register mdo,
1235 ciMethodData *md, ciProfileData *data,
1236 Register recv, Label* update_done) {
1237
1238 // Given a profile data offset, generate an Address which points to
1239 // the corresponding slot in mdo->data().
1240 // Clobbers rscratch2.
1241 auto slot_at = [=](ByteSize offset) -> Address {
1242 return __ form_address(rscratch2, mdo,
1243 md->byte_offset_of_slot(data, offset),
1244 LogBytesPerWord);
1245 };
1246
1247 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1248 Label next_test;
1249 // See if the receiver is receiver[n].
1250 __ ldr(rscratch1, slot_at(ReceiverTypeData::receiver_offset(i)));
1251 __ cmp(recv, rscratch1);
1252 __ br(Assembler::NE, next_test);
1253 __ addptr(slot_at(ReceiverTypeData::receiver_count_offset(i)),
1254 DataLayout::counter_increment);
1255 __ b(*update_done);
1256 __ bind(next_test);
1257 }
1258
1259 // Didn't find receiver; find next empty slot and fill it in
1260 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1261 Label next_test;
1262 Address recv_addr(slot_at(ReceiverTypeData::receiver_offset(i)));
1263 __ ldr(rscratch1, recv_addr);
1264 __ cbnz(rscratch1, next_test);
1265 __ str(recv, recv_addr);
1266 __ mov(rscratch1, DataLayout::counter_increment);
1267 __ str(rscratch1, slot_at(ReceiverTypeData::receiver_count_offset(i)));
1268 __ b(*update_done);
1269 __ bind(next_test);
1270 }
1271 }
1272
1273 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1274 // we always need a stub for the failure case.
1275 CodeStub* stub = op->stub();
1276 Register obj = op->object()->as_register();
1277 Register k_RInfo = op->tmp1()->as_register();
1278 Register klass_RInfo = op->tmp2()->as_register();
1279 Register dst = op->result_opr()->as_register();
1280 ciKlass* k = op->klass();
1281 Register Rtmp1 = noreg;
1282
1283 // check if it needs to be profiled
1284 ciMethodData* md;
1285 ciProfileData* data;
1286
1287 const bool should_profile = op->should_profile();
1288
1289 if (should_profile) {
1290 ciMethod* method = op->profiled_method();
1291 assert(method != nullptr, "Should have method");
1292 int bci = op->profiled_bci();
1293 md = method->method_data_or_null();
1294 assert(md != nullptr, "Sanity");
1295 data = md->bci_to_data(bci);
1296 assert(data != nullptr, "need data for type check");
1297 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1298 }
1299 Label* success_target = success;
1300 Label* failure_target = failure;
1301
1302 if (obj == k_RInfo) {
1303 k_RInfo = dst;
1304 } else if (obj == klass_RInfo) {
1305 klass_RInfo = dst;
1306 }
1307 if (k->is_loaded() && !UseCompressedClassPointers) {
1308 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1309 } else {
1310 Rtmp1 = op->tmp3()->as_register();
1311 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1312 }
1313
1314 assert_different_registers(obj, k_RInfo, klass_RInfo);
1315
1316 if (should_profile) {
1317 Register mdo = klass_RInfo;
1318 __ mov_metadata(mdo, md->constant_encoding());
1319 Label not_null;
1320 __ cbnz(obj, not_null);
1321 // Object is null; update MDO and exit
1322 Address data_addr
1323 = __ form_address(rscratch2, mdo,
1324 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1325 0);
1326 __ ldrb(rscratch1, data_addr);
1327 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1328 __ strb(rscratch1, data_addr);
1329 __ b(*obj_is_null);
1330 __ bind(not_null);
1331
1332 Label update_done;
1333 Register recv = k_RInfo;
1334 __ load_klass(recv, obj);
1335 type_profile_helper(mdo, md, data, recv, &update_done);
1336 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1337 __ addptr(counter_addr, DataLayout::counter_increment);
1338
1339 __ bind(update_done);
1340 } else {
1341 __ cbz(obj, *obj_is_null);
1342 }
1343
1344 if (!k->is_loaded()) {
1345 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1346 } else {
1347 __ mov_metadata(k_RInfo, k->constant_encoding());
1348 }
1349 __ verify_oop(obj);
1350
1351 if (op->fast_check()) {
1352 // get object class
1353 // not a safepoint as obj null check happens earlier
1354 __ load_klass(rscratch1, obj);
1355 __ cmp( rscratch1, k_RInfo);
1356
1357 __ br(Assembler::NE, *failure_target);
1358 // successful cast, fall through to profile or jump
1359 } else {
1360 // get object class
1361 // not a safepoint as obj null check happens earlier
1362 __ load_klass(klass_RInfo, obj);
1363 if (k->is_loaded()) {
1364 // See if we get an immediate positive hit
1365 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1366 __ cmp(k_RInfo, rscratch1);
1367 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1368 __ br(Assembler::NE, *failure_target);
1369 // successful cast, fall through to profile or jump
1370 } else {
1371 // See if we get an immediate positive hit
1372 __ br(Assembler::EQ, *success_target);
1373 // check for self
1374 __ cmp(klass_RInfo, k_RInfo);
1375 __ br(Assembler::EQ, *success_target);
1376
1377 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1378 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1379 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1380 // result is a boolean
1381 __ cbzw(klass_RInfo, *failure_target);
1382 // successful cast, fall through to profile or jump
1383 }
1384 } else {
1385 // perform the fast part of the checking logic
1386 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1387 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1388 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1389 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1390 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1391 // result is a boolean
1392 __ cbz(k_RInfo, *failure_target);
1393 // successful cast, fall through to profile or jump
1394 }
1395 }
1396 __ b(*success);
1397 }
1398
1399
1400 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1401 const bool should_profile = op->should_profile();
1402
1403 LIR_Code code = op->code();
1404 if (code == lir_store_check) {
1405 Register value = op->object()->as_register();
1406 Register array = op->array()->as_register();
1407 Register k_RInfo = op->tmp1()->as_register();
1408 Register klass_RInfo = op->tmp2()->as_register();
1409 Register Rtmp1 = op->tmp3()->as_register();
1410
1411 CodeStub* stub = op->stub();
1412
1413 // check if it needs to be profiled
1414 ciMethodData* md;
1415 ciProfileData* data;
1416
1417 if (should_profile) {
1418 ciMethod* method = op->profiled_method();
1419 assert(method != nullptr, "Should have method");
1420 int bci = op->profiled_bci();
1421 md = method->method_data_or_null();
1422 assert(md != nullptr, "Sanity");
1423 data = md->bci_to_data(bci);
1424 assert(data != nullptr, "need data for type check");
1425 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1426 }
1427 Label done;
1428 Label* success_target = &done;
1429 Label* failure_target = stub->entry();
1430
1431 if (should_profile) {
1432 Label not_null;
1433 Register mdo = klass_RInfo;
1434 __ mov_metadata(mdo, md->constant_encoding());
1435 __ cbnz(value, not_null);
1436 // Object is null; update MDO and exit
1437 Address data_addr
1438 = __ form_address(rscratch2, mdo,
1439 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1440 __ ldrb(rscratch1, data_addr);
1441 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1442 __ strb(rscratch1, data_addr);
1443 __ b(done);
1444 __ bind(not_null);
1445
1446 Label update_done;
1447 Register recv = k_RInfo;
1448 __ load_klass(recv, value);
1449 type_profile_helper(mdo, md, data, recv, &update_done);
1450 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1451 __ addptr(counter_addr, DataLayout::counter_increment);
1452 __ bind(update_done);
1453 } else {
1454 __ cbz(value, done);
1455 }
1456
1457 add_debug_info_for_null_check_here(op->info_for_exception());
1458 __ load_klass(k_RInfo, array);
1459 __ load_klass(klass_RInfo, value);
1460
1461 // get instance klass (it's already uncompressed)
1462 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1463 // perform the fast part of the checking logic
1464 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1465 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1466 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1467 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
1468 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1469 // result is a boolean
1470 __ cbzw(k_RInfo, *failure_target);
1471 // fall through to the success case
1472
1473 __ bind(done);
1474 } else if (code == lir_checkcast) {
1475 Register obj = op->object()->as_register();
1476 Register dst = op->result_opr()->as_register();
1477 Label success;
1478 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1479 __ bind(success);
1480 if (dst != obj) {
1481 __ mov(dst, obj);
1482 }
1483 } else if (code == lir_instanceof) {
1484 Register obj = op->object()->as_register();
1485 Register dst = op->result_opr()->as_register();
1486 Label success, failure, done;
1487 emit_typecheck_helper(op, &success, &failure, &failure);
1488 __ bind(failure);
1489 __ mov(dst, zr);
1490 __ b(done);
1491 __ bind(success);
1492 __ mov(dst, 1);
1493 __ bind(done);
1494 } else {
1495 ShouldNotReachHere();
1496 }
1497 }
1498
1499 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1500 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1501 __ cset(rscratch1, Assembler::NE);
1502 __ membar(__ AnyAny);
1503 }
1504
1505 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1506 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1507 __ cset(rscratch1, Assembler::NE);
1508 __ membar(__ AnyAny);
1509 }
1510
1511
1512 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1513 Register addr;
1514 if (op->addr()->is_register()) {
1515 addr = as_reg(op->addr());
1516 } else {
1517 assert(op->addr()->is_address(), "what else?");
1518 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1519 assert(addr_ptr->disp() == 0, "need 0 disp");
1520 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1521 addr = as_reg(addr_ptr->base());
1522 }
1523 Register newval = as_reg(op->new_value());
1524 Register cmpval = as_reg(op->cmp_value());
1525
1526 if (op->code() == lir_cas_obj) {
1527 if (UseCompressedOops) {
1528 Register t1 = op->tmp1()->as_register();
1529 assert(op->tmp1()->is_valid(), "must be");
1530 __ encode_heap_oop(t1, cmpval);
1531 cmpval = t1;
1532 __ encode_heap_oop(rscratch2, newval);
1533 newval = rscratch2;
1534 casw(addr, newval, cmpval);
1535 } else {
1536 casl(addr, newval, cmpval);
1537 }
1538 } else if (op->code() == lir_cas_int) {
1539 casw(addr, newval, cmpval);
1540 } else {
1541 casl(addr, newval, cmpval);
1542 }
1543 }
1544
1545
1546 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1547 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1548 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1549
1550 Assembler::Condition acond, ncond;
1551 switch (condition) {
1552 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1553 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1554 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1555 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1556 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1557 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1558 case lir_cond_belowEqual:
1559 case lir_cond_aboveEqual:
1560 default: ShouldNotReachHere();
1561 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1562 }
1563
1564 assert(result->is_single_cpu() || result->is_double_cpu(),
1565 "expect single register for result");
1566 if (opr1->is_constant() && opr2->is_constant()
1567 && opr1->type() == T_INT && opr2->type() == T_INT) {
1568 jint val1 = opr1->as_jint();
1569 jint val2 = opr2->as_jint();
1570 if (val1 == 0 && val2 == 1) {
1571 __ cset(result->as_register(), ncond);
1572 return;
1573 } else if (val1 == 1 && val2 == 0) {
1574 __ cset(result->as_register(), acond);
1575 return;
1576 }
1577 }
1578
1579 if (opr1->is_constant() && opr2->is_constant()
1580 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1581 jlong val1 = opr1->as_jlong();
1582 jlong val2 = opr2->as_jlong();
1583 if (val1 == 0 && val2 == 1) {
1584 __ cset(result->as_register_lo(), ncond);
1585 return;
1586 } else if (val1 == 1 && val2 == 0) {
1587 __ cset(result->as_register_lo(), acond);
1588 return;
1589 }
1590 }
1591
1592 if (opr1->is_stack()) {
1593 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1594 opr1 = FrameMap::rscratch1_opr;
1595 } else if (opr1->is_constant()) {
1596 LIR_Opr tmp
1597 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1598 const2reg(opr1, tmp, lir_patch_none, nullptr);
1599 opr1 = tmp;
1600 }
1601
1602 if (opr2->is_stack()) {
1603 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1604 opr2 = FrameMap::rscratch2_opr;
1605 } else if (opr2->is_constant()) {
1606 LIR_Opr tmp
1607 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1608 const2reg(opr2, tmp, lir_patch_none, nullptr);
1609 opr2 = tmp;
1610 }
1611
1612 if (result->type() == T_LONG)
1613 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1614 else
1615 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1616 }
1617
1618 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1619 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1620
1621 if (left->is_single_cpu()) {
1622 Register lreg = left->as_register();
1623 Register dreg = as_reg(dest);
1624
1625 if (right->is_single_cpu()) {
1626 // cpu register - cpu register
1627
1628 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1629 "should be");
1630 Register rreg = right->as_register();
1631 switch (code) {
1632 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1633 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1634 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1635 default: ShouldNotReachHere();
1636 }
1637
1638 } else if (right->is_double_cpu()) {
1639 Register rreg = right->as_register_lo();
1640 // single_cpu + double_cpu: can happen with obj+long
1641 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1642 switch (code) {
1643 case lir_add: __ add(dreg, lreg, rreg); break;
1644 case lir_sub: __ sub(dreg, lreg, rreg); break;
1645 default: ShouldNotReachHere();
1646 }
1647 } else if (right->is_constant()) {
1648 // cpu register - constant
1649 jlong c;
1650
1651 // FIXME. This is fugly: we really need to factor all this logic.
1652 switch(right->type()) {
1653 case T_LONG:
1654 c = right->as_constant_ptr()->as_jlong();
1655 break;
1656 case T_INT:
1657 case T_ADDRESS:
1658 c = right->as_constant_ptr()->as_jint();
1659 break;
1660 default:
1661 ShouldNotReachHere();
1662 c = 0; // unreachable
1663 break;
1664 }
1665
1666 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1667 if (c == 0 && dreg == lreg) {
1668 COMMENT("effective nop elided");
1669 return;
1670 }
1671 switch(left->type()) {
1672 case T_INT:
1673 switch (code) {
1674 case lir_add: __ addw(dreg, lreg, c); break;
1675 case lir_sub: __ subw(dreg, lreg, c); break;
1676 default: ShouldNotReachHere();
1677 }
1678 break;
1679 case T_OBJECT:
1680 case T_ADDRESS:
1681 switch (code) {
1682 case lir_add: __ add(dreg, lreg, c); break;
1683 case lir_sub: __ sub(dreg, lreg, c); break;
1684 default: ShouldNotReachHere();
1685 }
1686 break;
1687 default:
1688 ShouldNotReachHere();
1689 }
1690 } else {
1691 ShouldNotReachHere();
1692 }
1693
1694 } else if (left->is_double_cpu()) {
1695 Register lreg_lo = left->as_register_lo();
1696
1697 if (right->is_double_cpu()) {
1698 // cpu register - cpu register
1699 Register rreg_lo = right->as_register_lo();
1700 switch (code) {
1701 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1702 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1703 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1704 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1705 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1706 default:
1707 ShouldNotReachHere();
1708 }
1709
1710 } else if (right->is_constant()) {
1711 jlong c = right->as_constant_ptr()->as_jlong();
1712 Register dreg = as_reg(dest);
1713 switch (code) {
1714 case lir_add:
1715 case lir_sub:
1716 if (c == 0 && dreg == lreg_lo) {
1717 COMMENT("effective nop elided");
1718 return;
1719 }
1720 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1721 break;
1722 case lir_div:
1723 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1724 if (c == 1) {
1725 // move lreg_lo to dreg if divisor is 1
1726 __ mov(dreg, lreg_lo);
1727 } else {
1728 unsigned int shift = log2i_exact(c);
1729 // use rscratch1 as intermediate result register
1730 __ asr(rscratch1, lreg_lo, 63);
1731 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1732 __ asr(dreg, rscratch1, shift);
1733 }
1734 break;
1735 case lir_rem:
1736 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1737 if (c == 1) {
1738 // move 0 to dreg if divisor is 1
1739 __ mov(dreg, zr);
1740 } else {
1741 // use rscratch1 as intermediate result register
1742 __ negs(rscratch1, lreg_lo);
1743 __ andr(dreg, lreg_lo, c - 1);
1744 __ andr(rscratch1, rscratch1, c - 1);
1745 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1746 }
1747 break;
1748 default:
1749 ShouldNotReachHere();
1750 }
1751 } else {
1752 ShouldNotReachHere();
1753 }
1754 } else if (left->is_single_fpu()) {
1755 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1756 switch (code) {
1757 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1758 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1759 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1760 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1761 default:
1762 ShouldNotReachHere();
1763 }
1764 } else if (left->is_double_fpu()) {
1765 if (right->is_double_fpu()) {
1766 // fpu register - fpu register
1767 switch (code) {
1768 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1769 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1770 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1771 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1772 default:
1773 ShouldNotReachHere();
1774 }
1775 } else {
1776 if (right->is_constant()) {
1777 ShouldNotReachHere();
1778 }
1779 ShouldNotReachHere();
1780 }
1781 } else if (left->is_single_stack() || left->is_address()) {
1782 assert(left == dest, "left and dest must be equal");
1783 ShouldNotReachHere();
1784 } else {
1785 ShouldNotReachHere();
1786 }
1787 }
1788
1789 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1790 switch(code) {
1791 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1792 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1793 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1794 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1795 default : ShouldNotReachHere();
1796 }
1797 }
1798
1799 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1800
1801 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1802 Register Rleft = left->is_single_cpu() ? left->as_register() :
1803 left->as_register_lo();
1804 if (dst->is_single_cpu()) {
1805 Register Rdst = dst->as_register();
1806 if (right->is_constant()) {
1807 switch (code) {
1808 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1809 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1810 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1811 default: ShouldNotReachHere(); break;
1812 }
1813 } else {
1814 Register Rright = right->is_single_cpu() ? right->as_register() :
1815 right->as_register_lo();
1816 switch (code) {
1817 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1818 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1819 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1820 default: ShouldNotReachHere(); break;
1821 }
1822 }
1823 } else {
1824 Register Rdst = dst->as_register_lo();
1825 if (right->is_constant()) {
1826 switch (code) {
1827 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1828 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1829 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1830 default: ShouldNotReachHere(); break;
1831 }
1832 } else {
1833 Register Rright = right->is_single_cpu() ? right->as_register() :
1834 right->as_register_lo();
1835 switch (code) {
1836 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1837 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1838 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1839 default: ShouldNotReachHere(); break;
1840 }
1841 }
1842 }
1843 }
1844
1845
1846
1847 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1848
1849 // opcode check
1850 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1851 bool is_irem = (code == lir_irem);
1852
1853 // operand check
1854 assert(left->is_single_cpu(), "left must be register");
1855 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1856 assert(result->is_single_cpu(), "result must be register");
1857 Register lreg = left->as_register();
1858 Register dreg = result->as_register();
1859
1860 // power-of-2 constant check and codegen
1861 if (right->is_constant()) {
1862 int c = right->as_constant_ptr()->as_jint();
1863 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1864 if (is_irem) {
1865 if (c == 1) {
1866 // move 0 to dreg if divisor is 1
1867 __ movw(dreg, zr);
1868 } else {
1869 // use rscratch1 as intermediate result register
1870 __ negsw(rscratch1, lreg);
1871 __ andw(dreg, lreg, c - 1);
1872 __ andw(rscratch1, rscratch1, c - 1);
1873 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1874 }
1875 } else {
1876 if (c == 1) {
1877 // move lreg to dreg if divisor is 1
1878 __ movw(dreg, lreg);
1879 } else {
1880 unsigned int shift = exact_log2(c);
1881 // use rscratch1 as intermediate result register
1882 __ asrw(rscratch1, lreg, 31);
1883 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1884 __ asrw(dreg, rscratch1, shift);
1885 }
1886 }
1887 } else {
1888 Register rreg = right->as_register();
1889 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1890 }
1891 }
1892
1893
1894 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1895 if (opr1->is_constant() && opr2->is_single_cpu()) {
1896 // tableswitch
1897 Register reg = as_reg(opr2);
1898 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1899 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1900 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1901 Register reg1 = as_reg(opr1);
1902 if (opr2->is_single_cpu()) {
1903 // cpu register - cpu register
1904 Register reg2 = opr2->as_register();
1905 if (is_reference_type(opr1->type())) {
1906 __ cmpoop(reg1, reg2);
1907 } else {
1908 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1909 __ cmpw(reg1, reg2);
1910 }
1911 return;
1912 }
1913 if (opr2->is_double_cpu()) {
1914 // cpu register - cpu register
1915 Register reg2 = opr2->as_register_lo();
1916 __ cmp(reg1, reg2);
1917 return;
1918 }
1919
1920 if (opr2->is_constant()) {
1921 bool is_32bit = false; // width of register operand
1922 jlong imm;
1923
1924 switch(opr2->type()) {
1925 case T_INT:
1926 imm = opr2->as_constant_ptr()->as_jint();
1927 is_32bit = true;
1928 break;
1929 case T_LONG:
1930 imm = opr2->as_constant_ptr()->as_jlong();
1931 break;
1932 case T_ADDRESS:
1933 imm = opr2->as_constant_ptr()->as_jint();
1934 break;
1935 case T_METADATA:
1936 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1937 break;
1938 case T_OBJECT:
1939 case T_ARRAY:
1940 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1941 __ cmpoop(reg1, rscratch1);
1942 return;
1943 default:
1944 ShouldNotReachHere();
1945 imm = 0; // unreachable
1946 break;
1947 }
1948
1949 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1950 if (is_32bit)
1951 __ cmpw(reg1, imm);
1952 else
1953 __ subs(zr, reg1, imm);
1954 return;
1955 } else {
1956 __ mov(rscratch1, imm);
1957 if (is_32bit)
1958 __ cmpw(reg1, rscratch1);
1959 else
1960 __ cmp(reg1, rscratch1);
1961 return;
1962 }
1963 } else
1964 ShouldNotReachHere();
1965 } else if (opr1->is_single_fpu()) {
1966 FloatRegister reg1 = opr1->as_float_reg();
1967 assert(opr2->is_single_fpu(), "expect single float register");
1968 FloatRegister reg2 = opr2->as_float_reg();
1969 __ fcmps(reg1, reg2);
1970 } else if (opr1->is_double_fpu()) {
1971 FloatRegister reg1 = opr1->as_double_reg();
1972 assert(opr2->is_double_fpu(), "expect double float register");
1973 FloatRegister reg2 = opr2->as_double_reg();
1974 __ fcmpd(reg1, reg2);
1975 } else {
1976 ShouldNotReachHere();
1977 }
1978 }
1979
1980 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1981 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1982 bool is_unordered_less = (code == lir_ucmp_fd2i);
1983 if (left->is_single_fpu()) {
1984 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1985 } else if (left->is_double_fpu()) {
1986 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1987 } else {
1988 ShouldNotReachHere();
1989 }
1990 } else if (code == lir_cmp_l2i) {
1991 Label done;
1992 __ cmp(left->as_register_lo(), right->as_register_lo());
1993 __ mov(dst->as_register(), (uint64_t)-1L);
1994 __ br(Assembler::LT, done);
1995 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
1996 __ bind(done);
1997 } else {
1998 ShouldNotReachHere();
1999 }
2000 }
2001
2002
2003 void LIR_Assembler::align_call(LIR_Code code) { }
2004
2005
2006 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2007 address call = __ trampoline_call(Address(op->addr(), rtype));
2008 if (call == nullptr) {
2009 bailout("trampoline stub overflow");
2010 return;
2011 }
2012 add_call_info(code_offset(), op->info());
2013 __ post_call_nop();
2014 }
2015
2016
2017 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2018 address call = __ ic_call(op->addr());
2019 if (call == nullptr) {
2020 bailout("trampoline stub overflow");
2021 return;
2022 }
2023 add_call_info(code_offset(), op->info());
2024 __ post_call_nop();
2025 }
2026
2027 void LIR_Assembler::emit_static_call_stub() {
2028 address call_pc = __ pc();
2029 address stub = __ start_a_stub(call_stub_size());
2030 if (stub == nullptr) {
2031 bailout("static call stub overflow");
2032 return;
2033 }
2034
2035 int start = __ offset();
2036
2037 __ relocate(static_stub_Relocation::spec(call_pc));
2038 __ emit_static_call_stub();
2039
2040 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2041 <= call_stub_size(), "stub too big");
2042 __ end_a_stub();
2043 }
2044
2045
2046 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2047 assert(exceptionOop->as_register() == r0, "must match");
2048 assert(exceptionPC->as_register() == r3, "must match");
2049
2050 // exception object is not added to oop map by LinearScan
2051 // (LinearScan assumes that no oops are in fixed registers)
2052 info->add_register_oop(exceptionOop);
2053 StubId unwind_id;
2054
2055 // get current pc information
2056 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2057 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2058 // As no instructions have been generated yet for this LIR node it's
2059 // possible that an oop map already exists for the current offset.
2060 // In that case insert an dummy NOP here to ensure all oop map PCs
2061 // are unique. See JDK-8237483.
2062 __ nop();
2063 }
2064 int pc_for_athrow_offset = __ offset();
2065 InternalAddress pc_for_athrow(__ pc());
2066 __ adr(exceptionPC->as_register(), pc_for_athrow);
2067 add_call_info(pc_for_athrow_offset, info); // for exception handler
2068
2069 __ verify_not_null_oop(r0);
2070 // search an exception handler (r0: exception oop, r3: throwing pc)
2071 if (compilation()->has_fpu_code()) {
2072 unwind_id = StubId::c1_handle_exception_id;
2073 } else {
2074 unwind_id = StubId::c1_handle_exception_nofpu_id;
2075 }
2076 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2077
2078 // FIXME: enough room for two byte trap ????
2079 __ nop();
2080 }
2081
2082
2083 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2084 assert(exceptionOop->as_register() == r0, "must match");
2085
2086 __ b(_unwind_handler_entry);
2087 }
2088
2089
2090 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2091 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2092 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2093
2094 switch (left->type()) {
2095 case T_INT: {
2096 switch (code) {
2097 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2098 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2099 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2100 default:
2101 ShouldNotReachHere();
2102 break;
2103 }
2104 break;
2105 case T_LONG:
2106 case T_ADDRESS:
2107 case T_OBJECT:
2108 switch (code) {
2109 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2110 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2111 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2112 default:
2113 ShouldNotReachHere();
2114 break;
2115 }
2116 break;
2117 default:
2118 ShouldNotReachHere();
2119 break;
2120 }
2121 }
2122 }
2123
2124
2125 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2126 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2127 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2128
2129 switch (left->type()) {
2130 case T_INT: {
2131 switch (code) {
2132 case lir_shl: __ lslw (dreg, lreg, count); break;
2133 case lir_shr: __ asrw (dreg, lreg, count); break;
2134 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2135 default:
2136 ShouldNotReachHere();
2137 break;
2138 }
2139 break;
2140 case T_LONG:
2141 case T_ADDRESS:
2142 case T_OBJECT:
2143 switch (code) {
2144 case lir_shl: __ lsl (dreg, lreg, count); break;
2145 case lir_shr: __ asr (dreg, lreg, count); break;
2146 case lir_ushr: __ lsr (dreg, lreg, count); break;
2147 default:
2148 ShouldNotReachHere();
2149 break;
2150 }
2151 break;
2152 default:
2153 ShouldNotReachHere();
2154 break;
2155 }
2156 }
2157 }
2158
2159
2160 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2161 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2162 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2163 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2164 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2165 }
2166
2167
2168 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2169 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2170 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2171 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2172 __ mov (rscratch1, c);
2173 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2174 }
2175
2176
2177 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2178 ShouldNotReachHere();
2179 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2180 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2181 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2182 __ lea(rscratch1, __ constant_oop_address(o));
2183 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2184 }
2185
2186
2187 // This code replaces a call to arraycopy; no exception may
2188 // be thrown in this code, they must be thrown in the System.arraycopy
2189 // activation frame; we could save some checks if this would not be the case
2190 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2191 ciArrayKlass* default_type = op->expected_type();
2192 Register src = op->src()->as_register();
2193 Register dst = op->dst()->as_register();
2194 Register src_pos = op->src_pos()->as_register();
2195 Register dst_pos = op->dst_pos()->as_register();
2196 Register length = op->length()->as_register();
2197 Register tmp = op->tmp()->as_register();
2198
2199 CodeStub* stub = op->stub();
2200 int flags = op->flags();
2201 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2202 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2203
2204 // if we don't know anything, just go through the generic arraycopy
2205 if (default_type == nullptr // || basic_type == T_OBJECT
2206 ) {
2207 Label done;
2208 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2209
2210 // Save the arguments in case the generic arraycopy fails and we
2211 // have to fall back to the JNI stub
2212 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2213 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2214 __ str(src, Address(sp, 4*BytesPerWord));
2215
2216 address copyfunc_addr = StubRoutines::generic_arraycopy();
2217 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2218
2219 // The arguments are in java calling convention so we shift them
2220 // to C convention
2221 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2222 __ mov(c_rarg0, j_rarg0);
2223 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2224 __ mov(c_rarg1, j_rarg1);
2225 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2226 __ mov(c_rarg2, j_rarg2);
2227 assert_different_registers(c_rarg3, j_rarg4);
2228 __ mov(c_rarg3, j_rarg3);
2229 __ mov(c_rarg4, j_rarg4);
2230 #ifndef PRODUCT
2231 if (PrintC1Statistics) {
2232 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2233 }
2234 #endif
2235 __ far_call(RuntimeAddress(copyfunc_addr));
2236
2237 __ cbz(r0, *stub->continuation());
2238
2239 // Reload values from the stack so they are where the stub
2240 // expects them.
2241 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2242 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2243 __ ldr(src, Address(sp, 4*BytesPerWord));
2244
2245 // r0 is -1^K where K == partial copied count
2246 __ eonw(rscratch1, r0, zr);
2247 // adjust length down and src/end pos up by partial copied count
2248 __ subw(length, length, rscratch1);
2249 __ addw(src_pos, src_pos, rscratch1);
2250 __ addw(dst_pos, dst_pos, rscratch1);
2251 __ b(*stub->entry());
2252
2253 __ bind(*stub->continuation());
2254 return;
2255 }
2256
2257 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2258
2259 int elem_size = type2aelembytes(basic_type);
2260 int scale = exact_log2(elem_size);
2261
2262 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2263 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2264
2265 // test for null
2266 if (flags & LIR_OpArrayCopy::src_null_check) {
2267 __ cbz(src, *stub->entry());
2268 }
2269 if (flags & LIR_OpArrayCopy::dst_null_check) {
2270 __ cbz(dst, *stub->entry());
2271 }
2272
2273 // If the compiler was not able to prove that exact type of the source or the destination
2274 // of the arraycopy is an array type, check at runtime if the source or the destination is
2275 // an instance type.
2276 if (flags & LIR_OpArrayCopy::type_check) {
2277 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2278 __ load_klass(tmp, dst);
2279 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2280 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2281 __ br(Assembler::GE, *stub->entry());
2282 }
2283
2284 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2285 __ load_klass(tmp, src);
2286 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2287 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2288 __ br(Assembler::GE, *stub->entry());
2289 }
2290 }
2291
2292 // check if negative
2293 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2294 __ cmpw(src_pos, 0);
2295 __ br(Assembler::LT, *stub->entry());
2296 }
2297 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2298 __ cmpw(dst_pos, 0);
2299 __ br(Assembler::LT, *stub->entry());
2300 }
2301
2302 if (flags & LIR_OpArrayCopy::length_positive_check) {
2303 __ cmpw(length, 0);
2304 __ br(Assembler::LT, *stub->entry());
2305 }
2306
2307 if (flags & LIR_OpArrayCopy::src_range_check) {
2308 __ addw(tmp, src_pos, length);
2309 __ ldrw(rscratch1, src_length_addr);
2310 __ cmpw(tmp, rscratch1);
2311 __ br(Assembler::HI, *stub->entry());
2312 }
2313 if (flags & LIR_OpArrayCopy::dst_range_check) {
2314 __ addw(tmp, dst_pos, length);
2315 __ ldrw(rscratch1, dst_length_addr);
2316 __ cmpw(tmp, rscratch1);
2317 __ br(Assembler::HI, *stub->entry());
2318 }
2319
2320 if (flags & LIR_OpArrayCopy::type_check) {
2321 // We don't know the array types are compatible
2322 if (basic_type != T_OBJECT) {
2323 // Simple test for basic type arrays
2324 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2325 __ br(Assembler::NE, *stub->entry());
2326 } else {
2327 // For object arrays, if src is a sub class of dst then we can
2328 // safely do the copy.
2329 Label cont, slow;
2330
2331 #define PUSH(r1, r2) \
2332 stp(r1, r2, __ pre(sp, -2 * wordSize));
2333
2334 #define POP(r1, r2) \
2335 ldp(r1, r2, __ post(sp, 2 * wordSize));
2336
2337 __ PUSH(src, dst);
2338
2339 __ load_klass(src, src);
2340 __ load_klass(dst, dst);
2341
2342 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2343
2344 __ PUSH(src, dst);
2345 __ far_call(RuntimeAddress(Runtime1::entry_for(StubId::c1_slow_subtype_check_id)));
2346 __ POP(src, dst);
2347
2348 __ cbnz(src, cont);
2349
2350 __ bind(slow);
2351 __ POP(src, dst);
2352
2353 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2354 if (copyfunc_addr != nullptr) { // use stub if available
2355 // src is not a sub class of dst so we have to do a
2356 // per-element check.
2357
2358 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2359 if ((flags & mask) != mask) {
2360 // Check that at least both of them object arrays.
2361 assert(flags & mask, "one of the two should be known to be an object array");
2362
2363 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2364 __ load_klass(tmp, src);
2365 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2366 __ load_klass(tmp, dst);
2367 }
2368 int lh_offset = in_bytes(Klass::layout_helper_offset());
2369 Address klass_lh_addr(tmp, lh_offset);
2370 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2371 __ ldrw(rscratch1, klass_lh_addr);
2372 __ mov(rscratch2, objArray_lh);
2373 __ eorw(rscratch1, rscratch1, rscratch2);
2374 __ cbnzw(rscratch1, *stub->entry());
2375 }
2376
2377 // Spill because stubs can use any register they like and it's
2378 // easier to restore just those that we care about.
2379 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2380 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2381 __ str(src, Address(sp, 4*BytesPerWord));
2382
2383 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2384 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2385 assert_different_registers(c_rarg0, dst, dst_pos, length);
2386 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2387 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2388 assert_different_registers(c_rarg1, dst, length);
2389 __ uxtw(c_rarg2, length);
2390 assert_different_registers(c_rarg2, dst);
2391
2392 __ load_klass(c_rarg4, dst);
2393 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2394 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2395 __ far_call(RuntimeAddress(copyfunc_addr));
2396
2397 #ifndef PRODUCT
2398 if (PrintC1Statistics) {
2399 Label failed;
2400 __ cbnz(r0, failed);
2401 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2402 __ bind(failed);
2403 }
2404 #endif
2405
2406 __ cbz(r0, *stub->continuation());
2407
2408 #ifndef PRODUCT
2409 if (PrintC1Statistics) {
2410 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2411 }
2412 #endif
2413 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2414
2415 // Restore previously spilled arguments
2416 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2417 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2418 __ ldr(src, Address(sp, 4*BytesPerWord));
2419
2420 // return value is -1^K where K is partial copied count
2421 __ eonw(rscratch1, r0, zr);
2422 // adjust length down and src/end pos up by partial copied count
2423 __ subw(length, length, rscratch1);
2424 __ addw(src_pos, src_pos, rscratch1);
2425 __ addw(dst_pos, dst_pos, rscratch1);
2426 }
2427
2428 __ b(*stub->entry());
2429
2430 __ bind(cont);
2431 __ POP(src, dst);
2432 }
2433 }
2434
2435 #ifdef ASSERT
2436 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2437 // Sanity check the known type with the incoming class. For the
2438 // primitive case the types must match exactly with src.klass and
2439 // dst.klass each exactly matching the default type. For the
2440 // object array case, if no type check is needed then either the
2441 // dst type is exactly the expected type and the src type is a
2442 // subtype which we can't check or src is the same array as dst
2443 // but not necessarily exactly of type default_type.
2444 Label known_ok, halt;
2445 __ mov_metadata(tmp, default_type->constant_encoding());
2446
2447 if (basic_type != T_OBJECT) {
2448 __ cmp_klass(dst, tmp, rscratch1);
2449 __ br(Assembler::NE, halt);
2450 __ cmp_klass(src, tmp, rscratch1);
2451 __ br(Assembler::EQ, known_ok);
2452 } else {
2453 __ cmp_klass(dst, tmp, rscratch1);
2454 __ br(Assembler::EQ, known_ok);
2455 __ cmp(src, dst);
2456 __ br(Assembler::EQ, known_ok);
2457 }
2458 __ bind(halt);
2459 __ stop("incorrect type information in arraycopy");
2460 __ bind(known_ok);
2461 }
2462 #endif
2463
2464 #ifndef PRODUCT
2465 if (PrintC1Statistics) {
2466 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2467 }
2468 #endif
2469
2470 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2471 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2472 assert_different_registers(c_rarg0, dst, dst_pos, length);
2473 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2474 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2475 assert_different_registers(c_rarg1, dst, length);
2476 __ uxtw(c_rarg2, length);
2477 assert_different_registers(c_rarg2, dst);
2478
2479 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2480 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2481 const char *name;
2482 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2483
2484 CodeBlob *cb = CodeCache::find_blob(entry);
2485 if (cb) {
2486 __ far_call(RuntimeAddress(entry));
2487 } else {
2488 __ call_VM_leaf(entry, 3);
2489 }
2490
2491 if (stub != nullptr) {
2492 __ bind(*stub->continuation());
2493 }
2494 }
2495
2496
2497
2498
2499 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2500 Register obj = op->obj_opr()->as_register(); // may not be an oop
2501 Register hdr = op->hdr_opr()->as_register();
2502 Register lock = op->lock_opr()->as_register();
2503 Register temp = op->scratch_opr()->as_register();
2504 if (op->code() == lir_lock) {
2505 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2506 // add debug info for NullPointerException only if one is possible
2507 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2508 if (op->info() != nullptr) {
2509 add_debug_info_for_null_check(null_check_offset, op->info());
2510 }
2511 // done
2512 } else if (op->code() == lir_unlock) {
2513 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2514 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2515 } else {
2516 Unimplemented();
2517 }
2518 __ bind(*op->stub()->continuation());
2519 }
2520
2521 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2522 Register obj = op->obj()->as_pointer_register();
2523 Register result = op->result_opr()->as_pointer_register();
2524
2525 CodeEmitInfo* info = op->info();
2526 if (info != nullptr) {
2527 add_debug_info_for_null_check_here(info);
2528 }
2529
2530 __ load_klass(result, obj);
2531 }
2532
2533 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2534 ciMethod* method = op->profiled_method();
2535 int bci = op->profiled_bci();
2536 ciMethod* callee = op->profiled_callee();
2537
2538 // Update counter for all call types
2539 ciMethodData* md = method->method_data_or_null();
2540 assert(md != nullptr, "Sanity");
2541 ciProfileData* data = md->bci_to_data(bci);
2542 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2543 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2544 Register mdo = op->mdo()->as_register();
2545 __ mov_metadata(mdo, md->constant_encoding());
2546 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2547 // Perform additional virtual call profiling for invokevirtual and
2548 // invokeinterface bytecodes
2549 if (op->should_profile_receiver_type()) {
2550 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2551 Register recv = op->recv()->as_register();
2552 assert_different_registers(mdo, recv);
2553 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2554 ciKlass* known_klass = op->known_holder();
2555 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2556 // We know the type that will be seen at this call site; we can
2557 // statically update the MethodData* rather than needing to do
2558 // dynamic tests on the receiver type
2559
2560 // NOTE: we should probably put a lock around this search to
2561 // avoid collisions by concurrent compilations
2562 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2563 uint i;
2564 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2565 ciKlass* receiver = vc_data->receiver(i);
2566 if (known_klass->equals(receiver)) {
2567 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2568 __ addptr(data_addr, DataLayout::counter_increment);
2569 return;
2570 }
2571 }
2572
2573 // Receiver type not found in profile data; select an empty slot
2574
2575 // Note that this is less efficient than it should be because it
2576 // always does a write to the receiver part of the
2577 // VirtualCallData rather than just the first time
2578 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2579 ciKlass* receiver = vc_data->receiver(i);
2580 if (receiver == nullptr) {
2581 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2582 Address recv_addr =
2583 __ form_address(rscratch2, mdo,
2584 md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)),
2585 LogBytesPerWord);
2586 __ str(rscratch1, recv_addr);
2587 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2588 __ addptr(data_addr, DataLayout::counter_increment);
2589 return;
2590 }
2591 }
2592 } else {
2593 __ load_klass(recv, recv);
2594 Label update_done;
2595 type_profile_helper(mdo, md, data, recv, &update_done);
2596 // Receiver did not match any saved receiver and there is no empty row for it.
2597 // Increment total counter to indicate polymorphic case.
2598 __ addptr(counter_addr, DataLayout::counter_increment);
2599
2600 __ bind(update_done);
2601 }
2602 } else {
2603 // Static call
2604 __ addptr(counter_addr, DataLayout::counter_increment);
2605 }
2606 }
2607
2608
2609 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2610 Unimplemented();
2611 }
2612
2613
2614 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2615 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2616 }
2617
2618 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2619 assert(op->crc()->is_single_cpu(), "crc must be register");
2620 assert(op->val()->is_single_cpu(), "byte value must be register");
2621 assert(op->result_opr()->is_single_cpu(), "result must be register");
2622 Register crc = op->crc()->as_register();
2623 Register val = op->val()->as_register();
2624 Register res = op->result_opr()->as_register();
2625
2626 assert_different_registers(val, crc, res);
2627 uint64_t offset;
2628 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2629 __ add(res, res, offset);
2630
2631 __ mvnw(crc, crc); // ~crc
2632 __ update_byte_crc32(crc, val, res);
2633 __ mvnw(res, crc); // ~crc
2634 }
2635
2636 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2637 COMMENT("emit_profile_type {");
2638 Register obj = op->obj()->as_register();
2639 Register tmp = op->tmp()->as_pointer_register();
2640 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2641 ciKlass* exact_klass = op->exact_klass();
2642 intptr_t current_klass = op->current_klass();
2643 bool not_null = op->not_null();
2644 bool no_conflict = op->no_conflict();
2645
2646 Label update, next, none;
2647
2648 bool do_null = !not_null;
2649 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2650 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2651
2652 assert(do_null || do_update, "why are we here?");
2653 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2654 assert(mdo_addr.base() != rscratch1, "wrong register");
2655
2656 __ verify_oop(obj);
2657
2658 if (tmp != obj) {
2659 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2660 __ mov(tmp, obj);
2661 } else {
2662 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2663 }
2664 if (do_null) {
2665 __ cbnz(tmp, update);
2666 if (!TypeEntries::was_null_seen(current_klass)) {
2667 __ ldr(rscratch2, mdo_addr);
2668 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2669 __ str(rscratch2, mdo_addr);
2670 }
2671 if (do_update) {
2672 #ifndef ASSERT
2673 __ b(next);
2674 }
2675 #else
2676 __ b(next);
2677 }
2678 } else {
2679 __ cbnz(tmp, update);
2680 __ stop("unexpected null obj");
2681 #endif
2682 }
2683
2684 __ bind(update);
2685
2686 if (do_update) {
2687 #ifdef ASSERT
2688 if (exact_klass != nullptr) {
2689 Label ok;
2690 __ load_klass(tmp, tmp);
2691 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2692 __ eor(rscratch1, tmp, rscratch1);
2693 __ cbz(rscratch1, ok);
2694 __ stop("exact klass and actual klass differ");
2695 __ bind(ok);
2696 }
2697 #endif
2698 if (!no_conflict) {
2699 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2700 if (exact_klass != nullptr) {
2701 __ mov_metadata(tmp, exact_klass->constant_encoding());
2702 } else {
2703 __ load_klass(tmp, tmp);
2704 }
2705
2706 __ ldr(rscratch2, mdo_addr);
2707 __ eor(tmp, tmp, rscratch2);
2708 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2709 // klass seen before, nothing to do. The unknown bit may have been
2710 // set already but no need to check.
2711 __ cbz(rscratch1, next);
2712
2713 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2714
2715 if (TypeEntries::is_type_none(current_klass)) {
2716 __ cbz(rscratch2, none);
2717 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2718 __ br(Assembler::EQ, none);
2719 // There is a chance that the checks above
2720 // fail if another thread has just set the
2721 // profiling to this obj's klass
2722 __ dmb(Assembler::ISHLD);
2723 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2724 __ ldr(rscratch2, mdo_addr);
2725 __ eor(tmp, tmp, rscratch2);
2726 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2727 __ cbz(rscratch1, next);
2728 }
2729 } else {
2730 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2731 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2732
2733 __ ldr(tmp, mdo_addr);
2734 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2735 }
2736
2737 // different than before. Cannot keep accurate profile.
2738 __ ldr(rscratch2, mdo_addr);
2739 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2740 __ str(rscratch2, mdo_addr);
2741
2742 if (TypeEntries::is_type_none(current_klass)) {
2743 __ b(next);
2744
2745 __ bind(none);
2746 // first time here. Set profile type.
2747 __ str(tmp, mdo_addr);
2748 #ifdef ASSERT
2749 __ andr(tmp, tmp, TypeEntries::type_mask);
2750 __ verify_klass_ptr(tmp);
2751 #endif
2752 }
2753 } else {
2754 // There's a single possible klass at this profile point
2755 assert(exact_klass != nullptr, "should be");
2756 if (TypeEntries::is_type_none(current_klass)) {
2757 __ mov_metadata(tmp, exact_klass->constant_encoding());
2758 __ ldr(rscratch2, mdo_addr);
2759 __ eor(tmp, tmp, rscratch2);
2760 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2761 __ cbz(rscratch1, next);
2762 #ifdef ASSERT
2763 {
2764 Label ok;
2765 __ ldr(rscratch1, mdo_addr);
2766 __ cbz(rscratch1, ok);
2767 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2768 __ br(Assembler::EQ, ok);
2769 // may have been set by another thread
2770 __ dmb(Assembler::ISHLD);
2771 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2772 __ ldr(rscratch2, mdo_addr);
2773 __ eor(rscratch2, rscratch1, rscratch2);
2774 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2775 __ cbz(rscratch2, ok);
2776
2777 __ stop("unexpected profiling mismatch");
2778 __ bind(ok);
2779 }
2780 #endif
2781 // first time here. Set profile type.
2782 __ str(tmp, mdo_addr);
2783 #ifdef ASSERT
2784 __ andr(tmp, tmp, TypeEntries::type_mask);
2785 __ verify_klass_ptr(tmp);
2786 #endif
2787 } else {
2788 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2789 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2790
2791 __ ldr(tmp, mdo_addr);
2792 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2793
2794 __ orr(tmp, tmp, TypeEntries::type_unknown);
2795 __ str(tmp, mdo_addr);
2796 // FIXME: Write barrier needed here?
2797 }
2798 }
2799
2800 __ bind(next);
2801 }
2802 COMMENT("} emit_profile_type");
2803 }
2804
2805
2806 void LIR_Assembler::align_backward_branch_target() {
2807 }
2808
2809
2810 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2811 // tmp must be unused
2812 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2813
2814 if (left->is_single_cpu()) {
2815 assert(dest->is_single_cpu(), "expect single result reg");
2816 __ negw(dest->as_register(), left->as_register());
2817 } else if (left->is_double_cpu()) {
2818 assert(dest->is_double_cpu(), "expect double result reg");
2819 __ neg(dest->as_register_lo(), left->as_register_lo());
2820 } else if (left->is_single_fpu()) {
2821 assert(dest->is_single_fpu(), "expect single float result reg");
2822 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2823 } else {
2824 assert(left->is_double_fpu(), "expect double float operand reg");
2825 assert(dest->is_double_fpu(), "expect double float result reg");
2826 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2827 }
2828 }
2829
2830
2831 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2832 if (patch_code != lir_patch_none) {
2833 deoptimize_trap(info);
2834 return;
2835 }
2836
2837 __ lea(dest->as_pointer_register(), as_Address(addr->as_address_ptr()));
2838 }
2839
2840
2841 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2842 assert(!tmp->is_valid(), "don't need temporary");
2843
2844 CodeBlob *cb = CodeCache::find_blob(dest);
2845 if (cb) {
2846 __ far_call(RuntimeAddress(dest));
2847 } else {
2848 __ mov(rscratch1, RuntimeAddress(dest));
2849 __ blr(rscratch1);
2850 }
2851
2852 if (info != nullptr) {
2853 add_call_info_here(info);
2854 }
2855 __ post_call_nop();
2856 }
2857
2858 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2859 if (dest->is_address() || src->is_address()) {
2860 move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
2861 } else {
2862 ShouldNotReachHere();
2863 }
2864 }
2865
2866 #ifdef ASSERT
2867 // emit run-time assertion
2868 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2869 assert(op->code() == lir_assert, "must be");
2870
2871 if (op->in_opr1()->is_valid()) {
2872 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2873 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2874 } else {
2875 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2876 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2877 }
2878
2879 Label ok;
2880 if (op->condition() != lir_cond_always) {
2881 Assembler::Condition acond = Assembler::AL;
2882 switch (op->condition()) {
2883 case lir_cond_equal: acond = Assembler::EQ; break;
2884 case lir_cond_notEqual: acond = Assembler::NE; break;
2885 case lir_cond_less: acond = Assembler::LT; break;
2886 case lir_cond_lessEqual: acond = Assembler::LE; break;
2887 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2888 case lir_cond_greater: acond = Assembler::GT; break;
2889 case lir_cond_belowEqual: acond = Assembler::LS; break;
2890 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2891 default: ShouldNotReachHere();
2892 }
2893 __ br(acond, ok);
2894 }
2895 if (op->halt()) {
2896 const char* str = __ code_string(op->msg());
2897 __ stop(str);
2898 } else {
2899 breakpoint();
2900 }
2901 __ bind(ok);
2902 }
2903 #endif
2904
2905 #ifndef PRODUCT
2906 #define COMMENT(x) do { __ block_comment(x); } while (0)
2907 #else
2908 #define COMMENT(x)
2909 #endif
2910
2911 void LIR_Assembler::membar() {
2912 COMMENT("membar");
2913 __ membar(MacroAssembler::AnyAny);
2914 }
2915
2916 void LIR_Assembler::membar_acquire() {
2917 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2918 }
2919
2920 void LIR_Assembler::membar_release() {
2921 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2922 }
2923
2924 void LIR_Assembler::membar_loadload() {
2925 __ membar(Assembler::LoadLoad);
2926 }
2927
2928 void LIR_Assembler::membar_storestore() {
2929 __ membar(MacroAssembler::StoreStore);
2930 }
2931
2932 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2933
2934 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2935
2936 void LIR_Assembler::on_spin_wait() {
2937 __ spin_wait();
2938 }
2939
2940 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2941 __ mov(result_reg->as_register(), rthread);
2942 }
2943
2944
2945 void LIR_Assembler::peephole(LIR_List *lir) {
2946 #if 0
2947 if (tableswitch_count >= max_tableswitches)
2948 return;
2949
2950 /*
2951 This finite-state automaton recognizes sequences of compare-and-
2952 branch instructions. We will turn them into a tableswitch. You
2953 could argue that C1 really shouldn't be doing this sort of
2954 optimization, but without it the code is really horrible.
2955 */
2956
2957 enum { start_s, cmp1_s, beq_s, cmp_s } state;
2958 int first_key, last_key = -2147483648;
2959 int next_key = 0;
2960 int start_insn = -1;
2961 int last_insn = -1;
2962 Register reg = noreg;
2963 LIR_Opr reg_opr;
2964 state = start_s;
2965
2966 LIR_OpList* inst = lir->instructions_list();
2967 for (int i = 0; i < inst->length(); i++) {
2968 LIR_Op* op = inst->at(i);
2969 switch (state) {
2970 case start_s:
2971 first_key = -1;
2972 start_insn = i;
2973 switch (op->code()) {
2974 case lir_cmp:
2975 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2976 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2977 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2978 && opr2->is_constant()
2979 && opr2->type() == T_INT) {
2980 reg_opr = opr1;
2981 reg = opr1->as_register();
2982 first_key = opr2->as_constant_ptr()->as_jint();
2983 next_key = first_key + 1;
2984 state = cmp_s;
2985 goto next_state;
2986 }
2987 break;
2988 }
2989 break;
2990 case cmp_s:
2991 switch (op->code()) {
2992 case lir_branch:
2993 if (op->as_OpBranch()->cond() == lir_cond_equal) {
2994 state = beq_s;
2995 last_insn = i;
2996 goto next_state;
2997 }
2998 }
2999 state = start_s;
3000 break;
3001 case beq_s:
3002 switch (op->code()) {
3003 case lir_cmp: {
3004 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3005 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3006 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3007 && opr1->as_register() == reg
3008 && opr2->is_constant()
3009 && opr2->type() == T_INT
3010 && opr2->as_constant_ptr()->as_jint() == next_key) {
3011 last_key = next_key;
3012 next_key++;
3013 state = cmp_s;
3014 goto next_state;
3015 }
3016 }
3017 }
3018 last_key = next_key;
3019 state = start_s;
3020 break;
3021 default:
3022 assert(false, "impossible state");
3023 }
3024 if (state == start_s) {
3025 if (first_key < last_key - 5L && reg != noreg) {
3026 {
3027 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3028 // reg->encoding(),
3029 // start_insn, first_key, last_key);
3030 // for (int i = 0; i < inst->length(); i++) {
3031 // inst->at(i)->print();
3032 // tty->print("\n");
3033 // }
3034 // tty->print("\n");
3035 }
3036
3037 struct tableswitch *sw = &switches[tableswitch_count];
3038 sw->_insn_index = start_insn, sw->_first_key = first_key,
3039 sw->_last_key = last_key, sw->_reg = reg;
3040 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3041 {
3042 // Insert the new table of branches
3043 int offset = last_insn;
3044 for (int n = first_key; n < last_key; n++) {
3045 inst->insert_before
3046 (last_insn + 1,
3047 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3048 inst->at(offset)->as_OpBranch()->label()));
3049 offset -= 2, i++;
3050 }
3051 }
3052 // Delete all the old compare-and-branch instructions
3053 for (int n = first_key; n < last_key; n++) {
3054 inst->remove_at(start_insn);
3055 inst->remove_at(start_insn);
3056 }
3057 // Insert the tableswitch instruction
3058 inst->insert_before(start_insn,
3059 new LIR_Op2(lir_cmp, lir_cond_always,
3060 LIR_OprFact::intConst(tableswitch_count),
3061 reg_opr));
3062 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3063 tableswitch_count++;
3064 }
3065 reg = noreg;
3066 last_key = -2147483648;
3067 }
3068 next_state:
3069 ;
3070 }
3071 #endif
3072 }
3073
3074 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3075 Address addr = as_Address(src->as_address_ptr());
3076 BasicType type = src->type();
3077 bool is_oop = is_reference_type(type);
3078
3079 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3080 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3081
3082 switch(type) {
3083 case T_INT:
3084 xchg = &MacroAssembler::atomic_xchgalw;
3085 add = &MacroAssembler::atomic_addalw;
3086 break;
3087 case T_LONG:
3088 xchg = &MacroAssembler::atomic_xchgal;
3089 add = &MacroAssembler::atomic_addal;
3090 break;
3091 case T_OBJECT:
3092 case T_ARRAY:
3093 if (UseCompressedOops) {
3094 xchg = &MacroAssembler::atomic_xchgalw;
3095 add = &MacroAssembler::atomic_addalw;
3096 } else {
3097 xchg = &MacroAssembler::atomic_xchgal;
3098 add = &MacroAssembler::atomic_addal;
3099 }
3100 break;
3101 default:
3102 ShouldNotReachHere();
3103 xchg = &MacroAssembler::atomic_xchgal;
3104 add = &MacroAssembler::atomic_addal; // unreachable
3105 }
3106
3107 switch (code) {
3108 case lir_xadd:
3109 {
3110 RegisterOrConstant inc;
3111 Register tmp = as_reg(tmp_op);
3112 Register dst = as_reg(dest);
3113 if (data->is_constant()) {
3114 inc = RegisterOrConstant(as_long(data));
3115 assert_different_registers(dst, addr.base(), tmp,
3116 rscratch1, rscratch2);
3117 } else {
3118 inc = RegisterOrConstant(as_reg(data));
3119 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3120 rscratch1, rscratch2);
3121 }
3122 __ lea(tmp, addr);
3123 (_masm->*add)(dst, inc, tmp);
3124 break;
3125 }
3126 case lir_xchg:
3127 {
3128 Register tmp = tmp_op->as_register();
3129 Register obj = as_reg(data);
3130 Register dst = as_reg(dest);
3131 if (is_oop && UseCompressedOops) {
3132 __ encode_heap_oop(rscratch2, obj);
3133 obj = rscratch2;
3134 }
3135 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3136 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3137 __ lea(tmp, addr);
3138 (_masm->*xchg)(dst, obj, tmp);
3139 if (is_oop && UseCompressedOops) {
3140 __ decode_heap_oop(dst);
3141 }
3142 }
3143 break;
3144 default:
3145 ShouldNotReachHere();
3146 }
3147 if(!UseLSE) {
3148 __ membar(__ AnyAny);
3149 }
3150 }
3151
3152 #undef __