1 /*
2 * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "ci/ciUtilities.hpp"
38 #include "code/SCCache.hpp"
39 #include "code/compiledIC.hpp"
40 #include "gc/shared/collectedHeap.hpp"
41 #include "gc/shared/gc_globals.hpp"
42 #include "nativeInst_aarch64.hpp"
43 #include "oops/objArrayKlass.hpp"
44 #include "runtime/frame.inline.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/stubRoutines.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_aarch64.inline.hpp"
49
50
51 #ifndef PRODUCT
52 #define COMMENT(x) do { __ block_comment(x); } while (0)
53 #else
54 #define COMMENT(x)
55 #endif
56
57 NEEDS_CLEANUP // remove this definitions ?
58 const Register SYNC_header = r0; // synchronization header
59 const Register SHIFT_count = r0; // where count for shift operations must be
60
61 #define __ _masm->
62
63
64 static void select_different_registers(Register preserve,
65 Register extra,
66 Register &tmp1,
67 Register &tmp2) {
68 if (tmp1 == preserve) {
69 assert_different_registers(tmp1, tmp2, extra);
70 tmp1 = extra;
71 } else if (tmp2 == preserve) {
72 assert_different_registers(tmp1, tmp2, extra);
73 tmp2 = extra;
74 }
75 assert_different_registers(preserve, tmp1, tmp2);
76 }
77
78
79
80 static void select_different_registers(Register preserve,
81 Register extra,
82 Register &tmp1,
83 Register &tmp2,
84 Register &tmp3) {
85 if (tmp1 == preserve) {
86 assert_different_registers(tmp1, tmp2, tmp3, extra);
87 tmp1 = extra;
88 } else if (tmp2 == preserve) {
89 assert_different_registers(tmp1, tmp2, tmp3, extra);
90 tmp2 = extra;
91 } else if (tmp3 == preserve) {
92 assert_different_registers(tmp1, tmp2, tmp3, extra);
93 tmp3 = extra;
94 }
95 assert_different_registers(preserve, tmp1, tmp2, tmp3);
96 }
97
98
99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
100
101
102 LIR_Opr LIR_Assembler::receiverOpr() {
103 return FrameMap::receiver_opr;
104 }
105
106 LIR_Opr LIR_Assembler::osrBufferPointer() {
107 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
108 }
109
110 //--------------fpu register translations-----------------------
111
112
113 address LIR_Assembler::float_constant(float f) {
114 address const_addr = __ float_constant(f);
115 if (const_addr == nullptr) {
116 bailout("const section overflow");
117 return __ code()->consts()->start();
118 } else {
119 return const_addr;
120 }
121 }
122
123
124 address LIR_Assembler::double_constant(double d) {
125 address const_addr = __ double_constant(d);
126 if (const_addr == nullptr) {
127 bailout("const section overflow");
128 return __ code()->consts()->start();
129 } else {
130 return const_addr;
131 }
132 }
133
134 address LIR_Assembler::int_constant(jlong n) {
135 address const_addr = __ long_constant(n);
136 if (const_addr == nullptr) {
137 bailout("const section overflow");
138 return __ code()->consts()->start();
139 } else {
140 return const_addr;
141 }
142 }
143
144 void LIR_Assembler::breakpoint() { Unimplemented(); }
145
146 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
147
148 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
149
150 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
151 //-------------------------------------------
152
153 static Register as_reg(LIR_Opr op) {
154 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
155 }
156
157 static jlong as_long(LIR_Opr data) {
158 jlong result;
159 switch (data->type()) {
160 case T_INT:
161 result = (data->as_jint());
162 break;
163 case T_LONG:
164 result = (data->as_jlong());
165 break;
166 default:
167 ShouldNotReachHere();
168 result = 0; // unreachable
169 }
170 return result;
171 }
172
173 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
174 Register base = addr->base()->as_pointer_register();
175 LIR_Opr opr = addr->index();
176 if (opr->is_cpu_register()) {
177 Register index;
178 if (opr->is_single_cpu())
179 index = opr->as_register();
180 else
181 index = opr->as_register_lo();
182 assert(addr->disp() == 0, "must be");
183 switch(opr->type()) {
184 case T_INT:
185 return Address(base, index, Address::sxtw(addr->scale()));
186 case T_LONG:
187 return Address(base, index, Address::lsl(addr->scale()));
188 default:
189 ShouldNotReachHere();
190 }
191 } else {
192 assert(addr->scale() == 0,
193 "expected for immediate operand, was: %d", addr->scale());
194 ptrdiff_t offset = ptrdiff_t(addr->disp());
195 // NOTE: Does not handle any 16 byte vector access.
196 const uint type_size = type2aelembytes(addr->type(), true);
197 return __ legitimize_address(Address(base, offset), type_size, tmp);
198 }
199 return Address();
200 }
201
202 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
203 ShouldNotReachHere();
204 return Address();
205 }
206
207 Address LIR_Assembler::as_Address(LIR_Address* addr) {
208 return as_Address(addr, rscratch1);
209 }
210
211 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
212 return as_Address(addr, rscratch1); // Ouch
213 // FIXME: This needs to be much more clever. See x86.
214 }
215
216 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
217 // not encodable as a base + (immediate) offset, generate an explicit address
218 // calculation to hold the address in a temporary register.
219 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
220 precond(size == 4 || size == 8);
221 Address addr = frame_map()->address_for_slot(index, adjust);
222 precond(addr.getMode() == Address::base_plus_offset);
223 precond(addr.base() == sp);
224 precond(addr.offset() > 0);
225 uint mask = size - 1;
226 assert((addr.offset() & mask) == 0, "scaled offsets only");
227 return __ legitimize_address(addr, size, tmp);
228 }
229
230 void LIR_Assembler::osr_entry() {
231 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
232 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
233 ValueStack* entry_state = osr_entry->state();
234 int number_of_locks = entry_state->locks_size();
235
236 // we jump here if osr happens with the interpreter
237 // state set up to continue at the beginning of the
238 // loop that triggered osr - in particular, we have
239 // the following registers setup:
240 //
241 // r2: osr buffer
242 //
243
244 // build frame
245 ciMethod* m = compilation()->method();
246 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
247
248 // OSR buffer is
249 //
250 // locals[nlocals-1..0]
251 // monitors[0..number_of_locks]
252 //
253 // locals is a direct copy of the interpreter frame so in the osr buffer
254 // so first slot in the local array is the last local from the interpreter
255 // and last slot is local[0] (receiver) from the interpreter
256 //
257 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
258 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
259 // in the interpreter frame (the method lock if a sync method)
260
261 // Initialize monitors in the compiled activation.
262 // r2: pointer to osr buffer
263 //
264 // All other registers are dead at this point and the locals will be
265 // copied into place by code emitted in the IR.
266
267 Register OSR_buf = osrBufferPointer()->as_pointer_register();
268 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
269 int monitor_offset = BytesPerWord * method()->max_locals() +
270 (2 * BytesPerWord) * (number_of_locks - 1);
271 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
272 // the OSR buffer using 2 word entries: first the lock and then
273 // the oop.
274 for (int i = 0; i < number_of_locks; i++) {
275 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
276 #ifdef ASSERT
277 // verify the interpreter's monitor has a non-null object
278 {
279 Label L;
280 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
281 __ cbnz(rscratch1, L);
282 __ stop("locked object is null");
283 __ bind(L);
284 }
285 #endif
286 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
287 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
288 __ str(r19, frame_map()->address_for_monitor_lock(i));
289 __ str(r20, frame_map()->address_for_monitor_object(i));
290 }
291 }
292 }
293
294
295 // inline cache check; done before the frame is built.
296 int LIR_Assembler::check_icache() {
297 return __ ic_check(CodeEntryAlignment);
298 }
299
300 void LIR_Assembler::clinit_barrier(ciMethod* method) {
301 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
302 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
303
304 Label L_skip_barrier;
305
306 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
307 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
308 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
309 __ bind(L_skip_barrier);
310 }
311
312 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
313 if (o == nullptr) {
314 __ mov(reg, zr);
315 } else {
316 __ movoop(reg, o);
317 }
318 }
319
320 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
321 address target = nullptr;
322 relocInfo::relocType reloc_type = relocInfo::none;
323
324 switch (patching_id(info)) {
325 case PatchingStub::access_field_id:
326 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
327 reloc_type = relocInfo::section_word_type;
328 break;
329 case PatchingStub::load_klass_id:
330 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
331 reloc_type = relocInfo::metadata_type;
332 break;
333 case PatchingStub::load_mirror_id:
334 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
335 reloc_type = relocInfo::oop_type;
336 break;
337 case PatchingStub::load_appendix_id:
338 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
339 reloc_type = relocInfo::oop_type;
340 break;
341 default: ShouldNotReachHere();
342 }
343
344 __ far_call(RuntimeAddress(target));
345 add_call_info_here(info);
346 }
347
348 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
349 deoptimize_trap(info);
350 }
351
352
353 // This specifies the rsp decrement needed to build the frame
354 int LIR_Assembler::initial_frame_size_in_bytes() const {
355 // if rounding, must let FrameMap know!
356
357 return in_bytes(frame_map()->framesize_in_bytes());
358 }
359
360
361 int LIR_Assembler::emit_exception_handler() {
362 // generate code for exception handler
363 address handler_base = __ start_a_stub(exception_handler_size());
364 if (handler_base == nullptr) {
365 // not enough space left for the handler
366 bailout("exception handler overflow");
367 return -1;
368 }
369
370 int offset = code_offset();
371
372 // the exception oop and pc are in r0, and r3
373 // no other registers need to be preserved, so invalidate them
374 __ invalidate_registers(false, true, true, false, true, true);
375
376 // check that there is really an exception
377 __ verify_not_null_oop(r0);
378
379 // search an exception handler (r0: exception oop, r3: throwing pc)
380 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
381 __ should_not_reach_here();
382 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
383 __ end_a_stub();
384
385 return offset;
386 }
387
388
389 // Emit the code to remove the frame from the stack in the exception
390 // unwind path.
391 int LIR_Assembler::emit_unwind_handler() {
392 #ifndef PRODUCT
393 if (CommentedAssembly) {
394 _masm->block_comment("Unwind handler");
395 }
396 #endif
397
398 int offset = code_offset();
399
400 // Fetch the exception from TLS and clear out exception related thread state
401 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
402 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
403 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
404
405 __ bind(_unwind_handler_entry);
406 __ verify_not_null_oop(r0);
407 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
408 __ mov(r19, r0); // Preserve the exception
409 }
410
411 // Perform needed unlocking
412 MonitorExitStub* stub = nullptr;
413 if (method()->is_synchronized()) {
414 monitor_address(0, FrameMap::r0_opr);
415 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
416 if (LockingMode == LM_MONITOR) {
417 __ b(*stub->entry());
418 } else {
419 __ unlock_object(r5, r4, r0, r6, *stub->entry());
420 }
421 __ bind(*stub->continuation());
422 }
423
424 if (compilation()->env()->dtrace_method_probes()) {
425 __ mov(c_rarg0, rthread);
426 __ mov_metadata(c_rarg1, method()->constant_encoding());
427 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
428 }
429
430 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
431 __ mov(r0, r19); // Restore the exception
432 }
433
434 // remove the activation and dispatch to the unwind handler
435 __ block_comment("remove_frame and dispatch to the unwind handler");
436 __ remove_frame(initial_frame_size_in_bytes());
437 __ far_jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
438
439 // Emit the slow path assembly
440 if (stub != nullptr) {
441 stub->emit_code(this);
442 }
443
444 return offset;
445 }
446
447
448 int LIR_Assembler::emit_deopt_handler() {
449 // generate code for exception handler
450 address handler_base = __ start_a_stub(deopt_handler_size());
451 if (handler_base == nullptr) {
452 // not enough space left for the handler
453 bailout("deopt handler overflow");
454 return -1;
455 }
456
457 int offset = code_offset();
458
459 __ adr(lr, pc());
460 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
461 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
462 __ end_a_stub();
463
464 return offset;
465 }
466
467 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
468 _masm->code_section()->relocate(adr, relocInfo::poll_type);
469 int pc_offset = code_offset();
470 flush_debug_info(pc_offset);
471 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
472 if (info->exception_handlers() != nullptr) {
473 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
474 }
475 }
476
477 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
478 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
479
480 // Pop the stack before the safepoint code
481 __ remove_frame(initial_frame_size_in_bytes());
482
483 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
484 __ reserved_stack_check();
485 }
486
487 code_stub->set_safepoint_offset(__ offset());
488 __ relocate(relocInfo::poll_return_type);
489 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
490 __ ret(lr);
491 }
492
493 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
494 guarantee(info != nullptr, "Shouldn't be null");
495 __ get_polling_page(rscratch1, relocInfo::poll_type);
496 add_debug_info_for_branch(info); // This isn't just debug info:
497 // it's the oop map
498 __ read_polling_page(rscratch1, relocInfo::poll_type);
499 return __ offset();
500 }
501
502
503 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
504 if (from_reg == r31_sp)
505 from_reg = sp;
506 if (to_reg == r31_sp)
507 to_reg = sp;
508 __ mov(to_reg, from_reg);
509 }
510
511 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
512
513
514 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
515 assert(src->is_constant(), "should not call otherwise");
516 assert(dest->is_register(), "should not call otherwise");
517 LIR_Const* c = src->as_constant_ptr();
518
519 switch (c->type()) {
520 case T_INT: {
521 assert(patch_code == lir_patch_none, "no patching handled here");
522 __ movw(dest->as_register(), c->as_jint());
523 break;
524 }
525
526 case T_ADDRESS: {
527 assert(patch_code == lir_patch_none, "no patching handled here");
528 __ mov(dest->as_register(), c->as_jint());
529 break;
530 }
531
532 case T_LONG: {
533 assert(patch_code == lir_patch_none, "no patching handled here");
534 if (SCCache::is_on_for_write()) {
535 // SCA needs relocation info for card table base
536 address b = c->as_pointer();
537 if (is_card_table_address(b)) {
538 __ lea(dest->as_register_lo(), ExternalAddress(b));
539 break;
540 }
541 if (AOTRuntimeConstants::contains(b)) {
542 __ load_aotrc_address(dest->as_register_lo(), b);
543 break;
544 }
545 }
546 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
547 break;
548 }
549
550 case T_OBJECT: {
551 if (patch_code == lir_patch_none) {
552 jobject2reg(c->as_jobject(), dest->as_register());
553 } else {
554 jobject2reg_with_patching(dest->as_register(), info);
555 }
556 break;
557 }
558
559 case T_METADATA: {
560 if (patch_code != lir_patch_none) {
561 klass2reg_with_patching(dest->as_register(), info);
562 } else {
563 __ mov_metadata(dest->as_register(), c->as_metadata());
564 }
565 break;
566 }
567
568 case T_FLOAT: {
569 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
570 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
571 } else {
572 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
573 __ ldrs(dest->as_float_reg(), Address(rscratch1));
574 }
575 break;
576 }
577
578 case T_DOUBLE: {
579 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
580 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
581 } else {
582 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
583 __ ldrd(dest->as_double_reg(), Address(rscratch1));
584 }
585 break;
586 }
587
588 default:
589 ShouldNotReachHere();
590 }
591 }
592
593 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
594 LIR_Const* c = src->as_constant_ptr();
595 switch (c->type()) {
596 case T_OBJECT:
597 {
598 if (! c->as_jobject())
599 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
600 else {
601 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
602 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
603 }
604 }
605 break;
606 case T_ADDRESS:
607 {
608 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
609 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
610 }
611 case T_INT:
612 case T_FLOAT:
613 {
614 Register reg = zr;
615 if (c->as_jint_bits() == 0)
616 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
617 else {
618 __ movw(rscratch1, c->as_jint_bits());
619 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
620 }
621 }
622 break;
623 case T_LONG:
624 case T_DOUBLE:
625 {
626 Register reg = zr;
627 if (c->as_jlong_bits() == 0)
628 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
629 lo_word_offset_in_bytes));
630 else {
631 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
632 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
633 lo_word_offset_in_bytes));
634 }
635 }
636 break;
637 default:
638 ShouldNotReachHere();
639 }
640 }
641
642 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
643 assert(src->is_constant(), "should not call otherwise");
644 LIR_Const* c = src->as_constant_ptr();
645 LIR_Address* to_addr = dest->as_address_ptr();
646
647 void (Assembler::* insn)(Register Rt, const Address &adr);
648
649 switch (type) {
650 case T_ADDRESS:
651 assert(c->as_jint() == 0, "should be");
652 insn = &Assembler::str;
653 break;
654 case T_LONG:
655 assert(c->as_jlong() == 0, "should be");
656 insn = &Assembler::str;
657 break;
658 case T_INT:
659 assert(c->as_jint() == 0, "should be");
660 insn = &Assembler::strw;
661 break;
662 case T_OBJECT:
663 case T_ARRAY:
664 assert(c->as_jobject() == nullptr, "should be");
665 if (UseCompressedOops && !wide) {
666 insn = &Assembler::strw;
667 } else {
668 insn = &Assembler::str;
669 }
670 break;
671 case T_CHAR:
672 case T_SHORT:
673 assert(c->as_jint() == 0, "should be");
674 insn = &Assembler::strh;
675 break;
676 case T_BOOLEAN:
677 case T_BYTE:
678 assert(c->as_jint() == 0, "should be");
679 insn = &Assembler::strb;
680 break;
681 default:
682 ShouldNotReachHere();
683 insn = &Assembler::str; // unreachable
684 }
685
686 if (info) add_debug_info_for_null_check_here(info);
687 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
688 }
689
690 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
691 assert(src->is_register(), "should not call otherwise");
692 assert(dest->is_register(), "should not call otherwise");
693
694 // move between cpu-registers
695 if (dest->is_single_cpu()) {
696 if (src->type() == T_LONG) {
697 // Can do LONG -> OBJECT
698 move_regs(src->as_register_lo(), dest->as_register());
699 return;
700 }
701 assert(src->is_single_cpu(), "must match");
702 if (src->type() == T_OBJECT) {
703 __ verify_oop(src->as_register());
704 }
705 move_regs(src->as_register(), dest->as_register());
706
707 } else if (dest->is_double_cpu()) {
708 if (is_reference_type(src->type())) {
709 // Surprising to me but we can see move of a long to t_object
710 __ verify_oop(src->as_register());
711 move_regs(src->as_register(), dest->as_register_lo());
712 return;
713 }
714 assert(src->is_double_cpu(), "must match");
715 Register f_lo = src->as_register_lo();
716 Register f_hi = src->as_register_hi();
717 Register t_lo = dest->as_register_lo();
718 Register t_hi = dest->as_register_hi();
719 assert(f_hi == f_lo, "must be same");
720 assert(t_hi == t_lo, "must be same");
721 move_regs(f_lo, t_lo);
722
723 } else if (dest->is_single_fpu()) {
724 __ fmovs(dest->as_float_reg(), src->as_float_reg());
725
726 } else if (dest->is_double_fpu()) {
727 __ fmovd(dest->as_double_reg(), src->as_double_reg());
728
729 } else {
730 ShouldNotReachHere();
731 }
732 }
733
734 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
735 precond(src->is_register() && dest->is_stack());
736
737 uint const c_sz32 = sizeof(uint32_t);
738 uint const c_sz64 = sizeof(uint64_t);
739
740 if (src->is_single_cpu()) {
741 int index = dest->single_stack_ix();
742 if (is_reference_type(type)) {
743 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
744 __ verify_oop(src->as_register());
745 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
746 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
747 } else {
748 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
749 }
750
751 } else if (src->is_double_cpu()) {
752 int index = dest->double_stack_ix();
753 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
754 __ str(src->as_register_lo(), dest_addr_LO);
755
756 } else if (src->is_single_fpu()) {
757 int index = dest->single_stack_ix();
758 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
759
760 } else if (src->is_double_fpu()) {
761 int index = dest->double_stack_ix();
762 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
763
764 } else {
765 ShouldNotReachHere();
766 }
767 }
768
769
770 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
771 LIR_Address* to_addr = dest->as_address_ptr();
772 PatchingStub* patch = nullptr;
773 Register compressed_src = rscratch1;
774
775 if (patch_code != lir_patch_none) {
776 deoptimize_trap(info);
777 return;
778 }
779
780 if (is_reference_type(type)) {
781 __ verify_oop(src->as_register());
782
783 if (UseCompressedOops && !wide) {
784 __ encode_heap_oop(compressed_src, src->as_register());
785 } else {
786 compressed_src = src->as_register();
787 }
788 }
789
790 int null_check_here = code_offset();
791 switch (type) {
792 case T_FLOAT: {
793 __ strs(src->as_float_reg(), as_Address(to_addr));
794 break;
795 }
796
797 case T_DOUBLE: {
798 __ strd(src->as_double_reg(), as_Address(to_addr));
799 break;
800 }
801
802 case T_ARRAY: // fall through
803 case T_OBJECT: // fall through
804 if (UseCompressedOops && !wide) {
805 __ strw(compressed_src, as_Address(to_addr, rscratch2));
806 } else {
807 __ str(compressed_src, as_Address(to_addr));
808 }
809 break;
810 case T_METADATA:
811 // We get here to store a method pointer to the stack to pass to
812 // a dtrace runtime call. This can't work on 64 bit with
813 // compressed klass ptrs: T_METADATA can be a compressed klass
814 // ptr or a 64 bit method pointer.
815 ShouldNotReachHere();
816 __ str(src->as_register(), as_Address(to_addr));
817 break;
818 case T_ADDRESS:
819 __ str(src->as_register(), as_Address(to_addr));
820 break;
821 case T_INT:
822 __ strw(src->as_register(), as_Address(to_addr));
823 break;
824
825 case T_LONG: {
826 __ str(src->as_register_lo(), as_Address_lo(to_addr));
827 break;
828 }
829
830 case T_BYTE: // fall through
831 case T_BOOLEAN: {
832 __ strb(src->as_register(), as_Address(to_addr));
833 break;
834 }
835
836 case T_CHAR: // fall through
837 case T_SHORT:
838 __ strh(src->as_register(), as_Address(to_addr));
839 break;
840
841 default:
842 ShouldNotReachHere();
843 }
844 if (info != nullptr) {
845 add_debug_info_for_null_check(null_check_here, info);
846 }
847 }
848
849
850 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
851 precond(src->is_stack() && dest->is_register());
852
853 uint const c_sz32 = sizeof(uint32_t);
854 uint const c_sz64 = sizeof(uint64_t);
855
856 if (dest->is_single_cpu()) {
857 int index = src->single_stack_ix();
858 if (is_reference_type(type)) {
859 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
860 __ verify_oop(dest->as_register());
861 } else if (type == T_METADATA || type == T_ADDRESS) {
862 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
863 } else {
864 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
865 }
866
867 } else if (dest->is_double_cpu()) {
868 int index = src->double_stack_ix();
869 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
870 __ ldr(dest->as_register_lo(), src_addr_LO);
871
872 } else if (dest->is_single_fpu()) {
873 int index = src->single_stack_ix();
874 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
875
876 } else if (dest->is_double_fpu()) {
877 int index = src->double_stack_ix();
878 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
879
880 } else {
881 ShouldNotReachHere();
882 }
883 }
884
885
886 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
887 address target = nullptr;
888 relocInfo::relocType reloc_type = relocInfo::none;
889
890 switch (patching_id(info)) {
891 case PatchingStub::access_field_id:
892 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
893 reloc_type = relocInfo::section_word_type;
894 break;
895 case PatchingStub::load_klass_id:
896 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
897 reloc_type = relocInfo::metadata_type;
898 break;
899 case PatchingStub::load_mirror_id:
900 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
901 reloc_type = relocInfo::oop_type;
902 break;
903 case PatchingStub::load_appendix_id:
904 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
905 reloc_type = relocInfo::oop_type;
906 break;
907 default: ShouldNotReachHere();
908 }
909
910 __ far_call(RuntimeAddress(target));
911 add_call_info_here(info);
912 }
913
914 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
915
916 LIR_Opr temp;
917 if (type == T_LONG || type == T_DOUBLE)
918 temp = FrameMap::rscratch1_long_opr;
919 else
920 temp = FrameMap::rscratch1_opr;
921
922 stack2reg(src, temp, src->type());
923 reg2stack(temp, dest, dest->type(), false);
924 }
925
926
927 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
928 LIR_Address* addr = src->as_address_ptr();
929 LIR_Address* from_addr = src->as_address_ptr();
930
931 if (addr->base()->type() == T_OBJECT) {
932 __ verify_oop(addr->base()->as_pointer_register());
933 }
934
935 if (patch_code != lir_patch_none) {
936 deoptimize_trap(info);
937 return;
938 }
939
940 if (info != nullptr) {
941 add_debug_info_for_null_check_here(info);
942 }
943 int null_check_here = code_offset();
944 switch (type) {
945 case T_FLOAT: {
946 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
947 break;
948 }
949
950 case T_DOUBLE: {
951 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
952 break;
953 }
954
955 case T_ARRAY: // fall through
956 case T_OBJECT: // fall through
957 if (UseCompressedOops && !wide) {
958 __ ldrw(dest->as_register(), as_Address(from_addr));
959 } else {
960 __ ldr(dest->as_register(), as_Address(from_addr));
961 }
962 break;
963 case T_METADATA:
964 // We get here to store a method pointer to the stack to pass to
965 // a dtrace runtime call. This can't work on 64 bit with
966 // compressed klass ptrs: T_METADATA can be a compressed klass
967 // ptr or a 64 bit method pointer.
968 ShouldNotReachHere();
969 __ ldr(dest->as_register(), as_Address(from_addr));
970 break;
971 case T_ADDRESS:
972 __ ldr(dest->as_register(), as_Address(from_addr));
973 break;
974 case T_INT:
975 __ ldrw(dest->as_register(), as_Address(from_addr));
976 break;
977
978 case T_LONG: {
979 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
980 break;
981 }
982
983 case T_BYTE:
984 __ ldrsb(dest->as_register(), as_Address(from_addr));
985 break;
986 case T_BOOLEAN: {
987 __ ldrb(dest->as_register(), as_Address(from_addr));
988 break;
989 }
990
991 case T_CHAR:
992 __ ldrh(dest->as_register(), as_Address(from_addr));
993 break;
994 case T_SHORT:
995 __ ldrsh(dest->as_register(), as_Address(from_addr));
996 break;
997
998 default:
999 ShouldNotReachHere();
1000 }
1001
1002 if (is_reference_type(type)) {
1003 if (UseCompressedOops && !wide) {
1004 __ decode_heap_oop(dest->as_register());
1005 }
1006
1007 __ verify_oop(dest->as_register());
1008 }
1009 }
1010
1011
1012 int LIR_Assembler::array_element_size(BasicType type) const {
1013 int elem_size = type2aelembytes(type);
1014 return exact_log2(elem_size);
1015 }
1016
1017
1018 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1019 switch (op->code()) {
1020 case lir_idiv:
1021 case lir_irem:
1022 arithmetic_idiv(op->code(),
1023 op->in_opr1(),
1024 op->in_opr2(),
1025 op->in_opr3(),
1026 op->result_opr(),
1027 op->info());
1028 break;
1029 case lir_fmad:
1030 __ fmaddd(op->result_opr()->as_double_reg(),
1031 op->in_opr1()->as_double_reg(),
1032 op->in_opr2()->as_double_reg(),
1033 op->in_opr3()->as_double_reg());
1034 break;
1035 case lir_fmaf:
1036 __ fmadds(op->result_opr()->as_float_reg(),
1037 op->in_opr1()->as_float_reg(),
1038 op->in_opr2()->as_float_reg(),
1039 op->in_opr3()->as_float_reg());
1040 break;
1041 default: ShouldNotReachHere(); break;
1042 }
1043 }
1044
1045 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1046 #ifdef ASSERT
1047 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1048 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1049 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1050 #endif
1051
1052 if (op->cond() == lir_cond_always) {
1053 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1054 __ b(*(op->label()));
1055 } else {
1056 Assembler::Condition acond;
1057 if (op->code() == lir_cond_float_branch) {
1058 bool is_unordered = (op->ublock() == op->block());
1059 // Assembler::EQ does not permit unordered branches, so we add
1060 // another branch here. Likewise, Assembler::NE does not permit
1061 // ordered branches.
1062 if ((is_unordered && op->cond() == lir_cond_equal)
1063 || (!is_unordered && op->cond() == lir_cond_notEqual))
1064 __ br(Assembler::VS, *(op->ublock()->label()));
1065 switch(op->cond()) {
1066 case lir_cond_equal: acond = Assembler::EQ; break;
1067 case lir_cond_notEqual: acond = Assembler::NE; break;
1068 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1069 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1070 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1071 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1072 default: ShouldNotReachHere();
1073 acond = Assembler::EQ; // unreachable
1074 }
1075 } else {
1076 switch (op->cond()) {
1077 case lir_cond_equal: acond = Assembler::EQ; break;
1078 case lir_cond_notEqual: acond = Assembler::NE; break;
1079 case lir_cond_less: acond = Assembler::LT; break;
1080 case lir_cond_lessEqual: acond = Assembler::LE; break;
1081 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1082 case lir_cond_greater: acond = Assembler::GT; break;
1083 case lir_cond_belowEqual: acond = Assembler::LS; break;
1084 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1085 default: ShouldNotReachHere();
1086 acond = Assembler::EQ; // unreachable
1087 }
1088 }
1089 __ br(acond,*(op->label()));
1090 }
1091 }
1092
1093
1094
1095 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1096 LIR_Opr src = op->in_opr();
1097 LIR_Opr dest = op->result_opr();
1098
1099 switch (op->bytecode()) {
1100 case Bytecodes::_i2f:
1101 {
1102 __ scvtfws(dest->as_float_reg(), src->as_register());
1103 break;
1104 }
1105 case Bytecodes::_i2d:
1106 {
1107 __ scvtfwd(dest->as_double_reg(), src->as_register());
1108 break;
1109 }
1110 case Bytecodes::_l2d:
1111 {
1112 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1113 break;
1114 }
1115 case Bytecodes::_l2f:
1116 {
1117 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1118 break;
1119 }
1120 case Bytecodes::_f2d:
1121 {
1122 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1123 break;
1124 }
1125 case Bytecodes::_d2f:
1126 {
1127 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1128 break;
1129 }
1130 case Bytecodes::_i2c:
1131 {
1132 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1133 break;
1134 }
1135 case Bytecodes::_i2l:
1136 {
1137 __ sxtw(dest->as_register_lo(), src->as_register());
1138 break;
1139 }
1140 case Bytecodes::_i2s:
1141 {
1142 __ sxth(dest->as_register(), src->as_register());
1143 break;
1144 }
1145 case Bytecodes::_i2b:
1146 {
1147 __ sxtb(dest->as_register(), src->as_register());
1148 break;
1149 }
1150 case Bytecodes::_l2i:
1151 {
1152 _masm->block_comment("FIXME: This could be a no-op");
1153 __ uxtw(dest->as_register(), src->as_register_lo());
1154 break;
1155 }
1156 case Bytecodes::_d2l:
1157 {
1158 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1159 break;
1160 }
1161 case Bytecodes::_f2i:
1162 {
1163 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1164 break;
1165 }
1166 case Bytecodes::_f2l:
1167 {
1168 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1169 break;
1170 }
1171 case Bytecodes::_d2i:
1172 {
1173 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1174 break;
1175 }
1176 default: ShouldNotReachHere();
1177 }
1178 }
1179
1180 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1181 if (op->init_check()) {
1182 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1183 __ ldarb(rscratch1, rscratch1);
1184 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1185 add_debug_info_for_null_check_here(op->stub()->info());
1186 __ br(Assembler::NE, *op->stub()->entry());
1187 }
1188 __ allocate_object(op->obj()->as_register(),
1189 op->tmp1()->as_register(),
1190 op->tmp2()->as_register(),
1191 op->header_size(),
1192 op->object_size(),
1193 op->klass()->as_register(),
1194 *op->stub()->entry());
1195 __ bind(*op->stub()->continuation());
1196 }
1197
1198 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1199 Register len = op->len()->as_register();
1200 __ uxtw(len, len);
1201
1202 if (UseSlowPath ||
1203 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1204 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1205 __ b(*op->stub()->entry());
1206 } else {
1207 Register tmp1 = op->tmp1()->as_register();
1208 Register tmp2 = op->tmp2()->as_register();
1209 Register tmp3 = op->tmp3()->as_register();
1210 if (len == tmp1) {
1211 tmp1 = tmp3;
1212 } else if (len == tmp2) {
1213 tmp2 = tmp3;
1214 } else if (len == tmp3) {
1215 // everything is ok
1216 } else {
1217 __ mov(tmp3, len);
1218 }
1219 __ allocate_array(op->obj()->as_register(),
1220 len,
1221 tmp1,
1222 tmp2,
1223 arrayOopDesc::base_offset_in_bytes(op->type()),
1224 array_element_size(op->type()),
1225 op->klass()->as_register(),
1226 *op->stub()->entry(),
1227 op->zero_array());
1228 }
1229 __ bind(*op->stub()->continuation());
1230 }
1231
1232 void LIR_Assembler::type_profile_helper(Register mdo,
1233 ciMethodData *md, ciProfileData *data,
1234 Register recv, Label* update_done) {
1235 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1236 Label next_test;
1237 // See if the receiver is receiver[n].
1238 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1239 __ ldr(rscratch1, Address(rscratch2));
1240 __ cmp(recv, rscratch1);
1241 __ br(Assembler::NE, next_test);
1242 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1243 __ addptr(data_addr, DataLayout::counter_increment);
1244 __ b(*update_done);
1245 __ bind(next_test);
1246 }
1247
1248 // Didn't find receiver; find next empty slot and fill it in
1249 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1250 Label next_test;
1251 __ lea(rscratch2,
1252 Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1253 Address recv_addr(rscratch2);
1254 __ ldr(rscratch1, recv_addr);
1255 __ cbnz(rscratch1, next_test);
1256 __ str(recv, recv_addr);
1257 __ mov(rscratch1, DataLayout::counter_increment);
1258 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1259 __ str(rscratch1, Address(rscratch2));
1260 __ b(*update_done);
1261 __ bind(next_test);
1262 }
1263 }
1264
1265 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1266 // we always need a stub for the failure case.
1267 CodeStub* stub = op->stub();
1268 Register obj = op->object()->as_register();
1269 Register k_RInfo = op->tmp1()->as_register();
1270 Register klass_RInfo = op->tmp2()->as_register();
1271 Register dst = op->result_opr()->as_register();
1272 ciKlass* k = op->klass();
1273 Register Rtmp1 = noreg;
1274
1275 // check if it needs to be profiled
1276 ciMethodData* md;
1277 ciProfileData* data;
1278
1279 const bool should_profile = op->should_profile();
1280
1281 if (should_profile) {
1282 ciMethod* method = op->profiled_method();
1283 assert(method != nullptr, "Should have method");
1284 int bci = op->profiled_bci();
1285 md = method->method_data_or_null();
1286 assert(md != nullptr, "Sanity");
1287 data = md->bci_to_data(bci);
1288 assert(data != nullptr, "need data for type check");
1289 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1290 }
1291 Label* success_target = success;
1292 Label* failure_target = failure;
1293
1294 if (obj == k_RInfo) {
1295 k_RInfo = dst;
1296 } else if (obj == klass_RInfo) {
1297 klass_RInfo = dst;
1298 }
1299 if (k->is_loaded() && !UseCompressedClassPointers) {
1300 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1301 } else {
1302 Rtmp1 = op->tmp3()->as_register();
1303 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1304 }
1305
1306 assert_different_registers(obj, k_RInfo, klass_RInfo);
1307
1308 if (should_profile) {
1309 Register mdo = klass_RInfo;
1310 __ mov_metadata(mdo, md->constant_encoding());
1311 Label not_null;
1312 __ cbnz(obj, not_null);
1313 // Object is null; update MDO and exit
1314 Address data_addr
1315 = __ form_address(rscratch2, mdo,
1316 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1317 0);
1318 __ ldrb(rscratch1, data_addr);
1319 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1320 __ strb(rscratch1, data_addr);
1321 __ b(*obj_is_null);
1322 __ bind(not_null);
1323
1324 Label update_done;
1325 Register recv = k_RInfo;
1326 __ load_klass(recv, obj);
1327 type_profile_helper(mdo, md, data, recv, &update_done);
1328 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1329 __ addptr(counter_addr, DataLayout::counter_increment);
1330
1331 __ bind(update_done);
1332 } else {
1333 __ cbz(obj, *obj_is_null);
1334 }
1335
1336 if (!k->is_loaded()) {
1337 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1338 } else {
1339 __ mov_metadata(k_RInfo, k->constant_encoding());
1340 }
1341 __ verify_oop(obj);
1342
1343 if (op->fast_check()) {
1344 // get object class
1345 // not a safepoint as obj null check happens earlier
1346 __ load_klass(rscratch1, obj);
1347 __ cmp( rscratch1, k_RInfo);
1348
1349 __ br(Assembler::NE, *failure_target);
1350 // successful cast, fall through to profile or jump
1351 } else {
1352 // get object class
1353 // not a safepoint as obj null check happens earlier
1354 __ load_klass(klass_RInfo, obj);
1355 if (k->is_loaded()) {
1356 // See if we get an immediate positive hit
1357 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1358 __ cmp(k_RInfo, rscratch1);
1359 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1360 __ br(Assembler::NE, *failure_target);
1361 // successful cast, fall through to profile or jump
1362 } else {
1363 // See if we get an immediate positive hit
1364 __ br(Assembler::EQ, *success_target);
1365 // check for self
1366 __ cmp(klass_RInfo, k_RInfo);
1367 __ br(Assembler::EQ, *success_target);
1368
1369 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1370 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1371 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1372 // result is a boolean
1373 __ cbzw(klass_RInfo, *failure_target);
1374 // successful cast, fall through to profile or jump
1375 }
1376 } else {
1377 // perform the fast part of the checking logic
1378 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1379 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1380 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1381 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1382 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1383 // result is a boolean
1384 __ cbz(k_RInfo, *failure_target);
1385 // successful cast, fall through to profile or jump
1386 }
1387 }
1388 __ b(*success);
1389 }
1390
1391
1392 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1393 const bool should_profile = op->should_profile();
1394
1395 LIR_Code code = op->code();
1396 if (code == lir_store_check) {
1397 Register value = op->object()->as_register();
1398 Register array = op->array()->as_register();
1399 Register k_RInfo = op->tmp1()->as_register();
1400 Register klass_RInfo = op->tmp2()->as_register();
1401 Register Rtmp1 = op->tmp3()->as_register();
1402
1403 CodeStub* stub = op->stub();
1404
1405 // check if it needs to be profiled
1406 ciMethodData* md;
1407 ciProfileData* data;
1408
1409 if (should_profile) {
1410 ciMethod* method = op->profiled_method();
1411 assert(method != nullptr, "Should have method");
1412 int bci = op->profiled_bci();
1413 md = method->method_data_or_null();
1414 assert(md != nullptr, "Sanity");
1415 data = md->bci_to_data(bci);
1416 assert(data != nullptr, "need data for type check");
1417 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1418 }
1419 Label done;
1420 Label* success_target = &done;
1421 Label* failure_target = stub->entry();
1422
1423 if (should_profile) {
1424 Label not_null;
1425 Register mdo = klass_RInfo;
1426 __ mov_metadata(mdo, md->constant_encoding());
1427 __ cbnz(value, not_null);
1428 // Object is null; update MDO and exit
1429 Address data_addr
1430 = __ form_address(rscratch2, mdo,
1431 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1432 0);
1433 __ ldrb(rscratch1, data_addr);
1434 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1435 __ strb(rscratch1, data_addr);
1436 __ b(done);
1437 __ bind(not_null);
1438
1439 Label update_done;
1440 Register recv = k_RInfo;
1441 __ load_klass(recv, value);
1442 type_profile_helper(mdo, md, data, recv, &update_done);
1443 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1444 __ addptr(counter_addr, DataLayout::counter_increment);
1445 __ bind(update_done);
1446 } else {
1447 __ cbz(value, done);
1448 }
1449
1450 add_debug_info_for_null_check_here(op->info_for_exception());
1451 __ load_klass(k_RInfo, array);
1452 __ load_klass(klass_RInfo, value);
1453
1454 // get instance klass (it's already uncompressed)
1455 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1456 // perform the fast part of the checking logic
1457 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1458 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1459 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1460 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1461 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1462 // result is a boolean
1463 __ cbzw(k_RInfo, *failure_target);
1464 // fall through to the success case
1465
1466 __ bind(done);
1467 } else if (code == lir_checkcast) {
1468 Register obj = op->object()->as_register();
1469 Register dst = op->result_opr()->as_register();
1470 Label success;
1471 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1472 __ bind(success);
1473 if (dst != obj) {
1474 __ mov(dst, obj);
1475 }
1476 } else if (code == lir_instanceof) {
1477 Register obj = op->object()->as_register();
1478 Register dst = op->result_opr()->as_register();
1479 Label success, failure, done;
1480 emit_typecheck_helper(op, &success, &failure, &failure);
1481 __ bind(failure);
1482 __ mov(dst, zr);
1483 __ b(done);
1484 __ bind(success);
1485 __ mov(dst, 1);
1486 __ bind(done);
1487 } else {
1488 ShouldNotReachHere();
1489 }
1490 }
1491
1492 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1493 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1494 __ cset(rscratch1, Assembler::NE);
1495 __ membar(__ AnyAny);
1496 }
1497
1498 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1499 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1500 __ cset(rscratch1, Assembler::NE);
1501 __ membar(__ AnyAny);
1502 }
1503
1504
1505 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1506 Register addr;
1507 if (op->addr()->is_register()) {
1508 addr = as_reg(op->addr());
1509 } else {
1510 assert(op->addr()->is_address(), "what else?");
1511 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1512 assert(addr_ptr->disp() == 0, "need 0 disp");
1513 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1514 addr = as_reg(addr_ptr->base());
1515 }
1516 Register newval = as_reg(op->new_value());
1517 Register cmpval = as_reg(op->cmp_value());
1518
1519 if (op->code() == lir_cas_obj) {
1520 if (UseCompressedOops) {
1521 Register t1 = op->tmp1()->as_register();
1522 assert(op->tmp1()->is_valid(), "must be");
1523 __ encode_heap_oop(t1, cmpval);
1524 cmpval = t1;
1525 __ encode_heap_oop(rscratch2, newval);
1526 newval = rscratch2;
1527 casw(addr, newval, cmpval);
1528 } else {
1529 casl(addr, newval, cmpval);
1530 }
1531 } else if (op->code() == lir_cas_int) {
1532 casw(addr, newval, cmpval);
1533 } else {
1534 casl(addr, newval, cmpval);
1535 }
1536 }
1537
1538
1539 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1540 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1541 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1542
1543 Assembler::Condition acond, ncond;
1544 switch (condition) {
1545 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1546 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1547 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1548 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1549 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1550 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1551 case lir_cond_belowEqual:
1552 case lir_cond_aboveEqual:
1553 default: ShouldNotReachHere();
1554 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1555 }
1556
1557 assert(result->is_single_cpu() || result->is_double_cpu(),
1558 "expect single register for result");
1559 if (opr1->is_constant() && opr2->is_constant()
1560 && opr1->type() == T_INT && opr2->type() == T_INT) {
1561 jint val1 = opr1->as_jint();
1562 jint val2 = opr2->as_jint();
1563 if (val1 == 0 && val2 == 1) {
1564 __ cset(result->as_register(), ncond);
1565 return;
1566 } else if (val1 == 1 && val2 == 0) {
1567 __ cset(result->as_register(), acond);
1568 return;
1569 }
1570 }
1571
1572 if (opr1->is_constant() && opr2->is_constant()
1573 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1574 jlong val1 = opr1->as_jlong();
1575 jlong val2 = opr2->as_jlong();
1576 if (val1 == 0 && val2 == 1) {
1577 __ cset(result->as_register_lo(), ncond);
1578 return;
1579 } else if (val1 == 1 && val2 == 0) {
1580 __ cset(result->as_register_lo(), acond);
1581 return;
1582 }
1583 }
1584
1585 if (opr1->is_stack()) {
1586 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1587 opr1 = FrameMap::rscratch1_opr;
1588 } else if (opr1->is_constant()) {
1589 LIR_Opr tmp
1590 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1591 const2reg(opr1, tmp, lir_patch_none, nullptr);
1592 opr1 = tmp;
1593 }
1594
1595 if (opr2->is_stack()) {
1596 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1597 opr2 = FrameMap::rscratch2_opr;
1598 } else if (opr2->is_constant()) {
1599 LIR_Opr tmp
1600 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1601 const2reg(opr2, tmp, lir_patch_none, nullptr);
1602 opr2 = tmp;
1603 }
1604
1605 if (result->type() == T_LONG)
1606 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1607 else
1608 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1609 }
1610
1611 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1612 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1613
1614 if (left->is_single_cpu()) {
1615 Register lreg = left->as_register();
1616 Register dreg = as_reg(dest);
1617
1618 if (right->is_single_cpu()) {
1619 // cpu register - cpu register
1620
1621 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1622 "should be");
1623 Register rreg = right->as_register();
1624 switch (code) {
1625 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1626 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1627 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1628 default: ShouldNotReachHere();
1629 }
1630
1631 } else if (right->is_double_cpu()) {
1632 Register rreg = right->as_register_lo();
1633 // single_cpu + double_cpu: can happen with obj+long
1634 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1635 switch (code) {
1636 case lir_add: __ add(dreg, lreg, rreg); break;
1637 case lir_sub: __ sub(dreg, lreg, rreg); break;
1638 default: ShouldNotReachHere();
1639 }
1640 } else if (right->is_constant()) {
1641 // cpu register - constant
1642 jlong c;
1643
1644 // FIXME. This is fugly: we really need to factor all this logic.
1645 switch(right->type()) {
1646 case T_LONG:
1647 c = right->as_constant_ptr()->as_jlong();
1648 break;
1649 case T_INT:
1650 case T_ADDRESS:
1651 c = right->as_constant_ptr()->as_jint();
1652 break;
1653 default:
1654 ShouldNotReachHere();
1655 c = 0; // unreachable
1656 break;
1657 }
1658
1659 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1660 if (c == 0 && dreg == lreg) {
1661 COMMENT("effective nop elided");
1662 return;
1663 }
1664 switch(left->type()) {
1665 case T_INT:
1666 switch (code) {
1667 case lir_add: __ addw(dreg, lreg, c); break;
1668 case lir_sub: __ subw(dreg, lreg, c); break;
1669 default: ShouldNotReachHere();
1670 }
1671 break;
1672 case T_OBJECT:
1673 case T_ADDRESS:
1674 switch (code) {
1675 case lir_add: __ add(dreg, lreg, c); break;
1676 case lir_sub: __ sub(dreg, lreg, c); break;
1677 default: ShouldNotReachHere();
1678 }
1679 break;
1680 default:
1681 ShouldNotReachHere();
1682 }
1683 } else {
1684 ShouldNotReachHere();
1685 }
1686
1687 } else if (left->is_double_cpu()) {
1688 Register lreg_lo = left->as_register_lo();
1689
1690 if (right->is_double_cpu()) {
1691 // cpu register - cpu register
1692 Register rreg_lo = right->as_register_lo();
1693 switch (code) {
1694 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1695 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1696 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1697 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1698 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1699 default:
1700 ShouldNotReachHere();
1701 }
1702
1703 } else if (right->is_constant()) {
1704 jlong c = right->as_constant_ptr()->as_jlong();
1705 Register dreg = as_reg(dest);
1706 switch (code) {
1707 case lir_add:
1708 case lir_sub:
1709 if (c == 0 && dreg == lreg_lo) {
1710 COMMENT("effective nop elided");
1711 return;
1712 }
1713 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1714 break;
1715 case lir_div:
1716 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1717 if (c == 1) {
1718 // move lreg_lo to dreg if divisor is 1
1719 __ mov(dreg, lreg_lo);
1720 } else {
1721 unsigned int shift = log2i_exact(c);
1722 // use rscratch1 as intermediate result register
1723 __ asr(rscratch1, lreg_lo, 63);
1724 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1725 __ asr(dreg, rscratch1, shift);
1726 }
1727 break;
1728 case lir_rem:
1729 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1730 if (c == 1) {
1731 // move 0 to dreg if divisor is 1
1732 __ mov(dreg, zr);
1733 } else {
1734 // use rscratch1 as intermediate result register
1735 __ negs(rscratch1, lreg_lo);
1736 __ andr(dreg, lreg_lo, c - 1);
1737 __ andr(rscratch1, rscratch1, c - 1);
1738 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1739 }
1740 break;
1741 default:
1742 ShouldNotReachHere();
1743 }
1744 } else {
1745 ShouldNotReachHere();
1746 }
1747 } else if (left->is_single_fpu()) {
1748 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1749 switch (code) {
1750 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1751 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1752 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1753 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1754 default:
1755 ShouldNotReachHere();
1756 }
1757 } else if (left->is_double_fpu()) {
1758 if (right->is_double_fpu()) {
1759 // fpu register - fpu register
1760 switch (code) {
1761 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1762 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1763 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1764 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1765 default:
1766 ShouldNotReachHere();
1767 }
1768 } else {
1769 if (right->is_constant()) {
1770 ShouldNotReachHere();
1771 }
1772 ShouldNotReachHere();
1773 }
1774 } else if (left->is_single_stack() || left->is_address()) {
1775 assert(left == dest, "left and dest must be equal");
1776 ShouldNotReachHere();
1777 } else {
1778 ShouldNotReachHere();
1779 }
1780 }
1781
1782 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1783
1784
1785 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1786 switch(code) {
1787 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1788 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1789 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1790 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1791 default : ShouldNotReachHere();
1792 }
1793 }
1794
1795 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1796
1797 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1798 Register Rleft = left->is_single_cpu() ? left->as_register() :
1799 left->as_register_lo();
1800 if (dst->is_single_cpu()) {
1801 Register Rdst = dst->as_register();
1802 if (right->is_constant()) {
1803 switch (code) {
1804 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1805 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1806 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1807 default: ShouldNotReachHere(); break;
1808 }
1809 } else {
1810 Register Rright = right->is_single_cpu() ? right->as_register() :
1811 right->as_register_lo();
1812 switch (code) {
1813 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1814 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1815 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1816 default: ShouldNotReachHere(); break;
1817 }
1818 }
1819 } else {
1820 Register Rdst = dst->as_register_lo();
1821 if (right->is_constant()) {
1822 switch (code) {
1823 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1824 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1825 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1826 default: ShouldNotReachHere(); break;
1827 }
1828 } else {
1829 Register Rright = right->is_single_cpu() ? right->as_register() :
1830 right->as_register_lo();
1831 switch (code) {
1832 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1833 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1834 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1835 default: ShouldNotReachHere(); break;
1836 }
1837 }
1838 }
1839 }
1840
1841
1842
1843 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1844
1845 // opcode check
1846 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1847 bool is_irem = (code == lir_irem);
1848
1849 // operand check
1850 assert(left->is_single_cpu(), "left must be register");
1851 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1852 assert(result->is_single_cpu(), "result must be register");
1853 Register lreg = left->as_register();
1854 Register dreg = result->as_register();
1855
1856 // power-of-2 constant check and codegen
1857 if (right->is_constant()) {
1858 int c = right->as_constant_ptr()->as_jint();
1859 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1860 if (is_irem) {
1861 if (c == 1) {
1862 // move 0 to dreg if divisor is 1
1863 __ movw(dreg, zr);
1864 } else {
1865 // use rscratch1 as intermediate result register
1866 __ negsw(rscratch1, lreg);
1867 __ andw(dreg, lreg, c - 1);
1868 __ andw(rscratch1, rscratch1, c - 1);
1869 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1870 }
1871 } else {
1872 if (c == 1) {
1873 // move lreg to dreg if divisor is 1
1874 __ movw(dreg, lreg);
1875 } else {
1876 unsigned int shift = exact_log2(c);
1877 // use rscratch1 as intermediate result register
1878 __ asrw(rscratch1, lreg, 31);
1879 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1880 __ asrw(dreg, rscratch1, shift);
1881 }
1882 }
1883 } else {
1884 Register rreg = right->as_register();
1885 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1886 }
1887 }
1888
1889
1890 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1891 if (opr1->is_constant() && opr2->is_single_cpu()) {
1892 // tableswitch
1893 Register reg = as_reg(opr2);
1894 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1895 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1896 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1897 Register reg1 = as_reg(opr1);
1898 if (opr2->is_single_cpu()) {
1899 // cpu register - cpu register
1900 Register reg2 = opr2->as_register();
1901 if (is_reference_type(opr1->type())) {
1902 __ cmpoop(reg1, reg2);
1903 } else {
1904 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1905 __ cmpw(reg1, reg2);
1906 }
1907 return;
1908 }
1909 if (opr2->is_double_cpu()) {
1910 // cpu register - cpu register
1911 Register reg2 = opr2->as_register_lo();
1912 __ cmp(reg1, reg2);
1913 return;
1914 }
1915
1916 if (opr2->is_constant()) {
1917 bool is_32bit = false; // width of register operand
1918 jlong imm;
1919
1920 switch(opr2->type()) {
1921 case T_INT:
1922 imm = opr2->as_constant_ptr()->as_jint();
1923 is_32bit = true;
1924 break;
1925 case T_LONG:
1926 imm = opr2->as_constant_ptr()->as_jlong();
1927 break;
1928 case T_ADDRESS:
1929 imm = opr2->as_constant_ptr()->as_jint();
1930 break;
1931 case T_METADATA:
1932 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1933 break;
1934 case T_OBJECT:
1935 case T_ARRAY:
1936 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1937 __ cmpoop(reg1, rscratch1);
1938 return;
1939 default:
1940 ShouldNotReachHere();
1941 imm = 0; // unreachable
1942 break;
1943 }
1944
1945 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1946 if (is_32bit)
1947 __ cmpw(reg1, imm);
1948 else
1949 __ subs(zr, reg1, imm);
1950 return;
1951 } else {
1952 __ mov(rscratch1, imm);
1953 if (is_32bit)
1954 __ cmpw(reg1, rscratch1);
1955 else
1956 __ cmp(reg1, rscratch1);
1957 return;
1958 }
1959 } else
1960 ShouldNotReachHere();
1961 } else if (opr1->is_single_fpu()) {
1962 FloatRegister reg1 = opr1->as_float_reg();
1963 assert(opr2->is_single_fpu(), "expect single float register");
1964 FloatRegister reg2 = opr2->as_float_reg();
1965 __ fcmps(reg1, reg2);
1966 } else if (opr1->is_double_fpu()) {
1967 FloatRegister reg1 = opr1->as_double_reg();
1968 assert(opr2->is_double_fpu(), "expect double float register");
1969 FloatRegister reg2 = opr2->as_double_reg();
1970 __ fcmpd(reg1, reg2);
1971 } else {
1972 ShouldNotReachHere();
1973 }
1974 }
1975
1976 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1977 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1978 bool is_unordered_less = (code == lir_ucmp_fd2i);
1979 if (left->is_single_fpu()) {
1980 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1981 } else if (left->is_double_fpu()) {
1982 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1983 } else {
1984 ShouldNotReachHere();
1985 }
1986 } else if (code == lir_cmp_l2i) {
1987 Label done;
1988 __ cmp(left->as_register_lo(), right->as_register_lo());
1989 __ mov(dst->as_register(), (uint64_t)-1L);
1990 __ br(Assembler::LT, done);
1991 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
1992 __ bind(done);
1993 } else {
1994 ShouldNotReachHere();
1995 }
1996 }
1997
1998
1999 void LIR_Assembler::align_call(LIR_Code code) { }
2000
2001
2002 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2003 address call = __ trampoline_call(Address(op->addr(), rtype));
2004 if (call == nullptr) {
2005 bailout("trampoline stub overflow");
2006 return;
2007 }
2008 add_call_info(code_offset(), op->info());
2009 __ post_call_nop();
2010 }
2011
2012
2013 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2014 address call = __ ic_call(op->addr());
2015 if (call == nullptr) {
2016 bailout("trampoline stub overflow");
2017 return;
2018 }
2019 add_call_info(code_offset(), op->info());
2020 __ post_call_nop();
2021 }
2022
2023 void LIR_Assembler::emit_static_call_stub() {
2024 address call_pc = __ pc();
2025 address stub = __ start_a_stub(call_stub_size());
2026 if (stub == nullptr) {
2027 bailout("static call stub overflow");
2028 return;
2029 }
2030
2031 int start = __ offset();
2032
2033 __ relocate(static_stub_Relocation::spec(call_pc));
2034 __ emit_static_call_stub();
2035
2036 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2037 <= call_stub_size(), "stub too big");
2038 __ end_a_stub();
2039 }
2040
2041
2042 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2043 assert(exceptionOop->as_register() == r0, "must match");
2044 assert(exceptionPC->as_register() == r3, "must match");
2045
2046 // exception object is not added to oop map by LinearScan
2047 // (LinearScan assumes that no oops are in fixed registers)
2048 info->add_register_oop(exceptionOop);
2049 C1StubId unwind_id;
2050
2051 // get current pc information
2052 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2053 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2054 // As no instructions have been generated yet for this LIR node it's
2055 // possible that an oop map already exists for the current offset.
2056 // In that case insert an dummy NOP here to ensure all oop map PCs
2057 // are unique. See JDK-8237483.
2058 __ nop();
2059 }
2060 int pc_for_athrow_offset = __ offset();
2061 InternalAddress pc_for_athrow(__ pc());
2062 __ adr(exceptionPC->as_register(), pc_for_athrow);
2063 add_call_info(pc_for_athrow_offset, info); // for exception handler
2064
2065 __ verify_not_null_oop(r0);
2066 // search an exception handler (r0: exception oop, r3: throwing pc)
2067 if (compilation()->has_fpu_code()) {
2068 unwind_id = C1StubId::handle_exception_id;
2069 } else {
2070 unwind_id = C1StubId::handle_exception_nofpu_id;
2071 }
2072 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2073
2074 // FIXME: enough room for two byte trap ????
2075 __ nop();
2076 }
2077
2078
2079 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2080 assert(exceptionOop->as_register() == r0, "must match");
2081
2082 __ b(_unwind_handler_entry);
2083 }
2084
2085
2086 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2087 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2088 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2089
2090 switch (left->type()) {
2091 case T_INT: {
2092 switch (code) {
2093 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2094 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2095 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2096 default:
2097 ShouldNotReachHere();
2098 break;
2099 }
2100 break;
2101 case T_LONG:
2102 case T_ADDRESS:
2103 case T_OBJECT:
2104 switch (code) {
2105 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2106 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2107 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2108 default:
2109 ShouldNotReachHere();
2110 break;
2111 }
2112 break;
2113 default:
2114 ShouldNotReachHere();
2115 break;
2116 }
2117 }
2118 }
2119
2120
2121 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2122 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2123 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2124
2125 switch (left->type()) {
2126 case T_INT: {
2127 switch (code) {
2128 case lir_shl: __ lslw (dreg, lreg, count); break;
2129 case lir_shr: __ asrw (dreg, lreg, count); break;
2130 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2131 default:
2132 ShouldNotReachHere();
2133 break;
2134 }
2135 break;
2136 case T_LONG:
2137 case T_ADDRESS:
2138 case T_OBJECT:
2139 switch (code) {
2140 case lir_shl: __ lsl (dreg, lreg, count); break;
2141 case lir_shr: __ asr (dreg, lreg, count); break;
2142 case lir_ushr: __ lsr (dreg, lreg, count); break;
2143 default:
2144 ShouldNotReachHere();
2145 break;
2146 }
2147 break;
2148 default:
2149 ShouldNotReachHere();
2150 break;
2151 }
2152 }
2153 }
2154
2155
2156 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2157 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2158 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2159 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2160 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2161 }
2162
2163
2164 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2165 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2166 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2167 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2168 __ mov (rscratch1, c);
2169 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2170 }
2171
2172
2173 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2174 ShouldNotReachHere();
2175 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2176 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2177 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2178 __ lea(rscratch1, __ constant_oop_address(o));
2179 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2180 }
2181
2182
2183 // This code replaces a call to arraycopy; no exception may
2184 // be thrown in this code, they must be thrown in the System.arraycopy
2185 // activation frame; we could save some checks if this would not be the case
2186 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2187 ciArrayKlass* default_type = op->expected_type();
2188 Register src = op->src()->as_register();
2189 Register dst = op->dst()->as_register();
2190 Register src_pos = op->src_pos()->as_register();
2191 Register dst_pos = op->dst_pos()->as_register();
2192 Register length = op->length()->as_register();
2193 Register tmp = op->tmp()->as_register();
2194
2195 CodeStub* stub = op->stub();
2196 int flags = op->flags();
2197 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2198 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2199
2200 // if we don't know anything, just go through the generic arraycopy
2201 if (default_type == nullptr // || basic_type == T_OBJECT
2202 ) {
2203 Label done;
2204 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2205
2206 // Save the arguments in case the generic arraycopy fails and we
2207 // have to fall back to the JNI stub
2208 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2209 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2210 __ str(src, Address(sp, 4*BytesPerWord));
2211
2212 address copyfunc_addr = StubRoutines::generic_arraycopy();
2213 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2214
2215 // The arguments are in java calling convention so we shift them
2216 // to C convention
2217 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2218 __ mov(c_rarg0, j_rarg0);
2219 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2220 __ mov(c_rarg1, j_rarg1);
2221 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2222 __ mov(c_rarg2, j_rarg2);
2223 assert_different_registers(c_rarg3, j_rarg4);
2224 __ mov(c_rarg3, j_rarg3);
2225 __ mov(c_rarg4, j_rarg4);
2226 #ifndef PRODUCT
2227 if (PrintC1Statistics) {
2228 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2229 }
2230 #endif
2231 __ far_call(RuntimeAddress(copyfunc_addr));
2232
2233 __ cbz(r0, *stub->continuation());
2234
2235 // Reload values from the stack so they are where the stub
2236 // expects them.
2237 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2238 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2239 __ ldr(src, Address(sp, 4*BytesPerWord));
2240
2241 // r0 is -1^K where K == partial copied count
2242 __ eonw(rscratch1, r0, zr);
2243 // adjust length down and src/end pos up by partial copied count
2244 __ subw(length, length, rscratch1);
2245 __ addw(src_pos, src_pos, rscratch1);
2246 __ addw(dst_pos, dst_pos, rscratch1);
2247 __ b(*stub->entry());
2248
2249 __ bind(*stub->continuation());
2250 return;
2251 }
2252
2253 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2254
2255 int elem_size = type2aelembytes(basic_type);
2256 int scale = exact_log2(elem_size);
2257
2258 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2259 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2260
2261 // test for null
2262 if (flags & LIR_OpArrayCopy::src_null_check) {
2263 __ cbz(src, *stub->entry());
2264 }
2265 if (flags & LIR_OpArrayCopy::dst_null_check) {
2266 __ cbz(dst, *stub->entry());
2267 }
2268
2269 // If the compiler was not able to prove that exact type of the source or the destination
2270 // of the arraycopy is an array type, check at runtime if the source or the destination is
2271 // an instance type.
2272 if (flags & LIR_OpArrayCopy::type_check) {
2273 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2274 __ load_klass(tmp, dst);
2275 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2276 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2277 __ br(Assembler::GE, *stub->entry());
2278 }
2279
2280 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2281 __ load_klass(tmp, src);
2282 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2283 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2284 __ br(Assembler::GE, *stub->entry());
2285 }
2286 }
2287
2288 // check if negative
2289 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2290 __ cmpw(src_pos, 0);
2291 __ br(Assembler::LT, *stub->entry());
2292 }
2293 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2294 __ cmpw(dst_pos, 0);
2295 __ br(Assembler::LT, *stub->entry());
2296 }
2297
2298 if (flags & LIR_OpArrayCopy::length_positive_check) {
2299 __ cmpw(length, 0);
2300 __ br(Assembler::LT, *stub->entry());
2301 }
2302
2303 if (flags & LIR_OpArrayCopy::src_range_check) {
2304 __ addw(tmp, src_pos, length);
2305 __ ldrw(rscratch1, src_length_addr);
2306 __ cmpw(tmp, rscratch1);
2307 __ br(Assembler::HI, *stub->entry());
2308 }
2309 if (flags & LIR_OpArrayCopy::dst_range_check) {
2310 __ addw(tmp, dst_pos, length);
2311 __ ldrw(rscratch1, dst_length_addr);
2312 __ cmpw(tmp, rscratch1);
2313 __ br(Assembler::HI, *stub->entry());
2314 }
2315
2316 if (flags & LIR_OpArrayCopy::type_check) {
2317 // We don't know the array types are compatible
2318 if (basic_type != T_OBJECT) {
2319 // Simple test for basic type arrays
2320 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2321 __ br(Assembler::NE, *stub->entry());
2322 } else {
2323 // For object arrays, if src is a sub class of dst then we can
2324 // safely do the copy.
2325 Label cont, slow;
2326
2327 #define PUSH(r1, r2) \
2328 stp(r1, r2, __ pre(sp, -2 * wordSize));
2329
2330 #define POP(r1, r2) \
2331 ldp(r1, r2, __ post(sp, 2 * wordSize));
2332
2333 __ PUSH(src, dst);
2334
2335 __ load_klass(src, src);
2336 __ load_klass(dst, dst);
2337
2338 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2339
2340 __ PUSH(src, dst);
2341 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
2342 __ POP(src, dst);
2343
2344 __ cbnz(src, cont);
2345
2346 __ bind(slow);
2347 __ POP(src, dst);
2348
2349 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2350 if (copyfunc_addr != nullptr) { // use stub if available
2351 // src is not a sub class of dst so we have to do a
2352 // per-element check.
2353
2354 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2355 if ((flags & mask) != mask) {
2356 // Check that at least both of them object arrays.
2357 assert(flags & mask, "one of the two should be known to be an object array");
2358
2359 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2360 __ load_klass(tmp, src);
2361 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2362 __ load_klass(tmp, dst);
2363 }
2364 int lh_offset = in_bytes(Klass::layout_helper_offset());
2365 Address klass_lh_addr(tmp, lh_offset);
2366 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2367 __ ldrw(rscratch1, klass_lh_addr);
2368 __ mov(rscratch2, objArray_lh);
2369 __ eorw(rscratch1, rscratch1, rscratch2);
2370 __ cbnzw(rscratch1, *stub->entry());
2371 }
2372
2373 // Spill because stubs can use any register they like and it's
2374 // easier to restore just those that we care about.
2375 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2376 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2377 __ str(src, Address(sp, 4*BytesPerWord));
2378
2379 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2380 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2381 assert_different_registers(c_rarg0, dst, dst_pos, length);
2382 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2383 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2384 assert_different_registers(c_rarg1, dst, length);
2385 __ uxtw(c_rarg2, length);
2386 assert_different_registers(c_rarg2, dst);
2387
2388 __ load_klass(c_rarg4, dst);
2389 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2390 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2391 __ far_call(RuntimeAddress(copyfunc_addr));
2392
2393 #ifndef PRODUCT
2394 if (PrintC1Statistics) {
2395 Label failed;
2396 __ cbnz(r0, failed);
2397 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2398 __ bind(failed);
2399 }
2400 #endif
2401
2402 __ cbz(r0, *stub->continuation());
2403
2404 #ifndef PRODUCT
2405 if (PrintC1Statistics) {
2406 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2407 }
2408 #endif
2409 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2410
2411 // Restore previously spilled arguments
2412 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2413 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2414 __ ldr(src, Address(sp, 4*BytesPerWord));
2415
2416 // return value is -1^K where K is partial copied count
2417 __ eonw(rscratch1, r0, zr);
2418 // adjust length down and src/end pos up by partial copied count
2419 __ subw(length, length, rscratch1);
2420 __ addw(src_pos, src_pos, rscratch1);
2421 __ addw(dst_pos, dst_pos, rscratch1);
2422 }
2423
2424 __ b(*stub->entry());
2425
2426 __ bind(cont);
2427 __ POP(src, dst);
2428 }
2429 }
2430
2431 #ifdef ASSERT
2432 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2433 // Sanity check the known type with the incoming class. For the
2434 // primitive case the types must match exactly with src.klass and
2435 // dst.klass each exactly matching the default type. For the
2436 // object array case, if no type check is needed then either the
2437 // dst type is exactly the expected type and the src type is a
2438 // subtype which we can't check or src is the same array as dst
2439 // but not necessarily exactly of type default_type.
2440 Label known_ok, halt;
2441 __ mov_metadata(tmp, default_type->constant_encoding());
2442
2443 if (basic_type != T_OBJECT) {
2444 __ cmp_klass(dst, tmp, rscratch1);
2445 __ br(Assembler::NE, halt);
2446 __ cmp_klass(src, tmp, rscratch1);
2447 __ br(Assembler::EQ, known_ok);
2448 } else {
2449 __ cmp_klass(dst, tmp, rscratch1);
2450 __ br(Assembler::EQ, known_ok);
2451 __ cmp(src, dst);
2452 __ br(Assembler::EQ, known_ok);
2453 }
2454 __ bind(halt);
2455 __ stop("incorrect type information in arraycopy");
2456 __ bind(known_ok);
2457 }
2458 #endif
2459
2460 #ifndef PRODUCT
2461 if (PrintC1Statistics) {
2462 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2463 }
2464 #endif
2465
2466 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2467 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2468 assert_different_registers(c_rarg0, dst, dst_pos, length);
2469 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2470 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2471 assert_different_registers(c_rarg1, dst, length);
2472 __ uxtw(c_rarg2, length);
2473 assert_different_registers(c_rarg2, dst);
2474
2475 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2476 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2477 const char *name;
2478 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2479
2480 CodeBlob *cb = CodeCache::find_blob(entry);
2481 if (cb) {
2482 __ far_call(RuntimeAddress(entry));
2483 } else {
2484 __ call_VM_leaf(entry, 3);
2485 }
2486
2487 if (stub != nullptr) {
2488 __ bind(*stub->continuation());
2489 }
2490 }
2491
2492
2493
2494
2495 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2496 Register obj = op->obj_opr()->as_register(); // may not be an oop
2497 Register hdr = op->hdr_opr()->as_register();
2498 Register lock = op->lock_opr()->as_register();
2499 Register temp = op->scratch_opr()->as_register();
2500 if (LockingMode == LM_MONITOR) {
2501 if (op->info() != nullptr) {
2502 add_debug_info_for_null_check_here(op->info());
2503 __ null_check(obj, -1);
2504 }
2505 __ b(*op->stub()->entry());
2506 } else if (op->code() == lir_lock) {
2507 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2508 // add debug info for NullPointerException only if one is possible
2509 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2510 if (op->info() != nullptr) {
2511 add_debug_info_for_null_check(null_check_offset, op->info());
2512 }
2513 // done
2514 } else if (op->code() == lir_unlock) {
2515 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2516 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2517 } else {
2518 Unimplemented();
2519 }
2520 __ bind(*op->stub()->continuation());
2521 }
2522
2523 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2524 Register obj = op->obj()->as_pointer_register();
2525 Register result = op->result_opr()->as_pointer_register();
2526
2527 CodeEmitInfo* info = op->info();
2528 if (info != nullptr) {
2529 add_debug_info_for_null_check_here(info);
2530 }
2531
2532 __ load_klass(result, obj);
2533 }
2534
2535 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2536 ciMethod* method = op->profiled_method();
2537 int bci = op->profiled_bci();
2538 ciMethod* callee = op->profiled_callee();
2539
2540 // Update counter for all call types
2541 ciMethodData* md = method->method_data_or_null();
2542 assert(md != nullptr, "Sanity");
2543 ciProfileData* data = md->bci_to_data(bci);
2544 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2545 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2546 Register mdo = op->mdo()->as_register();
2547 __ mov_metadata(mdo, md->constant_encoding());
2548 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2549 // Perform additional virtual call profiling for invokevirtual and
2550 // invokeinterface bytecodes
2551 if (op->should_profile_receiver_type()) {
2552 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2553 Register recv = op->recv()->as_register();
2554 assert_different_registers(mdo, recv);
2555 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2556 ciKlass* known_klass = op->known_holder();
2557 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2558 // We know the type that will be seen at this call site; we can
2559 // statically update the MethodData* rather than needing to do
2560 // dynamic tests on the receiver type
2561
2562 // NOTE: we should probably put a lock around this search to
2563 // avoid collisions by concurrent compilations
2564 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2565 uint i;
2566 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2567 ciKlass* receiver = vc_data->receiver(i);
2568 if (known_klass->equals(receiver)) {
2569 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2570 __ addptr(data_addr, DataLayout::counter_increment);
2571 return;
2572 }
2573 }
2574
2575 // Receiver type not found in profile data; select an empty slot
2576
2577 // Note that this is less efficient than it should be because it
2578 // always does a write to the receiver part of the
2579 // VirtualCallData rather than just the first time
2580 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2581 ciKlass* receiver = vc_data->receiver(i);
2582 if (receiver == nullptr) {
2583 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2584 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2585 __ lea(rscratch2, recv_addr);
2586 __ str(rscratch1, Address(rscratch2));
2587 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2588 __ addptr(data_addr, DataLayout::counter_increment);
2589 return;
2590 }
2591 }
2592 } else {
2593 __ load_klass(recv, recv);
2594 Label update_done;
2595 type_profile_helper(mdo, md, data, recv, &update_done);
2596 // Receiver did not match any saved receiver and there is no empty row for it.
2597 // Increment total counter to indicate polymorphic case.
2598 __ addptr(counter_addr, DataLayout::counter_increment);
2599
2600 __ bind(update_done);
2601 }
2602 } else {
2603 // Static call
2604 __ addptr(counter_addr, DataLayout::counter_increment);
2605 }
2606 }
2607
2608
2609 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2610 Unimplemented();
2611 }
2612
2613
2614 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2615 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2616 }
2617
2618 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2619 assert(op->crc()->is_single_cpu(), "crc must be register");
2620 assert(op->val()->is_single_cpu(), "byte value must be register");
2621 assert(op->result_opr()->is_single_cpu(), "result must be register");
2622 Register crc = op->crc()->as_register();
2623 Register val = op->val()->as_register();
2624 Register res = op->result_opr()->as_register();
2625
2626 assert_different_registers(val, crc, res);
2627 uint64_t offset;
2628 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2629 __ add(res, res, offset);
2630
2631 __ mvnw(crc, crc); // ~crc
2632 __ update_byte_crc32(crc, val, res);
2633 __ mvnw(res, crc); // ~crc
2634 }
2635
2636 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2637 COMMENT("emit_profile_type {");
2638 Register obj = op->obj()->as_register();
2639 Register tmp = op->tmp()->as_pointer_register();
2640 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2641 ciKlass* exact_klass = op->exact_klass();
2642 intptr_t current_klass = op->current_klass();
2643 bool not_null = op->not_null();
2644 bool no_conflict = op->no_conflict();
2645
2646 Label update, next, none;
2647
2648 bool do_null = !not_null;
2649 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2650 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2651
2652 assert(do_null || do_update, "why are we here?");
2653 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2654 assert(mdo_addr.base() != rscratch1, "wrong register");
2655
2656 __ verify_oop(obj);
2657
2658 if (tmp != obj) {
2659 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2660 __ mov(tmp, obj);
2661 } else {
2662 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2663 }
2664 if (do_null) {
2665 __ cbnz(tmp, update);
2666 if (!TypeEntries::was_null_seen(current_klass)) {
2667 __ ldr(rscratch2, mdo_addr);
2668 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2669 __ str(rscratch2, mdo_addr);
2670 }
2671 if (do_update) {
2672 #ifndef ASSERT
2673 __ b(next);
2674 }
2675 #else
2676 __ b(next);
2677 }
2678 } else {
2679 __ cbnz(tmp, update);
2680 __ stop("unexpected null obj");
2681 #endif
2682 }
2683
2684 __ bind(update);
2685
2686 if (do_update) {
2687 #ifdef ASSERT
2688 if (exact_klass != nullptr) {
2689 Label ok;
2690 __ load_klass(tmp, tmp);
2691 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2692 __ eor(rscratch1, tmp, rscratch1);
2693 __ cbz(rscratch1, ok);
2694 __ stop("exact klass and actual klass differ");
2695 __ bind(ok);
2696 }
2697 #endif
2698 if (!no_conflict) {
2699 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2700 if (exact_klass != nullptr) {
2701 __ mov_metadata(tmp, exact_klass->constant_encoding());
2702 } else {
2703 __ load_klass(tmp, tmp);
2704 }
2705
2706 __ ldr(rscratch2, mdo_addr);
2707 __ eor(tmp, tmp, rscratch2);
2708 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2709 // klass seen before, nothing to do. The unknown bit may have been
2710 // set already but no need to check.
2711 __ cbz(rscratch1, next);
2712
2713 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2714
2715 if (TypeEntries::is_type_none(current_klass)) {
2716 __ cbz(rscratch2, none);
2717 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2718 __ br(Assembler::EQ, none);
2719 // There is a chance that the checks above
2720 // fail if another thread has just set the
2721 // profiling to this obj's klass
2722 __ dmb(Assembler::ISHLD);
2723 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2724 __ ldr(rscratch2, mdo_addr);
2725 __ eor(tmp, tmp, rscratch2);
2726 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2727 __ cbz(rscratch1, next);
2728 }
2729 } else {
2730 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2731 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2732
2733 __ ldr(tmp, mdo_addr);
2734 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2735 }
2736
2737 // different than before. Cannot keep accurate profile.
2738 __ ldr(rscratch2, mdo_addr);
2739 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2740 __ str(rscratch2, mdo_addr);
2741
2742 if (TypeEntries::is_type_none(current_klass)) {
2743 __ b(next);
2744
2745 __ bind(none);
2746 // first time here. Set profile type.
2747 __ str(tmp, mdo_addr);
2748 #ifdef ASSERT
2749 __ andr(tmp, tmp, TypeEntries::type_mask);
2750 __ verify_klass_ptr(tmp);
2751 #endif
2752 }
2753 } else {
2754 // There's a single possible klass at this profile point
2755 assert(exact_klass != nullptr, "should be");
2756 if (TypeEntries::is_type_none(current_klass)) {
2757 __ mov_metadata(tmp, exact_klass->constant_encoding());
2758 __ ldr(rscratch2, mdo_addr);
2759 __ eor(tmp, tmp, rscratch2);
2760 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2761 __ cbz(rscratch1, next);
2762 #ifdef ASSERT
2763 {
2764 Label ok;
2765 __ ldr(rscratch1, mdo_addr);
2766 __ cbz(rscratch1, ok);
2767 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2768 __ br(Assembler::EQ, ok);
2769 // may have been set by another thread
2770 __ dmb(Assembler::ISHLD);
2771 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2772 __ ldr(rscratch2, mdo_addr);
2773 __ eor(rscratch2, rscratch1, rscratch2);
2774 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2775 __ cbz(rscratch2, ok);
2776
2777 __ stop("unexpected profiling mismatch");
2778 __ bind(ok);
2779 }
2780 #endif
2781 // first time here. Set profile type.
2782 __ str(tmp, mdo_addr);
2783 #ifdef ASSERT
2784 __ andr(tmp, tmp, TypeEntries::type_mask);
2785 __ verify_klass_ptr(tmp);
2786 #endif
2787 } else {
2788 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2789 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2790
2791 __ ldr(tmp, mdo_addr);
2792 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2793
2794 __ orr(tmp, tmp, TypeEntries::type_unknown);
2795 __ str(tmp, mdo_addr);
2796 // FIXME: Write barrier needed here?
2797 }
2798 }
2799
2800 __ bind(next);
2801 }
2802 COMMENT("} emit_profile_type");
2803 }
2804
2805
2806 void LIR_Assembler::align_backward_branch_target() {
2807 }
2808
2809
2810 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2811 // tmp must be unused
2812 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2813
2814 if (left->is_single_cpu()) {
2815 assert(dest->is_single_cpu(), "expect single result reg");
2816 __ negw(dest->as_register(), left->as_register());
2817 } else if (left->is_double_cpu()) {
2818 assert(dest->is_double_cpu(), "expect double result reg");
2819 __ neg(dest->as_register_lo(), left->as_register_lo());
2820 } else if (left->is_single_fpu()) {
2821 assert(dest->is_single_fpu(), "expect single float result reg");
2822 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2823 } else {
2824 assert(left->is_double_fpu(), "expect double float operand reg");
2825 assert(dest->is_double_fpu(), "expect double float result reg");
2826 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2827 }
2828 }
2829
2830
2831 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2832 if (patch_code != lir_patch_none) {
2833 deoptimize_trap(info);
2834 return;
2835 }
2836
2837 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2838 }
2839
2840
2841 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2842 assert(!tmp->is_valid(), "don't need temporary");
2843
2844 CodeBlob *cb = CodeCache::find_blob(dest);
2845 if (cb) {
2846 __ far_call(RuntimeAddress(dest));
2847 } else {
2848 __ mov(rscratch1, RuntimeAddress(dest));
2849 __ blr(rscratch1);
2850 }
2851
2852 if (info != nullptr) {
2853 add_call_info_here(info);
2854 }
2855 __ post_call_nop();
2856 }
2857
2858 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2859 if (dest->is_address() || src->is_address()) {
2860 move_op(src, dest, type, lir_patch_none, info,
2861 /*pop_fpu_stack*/false, /*wide*/false);
2862 } else {
2863 ShouldNotReachHere();
2864 }
2865 }
2866
2867 #ifdef ASSERT
2868 // emit run-time assertion
2869 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2870 assert(op->code() == lir_assert, "must be");
2871
2872 if (op->in_opr1()->is_valid()) {
2873 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2874 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2875 } else {
2876 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2877 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2878 }
2879
2880 Label ok;
2881 if (op->condition() != lir_cond_always) {
2882 Assembler::Condition acond = Assembler::AL;
2883 switch (op->condition()) {
2884 case lir_cond_equal: acond = Assembler::EQ; break;
2885 case lir_cond_notEqual: acond = Assembler::NE; break;
2886 case lir_cond_less: acond = Assembler::LT; break;
2887 case lir_cond_lessEqual: acond = Assembler::LE; break;
2888 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2889 case lir_cond_greater: acond = Assembler::GT; break;
2890 case lir_cond_belowEqual: acond = Assembler::LS; break;
2891 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2892 default: ShouldNotReachHere();
2893 }
2894 __ br(acond, ok);
2895 }
2896 if (op->halt()) {
2897 const char* str = __ code_string(op->msg());
2898 __ stop(str);
2899 } else {
2900 breakpoint();
2901 }
2902 __ bind(ok);
2903 }
2904 #endif
2905
2906 #ifndef PRODUCT
2907 #define COMMENT(x) do { __ block_comment(x); } while (0)
2908 #else
2909 #define COMMENT(x)
2910 #endif
2911
2912 void LIR_Assembler::membar() {
2913 COMMENT("membar");
2914 __ membar(MacroAssembler::AnyAny);
2915 }
2916
2917 void LIR_Assembler::membar_acquire() {
2918 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2919 }
2920
2921 void LIR_Assembler::membar_release() {
2922 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2923 }
2924
2925 void LIR_Assembler::membar_loadload() {
2926 __ membar(Assembler::LoadLoad);
2927 }
2928
2929 void LIR_Assembler::membar_storestore() {
2930 __ membar(MacroAssembler::StoreStore);
2931 }
2932
2933 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2934
2935 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2936
2937 void LIR_Assembler::on_spin_wait() {
2938 __ spin_wait();
2939 }
2940
2941 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2942 __ mov(result_reg->as_register(), rthread);
2943 }
2944
2945
2946 void LIR_Assembler::peephole(LIR_List *lir) {
2947 #if 0
2948 if (tableswitch_count >= max_tableswitches)
2949 return;
2950
2951 /*
2952 This finite-state automaton recognizes sequences of compare-and-
2953 branch instructions. We will turn them into a tableswitch. You
2954 could argue that C1 really shouldn't be doing this sort of
2955 optimization, but without it the code is really horrible.
2956 */
2957
2958 enum { start_s, cmp1_s, beq_s, cmp_s } state;
2959 int first_key, last_key = -2147483648;
2960 int next_key = 0;
2961 int start_insn = -1;
2962 int last_insn = -1;
2963 Register reg = noreg;
2964 LIR_Opr reg_opr;
2965 state = start_s;
2966
2967 LIR_OpList* inst = lir->instructions_list();
2968 for (int i = 0; i < inst->length(); i++) {
2969 LIR_Op* op = inst->at(i);
2970 switch (state) {
2971 case start_s:
2972 first_key = -1;
2973 start_insn = i;
2974 switch (op->code()) {
2975 case lir_cmp:
2976 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2977 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2978 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2979 && opr2->is_constant()
2980 && opr2->type() == T_INT) {
2981 reg_opr = opr1;
2982 reg = opr1->as_register();
2983 first_key = opr2->as_constant_ptr()->as_jint();
2984 next_key = first_key + 1;
2985 state = cmp_s;
2986 goto next_state;
2987 }
2988 break;
2989 }
2990 break;
2991 case cmp_s:
2992 switch (op->code()) {
2993 case lir_branch:
2994 if (op->as_OpBranch()->cond() == lir_cond_equal) {
2995 state = beq_s;
2996 last_insn = i;
2997 goto next_state;
2998 }
2999 }
3000 state = start_s;
3001 break;
3002 case beq_s:
3003 switch (op->code()) {
3004 case lir_cmp: {
3005 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3006 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3007 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3008 && opr1->as_register() == reg
3009 && opr2->is_constant()
3010 && opr2->type() == T_INT
3011 && opr2->as_constant_ptr()->as_jint() == next_key) {
3012 last_key = next_key;
3013 next_key++;
3014 state = cmp_s;
3015 goto next_state;
3016 }
3017 }
3018 }
3019 last_key = next_key;
3020 state = start_s;
3021 break;
3022 default:
3023 assert(false, "impossible state");
3024 }
3025 if (state == start_s) {
3026 if (first_key < last_key - 5L && reg != noreg) {
3027 {
3028 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3029 // reg->encoding(),
3030 // start_insn, first_key, last_key);
3031 // for (int i = 0; i < inst->length(); i++) {
3032 // inst->at(i)->print();
3033 // tty->print("\n");
3034 // }
3035 // tty->print("\n");
3036 }
3037
3038 struct tableswitch *sw = &switches[tableswitch_count];
3039 sw->_insn_index = start_insn, sw->_first_key = first_key,
3040 sw->_last_key = last_key, sw->_reg = reg;
3041 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3042 {
3043 // Insert the new table of branches
3044 int offset = last_insn;
3045 for (int n = first_key; n < last_key; n++) {
3046 inst->insert_before
3047 (last_insn + 1,
3048 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3049 inst->at(offset)->as_OpBranch()->label()));
3050 offset -= 2, i++;
3051 }
3052 }
3053 // Delete all the old compare-and-branch instructions
3054 for (int n = first_key; n < last_key; n++) {
3055 inst->remove_at(start_insn);
3056 inst->remove_at(start_insn);
3057 }
3058 // Insert the tableswitch instruction
3059 inst->insert_before(start_insn,
3060 new LIR_Op2(lir_cmp, lir_cond_always,
3061 LIR_OprFact::intConst(tableswitch_count),
3062 reg_opr));
3063 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3064 tableswitch_count++;
3065 }
3066 reg = noreg;
3067 last_key = -2147483648;
3068 }
3069 next_state:
3070 ;
3071 }
3072 #endif
3073 }
3074
3075 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3076 Address addr = as_Address(src->as_address_ptr());
3077 BasicType type = src->type();
3078 bool is_oop = is_reference_type(type);
3079
3080 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3081 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3082
3083 switch(type) {
3084 case T_INT:
3085 xchg = &MacroAssembler::atomic_xchgalw;
3086 add = &MacroAssembler::atomic_addalw;
3087 break;
3088 case T_LONG:
3089 xchg = &MacroAssembler::atomic_xchgal;
3090 add = &MacroAssembler::atomic_addal;
3091 break;
3092 case T_OBJECT:
3093 case T_ARRAY:
3094 if (UseCompressedOops) {
3095 xchg = &MacroAssembler::atomic_xchgalw;
3096 add = &MacroAssembler::atomic_addalw;
3097 } else {
3098 xchg = &MacroAssembler::atomic_xchgal;
3099 add = &MacroAssembler::atomic_addal;
3100 }
3101 break;
3102 default:
3103 ShouldNotReachHere();
3104 xchg = &MacroAssembler::atomic_xchgal;
3105 add = &MacroAssembler::atomic_addal; // unreachable
3106 }
3107
3108 switch (code) {
3109 case lir_xadd:
3110 {
3111 RegisterOrConstant inc;
3112 Register tmp = as_reg(tmp_op);
3113 Register dst = as_reg(dest);
3114 if (data->is_constant()) {
3115 inc = RegisterOrConstant(as_long(data));
3116 assert_different_registers(dst, addr.base(), tmp,
3117 rscratch1, rscratch2);
3118 } else {
3119 inc = RegisterOrConstant(as_reg(data));
3120 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3121 rscratch1, rscratch2);
3122 }
3123 __ lea(tmp, addr);
3124 (_masm->*add)(dst, inc, tmp);
3125 break;
3126 }
3127 case lir_xchg:
3128 {
3129 Register tmp = tmp_op->as_register();
3130 Register obj = as_reg(data);
3131 Register dst = as_reg(dest);
3132 if (is_oop && UseCompressedOops) {
3133 __ encode_heap_oop(rscratch2, obj);
3134 obj = rscratch2;
3135 }
3136 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3137 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3138 __ lea(tmp, addr);
3139 (_masm->*xchg)(dst, obj, tmp);
3140 if (is_oop && UseCompressedOops) {
3141 __ decode_heap_oop(dst);
3142 }
3143 }
3144 break;
3145 default:
3146 ShouldNotReachHere();
3147 }
3148 __ membar(__ AnyAny);
3149 }
3150
3151 #undef __