213                          FloatRegister vtmp1, FloatRegister vtmp2, FloatRegister vtmp3,
214                          PRegister ptmp, PRegister pgtmp, unsigned vector_length_in_bytes);
215 
216   void sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
217                           FloatRegister vzr, FloatRegister vtmp,
218                           PRegister pgtmp, unsigned vector_length_in_bytes);
219 
220   void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
221 
222   void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
223 
224   void neon_rearrange_hsd(FloatRegister dst, FloatRegister src, FloatRegister shuffle,
225                           FloatRegister tmp, BasicType bt, bool isQ);
226   // java.lang.Math::signum intrinsics
227   void vector_signum_neon(FloatRegister dst, FloatRegister src, FloatRegister zero,
228                           FloatRegister one, SIMD_Arrangement T);
229 
230   void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero,
231                          FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T);
232 



233   void verify_int_in_range(uint idx, const TypeInt* t, Register val, Register tmp);
234   void verify_long_in_range(uint idx, const TypeLong* t, Register val, Register tmp);
235 
236   void reconstruct_frame_pointer(Register rtmp);
237 
238   // Select from a table of two vectors
239   void select_from_two_vectors(FloatRegister dst, FloatRegister src1, FloatRegister src2,
240                                FloatRegister index, FloatRegister tmp, BasicType bt,
241                                unsigned vector_length_in_bytes);
242 
243   void vector_expand_neon(FloatRegister dst, FloatRegister src, FloatRegister mask,
244                           FloatRegister tmp1, FloatRegister tmp2, BasicType bt,
245                           int vector_length_in_bytes);
246   void vector_expand_sve(FloatRegister dst, FloatRegister src, PRegister pg,
247                          FloatRegister tmp1, FloatRegister tmp2, BasicType bt,
248                          int vector_length_in_bytes);
249 
250   void sve_cpy(FloatRegister dst, SIMD_RegVariant T, PRegister pg, int imm8,
251                bool isMerge);
252 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP

213                          FloatRegister vtmp1, FloatRegister vtmp2, FloatRegister vtmp3,
214                          PRegister ptmp, PRegister pgtmp, unsigned vector_length_in_bytes);
215 
216   void sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
217                           FloatRegister vzr, FloatRegister vtmp,
218                           PRegister pgtmp, unsigned vector_length_in_bytes);
219 
220   void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
221 
222   void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
223 
224   void neon_rearrange_hsd(FloatRegister dst, FloatRegister src, FloatRegister shuffle,
225                           FloatRegister tmp, BasicType bt, bool isQ);
226   // java.lang.Math::signum intrinsics
227   void vector_signum_neon(FloatRegister dst, FloatRegister src, FloatRegister zero,
228                           FloatRegister one, SIMD_Arrangement T);
229 
230   void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero,
231                          FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T);
232 
233   static void abort_verify_int_in_range(uint idx, jint val, jint lo, jint hi);
234   static void abort_verify_long_in_range(uint idx, jlong val, jlong lo, jlong hi);
235 
236   void verify_int_in_range(uint idx, const TypeInt* t, Register val, Register tmp);
237   void verify_long_in_range(uint idx, const TypeLong* t, Register val, Register tmp);
238 
239   void reconstruct_frame_pointer(Register rtmp);
240 
241   // Select from a table of two vectors
242   void select_from_two_vectors(FloatRegister dst, FloatRegister src1, FloatRegister src2,
243                                FloatRegister index, FloatRegister tmp, BasicType bt,
244                                unsigned vector_length_in_bytes);
245 
246   void vector_expand_neon(FloatRegister dst, FloatRegister src, FloatRegister mask,
247                           FloatRegister tmp1, FloatRegister tmp2, BasicType bt,
248                           int vector_length_in_bytes);
249   void vector_expand_sve(FloatRegister dst, FloatRegister src, PRegister pg,
250                          FloatRegister tmp1, FloatRegister tmp2, BasicType bt,
251                          int vector_length_in_bytes);
252 
253   void sve_cpy(FloatRegister dst, SIMD_RegVariant T, PRegister pg, int imm8,
254                bool isMerge);
255 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP