6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/macroAssembler.inline.hpp"
26 #include "gc/g1/g1BarrierSet.hpp"
27 #include "gc/g1/g1BarrierSetAssembler.hpp"
28 #include "gc/g1/g1BarrierSetRuntime.hpp"
29 #include "gc/g1/g1CardTable.hpp"
30 #include "gc/g1/g1HeapRegion.hpp"
31 #include "gc/g1/g1ThreadLocalData.hpp"
32 #include "gc/shared/collectedHeap.hpp"
33 #include "interpreter/interp_masm.hpp"
34 #include "runtime/javaThread.hpp"
35 #include "runtime/sharedRuntime.hpp"
36 #ifdef COMPILER1
37 #include "c1/c1_LIRAssembler.hpp"
38 #include "c1/c1_MacroAssembler.hpp"
39 #include "gc/g1/c1/g1BarrierSetC1.hpp"
40 #endif // COMPILER1
41 #ifdef COMPILER2
42 #include "gc/g1/c2/g1BarrierSetC2.hpp"
43 #endif // COMPILER2
44
45 #define __ masm->
226 }
227
228 __ pop_call_clobbered_registers();
229
230 __ bind(done);
231
232 }
233
234 static void generate_post_barrier(MacroAssembler* masm,
235 const Register store_addr,
236 const Register new_val,
237 const Register thread,
238 const Register tmp1,
239 const Register tmp2,
240 Label& done,
241 bool new_val_may_be_null) {
242 assert(thread == rthread, "must be");
243 assert_different_registers(store_addr, new_val, thread, tmp1, tmp2, noreg, rscratch1);
244
245 // Does store cross heap regions?
246 __ eor(tmp1, store_addr, new_val); // tmp1 := store address ^ new value
247 __ lsr(tmp1, tmp1, G1HeapRegion::LogOfHRGrainBytes); // tmp1 := ((store address ^ new value) >> LogOfHRGrainBytes)
248 __ cbz(tmp1, done);
249 // Crosses regions, storing null?
250 if (new_val_may_be_null) {
251 __ cbz(new_val, done);
252 }
253 // Storing region crossing non-null.
254 __ lsr(tmp1, store_addr, CardTable::card_shift()); // tmp1 := card address relative to card table base
255
256 Address card_table_addr(thread, in_bytes(G1ThreadLocalData::card_table_base_offset()));
257 __ ldr(tmp2, card_table_addr); // tmp2 := card table base address
258 if (UseCondCardMark) {
259 __ ldrb(rscratch1, Address(tmp1, tmp2)); // rscratch1 := card
260 // Instead of loading clean_card_val and comparing, we exploit the fact that
261 // the LSB of non-clean cards is always 0, and the LSB of clean cards 1.
262 __ tbz(rscratch1, 0, done);
263 }
264 static_assert(G1CardTable::dirty_card_val() == 0, "must be to use zr");
265 __ strb(zr, Address(tmp1, tmp2)); // *(card address) := dirty_card_val
266 }
267
268 void G1BarrierSetAssembler::g1_write_barrier_post(MacroAssembler* masm,
269 Register store_addr,
270 Register new_val,
271 Register thread,
272 Register tmp1,
273 Register tmp2) {
274 Label done;
275 generate_post_barrier(masm, store_addr, new_val, thread, tmp1, tmp2, done, false /* new_val_may_be_null */);
276 __ bind(done);
277 }
278
279 #if defined(COMPILER2)
280
281 static void generate_c2_barrier_runtime_call(MacroAssembler* masm, G1BarrierStubC2* stub, const Register arg, const address runtime_path) {
282 SaveLiveRegisters save_registers(masm, stub);
283 if (c_rarg0 != arg) {
284 __ mov(c_rarg0, arg);
285 }
286 __ mov(c_rarg1, rthread);
287 __ mov(rscratch1, runtime_path);
288 __ blr(rscratch1);
289 }
290
291 void G1BarrierSetAssembler::g1_write_barrier_pre_c2(MacroAssembler* masm,
292 Register obj,
293 Register pre_val,
294 Register thread,
295 Register tmp1,
296 Register tmp2,
297 G1PreBarrierStubC2* stub) {
298 assert(thread == rthread, "must be");
299 assert_different_registers(obj, pre_val, tmp1, tmp2);
300 assert(pre_val != noreg && tmp1 != noreg && tmp2 != noreg, "expecting a register");
301
302 stub->initialize_registers(obj, pre_val, thread, tmp1, tmp2);
303
304 generate_pre_barrier_fast_path(masm, thread, tmp1);
305 // If marking is active (*(mark queue active address) != 0), jump to stub (slow path)
306 __ cbnzw(tmp1, *stub->entry());
307
|
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/macroAssembler.inline.hpp"
26 #include "code/aotCodeCache.hpp"
27 #include "gc/g1/g1BarrierSet.hpp"
28 #include "gc/g1/g1BarrierSetAssembler.hpp"
29 #include "gc/g1/g1BarrierSetRuntime.hpp"
30 #include "gc/g1/g1CardTable.hpp"
31 #include "gc/g1/g1HeapRegion.hpp"
32 #include "gc/g1/g1ThreadLocalData.hpp"
33 #include "gc/shared/collectedHeap.hpp"
34 #include "interpreter/interp_masm.hpp"
35 #include "runtime/javaThread.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #ifdef COMPILER1
38 #include "c1/c1_LIRAssembler.hpp"
39 #include "c1/c1_MacroAssembler.hpp"
40 #include "gc/g1/c1/g1BarrierSetC1.hpp"
41 #endif // COMPILER1
42 #ifdef COMPILER2
43 #include "gc/g1/c2/g1BarrierSetC2.hpp"
44 #endif // COMPILER2
45
46 #define __ masm->
227 }
228
229 __ pop_call_clobbered_registers();
230
231 __ bind(done);
232
233 }
234
235 static void generate_post_barrier(MacroAssembler* masm,
236 const Register store_addr,
237 const Register new_val,
238 const Register thread,
239 const Register tmp1,
240 const Register tmp2,
241 Label& done,
242 bool new_val_may_be_null) {
243 assert(thread == rthread, "must be");
244 assert_different_registers(store_addr, new_val, thread, tmp1, tmp2, noreg, rscratch1);
245
246 // Does store cross heap regions?
247 #if INCLUDE_CDS
248 // AOT code needs to load the barrier grain shift from the aot
249 // runtime constants area in the code cache otherwise we can compile
250 // it as an immediate operand
251 if (AOTCodeCache::is_on_for_dump()) {
252 address grain_shift_address = (address)AOTRuntimeConstants::grain_shift_address();
253 __ eor(tmp1, store_addr, new_val);
254 __ lea(tmp2, ExternalAddress(grain_shift_address));
255 __ ldrb(tmp2, tmp2);
256 __ lsrv(tmp1, tmp1, tmp2);
257 __ cbz(tmp1, done);
258 } else
259 #endif
260 {
261 __ eor(tmp1, store_addr, new_val); // tmp1 := store address ^ new value
262 __ lsr(tmp1, tmp1, G1HeapRegion::LogOfHRGrainBytes); // tmp1 := ((store address ^ new value) >> LogOfHRGrainBytes)
263 __ cbz(tmp1, done);
264 }
265
266 // Crosses regions, storing null?
267 if (new_val_may_be_null) {
268 __ cbz(new_val, done);
269 }
270 // Storing region crossing non-null.
271 __ lsr(tmp1, store_addr, CardTable::card_shift()); // tmp1 := card address relative to card table base
272
273 Address card_table_addr(thread, in_bytes(G1ThreadLocalData::card_table_base_offset()));
274 __ ldr(tmp2, card_table_addr); // tmp2 := card table base address
275 if (UseCondCardMark) {
276 __ ldrb(rscratch1, Address(tmp1, tmp2)); // rscratch1 := card
277 // Instead of loading clean_card_val and comparing, we exploit the fact that
278 // the LSB of non-clean cards is always 0, and the LSB of clean cards 1.
279 __ tbz(rscratch1, 0, done);
280 }
281 static_assert(G1CardTable::dirty_card_val() == 0, "must be to use zr");
282 __ strb(zr, Address(tmp1, tmp2)); // *(card address) := dirty_card_val
283 }
284
285 void G1BarrierSetAssembler::g1_write_barrier_post(MacroAssembler* masm,
286 Register store_addr,
287 Register new_val,
288 Register thread,
289 Register tmp1,
290 Register tmp2) {
291 Label done;
292 generate_post_barrier(masm, store_addr, new_val, thread, tmp1, tmp2, done, false /* new_val_may_be_null */);
293 __ bind(done);
294 }
295
296 #if defined(COMPILER2)
297
298 static void generate_c2_barrier_runtime_call(MacroAssembler* masm, G1BarrierStubC2* stub, const Register arg, const address runtime_path) {
299 SaveLiveRegisters save_registers(masm, stub);
300 if (c_rarg0 != arg) {
301 __ mov(c_rarg0, arg);
302 }
303 __ mov(c_rarg1, rthread);
304 __ lea(rscratch1, RuntimeAddress(runtime_path));
305 __ blr(rscratch1);
306 }
307
308 void G1BarrierSetAssembler::g1_write_barrier_pre_c2(MacroAssembler* masm,
309 Register obj,
310 Register pre_val,
311 Register thread,
312 Register tmp1,
313 Register tmp2,
314 G1PreBarrierStubC2* stub) {
315 assert(thread == rthread, "must be");
316 assert_different_registers(obj, pre_val, tmp1, tmp2);
317 assert(pre_val != noreg && tmp1 != noreg && tmp2 != noreg, "expecting a register");
318
319 stub->initialize_registers(obj, pre_val, thread, tmp1, tmp2);
320
321 generate_pre_barrier_fast_path(masm, thread, tmp1);
322 // If marking is active (*(mark queue active address) != 0), jump to stub (slow path)
323 __ cbnzw(tmp1, *stub->entry());
324
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