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src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.cpp

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  6  * under the terms of the GNU General Public License version 2 only, as
  7  * published by the Free Software Foundation.
  8  *
  9  * This code is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 12  * version 2 for more details (a copy is included in the LICENSE file that
 13  * accompanied this code).
 14  *
 15  * You should have received a copy of the GNU General Public License version
 16  * 2 along with this work; if not, write to the Free Software Foundation,
 17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 18  *
 19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 20  * or visit www.oracle.com if you need additional information or have any
 21  * questions.
 22  *
 23  */
 24 
 25 #include "asm/macroAssembler.inline.hpp"

 26 #include "gc/g1/g1BarrierSet.hpp"
 27 #include "gc/g1/g1BarrierSetAssembler.hpp"
 28 #include "gc/g1/g1BarrierSetRuntime.hpp"
 29 #include "gc/g1/g1CardTable.hpp"
 30 #include "gc/g1/g1HeapRegion.hpp"
 31 #include "gc/g1/g1ThreadLocalData.hpp"
 32 #include "gc/shared/collectedHeap.hpp"
 33 #include "interpreter/interp_masm.hpp"
 34 #include "runtime/javaThread.hpp"
 35 #include "runtime/sharedRuntime.hpp"
 36 #ifdef COMPILER1
 37 #include "c1/c1_LIRAssembler.hpp"
 38 #include "c1/c1_MacroAssembler.hpp"
 39 #include "gc/g1/c1/g1BarrierSetC1.hpp"
 40 #endif // COMPILER1
 41 #ifdef COMPILER2
 42 #include "gc/g1/c2/g1BarrierSetC2.hpp"
 43 #endif // COMPILER2
 44 
 45 #define __ masm->

227   }
228 
229   __ pop_call_clobbered_registers();
230 
231   __ bind(done);
232 
233 }
234 
235 static void generate_post_barrier_fast_path(MacroAssembler* masm,
236                                             const Register store_addr,
237                                             const Register new_val,
238                                             const Register thread,
239                                             const Register tmp1,
240                                             const Register tmp2,
241                                             Label& done,
242                                             bool new_val_may_be_null) {
243   assert(thread == rthread, "must be");
244   assert_different_registers(store_addr, new_val, thread, tmp1, tmp2, noreg, rscratch1);
245 
246   // Does store cross heap regions?
247   __ eor(tmp1, store_addr, new_val);                     // tmp1 := store address ^ new value
248   __ lsr(tmp1, tmp1, G1HeapRegion::LogOfHRGrainBytes);   // tmp1 := ((store address ^ new value) >> LogOfHRGrainBytes)
249   __ cbz(tmp1, done);
















250   // Crosses regions, storing null?
251   if (new_val_may_be_null) {
252     __ cbz(new_val, done);
253   }
254   // Storing region crossing non-null.
255   __ lsr(tmp1, store_addr, CardTable::card_shift());     // tmp1 := card address relative to card table base
256 
257   Address card_table_addr(thread, in_bytes(G1ThreadLocalData::card_table_base_offset()));
258   __ ldr(tmp2, card_table_addr);                         // tmp2 := card table base address
259   if (UseCondCardMark) {
260     __ ldrb(rscratch1, Address(tmp1, tmp2));             // rscratch1 := card
261     // Instead of loading clean_card_val and comparing, we exploit the fact that
262     // the LSB of non-clean cards is always 0, and the LSB of clean cards 1.
263     __ tbz(rscratch1, 0, done);
264   }
265   static_assert(G1CardTable::dirty_card_val() == 0, "must be to use zr");
266   __ strb(zr, Address(tmp1, tmp2));                      // *(card address) := dirty_card_val
267 }
268 
269 void G1BarrierSetAssembler::g1_write_barrier_post(MacroAssembler* masm,
270                                                   Register store_addr,
271                                                   Register new_val,
272                                                   Register thread,
273                                                   Register tmp1,
274                                                   Register tmp2) {
275   Label done;
276   generate_post_barrier_fast_path(masm, store_addr, new_val, thread, tmp1, tmp2, done, false /* new_val_may_be_null */);
277   __ bind(done);
278 }
279 
280 #if defined(COMPILER2)
281 
282 static void generate_c2_barrier_runtime_call(MacroAssembler* masm, G1BarrierStubC2* stub, const Register arg, const address runtime_path) {
283   SaveLiveRegisters save_registers(masm, stub);
284   if (c_rarg0 != arg) {
285     __ mov(c_rarg0, arg);
286   }
287   __ mov(c_rarg1, rthread);
288   __ mov(rscratch1, runtime_path);
289   __ blr(rscratch1);
290 }
291 
292 void G1BarrierSetAssembler::g1_write_barrier_pre_c2(MacroAssembler* masm,
293                                                     Register obj,
294                                                     Register pre_val,
295                                                     Register thread,
296                                                     Register tmp1,
297                                                     Register tmp2,
298                                                     G1PreBarrierStubC2* stub) {
299   assert(thread == rthread, "must be");
300   assert_different_registers(obj, pre_val, tmp1, tmp2);
301   assert(pre_val != noreg && tmp1 != noreg && tmp2 != noreg, "expecting a register");
302 
303   stub->initialize_registers(obj, pre_val, thread, tmp1, tmp2);
304 
305   generate_pre_barrier_fast_path(masm, thread, tmp1);
306   // If marking is active (*(mark queue active address) != 0), jump to stub (slow path)
307   __ cbnzw(tmp1, *stub->entry());
308 

  6  * under the terms of the GNU General Public License version 2 only, as
  7  * published by the Free Software Foundation.
  8  *
  9  * This code is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 12  * version 2 for more details (a copy is included in the LICENSE file that
 13  * accompanied this code).
 14  *
 15  * You should have received a copy of the GNU General Public License version
 16  * 2 along with this work; if not, write to the Free Software Foundation,
 17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 18  *
 19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 20  * or visit www.oracle.com if you need additional information or have any
 21  * questions.
 22  *
 23  */
 24 
 25 #include "asm/macroAssembler.inline.hpp"
 26 #include "code/aotCodeCache.hpp"
 27 #include "gc/g1/g1BarrierSet.hpp"
 28 #include "gc/g1/g1BarrierSetAssembler.hpp"
 29 #include "gc/g1/g1BarrierSetRuntime.hpp"
 30 #include "gc/g1/g1CardTable.hpp"
 31 #include "gc/g1/g1HeapRegion.hpp"
 32 #include "gc/g1/g1ThreadLocalData.hpp"
 33 #include "gc/shared/collectedHeap.hpp"
 34 #include "interpreter/interp_masm.hpp"
 35 #include "runtime/javaThread.hpp"
 36 #include "runtime/sharedRuntime.hpp"
 37 #ifdef COMPILER1
 38 #include "c1/c1_LIRAssembler.hpp"
 39 #include "c1/c1_MacroAssembler.hpp"
 40 #include "gc/g1/c1/g1BarrierSetC1.hpp"
 41 #endif // COMPILER1
 42 #ifdef COMPILER2
 43 #include "gc/g1/c2/g1BarrierSetC2.hpp"
 44 #endif // COMPILER2
 45 
 46 #define __ masm->

228   }
229 
230   __ pop_call_clobbered_registers();
231 
232   __ bind(done);
233 
234 }
235 
236 static void generate_post_barrier_fast_path(MacroAssembler* masm,
237                                             const Register store_addr,
238                                             const Register new_val,
239                                             const Register thread,
240                                             const Register tmp1,
241                                             const Register tmp2,
242                                             Label& done,
243                                             bool new_val_may_be_null) {
244   assert(thread == rthread, "must be");
245   assert_different_registers(store_addr, new_val, thread, tmp1, tmp2, noreg, rscratch1);
246 
247   // Does store cross heap regions?
248 #if INCLUDE_CDS
249   // AOT code needs to load the barrier grain shift from the aot
250   // runtime constants area in the code cache otherwise we can compile
251   // it as an immediate operand
252   if (AOTCodeCache::is_on_for_dump()) {
253     address grain_shift_address = (address)AOTRuntimeConstants::grain_shift_address();
254     __ eor(tmp1, store_addr, new_val);
255     __ lea(tmp2, ExternalAddress(grain_shift_address));
256     __ ldrb(tmp2, tmp2);
257     __ lsrv(tmp1, tmp1, tmp2);
258     __ cbz(tmp1, done);
259   } else
260 #endif
261   {
262     __ eor(tmp1, store_addr, new_val);                     // tmp1 := store address ^ new value
263     __ lsr(tmp1, tmp1, G1HeapRegion::LogOfHRGrainBytes);   // tmp1 := ((store address ^ new value) >> LogOfHRGrainBytes)
264     __ cbz(tmp1, done);
265   }
266 
267   // Crosses regions, storing null?
268   if (new_val_may_be_null) {
269     __ cbz(new_val, done);
270   }
271   // Storing region crossing non-null.
272   __ lsr(tmp1, store_addr, CardTable::card_shift());     // tmp1 := card address relative to card table base
273 
274   Address card_table_addr(thread, in_bytes(G1ThreadLocalData::card_table_base_offset()));
275   __ ldr(tmp2, card_table_addr);                         // tmp2 := card table base address
276   if (UseCondCardMark) {
277     __ ldrb(rscratch1, Address(tmp1, tmp2));             // rscratch1 := card
278     // Instead of loading clean_card_val and comparing, we exploit the fact that
279     // the LSB of non-clean cards is always 0, and the LSB of clean cards 1.
280     __ tbz(rscratch1, 0, done);
281   }
282   static_assert(G1CardTable::dirty_card_val() == 0, "must be to use zr");
283   __ strb(zr, Address(tmp1, tmp2));                      // *(card address) := dirty_card_val
284 }
285 
286 void G1BarrierSetAssembler::g1_write_barrier_post(MacroAssembler* masm,
287                                                   Register store_addr,
288                                                   Register new_val,
289                                                   Register thread,
290                                                   Register tmp1,
291                                                   Register tmp2) {
292   Label done;
293   generate_post_barrier_fast_path(masm, store_addr, new_val, thread, tmp1, tmp2, done, false /* new_val_may_be_null */);
294   __ bind(done);
295 }
296 
297 #if defined(COMPILER2)
298 
299 static void generate_c2_barrier_runtime_call(MacroAssembler* masm, G1BarrierStubC2* stub, const Register arg, const address runtime_path) {
300   SaveLiveRegisters save_registers(masm, stub);
301   if (c_rarg0 != arg) {
302     __ mov(c_rarg0, arg);
303   }
304   __ mov(c_rarg1, rthread);
305   __ lea(rscratch1, RuntimeAddress(runtime_path));
306   __ blr(rscratch1);
307 }
308 
309 void G1BarrierSetAssembler::g1_write_barrier_pre_c2(MacroAssembler* masm,
310                                                     Register obj,
311                                                     Register pre_val,
312                                                     Register thread,
313                                                     Register tmp1,
314                                                     Register tmp2,
315                                                     G1PreBarrierStubC2* stub) {
316   assert(thread == rthread, "must be");
317   assert_different_registers(obj, pre_val, tmp1, tmp2);
318   assert(pre_val != noreg && tmp1 != noreg && tmp2 != noreg, "expecting a register");
319 
320   stub->initialize_registers(obj, pre_val, thread, tmp1, tmp2);
321 
322   generate_pre_barrier_fast_path(masm, thread, tmp1);
323   // If marking is active (*(mark queue active address) != 0), jump to stub (slow path)
324   __ cbnzw(tmp1, *stub->entry());
325 
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