1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "ci/ciEnv.hpp"
29 #include "code/compiledIC.hpp"
30 #include "compiler/compileTask.hpp"
31 #include "compiler/disassembler.hpp"
32 #include "compiler/oopMap.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/cardTableBarrierSet.hpp"
36 #include "gc/shared/cardTable.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "gc/shared/tlab_globals.hpp"
39 #include "interpreter/bytecodeHistogram.hpp"
40 #include "interpreter/interpreter.hpp"
41 #include "interpreter/interpreterRuntime.hpp"
42 #include "jvm.h"
43 #include "memory/resourceArea.hpp"
44 #include "memory/universe.hpp"
45 #include "nativeInst_aarch64.hpp"
46 #include "oops/accessDecorators.hpp"
47 #include "oops/compressedKlass.inline.hpp"
48 #include "oops/compressedOops.inline.hpp"
49 #include "oops/klass.inline.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/icache.hpp"
52 #include "runtime/interfaceSupport.inline.hpp"
53 #include "runtime/javaThread.hpp"
54 #include "runtime/jniHandles.inline.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/globalDefinitions.hpp"
58 #include "utilities/powerOfTwo.hpp"
59 #ifdef COMPILER1
60 #include "c1/c1_LIRAssembler.hpp"
61 #endif
62 #ifdef COMPILER2
63 #include "oops/oop.hpp"
64 #include "opto/compile.hpp"
65 #include "opto/node.hpp"
66 #include "opto/output.hpp"
67 #endif
68
69 #include <sys/types.h>
70
71 #ifdef PRODUCT
72 #define BLOCK_COMMENT(str) /* nothing */
73 #else
74 #define BLOCK_COMMENT(str) block_comment(str)
75 #endif
76 #define STOP(str) stop(str);
77 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
78
79 #ifdef ASSERT
80 extern "C" void disnm(intptr_t p);
81 #endif
82 // Target-dependent relocation processing
83 //
84 // Instruction sequences whose target may need to be retrieved or
85 // patched are distinguished by their leading instruction, sorting
86 // them into three main instruction groups and related subgroups.
87 //
88 // 1) Branch, Exception and System (insn count = 1)
89 // 1a) Unconditional branch (immediate):
90 // b/bl imm19
91 // 1b) Compare & branch (immediate):
92 // cbz/cbnz Rt imm19
93 // 1c) Test & branch (immediate):
94 // tbz/tbnz Rt imm14
95 // 1d) Conditional branch (immediate):
96 // b.cond imm19
97 //
98 // 2) Loads and Stores (insn count = 1)
99 // 2a) Load register literal:
100 // ldr Rt imm19
101 //
102 // 3) Data Processing Immediate (insn count = 2 or 3)
103 // 3a) PC-rel. addressing
104 // adr/adrp Rx imm21; ldr/str Ry Rx #imm12
105 // adr/adrp Rx imm21; add Ry Rx #imm12
106 // adr/adrp Rx imm21; movk Rx #imm16<<32; ldr/str Ry, [Rx, #offset_in_page]
107 // adr/adrp Rx imm21
108 // adr/adrp Rx imm21; movk Rx #imm16<<32
109 // adr/adrp Rx imm21; movk Rx #imm16<<32; add Ry, Rx, #offset_in_page
110 // The latter form can only happen when the target is an
111 // ExternalAddress, and (by definition) ExternalAddresses don't
112 // move. Because of that property, there is never any need to
113 // patch the last of the three instructions. However,
114 // MacroAssembler::target_addr_for_insn takes all three
115 // instructions into account and returns the correct address.
116 // 3b) Move wide (immediate)
117 // movz Rx #imm16; movk Rx #imm16 << 16; movk Rx #imm16 << 32;
118 //
119 // A switch on a subset of the instruction's bits provides an
120 // efficient dispatch to these subcases.
121 //
122 // insn[28:26] -> main group ('x' == don't care)
123 // 00x -> UNALLOCATED
124 // 100 -> Data Processing Immediate
125 // 101 -> Branch, Exception and System
126 // x1x -> Loads and Stores
127 //
128 // insn[30:25] -> subgroup ('_' == group, 'x' == don't care).
129 // n.b. in some cases extra bits need to be checked to verify the
130 // instruction is as expected
131 //
132 // 1) ... xx101x Branch, Exception and System
133 // 1a) 00___x Unconditional branch (immediate)
134 // 1b) 01___0 Compare & branch (immediate)
135 // 1c) 01___1 Test & branch (immediate)
136 // 1d) 10___0 Conditional branch (immediate)
137 // other Should not happen
138 //
139 // 2) ... xxx1x0 Loads and Stores
140 // 2a) xx1__00 Load/Store register (insn[28] == 1 && insn[24] == 0)
141 // 2aa) x01__00 Load register literal (i.e. requires insn[29] == 0)
142 // strictly should be 64 bit non-FP/SIMD i.e.
143 // 0101_000 (i.e. requires insn[31:24] == 01011000)
144 //
145 // 3) ... xx100x Data Processing Immediate
146 // 3a) xx___00 PC-rel. addressing (n.b. requires insn[24] == 0)
147 // 3b) xx___101 Move wide (immediate) (n.b. requires insn[24:23] == 01)
148 // strictly should be 64 bit movz #imm16<<0
149 // 110___10100 (i.e. requires insn[31:21] == 11010010100)
150 //
151
152 static uint32_t insn_at(address insn_addr, int n) {
153 return ((uint32_t*)insn_addr)[n];
154 }
155
156 template<typename T>
157 class RelocActions : public AllStatic {
158
159 public:
160
161 static int ALWAYSINLINE run(address insn_addr, address &target) {
162 int instructions = 1;
163 uint32_t insn = insn_at(insn_addr, 0);
164
165 uint32_t dispatch = Instruction_aarch64::extract(insn, 30, 25);
166 switch(dispatch) {
167 case 0b001010:
168 case 0b001011: {
169 instructions = T::unconditionalBranch(insn_addr, target);
170 break;
171 }
172 case 0b101010: // Conditional branch (immediate)
173 case 0b011010: { // Compare & branch (immediate)
174 instructions = T::conditionalBranch(insn_addr, target);
175 break;
176 }
177 case 0b011011: {
178 instructions = T::testAndBranch(insn_addr, target);
179 break;
180 }
181 case 0b001100:
182 case 0b001110:
183 case 0b011100:
184 case 0b011110:
185 case 0b101100:
186 case 0b101110:
187 case 0b111100:
188 case 0b111110: {
189 // load/store
190 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
191 // Load register (literal)
192 instructions = T::loadStore(insn_addr, target);
193 break;
194 } else {
195 // nothing to do
196 assert(target == nullptr, "did not expect to relocate target for polling page load");
197 }
198 break;
199 }
200 case 0b001000:
201 case 0b011000:
202 case 0b101000:
203 case 0b111000: {
204 // adr/adrp
205 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
206 int shift = Instruction_aarch64::extract(insn, 31, 31);
207 if (shift) {
208 uint32_t insn2 = insn_at(insn_addr, 1);
209 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
210 Instruction_aarch64::extract(insn, 4, 0) ==
211 Instruction_aarch64::extract(insn2, 9, 5)) {
212 instructions = T::adrp(insn_addr, target, T::adrpMem);
213 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
214 Instruction_aarch64::extract(insn, 4, 0) ==
215 Instruction_aarch64::extract(insn2, 4, 0)) {
216 instructions = T::adrp(insn_addr, target, T::adrpAdd);
217 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
218 Instruction_aarch64::extract(insn, 4, 0) ==
219 Instruction_aarch64::extract(insn2, 4, 0)) {
220 instructions = T::adrp(insn_addr, target, T::adrpMovk);
221 } else {
222 ShouldNotReachHere();
223 }
224 } else {
225 instructions = T::adr(insn_addr, target);
226 }
227 break;
228 }
229 case 0b001001:
230 case 0b011001:
231 case 0b101001:
232 case 0b111001: {
233 instructions = T::immediate(insn_addr, target);
234 break;
235 }
236 default: {
237 ShouldNotReachHere();
238 }
239 }
240
241 T::verify(insn_addr, target);
242 return instructions * NativeInstruction::instruction_size;
243 }
244 };
245
246 class Patcher : public AllStatic {
247 public:
248 static int unconditionalBranch(address insn_addr, address &target) {
249 intptr_t offset = (target - insn_addr) >> 2;
250 Instruction_aarch64::spatch(insn_addr, 25, 0, offset);
251 return 1;
252 }
253 static int conditionalBranch(address insn_addr, address &target) {
254 intptr_t offset = (target - insn_addr) >> 2;
255 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
256 return 1;
257 }
258 static int testAndBranch(address insn_addr, address &target) {
259 intptr_t offset = (target - insn_addr) >> 2;
260 Instruction_aarch64::spatch(insn_addr, 18, 5, offset);
261 return 1;
262 }
263 static int loadStore(address insn_addr, address &target) {
264 intptr_t offset = (target - insn_addr) >> 2;
265 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
266 return 1;
267 }
268 static int adr(address insn_addr, address &target) {
269 #ifdef ASSERT
270 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
271 #endif
272 // PC-rel. addressing
273 ptrdiff_t offset = target - insn_addr;
274 int offset_lo = offset & 3;
275 offset >>= 2;
276 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
277 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
278 return 1;
279 }
280 template<typename U>
281 static int adrp(address insn_addr, address &target, U inner) {
282 int instructions = 1;
283 #ifdef ASSERT
284 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
285 #endif
286 ptrdiff_t offset = target - insn_addr;
287 instructions = 2;
288 precond(inner != nullptr);
289 // Give the inner reloc a chance to modify the target.
290 address adjusted_target = target;
291 instructions = inner(insn_addr, adjusted_target);
292 uintptr_t pc_page = (uintptr_t)insn_addr >> 12;
293 uintptr_t adr_page = (uintptr_t)adjusted_target >> 12;
294 offset = adr_page - pc_page;
295 int offset_lo = offset & 3;
296 offset >>= 2;
297 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
298 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
299 return instructions;
300 }
301 static int adrpMem(address insn_addr, address &target) {
302 uintptr_t dest = (uintptr_t)target;
303 int offset_lo = dest & 0xfff;
304 uint32_t insn2 = insn_at(insn_addr, 1);
305 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
306 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo >> size);
307 guarantee(((dest >> size) << size) == dest, "misaligned target");
308 return 2;
309 }
310 static int adrpAdd(address insn_addr, address &target) {
311 uintptr_t dest = (uintptr_t)target;
312 int offset_lo = dest & 0xfff;
313 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo);
314 return 2;
315 }
316 static int adrpMovk(address insn_addr, address &target) {
317 uintptr_t dest = uintptr_t(target);
318 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 20, 5, (uintptr_t)target >> 32);
319 dest = (dest & 0xffffffffULL) | (uintptr_t(insn_addr) & 0xffff00000000ULL);
320 target = address(dest);
321 return 2;
322 }
323 static int immediate(address insn_addr, address &target) {
324 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 31, 21) == 0b11010010100, "must be");
325 uint64_t dest = (uint64_t)target;
326 // Move wide constant
327 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
328 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
329 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
330 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
331 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
332 return 3;
333 }
334 static void verify(address insn_addr, address &target) {
335 #ifdef ASSERT
336 address address_is = MacroAssembler::target_addr_for_insn(insn_addr);
337 if (!(address_is == target)) {
338 tty->print_cr("%p at %p should be %p", address_is, insn_addr, target);
339 disnm((intptr_t)insn_addr);
340 assert(address_is == target, "should be");
341 }
342 #endif
343 }
344 };
345
346 // If insn1 and insn2 use the same register to form an address, either
347 // by an offsetted LDR or a simple ADD, return the offset. If the
348 // second instruction is an LDR, the offset may be scaled.
349 static bool offset_for(uint32_t insn1, uint32_t insn2, ptrdiff_t &byte_offset) {
350 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
351 Instruction_aarch64::extract(insn1, 4, 0) ==
352 Instruction_aarch64::extract(insn2, 9, 5)) {
353 // Load/store register (unsigned immediate)
354 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
355 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
356 byte_offset <<= size;
357 return true;
358 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
359 Instruction_aarch64::extract(insn1, 4, 0) ==
360 Instruction_aarch64::extract(insn2, 4, 0)) {
361 // add (immediate)
362 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
363 return true;
364 }
365 return false;
366 }
367
368 class AArch64Decoder : public AllStatic {
369 public:
370
371 static int loadStore(address insn_addr, address &target) {
372 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
373 target = insn_addr + (offset << 2);
374 return 1;
375 }
376 static int unconditionalBranch(address insn_addr, address &target) {
377 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 25, 0);
378 target = insn_addr + (offset << 2);
379 return 1;
380 }
381 static int conditionalBranch(address insn_addr, address &target) {
382 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
383 target = address(((uint64_t)insn_addr + (offset << 2)));
384 return 1;
385 }
386 static int testAndBranch(address insn_addr, address &target) {
387 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 18, 5);
388 target = address(((uint64_t)insn_addr + (offset << 2)));
389 return 1;
390 }
391 static int adr(address insn_addr, address &target) {
392 // PC-rel. addressing
393 uint32_t insn = insn_at(insn_addr, 0);
394 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
395 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
396 target = address((uint64_t)insn_addr + offset);
397 return 1;
398 }
399 template<typename U>
400 static int adrp(address insn_addr, address &target, U inner) {
401 uint32_t insn = insn_at(insn_addr, 0);
402 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
403 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
404 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
405 int shift = 12;
406 offset <<= shift;
407 uint64_t target_page = ((uint64_t)insn_addr) + offset;
408 target_page &= ((uint64_t)-1) << shift;
409 target = address(target_page);
410 precond(inner != nullptr);
411 inner(insn_addr, target);
412 return 2;
413 }
414 static int adrpMem(address insn_addr, address &target) {
415 uint32_t insn2 = insn_at(insn_addr, 1);
416 // Load/store register (unsigned immediate)
417 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
418 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
419 byte_offset <<= size;
420 target += byte_offset;
421 return 2;
422 }
423 static int adrpAdd(address insn_addr, address &target) {
424 uint32_t insn2 = insn_at(insn_addr, 1);
425 // add (immediate)
426 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
427 target += byte_offset;
428 return 2;
429 }
430 static int adrpMovk(address insn_addr, address &target) {
431 uint32_t insn2 = insn_at(insn_addr, 1);
432 uint64_t dest = uint64_t(target);
433 dest = (dest & 0xffff0000ffffffff) |
434 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
435 target = address(dest);
436
437 // We know the destination 4k page. Maybe we have a third
438 // instruction.
439 uint32_t insn = insn_at(insn_addr, 0);
440 uint32_t insn3 = insn_at(insn_addr, 2);
441 ptrdiff_t byte_offset;
442 if (offset_for(insn, insn3, byte_offset)) {
443 target += byte_offset;
444 return 3;
445 } else {
446 return 2;
447 }
448 }
449 static int immediate(address insn_addr, address &target) {
450 uint32_t *insns = (uint32_t *)insn_addr;
451 assert(Instruction_aarch64::extract(insns[0], 31, 21) == 0b11010010100, "must be");
452 // Move wide constant: movz, movk, movk. See movptr().
453 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
454 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
455 target = address(uint64_t(Instruction_aarch64::extract(insns[0], 20, 5))
456 + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
457 + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
458 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
459 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
460 return 3;
461 }
462 static void verify(address insn_addr, address &target) {
463 }
464 };
465
466 address MacroAssembler::target_addr_for_insn(address insn_addr) {
467 address target;
468 RelocActions<AArch64Decoder>::run(insn_addr, target);
469 return target;
470 }
471
472 // Patch any kind of instruction; there may be several instructions.
473 // Return the total length (in bytes) of the instructions.
474 int MacroAssembler::pd_patch_instruction_size(address insn_addr, address target) {
475 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
476 return RelocActions<Patcher>::run(insn_addr, target);
477 }
478
479 int MacroAssembler::patch_oop(address insn_addr, address o) {
480 int instructions;
481 unsigned insn = *(unsigned*)insn_addr;
482 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
483
484 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
485
486 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
487 // narrow OOPs by setting the upper 16 bits in the first
488 // instruction.
489 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
490 // Move narrow OOP
491 uint32_t n = CompressedOops::narrow_oop_value(cast_to_oop(o));
492 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
493 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
494 instructions = 2;
495 } else {
496 // Move wide OOP
497 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
498 uintptr_t dest = (uintptr_t)o;
499 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
500 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
501 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
502 instructions = 3;
503 }
504 return instructions * NativeInstruction::instruction_size;
505 }
506
507 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
508 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
509 // We encode narrow ones by setting the upper 16 bits in the first
510 // instruction.
511 NativeInstruction *insn = nativeInstruction_at(insn_addr);
512 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 &&
513 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
514
515 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
516
517 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
518 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
519 return 2 * NativeInstruction::instruction_size;
520 }
521
522 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp) {
523 ldr(tmp, Address(rthread, JavaThread::polling_word_offset()));
524 if (at_return) {
525 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
526 // we may safely use the sp instead to perform the stack watermark check.
527 cmp(in_nmethod ? sp : rfp, tmp);
528 br(Assembler::HI, slow_path);
529 } else {
530 tbnz(tmp, log2i_exact(SafepointMechanism::poll_bit()), slow_path);
531 }
532 }
533
534 void MacroAssembler::rt_call(address dest, Register tmp) {
535 CodeBlob *cb = CodeCache::find_blob(dest);
536 if (cb) {
537 far_call(RuntimeAddress(dest));
538 } else {
539 lea(tmp, RuntimeAddress(dest));
540 blr(tmp);
541 }
542 }
543
544 void MacroAssembler::push_cont_fastpath(Register java_thread) {
545 if (!Continuations::enabled()) return;
546 Label done;
547 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
548 cmp(sp, rscratch1);
549 br(Assembler::LS, done);
550 mov(rscratch1, sp); // we can't use sp as the source in str
551 str(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
552 bind(done);
553 }
554
555 void MacroAssembler::pop_cont_fastpath(Register java_thread) {
556 if (!Continuations::enabled()) return;
557 Label done;
558 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
559 cmp(sp, rscratch1);
560 br(Assembler::LO, done);
561 str(zr, Address(java_thread, JavaThread::cont_fastpath_offset()));
562 bind(done);
563 }
564
565 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
566 // we must set sp to zero to clear frame
567 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
568
569 // must clear fp, so that compiled frames are not confused; it is
570 // possible that we need it only for debugging
571 if (clear_fp) {
572 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
573 }
574
575 // Always clear the pc because it could have been set by make_walkable()
576 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
577 }
578
579 // Calls to C land
580 //
581 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
582 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
583 // has to be reset to 0. This is required to allow proper stack traversal.
584 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
585 Register last_java_fp,
586 Register last_java_pc,
587 Register scratch) {
588
589 if (last_java_pc->is_valid()) {
590 str(last_java_pc, Address(rthread,
591 JavaThread::frame_anchor_offset()
592 + JavaFrameAnchor::last_Java_pc_offset()));
593 }
594
595 // determine last_java_sp register
596 if (last_java_sp == sp) {
597 mov(scratch, sp);
598 last_java_sp = scratch;
599 } else if (!last_java_sp->is_valid()) {
600 last_java_sp = esp;
601 }
602
603 // last_java_fp is optional
604 if (last_java_fp->is_valid()) {
605 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
606 }
607
608 // We must set sp last.
609 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
610 }
611
612 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
613 Register last_java_fp,
614 address last_java_pc,
615 Register scratch) {
616 assert(last_java_pc != nullptr, "must provide a valid PC");
617
618 adr(scratch, last_java_pc);
619 str(scratch, Address(rthread,
620 JavaThread::frame_anchor_offset()
621 + JavaFrameAnchor::last_Java_pc_offset()));
622
623 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
624 }
625
626 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
627 Register last_java_fp,
628 Label &L,
629 Register scratch) {
630 if (L.is_bound()) {
631 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
632 } else {
633 InstructionMark im(this);
634 L.add_patch_at(code(), locator());
635 set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, scratch);
636 }
637 }
638
639 static inline bool target_needs_far_branch(address addr) {
640 if (AOTCodeCache::is_on_for_dump()) {
641 return true;
642 }
643 // codecache size <= 128M
644 if (!MacroAssembler::far_branches()) {
645 return false;
646 }
647 // codecache size > 240M
648 if (MacroAssembler::codestub_branch_needs_far_jump()) {
649 return true;
650 }
651 // codecache size: 128M..240M
652 return !CodeCache::is_non_nmethod(addr);
653 }
654
655 void MacroAssembler::far_call(Address entry, Register tmp) {
656 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
657 assert(CodeCache::find_blob(entry.target()) != nullptr,
658 "destination of far call not found in code cache");
659 assert(entry.rspec().type() == relocInfo::external_word_type
660 || entry.rspec().type() == relocInfo::runtime_call_type
661 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
662 if (target_needs_far_branch(entry.target())) {
663 uint64_t offset;
664 // We can use ADRP here because we know that the total size of
665 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
666 adrp(tmp, entry, offset);
667 add(tmp, tmp, offset);
668 blr(tmp);
669 } else {
670 bl(entry);
671 }
672 }
673
674 int MacroAssembler::far_jump(Address entry, Register tmp) {
675 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
676 assert(CodeCache::find_blob(entry.target()) != nullptr,
677 "destination of far call not found in code cache");
678 assert(entry.rspec().type() == relocInfo::external_word_type
679 || entry.rspec().type() == relocInfo::runtime_call_type
680 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
681 address start = pc();
682 if (target_needs_far_branch(entry.target())) {
683 uint64_t offset;
684 // We can use ADRP here because we know that the total size of
685 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
686 adrp(tmp, entry, offset);
687 add(tmp, tmp, offset);
688 br(tmp);
689 } else {
690 b(entry);
691 }
692 return pc() - start;
693 }
694
695 void MacroAssembler::reserved_stack_check() {
696 // testing if reserved zone needs to be enabled
697 Label no_reserved_zone_enabling;
698
699 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset()));
700 cmp(sp, rscratch1);
701 br(Assembler::LO, no_reserved_zone_enabling);
702
703 enter(); // LR and FP are live.
704 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone)));
705 mov(c_rarg0, rthread);
706 blr(rscratch1);
707 leave();
708
709 // We have already removed our own frame.
710 // throw_delayed_StackOverflowError will think that it's been
711 // called by our caller.
712 lea(rscratch1, RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
713 br(rscratch1);
714 should_not_reach_here();
715
716 bind(no_reserved_zone_enabling);
717 }
718
719 static void pass_arg0(MacroAssembler* masm, Register arg) {
720 if (c_rarg0 != arg ) {
721 masm->mov(c_rarg0, arg);
722 }
723 }
724
725 static void pass_arg1(MacroAssembler* masm, Register arg) {
726 if (c_rarg1 != arg ) {
727 masm->mov(c_rarg1, arg);
728 }
729 }
730
731 static void pass_arg2(MacroAssembler* masm, Register arg) {
732 if (c_rarg2 != arg ) {
733 masm->mov(c_rarg2, arg);
734 }
735 }
736
737 static void pass_arg3(MacroAssembler* masm, Register arg) {
738 if (c_rarg3 != arg ) {
739 masm->mov(c_rarg3, arg);
740 }
741 }
742
743 void MacroAssembler::call_VM_base(Register oop_result,
744 Register java_thread,
745 Register last_java_sp,
746 Label* return_pc,
747 address entry_point,
748 int number_of_arguments,
749 bool check_exceptions) {
750 // determine java_thread register
751 if (!java_thread->is_valid()) {
752 java_thread = rthread;
753 }
754
755 // determine last_java_sp register
756 if (!last_java_sp->is_valid()) {
757 last_java_sp = esp;
758 }
759
760 // debugging support
761 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
762 assert(java_thread == rthread, "unexpected register");
763 #ifdef ASSERT
764 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
765 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
766 #endif // ASSERT
767
768 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
769 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
770
771 // push java thread (becomes first argument of C function)
772
773 mov(c_rarg0, java_thread);
774
775 // set last Java frame before call
776 assert(last_java_sp != rfp, "can't use rfp");
777
778 Label l;
779 set_last_Java_frame(last_java_sp, rfp, return_pc != nullptr ? *return_pc : l, rscratch1);
780
781 // do the call, remove parameters
782 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
783
784 // lr could be poisoned with PAC signature during throw_pending_exception
785 // if it was tail-call optimized by compiler, since lr is not callee-saved
786 // reload it with proper value
787 adr(lr, l);
788
789 // reset last Java frame
790 // Only interpreter should have to clear fp
791 reset_last_Java_frame(true);
792
793 // C++ interp handles this in the interpreter
794 check_and_handle_popframe(java_thread);
795 check_and_handle_earlyret(java_thread);
796
797 if (check_exceptions) {
798 // check for pending exceptions (java_thread is set upon return)
799 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
800 Label ok;
801 cbz(rscratch1, ok);
802 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
803 br(rscratch1);
804 bind(ok);
805 }
806
807 // get oop result if there is one and reset the value in the thread
808 if (oop_result->is_valid()) {
809 get_vm_result_oop(oop_result, java_thread);
810 }
811 }
812
813 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
814 call_VM_base(oop_result, noreg, noreg, nullptr, entry_point, number_of_arguments, check_exceptions);
815 }
816
817 // Check the entry target is always reachable from any branch.
818 static bool is_always_within_branch_range(Address entry) {
819 if (AOTCodeCache::is_on_for_dump()) {
820 return false;
821 }
822 const address target = entry.target();
823
824 if (!CodeCache::contains(target)) {
825 // We always use trampolines for callees outside CodeCache.
826 assert(entry.rspec().type() == relocInfo::runtime_call_type, "non-runtime call of an external target");
827 return false;
828 }
829
830 if (!MacroAssembler::far_branches()) {
831 return true;
832 }
833
834 if (entry.rspec().type() == relocInfo::runtime_call_type) {
835 // Runtime calls are calls of a non-compiled method (stubs, adapters).
836 // Non-compiled methods stay forever in CodeCache.
837 // We check whether the longest possible branch is within the branch range.
838 assert(CodeCache::find_blob(target) != nullptr &&
839 !CodeCache::find_blob(target)->is_nmethod(),
840 "runtime call of compiled method");
841 const address right_longest_branch_start = CodeCache::high_bound() - NativeInstruction::instruction_size;
842 const address left_longest_branch_start = CodeCache::low_bound();
843 const bool is_reachable = Assembler::reachable_from_branch_at(left_longest_branch_start, target) &&
844 Assembler::reachable_from_branch_at(right_longest_branch_start, target);
845 return is_reachable;
846 }
847
848 return false;
849 }
850
851 // Maybe emit a call via a trampoline. If the code cache is small
852 // trampolines won't be emitted.
853 address MacroAssembler::trampoline_call(Address entry) {
854 assert(entry.rspec().type() == relocInfo::runtime_call_type
855 || entry.rspec().type() == relocInfo::opt_virtual_call_type
856 || entry.rspec().type() == relocInfo::static_call_type
857 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
858
859 address target = entry.target();
860
861 if (!is_always_within_branch_range(entry)) {
862 if (!in_scratch_emit_size()) {
863 // We don't want to emit a trampoline if C2 is generating dummy
864 // code during its branch shortening phase.
865 if (entry.rspec().type() == relocInfo::runtime_call_type) {
866 assert(CodeBuffer::supports_shared_stubs(), "must support shared stubs");
867 code()->share_trampoline_for(entry.target(), offset());
868 } else {
869 address stub = emit_trampoline_stub(offset(), target);
870 if (stub == nullptr) {
871 postcond(pc() == badAddress);
872 return nullptr; // CodeCache is full
873 }
874 }
875 }
876 target = pc();
877 }
878
879 address call_pc = pc();
880 relocate(entry.rspec());
881 bl(target);
882
883 postcond(pc() != badAddress);
884 return call_pc;
885 }
886
887 // Emit a trampoline stub for a call to a target which is too far away.
888 //
889 // code sequences:
890 //
891 // call-site:
892 // branch-and-link to <destination> or <trampoline stub>
893 //
894 // Related trampoline stub for this call site in the stub section:
895 // load the call target from the constant pool
896 // branch (LR still points to the call site above)
897
898 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
899 address dest) {
900 // Max stub size: alignment nop, TrampolineStub.
901 address stub = start_a_stub(max_trampoline_stub_size());
902 if (stub == nullptr) {
903 return nullptr; // CodeBuffer::expand failed
904 }
905
906 // Create a trampoline stub relocation which relates this trampoline stub
907 // with the call instruction at insts_call_instruction_offset in the
908 // instructions code-section.
909 align(wordSize);
910 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
911 + insts_call_instruction_offset));
912 const int stub_start_offset = offset();
913
914 // Now, create the trampoline stub's code:
915 // - load the call
916 // - call
917 Label target;
918 ldr(rscratch1, target);
919 br(rscratch1);
920 bind(target);
921 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
922 "should be");
923 emit_int64((int64_t)dest);
924
925 const address stub_start_addr = addr_at(stub_start_offset);
926
927 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
928
929 end_a_stub();
930 return stub_start_addr;
931 }
932
933 int MacroAssembler::max_trampoline_stub_size() {
934 // Max stub size: alignment nop, TrampolineStub.
935 return NativeInstruction::instruction_size + NativeCallTrampolineStub::instruction_size;
936 }
937
938 void MacroAssembler::emit_static_call_stub() {
939 // CompiledDirectCall::set_to_interpreted knows the
940 // exact layout of this stub.
941
942 isb();
943 mov_metadata(rmethod, nullptr);
944
945 // Jump to the entry point of the c2i stub.
946 if (codestub_branch_needs_far_jump()) {
947 movptr(rscratch1, 0);
948 br(rscratch1);
949 } else {
950 b(pc());
951 }
952 }
953
954 int MacroAssembler::static_call_stub_size() {
955 if (!codestub_branch_needs_far_jump()) {
956 // isb; movk; movz; movz; b
957 return 5 * NativeInstruction::instruction_size;
958 }
959 // isb; movk; movz; movz; movk; movz; movz; br
960 return 8 * NativeInstruction::instruction_size;
961 }
962
963 void MacroAssembler::c2bool(Register x) {
964 // implements x == 0 ? 0 : 1
965 // note: must only look at least-significant byte of x
966 // since C-style booleans are stored in one byte
967 // only! (was bug)
968 tst(x, 0xff);
969 cset(x, Assembler::NE);
970 }
971
972 address MacroAssembler::ic_call(address entry, jint method_index) {
973 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
974 movptr(rscratch2, (intptr_t)Universe::non_oop_word());
975 return trampoline_call(Address(entry, rh));
976 }
977
978 int MacroAssembler::ic_check_size() {
979 int extra_instructions = UseCompactObjectHeaders ? 1 : 0;
980 if (target_needs_far_branch(CAST_FROM_FN_PTR(address, SharedRuntime::get_ic_miss_stub()))) {
981 return NativeInstruction::instruction_size * (7 + extra_instructions);
982 } else {
983 return NativeInstruction::instruction_size * (5 + extra_instructions);
984 }
985 }
986
987 int MacroAssembler::ic_check(int end_alignment) {
988 Register receiver = j_rarg0;
989 Register data = rscratch2;
990 Register tmp1 = rscratch1;
991 Register tmp2 = r10;
992
993 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
994 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
995 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
996 // before the inline cache check here, and not after
997 align(end_alignment, offset() + ic_check_size());
998
999 int uep_offset = offset();
1000
1001 if (UseCompactObjectHeaders) {
1002 load_narrow_klass_compact(tmp1, receiver);
1003 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1004 cmpw(tmp1, tmp2);
1005 } else if (UseCompressedClassPointers) {
1006 ldrw(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1007 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1008 cmpw(tmp1, tmp2);
1009 } else {
1010 ldr(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1011 ldr(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1012 cmp(tmp1, tmp2);
1013 }
1014
1015 Label dont;
1016 br(Assembler::EQ, dont);
1017 far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1018 bind(dont);
1019 assert((offset() % end_alignment) == 0, "Misaligned verified entry point");
1020
1021 return uep_offset;
1022 }
1023
1024 // Implementation of call_VM versions
1025
1026 void MacroAssembler::call_VM(Register oop_result,
1027 address entry_point,
1028 bool check_exceptions) {
1029 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1030 }
1031
1032 void MacroAssembler::call_VM(Register oop_result,
1033 address entry_point,
1034 Register arg_1,
1035 bool check_exceptions) {
1036 pass_arg1(this, arg_1);
1037 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1038 }
1039
1040 void MacroAssembler::call_VM(Register oop_result,
1041 address entry_point,
1042 Register arg_1,
1043 Register arg_2,
1044 bool check_exceptions) {
1045 assert_different_registers(arg_1, c_rarg2);
1046 pass_arg2(this, arg_2);
1047 pass_arg1(this, arg_1);
1048 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1049 }
1050
1051 void MacroAssembler::call_VM(Register oop_result,
1052 address entry_point,
1053 Register arg_1,
1054 Register arg_2,
1055 Register arg_3,
1056 bool check_exceptions) {
1057 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1058 assert_different_registers(arg_2, c_rarg3);
1059 pass_arg3(this, arg_3);
1060
1061 pass_arg2(this, arg_2);
1062
1063 pass_arg1(this, arg_1);
1064 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1065 }
1066
1067 void MacroAssembler::call_VM(Register oop_result,
1068 Register last_java_sp,
1069 address entry_point,
1070 int number_of_arguments,
1071 bool check_exceptions) {
1072 call_VM_base(oop_result, rthread, last_java_sp, nullptr, entry_point, number_of_arguments, check_exceptions);
1073 }
1074
1075 void MacroAssembler::call_VM(Register oop_result,
1076 Register last_java_sp,
1077 address entry_point,
1078 Register arg_1,
1079 bool check_exceptions) {
1080 pass_arg1(this, arg_1);
1081 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1082 }
1083
1084 void MacroAssembler::call_VM(Register oop_result,
1085 Register last_java_sp,
1086 address entry_point,
1087 Register arg_1,
1088 Register arg_2,
1089 bool check_exceptions) {
1090
1091 assert_different_registers(arg_1, c_rarg2);
1092 pass_arg2(this, arg_2);
1093 pass_arg1(this, arg_1);
1094 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1095 }
1096
1097 void MacroAssembler::call_VM(Register oop_result,
1098 Register last_java_sp,
1099 address entry_point,
1100 Register arg_1,
1101 Register arg_2,
1102 Register arg_3,
1103 bool check_exceptions) {
1104 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1105 assert_different_registers(arg_2, c_rarg3);
1106 pass_arg3(this, arg_3);
1107 pass_arg2(this, arg_2);
1108 pass_arg1(this, arg_1);
1109 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1110 }
1111
1112
1113 void MacroAssembler::get_vm_result_oop(Register oop_result, Register java_thread) {
1114 ldr(oop_result, Address(java_thread, JavaThread::vm_result_oop_offset()));
1115 str(zr, Address(java_thread, JavaThread::vm_result_oop_offset()));
1116 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1117 }
1118
1119 void MacroAssembler::get_vm_result_metadata(Register metadata_result, Register java_thread) {
1120 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1121 str(zr, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1122 }
1123
1124 void MacroAssembler::align(int modulus) {
1125 align(modulus, offset());
1126 }
1127
1128 // Ensure that the code at target bytes offset from the current offset() is aligned
1129 // according to modulus.
1130 void MacroAssembler::align(int modulus, int target) {
1131 int delta = target - offset();
1132 while ((offset() + delta) % modulus != 0) nop();
1133 }
1134
1135 void MacroAssembler::post_call_nop() {
1136 if (!Continuations::enabled()) {
1137 return;
1138 }
1139 InstructionMark im(this);
1140 relocate(post_call_nop_Relocation::spec());
1141 InlineSkippedInstructionsCounter skipCounter(this);
1142 nop();
1143 movk(zr, 0);
1144 movk(zr, 0);
1145 }
1146
1147 // these are no-ops overridden by InterpreterMacroAssembler
1148
1149 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1150
1151 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1152
1153 // Look up the method for a megamorphic invokeinterface call.
1154 // The target method is determined by <intf_klass, itable_index>.
1155 // The receiver klass is in recv_klass.
1156 // On success, the result will be in method_result, and execution falls through.
1157 // On failure, execution transfers to the given label.
1158 void MacroAssembler::lookup_interface_method(Register recv_klass,
1159 Register intf_klass,
1160 RegisterOrConstant itable_index,
1161 Register method_result,
1162 Register scan_temp,
1163 Label& L_no_such_interface,
1164 bool return_method) {
1165 assert_different_registers(recv_klass, intf_klass, scan_temp);
1166 assert_different_registers(method_result, intf_klass, scan_temp);
1167 assert(recv_klass != method_result || !return_method,
1168 "recv_klass can be destroyed when method isn't needed");
1169 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1170 "caller must use same register for non-constant itable index as for method");
1171
1172 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1173 int vtable_base = in_bytes(Klass::vtable_start_offset());
1174 int itentry_off = in_bytes(itableMethodEntry::method_offset());
1175 int scan_step = itableOffsetEntry::size() * wordSize;
1176 int vte_size = vtableEntry::size_in_bytes();
1177 assert(vte_size == wordSize, "else adjust times_vte_scale");
1178
1179 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1180
1181 // Could store the aligned, prescaled offset in the klass.
1182 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
1183 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
1184 add(scan_temp, scan_temp, vtable_base);
1185
1186 if (return_method) {
1187 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1188 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1189 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
1190 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
1191 if (itentry_off)
1192 add(recv_klass, recv_klass, itentry_off);
1193 }
1194
1195 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
1196 // if (scan->interface() == intf) {
1197 // result = (klass + scan->offset() + itable_index);
1198 // }
1199 // }
1200 Label search, found_method;
1201
1202 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1203 cmp(intf_klass, method_result);
1204 br(Assembler::EQ, found_method);
1205 bind(search);
1206 // Check that the previous entry is non-null. A null entry means that
1207 // the receiver class doesn't implement the interface, and wasn't the
1208 // same as when the caller was compiled.
1209 cbz(method_result, L_no_such_interface);
1210 if (itableOffsetEntry::interface_offset() != 0) {
1211 add(scan_temp, scan_temp, scan_step);
1212 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1213 } else {
1214 ldr(method_result, Address(pre(scan_temp, scan_step)));
1215 }
1216 cmp(intf_klass, method_result);
1217 br(Assembler::NE, search);
1218
1219 bind(found_method);
1220
1221 // Got a hit.
1222 if (return_method) {
1223 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
1224 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0)));
1225 }
1226 }
1227
1228 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
1229 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
1230 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
1231 // The target method is determined by <holder_klass, itable_index>.
1232 // The receiver klass is in recv_klass.
1233 // On success, the result will be in method_result, and execution falls through.
1234 // On failure, execution transfers to the given label.
1235 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
1236 Register holder_klass,
1237 Register resolved_klass,
1238 Register method_result,
1239 Register temp_itbl_klass,
1240 Register scan_temp,
1241 int itable_index,
1242 Label& L_no_such_interface) {
1243 // 'method_result' is only used as output register at the very end of this method.
1244 // Until then we can reuse it as 'holder_offset'.
1245 Register holder_offset = method_result;
1246 assert_different_registers(resolved_klass, recv_klass, holder_klass, temp_itbl_klass, scan_temp, holder_offset);
1247
1248 int vtable_start_offset = in_bytes(Klass::vtable_start_offset());
1249 int itable_offset_entry_size = itableOffsetEntry::size() * wordSize;
1250 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
1251 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
1252
1253 Label L_loop_search_resolved_entry, L_resolved_found, L_holder_found;
1254
1255 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1256 add(recv_klass, recv_klass, vtable_start_offset + ioffset);
1257 // itableOffsetEntry[] itable = recv_klass + Klass::vtable_start_offset() + sizeof(vtableEntry) * recv_klass->_vtable_len;
1258 // temp_itbl_klass = itable[0]._interface;
1259 int vtblEntrySize = vtableEntry::size_in_bytes();
1260 assert(vtblEntrySize == wordSize, "ldr lsl shift amount must be 3");
1261 ldr(temp_itbl_klass, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1262 mov(holder_offset, zr);
1263 // scan_temp = &(itable[0]._interface)
1264 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1265
1266 // Initial checks:
1267 // - if (holder_klass != resolved_klass), go to "scan for resolved"
1268 // - if (itable[0] == holder_klass), shortcut to "holder found"
1269 // - if (itable[0] == 0), no such interface
1270 cmp(resolved_klass, holder_klass);
1271 br(Assembler::NE, L_loop_search_resolved_entry);
1272 cmp(holder_klass, temp_itbl_klass);
1273 br(Assembler::EQ, L_holder_found);
1274 cbz(temp_itbl_klass, L_no_such_interface);
1275
1276 // Loop: Look for holder_klass record in itable
1277 // do {
1278 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1279 // if (temp_itbl_klass == holder_klass) {
1280 // goto L_holder_found; // Found!
1281 // }
1282 // } while (temp_itbl_klass != 0);
1283 // goto L_no_such_interface // Not found.
1284 Label L_search_holder;
1285 bind(L_search_holder);
1286 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1287 cmp(holder_klass, temp_itbl_klass);
1288 br(Assembler::EQ, L_holder_found);
1289 cbnz(temp_itbl_klass, L_search_holder);
1290
1291 b(L_no_such_interface);
1292
1293 // Loop: Look for resolved_class record in itable
1294 // while (true) {
1295 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1296 // if (temp_itbl_klass == 0) {
1297 // goto L_no_such_interface;
1298 // }
1299 // if (temp_itbl_klass == resolved_klass) {
1300 // goto L_resolved_found; // Found!
1301 // }
1302 // if (temp_itbl_klass == holder_klass) {
1303 // holder_offset = scan_temp;
1304 // }
1305 // }
1306 //
1307 Label L_loop_search_resolved;
1308 bind(L_loop_search_resolved);
1309 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1310 bind(L_loop_search_resolved_entry);
1311 cbz(temp_itbl_klass, L_no_such_interface);
1312 cmp(resolved_klass, temp_itbl_klass);
1313 br(Assembler::EQ, L_resolved_found);
1314 cmp(holder_klass, temp_itbl_klass);
1315 br(Assembler::NE, L_loop_search_resolved);
1316 mov(holder_offset, scan_temp);
1317 b(L_loop_search_resolved);
1318
1319 // See if we already have a holder klass. If not, go and scan for it.
1320 bind(L_resolved_found);
1321 cbz(holder_offset, L_search_holder);
1322 mov(scan_temp, holder_offset);
1323
1324 // Finally, scan_temp contains holder_klass vtable offset
1325 bind(L_holder_found);
1326 ldrw(method_result, Address(scan_temp, ooffset - ioffset));
1327 add(recv_klass, recv_klass, itable_index * wordSize + in_bytes(itableMethodEntry::method_offset())
1328 - vtable_start_offset - ioffset); // substract offsets to restore the original value of recv_klass
1329 ldr(method_result, Address(recv_klass, method_result, Address::uxtw(0)));
1330 }
1331
1332 // virtual method calling
1333 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1334 RegisterOrConstant vtable_index,
1335 Register method_result) {
1336 assert(vtableEntry::size() * wordSize == 8,
1337 "adjust the scaling in the code below");
1338 int64_t vtable_offset_in_bytes = in_bytes(Klass::vtable_start_offset() + vtableEntry::method_offset());
1339
1340 if (vtable_index.is_register()) {
1341 lea(method_result, Address(recv_klass,
1342 vtable_index.as_register(),
1343 Address::lsl(LogBytesPerWord)));
1344 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
1345 } else {
1346 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
1347 ldr(method_result,
1348 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0));
1349 }
1350 }
1351
1352 void MacroAssembler::check_klass_subtype(Register sub_klass,
1353 Register super_klass,
1354 Register temp_reg,
1355 Label& L_success) {
1356 Label L_failure;
1357 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
1358 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
1359 bind(L_failure);
1360 }
1361
1362
1363 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1364 Register super_klass,
1365 Register temp_reg,
1366 Label* L_success,
1367 Label* L_failure,
1368 Label* L_slow_path,
1369 Register super_check_offset) {
1370 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset);
1371 bool must_load_sco = ! super_check_offset->is_valid();
1372 if (must_load_sco) {
1373 assert(temp_reg != noreg, "supply either a temp or a register offset");
1374 }
1375
1376 Label L_fallthrough;
1377 int label_nulls = 0;
1378 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1379 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1380 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
1381 assert(label_nulls <= 1, "at most one null in the batch");
1382
1383 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1384 Address super_check_offset_addr(super_klass, sco_offset);
1385
1386 // Hacked jmp, which may only be used just before L_fallthrough.
1387 #define final_jmp(label) \
1388 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1389 else b(label) /*omit semi*/
1390
1391 // If the pointers are equal, we are done (e.g., String[] elements).
1392 // This self-check enables sharing of secondary supertype arrays among
1393 // non-primary types such as array-of-interface. Otherwise, each such
1394 // type would need its own customized SSA.
1395 // We move this check to the front of the fast path because many
1396 // type checks are in fact trivially successful in this manner,
1397 // so we get a nicely predicted branch right at the start of the check.
1398 cmp(sub_klass, super_klass);
1399 br(Assembler::EQ, *L_success);
1400
1401 // Check the supertype display:
1402 if (must_load_sco) {
1403 ldrw(temp_reg, super_check_offset_addr);
1404 super_check_offset = temp_reg;
1405 }
1406
1407 Address super_check_addr(sub_klass, super_check_offset);
1408 ldr(rscratch1, super_check_addr);
1409 cmp(super_klass, rscratch1); // load displayed supertype
1410 br(Assembler::EQ, *L_success);
1411
1412 // This check has worked decisively for primary supers.
1413 // Secondary supers are sought in the super_cache ('super_cache_addr').
1414 // (Secondary supers are interfaces and very deeply nested subtypes.)
1415 // This works in the same check above because of a tricky aliasing
1416 // between the super_cache and the primary super display elements.
1417 // (The 'super_check_addr' can address either, as the case requires.)
1418 // Note that the cache is updated below if it does not help us find
1419 // what we need immediately.
1420 // So if it was a primary super, we can just fail immediately.
1421 // Otherwise, it's the slow path for us (no success at this point).
1422
1423 sub(rscratch1, super_check_offset, in_bytes(Klass::secondary_super_cache_offset()));
1424 if (L_failure == &L_fallthrough) {
1425 cbz(rscratch1, *L_slow_path);
1426 } else {
1427 cbnz(rscratch1, *L_failure);
1428 final_jmp(*L_slow_path);
1429 }
1430
1431 bind(L_fallthrough);
1432
1433 #undef final_jmp
1434 }
1435
1436 // These two are taken from x86, but they look generally useful
1437
1438 // scans count pointer sized words at [addr] for occurrence of value,
1439 // generic
1440 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1441 Register scratch) {
1442 Label Lloop, Lexit;
1443 cbz(count, Lexit);
1444 bind(Lloop);
1445 ldr(scratch, post(addr, wordSize));
1446 cmp(value, scratch);
1447 br(EQ, Lexit);
1448 sub(count, count, 1);
1449 cbnz(count, Lloop);
1450 bind(Lexit);
1451 }
1452
1453 // scans count 4 byte words at [addr] for occurrence of value,
1454 // generic
1455 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1456 Register scratch) {
1457 Label Lloop, Lexit;
1458 cbz(count, Lexit);
1459 bind(Lloop);
1460 ldrw(scratch, post(addr, wordSize));
1461 cmpw(value, scratch);
1462 br(EQ, Lexit);
1463 sub(count, count, 1);
1464 cbnz(count, Lloop);
1465 bind(Lexit);
1466 }
1467
1468 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
1469 Register super_klass,
1470 Register temp_reg,
1471 Register temp2_reg,
1472 Label* L_success,
1473 Label* L_failure,
1474 bool set_cond_codes) {
1475 // NB! Callers may assume that, when temp2_reg is a valid register,
1476 // this code sets it to a nonzero value.
1477
1478 assert_different_registers(sub_klass, super_klass, temp_reg);
1479 if (temp2_reg != noreg)
1480 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1481 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1482
1483 Label L_fallthrough;
1484 int label_nulls = 0;
1485 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1486 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1487 assert(label_nulls <= 1, "at most one null in the batch");
1488
1489 // a couple of useful fields in sub_klass:
1490 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1491 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1492 Address secondary_supers_addr(sub_klass, ss_offset);
1493 Address super_cache_addr( sub_klass, sc_offset);
1494
1495 BLOCK_COMMENT("check_klass_subtype_slow_path");
1496
1497 // Do a linear scan of the secondary super-klass chain.
1498 // This code is rarely used, so simplicity is a virtue here.
1499 // The repne_scan instruction uses fixed registers, which we must spill.
1500 // Don't worry too much about pre-existing connections with the input regs.
1501
1502 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1503 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1504
1505 RegSet pushed_registers;
1506 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1507 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1508
1509 if (super_klass != r0) {
1510 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1511 }
1512
1513 push(pushed_registers, sp);
1514
1515 // Get super_klass value into r0 (even if it was in r5 or r2).
1516 if (super_klass != r0) {
1517 mov(r0, super_klass);
1518 }
1519
1520 #ifndef PRODUCT
1521 incrementw(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
1522 #endif //PRODUCT
1523
1524 // We will consult the secondary-super array.
1525 ldr(r5, secondary_supers_addr);
1526 // Load the array length.
1527 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1528 // Skip to start of data.
1529 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1530
1531 cmp(sp, zr); // Clear Z flag; SP is never zero
1532 // Scan R2 words at [R5] for an occurrence of R0.
1533 // Set NZ/Z based on last compare.
1534 repne_scan(r5, r0, r2, rscratch1);
1535
1536 // Unspill the temp. registers:
1537 pop(pushed_registers, sp);
1538
1539 br(Assembler::NE, *L_failure);
1540
1541 // Success. Cache the super we found and proceed in triumph.
1542
1543 if (UseSecondarySupersCache) {
1544 str(super_klass, super_cache_addr);
1545 }
1546
1547 if (L_success != &L_fallthrough) {
1548 b(*L_success);
1549 }
1550
1551 #undef IS_A_TEMP
1552
1553 bind(L_fallthrough);
1554 }
1555
1556 // If Register r is invalid, remove a new register from
1557 // available_regs, and add new register to regs_to_push.
1558 Register MacroAssembler::allocate_if_noreg(Register r,
1559 RegSetIterator<Register> &available_regs,
1560 RegSet ®s_to_push) {
1561 if (!r->is_valid()) {
1562 r = *available_regs++;
1563 regs_to_push += r;
1564 }
1565 return r;
1566 }
1567
1568 // check_klass_subtype_slow_path_table() looks for super_klass in the
1569 // hash table belonging to super_klass, branching to L_success or
1570 // L_failure as appropriate. This is essentially a shim which
1571 // allocates registers as necessary then calls
1572 // lookup_secondary_supers_table() to do the work. Any of the temp
1573 // regs may be noreg, in which case this logic will chooses some
1574 // registers push and pop them from the stack.
1575 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
1576 Register super_klass,
1577 Register temp_reg,
1578 Register temp2_reg,
1579 Register temp3_reg,
1580 Register result_reg,
1581 FloatRegister vtemp,
1582 Label* L_success,
1583 Label* L_failure,
1584 bool set_cond_codes) {
1585 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
1586
1587 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1588
1589 Label L_fallthrough;
1590 int label_nulls = 0;
1591 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1592 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1593 assert(label_nulls <= 1, "at most one null in the batch");
1594
1595 BLOCK_COMMENT("check_klass_subtype_slow_path");
1596
1597 RegSetIterator<Register> available_regs
1598 = (RegSet::range(r0, r15) - temps - sub_klass - super_klass).begin();
1599
1600 RegSet pushed_regs;
1601
1602 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
1603 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
1604 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
1605 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
1606
1607 push(pushed_regs, sp);
1608
1609 lookup_secondary_supers_table_var(sub_klass,
1610 super_klass,
1611 temp_reg, temp2_reg, temp3_reg, vtemp, result_reg,
1612 nullptr);
1613 cmp(result_reg, zr);
1614
1615 // Unspill the temp. registers:
1616 pop(pushed_regs, sp);
1617
1618 // NB! Callers may assume that, when set_cond_codes is true, this
1619 // code sets temp2_reg to a nonzero value.
1620 if (set_cond_codes) {
1621 mov(temp2_reg, 1);
1622 }
1623
1624 br(Assembler::NE, *L_failure);
1625
1626 if (L_success != &L_fallthrough) {
1627 b(*L_success);
1628 }
1629
1630 bind(L_fallthrough);
1631 }
1632
1633 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1634 Register super_klass,
1635 Register temp_reg,
1636 Register temp2_reg,
1637 Label* L_success,
1638 Label* L_failure,
1639 bool set_cond_codes) {
1640 if (UseSecondarySupersTable) {
1641 check_klass_subtype_slow_path_table
1642 (sub_klass, super_klass, temp_reg, temp2_reg, /*temp3*/noreg, /*result*/noreg,
1643 /*vtemp*/fnoreg,
1644 L_success, L_failure, set_cond_codes);
1645 } else {
1646 check_klass_subtype_slow_path_linear
1647 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
1648 }
1649 }
1650
1651
1652 // Ensure that the inline code and the stub are using the same registers.
1653 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
1654 do { \
1655 assert(r_super_klass == r0 && \
1656 r_array_base == r1 && \
1657 r_array_length == r2 && \
1658 (r_array_index == r3 || r_array_index == noreg) && \
1659 (r_sub_klass == r4 || r_sub_klass == noreg) && \
1660 (r_bitmap == rscratch2 || r_bitmap == noreg) && \
1661 (result == r5 || result == noreg), "registers must match aarch64.ad"); \
1662 } while(0)
1663
1664 bool MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
1665 Register r_super_klass,
1666 Register temp1,
1667 Register temp2,
1668 Register temp3,
1669 FloatRegister vtemp,
1670 Register result,
1671 u1 super_klass_slot,
1672 bool stub_is_near) {
1673 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1674
1675 Label L_fallthrough;
1676
1677 BLOCK_COMMENT("lookup_secondary_supers_table {");
1678
1679 const Register
1680 r_array_base = temp1, // r1
1681 r_array_length = temp2, // r2
1682 r_array_index = temp3, // r3
1683 r_bitmap = rscratch2;
1684
1685 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1686
1687 u1 bit = super_klass_slot;
1688
1689 // Make sure that result is nonzero if the TBZ below misses.
1690 mov(result, 1);
1691
1692 // We're going to need the bitmap in a vector reg and in a core reg,
1693 // so load both now.
1694 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1695 if (bit != 0) {
1696 ldrd(vtemp, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1697 }
1698 // First check the bitmap to see if super_klass might be present. If
1699 // the bit is zero, we are certain that super_klass is not one of
1700 // the secondary supers.
1701 tbz(r_bitmap, bit, L_fallthrough);
1702
1703 // Get the first array index that can contain super_klass into r_array_index.
1704 if (bit != 0) {
1705 shld(vtemp, vtemp, Klass::SECONDARY_SUPERS_TABLE_MASK - bit);
1706 cnt(vtemp, T8B, vtemp);
1707 addv(vtemp, T8B, vtemp);
1708 fmovd(r_array_index, vtemp);
1709 } else {
1710 mov(r_array_index, (u1)1);
1711 }
1712 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1713
1714 // We will consult the secondary-super array.
1715 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1716
1717 // The value i in r_array_index is >= 1, so even though r_array_base
1718 // points to the length, we don't need to adjust it to point to the
1719 // data.
1720 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1721 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1722
1723 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1724 eor(result, result, r_super_klass);
1725 cbz(result, L_fallthrough); // Found a match
1726
1727 // Is there another entry to check? Consult the bitmap.
1728 tbz(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK, L_fallthrough);
1729
1730 // Linear probe.
1731 if (bit != 0) {
1732 ror(r_bitmap, r_bitmap, bit);
1733 }
1734
1735 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1736 // The next slot to be inspected, by the stub we're about to call,
1737 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1738 // have been checked.
1739 Address stub = RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub());
1740 if (stub_is_near) {
1741 bl(stub);
1742 } else {
1743 address call = trampoline_call(stub);
1744 if (call == nullptr) {
1745 return false; // trampoline allocation failed
1746 }
1747 }
1748
1749 BLOCK_COMMENT("} lookup_secondary_supers_table");
1750
1751 bind(L_fallthrough);
1752
1753 if (VerifySecondarySupers) {
1754 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1755 temp1, temp2, result); // r1, r2, r5
1756 }
1757 return true;
1758 }
1759
1760 // At runtime, return 0 in result if r_super_klass is a superclass of
1761 // r_sub_klass, otherwise return nonzero. Use this version of
1762 // lookup_secondary_supers_table() if you don't know ahead of time
1763 // which superclass will be searched for. Used by interpreter and
1764 // runtime stubs. It is larger and has somewhat greater latency than
1765 // the version above, which takes a constant super_klass_slot.
1766 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
1767 Register r_super_klass,
1768 Register temp1,
1769 Register temp2,
1770 Register temp3,
1771 FloatRegister vtemp,
1772 Register result,
1773 Label *L_success) {
1774 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1775
1776 Label L_fallthrough;
1777
1778 BLOCK_COMMENT("lookup_secondary_supers_table {");
1779
1780 const Register
1781 r_array_index = temp3,
1782 slot = rscratch1,
1783 r_bitmap = rscratch2;
1784
1785 ldrb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
1786
1787 // Make sure that result is nonzero if the test below misses.
1788 mov(result, 1);
1789
1790 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1791
1792 // First check the bitmap to see if super_klass might be present. If
1793 // the bit is zero, we are certain that super_klass is not one of
1794 // the secondary supers.
1795
1796 // This next instruction is equivalent to:
1797 // mov(tmp_reg, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1798 // sub(temp2, tmp_reg, slot);
1799 eor(temp2, slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1800 lslv(temp2, r_bitmap, temp2);
1801 tbz(temp2, Klass::SECONDARY_SUPERS_TABLE_SIZE - 1, L_fallthrough);
1802
1803 bool must_save_v0 = (vtemp == fnoreg);
1804 if (must_save_v0) {
1805 // temp1 and result are free, so use them to preserve vtemp
1806 vtemp = v0;
1807 mov(temp1, vtemp, D, 0);
1808 mov(result, vtemp, D, 1);
1809 }
1810
1811 // Get the first array index that can contain super_klass into r_array_index.
1812 mov(vtemp, D, 0, temp2);
1813 cnt(vtemp, T8B, vtemp);
1814 addv(vtemp, T8B, vtemp);
1815 mov(r_array_index, vtemp, D, 0);
1816
1817 if (must_save_v0) {
1818 mov(vtemp, D, 0, temp1 );
1819 mov(vtemp, D, 1, result);
1820 }
1821
1822 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1823
1824 const Register
1825 r_array_base = temp1,
1826 r_array_length = temp2;
1827
1828 // The value i in r_array_index is >= 1, so even though r_array_base
1829 // points to the length, we don't need to adjust it to point to the
1830 // data.
1831 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1832 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1833
1834 // We will consult the secondary-super array.
1835 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1836
1837 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1838 eor(result, result, r_super_klass);
1839 cbz(result, L_success ? *L_success : L_fallthrough); // Found a match
1840
1841 // Is there another entry to check? Consult the bitmap.
1842 rorv(r_bitmap, r_bitmap, slot);
1843 // rol(r_bitmap, r_bitmap, 1);
1844 tbz(r_bitmap, 1, L_fallthrough);
1845
1846 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1847 // The next slot to be inspected, by the logic we're about to call,
1848 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1849 // have been checked.
1850 lookup_secondary_supers_table_slow_path(r_super_klass, r_array_base, r_array_index,
1851 r_bitmap, r_array_length, result, /*is_stub*/false);
1852
1853 BLOCK_COMMENT("} lookup_secondary_supers_table");
1854
1855 bind(L_fallthrough);
1856
1857 if (VerifySecondarySupers) {
1858 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1859 temp1, temp2, result); // r1, r2, r5
1860 }
1861
1862 if (L_success) {
1863 cbz(result, *L_success);
1864 }
1865 }
1866
1867 // Called by code generated by check_klass_subtype_slow_path
1868 // above. This is called when there is a collision in the hashed
1869 // lookup in the secondary supers array.
1870 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
1871 Register r_array_base,
1872 Register r_array_index,
1873 Register r_bitmap,
1874 Register temp1,
1875 Register result,
1876 bool is_stub) {
1877 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, result, rscratch1);
1878
1879 const Register
1880 r_array_length = temp1,
1881 r_sub_klass = noreg; // unused
1882
1883 if (is_stub) {
1884 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1885 }
1886
1887 Label L_fallthrough, L_huge;
1888
1889 // Load the array length.
1890 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1891 // And adjust the array base to point to the data.
1892 // NB! Effectively increments current slot index by 1.
1893 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
1894 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1895
1896 // The bitmap is full to bursting.
1897 // Implicit invariant: BITMAP_FULL implies (length > 0)
1898 assert(Klass::SECONDARY_SUPERS_BITMAP_FULL == ~uintx(0), "");
1899 cmpw(r_array_length, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 2));
1900 br(GT, L_huge);
1901
1902 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
1903 // current slot (at secondary_supers[r_array_index]) has not yet
1904 // been inspected, and r_array_index may be out of bounds if we
1905 // wrapped around the end of the array.
1906
1907 { // This is conventional linear probing, but instead of terminating
1908 // when a null entry is found in the table, we maintain a bitmap
1909 // in which a 0 indicates missing entries.
1910 // As long as the bitmap is not completely full,
1911 // array_length == popcount(bitmap). The array_length check above
1912 // guarantees there are 0s in the bitmap, so the loop eventually
1913 // terminates.
1914 Label L_loop;
1915 bind(L_loop);
1916
1917 // Check for wraparound.
1918 cmp(r_array_index, r_array_length);
1919 csel(r_array_index, zr, r_array_index, GE);
1920
1921 ldr(rscratch1, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1922 eor(result, rscratch1, r_super_klass);
1923 cbz(result, L_fallthrough);
1924
1925 tbz(r_bitmap, 2, L_fallthrough); // look-ahead check (Bit 2); result is non-zero
1926
1927 ror(r_bitmap, r_bitmap, 1);
1928 add(r_array_index, r_array_index, 1);
1929 b(L_loop);
1930 }
1931
1932 { // Degenerate case: more than 64 secondary supers.
1933 // FIXME: We could do something smarter here, maybe a vectorized
1934 // comparison or a binary search, but is that worth any added
1935 // complexity?
1936 bind(L_huge);
1937 cmp(sp, zr); // Clear Z flag; SP is never zero
1938 repne_scan(r_array_base, r_super_klass, r_array_length, rscratch1);
1939 cset(result, NE); // result == 0 iff we got a match.
1940 }
1941
1942 bind(L_fallthrough);
1943 }
1944
1945 // Make sure that the hashed lookup and a linear scan agree.
1946 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
1947 Register r_super_klass,
1948 Register temp1,
1949 Register temp2,
1950 Register result) {
1951 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, result, rscratch1);
1952
1953 const Register
1954 r_array_base = temp1,
1955 r_array_length = temp2;
1956
1957 BLOCK_COMMENT("verify_secondary_supers_table {");
1958
1959 // We will consult the secondary-super array.
1960 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1961
1962 // Load the array length.
1963 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1964 // And adjust the array base to point to the data.
1965 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1966
1967 cmp(sp, zr); // Clear Z flag; SP is never zero
1968 // Scan R2 words at [R5] for an occurrence of R0.
1969 // Set NZ/Z based on last compare.
1970 repne_scan(/*addr*/r_array_base, /*value*/r_super_klass, /*count*/r_array_length, rscratch2);
1971 // rscratch1 == 0 iff we got a match.
1972 cset(rscratch1, NE);
1973
1974 Label passed;
1975 cmp(result, zr);
1976 cset(result, NE); // normalize result to 0/1 for comparison
1977
1978 cmp(rscratch1, result);
1979 br(EQ, passed);
1980 {
1981 mov(r0, r_super_klass); // r0 <- r0
1982 mov(r1, r_sub_klass); // r1 <- r4
1983 mov(r2, /*expected*/rscratch1); // r2 <- r8
1984 mov(r3, result); // r3 <- r5
1985 mov(r4, (address)("mismatch")); // r4 <- const
1986 rt_call(CAST_FROM_FN_PTR(address, Klass::on_secondary_supers_verification_failure), rscratch2);
1987 should_not_reach_here();
1988 }
1989 bind(passed);
1990
1991 BLOCK_COMMENT("} verify_secondary_supers_table");
1992 }
1993
1994 void MacroAssembler::clinit_barrier(Register klass, Register scratch, Label* L_fast_path, Label* L_slow_path) {
1995 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
1996 assert_different_registers(klass, rthread, scratch);
1997
1998 Label L_fallthrough, L_tmp;
1999 if (L_fast_path == nullptr) {
2000 L_fast_path = &L_fallthrough;
2001 } else if (L_slow_path == nullptr) {
2002 L_slow_path = &L_fallthrough;
2003 }
2004 // Fast path check: class is fully initialized
2005 lea(scratch, Address(klass, InstanceKlass::init_state_offset()));
2006 ldarb(scratch, scratch);
2007 cmp(scratch, InstanceKlass::fully_initialized);
2008 br(Assembler::EQ, *L_fast_path);
2009
2010 // Fast path check: current thread is initializer thread
2011 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
2012 cmp(rthread, scratch);
2013
2014 if (L_slow_path == &L_fallthrough) {
2015 br(Assembler::EQ, *L_fast_path);
2016 bind(*L_slow_path);
2017 } else if (L_fast_path == &L_fallthrough) {
2018 br(Assembler::NE, *L_slow_path);
2019 bind(*L_fast_path);
2020 } else {
2021 Unimplemented();
2022 }
2023 }
2024
2025 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
2026 if (!VerifyOops) return;
2027
2028 // Pass register number to verify_oop_subroutine
2029 const char* b = nullptr;
2030 {
2031 ResourceMark rm;
2032 stringStream ss;
2033 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
2034 b = code_string(ss.as_string());
2035 }
2036 BLOCK_COMMENT("verify_oop {");
2037
2038 strip_return_address(); // This might happen within a stack frame.
2039 protect_return_address();
2040 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2041 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2042
2043 mov(r0, reg);
2044 movptr(rscratch1, (uintptr_t)(address)b);
2045
2046 // call indirectly to solve generation ordering problem
2047 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2048 ldr(rscratch2, Address(rscratch2));
2049 blr(rscratch2);
2050
2051 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2052 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2053 authenticate_return_address();
2054
2055 BLOCK_COMMENT("} verify_oop");
2056 }
2057
2058 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
2059 if (!VerifyOops) return;
2060
2061 const char* b = nullptr;
2062 {
2063 ResourceMark rm;
2064 stringStream ss;
2065 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
2066 b = code_string(ss.as_string());
2067 }
2068 BLOCK_COMMENT("verify_oop_addr {");
2069
2070 strip_return_address(); // This might happen within a stack frame.
2071 protect_return_address();
2072 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2073 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2074
2075 // addr may contain sp so we will have to adjust it based on the
2076 // pushes that we just did.
2077 if (addr.uses(sp)) {
2078 lea(r0, addr);
2079 ldr(r0, Address(r0, 4 * wordSize));
2080 } else {
2081 ldr(r0, addr);
2082 }
2083 movptr(rscratch1, (uintptr_t)(address)b);
2084
2085 // call indirectly to solve generation ordering problem
2086 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2087 ldr(rscratch2, Address(rscratch2));
2088 blr(rscratch2);
2089
2090 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2091 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2092 authenticate_return_address();
2093
2094 BLOCK_COMMENT("} verify_oop_addr");
2095 }
2096
2097 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
2098 int extra_slot_offset) {
2099 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
2100 int stackElementSize = Interpreter::stackElementSize;
2101 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
2102 #ifdef ASSERT
2103 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
2104 assert(offset1 - offset == stackElementSize, "correct arithmetic");
2105 #endif
2106 if (arg_slot.is_constant()) {
2107 return Address(esp, arg_slot.as_constant() * stackElementSize
2108 + offset);
2109 } else {
2110 add(rscratch1, esp, arg_slot.as_register(),
2111 ext::uxtx, exact_log2(stackElementSize));
2112 return Address(rscratch1, offset);
2113 }
2114 }
2115
2116 // Handle the receiver type profile update given the "recv" klass.
2117 //
2118 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
2119 // If there are no matching or claimable receiver entries in RD, updates
2120 // the polymorphic counter.
2121 //
2122 // This code expected to run by either the interpreter or JIT-ed code, without
2123 // extra synchronization. For safety, receiver cells are claimed atomically, which
2124 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
2125 // counter updates are not atomic.
2126 //
2127 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
2128 assert_different_registers(recv, mdp, rscratch1, rscratch2);
2129
2130 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
2131 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
2132 int poly_count_offset = in_bytes(CounterData::count_offset());
2133 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
2134 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
2135
2136 // Adjust for MDP offsets.
2137 base_receiver_offset += mdp_offset;
2138 end_receiver_offset += mdp_offset;
2139 poly_count_offset += mdp_offset;
2140
2141 #ifdef ASSERT
2142 // We are about to walk the MDO slots without asking for offsets.
2143 // Check that our math hits all the right spots.
2144 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
2145 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
2146 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
2147 int offset = base_receiver_offset + receiver_step*c;
2148 int count_offset = offset + receiver_to_count_step;
2149 assert(offset == real_recv_offset, "receiver slot math");
2150 assert(count_offset == real_count_offset, "receiver count math");
2151 }
2152 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
2153 assert(poly_count_offset == real_poly_count_offset, "poly counter math");
2154 #endif
2155
2156 // Corner case: no profile table. Increment poly counter and exit.
2157 if (ReceiverTypeData::row_limit() == 0) {
2158 increment(Address(mdp, poly_count_offset), DataLayout::counter_increment);
2159 return;
2160 }
2161
2162 Register offset = rscratch2;
2163
2164 Label L_loop_search_receiver, L_loop_search_empty;
2165 Label L_restart, L_found_recv, L_found_empty, L_polymorphic, L_count_update;
2166
2167 // The code here recognizes three major cases:
2168 // A. Fastest: receiver found in the table
2169 // B. Fast: no receiver in the table, and the table is full
2170 // C. Slow: no receiver in the table, free slots in the table
2171 //
2172 // The case A performance is most important, as perfectly-behaved code would end up
2173 // there, especially with larger TypeProfileWidth. The case B performance is
2174 // important as well, this is where bulk of code would land for normally megamorphic
2175 // cases. The case C performance is not essential, its job is to deal with installation
2176 // races, we optimize for code density instead. Case C needs to make sure that receiver
2177 // rows are only claimed once. This makes sure we never overwrite a row for another
2178 // receiver and never duplicate the receivers in the list, making profile type-accurate.
2179 //
2180 // It is very tempting to handle these cases in a single loop, and claim the first slot
2181 // without checking the rest of the table. But, profiling code should tolerate free slots
2182 // in the table, as class unloading can clear them. After such cleanup, the receiver
2183 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
2184 // to complete, before trying to install new slots. Splitting the code in several tight
2185 // loops also helpfully optimizes for cases A and B.
2186 //
2187 // This code is effectively:
2188 //
2189 // restart:
2190 // // Fastest: receiver is already installed
2191 // for (i = 0; i < receiver_count(); i++) {
2192 // if (receiver(i) == recv) goto found_recv(i);
2193 // }
2194 //
2195 // // Fast: no receiver, but profile is full
2196 // for (i = 0; i < receiver_count(); i++) {
2197 // if (receiver(i) == null) goto found_null(i);
2198 // }
2199 // goto polymorphic
2200 //
2201 // // Slow: try to install receiver
2202 // found_null(i):
2203 // CAS(&receiver(i), null, recv);
2204 // goto restart
2205 //
2206 // polymorphic:
2207 // count++;
2208 // return
2209 //
2210 // found_recv(i):
2211 // *receiver_count(i)++
2212 //
2213
2214 bind(L_restart);
2215
2216 // Fastest: receiver is already installed
2217 mov(offset, base_receiver_offset);
2218 bind(L_loop_search_receiver);
2219 ldr(rscratch1, Address(mdp, offset));
2220 cmp(rscratch1, recv);
2221 br(Assembler::EQ, L_found_recv);
2222 add(offset, offset, receiver_step);
2223 sub(rscratch1, offset, end_receiver_offset);
2224 cbnz(rscratch1, L_loop_search_receiver);
2225
2226 // Fast: no receiver, but profile is full
2227 mov(offset, base_receiver_offset);
2228 bind(L_loop_search_empty);
2229 ldr(rscratch1, Address(mdp, offset));
2230 cbz(rscratch1, L_found_empty);
2231 add(offset, offset, receiver_step);
2232 sub(rscratch1, offset, end_receiver_offset);
2233 cbnz(rscratch1, L_loop_search_empty);
2234 b(L_polymorphic);
2235
2236 // Slow: try to install receiver
2237 bind(L_found_empty);
2238
2239 // Atomically swing receiver slot: null -> recv.
2240 //
2241 // The update uses CAS, which clobbers rscratch1. Therefore, rscratch2
2242 // is used to hold the destination address. This is safe because the
2243 // offset is no longer needed after the address is computed.
2244
2245 lea(rscratch2, Address(mdp, offset));
2246 cmpxchg(/*addr*/ rscratch2, /*expected*/ zr, /*new*/ recv, Assembler::xword,
2247 /*acquire*/ false, /*release*/ false, /*weak*/ true, noreg);
2248
2249 // CAS success means the slot now has the receiver we want. CAS failure means
2250 // something had claimed the slot concurrently: it can be the same receiver we want,
2251 // or something else. Since this is a slow path, we can optimize for code density,
2252 // and just restart the search from the beginning.
2253 b(L_restart);
2254
2255 // Counter updates:
2256
2257 // Increment polymorphic counter instead of receiver slot.
2258 bind(L_polymorphic);
2259 mov(offset, poly_count_offset);
2260 b(L_count_update);
2261
2262 // Found a receiver, convert its slot offset to corresponding count offset.
2263 bind(L_found_recv);
2264 add(offset, offset, receiver_to_count_step);
2265
2266 bind(L_count_update);
2267 increment(Address(mdp, offset), DataLayout::counter_increment);
2268 }
2269
2270
2271 void MacroAssembler::call_VM_leaf_base(address entry_point,
2272 int number_of_arguments,
2273 Label *retaddr) {
2274 Label E, L;
2275
2276 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
2277
2278 mov(rscratch1, RuntimeAddress(entry_point));
2279 blr(rscratch1);
2280 if (retaddr)
2281 bind(*retaddr);
2282
2283 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
2284 }
2285
2286 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2287 call_VM_leaf_base(entry_point, number_of_arguments);
2288 }
2289
2290 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2291 pass_arg0(this, arg_0);
2292 call_VM_leaf_base(entry_point, 1);
2293 }
2294
2295 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2296 assert_different_registers(arg_1, c_rarg0);
2297 pass_arg0(this, arg_0);
2298 pass_arg1(this, arg_1);
2299 call_VM_leaf_base(entry_point, 2);
2300 }
2301
2302 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
2303 Register arg_1, Register arg_2) {
2304 assert_different_registers(arg_1, c_rarg0);
2305 assert_different_registers(arg_2, c_rarg0, c_rarg1);
2306 pass_arg0(this, arg_0);
2307 pass_arg1(this, arg_1);
2308 pass_arg2(this, arg_2);
2309 call_VM_leaf_base(entry_point, 3);
2310 }
2311
2312 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2313 pass_arg0(this, arg_0);
2314 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2315 }
2316
2317 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2318
2319 assert_different_registers(arg_0, c_rarg1);
2320 pass_arg1(this, arg_1);
2321 pass_arg0(this, arg_0);
2322 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2323 }
2324
2325 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2326 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2327 assert_different_registers(arg_1, c_rarg2);
2328 pass_arg2(this, arg_2);
2329 pass_arg1(this, arg_1);
2330 pass_arg0(this, arg_0);
2331 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2332 }
2333
2334 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2335 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
2336 assert_different_registers(arg_1, c_rarg2, c_rarg3);
2337 assert_different_registers(arg_2, c_rarg3);
2338 pass_arg3(this, arg_3);
2339 pass_arg2(this, arg_2);
2340 pass_arg1(this, arg_1);
2341 pass_arg0(this, arg_0);
2342 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2343 }
2344
2345 void MacroAssembler::null_check(Register reg, int offset) {
2346 if (needs_explicit_null_check(offset)) {
2347 // provoke OS null exception if reg is null by
2348 // accessing M[reg] w/o changing any registers
2349 // NOTE: this is plenty to provoke a segv
2350 ldr(zr, Address(reg));
2351 } else {
2352 // nothing to do, (later) access of M[reg + offset]
2353 // will provoke OS null exception if reg is null
2354 }
2355 }
2356
2357 // MacroAssembler protected routines needed to implement
2358 // public methods
2359
2360 void MacroAssembler::mov(Register r, Address dest) {
2361 code_section()->relocate(pc(), dest.rspec());
2362 uint64_t imm64 = (uint64_t)dest.target();
2363 movptr(r, imm64);
2364 }
2365
2366 // Move a constant pointer into r. In AArch64 mode the virtual
2367 // address space is 48 bits in size, so we only need three
2368 // instructions to create a patchable instruction sequence that can
2369 // reach anywhere.
2370 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2371 #ifndef PRODUCT
2372 {
2373 char buffer[64];
2374 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2375 block_comment(buffer);
2376 }
2377 #endif
2378 assert(imm64 < (1ull << 48), "48-bit overflow in address constant");
2379 movz(r, imm64 & 0xffff);
2380 imm64 >>= 16;
2381 movk(r, imm64 & 0xffff, 16);
2382 imm64 >>= 16;
2383 movk(r, imm64 & 0xffff, 32);
2384 }
2385
2386 // Macro to mov replicated immediate to vector register.
2387 // imm64: only the lower 8/16/32 bits are considered for B/H/S type. That is,
2388 // the upper 56/48/32 bits must be zeros for B/H/S type.
2389 // Vd will get the following values for different arrangements in T
2390 // imm64 == hex 000000gh T8B: Vd = ghghghghghghghgh
2391 // imm64 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
2392 // imm64 == hex 0000efgh T4H: Vd = efghefghefghefgh
2393 // imm64 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
2394 // imm64 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
2395 // imm64 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
2396 // imm64 == hex abcdefgh T1D: Vd = 00000000abcdefgh
2397 // imm64 == hex abcdefgh T2D: Vd = 00000000abcdefgh00000000abcdefgh
2398 // Clobbers rscratch1
2399 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64) {
2400 assert(T != T1Q, "unsupported");
2401 if (T == T1D || T == T2D) {
2402 int imm = operand_valid_for_movi_immediate(imm64, T);
2403 if (-1 != imm) {
2404 movi(Vd, T, imm);
2405 } else {
2406 mov(rscratch1, imm64);
2407 dup(Vd, T, rscratch1);
2408 }
2409 return;
2410 }
2411
2412 #ifdef ASSERT
2413 if (T == T8B || T == T16B) assert((imm64 & ~0xff) == 0, "extraneous bits (T8B/T16B)");
2414 if (T == T4H || T == T8H) assert((imm64 & ~0xffff) == 0, "extraneous bits (T4H/T8H)");
2415 if (T == T2S || T == T4S) assert((imm64 & ~0xffffffff) == 0, "extraneous bits (T2S/T4S)");
2416 #endif
2417 int shift = operand_valid_for_movi_immediate(imm64, T);
2418 uint32_t imm32 = imm64 & 0xffffffffULL;
2419 if (shift >= 0) {
2420 movi(Vd, T, (imm32 >> shift) & 0xff, shift);
2421 } else {
2422 movw(rscratch1, imm32);
2423 dup(Vd, T, rscratch1);
2424 }
2425 }
2426
2427 void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64)
2428 {
2429 #ifndef PRODUCT
2430 {
2431 char buffer[64];
2432 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, imm64);
2433 block_comment(buffer);
2434 }
2435 #endif
2436 if (operand_valid_for_logical_immediate(false, imm64)) {
2437 orr(dst, zr, imm64);
2438 } else {
2439 // we can use a combination of MOVZ or MOVN with
2440 // MOVK to build up the constant
2441 uint64_t imm_h[4];
2442 int zero_count = 0;
2443 int neg_count = 0;
2444 int i;
2445 for (i = 0; i < 4; i++) {
2446 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
2447 if (imm_h[i] == 0) {
2448 zero_count++;
2449 } else if (imm_h[i] == 0xffffL) {
2450 neg_count++;
2451 }
2452 }
2453 if (zero_count == 4) {
2454 // one MOVZ will do
2455 movz(dst, 0);
2456 } else if (neg_count == 4) {
2457 // one MOVN will do
2458 movn(dst, 0);
2459 } else if (zero_count == 3) {
2460 for (i = 0; i < 4; i++) {
2461 if (imm_h[i] != 0L) {
2462 movz(dst, (uint32_t)imm_h[i], (i << 4));
2463 break;
2464 }
2465 }
2466 } else if (neg_count == 3) {
2467 // one MOVN will do
2468 for (int i = 0; i < 4; i++) {
2469 if (imm_h[i] != 0xffffL) {
2470 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2471 break;
2472 }
2473 }
2474 } else if (zero_count == 2) {
2475 // one MOVZ and one MOVK will do
2476 for (i = 0; i < 3; i++) {
2477 if (imm_h[i] != 0L) {
2478 movz(dst, (uint32_t)imm_h[i], (i << 4));
2479 i++;
2480 break;
2481 }
2482 }
2483 for (;i < 4; i++) {
2484 if (imm_h[i] != 0L) {
2485 movk(dst, (uint32_t)imm_h[i], (i << 4));
2486 }
2487 }
2488 } else if (neg_count == 2) {
2489 // one MOVN and one MOVK will do
2490 for (i = 0; i < 4; i++) {
2491 if (imm_h[i] != 0xffffL) {
2492 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2493 i++;
2494 break;
2495 }
2496 }
2497 for (;i < 4; i++) {
2498 if (imm_h[i] != 0xffffL) {
2499 movk(dst, (uint32_t)imm_h[i], (i << 4));
2500 }
2501 }
2502 } else if (zero_count == 1) {
2503 // one MOVZ and two MOVKs will do
2504 for (i = 0; i < 4; i++) {
2505 if (imm_h[i] != 0L) {
2506 movz(dst, (uint32_t)imm_h[i], (i << 4));
2507 i++;
2508 break;
2509 }
2510 }
2511 for (;i < 4; i++) {
2512 if (imm_h[i] != 0x0L) {
2513 movk(dst, (uint32_t)imm_h[i], (i << 4));
2514 }
2515 }
2516 } else if (neg_count == 1) {
2517 // one MOVN and two MOVKs will do
2518 for (i = 0; i < 4; i++) {
2519 if (imm_h[i] != 0xffffL) {
2520 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2521 i++;
2522 break;
2523 }
2524 }
2525 for (;i < 4; i++) {
2526 if (imm_h[i] != 0xffffL) {
2527 movk(dst, (uint32_t)imm_h[i], (i << 4));
2528 }
2529 }
2530 } else {
2531 // use a MOVZ and 3 MOVKs (makes it easier to debug)
2532 movz(dst, (uint32_t)imm_h[0], 0);
2533 for (i = 1; i < 4; i++) {
2534 movk(dst, (uint32_t)imm_h[i], (i << 4));
2535 }
2536 }
2537 }
2538 }
2539
2540 void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32)
2541 {
2542 #ifndef PRODUCT
2543 {
2544 char buffer[64];
2545 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX32, imm32);
2546 block_comment(buffer);
2547 }
2548 #endif
2549 if (operand_valid_for_logical_immediate(true, imm32)) {
2550 orrw(dst, zr, imm32);
2551 } else {
2552 // we can use MOVZ, MOVN or two calls to MOVK to build up the
2553 // constant
2554 uint32_t imm_h[2];
2555 imm_h[0] = imm32 & 0xffff;
2556 imm_h[1] = ((imm32 >> 16) & 0xffff);
2557 if (imm_h[0] == 0) {
2558 movzw(dst, imm_h[1], 16);
2559 } else if (imm_h[0] == 0xffff) {
2560 movnw(dst, imm_h[1] ^ 0xffff, 16);
2561 } else if (imm_h[1] == 0) {
2562 movzw(dst, imm_h[0], 0);
2563 } else if (imm_h[1] == 0xffff) {
2564 movnw(dst, imm_h[0] ^ 0xffff, 0);
2565 } else {
2566 // use a MOVZ and MOVK (makes it easier to debug)
2567 movzw(dst, imm_h[0], 0);
2568 movkw(dst, imm_h[1], 16);
2569 }
2570 }
2571 }
2572
2573 // Form an address from base + offset in Rd. Rd may or may
2574 // not actually be used: you must use the Address that is returned.
2575 // It is up to you to ensure that the shift provided matches the size
2576 // of your data.
2577 Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) {
2578 if (Address::offset_ok_for_immed(byte_offset, shift))
2579 // It fits; no need for any heroics
2580 return Address(base, byte_offset);
2581
2582 // Don't do anything clever with negative or misaligned offsets
2583 unsigned mask = (1 << shift) - 1;
2584 if (byte_offset < 0 || byte_offset & mask) {
2585 mov(Rd, byte_offset);
2586 add(Rd, base, Rd);
2587 return Address(Rd);
2588 }
2589
2590 // See if we can do this with two 12-bit offsets
2591 {
2592 uint64_t word_offset = byte_offset >> shift;
2593 uint64_t masked_offset = word_offset & 0xfff000;
2594 if (Address::offset_ok_for_immed(word_offset - masked_offset, 0)
2595 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
2596 add(Rd, base, masked_offset << shift);
2597 word_offset -= masked_offset;
2598 return Address(Rd, word_offset << shift);
2599 }
2600 }
2601
2602 // Do it the hard way
2603 mov(Rd, byte_offset);
2604 add(Rd, base, Rd);
2605 return Address(Rd);
2606 }
2607
2608 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
2609 bool want_remainder, Register scratch)
2610 {
2611 // Full implementation of Java idiv and irem. The function
2612 // returns the (pc) offset of the div instruction - may be needed
2613 // for implicit exceptions.
2614 //
2615 // constraint : ra/rb =/= scratch
2616 // normal case
2617 //
2618 // input : ra: dividend
2619 // rb: divisor
2620 //
2621 // result: either
2622 // quotient (= ra idiv rb)
2623 // remainder (= ra irem rb)
2624
2625 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2626
2627 int idivl_offset = offset();
2628 if (! want_remainder) {
2629 sdivw(result, ra, rb);
2630 } else {
2631 sdivw(scratch, ra, rb);
2632 Assembler::msubw(result, scratch, rb, ra);
2633 }
2634
2635 return idivl_offset;
2636 }
2637
2638 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
2639 bool want_remainder, Register scratch)
2640 {
2641 // Full implementation of Java ldiv and lrem. The function
2642 // returns the (pc) offset of the div instruction - may be needed
2643 // for implicit exceptions.
2644 //
2645 // constraint : ra/rb =/= scratch
2646 // normal case
2647 //
2648 // input : ra: dividend
2649 // rb: divisor
2650 //
2651 // result: either
2652 // quotient (= ra idiv rb)
2653 // remainder (= ra irem rb)
2654
2655 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2656
2657 int idivq_offset = offset();
2658 if (! want_remainder) {
2659 sdiv(result, ra, rb);
2660 } else {
2661 sdiv(scratch, ra, rb);
2662 Assembler::msub(result, scratch, rb, ra);
2663 }
2664
2665 return idivq_offset;
2666 }
2667
2668 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
2669 address prev = pc() - NativeMembar::instruction_size;
2670 address last = code()->last_insn();
2671 if (last != nullptr && nativeInstruction_at(last)->is_Membar() && prev == last) {
2672 NativeMembar *bar = NativeMembar_at(prev);
2673 if (AlwaysMergeDMB) {
2674 bar->set_kind(bar->get_kind() | order_constraint);
2675 BLOCK_COMMENT("merged membar(always)");
2676 return;
2677 }
2678 // Don't promote DMB ST|DMB LD to DMB (a full barrier) because
2679 // doing so would introduce a StoreLoad which the caller did not
2680 // intend
2681 if (bar->get_kind() == order_constraint
2682 || bar->get_kind() == AnyAny
2683 || order_constraint == AnyAny) {
2684 // We are merging two memory barrier instructions. On AArch64 we
2685 // can do this simply by ORing them together.
2686 bar->set_kind(bar->get_kind() | order_constraint);
2687 BLOCK_COMMENT("merged membar");
2688 return;
2689 } else {
2690 // A special case like "DMB ST;DMB LD;DMB ST", the last DMB can be skipped
2691 // We need check the last 2 instructions
2692 address prev2 = prev - NativeMembar::instruction_size;
2693 if (last != code()->last_label() && nativeInstruction_at(prev2)->is_Membar()) {
2694 NativeMembar *bar2 = NativeMembar_at(prev2);
2695 assert(bar2->get_kind() == order_constraint, "it should be merged before");
2696 BLOCK_COMMENT("merged membar(elided)");
2697 return;
2698 }
2699 }
2700 }
2701 code()->set_last_insn(pc());
2702 dmb(Assembler::barrier(order_constraint));
2703 }
2704
2705 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) {
2706 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) {
2707 merge_ldst(rt, adr, size_in_bytes, is_store);
2708 code()->clear_last_insn();
2709 return true;
2710 } else {
2711 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported.");
2712 const uint64_t mask = size_in_bytes - 1;
2713 if (adr.getMode() == Address::base_plus_offset &&
2714 (adr.offset() & mask) == 0) { // only supports base_plus_offset.
2715 code()->set_last_insn(pc());
2716 }
2717 return false;
2718 }
2719 }
2720
2721 void MacroAssembler::ldr(Register Rx, const Address &adr) {
2722 // We always try to merge two adjacent loads into one ldp.
2723 if (!try_merge_ldst(Rx, adr, 8, false)) {
2724 Assembler::ldr(Rx, adr);
2725 }
2726 }
2727
2728 void MacroAssembler::ldrw(Register Rw, const Address &adr) {
2729 // We always try to merge two adjacent loads into one ldp.
2730 if (!try_merge_ldst(Rw, adr, 4, false)) {
2731 Assembler::ldrw(Rw, adr);
2732 }
2733 }
2734
2735 void MacroAssembler::str(Register Rx, const Address &adr) {
2736 // We always try to merge two adjacent stores into one stp.
2737 if (!try_merge_ldst(Rx, adr, 8, true)) {
2738 Assembler::str(Rx, adr);
2739 }
2740 }
2741
2742 void MacroAssembler::strw(Register Rw, const Address &adr) {
2743 // We always try to merge two adjacent stores into one stp.
2744 if (!try_merge_ldst(Rw, adr, 4, true)) {
2745 Assembler::strw(Rw, adr);
2746 }
2747 }
2748
2749 // MacroAssembler routines found actually to be needed
2750
2751 void MacroAssembler::push(Register src)
2752 {
2753 str(src, Address(pre(esp, -1 * wordSize)));
2754 }
2755
2756 void MacroAssembler::pop(Register dst)
2757 {
2758 ldr(dst, Address(post(esp, 1 * wordSize)));
2759 }
2760
2761 // Note: load_unsigned_short used to be called load_unsigned_word.
2762 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2763 int off = offset();
2764 ldrh(dst, src);
2765 return off;
2766 }
2767
2768 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2769 int off = offset();
2770 ldrb(dst, src);
2771 return off;
2772 }
2773
2774 int MacroAssembler::load_signed_short(Register dst, Address src) {
2775 int off = offset();
2776 ldrsh(dst, src);
2777 return off;
2778 }
2779
2780 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2781 int off = offset();
2782 ldrsb(dst, src);
2783 return off;
2784 }
2785
2786 int MacroAssembler::load_signed_short32(Register dst, Address src) {
2787 int off = offset();
2788 ldrshw(dst, src);
2789 return off;
2790 }
2791
2792 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
2793 int off = offset();
2794 ldrsbw(dst, src);
2795 return off;
2796 }
2797
2798 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) {
2799 switch (size_in_bytes) {
2800 case 8: ldr(dst, src); break;
2801 case 4: ldrw(dst, src); break;
2802 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2803 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2804 default: ShouldNotReachHere();
2805 }
2806 }
2807
2808 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes) {
2809 switch (size_in_bytes) {
2810 case 8: str(src, dst); break;
2811 case 4: strw(src, dst); break;
2812 case 2: strh(src, dst); break;
2813 case 1: strb(src, dst); break;
2814 default: ShouldNotReachHere();
2815 }
2816 }
2817
2818 void MacroAssembler::decrementw(Register reg, int value)
2819 {
2820 if (value < 0) { incrementw(reg, -value); return; }
2821 if (value == 0) { return; }
2822 if (value < (1 << 12)) { subw(reg, reg, value); return; }
2823 /* else */ {
2824 guarantee(reg != rscratch2, "invalid dst for register decrement");
2825 movw(rscratch2, (unsigned)value);
2826 subw(reg, reg, rscratch2);
2827 }
2828 }
2829
2830 void MacroAssembler::decrement(Register reg, int value)
2831 {
2832 if (value < 0) { increment(reg, -value); return; }
2833 if (value == 0) { return; }
2834 if (value < (1 << 12)) { sub(reg, reg, value); return; }
2835 /* else */ {
2836 assert(reg != rscratch2, "invalid dst for register decrement");
2837 mov(rscratch2, (uint64_t)value);
2838 sub(reg, reg, rscratch2);
2839 }
2840 }
2841
2842 void MacroAssembler::decrementw(Address dst, int value)
2843 {
2844 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
2845 if (dst.getMode() == Address::literal) {
2846 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2847 lea(rscratch2, dst);
2848 dst = Address(rscratch2);
2849 }
2850 ldrw(rscratch1, dst);
2851 decrementw(rscratch1, value);
2852 strw(rscratch1, dst);
2853 }
2854
2855 void MacroAssembler::decrement(Address dst, int value)
2856 {
2857 assert(!dst.uses(rscratch1), "invalid address for decrement");
2858 if (dst.getMode() == Address::literal) {
2859 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2860 lea(rscratch2, dst);
2861 dst = Address(rscratch2);
2862 }
2863 ldr(rscratch1, dst);
2864 decrement(rscratch1, value);
2865 str(rscratch1, dst);
2866 }
2867
2868 void MacroAssembler::incrementw(Register reg, int value)
2869 {
2870 if (value < 0) { decrementw(reg, -value); return; }
2871 if (value == 0) { return; }
2872 if (value < (1 << 12)) { addw(reg, reg, value); return; }
2873 /* else */ {
2874 assert(reg != rscratch2, "invalid dst for register increment");
2875 movw(rscratch2, (unsigned)value);
2876 addw(reg, reg, rscratch2);
2877 }
2878 }
2879
2880 void MacroAssembler::increment(Register reg, int value)
2881 {
2882 if (value < 0) { decrement(reg, -value); return; }
2883 if (value == 0) { return; }
2884 if (value < (1 << 12)) { add(reg, reg, value); return; }
2885 /* else */ {
2886 assert(reg != rscratch2, "invalid dst for register increment");
2887 movw(rscratch2, (unsigned)value);
2888 add(reg, reg, rscratch2);
2889 }
2890 }
2891
2892 void MacroAssembler::incrementw(Address dst, int value)
2893 {
2894 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2895 if (dst.getMode() == Address::literal) {
2896 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2897 lea(rscratch2, dst);
2898 dst = Address(rscratch2);
2899 }
2900 ldrw(rscratch1, dst);
2901 incrementw(rscratch1, value);
2902 strw(rscratch1, dst);
2903 }
2904
2905 void MacroAssembler::increment(Address dst, int value)
2906 {
2907 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2908 if (dst.getMode() == Address::literal) {
2909 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2910 lea(rscratch2, dst);
2911 dst = Address(rscratch2);
2912 }
2913 ldr(rscratch1, dst);
2914 increment(rscratch1, value);
2915 str(rscratch1, dst);
2916 }
2917
2918 // Push lots of registers in the bit set supplied. Don't push sp.
2919 // Return the number of words pushed
2920 int MacroAssembler::push(unsigned int bitset, Register stack) {
2921 int words_pushed = 0;
2922
2923 // Scan bitset to accumulate register pairs
2924 unsigned char regs[32];
2925 int count = 0;
2926 for (int reg = 0; reg <= 30; reg++) {
2927 if (1 & bitset)
2928 regs[count++] = reg;
2929 bitset >>= 1;
2930 }
2931 regs[count++] = zr->raw_encoding();
2932 count &= ~1; // Only push an even number of regs
2933
2934 if (count) {
2935 stp(as_Register(regs[0]), as_Register(regs[1]),
2936 Address(pre(stack, -count * wordSize)));
2937 words_pushed += 2;
2938 }
2939 for (int i = 2; i < count; i += 2) {
2940 stp(as_Register(regs[i]), as_Register(regs[i+1]),
2941 Address(stack, i * wordSize));
2942 words_pushed += 2;
2943 }
2944
2945 assert(words_pushed == count, "oops, pushed != count");
2946
2947 return count;
2948 }
2949
2950 int MacroAssembler::pop(unsigned int bitset, Register stack) {
2951 int words_pushed = 0;
2952
2953 // Scan bitset to accumulate register pairs
2954 unsigned char regs[32];
2955 int count = 0;
2956 for (int reg = 0; reg <= 30; reg++) {
2957 if (1 & bitset)
2958 regs[count++] = reg;
2959 bitset >>= 1;
2960 }
2961 regs[count++] = zr->raw_encoding();
2962 count &= ~1;
2963
2964 for (int i = 2; i < count; i += 2) {
2965 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
2966 Address(stack, i * wordSize));
2967 words_pushed += 2;
2968 }
2969 if (count) {
2970 ldp(as_Register(regs[0]), as_Register(regs[1]),
2971 Address(post(stack, count * wordSize)));
2972 words_pushed += 2;
2973 }
2974
2975 assert(words_pushed == count, "oops, pushed != count");
2976
2977 return count;
2978 }
2979
2980 // Push lots of registers in the bit set supplied. Don't push sp.
2981 // Return the number of dwords pushed
2982 int MacroAssembler::push_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
2983 int words_pushed = 0;
2984 bool use_sve = false;
2985 int sve_vector_size_in_bytes = 0;
2986
2987 #ifdef COMPILER2
2988 use_sve = Matcher::supports_scalable_vector();
2989 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
2990 #endif
2991
2992 // Scan bitset to accumulate register pairs
2993 unsigned char regs[32];
2994 int count = 0;
2995 for (int reg = 0; reg <= 31; reg++) {
2996 if (1 & bitset)
2997 regs[count++] = reg;
2998 bitset >>= 1;
2999 }
3000
3001 if (count == 0) {
3002 return 0;
3003 }
3004
3005 if (mode == PushPopFull) {
3006 if (use_sve && sve_vector_size_in_bytes > 16) {
3007 mode = PushPopSVE;
3008 } else {
3009 mode = PushPopNeon;
3010 }
3011 }
3012
3013 #ifndef PRODUCT
3014 {
3015 char buffer[48];
3016 if (mode == PushPopSVE) {
3017 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d SVE registers", count);
3018 } else if (mode == PushPopNeon) {
3019 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d Neon registers", count);
3020 } else {
3021 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d fp registers", count);
3022 }
3023 block_comment(buffer);
3024 }
3025 #endif
3026
3027 if (mode == PushPopSVE) {
3028 sub(stack, stack, sve_vector_size_in_bytes * count);
3029 for (int i = 0; i < count; i++) {
3030 sve_str(as_FloatRegister(regs[i]), Address(stack, i));
3031 }
3032 return count * sve_vector_size_in_bytes / 8;
3033 }
3034
3035 if (mode == PushPopNeon) {
3036 if (count == 1) {
3037 strq(as_FloatRegister(regs[0]), Address(pre(stack, -wordSize * 2)));
3038 return 2;
3039 }
3040
3041 bool odd = (count & 1) == 1;
3042 int push_slots = count + (odd ? 1 : 0);
3043
3044 // Always pushing full 128 bit registers.
3045 stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize * 2)));
3046 words_pushed += 2;
3047
3048 for (int i = 2; i + 1 < count; i += 2) {
3049 stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3050 words_pushed += 2;
3051 }
3052
3053 if (odd) {
3054 strq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3055 words_pushed++;
3056 }
3057
3058 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3059 return count * 2;
3060 }
3061
3062 if (mode == PushPopFp) {
3063 bool odd = (count & 1) == 1;
3064 int push_slots = count + (odd ? 1 : 0);
3065
3066 if (count == 1) {
3067 // Stack pointer must be 16 bytes aligned
3068 strd(as_FloatRegister(regs[0]), Address(pre(stack, -push_slots * wordSize)));
3069 return 1;
3070 }
3071
3072 stpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize)));
3073 words_pushed += 2;
3074
3075 for (int i = 2; i + 1 < count; i += 2) {
3076 stpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3077 words_pushed += 2;
3078 }
3079
3080 if (odd) {
3081 // Stack pointer must be 16 bytes aligned
3082 strd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3083 words_pushed++;
3084 }
3085
3086 assert(words_pushed == count, "oops, pushed != count");
3087
3088 return count;
3089 }
3090
3091 return 0;
3092 }
3093
3094 // Return the number of dwords popped
3095 int MacroAssembler::pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
3096 int words_pushed = 0;
3097 bool use_sve = false;
3098 int sve_vector_size_in_bytes = 0;
3099
3100 #ifdef COMPILER2
3101 use_sve = Matcher::supports_scalable_vector();
3102 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
3103 #endif
3104 // Scan bitset to accumulate register pairs
3105 unsigned char regs[32];
3106 int count = 0;
3107 for (int reg = 0; reg <= 31; reg++) {
3108 if (1 & bitset)
3109 regs[count++] = reg;
3110 bitset >>= 1;
3111 }
3112
3113 if (count == 0) {
3114 return 0;
3115 }
3116
3117 if (mode == PushPopFull) {
3118 if (use_sve && sve_vector_size_in_bytes > 16) {
3119 mode = PushPopSVE;
3120 } else {
3121 mode = PushPopNeon;
3122 }
3123 }
3124
3125 #ifndef PRODUCT
3126 {
3127 char buffer[48];
3128 if (mode == PushPopSVE) {
3129 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d SVE registers", count);
3130 } else if (mode == PushPopNeon) {
3131 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d Neon registers", count);
3132 } else {
3133 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d fp registers", count);
3134 }
3135 block_comment(buffer);
3136 }
3137 #endif
3138
3139 if (mode == PushPopSVE) {
3140 for (int i = count - 1; i >= 0; i--) {
3141 sve_ldr(as_FloatRegister(regs[i]), Address(stack, i));
3142 }
3143 add(stack, stack, sve_vector_size_in_bytes * count);
3144 return count * sve_vector_size_in_bytes / 8;
3145 }
3146
3147 if (mode == PushPopNeon) {
3148 if (count == 1) {
3149 ldrq(as_FloatRegister(regs[0]), Address(post(stack, wordSize * 2)));
3150 return 2;
3151 }
3152
3153 bool odd = (count & 1) == 1;
3154 int push_slots = count + (odd ? 1 : 0);
3155
3156 if (odd) {
3157 ldrq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3158 words_pushed++;
3159 }
3160
3161 for (int i = 2; i + 1 < count; i += 2) {
3162 ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3163 words_pushed += 2;
3164 }
3165
3166 ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize * 2)));
3167 words_pushed += 2;
3168
3169 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3170
3171 return count * 2;
3172 }
3173
3174 if (mode == PushPopFp) {
3175 bool odd = (count & 1) == 1;
3176 int push_slots = count + (odd ? 1 : 0);
3177
3178 if (count == 1) {
3179 ldrd(as_FloatRegister(regs[0]), Address(post(stack, push_slots * wordSize)));
3180 return 1;
3181 }
3182
3183 if (odd) {
3184 ldrd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3185 words_pushed++;
3186 }
3187
3188 for (int i = 2; i + 1 < count; i += 2) {
3189 ldpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3190 words_pushed += 2;
3191 }
3192
3193 ldpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize)));
3194 words_pushed += 2;
3195
3196 assert(words_pushed == count, "oops, pushed != count");
3197
3198 return count;
3199 }
3200
3201 return 0;
3202 }
3203
3204 // Return the number of dwords pushed
3205 int MacroAssembler::push_p(unsigned int bitset, Register stack) {
3206 bool use_sve = false;
3207 int sve_predicate_size_in_slots = 0;
3208
3209 #ifdef COMPILER2
3210 use_sve = Matcher::supports_scalable_vector();
3211 if (use_sve) {
3212 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3213 }
3214 #endif
3215
3216 if (!use_sve) {
3217 return 0;
3218 }
3219
3220 unsigned char regs[PRegister::number_of_registers];
3221 int count = 0;
3222 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3223 if (1 & bitset)
3224 regs[count++] = reg;
3225 bitset >>= 1;
3226 }
3227
3228 if (count == 0) {
3229 return 0;
3230 }
3231
3232 int total_push_bytes = align_up(sve_predicate_size_in_slots *
3233 VMRegImpl::stack_slot_size * count, 16);
3234 sub(stack, stack, total_push_bytes);
3235 for (int i = 0; i < count; i++) {
3236 sve_str(as_PRegister(regs[i]), Address(stack, i));
3237 }
3238 return total_push_bytes / 8;
3239 }
3240
3241 // Return the number of dwords popped
3242 int MacroAssembler::pop_p(unsigned int bitset, Register stack) {
3243 bool use_sve = false;
3244 int sve_predicate_size_in_slots = 0;
3245
3246 #ifdef COMPILER2
3247 use_sve = Matcher::supports_scalable_vector();
3248 if (use_sve) {
3249 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3250 }
3251 #endif
3252
3253 if (!use_sve) {
3254 return 0;
3255 }
3256
3257 unsigned char regs[PRegister::number_of_registers];
3258 int count = 0;
3259 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3260 if (1 & bitset)
3261 regs[count++] = reg;
3262 bitset >>= 1;
3263 }
3264
3265 if (count == 0) {
3266 return 0;
3267 }
3268
3269 int total_pop_bytes = align_up(sve_predicate_size_in_slots *
3270 VMRegImpl::stack_slot_size * count, 16);
3271 for (int i = count - 1; i >= 0; i--) {
3272 sve_ldr(as_PRegister(regs[i]), Address(stack, i));
3273 }
3274 add(stack, stack, total_pop_bytes);
3275 return total_pop_bytes / 8;
3276 }
3277
3278 #ifdef ASSERT
3279 void MacroAssembler::verify_heapbase(const char* msg) {
3280 #if 0
3281 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
3282 assert (Universe::heap() != nullptr, "java heap should be initialized");
3283 if (!UseCompressedOops || Universe::ptr_base() == nullptr) {
3284 // rheapbase is allocated as general register
3285 return;
3286 }
3287 if (CheckCompressedOops) {
3288 Label ok;
3289 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
3290 cmpptr(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3291 br(Assembler::EQ, ok);
3292 stop(msg);
3293 bind(ok);
3294 pop(1 << rscratch1->encoding(), sp);
3295 }
3296 #endif
3297 }
3298 #endif
3299
3300 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2) {
3301 assert_different_registers(value, tmp1, tmp2);
3302 Label done, tagged, weak_tagged;
3303
3304 cbz(value, done); // Use null as-is.
3305 tst(value, JNIHandles::tag_mask); // Test for tag.
3306 br(Assembler::NE, tagged);
3307
3308 // Resolve local handle
3309 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp1, tmp2);
3310 verify_oop(value);
3311 b(done);
3312
3313 bind(tagged);
3314 STATIC_ASSERT(JNIHandles::TypeTag::weak_global == 0b1);
3315 tbnz(value, 0, weak_tagged); // Test for weak tag.
3316
3317 // Resolve global handle
3318 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3319 verify_oop(value);
3320 b(done);
3321
3322 bind(weak_tagged);
3323 // Resolve jweak.
3324 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3325 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp1, tmp2);
3326 verify_oop(value);
3327
3328 bind(done);
3329 }
3330
3331 void MacroAssembler::resolve_global_jobject(Register value, Register tmp1, Register tmp2) {
3332 assert_different_registers(value, tmp1, tmp2);
3333 Label done;
3334
3335 cbz(value, done); // Use null as-is.
3336
3337 #ifdef ASSERT
3338 {
3339 STATIC_ASSERT(JNIHandles::TypeTag::global == 0b10);
3340 Label valid_global_tag;
3341 tbnz(value, 1, valid_global_tag); // Test for global tag
3342 stop("non global jobject using resolve_global_jobject");
3343 bind(valid_global_tag);
3344 }
3345 #endif
3346
3347 // Resolve global handle
3348 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3349 verify_oop(value);
3350
3351 bind(done);
3352 }
3353
3354 void MacroAssembler::stop(const char* msg) {
3355 // Skip AOT caching C strings in scratch buffer.
3356 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
3357 BLOCK_COMMENT(str);
3358 // load msg into r0 so we can access it from the signal handler
3359 // ExternalAddress enables saving and restoring via the code cache
3360 lea(c_rarg0, ExternalAddress((address) str));
3361 dcps1(0xdeae);
3362 }
3363
3364 void MacroAssembler::unimplemented(const char* what) {
3365 const char* buf = nullptr;
3366 {
3367 ResourceMark rm;
3368 stringStream ss;
3369 ss.print("unimplemented: %s", what);
3370 buf = code_string(ss.as_string());
3371 }
3372 stop(buf);
3373 }
3374
3375 void MacroAssembler::_assert_asm(Assembler::Condition cc, const char* msg) {
3376 #ifdef ASSERT
3377 Label OK;
3378 br(cc, OK);
3379 stop(msg);
3380 bind(OK);
3381 #endif
3382 }
3383
3384 // If a constant does not fit in an immediate field, generate some
3385 // number of MOV instructions and then perform the operation.
3386 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
3387 add_sub_imm_insn insn1,
3388 add_sub_reg_insn insn2,
3389 bool is32) {
3390 assert(Rd != zr, "Rd = zr and not setting flags?");
3391 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3392 if (fits) {
3393 (this->*insn1)(Rd, Rn, imm);
3394 } else {
3395 if (g_uabs(imm) < (1 << 24)) {
3396 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
3397 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
3398 } else {
3399 assert_different_registers(Rd, Rn);
3400 mov(Rd, imm);
3401 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3402 }
3403 }
3404 }
3405
3406 // Separate vsn which sets the flags. Optimisations are more restricted
3407 // because we must set the flags correctly.
3408 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
3409 add_sub_imm_insn insn1,
3410 add_sub_reg_insn insn2,
3411 bool is32) {
3412 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3413 if (fits) {
3414 (this->*insn1)(Rd, Rn, imm);
3415 } else {
3416 assert_different_registers(Rd, Rn);
3417 assert(Rd != zr, "overflow in immediate operand");
3418 mov(Rd, imm);
3419 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3420 }
3421 }
3422
3423
3424 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
3425 if (increment.is_register()) {
3426 add(Rd, Rn, increment.as_register());
3427 } else {
3428 add(Rd, Rn, increment.as_constant());
3429 }
3430 }
3431
3432 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
3433 if (increment.is_register()) {
3434 addw(Rd, Rn, increment.as_register());
3435 } else {
3436 addw(Rd, Rn, increment.as_constant());
3437 }
3438 }
3439
3440 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
3441 if (decrement.is_register()) {
3442 sub(Rd, Rn, decrement.as_register());
3443 } else {
3444 sub(Rd, Rn, decrement.as_constant());
3445 }
3446 }
3447
3448 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
3449 if (decrement.is_register()) {
3450 subw(Rd, Rn, decrement.as_register());
3451 } else {
3452 subw(Rd, Rn, decrement.as_constant());
3453 }
3454 }
3455
3456 void MacroAssembler::reinit_heapbase()
3457 {
3458 if (UseCompressedOops) {
3459 if (Universe::is_fully_initialized()) {
3460 mov(rheapbase, CompressedOops::base());
3461 } else {
3462 lea(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3463 ldr(rheapbase, Address(rheapbase));
3464 }
3465 }
3466 }
3467
3468 // A generic CAS; success or failure is in the EQ flag. A weak CAS
3469 // doesn't retry and may fail spuriously. If the oldval is wanted,
3470 // Pass a register for the result, otherwise pass noreg.
3471
3472 // Clobbers rscratch1
3473 void MacroAssembler::cmpxchg(Register addr, Register expected,
3474 Register new_val,
3475 enum operand_size size,
3476 bool acquire, bool release,
3477 bool weak,
3478 Register result) {
3479 if (result == noreg) result = rscratch1;
3480 BLOCK_COMMENT("cmpxchg {");
3481 if (UseLSE) {
3482 mov(result, expected);
3483 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
3484 compare_eq(result, expected, size);
3485 #ifdef ASSERT
3486 // Poison rscratch1 which is written on !UseLSE branch
3487 mov(rscratch1, 0x1f1f1f1f1f1f1f1f);
3488 #endif
3489 } else {
3490 Label retry_load, done;
3491 prfm(Address(addr), PSTL1STRM);
3492 bind(retry_load);
3493 load_exclusive(result, addr, size, acquire);
3494 compare_eq(result, expected, size);
3495 br(Assembler::NE, done);
3496 store_exclusive(rscratch1, new_val, addr, size, release);
3497 if (weak) {
3498 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
3499 } else {
3500 cbnzw(rscratch1, retry_load);
3501 }
3502 bind(done);
3503 }
3504 BLOCK_COMMENT("} cmpxchg");
3505 }
3506
3507 // A generic comparison. Only compares for equality, clobbers rscratch1.
3508 void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) {
3509 if (size == xword) {
3510 cmp(rm, rn);
3511 } else if (size == word) {
3512 cmpw(rm, rn);
3513 } else if (size == halfword) {
3514 eorw(rscratch1, rm, rn);
3515 ands(zr, rscratch1, 0xffff);
3516 } else if (size == byte) {
3517 eorw(rscratch1, rm, rn);
3518 ands(zr, rscratch1, 0xff);
3519 } else {
3520 ShouldNotReachHere();
3521 }
3522 }
3523
3524
3525 static bool different(Register a, RegisterOrConstant b, Register c) {
3526 if (b.is_constant())
3527 return a != c;
3528 else
3529 return a != b.as_register() && a != c && b.as_register() != c;
3530 }
3531
3532 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \
3533 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \
3534 if (UseLSE) { \
3535 prev = prev->is_valid() ? prev : zr; \
3536 if (incr.is_register()) { \
3537 AOP(sz, incr.as_register(), prev, addr); \
3538 } else { \
3539 mov(rscratch2, incr.as_constant()); \
3540 AOP(sz, rscratch2, prev, addr); \
3541 } \
3542 return; \
3543 } \
3544 Register result = rscratch2; \
3545 if (prev->is_valid()) \
3546 result = different(prev, incr, addr) ? prev : rscratch2; \
3547 \
3548 Label retry_load; \
3549 prfm(Address(addr), PSTL1STRM); \
3550 bind(retry_load); \
3551 LDXR(result, addr); \
3552 OP(rscratch1, result, incr); \
3553 STXR(rscratch2, rscratch1, addr); \
3554 cbnzw(rscratch2, retry_load); \
3555 if (prev->is_valid() && prev != result) { \
3556 IOP(prev, rscratch1, incr); \
3557 } \
3558 }
3559
3560 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword)
3561 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
3562 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword)
3563 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word)
3564
3565 #undef ATOMIC_OP
3566
3567 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \
3568 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
3569 if (UseLSE) { \
3570 prev = prev->is_valid() ? prev : zr; \
3571 AOP(sz, newv, prev, addr); \
3572 return; \
3573 } \
3574 Register result = rscratch2; \
3575 if (prev->is_valid()) \
3576 result = different(prev, newv, addr) ? prev : rscratch2; \
3577 \
3578 Label retry_load; \
3579 prfm(Address(addr), PSTL1STRM); \
3580 bind(retry_load); \
3581 LDXR(result, addr); \
3582 STXR(rscratch1, newv, addr); \
3583 cbnzw(rscratch1, retry_load); \
3584 if (prev->is_valid() && prev != result) \
3585 mov(prev, result); \
3586 }
3587
3588 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
3589 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
3590 ATOMIC_XCHG(xchgl, swpl, ldxr, stlxr, Assembler::xword)
3591 ATOMIC_XCHG(xchglw, swpl, ldxrw, stlxrw, Assembler::word)
3592 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
3593 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
3594
3595 #undef ATOMIC_XCHG
3596
3597 #ifndef PRODUCT
3598 extern "C" void findpc(intptr_t x);
3599 #endif
3600
3601 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
3602 {
3603 // In order to get locks to work, we need to fake a in_VM state
3604 if (ShowMessageBoxOnError) {
3605 JavaThread* thread = JavaThread::current();
3606 thread->set_thread_state(_thread_in_vm);
3607 #ifndef PRODUCT
3608 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
3609 ttyLocker ttyl;
3610 BytecodeCounter::print();
3611 }
3612 #endif
3613 if (os::message_box(msg, "Execution stopped, print registers?")) {
3614 ttyLocker ttyl;
3615 tty->print_cr(" pc = 0x%016" PRIx64, pc);
3616 #ifndef PRODUCT
3617 tty->cr();
3618 findpc(pc);
3619 tty->cr();
3620 #endif
3621 tty->print_cr(" r0 = 0x%016" PRIx64, regs[0]);
3622 tty->print_cr(" r1 = 0x%016" PRIx64, regs[1]);
3623 tty->print_cr(" r2 = 0x%016" PRIx64, regs[2]);
3624 tty->print_cr(" r3 = 0x%016" PRIx64, regs[3]);
3625 tty->print_cr(" r4 = 0x%016" PRIx64, regs[4]);
3626 tty->print_cr(" r5 = 0x%016" PRIx64, regs[5]);
3627 tty->print_cr(" r6 = 0x%016" PRIx64, regs[6]);
3628 tty->print_cr(" r7 = 0x%016" PRIx64, regs[7]);
3629 tty->print_cr(" r8 = 0x%016" PRIx64, regs[8]);
3630 tty->print_cr(" r9 = 0x%016" PRIx64, regs[9]);
3631 tty->print_cr("r10 = 0x%016" PRIx64, regs[10]);
3632 tty->print_cr("r11 = 0x%016" PRIx64, regs[11]);
3633 tty->print_cr("r12 = 0x%016" PRIx64, regs[12]);
3634 tty->print_cr("r13 = 0x%016" PRIx64, regs[13]);
3635 tty->print_cr("r14 = 0x%016" PRIx64, regs[14]);
3636 tty->print_cr("r15 = 0x%016" PRIx64, regs[15]);
3637 tty->print_cr("r16 = 0x%016" PRIx64, regs[16]);
3638 tty->print_cr("r17 = 0x%016" PRIx64, regs[17]);
3639 tty->print_cr("r18 = 0x%016" PRIx64, regs[18]);
3640 tty->print_cr("r19 = 0x%016" PRIx64, regs[19]);
3641 tty->print_cr("r20 = 0x%016" PRIx64, regs[20]);
3642 tty->print_cr("r21 = 0x%016" PRIx64, regs[21]);
3643 tty->print_cr("r22 = 0x%016" PRIx64, regs[22]);
3644 tty->print_cr("r23 = 0x%016" PRIx64, regs[23]);
3645 tty->print_cr("r24 = 0x%016" PRIx64, regs[24]);
3646 tty->print_cr("r25 = 0x%016" PRIx64, regs[25]);
3647 tty->print_cr("r26 = 0x%016" PRIx64, regs[26]);
3648 tty->print_cr("r27 = 0x%016" PRIx64, regs[27]);
3649 tty->print_cr("r28 = 0x%016" PRIx64, regs[28]);
3650 tty->print_cr("r30 = 0x%016" PRIx64, regs[30]);
3651 tty->print_cr("r31 = 0x%016" PRIx64, regs[31]);
3652 BREAKPOINT;
3653 }
3654 }
3655 fatal("DEBUG MESSAGE: %s", msg);
3656 }
3657
3658 RegSet MacroAssembler::call_clobbered_gp_registers() {
3659 RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2);
3660 #ifndef R18_RESERVED
3661 regs += r18_tls;
3662 #endif
3663 return regs;
3664 }
3665
3666 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
3667 int step = 4 * wordSize;
3668 push(call_clobbered_gp_registers() - exclude, sp);
3669 sub(sp, sp, step);
3670 mov(rscratch1, -step);
3671 // Push v0-v7, v16-v31.
3672 for (int i = 31; i>= 4; i -= 4) {
3673 if (i <= v7->encoding() || i >= v16->encoding())
3674 st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1),
3675 as_FloatRegister(i), T1D, Address(post(sp, rscratch1)));
3676 }
3677 st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2),
3678 as_FloatRegister(3), T1D, Address(sp));
3679 }
3680
3681 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
3682 for (int i = 0; i < 32; i += 4) {
3683 if (i <= v7->encoding() || i >= v16->encoding())
3684 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3685 as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
3686 }
3687
3688 reinitialize_ptrue();
3689
3690 pop(call_clobbered_gp_registers() - exclude, sp);
3691 }
3692
3693 void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve,
3694 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3695 push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
3696 if (save_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3697 sub(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3698 for (int i = 0; i < FloatRegister::number_of_registers; i++) {
3699 sve_str(as_FloatRegister(i), Address(sp, i));
3700 }
3701 } else {
3702 int step = (save_vectors ? 8 : 4) * wordSize;
3703 mov(rscratch1, -step);
3704 sub(sp, sp, step);
3705 for (int i = 28; i >= 4; i -= 4) {
3706 st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3707 as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1)));
3708 }
3709 st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp);
3710 }
3711 if (save_vectors && use_sve && total_predicate_in_bytes > 0) {
3712 sub(sp, sp, total_predicate_in_bytes);
3713 for (int i = 0; i < PRegister::number_of_registers; i++) {
3714 sve_str(as_PRegister(i), Address(sp, i));
3715 }
3716 }
3717 }
3718
3719 void MacroAssembler::pop_CPU_state(bool restore_vectors, bool use_sve,
3720 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3721 if (restore_vectors && use_sve && total_predicate_in_bytes > 0) {
3722 for (int i = PRegister::number_of_registers - 1; i >= 0; i--) {
3723 sve_ldr(as_PRegister(i), Address(sp, i));
3724 }
3725 add(sp, sp, total_predicate_in_bytes);
3726 }
3727 if (restore_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3728 for (int i = FloatRegister::number_of_registers - 1; i >= 0; i--) {
3729 sve_ldr(as_FloatRegister(i), Address(sp, i));
3730 }
3731 add(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3732 } else {
3733 int step = (restore_vectors ? 8 : 4) * wordSize;
3734 for (int i = 0; i <= 28; i += 4)
3735 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3736 as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step)));
3737 }
3738
3739 // We may use predicate registers and rely on ptrue with SVE,
3740 // regardless of wide vector (> 8 bytes) used or not.
3741 if (use_sve) {
3742 reinitialize_ptrue();
3743 }
3744
3745 // integer registers except lr & sp
3746 pop(RegSet::range(r0, r17), sp);
3747 #ifdef R18_RESERVED
3748 ldp(zr, r19, Address(post(sp, 2 * wordSize)));
3749 pop(RegSet::range(r20, r29), sp);
3750 #else
3751 pop(RegSet::range(r18_tls, r29), sp);
3752 #endif
3753 }
3754
3755 /**
3756 * Helpers for multiply_to_len().
3757 */
3758 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
3759 Register src1, Register src2) {
3760 adds(dest_lo, dest_lo, src1);
3761 adc(dest_hi, dest_hi, zr);
3762 adds(dest_lo, dest_lo, src2);
3763 adc(final_dest_hi, dest_hi, zr);
3764 }
3765
3766 // Generate an address from (r + r1 extend offset). "size" is the
3767 // size of the operand. The result may be in rscratch2.
3768 Address MacroAssembler::offsetted_address(Register r, Register r1,
3769 Address::extend ext, int offset, int size) {
3770 if (offset || (ext.shift() % size != 0)) {
3771 lea(rscratch2, Address(r, r1, ext));
3772 return Address(rscratch2, offset);
3773 } else {
3774 return Address(r, r1, ext);
3775 }
3776 }
3777
3778 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
3779 {
3780 assert(offset >= 0, "spill to negative address?");
3781 // Offset reachable ?
3782 // Not aligned - 9 bits signed offset
3783 // Aligned - 12 bits unsigned offset shifted
3784 Register base = sp;
3785 if ((offset & (size-1)) && offset >= (1<<8)) {
3786 add(tmp, base, offset & ((1<<12)-1));
3787 base = tmp;
3788 offset &= -1u<<12;
3789 }
3790
3791 if (offset >= (1<<12) * size) {
3792 add(tmp, base, offset & (((1<<12)-1)<<12));
3793 base = tmp;
3794 offset &= ~(((1<<12)-1)<<12);
3795 }
3796
3797 return Address(base, offset);
3798 }
3799
3800 Address MacroAssembler::sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp) {
3801 assert(offset >= 0, "spill to negative address?");
3802
3803 Register base = sp;
3804
3805 // An immediate offset in the range 0 to 255 which is multiplied
3806 // by the current vector or predicate register size in bytes.
3807 if (offset % sve_reg_size_in_bytes == 0 && offset < ((1<<8)*sve_reg_size_in_bytes)) {
3808 return Address(base, offset / sve_reg_size_in_bytes);
3809 }
3810
3811 add(tmp, base, offset);
3812 return Address(tmp);
3813 }
3814
3815 // Checks whether offset is aligned.
3816 // Returns true if it is, else false.
3817 bool MacroAssembler::merge_alignment_check(Register base,
3818 size_t size,
3819 int64_t cur_offset,
3820 int64_t prev_offset) const {
3821 if (AvoidUnalignedAccesses) {
3822 if (base == sp) {
3823 // Checks whether low offset if aligned to pair of registers.
3824 int64_t pair_mask = size * 2 - 1;
3825 int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3826 return (offset & pair_mask) == 0;
3827 } else { // If base is not sp, we can't guarantee the access is aligned.
3828 return false;
3829 }
3830 } else {
3831 int64_t mask = size - 1;
3832 // Load/store pair instruction only supports element size aligned offset.
3833 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
3834 }
3835 }
3836
3837 // Checks whether current and previous loads/stores can be merged.
3838 // Returns true if it can be merged, else false.
3839 bool MacroAssembler::ldst_can_merge(Register rt,
3840 const Address &adr,
3841 size_t cur_size_in_bytes,
3842 bool is_store) const {
3843 address prev = pc() - NativeInstruction::instruction_size;
3844 address last = code()->last_insn();
3845
3846 if (last == nullptr || !nativeInstruction_at(last)->is_Imm_LdSt()) {
3847 return false;
3848 }
3849
3850 if (adr.getMode() != Address::base_plus_offset || prev != last) {
3851 return false;
3852 }
3853
3854 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3855 size_t prev_size_in_bytes = prev_ldst->size_in_bytes();
3856
3857 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging.");
3858 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging.");
3859
3860 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) {
3861 return false;
3862 }
3863
3864 int64_t max_offset = 63 * prev_size_in_bytes;
3865 int64_t min_offset = -64 * prev_size_in_bytes;
3866
3867 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
3868
3869 // Only same base can be merged.
3870 if (adr.base() != prev_ldst->base()) {
3871 return false;
3872 }
3873
3874 int64_t cur_offset = adr.offset();
3875 int64_t prev_offset = prev_ldst->offset();
3876 size_t diff = abs(cur_offset - prev_offset);
3877 if (diff != prev_size_in_bytes) {
3878 return false;
3879 }
3880
3881 // Following cases can not be merged:
3882 // ldr x2, [x2, #8]
3883 // ldr x3, [x2, #16]
3884 // or:
3885 // ldr x2, [x3, #8]
3886 // ldr x2, [x3, #16]
3887 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL.
3888 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) {
3889 return false;
3890 }
3891
3892 int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3893 // Offset range must be in ldp/stp instruction's range.
3894 if (low_offset > max_offset || low_offset < min_offset) {
3895 return false;
3896 }
3897
3898 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) {
3899 return true;
3900 }
3901
3902 return false;
3903 }
3904
3905 // Merge current load/store with previous load/store into ldp/stp.
3906 void MacroAssembler::merge_ldst(Register rt,
3907 const Address &adr,
3908 size_t cur_size_in_bytes,
3909 bool is_store) {
3910
3911 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged.");
3912
3913 Register rt_low, rt_high;
3914 address prev = pc() - NativeInstruction::instruction_size;
3915 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3916
3917 int64_t offset;
3918
3919 if (adr.offset() < prev_ldst->offset()) {
3920 offset = adr.offset();
3921 rt_low = rt;
3922 rt_high = prev_ldst->target();
3923 } else {
3924 offset = prev_ldst->offset();
3925 rt_low = prev_ldst->target();
3926 rt_high = rt;
3927 }
3928
3929 Address adr_p = Address(prev_ldst->base(), offset);
3930 // Overwrite previous generated binary.
3931 code_section()->set_end(prev);
3932
3933 const size_t sz = prev_ldst->size_in_bytes();
3934 assert(sz == 8 || sz == 4, "only supports 64/32bit merging.");
3935 if (!is_store) {
3936 BLOCK_COMMENT("merged ldr pair");
3937 if (sz == 8) {
3938 ldp(rt_low, rt_high, adr_p);
3939 } else {
3940 ldpw(rt_low, rt_high, adr_p);
3941 }
3942 } else {
3943 BLOCK_COMMENT("merged str pair");
3944 if (sz == 8) {
3945 stp(rt_low, rt_high, adr_p);
3946 } else {
3947 stpw(rt_low, rt_high, adr_p);
3948 }
3949 }
3950 }
3951
3952 /**
3953 * Multiply 64 bit by 64 bit first loop.
3954 */
3955 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
3956 Register y, Register y_idx, Register z,
3957 Register carry, Register product,
3958 Register idx, Register kdx) {
3959 //
3960 // jlong carry, x[], y[], z[];
3961 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
3962 // huge_128 product = y[idx] * x[xstart] + carry;
3963 // z[kdx] = (jlong)product;
3964 // carry = (jlong)(product >>> 64);
3965 // }
3966 // z[xstart] = carry;
3967 //
3968
3969 Label L_first_loop, L_first_loop_exit;
3970 Label L_one_x, L_one_y, L_multiply;
3971
3972 subsw(xstart, xstart, 1);
3973 br(Assembler::MI, L_one_x);
3974
3975 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
3976 ldr(x_xstart, Address(rscratch1));
3977 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
3978
3979 bind(L_first_loop);
3980 subsw(idx, idx, 1);
3981 br(Assembler::MI, L_first_loop_exit);
3982 subsw(idx, idx, 1);
3983 br(Assembler::MI, L_one_y);
3984 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3985 ldr(y_idx, Address(rscratch1));
3986 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
3987 bind(L_multiply);
3988
3989 // AArch64 has a multiply-accumulate instruction that we can't use
3990 // here because it has no way to process carries, so we have to use
3991 // separate add and adc instructions. Bah.
3992 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
3993 mul(product, x_xstart, y_idx);
3994 adds(product, product, carry);
3995 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
3996
3997 subw(kdx, kdx, 2);
3998 ror(product, product, 32); // back to big-endian
3999 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
4000
4001 b(L_first_loop);
4002
4003 bind(L_one_y);
4004 ldrw(y_idx, Address(y, 0));
4005 b(L_multiply);
4006
4007 bind(L_one_x);
4008 ldrw(x_xstart, Address(x, 0));
4009 b(L_first_loop);
4010
4011 bind(L_first_loop_exit);
4012 }
4013
4014 /**
4015 * Multiply 128 bit by 128. Unrolled inner loop.
4016 *
4017 */
4018 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
4019 Register carry, Register carry2,
4020 Register idx, Register jdx,
4021 Register yz_idx1, Register yz_idx2,
4022 Register tmp, Register tmp3, Register tmp4,
4023 Register tmp6, Register product_hi) {
4024
4025 // jlong carry, x[], y[], z[];
4026 // int kdx = ystart+1;
4027 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
4028 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
4029 // jlong carry2 = (jlong)(tmp3 >>> 64);
4030 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
4031 // carry = (jlong)(tmp4 >>> 64);
4032 // z[kdx+idx+1] = (jlong)tmp3;
4033 // z[kdx+idx] = (jlong)tmp4;
4034 // }
4035 // idx += 2;
4036 // if (idx > 0) {
4037 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
4038 // z[kdx+idx] = (jlong)yz_idx1;
4039 // carry = (jlong)(yz_idx1 >>> 64);
4040 // }
4041 //
4042
4043 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
4044
4045 lsrw(jdx, idx, 2);
4046
4047 bind(L_third_loop);
4048
4049 subsw(jdx, jdx, 1);
4050 br(Assembler::MI, L_third_loop_exit);
4051 subw(idx, idx, 4);
4052
4053 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4054
4055 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
4056
4057 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4058
4059 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
4060 ror(yz_idx2, yz_idx2, 32);
4061
4062 ldp(rscratch2, rscratch1, Address(tmp6, 0));
4063
4064 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4065 umulh(tmp4, product_hi, yz_idx1);
4066
4067 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
4068 ror(rscratch2, rscratch2, 32);
4069
4070 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
4071 umulh(carry2, product_hi, yz_idx2);
4072
4073 // propagate sum of both multiplications into carry:tmp4:tmp3
4074 adds(tmp3, tmp3, carry);
4075 adc(tmp4, tmp4, zr);
4076 adds(tmp3, tmp3, rscratch1);
4077 adcs(tmp4, tmp4, tmp);
4078 adc(carry, carry2, zr);
4079 adds(tmp4, tmp4, rscratch2);
4080 adc(carry, carry, zr);
4081
4082 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
4083 ror(tmp4, tmp4, 32);
4084 stp(tmp4, tmp3, Address(tmp6, 0));
4085
4086 b(L_third_loop);
4087 bind (L_third_loop_exit);
4088
4089 andw (idx, idx, 0x3);
4090 cbz(idx, L_post_third_loop_done);
4091
4092 Label L_check_1;
4093 subsw(idx, idx, 2);
4094 br(Assembler::MI, L_check_1);
4095
4096 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4097 ldr(yz_idx1, Address(rscratch1, 0));
4098 ror(yz_idx1, yz_idx1, 32);
4099 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4100 umulh(tmp4, product_hi, yz_idx1);
4101 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4102 ldr(yz_idx2, Address(rscratch1, 0));
4103 ror(yz_idx2, yz_idx2, 32);
4104
4105 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
4106
4107 ror(tmp3, tmp3, 32);
4108 str(tmp3, Address(rscratch1, 0));
4109
4110 bind (L_check_1);
4111
4112 andw (idx, idx, 0x1);
4113 subsw(idx, idx, 1);
4114 br(Assembler::MI, L_post_third_loop_done);
4115 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4116 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
4117 umulh(carry2, tmp4, product_hi);
4118 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4119
4120 add2_with_carry(carry2, tmp3, tmp4, carry);
4121
4122 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4123 extr(carry, carry2, tmp3, 32);
4124
4125 bind(L_post_third_loop_done);
4126 }
4127
4128 /**
4129 * Code for BigInteger::multiplyToLen() intrinsic.
4130 *
4131 * r0: x
4132 * r1: xlen
4133 * r2: y
4134 * r3: ylen
4135 * r4: z
4136 * r5: tmp0
4137 * r10: tmp1
4138 * r11: tmp2
4139 * r12: tmp3
4140 * r13: tmp4
4141 * r14: tmp5
4142 * r15: tmp6
4143 * r16: tmp7
4144 *
4145 */
4146 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
4147 Register z, Register tmp0,
4148 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
4149 Register tmp5, Register tmp6, Register product_hi) {
4150
4151 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, product_hi);
4152
4153 const Register idx = tmp1;
4154 const Register kdx = tmp2;
4155 const Register xstart = tmp3;
4156
4157 const Register y_idx = tmp4;
4158 const Register carry = tmp5;
4159 const Register product = xlen;
4160 const Register x_xstart = tmp0;
4161
4162 // First Loop.
4163 //
4164 // final static long LONG_MASK = 0xffffffffL;
4165 // int xstart = xlen - 1;
4166 // int ystart = ylen - 1;
4167 // long carry = 0;
4168 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
4169 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
4170 // z[kdx] = (int)product;
4171 // carry = product >>> 32;
4172 // }
4173 // z[xstart] = (int)carry;
4174 //
4175
4176 movw(idx, ylen); // idx = ylen;
4177 addw(kdx, xlen, ylen); // kdx = xlen+ylen;
4178 mov(carry, zr); // carry = 0;
4179
4180 Label L_done;
4181
4182 movw(xstart, xlen);
4183 subsw(xstart, xstart, 1);
4184 br(Assembler::MI, L_done);
4185
4186 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
4187
4188 Label L_second_loop;
4189 cbzw(kdx, L_second_loop);
4190
4191 Label L_carry;
4192 subw(kdx, kdx, 1);
4193 cbzw(kdx, L_carry);
4194
4195 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4196 lsr(carry, carry, 32);
4197 subw(kdx, kdx, 1);
4198
4199 bind(L_carry);
4200 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4201
4202 // Second and third (nested) loops.
4203 //
4204 // for (int i = xstart-1; i >= 0; i--) { // Second loop
4205 // carry = 0;
4206 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
4207 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
4208 // (z[k] & LONG_MASK) + carry;
4209 // z[k] = (int)product;
4210 // carry = product >>> 32;
4211 // }
4212 // z[i] = (int)carry;
4213 // }
4214 //
4215 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
4216
4217 const Register jdx = tmp1;
4218
4219 bind(L_second_loop);
4220 mov(carry, zr); // carry = 0;
4221 movw(jdx, ylen); // j = ystart+1
4222
4223 subsw(xstart, xstart, 1); // i = xstart-1;
4224 br(Assembler::MI, L_done);
4225
4226 str(z, Address(pre(sp, -4 * wordSize)));
4227
4228 Label L_last_x;
4229 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
4230 subsw(xstart, xstart, 1); // i = xstart-1;
4231 br(Assembler::MI, L_last_x);
4232
4233 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
4234 ldr(product_hi, Address(rscratch1));
4235 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
4236
4237 Label L_third_loop_prologue;
4238 bind(L_third_loop_prologue);
4239
4240 str(ylen, Address(sp, wordSize));
4241 stp(x, xstart, Address(sp, 2 * wordSize));
4242 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
4243 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
4244 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
4245 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
4246
4247 addw(tmp3, xlen, 1);
4248 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4249 subsw(tmp3, tmp3, 1);
4250 br(Assembler::MI, L_done);
4251
4252 lsr(carry, carry, 32);
4253 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4254 b(L_second_loop);
4255
4256 // Next infrequent code is moved outside loops.
4257 bind(L_last_x);
4258 ldrw(product_hi, Address(x, 0));
4259 b(L_third_loop_prologue);
4260
4261 bind(L_done);
4262 }
4263
4264 // Code for BigInteger::mulAdd intrinsic
4265 // out = r0
4266 // in = r1
4267 // offset = r2 (already out.length-offset)
4268 // len = r3
4269 // k = r4
4270 //
4271 // pseudo code from java implementation:
4272 // carry = 0;
4273 // offset = out.length-offset - 1;
4274 // for (int j=len-1; j >= 0; j--) {
4275 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry;
4276 // out[offset--] = (int)product;
4277 // carry = product >>> 32;
4278 // }
4279 // return (int)carry;
4280 void MacroAssembler::mul_add(Register out, Register in, Register offset,
4281 Register len, Register k) {
4282 Label LOOP, END;
4283 // pre-loop
4284 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches
4285 csel(out, zr, out, Assembler::EQ);
4286 br(Assembler::EQ, END);
4287 add(in, in, len, LSL, 2); // in[j+1] address
4288 add(offset, out, offset, LSL, 2); // out[offset + 1] address
4289 mov(out, zr); // used to keep carry now
4290 BIND(LOOP);
4291 ldrw(rscratch1, Address(pre(in, -4)));
4292 madd(rscratch1, rscratch1, k, out);
4293 ldrw(rscratch2, Address(pre(offset, -4)));
4294 add(rscratch1, rscratch1, rscratch2);
4295 strw(rscratch1, Address(offset));
4296 lsr(out, rscratch1, 32);
4297 subs(len, len, 1);
4298 br(Assembler::NE, LOOP);
4299 BIND(END);
4300 }
4301
4302 /**
4303 * Emits code to update CRC-32 with a byte value according to constants in table
4304 *
4305 * @param [in,out]crc Register containing the crc.
4306 * @param [in]val Register containing the byte to fold into the CRC.
4307 * @param [in]table Register containing the table of crc constants.
4308 *
4309 * uint32_t crc;
4310 * val = crc_table[(val ^ crc) & 0xFF];
4311 * crc = val ^ (crc >> 8);
4312 *
4313 */
4314 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
4315 eor(val, val, crc);
4316 andr(val, val, 0xff);
4317 ldrw(val, Address(table, val, Address::lsl(2)));
4318 eor(crc, val, crc, Assembler::LSR, 8);
4319 }
4320
4321 /**
4322 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
4323 *
4324 * @param [in,out]crc Register containing the crc.
4325 * @param [in]v Register containing the 32-bit to fold into the CRC.
4326 * @param [in]table0 Register containing table 0 of crc constants.
4327 * @param [in]table1 Register containing table 1 of crc constants.
4328 * @param [in]table2 Register containing table 2 of crc constants.
4329 * @param [in]table3 Register containing table 3 of crc constants.
4330 *
4331 * uint32_t crc;
4332 * v = crc ^ v
4333 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
4334 *
4335 */
4336 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
4337 Register table0, Register table1, Register table2, Register table3,
4338 bool upper) {
4339 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
4340 uxtb(tmp, v);
4341 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
4342 ubfx(tmp, v, 8, 8);
4343 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
4344 eor(crc, crc, tmp);
4345 ubfx(tmp, v, 16, 8);
4346 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
4347 eor(crc, crc, tmp);
4348 ubfx(tmp, v, 24, 8);
4349 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
4350 eor(crc, crc, tmp);
4351 }
4352
4353 void MacroAssembler::kernel_crc32_using_crypto_pmull(Register crc, Register buf,
4354 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4355 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4356 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4357
4358 subs(tmp0, len, 384);
4359 mvnw(crc, crc);
4360 br(Assembler::GE, CRC_by128_pre);
4361 BIND(CRC_less128);
4362 subs(len, len, 32);
4363 br(Assembler::GE, CRC_by32_loop);
4364 BIND(CRC_less32);
4365 adds(len, len, 32 - 4);
4366 br(Assembler::GE, CRC_by4_loop);
4367 adds(len, len, 4);
4368 br(Assembler::GT, CRC_by1_loop);
4369 b(L_exit);
4370
4371 BIND(CRC_by32_loop);
4372 ldp(tmp0, tmp1, Address(buf));
4373 crc32x(crc, crc, tmp0);
4374 ldp(tmp2, tmp3, Address(buf, 16));
4375 crc32x(crc, crc, tmp1);
4376 add(buf, buf, 32);
4377 crc32x(crc, crc, tmp2);
4378 subs(len, len, 32);
4379 crc32x(crc, crc, tmp3);
4380 br(Assembler::GE, CRC_by32_loop);
4381 cmn(len, (u1)32);
4382 br(Assembler::NE, CRC_less32);
4383 b(L_exit);
4384
4385 BIND(CRC_by4_loop);
4386 ldrw(tmp0, Address(post(buf, 4)));
4387 subs(len, len, 4);
4388 crc32w(crc, crc, tmp0);
4389 br(Assembler::GE, CRC_by4_loop);
4390 adds(len, len, 4);
4391 br(Assembler::LE, L_exit);
4392 BIND(CRC_by1_loop);
4393 ldrb(tmp0, Address(post(buf, 1)));
4394 subs(len, len, 1);
4395 crc32b(crc, crc, tmp0);
4396 br(Assembler::GT, CRC_by1_loop);
4397 b(L_exit);
4398
4399 BIND(CRC_by128_pre);
4400 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4401 4*256*sizeof(juint) + 8*sizeof(juint));
4402 mov(crc, 0);
4403 crc32x(crc, crc, tmp0);
4404 crc32x(crc, crc, tmp1);
4405
4406 cbnz(len, CRC_less128);
4407
4408 BIND(L_exit);
4409 mvnw(crc, crc);
4410 }
4411
4412 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf,
4413 Register len, Register tmp0, Register tmp1, Register tmp2,
4414 Register tmp3) {
4415 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4416 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4417
4418 mvnw(crc, crc);
4419
4420 subs(len, len, 128);
4421 br(Assembler::GE, CRC_by64_pre);
4422 BIND(CRC_less64);
4423 adds(len, len, 128-32);
4424 br(Assembler::GE, CRC_by32_loop);
4425 BIND(CRC_less32);
4426 adds(len, len, 32-4);
4427 br(Assembler::GE, CRC_by4_loop);
4428 adds(len, len, 4);
4429 br(Assembler::GT, CRC_by1_loop);
4430 b(L_exit);
4431
4432 BIND(CRC_by32_loop);
4433 ldp(tmp0, tmp1, Address(post(buf, 16)));
4434 subs(len, len, 32);
4435 crc32x(crc, crc, tmp0);
4436 ldr(tmp2, Address(post(buf, 8)));
4437 crc32x(crc, crc, tmp1);
4438 ldr(tmp3, Address(post(buf, 8)));
4439 crc32x(crc, crc, tmp2);
4440 crc32x(crc, crc, tmp3);
4441 br(Assembler::GE, CRC_by32_loop);
4442 cmn(len, (u1)32);
4443 br(Assembler::NE, CRC_less32);
4444 b(L_exit);
4445
4446 BIND(CRC_by4_loop);
4447 ldrw(tmp0, Address(post(buf, 4)));
4448 subs(len, len, 4);
4449 crc32w(crc, crc, tmp0);
4450 br(Assembler::GE, CRC_by4_loop);
4451 adds(len, len, 4);
4452 br(Assembler::LE, L_exit);
4453 BIND(CRC_by1_loop);
4454 ldrb(tmp0, Address(post(buf, 1)));
4455 subs(len, len, 1);
4456 crc32b(crc, crc, tmp0);
4457 br(Assembler::GT, CRC_by1_loop);
4458 b(L_exit);
4459
4460 BIND(CRC_by64_pre);
4461 sub(buf, buf, 8);
4462 ldp(tmp0, tmp1, Address(buf, 8));
4463 crc32x(crc, crc, tmp0);
4464 ldr(tmp2, Address(buf, 24));
4465 crc32x(crc, crc, tmp1);
4466 ldr(tmp3, Address(buf, 32));
4467 crc32x(crc, crc, tmp2);
4468 ldr(tmp0, Address(buf, 40));
4469 crc32x(crc, crc, tmp3);
4470 ldr(tmp1, Address(buf, 48));
4471 crc32x(crc, crc, tmp0);
4472 ldr(tmp2, Address(buf, 56));
4473 crc32x(crc, crc, tmp1);
4474 ldr(tmp3, Address(pre(buf, 64)));
4475
4476 b(CRC_by64_loop);
4477
4478 align(CodeEntryAlignment);
4479 BIND(CRC_by64_loop);
4480 subs(len, len, 64);
4481 crc32x(crc, crc, tmp2);
4482 ldr(tmp0, Address(buf, 8));
4483 crc32x(crc, crc, tmp3);
4484 ldr(tmp1, Address(buf, 16));
4485 crc32x(crc, crc, tmp0);
4486 ldr(tmp2, Address(buf, 24));
4487 crc32x(crc, crc, tmp1);
4488 ldr(tmp3, Address(buf, 32));
4489 crc32x(crc, crc, tmp2);
4490 ldr(tmp0, Address(buf, 40));
4491 crc32x(crc, crc, tmp3);
4492 ldr(tmp1, Address(buf, 48));
4493 crc32x(crc, crc, tmp0);
4494 ldr(tmp2, Address(buf, 56));
4495 crc32x(crc, crc, tmp1);
4496 ldr(tmp3, Address(pre(buf, 64)));
4497 br(Assembler::GE, CRC_by64_loop);
4498
4499 // post-loop
4500 crc32x(crc, crc, tmp2);
4501 crc32x(crc, crc, tmp3);
4502
4503 sub(len, len, 64);
4504 add(buf, buf, 8);
4505 cmn(len, (u1)128);
4506 br(Assembler::NE, CRC_less64);
4507 BIND(L_exit);
4508 mvnw(crc, crc);
4509 }
4510
4511 /**
4512 * @param crc register containing existing CRC (32-bit)
4513 * @param buf register pointing to input byte buffer (byte*)
4514 * @param len register containing number of bytes
4515 * @param table register that will contain address of CRC table
4516 * @param tmp scratch register
4517 */
4518 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
4519 Register table0, Register table1, Register table2, Register table3,
4520 Register tmp, Register tmp2, Register tmp3) {
4521 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
4522
4523 if (UseCryptoPmullForCRC32) {
4524 kernel_crc32_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4525 return;
4526 }
4527
4528 if (UseCRC32) {
4529 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
4530 return;
4531 }
4532
4533 mvnw(crc, crc);
4534
4535 {
4536 uint64_t offset;
4537 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4538 add(table0, table0, offset);
4539 }
4540 add(table1, table0, 1*256*sizeof(juint));
4541 add(table2, table0, 2*256*sizeof(juint));
4542 add(table3, table0, 3*256*sizeof(juint));
4543
4544 { // Neon code start
4545 cmp(len, (u1)64);
4546 br(Assembler::LT, L_by16);
4547 eor(v16, T16B, v16, v16);
4548
4549 Label L_fold;
4550
4551 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
4552
4553 ld1(v0, v1, T2D, post(buf, 32));
4554 ld1r(v4, T2D, post(tmp, 8));
4555 ld1r(v5, T2D, post(tmp, 8));
4556 ld1r(v6, T2D, post(tmp, 8));
4557 ld1r(v7, T2D, post(tmp, 8));
4558 mov(v16, S, 0, crc);
4559
4560 eor(v0, T16B, v0, v16);
4561 sub(len, len, 64);
4562
4563 BIND(L_fold);
4564 pmull(v22, T8H, v0, v5, T8B);
4565 pmull(v20, T8H, v0, v7, T8B);
4566 pmull(v23, T8H, v0, v4, T8B);
4567 pmull(v21, T8H, v0, v6, T8B);
4568
4569 pmull2(v18, T8H, v0, v5, T16B);
4570 pmull2(v16, T8H, v0, v7, T16B);
4571 pmull2(v19, T8H, v0, v4, T16B);
4572 pmull2(v17, T8H, v0, v6, T16B);
4573
4574 uzp1(v24, T8H, v20, v22);
4575 uzp2(v25, T8H, v20, v22);
4576 eor(v20, T16B, v24, v25);
4577
4578 uzp1(v26, T8H, v16, v18);
4579 uzp2(v27, T8H, v16, v18);
4580 eor(v16, T16B, v26, v27);
4581
4582 ushll2(v22, T4S, v20, T8H, 8);
4583 ushll(v20, T4S, v20, T4H, 8);
4584
4585 ushll2(v18, T4S, v16, T8H, 8);
4586 ushll(v16, T4S, v16, T4H, 8);
4587
4588 eor(v22, T16B, v23, v22);
4589 eor(v18, T16B, v19, v18);
4590 eor(v20, T16B, v21, v20);
4591 eor(v16, T16B, v17, v16);
4592
4593 uzp1(v17, T2D, v16, v20);
4594 uzp2(v21, T2D, v16, v20);
4595 eor(v17, T16B, v17, v21);
4596
4597 ushll2(v20, T2D, v17, T4S, 16);
4598 ushll(v16, T2D, v17, T2S, 16);
4599
4600 eor(v20, T16B, v20, v22);
4601 eor(v16, T16B, v16, v18);
4602
4603 uzp1(v17, T2D, v20, v16);
4604 uzp2(v21, T2D, v20, v16);
4605 eor(v28, T16B, v17, v21);
4606
4607 pmull(v22, T8H, v1, v5, T8B);
4608 pmull(v20, T8H, v1, v7, T8B);
4609 pmull(v23, T8H, v1, v4, T8B);
4610 pmull(v21, T8H, v1, v6, T8B);
4611
4612 pmull2(v18, T8H, v1, v5, T16B);
4613 pmull2(v16, T8H, v1, v7, T16B);
4614 pmull2(v19, T8H, v1, v4, T16B);
4615 pmull2(v17, T8H, v1, v6, T16B);
4616
4617 ld1(v0, v1, T2D, post(buf, 32));
4618
4619 uzp1(v24, T8H, v20, v22);
4620 uzp2(v25, T8H, v20, v22);
4621 eor(v20, T16B, v24, v25);
4622
4623 uzp1(v26, T8H, v16, v18);
4624 uzp2(v27, T8H, v16, v18);
4625 eor(v16, T16B, v26, v27);
4626
4627 ushll2(v22, T4S, v20, T8H, 8);
4628 ushll(v20, T4S, v20, T4H, 8);
4629
4630 ushll2(v18, T4S, v16, T8H, 8);
4631 ushll(v16, T4S, v16, T4H, 8);
4632
4633 eor(v22, T16B, v23, v22);
4634 eor(v18, T16B, v19, v18);
4635 eor(v20, T16B, v21, v20);
4636 eor(v16, T16B, v17, v16);
4637
4638 uzp1(v17, T2D, v16, v20);
4639 uzp2(v21, T2D, v16, v20);
4640 eor(v16, T16B, v17, v21);
4641
4642 ushll2(v20, T2D, v16, T4S, 16);
4643 ushll(v16, T2D, v16, T2S, 16);
4644
4645 eor(v20, T16B, v22, v20);
4646 eor(v16, T16B, v16, v18);
4647
4648 uzp1(v17, T2D, v20, v16);
4649 uzp2(v21, T2D, v20, v16);
4650 eor(v20, T16B, v17, v21);
4651
4652 shl(v16, T2D, v28, 1);
4653 shl(v17, T2D, v20, 1);
4654
4655 eor(v0, T16B, v0, v16);
4656 eor(v1, T16B, v1, v17);
4657
4658 subs(len, len, 32);
4659 br(Assembler::GE, L_fold);
4660
4661 mov(crc, 0);
4662 mov(tmp, v0, D, 0);
4663 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4664 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4665 mov(tmp, v0, D, 1);
4666 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4667 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4668 mov(tmp, v1, D, 0);
4669 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4670 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4671 mov(tmp, v1, D, 1);
4672 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4673 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4674
4675 add(len, len, 32);
4676 } // Neon code end
4677
4678 BIND(L_by16);
4679 subs(len, len, 16);
4680 br(Assembler::GE, L_by16_loop);
4681 adds(len, len, 16-4);
4682 br(Assembler::GE, L_by4_loop);
4683 adds(len, len, 4);
4684 br(Assembler::GT, L_by1_loop);
4685 b(L_exit);
4686
4687 BIND(L_by4_loop);
4688 ldrw(tmp, Address(post(buf, 4)));
4689 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
4690 subs(len, len, 4);
4691 br(Assembler::GE, L_by4_loop);
4692 adds(len, len, 4);
4693 br(Assembler::LE, L_exit);
4694 BIND(L_by1_loop);
4695 subs(len, len, 1);
4696 ldrb(tmp, Address(post(buf, 1)));
4697 update_byte_crc32(crc, tmp, table0);
4698 br(Assembler::GT, L_by1_loop);
4699 b(L_exit);
4700
4701 align(CodeEntryAlignment);
4702 BIND(L_by16_loop);
4703 subs(len, len, 16);
4704 ldp(tmp, tmp3, Address(post(buf, 16)));
4705 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4706 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4707 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
4708 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
4709 br(Assembler::GE, L_by16_loop);
4710 adds(len, len, 16-4);
4711 br(Assembler::GE, L_by4_loop);
4712 adds(len, len, 4);
4713 br(Assembler::GT, L_by1_loop);
4714 BIND(L_exit);
4715 mvnw(crc, crc);
4716 }
4717
4718 void MacroAssembler::kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
4719 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4720 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4721 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4722
4723 subs(tmp0, len, 384);
4724 br(Assembler::GE, CRC_by128_pre);
4725 BIND(CRC_less128);
4726 subs(len, len, 32);
4727 br(Assembler::GE, CRC_by32_loop);
4728 BIND(CRC_less32);
4729 adds(len, len, 32 - 4);
4730 br(Assembler::GE, CRC_by4_loop);
4731 adds(len, len, 4);
4732 br(Assembler::GT, CRC_by1_loop);
4733 b(L_exit);
4734
4735 BIND(CRC_by32_loop);
4736 ldp(tmp0, tmp1, Address(buf));
4737 crc32cx(crc, crc, tmp0);
4738 ldr(tmp2, Address(buf, 16));
4739 crc32cx(crc, crc, tmp1);
4740 ldr(tmp3, Address(buf, 24));
4741 crc32cx(crc, crc, tmp2);
4742 add(buf, buf, 32);
4743 subs(len, len, 32);
4744 crc32cx(crc, crc, tmp3);
4745 br(Assembler::GE, CRC_by32_loop);
4746 cmn(len, (u1)32);
4747 br(Assembler::NE, CRC_less32);
4748 b(L_exit);
4749
4750 BIND(CRC_by4_loop);
4751 ldrw(tmp0, Address(post(buf, 4)));
4752 subs(len, len, 4);
4753 crc32cw(crc, crc, tmp0);
4754 br(Assembler::GE, CRC_by4_loop);
4755 adds(len, len, 4);
4756 br(Assembler::LE, L_exit);
4757 BIND(CRC_by1_loop);
4758 ldrb(tmp0, Address(post(buf, 1)));
4759 subs(len, len, 1);
4760 crc32cb(crc, crc, tmp0);
4761 br(Assembler::GT, CRC_by1_loop);
4762 b(L_exit);
4763
4764 BIND(CRC_by128_pre);
4765 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4766 4*256*sizeof(juint) + 8*sizeof(juint) + 0x50);
4767 mov(crc, 0);
4768 crc32cx(crc, crc, tmp0);
4769 crc32cx(crc, crc, tmp1);
4770
4771 cbnz(len, CRC_less128);
4772
4773 BIND(L_exit);
4774 }
4775
4776 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf,
4777 Register len, Register tmp0, Register tmp1, Register tmp2,
4778 Register tmp3) {
4779 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4780 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4781
4782 subs(len, len, 128);
4783 br(Assembler::GE, CRC_by64_pre);
4784 BIND(CRC_less64);
4785 adds(len, len, 128-32);
4786 br(Assembler::GE, CRC_by32_loop);
4787 BIND(CRC_less32);
4788 adds(len, len, 32-4);
4789 br(Assembler::GE, CRC_by4_loop);
4790 adds(len, len, 4);
4791 br(Assembler::GT, CRC_by1_loop);
4792 b(L_exit);
4793
4794 BIND(CRC_by32_loop);
4795 ldp(tmp0, tmp1, Address(post(buf, 16)));
4796 subs(len, len, 32);
4797 crc32cx(crc, crc, tmp0);
4798 ldr(tmp2, Address(post(buf, 8)));
4799 crc32cx(crc, crc, tmp1);
4800 ldr(tmp3, Address(post(buf, 8)));
4801 crc32cx(crc, crc, tmp2);
4802 crc32cx(crc, crc, tmp3);
4803 br(Assembler::GE, CRC_by32_loop);
4804 cmn(len, (u1)32);
4805 br(Assembler::NE, CRC_less32);
4806 b(L_exit);
4807
4808 BIND(CRC_by4_loop);
4809 ldrw(tmp0, Address(post(buf, 4)));
4810 subs(len, len, 4);
4811 crc32cw(crc, crc, tmp0);
4812 br(Assembler::GE, CRC_by4_loop);
4813 adds(len, len, 4);
4814 br(Assembler::LE, L_exit);
4815 BIND(CRC_by1_loop);
4816 ldrb(tmp0, Address(post(buf, 1)));
4817 subs(len, len, 1);
4818 crc32cb(crc, crc, tmp0);
4819 br(Assembler::GT, CRC_by1_loop);
4820 b(L_exit);
4821
4822 BIND(CRC_by64_pre);
4823 sub(buf, buf, 8);
4824 ldp(tmp0, tmp1, Address(buf, 8));
4825 crc32cx(crc, crc, tmp0);
4826 ldr(tmp2, Address(buf, 24));
4827 crc32cx(crc, crc, tmp1);
4828 ldr(tmp3, Address(buf, 32));
4829 crc32cx(crc, crc, tmp2);
4830 ldr(tmp0, Address(buf, 40));
4831 crc32cx(crc, crc, tmp3);
4832 ldr(tmp1, Address(buf, 48));
4833 crc32cx(crc, crc, tmp0);
4834 ldr(tmp2, Address(buf, 56));
4835 crc32cx(crc, crc, tmp1);
4836 ldr(tmp3, Address(pre(buf, 64)));
4837
4838 b(CRC_by64_loop);
4839
4840 align(CodeEntryAlignment);
4841 BIND(CRC_by64_loop);
4842 subs(len, len, 64);
4843 crc32cx(crc, crc, tmp2);
4844 ldr(tmp0, Address(buf, 8));
4845 crc32cx(crc, crc, tmp3);
4846 ldr(tmp1, Address(buf, 16));
4847 crc32cx(crc, crc, tmp0);
4848 ldr(tmp2, Address(buf, 24));
4849 crc32cx(crc, crc, tmp1);
4850 ldr(tmp3, Address(buf, 32));
4851 crc32cx(crc, crc, tmp2);
4852 ldr(tmp0, Address(buf, 40));
4853 crc32cx(crc, crc, tmp3);
4854 ldr(tmp1, Address(buf, 48));
4855 crc32cx(crc, crc, tmp0);
4856 ldr(tmp2, Address(buf, 56));
4857 crc32cx(crc, crc, tmp1);
4858 ldr(tmp3, Address(pre(buf, 64)));
4859 br(Assembler::GE, CRC_by64_loop);
4860
4861 // post-loop
4862 crc32cx(crc, crc, tmp2);
4863 crc32cx(crc, crc, tmp3);
4864
4865 sub(len, len, 64);
4866 add(buf, buf, 8);
4867 cmn(len, (u1)128);
4868 br(Assembler::NE, CRC_less64);
4869 BIND(L_exit);
4870 }
4871
4872 /**
4873 * @param crc register containing existing CRC (32-bit)
4874 * @param buf register pointing to input byte buffer (byte*)
4875 * @param len register containing number of bytes
4876 * @param table register that will contain address of CRC table
4877 * @param tmp scratch register
4878 */
4879 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
4880 Register table0, Register table1, Register table2, Register table3,
4881 Register tmp, Register tmp2, Register tmp3) {
4882 if (UseCryptoPmullForCRC32) {
4883 kernel_crc32c_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4884 } else {
4885 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3);
4886 }
4887 }
4888
4889 void MacroAssembler::kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
4890 Register len, Register tmp0, Register tmp1, Register tmp2, size_t table_offset) {
4891 Label CRC_by128_loop;
4892 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4893
4894 sub(len, len, 256);
4895 Register table = tmp0;
4896 {
4897 uint64_t offset;
4898 adrp(table, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4899 add(table, table, offset);
4900 }
4901 add(table, table, table_offset);
4902
4903 // Registers v0..v7 are used as data registers.
4904 // Registers v16..v31 are used as tmp registers.
4905 sub(buf, buf, 0x10);
4906 ldrq(v0, Address(buf, 0x10));
4907 ldrq(v1, Address(buf, 0x20));
4908 ldrq(v2, Address(buf, 0x30));
4909 ldrq(v3, Address(buf, 0x40));
4910 ldrq(v4, Address(buf, 0x50));
4911 ldrq(v5, Address(buf, 0x60));
4912 ldrq(v6, Address(buf, 0x70));
4913 ldrq(v7, Address(pre(buf, 0x80)));
4914
4915 movi(v31, T4S, 0);
4916 mov(v31, S, 0, crc);
4917 eor(v0, T16B, v0, v31);
4918
4919 // Register v16 contains constants from the crc table.
4920 ldrq(v16, Address(table));
4921 b(CRC_by128_loop);
4922
4923 align(OptoLoopAlignment);
4924 BIND(CRC_by128_loop);
4925 pmull (v17, T1Q, v0, v16, T1D);
4926 pmull2(v18, T1Q, v0, v16, T2D);
4927 ldrq(v0, Address(buf, 0x10));
4928 eor3(v0, T16B, v17, v18, v0);
4929
4930 pmull (v19, T1Q, v1, v16, T1D);
4931 pmull2(v20, T1Q, v1, v16, T2D);
4932 ldrq(v1, Address(buf, 0x20));
4933 eor3(v1, T16B, v19, v20, v1);
4934
4935 pmull (v21, T1Q, v2, v16, T1D);
4936 pmull2(v22, T1Q, v2, v16, T2D);
4937 ldrq(v2, Address(buf, 0x30));
4938 eor3(v2, T16B, v21, v22, v2);
4939
4940 pmull (v23, T1Q, v3, v16, T1D);
4941 pmull2(v24, T1Q, v3, v16, T2D);
4942 ldrq(v3, Address(buf, 0x40));
4943 eor3(v3, T16B, v23, v24, v3);
4944
4945 pmull (v25, T1Q, v4, v16, T1D);
4946 pmull2(v26, T1Q, v4, v16, T2D);
4947 ldrq(v4, Address(buf, 0x50));
4948 eor3(v4, T16B, v25, v26, v4);
4949
4950 pmull (v27, T1Q, v5, v16, T1D);
4951 pmull2(v28, T1Q, v5, v16, T2D);
4952 ldrq(v5, Address(buf, 0x60));
4953 eor3(v5, T16B, v27, v28, v5);
4954
4955 pmull (v29, T1Q, v6, v16, T1D);
4956 pmull2(v30, T1Q, v6, v16, T2D);
4957 ldrq(v6, Address(buf, 0x70));
4958 eor3(v6, T16B, v29, v30, v6);
4959
4960 // Reuse registers v23, v24.
4961 // Using them won't block the first instruction of the next iteration.
4962 pmull (v23, T1Q, v7, v16, T1D);
4963 pmull2(v24, T1Q, v7, v16, T2D);
4964 ldrq(v7, Address(pre(buf, 0x80)));
4965 eor3(v7, T16B, v23, v24, v7);
4966
4967 subs(len, len, 0x80);
4968 br(Assembler::GE, CRC_by128_loop);
4969
4970 // fold into 512 bits
4971 // Use v31 for constants because v16 can be still in use.
4972 ldrq(v31, Address(table, 0x10));
4973
4974 pmull (v17, T1Q, v0, v31, T1D);
4975 pmull2(v18, T1Q, v0, v31, T2D);
4976 eor3(v0, T16B, v17, v18, v4);
4977
4978 pmull (v19, T1Q, v1, v31, T1D);
4979 pmull2(v20, T1Q, v1, v31, T2D);
4980 eor3(v1, T16B, v19, v20, v5);
4981
4982 pmull (v21, T1Q, v2, v31, T1D);
4983 pmull2(v22, T1Q, v2, v31, T2D);
4984 eor3(v2, T16B, v21, v22, v6);
4985
4986 pmull (v23, T1Q, v3, v31, T1D);
4987 pmull2(v24, T1Q, v3, v31, T2D);
4988 eor3(v3, T16B, v23, v24, v7);
4989
4990 // fold into 128 bits
4991 // Use v17 for constants because v31 can be still in use.
4992 ldrq(v17, Address(table, 0x20));
4993 pmull (v25, T1Q, v0, v17, T1D);
4994 pmull2(v26, T1Q, v0, v17, T2D);
4995 eor3(v3, T16B, v3, v25, v26);
4996
4997 // Use v18 for constants because v17 can be still in use.
4998 ldrq(v18, Address(table, 0x30));
4999 pmull (v27, T1Q, v1, v18, T1D);
5000 pmull2(v28, T1Q, v1, v18, T2D);
5001 eor3(v3, T16B, v3, v27, v28);
5002
5003 // Use v19 for constants because v18 can be still in use.
5004 ldrq(v19, Address(table, 0x40));
5005 pmull (v29, T1Q, v2, v19, T1D);
5006 pmull2(v30, T1Q, v2, v19, T2D);
5007 eor3(v0, T16B, v3, v29, v30);
5008
5009 add(len, len, 0x80);
5010 add(buf, buf, 0x10);
5011
5012 mov(tmp0, v0, D, 0);
5013 mov(tmp1, v0, D, 1);
5014 }
5015
5016 void MacroAssembler::addptr(const Address &dst, int32_t src) {
5017 Address adr;
5018 switch(dst.getMode()) {
5019 case Address::base_plus_offset:
5020 // This is the expected mode, although we allow all the other
5021 // forms below.
5022 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
5023 break;
5024 default:
5025 lea(rscratch2, dst);
5026 adr = Address(rscratch2);
5027 break;
5028 }
5029 ldr(rscratch1, adr);
5030 add(rscratch1, rscratch1, src);
5031 str(rscratch1, adr);
5032 }
5033
5034 void MacroAssembler::cmpptr(Register src1, Address src2) {
5035 uint64_t offset;
5036 adrp(rscratch1, src2, offset);
5037 ldr(rscratch1, Address(rscratch1, offset));
5038 cmp(src1, rscratch1);
5039 }
5040
5041 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
5042 cmp(obj1, obj2);
5043 }
5044
5045 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5046 load_method_holder(rresult, rmethod);
5047 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5048 }
5049
5050 void MacroAssembler::load_method_holder(Register holder, Register method) {
5051 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
5052 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5053 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5054 }
5055
5056 // Loads the obj's Klass* into dst.
5057 // Preserves all registers (incl src, rscratch1 and rscratch2).
5058 // Input:
5059 // src - the oop we want to load the klass from.
5060 // dst - output narrow klass.
5061 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5062 assert(UseCompactObjectHeaders, "expects UseCompactObjectHeaders");
5063 ldr(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5064 lsr(dst, dst, markWord::klass_shift);
5065 }
5066
5067 void MacroAssembler::load_klass(Register dst, Register src) {
5068 if (UseCompactObjectHeaders) {
5069 load_narrow_klass_compact(dst, src);
5070 decode_klass_not_null(dst);
5071 } else if (UseCompressedClassPointers) {
5072 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5073 decode_klass_not_null(dst);
5074 } else {
5075 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5076 }
5077 }
5078
5079 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
5080 if (RestoreMXCSROnJNICalls) {
5081 Label OK;
5082 get_fpcr(tmp1);
5083 mov(tmp2, tmp1);
5084 // Set FPCR to the state we need. We do want Round to Nearest. We
5085 // don't want non-IEEE rounding modes or floating-point traps.
5086 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
5087 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
5088 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
5089 eor(tmp2, tmp1, tmp2);
5090 cbz(tmp2, OK); // Only reset FPCR if it's wrong
5091 set_fpcr(tmp1);
5092 bind(OK);
5093 }
5094 }
5095
5096 // ((OopHandle)result).resolve();
5097 void MacroAssembler::resolve_oop_handle(Register result, Register tmp1, Register tmp2) {
5098 // OopHandle::resolve is an indirection.
5099 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp1, tmp2);
5100 }
5101
5102 // ((WeakHandle)result).resolve();
5103 void MacroAssembler::resolve_weak_handle(Register result, Register tmp1, Register tmp2) {
5104 assert_different_registers(result, tmp1, tmp2);
5105 Label resolved;
5106
5107 // A null weak handle resolves to null.
5108 cbz(result, resolved);
5109
5110 // Only 64 bit platforms support GCs that require a tmp register
5111 // WeakHandle::resolve is an indirection like jweak.
5112 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5113 result, Address(result), tmp1, tmp2);
5114 bind(resolved);
5115 }
5116
5117 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp1, Register tmp2) {
5118 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5119 ldr(dst, Address(rmethod, Method::const_offset()));
5120 ldr(dst, Address(dst, ConstMethod::constants_offset()));
5121 ldr(dst, Address(dst, ConstantPool::pool_holder_offset()));
5122 ldr(dst, Address(dst, mirror_offset));
5123 resolve_oop_handle(dst, tmp1, tmp2);
5124 }
5125
5126 void MacroAssembler::cmp_klass(Register obj, Register klass, Register tmp) {
5127 assert_different_registers(obj, klass, tmp);
5128 if (UseCompressedClassPointers) {
5129 if (UseCompactObjectHeaders) {
5130 load_narrow_klass_compact(tmp, obj);
5131 } else {
5132 ldrw(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5133 }
5134 if (CompressedKlassPointers::base() == nullptr) {
5135 cmp(klass, tmp, LSL, CompressedKlassPointers::shift());
5136 return;
5137 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
5138 && CompressedKlassPointers::shift() == 0) {
5139 // Only the bottom 32 bits matter
5140 cmpw(klass, tmp);
5141 return;
5142 }
5143 decode_klass_not_null(tmp);
5144 } else {
5145 ldr(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5146 }
5147 cmp(klass, tmp);
5148 }
5149
5150 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5151 if (UseCompactObjectHeaders) {
5152 load_narrow_klass_compact(tmp1, obj1);
5153 load_narrow_klass_compact(tmp2, obj2);
5154 cmpw(tmp1, tmp2);
5155 } else if (UseCompressedClassPointers) {
5156 ldrw(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5157 ldrw(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5158 cmpw(tmp1, tmp2);
5159 } else {
5160 ldr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5161 ldr(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5162 cmp(tmp1, tmp2);
5163 }
5164 }
5165
5166 void MacroAssembler::store_klass(Register dst, Register src) {
5167 // FIXME: Should this be a store release? concurrent gcs assumes
5168 // klass length is valid if klass field is not null.
5169 assert(!UseCompactObjectHeaders, "not with compact headers");
5170 if (UseCompressedClassPointers) {
5171 encode_klass_not_null(src);
5172 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5173 } else {
5174 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5175 }
5176 }
5177
5178 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5179 assert(!UseCompactObjectHeaders, "not with compact headers");
5180 if (UseCompressedClassPointers) {
5181 // Store to klass gap in destination
5182 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
5183 }
5184 }
5185
5186 // Algorithm must match CompressedOops::encode.
5187 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5188 #ifdef ASSERT
5189 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5190 #endif
5191 verify_oop_msg(s, "broken oop in encode_heap_oop");
5192 if (CompressedOops::base() == nullptr) {
5193 if (CompressedOops::shift() != 0) {
5194 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5195 lsr(d, s, LogMinObjAlignmentInBytes);
5196 } else {
5197 mov(d, s);
5198 }
5199 } else {
5200 subs(d, s, rheapbase);
5201 csel(d, d, zr, Assembler::HS);
5202 lsr(d, d, LogMinObjAlignmentInBytes);
5203
5204 /* Old algorithm: is this any worse?
5205 Label nonnull;
5206 cbnz(r, nonnull);
5207 sub(r, r, rheapbase);
5208 bind(nonnull);
5209 lsr(r, r, LogMinObjAlignmentInBytes);
5210 */
5211 }
5212 }
5213
5214 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5215 #ifdef ASSERT
5216 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5217 if (CheckCompressedOops) {
5218 Label ok;
5219 cbnz(r, ok);
5220 stop("null oop passed to encode_heap_oop_not_null");
5221 bind(ok);
5222 }
5223 #endif
5224 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5225 if (CompressedOops::base() != nullptr) {
5226 sub(r, r, rheapbase);
5227 }
5228 if (CompressedOops::shift() != 0) {
5229 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5230 lsr(r, r, LogMinObjAlignmentInBytes);
5231 }
5232 }
5233
5234 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5235 #ifdef ASSERT
5236 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5237 if (CheckCompressedOops) {
5238 Label ok;
5239 cbnz(src, ok);
5240 stop("null oop passed to encode_heap_oop_not_null2");
5241 bind(ok);
5242 }
5243 #endif
5244 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5245
5246 Register data = src;
5247 if (CompressedOops::base() != nullptr) {
5248 sub(dst, src, rheapbase);
5249 data = dst;
5250 }
5251 if (CompressedOops::shift() != 0) {
5252 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5253 lsr(dst, data, LogMinObjAlignmentInBytes);
5254 data = dst;
5255 }
5256 if (data == src)
5257 mov(dst, src);
5258 }
5259
5260 void MacroAssembler::decode_heap_oop(Register d, Register s) {
5261 #ifdef ASSERT
5262 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5263 #endif
5264 if (CompressedOops::base() == nullptr) {
5265 if (CompressedOops::shift() != 0) {
5266 lsl(d, s, CompressedOops::shift());
5267 } else if (d != s) {
5268 mov(d, s);
5269 }
5270 } else {
5271 Label done;
5272 if (d != s)
5273 mov(d, s);
5274 cbz(s, done);
5275 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
5276 bind(done);
5277 }
5278 verify_oop_msg(d, "broken oop in decode_heap_oop");
5279 }
5280
5281 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5282 assert (UseCompressedOops, "should only be used for compressed headers");
5283 assert (Universe::heap() != nullptr, "java heap should be initialized");
5284 // Cannot assert, unverified entry point counts instructions (see .ad file)
5285 // vtableStubs also counts instructions in pd_code_size_limit.
5286 // Also do not verify_oop as this is called by verify_oop.
5287 if (CompressedOops::shift() != 0) {
5288 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5289 if (CompressedOops::base() != nullptr) {
5290 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5291 } else {
5292 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5293 }
5294 } else {
5295 assert (CompressedOops::base() == nullptr, "sanity");
5296 }
5297 }
5298
5299 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5300 assert (UseCompressedOops, "should only be used for compressed headers");
5301 assert (Universe::heap() != nullptr, "java heap should be initialized");
5302 // Cannot assert, unverified entry point counts instructions (see .ad file)
5303 // vtableStubs also counts instructions in pd_code_size_limit.
5304 // Also do not verify_oop as this is called by verify_oop.
5305 if (CompressedOops::shift() != 0) {
5306 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5307 if (CompressedOops::base() != nullptr) {
5308 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5309 } else {
5310 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5311 }
5312 } else {
5313 assert (CompressedOops::base() == nullptr, "sanity");
5314 if (dst != src) {
5315 mov(dst, src);
5316 }
5317 }
5318 }
5319
5320 MacroAssembler::KlassDecodeMode MacroAssembler::_klass_decode_mode(KlassDecodeNone);
5321
5322 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() {
5323 assert(Metaspace::initialized(), "metaspace not initialized yet");
5324 assert(_klass_decode_mode != KlassDecodeNone, "should be initialized");
5325 return _klass_decode_mode;
5326 }
5327
5328 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode(address base, int shift, const size_t range) {
5329 assert(UseCompressedClassPointers, "not using compressed class pointers");
5330
5331 // KlassDecodeMode shouldn't be set already.
5332 assert(_klass_decode_mode == KlassDecodeNone, "set once");
5333
5334 if (base == nullptr) {
5335 return KlassDecodeZero;
5336 }
5337
5338 if (operand_valid_for_logical_immediate(
5339 /*is32*/false, (uint64_t)base)) {
5340 const uint64_t range_mask = right_n_bits(log2i_ceil(range));
5341 if (((uint64_t)base & range_mask) == 0) {
5342 return KlassDecodeXor;
5343 }
5344 }
5345
5346 const uint64_t shifted_base =
5347 (uint64_t)base >> shift;
5348 if ((shifted_base & 0xffff0000ffffffff) == 0) {
5349 return KlassDecodeMovk;
5350 }
5351
5352 // No valid encoding.
5353 return KlassDecodeNone;
5354 }
5355
5356 // Check if one of the above decoding modes will work for given base, shift and range.
5357 bool MacroAssembler::check_klass_decode_mode(address base, int shift, const size_t range) {
5358 return klass_decode_mode(base, shift, range) != KlassDecodeNone;
5359 }
5360
5361 bool MacroAssembler::set_klass_decode_mode(address base, int shift, const size_t range) {
5362 _klass_decode_mode = klass_decode_mode(base, shift, range);
5363 return _klass_decode_mode != KlassDecodeNone;
5364 }
5365
5366 static Register pick_different_tmp(Register dst, Register src) {
5367 auto tmps = RegSet::of(r0, r1, r2) - RegSet::of(src, dst);
5368 return *tmps.begin();
5369 }
5370
5371 void MacroAssembler::encode_klass_not_null_for_aot(Register dst, Register src) {
5372 // we have to load the klass base from the AOT constants area but
5373 // not the shift because it is not allowed to change
5374 int shift = CompressedKlassPointers::shift();
5375 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5376 if (dst != src) {
5377 // we can load the base into dst, subtract it formthe src and shift down
5378 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5379 ldr(dst, dst);
5380 sub(dst, src, dst);
5381 lsr(dst, dst, shift);
5382 } else {
5383 // we need an extra register in order to load the coop base
5384 Register tmp = pick_different_tmp(dst, src);
5385 RegSet regs = RegSet::of(tmp);
5386 push(regs, sp);
5387 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5388 ldr(tmp, tmp);
5389 sub(dst, src, tmp);
5390 lsr(dst, dst, shift);
5391 pop(regs, sp);
5392 }
5393 }
5394
5395 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5396 if (AOTCodeCache::is_on_for_dump()) {
5397 encode_klass_not_null_for_aot(dst, src);
5398 return;
5399 }
5400
5401 switch (klass_decode_mode()) {
5402 case KlassDecodeZero:
5403 if (CompressedKlassPointers::shift() != 0) {
5404 lsr(dst, src, CompressedKlassPointers::shift());
5405 } else {
5406 if (dst != src) mov(dst, src);
5407 }
5408 break;
5409
5410 case KlassDecodeXor:
5411 if (CompressedKlassPointers::shift() != 0) {
5412 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5413 lsr(dst, dst, CompressedKlassPointers::shift());
5414 } else {
5415 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5416 }
5417 break;
5418
5419 case KlassDecodeMovk:
5420 if (CompressedKlassPointers::shift() != 0) {
5421 ubfx(dst, src, CompressedKlassPointers::shift(), 32);
5422 } else {
5423 movw(dst, src);
5424 }
5425 break;
5426
5427 case KlassDecodeNone:
5428 ShouldNotReachHere();
5429 break;
5430 }
5431 }
5432
5433 void MacroAssembler::encode_klass_not_null(Register r) {
5434 encode_klass_not_null(r, r);
5435 }
5436
5437 void MacroAssembler::decode_klass_not_null_for_aot(Register dst, Register src) {
5438 // we have to load the klass base from the AOT constants area but
5439 // not the shift because it is not allowed to change
5440 int shift = CompressedKlassPointers::shift();
5441 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5442 if (dst != src) {
5443 // we can load the base into dst then add the offset with a suitable shift
5444 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5445 ldr(dst, dst);
5446 add(dst, dst, src, LSL, shift);
5447 } else {
5448 // we need an extra register in order to load the coop base
5449 Register tmp = pick_different_tmp(dst, src);
5450 RegSet regs = RegSet::of(tmp);
5451 push(regs, sp);
5452 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5453 ldr(tmp, tmp);
5454 add(dst, tmp, src, LSL, shift);
5455 pop(regs, sp);
5456 }
5457 }
5458
5459 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5460 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5461
5462 if (AOTCodeCache::is_on_for_dump()) {
5463 decode_klass_not_null_for_aot(dst, src);
5464 return;
5465 }
5466
5467 switch (klass_decode_mode()) {
5468 case KlassDecodeZero:
5469 if (CompressedKlassPointers::shift() != 0) {
5470 lsl(dst, src, CompressedKlassPointers::shift());
5471 } else {
5472 if (dst != src) mov(dst, src);
5473 }
5474 break;
5475
5476 case KlassDecodeXor:
5477 if (CompressedKlassPointers::shift() != 0) {
5478 lsl(dst, src, CompressedKlassPointers::shift());
5479 eor(dst, dst, (uint64_t)CompressedKlassPointers::base());
5480 } else {
5481 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5482 }
5483 break;
5484
5485 case KlassDecodeMovk: {
5486 const uint64_t shifted_base =
5487 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5488
5489 if (dst != src) movw(dst, src);
5490 movk(dst, shifted_base >> 32, 32);
5491
5492 if (CompressedKlassPointers::shift() != 0) {
5493 lsl(dst, dst, CompressedKlassPointers::shift());
5494 }
5495
5496 break;
5497 }
5498
5499 case KlassDecodeNone:
5500 ShouldNotReachHere();
5501 break;
5502 }
5503 }
5504
5505 void MacroAssembler::decode_klass_not_null(Register r) {
5506 decode_klass_not_null(r, r);
5507 }
5508
5509 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5510 #ifdef ASSERT
5511 {
5512 ThreadInVMfromUnknown tiv;
5513 assert (UseCompressedOops, "should only be used for compressed oops");
5514 assert (Universe::heap() != nullptr, "java heap should be initialized");
5515 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5516 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5517 }
5518 #endif
5519 int oop_index = oop_recorder()->find_index(obj);
5520 InstructionMark im(this);
5521 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5522 code_section()->relocate(inst_mark(), rspec);
5523 movz(dst, 0xDEAD, 16);
5524 movk(dst, 0xBEEF);
5525 }
5526
5527 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5528 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5529 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5530 int index = oop_recorder()->find_index(k);
5531
5532 InstructionMark im(this);
5533 RelocationHolder rspec = metadata_Relocation::spec(index);
5534 code_section()->relocate(inst_mark(), rspec);
5535 narrowKlass nk = CompressedKlassPointers::encode(k);
5536 movz(dst, (nk >> 16), 16);
5537 movk(dst, nk & 0xffff);
5538 }
5539
5540 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
5541 Register dst, Address src,
5542 Register tmp1, Register tmp2) {
5543 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5544 decorators = AccessInternal::decorator_fixup(decorators, type);
5545 bool as_raw = (decorators & AS_RAW) != 0;
5546 if (as_raw) {
5547 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5548 } else {
5549 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5550 }
5551 }
5552
5553 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5554 Address dst, Register val,
5555 Register tmp1, Register tmp2, Register tmp3) {
5556 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5557 decorators = AccessInternal::decorator_fixup(decorators, type);
5558 bool as_raw = (decorators & AS_RAW) != 0;
5559 if (as_raw) {
5560 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5561 } else {
5562 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5563 }
5564 }
5565
5566 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5567 Register tmp2, DecoratorSet decorators) {
5568 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5569 }
5570
5571 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5572 Register tmp2, DecoratorSet decorators) {
5573 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5574 }
5575
5576 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5577 Register tmp2, Register tmp3, DecoratorSet decorators) {
5578 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5579 }
5580
5581 // Used for storing nulls.
5582 void MacroAssembler::store_heap_oop_null(Address dst) {
5583 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5584 }
5585
5586 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
5587 assert(oop_recorder() != nullptr, "this assembler needs a Recorder");
5588 int index = oop_recorder()->allocate_metadata_index(obj);
5589 RelocationHolder rspec = metadata_Relocation::spec(index);
5590 return Address((address)obj, rspec);
5591 }
5592
5593 // Move an oop into a register.
5594 void MacroAssembler::movoop(Register dst, jobject obj) {
5595 int oop_index;
5596 if (obj == nullptr) {
5597 oop_index = oop_recorder()->allocate_oop_index(obj);
5598 } else {
5599 #ifdef ASSERT
5600 {
5601 ThreadInVMfromUnknown tiv;
5602 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5603 }
5604 #endif
5605 oop_index = oop_recorder()->find_index(obj);
5606 }
5607 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5608
5609 if (BarrierSet::barrier_set()->barrier_set_assembler()->supports_instruction_patching()) {
5610 mov(dst, Address((address)obj, rspec));
5611 } else {
5612 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
5613 ldr(dst, Address(dummy, rspec));
5614 }
5615 }
5616
5617 // Move a metadata address into a register.
5618 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
5619 int oop_index;
5620 if (obj == nullptr) {
5621 oop_index = oop_recorder()->allocate_metadata_index(obj);
5622 } else {
5623 oop_index = oop_recorder()->find_index(obj);
5624 }
5625 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5626 mov(dst, Address((address)obj, rspec));
5627 }
5628
5629 Address MacroAssembler::constant_oop_address(jobject obj) {
5630 #ifdef ASSERT
5631 {
5632 ThreadInVMfromUnknown tiv;
5633 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5634 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5635 }
5636 #endif
5637 int oop_index = oop_recorder()->find_index(obj);
5638 return Address((address)obj, oop_Relocation::spec(oop_index));
5639 }
5640
5641 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5642 void MacroAssembler::tlab_allocate(Register obj,
5643 Register var_size_in_bytes,
5644 int con_size_in_bytes,
5645 Register t1,
5646 Register t2,
5647 Label& slow_case) {
5648 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5649 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5650 }
5651
5652 void MacroAssembler::verify_tlab() {
5653 #ifdef ASSERT
5654 if (UseTLAB && VerifyOops) {
5655 Label next, ok;
5656
5657 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5658
5659 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5660 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5661 cmp(rscratch2, rscratch1);
5662 br(Assembler::HS, next);
5663 STOP("assert(top >= start)");
5664 should_not_reach_here();
5665
5666 bind(next);
5667 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5668 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5669 cmp(rscratch2, rscratch1);
5670 br(Assembler::HS, ok);
5671 STOP("assert(top <= end)");
5672 should_not_reach_here();
5673
5674 bind(ok);
5675 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5676 }
5677 #endif
5678 }
5679
5680 // Writes to stack successive pages until offset reached to check for
5681 // stack overflow + shadow pages. This clobbers tmp.
5682 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5683 assert_different_registers(tmp, size, rscratch1);
5684 mov(tmp, sp);
5685 // Bang stack for total size given plus shadow page size.
5686 // Bang one page at a time because large size can bang beyond yellow and
5687 // red zones.
5688 Label loop;
5689 mov(rscratch1, (int)os::vm_page_size());
5690 bind(loop);
5691 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5692 subsw(size, size, rscratch1);
5693 str(size, Address(tmp));
5694 br(Assembler::GT, loop);
5695
5696 // Bang down shadow pages too.
5697 // At this point, (tmp-0) is the last address touched, so don't
5698 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5699 // was post-decremented.) Skip this address by starting at i=1, and
5700 // touch a few more pages below. N.B. It is important to touch all
5701 // the way down to and including i=StackShadowPages.
5702 for (int i = 0; i < (int)(StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()) - 1; i++) {
5703 // this could be any sized move but this is can be a debugging crumb
5704 // so the bigger the better.
5705 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5706 str(size, Address(tmp));
5707 }
5708 }
5709
5710 // Move the address of the polling page into dest.
5711 void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype) {
5712 ldr(dest, Address(rthread, JavaThread::polling_page_offset()));
5713 }
5714
5715 // Read the polling page. The address of the polling page must
5716 // already be in r.
5717 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
5718 address mark;
5719 {
5720 InstructionMark im(this);
5721 code_section()->relocate(inst_mark(), rtype);
5722 ldrw(zr, Address(r, 0));
5723 mark = inst_mark();
5724 }
5725 verify_cross_modify_fence_not_required();
5726 return mark;
5727 }
5728
5729 void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
5730 uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12;
5731 uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12;
5732 uint64_t dest_page = (uint64_t)dest.target() >> 12;
5733 int64_t offset_low = dest_page - low_page;
5734 int64_t offset_high = dest_page - high_page;
5735
5736 assert(is_valid_AArch64_address(dest.target()), "bad address");
5737 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
5738
5739 InstructionMark im(this);
5740 code_section()->relocate(inst_mark(), dest.rspec());
5741 // 8143067: Ensure that the adrp can reach the dest from anywhere within
5742 // the code cache so that if it is relocated we know it will still reach
5743 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
5744 _adrp(reg1, dest.target());
5745 } else {
5746 uint64_t target = (uint64_t)dest.target();
5747 uint64_t adrp_target
5748 = (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL);
5749
5750 _adrp(reg1, (address)adrp_target);
5751 movk(reg1, target >> 32, 32);
5752 }
5753 byte_offset = (uint64_t)dest.target() & 0xfff;
5754 }
5755
5756 void MacroAssembler::load_byte_map_base(Register reg) {
5757 #if INCLUDE_CDS
5758 if (AOTCodeCache::is_on_for_dump()) {
5759 address byte_map_base_adr = AOTRuntimeConstants::card_table_base_address();
5760 lea(reg, ExternalAddress(byte_map_base_adr));
5761 ldr(reg, Address(reg));
5762 return;
5763 }
5764 #endif
5765 CardTableBarrierSet* ctbs = CardTableBarrierSet::barrier_set();
5766
5767 // Strictly speaking the card table base isn't an address at all, and it might
5768 // even be negative. It is thus materialised as a constant.
5769 mov(reg, (uint64_t)ctbs->card_table_base_const());
5770 }
5771
5772 void MacroAssembler::load_aotrc_address(Register reg, address a) {
5773 #if INCLUDE_CDS
5774 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
5775 if (AOTCodeCache::is_on_for_dump()) {
5776 // all aotrc field addresses should be registered in the AOTCodeCache address table
5777 lea(reg, ExternalAddress(a));
5778 } else {
5779 mov(reg, (uint64_t)a);
5780 }
5781 #else
5782 ShouldNotReachHere();
5783 #endif
5784 }
5785
5786 void MacroAssembler::build_frame(int framesize) {
5787 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5788 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5789 protect_return_address();
5790 if (framesize < ((1 << 9) + 2 * wordSize)) {
5791 sub(sp, sp, framesize);
5792 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5793 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
5794 } else {
5795 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
5796 if (PreserveFramePointer) mov(rfp, sp);
5797 if (framesize < ((1 << 12) + 2 * wordSize))
5798 sub(sp, sp, framesize - 2 * wordSize);
5799 else {
5800 mov(rscratch1, framesize - 2 * wordSize);
5801 sub(sp, sp, rscratch1);
5802 }
5803 }
5804 verify_cross_modify_fence_not_required();
5805 }
5806
5807 void MacroAssembler::remove_frame(int framesize) {
5808 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5809 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5810 if (framesize < ((1 << 9) + 2 * wordSize)) {
5811 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5812 add(sp, sp, framesize);
5813 } else {
5814 if (framesize < ((1 << 12) + 2 * wordSize))
5815 add(sp, sp, framesize - 2 * wordSize);
5816 else {
5817 mov(rscratch1, framesize - 2 * wordSize);
5818 add(sp, sp, rscratch1);
5819 }
5820 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5821 }
5822 authenticate_return_address();
5823 }
5824
5825
5826 // This method counts leading positive bytes (highest bit not set) in provided byte array
5827 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5828 // Simple and most common case of aligned small array which is not at the
5829 // end of memory page is placed here. All other cases are in stub.
5830 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5831 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5832 assert_different_registers(ary1, len, result);
5833
5834 mov(result, len);
5835 cmpw(len, 0);
5836 br(LE, DONE);
5837 cmpw(len, 4 * wordSize);
5838 br(GE, STUB_LONG); // size > 32 then go to stub
5839
5840 int shift = 64 - exact_log2(os::vm_page_size());
5841 lsl(rscratch1, ary1, shift);
5842 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5843 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5844 br(CS, STUB); // at the end of page then go to stub
5845 subs(len, len, wordSize);
5846 br(LT, END);
5847
5848 BIND(LOOP);
5849 ldr(rscratch1, Address(post(ary1, wordSize)));
5850 tst(rscratch1, UPPER_BIT_MASK);
5851 br(NE, SET_RESULT);
5852 subs(len, len, wordSize);
5853 br(GE, LOOP);
5854 cmpw(len, -wordSize);
5855 br(EQ, DONE);
5856
5857 BIND(END);
5858 ldr(rscratch1, Address(ary1));
5859 sub(rscratch2, zr, len, LSL, 3); // LSL 3 is to get bits from bytes
5860 lslv(rscratch1, rscratch1, rscratch2);
5861 tst(rscratch1, UPPER_BIT_MASK);
5862 br(NE, SET_RESULT);
5863 b(DONE);
5864
5865 BIND(STUB);
5866 RuntimeAddress count_pos = RuntimeAddress(StubRoutines::aarch64::count_positives());
5867 assert(count_pos.target() != nullptr, "count_positives stub has not been generated");
5868 address tpc1 = trampoline_call(count_pos);
5869 if (tpc1 == nullptr) {
5870 DEBUG_ONLY(reset_labels(STUB_LONG, SET_RESULT, DONE));
5871 postcond(pc() == badAddress);
5872 return nullptr;
5873 }
5874 b(DONE);
5875
5876 BIND(STUB_LONG);
5877 RuntimeAddress count_pos_long = RuntimeAddress(StubRoutines::aarch64::count_positives_long());
5878 assert(count_pos_long.target() != nullptr, "count_positives_long stub has not been generated");
5879 address tpc2 = trampoline_call(count_pos_long);
5880 if (tpc2 == nullptr) {
5881 DEBUG_ONLY(reset_labels(SET_RESULT, DONE));
5882 postcond(pc() == badAddress);
5883 return nullptr;
5884 }
5885 b(DONE);
5886
5887 BIND(SET_RESULT);
5888
5889 add(len, len, wordSize);
5890 sub(result, result, len);
5891
5892 BIND(DONE);
5893 postcond(pc() != badAddress);
5894 return pc();
5895 }
5896
5897 // Clobbers: rscratch1, rscratch2, rflags
5898 // May also clobber v0-v7 when (!UseSimpleArrayEquals && UseSIMDForArrayEquals)
5899 address MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
5900 Register tmp4, Register tmp5, Register result,
5901 Register cnt1, int elem_size) {
5902 Label DONE, SAME;
5903 Register tmp1 = rscratch1;
5904 Register tmp2 = rscratch2;
5905 int elem_per_word = wordSize/elem_size;
5906 int log_elem_size = exact_log2(elem_size);
5907 int klass_offset = arrayOopDesc::klass_offset_in_bytes();
5908 int length_offset = arrayOopDesc::length_offset_in_bytes();
5909 int base_offset
5910 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
5911 // When the length offset is not aligned to 8 bytes,
5912 // then we align it down. This is valid because the new
5913 // offset will always be the klass which is the same
5914 // for type arrays.
5915 int start_offset = align_down(length_offset, BytesPerWord);
5916 int extra_length = base_offset - start_offset;
5917 assert(start_offset == length_offset || start_offset == klass_offset,
5918 "start offset must be 8-byte-aligned or be the klass offset");
5919 assert(base_offset != start_offset, "must include the length field");
5920 extra_length = extra_length / elem_size; // We count in elements, not bytes.
5921 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16);
5922
5923 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
5924 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5925
5926 #ifndef PRODUCT
5927 {
5928 const char kind = (elem_size == 2) ? 'U' : 'L';
5929 char comment[64];
5930 os::snprintf_checked(comment, sizeof comment, "array_equals%c{", kind);
5931 BLOCK_COMMENT(comment);
5932 }
5933 #endif
5934
5935 // if (a1 == a2)
5936 // return true;
5937 cmpoop(a1, a2); // May have read barriers for a1 and a2.
5938 br(EQ, SAME);
5939
5940 if (UseSimpleArrayEquals) {
5941 Label NEXT_WORD, SHORT, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL;
5942 // if (a1 == nullptr || a2 == nullptr)
5943 // return false;
5944 // a1 & a2 == 0 means (some-pointer is null) or
5945 // (very-rare-or-even-probably-impossible-pointer-values)
5946 // so, we can save one branch in most cases
5947 tst(a1, a2);
5948 mov(result, false);
5949 br(EQ, A_MIGHT_BE_NULL);
5950 // if (a1.length != a2.length)
5951 // return false;
5952 bind(A_IS_NOT_NULL);
5953 ldrw(cnt1, Address(a1, length_offset));
5954 ldrw(tmp5, Address(a2, length_offset));
5955 cmp(cnt1, tmp5);
5956 br(NE, DONE); // If lengths differ, return false
5957 // Increase loop counter by diff between base- and actual start-offset.
5958 addw(cnt1, cnt1, extra_length);
5959 lea(a1, Address(a1, start_offset));
5960 lea(a2, Address(a2, start_offset));
5961 // Check for short strings, i.e. smaller than wordSize.
5962 subs(cnt1, cnt1, elem_per_word);
5963 br(Assembler::LT, SHORT);
5964 // Main 8 byte comparison loop.
5965 bind(NEXT_WORD); {
5966 ldr(tmp1, Address(post(a1, wordSize)));
5967 ldr(tmp2, Address(post(a2, wordSize)));
5968 subs(cnt1, cnt1, elem_per_word);
5969 eor(tmp5, tmp1, tmp2);
5970 cbnz(tmp5, DONE);
5971 } br(GT, NEXT_WORD);
5972 // Last longword. In the case where length == 4 we compare the
5973 // same longword twice, but that's still faster than another
5974 // conditional branch.
5975 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
5976 // length == 4.
5977 if (log_elem_size > 0)
5978 lsl(cnt1, cnt1, log_elem_size);
5979 ldr(tmp3, Address(a1, cnt1));
5980 ldr(tmp4, Address(a2, cnt1));
5981 eor(tmp5, tmp3, tmp4);
5982 cbnz(tmp5, DONE);
5983 b(SAME);
5984 bind(A_MIGHT_BE_NULL);
5985 // in case both a1 and a2 are not-null, proceed with loads
5986 cbz(a1, DONE);
5987 cbz(a2, DONE);
5988 b(A_IS_NOT_NULL);
5989 bind(SHORT);
5990
5991 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
5992 {
5993 ldrw(tmp1, Address(post(a1, 4)));
5994 ldrw(tmp2, Address(post(a2, 4)));
5995 eorw(tmp5, tmp1, tmp2);
5996 cbnzw(tmp5, DONE);
5997 }
5998 bind(TAIL03);
5999 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
6000 {
6001 ldrh(tmp3, Address(post(a1, 2)));
6002 ldrh(tmp4, Address(post(a2, 2)));
6003 eorw(tmp5, tmp3, tmp4);
6004 cbnzw(tmp5, DONE);
6005 }
6006 bind(TAIL01);
6007 if (elem_size == 1) { // Only needed when comparing byte arrays.
6008 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6009 {
6010 ldrb(tmp1, a1);
6011 ldrb(tmp2, a2);
6012 eorw(tmp5, tmp1, tmp2);
6013 cbnzw(tmp5, DONE);
6014 }
6015 }
6016 } else {
6017 Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB,
6018 CSET_EQ, LAST_CHECK;
6019 mov(result, false);
6020 cbz(a1, DONE);
6021 ldrw(cnt1, Address(a1, length_offset));
6022 cbz(a2, DONE);
6023 ldrw(tmp5, Address(a2, length_offset));
6024 cmp(cnt1, tmp5);
6025 br(NE, DONE); // If lengths differ, return false
6026 // Increase loop counter by diff between base- and actual start-offset.
6027 addw(cnt1, cnt1, extra_length);
6028
6029 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's
6030 // faster to perform another branch before comparing a1 and a2
6031 cmp(cnt1, (u1)elem_per_word);
6032 br(LE, SHORT); // short or same
6033 ldr(tmp3, Address(pre(a1, start_offset)));
6034 subs(zr, cnt1, stubBytesThreshold);
6035 br(GE, STUB);
6036 ldr(tmp4, Address(pre(a2, start_offset)));
6037 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6038
6039 // Main 16 byte comparison loop with 2 exits
6040 bind(NEXT_DWORD); {
6041 ldr(tmp1, Address(pre(a1, wordSize)));
6042 ldr(tmp2, Address(pre(a2, wordSize)));
6043 subs(cnt1, cnt1, 2 * elem_per_word);
6044 br(LE, TAIL);
6045 eor(tmp4, tmp3, tmp4);
6046 cbnz(tmp4, DONE);
6047 ldr(tmp3, Address(pre(a1, wordSize)));
6048 ldr(tmp4, Address(pre(a2, wordSize)));
6049 cmp(cnt1, (u1)elem_per_word);
6050 br(LE, TAIL2);
6051 cmp(tmp1, tmp2);
6052 } br(EQ, NEXT_DWORD);
6053 b(DONE);
6054
6055 bind(TAIL);
6056 eor(tmp4, tmp3, tmp4);
6057 eor(tmp2, tmp1, tmp2);
6058 lslv(tmp2, tmp2, tmp5);
6059 orr(tmp5, tmp4, tmp2);
6060 cmp(tmp5, zr);
6061 b(CSET_EQ);
6062
6063 bind(TAIL2);
6064 eor(tmp2, tmp1, tmp2);
6065 cbnz(tmp2, DONE);
6066 b(LAST_CHECK);
6067
6068 bind(STUB);
6069 ldr(tmp4, Address(pre(a2, start_offset)));
6070 if (elem_size == 2) { // convert to byte counter
6071 lsl(cnt1, cnt1, 1);
6072 }
6073 eor(tmp5, tmp3, tmp4);
6074 cbnz(tmp5, DONE);
6075 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
6076 assert(stub.target() != nullptr, "array_equals_long stub has not been generated");
6077 address tpc = trampoline_call(stub);
6078 if (tpc == nullptr) {
6079 DEBUG_ONLY(reset_labels(SHORT, LAST_CHECK, CSET_EQ, SAME, DONE));
6080 postcond(pc() == badAddress);
6081 return nullptr;
6082 }
6083 b(DONE);
6084
6085 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
6086 // so, if a2 == null => return false(0), else return true, so we can return a2
6087 mov(result, a2);
6088 b(DONE);
6089 bind(SHORT);
6090 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6091 ldr(tmp3, Address(a1, start_offset));
6092 ldr(tmp4, Address(a2, start_offset));
6093 bind(LAST_CHECK);
6094 eor(tmp4, tmp3, tmp4);
6095 lslv(tmp5, tmp4, tmp5);
6096 cmp(tmp5, zr);
6097 bind(CSET_EQ);
6098 cset(result, EQ);
6099 b(DONE);
6100 }
6101
6102 bind(SAME);
6103 mov(result, true);
6104 // That's it.
6105 bind(DONE);
6106
6107 BLOCK_COMMENT("} array_equals");
6108 postcond(pc() != badAddress);
6109 return pc();
6110 }
6111
6112 // Compare Strings
6113
6114 // For Strings we're passed the address of the first characters in a1
6115 // and a2 and the length in cnt1.
6116 // There are two implementations. For arrays >= 8 bytes, all
6117 // comparisons (including the final one, which may overlap) are
6118 // performed 8 bytes at a time. For strings < 8 bytes, we compare a
6119 // halfword, then a short, and then a byte.
6120
6121 void MacroAssembler::string_equals(Register a1, Register a2,
6122 Register result, Register cnt1)
6123 {
6124 Label SAME, DONE, SHORT, NEXT_WORD;
6125 Register tmp1 = rscratch1;
6126 Register tmp2 = rscratch2;
6127
6128 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
6129
6130 #ifndef PRODUCT
6131 {
6132 char comment[64];
6133 os::snprintf_checked(comment, sizeof comment, "{string_equalsL");
6134 BLOCK_COMMENT(comment);
6135 }
6136 #endif
6137
6138 mov(result, false);
6139
6140 // Check for short strings, i.e. smaller than wordSize.
6141 subs(cnt1, cnt1, wordSize);
6142 br(Assembler::LT, SHORT);
6143 // Main 8 byte comparison loop.
6144 bind(NEXT_WORD); {
6145 ldr(tmp1, Address(post(a1, wordSize)));
6146 ldr(tmp2, Address(post(a2, wordSize)));
6147 subs(cnt1, cnt1, wordSize);
6148 eor(tmp1, tmp1, tmp2);
6149 cbnz(tmp1, DONE);
6150 } br(GT, NEXT_WORD);
6151 // Last longword. In the case where length == 4 we compare the
6152 // same longword twice, but that's still faster than another
6153 // conditional branch.
6154 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
6155 // length == 4.
6156 ldr(tmp1, Address(a1, cnt1));
6157 ldr(tmp2, Address(a2, cnt1));
6158 eor(tmp2, tmp1, tmp2);
6159 cbnz(tmp2, DONE);
6160 b(SAME);
6161
6162 bind(SHORT);
6163 Label TAIL03, TAIL01;
6164
6165 tbz(cnt1, 2, TAIL03); // 0-7 bytes left.
6166 {
6167 ldrw(tmp1, Address(post(a1, 4)));
6168 ldrw(tmp2, Address(post(a2, 4)));
6169 eorw(tmp1, tmp1, tmp2);
6170 cbnzw(tmp1, DONE);
6171 }
6172 bind(TAIL03);
6173 tbz(cnt1, 1, TAIL01); // 0-3 bytes left.
6174 {
6175 ldrh(tmp1, Address(post(a1, 2)));
6176 ldrh(tmp2, Address(post(a2, 2)));
6177 eorw(tmp1, tmp1, tmp2);
6178 cbnzw(tmp1, DONE);
6179 }
6180 bind(TAIL01);
6181 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6182 {
6183 ldrb(tmp1, a1);
6184 ldrb(tmp2, a2);
6185 eorw(tmp1, tmp1, tmp2);
6186 cbnzw(tmp1, DONE);
6187 }
6188 // Arrays are equal.
6189 bind(SAME);
6190 mov(result, true);
6191
6192 // That's it.
6193 bind(DONE);
6194 BLOCK_COMMENT("} string_equals");
6195 }
6196
6197
6198 // The size of the blocks erased by the zero_blocks stub. We must
6199 // handle anything smaller than this ourselves in zero_words().
6200 const int MacroAssembler::zero_words_block_size = 8;
6201
6202 // zero_words() is used by C2 ClearArray patterns and by
6203 // C1_MacroAssembler. It is as small as possible, handling small word
6204 // counts locally and delegating anything larger to the zero_blocks
6205 // stub. It is expanded many times in compiled code, so it is
6206 // important to keep it short.
6207
6208 // ptr: Address of a buffer to be zeroed.
6209 // cnt: Count in HeapWords.
6210 //
6211 // ptr, cnt, rscratch1, and rscratch2 are clobbered.
6212 address MacroAssembler::zero_words(Register ptr, Register cnt)
6213 {
6214 assert(is_power_of_2(zero_words_block_size), "adjust this");
6215
6216 BLOCK_COMMENT("zero_words {");
6217 assert(ptr == r10 && cnt == r11, "mismatch in register usage");
6218 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6219 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6220
6221 subs(rscratch1, cnt, zero_words_block_size);
6222 Label around;
6223 br(LO, around);
6224 {
6225 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6226 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6227 // Make sure this is a C2 compilation. C1 allocates space only for
6228 // trampoline stubs generated by Call LIR ops, and in any case it
6229 // makes sense for a C1 compilation task to proceed as quickly as
6230 // possible.
6231 CompileTask* task;
6232 if (StubRoutines::aarch64::complete()
6233 && Thread::current()->is_Compiler_thread()
6234 && (task = ciEnv::current()->task())
6235 && is_c2_compile(task->comp_level())) {
6236 address tpc = trampoline_call(zero_blocks);
6237 if (tpc == nullptr) {
6238 DEBUG_ONLY(reset_labels(around));
6239 return nullptr;
6240 }
6241 } else {
6242 far_call(zero_blocks);
6243 }
6244 }
6245 bind(around);
6246
6247 // We have a few words left to do. zero_blocks has adjusted r10 and r11
6248 // for us.
6249 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) {
6250 Label l;
6251 tbz(cnt, exact_log2(i), l);
6252 for (int j = 0; j < i; j += 2) {
6253 stp(zr, zr, post(ptr, 2 * BytesPerWord));
6254 }
6255 bind(l);
6256 }
6257 {
6258 Label l;
6259 tbz(cnt, 0, l);
6260 str(zr, Address(ptr));
6261 bind(l);
6262 }
6263
6264 BLOCK_COMMENT("} zero_words");
6265 return pc();
6266 }
6267
6268 // base: Address of a buffer to be zeroed, 8 bytes aligned.
6269 // cnt: Immediate count in HeapWords.
6270 //
6271 // r10, r11, rscratch1, and rscratch2 are clobbered.
6272 address MacroAssembler::zero_words(Register base, uint64_t cnt)
6273 {
6274 assert(wordSize <= BlockZeroingLowLimit,
6275 "increase BlockZeroingLowLimit");
6276 address result = nullptr;
6277 if (cnt <= (uint64_t)BlockZeroingLowLimit / BytesPerWord) {
6278 #ifndef PRODUCT
6279 {
6280 char buf[64];
6281 os::snprintf_checked(buf, sizeof buf, "zero_words (count = %" PRIu64 ") {", cnt);
6282 BLOCK_COMMENT(buf);
6283 }
6284 #endif
6285 if (cnt >= 16) {
6286 uint64_t loops = cnt/16;
6287 if (loops > 1) {
6288 mov(rscratch2, loops - 1);
6289 }
6290 {
6291 Label loop;
6292 bind(loop);
6293 for (int i = 0; i < 16; i += 2) {
6294 stp(zr, zr, Address(base, i * BytesPerWord));
6295 }
6296 add(base, base, 16 * BytesPerWord);
6297 if (loops > 1) {
6298 subs(rscratch2, rscratch2, 1);
6299 br(GE, loop);
6300 }
6301 }
6302 }
6303 cnt %= 16;
6304 int i = cnt & 1; // store any odd word to start
6305 if (i) str(zr, Address(base));
6306 for (; i < (int)cnt; i += 2) {
6307 stp(zr, zr, Address(base, i * wordSize));
6308 }
6309 BLOCK_COMMENT("} zero_words");
6310 result = pc();
6311 } else {
6312 mov(r10, base); mov(r11, cnt);
6313 result = zero_words(r10, r11);
6314 }
6315 return result;
6316 }
6317
6318 // Zero blocks of memory by using DC ZVA.
6319 //
6320 // Aligns the base address first sufficiently for DC ZVA, then uses
6321 // DC ZVA repeatedly for every full block. cnt is the size to be
6322 // zeroed in HeapWords. Returns the count of words left to be zeroed
6323 // in cnt.
6324 //
6325 // NOTE: This is intended to be used in the zero_blocks() stub. If
6326 // you want to use it elsewhere, note that cnt must be >= 2*zva_length.
6327 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) {
6328 Register tmp = rscratch1;
6329 Register tmp2 = rscratch2;
6330 int zva_length = VM_Version::zva_length();
6331 Label initial_table_end, loop_zva;
6332 Label fini;
6333
6334 // Base must be 16 byte aligned. If not just return and let caller handle it
6335 tst(base, 0x0f);
6336 br(Assembler::NE, fini);
6337 // Align base with ZVA length.
6338 neg(tmp, base);
6339 andr(tmp, tmp, zva_length - 1);
6340
6341 // tmp: the number of bytes to be filled to align the base with ZVA length.
6342 add(base, base, tmp);
6343 sub(cnt, cnt, tmp, Assembler::ASR, 3);
6344 adr(tmp2, initial_table_end);
6345 sub(tmp2, tmp2, tmp, Assembler::LSR, 2);
6346 br(tmp2);
6347
6348 for (int i = -zva_length + 16; i < 0; i += 16)
6349 stp(zr, zr, Address(base, i));
6350 bind(initial_table_end);
6351
6352 sub(cnt, cnt, zva_length >> 3);
6353 bind(loop_zva);
6354 dc(Assembler::ZVA, base);
6355 subs(cnt, cnt, zva_length >> 3);
6356 add(base, base, zva_length);
6357 br(Assembler::GE, loop_zva);
6358 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA
6359 bind(fini);
6360 }
6361
6362 // base: Address of a buffer to be filled, 8 bytes aligned.
6363 // cnt: Count in 8-byte unit.
6364 // value: Value to be filled with.
6365 // base will point to the end of the buffer after filling.
6366 void MacroAssembler::fill_words(Register base, Register cnt, Register value)
6367 {
6368 // Algorithm:
6369 //
6370 // if (cnt == 0) {
6371 // return;
6372 // }
6373 // if ((p & 8) != 0) {
6374 // *p++ = v;
6375 // }
6376 //
6377 // scratch1 = cnt & 14;
6378 // cnt -= scratch1;
6379 // p += scratch1;
6380 // switch (scratch1 / 2) {
6381 // do {
6382 // cnt -= 16;
6383 // p[-16] = v;
6384 // p[-15] = v;
6385 // case 7:
6386 // p[-14] = v;
6387 // p[-13] = v;
6388 // case 6:
6389 // p[-12] = v;
6390 // p[-11] = v;
6391 // // ...
6392 // case 1:
6393 // p[-2] = v;
6394 // p[-1] = v;
6395 // case 0:
6396 // p += 16;
6397 // } while (cnt);
6398 // }
6399 // if ((cnt & 1) == 1) {
6400 // *p++ = v;
6401 // }
6402
6403 assert_different_registers(base, cnt, value, rscratch1, rscratch2);
6404
6405 Label fini, skip, entry, loop;
6406 const int unroll = 8; // Number of stp instructions we'll unroll
6407
6408 cbz(cnt, fini);
6409 tbz(base, 3, skip);
6410 str(value, Address(post(base, 8)));
6411 sub(cnt, cnt, 1);
6412 bind(skip);
6413
6414 andr(rscratch1, cnt, (unroll-1) * 2);
6415 sub(cnt, cnt, rscratch1);
6416 add(base, base, rscratch1, Assembler::LSL, 3);
6417 adr(rscratch2, entry);
6418 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1);
6419 br(rscratch2);
6420
6421 bind(loop);
6422 add(base, base, unroll * 16);
6423 for (int i = -unroll; i < 0; i++)
6424 stp(value, value, Address(base, i * 16));
6425 bind(entry);
6426 subs(cnt, cnt, unroll * 2);
6427 br(Assembler::GE, loop);
6428
6429 tbz(cnt, 0, fini);
6430 str(value, Address(post(base, 8)));
6431 bind(fini);
6432 }
6433
6434 // Intrinsic for
6435 //
6436 // - sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6437 // Encodes char[] to byte[] in ISO-8859-1
6438 //
6439 // - java.lang.StringCoding#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6440 // Encodes byte[] (containing UTF-16) to byte[] in ISO-8859-1
6441 //
6442 // - java.lang.StringCoding#encodeAsciiArray0(char[] sa, int sp, byte[] da, int dp, int len)
6443 // Encodes char[] to byte[] in ASCII
6444 //
6445 // This version always returns the number of characters copied, and does not
6446 // clobber the 'len' register. A successful copy will complete with the post-
6447 // condition: 'res' == 'len', while an unsuccessful copy will exit with the
6448 // post-condition: 0 <= 'res' < 'len'.
6449 //
6450 // NOTE: Attempts to use 'ld2' (and 'umaxv' in the ISO part) has proven to
6451 // degrade performance (on Ampere Altra - Neoverse N1), to an extent
6452 // beyond the acceptable, even though the footprint would be smaller.
6453 // Using 'umaxv' in the ASCII-case comes with a small penalty but does
6454 // avoid additional bloat.
6455 //
6456 // Clobbers: src, dst, res, rscratch1, rscratch2, rflags
6457 void MacroAssembler::encode_iso_array(Register src, Register dst,
6458 Register len, Register res, bool ascii,
6459 FloatRegister vtmp0, FloatRegister vtmp1,
6460 FloatRegister vtmp2, FloatRegister vtmp3,
6461 FloatRegister vtmp4, FloatRegister vtmp5)
6462 {
6463 Register cnt = res;
6464 Register max = rscratch1;
6465 Register chk = rscratch2;
6466
6467 prfm(Address(src), PLDL1STRM);
6468 movw(cnt, len);
6469
6470 #define ASCII(insn) do { if (ascii) { insn; } } while (0)
6471
6472 Label LOOP_32, DONE_32, FAIL_32;
6473
6474 BIND(LOOP_32);
6475 {
6476 cmpw(cnt, 32);
6477 br(LT, DONE_32);
6478 ld1(vtmp0, vtmp1, vtmp2, vtmp3, T8H, Address(post(src, 64)));
6479 // Extract lower bytes.
6480 FloatRegister vlo0 = vtmp4;
6481 FloatRegister vlo1 = vtmp5;
6482 uzp1(vlo0, T16B, vtmp0, vtmp1);
6483 uzp1(vlo1, T16B, vtmp2, vtmp3);
6484 // Merge bits...
6485 orr(vtmp0, T16B, vtmp0, vtmp1);
6486 orr(vtmp2, T16B, vtmp2, vtmp3);
6487 // Extract merged upper bytes.
6488 FloatRegister vhix = vtmp0;
6489 uzp2(vhix, T16B, vtmp0, vtmp2);
6490 // ISO-check on hi-parts (all zero).
6491 // ASCII-check on lo-parts (no sign).
6492 FloatRegister vlox = vtmp1; // Merge lower bytes.
6493 ASCII(orr(vlox, T16B, vlo0, vlo1));
6494 umov(chk, vhix, D, 1); ASCII(cm(LT, vlox, T16B, vlox));
6495 fmovd(max, vhix); ASCII(umaxv(vlox, T16B, vlox));
6496 orr(chk, chk, max); ASCII(umov(max, vlox, B, 0));
6497 ASCII(orr(chk, chk, max));
6498 cbnz(chk, FAIL_32);
6499 subw(cnt, cnt, 32);
6500 st1(vlo0, vlo1, T16B, Address(post(dst, 32)));
6501 b(LOOP_32);
6502 }
6503 BIND(FAIL_32);
6504 sub(src, src, 64);
6505 BIND(DONE_32);
6506
6507 Label LOOP_8, SKIP_8;
6508
6509 BIND(LOOP_8);
6510 {
6511 cmpw(cnt, 8);
6512 br(LT, SKIP_8);
6513 FloatRegister vhi = vtmp0;
6514 FloatRegister vlo = vtmp1;
6515 ld1(vtmp3, T8H, src);
6516 uzp1(vlo, T16B, vtmp3, vtmp3);
6517 uzp2(vhi, T16B, vtmp3, vtmp3);
6518 // ISO-check on hi-parts (all zero).
6519 // ASCII-check on lo-parts (no sign).
6520 ASCII(cm(LT, vtmp2, T16B, vlo));
6521 fmovd(chk, vhi); ASCII(umaxv(vtmp2, T16B, vtmp2));
6522 ASCII(umov(max, vtmp2, B, 0));
6523 ASCII(orr(chk, chk, max));
6524 cbnz(chk, SKIP_8);
6525
6526 strd(vlo, Address(post(dst, 8)));
6527 subw(cnt, cnt, 8);
6528 add(src, src, 16);
6529 b(LOOP_8);
6530 }
6531 BIND(SKIP_8);
6532
6533 #undef ASCII
6534
6535 Label LOOP, DONE;
6536
6537 cbz(cnt, DONE);
6538 BIND(LOOP);
6539 {
6540 Register chr = rscratch1;
6541 ldrh(chr, Address(post(src, 2)));
6542 tst(chr, ascii ? 0xff80 : 0xff00);
6543 br(NE, DONE);
6544 strb(chr, Address(post(dst, 1)));
6545 subs(cnt, cnt, 1);
6546 br(GT, LOOP);
6547 }
6548 BIND(DONE);
6549 // Return index where we stopped.
6550 subw(res, len, cnt);
6551 }
6552
6553 // Inflate byte[] array to char[].
6554 // Clobbers: src, dst, len, rflags, rscratch1, v0-v6
6555 address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
6556 FloatRegister vtmp1, FloatRegister vtmp2,
6557 FloatRegister vtmp3, Register tmp4) {
6558 Label big, done, after_init, to_stub;
6559
6560 assert_different_registers(src, dst, len, tmp4, rscratch1);
6561
6562 fmovd(vtmp1, 0.0);
6563 lsrw(tmp4, len, 3);
6564 bind(after_init);
6565 cbnzw(tmp4, big);
6566 // Short string: less than 8 bytes.
6567 {
6568 Label loop, tiny;
6569
6570 cmpw(len, 4);
6571 br(LT, tiny);
6572 // Use SIMD to do 4 bytes.
6573 ldrs(vtmp2, post(src, 4));
6574 zip1(vtmp3, T8B, vtmp2, vtmp1);
6575 subw(len, len, 4);
6576 strd(vtmp3, post(dst, 8));
6577
6578 cbzw(len, done);
6579
6580 // Do the remaining bytes by steam.
6581 bind(loop);
6582 ldrb(tmp4, post(src, 1));
6583 strh(tmp4, post(dst, 2));
6584 subw(len, len, 1);
6585
6586 bind(tiny);
6587 cbnz(len, loop);
6588
6589 b(done);
6590 }
6591
6592 if (SoftwarePrefetchHintDistance >= 0) {
6593 bind(to_stub);
6594 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate());
6595 assert(stub.target() != nullptr, "large_byte_array_inflate stub has not been generated");
6596 address tpc = trampoline_call(stub);
6597 if (tpc == nullptr) {
6598 DEBUG_ONLY(reset_labels(big, done));
6599 postcond(pc() == badAddress);
6600 return nullptr;
6601 }
6602 b(after_init);
6603 }
6604
6605 // Unpack the bytes 8 at a time.
6606 bind(big);
6607 {
6608 Label loop, around, loop_last, loop_start;
6609
6610 if (SoftwarePrefetchHintDistance >= 0) {
6611 const int large_loop_threshold = (64 + 16)/8;
6612 ldrd(vtmp2, post(src, 8));
6613 andw(len, len, 7);
6614 cmp(tmp4, (u1)large_loop_threshold);
6615 br(GE, to_stub);
6616 b(loop_start);
6617
6618 bind(loop);
6619 ldrd(vtmp2, post(src, 8));
6620 bind(loop_start);
6621 subs(tmp4, tmp4, 1);
6622 br(EQ, loop_last);
6623 zip1(vtmp2, T16B, vtmp2, vtmp1);
6624 ldrd(vtmp3, post(src, 8));
6625 st1(vtmp2, T8H, post(dst, 16));
6626 subs(tmp4, tmp4, 1);
6627 zip1(vtmp3, T16B, vtmp3, vtmp1);
6628 st1(vtmp3, T8H, post(dst, 16));
6629 br(NE, loop);
6630 b(around);
6631 bind(loop_last);
6632 zip1(vtmp2, T16B, vtmp2, vtmp1);
6633 st1(vtmp2, T8H, post(dst, 16));
6634 bind(around);
6635 cbz(len, done);
6636 } else {
6637 andw(len, len, 7);
6638 bind(loop);
6639 ldrd(vtmp2, post(src, 8));
6640 sub(tmp4, tmp4, 1);
6641 zip1(vtmp3, T16B, vtmp2, vtmp1);
6642 st1(vtmp3, T8H, post(dst, 16));
6643 cbnz(tmp4, loop);
6644 }
6645 }
6646
6647 // Do the tail of up to 8 bytes.
6648 add(src, src, len);
6649 ldrd(vtmp3, Address(src, -8));
6650 add(dst, dst, len, ext::uxtw, 1);
6651 zip1(vtmp3, T16B, vtmp3, vtmp1);
6652 strq(vtmp3, Address(dst, -16));
6653
6654 bind(done);
6655 postcond(pc() != badAddress);
6656 return pc();
6657 }
6658
6659 // Compress char[] array to byte[].
6660 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
6661 // Return the array length if every element in array can be encoded,
6662 // otherwise, the index of first non-latin1 (> 0xff) character.
6663 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
6664 Register res,
6665 FloatRegister tmp0, FloatRegister tmp1,
6666 FloatRegister tmp2, FloatRegister tmp3,
6667 FloatRegister tmp4, FloatRegister tmp5) {
6668 encode_iso_array(src, dst, len, res, false, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5);
6669 }
6670
6671 // java.math.round(double a)
6672 // Returns the closest long to the argument, with ties rounding to
6673 // positive infinity. This requires some fiddling for corner
6674 // cases. We take care to avoid double rounding in e.g. (jlong)(a + 0.5).
6675 void MacroAssembler::java_round_double(Register dst, FloatRegister src,
6676 FloatRegister ftmp) {
6677 Label DONE;
6678 BLOCK_COMMENT("java_round_double: { ");
6679 fmovd(rscratch1, src);
6680 // Use RoundToNearestTiesAway unless src small and -ve.
6681 fcvtasd(dst, src);
6682 // Test if src >= 0 || abs(src) >= 0x1.0p52
6683 eor(rscratch1, rscratch1, UCONST64(1) << 63); // flip sign bit
6684 mov(rscratch2, julong_cast(0x1.0p52));
6685 cmp(rscratch1, rscratch2);
6686 br(HS, DONE); {
6687 // src < 0 && abs(src) < 0x1.0p52
6688 // src may have a fractional part, so add 0.5
6689 fmovd(ftmp, 0.5);
6690 faddd(ftmp, src, ftmp);
6691 // Convert double to jlong, use RoundTowardsNegative
6692 fcvtmsd(dst, ftmp);
6693 }
6694 bind(DONE);
6695 BLOCK_COMMENT("} java_round_double");
6696 }
6697
6698 void MacroAssembler::java_round_float(Register dst, FloatRegister src,
6699 FloatRegister ftmp) {
6700 Label DONE;
6701 BLOCK_COMMENT("java_round_float: { ");
6702 fmovs(rscratch1, src);
6703 // Use RoundToNearestTiesAway unless src small and -ve.
6704 fcvtassw(dst, src);
6705 // Test if src >= 0 || abs(src) >= 0x1.0p23
6706 eor(rscratch1, rscratch1, 0x80000000); // flip sign bit
6707 mov(rscratch2, jint_cast(0x1.0p23f));
6708 cmp(rscratch1, rscratch2);
6709 br(HS, DONE); {
6710 // src < 0 && |src| < 0x1.0p23
6711 // src may have a fractional part, so add 0.5
6712 fmovs(ftmp, 0.5f);
6713 fadds(ftmp, src, ftmp);
6714 // Convert float to jint, use RoundTowardsNegative
6715 fcvtmssw(dst, ftmp);
6716 }
6717 bind(DONE);
6718 BLOCK_COMMENT("} java_round_float");
6719 }
6720
6721 // get_thread() can be called anywhere inside generated code so we
6722 // need to save whatever non-callee save context might get clobbered
6723 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
6724 // the call setup code.
6725 //
6726 // On Linux, aarch64_get_thread_helper() clobbers only r0, r1, and flags.
6727 // On other systems, the helper is a usual C function.
6728 //
6729 void MacroAssembler::get_thread(Register dst) {
6730 RegSet saved_regs =
6731 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6732 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6733
6734 protect_return_address();
6735 push(saved_regs, sp);
6736
6737 mov(lr, ExternalAddress(CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)));
6738 blr(lr);
6739 if (dst != c_rarg0) {
6740 mov(dst, c_rarg0);
6741 }
6742
6743 pop(saved_regs, sp);
6744 authenticate_return_address();
6745 }
6746
6747 void MacroAssembler::cache_wb(Address line) {
6748 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
6749 assert(line.index() == noreg, "index should be noreg");
6750 assert(line.offset() == 0, "offset should be 0");
6751 // would like to assert this
6752 // assert(line._ext.shift == 0, "shift should be zero");
6753 if (VM_Version::supports_dcpop()) {
6754 // writeback using clear virtual address to point of persistence
6755 dc(Assembler::CVAP, line.base());
6756 } else {
6757 // no need to generate anything as Unsafe.writebackMemory should
6758 // never invoke this stub
6759 }
6760 }
6761
6762 void MacroAssembler::cache_wbsync(bool is_pre) {
6763 // we only need a barrier post sync
6764 if (!is_pre) {
6765 membar(Assembler::AnyAny);
6766 }
6767 }
6768
6769 void MacroAssembler::verify_sve_vector_length(Register tmp) {
6770 if (!UseSVE || VM_Version::get_max_supported_sve_vector_length() == FloatRegister::sve_vl_min) {
6771 return;
6772 }
6773 // Make sure that native code does not change SVE vector length.
6774 Label verify_ok;
6775 movw(tmp, zr);
6776 sve_inc(tmp, B);
6777 subsw(zr, tmp, VM_Version::get_initial_sve_vector_length());
6778 br(EQ, verify_ok);
6779 stop("Error: SVE vector length has changed since jvm startup");
6780 bind(verify_ok);
6781 }
6782
6783 void MacroAssembler::verify_ptrue() {
6784 Label verify_ok;
6785 if (!UseSVE) {
6786 return;
6787 }
6788 sve_cntp(rscratch1, B, ptrue, ptrue); // get true elements count.
6789 sve_dec(rscratch1, B);
6790 cbz(rscratch1, verify_ok);
6791 stop("Error: the preserved predicate register (p7) elements are not all true");
6792 bind(verify_ok);
6793 }
6794
6795 void MacroAssembler::safepoint_isb() {
6796 isb();
6797 #ifndef PRODUCT
6798 if (VerifyCrossModifyFence) {
6799 // Clear the thread state.
6800 strb(zr, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6801 }
6802 #endif
6803 }
6804
6805 #ifndef PRODUCT
6806 void MacroAssembler::verify_cross_modify_fence_not_required() {
6807 if (VerifyCrossModifyFence) {
6808 // Check if thread needs a cross modify fence.
6809 ldrb(rscratch1, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6810 Label fence_not_required;
6811 cbz(rscratch1, fence_not_required);
6812 // If it does then fail.
6813 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::verify_cross_modify_fence_failure)));
6814 mov(c_rarg0, rthread);
6815 blr(rscratch1);
6816 bind(fence_not_required);
6817 }
6818 }
6819 #endif
6820
6821 void MacroAssembler::spin_wait() {
6822 block_comment("spin_wait {");
6823 for (int i = 0; i < VM_Version::spin_wait_desc().inst_count(); ++i) {
6824 switch (VM_Version::spin_wait_desc().inst()) {
6825 case SpinWait::NOP:
6826 nop();
6827 break;
6828 case SpinWait::ISB:
6829 isb();
6830 break;
6831 case SpinWait::YIELD:
6832 yield();
6833 break;
6834 case SpinWait::SB:
6835 assert(VM_Version::supports_sb(), "current CPU does not support SB instruction");
6836 sb();
6837 break;
6838 default:
6839 ShouldNotReachHere();
6840 }
6841 }
6842 block_comment("}");
6843 }
6844
6845 // Stack frame creation/removal
6846
6847 void MacroAssembler::enter(bool strip_ret_addr) {
6848 if (strip_ret_addr) {
6849 // Addresses can only be signed once. If there are multiple nested frames being created
6850 // in the same function, then the return address needs stripping first.
6851 strip_return_address();
6852 }
6853 protect_return_address();
6854 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
6855 mov(rfp, sp);
6856 }
6857
6858 void MacroAssembler::leave() {
6859 mov(sp, rfp);
6860 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
6861 authenticate_return_address();
6862 }
6863
6864 // ROP Protection
6865 // Use the AArch64 PAC feature to add ROP protection for generated code. Use whenever creating/
6866 // destroying stack frames or whenever directly loading/storing the LR to memory.
6867 // If ROP protection is not set then these functions are no-ops.
6868 // For more details on PAC see pauth_aarch64.hpp.
6869
6870 // Sign the LR. Use during construction of a stack frame, before storing the LR to memory.
6871 // Uses value zero as the modifier.
6872 //
6873 void MacroAssembler::protect_return_address() {
6874 if (VM_Version::use_rop_protection()) {
6875 check_return_address();
6876 paciaz();
6877 }
6878 }
6879
6880 // Sign the return value in the given register. Use before updating the LR in the existing stack
6881 // frame for the current function.
6882 // Uses value zero as the modifier.
6883 //
6884 void MacroAssembler::protect_return_address(Register return_reg) {
6885 if (VM_Version::use_rop_protection()) {
6886 check_return_address(return_reg);
6887 paciza(return_reg);
6888 }
6889 }
6890
6891 // Authenticate the LR. Use before function return, after restoring FP and loading LR from memory.
6892 // Uses value zero as the modifier.
6893 //
6894 void MacroAssembler::authenticate_return_address() {
6895 if (VM_Version::use_rop_protection()) {
6896 autiaz();
6897 check_return_address();
6898 }
6899 }
6900
6901 // Authenticate the return value in the given register. Use before updating the LR in the existing
6902 // stack frame for the current function.
6903 // Uses value zero as the modifier.
6904 //
6905 void MacroAssembler::authenticate_return_address(Register return_reg) {
6906 if (VM_Version::use_rop_protection()) {
6907 autiza(return_reg);
6908 check_return_address(return_reg);
6909 }
6910 }
6911
6912 // Strip any PAC data from LR without performing any authentication. Use with caution - only if
6913 // there is no guaranteed way of authenticating the LR.
6914 //
6915 void MacroAssembler::strip_return_address() {
6916 if (VM_Version::use_rop_protection()) {
6917 xpaclri();
6918 }
6919 }
6920
6921 #ifndef PRODUCT
6922 // PAC failures can be difficult to debug. After an authentication failure, a segfault will only
6923 // occur when the pointer is used - ie when the program returns to the invalid LR. At this point
6924 // it is difficult to debug back to the callee function.
6925 // This function simply loads from the address in the given register.
6926 // Use directly after authentication to catch authentication failures.
6927 // Also use before signing to check that the pointer is valid and hasn't already been signed.
6928 //
6929 void MacroAssembler::check_return_address(Register return_reg) {
6930 if (VM_Version::use_rop_protection()) {
6931 ldr(zr, Address(return_reg));
6932 }
6933 }
6934 #endif
6935
6936 // The java_calling_convention describes stack locations as ideal slots on
6937 // a frame with no abi restrictions. Since we must observe abi restrictions
6938 // (like the placement of the register window) the slots must be biased by
6939 // the following value.
6940 static int reg2offset_in(VMReg r) {
6941 // Account for saved rfp and lr
6942 // This should really be in_preserve_stack_slots
6943 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
6944 }
6945
6946 static int reg2offset_out(VMReg r) {
6947 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
6948 }
6949
6950 // On 64bit we will store integer like items to the stack as
6951 // 64bits items (AArch64 ABI) even though java would only store
6952 // 32bits for a parameter. On 32bit it will simply be 32bits
6953 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
6954 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp) {
6955 if (src.first()->is_stack()) {
6956 if (dst.first()->is_stack()) {
6957 // stack to stack
6958 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
6959 str(tmp, Address(sp, reg2offset_out(dst.first())));
6960 } else {
6961 // stack to reg
6962 ldrsw(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
6963 }
6964 } else if (dst.first()->is_stack()) {
6965 // reg to stack
6966 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
6967 } else {
6968 if (dst.first() != src.first()) {
6969 sxtw(dst.first()->as_Register(), src.first()->as_Register());
6970 }
6971 }
6972 }
6973
6974 // An oop arg. Must pass a handle not the oop itself
6975 void MacroAssembler::object_move(
6976 OopMap* map,
6977 int oop_handle_offset,
6978 int framesize_in_slots,
6979 VMRegPair src,
6980 VMRegPair dst,
6981 bool is_receiver,
6982 int* receiver_offset) {
6983
6984 // must pass a handle. First figure out the location we use as a handle
6985
6986 Register rHandle = dst.first()->is_stack() ? rscratch2 : dst.first()->as_Register();
6987
6988 // See if oop is null if it is we need no handle
6989
6990 if (src.first()->is_stack()) {
6991
6992 // Oop is already on the stack as an argument
6993 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
6994 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
6995 if (is_receiver) {
6996 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
6997 }
6998
6999 ldr(rscratch1, Address(rfp, reg2offset_in(src.first())));
7000 lea(rHandle, Address(rfp, reg2offset_in(src.first())));
7001 // conditionally move a null
7002 cmp(rscratch1, zr);
7003 csel(rHandle, zr, rHandle, Assembler::EQ);
7004 } else {
7005
7006 // Oop is in an a register we must store it to the space we reserve
7007 // on the stack for oop_handles and pass a handle if oop is non-null
7008
7009 const Register rOop = src.first()->as_Register();
7010 int oop_slot;
7011 if (rOop == j_rarg0)
7012 oop_slot = 0;
7013 else if (rOop == j_rarg1)
7014 oop_slot = 1;
7015 else if (rOop == j_rarg2)
7016 oop_slot = 2;
7017 else if (rOop == j_rarg3)
7018 oop_slot = 3;
7019 else if (rOop == j_rarg4)
7020 oop_slot = 4;
7021 else if (rOop == j_rarg5)
7022 oop_slot = 5;
7023 else if (rOop == j_rarg6)
7024 oop_slot = 6;
7025 else {
7026 assert(rOop == j_rarg7, "wrong register");
7027 oop_slot = 7;
7028 }
7029
7030 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
7031 int offset = oop_slot*VMRegImpl::stack_slot_size;
7032
7033 map->set_oop(VMRegImpl::stack2reg(oop_slot));
7034 // Store oop in handle area, may be null
7035 str(rOop, Address(sp, offset));
7036 if (is_receiver) {
7037 *receiver_offset = offset;
7038 }
7039
7040 cmp(rOop, zr);
7041 lea(rHandle, Address(sp, offset));
7042 // conditionally move a null
7043 csel(rHandle, zr, rHandle, Assembler::EQ);
7044 }
7045
7046 // If arg is on the stack then place it otherwise it is already in correct reg.
7047 if (dst.first()->is_stack()) {
7048 str(rHandle, Address(sp, reg2offset_out(dst.first())));
7049 }
7050 }
7051
7052 // A float arg may have to do float reg int reg conversion
7053 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp) {
7054 if (src.first()->is_stack()) {
7055 if (dst.first()->is_stack()) {
7056 ldrw(tmp, Address(rfp, reg2offset_in(src.first())));
7057 strw(tmp, Address(sp, reg2offset_out(dst.first())));
7058 } else {
7059 ldrs(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7060 }
7061 } else if (src.first() != dst.first()) {
7062 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7063 fmovs(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7064 else
7065 strs(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7066 }
7067 }
7068
7069 // A long move
7070 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp) {
7071 if (src.first()->is_stack()) {
7072 if (dst.first()->is_stack()) {
7073 // stack to stack
7074 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7075 str(tmp, Address(sp, reg2offset_out(dst.first())));
7076 } else {
7077 // stack to reg
7078 ldr(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
7079 }
7080 } else if (dst.first()->is_stack()) {
7081 // reg to stack
7082 // Do we really have to sign extend???
7083 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
7084 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
7085 } else {
7086 if (dst.first() != src.first()) {
7087 mov(dst.first()->as_Register(), src.first()->as_Register());
7088 }
7089 }
7090 }
7091
7092
7093 // A double move
7094 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp) {
7095 if (src.first()->is_stack()) {
7096 if (dst.first()->is_stack()) {
7097 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7098 str(tmp, Address(sp, reg2offset_out(dst.first())));
7099 } else {
7100 ldrd(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7101 }
7102 } else if (src.first() != dst.first()) {
7103 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7104 fmovd(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7105 else
7106 strd(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7107 }
7108 }
7109
7110 // Implements fast-locking.
7111 //
7112 // - obj: the object to be locked
7113 // - t1, t2, t3: temporary registers, will be destroyed
7114 // - slow: branched to if locking fails, absolute offset may larger than 32KB (imm14 encoding).
7115 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow) {
7116 assert_different_registers(basic_lock, obj, t1, t2, t3, rscratch1);
7117
7118 Label push;
7119 const Register top = t1;
7120 const Register mark = t2;
7121 const Register t = t3;
7122
7123 // Preload the markWord. It is important that this is the first
7124 // instruction emitted as it is part of C1's null check semantics.
7125 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7126
7127 if (UseObjectMonitorTable) {
7128 // Clear cache in case fast locking succeeds or we need to take the slow-path.
7129 str(zr, Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))));
7130 }
7131
7132 if (DiagnoseSyncOnValueBasedClasses != 0) {
7133 load_klass(t1, obj);
7134 ldrb(t1, Address(t1, Klass::misc_flags_offset()));
7135 tst(t1, KlassFlags::_misc_is_value_based_class);
7136 br(Assembler::NE, slow);
7137 }
7138
7139 // Check if the lock-stack is full.
7140 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7141 cmpw(top, (unsigned)LockStack::end_offset());
7142 br(Assembler::GE, slow);
7143
7144 // Check for recursion.
7145 subw(t, top, oopSize);
7146 ldr(t, Address(rthread, t));
7147 cmp(obj, t);
7148 br(Assembler::EQ, push);
7149
7150 // Check header for monitor (0b10).
7151 tst(mark, markWord::monitor_value);
7152 br(Assembler::NE, slow);
7153
7154 // Try to lock. Transition lock bits 0b01 => 0b00
7155 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7156 orr(mark, mark, markWord::unlocked_value);
7157 eor(t, mark, markWord::unlocked_value);
7158 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
7159 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
7160 br(Assembler::NE, slow);
7161
7162 bind(push);
7163 // After successful lock, push object on lock-stack.
7164 str(obj, Address(rthread, top));
7165 addw(top, top, oopSize);
7166 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7167 }
7168
7169 // Implements fast-unlocking.
7170 //
7171 // - obj: the object to be unlocked
7172 // - t1, t2, t3: temporary registers
7173 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
7174 void MacroAssembler::fast_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
7175 // cmpxchg clobbers rscratch1.
7176 assert_different_registers(obj, t1, t2, t3, rscratch1);
7177
7178 #ifdef ASSERT
7179 {
7180 // Check for lock-stack underflow.
7181 Label stack_ok;
7182 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
7183 cmpw(t1, (unsigned)LockStack::start_offset());
7184 br(Assembler::GE, stack_ok);
7185 STOP("Lock-stack underflow");
7186 bind(stack_ok);
7187 }
7188 #endif
7189
7190 Label unlocked, push_and_slow;
7191 const Register top = t1;
7192 const Register mark = t2;
7193 const Register t = t3;
7194
7195 // Check if obj is top of lock-stack.
7196 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7197 subw(top, top, oopSize);
7198 ldr(t, Address(rthread, top));
7199 cmp(obj, t);
7200 br(Assembler::NE, slow);
7201
7202 // Pop lock-stack.
7203 DEBUG_ONLY(str(zr, Address(rthread, top));)
7204 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7205
7206 // Check if recursive.
7207 subw(t, top, oopSize);
7208 ldr(t, Address(rthread, t));
7209 cmp(obj, t);
7210 br(Assembler::EQ, unlocked);
7211
7212 // Not recursive. Check header for monitor (0b10).
7213 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7214 tbnz(mark, log2i_exact(markWord::monitor_value), push_and_slow);
7215
7216 #ifdef ASSERT
7217 // Check header not unlocked (0b01).
7218 Label not_unlocked;
7219 tbz(mark, log2i_exact(markWord::unlocked_value), not_unlocked);
7220 stop("fast_unlock already unlocked");
7221 bind(not_unlocked);
7222 #endif
7223
7224 // Try to unlock. Transition lock bits 0b00 => 0b01
7225 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7226 orr(t, mark, markWord::unlocked_value);
7227 cmpxchg(obj, mark, t, Assembler::xword,
7228 /*acquire*/ false, /*release*/ true, /*weak*/ false, noreg);
7229 br(Assembler::EQ, unlocked);
7230
7231 bind(push_and_slow);
7232 // Restore lock-stack and handle the unlock in runtime.
7233 DEBUG_ONLY(str(obj, Address(rthread, top));)
7234 addw(top, top, oopSize);
7235 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7236 b(slow);
7237
7238 bind(unlocked);
7239 }