1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "ci/ciEnv.hpp"
30 #include "code/compiledIC.hpp"
31 #include "compiler/compileTask.hpp"
32 #include "compiler/disassembler.hpp"
33 #include "compiler/oopMap.hpp"
34 #include "gc/shared/barrierSet.hpp"
35 #include "gc/shared/barrierSetAssembler.hpp"
36 #include "gc/shared/cardTableBarrierSet.hpp"
37 #include "gc/shared/cardTable.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/tlab_globals.hpp"
40 #include "interpreter/bytecodeHistogram.hpp"
41 #include "interpreter/interpreter.hpp"
42 #include "jvm.h"
43 #include "memory/resourceArea.hpp"
44 #include "memory/universe.hpp"
45 #include "nativeInst_aarch64.hpp"
46 #include "oops/accessDecorators.hpp"
47 #include "oops/compressedKlass.inline.hpp"
48 #include "oops/compressedOops.inline.hpp"
49 #include "oops/klass.inline.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/icache.hpp"
52 #include "runtime/interfaceSupport.inline.hpp"
53 #include "runtime/javaThread.hpp"
54 #include "runtime/jniHandles.inline.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/globalDefinitions.hpp"
58 #include "utilities/powerOfTwo.hpp"
59 #ifdef COMPILER1
60 #include "c1/c1_LIRAssembler.hpp"
61 #endif
62 #ifdef COMPILER2
63 #include "oops/oop.hpp"
64 #include "opto/compile.hpp"
65 #include "opto/node.hpp"
66 #include "opto/output.hpp"
67 #endif
68
69 #include <sys/types.h>
70
71 #ifdef PRODUCT
72 #define BLOCK_COMMENT(str) /* nothing */
73 #else
74 #define BLOCK_COMMENT(str) block_comment(str)
75 #endif
76 #define STOP(str) stop(str);
77 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
78
79 #ifdef ASSERT
80 extern "C" void disnm(intptr_t p);
81 #endif
82 // Target-dependent relocation processing
83 //
84 // Instruction sequences whose target may need to be retrieved or
85 // patched are distinguished by their leading instruction, sorting
86 // them into three main instruction groups and related subgroups.
87 //
88 // 1) Branch, Exception and System (insn count = 1)
89 // 1a) Unconditional branch (immediate):
90 // b/bl imm19
91 // 1b) Compare & branch (immediate):
92 // cbz/cbnz Rt imm19
93 // 1c) Test & branch (immediate):
94 // tbz/tbnz Rt imm14
95 // 1d) Conditional branch (immediate):
96 // b.cond imm19
97 //
98 // 2) Loads and Stores (insn count = 1)
99 // 2a) Load register literal:
100 // ldr Rt imm19
101 //
102 // 3) Data Processing Immediate (insn count = 2 or 3)
103 // 3a) PC-rel. addressing
104 // adr/adrp Rx imm21; ldr/str Ry Rx #imm12
105 // adr/adrp Rx imm21; add Ry Rx #imm12
106 // adr/adrp Rx imm21; movk Rx #imm16<<32; ldr/str Ry, [Rx, #offset_in_page]
107 // adr/adrp Rx imm21
108 // adr/adrp Rx imm21; movk Rx #imm16<<32
109 // adr/adrp Rx imm21; movk Rx #imm16<<32; add Ry, Rx, #offset_in_page
110 // The latter form can only happen when the target is an
111 // ExternalAddress, and (by definition) ExternalAddresses don't
112 // move. Because of that property, there is never any need to
113 // patch the last of the three instructions. However,
114 // MacroAssembler::target_addr_for_insn takes all three
115 // instructions into account and returns the correct address.
116 // 3b) Move wide (immediate)
117 // movz Rx #imm16; movk Rx #imm16 << 16; movk Rx #imm16 << 32;
118 //
119 // A switch on a subset of the instruction's bits provides an
120 // efficient dispatch to these subcases.
121 //
122 // insn[28:26] -> main group ('x' == don't care)
123 // 00x -> UNALLOCATED
124 // 100 -> Data Processing Immediate
125 // 101 -> Branch, Exception and System
126 // x1x -> Loads and Stores
127 //
128 // insn[30:25] -> subgroup ('_' == group, 'x' == don't care).
129 // n.b. in some cases extra bits need to be checked to verify the
130 // instruction is as expected
131 //
132 // 1) ... xx101x Branch, Exception and System
133 // 1a) 00___x Unconditional branch (immediate)
134 // 1b) 01___0 Compare & branch (immediate)
135 // 1c) 01___1 Test & branch (immediate)
136 // 1d) 10___0 Conditional branch (immediate)
137 // other Should not happen
138 //
139 // 2) ... xxx1x0 Loads and Stores
140 // 2a) xx1__00 Load/Store register (insn[28] == 1 && insn[24] == 0)
141 // 2aa) x01__00 Load register literal (i.e. requires insn[29] == 0)
142 // strictly should be 64 bit non-FP/SIMD i.e.
143 // 0101_000 (i.e. requires insn[31:24] == 01011000)
144 //
145 // 3) ... xx100x Data Processing Immediate
146 // 3a) xx___00 PC-rel. addressing (n.b. requires insn[24] == 0)
147 // 3b) xx___101 Move wide (immediate) (n.b. requires insn[24:23] == 01)
148 // strictly should be 64 bit movz #imm16<<0
149 // 110___10100 (i.e. requires insn[31:21] == 11010010100)
150 //
151 class RelocActions {
152 protected:
153 typedef int (*reloc_insn)(address insn_addr, address &target);
154
155 virtual reloc_insn adrpMem() = 0;
156 virtual reloc_insn adrpAdd() = 0;
157 virtual reloc_insn adrpMovk() = 0;
158
159 const address _insn_addr;
160 const uint32_t _insn;
161
162 static uint32_t insn_at(address insn_addr, int n) {
163 return ((uint32_t*)insn_addr)[n];
164 }
165 uint32_t insn_at(int n) const {
166 return insn_at(_insn_addr, n);
167 }
168
169 public:
170
171 RelocActions(address insn_addr) : _insn_addr(insn_addr), _insn(insn_at(insn_addr, 0)) {}
172 RelocActions(address insn_addr, uint32_t insn)
173 : _insn_addr(insn_addr), _insn(insn) {}
174
175 virtual int unconditionalBranch(address insn_addr, address &target) = 0;
176 virtual int conditionalBranch(address insn_addr, address &target) = 0;
177 virtual int testAndBranch(address insn_addr, address &target) = 0;
178 virtual int loadStore(address insn_addr, address &target) = 0;
179 virtual int adr(address insn_addr, address &target) = 0;
180 virtual int adrp(address insn_addr, address &target, reloc_insn inner) = 0;
181 virtual int immediate(address insn_addr, address &target) = 0;
182 virtual void verify(address insn_addr, address &target) = 0;
183
184 int ALWAYSINLINE run(address insn_addr, address &target) {
185 int instructions = 1;
186
187 uint32_t dispatch = Instruction_aarch64::extract(_insn, 30, 25);
188 switch(dispatch) {
189 case 0b001010:
190 case 0b001011: {
191 instructions = unconditionalBranch(insn_addr, target);
192 break;
193 }
194 case 0b101010: // Conditional branch (immediate)
195 case 0b011010: { // Compare & branch (immediate)
196 instructions = conditionalBranch(insn_addr, target);
197 break;
198 }
199 case 0b011011: {
200 instructions = testAndBranch(insn_addr, target);
201 break;
202 }
203 case 0b001100:
204 case 0b001110:
205 case 0b011100:
206 case 0b011110:
207 case 0b101100:
208 case 0b101110:
209 case 0b111100:
210 case 0b111110: {
211 // load/store
212 if ((Instruction_aarch64::extract(_insn, 29, 24) & 0b111011) == 0b011000) {
213 // Load register (literal)
214 instructions = loadStore(insn_addr, target);
215 break;
216 } else {
217 // nothing to do
218 assert(target == 0, "did not expect to relocate target for polling page load");
219 }
220 break;
221 }
222 case 0b001000:
223 case 0b011000:
224 case 0b101000:
225 case 0b111000: {
226 // adr/adrp
227 assert(Instruction_aarch64::extract(_insn, 28, 24) == 0b10000, "must be");
228 int shift = Instruction_aarch64::extract(_insn, 31, 31);
229 if (shift) {
230 uint32_t insn2 = insn_at(1);
231 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
232 Instruction_aarch64::extract(_insn, 4, 0) ==
233 Instruction_aarch64::extract(insn2, 9, 5)) {
234 instructions = adrp(insn_addr, target, adrpMem());
235 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
236 Instruction_aarch64::extract(_insn, 4, 0) ==
237 Instruction_aarch64::extract(insn2, 4, 0)) {
238 instructions = adrp(insn_addr, target, adrpAdd());
239 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
240 Instruction_aarch64::extract(_insn, 4, 0) ==
241 Instruction_aarch64::extract(insn2, 4, 0)) {
242 instructions = adrp(insn_addr, target, adrpMovk());
243 } else {
244 ShouldNotReachHere();
245 }
246 } else {
247 instructions = adr(insn_addr, target);
248 }
249 break;
250 }
251 case 0b001001:
252 case 0b011001:
253 case 0b101001:
254 case 0b111001: {
255 instructions = immediate(insn_addr, target);
256 break;
257 }
258 default: {
259 ShouldNotReachHere();
260 }
261 }
262
263 verify(insn_addr, target);
264 return instructions * NativeInstruction::instruction_size;
265 }
266 };
267
268 class Patcher : public RelocActions {
269 virtual reloc_insn adrpMem() { return &Patcher::adrpMem_impl; }
270 virtual reloc_insn adrpAdd() { return &Patcher::adrpAdd_impl; }
271 virtual reloc_insn adrpMovk() { return &Patcher::adrpMovk_impl; }
272
273 public:
274 Patcher(address insn_addr) : RelocActions(insn_addr) {}
275
276 virtual int unconditionalBranch(address insn_addr, address &target) {
277 intptr_t offset = (target - insn_addr) >> 2;
278 Instruction_aarch64::spatch(insn_addr, 25, 0, offset);
279 return 1;
280 }
281 virtual int conditionalBranch(address insn_addr, address &target) {
282 intptr_t offset = (target - insn_addr) >> 2;
283 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
284 return 1;
285 }
286 virtual int testAndBranch(address insn_addr, address &target) {
287 intptr_t offset = (target - insn_addr) >> 2;
288 Instruction_aarch64::spatch(insn_addr, 18, 5, offset);
289 return 1;
290 }
291 virtual int loadStore(address insn_addr, address &target) {
292 intptr_t offset = (target - insn_addr) >> 2;
293 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
294 return 1;
295 }
296 virtual int adr(address insn_addr, address &target) {
297 #ifdef ASSERT
298 assert(Instruction_aarch64::extract(_insn, 28, 24) == 0b10000, "must be");
299 #endif
300 // PC-rel. addressing
301 ptrdiff_t offset = target - insn_addr;
302 int offset_lo = offset & 3;
303 offset >>= 2;
304 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
305 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
306 return 1;
307 }
308 virtual int adrp(address insn_addr, address &target, reloc_insn inner) {
309 int instructions = 1;
310 #ifdef ASSERT
311 assert(Instruction_aarch64::extract(_insn, 28, 24) == 0b10000, "must be");
312 #endif
313 ptrdiff_t offset = target - insn_addr;
314 instructions = 2;
315 precond(inner != nullptr);
316 // Give the inner reloc a chance to modify the target.
317 address adjusted_target = target;
318 instructions = (*inner)(insn_addr, adjusted_target);
319 uintptr_t pc_page = (uintptr_t)insn_addr >> 12;
320 uintptr_t adr_page = (uintptr_t)adjusted_target >> 12;
321 offset = adr_page - pc_page;
322 int offset_lo = offset & 3;
323 offset >>= 2;
324 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
325 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
326 return instructions;
327 }
328 static int adrpMem_impl(address insn_addr, address &target) {
329 uintptr_t dest = (uintptr_t)target;
330 int offset_lo = dest & 0xfff;
331 uint32_t insn2 = insn_at(insn_addr, 1);
332 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
333 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo >> size);
334 guarantee(((dest >> size) << size) == dest, "misaligned target");
335 return 2;
336 }
337 static int adrpAdd_impl(address insn_addr, address &target) {
338 uintptr_t dest = (uintptr_t)target;
339 int offset_lo = dest & 0xfff;
340 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo);
341 return 2;
342 }
343 static int adrpMovk_impl(address insn_addr, address &target) {
344 uintptr_t dest = uintptr_t(target);
345 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 20, 5, (uintptr_t)target >> 32);
346 dest = (dest & 0xffffffffULL) | (uintptr_t(insn_addr) & 0xffff00000000ULL);
347 target = address(dest);
348 return 2;
349 }
350 virtual int immediate(address insn_addr, address &target) {
351 assert(Instruction_aarch64::extract(_insn, 31, 21) == 0b11010010100, "must be");
352 uint64_t dest = (uint64_t)target;
353 // Move wide constant
354 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
355 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
356 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
357 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
358 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
359 return 3;
360 }
361 virtual void verify(address insn_addr, address &target) {
362 #ifdef ASSERT
363 address address_is = MacroAssembler::target_addr_for_insn(insn_addr);
364 if (!(address_is == target)) {
365 tty->print_cr("%p at %p should be %p", address_is, insn_addr, target);
366 disnm((intptr_t)insn_addr);
367 assert(address_is == target, "should be");
368 }
369 #endif
370 }
371 };
372
373 // If insn1 and insn2 use the same register to form an address, either
374 // by an offsetted LDR or a simple ADD, return the offset. If the
375 // second instruction is an LDR, the offset may be scaled.
376 static bool offset_for(uint32_t insn1, uint32_t insn2, ptrdiff_t &byte_offset) {
377 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
378 Instruction_aarch64::extract(insn1, 4, 0) ==
379 Instruction_aarch64::extract(insn2, 9, 5)) {
380 // Load/store register (unsigned immediate)
381 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
382 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
383 byte_offset <<= size;
384 return true;
385 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
386 Instruction_aarch64::extract(insn1, 4, 0) ==
387 Instruction_aarch64::extract(insn2, 4, 0)) {
388 // add (immediate)
389 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
390 return true;
391 }
392 return false;
393 }
394
395 class AArch64Decoder : public RelocActions {
396 virtual reloc_insn adrpMem() { return &AArch64Decoder::adrpMem_impl; }
397 virtual reloc_insn adrpAdd() { return &AArch64Decoder::adrpAdd_impl; }
398 virtual reloc_insn adrpMovk() { return &AArch64Decoder::adrpMovk_impl; }
399
400 public:
401 AArch64Decoder(address insn_addr, uint32_t insn) : RelocActions(insn_addr, insn) {}
402
403 virtual int loadStore(address insn_addr, address &target) {
404 intptr_t offset = Instruction_aarch64::sextract(_insn, 23, 5);
405 target = insn_addr + (offset << 2);
406 return 1;
407 }
408 virtual int unconditionalBranch(address insn_addr, address &target) {
409 intptr_t offset = Instruction_aarch64::sextract(_insn, 25, 0);
410 target = insn_addr + (offset << 2);
411 return 1;
412 }
413 virtual int conditionalBranch(address insn_addr, address &target) {
414 intptr_t offset = Instruction_aarch64::sextract(_insn, 23, 5);
415 target = address(((uint64_t)insn_addr + (offset << 2)));
416 return 1;
417 }
418 virtual int testAndBranch(address insn_addr, address &target) {
419 intptr_t offset = Instruction_aarch64::sextract(_insn, 18, 5);
420 target = address(((uint64_t)insn_addr + (offset << 2)));
421 return 1;
422 }
423 virtual int adr(address insn_addr, address &target) {
424 // PC-rel. addressing
425 intptr_t offset = Instruction_aarch64::extract(_insn, 30, 29);
426 offset |= Instruction_aarch64::sextract(_insn, 23, 5) << 2;
427 target = address((uint64_t)insn_addr + offset);
428 return 1;
429 }
430 virtual int adrp(address insn_addr, address &target, reloc_insn inner) {
431 assert(Instruction_aarch64::extract(_insn, 28, 24) == 0b10000, "must be");
432 intptr_t offset = Instruction_aarch64::extract(_insn, 30, 29);
433 offset |= Instruction_aarch64::sextract(_insn, 23, 5) << 2;
434 int shift = 12;
435 offset <<= shift;
436 uint64_t target_page = ((uint64_t)insn_addr) + offset;
437 target_page &= ((uint64_t)-1) << shift;
438 uint32_t insn2 = insn_at(1);
439 target = address(target_page);
440 precond(inner != nullptr);
441 (*inner)(insn_addr, target);
442 return 2;
443 }
444 static int adrpMem_impl(address insn_addr, address &target) {
445 uint32_t insn2 = insn_at(insn_addr, 1);
446 // Load/store register (unsigned immediate)
447 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
448 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
449 byte_offset <<= size;
450 target += byte_offset;
451 return 2;
452 }
453 static int adrpAdd_impl(address insn_addr, address &target) {
454 uint32_t insn2 = insn_at(insn_addr, 1);
455 // add (immediate)
456 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
457 target += byte_offset;
458 return 2;
459 }
460 static int adrpMovk_impl(address insn_addr, address &target) {
461 uint32_t insn2 = insn_at(insn_addr, 1);
462 uint64_t dest = uint64_t(target);
463 dest = (dest & 0xffff0000ffffffff) |
464 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
465 target = address(dest);
466
467 // We know the destination 4k page. Maybe we have a third
468 // instruction.
469 uint32_t insn = insn_at(insn_addr, 0);
470 uint32_t insn3 = insn_at(insn_addr, 2);
471 ptrdiff_t byte_offset;
472 if (offset_for(insn, insn3, byte_offset)) {
473 target += byte_offset;
474 return 3;
475 } else {
476 return 2;
477 }
478 }
479 virtual int immediate(address insn_addr, address &target) {
480 uint32_t *insns = (uint32_t *)insn_addr;
481 assert(Instruction_aarch64::extract(_insn, 31, 21) == 0b11010010100, "must be");
482 // Move wide constant: movz, movk, movk. See movptr().
483 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
484 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
485 target = address(uint64_t(Instruction_aarch64::extract(_insn, 20, 5))
486 + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
487 + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
488 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
489 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
490 return 3;
491 }
492 virtual void verify(address insn_addr, address &target) {
493 }
494 };
495
496 address MacroAssembler::target_addr_for_insn(address insn_addr, uint32_t insn) {
497 AArch64Decoder decoder(insn_addr, insn);
498 address target;
499 decoder.run(insn_addr, target);
500 return target;
501 }
502
503 // Patch any kind of instruction; there may be several instructions.
504 // Return the total length (in bytes) of the instructions.
505 int MacroAssembler::pd_patch_instruction_size(address insn_addr, address target) {
506 Patcher patcher(insn_addr);
507 return patcher.run(insn_addr, target);
508 }
509
510 int MacroAssembler::patch_oop(address insn_addr, address o) {
511 int instructions;
512 unsigned insn = *(unsigned*)insn_addr;
513 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
514
515 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
516 // narrow OOPs by setting the upper 16 bits in the first
517 // instruction.
518 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
519 // Move narrow OOP
520 uint32_t n = CompressedOops::narrow_oop_value(cast_to_oop(o));
521 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
522 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
523 instructions = 2;
524 } else {
525 // Move wide OOP
526 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
527 uintptr_t dest = (uintptr_t)o;
528 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
529 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
530 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
531 instructions = 3;
532 }
533 return instructions * NativeInstruction::instruction_size;
534 }
535
536 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
537 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
538 // We encode narrow ones by setting the upper 16 bits in the first
539 // instruction.
540 NativeInstruction *insn = nativeInstruction_at(insn_addr);
541 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 &&
542 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
543
544 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
545 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
546 return 2 * NativeInstruction::instruction_size;
547 }
548
549 address MacroAssembler::target_addr_for_insn_or_null(address insn_addr, unsigned insn) {
550 if (NativeInstruction::is_ldrw_to_zr(address(&insn))) {
551 return nullptr;
552 }
553 return MacroAssembler::target_addr_for_insn(insn_addr, insn);
554 }
555
556 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp) {
557 if (acquire) {
558 lea(tmp, Address(rthread, JavaThread::polling_word_offset()));
559 ldar(tmp, tmp);
560 } else {
561 ldr(tmp, Address(rthread, JavaThread::polling_word_offset()));
562 }
563 if (at_return) {
564 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
565 // we may safely use the sp instead to perform the stack watermark check.
566 cmp(in_nmethod ? sp : rfp, tmp);
567 br(Assembler::HI, slow_path);
568 } else {
569 tbnz(tmp, log2i_exact(SafepointMechanism::poll_bit()), slow_path);
570 }
571 }
572
573 void MacroAssembler::rt_call(address dest, Register tmp) {
574 CodeBlob *cb = CodeCache::find_blob(dest);
575 if (cb) {
576 far_call(RuntimeAddress(dest));
577 } else {
578 lea(tmp, RuntimeAddress(dest));
579 blr(tmp);
580 }
581 }
582
583 void MacroAssembler::push_cont_fastpath(Register java_thread) {
584 if (!Continuations::enabled()) return;
585 Label done;
586 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
587 cmp(sp, rscratch1);
588 br(Assembler::LS, done);
589 mov(rscratch1, sp); // we can't use sp as the source in str
590 str(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
591 bind(done);
592 }
593
594 void MacroAssembler::pop_cont_fastpath(Register java_thread) {
595 if (!Continuations::enabled()) return;
596 Label done;
597 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
598 cmp(sp, rscratch1);
599 br(Assembler::LO, done);
600 str(zr, Address(java_thread, JavaThread::cont_fastpath_offset()));
601 bind(done);
602 }
603
604 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
605 // we must set sp to zero to clear frame
606 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
607
608 // must clear fp, so that compiled frames are not confused; it is
609 // possible that we need it only for debugging
610 if (clear_fp) {
611 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
612 }
613
614 // Always clear the pc because it could have been set by make_walkable()
615 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
616 }
617
618 // Calls to C land
619 //
620 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
621 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
622 // has to be reset to 0. This is required to allow proper stack traversal.
623 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
624 Register last_java_fp,
625 Register last_java_pc,
626 Register scratch) {
627
628 if (last_java_pc->is_valid()) {
629 str(last_java_pc, Address(rthread,
630 JavaThread::frame_anchor_offset()
631 + JavaFrameAnchor::last_Java_pc_offset()));
632 }
633
634 // determine last_java_sp register
635 if (last_java_sp == sp) {
636 mov(scratch, sp);
637 last_java_sp = scratch;
638 } else if (!last_java_sp->is_valid()) {
639 last_java_sp = esp;
640 }
641
642 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
643
644 // last_java_fp is optional
645 if (last_java_fp->is_valid()) {
646 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
647 }
648 }
649
650 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
651 Register last_java_fp,
652 address last_java_pc,
653 Register scratch) {
654 assert(last_java_pc != nullptr, "must provide a valid PC");
655
656 adr(scratch, last_java_pc);
657 str(scratch, Address(rthread,
658 JavaThread::frame_anchor_offset()
659 + JavaFrameAnchor::last_Java_pc_offset()));
660
661 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
662 }
663
664 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
665 Register last_java_fp,
666 Label &L,
667 Register scratch) {
668 if (L.is_bound()) {
669 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
670 } else {
671 InstructionMark im(this);
672 L.add_patch_at(code(), locator());
673 set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, scratch);
674 }
675 }
676
677 static inline bool target_needs_far_branch(address addr) {
678 // codecache size <= 128M
679 if (!MacroAssembler::far_branches()) {
680 return false;
681 }
682 // codecache size > 240M
683 if (MacroAssembler::codestub_branch_needs_far_jump()) {
684 return true;
685 }
686 // codecache size: 128M..240M
687 return !CodeCache::is_non_nmethod(addr);
688 }
689
690 void MacroAssembler::far_call(Address entry, Register tmp) {
691 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
692 assert(CodeCache::find_blob(entry.target()) != nullptr,
693 "destination of far call not found in code cache");
694 assert(entry.rspec().type() == relocInfo::external_word_type
695 || entry.rspec().type() == relocInfo::runtime_call_type
696 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
697 if (target_needs_far_branch(entry.target())) {
698 uint64_t offset;
699 // We can use ADRP here because we know that the total size of
700 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
701 adrp(tmp, entry, offset);
702 add(tmp, tmp, offset);
703 blr(tmp);
704 } else {
705 bl(entry);
706 }
707 }
708
709 int MacroAssembler::far_jump(Address entry, Register tmp) {
710 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
711 assert(CodeCache::find_blob(entry.target()) != nullptr,
712 "destination of far call not found in code cache");
713 assert(entry.rspec().type() == relocInfo::external_word_type
714 || entry.rspec().type() == relocInfo::runtime_call_type
715 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
716 address start = pc();
717 if (target_needs_far_branch(entry.target())) {
718 uint64_t offset;
719 // We can use ADRP here because we know that the total size of
720 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
721 adrp(tmp, entry, offset);
722 add(tmp, tmp, offset);
723 br(tmp);
724 } else {
725 b(entry);
726 }
727 return pc() - start;
728 }
729
730 void MacroAssembler::reserved_stack_check() {
731 // testing if reserved zone needs to be enabled
732 Label no_reserved_zone_enabling;
733
734 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset()));
735 cmp(sp, rscratch1);
736 br(Assembler::LO, no_reserved_zone_enabling);
737
738 enter(); // LR and FP are live.
739 lea(rscratch1, CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone));
740 mov(c_rarg0, rthread);
741 blr(rscratch1);
742 leave();
743
744 // We have already removed our own frame.
745 // throw_delayed_StackOverflowError will think that it's been
746 // called by our caller.
747 lea(rscratch1, RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
748 br(rscratch1);
749 should_not_reach_here();
750
751 bind(no_reserved_zone_enabling);
752 }
753
754 static void pass_arg0(MacroAssembler* masm, Register arg) {
755 if (c_rarg0 != arg ) {
756 masm->mov(c_rarg0, arg);
757 }
758 }
759
760 static void pass_arg1(MacroAssembler* masm, Register arg) {
761 if (c_rarg1 != arg ) {
762 masm->mov(c_rarg1, arg);
763 }
764 }
765
766 static void pass_arg2(MacroAssembler* masm, Register arg) {
767 if (c_rarg2 != arg ) {
768 masm->mov(c_rarg2, arg);
769 }
770 }
771
772 static void pass_arg3(MacroAssembler* masm, Register arg) {
773 if (c_rarg3 != arg ) {
774 masm->mov(c_rarg3, arg);
775 }
776 }
777
778 void MacroAssembler::call_VM_base(Register oop_result,
779 Register java_thread,
780 Register last_java_sp,
781 address entry_point,
782 int number_of_arguments,
783 bool check_exceptions) {
784 // determine java_thread register
785 if (!java_thread->is_valid()) {
786 java_thread = rthread;
787 }
788
789 // determine last_java_sp register
790 if (!last_java_sp->is_valid()) {
791 last_java_sp = esp;
792 }
793
794 // debugging support
795 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
796 assert(java_thread == rthread, "unexpected register");
797 #ifdef ASSERT
798 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
799 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
800 #endif // ASSERT
801
802 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
803 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
804
805 // push java thread (becomes first argument of C function)
806
807 mov(c_rarg0, java_thread);
808
809 // set last Java frame before call
810 assert(last_java_sp != rfp, "can't use rfp");
811
812 Label l;
813 set_last_Java_frame(last_java_sp, rfp, l, rscratch1);
814
815 // do the call, remove parameters
816 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
817
818 // lr could be poisoned with PAC signature during throw_pending_exception
819 // if it was tail-call optimized by compiler, since lr is not callee-saved
820 // reload it with proper value
821 adr(lr, l);
822
823 // reset last Java frame
824 // Only interpreter should have to clear fp
825 reset_last_Java_frame(true);
826
827 // C++ interp handles this in the interpreter
828 check_and_handle_popframe(java_thread);
829 check_and_handle_earlyret(java_thread);
830
831 if (check_exceptions) {
832 // check for pending exceptions (java_thread is set upon return)
833 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
834 Label ok;
835 cbz(rscratch1, ok);
836 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
837 br(rscratch1);
838 bind(ok);
839 }
840
841 // get oop result if there is one and reset the value in the thread
842 if (oop_result->is_valid()) {
843 get_vm_result(oop_result, java_thread);
844 }
845 }
846
847 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
848 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
849 }
850
851 // Check the entry target is always reachable from any branch.
852 static bool is_always_within_branch_range(Address entry) {
853 const address target = entry.target();
854
855 if (!CodeCache::contains(target)) {
856 // We always use trampolines for callees outside CodeCache.
857 assert(entry.rspec().type() == relocInfo::runtime_call_type, "non-runtime call of an external target");
858 return false;
859 }
860
861 if (!MacroAssembler::far_branches()) {
862 return true;
863 }
864
865 if (entry.rspec().type() == relocInfo::runtime_call_type) {
866 // Runtime calls are calls of a non-compiled method (stubs, adapters).
867 // Non-compiled methods stay forever in CodeCache.
868 // We check whether the longest possible branch is within the branch range.
869 assert(CodeCache::find_blob(target) != nullptr &&
870 !CodeCache::find_blob(target)->is_nmethod(),
871 "runtime call of compiled method");
872 const address right_longest_branch_start = CodeCache::high_bound() - NativeInstruction::instruction_size;
873 const address left_longest_branch_start = CodeCache::low_bound();
874 const bool is_reachable = Assembler::reachable_from_branch_at(left_longest_branch_start, target) &&
875 Assembler::reachable_from_branch_at(right_longest_branch_start, target);
876 return is_reachable;
877 }
878
879 return false;
880 }
881
882 // Maybe emit a call via a trampoline. If the code cache is small
883 // trampolines won't be emitted.
884 address MacroAssembler::trampoline_call(Address entry) {
885 assert(entry.rspec().type() == relocInfo::runtime_call_type
886 || entry.rspec().type() == relocInfo::opt_virtual_call_type
887 || entry.rspec().type() == relocInfo::static_call_type
888 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
889
890 address target = entry.target();
891
892 if (!is_always_within_branch_range(entry)) {
893 if (!in_scratch_emit_size()) {
894 // We don't want to emit a trampoline if C2 is generating dummy
895 // code during its branch shortening phase.
896 if (entry.rspec().type() == relocInfo::runtime_call_type) {
897 assert(CodeBuffer::supports_shared_stubs(), "must support shared stubs");
898 code()->share_trampoline_for(entry.target(), offset());
899 } else {
900 address stub = emit_trampoline_stub(offset(), target);
901 if (stub == nullptr) {
902 postcond(pc() == badAddress);
903 return nullptr; // CodeCache is full
904 }
905 }
906 }
907 target = pc();
908 }
909
910 address call_pc = pc();
911 relocate(entry.rspec());
912 bl(target);
913
914 postcond(pc() != badAddress);
915 return call_pc;
916 }
917
918 // Emit a trampoline stub for a call to a target which is too far away.
919 //
920 // code sequences:
921 //
922 // call-site:
923 // branch-and-link to <destination> or <trampoline stub>
924 //
925 // Related trampoline stub for this call site in the stub section:
926 // load the call target from the constant pool
927 // branch (LR still points to the call site above)
928
929 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
930 address dest) {
931 // Max stub size: alignment nop, TrampolineStub.
932 address stub = start_a_stub(max_trampoline_stub_size());
933 if (stub == nullptr) {
934 return nullptr; // CodeBuffer::expand failed
935 }
936
937 // Create a trampoline stub relocation which relates this trampoline stub
938 // with the call instruction at insts_call_instruction_offset in the
939 // instructions code-section.
940 align(wordSize);
941 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
942 + insts_call_instruction_offset));
943 const int stub_start_offset = offset();
944
945 // Now, create the trampoline stub's code:
946 // - load the call
947 // - call
948 Label target;
949 ldr(rscratch1, target);
950 br(rscratch1);
951 bind(target);
952 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
953 "should be");
954 emit_int64((int64_t)dest);
955
956 const address stub_start_addr = addr_at(stub_start_offset);
957
958 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
959
960 end_a_stub();
961 return stub_start_addr;
962 }
963
964 int MacroAssembler::max_trampoline_stub_size() {
965 // Max stub size: alignment nop, TrampolineStub.
966 return NativeInstruction::instruction_size + NativeCallTrampolineStub::instruction_size;
967 }
968
969 void MacroAssembler::emit_static_call_stub() {
970 // CompiledDirectCall::set_to_interpreted knows the
971 // exact layout of this stub.
972
973 isb();
974 mov_metadata(rmethod, nullptr);
975
976 // Jump to the entry point of the c2i stub.
977 movptr(rscratch1, 0);
978 br(rscratch1);
979 }
980
981 int MacroAssembler::static_call_stub_size() {
982 // isb; movk; movz; movz; movk; movz; movz; br
983 return 8 * NativeInstruction::instruction_size;
984 }
985
986 void MacroAssembler::c2bool(Register x) {
987 // implements x == 0 ? 0 : 1
988 // note: must only look at least-significant byte of x
989 // since C-style booleans are stored in one byte
990 // only! (was bug)
991 tst(x, 0xff);
992 cset(x, Assembler::NE);
993 }
994
995 address MacroAssembler::ic_call(address entry, jint method_index) {
996 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
997 // address const_ptr = long_constant((jlong)Universe::non_oop_word());
998 // uintptr_t offset;
999 // ldr_constant(rscratch2, const_ptr);
1000 movptr(rscratch2, (intptr_t)Universe::non_oop_word());
1001 return trampoline_call(Address(entry, rh));
1002 }
1003
1004 int MacroAssembler::ic_check_size() {
1005 if (target_needs_far_branch(CAST_FROM_FN_PTR(address, SharedRuntime::get_ic_miss_stub()))) {
1006 return NativeInstruction::instruction_size * 7;
1007 } else {
1008 return NativeInstruction::instruction_size * 5;
1009 }
1010 }
1011
1012 int MacroAssembler::ic_check(int end_alignment) {
1013 Register receiver = j_rarg0;
1014 Register data = rscratch2;
1015 Register tmp1 = rscratch1;
1016 Register tmp2 = r10;
1017
1018 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1019 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1020 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1021 // before the inline cache check here, and not after
1022 align(end_alignment, offset() + ic_check_size());
1023
1024 int uep_offset = offset();
1025
1026 if (UseCompressedClassPointers) {
1027 ldrw(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1028 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1029 cmpw(tmp1, tmp2);
1030 } else {
1031 ldr(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1032 ldr(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1033 cmp(tmp1, tmp2);
1034 }
1035
1036 Label dont;
1037 br(Assembler::EQ, dont);
1038 far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1039 bind(dont);
1040 assert((offset() % end_alignment) == 0, "Misaligned verified entry point");
1041
1042 return uep_offset;
1043 }
1044
1045 // Implementation of call_VM versions
1046
1047 void MacroAssembler::call_VM(Register oop_result,
1048 address entry_point,
1049 bool check_exceptions) {
1050 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1051 }
1052
1053 void MacroAssembler::call_VM(Register oop_result,
1054 address entry_point,
1055 Register arg_1,
1056 bool check_exceptions) {
1057 pass_arg1(this, arg_1);
1058 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1059 }
1060
1061 void MacroAssembler::call_VM(Register oop_result,
1062 address entry_point,
1063 Register arg_1,
1064 Register arg_2,
1065 bool check_exceptions) {
1066 assert_different_registers(arg_1, c_rarg2);
1067 pass_arg2(this, arg_2);
1068 pass_arg1(this, arg_1);
1069 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1070 }
1071
1072 void MacroAssembler::call_VM(Register oop_result,
1073 address entry_point,
1074 Register arg_1,
1075 Register arg_2,
1076 Register arg_3,
1077 bool check_exceptions) {
1078 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1079 assert_different_registers(arg_2, c_rarg3);
1080 pass_arg3(this, arg_3);
1081
1082 pass_arg2(this, arg_2);
1083
1084 pass_arg1(this, arg_1);
1085 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1086 }
1087
1088 void MacroAssembler::call_VM(Register oop_result,
1089 Register last_java_sp,
1090 address entry_point,
1091 int number_of_arguments,
1092 bool check_exceptions) {
1093 call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1094 }
1095
1096 void MacroAssembler::call_VM(Register oop_result,
1097 Register last_java_sp,
1098 address entry_point,
1099 Register arg_1,
1100 bool check_exceptions) {
1101 pass_arg1(this, arg_1);
1102 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1103 }
1104
1105 void MacroAssembler::call_VM(Register oop_result,
1106 Register last_java_sp,
1107 address entry_point,
1108 Register arg_1,
1109 Register arg_2,
1110 bool check_exceptions) {
1111
1112 assert_different_registers(arg_1, c_rarg2);
1113 pass_arg2(this, arg_2);
1114 pass_arg1(this, arg_1);
1115 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1116 }
1117
1118 void MacroAssembler::call_VM(Register oop_result,
1119 Register last_java_sp,
1120 address entry_point,
1121 Register arg_1,
1122 Register arg_2,
1123 Register arg_3,
1124 bool check_exceptions) {
1125 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1126 assert_different_registers(arg_2, c_rarg3);
1127 pass_arg3(this, arg_3);
1128 pass_arg2(this, arg_2);
1129 pass_arg1(this, arg_1);
1130 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1131 }
1132
1133
1134 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1135 ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1136 str(zr, Address(java_thread, JavaThread::vm_result_offset()));
1137 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1138 }
1139
1140 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1141 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1142 str(zr, Address(java_thread, JavaThread::vm_result_2_offset()));
1143 }
1144
1145 void MacroAssembler::align(int modulus) {
1146 align(modulus, offset());
1147 }
1148
1149 // Ensure that the code at target bytes offset from the current offset() is aligned
1150 // according to modulus.
1151 void MacroAssembler::align(int modulus, int target) {
1152 int delta = target - offset();
1153 while ((offset() + delta) % modulus != 0) nop();
1154 }
1155
1156 void MacroAssembler::post_call_nop() {
1157 if (!Continuations::enabled()) {
1158 return;
1159 }
1160 InstructionMark im(this);
1161 relocate(post_call_nop_Relocation::spec());
1162 InlineSkippedInstructionsCounter skipCounter(this);
1163 nop();
1164 movk(zr, 0);
1165 movk(zr, 0);
1166 }
1167
1168 // these are no-ops overridden by InterpreterMacroAssembler
1169
1170 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1171
1172 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1173
1174 // Look up the method for a megamorphic invokeinterface call.
1175 // The target method is determined by <intf_klass, itable_index>.
1176 // The receiver klass is in recv_klass.
1177 // On success, the result will be in method_result, and execution falls through.
1178 // On failure, execution transfers to the given label.
1179 void MacroAssembler::lookup_interface_method(Register recv_klass,
1180 Register intf_klass,
1181 RegisterOrConstant itable_index,
1182 Register method_result,
1183 Register scan_temp,
1184 Label& L_no_such_interface,
1185 bool return_method) {
1186 assert_different_registers(recv_klass, intf_klass, scan_temp);
1187 assert_different_registers(method_result, intf_klass, scan_temp);
1188 assert(recv_klass != method_result || !return_method,
1189 "recv_klass can be destroyed when method isn't needed");
1190 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1191 "caller must use same register for non-constant itable index as for method");
1192
1193 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1194 int vtable_base = in_bytes(Klass::vtable_start_offset());
1195 int itentry_off = in_bytes(itableMethodEntry::method_offset());
1196 int scan_step = itableOffsetEntry::size() * wordSize;
1197 int vte_size = vtableEntry::size_in_bytes();
1198 assert(vte_size == wordSize, "else adjust times_vte_scale");
1199
1200 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1201
1202 // Could store the aligned, prescaled offset in the klass.
1203 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
1204 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
1205 add(scan_temp, scan_temp, vtable_base);
1206
1207 if (return_method) {
1208 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1209 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1210 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
1211 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
1212 if (itentry_off)
1213 add(recv_klass, recv_klass, itentry_off);
1214 }
1215
1216 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
1217 // if (scan->interface() == intf) {
1218 // result = (klass + scan->offset() + itable_index);
1219 // }
1220 // }
1221 Label search, found_method;
1222
1223 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1224 cmp(intf_klass, method_result);
1225 br(Assembler::EQ, found_method);
1226 bind(search);
1227 // Check that the previous entry is non-null. A null entry means that
1228 // the receiver class doesn't implement the interface, and wasn't the
1229 // same as when the caller was compiled.
1230 cbz(method_result, L_no_such_interface);
1231 if (itableOffsetEntry::interface_offset() != 0) {
1232 add(scan_temp, scan_temp, scan_step);
1233 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1234 } else {
1235 ldr(method_result, Address(pre(scan_temp, scan_step)));
1236 }
1237 cmp(intf_klass, method_result);
1238 br(Assembler::NE, search);
1239
1240 bind(found_method);
1241
1242 // Got a hit.
1243 if (return_method) {
1244 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
1245 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0)));
1246 }
1247 }
1248
1249 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
1250 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
1251 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
1252 // The target method is determined by <holder_klass, itable_index>.
1253 // The receiver klass is in recv_klass.
1254 // On success, the result will be in method_result, and execution falls through.
1255 // On failure, execution transfers to the given label.
1256 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
1257 Register holder_klass,
1258 Register resolved_klass,
1259 Register method_result,
1260 Register temp_itbl_klass,
1261 Register scan_temp,
1262 int itable_index,
1263 Label& L_no_such_interface) {
1264 // 'method_result' is only used as output register at the very end of this method.
1265 // Until then we can reuse it as 'holder_offset'.
1266 Register holder_offset = method_result;
1267 assert_different_registers(resolved_klass, recv_klass, holder_klass, temp_itbl_klass, scan_temp, holder_offset);
1268
1269 int vtable_start_offset = in_bytes(Klass::vtable_start_offset());
1270 int itable_offset_entry_size = itableOffsetEntry::size() * wordSize;
1271 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
1272 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
1273
1274 Label L_loop_search_resolved_entry, L_resolved_found, L_holder_found;
1275
1276 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1277 add(recv_klass, recv_klass, vtable_start_offset + ioffset);
1278 // itableOffsetEntry[] itable = recv_klass + Klass::vtable_start_offset() + sizeof(vtableEntry) * recv_klass->_vtable_len;
1279 // temp_itbl_klass = itable[0]._interface;
1280 int vtblEntrySize = vtableEntry::size_in_bytes();
1281 assert(vtblEntrySize == wordSize, "ldr lsl shift amount must be 3");
1282 ldr(temp_itbl_klass, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1283 mov(holder_offset, zr);
1284 // scan_temp = &(itable[0]._interface)
1285 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1286
1287 // Initial checks:
1288 // - if (holder_klass != resolved_klass), go to "scan for resolved"
1289 // - if (itable[0] == holder_klass), shortcut to "holder found"
1290 // - if (itable[0] == 0), no such interface
1291 cmp(resolved_klass, holder_klass);
1292 br(Assembler::NE, L_loop_search_resolved_entry);
1293 cmp(holder_klass, temp_itbl_klass);
1294 br(Assembler::EQ, L_holder_found);
1295 cbz(temp_itbl_klass, L_no_such_interface);
1296
1297 // Loop: Look for holder_klass record in itable
1298 // do {
1299 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1300 // if (temp_itbl_klass == holder_klass) {
1301 // goto L_holder_found; // Found!
1302 // }
1303 // } while (temp_itbl_klass != 0);
1304 // goto L_no_such_interface // Not found.
1305 Label L_search_holder;
1306 bind(L_search_holder);
1307 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1308 cmp(holder_klass, temp_itbl_klass);
1309 br(Assembler::EQ, L_holder_found);
1310 cbnz(temp_itbl_klass, L_search_holder);
1311
1312 b(L_no_such_interface);
1313
1314 // Loop: Look for resolved_class record in itable
1315 // while (true) {
1316 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1317 // if (temp_itbl_klass == 0) {
1318 // goto L_no_such_interface;
1319 // }
1320 // if (temp_itbl_klass == resolved_klass) {
1321 // goto L_resolved_found; // Found!
1322 // }
1323 // if (temp_itbl_klass == holder_klass) {
1324 // holder_offset = scan_temp;
1325 // }
1326 // }
1327 //
1328 Label L_loop_search_resolved;
1329 bind(L_loop_search_resolved);
1330 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1331 bind(L_loop_search_resolved_entry);
1332 cbz(temp_itbl_klass, L_no_such_interface);
1333 cmp(resolved_klass, temp_itbl_klass);
1334 br(Assembler::EQ, L_resolved_found);
1335 cmp(holder_klass, temp_itbl_klass);
1336 br(Assembler::NE, L_loop_search_resolved);
1337 mov(holder_offset, scan_temp);
1338 b(L_loop_search_resolved);
1339
1340 // See if we already have a holder klass. If not, go and scan for it.
1341 bind(L_resolved_found);
1342 cbz(holder_offset, L_search_holder);
1343 mov(scan_temp, holder_offset);
1344
1345 // Finally, scan_temp contains holder_klass vtable offset
1346 bind(L_holder_found);
1347 ldrw(method_result, Address(scan_temp, ooffset - ioffset));
1348 add(recv_klass, recv_klass, itable_index * wordSize + in_bytes(itableMethodEntry::method_offset())
1349 - vtable_start_offset - ioffset); // substract offsets to restore the original value of recv_klass
1350 ldr(method_result, Address(recv_klass, method_result, Address::uxtw(0)));
1351 }
1352
1353 // virtual method calling
1354 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1355 RegisterOrConstant vtable_index,
1356 Register method_result) {
1357 assert(vtableEntry::size() * wordSize == 8,
1358 "adjust the scaling in the code below");
1359 int64_t vtable_offset_in_bytes = in_bytes(Klass::vtable_start_offset() + vtableEntry::method_offset());
1360
1361 if (vtable_index.is_register()) {
1362 lea(method_result, Address(recv_klass,
1363 vtable_index.as_register(),
1364 Address::lsl(LogBytesPerWord)));
1365 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
1366 } else {
1367 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
1368 ldr(method_result,
1369 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0));
1370 }
1371 }
1372
1373 void MacroAssembler::check_klass_subtype(Register sub_klass,
1374 Register super_klass,
1375 Register temp_reg,
1376 Label& L_success) {
1377 Label L_failure;
1378 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
1379 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
1380 bind(L_failure);
1381 }
1382
1383
1384 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1385 Register super_klass,
1386 Register temp_reg,
1387 Label* L_success,
1388 Label* L_failure,
1389 Label* L_slow_path,
1390 RegisterOrConstant super_check_offset) {
1391 assert_different_registers(sub_klass, super_klass, temp_reg);
1392 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
1393 if (super_check_offset.is_register()) {
1394 assert_different_registers(sub_klass, super_klass,
1395 super_check_offset.as_register());
1396 } else if (must_load_sco) {
1397 assert(temp_reg != noreg, "supply either a temp or a register offset");
1398 }
1399
1400 Label L_fallthrough;
1401 int label_nulls = 0;
1402 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1403 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1404 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
1405 assert(label_nulls <= 1, "at most one null in the batch");
1406
1407 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1408 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1409 Address super_check_offset_addr(super_klass, sco_offset);
1410
1411 // Hacked jmp, which may only be used just before L_fallthrough.
1412 #define final_jmp(label) \
1413 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1414 else b(label) /*omit semi*/
1415
1416 // If the pointers are equal, we are done (e.g., String[] elements).
1417 // This self-check enables sharing of secondary supertype arrays among
1418 // non-primary types such as array-of-interface. Otherwise, each such
1419 // type would need its own customized SSA.
1420 // We move this check to the front of the fast path because many
1421 // type checks are in fact trivially successful in this manner,
1422 // so we get a nicely predicted branch right at the start of the check.
1423 cmp(sub_klass, super_klass);
1424 br(Assembler::EQ, *L_success);
1425
1426 // Check the supertype display:
1427 if (must_load_sco) {
1428 ldrw(temp_reg, super_check_offset_addr);
1429 super_check_offset = RegisterOrConstant(temp_reg);
1430 }
1431 Address super_check_addr(sub_klass, super_check_offset);
1432 ldr(rscratch1, super_check_addr);
1433 cmp(super_klass, rscratch1); // load displayed supertype
1434
1435 // This check has worked decisively for primary supers.
1436 // Secondary supers are sought in the super_cache ('super_cache_addr').
1437 // (Secondary supers are interfaces and very deeply nested subtypes.)
1438 // This works in the same check above because of a tricky aliasing
1439 // between the super_cache and the primary super display elements.
1440 // (The 'super_check_addr' can address either, as the case requires.)
1441 // Note that the cache is updated below if it does not help us find
1442 // what we need immediately.
1443 // So if it was a primary super, we can just fail immediately.
1444 // Otherwise, it's the slow path for us (no success at this point).
1445
1446 if (super_check_offset.is_register()) {
1447 br(Assembler::EQ, *L_success);
1448 subs(zr, super_check_offset.as_register(), sc_offset);
1449 if (L_failure == &L_fallthrough) {
1450 br(Assembler::EQ, *L_slow_path);
1451 } else {
1452 br(Assembler::NE, *L_failure);
1453 final_jmp(*L_slow_path);
1454 }
1455 } else if (super_check_offset.as_constant() == sc_offset) {
1456 // Need a slow path; fast failure is impossible.
1457 if (L_slow_path == &L_fallthrough) {
1458 br(Assembler::EQ, *L_success);
1459 } else {
1460 br(Assembler::NE, *L_slow_path);
1461 final_jmp(*L_success);
1462 }
1463 } else {
1464 // No slow path; it's a fast decision.
1465 if (L_failure == &L_fallthrough) {
1466 br(Assembler::EQ, *L_success);
1467 } else {
1468 br(Assembler::NE, *L_failure);
1469 final_jmp(*L_success);
1470 }
1471 }
1472
1473 bind(L_fallthrough);
1474
1475 #undef final_jmp
1476 }
1477
1478 // These two are taken from x86, but they look generally useful
1479
1480 // scans count pointer sized words at [addr] for occurrence of value,
1481 // generic
1482 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1483 Register scratch) {
1484 Label Lloop, Lexit;
1485 cbz(count, Lexit);
1486 bind(Lloop);
1487 ldr(scratch, post(addr, wordSize));
1488 cmp(value, scratch);
1489 br(EQ, Lexit);
1490 sub(count, count, 1);
1491 cbnz(count, Lloop);
1492 bind(Lexit);
1493 }
1494
1495 // scans count 4 byte words at [addr] for occurrence of value,
1496 // generic
1497 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1498 Register scratch) {
1499 Label Lloop, Lexit;
1500 cbz(count, Lexit);
1501 bind(Lloop);
1502 ldrw(scratch, post(addr, wordSize));
1503 cmpw(value, scratch);
1504 br(EQ, Lexit);
1505 sub(count, count, 1);
1506 cbnz(count, Lloop);
1507 bind(Lexit);
1508 }
1509
1510 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1511 Register super_klass,
1512 Register temp_reg,
1513 Register temp2_reg,
1514 Label* L_success,
1515 Label* L_failure,
1516 bool set_cond_codes) {
1517 // NB! Callers may assume that, when temp2_reg is a valid register,
1518 // this code sets it to a nonzero value.
1519
1520 assert_different_registers(sub_klass, super_klass, temp_reg);
1521 if (temp2_reg != noreg)
1522 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1523 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1524
1525 Label L_fallthrough;
1526 int label_nulls = 0;
1527 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1528 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1529 assert(label_nulls <= 1, "at most one null in the batch");
1530
1531 // a couple of useful fields in sub_klass:
1532 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1533 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1534 Address secondary_supers_addr(sub_klass, ss_offset);
1535 Address super_cache_addr( sub_klass, sc_offset);
1536
1537 BLOCK_COMMENT("check_klass_subtype_slow_path");
1538
1539 // Do a linear scan of the secondary super-klass chain.
1540 // This code is rarely used, so simplicity is a virtue here.
1541 // The repne_scan instruction uses fixed registers, which we must spill.
1542 // Don't worry too much about pre-existing connections with the input regs.
1543
1544 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1545 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1546
1547 RegSet pushed_registers;
1548 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1549 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1550
1551 if (super_klass != r0) {
1552 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1553 }
1554
1555 push(pushed_registers, sp);
1556
1557 // Get super_klass value into r0 (even if it was in r5 or r2).
1558 if (super_klass != r0) {
1559 mov(r0, super_klass);
1560 }
1561
1562 #ifndef PRODUCT
1563 incrementw(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
1564 #endif //PRODUCT
1565
1566 // We will consult the secondary-super array.
1567 ldr(r5, secondary_supers_addr);
1568 // Load the array length.
1569 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1570 // Skip to start of data.
1571 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1572
1573 cmp(sp, zr); // Clear Z flag; SP is never zero
1574 // Scan R2 words at [R5] for an occurrence of R0.
1575 // Set NZ/Z based on last compare.
1576 repne_scan(r5, r0, r2, rscratch1);
1577
1578 // Unspill the temp. registers:
1579 pop(pushed_registers, sp);
1580
1581 br(Assembler::NE, *L_failure);
1582
1583 // Success. Cache the super we found and proceed in triumph.
1584 str(super_klass, super_cache_addr);
1585
1586 if (L_success != &L_fallthrough) {
1587 b(*L_success);
1588 }
1589
1590 #undef IS_A_TEMP
1591
1592 bind(L_fallthrough);
1593 }
1594
1595 // Ensure that the inline code and the stub are using the same registers.
1596 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
1597 do { \
1598 assert(r_super_klass == r0 && \
1599 r_array_base == r1 && \
1600 r_array_length == r2 && \
1601 (r_array_index == r3 || r_array_index == noreg) && \
1602 (r_sub_klass == r4 || r_sub_klass == noreg) && \
1603 (r_bitmap == rscratch2 || r_bitmap == noreg) && \
1604 (result == r5 || result == noreg), "registers must match aarch64.ad"); \
1605 } while(0)
1606
1607 // Return true: we succeeded in generating this code
1608 bool MacroAssembler::lookup_secondary_supers_table(Register r_sub_klass,
1609 Register r_super_klass,
1610 Register temp1,
1611 Register temp2,
1612 Register temp3,
1613 FloatRegister vtemp,
1614 Register result,
1615 u1 super_klass_slot,
1616 bool stub_is_near) {
1617 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1618
1619 Label L_fallthrough;
1620
1621 BLOCK_COMMENT("lookup_secondary_supers_table {");
1622
1623 const Register
1624 r_array_base = temp1, // r1
1625 r_array_length = temp2, // r2
1626 r_array_index = temp3, // r3
1627 r_bitmap = rscratch2;
1628
1629 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1630
1631 u1 bit = super_klass_slot;
1632
1633 // Make sure that result is nonzero if the TBZ below misses.
1634 mov(result, 1);
1635
1636 // We're going to need the bitmap in a vector reg and in a core reg,
1637 // so load both now.
1638 ldr(r_bitmap, Address(r_sub_klass, Klass::bitmap_offset()));
1639 if (bit != 0) {
1640 ldrd(vtemp, Address(r_sub_klass, Klass::bitmap_offset()));
1641 }
1642 // First check the bitmap to see if super_klass might be present. If
1643 // the bit is zero, we are certain that super_klass is not one of
1644 // the secondary supers.
1645 tbz(r_bitmap, bit, L_fallthrough);
1646
1647 // Get the first array index that can contain super_klass into r_array_index.
1648 if (bit != 0) {
1649 shld(vtemp, vtemp, Klass::SECONDARY_SUPERS_TABLE_MASK - bit);
1650 cnt(vtemp, T8B, vtemp);
1651 addv(vtemp, T8B, vtemp);
1652 fmovd(r_array_index, vtemp);
1653 } else {
1654 mov(r_array_index, (u1)1);
1655 }
1656 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1657
1658 // We will consult the secondary-super array.
1659 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1660
1661 // The value i in r_array_index is >= 1, so even though r_array_base
1662 // points to the length, we don't need to adjust it to point to the
1663 // data.
1664 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1665 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1666
1667 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1668 eor(result, result, r_super_klass);
1669 cbz(result, L_fallthrough); // Found a match
1670
1671 // Is there another entry to check? Consult the bitmap.
1672 tbz(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK, L_fallthrough);
1673
1674 // Linear probe.
1675 if (bit != 0) {
1676 ror(r_bitmap, r_bitmap, bit);
1677 }
1678
1679 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1680 // The next slot to be inspected, by the stub we're about to call,
1681 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1682 // have been checked.
1683 Address stub = RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub());
1684 if (stub_is_near) {
1685 bl(stub);
1686 } else {
1687 address call = trampoline_call(stub);
1688 if (call == nullptr) {
1689 return false; // trampoline allocation failed
1690 }
1691 }
1692
1693 BLOCK_COMMENT("} lookup_secondary_supers_table");
1694
1695 bind(L_fallthrough);
1696
1697 if (VerifySecondarySupers) {
1698 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1699 temp1, temp2, result); // r1, r2, r5
1700 }
1701 return true;
1702 }
1703
1704 // Called by code generated by check_klass_subtype_slow_path
1705 // above. This is called when there is a collision in the hashed
1706 // lookup in the secondary supers array.
1707 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
1708 Register r_array_base,
1709 Register r_array_index,
1710 Register r_bitmap,
1711 Register temp1,
1712 Register result) {
1713 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, result, rscratch1);
1714
1715 const Register
1716 r_array_length = temp1,
1717 r_sub_klass = noreg; // unused
1718
1719 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1720
1721 Label L_fallthrough, L_huge;
1722
1723 // Load the array length.
1724 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1725 // And adjust the array base to point to the data.
1726 // NB! Effectively increments current slot index by 1.
1727 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
1728 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1729
1730 // The bitmap is full to bursting.
1731 // Implicit invariant: BITMAP_FULL implies (length > 0)
1732 assert(Klass::SECONDARY_SUPERS_BITMAP_FULL == ~uintx(0), "");
1733 cmn(r_bitmap, (u1)1);
1734 br(EQ, L_huge);
1735
1736 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
1737 // current slot (at secondary_supers[r_array_index]) has not yet
1738 // been inspected, and r_array_index may be out of bounds if we
1739 // wrapped around the end of the array.
1740
1741 { // This is conventional linear probing, but instead of terminating
1742 // when a null entry is found in the table, we maintain a bitmap
1743 // in which a 0 indicates missing entries.
1744 // The check above guarantees there are 0s in the bitmap, so the loop
1745 // eventually terminates.
1746 Label L_loop;
1747 bind(L_loop);
1748
1749 // Check for wraparound.
1750 cmp(r_array_index, r_array_length);
1751 csel(r_array_index, zr, r_array_index, GE);
1752
1753 ldr(rscratch1, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1754 eor(result, rscratch1, r_super_klass);
1755 cbz(result, L_fallthrough);
1756
1757 tbz(r_bitmap, 2, L_fallthrough); // look-ahead check (Bit 2); result is non-zero
1758
1759 ror(r_bitmap, r_bitmap, 1);
1760 add(r_array_index, r_array_index, 1);
1761 b(L_loop);
1762 }
1763
1764 { // Degenerate case: more than 64 secondary supers.
1765 // FIXME: We could do something smarter here, maybe a vectorized
1766 // comparison or a binary search, but is that worth any added
1767 // complexity?
1768 bind(L_huge);
1769 cmp(sp, zr); // Clear Z flag; SP is never zero
1770 repne_scan(r_array_base, r_super_klass, r_array_length, rscratch1);
1771 cset(result, NE); // result == 0 iff we got a match.
1772 }
1773
1774 bind(L_fallthrough);
1775 }
1776
1777 // Make sure that the hashed lookup and a linear scan agree.
1778 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
1779 Register r_super_klass,
1780 Register temp1,
1781 Register temp2,
1782 Register result) {
1783 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, result, rscratch1);
1784
1785 const Register
1786 r_array_base = temp1,
1787 r_array_length = temp2,
1788 r_array_index = noreg, // unused
1789 r_bitmap = noreg; // unused
1790
1791 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1792
1793 BLOCK_COMMENT("verify_secondary_supers_table {");
1794
1795 // We will consult the secondary-super array.
1796 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1797
1798 // Load the array length.
1799 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1800 // And adjust the array base to point to the data.
1801 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1802
1803 cmp(sp, zr); // Clear Z flag; SP is never zero
1804 // Scan R2 words at [R5] for an occurrence of R0.
1805 // Set NZ/Z based on last compare.
1806 repne_scan(/*addr*/r_array_base, /*value*/r_super_klass, /*count*/r_array_length, rscratch2);
1807 // rscratch1 == 0 iff we got a match.
1808 cset(rscratch1, NE);
1809
1810 Label passed;
1811 cmp(result, zr);
1812 cset(result, NE); // normalize result to 0/1 for comparison
1813
1814 cmp(rscratch1, result);
1815 br(EQ, passed);
1816 {
1817 mov(r0, r_super_klass); // r0 <- r0
1818 mov(r1, r_sub_klass); // r1 <- r4
1819 mov(r2, /*expected*/rscratch1); // r2 <- r8
1820 mov(r3, result); // r3 <- r5
1821 mov(r4, (address)("mismatch")); // r4 <- const
1822 rt_call(CAST_FROM_FN_PTR(address, Klass::on_secondary_supers_verification_failure), rscratch2);
1823 should_not_reach_here();
1824 }
1825 bind(passed);
1826
1827 BLOCK_COMMENT("} verify_secondary_supers_table");
1828 }
1829
1830 void MacroAssembler::clinit_barrier(Register klass, Register scratch, Label* L_fast_path, Label* L_slow_path) {
1831 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
1832 assert_different_registers(klass, rthread, scratch);
1833
1834 Label L_fallthrough, L_tmp;
1835 if (L_fast_path == nullptr) {
1836 L_fast_path = &L_fallthrough;
1837 } else if (L_slow_path == nullptr) {
1838 L_slow_path = &L_fallthrough;
1839 }
1840 // Fast path check: class is fully initialized
1841 ldrb(scratch, Address(klass, InstanceKlass::init_state_offset()));
1842 subs(zr, scratch, InstanceKlass::fully_initialized);
1843 br(Assembler::EQ, *L_fast_path);
1844
1845 // Fast path check: current thread is initializer thread
1846 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
1847 cmp(rthread, scratch);
1848
1849 if (L_slow_path == &L_fallthrough) {
1850 br(Assembler::EQ, *L_fast_path);
1851 bind(*L_slow_path);
1852 } else if (L_fast_path == &L_fallthrough) {
1853 br(Assembler::NE, *L_slow_path);
1854 bind(*L_fast_path);
1855 } else {
1856 Unimplemented();
1857 }
1858 }
1859
1860 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
1861 if (!VerifyOops) return;
1862
1863 // Pass register number to verify_oop_subroutine
1864 const char* b = nullptr;
1865 {
1866 ResourceMark rm;
1867 stringStream ss;
1868 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
1869 b = code_string(ss.as_string());
1870 }
1871 BLOCK_COMMENT("verify_oop {");
1872
1873 strip_return_address(); // This might happen within a stack frame.
1874 protect_return_address();
1875 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1876 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1877
1878 mov(r0, reg);
1879 movptr(rscratch1, (uintptr_t)(address)b);
1880
1881 // call indirectly to solve generation ordering problem
1882 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1883 ldr(rscratch2, Address(rscratch2));
1884 blr(rscratch2);
1885
1886 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1887 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1888 authenticate_return_address();
1889
1890 BLOCK_COMMENT("} verify_oop");
1891 }
1892
1893 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
1894 if (!VerifyOops) return;
1895
1896 const char* b = nullptr;
1897 {
1898 ResourceMark rm;
1899 stringStream ss;
1900 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
1901 b = code_string(ss.as_string());
1902 }
1903 BLOCK_COMMENT("verify_oop_addr {");
1904
1905 strip_return_address(); // This might happen within a stack frame.
1906 protect_return_address();
1907 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1908 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1909
1910 // addr may contain sp so we will have to adjust it based on the
1911 // pushes that we just did.
1912 if (addr.uses(sp)) {
1913 lea(r0, addr);
1914 ldr(r0, Address(r0, 4 * wordSize));
1915 } else {
1916 ldr(r0, addr);
1917 }
1918 movptr(rscratch1, (uintptr_t)(address)b);
1919
1920 // call indirectly to solve generation ordering problem
1921 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1922 ldr(rscratch2, Address(rscratch2));
1923 blr(rscratch2);
1924
1925 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1926 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1927 authenticate_return_address();
1928
1929 BLOCK_COMMENT("} verify_oop_addr");
1930 }
1931
1932 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
1933 int extra_slot_offset) {
1934 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
1935 int stackElementSize = Interpreter::stackElementSize;
1936 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
1937 #ifdef ASSERT
1938 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
1939 assert(offset1 - offset == stackElementSize, "correct arithmetic");
1940 #endif
1941 if (arg_slot.is_constant()) {
1942 return Address(esp, arg_slot.as_constant() * stackElementSize
1943 + offset);
1944 } else {
1945 add(rscratch1, esp, arg_slot.as_register(),
1946 ext::uxtx, exact_log2(stackElementSize));
1947 return Address(rscratch1, offset);
1948 }
1949 }
1950
1951 void MacroAssembler::call_VM_leaf_base(address entry_point,
1952 int number_of_arguments,
1953 Label *retaddr) {
1954 Label E, L;
1955
1956 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
1957
1958 mov(rscratch1, entry_point);
1959 blr(rscratch1);
1960 if (retaddr)
1961 bind(*retaddr);
1962
1963 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
1964 }
1965
1966 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1967 call_VM_leaf_base(entry_point, number_of_arguments);
1968 }
1969
1970 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1971 pass_arg0(this, arg_0);
1972 call_VM_leaf_base(entry_point, 1);
1973 }
1974
1975 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1976 assert_different_registers(arg_1, c_rarg0);
1977 pass_arg0(this, arg_0);
1978 pass_arg1(this, arg_1);
1979 call_VM_leaf_base(entry_point, 2);
1980 }
1981
1982 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1983 Register arg_1, Register arg_2) {
1984 assert_different_registers(arg_1, c_rarg0);
1985 assert_different_registers(arg_2, c_rarg0, c_rarg1);
1986 pass_arg0(this, arg_0);
1987 pass_arg1(this, arg_1);
1988 pass_arg2(this, arg_2);
1989 call_VM_leaf_base(entry_point, 3);
1990 }
1991
1992 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1993 pass_arg0(this, arg_0);
1994 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1995 }
1996
1997 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1998
1999 assert_different_registers(arg_0, c_rarg1);
2000 pass_arg1(this, arg_1);
2001 pass_arg0(this, arg_0);
2002 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2003 }
2004
2005 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2006 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2007 assert_different_registers(arg_1, c_rarg2);
2008 pass_arg2(this, arg_2);
2009 pass_arg1(this, arg_1);
2010 pass_arg0(this, arg_0);
2011 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2012 }
2013
2014 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2015 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
2016 assert_different_registers(arg_1, c_rarg2, c_rarg3);
2017 assert_different_registers(arg_2, c_rarg3);
2018 pass_arg3(this, arg_3);
2019 pass_arg2(this, arg_2);
2020 pass_arg1(this, arg_1);
2021 pass_arg0(this, arg_0);
2022 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2023 }
2024
2025 void MacroAssembler::null_check(Register reg, int offset) {
2026 if (needs_explicit_null_check(offset)) {
2027 // provoke OS null exception if reg is null by
2028 // accessing M[reg] w/o changing any registers
2029 // NOTE: this is plenty to provoke a segv
2030 ldr(zr, Address(reg));
2031 } else {
2032 // nothing to do, (later) access of M[reg + offset]
2033 // will provoke OS null exception if reg is null
2034 }
2035 }
2036
2037 // MacroAssembler protected routines needed to implement
2038 // public methods
2039
2040 void MacroAssembler::mov(Register r, Address dest) {
2041 code_section()->relocate(pc(), dest.rspec());
2042 uint64_t imm64 = (uint64_t)dest.target();
2043 movptr(r, imm64);
2044 }
2045
2046 // Move a constant pointer into r. In AArch64 mode the virtual
2047 // address space is 48 bits in size, so we only need three
2048 // instructions to create a patchable instruction sequence that can
2049 // reach anywhere.
2050 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2051 #ifndef PRODUCT
2052 {
2053 char buffer[64];
2054 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2055 block_comment(buffer);
2056 }
2057 #endif
2058 assert(imm64 < (1ull << 48), "48-bit overflow in address constant");
2059 movz(r, imm64 & 0xffff);
2060 imm64 >>= 16;
2061 movk(r, imm64 & 0xffff, 16);
2062 imm64 >>= 16;
2063 movk(r, imm64 & 0xffff, 32);
2064 }
2065
2066 // Macro to mov replicated immediate to vector register.
2067 // imm64: only the lower 8/16/32 bits are considered for B/H/S type. That is,
2068 // the upper 56/48/32 bits must be zeros for B/H/S type.
2069 // Vd will get the following values for different arrangements in T
2070 // imm64 == hex 000000gh T8B: Vd = ghghghghghghghgh
2071 // imm64 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
2072 // imm64 == hex 0000efgh T4H: Vd = efghefghefghefgh
2073 // imm64 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
2074 // imm64 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
2075 // imm64 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
2076 // imm64 == hex abcdefgh T1D: Vd = 00000000abcdefgh
2077 // imm64 == hex abcdefgh T2D: Vd = 00000000abcdefgh00000000abcdefgh
2078 // Clobbers rscratch1
2079 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64) {
2080 assert(T != T1Q, "unsupported");
2081 if (T == T1D || T == T2D) {
2082 int imm = operand_valid_for_movi_immediate(imm64, T);
2083 if (-1 != imm) {
2084 movi(Vd, T, imm);
2085 } else {
2086 mov(rscratch1, imm64);
2087 dup(Vd, T, rscratch1);
2088 }
2089 return;
2090 }
2091
2092 #ifdef ASSERT
2093 if (T == T8B || T == T16B) assert((imm64 & ~0xff) == 0, "extraneous bits (T8B/T16B)");
2094 if (T == T4H || T == T8H) assert((imm64 & ~0xffff) == 0, "extraneous bits (T4H/T8H)");
2095 if (T == T2S || T == T4S) assert((imm64 & ~0xffffffff) == 0, "extraneous bits (T2S/T4S)");
2096 #endif
2097 int shift = operand_valid_for_movi_immediate(imm64, T);
2098 uint32_t imm32 = imm64 & 0xffffffffULL;
2099 if (shift >= 0) {
2100 movi(Vd, T, (imm32 >> shift) & 0xff, shift);
2101 } else {
2102 movw(rscratch1, imm32);
2103 dup(Vd, T, rscratch1);
2104 }
2105 }
2106
2107 void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64)
2108 {
2109 #ifndef PRODUCT
2110 {
2111 char buffer[64];
2112 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, imm64);
2113 block_comment(buffer);
2114 }
2115 #endif
2116 if (operand_valid_for_logical_immediate(false, imm64)) {
2117 orr(dst, zr, imm64);
2118 } else {
2119 // we can use a combination of MOVZ or MOVN with
2120 // MOVK to build up the constant
2121 uint64_t imm_h[4];
2122 int zero_count = 0;
2123 int neg_count = 0;
2124 int i;
2125 for (i = 0; i < 4; i++) {
2126 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
2127 if (imm_h[i] == 0) {
2128 zero_count++;
2129 } else if (imm_h[i] == 0xffffL) {
2130 neg_count++;
2131 }
2132 }
2133 if (zero_count == 4) {
2134 // one MOVZ will do
2135 movz(dst, 0);
2136 } else if (neg_count == 4) {
2137 // one MOVN will do
2138 movn(dst, 0);
2139 } else if (zero_count == 3) {
2140 for (i = 0; i < 4; i++) {
2141 if (imm_h[i] != 0L) {
2142 movz(dst, (uint32_t)imm_h[i], (i << 4));
2143 break;
2144 }
2145 }
2146 } else if (neg_count == 3) {
2147 // one MOVN will do
2148 for (int i = 0; i < 4; i++) {
2149 if (imm_h[i] != 0xffffL) {
2150 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2151 break;
2152 }
2153 }
2154 } else if (zero_count == 2) {
2155 // one MOVZ and one MOVK will do
2156 for (i = 0; i < 3; i++) {
2157 if (imm_h[i] != 0L) {
2158 movz(dst, (uint32_t)imm_h[i], (i << 4));
2159 i++;
2160 break;
2161 }
2162 }
2163 for (;i < 4; i++) {
2164 if (imm_h[i] != 0L) {
2165 movk(dst, (uint32_t)imm_h[i], (i << 4));
2166 }
2167 }
2168 } else if (neg_count == 2) {
2169 // one MOVN and one MOVK will do
2170 for (i = 0; i < 4; i++) {
2171 if (imm_h[i] != 0xffffL) {
2172 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2173 i++;
2174 break;
2175 }
2176 }
2177 for (;i < 4; i++) {
2178 if (imm_h[i] != 0xffffL) {
2179 movk(dst, (uint32_t)imm_h[i], (i << 4));
2180 }
2181 }
2182 } else if (zero_count == 1) {
2183 // one MOVZ and two MOVKs will do
2184 for (i = 0; i < 4; i++) {
2185 if (imm_h[i] != 0L) {
2186 movz(dst, (uint32_t)imm_h[i], (i << 4));
2187 i++;
2188 break;
2189 }
2190 }
2191 for (;i < 4; i++) {
2192 if (imm_h[i] != 0x0L) {
2193 movk(dst, (uint32_t)imm_h[i], (i << 4));
2194 }
2195 }
2196 } else if (neg_count == 1) {
2197 // one MOVN and two MOVKs will do
2198 for (i = 0; i < 4; i++) {
2199 if (imm_h[i] != 0xffffL) {
2200 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2201 i++;
2202 break;
2203 }
2204 }
2205 for (;i < 4; i++) {
2206 if (imm_h[i] != 0xffffL) {
2207 movk(dst, (uint32_t)imm_h[i], (i << 4));
2208 }
2209 }
2210 } else {
2211 // use a MOVZ and 3 MOVKs (makes it easier to debug)
2212 movz(dst, (uint32_t)imm_h[0], 0);
2213 for (i = 1; i < 4; i++) {
2214 movk(dst, (uint32_t)imm_h[i], (i << 4));
2215 }
2216 }
2217 }
2218 }
2219
2220 void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32)
2221 {
2222 #ifndef PRODUCT
2223 {
2224 char buffer[64];
2225 snprintf(buffer, sizeof(buffer), "0x%" PRIX32, imm32);
2226 block_comment(buffer);
2227 }
2228 #endif
2229 if (operand_valid_for_logical_immediate(true, imm32)) {
2230 orrw(dst, zr, imm32);
2231 } else {
2232 // we can use MOVZ, MOVN or two calls to MOVK to build up the
2233 // constant
2234 uint32_t imm_h[2];
2235 imm_h[0] = imm32 & 0xffff;
2236 imm_h[1] = ((imm32 >> 16) & 0xffff);
2237 if (imm_h[0] == 0) {
2238 movzw(dst, imm_h[1], 16);
2239 } else if (imm_h[0] == 0xffff) {
2240 movnw(dst, imm_h[1] ^ 0xffff, 16);
2241 } else if (imm_h[1] == 0) {
2242 movzw(dst, imm_h[0], 0);
2243 } else if (imm_h[1] == 0xffff) {
2244 movnw(dst, imm_h[0] ^ 0xffff, 0);
2245 } else {
2246 // use a MOVZ and MOVK (makes it easier to debug)
2247 movzw(dst, imm_h[0], 0);
2248 movkw(dst, imm_h[1], 16);
2249 }
2250 }
2251 }
2252
2253 // Form an address from base + offset in Rd. Rd may or may
2254 // not actually be used: you must use the Address that is returned.
2255 // It is up to you to ensure that the shift provided matches the size
2256 // of your data.
2257 Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) {
2258 if (Address::offset_ok_for_immed(byte_offset, shift))
2259 // It fits; no need for any heroics
2260 return Address(base, byte_offset);
2261
2262 // Don't do anything clever with negative or misaligned offsets
2263 unsigned mask = (1 << shift) - 1;
2264 if (byte_offset < 0 || byte_offset & mask) {
2265 mov(Rd, byte_offset);
2266 add(Rd, base, Rd);
2267 return Address(Rd);
2268 }
2269
2270 // See if we can do this with two 12-bit offsets
2271 {
2272 uint64_t word_offset = byte_offset >> shift;
2273 uint64_t masked_offset = word_offset & 0xfff000;
2274 if (Address::offset_ok_for_immed(word_offset - masked_offset, 0)
2275 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
2276 add(Rd, base, masked_offset << shift);
2277 word_offset -= masked_offset;
2278 return Address(Rd, word_offset << shift);
2279 }
2280 }
2281
2282 // Do it the hard way
2283 mov(Rd, byte_offset);
2284 add(Rd, base, Rd);
2285 return Address(Rd);
2286 }
2287
2288 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
2289 bool want_remainder, Register scratch)
2290 {
2291 // Full implementation of Java idiv and irem. The function
2292 // returns the (pc) offset of the div instruction - may be needed
2293 // for implicit exceptions.
2294 //
2295 // constraint : ra/rb =/= scratch
2296 // normal case
2297 //
2298 // input : ra: dividend
2299 // rb: divisor
2300 //
2301 // result: either
2302 // quotient (= ra idiv rb)
2303 // remainder (= ra irem rb)
2304
2305 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2306
2307 int idivl_offset = offset();
2308 if (! want_remainder) {
2309 sdivw(result, ra, rb);
2310 } else {
2311 sdivw(scratch, ra, rb);
2312 Assembler::msubw(result, scratch, rb, ra);
2313 }
2314
2315 return idivl_offset;
2316 }
2317
2318 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
2319 bool want_remainder, Register scratch)
2320 {
2321 // Full implementation of Java ldiv and lrem. The function
2322 // returns the (pc) offset of the div instruction - may be needed
2323 // for implicit exceptions.
2324 //
2325 // constraint : ra/rb =/= scratch
2326 // normal case
2327 //
2328 // input : ra: dividend
2329 // rb: divisor
2330 //
2331 // result: either
2332 // quotient (= ra idiv rb)
2333 // remainder (= ra irem rb)
2334
2335 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2336
2337 int idivq_offset = offset();
2338 if (! want_remainder) {
2339 sdiv(result, ra, rb);
2340 } else {
2341 sdiv(scratch, ra, rb);
2342 Assembler::msub(result, scratch, rb, ra);
2343 }
2344
2345 return idivq_offset;
2346 }
2347
2348 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
2349 address prev = pc() - NativeMembar::instruction_size;
2350 address last = code()->last_insn();
2351 if (last != nullptr && nativeInstruction_at(last)->is_Membar() && prev == last) {
2352 NativeMembar *bar = NativeMembar_at(prev);
2353 // We are merging two memory barrier instructions. On AArch64 we
2354 // can do this simply by ORing them together.
2355 bar->set_kind(bar->get_kind() | order_constraint);
2356 BLOCK_COMMENT("merged membar");
2357 } else {
2358 code()->set_last_insn(pc());
2359 dmb(Assembler::barrier(order_constraint));
2360 }
2361 }
2362
2363 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) {
2364 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) {
2365 merge_ldst(rt, adr, size_in_bytes, is_store);
2366 code()->clear_last_insn();
2367 return true;
2368 } else {
2369 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported.");
2370 const uint64_t mask = size_in_bytes - 1;
2371 if (adr.getMode() == Address::base_plus_offset &&
2372 (adr.offset() & mask) == 0) { // only supports base_plus_offset.
2373 code()->set_last_insn(pc());
2374 }
2375 return false;
2376 }
2377 }
2378
2379 void MacroAssembler::ldr(Register Rx, const Address &adr) {
2380 // We always try to merge two adjacent loads into one ldp.
2381 if (!try_merge_ldst(Rx, adr, 8, false)) {
2382 Assembler::ldr(Rx, adr);
2383 }
2384 }
2385
2386 void MacroAssembler::ldrw(Register Rw, const Address &adr) {
2387 // We always try to merge two adjacent loads into one ldp.
2388 if (!try_merge_ldst(Rw, adr, 4, false)) {
2389 Assembler::ldrw(Rw, adr);
2390 }
2391 }
2392
2393 void MacroAssembler::str(Register Rx, const Address &adr) {
2394 // We always try to merge two adjacent stores into one stp.
2395 if (!try_merge_ldst(Rx, adr, 8, true)) {
2396 Assembler::str(Rx, adr);
2397 }
2398 }
2399
2400 void MacroAssembler::strw(Register Rw, const Address &adr) {
2401 // We always try to merge two adjacent stores into one stp.
2402 if (!try_merge_ldst(Rw, adr, 4, true)) {
2403 Assembler::strw(Rw, adr);
2404 }
2405 }
2406
2407 // MacroAssembler routines found actually to be needed
2408
2409 void MacroAssembler::push(Register src)
2410 {
2411 str(src, Address(pre(esp, -1 * wordSize)));
2412 }
2413
2414 void MacroAssembler::pop(Register dst)
2415 {
2416 ldr(dst, Address(post(esp, 1 * wordSize)));
2417 }
2418
2419 // Note: load_unsigned_short used to be called load_unsigned_word.
2420 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2421 int off = offset();
2422 ldrh(dst, src);
2423 return off;
2424 }
2425
2426 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2427 int off = offset();
2428 ldrb(dst, src);
2429 return off;
2430 }
2431
2432 int MacroAssembler::load_signed_short(Register dst, Address src) {
2433 int off = offset();
2434 ldrsh(dst, src);
2435 return off;
2436 }
2437
2438 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2439 int off = offset();
2440 ldrsb(dst, src);
2441 return off;
2442 }
2443
2444 int MacroAssembler::load_signed_short32(Register dst, Address src) {
2445 int off = offset();
2446 ldrshw(dst, src);
2447 return off;
2448 }
2449
2450 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
2451 int off = offset();
2452 ldrsbw(dst, src);
2453 return off;
2454 }
2455
2456 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) {
2457 switch (size_in_bytes) {
2458 case 8: ldr(dst, src); break;
2459 case 4: ldrw(dst, src); break;
2460 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2461 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2462 default: ShouldNotReachHere();
2463 }
2464 }
2465
2466 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes) {
2467 switch (size_in_bytes) {
2468 case 8: str(src, dst); break;
2469 case 4: strw(src, dst); break;
2470 case 2: strh(src, dst); break;
2471 case 1: strb(src, dst); break;
2472 default: ShouldNotReachHere();
2473 }
2474 }
2475
2476 void MacroAssembler::decrementw(Register reg, int value)
2477 {
2478 if (value < 0) { incrementw(reg, -value); return; }
2479 if (value == 0) { return; }
2480 if (value < (1 << 12)) { subw(reg, reg, value); return; }
2481 /* else */ {
2482 guarantee(reg != rscratch2, "invalid dst for register decrement");
2483 movw(rscratch2, (unsigned)value);
2484 subw(reg, reg, rscratch2);
2485 }
2486 }
2487
2488 void MacroAssembler::decrement(Register reg, int value)
2489 {
2490 if (value < 0) { increment(reg, -value); return; }
2491 if (value == 0) { return; }
2492 if (value < (1 << 12)) { sub(reg, reg, value); return; }
2493 /* else */ {
2494 assert(reg != rscratch2, "invalid dst for register decrement");
2495 mov(rscratch2, (uint64_t)value);
2496 sub(reg, reg, rscratch2);
2497 }
2498 }
2499
2500 void MacroAssembler::decrementw(Address dst, int value)
2501 {
2502 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
2503 if (dst.getMode() == Address::literal) {
2504 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2505 lea(rscratch2, dst);
2506 dst = Address(rscratch2);
2507 }
2508 ldrw(rscratch1, dst);
2509 decrementw(rscratch1, value);
2510 strw(rscratch1, dst);
2511 }
2512
2513 void MacroAssembler::decrement(Address dst, int value)
2514 {
2515 assert(!dst.uses(rscratch1), "invalid address for decrement");
2516 if (dst.getMode() == Address::literal) {
2517 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2518 lea(rscratch2, dst);
2519 dst = Address(rscratch2);
2520 }
2521 ldr(rscratch1, dst);
2522 decrement(rscratch1, value);
2523 str(rscratch1, dst);
2524 }
2525
2526 void MacroAssembler::incrementw(Register reg, int value)
2527 {
2528 if (value < 0) { decrementw(reg, -value); return; }
2529 if (value == 0) { return; }
2530 if (value < (1 << 12)) { addw(reg, reg, value); return; }
2531 /* else */ {
2532 assert(reg != rscratch2, "invalid dst for register increment");
2533 movw(rscratch2, (unsigned)value);
2534 addw(reg, reg, rscratch2);
2535 }
2536 }
2537
2538 void MacroAssembler::increment(Register reg, int value)
2539 {
2540 if (value < 0) { decrement(reg, -value); return; }
2541 if (value == 0) { return; }
2542 if (value < (1 << 12)) { add(reg, reg, value); return; }
2543 /* else */ {
2544 assert(reg != rscratch2, "invalid dst for register increment");
2545 movw(rscratch2, (unsigned)value);
2546 add(reg, reg, rscratch2);
2547 }
2548 }
2549
2550 void MacroAssembler::incrementw(Address dst, int value)
2551 {
2552 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2553 if (dst.getMode() == Address::literal) {
2554 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2555 lea(rscratch2, dst);
2556 dst = Address(rscratch2);
2557 }
2558 ldrw(rscratch1, dst);
2559 incrementw(rscratch1, value);
2560 strw(rscratch1, dst);
2561 }
2562
2563 void MacroAssembler::increment(Address dst, int value)
2564 {
2565 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2566 if (dst.getMode() == Address::literal) {
2567 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2568 lea(rscratch2, dst);
2569 dst = Address(rscratch2);
2570 }
2571 ldr(rscratch1, dst);
2572 increment(rscratch1, value);
2573 str(rscratch1, dst);
2574 }
2575
2576 // Push lots of registers in the bit set supplied. Don't push sp.
2577 // Return the number of words pushed
2578 int MacroAssembler::push(unsigned int bitset, Register stack) {
2579 int words_pushed = 0;
2580
2581 // Scan bitset to accumulate register pairs
2582 unsigned char regs[32];
2583 int count = 0;
2584 for (int reg = 0; reg <= 30; reg++) {
2585 if (1 & bitset)
2586 regs[count++] = reg;
2587 bitset >>= 1;
2588 }
2589 regs[count++] = zr->raw_encoding();
2590 count &= ~1; // Only push an even number of regs
2591
2592 if (count) {
2593 stp(as_Register(regs[0]), as_Register(regs[1]),
2594 Address(pre(stack, -count * wordSize)));
2595 words_pushed += 2;
2596 }
2597 for (int i = 2; i < count; i += 2) {
2598 stp(as_Register(regs[i]), as_Register(regs[i+1]),
2599 Address(stack, i * wordSize));
2600 words_pushed += 2;
2601 }
2602
2603 assert(words_pushed == count, "oops, pushed != count");
2604
2605 return count;
2606 }
2607
2608 int MacroAssembler::pop(unsigned int bitset, Register stack) {
2609 int words_pushed = 0;
2610
2611 // Scan bitset to accumulate register pairs
2612 unsigned char regs[32];
2613 int count = 0;
2614 for (int reg = 0; reg <= 30; reg++) {
2615 if (1 & bitset)
2616 regs[count++] = reg;
2617 bitset >>= 1;
2618 }
2619 regs[count++] = zr->raw_encoding();
2620 count &= ~1;
2621
2622 for (int i = 2; i < count; i += 2) {
2623 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
2624 Address(stack, i * wordSize));
2625 words_pushed += 2;
2626 }
2627 if (count) {
2628 ldp(as_Register(regs[0]), as_Register(regs[1]),
2629 Address(post(stack, count * wordSize)));
2630 words_pushed += 2;
2631 }
2632
2633 assert(words_pushed == count, "oops, pushed != count");
2634
2635 return count;
2636 }
2637
2638 // Push lots of registers in the bit set supplied. Don't push sp.
2639 // Return the number of dwords pushed
2640 int MacroAssembler::push_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
2641 int words_pushed = 0;
2642 bool use_sve = false;
2643 int sve_vector_size_in_bytes = 0;
2644
2645 #ifdef COMPILER2
2646 use_sve = Matcher::supports_scalable_vector();
2647 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
2648 #endif
2649
2650 // Scan bitset to accumulate register pairs
2651 unsigned char regs[32];
2652 int count = 0;
2653 for (int reg = 0; reg <= 31; reg++) {
2654 if (1 & bitset)
2655 regs[count++] = reg;
2656 bitset >>= 1;
2657 }
2658
2659 if (count == 0) {
2660 return 0;
2661 }
2662
2663 if (mode == PushPopFull) {
2664 if (use_sve && sve_vector_size_in_bytes > 16) {
2665 mode = PushPopSVE;
2666 } else {
2667 mode = PushPopNeon;
2668 }
2669 }
2670
2671 #ifndef PRODUCT
2672 {
2673 char buffer[48];
2674 if (mode == PushPopSVE) {
2675 snprintf(buffer, sizeof(buffer), "push_fp: %d SVE registers", count);
2676 } else if (mode == PushPopNeon) {
2677 snprintf(buffer, sizeof(buffer), "push_fp: %d Neon registers", count);
2678 } else {
2679 snprintf(buffer, sizeof(buffer), "push_fp: %d fp registers", count);
2680 }
2681 block_comment(buffer);
2682 }
2683 #endif
2684
2685 if (mode == PushPopSVE) {
2686 sub(stack, stack, sve_vector_size_in_bytes * count);
2687 for (int i = 0; i < count; i++) {
2688 sve_str(as_FloatRegister(regs[i]), Address(stack, i));
2689 }
2690 return count * sve_vector_size_in_bytes / 8;
2691 }
2692
2693 if (mode == PushPopNeon) {
2694 if (count == 1) {
2695 strq(as_FloatRegister(regs[0]), Address(pre(stack, -wordSize * 2)));
2696 return 2;
2697 }
2698
2699 bool odd = (count & 1) == 1;
2700 int push_slots = count + (odd ? 1 : 0);
2701
2702 // Always pushing full 128 bit registers.
2703 stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize * 2)));
2704 words_pushed += 2;
2705
2706 for (int i = 2; i + 1 < count; i += 2) {
2707 stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
2708 words_pushed += 2;
2709 }
2710
2711 if (odd) {
2712 strq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
2713 words_pushed++;
2714 }
2715
2716 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
2717 return count * 2;
2718 }
2719
2720 if (mode == PushPopFp) {
2721 bool odd = (count & 1) == 1;
2722 int push_slots = count + (odd ? 1 : 0);
2723
2724 if (count == 1) {
2725 // Stack pointer must be 16 bytes aligned
2726 strd(as_FloatRegister(regs[0]), Address(pre(stack, -push_slots * wordSize)));
2727 return 1;
2728 }
2729
2730 stpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize)));
2731 words_pushed += 2;
2732
2733 for (int i = 2; i + 1 < count; i += 2) {
2734 stpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
2735 words_pushed += 2;
2736 }
2737
2738 if (odd) {
2739 // Stack pointer must be 16 bytes aligned
2740 strd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
2741 words_pushed++;
2742 }
2743
2744 assert(words_pushed == count, "oops, pushed != count");
2745
2746 return count;
2747 }
2748
2749 return 0;
2750 }
2751
2752 // Return the number of dwords popped
2753 int MacroAssembler::pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
2754 int words_pushed = 0;
2755 bool use_sve = false;
2756 int sve_vector_size_in_bytes = 0;
2757
2758 #ifdef COMPILER2
2759 use_sve = Matcher::supports_scalable_vector();
2760 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
2761 #endif
2762 // Scan bitset to accumulate register pairs
2763 unsigned char regs[32];
2764 int count = 0;
2765 for (int reg = 0; reg <= 31; reg++) {
2766 if (1 & bitset)
2767 regs[count++] = reg;
2768 bitset >>= 1;
2769 }
2770
2771 if (count == 0) {
2772 return 0;
2773 }
2774
2775 if (mode == PushPopFull) {
2776 if (use_sve && sve_vector_size_in_bytes > 16) {
2777 mode = PushPopSVE;
2778 } else {
2779 mode = PushPopNeon;
2780 }
2781 }
2782
2783 #ifndef PRODUCT
2784 {
2785 char buffer[48];
2786 if (mode == PushPopSVE) {
2787 snprintf(buffer, sizeof(buffer), "pop_fp: %d SVE registers", count);
2788 } else if (mode == PushPopNeon) {
2789 snprintf(buffer, sizeof(buffer), "pop_fp: %d Neon registers", count);
2790 } else {
2791 snprintf(buffer, sizeof(buffer), "pop_fp: %d fp registers", count);
2792 }
2793 block_comment(buffer);
2794 }
2795 #endif
2796
2797 if (mode == PushPopSVE) {
2798 for (int i = count - 1; i >= 0; i--) {
2799 sve_ldr(as_FloatRegister(regs[i]), Address(stack, i));
2800 }
2801 add(stack, stack, sve_vector_size_in_bytes * count);
2802 return count * sve_vector_size_in_bytes / 8;
2803 }
2804
2805 if (mode == PushPopNeon) {
2806 if (count == 1) {
2807 ldrq(as_FloatRegister(regs[0]), Address(post(stack, wordSize * 2)));
2808 return 2;
2809 }
2810
2811 bool odd = (count & 1) == 1;
2812 int push_slots = count + (odd ? 1 : 0);
2813
2814 if (odd) {
2815 ldrq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
2816 words_pushed++;
2817 }
2818
2819 for (int i = 2; i + 1 < count; i += 2) {
2820 ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
2821 words_pushed += 2;
2822 }
2823
2824 ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize * 2)));
2825 words_pushed += 2;
2826
2827 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
2828
2829 return count * 2;
2830 }
2831
2832 if (mode == PushPopFp) {
2833 bool odd = (count & 1) == 1;
2834 int push_slots = count + (odd ? 1 : 0);
2835
2836 if (count == 1) {
2837 ldrd(as_FloatRegister(regs[0]), Address(post(stack, push_slots * wordSize)));
2838 return 1;
2839 }
2840
2841 if (odd) {
2842 ldrd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
2843 words_pushed++;
2844 }
2845
2846 for (int i = 2; i + 1 < count; i += 2) {
2847 ldpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
2848 words_pushed += 2;
2849 }
2850
2851 ldpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize)));
2852 words_pushed += 2;
2853
2854 assert(words_pushed == count, "oops, pushed != count");
2855
2856 return count;
2857 }
2858
2859 return 0;
2860 }
2861
2862 // Return the number of dwords pushed
2863 int MacroAssembler::push_p(unsigned int bitset, Register stack) {
2864 bool use_sve = false;
2865 int sve_predicate_size_in_slots = 0;
2866
2867 #ifdef COMPILER2
2868 use_sve = Matcher::supports_scalable_vector();
2869 if (use_sve) {
2870 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
2871 }
2872 #endif
2873
2874 if (!use_sve) {
2875 return 0;
2876 }
2877
2878 unsigned char regs[PRegister::number_of_registers];
2879 int count = 0;
2880 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
2881 if (1 & bitset)
2882 regs[count++] = reg;
2883 bitset >>= 1;
2884 }
2885
2886 if (count == 0) {
2887 return 0;
2888 }
2889
2890 int total_push_bytes = align_up(sve_predicate_size_in_slots *
2891 VMRegImpl::stack_slot_size * count, 16);
2892 sub(stack, stack, total_push_bytes);
2893 for (int i = 0; i < count; i++) {
2894 sve_str(as_PRegister(regs[i]), Address(stack, i));
2895 }
2896 return total_push_bytes / 8;
2897 }
2898
2899 // Return the number of dwords popped
2900 int MacroAssembler::pop_p(unsigned int bitset, Register stack) {
2901 bool use_sve = false;
2902 int sve_predicate_size_in_slots = 0;
2903
2904 #ifdef COMPILER2
2905 use_sve = Matcher::supports_scalable_vector();
2906 if (use_sve) {
2907 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
2908 }
2909 #endif
2910
2911 if (!use_sve) {
2912 return 0;
2913 }
2914
2915 unsigned char regs[PRegister::number_of_registers];
2916 int count = 0;
2917 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
2918 if (1 & bitset)
2919 regs[count++] = reg;
2920 bitset >>= 1;
2921 }
2922
2923 if (count == 0) {
2924 return 0;
2925 }
2926
2927 int total_pop_bytes = align_up(sve_predicate_size_in_slots *
2928 VMRegImpl::stack_slot_size * count, 16);
2929 for (int i = count - 1; i >= 0; i--) {
2930 sve_ldr(as_PRegister(regs[i]), Address(stack, i));
2931 }
2932 add(stack, stack, total_pop_bytes);
2933 return total_pop_bytes / 8;
2934 }
2935
2936 #ifdef ASSERT
2937 void MacroAssembler::verify_heapbase(const char* msg) {
2938 #if 0
2939 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
2940 assert (Universe::heap() != nullptr, "java heap should be initialized");
2941 if (!UseCompressedOops || Universe::ptr_base() == nullptr) {
2942 // rheapbase is allocated as general register
2943 return;
2944 }
2945 if (CheckCompressedOops) {
2946 Label ok;
2947 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
2948 cmpptr(rheapbase, ExternalAddress(CompressedOops::ptrs_base_addr()));
2949 br(Assembler::EQ, ok);
2950 stop(msg);
2951 bind(ok);
2952 pop(1 << rscratch1->encoding(), sp);
2953 }
2954 #endif
2955 }
2956 #endif
2957
2958 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2) {
2959 assert_different_registers(value, tmp1, tmp2);
2960 Label done, tagged, weak_tagged;
2961
2962 cbz(value, done); // Use null as-is.
2963 tst(value, JNIHandles::tag_mask); // Test for tag.
2964 br(Assembler::NE, tagged);
2965
2966 // Resolve local handle
2967 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp1, tmp2);
2968 verify_oop(value);
2969 b(done);
2970
2971 bind(tagged);
2972 STATIC_ASSERT(JNIHandles::TypeTag::weak_global == 0b1);
2973 tbnz(value, 0, weak_tagged); // Test for weak tag.
2974
2975 // Resolve global handle
2976 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
2977 verify_oop(value);
2978 b(done);
2979
2980 bind(weak_tagged);
2981 // Resolve jweak.
2982 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
2983 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp1, tmp2);
2984 verify_oop(value);
2985
2986 bind(done);
2987 }
2988
2989 void MacroAssembler::resolve_global_jobject(Register value, Register tmp1, Register tmp2) {
2990 assert_different_registers(value, tmp1, tmp2);
2991 Label done;
2992
2993 cbz(value, done); // Use null as-is.
2994
2995 #ifdef ASSERT
2996 {
2997 STATIC_ASSERT(JNIHandles::TypeTag::global == 0b10);
2998 Label valid_global_tag;
2999 tbnz(value, 1, valid_global_tag); // Test for global tag
3000 stop("non global jobject using resolve_global_jobject");
3001 bind(valid_global_tag);
3002 }
3003 #endif
3004
3005 // Resolve global handle
3006 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3007 verify_oop(value);
3008
3009 bind(done);
3010 }
3011
3012 void MacroAssembler::stop(const char* msg) {
3013 BLOCK_COMMENT(msg);
3014 dcps1(0xdeae);
3015 emit_int64((uintptr_t)msg);
3016 }
3017
3018 void MacroAssembler::unimplemented(const char* what) {
3019 const char* buf = nullptr;
3020 {
3021 ResourceMark rm;
3022 stringStream ss;
3023 ss.print("unimplemented: %s", what);
3024 buf = code_string(ss.as_string());
3025 }
3026 stop(buf);
3027 }
3028
3029 void MacroAssembler::_assert_asm(Assembler::Condition cc, const char* msg) {
3030 #ifdef ASSERT
3031 Label OK;
3032 br(cc, OK);
3033 stop(msg);
3034 bind(OK);
3035 #endif
3036 }
3037
3038 // If a constant does not fit in an immediate field, generate some
3039 // number of MOV instructions and then perform the operation.
3040 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
3041 add_sub_imm_insn insn1,
3042 add_sub_reg_insn insn2,
3043 bool is32) {
3044 assert(Rd != zr, "Rd = zr and not setting flags?");
3045 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3046 if (fits) {
3047 (this->*insn1)(Rd, Rn, imm);
3048 } else {
3049 if (uabs(imm) < (1 << 24)) {
3050 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
3051 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
3052 } else {
3053 assert_different_registers(Rd, Rn);
3054 mov(Rd, imm);
3055 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3056 }
3057 }
3058 }
3059
3060 // Separate vsn which sets the flags. Optimisations are more restricted
3061 // because we must set the flags correctly.
3062 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
3063 add_sub_imm_insn insn1,
3064 add_sub_reg_insn insn2,
3065 bool is32) {
3066 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3067 if (fits) {
3068 (this->*insn1)(Rd, Rn, imm);
3069 } else {
3070 assert_different_registers(Rd, Rn);
3071 assert(Rd != zr, "overflow in immediate operand");
3072 mov(Rd, imm);
3073 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3074 }
3075 }
3076
3077
3078 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
3079 if (increment.is_register()) {
3080 add(Rd, Rn, increment.as_register());
3081 } else {
3082 add(Rd, Rn, increment.as_constant());
3083 }
3084 }
3085
3086 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
3087 if (increment.is_register()) {
3088 addw(Rd, Rn, increment.as_register());
3089 } else {
3090 addw(Rd, Rn, increment.as_constant());
3091 }
3092 }
3093
3094 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
3095 if (decrement.is_register()) {
3096 sub(Rd, Rn, decrement.as_register());
3097 } else {
3098 sub(Rd, Rn, decrement.as_constant());
3099 }
3100 }
3101
3102 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
3103 if (decrement.is_register()) {
3104 subw(Rd, Rn, decrement.as_register());
3105 } else {
3106 subw(Rd, Rn, decrement.as_constant());
3107 }
3108 }
3109
3110 void MacroAssembler::reinit_heapbase()
3111 {
3112 if (UseCompressedOops) {
3113 if (Universe::is_fully_initialized()) {
3114 mov(rheapbase, CompressedOops::ptrs_base());
3115 } else {
3116 lea(rheapbase, ExternalAddress(CompressedOops::ptrs_base_addr()));
3117 ldr(rheapbase, Address(rheapbase));
3118 }
3119 }
3120 }
3121
3122 // this simulates the behaviour of the x86 cmpxchg instruction using a
3123 // load linked/store conditional pair. we use the acquire/release
3124 // versions of these instructions so that we flush pending writes as
3125 // per Java semantics.
3126
3127 // n.b the x86 version assumes the old value to be compared against is
3128 // in rax and updates rax with the value located in memory if the
3129 // cmpxchg fails. we supply a register for the old value explicitly
3130
3131 // the aarch64 load linked/store conditional instructions do not
3132 // accept an offset. so, unlike x86, we must provide a plain register
3133 // to identify the memory word to be compared/exchanged rather than a
3134 // register+offset Address.
3135
3136 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
3137 Label &succeed, Label *fail) {
3138 // oldv holds comparison value
3139 // newv holds value to write in exchange
3140 // addr identifies memory word to compare against/update
3141 if (UseLSE) {
3142 mov(tmp, oldv);
3143 casal(Assembler::xword, oldv, newv, addr);
3144 cmp(tmp, oldv);
3145 br(Assembler::EQ, succeed);
3146 membar(AnyAny);
3147 } else {
3148 Label retry_load, nope;
3149 prfm(Address(addr), PSTL1STRM);
3150 bind(retry_load);
3151 // flush and load exclusive from the memory location
3152 // and fail if it is not what we expect
3153 ldaxr(tmp, addr);
3154 cmp(tmp, oldv);
3155 br(Assembler::NE, nope);
3156 // if we store+flush with no intervening write tmp will be zero
3157 stlxr(tmp, newv, addr);
3158 cbzw(tmp, succeed);
3159 // retry so we only ever return after a load fails to compare
3160 // ensures we don't return a stale value after a failed write.
3161 b(retry_load);
3162 // if the memory word differs we return it in oldv and signal a fail
3163 bind(nope);
3164 membar(AnyAny);
3165 mov(oldv, tmp);
3166 }
3167 if (fail)
3168 b(*fail);
3169 }
3170
3171 void MacroAssembler::cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
3172 Label &succeed, Label *fail) {
3173 assert(oopDesc::mark_offset_in_bytes() == 0, "assumption");
3174 cmpxchgptr(oldv, newv, obj, tmp, succeed, fail);
3175 }
3176
3177 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
3178 Label &succeed, Label *fail) {
3179 // oldv holds comparison value
3180 // newv holds value to write in exchange
3181 // addr identifies memory word to compare against/update
3182 // tmp returns 0/1 for success/failure
3183 if (UseLSE) {
3184 mov(tmp, oldv);
3185 casal(Assembler::word, oldv, newv, addr);
3186 cmp(tmp, oldv);
3187 br(Assembler::EQ, succeed);
3188 membar(AnyAny);
3189 } else {
3190 Label retry_load, nope;
3191 prfm(Address(addr), PSTL1STRM);
3192 bind(retry_load);
3193 // flush and load exclusive from the memory location
3194 // and fail if it is not what we expect
3195 ldaxrw(tmp, addr);
3196 cmp(tmp, oldv);
3197 br(Assembler::NE, nope);
3198 // if we store+flush with no intervening write tmp will be zero
3199 stlxrw(tmp, newv, addr);
3200 cbzw(tmp, succeed);
3201 // retry so we only ever return after a load fails to compare
3202 // ensures we don't return a stale value after a failed write.
3203 b(retry_load);
3204 // if the memory word differs we return it in oldv and signal a fail
3205 bind(nope);
3206 membar(AnyAny);
3207 mov(oldv, tmp);
3208 }
3209 if (fail)
3210 b(*fail);
3211 }
3212
3213 // A generic CAS; success or failure is in the EQ flag. A weak CAS
3214 // doesn't retry and may fail spuriously. If the oldval is wanted,
3215 // Pass a register for the result, otherwise pass noreg.
3216
3217 // Clobbers rscratch1
3218 void MacroAssembler::cmpxchg(Register addr, Register expected,
3219 Register new_val,
3220 enum operand_size size,
3221 bool acquire, bool release,
3222 bool weak,
3223 Register result) {
3224 if (result == noreg) result = rscratch1;
3225 BLOCK_COMMENT("cmpxchg {");
3226 if (UseLSE) {
3227 mov(result, expected);
3228 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
3229 compare_eq(result, expected, size);
3230 #ifdef ASSERT
3231 // Poison rscratch1 which is written on !UseLSE branch
3232 mov(rscratch1, 0x1f1f1f1f1f1f1f1f);
3233 #endif
3234 } else {
3235 Label retry_load, done;
3236 prfm(Address(addr), PSTL1STRM);
3237 bind(retry_load);
3238 load_exclusive(result, addr, size, acquire);
3239 compare_eq(result, expected, size);
3240 br(Assembler::NE, done);
3241 store_exclusive(rscratch1, new_val, addr, size, release);
3242 if (weak) {
3243 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
3244 } else {
3245 cbnzw(rscratch1, retry_load);
3246 }
3247 bind(done);
3248 }
3249 BLOCK_COMMENT("} cmpxchg");
3250 }
3251
3252 // A generic comparison. Only compares for equality, clobbers rscratch1.
3253 void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) {
3254 if (size == xword) {
3255 cmp(rm, rn);
3256 } else if (size == word) {
3257 cmpw(rm, rn);
3258 } else if (size == halfword) {
3259 eorw(rscratch1, rm, rn);
3260 ands(zr, rscratch1, 0xffff);
3261 } else if (size == byte) {
3262 eorw(rscratch1, rm, rn);
3263 ands(zr, rscratch1, 0xff);
3264 } else {
3265 ShouldNotReachHere();
3266 }
3267 }
3268
3269
3270 static bool different(Register a, RegisterOrConstant b, Register c) {
3271 if (b.is_constant())
3272 return a != c;
3273 else
3274 return a != b.as_register() && a != c && b.as_register() != c;
3275 }
3276
3277 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \
3278 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \
3279 if (UseLSE) { \
3280 prev = prev->is_valid() ? prev : zr; \
3281 if (incr.is_register()) { \
3282 AOP(sz, incr.as_register(), prev, addr); \
3283 } else { \
3284 mov(rscratch2, incr.as_constant()); \
3285 AOP(sz, rscratch2, prev, addr); \
3286 } \
3287 return; \
3288 } \
3289 Register result = rscratch2; \
3290 if (prev->is_valid()) \
3291 result = different(prev, incr, addr) ? prev : rscratch2; \
3292 \
3293 Label retry_load; \
3294 prfm(Address(addr), PSTL1STRM); \
3295 bind(retry_load); \
3296 LDXR(result, addr); \
3297 OP(rscratch1, result, incr); \
3298 STXR(rscratch2, rscratch1, addr); \
3299 cbnzw(rscratch2, retry_load); \
3300 if (prev->is_valid() && prev != result) { \
3301 IOP(prev, rscratch1, incr); \
3302 } \
3303 }
3304
3305 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword)
3306 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
3307 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword)
3308 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word)
3309
3310 #undef ATOMIC_OP
3311
3312 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \
3313 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
3314 if (UseLSE) { \
3315 prev = prev->is_valid() ? prev : zr; \
3316 AOP(sz, newv, prev, addr); \
3317 return; \
3318 } \
3319 Register result = rscratch2; \
3320 if (prev->is_valid()) \
3321 result = different(prev, newv, addr) ? prev : rscratch2; \
3322 \
3323 Label retry_load; \
3324 prfm(Address(addr), PSTL1STRM); \
3325 bind(retry_load); \
3326 LDXR(result, addr); \
3327 STXR(rscratch1, newv, addr); \
3328 cbnzw(rscratch1, retry_load); \
3329 if (prev->is_valid() && prev != result) \
3330 mov(prev, result); \
3331 }
3332
3333 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
3334 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
3335 ATOMIC_XCHG(xchgl, swpl, ldxr, stlxr, Assembler::xword)
3336 ATOMIC_XCHG(xchglw, swpl, ldxrw, stlxrw, Assembler::word)
3337 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
3338 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
3339
3340 #undef ATOMIC_XCHG
3341
3342 #ifndef PRODUCT
3343 extern "C" void findpc(intptr_t x);
3344 #endif
3345
3346 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
3347 {
3348 // In order to get locks to work, we need to fake a in_VM state
3349 if (ShowMessageBoxOnError ) {
3350 JavaThread* thread = JavaThread::current();
3351 JavaThreadState saved_state = thread->thread_state();
3352 thread->set_thread_state(_thread_in_vm);
3353 #ifndef PRODUCT
3354 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
3355 ttyLocker ttyl;
3356 BytecodeCounter::print();
3357 }
3358 #endif
3359 if (os::message_box(msg, "Execution stopped, print registers?")) {
3360 ttyLocker ttyl;
3361 tty->print_cr(" pc = 0x%016" PRIx64, pc);
3362 #ifndef PRODUCT
3363 tty->cr();
3364 findpc(pc);
3365 tty->cr();
3366 #endif
3367 tty->print_cr(" r0 = 0x%016" PRIx64, regs[0]);
3368 tty->print_cr(" r1 = 0x%016" PRIx64, regs[1]);
3369 tty->print_cr(" r2 = 0x%016" PRIx64, regs[2]);
3370 tty->print_cr(" r3 = 0x%016" PRIx64, regs[3]);
3371 tty->print_cr(" r4 = 0x%016" PRIx64, regs[4]);
3372 tty->print_cr(" r5 = 0x%016" PRIx64, regs[5]);
3373 tty->print_cr(" r6 = 0x%016" PRIx64, regs[6]);
3374 tty->print_cr(" r7 = 0x%016" PRIx64, regs[7]);
3375 tty->print_cr(" r8 = 0x%016" PRIx64, regs[8]);
3376 tty->print_cr(" r9 = 0x%016" PRIx64, regs[9]);
3377 tty->print_cr("r10 = 0x%016" PRIx64, regs[10]);
3378 tty->print_cr("r11 = 0x%016" PRIx64, regs[11]);
3379 tty->print_cr("r12 = 0x%016" PRIx64, regs[12]);
3380 tty->print_cr("r13 = 0x%016" PRIx64, regs[13]);
3381 tty->print_cr("r14 = 0x%016" PRIx64, regs[14]);
3382 tty->print_cr("r15 = 0x%016" PRIx64, regs[15]);
3383 tty->print_cr("r16 = 0x%016" PRIx64, regs[16]);
3384 tty->print_cr("r17 = 0x%016" PRIx64, regs[17]);
3385 tty->print_cr("r18 = 0x%016" PRIx64, regs[18]);
3386 tty->print_cr("r19 = 0x%016" PRIx64, regs[19]);
3387 tty->print_cr("r20 = 0x%016" PRIx64, regs[20]);
3388 tty->print_cr("r21 = 0x%016" PRIx64, regs[21]);
3389 tty->print_cr("r22 = 0x%016" PRIx64, regs[22]);
3390 tty->print_cr("r23 = 0x%016" PRIx64, regs[23]);
3391 tty->print_cr("r24 = 0x%016" PRIx64, regs[24]);
3392 tty->print_cr("r25 = 0x%016" PRIx64, regs[25]);
3393 tty->print_cr("r26 = 0x%016" PRIx64, regs[26]);
3394 tty->print_cr("r27 = 0x%016" PRIx64, regs[27]);
3395 tty->print_cr("r28 = 0x%016" PRIx64, regs[28]);
3396 tty->print_cr("r30 = 0x%016" PRIx64, regs[30]);
3397 tty->print_cr("r31 = 0x%016" PRIx64, regs[31]);
3398 BREAKPOINT;
3399 }
3400 }
3401 fatal("DEBUG MESSAGE: %s", msg);
3402 }
3403
3404 RegSet MacroAssembler::call_clobbered_gp_registers() {
3405 RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2);
3406 #ifndef R18_RESERVED
3407 regs += r18_tls;
3408 #endif
3409 return regs;
3410 }
3411
3412 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
3413 int step = 4 * wordSize;
3414 push(call_clobbered_gp_registers() - exclude, sp);
3415 sub(sp, sp, step);
3416 mov(rscratch1, -step);
3417 // Push v0-v7, v16-v31.
3418 for (int i = 31; i>= 4; i -= 4) {
3419 if (i <= v7->encoding() || i >= v16->encoding())
3420 st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1),
3421 as_FloatRegister(i), T1D, Address(post(sp, rscratch1)));
3422 }
3423 st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2),
3424 as_FloatRegister(3), T1D, Address(sp));
3425 }
3426
3427 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
3428 for (int i = 0; i < 32; i += 4) {
3429 if (i <= v7->encoding() || i >= v16->encoding())
3430 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3431 as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
3432 }
3433
3434 reinitialize_ptrue();
3435
3436 pop(call_clobbered_gp_registers() - exclude, sp);
3437 }
3438
3439 void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve,
3440 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3441 push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
3442 if (save_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3443 sub(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3444 for (int i = 0; i < FloatRegister::number_of_registers; i++) {
3445 sve_str(as_FloatRegister(i), Address(sp, i));
3446 }
3447 } else {
3448 int step = (save_vectors ? 8 : 4) * wordSize;
3449 mov(rscratch1, -step);
3450 sub(sp, sp, step);
3451 for (int i = 28; i >= 4; i -= 4) {
3452 st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3453 as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1)));
3454 }
3455 st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp);
3456 }
3457 if (save_vectors && use_sve && total_predicate_in_bytes > 0) {
3458 sub(sp, sp, total_predicate_in_bytes);
3459 for (int i = 0; i < PRegister::number_of_registers; i++) {
3460 sve_str(as_PRegister(i), Address(sp, i));
3461 }
3462 }
3463 }
3464
3465 void MacroAssembler::pop_CPU_state(bool restore_vectors, bool use_sve,
3466 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3467 if (restore_vectors && use_sve && total_predicate_in_bytes > 0) {
3468 for (int i = PRegister::number_of_registers - 1; i >= 0; i--) {
3469 sve_ldr(as_PRegister(i), Address(sp, i));
3470 }
3471 add(sp, sp, total_predicate_in_bytes);
3472 }
3473 if (restore_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3474 for (int i = FloatRegister::number_of_registers - 1; i >= 0; i--) {
3475 sve_ldr(as_FloatRegister(i), Address(sp, i));
3476 }
3477 add(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3478 } else {
3479 int step = (restore_vectors ? 8 : 4) * wordSize;
3480 for (int i = 0; i <= 28; i += 4)
3481 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3482 as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step)));
3483 }
3484
3485 // We may use predicate registers and rely on ptrue with SVE,
3486 // regardless of wide vector (> 8 bytes) used or not.
3487 if (use_sve) {
3488 reinitialize_ptrue();
3489 }
3490
3491 // integer registers except lr & sp
3492 pop(RegSet::range(r0, r17), sp);
3493 #ifdef R18_RESERVED
3494 ldp(zr, r19, Address(post(sp, 2 * wordSize)));
3495 pop(RegSet::range(r20, r29), sp);
3496 #else
3497 pop(RegSet::range(r18_tls, r29), sp);
3498 #endif
3499 }
3500
3501 /**
3502 * Helpers for multiply_to_len().
3503 */
3504 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
3505 Register src1, Register src2) {
3506 adds(dest_lo, dest_lo, src1);
3507 adc(dest_hi, dest_hi, zr);
3508 adds(dest_lo, dest_lo, src2);
3509 adc(final_dest_hi, dest_hi, zr);
3510 }
3511
3512 // Generate an address from (r + r1 extend offset). "size" is the
3513 // size of the operand. The result may be in rscratch2.
3514 Address MacroAssembler::offsetted_address(Register r, Register r1,
3515 Address::extend ext, int offset, int size) {
3516 if (offset || (ext.shift() % size != 0)) {
3517 lea(rscratch2, Address(r, r1, ext));
3518 return Address(rscratch2, offset);
3519 } else {
3520 return Address(r, r1, ext);
3521 }
3522 }
3523
3524 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
3525 {
3526 assert(offset >= 0, "spill to negative address?");
3527 // Offset reachable ?
3528 // Not aligned - 9 bits signed offset
3529 // Aligned - 12 bits unsigned offset shifted
3530 Register base = sp;
3531 if ((offset & (size-1)) && offset >= (1<<8)) {
3532 add(tmp, base, offset & ((1<<12)-1));
3533 base = tmp;
3534 offset &= -1u<<12;
3535 }
3536
3537 if (offset >= (1<<12) * size) {
3538 add(tmp, base, offset & (((1<<12)-1)<<12));
3539 base = tmp;
3540 offset &= ~(((1<<12)-1)<<12);
3541 }
3542
3543 return Address(base, offset);
3544 }
3545
3546 Address MacroAssembler::sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp) {
3547 assert(offset >= 0, "spill to negative address?");
3548
3549 Register base = sp;
3550
3551 // An immediate offset in the range 0 to 255 which is multiplied
3552 // by the current vector or predicate register size in bytes.
3553 if (offset % sve_reg_size_in_bytes == 0 && offset < ((1<<8)*sve_reg_size_in_bytes)) {
3554 return Address(base, offset / sve_reg_size_in_bytes);
3555 }
3556
3557 add(tmp, base, offset);
3558 return Address(tmp);
3559 }
3560
3561 // Checks whether offset is aligned.
3562 // Returns true if it is, else false.
3563 bool MacroAssembler::merge_alignment_check(Register base,
3564 size_t size,
3565 int64_t cur_offset,
3566 int64_t prev_offset) const {
3567 if (AvoidUnalignedAccesses) {
3568 if (base == sp) {
3569 // Checks whether low offset if aligned to pair of registers.
3570 int64_t pair_mask = size * 2 - 1;
3571 int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3572 return (offset & pair_mask) == 0;
3573 } else { // If base is not sp, we can't guarantee the access is aligned.
3574 return false;
3575 }
3576 } else {
3577 int64_t mask = size - 1;
3578 // Load/store pair instruction only supports element size aligned offset.
3579 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
3580 }
3581 }
3582
3583 // Checks whether current and previous loads/stores can be merged.
3584 // Returns true if it can be merged, else false.
3585 bool MacroAssembler::ldst_can_merge(Register rt,
3586 const Address &adr,
3587 size_t cur_size_in_bytes,
3588 bool is_store) const {
3589 address prev = pc() - NativeInstruction::instruction_size;
3590 address last = code()->last_insn();
3591
3592 if (last == nullptr || !nativeInstruction_at(last)->is_Imm_LdSt()) {
3593 return false;
3594 }
3595
3596 if (adr.getMode() != Address::base_plus_offset || prev != last) {
3597 return false;
3598 }
3599
3600 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3601 size_t prev_size_in_bytes = prev_ldst->size_in_bytes();
3602
3603 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging.");
3604 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging.");
3605
3606 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) {
3607 return false;
3608 }
3609
3610 int64_t max_offset = 63 * prev_size_in_bytes;
3611 int64_t min_offset = -64 * prev_size_in_bytes;
3612
3613 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
3614
3615 // Only same base can be merged.
3616 if (adr.base() != prev_ldst->base()) {
3617 return false;
3618 }
3619
3620 int64_t cur_offset = adr.offset();
3621 int64_t prev_offset = prev_ldst->offset();
3622 size_t diff = abs(cur_offset - prev_offset);
3623 if (diff != prev_size_in_bytes) {
3624 return false;
3625 }
3626
3627 // Following cases can not be merged:
3628 // ldr x2, [x2, #8]
3629 // ldr x3, [x2, #16]
3630 // or:
3631 // ldr x2, [x3, #8]
3632 // ldr x2, [x3, #16]
3633 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL.
3634 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) {
3635 return false;
3636 }
3637
3638 int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3639 // Offset range must be in ldp/stp instruction's range.
3640 if (low_offset > max_offset || low_offset < min_offset) {
3641 return false;
3642 }
3643
3644 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) {
3645 return true;
3646 }
3647
3648 return false;
3649 }
3650
3651 // Merge current load/store with previous load/store into ldp/stp.
3652 void MacroAssembler::merge_ldst(Register rt,
3653 const Address &adr,
3654 size_t cur_size_in_bytes,
3655 bool is_store) {
3656
3657 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged.");
3658
3659 Register rt_low, rt_high;
3660 address prev = pc() - NativeInstruction::instruction_size;
3661 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3662
3663 int64_t offset;
3664
3665 if (adr.offset() < prev_ldst->offset()) {
3666 offset = adr.offset();
3667 rt_low = rt;
3668 rt_high = prev_ldst->target();
3669 } else {
3670 offset = prev_ldst->offset();
3671 rt_low = prev_ldst->target();
3672 rt_high = rt;
3673 }
3674
3675 Address adr_p = Address(prev_ldst->base(), offset);
3676 // Overwrite previous generated binary.
3677 code_section()->set_end(prev);
3678
3679 const size_t sz = prev_ldst->size_in_bytes();
3680 assert(sz == 8 || sz == 4, "only supports 64/32bit merging.");
3681 if (!is_store) {
3682 BLOCK_COMMENT("merged ldr pair");
3683 if (sz == 8) {
3684 ldp(rt_low, rt_high, adr_p);
3685 } else {
3686 ldpw(rt_low, rt_high, adr_p);
3687 }
3688 } else {
3689 BLOCK_COMMENT("merged str pair");
3690 if (sz == 8) {
3691 stp(rt_low, rt_high, adr_p);
3692 } else {
3693 stpw(rt_low, rt_high, adr_p);
3694 }
3695 }
3696 }
3697
3698 /**
3699 * Multiply 64 bit by 64 bit first loop.
3700 */
3701 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
3702 Register y, Register y_idx, Register z,
3703 Register carry, Register product,
3704 Register idx, Register kdx) {
3705 //
3706 // jlong carry, x[], y[], z[];
3707 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
3708 // huge_128 product = y[idx] * x[xstart] + carry;
3709 // z[kdx] = (jlong)product;
3710 // carry = (jlong)(product >>> 64);
3711 // }
3712 // z[xstart] = carry;
3713 //
3714
3715 Label L_first_loop, L_first_loop_exit;
3716 Label L_one_x, L_one_y, L_multiply;
3717
3718 subsw(xstart, xstart, 1);
3719 br(Assembler::MI, L_one_x);
3720
3721 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
3722 ldr(x_xstart, Address(rscratch1));
3723 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
3724
3725 bind(L_first_loop);
3726 subsw(idx, idx, 1);
3727 br(Assembler::MI, L_first_loop_exit);
3728 subsw(idx, idx, 1);
3729 br(Assembler::MI, L_one_y);
3730 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3731 ldr(y_idx, Address(rscratch1));
3732 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
3733 bind(L_multiply);
3734
3735 // AArch64 has a multiply-accumulate instruction that we can't use
3736 // here because it has no way to process carries, so we have to use
3737 // separate add and adc instructions. Bah.
3738 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
3739 mul(product, x_xstart, y_idx);
3740 adds(product, product, carry);
3741 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
3742
3743 subw(kdx, kdx, 2);
3744 ror(product, product, 32); // back to big-endian
3745 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
3746
3747 b(L_first_loop);
3748
3749 bind(L_one_y);
3750 ldrw(y_idx, Address(y, 0));
3751 b(L_multiply);
3752
3753 bind(L_one_x);
3754 ldrw(x_xstart, Address(x, 0));
3755 b(L_first_loop);
3756
3757 bind(L_first_loop_exit);
3758 }
3759
3760 /**
3761 * Multiply 128 bit by 128. Unrolled inner loop.
3762 *
3763 */
3764 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
3765 Register carry, Register carry2,
3766 Register idx, Register jdx,
3767 Register yz_idx1, Register yz_idx2,
3768 Register tmp, Register tmp3, Register tmp4,
3769 Register tmp6, Register product_hi) {
3770
3771 // jlong carry, x[], y[], z[];
3772 // int kdx = ystart+1;
3773 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
3774 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
3775 // jlong carry2 = (jlong)(tmp3 >>> 64);
3776 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
3777 // carry = (jlong)(tmp4 >>> 64);
3778 // z[kdx+idx+1] = (jlong)tmp3;
3779 // z[kdx+idx] = (jlong)tmp4;
3780 // }
3781 // idx += 2;
3782 // if (idx > 0) {
3783 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
3784 // z[kdx+idx] = (jlong)yz_idx1;
3785 // carry = (jlong)(yz_idx1 >>> 64);
3786 // }
3787 //
3788
3789 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
3790
3791 lsrw(jdx, idx, 2);
3792
3793 bind(L_third_loop);
3794
3795 subsw(jdx, jdx, 1);
3796 br(Assembler::MI, L_third_loop_exit);
3797 subw(idx, idx, 4);
3798
3799 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3800
3801 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
3802
3803 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
3804
3805 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
3806 ror(yz_idx2, yz_idx2, 32);
3807
3808 ldp(rscratch2, rscratch1, Address(tmp6, 0));
3809
3810 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
3811 umulh(tmp4, product_hi, yz_idx1);
3812
3813 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
3814 ror(rscratch2, rscratch2, 32);
3815
3816 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
3817 umulh(carry2, product_hi, yz_idx2);
3818
3819 // propagate sum of both multiplications into carry:tmp4:tmp3
3820 adds(tmp3, tmp3, carry);
3821 adc(tmp4, tmp4, zr);
3822 adds(tmp3, tmp3, rscratch1);
3823 adcs(tmp4, tmp4, tmp);
3824 adc(carry, carry2, zr);
3825 adds(tmp4, tmp4, rscratch2);
3826 adc(carry, carry, zr);
3827
3828 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
3829 ror(tmp4, tmp4, 32);
3830 stp(tmp4, tmp3, Address(tmp6, 0));
3831
3832 b(L_third_loop);
3833 bind (L_third_loop_exit);
3834
3835 andw (idx, idx, 0x3);
3836 cbz(idx, L_post_third_loop_done);
3837
3838 Label L_check_1;
3839 subsw(idx, idx, 2);
3840 br(Assembler::MI, L_check_1);
3841
3842 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3843 ldr(yz_idx1, Address(rscratch1, 0));
3844 ror(yz_idx1, yz_idx1, 32);
3845 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
3846 umulh(tmp4, product_hi, yz_idx1);
3847 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
3848 ldr(yz_idx2, Address(rscratch1, 0));
3849 ror(yz_idx2, yz_idx2, 32);
3850
3851 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
3852
3853 ror(tmp3, tmp3, 32);
3854 str(tmp3, Address(rscratch1, 0));
3855
3856 bind (L_check_1);
3857
3858 andw (idx, idx, 0x1);
3859 subsw(idx, idx, 1);
3860 br(Assembler::MI, L_post_third_loop_done);
3861 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3862 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
3863 umulh(carry2, tmp4, product_hi);
3864 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
3865
3866 add2_with_carry(carry2, tmp3, tmp4, carry);
3867
3868 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
3869 extr(carry, carry2, tmp3, 32);
3870
3871 bind(L_post_third_loop_done);
3872 }
3873
3874 /**
3875 * Code for BigInteger::multiplyToLen() intrinsic.
3876 *
3877 * r0: x
3878 * r1: xlen
3879 * r2: y
3880 * r3: ylen
3881 * r4: z
3882 * r5: zlen
3883 * r10: tmp1
3884 * r11: tmp2
3885 * r12: tmp3
3886 * r13: tmp4
3887 * r14: tmp5
3888 * r15: tmp6
3889 * r16: tmp7
3890 *
3891 */
3892 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
3893 Register z, Register zlen,
3894 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
3895 Register tmp5, Register tmp6, Register product_hi) {
3896
3897 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6);
3898
3899 const Register idx = tmp1;
3900 const Register kdx = tmp2;
3901 const Register xstart = tmp3;
3902
3903 const Register y_idx = tmp4;
3904 const Register carry = tmp5;
3905 const Register product = xlen;
3906 const Register x_xstart = zlen; // reuse register
3907
3908 // First Loop.
3909 //
3910 // final static long LONG_MASK = 0xffffffffL;
3911 // int xstart = xlen - 1;
3912 // int ystart = ylen - 1;
3913 // long carry = 0;
3914 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
3915 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
3916 // z[kdx] = (int)product;
3917 // carry = product >>> 32;
3918 // }
3919 // z[xstart] = (int)carry;
3920 //
3921
3922 movw(idx, ylen); // idx = ylen;
3923 movw(kdx, zlen); // kdx = xlen+ylen;
3924 mov(carry, zr); // carry = 0;
3925
3926 Label L_done;
3927
3928 movw(xstart, xlen);
3929 subsw(xstart, xstart, 1);
3930 br(Assembler::MI, L_done);
3931
3932 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
3933
3934 Label L_second_loop;
3935 cbzw(kdx, L_second_loop);
3936
3937 Label L_carry;
3938 subw(kdx, kdx, 1);
3939 cbzw(kdx, L_carry);
3940
3941 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
3942 lsr(carry, carry, 32);
3943 subw(kdx, kdx, 1);
3944
3945 bind(L_carry);
3946 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
3947
3948 // Second and third (nested) loops.
3949 //
3950 // for (int i = xstart-1; i >= 0; i--) { // Second loop
3951 // carry = 0;
3952 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
3953 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
3954 // (z[k] & LONG_MASK) + carry;
3955 // z[k] = (int)product;
3956 // carry = product >>> 32;
3957 // }
3958 // z[i] = (int)carry;
3959 // }
3960 //
3961 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
3962
3963 const Register jdx = tmp1;
3964
3965 bind(L_second_loop);
3966 mov(carry, zr); // carry = 0;
3967 movw(jdx, ylen); // j = ystart+1
3968
3969 subsw(xstart, xstart, 1); // i = xstart-1;
3970 br(Assembler::MI, L_done);
3971
3972 str(z, Address(pre(sp, -4 * wordSize)));
3973
3974 Label L_last_x;
3975 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
3976 subsw(xstart, xstart, 1); // i = xstart-1;
3977 br(Assembler::MI, L_last_x);
3978
3979 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
3980 ldr(product_hi, Address(rscratch1));
3981 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
3982
3983 Label L_third_loop_prologue;
3984 bind(L_third_loop_prologue);
3985
3986 str(ylen, Address(sp, wordSize));
3987 stp(x, xstart, Address(sp, 2 * wordSize));
3988 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
3989 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
3990 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
3991 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
3992
3993 addw(tmp3, xlen, 1);
3994 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
3995 subsw(tmp3, tmp3, 1);
3996 br(Assembler::MI, L_done);
3997
3998 lsr(carry, carry, 32);
3999 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4000 b(L_second_loop);
4001
4002 // Next infrequent code is moved outside loops.
4003 bind(L_last_x);
4004 ldrw(product_hi, Address(x, 0));
4005 b(L_third_loop_prologue);
4006
4007 bind(L_done);
4008 }
4009
4010 // Code for BigInteger::mulAdd intrinsic
4011 // out = r0
4012 // in = r1
4013 // offset = r2 (already out.length-offset)
4014 // len = r3
4015 // k = r4
4016 //
4017 // pseudo code from java implementation:
4018 // carry = 0;
4019 // offset = out.length-offset - 1;
4020 // for (int j=len-1; j >= 0; j--) {
4021 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry;
4022 // out[offset--] = (int)product;
4023 // carry = product >>> 32;
4024 // }
4025 // return (int)carry;
4026 void MacroAssembler::mul_add(Register out, Register in, Register offset,
4027 Register len, Register k) {
4028 Label LOOP, END;
4029 // pre-loop
4030 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches
4031 csel(out, zr, out, Assembler::EQ);
4032 br(Assembler::EQ, END);
4033 add(in, in, len, LSL, 2); // in[j+1] address
4034 add(offset, out, offset, LSL, 2); // out[offset + 1] address
4035 mov(out, zr); // used to keep carry now
4036 BIND(LOOP);
4037 ldrw(rscratch1, Address(pre(in, -4)));
4038 madd(rscratch1, rscratch1, k, out);
4039 ldrw(rscratch2, Address(pre(offset, -4)));
4040 add(rscratch1, rscratch1, rscratch2);
4041 strw(rscratch1, Address(offset));
4042 lsr(out, rscratch1, 32);
4043 subs(len, len, 1);
4044 br(Assembler::NE, LOOP);
4045 BIND(END);
4046 }
4047
4048 /**
4049 * Emits code to update CRC-32 with a byte value according to constants in table
4050 *
4051 * @param [in,out]crc Register containing the crc.
4052 * @param [in]val Register containing the byte to fold into the CRC.
4053 * @param [in]table Register containing the table of crc constants.
4054 *
4055 * uint32_t crc;
4056 * val = crc_table[(val ^ crc) & 0xFF];
4057 * crc = val ^ (crc >> 8);
4058 *
4059 */
4060 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
4061 eor(val, val, crc);
4062 andr(val, val, 0xff);
4063 ldrw(val, Address(table, val, Address::lsl(2)));
4064 eor(crc, val, crc, Assembler::LSR, 8);
4065 }
4066
4067 /**
4068 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
4069 *
4070 * @param [in,out]crc Register containing the crc.
4071 * @param [in]v Register containing the 32-bit to fold into the CRC.
4072 * @param [in]table0 Register containing table 0 of crc constants.
4073 * @param [in]table1 Register containing table 1 of crc constants.
4074 * @param [in]table2 Register containing table 2 of crc constants.
4075 * @param [in]table3 Register containing table 3 of crc constants.
4076 *
4077 * uint32_t crc;
4078 * v = crc ^ v
4079 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
4080 *
4081 */
4082 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
4083 Register table0, Register table1, Register table2, Register table3,
4084 bool upper) {
4085 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
4086 uxtb(tmp, v);
4087 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
4088 ubfx(tmp, v, 8, 8);
4089 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
4090 eor(crc, crc, tmp);
4091 ubfx(tmp, v, 16, 8);
4092 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
4093 eor(crc, crc, tmp);
4094 ubfx(tmp, v, 24, 8);
4095 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
4096 eor(crc, crc, tmp);
4097 }
4098
4099 void MacroAssembler::kernel_crc32_using_crypto_pmull(Register crc, Register buf,
4100 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4101 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4102 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4103
4104 subs(tmp0, len, 384);
4105 mvnw(crc, crc);
4106 br(Assembler::GE, CRC_by128_pre);
4107 BIND(CRC_less128);
4108 subs(len, len, 32);
4109 br(Assembler::GE, CRC_by32_loop);
4110 BIND(CRC_less32);
4111 adds(len, len, 32 - 4);
4112 br(Assembler::GE, CRC_by4_loop);
4113 adds(len, len, 4);
4114 br(Assembler::GT, CRC_by1_loop);
4115 b(L_exit);
4116
4117 BIND(CRC_by32_loop);
4118 ldp(tmp0, tmp1, Address(buf));
4119 crc32x(crc, crc, tmp0);
4120 ldp(tmp2, tmp3, Address(buf, 16));
4121 crc32x(crc, crc, tmp1);
4122 add(buf, buf, 32);
4123 crc32x(crc, crc, tmp2);
4124 subs(len, len, 32);
4125 crc32x(crc, crc, tmp3);
4126 br(Assembler::GE, CRC_by32_loop);
4127 cmn(len, (u1)32);
4128 br(Assembler::NE, CRC_less32);
4129 b(L_exit);
4130
4131 BIND(CRC_by4_loop);
4132 ldrw(tmp0, Address(post(buf, 4)));
4133 subs(len, len, 4);
4134 crc32w(crc, crc, tmp0);
4135 br(Assembler::GE, CRC_by4_loop);
4136 adds(len, len, 4);
4137 br(Assembler::LE, L_exit);
4138 BIND(CRC_by1_loop);
4139 ldrb(tmp0, Address(post(buf, 1)));
4140 subs(len, len, 1);
4141 crc32b(crc, crc, tmp0);
4142 br(Assembler::GT, CRC_by1_loop);
4143 b(L_exit);
4144
4145 BIND(CRC_by128_pre);
4146 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4147 4*256*sizeof(juint) + 8*sizeof(juint));
4148 mov(crc, 0);
4149 crc32x(crc, crc, tmp0);
4150 crc32x(crc, crc, tmp1);
4151
4152 cbnz(len, CRC_less128);
4153
4154 BIND(L_exit);
4155 mvnw(crc, crc);
4156 }
4157
4158 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf,
4159 Register len, Register tmp0, Register tmp1, Register tmp2,
4160 Register tmp3) {
4161 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4162 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4163
4164 mvnw(crc, crc);
4165
4166 subs(len, len, 128);
4167 br(Assembler::GE, CRC_by64_pre);
4168 BIND(CRC_less64);
4169 adds(len, len, 128-32);
4170 br(Assembler::GE, CRC_by32_loop);
4171 BIND(CRC_less32);
4172 adds(len, len, 32-4);
4173 br(Assembler::GE, CRC_by4_loop);
4174 adds(len, len, 4);
4175 br(Assembler::GT, CRC_by1_loop);
4176 b(L_exit);
4177
4178 BIND(CRC_by32_loop);
4179 ldp(tmp0, tmp1, Address(post(buf, 16)));
4180 subs(len, len, 32);
4181 crc32x(crc, crc, tmp0);
4182 ldr(tmp2, Address(post(buf, 8)));
4183 crc32x(crc, crc, tmp1);
4184 ldr(tmp3, Address(post(buf, 8)));
4185 crc32x(crc, crc, tmp2);
4186 crc32x(crc, crc, tmp3);
4187 br(Assembler::GE, CRC_by32_loop);
4188 cmn(len, (u1)32);
4189 br(Assembler::NE, CRC_less32);
4190 b(L_exit);
4191
4192 BIND(CRC_by4_loop);
4193 ldrw(tmp0, Address(post(buf, 4)));
4194 subs(len, len, 4);
4195 crc32w(crc, crc, tmp0);
4196 br(Assembler::GE, CRC_by4_loop);
4197 adds(len, len, 4);
4198 br(Assembler::LE, L_exit);
4199 BIND(CRC_by1_loop);
4200 ldrb(tmp0, Address(post(buf, 1)));
4201 subs(len, len, 1);
4202 crc32b(crc, crc, tmp0);
4203 br(Assembler::GT, CRC_by1_loop);
4204 b(L_exit);
4205
4206 BIND(CRC_by64_pre);
4207 sub(buf, buf, 8);
4208 ldp(tmp0, tmp1, Address(buf, 8));
4209 crc32x(crc, crc, tmp0);
4210 ldr(tmp2, Address(buf, 24));
4211 crc32x(crc, crc, tmp1);
4212 ldr(tmp3, Address(buf, 32));
4213 crc32x(crc, crc, tmp2);
4214 ldr(tmp0, Address(buf, 40));
4215 crc32x(crc, crc, tmp3);
4216 ldr(tmp1, Address(buf, 48));
4217 crc32x(crc, crc, tmp0);
4218 ldr(tmp2, Address(buf, 56));
4219 crc32x(crc, crc, tmp1);
4220 ldr(tmp3, Address(pre(buf, 64)));
4221
4222 b(CRC_by64_loop);
4223
4224 align(CodeEntryAlignment);
4225 BIND(CRC_by64_loop);
4226 subs(len, len, 64);
4227 crc32x(crc, crc, tmp2);
4228 ldr(tmp0, Address(buf, 8));
4229 crc32x(crc, crc, tmp3);
4230 ldr(tmp1, Address(buf, 16));
4231 crc32x(crc, crc, tmp0);
4232 ldr(tmp2, Address(buf, 24));
4233 crc32x(crc, crc, tmp1);
4234 ldr(tmp3, Address(buf, 32));
4235 crc32x(crc, crc, tmp2);
4236 ldr(tmp0, Address(buf, 40));
4237 crc32x(crc, crc, tmp3);
4238 ldr(tmp1, Address(buf, 48));
4239 crc32x(crc, crc, tmp0);
4240 ldr(tmp2, Address(buf, 56));
4241 crc32x(crc, crc, tmp1);
4242 ldr(tmp3, Address(pre(buf, 64)));
4243 br(Assembler::GE, CRC_by64_loop);
4244
4245 // post-loop
4246 crc32x(crc, crc, tmp2);
4247 crc32x(crc, crc, tmp3);
4248
4249 sub(len, len, 64);
4250 add(buf, buf, 8);
4251 cmn(len, (u1)128);
4252 br(Assembler::NE, CRC_less64);
4253 BIND(L_exit);
4254 mvnw(crc, crc);
4255 }
4256
4257 /**
4258 * @param crc register containing existing CRC (32-bit)
4259 * @param buf register pointing to input byte buffer (byte*)
4260 * @param len register containing number of bytes
4261 * @param table register that will contain address of CRC table
4262 * @param tmp scratch register
4263 */
4264 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
4265 Register table0, Register table1, Register table2, Register table3,
4266 Register tmp, Register tmp2, Register tmp3) {
4267 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
4268
4269 if (UseCryptoPmullForCRC32) {
4270 kernel_crc32_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4271 return;
4272 }
4273
4274 if (UseCRC32) {
4275 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
4276 return;
4277 }
4278
4279 mvnw(crc, crc);
4280
4281 {
4282 uint64_t offset;
4283 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4284 add(table0, table0, offset);
4285 }
4286 add(table1, table0, 1*256*sizeof(juint));
4287 add(table2, table0, 2*256*sizeof(juint));
4288 add(table3, table0, 3*256*sizeof(juint));
4289
4290 { // Neon code start
4291 cmp(len, (u1)64);
4292 br(Assembler::LT, L_by16);
4293 eor(v16, T16B, v16, v16);
4294
4295 Label L_fold;
4296
4297 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
4298
4299 ld1(v0, v1, T2D, post(buf, 32));
4300 ld1r(v4, T2D, post(tmp, 8));
4301 ld1r(v5, T2D, post(tmp, 8));
4302 ld1r(v6, T2D, post(tmp, 8));
4303 ld1r(v7, T2D, post(tmp, 8));
4304 mov(v16, S, 0, crc);
4305
4306 eor(v0, T16B, v0, v16);
4307 sub(len, len, 64);
4308
4309 BIND(L_fold);
4310 pmull(v22, T8H, v0, v5, T8B);
4311 pmull(v20, T8H, v0, v7, T8B);
4312 pmull(v23, T8H, v0, v4, T8B);
4313 pmull(v21, T8H, v0, v6, T8B);
4314
4315 pmull2(v18, T8H, v0, v5, T16B);
4316 pmull2(v16, T8H, v0, v7, T16B);
4317 pmull2(v19, T8H, v0, v4, T16B);
4318 pmull2(v17, T8H, v0, v6, T16B);
4319
4320 uzp1(v24, T8H, v20, v22);
4321 uzp2(v25, T8H, v20, v22);
4322 eor(v20, T16B, v24, v25);
4323
4324 uzp1(v26, T8H, v16, v18);
4325 uzp2(v27, T8H, v16, v18);
4326 eor(v16, T16B, v26, v27);
4327
4328 ushll2(v22, T4S, v20, T8H, 8);
4329 ushll(v20, T4S, v20, T4H, 8);
4330
4331 ushll2(v18, T4S, v16, T8H, 8);
4332 ushll(v16, T4S, v16, T4H, 8);
4333
4334 eor(v22, T16B, v23, v22);
4335 eor(v18, T16B, v19, v18);
4336 eor(v20, T16B, v21, v20);
4337 eor(v16, T16B, v17, v16);
4338
4339 uzp1(v17, T2D, v16, v20);
4340 uzp2(v21, T2D, v16, v20);
4341 eor(v17, T16B, v17, v21);
4342
4343 ushll2(v20, T2D, v17, T4S, 16);
4344 ushll(v16, T2D, v17, T2S, 16);
4345
4346 eor(v20, T16B, v20, v22);
4347 eor(v16, T16B, v16, v18);
4348
4349 uzp1(v17, T2D, v20, v16);
4350 uzp2(v21, T2D, v20, v16);
4351 eor(v28, T16B, v17, v21);
4352
4353 pmull(v22, T8H, v1, v5, T8B);
4354 pmull(v20, T8H, v1, v7, T8B);
4355 pmull(v23, T8H, v1, v4, T8B);
4356 pmull(v21, T8H, v1, v6, T8B);
4357
4358 pmull2(v18, T8H, v1, v5, T16B);
4359 pmull2(v16, T8H, v1, v7, T16B);
4360 pmull2(v19, T8H, v1, v4, T16B);
4361 pmull2(v17, T8H, v1, v6, T16B);
4362
4363 ld1(v0, v1, T2D, post(buf, 32));
4364
4365 uzp1(v24, T8H, v20, v22);
4366 uzp2(v25, T8H, v20, v22);
4367 eor(v20, T16B, v24, v25);
4368
4369 uzp1(v26, T8H, v16, v18);
4370 uzp2(v27, T8H, v16, v18);
4371 eor(v16, T16B, v26, v27);
4372
4373 ushll2(v22, T4S, v20, T8H, 8);
4374 ushll(v20, T4S, v20, T4H, 8);
4375
4376 ushll2(v18, T4S, v16, T8H, 8);
4377 ushll(v16, T4S, v16, T4H, 8);
4378
4379 eor(v22, T16B, v23, v22);
4380 eor(v18, T16B, v19, v18);
4381 eor(v20, T16B, v21, v20);
4382 eor(v16, T16B, v17, v16);
4383
4384 uzp1(v17, T2D, v16, v20);
4385 uzp2(v21, T2D, v16, v20);
4386 eor(v16, T16B, v17, v21);
4387
4388 ushll2(v20, T2D, v16, T4S, 16);
4389 ushll(v16, T2D, v16, T2S, 16);
4390
4391 eor(v20, T16B, v22, v20);
4392 eor(v16, T16B, v16, v18);
4393
4394 uzp1(v17, T2D, v20, v16);
4395 uzp2(v21, T2D, v20, v16);
4396 eor(v20, T16B, v17, v21);
4397
4398 shl(v16, T2D, v28, 1);
4399 shl(v17, T2D, v20, 1);
4400
4401 eor(v0, T16B, v0, v16);
4402 eor(v1, T16B, v1, v17);
4403
4404 subs(len, len, 32);
4405 br(Assembler::GE, L_fold);
4406
4407 mov(crc, 0);
4408 mov(tmp, v0, D, 0);
4409 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4410 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4411 mov(tmp, v0, D, 1);
4412 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4413 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4414 mov(tmp, v1, D, 0);
4415 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4416 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4417 mov(tmp, v1, D, 1);
4418 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4419 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4420
4421 add(len, len, 32);
4422 } // Neon code end
4423
4424 BIND(L_by16);
4425 subs(len, len, 16);
4426 br(Assembler::GE, L_by16_loop);
4427 adds(len, len, 16-4);
4428 br(Assembler::GE, L_by4_loop);
4429 adds(len, len, 4);
4430 br(Assembler::GT, L_by1_loop);
4431 b(L_exit);
4432
4433 BIND(L_by4_loop);
4434 ldrw(tmp, Address(post(buf, 4)));
4435 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
4436 subs(len, len, 4);
4437 br(Assembler::GE, L_by4_loop);
4438 adds(len, len, 4);
4439 br(Assembler::LE, L_exit);
4440 BIND(L_by1_loop);
4441 subs(len, len, 1);
4442 ldrb(tmp, Address(post(buf, 1)));
4443 update_byte_crc32(crc, tmp, table0);
4444 br(Assembler::GT, L_by1_loop);
4445 b(L_exit);
4446
4447 align(CodeEntryAlignment);
4448 BIND(L_by16_loop);
4449 subs(len, len, 16);
4450 ldp(tmp, tmp3, Address(post(buf, 16)));
4451 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4452 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4453 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
4454 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
4455 br(Assembler::GE, L_by16_loop);
4456 adds(len, len, 16-4);
4457 br(Assembler::GE, L_by4_loop);
4458 adds(len, len, 4);
4459 br(Assembler::GT, L_by1_loop);
4460 BIND(L_exit);
4461 mvnw(crc, crc);
4462 }
4463
4464 void MacroAssembler::kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
4465 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4466 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4467 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4468
4469 subs(tmp0, len, 384);
4470 br(Assembler::GE, CRC_by128_pre);
4471 BIND(CRC_less128);
4472 subs(len, len, 32);
4473 br(Assembler::GE, CRC_by32_loop);
4474 BIND(CRC_less32);
4475 adds(len, len, 32 - 4);
4476 br(Assembler::GE, CRC_by4_loop);
4477 adds(len, len, 4);
4478 br(Assembler::GT, CRC_by1_loop);
4479 b(L_exit);
4480
4481 BIND(CRC_by32_loop);
4482 ldp(tmp0, tmp1, Address(buf));
4483 crc32cx(crc, crc, tmp0);
4484 ldr(tmp2, Address(buf, 16));
4485 crc32cx(crc, crc, tmp1);
4486 ldr(tmp3, Address(buf, 24));
4487 crc32cx(crc, crc, tmp2);
4488 add(buf, buf, 32);
4489 subs(len, len, 32);
4490 crc32cx(crc, crc, tmp3);
4491 br(Assembler::GE, CRC_by32_loop);
4492 cmn(len, (u1)32);
4493 br(Assembler::NE, CRC_less32);
4494 b(L_exit);
4495
4496 BIND(CRC_by4_loop);
4497 ldrw(tmp0, Address(post(buf, 4)));
4498 subs(len, len, 4);
4499 crc32cw(crc, crc, tmp0);
4500 br(Assembler::GE, CRC_by4_loop);
4501 adds(len, len, 4);
4502 br(Assembler::LE, L_exit);
4503 BIND(CRC_by1_loop);
4504 ldrb(tmp0, Address(post(buf, 1)));
4505 subs(len, len, 1);
4506 crc32cb(crc, crc, tmp0);
4507 br(Assembler::GT, CRC_by1_loop);
4508 b(L_exit);
4509
4510 BIND(CRC_by128_pre);
4511 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4512 4*256*sizeof(juint) + 8*sizeof(juint) + 0x50);
4513 mov(crc, 0);
4514 crc32cx(crc, crc, tmp0);
4515 crc32cx(crc, crc, tmp1);
4516
4517 cbnz(len, CRC_less128);
4518
4519 BIND(L_exit);
4520 }
4521
4522 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf,
4523 Register len, Register tmp0, Register tmp1, Register tmp2,
4524 Register tmp3) {
4525 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4526 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4527
4528 subs(len, len, 128);
4529 br(Assembler::GE, CRC_by64_pre);
4530 BIND(CRC_less64);
4531 adds(len, len, 128-32);
4532 br(Assembler::GE, CRC_by32_loop);
4533 BIND(CRC_less32);
4534 adds(len, len, 32-4);
4535 br(Assembler::GE, CRC_by4_loop);
4536 adds(len, len, 4);
4537 br(Assembler::GT, CRC_by1_loop);
4538 b(L_exit);
4539
4540 BIND(CRC_by32_loop);
4541 ldp(tmp0, tmp1, Address(post(buf, 16)));
4542 subs(len, len, 32);
4543 crc32cx(crc, crc, tmp0);
4544 ldr(tmp2, Address(post(buf, 8)));
4545 crc32cx(crc, crc, tmp1);
4546 ldr(tmp3, Address(post(buf, 8)));
4547 crc32cx(crc, crc, tmp2);
4548 crc32cx(crc, crc, tmp3);
4549 br(Assembler::GE, CRC_by32_loop);
4550 cmn(len, (u1)32);
4551 br(Assembler::NE, CRC_less32);
4552 b(L_exit);
4553
4554 BIND(CRC_by4_loop);
4555 ldrw(tmp0, Address(post(buf, 4)));
4556 subs(len, len, 4);
4557 crc32cw(crc, crc, tmp0);
4558 br(Assembler::GE, CRC_by4_loop);
4559 adds(len, len, 4);
4560 br(Assembler::LE, L_exit);
4561 BIND(CRC_by1_loop);
4562 ldrb(tmp0, Address(post(buf, 1)));
4563 subs(len, len, 1);
4564 crc32cb(crc, crc, tmp0);
4565 br(Assembler::GT, CRC_by1_loop);
4566 b(L_exit);
4567
4568 BIND(CRC_by64_pre);
4569 sub(buf, buf, 8);
4570 ldp(tmp0, tmp1, Address(buf, 8));
4571 crc32cx(crc, crc, tmp0);
4572 ldr(tmp2, Address(buf, 24));
4573 crc32cx(crc, crc, tmp1);
4574 ldr(tmp3, Address(buf, 32));
4575 crc32cx(crc, crc, tmp2);
4576 ldr(tmp0, Address(buf, 40));
4577 crc32cx(crc, crc, tmp3);
4578 ldr(tmp1, Address(buf, 48));
4579 crc32cx(crc, crc, tmp0);
4580 ldr(tmp2, Address(buf, 56));
4581 crc32cx(crc, crc, tmp1);
4582 ldr(tmp3, Address(pre(buf, 64)));
4583
4584 b(CRC_by64_loop);
4585
4586 align(CodeEntryAlignment);
4587 BIND(CRC_by64_loop);
4588 subs(len, len, 64);
4589 crc32cx(crc, crc, tmp2);
4590 ldr(tmp0, Address(buf, 8));
4591 crc32cx(crc, crc, tmp3);
4592 ldr(tmp1, Address(buf, 16));
4593 crc32cx(crc, crc, tmp0);
4594 ldr(tmp2, Address(buf, 24));
4595 crc32cx(crc, crc, tmp1);
4596 ldr(tmp3, Address(buf, 32));
4597 crc32cx(crc, crc, tmp2);
4598 ldr(tmp0, Address(buf, 40));
4599 crc32cx(crc, crc, tmp3);
4600 ldr(tmp1, Address(buf, 48));
4601 crc32cx(crc, crc, tmp0);
4602 ldr(tmp2, Address(buf, 56));
4603 crc32cx(crc, crc, tmp1);
4604 ldr(tmp3, Address(pre(buf, 64)));
4605 br(Assembler::GE, CRC_by64_loop);
4606
4607 // post-loop
4608 crc32cx(crc, crc, tmp2);
4609 crc32cx(crc, crc, tmp3);
4610
4611 sub(len, len, 64);
4612 add(buf, buf, 8);
4613 cmn(len, (u1)128);
4614 br(Assembler::NE, CRC_less64);
4615 BIND(L_exit);
4616 }
4617
4618 /**
4619 * @param crc register containing existing CRC (32-bit)
4620 * @param buf register pointing to input byte buffer (byte*)
4621 * @param len register containing number of bytes
4622 * @param table register that will contain address of CRC table
4623 * @param tmp scratch register
4624 */
4625 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
4626 Register table0, Register table1, Register table2, Register table3,
4627 Register tmp, Register tmp2, Register tmp3) {
4628 if (UseCryptoPmullForCRC32) {
4629 kernel_crc32c_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4630 } else {
4631 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3);
4632 }
4633 }
4634
4635 void MacroAssembler::kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
4636 Register len, Register tmp0, Register tmp1, Register tmp2, size_t table_offset) {
4637 Label CRC_by128_loop;
4638 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4639
4640 sub(len, len, 256);
4641 Register table = tmp0;
4642 {
4643 uint64_t offset;
4644 adrp(table, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4645 add(table, table, offset);
4646 }
4647 add(table, table, table_offset);
4648
4649 // Registers v0..v7 are used as data registers.
4650 // Registers v16..v31 are used as tmp registers.
4651 sub(buf, buf, 0x10);
4652 ldrq(v0, Address(buf, 0x10));
4653 ldrq(v1, Address(buf, 0x20));
4654 ldrq(v2, Address(buf, 0x30));
4655 ldrq(v3, Address(buf, 0x40));
4656 ldrq(v4, Address(buf, 0x50));
4657 ldrq(v5, Address(buf, 0x60));
4658 ldrq(v6, Address(buf, 0x70));
4659 ldrq(v7, Address(pre(buf, 0x80)));
4660
4661 movi(v31, T4S, 0);
4662 mov(v31, S, 0, crc);
4663 eor(v0, T16B, v0, v31);
4664
4665 // Register v16 contains constants from the crc table.
4666 ldrq(v16, Address(table));
4667 b(CRC_by128_loop);
4668
4669 align(OptoLoopAlignment);
4670 BIND(CRC_by128_loop);
4671 pmull (v17, T1Q, v0, v16, T1D);
4672 pmull2(v18, T1Q, v0, v16, T2D);
4673 ldrq(v0, Address(buf, 0x10));
4674 eor3(v0, T16B, v17, v18, v0);
4675
4676 pmull (v19, T1Q, v1, v16, T1D);
4677 pmull2(v20, T1Q, v1, v16, T2D);
4678 ldrq(v1, Address(buf, 0x20));
4679 eor3(v1, T16B, v19, v20, v1);
4680
4681 pmull (v21, T1Q, v2, v16, T1D);
4682 pmull2(v22, T1Q, v2, v16, T2D);
4683 ldrq(v2, Address(buf, 0x30));
4684 eor3(v2, T16B, v21, v22, v2);
4685
4686 pmull (v23, T1Q, v3, v16, T1D);
4687 pmull2(v24, T1Q, v3, v16, T2D);
4688 ldrq(v3, Address(buf, 0x40));
4689 eor3(v3, T16B, v23, v24, v3);
4690
4691 pmull (v25, T1Q, v4, v16, T1D);
4692 pmull2(v26, T1Q, v4, v16, T2D);
4693 ldrq(v4, Address(buf, 0x50));
4694 eor3(v4, T16B, v25, v26, v4);
4695
4696 pmull (v27, T1Q, v5, v16, T1D);
4697 pmull2(v28, T1Q, v5, v16, T2D);
4698 ldrq(v5, Address(buf, 0x60));
4699 eor3(v5, T16B, v27, v28, v5);
4700
4701 pmull (v29, T1Q, v6, v16, T1D);
4702 pmull2(v30, T1Q, v6, v16, T2D);
4703 ldrq(v6, Address(buf, 0x70));
4704 eor3(v6, T16B, v29, v30, v6);
4705
4706 // Reuse registers v23, v24.
4707 // Using them won't block the first instruction of the next iteration.
4708 pmull (v23, T1Q, v7, v16, T1D);
4709 pmull2(v24, T1Q, v7, v16, T2D);
4710 ldrq(v7, Address(pre(buf, 0x80)));
4711 eor3(v7, T16B, v23, v24, v7);
4712
4713 subs(len, len, 0x80);
4714 br(Assembler::GE, CRC_by128_loop);
4715
4716 // fold into 512 bits
4717 // Use v31 for constants because v16 can be still in use.
4718 ldrq(v31, Address(table, 0x10));
4719
4720 pmull (v17, T1Q, v0, v31, T1D);
4721 pmull2(v18, T1Q, v0, v31, T2D);
4722 eor3(v0, T16B, v17, v18, v4);
4723
4724 pmull (v19, T1Q, v1, v31, T1D);
4725 pmull2(v20, T1Q, v1, v31, T2D);
4726 eor3(v1, T16B, v19, v20, v5);
4727
4728 pmull (v21, T1Q, v2, v31, T1D);
4729 pmull2(v22, T1Q, v2, v31, T2D);
4730 eor3(v2, T16B, v21, v22, v6);
4731
4732 pmull (v23, T1Q, v3, v31, T1D);
4733 pmull2(v24, T1Q, v3, v31, T2D);
4734 eor3(v3, T16B, v23, v24, v7);
4735
4736 // fold into 128 bits
4737 // Use v17 for constants because v31 can be still in use.
4738 ldrq(v17, Address(table, 0x20));
4739 pmull (v25, T1Q, v0, v17, T1D);
4740 pmull2(v26, T1Q, v0, v17, T2D);
4741 eor3(v3, T16B, v3, v25, v26);
4742
4743 // Use v18 for constants because v17 can be still in use.
4744 ldrq(v18, Address(table, 0x30));
4745 pmull (v27, T1Q, v1, v18, T1D);
4746 pmull2(v28, T1Q, v1, v18, T2D);
4747 eor3(v3, T16B, v3, v27, v28);
4748
4749 // Use v19 for constants because v18 can be still in use.
4750 ldrq(v19, Address(table, 0x40));
4751 pmull (v29, T1Q, v2, v19, T1D);
4752 pmull2(v30, T1Q, v2, v19, T2D);
4753 eor3(v0, T16B, v3, v29, v30);
4754
4755 add(len, len, 0x80);
4756 add(buf, buf, 0x10);
4757
4758 mov(tmp0, v0, D, 0);
4759 mov(tmp1, v0, D, 1);
4760 }
4761
4762 SkipIfEqual::SkipIfEqual(
4763 MacroAssembler* masm, const bool* flag_addr, bool value) {
4764 _masm = masm;
4765 uint64_t offset;
4766 _masm->adrp(rscratch1, ExternalAddress((address)flag_addr), offset);
4767 _masm->ldrb(rscratch1, Address(rscratch1, offset));
4768 if (value) {
4769 _masm->cbnzw(rscratch1, _label);
4770 } else {
4771 _masm->cbzw(rscratch1, _label);
4772 }
4773 }
4774
4775 SkipIfEqual::~SkipIfEqual() {
4776 _masm->bind(_label);
4777 }
4778
4779 void MacroAssembler::addptr(const Address &dst, int32_t src) {
4780 Address adr;
4781 switch(dst.getMode()) {
4782 case Address::base_plus_offset:
4783 // This is the expected mode, although we allow all the other
4784 // forms below.
4785 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
4786 break;
4787 default:
4788 lea(rscratch2, dst);
4789 adr = Address(rscratch2);
4790 break;
4791 }
4792 ldr(rscratch1, adr);
4793 add(rscratch1, rscratch1, src);
4794 str(rscratch1, adr);
4795 }
4796
4797 void MacroAssembler::cmpptr(Register src1, Address src2) {
4798 uint64_t offset;
4799 adrp(rscratch1, src2, offset);
4800 ldr(rscratch1, Address(rscratch1, offset));
4801 cmp(src1, rscratch1);
4802 }
4803
4804 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
4805 cmp(obj1, obj2);
4806 }
4807
4808 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4809 load_method_holder(rresult, rmethod);
4810 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4811 }
4812
4813 void MacroAssembler::load_method_holder(Register holder, Register method) {
4814 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
4815 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
4816 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
4817 }
4818
4819 void MacroAssembler::load_klass(Register dst, Register src) {
4820 if (UseCompressedClassPointers) {
4821 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4822 decode_klass_not_null(dst);
4823 } else {
4824 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4825 }
4826 }
4827
4828 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
4829 if (RestoreMXCSROnJNICalls) {
4830 Label OK;
4831 get_fpcr(tmp1);
4832 mov(tmp2, tmp1);
4833 // Set FPCR to the state we need. We do want Round to Nearest. We
4834 // don't want non-IEEE rounding modes or floating-point traps.
4835 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
4836 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
4837 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
4838 eor(tmp2, tmp1, tmp2);
4839 cbz(tmp2, OK); // Only reset FPCR if it's wrong
4840 set_fpcr(tmp1);
4841 bind(OK);
4842 }
4843 }
4844
4845 // ((OopHandle)result).resolve();
4846 void MacroAssembler::resolve_oop_handle(Register result, Register tmp1, Register tmp2) {
4847 // OopHandle::resolve is an indirection.
4848 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp1, tmp2);
4849 }
4850
4851 // ((WeakHandle)result).resolve();
4852 void MacroAssembler::resolve_weak_handle(Register result, Register tmp1, Register tmp2) {
4853 assert_different_registers(result, tmp1, tmp2);
4854 Label resolved;
4855
4856 // A null weak handle resolves to null.
4857 cbz(result, resolved);
4858
4859 // Only 64 bit platforms support GCs that require a tmp register
4860 // WeakHandle::resolve is an indirection like jweak.
4861 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4862 result, Address(result), tmp1, tmp2);
4863 bind(resolved);
4864 }
4865
4866 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp1, Register tmp2) {
4867 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
4868 ldr(dst, Address(rmethod, Method::const_offset()));
4869 ldr(dst, Address(dst, ConstMethod::constants_offset()));
4870 ldr(dst, Address(dst, ConstantPool::pool_holder_offset()));
4871 ldr(dst, Address(dst, mirror_offset));
4872 resolve_oop_handle(dst, tmp1, tmp2);
4873 }
4874
4875 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
4876 if (UseCompressedClassPointers) {
4877 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
4878 if (CompressedKlassPointers::base() == nullptr) {
4879 cmp(trial_klass, tmp, LSL, CompressedKlassPointers::shift());
4880 return;
4881 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
4882 && CompressedKlassPointers::shift() == 0) {
4883 // Only the bottom 32 bits matter
4884 cmpw(trial_klass, tmp);
4885 return;
4886 }
4887 decode_klass_not_null(tmp);
4888 } else {
4889 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
4890 }
4891 cmp(trial_klass, tmp);
4892 }
4893
4894 void MacroAssembler::store_klass(Register dst, Register src) {
4895 // FIXME: Should this be a store release? concurrent gcs assumes
4896 // klass length is valid if klass field is not null.
4897 if (UseCompressedClassPointers) {
4898 encode_klass_not_null(src);
4899 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
4900 } else {
4901 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
4902 }
4903 }
4904
4905 void MacroAssembler::store_klass_gap(Register dst, Register src) {
4906 if (UseCompressedClassPointers) {
4907 // Store to klass gap in destination
4908 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
4909 }
4910 }
4911
4912 // Algorithm must match CompressedOops::encode.
4913 void MacroAssembler::encode_heap_oop(Register d, Register s) {
4914 #ifdef ASSERT
4915 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
4916 #endif
4917 verify_oop_msg(s, "broken oop in encode_heap_oop");
4918 if (CompressedOops::base() == nullptr) {
4919 if (CompressedOops::shift() != 0) {
4920 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4921 lsr(d, s, LogMinObjAlignmentInBytes);
4922 } else {
4923 mov(d, s);
4924 }
4925 } else {
4926 subs(d, s, rheapbase);
4927 csel(d, d, zr, Assembler::HS);
4928 lsr(d, d, LogMinObjAlignmentInBytes);
4929
4930 /* Old algorithm: is this any worse?
4931 Label nonnull;
4932 cbnz(r, nonnull);
4933 sub(r, r, rheapbase);
4934 bind(nonnull);
4935 lsr(r, r, LogMinObjAlignmentInBytes);
4936 */
4937 }
4938 }
4939
4940 void MacroAssembler::encode_heap_oop_not_null(Register r) {
4941 #ifdef ASSERT
4942 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
4943 if (CheckCompressedOops) {
4944 Label ok;
4945 cbnz(r, ok);
4946 stop("null oop passed to encode_heap_oop_not_null");
4947 bind(ok);
4948 }
4949 #endif
4950 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
4951 if (CompressedOops::base() != nullptr) {
4952 sub(r, r, rheapbase);
4953 }
4954 if (CompressedOops::shift() != 0) {
4955 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4956 lsr(r, r, LogMinObjAlignmentInBytes);
4957 }
4958 }
4959
4960 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
4961 #ifdef ASSERT
4962 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
4963 if (CheckCompressedOops) {
4964 Label ok;
4965 cbnz(src, ok);
4966 stop("null oop passed to encode_heap_oop_not_null2");
4967 bind(ok);
4968 }
4969 #endif
4970 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
4971
4972 Register data = src;
4973 if (CompressedOops::base() != nullptr) {
4974 sub(dst, src, rheapbase);
4975 data = dst;
4976 }
4977 if (CompressedOops::shift() != 0) {
4978 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4979 lsr(dst, data, LogMinObjAlignmentInBytes);
4980 data = dst;
4981 }
4982 if (data == src)
4983 mov(dst, src);
4984 }
4985
4986 void MacroAssembler::decode_heap_oop(Register d, Register s) {
4987 #ifdef ASSERT
4988 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
4989 #endif
4990 if (CompressedOops::base() == nullptr) {
4991 if (CompressedOops::shift() != 0 || d != s) {
4992 lsl(d, s, CompressedOops::shift());
4993 }
4994 } else {
4995 Label done;
4996 if (d != s)
4997 mov(d, s);
4998 cbz(s, done);
4999 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
5000 bind(done);
5001 }
5002 verify_oop_msg(d, "broken oop in decode_heap_oop");
5003 }
5004
5005 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5006 assert (UseCompressedOops, "should only be used for compressed headers");
5007 assert (Universe::heap() != nullptr, "java heap should be initialized");
5008 // Cannot assert, unverified entry point counts instructions (see .ad file)
5009 // vtableStubs also counts instructions in pd_code_size_limit.
5010 // Also do not verify_oop as this is called by verify_oop.
5011 if (CompressedOops::shift() != 0) {
5012 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5013 if (CompressedOops::base() != nullptr) {
5014 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5015 } else {
5016 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5017 }
5018 } else {
5019 assert (CompressedOops::base() == nullptr, "sanity");
5020 }
5021 }
5022
5023 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5024 assert (UseCompressedOops, "should only be used for compressed headers");
5025 assert (Universe::heap() != nullptr, "java heap should be initialized");
5026 // Cannot assert, unverified entry point counts instructions (see .ad file)
5027 // vtableStubs also counts instructions in pd_code_size_limit.
5028 // Also do not verify_oop as this is called by verify_oop.
5029 if (CompressedOops::shift() != 0) {
5030 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5031 if (CompressedOops::base() != nullptr) {
5032 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5033 } else {
5034 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5035 }
5036 } else {
5037 assert (CompressedOops::base() == nullptr, "sanity");
5038 if (dst != src) {
5039 mov(dst, src);
5040 }
5041 }
5042 }
5043
5044 MacroAssembler::KlassDecodeMode MacroAssembler::_klass_decode_mode(KlassDecodeNone);
5045
5046 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() {
5047 assert(UseCompressedClassPointers, "not using compressed class pointers");
5048 assert(Metaspace::initialized(), "metaspace not initialized yet");
5049
5050 if (_klass_decode_mode != KlassDecodeNone) {
5051 return _klass_decode_mode;
5052 }
5053
5054 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift()
5055 || 0 == CompressedKlassPointers::shift(), "decode alg wrong");
5056
5057 if (CompressedKlassPointers::base() == nullptr) {
5058 return (_klass_decode_mode = KlassDecodeZero);
5059 }
5060
5061 if (operand_valid_for_logical_immediate(
5062 /*is32*/false, (uint64_t)CompressedKlassPointers::base())) {
5063 const uint64_t range_mask =
5064 (1ULL << log2i(CompressedKlassPointers::range())) - 1;
5065 if (((uint64_t)CompressedKlassPointers::base() & range_mask) == 0) {
5066 return (_klass_decode_mode = KlassDecodeXor);
5067 }
5068 }
5069
5070 const uint64_t shifted_base =
5071 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5072 guarantee((shifted_base & 0xffff0000ffffffff) == 0,
5073 "compressed class base bad alignment");
5074
5075 return (_klass_decode_mode = KlassDecodeMovk);
5076 }
5077
5078 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5079 switch (klass_decode_mode()) {
5080 case KlassDecodeZero:
5081 if (CompressedKlassPointers::shift() != 0) {
5082 lsr(dst, src, LogKlassAlignmentInBytes);
5083 } else {
5084 if (dst != src) mov(dst, src);
5085 }
5086 break;
5087
5088 case KlassDecodeXor:
5089 if (CompressedKlassPointers::shift() != 0) {
5090 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5091 lsr(dst, dst, LogKlassAlignmentInBytes);
5092 } else {
5093 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5094 }
5095 break;
5096
5097 case KlassDecodeMovk:
5098 if (CompressedKlassPointers::shift() != 0) {
5099 ubfx(dst, src, LogKlassAlignmentInBytes, 32);
5100 } else {
5101 movw(dst, src);
5102 }
5103 break;
5104
5105 case KlassDecodeNone:
5106 ShouldNotReachHere();
5107 break;
5108 }
5109 }
5110
5111 void MacroAssembler::encode_klass_not_null(Register r) {
5112 encode_klass_not_null(r, r);
5113 }
5114
5115 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5116 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5117
5118 switch (klass_decode_mode()) {
5119 case KlassDecodeZero:
5120 if (CompressedKlassPointers::shift() != 0) {
5121 lsl(dst, src, LogKlassAlignmentInBytes);
5122 } else {
5123 if (dst != src) mov(dst, src);
5124 }
5125 break;
5126
5127 case KlassDecodeXor:
5128 if (CompressedKlassPointers::shift() != 0) {
5129 lsl(dst, src, LogKlassAlignmentInBytes);
5130 eor(dst, dst, (uint64_t)CompressedKlassPointers::base());
5131 } else {
5132 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5133 }
5134 break;
5135
5136 case KlassDecodeMovk: {
5137 const uint64_t shifted_base =
5138 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5139
5140 if (dst != src) movw(dst, src);
5141 movk(dst, shifted_base >> 32, 32);
5142
5143 if (CompressedKlassPointers::shift() != 0) {
5144 lsl(dst, dst, LogKlassAlignmentInBytes);
5145 }
5146
5147 break;
5148 }
5149
5150 case KlassDecodeNone:
5151 ShouldNotReachHere();
5152 break;
5153 }
5154 }
5155
5156 void MacroAssembler::decode_klass_not_null(Register r) {
5157 decode_klass_not_null(r, r);
5158 }
5159
5160 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5161 #ifdef ASSERT
5162 {
5163 ThreadInVMfromUnknown tiv;
5164 assert (UseCompressedOops, "should only be used for compressed oops");
5165 assert (Universe::heap() != nullptr, "java heap should be initialized");
5166 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5167 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5168 }
5169 #endif
5170 int oop_index = oop_recorder()->find_index(obj);
5171 InstructionMark im(this);
5172 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5173 code_section()->relocate(inst_mark(), rspec);
5174 movz(dst, 0xDEAD, 16);
5175 movk(dst, 0xBEEF);
5176 }
5177
5178 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5179 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5180 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5181 int index = oop_recorder()->find_index(k);
5182 assert(! Universe::heap()->is_in(k), "should not be an oop");
5183
5184 InstructionMark im(this);
5185 RelocationHolder rspec = metadata_Relocation::spec(index);
5186 code_section()->relocate(inst_mark(), rspec);
5187 narrowKlass nk = CompressedKlassPointers::encode(k);
5188 movz(dst, (nk >> 16), 16);
5189 movk(dst, nk & 0xffff);
5190 }
5191
5192 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
5193 Register dst, Address src,
5194 Register tmp1, Register tmp2) {
5195 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5196 decorators = AccessInternal::decorator_fixup(decorators, type);
5197 bool as_raw = (decorators & AS_RAW) != 0;
5198 if (as_raw) {
5199 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5200 } else {
5201 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5202 }
5203 }
5204
5205 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5206 Address dst, Register val,
5207 Register tmp1, Register tmp2, Register tmp3) {
5208 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5209 decorators = AccessInternal::decorator_fixup(decorators, type);
5210 bool as_raw = (decorators & AS_RAW) != 0;
5211 if (as_raw) {
5212 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5213 } else {
5214 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5215 }
5216 }
5217
5218 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5219 Register tmp2, DecoratorSet decorators) {
5220 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5221 }
5222
5223 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5224 Register tmp2, DecoratorSet decorators) {
5225 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5226 }
5227
5228 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5229 Register tmp2, Register tmp3, DecoratorSet decorators) {
5230 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5231 }
5232
5233 // Used for storing nulls.
5234 void MacroAssembler::store_heap_oop_null(Address dst) {
5235 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5236 }
5237
5238 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
5239 assert(oop_recorder() != nullptr, "this assembler needs a Recorder");
5240 int index = oop_recorder()->allocate_metadata_index(obj);
5241 RelocationHolder rspec = metadata_Relocation::spec(index);
5242 return Address((address)obj, rspec);
5243 }
5244
5245 // Move an oop into a register.
5246 void MacroAssembler::movoop(Register dst, jobject obj) {
5247 int oop_index;
5248 if (obj == nullptr) {
5249 oop_index = oop_recorder()->allocate_oop_index(obj);
5250 } else {
5251 #ifdef ASSERT
5252 {
5253 ThreadInVMfromUnknown tiv;
5254 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5255 }
5256 #endif
5257 oop_index = oop_recorder()->find_index(obj);
5258 }
5259 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5260
5261 if (BarrierSet::barrier_set()->barrier_set_assembler()->supports_instruction_patching()) {
5262 mov(dst, Address((address)obj, rspec));
5263 } else {
5264 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
5265 ldr_constant(dst, Address(dummy, rspec));
5266 }
5267
5268 }
5269
5270 // Move a metadata address into a register.
5271 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
5272 int oop_index;
5273 if (obj == nullptr) {
5274 oop_index = oop_recorder()->allocate_metadata_index(obj);
5275 } else {
5276 oop_index = oop_recorder()->find_index(obj);
5277 }
5278 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5279 mov(dst, Address((address)obj, rspec));
5280 }
5281
5282 Address MacroAssembler::constant_oop_address(jobject obj) {
5283 #ifdef ASSERT
5284 {
5285 ThreadInVMfromUnknown tiv;
5286 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5287 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5288 }
5289 #endif
5290 int oop_index = oop_recorder()->find_index(obj);
5291 return Address((address)obj, oop_Relocation::spec(oop_index));
5292 }
5293
5294 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5295 void MacroAssembler::tlab_allocate(Register obj,
5296 Register var_size_in_bytes,
5297 int con_size_in_bytes,
5298 Register t1,
5299 Register t2,
5300 Label& slow_case) {
5301 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5302 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5303 }
5304
5305 void MacroAssembler::verify_tlab() {
5306 #ifdef ASSERT
5307 if (UseTLAB && VerifyOops) {
5308 Label next, ok;
5309
5310 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5311
5312 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5313 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5314 cmp(rscratch2, rscratch1);
5315 br(Assembler::HS, next);
5316 STOP("assert(top >= start)");
5317 should_not_reach_here();
5318
5319 bind(next);
5320 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5321 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5322 cmp(rscratch2, rscratch1);
5323 br(Assembler::HS, ok);
5324 STOP("assert(top <= end)");
5325 should_not_reach_here();
5326
5327 bind(ok);
5328 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5329 }
5330 #endif
5331 }
5332
5333 // Writes to stack successive pages until offset reached to check for
5334 // stack overflow + shadow pages. This clobbers tmp.
5335 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5336 assert_different_registers(tmp, size, rscratch1);
5337 mov(tmp, sp);
5338 // Bang stack for total size given plus shadow page size.
5339 // Bang one page at a time because large size can bang beyond yellow and
5340 // red zones.
5341 Label loop;
5342 mov(rscratch1, (int)os::vm_page_size());
5343 bind(loop);
5344 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5345 subsw(size, size, rscratch1);
5346 str(size, Address(tmp));
5347 br(Assembler::GT, loop);
5348
5349 // Bang down shadow pages too.
5350 // At this point, (tmp-0) is the last address touched, so don't
5351 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5352 // was post-decremented.) Skip this address by starting at i=1, and
5353 // touch a few more pages below. N.B. It is important to touch all
5354 // the way down to and including i=StackShadowPages.
5355 for (int i = 0; i < (int)(StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()) - 1; i++) {
5356 // this could be any sized move but this is can be a debugging crumb
5357 // so the bigger the better.
5358 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5359 str(size, Address(tmp));
5360 }
5361 }
5362
5363 // Move the address of the polling page into dest.
5364 void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype) {
5365 ldr(dest, Address(rthread, JavaThread::polling_page_offset()));
5366 }
5367
5368 // Read the polling page. The address of the polling page must
5369 // already be in r.
5370 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
5371 address mark;
5372 {
5373 InstructionMark im(this);
5374 code_section()->relocate(inst_mark(), rtype);
5375 ldrw(zr, Address(r, 0));
5376 mark = inst_mark();
5377 }
5378 verify_cross_modify_fence_not_required();
5379 return mark;
5380 }
5381
5382 void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
5383 relocInfo::relocType rtype = dest.rspec().reloc()->type();
5384 uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12;
5385 uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12;
5386 uint64_t dest_page = (uint64_t)dest.target() >> 12;
5387 int64_t offset_low = dest_page - low_page;
5388 int64_t offset_high = dest_page - high_page;
5389
5390 assert(is_valid_AArch64_address(dest.target()), "bad address");
5391 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
5392
5393 InstructionMark im(this);
5394 code_section()->relocate(inst_mark(), dest.rspec());
5395 // 8143067: Ensure that the adrp can reach the dest from anywhere within
5396 // the code cache so that if it is relocated we know it will still reach
5397 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
5398 _adrp(reg1, dest.target());
5399 } else {
5400 uint64_t target = (uint64_t)dest.target();
5401 uint64_t adrp_target
5402 = (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL);
5403
5404 _adrp(reg1, (address)adrp_target);
5405 movk(reg1, target >> 32, 32);
5406 }
5407 byte_offset = (uint64_t)dest.target() & 0xfff;
5408 }
5409
5410 void MacroAssembler::load_byte_map_base(Register reg) {
5411 CardTable::CardValue* byte_map_base =
5412 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base();
5413
5414 // Strictly speaking the byte_map_base isn't an address at all, and it might
5415 // even be negative. It is thus materialised as a constant.
5416 mov(reg, (uint64_t)byte_map_base);
5417 }
5418
5419 void MacroAssembler::build_frame(int framesize) {
5420 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5421 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5422 protect_return_address();
5423 if (framesize < ((1 << 9) + 2 * wordSize)) {
5424 sub(sp, sp, framesize);
5425 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5426 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
5427 } else {
5428 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
5429 if (PreserveFramePointer) mov(rfp, sp);
5430 if (framesize < ((1 << 12) + 2 * wordSize))
5431 sub(sp, sp, framesize - 2 * wordSize);
5432 else {
5433 mov(rscratch1, framesize - 2 * wordSize);
5434 sub(sp, sp, rscratch1);
5435 }
5436 }
5437 verify_cross_modify_fence_not_required();
5438 }
5439
5440 void MacroAssembler::remove_frame(int framesize) {
5441 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5442 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5443 if (framesize < ((1 << 9) + 2 * wordSize)) {
5444 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5445 add(sp, sp, framesize);
5446 } else {
5447 if (framesize < ((1 << 12) + 2 * wordSize))
5448 add(sp, sp, framesize - 2 * wordSize);
5449 else {
5450 mov(rscratch1, framesize - 2 * wordSize);
5451 add(sp, sp, rscratch1);
5452 }
5453 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5454 }
5455 authenticate_return_address();
5456 }
5457
5458
5459 // This method counts leading positive bytes (highest bit not set) in provided byte array
5460 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5461 // Simple and most common case of aligned small array which is not at the
5462 // end of memory page is placed here. All other cases are in stub.
5463 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5464 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5465 assert_different_registers(ary1, len, result);
5466
5467 mov(result, len);
5468 cmpw(len, 0);
5469 br(LE, DONE);
5470 cmpw(len, 4 * wordSize);
5471 br(GE, STUB_LONG); // size > 32 then go to stub
5472
5473 int shift = 64 - exact_log2(os::vm_page_size());
5474 lsl(rscratch1, ary1, shift);
5475 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5476 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5477 br(CS, STUB); // at the end of page then go to stub
5478 subs(len, len, wordSize);
5479 br(LT, END);
5480
5481 BIND(LOOP);
5482 ldr(rscratch1, Address(post(ary1, wordSize)));
5483 tst(rscratch1, UPPER_BIT_MASK);
5484 br(NE, SET_RESULT);
5485 subs(len, len, wordSize);
5486 br(GE, LOOP);
5487 cmpw(len, -wordSize);
5488 br(EQ, DONE);
5489
5490 BIND(END);
5491 ldr(rscratch1, Address(ary1));
5492 sub(rscratch2, zr, len, LSL, 3); // LSL 3 is to get bits from bytes
5493 lslv(rscratch1, rscratch1, rscratch2);
5494 tst(rscratch1, UPPER_BIT_MASK);
5495 br(NE, SET_RESULT);
5496 b(DONE);
5497
5498 BIND(STUB);
5499 RuntimeAddress count_pos = RuntimeAddress(StubRoutines::aarch64::count_positives());
5500 assert(count_pos.target() != nullptr, "count_positives stub has not been generated");
5501 address tpc1 = trampoline_call(count_pos);
5502 if (tpc1 == nullptr) {
5503 DEBUG_ONLY(reset_labels(STUB_LONG, SET_RESULT, DONE));
5504 postcond(pc() == badAddress);
5505 return nullptr;
5506 }
5507 b(DONE);
5508
5509 BIND(STUB_LONG);
5510 RuntimeAddress count_pos_long = RuntimeAddress(StubRoutines::aarch64::count_positives_long());
5511 assert(count_pos_long.target() != nullptr, "count_positives_long stub has not been generated");
5512 address tpc2 = trampoline_call(count_pos_long);
5513 if (tpc2 == nullptr) {
5514 DEBUG_ONLY(reset_labels(SET_RESULT, DONE));
5515 postcond(pc() == badAddress);
5516 return nullptr;
5517 }
5518 b(DONE);
5519
5520 BIND(SET_RESULT);
5521
5522 add(len, len, wordSize);
5523 sub(result, result, len);
5524
5525 BIND(DONE);
5526 postcond(pc() != badAddress);
5527 return pc();
5528 }
5529
5530 // Clobbers: rscratch1, rscratch2, rflags
5531 // May also clobber v0-v7 when (!UseSimpleArrayEquals && UseSIMDForArrayEquals)
5532 address MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
5533 Register tmp4, Register tmp5, Register result,
5534 Register cnt1, int elem_size) {
5535 Label DONE, SAME;
5536 Register tmp1 = rscratch1;
5537 Register tmp2 = rscratch2;
5538 int elem_per_word = wordSize/elem_size;
5539 int log_elem_size = exact_log2(elem_size);
5540 int klass_offset = arrayOopDesc::klass_offset_in_bytes();
5541 int length_offset = arrayOopDesc::length_offset_in_bytes();
5542 int base_offset
5543 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
5544 // When the length offset is not aligned to 8 bytes,
5545 // then we align it down. This is valid because the new
5546 // offset will always be the klass which is the same
5547 // for type arrays.
5548 int start_offset = align_down(length_offset, BytesPerWord);
5549 int extra_length = base_offset - start_offset;
5550 assert(start_offset == length_offset || start_offset == klass_offset,
5551 "start offset must be 8-byte-aligned or be the klass offset");
5552 assert(base_offset != start_offset, "must include the length field");
5553 extra_length = extra_length / elem_size; // We count in elements, not bytes.
5554 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16);
5555
5556 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
5557 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5558
5559 #ifndef PRODUCT
5560 {
5561 const char kind = (elem_size == 2) ? 'U' : 'L';
5562 char comment[64];
5563 snprintf(comment, sizeof comment, "array_equals%c{", kind);
5564 BLOCK_COMMENT(comment);
5565 }
5566 #endif
5567
5568 // if (a1 == a2)
5569 // return true;
5570 cmpoop(a1, a2); // May have read barriers for a1 and a2.
5571 br(EQ, SAME);
5572
5573 if (UseSimpleArrayEquals) {
5574 Label NEXT_WORD, SHORT, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL;
5575 // if (a1 == nullptr || a2 == nullptr)
5576 // return false;
5577 // a1 & a2 == 0 means (some-pointer is null) or
5578 // (very-rare-or-even-probably-impossible-pointer-values)
5579 // so, we can save one branch in most cases
5580 tst(a1, a2);
5581 mov(result, false);
5582 br(EQ, A_MIGHT_BE_NULL);
5583 // if (a1.length != a2.length)
5584 // return false;
5585 bind(A_IS_NOT_NULL);
5586 ldrw(cnt1, Address(a1, length_offset));
5587 // Increase loop counter by diff between base- and actual start-offset.
5588 addw(cnt1, cnt1, extra_length);
5589 lea(a1, Address(a1, start_offset));
5590 lea(a2, Address(a2, start_offset));
5591 // Check for short strings, i.e. smaller than wordSize.
5592 subs(cnt1, cnt1, elem_per_word);
5593 br(Assembler::LT, SHORT);
5594 // Main 8 byte comparison loop.
5595 bind(NEXT_WORD); {
5596 ldr(tmp1, Address(post(a1, wordSize)));
5597 ldr(tmp2, Address(post(a2, wordSize)));
5598 subs(cnt1, cnt1, elem_per_word);
5599 eor(tmp5, tmp1, tmp2);
5600 cbnz(tmp5, DONE);
5601 } br(GT, NEXT_WORD);
5602 // Last longword. In the case where length == 4 we compare the
5603 // same longword twice, but that's still faster than another
5604 // conditional branch.
5605 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
5606 // length == 4.
5607 if (log_elem_size > 0)
5608 lsl(cnt1, cnt1, log_elem_size);
5609 ldr(tmp3, Address(a1, cnt1));
5610 ldr(tmp4, Address(a2, cnt1));
5611 eor(tmp5, tmp3, tmp4);
5612 cbnz(tmp5, DONE);
5613 b(SAME);
5614 bind(A_MIGHT_BE_NULL);
5615 // in case both a1 and a2 are not-null, proceed with loads
5616 cbz(a1, DONE);
5617 cbz(a2, DONE);
5618 b(A_IS_NOT_NULL);
5619 bind(SHORT);
5620
5621 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
5622 {
5623 ldrw(tmp1, Address(post(a1, 4)));
5624 ldrw(tmp2, Address(post(a2, 4)));
5625 eorw(tmp5, tmp1, tmp2);
5626 cbnzw(tmp5, DONE);
5627 }
5628 bind(TAIL03);
5629 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
5630 {
5631 ldrh(tmp3, Address(post(a1, 2)));
5632 ldrh(tmp4, Address(post(a2, 2)));
5633 eorw(tmp5, tmp3, tmp4);
5634 cbnzw(tmp5, DONE);
5635 }
5636 bind(TAIL01);
5637 if (elem_size == 1) { // Only needed when comparing byte arrays.
5638 tbz(cnt1, 0, SAME); // 0-1 bytes left.
5639 {
5640 ldrb(tmp1, a1);
5641 ldrb(tmp2, a2);
5642 eorw(tmp5, tmp1, tmp2);
5643 cbnzw(tmp5, DONE);
5644 }
5645 }
5646 } else {
5647 Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB,
5648 CSET_EQ, LAST_CHECK;
5649 mov(result, false);
5650 cbz(a1, DONE);
5651 ldrw(cnt1, Address(a1, length_offset));
5652 cbz(a2, DONE);
5653 // Increase loop counter by diff between base- and actual start-offset.
5654 addw(cnt1, cnt1, extra_length);
5655
5656 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's
5657 // faster to perform another branch before comparing a1 and a2
5658 cmp(cnt1, (u1)elem_per_word);
5659 br(LE, SHORT); // short or same
5660 ldr(tmp3, Address(pre(a1, start_offset)));
5661 subs(zr, cnt1, stubBytesThreshold);
5662 br(GE, STUB);
5663 ldr(tmp4, Address(pre(a2, start_offset)));
5664 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
5665
5666 // Main 16 byte comparison loop with 2 exits
5667 bind(NEXT_DWORD); {
5668 ldr(tmp1, Address(pre(a1, wordSize)));
5669 ldr(tmp2, Address(pre(a2, wordSize)));
5670 subs(cnt1, cnt1, 2 * elem_per_word);
5671 br(LE, TAIL);
5672 eor(tmp4, tmp3, tmp4);
5673 cbnz(tmp4, DONE);
5674 ldr(tmp3, Address(pre(a1, wordSize)));
5675 ldr(tmp4, Address(pre(a2, wordSize)));
5676 cmp(cnt1, (u1)elem_per_word);
5677 br(LE, TAIL2);
5678 cmp(tmp1, tmp2);
5679 } br(EQ, NEXT_DWORD);
5680 b(DONE);
5681
5682 bind(TAIL);
5683 eor(tmp4, tmp3, tmp4);
5684 eor(tmp2, tmp1, tmp2);
5685 lslv(tmp2, tmp2, tmp5);
5686 orr(tmp5, tmp4, tmp2);
5687 cmp(tmp5, zr);
5688 b(CSET_EQ);
5689
5690 bind(TAIL2);
5691 eor(tmp2, tmp1, tmp2);
5692 cbnz(tmp2, DONE);
5693 b(LAST_CHECK);
5694
5695 bind(STUB);
5696 ldr(tmp4, Address(pre(a2, start_offset)));
5697 if (elem_size == 2) { // convert to byte counter
5698 lsl(cnt1, cnt1, 1);
5699 }
5700 eor(tmp5, tmp3, tmp4);
5701 cbnz(tmp5, DONE);
5702 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
5703 assert(stub.target() != nullptr, "array_equals_long stub has not been generated");
5704 address tpc = trampoline_call(stub);
5705 if (tpc == nullptr) {
5706 DEBUG_ONLY(reset_labels(SHORT, LAST_CHECK, CSET_EQ, SAME, DONE));
5707 postcond(pc() == badAddress);
5708 return nullptr;
5709 }
5710 b(DONE);
5711
5712 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
5713 // so, if a2 == null => return false(0), else return true, so we can return a2
5714 mov(result, a2);
5715 b(DONE);
5716 bind(SHORT);
5717 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
5718 ldr(tmp3, Address(a1, start_offset));
5719 ldr(tmp4, Address(a2, start_offset));
5720 bind(LAST_CHECK);
5721 eor(tmp4, tmp3, tmp4);
5722 lslv(tmp5, tmp4, tmp5);
5723 cmp(tmp5, zr);
5724 bind(CSET_EQ);
5725 cset(result, EQ);
5726 b(DONE);
5727 }
5728
5729 bind(SAME);
5730 mov(result, true);
5731 // That's it.
5732 bind(DONE);
5733
5734 BLOCK_COMMENT("} array_equals");
5735 postcond(pc() != badAddress);
5736 return pc();
5737 }
5738
5739 // Compare Strings
5740
5741 // For Strings we're passed the address of the first characters in a1
5742 // and a2 and the length in cnt1.
5743 // There are two implementations. For arrays >= 8 bytes, all
5744 // comparisons (including the final one, which may overlap) are
5745 // performed 8 bytes at a time. For strings < 8 bytes, we compare a
5746 // halfword, then a short, and then a byte.
5747
5748 void MacroAssembler::string_equals(Register a1, Register a2,
5749 Register result, Register cnt1)
5750 {
5751 Label SAME, DONE, SHORT, NEXT_WORD;
5752 Register tmp1 = rscratch1;
5753 Register tmp2 = rscratch2;
5754 Register cnt2 = tmp2; // cnt2 only used in array length compare
5755
5756 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5757
5758 #ifndef PRODUCT
5759 {
5760 char comment[64];
5761 snprintf(comment, sizeof comment, "{string_equalsL");
5762 BLOCK_COMMENT(comment);
5763 }
5764 #endif
5765
5766 mov(result, false);
5767
5768 // Check for short strings, i.e. smaller than wordSize.
5769 subs(cnt1, cnt1, wordSize);
5770 br(Assembler::LT, SHORT);
5771 // Main 8 byte comparison loop.
5772 bind(NEXT_WORD); {
5773 ldr(tmp1, Address(post(a1, wordSize)));
5774 ldr(tmp2, Address(post(a2, wordSize)));
5775 subs(cnt1, cnt1, wordSize);
5776 eor(tmp1, tmp1, tmp2);
5777 cbnz(tmp1, DONE);
5778 } br(GT, NEXT_WORD);
5779 // Last longword. In the case where length == 4 we compare the
5780 // same longword twice, but that's still faster than another
5781 // conditional branch.
5782 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
5783 // length == 4.
5784 ldr(tmp1, Address(a1, cnt1));
5785 ldr(tmp2, Address(a2, cnt1));
5786 eor(tmp2, tmp1, tmp2);
5787 cbnz(tmp2, DONE);
5788 b(SAME);
5789
5790 bind(SHORT);
5791 Label TAIL03, TAIL01;
5792
5793 tbz(cnt1, 2, TAIL03); // 0-7 bytes left.
5794 {
5795 ldrw(tmp1, Address(post(a1, 4)));
5796 ldrw(tmp2, Address(post(a2, 4)));
5797 eorw(tmp1, tmp1, tmp2);
5798 cbnzw(tmp1, DONE);
5799 }
5800 bind(TAIL03);
5801 tbz(cnt1, 1, TAIL01); // 0-3 bytes left.
5802 {
5803 ldrh(tmp1, Address(post(a1, 2)));
5804 ldrh(tmp2, Address(post(a2, 2)));
5805 eorw(tmp1, tmp1, tmp2);
5806 cbnzw(tmp1, DONE);
5807 }
5808 bind(TAIL01);
5809 tbz(cnt1, 0, SAME); // 0-1 bytes left.
5810 {
5811 ldrb(tmp1, a1);
5812 ldrb(tmp2, a2);
5813 eorw(tmp1, tmp1, tmp2);
5814 cbnzw(tmp1, DONE);
5815 }
5816 // Arrays are equal.
5817 bind(SAME);
5818 mov(result, true);
5819
5820 // That's it.
5821 bind(DONE);
5822 BLOCK_COMMENT("} string_equals");
5823 }
5824
5825
5826 // The size of the blocks erased by the zero_blocks stub. We must
5827 // handle anything smaller than this ourselves in zero_words().
5828 const int MacroAssembler::zero_words_block_size = 8;
5829
5830 // zero_words() is used by C2 ClearArray patterns and by
5831 // C1_MacroAssembler. It is as small as possible, handling small word
5832 // counts locally and delegating anything larger to the zero_blocks
5833 // stub. It is expanded many times in compiled code, so it is
5834 // important to keep it short.
5835
5836 // ptr: Address of a buffer to be zeroed.
5837 // cnt: Count in HeapWords.
5838 //
5839 // ptr, cnt, rscratch1, and rscratch2 are clobbered.
5840 address MacroAssembler::zero_words(Register ptr, Register cnt)
5841 {
5842 assert(is_power_of_2(zero_words_block_size), "adjust this");
5843
5844 BLOCK_COMMENT("zero_words {");
5845 assert(ptr == r10 && cnt == r11, "mismatch in register usage");
5846 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
5847 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
5848
5849 subs(rscratch1, cnt, zero_words_block_size);
5850 Label around;
5851 br(LO, around);
5852 {
5853 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
5854 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
5855 // Make sure this is a C2 compilation. C1 allocates space only for
5856 // trampoline stubs generated by Call LIR ops, and in any case it
5857 // makes sense for a C1 compilation task to proceed as quickly as
5858 // possible.
5859 CompileTask* task;
5860 if (StubRoutines::aarch64::complete()
5861 && Thread::current()->is_Compiler_thread()
5862 && (task = ciEnv::current()->task())
5863 && is_c2_compile(task->comp_level())) {
5864 address tpc = trampoline_call(zero_blocks);
5865 if (tpc == nullptr) {
5866 DEBUG_ONLY(reset_labels(around));
5867 return nullptr;
5868 }
5869 } else {
5870 far_call(zero_blocks);
5871 }
5872 }
5873 bind(around);
5874
5875 // We have a few words left to do. zero_blocks has adjusted r10 and r11
5876 // for us.
5877 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) {
5878 Label l;
5879 tbz(cnt, exact_log2(i), l);
5880 for (int j = 0; j < i; j += 2) {
5881 stp(zr, zr, post(ptr, 2 * BytesPerWord));
5882 }
5883 bind(l);
5884 }
5885 {
5886 Label l;
5887 tbz(cnt, 0, l);
5888 str(zr, Address(ptr));
5889 bind(l);
5890 }
5891
5892 BLOCK_COMMENT("} zero_words");
5893 return pc();
5894 }
5895
5896 // base: Address of a buffer to be zeroed, 8 bytes aligned.
5897 // cnt: Immediate count in HeapWords.
5898 //
5899 // r10, r11, rscratch1, and rscratch2 are clobbered.
5900 address MacroAssembler::zero_words(Register base, uint64_t cnt)
5901 {
5902 assert(wordSize <= BlockZeroingLowLimit,
5903 "increase BlockZeroingLowLimit");
5904 address result = nullptr;
5905 if (cnt <= (uint64_t)BlockZeroingLowLimit / BytesPerWord) {
5906 #ifndef PRODUCT
5907 {
5908 char buf[64];
5909 snprintf(buf, sizeof buf, "zero_words (count = %" PRIu64 ") {", cnt);
5910 BLOCK_COMMENT(buf);
5911 }
5912 #endif
5913 if (cnt >= 16) {
5914 uint64_t loops = cnt/16;
5915 if (loops > 1) {
5916 mov(rscratch2, loops - 1);
5917 }
5918 {
5919 Label loop;
5920 bind(loop);
5921 for (int i = 0; i < 16; i += 2) {
5922 stp(zr, zr, Address(base, i * BytesPerWord));
5923 }
5924 add(base, base, 16 * BytesPerWord);
5925 if (loops > 1) {
5926 subs(rscratch2, rscratch2, 1);
5927 br(GE, loop);
5928 }
5929 }
5930 }
5931 cnt %= 16;
5932 int i = cnt & 1; // store any odd word to start
5933 if (i) str(zr, Address(base));
5934 for (; i < (int)cnt; i += 2) {
5935 stp(zr, zr, Address(base, i * wordSize));
5936 }
5937 BLOCK_COMMENT("} zero_words");
5938 result = pc();
5939 } else {
5940 mov(r10, base); mov(r11, cnt);
5941 result = zero_words(r10, r11);
5942 }
5943 return result;
5944 }
5945
5946 // Zero blocks of memory by using DC ZVA.
5947 //
5948 // Aligns the base address first sufficiently for DC ZVA, then uses
5949 // DC ZVA repeatedly for every full block. cnt is the size to be
5950 // zeroed in HeapWords. Returns the count of words left to be zeroed
5951 // in cnt.
5952 //
5953 // NOTE: This is intended to be used in the zero_blocks() stub. If
5954 // you want to use it elsewhere, note that cnt must be >= 2*zva_length.
5955 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) {
5956 Register tmp = rscratch1;
5957 Register tmp2 = rscratch2;
5958 int zva_length = VM_Version::zva_length();
5959 Label initial_table_end, loop_zva;
5960 Label fini;
5961
5962 // Base must be 16 byte aligned. If not just return and let caller handle it
5963 tst(base, 0x0f);
5964 br(Assembler::NE, fini);
5965 // Align base with ZVA length.
5966 neg(tmp, base);
5967 andr(tmp, tmp, zva_length - 1);
5968
5969 // tmp: the number of bytes to be filled to align the base with ZVA length.
5970 add(base, base, tmp);
5971 sub(cnt, cnt, tmp, Assembler::ASR, 3);
5972 adr(tmp2, initial_table_end);
5973 sub(tmp2, tmp2, tmp, Assembler::LSR, 2);
5974 br(tmp2);
5975
5976 for (int i = -zva_length + 16; i < 0; i += 16)
5977 stp(zr, zr, Address(base, i));
5978 bind(initial_table_end);
5979
5980 sub(cnt, cnt, zva_length >> 3);
5981 bind(loop_zva);
5982 dc(Assembler::ZVA, base);
5983 subs(cnt, cnt, zva_length >> 3);
5984 add(base, base, zva_length);
5985 br(Assembler::GE, loop_zva);
5986 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA
5987 bind(fini);
5988 }
5989
5990 // base: Address of a buffer to be filled, 8 bytes aligned.
5991 // cnt: Count in 8-byte unit.
5992 // value: Value to be filled with.
5993 // base will point to the end of the buffer after filling.
5994 void MacroAssembler::fill_words(Register base, Register cnt, Register value)
5995 {
5996 // Algorithm:
5997 //
5998 // if (cnt == 0) {
5999 // return;
6000 // }
6001 // if ((p & 8) != 0) {
6002 // *p++ = v;
6003 // }
6004 //
6005 // scratch1 = cnt & 14;
6006 // cnt -= scratch1;
6007 // p += scratch1;
6008 // switch (scratch1 / 2) {
6009 // do {
6010 // cnt -= 16;
6011 // p[-16] = v;
6012 // p[-15] = v;
6013 // case 7:
6014 // p[-14] = v;
6015 // p[-13] = v;
6016 // case 6:
6017 // p[-12] = v;
6018 // p[-11] = v;
6019 // // ...
6020 // case 1:
6021 // p[-2] = v;
6022 // p[-1] = v;
6023 // case 0:
6024 // p += 16;
6025 // } while (cnt);
6026 // }
6027 // if ((cnt & 1) == 1) {
6028 // *p++ = v;
6029 // }
6030
6031 assert_different_registers(base, cnt, value, rscratch1, rscratch2);
6032
6033 Label fini, skip, entry, loop;
6034 const int unroll = 8; // Number of stp instructions we'll unroll
6035
6036 cbz(cnt, fini);
6037 tbz(base, 3, skip);
6038 str(value, Address(post(base, 8)));
6039 sub(cnt, cnt, 1);
6040 bind(skip);
6041
6042 andr(rscratch1, cnt, (unroll-1) * 2);
6043 sub(cnt, cnt, rscratch1);
6044 add(base, base, rscratch1, Assembler::LSL, 3);
6045 adr(rscratch2, entry);
6046 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1);
6047 br(rscratch2);
6048
6049 bind(loop);
6050 add(base, base, unroll * 16);
6051 for (int i = -unroll; i < 0; i++)
6052 stp(value, value, Address(base, i * 16));
6053 bind(entry);
6054 subs(cnt, cnt, unroll * 2);
6055 br(Assembler::GE, loop);
6056
6057 tbz(cnt, 0, fini);
6058 str(value, Address(post(base, 8)));
6059 bind(fini);
6060 }
6061
6062 // Intrinsic for
6063 //
6064 // - sun/nio/cs/ISO_8859_1$Encoder.implEncodeISOArray
6065 // return the number of characters copied.
6066 // - java/lang/StringUTF16.compress
6067 // return index of non-latin1 character if copy fails, otherwise 'len'.
6068 //
6069 // This version always returns the number of characters copied, and does not
6070 // clobber the 'len' register. A successful copy will complete with the post-
6071 // condition: 'res' == 'len', while an unsuccessful copy will exit with the
6072 // post-condition: 0 <= 'res' < 'len'.
6073 //
6074 // NOTE: Attempts to use 'ld2' (and 'umaxv' in the ISO part) has proven to
6075 // degrade performance (on Ampere Altra - Neoverse N1), to an extent
6076 // beyond the acceptable, even though the footprint would be smaller.
6077 // Using 'umaxv' in the ASCII-case comes with a small penalty but does
6078 // avoid additional bloat.
6079 //
6080 // Clobbers: src, dst, res, rscratch1, rscratch2, rflags
6081 void MacroAssembler::encode_iso_array(Register src, Register dst,
6082 Register len, Register res, bool ascii,
6083 FloatRegister vtmp0, FloatRegister vtmp1,
6084 FloatRegister vtmp2, FloatRegister vtmp3,
6085 FloatRegister vtmp4, FloatRegister vtmp5)
6086 {
6087 Register cnt = res;
6088 Register max = rscratch1;
6089 Register chk = rscratch2;
6090
6091 prfm(Address(src), PLDL1STRM);
6092 movw(cnt, len);
6093
6094 #define ASCII(insn) do { if (ascii) { insn; } } while (0)
6095
6096 Label LOOP_32, DONE_32, FAIL_32;
6097
6098 BIND(LOOP_32);
6099 {
6100 cmpw(cnt, 32);
6101 br(LT, DONE_32);
6102 ld1(vtmp0, vtmp1, vtmp2, vtmp3, T8H, Address(post(src, 64)));
6103 // Extract lower bytes.
6104 FloatRegister vlo0 = vtmp4;
6105 FloatRegister vlo1 = vtmp5;
6106 uzp1(vlo0, T16B, vtmp0, vtmp1);
6107 uzp1(vlo1, T16B, vtmp2, vtmp3);
6108 // Merge bits...
6109 orr(vtmp0, T16B, vtmp0, vtmp1);
6110 orr(vtmp2, T16B, vtmp2, vtmp3);
6111 // Extract merged upper bytes.
6112 FloatRegister vhix = vtmp0;
6113 uzp2(vhix, T16B, vtmp0, vtmp2);
6114 // ISO-check on hi-parts (all zero).
6115 // ASCII-check on lo-parts (no sign).
6116 FloatRegister vlox = vtmp1; // Merge lower bytes.
6117 ASCII(orr(vlox, T16B, vlo0, vlo1));
6118 umov(chk, vhix, D, 1); ASCII(cm(LT, vlox, T16B, vlox));
6119 fmovd(max, vhix); ASCII(umaxv(vlox, T16B, vlox));
6120 orr(chk, chk, max); ASCII(umov(max, vlox, B, 0));
6121 ASCII(orr(chk, chk, max));
6122 cbnz(chk, FAIL_32);
6123 subw(cnt, cnt, 32);
6124 st1(vlo0, vlo1, T16B, Address(post(dst, 32)));
6125 b(LOOP_32);
6126 }
6127 BIND(FAIL_32);
6128 sub(src, src, 64);
6129 BIND(DONE_32);
6130
6131 Label LOOP_8, SKIP_8;
6132
6133 BIND(LOOP_8);
6134 {
6135 cmpw(cnt, 8);
6136 br(LT, SKIP_8);
6137 FloatRegister vhi = vtmp0;
6138 FloatRegister vlo = vtmp1;
6139 ld1(vtmp3, T8H, src);
6140 uzp1(vlo, T16B, vtmp3, vtmp3);
6141 uzp2(vhi, T16B, vtmp3, vtmp3);
6142 // ISO-check on hi-parts (all zero).
6143 // ASCII-check on lo-parts (no sign).
6144 ASCII(cm(LT, vtmp2, T16B, vlo));
6145 fmovd(chk, vhi); ASCII(umaxv(vtmp2, T16B, vtmp2));
6146 ASCII(umov(max, vtmp2, B, 0));
6147 ASCII(orr(chk, chk, max));
6148 cbnz(chk, SKIP_8);
6149
6150 strd(vlo, Address(post(dst, 8)));
6151 subw(cnt, cnt, 8);
6152 add(src, src, 16);
6153 b(LOOP_8);
6154 }
6155 BIND(SKIP_8);
6156
6157 #undef ASCII
6158
6159 Label LOOP, DONE;
6160
6161 cbz(cnt, DONE);
6162 BIND(LOOP);
6163 {
6164 Register chr = rscratch1;
6165 ldrh(chr, Address(post(src, 2)));
6166 tst(chr, ascii ? 0xff80 : 0xff00);
6167 br(NE, DONE);
6168 strb(chr, Address(post(dst, 1)));
6169 subs(cnt, cnt, 1);
6170 br(GT, LOOP);
6171 }
6172 BIND(DONE);
6173 // Return index where we stopped.
6174 subw(res, len, cnt);
6175 }
6176
6177 // Inflate byte[] array to char[].
6178 // Clobbers: src, dst, len, rflags, rscratch1, v0-v6
6179 address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
6180 FloatRegister vtmp1, FloatRegister vtmp2,
6181 FloatRegister vtmp3, Register tmp4) {
6182 Label big, done, after_init, to_stub;
6183
6184 assert_different_registers(src, dst, len, tmp4, rscratch1);
6185
6186 fmovd(vtmp1, 0.0);
6187 lsrw(tmp4, len, 3);
6188 bind(after_init);
6189 cbnzw(tmp4, big);
6190 // Short string: less than 8 bytes.
6191 {
6192 Label loop, tiny;
6193
6194 cmpw(len, 4);
6195 br(LT, tiny);
6196 // Use SIMD to do 4 bytes.
6197 ldrs(vtmp2, post(src, 4));
6198 zip1(vtmp3, T8B, vtmp2, vtmp1);
6199 subw(len, len, 4);
6200 strd(vtmp3, post(dst, 8));
6201
6202 cbzw(len, done);
6203
6204 // Do the remaining bytes by steam.
6205 bind(loop);
6206 ldrb(tmp4, post(src, 1));
6207 strh(tmp4, post(dst, 2));
6208 subw(len, len, 1);
6209
6210 bind(tiny);
6211 cbnz(len, loop);
6212
6213 b(done);
6214 }
6215
6216 if (SoftwarePrefetchHintDistance >= 0) {
6217 bind(to_stub);
6218 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate());
6219 assert(stub.target() != nullptr, "large_byte_array_inflate stub has not been generated");
6220 address tpc = trampoline_call(stub);
6221 if (tpc == nullptr) {
6222 DEBUG_ONLY(reset_labels(big, done));
6223 postcond(pc() == badAddress);
6224 return nullptr;
6225 }
6226 b(after_init);
6227 }
6228
6229 // Unpack the bytes 8 at a time.
6230 bind(big);
6231 {
6232 Label loop, around, loop_last, loop_start;
6233
6234 if (SoftwarePrefetchHintDistance >= 0) {
6235 const int large_loop_threshold = (64 + 16)/8;
6236 ldrd(vtmp2, post(src, 8));
6237 andw(len, len, 7);
6238 cmp(tmp4, (u1)large_loop_threshold);
6239 br(GE, to_stub);
6240 b(loop_start);
6241
6242 bind(loop);
6243 ldrd(vtmp2, post(src, 8));
6244 bind(loop_start);
6245 subs(tmp4, tmp4, 1);
6246 br(EQ, loop_last);
6247 zip1(vtmp2, T16B, vtmp2, vtmp1);
6248 ldrd(vtmp3, post(src, 8));
6249 st1(vtmp2, T8H, post(dst, 16));
6250 subs(tmp4, tmp4, 1);
6251 zip1(vtmp3, T16B, vtmp3, vtmp1);
6252 st1(vtmp3, T8H, post(dst, 16));
6253 br(NE, loop);
6254 b(around);
6255 bind(loop_last);
6256 zip1(vtmp2, T16B, vtmp2, vtmp1);
6257 st1(vtmp2, T8H, post(dst, 16));
6258 bind(around);
6259 cbz(len, done);
6260 } else {
6261 andw(len, len, 7);
6262 bind(loop);
6263 ldrd(vtmp2, post(src, 8));
6264 sub(tmp4, tmp4, 1);
6265 zip1(vtmp3, T16B, vtmp2, vtmp1);
6266 st1(vtmp3, T8H, post(dst, 16));
6267 cbnz(tmp4, loop);
6268 }
6269 }
6270
6271 // Do the tail of up to 8 bytes.
6272 add(src, src, len);
6273 ldrd(vtmp3, Address(src, -8));
6274 add(dst, dst, len, ext::uxtw, 1);
6275 zip1(vtmp3, T16B, vtmp3, vtmp1);
6276 strq(vtmp3, Address(dst, -16));
6277
6278 bind(done);
6279 postcond(pc() != badAddress);
6280 return pc();
6281 }
6282
6283 // Compress char[] array to byte[].
6284 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
6285 // Return the array length if every element in array can be encoded,
6286 // otherwise, the index of first non-latin1 (> 0xff) character.
6287 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
6288 Register res,
6289 FloatRegister tmp0, FloatRegister tmp1,
6290 FloatRegister tmp2, FloatRegister tmp3,
6291 FloatRegister tmp4, FloatRegister tmp5) {
6292 encode_iso_array(src, dst, len, res, false, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5);
6293 }
6294
6295 // java.math.round(double a)
6296 // Returns the closest long to the argument, with ties rounding to
6297 // positive infinity. This requires some fiddling for corner
6298 // cases. We take care to avoid double rounding in e.g. (jlong)(a + 0.5).
6299 void MacroAssembler::java_round_double(Register dst, FloatRegister src,
6300 FloatRegister ftmp) {
6301 Label DONE;
6302 BLOCK_COMMENT("java_round_double: { ");
6303 fmovd(rscratch1, src);
6304 // Use RoundToNearestTiesAway unless src small and -ve.
6305 fcvtasd(dst, src);
6306 // Test if src >= 0 || abs(src) >= 0x1.0p52
6307 eor(rscratch1, rscratch1, UCONST64(1) << 63); // flip sign bit
6308 mov(rscratch2, julong_cast(0x1.0p52));
6309 cmp(rscratch1, rscratch2);
6310 br(HS, DONE); {
6311 // src < 0 && abs(src) < 0x1.0p52
6312 // src may have a fractional part, so add 0.5
6313 fmovd(ftmp, 0.5);
6314 faddd(ftmp, src, ftmp);
6315 // Convert double to jlong, use RoundTowardsNegative
6316 fcvtmsd(dst, ftmp);
6317 }
6318 bind(DONE);
6319 BLOCK_COMMENT("} java_round_double");
6320 }
6321
6322 void MacroAssembler::java_round_float(Register dst, FloatRegister src,
6323 FloatRegister ftmp) {
6324 Label DONE;
6325 BLOCK_COMMENT("java_round_float: { ");
6326 fmovs(rscratch1, src);
6327 // Use RoundToNearestTiesAway unless src small and -ve.
6328 fcvtassw(dst, src);
6329 // Test if src >= 0 || abs(src) >= 0x1.0p23
6330 eor(rscratch1, rscratch1, 0x80000000); // flip sign bit
6331 mov(rscratch2, jint_cast(0x1.0p23f));
6332 cmp(rscratch1, rscratch2);
6333 br(HS, DONE); {
6334 // src < 0 && |src| < 0x1.0p23
6335 // src may have a fractional part, so add 0.5
6336 fmovs(ftmp, 0.5f);
6337 fadds(ftmp, src, ftmp);
6338 // Convert float to jint, use RoundTowardsNegative
6339 fcvtmssw(dst, ftmp);
6340 }
6341 bind(DONE);
6342 BLOCK_COMMENT("} java_round_float");
6343 }
6344
6345 // get_thread() can be called anywhere inside generated code so we
6346 // need to save whatever non-callee save context might get clobbered
6347 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
6348 // the call setup code.
6349 //
6350 // On Linux, aarch64_get_thread_helper() clobbers only r0, r1, and flags.
6351 // On other systems, the helper is a usual C function.
6352 //
6353 void MacroAssembler::get_thread(Register dst) {
6354 RegSet saved_regs =
6355 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6356 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6357
6358 protect_return_address();
6359 push(saved_regs, sp);
6360
6361 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
6362 blr(lr);
6363 if (dst != c_rarg0) {
6364 mov(dst, c_rarg0);
6365 }
6366
6367 pop(saved_regs, sp);
6368 authenticate_return_address();
6369 }
6370
6371 void MacroAssembler::cache_wb(Address line) {
6372 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
6373 assert(line.index() == noreg, "index should be noreg");
6374 assert(line.offset() == 0, "offset should be 0");
6375 // would like to assert this
6376 // assert(line._ext.shift == 0, "shift should be zero");
6377 if (VM_Version::supports_dcpop()) {
6378 // writeback using clear virtual address to point of persistence
6379 dc(Assembler::CVAP, line.base());
6380 } else {
6381 // no need to generate anything as Unsafe.writebackMemory should
6382 // never invoke this stub
6383 }
6384 }
6385
6386 void MacroAssembler::cache_wbsync(bool is_pre) {
6387 // we only need a barrier post sync
6388 if (!is_pre) {
6389 membar(Assembler::AnyAny);
6390 }
6391 }
6392
6393 void MacroAssembler::verify_sve_vector_length(Register tmp) {
6394 // Make sure that native code does not change SVE vector length.
6395 if (!UseSVE) return;
6396 Label verify_ok;
6397 movw(tmp, zr);
6398 sve_inc(tmp, B);
6399 subsw(zr, tmp, VM_Version::get_initial_sve_vector_length());
6400 br(EQ, verify_ok);
6401 stop("Error: SVE vector length has changed since jvm startup");
6402 bind(verify_ok);
6403 }
6404
6405 void MacroAssembler::verify_ptrue() {
6406 Label verify_ok;
6407 if (!UseSVE) {
6408 return;
6409 }
6410 sve_cntp(rscratch1, B, ptrue, ptrue); // get true elements count.
6411 sve_dec(rscratch1, B);
6412 cbz(rscratch1, verify_ok);
6413 stop("Error: the preserved predicate register (p7) elements are not all true");
6414 bind(verify_ok);
6415 }
6416
6417 void MacroAssembler::safepoint_isb() {
6418 isb();
6419 #ifndef PRODUCT
6420 if (VerifyCrossModifyFence) {
6421 // Clear the thread state.
6422 strb(zr, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6423 }
6424 #endif
6425 }
6426
6427 #ifndef PRODUCT
6428 void MacroAssembler::verify_cross_modify_fence_not_required() {
6429 if (VerifyCrossModifyFence) {
6430 // Check if thread needs a cross modify fence.
6431 ldrb(rscratch1, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6432 Label fence_not_required;
6433 cbz(rscratch1, fence_not_required);
6434 // If it does then fail.
6435 lea(rscratch1, CAST_FROM_FN_PTR(address, JavaThread::verify_cross_modify_fence_failure));
6436 mov(c_rarg0, rthread);
6437 blr(rscratch1);
6438 bind(fence_not_required);
6439 }
6440 }
6441 #endif
6442
6443 void MacroAssembler::spin_wait() {
6444 for (int i = 0; i < VM_Version::spin_wait_desc().inst_count(); ++i) {
6445 switch (VM_Version::spin_wait_desc().inst()) {
6446 case SpinWait::NOP:
6447 nop();
6448 break;
6449 case SpinWait::ISB:
6450 isb();
6451 break;
6452 case SpinWait::YIELD:
6453 yield();
6454 break;
6455 default:
6456 ShouldNotReachHere();
6457 }
6458 }
6459 }
6460
6461 // Stack frame creation/removal
6462
6463 void MacroAssembler::enter(bool strip_ret_addr) {
6464 if (strip_ret_addr) {
6465 // Addresses can only be signed once. If there are multiple nested frames being created
6466 // in the same function, then the return address needs stripping first.
6467 strip_return_address();
6468 }
6469 protect_return_address();
6470 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
6471 mov(rfp, sp);
6472 }
6473
6474 void MacroAssembler::leave() {
6475 mov(sp, rfp);
6476 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
6477 authenticate_return_address();
6478 }
6479
6480 // ROP Protection
6481 // Use the AArch64 PAC feature to add ROP protection for generated code. Use whenever creating/
6482 // destroying stack frames or whenever directly loading/storing the LR to memory.
6483 // If ROP protection is not set then these functions are no-ops.
6484 // For more details on PAC see pauth_aarch64.hpp.
6485
6486 // Sign the LR. Use during construction of a stack frame, before storing the LR to memory.
6487 // Uses value zero as the modifier.
6488 //
6489 void MacroAssembler::protect_return_address() {
6490 if (VM_Version::use_rop_protection()) {
6491 check_return_address();
6492 paciaz();
6493 }
6494 }
6495
6496 // Sign the return value in the given register. Use before updating the LR in the existing stack
6497 // frame for the current function.
6498 // Uses value zero as the modifier.
6499 //
6500 void MacroAssembler::protect_return_address(Register return_reg) {
6501 if (VM_Version::use_rop_protection()) {
6502 check_return_address(return_reg);
6503 paciza(return_reg);
6504 }
6505 }
6506
6507 // Authenticate the LR. Use before function return, after restoring FP and loading LR from memory.
6508 // Uses value zero as the modifier.
6509 //
6510 void MacroAssembler::authenticate_return_address() {
6511 if (VM_Version::use_rop_protection()) {
6512 autiaz();
6513 check_return_address();
6514 }
6515 }
6516
6517 // Authenticate the return value in the given register. Use before updating the LR in the existing
6518 // stack frame for the current function.
6519 // Uses value zero as the modifier.
6520 //
6521 void MacroAssembler::authenticate_return_address(Register return_reg) {
6522 if (VM_Version::use_rop_protection()) {
6523 autiza(return_reg);
6524 check_return_address(return_reg);
6525 }
6526 }
6527
6528 // Strip any PAC data from LR without performing any authentication. Use with caution - only if
6529 // there is no guaranteed way of authenticating the LR.
6530 //
6531 void MacroAssembler::strip_return_address() {
6532 if (VM_Version::use_rop_protection()) {
6533 xpaclri();
6534 }
6535 }
6536
6537 #ifndef PRODUCT
6538 // PAC failures can be difficult to debug. After an authentication failure, a segfault will only
6539 // occur when the pointer is used - ie when the program returns to the invalid LR. At this point
6540 // it is difficult to debug back to the callee function.
6541 // This function simply loads from the address in the given register.
6542 // Use directly after authentication to catch authentication failures.
6543 // Also use before signing to check that the pointer is valid and hasn't already been signed.
6544 //
6545 void MacroAssembler::check_return_address(Register return_reg) {
6546 if (VM_Version::use_rop_protection()) {
6547 ldr(zr, Address(return_reg));
6548 }
6549 }
6550 #endif
6551
6552 // The java_calling_convention describes stack locations as ideal slots on
6553 // a frame with no abi restrictions. Since we must observe abi restrictions
6554 // (like the placement of the register window) the slots must be biased by
6555 // the following value.
6556 static int reg2offset_in(VMReg r) {
6557 // Account for saved rfp and lr
6558 // This should really be in_preserve_stack_slots
6559 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
6560 }
6561
6562 static int reg2offset_out(VMReg r) {
6563 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
6564 }
6565
6566 // On 64bit we will store integer like items to the stack as
6567 // 64bits items (AArch64 ABI) even though java would only store
6568 // 32bits for a parameter. On 32bit it will simply be 32bits
6569 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
6570 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp) {
6571 if (src.first()->is_stack()) {
6572 if (dst.first()->is_stack()) {
6573 // stack to stack
6574 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
6575 str(tmp, Address(sp, reg2offset_out(dst.first())));
6576 } else {
6577 // stack to reg
6578 ldrsw(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
6579 }
6580 } else if (dst.first()->is_stack()) {
6581 // reg to stack
6582 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
6583 } else {
6584 if (dst.first() != src.first()) {
6585 sxtw(dst.first()->as_Register(), src.first()->as_Register());
6586 }
6587 }
6588 }
6589
6590 // An oop arg. Must pass a handle not the oop itself
6591 void MacroAssembler::object_move(
6592 OopMap* map,
6593 int oop_handle_offset,
6594 int framesize_in_slots,
6595 VMRegPair src,
6596 VMRegPair dst,
6597 bool is_receiver,
6598 int* receiver_offset) {
6599
6600 // must pass a handle. First figure out the location we use as a handle
6601
6602 Register rHandle = dst.first()->is_stack() ? rscratch2 : dst.first()->as_Register();
6603
6604 // See if oop is null if it is we need no handle
6605
6606 if (src.first()->is_stack()) {
6607
6608 // Oop is already on the stack as an argument
6609 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
6610 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
6611 if (is_receiver) {
6612 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
6613 }
6614
6615 ldr(rscratch1, Address(rfp, reg2offset_in(src.first())));
6616 lea(rHandle, Address(rfp, reg2offset_in(src.first())));
6617 // conditionally move a null
6618 cmp(rscratch1, zr);
6619 csel(rHandle, zr, rHandle, Assembler::EQ);
6620 } else {
6621
6622 // Oop is in an a register we must store it to the space we reserve
6623 // on the stack for oop_handles and pass a handle if oop is non-null
6624
6625 const Register rOop = src.first()->as_Register();
6626 int oop_slot;
6627 if (rOop == j_rarg0)
6628 oop_slot = 0;
6629 else if (rOop == j_rarg1)
6630 oop_slot = 1;
6631 else if (rOop == j_rarg2)
6632 oop_slot = 2;
6633 else if (rOop == j_rarg3)
6634 oop_slot = 3;
6635 else if (rOop == j_rarg4)
6636 oop_slot = 4;
6637 else if (rOop == j_rarg5)
6638 oop_slot = 5;
6639 else if (rOop == j_rarg6)
6640 oop_slot = 6;
6641 else {
6642 assert(rOop == j_rarg7, "wrong register");
6643 oop_slot = 7;
6644 }
6645
6646 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
6647 int offset = oop_slot*VMRegImpl::stack_slot_size;
6648
6649 map->set_oop(VMRegImpl::stack2reg(oop_slot));
6650 // Store oop in handle area, may be null
6651 str(rOop, Address(sp, offset));
6652 if (is_receiver) {
6653 *receiver_offset = offset;
6654 }
6655
6656 cmp(rOop, zr);
6657 lea(rHandle, Address(sp, offset));
6658 // conditionally move a null
6659 csel(rHandle, zr, rHandle, Assembler::EQ);
6660 }
6661
6662 // If arg is on the stack then place it otherwise it is already in correct reg.
6663 if (dst.first()->is_stack()) {
6664 str(rHandle, Address(sp, reg2offset_out(dst.first())));
6665 }
6666 }
6667
6668 // A float arg may have to do float reg int reg conversion
6669 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp) {
6670 if (src.first()->is_stack()) {
6671 if (dst.first()->is_stack()) {
6672 ldrw(tmp, Address(rfp, reg2offset_in(src.first())));
6673 strw(tmp, Address(sp, reg2offset_out(dst.first())));
6674 } else {
6675 ldrs(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
6676 }
6677 } else if (src.first() != dst.first()) {
6678 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
6679 fmovs(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
6680 else
6681 strs(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
6682 }
6683 }
6684
6685 // A long move
6686 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp) {
6687 if (src.first()->is_stack()) {
6688 if (dst.first()->is_stack()) {
6689 // stack to stack
6690 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
6691 str(tmp, Address(sp, reg2offset_out(dst.first())));
6692 } else {
6693 // stack to reg
6694 ldr(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
6695 }
6696 } else if (dst.first()->is_stack()) {
6697 // reg to stack
6698 // Do we really have to sign extend???
6699 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
6700 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
6701 } else {
6702 if (dst.first() != src.first()) {
6703 mov(dst.first()->as_Register(), src.first()->as_Register());
6704 }
6705 }
6706 }
6707
6708
6709 // A double move
6710 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp) {
6711 if (src.first()->is_stack()) {
6712 if (dst.first()->is_stack()) {
6713 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
6714 str(tmp, Address(sp, reg2offset_out(dst.first())));
6715 } else {
6716 ldrd(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
6717 }
6718 } else if (src.first() != dst.first()) {
6719 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
6720 fmovd(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
6721 else
6722 strd(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
6723 }
6724 }
6725
6726 // Implements lightweight-locking.
6727 //
6728 // - obj: the object to be locked
6729 // - t1, t2, t3: temporary registers, will be destroyed
6730 // - slow: branched to if locking fails, absolute offset may larger than 32KB (imm14 encoding).
6731 void MacroAssembler::lightweight_lock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
6732 assert(LockingMode == LM_LIGHTWEIGHT, "only used with new lightweight locking");
6733 assert_different_registers(obj, t1, t2, t3, rscratch1);
6734
6735 Label push;
6736 const Register top = t1;
6737 const Register mark = t2;
6738 const Register t = t3;
6739
6740 // Preload the markWord. It is important that this is the first
6741 // instruction emitted as it is part of C1's null check semantics.
6742 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
6743
6744 // Check if the lock-stack is full.
6745 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
6746 cmpw(top, (unsigned)LockStack::end_offset());
6747 br(Assembler::GE, slow);
6748
6749 // Check for recursion.
6750 subw(t, top, oopSize);
6751 ldr(t, Address(rthread, t));
6752 cmp(obj, t);
6753 br(Assembler::EQ, push);
6754
6755 // Check header for monitor (0b10).
6756 tst(mark, markWord::monitor_value);
6757 br(Assembler::NE, slow);
6758
6759 // Try to lock. Transition lock bits 0b01 => 0b00
6760 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
6761 orr(mark, mark, markWord::unlocked_value);
6762 eor(t, mark, markWord::unlocked_value);
6763 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
6764 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
6765 br(Assembler::NE, slow);
6766
6767 bind(push);
6768 // After successful lock, push object on lock-stack.
6769 str(obj, Address(rthread, top));
6770 addw(top, top, oopSize);
6771 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
6772 }
6773
6774 // Implements lightweight-unlocking.
6775 //
6776 // - obj: the object to be unlocked
6777 // - t1, t2, t3: temporary registers
6778 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
6779 void MacroAssembler::lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
6780 assert(LockingMode == LM_LIGHTWEIGHT, "only used with new lightweight locking");
6781 // cmpxchg clobbers rscratch1.
6782 assert_different_registers(obj, t1, t2, t3, rscratch1);
6783
6784 #ifdef ASSERT
6785 {
6786 // Check for lock-stack underflow.
6787 Label stack_ok;
6788 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
6789 cmpw(t1, (unsigned)LockStack::start_offset());
6790 br(Assembler::GE, stack_ok);
6791 STOP("Lock-stack underflow");
6792 bind(stack_ok);
6793 }
6794 #endif
6795
6796 Label unlocked, push_and_slow;
6797 const Register top = t1;
6798 const Register mark = t2;
6799 const Register t = t3;
6800
6801 // Check if obj is top of lock-stack.
6802 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
6803 subw(top, top, oopSize);
6804 ldr(t, Address(rthread, top));
6805 cmp(obj, t);
6806 br(Assembler::NE, slow);
6807
6808 // Pop lock-stack.
6809 DEBUG_ONLY(str(zr, Address(rthread, top));)
6810 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
6811
6812 // Check if recursive.
6813 subw(t, top, oopSize);
6814 ldr(t, Address(rthread, t));
6815 cmp(obj, t);
6816 br(Assembler::EQ, unlocked);
6817
6818 // Not recursive. Check header for monitor (0b10).
6819 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
6820 tbnz(mark, log2i_exact(markWord::monitor_value), push_and_slow);
6821
6822 #ifdef ASSERT
6823 // Check header not unlocked (0b01).
6824 Label not_unlocked;
6825 tbz(mark, log2i_exact(markWord::unlocked_value), not_unlocked);
6826 stop("lightweight_unlock already unlocked");
6827 bind(not_unlocked);
6828 #endif
6829
6830 // Try to unlock. Transition lock bits 0b00 => 0b01
6831 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
6832 orr(t, mark, markWord::unlocked_value);
6833 cmpxchg(obj, mark, t, Assembler::xword,
6834 /*acquire*/ false, /*release*/ true, /*weak*/ false, noreg);
6835 br(Assembler::EQ, unlocked);
6836
6837 bind(push_and_slow);
6838 // Restore lock-stack and handle the unlock in runtime.
6839 DEBUG_ONLY(str(obj, Address(rthread, top));)
6840 addw(top, top, oopSize);
6841 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
6842 b(slow);
6843
6844 bind(unlocked);
6845 }