1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "ci/ciEnv.hpp"
29 #include "ci/ciUtilities.hpp"
30 #include "code/compiledIC.hpp"
31 #include "compiler/compileTask.hpp"
32 #include "compiler/disassembler.hpp"
33 #include "compiler/oopMap.hpp"
34 #include "gc/shared/barrierSet.hpp"
35 #include "gc/shared/barrierSetAssembler.hpp"
36 #include "gc/shared/cardTableBarrierSet.hpp"
37 #include "gc/shared/cardTable.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/tlab_globals.hpp"
40 #include "interpreter/bytecodeHistogram.hpp"
41 #include "interpreter/interpreter.hpp"
42 #include "interpreter/interpreterRuntime.hpp"
43 #include "jvm.h"
44 #include "memory/resourceArea.hpp"
45 #include "memory/universe.hpp"
46 #include "nativeInst_aarch64.hpp"
47 #include "oops/accessDecorators.hpp"
48 #include "oops/compressedKlass.inline.hpp"
49 #include "oops/compressedOops.inline.hpp"
50 #include "oops/klass.inline.hpp"
51 #include "runtime/continuation.hpp"
52 #include "runtime/icache.hpp"
53 #include "runtime/interfaceSupport.inline.hpp"
54 #include "runtime/javaThread.hpp"
55 #include "runtime/jniHandles.inline.hpp"
56 #include "runtime/sharedRuntime.hpp"
57 #include "runtime/stubRoutines.hpp"
58 #include "utilities/globalDefinitions.hpp"
59 #include "utilities/powerOfTwo.hpp"
60 #ifdef COMPILER1
61 #include "c1/c1_LIRAssembler.hpp"
62 #endif
63 #ifdef COMPILER2
64 #include "oops/oop.hpp"
65 #include "opto/compile.hpp"
66 #include "opto/node.hpp"
67 #include "opto/output.hpp"
68 #endif
69
70 #include <sys/types.h>
71
72 #ifdef PRODUCT
73 #define BLOCK_COMMENT(str) /* nothing */
74 #else
75 #define BLOCK_COMMENT(str) block_comment(str)
76 #endif
77 #define STOP(str) stop(str);
78 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
79
80 #ifdef ASSERT
81 extern "C" void disnm(intptr_t p);
82 #endif
83 // Target-dependent relocation processing
84 //
85 // Instruction sequences whose target may need to be retrieved or
86 // patched are distinguished by their leading instruction, sorting
87 // them into three main instruction groups and related subgroups.
88 //
89 // 1) Branch, Exception and System (insn count = 1)
90 // 1a) Unconditional branch (immediate):
91 // b/bl imm19
92 // 1b) Compare & branch (immediate):
93 // cbz/cbnz Rt imm19
94 // 1c) Test & branch (immediate):
95 // tbz/tbnz Rt imm14
96 // 1d) Conditional branch (immediate):
97 // b.cond imm19
98 //
99 // 2) Loads and Stores (insn count = 1)
100 // 2a) Load register literal:
101 // ldr Rt imm19
102 //
103 // 3) Data Processing Immediate (insn count = 2 or 3)
104 // 3a) PC-rel. addressing
105 // adr/adrp Rx imm21; ldr/str Ry Rx #imm12
106 // adr/adrp Rx imm21; add Ry Rx #imm12
107 // adr/adrp Rx imm21; movk Rx #imm16<<32; ldr/str Ry, [Rx, #offset_in_page]
108 // adr/adrp Rx imm21
109 // adr/adrp Rx imm21; movk Rx #imm16<<32
110 // adr/adrp Rx imm21; movk Rx #imm16<<32; add Ry, Rx, #offset_in_page
111 // The latter form can only happen when the target is an
112 // ExternalAddress, and (by definition) ExternalAddresses don't
113 // move. Because of that property, there is never any need to
114 // patch the last of the three instructions. However,
115 // MacroAssembler::target_addr_for_insn takes all three
116 // instructions into account and returns the correct address.
117 // 3b) Move wide (immediate)
118 // movz Rx #imm16; movk Rx #imm16 << 16; movk Rx #imm16 << 32;
119 //
120 // A switch on a subset of the instruction's bits provides an
121 // efficient dispatch to these subcases.
122 //
123 // insn[28:26] -> main group ('x' == don't care)
124 // 00x -> UNALLOCATED
125 // 100 -> Data Processing Immediate
126 // 101 -> Branch, Exception and System
127 // x1x -> Loads and Stores
128 //
129 // insn[30:25] -> subgroup ('_' == group, 'x' == don't care).
130 // n.b. in some cases extra bits need to be checked to verify the
131 // instruction is as expected
132 //
133 // 1) ... xx101x Branch, Exception and System
134 // 1a) 00___x Unconditional branch (immediate)
135 // 1b) 01___0 Compare & branch (immediate)
136 // 1c) 01___1 Test & branch (immediate)
137 // 1d) 10___0 Conditional branch (immediate)
138 // other Should not happen
139 //
140 // 2) ... xxx1x0 Loads and Stores
141 // 2a) xx1__00 Load/Store register (insn[28] == 1 && insn[24] == 0)
142 // 2aa) x01__00 Load register literal (i.e. requires insn[29] == 0)
143 // strictly should be 64 bit non-FP/SIMD i.e.
144 // 0101_000 (i.e. requires insn[31:24] == 01011000)
145 //
146 // 3) ... xx100x Data Processing Immediate
147 // 3a) xx___00 PC-rel. addressing (n.b. requires insn[24] == 0)
148 // 3b) xx___101 Move wide (immediate) (n.b. requires insn[24:23] == 01)
149 // strictly should be 64 bit movz #imm16<<0
150 // 110___10100 (i.e. requires insn[31:21] == 11010010100)
151 //
152
153 static uint32_t insn_at(address insn_addr, int n) {
154 return ((uint32_t*)insn_addr)[n];
155 }
156
157 template<typename T>
158 class RelocActions : public AllStatic {
159
160 public:
161
162 static int ALWAYSINLINE run(address insn_addr, address &target) {
163 int instructions = 1;
164 uint32_t insn = insn_at(insn_addr, 0);
165
166 uint32_t dispatch = Instruction_aarch64::extract(insn, 30, 25);
167 switch(dispatch) {
168 case 0b001010:
169 case 0b001011: {
170 instructions = T::unconditionalBranch(insn_addr, target);
171 break;
172 }
173 case 0b101010: // Conditional branch (immediate)
174 case 0b011010: { // Compare & branch (immediate)
175 instructions = T::conditionalBranch(insn_addr, target);
176 break;
177 }
178 case 0b011011: {
179 instructions = T::testAndBranch(insn_addr, target);
180 break;
181 }
182 case 0b001100:
183 case 0b001110:
184 case 0b011100:
185 case 0b011110:
186 case 0b101100:
187 case 0b101110:
188 case 0b111100:
189 case 0b111110: {
190 // load/store
191 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
192 // Load register (literal)
193 instructions = T::loadStore(insn_addr, target);
194 break;
195 } else {
196 // nothing to do
197 assert(target == nullptr, "did not expect to relocate target for polling page load");
198 }
199 break;
200 }
201 case 0b001000:
202 case 0b011000:
203 case 0b101000:
204 case 0b111000: {
205 // adr/adrp
206 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
207 int shift = Instruction_aarch64::extract(insn, 31, 31);
208 if (shift) {
209 uint32_t insn2 = insn_at(insn_addr, 1);
210 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
211 Instruction_aarch64::extract(insn, 4, 0) ==
212 Instruction_aarch64::extract(insn2, 9, 5)) {
213 instructions = T::adrp(insn_addr, target, T::adrpMem);
214 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
215 Instruction_aarch64::extract(insn, 4, 0) ==
216 Instruction_aarch64::extract(insn2, 4, 0)) {
217 instructions = T::adrp(insn_addr, target, T::adrpAdd);
218 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
219 Instruction_aarch64::extract(insn, 4, 0) ==
220 Instruction_aarch64::extract(insn2, 4, 0)) {
221 instructions = T::adrp(insn_addr, target, T::adrpMovk);
222 } else {
223 ShouldNotReachHere();
224 }
225 } else {
226 instructions = T::adr(insn_addr, target);
227 }
228 break;
229 }
230 case 0b001001:
231 case 0b011001:
232 case 0b101001:
233 case 0b111001: {
234 instructions = T::immediate(insn_addr, target);
235 break;
236 }
237 default: {
238 ShouldNotReachHere();
239 }
240 }
241
242 T::verify(insn_addr, target);
243 return instructions * NativeInstruction::instruction_size;
244 }
245 };
246
247 class Patcher : public AllStatic {
248 public:
249 static int unconditionalBranch(address insn_addr, address &target) {
250 intptr_t offset = (target - insn_addr) >> 2;
251 Instruction_aarch64::spatch(insn_addr, 25, 0, offset);
252 return 1;
253 }
254 static int conditionalBranch(address insn_addr, address &target) {
255 intptr_t offset = (target - insn_addr) >> 2;
256 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
257 return 1;
258 }
259 static int testAndBranch(address insn_addr, address &target) {
260 intptr_t offset = (target - insn_addr) >> 2;
261 Instruction_aarch64::spatch(insn_addr, 18, 5, offset);
262 return 1;
263 }
264 static int loadStore(address insn_addr, address &target) {
265 intptr_t offset = (target - insn_addr) >> 2;
266 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
267 return 1;
268 }
269 static int adr(address insn_addr, address &target) {
270 #ifdef ASSERT
271 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
272 #endif
273 // PC-rel. addressing
274 ptrdiff_t offset = target - insn_addr;
275 int offset_lo = offset & 3;
276 offset >>= 2;
277 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
278 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
279 return 1;
280 }
281 template<typename U>
282 static int adrp(address insn_addr, address &target, U inner) {
283 int instructions = 1;
284 #ifdef ASSERT
285 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
286 #endif
287 ptrdiff_t offset = target - insn_addr;
288 instructions = 2;
289 precond(inner != nullptr);
290 // Give the inner reloc a chance to modify the target.
291 address adjusted_target = target;
292 instructions = inner(insn_addr, adjusted_target);
293 uintptr_t pc_page = (uintptr_t)insn_addr >> 12;
294 uintptr_t adr_page = (uintptr_t)adjusted_target >> 12;
295 offset = adr_page - pc_page;
296 int offset_lo = offset & 3;
297 offset >>= 2;
298 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
299 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
300 return instructions;
301 }
302 static int adrpMem(address insn_addr, address &target) {
303 uintptr_t dest = (uintptr_t)target;
304 int offset_lo = dest & 0xfff;
305 uint32_t insn2 = insn_at(insn_addr, 1);
306 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
307 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo >> size);
308 guarantee(((dest >> size) << size) == dest, "misaligned target");
309 return 2;
310 }
311 static int adrpAdd(address insn_addr, address &target) {
312 uintptr_t dest = (uintptr_t)target;
313 int offset_lo = dest & 0xfff;
314 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo);
315 return 2;
316 }
317 static int adrpMovk(address insn_addr, address &target) {
318 uintptr_t dest = uintptr_t(target);
319 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 20, 5, (uintptr_t)target >> 32);
320 dest = (dest & 0xffffffffULL) | (uintptr_t(insn_addr) & 0xffff00000000ULL);
321 target = address(dest);
322 return 2;
323 }
324 static int immediate(address insn_addr, address &target) {
325 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
326 // We encode narrow ones by setting the upper 16 bits in the first
327 // instruction.
328 if (Instruction_aarch64::extract(insn_at(insn_addr, 0), 31, 21) == 0b11010010101) {
329 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
330 narrowKlass nk = CompressedKlassPointers::encode((Klass*)target);
331 Instruction_aarch64::patch(insn_addr, 20, 5, nk >> 16);
332 Instruction_aarch64::patch(insn_addr+4, 20, 5, nk & 0xffff);
333 return 2;
334 }
335 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 31, 21) == 0b11010010100, "must be");
336 uint64_t dest = (uint64_t)target;
337 // Move wide constant
338 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
339 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
340 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
341 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
342 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
343 return 3;
344 }
345 static void verify(address insn_addr, address &target) {
346 #ifdef ASSERT
347 address address_is = MacroAssembler::target_addr_for_insn(insn_addr);
348 if (!(address_is == target)) {
349 tty->print_cr("%p at %p should be %p", address_is, insn_addr, target);
350 disnm((intptr_t)insn_addr);
351 assert(address_is == target, "should be");
352 }
353 #endif
354 }
355 };
356
357 // If insn1 and insn2 use the same register to form an address, either
358 // by an offsetted LDR or a simple ADD, return the offset. If the
359 // second instruction is an LDR, the offset may be scaled.
360 static bool offset_for(uint32_t insn1, uint32_t insn2, ptrdiff_t &byte_offset) {
361 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
362 Instruction_aarch64::extract(insn1, 4, 0) ==
363 Instruction_aarch64::extract(insn2, 9, 5)) {
364 // Load/store register (unsigned immediate)
365 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
366 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
367 byte_offset <<= size;
368 return true;
369 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
370 Instruction_aarch64::extract(insn1, 4, 0) ==
371 Instruction_aarch64::extract(insn2, 4, 0)) {
372 // add (immediate)
373 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
374 return true;
375 }
376 return false;
377 }
378
379 class AArch64Decoder : public AllStatic {
380 public:
381
382 static int loadStore(address insn_addr, address &target) {
383 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
384 target = insn_addr + (offset << 2);
385 return 1;
386 }
387 static int unconditionalBranch(address insn_addr, address &target) {
388 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 25, 0);
389 target = insn_addr + (offset << 2);
390 return 1;
391 }
392 static int conditionalBranch(address insn_addr, address &target) {
393 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
394 target = address(((uint64_t)insn_addr + (offset << 2)));
395 return 1;
396 }
397 static int testAndBranch(address insn_addr, address &target) {
398 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 18, 5);
399 target = address(((uint64_t)insn_addr + (offset << 2)));
400 return 1;
401 }
402 static int adr(address insn_addr, address &target) {
403 // PC-rel. addressing
404 uint32_t insn = insn_at(insn_addr, 0);
405 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
406 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
407 target = address((uint64_t)insn_addr + offset);
408 return 1;
409 }
410 template<typename U>
411 static int adrp(address insn_addr, address &target, U inner) {
412 uint32_t insn = insn_at(insn_addr, 0);
413 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
414 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
415 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
416 int shift = 12;
417 offset <<= shift;
418 uint64_t target_page = ((uint64_t)insn_addr) + offset;
419 target_page &= ((uint64_t)-1) << shift;
420 uint32_t insn2 = insn_at(insn_addr, 1);
421 target = address(target_page);
422 precond(inner != nullptr);
423 inner(insn_addr, target);
424 return 2;
425 }
426 static int adrpMem(address insn_addr, address &target) {
427 uint32_t insn2 = insn_at(insn_addr, 1);
428 // Load/store register (unsigned immediate)
429 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
430 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
431 byte_offset <<= size;
432 target += byte_offset;
433 return 2;
434 }
435 static int adrpAdd(address insn_addr, address &target) {
436 uint32_t insn2 = insn_at(insn_addr, 1);
437 // add (immediate)
438 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
439 target += byte_offset;
440 return 2;
441 }
442 static int adrpMovk(address insn_addr, address &target) {
443 uint32_t insn2 = insn_at(insn_addr, 1);
444 uint64_t dest = uint64_t(target);
445 dest = (dest & 0xffff0000ffffffff) |
446 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
447 target = address(dest);
448
449 // We know the destination 4k page. Maybe we have a third
450 // instruction.
451 uint32_t insn = insn_at(insn_addr, 0);
452 uint32_t insn3 = insn_at(insn_addr, 2);
453 ptrdiff_t byte_offset;
454 if (offset_for(insn, insn3, byte_offset)) {
455 target += byte_offset;
456 return 3;
457 } else {
458 return 2;
459 }
460 }
461 static int immediate(address insn_addr, address &target) {
462 uint32_t *insns = (uint32_t *)insn_addr;
463 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
464 // We encode narrow ones by setting the upper 16 bits in the first
465 // instruction.
466 if (Instruction_aarch64::extract(insns[0], 31, 21) == 0b11010010101) {
467 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
468 narrowKlass nk = (narrowKlass)((uint32_t(Instruction_aarch64::extract(insns[0], 20, 5)) << 16)
469 + uint32_t(Instruction_aarch64::extract(insns[1], 20, 5)));
470 target = (address)CompressedKlassPointers::decode(nk);
471 return 2;
472 }
473 assert(Instruction_aarch64::extract(insns[0], 31, 21) == 0b11010010100, "must be");
474 // Move wide constant: movz, movk, movk. See movptr().
475 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
476 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
477 target = address(uint64_t(Instruction_aarch64::extract(insns[0], 20, 5))
478 + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
479 + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
480 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
481 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
482 return 3;
483 }
484 static void verify(address insn_addr, address &target) {
485 }
486 };
487
488 address MacroAssembler::target_addr_for_insn(address insn_addr) {
489 address target;
490 RelocActions<AArch64Decoder>::run(insn_addr, target);
491 return target;
492 }
493
494 // Patch any kind of instruction; there may be several instructions.
495 // Return the total length (in bytes) of the instructions.
496 int MacroAssembler::pd_patch_instruction_size(address insn_addr, address target) {
497 return RelocActions<Patcher>::run(insn_addr, target);
498 }
499
500 int MacroAssembler::patch_oop(address insn_addr, address o) {
501 int instructions;
502 unsigned insn = *(unsigned*)insn_addr;
503 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
504
505 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
506 // narrow OOPs by setting the upper 16 bits in the first
507 // instruction.
508 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
509 // Move narrow OOP
510 uint32_t n = CompressedOops::narrow_oop_value(cast_to_oop(o));
511 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
512 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
513 instructions = 2;
514 } else {
515 // Move wide OOP
516 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
517 uintptr_t dest = (uintptr_t)o;
518 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
519 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
520 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
521 instructions = 3;
522 }
523 return instructions * NativeInstruction::instruction_size;
524 }
525
526 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
527 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
528 // We encode narrow ones by setting the upper 16 bits in the first
529 // instruction.
530 NativeInstruction *insn = nativeInstruction_at(insn_addr);
531 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 &&
532 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
533
534 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
535 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
536 return 2 * NativeInstruction::instruction_size;
537 }
538
539 address MacroAssembler::target_addr_for_insn_or_null(address insn_addr) {
540 if (NativeInstruction::is_ldrw_to_zr(insn_addr)) {
541 return nullptr;
542 }
543 return MacroAssembler::target_addr_for_insn(insn_addr);
544 }
545
546 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp) {
547 ldr(tmp, Address(rthread, JavaThread::polling_word_offset()));
548 if (at_return) {
549 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
550 // we may safely use the sp instead to perform the stack watermark check.
551 cmp(in_nmethod ? sp : rfp, tmp);
552 br(Assembler::HI, slow_path);
553 } else {
554 tbnz(tmp, log2i_exact(SafepointMechanism::poll_bit()), slow_path);
555 }
556 }
557
558 void MacroAssembler::rt_call(address dest, Register tmp) {
559 CodeBlob *cb = CodeCache::find_blob(dest);
560 if (cb) {
561 far_call(RuntimeAddress(dest));
562 } else {
563 lea(tmp, RuntimeAddress(dest));
564 blr(tmp);
565 }
566 }
567
568 void MacroAssembler::push_cont_fastpath(Register java_thread) {
569 if (!Continuations::enabled()) return;
570 Label done;
571 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
572 cmp(sp, rscratch1);
573 br(Assembler::LS, done);
574 mov(rscratch1, sp); // we can't use sp as the source in str
575 str(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
576 bind(done);
577 }
578
579 void MacroAssembler::pop_cont_fastpath(Register java_thread) {
580 if (!Continuations::enabled()) return;
581 Label done;
582 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
583 cmp(sp, rscratch1);
584 br(Assembler::LO, done);
585 str(zr, Address(java_thread, JavaThread::cont_fastpath_offset()));
586 bind(done);
587 }
588
589 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
590 // we must set sp to zero to clear frame
591 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
592
593 // must clear fp, so that compiled frames are not confused; it is
594 // possible that we need it only for debugging
595 if (clear_fp) {
596 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
597 }
598
599 // Always clear the pc because it could have been set by make_walkable()
600 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
601 }
602
603 // Calls to C land
604 //
605 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
606 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
607 // has to be reset to 0. This is required to allow proper stack traversal.
608 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
609 Register last_java_fp,
610 Register last_java_pc,
611 Register scratch) {
612
613 if (last_java_pc->is_valid()) {
614 str(last_java_pc, Address(rthread,
615 JavaThread::frame_anchor_offset()
616 + JavaFrameAnchor::last_Java_pc_offset()));
617 }
618
619 // determine last_java_sp register
620 if (last_java_sp == sp) {
621 mov(scratch, sp);
622 last_java_sp = scratch;
623 } else if (!last_java_sp->is_valid()) {
624 last_java_sp = esp;
625 }
626
627 // last_java_fp is optional
628 if (last_java_fp->is_valid()) {
629 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
630 }
631
632 // We must set sp last.
633 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
634 }
635
636 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
637 Register last_java_fp,
638 address last_java_pc,
639 Register scratch) {
640 assert(last_java_pc != nullptr, "must provide a valid PC");
641
642 adr(scratch, last_java_pc);
643 str(scratch, Address(rthread,
644 JavaThread::frame_anchor_offset()
645 + JavaFrameAnchor::last_Java_pc_offset()));
646
647 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
648 }
649
650 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
651 Register last_java_fp,
652 Label &L,
653 Register scratch) {
654 if (L.is_bound()) {
655 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
656 } else {
657 InstructionMark im(this);
658 L.add_patch_at(code(), locator());
659 set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, scratch);
660 }
661 }
662
663 static inline bool target_needs_far_branch(address addr) {
664 if (AOTCodeCache::is_on_for_dump()) {
665 return true;
666 }
667 // codecache size <= 128M
668 if (!MacroAssembler::far_branches()) {
669 return false;
670 }
671 // codecache size > 240M
672 if (MacroAssembler::codestub_branch_needs_far_jump()) {
673 return true;
674 }
675 // codecache size: 128M..240M
676 return !CodeCache::is_non_nmethod(addr);
677 }
678
679 void MacroAssembler::far_call(Address entry, Register tmp) {
680 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
681 assert(CodeCache::find_blob(entry.target()) != nullptr,
682 "destination of far call not found in code cache");
683 assert(entry.rspec().type() == relocInfo::external_word_type
684 || entry.rspec().type() == relocInfo::runtime_call_type
685 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
686 if (target_needs_far_branch(entry.target())) {
687 uint64_t offset;
688 // We can use ADRP here because we know that the total size of
689 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
690 adrp(tmp, entry, offset);
691 add(tmp, tmp, offset);
692 blr(tmp);
693 } else {
694 bl(entry);
695 }
696 }
697
698 int MacroAssembler::far_jump(Address entry, Register tmp) {
699 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
700 assert(CodeCache::find_blob(entry.target()) != nullptr,
701 "destination of far call not found in code cache");
702 assert(entry.rspec().type() == relocInfo::external_word_type
703 || entry.rspec().type() == relocInfo::runtime_call_type
704 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
705 address start = pc();
706 if (target_needs_far_branch(entry.target())) {
707 uint64_t offset;
708 // We can use ADRP here because we know that the total size of
709 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
710 adrp(tmp, entry, offset);
711 add(tmp, tmp, offset);
712 br(tmp);
713 } else {
714 b(entry);
715 }
716 return pc() - start;
717 }
718
719 void MacroAssembler::reserved_stack_check() {
720 // testing if reserved zone needs to be enabled
721 Label no_reserved_zone_enabling;
722
723 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset()));
724 cmp(sp, rscratch1);
725 br(Assembler::LO, no_reserved_zone_enabling);
726
727 enter(); // LR and FP are live.
728 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone)));
729 mov(c_rarg0, rthread);
730 blr(rscratch1);
731 leave();
732
733 // We have already removed our own frame.
734 // throw_delayed_StackOverflowError will think that it's been
735 // called by our caller.
736 lea(rscratch1, RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
737 br(rscratch1);
738 should_not_reach_here();
739
740 bind(no_reserved_zone_enabling);
741 }
742
743 static void pass_arg0(MacroAssembler* masm, Register arg) {
744 if (c_rarg0 != arg ) {
745 masm->mov(c_rarg0, arg);
746 }
747 }
748
749 static void pass_arg1(MacroAssembler* masm, Register arg) {
750 if (c_rarg1 != arg ) {
751 masm->mov(c_rarg1, arg);
752 }
753 }
754
755 static void pass_arg2(MacroAssembler* masm, Register arg) {
756 if (c_rarg2 != arg ) {
757 masm->mov(c_rarg2, arg);
758 }
759 }
760
761 static void pass_arg3(MacroAssembler* masm, Register arg) {
762 if (c_rarg3 != arg ) {
763 masm->mov(c_rarg3, arg);
764 }
765 }
766
767 void MacroAssembler::call_VM_base(Register oop_result,
768 Register java_thread,
769 Register last_java_sp,
770 Label* return_pc,
771 address entry_point,
772 int number_of_arguments,
773 bool check_exceptions) {
774 // determine java_thread register
775 if (!java_thread->is_valid()) {
776 java_thread = rthread;
777 }
778
779 // determine last_java_sp register
780 if (!last_java_sp->is_valid()) {
781 last_java_sp = esp;
782 }
783
784 // debugging support
785 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
786 assert(java_thread == rthread, "unexpected register");
787 #ifdef ASSERT
788 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
789 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
790 #endif // ASSERT
791
792 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
793 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
794
795 // push java thread (becomes first argument of C function)
796
797 mov(c_rarg0, java_thread);
798
799 // set last Java frame before call
800 assert(last_java_sp != rfp, "can't use rfp");
801
802 Label l;
803 set_last_Java_frame(last_java_sp, rfp, return_pc != nullptr ? *return_pc : l, rscratch1);
804
805 // do the call, remove parameters
806 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
807
808 // lr could be poisoned with PAC signature during throw_pending_exception
809 // if it was tail-call optimized by compiler, since lr is not callee-saved
810 // reload it with proper value
811 adr(lr, l);
812
813 // reset last Java frame
814 // Only interpreter should have to clear fp
815 reset_last_Java_frame(true);
816
817 // C++ interp handles this in the interpreter
818 check_and_handle_popframe(java_thread);
819 check_and_handle_earlyret(java_thread);
820
821 if (check_exceptions) {
822 // check for pending exceptions (java_thread is set upon return)
823 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
824 Label ok;
825 cbz(rscratch1, ok);
826 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
827 br(rscratch1);
828 bind(ok);
829 }
830
831 // get oop result if there is one and reset the value in the thread
832 if (oop_result->is_valid()) {
833 get_vm_result_oop(oop_result, java_thread);
834 }
835 }
836
837 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
838 call_VM_base(oop_result, noreg, noreg, nullptr, entry_point, number_of_arguments, check_exceptions);
839 }
840
841 // Check the entry target is always reachable from any branch.
842 static bool is_always_within_branch_range(Address entry) {
843 if (AOTCodeCache::is_on_for_dump()) {
844 return false;
845 }
846 const address target = entry.target();
847
848 if (!CodeCache::contains(target)) {
849 // We always use trampolines for callees outside CodeCache.
850 assert(entry.rspec().type() == relocInfo::runtime_call_type, "non-runtime call of an external target");
851 return false;
852 }
853
854 if (!MacroAssembler::far_branches()) {
855 return true;
856 }
857
858 if (entry.rspec().type() == relocInfo::runtime_call_type) {
859 // Runtime calls are calls of a non-compiled method (stubs, adapters).
860 // Non-compiled methods stay forever in CodeCache.
861 // We check whether the longest possible branch is within the branch range.
862 assert(CodeCache::find_blob(target) != nullptr &&
863 !CodeCache::find_blob(target)->is_nmethod(),
864 "runtime call of compiled method");
865 const address right_longest_branch_start = CodeCache::high_bound() - NativeInstruction::instruction_size;
866 const address left_longest_branch_start = CodeCache::low_bound();
867 const bool is_reachable = Assembler::reachable_from_branch_at(left_longest_branch_start, target) &&
868 Assembler::reachable_from_branch_at(right_longest_branch_start, target);
869 return is_reachable;
870 }
871
872 return false;
873 }
874
875 // Maybe emit a call via a trampoline. If the code cache is small
876 // trampolines won't be emitted.
877 address MacroAssembler::trampoline_call(Address entry) {
878 assert(entry.rspec().type() == relocInfo::runtime_call_type
879 || entry.rspec().type() == relocInfo::opt_virtual_call_type
880 || entry.rspec().type() == relocInfo::static_call_type
881 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
882
883 address target = entry.target();
884
885 if (!is_always_within_branch_range(entry)) {
886 if (!in_scratch_emit_size()) {
887 // We don't want to emit a trampoline if C2 is generating dummy
888 // code during its branch shortening phase.
889 if (entry.rspec().type() == relocInfo::runtime_call_type) {
890 assert(CodeBuffer::supports_shared_stubs(), "must support shared stubs");
891 code()->share_trampoline_for(entry.target(), offset());
892 } else {
893 address stub = emit_trampoline_stub(offset(), target);
894 if (stub == nullptr) {
895 postcond(pc() == badAddress);
896 return nullptr; // CodeCache is full
897 }
898 }
899 }
900 target = pc();
901 }
902
903 address call_pc = pc();
904 relocate(entry.rspec());
905 bl(target);
906
907 postcond(pc() != badAddress);
908 return call_pc;
909 }
910
911 // Emit a trampoline stub for a call to a target which is too far away.
912 //
913 // code sequences:
914 //
915 // call-site:
916 // branch-and-link to <destination> or <trampoline stub>
917 //
918 // Related trampoline stub for this call site in the stub section:
919 // load the call target from the constant pool
920 // branch (LR still points to the call site above)
921
922 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
923 address dest) {
924 // Max stub size: alignment nop, TrampolineStub.
925 address stub = start_a_stub(max_trampoline_stub_size());
926 if (stub == nullptr) {
927 return nullptr; // CodeBuffer::expand failed
928 }
929
930 // Create a trampoline stub relocation which relates this trampoline stub
931 // with the call instruction at insts_call_instruction_offset in the
932 // instructions code-section.
933 align(wordSize);
934 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
935 + insts_call_instruction_offset));
936 const int stub_start_offset = offset();
937
938 // Now, create the trampoline stub's code:
939 // - load the call
940 // - call
941 Label target;
942 ldr(rscratch1, target);
943 br(rscratch1);
944 bind(target);
945 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
946 "should be");
947 emit_int64((int64_t)dest);
948
949 const address stub_start_addr = addr_at(stub_start_offset);
950
951 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
952
953 end_a_stub();
954 return stub_start_addr;
955 }
956
957 int MacroAssembler::max_trampoline_stub_size() {
958 // Max stub size: alignment nop, TrampolineStub.
959 return NativeInstruction::instruction_size + NativeCallTrampolineStub::instruction_size;
960 }
961
962 void MacroAssembler::emit_static_call_stub() {
963 // CompiledDirectCall::set_to_interpreted knows the
964 // exact layout of this stub.
965
966 isb();
967 mov_metadata(rmethod, nullptr);
968
969 // Jump to the entry point of the c2i stub.
970 if (codestub_branch_needs_far_jump()) {
971 movptr(rscratch1, 0);
972 br(rscratch1);
973 } else {
974 b(pc());
975 }
976 }
977
978 int MacroAssembler::max_static_call_stub_size() {
979 // isb; movk; movz; movz; movk; movz; movz; br
980 return 8 * NativeInstruction::instruction_size;
981 }
982
983 void MacroAssembler::c2bool(Register x) {
984 // implements x == 0 ? 0 : 1
985 // note: must only look at least-significant byte of x
986 // since C-style booleans are stored in one byte
987 // only! (was bug)
988 tst(x, 0xff);
989 cset(x, Assembler::NE);
990 }
991
992 address MacroAssembler::ic_call(address entry, jint method_index) {
993 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
994 movptr(rscratch2, (intptr_t)Universe::non_oop_word());
995 return trampoline_call(Address(entry, rh));
996 }
997
998 int MacroAssembler::ic_check_size() {
999 int extra_instructions = UseCompactObjectHeaders ? 1 : 0;
1000 if (target_needs_far_branch(CAST_FROM_FN_PTR(address, SharedRuntime::get_ic_miss_stub()))) {
1001 return NativeInstruction::instruction_size * (7 + extra_instructions);
1002 } else {
1003 return NativeInstruction::instruction_size * (5 + extra_instructions);
1004 }
1005 }
1006
1007 int MacroAssembler::ic_check(int end_alignment) {
1008 Register receiver = j_rarg0;
1009 Register data = rscratch2;
1010 Register tmp1 = rscratch1;
1011 Register tmp2 = r10;
1012
1013 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1014 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1015 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1016 // before the inline cache check here, and not after
1017 align(end_alignment, offset() + ic_check_size());
1018
1019 int uep_offset = offset();
1020
1021 if (UseCompactObjectHeaders) {
1022 load_narrow_klass_compact(tmp1, receiver);
1023 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1024 cmpw(tmp1, tmp2);
1025 } else if (UseCompressedClassPointers) {
1026 ldrw(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1027 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1028 cmpw(tmp1, tmp2);
1029 } else {
1030 ldr(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1031 ldr(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1032 cmp(tmp1, tmp2);
1033 }
1034
1035 Label dont;
1036 br(Assembler::EQ, dont);
1037 far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1038 bind(dont);
1039 assert((offset() % end_alignment) == 0, "Misaligned verified entry point");
1040
1041 return uep_offset;
1042 }
1043
1044 // Implementation of call_VM versions
1045
1046 void MacroAssembler::call_VM(Register oop_result,
1047 address entry_point,
1048 bool check_exceptions) {
1049 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1050 }
1051
1052 void MacroAssembler::call_VM(Register oop_result,
1053 address entry_point,
1054 Register arg_1,
1055 bool check_exceptions) {
1056 pass_arg1(this, arg_1);
1057 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1058 }
1059
1060 void MacroAssembler::call_VM(Register oop_result,
1061 address entry_point,
1062 Register arg_1,
1063 Register arg_2,
1064 bool check_exceptions) {
1065 assert_different_registers(arg_1, c_rarg2);
1066 pass_arg2(this, arg_2);
1067 pass_arg1(this, arg_1);
1068 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1069 }
1070
1071 void MacroAssembler::call_VM(Register oop_result,
1072 address entry_point,
1073 Register arg_1,
1074 Register arg_2,
1075 Register arg_3,
1076 bool check_exceptions) {
1077 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1078 assert_different_registers(arg_2, c_rarg3);
1079 pass_arg3(this, arg_3);
1080
1081 pass_arg2(this, arg_2);
1082
1083 pass_arg1(this, arg_1);
1084 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1085 }
1086
1087 void MacroAssembler::call_VM(Register oop_result,
1088 Register last_java_sp,
1089 address entry_point,
1090 int number_of_arguments,
1091 bool check_exceptions) {
1092 call_VM_base(oop_result, rthread, last_java_sp, nullptr, entry_point, number_of_arguments, check_exceptions);
1093 }
1094
1095 void MacroAssembler::call_VM(Register oop_result,
1096 Register last_java_sp,
1097 address entry_point,
1098 Register arg_1,
1099 bool check_exceptions) {
1100 pass_arg1(this, arg_1);
1101 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1102 }
1103
1104 void MacroAssembler::call_VM(Register oop_result,
1105 Register last_java_sp,
1106 address entry_point,
1107 Register arg_1,
1108 Register arg_2,
1109 bool check_exceptions) {
1110
1111 assert_different_registers(arg_1, c_rarg2);
1112 pass_arg2(this, arg_2);
1113 pass_arg1(this, arg_1);
1114 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1115 }
1116
1117 void MacroAssembler::call_VM(Register oop_result,
1118 Register last_java_sp,
1119 address entry_point,
1120 Register arg_1,
1121 Register arg_2,
1122 Register arg_3,
1123 bool check_exceptions) {
1124 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1125 assert_different_registers(arg_2, c_rarg3);
1126 pass_arg3(this, arg_3);
1127 pass_arg2(this, arg_2);
1128 pass_arg1(this, arg_1);
1129 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1130 }
1131
1132
1133 void MacroAssembler::get_vm_result_oop(Register oop_result, Register java_thread) {
1134 ldr(oop_result, Address(java_thread, JavaThread::vm_result_oop_offset()));
1135 str(zr, Address(java_thread, JavaThread::vm_result_oop_offset()));
1136 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1137 }
1138
1139 void MacroAssembler::get_vm_result_metadata(Register metadata_result, Register java_thread) {
1140 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1141 str(zr, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1142 }
1143
1144 void MacroAssembler::align(int modulus) {
1145 align(modulus, offset());
1146 }
1147
1148 // Ensure that the code at target bytes offset from the current offset() is aligned
1149 // according to modulus.
1150 void MacroAssembler::align(int modulus, int target) {
1151 int delta = target - offset();
1152 while ((offset() + delta) % modulus != 0) nop();
1153 }
1154
1155 void MacroAssembler::post_call_nop() {
1156 if (!Continuations::enabled()) {
1157 return;
1158 }
1159 InstructionMark im(this);
1160 relocate(post_call_nop_Relocation::spec());
1161 InlineSkippedInstructionsCounter skipCounter(this);
1162 nop();
1163 movk(zr, 0);
1164 movk(zr, 0);
1165 }
1166
1167 // these are no-ops overridden by InterpreterMacroAssembler
1168
1169 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1170
1171 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1172
1173 // Look up the method for a megamorphic invokeinterface call.
1174 // The target method is determined by <intf_klass, itable_index>.
1175 // The receiver klass is in recv_klass.
1176 // On success, the result will be in method_result, and execution falls through.
1177 // On failure, execution transfers to the given label.
1178 void MacroAssembler::lookup_interface_method(Register recv_klass,
1179 Register intf_klass,
1180 RegisterOrConstant itable_index,
1181 Register method_result,
1182 Register scan_temp,
1183 Label& L_no_such_interface,
1184 bool return_method) {
1185 assert_different_registers(recv_klass, intf_klass, scan_temp);
1186 assert_different_registers(method_result, intf_klass, scan_temp);
1187 assert(recv_klass != method_result || !return_method,
1188 "recv_klass can be destroyed when method isn't needed");
1189 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1190 "caller must use same register for non-constant itable index as for method");
1191
1192 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1193 int vtable_base = in_bytes(Klass::vtable_start_offset());
1194 int itentry_off = in_bytes(itableMethodEntry::method_offset());
1195 int scan_step = itableOffsetEntry::size() * wordSize;
1196 int vte_size = vtableEntry::size_in_bytes();
1197 assert(vte_size == wordSize, "else adjust times_vte_scale");
1198
1199 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1200
1201 // Could store the aligned, prescaled offset in the klass.
1202 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
1203 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
1204 add(scan_temp, scan_temp, vtable_base);
1205
1206 if (return_method) {
1207 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1208 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1209 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
1210 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
1211 if (itentry_off)
1212 add(recv_klass, recv_klass, itentry_off);
1213 }
1214
1215 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
1216 // if (scan->interface() == intf) {
1217 // result = (klass + scan->offset() + itable_index);
1218 // }
1219 // }
1220 Label search, found_method;
1221
1222 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1223 cmp(intf_klass, method_result);
1224 br(Assembler::EQ, found_method);
1225 bind(search);
1226 // Check that the previous entry is non-null. A null entry means that
1227 // the receiver class doesn't implement the interface, and wasn't the
1228 // same as when the caller was compiled.
1229 cbz(method_result, L_no_such_interface);
1230 if (itableOffsetEntry::interface_offset() != 0) {
1231 add(scan_temp, scan_temp, scan_step);
1232 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1233 } else {
1234 ldr(method_result, Address(pre(scan_temp, scan_step)));
1235 }
1236 cmp(intf_klass, method_result);
1237 br(Assembler::NE, search);
1238
1239 bind(found_method);
1240
1241 // Got a hit.
1242 if (return_method) {
1243 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
1244 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0)));
1245 }
1246 }
1247
1248 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
1249 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
1250 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
1251 // The target method is determined by <holder_klass, itable_index>.
1252 // The receiver klass is in recv_klass.
1253 // On success, the result will be in method_result, and execution falls through.
1254 // On failure, execution transfers to the given label.
1255 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
1256 Register holder_klass,
1257 Register resolved_klass,
1258 Register method_result,
1259 Register temp_itbl_klass,
1260 Register scan_temp,
1261 int itable_index,
1262 Label& L_no_such_interface) {
1263 // 'method_result' is only used as output register at the very end of this method.
1264 // Until then we can reuse it as 'holder_offset'.
1265 Register holder_offset = method_result;
1266 assert_different_registers(resolved_klass, recv_klass, holder_klass, temp_itbl_klass, scan_temp, holder_offset);
1267
1268 int vtable_start_offset = in_bytes(Klass::vtable_start_offset());
1269 int itable_offset_entry_size = itableOffsetEntry::size() * wordSize;
1270 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
1271 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
1272
1273 Label L_loop_search_resolved_entry, L_resolved_found, L_holder_found;
1274
1275 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1276 add(recv_klass, recv_klass, vtable_start_offset + ioffset);
1277 // itableOffsetEntry[] itable = recv_klass + Klass::vtable_start_offset() + sizeof(vtableEntry) * recv_klass->_vtable_len;
1278 // temp_itbl_klass = itable[0]._interface;
1279 int vtblEntrySize = vtableEntry::size_in_bytes();
1280 assert(vtblEntrySize == wordSize, "ldr lsl shift amount must be 3");
1281 ldr(temp_itbl_klass, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1282 mov(holder_offset, zr);
1283 // scan_temp = &(itable[0]._interface)
1284 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1285
1286 // Initial checks:
1287 // - if (holder_klass != resolved_klass), go to "scan for resolved"
1288 // - if (itable[0] == holder_klass), shortcut to "holder found"
1289 // - if (itable[0] == 0), no such interface
1290 cmp(resolved_klass, holder_klass);
1291 br(Assembler::NE, L_loop_search_resolved_entry);
1292 cmp(holder_klass, temp_itbl_klass);
1293 br(Assembler::EQ, L_holder_found);
1294 cbz(temp_itbl_klass, L_no_such_interface);
1295
1296 // Loop: Look for holder_klass record in itable
1297 // do {
1298 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1299 // if (temp_itbl_klass == holder_klass) {
1300 // goto L_holder_found; // Found!
1301 // }
1302 // } while (temp_itbl_klass != 0);
1303 // goto L_no_such_interface // Not found.
1304 Label L_search_holder;
1305 bind(L_search_holder);
1306 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1307 cmp(holder_klass, temp_itbl_klass);
1308 br(Assembler::EQ, L_holder_found);
1309 cbnz(temp_itbl_klass, L_search_holder);
1310
1311 b(L_no_such_interface);
1312
1313 // Loop: Look for resolved_class record in itable
1314 // while (true) {
1315 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1316 // if (temp_itbl_klass == 0) {
1317 // goto L_no_such_interface;
1318 // }
1319 // if (temp_itbl_klass == resolved_klass) {
1320 // goto L_resolved_found; // Found!
1321 // }
1322 // if (temp_itbl_klass == holder_klass) {
1323 // holder_offset = scan_temp;
1324 // }
1325 // }
1326 //
1327 Label L_loop_search_resolved;
1328 bind(L_loop_search_resolved);
1329 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1330 bind(L_loop_search_resolved_entry);
1331 cbz(temp_itbl_klass, L_no_such_interface);
1332 cmp(resolved_klass, temp_itbl_klass);
1333 br(Assembler::EQ, L_resolved_found);
1334 cmp(holder_klass, temp_itbl_klass);
1335 br(Assembler::NE, L_loop_search_resolved);
1336 mov(holder_offset, scan_temp);
1337 b(L_loop_search_resolved);
1338
1339 // See if we already have a holder klass. If not, go and scan for it.
1340 bind(L_resolved_found);
1341 cbz(holder_offset, L_search_holder);
1342 mov(scan_temp, holder_offset);
1343
1344 // Finally, scan_temp contains holder_klass vtable offset
1345 bind(L_holder_found);
1346 ldrw(method_result, Address(scan_temp, ooffset - ioffset));
1347 add(recv_klass, recv_klass, itable_index * wordSize + in_bytes(itableMethodEntry::method_offset())
1348 - vtable_start_offset - ioffset); // substract offsets to restore the original value of recv_klass
1349 ldr(method_result, Address(recv_klass, method_result, Address::uxtw(0)));
1350 }
1351
1352 // virtual method calling
1353 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1354 RegisterOrConstant vtable_index,
1355 Register method_result) {
1356 assert(vtableEntry::size() * wordSize == 8,
1357 "adjust the scaling in the code below");
1358 int64_t vtable_offset_in_bytes = in_bytes(Klass::vtable_start_offset() + vtableEntry::method_offset());
1359
1360 if (vtable_index.is_register()) {
1361 lea(method_result, Address(recv_klass,
1362 vtable_index.as_register(),
1363 Address::lsl(LogBytesPerWord)));
1364 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
1365 } else {
1366 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
1367 ldr(method_result,
1368 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0));
1369 }
1370 }
1371
1372 void MacroAssembler::check_klass_subtype(Register sub_klass,
1373 Register super_klass,
1374 Register temp_reg,
1375 Label& L_success) {
1376 Label L_failure;
1377 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
1378 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
1379 bind(L_failure);
1380 }
1381
1382
1383 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1384 Register super_klass,
1385 Register temp_reg,
1386 Label* L_success,
1387 Label* L_failure,
1388 Label* L_slow_path,
1389 Register super_check_offset) {
1390 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset);
1391 bool must_load_sco = ! super_check_offset->is_valid();
1392 if (must_load_sco) {
1393 assert(temp_reg != noreg, "supply either a temp or a register offset");
1394 }
1395
1396 Label L_fallthrough;
1397 int label_nulls = 0;
1398 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1399 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1400 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
1401 assert(label_nulls <= 1, "at most one null in the batch");
1402
1403 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1404 Address super_check_offset_addr(super_klass, sco_offset);
1405
1406 // Hacked jmp, which may only be used just before L_fallthrough.
1407 #define final_jmp(label) \
1408 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1409 else b(label) /*omit semi*/
1410
1411 // If the pointers are equal, we are done (e.g., String[] elements).
1412 // This self-check enables sharing of secondary supertype arrays among
1413 // non-primary types such as array-of-interface. Otherwise, each such
1414 // type would need its own customized SSA.
1415 // We move this check to the front of the fast path because many
1416 // type checks are in fact trivially successful in this manner,
1417 // so we get a nicely predicted branch right at the start of the check.
1418 cmp(sub_klass, super_klass);
1419 br(Assembler::EQ, *L_success);
1420
1421 // Check the supertype display:
1422 if (must_load_sco) {
1423 ldrw(temp_reg, super_check_offset_addr);
1424 super_check_offset = temp_reg;
1425 }
1426
1427 Address super_check_addr(sub_klass, super_check_offset);
1428 ldr(rscratch1, super_check_addr);
1429 cmp(super_klass, rscratch1); // load displayed supertype
1430 br(Assembler::EQ, *L_success);
1431
1432 // This check has worked decisively for primary supers.
1433 // Secondary supers are sought in the super_cache ('super_cache_addr').
1434 // (Secondary supers are interfaces and very deeply nested subtypes.)
1435 // This works in the same check above because of a tricky aliasing
1436 // between the super_cache and the primary super display elements.
1437 // (The 'super_check_addr' can address either, as the case requires.)
1438 // Note that the cache is updated below if it does not help us find
1439 // what we need immediately.
1440 // So if it was a primary super, we can just fail immediately.
1441 // Otherwise, it's the slow path for us (no success at this point).
1442
1443 sub(rscratch1, super_check_offset, in_bytes(Klass::secondary_super_cache_offset()));
1444 if (L_failure == &L_fallthrough) {
1445 cbz(rscratch1, *L_slow_path);
1446 } else {
1447 cbnz(rscratch1, *L_failure);
1448 final_jmp(*L_slow_path);
1449 }
1450
1451 bind(L_fallthrough);
1452
1453 #undef final_jmp
1454 }
1455
1456 // These two are taken from x86, but they look generally useful
1457
1458 // scans count pointer sized words at [addr] for occurrence of value,
1459 // generic
1460 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1461 Register scratch) {
1462 Label Lloop, Lexit;
1463 cbz(count, Lexit);
1464 bind(Lloop);
1465 ldr(scratch, post(addr, wordSize));
1466 cmp(value, scratch);
1467 br(EQ, Lexit);
1468 sub(count, count, 1);
1469 cbnz(count, Lloop);
1470 bind(Lexit);
1471 }
1472
1473 // scans count 4 byte words at [addr] for occurrence of value,
1474 // generic
1475 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1476 Register scratch) {
1477 Label Lloop, Lexit;
1478 cbz(count, Lexit);
1479 bind(Lloop);
1480 ldrw(scratch, post(addr, wordSize));
1481 cmpw(value, scratch);
1482 br(EQ, Lexit);
1483 sub(count, count, 1);
1484 cbnz(count, Lloop);
1485 bind(Lexit);
1486 }
1487
1488 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
1489 Register super_klass,
1490 Register temp_reg,
1491 Register temp2_reg,
1492 Label* L_success,
1493 Label* L_failure,
1494 bool set_cond_codes) {
1495 // NB! Callers may assume that, when temp2_reg is a valid register,
1496 // this code sets it to a nonzero value.
1497
1498 assert_different_registers(sub_klass, super_klass, temp_reg);
1499 if (temp2_reg != noreg)
1500 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1501 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1502
1503 Label L_fallthrough;
1504 int label_nulls = 0;
1505 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1506 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1507 assert(label_nulls <= 1, "at most one null in the batch");
1508
1509 // a couple of useful fields in sub_klass:
1510 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1511 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1512 Address secondary_supers_addr(sub_klass, ss_offset);
1513 Address super_cache_addr( sub_klass, sc_offset);
1514
1515 BLOCK_COMMENT("check_klass_subtype_slow_path");
1516
1517 // Do a linear scan of the secondary super-klass chain.
1518 // This code is rarely used, so simplicity is a virtue here.
1519 // The repne_scan instruction uses fixed registers, which we must spill.
1520 // Don't worry too much about pre-existing connections with the input regs.
1521
1522 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1523 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1524
1525 RegSet pushed_registers;
1526 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1527 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1528
1529 if (super_klass != r0) {
1530 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1531 }
1532
1533 push(pushed_registers, sp);
1534
1535 // Get super_klass value into r0 (even if it was in r5 or r2).
1536 if (super_klass != r0) {
1537 mov(r0, super_klass);
1538 }
1539
1540 #ifndef PRODUCT
1541 incrementw(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
1542 #endif //PRODUCT
1543
1544 // We will consult the secondary-super array.
1545 ldr(r5, secondary_supers_addr);
1546 // Load the array length.
1547 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1548 // Skip to start of data.
1549 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1550
1551 cmp(sp, zr); // Clear Z flag; SP is never zero
1552 // Scan R2 words at [R5] for an occurrence of R0.
1553 // Set NZ/Z based on last compare.
1554 repne_scan(r5, r0, r2, rscratch1);
1555
1556 // Unspill the temp. registers:
1557 pop(pushed_registers, sp);
1558
1559 br(Assembler::NE, *L_failure);
1560
1561 // Success. Cache the super we found and proceed in triumph.
1562
1563 if (UseSecondarySupersCache) {
1564 str(super_klass, super_cache_addr);
1565 }
1566
1567 if (L_success != &L_fallthrough) {
1568 b(*L_success);
1569 }
1570
1571 #undef IS_A_TEMP
1572
1573 bind(L_fallthrough);
1574 }
1575
1576 // If Register r is invalid, remove a new register from
1577 // available_regs, and add new register to regs_to_push.
1578 Register MacroAssembler::allocate_if_noreg(Register r,
1579 RegSetIterator<Register> &available_regs,
1580 RegSet ®s_to_push) {
1581 if (!r->is_valid()) {
1582 r = *available_regs++;
1583 regs_to_push += r;
1584 }
1585 return r;
1586 }
1587
1588 // check_klass_subtype_slow_path_table() looks for super_klass in the
1589 // hash table belonging to super_klass, branching to L_success or
1590 // L_failure as appropriate. This is essentially a shim which
1591 // allocates registers as necessary then calls
1592 // lookup_secondary_supers_table() to do the work. Any of the temp
1593 // regs may be noreg, in which case this logic will chooses some
1594 // registers push and pop them from the stack.
1595 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
1596 Register super_klass,
1597 Register temp_reg,
1598 Register temp2_reg,
1599 Register temp3_reg,
1600 Register result_reg,
1601 FloatRegister vtemp,
1602 Label* L_success,
1603 Label* L_failure,
1604 bool set_cond_codes) {
1605 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
1606
1607 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1608
1609 Label L_fallthrough;
1610 int label_nulls = 0;
1611 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1612 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1613 assert(label_nulls <= 1, "at most one null in the batch");
1614
1615 BLOCK_COMMENT("check_klass_subtype_slow_path");
1616
1617 RegSetIterator<Register> available_regs
1618 = (RegSet::range(r0, r15) - temps - sub_klass - super_klass).begin();
1619
1620 RegSet pushed_regs;
1621
1622 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
1623 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
1624 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
1625 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
1626
1627 push(pushed_regs, sp);
1628
1629 lookup_secondary_supers_table_var(sub_klass,
1630 super_klass,
1631 temp_reg, temp2_reg, temp3_reg, vtemp, result_reg,
1632 nullptr);
1633 cmp(result_reg, zr);
1634
1635 // Unspill the temp. registers:
1636 pop(pushed_regs, sp);
1637
1638 // NB! Callers may assume that, when set_cond_codes is true, this
1639 // code sets temp2_reg to a nonzero value.
1640 if (set_cond_codes) {
1641 mov(temp2_reg, 1);
1642 }
1643
1644 br(Assembler::NE, *L_failure);
1645
1646 if (L_success != &L_fallthrough) {
1647 b(*L_success);
1648 }
1649
1650 bind(L_fallthrough);
1651 }
1652
1653 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1654 Register super_klass,
1655 Register temp_reg,
1656 Register temp2_reg,
1657 Label* L_success,
1658 Label* L_failure,
1659 bool set_cond_codes) {
1660 if (UseSecondarySupersTable) {
1661 check_klass_subtype_slow_path_table
1662 (sub_klass, super_klass, temp_reg, temp2_reg, /*temp3*/noreg, /*result*/noreg,
1663 /*vtemp*/fnoreg,
1664 L_success, L_failure, set_cond_codes);
1665 } else {
1666 check_klass_subtype_slow_path_linear
1667 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
1668 }
1669 }
1670
1671
1672 // Ensure that the inline code and the stub are using the same registers.
1673 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
1674 do { \
1675 assert(r_super_klass == r0 && \
1676 r_array_base == r1 && \
1677 r_array_length == r2 && \
1678 (r_array_index == r3 || r_array_index == noreg) && \
1679 (r_sub_klass == r4 || r_sub_klass == noreg) && \
1680 (r_bitmap == rscratch2 || r_bitmap == noreg) && \
1681 (result == r5 || result == noreg), "registers must match aarch64.ad"); \
1682 } while(0)
1683
1684 bool MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
1685 Register r_super_klass,
1686 Register temp1,
1687 Register temp2,
1688 Register temp3,
1689 FloatRegister vtemp,
1690 Register result,
1691 u1 super_klass_slot,
1692 bool stub_is_near) {
1693 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1694
1695 Label L_fallthrough;
1696
1697 BLOCK_COMMENT("lookup_secondary_supers_table {");
1698
1699 const Register
1700 r_array_base = temp1, // r1
1701 r_array_length = temp2, // r2
1702 r_array_index = temp3, // r3
1703 r_bitmap = rscratch2;
1704
1705 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1706
1707 u1 bit = super_klass_slot;
1708
1709 // Make sure that result is nonzero if the TBZ below misses.
1710 mov(result, 1);
1711
1712 // We're going to need the bitmap in a vector reg and in a core reg,
1713 // so load both now.
1714 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1715 if (bit != 0) {
1716 ldrd(vtemp, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1717 }
1718 // First check the bitmap to see if super_klass might be present. If
1719 // the bit is zero, we are certain that super_klass is not one of
1720 // the secondary supers.
1721 tbz(r_bitmap, bit, L_fallthrough);
1722
1723 // Get the first array index that can contain super_klass into r_array_index.
1724 if (bit != 0) {
1725 shld(vtemp, vtemp, Klass::SECONDARY_SUPERS_TABLE_MASK - bit);
1726 cnt(vtemp, T8B, vtemp);
1727 addv(vtemp, T8B, vtemp);
1728 fmovd(r_array_index, vtemp);
1729 } else {
1730 mov(r_array_index, (u1)1);
1731 }
1732 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1733
1734 // We will consult the secondary-super array.
1735 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1736
1737 // The value i in r_array_index is >= 1, so even though r_array_base
1738 // points to the length, we don't need to adjust it to point to the
1739 // data.
1740 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1741 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1742
1743 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1744 eor(result, result, r_super_klass);
1745 cbz(result, L_fallthrough); // Found a match
1746
1747 // Is there another entry to check? Consult the bitmap.
1748 tbz(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK, L_fallthrough);
1749
1750 // Linear probe.
1751 if (bit != 0) {
1752 ror(r_bitmap, r_bitmap, bit);
1753 }
1754
1755 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1756 // The next slot to be inspected, by the stub we're about to call,
1757 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1758 // have been checked.
1759 Address stub = RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub());
1760 if (stub_is_near) {
1761 bl(stub);
1762 } else {
1763 address call = trampoline_call(stub);
1764 if (call == nullptr) {
1765 return false; // trampoline allocation failed
1766 }
1767 }
1768
1769 BLOCK_COMMENT("} lookup_secondary_supers_table");
1770
1771 bind(L_fallthrough);
1772
1773 if (VerifySecondarySupers) {
1774 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1775 temp1, temp2, result); // r1, r2, r5
1776 }
1777 return true;
1778 }
1779
1780 // At runtime, return 0 in result if r_super_klass is a superclass of
1781 // r_sub_klass, otherwise return nonzero. Use this version of
1782 // lookup_secondary_supers_table() if you don't know ahead of time
1783 // which superclass will be searched for. Used by interpreter and
1784 // runtime stubs. It is larger and has somewhat greater latency than
1785 // the version above, which takes a constant super_klass_slot.
1786 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
1787 Register r_super_klass,
1788 Register temp1,
1789 Register temp2,
1790 Register temp3,
1791 FloatRegister vtemp,
1792 Register result,
1793 Label *L_success) {
1794 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1795
1796 Label L_fallthrough;
1797
1798 BLOCK_COMMENT("lookup_secondary_supers_table {");
1799
1800 const Register
1801 r_array_index = temp3,
1802 slot = rscratch1,
1803 r_bitmap = rscratch2;
1804
1805 ldrb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
1806
1807 // Make sure that result is nonzero if the test below misses.
1808 mov(result, 1);
1809
1810 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1811
1812 // First check the bitmap to see if super_klass might be present. If
1813 // the bit is zero, we are certain that super_klass is not one of
1814 // the secondary supers.
1815
1816 // This next instruction is equivalent to:
1817 // mov(tmp_reg, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1818 // sub(temp2, tmp_reg, slot);
1819 eor(temp2, slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1820 lslv(temp2, r_bitmap, temp2);
1821 tbz(temp2, Klass::SECONDARY_SUPERS_TABLE_SIZE - 1, L_fallthrough);
1822
1823 bool must_save_v0 = (vtemp == fnoreg);
1824 if (must_save_v0) {
1825 // temp1 and result are free, so use them to preserve vtemp
1826 vtemp = v0;
1827 mov(temp1, vtemp, D, 0);
1828 mov(result, vtemp, D, 1);
1829 }
1830
1831 // Get the first array index that can contain super_klass into r_array_index.
1832 mov(vtemp, D, 0, temp2);
1833 cnt(vtemp, T8B, vtemp);
1834 addv(vtemp, T8B, vtemp);
1835 mov(r_array_index, vtemp, D, 0);
1836
1837 if (must_save_v0) {
1838 mov(vtemp, D, 0, temp1 );
1839 mov(vtemp, D, 1, result);
1840 }
1841
1842 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1843
1844 const Register
1845 r_array_base = temp1,
1846 r_array_length = temp2;
1847
1848 // The value i in r_array_index is >= 1, so even though r_array_base
1849 // points to the length, we don't need to adjust it to point to the
1850 // data.
1851 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1852 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1853
1854 // We will consult the secondary-super array.
1855 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1856
1857 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1858 eor(result, result, r_super_klass);
1859 cbz(result, L_success ? *L_success : L_fallthrough); // Found a match
1860
1861 // Is there another entry to check? Consult the bitmap.
1862 rorv(r_bitmap, r_bitmap, slot);
1863 // rol(r_bitmap, r_bitmap, 1);
1864 tbz(r_bitmap, 1, L_fallthrough);
1865
1866 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1867 // The next slot to be inspected, by the logic we're about to call,
1868 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1869 // have been checked.
1870 lookup_secondary_supers_table_slow_path(r_super_klass, r_array_base, r_array_index,
1871 r_bitmap, r_array_length, result, /*is_stub*/false);
1872
1873 BLOCK_COMMENT("} lookup_secondary_supers_table");
1874
1875 bind(L_fallthrough);
1876
1877 if (VerifySecondarySupers) {
1878 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1879 temp1, temp2, result); // r1, r2, r5
1880 }
1881
1882 if (L_success) {
1883 cbz(result, *L_success);
1884 }
1885 }
1886
1887 // Called by code generated by check_klass_subtype_slow_path
1888 // above. This is called when there is a collision in the hashed
1889 // lookup in the secondary supers array.
1890 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
1891 Register r_array_base,
1892 Register r_array_index,
1893 Register r_bitmap,
1894 Register temp1,
1895 Register result,
1896 bool is_stub) {
1897 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, result, rscratch1);
1898
1899 const Register
1900 r_array_length = temp1,
1901 r_sub_klass = noreg; // unused
1902
1903 if (is_stub) {
1904 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1905 }
1906
1907 Label L_fallthrough, L_huge;
1908
1909 // Load the array length.
1910 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1911 // And adjust the array base to point to the data.
1912 // NB! Effectively increments current slot index by 1.
1913 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
1914 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1915
1916 // The bitmap is full to bursting.
1917 // Implicit invariant: BITMAP_FULL implies (length > 0)
1918 assert(Klass::SECONDARY_SUPERS_BITMAP_FULL == ~uintx(0), "");
1919 cmpw(r_array_length, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 2));
1920 br(GT, L_huge);
1921
1922 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
1923 // current slot (at secondary_supers[r_array_index]) has not yet
1924 // been inspected, and r_array_index may be out of bounds if we
1925 // wrapped around the end of the array.
1926
1927 { // This is conventional linear probing, but instead of terminating
1928 // when a null entry is found in the table, we maintain a bitmap
1929 // in which a 0 indicates missing entries.
1930 // As long as the bitmap is not completely full,
1931 // array_length == popcount(bitmap). The array_length check above
1932 // guarantees there are 0s in the bitmap, so the loop eventually
1933 // terminates.
1934 Label L_loop;
1935 bind(L_loop);
1936
1937 // Check for wraparound.
1938 cmp(r_array_index, r_array_length);
1939 csel(r_array_index, zr, r_array_index, GE);
1940
1941 ldr(rscratch1, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1942 eor(result, rscratch1, r_super_klass);
1943 cbz(result, L_fallthrough);
1944
1945 tbz(r_bitmap, 2, L_fallthrough); // look-ahead check (Bit 2); result is non-zero
1946
1947 ror(r_bitmap, r_bitmap, 1);
1948 add(r_array_index, r_array_index, 1);
1949 b(L_loop);
1950 }
1951
1952 { // Degenerate case: more than 64 secondary supers.
1953 // FIXME: We could do something smarter here, maybe a vectorized
1954 // comparison or a binary search, but is that worth any added
1955 // complexity?
1956 bind(L_huge);
1957 cmp(sp, zr); // Clear Z flag; SP is never zero
1958 repne_scan(r_array_base, r_super_klass, r_array_length, rscratch1);
1959 cset(result, NE); // result == 0 iff we got a match.
1960 }
1961
1962 bind(L_fallthrough);
1963 }
1964
1965 // Make sure that the hashed lookup and a linear scan agree.
1966 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
1967 Register r_super_klass,
1968 Register temp1,
1969 Register temp2,
1970 Register result) {
1971 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, result, rscratch1);
1972
1973 const Register
1974 r_array_base = temp1,
1975 r_array_length = temp2,
1976 r_array_index = noreg, // unused
1977 r_bitmap = noreg; // unused
1978
1979 BLOCK_COMMENT("verify_secondary_supers_table {");
1980
1981 // We will consult the secondary-super array.
1982 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1983
1984 // Load the array length.
1985 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1986 // And adjust the array base to point to the data.
1987 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1988
1989 cmp(sp, zr); // Clear Z flag; SP is never zero
1990 // Scan R2 words at [R5] for an occurrence of R0.
1991 // Set NZ/Z based on last compare.
1992 repne_scan(/*addr*/r_array_base, /*value*/r_super_klass, /*count*/r_array_length, rscratch2);
1993 // rscratch1 == 0 iff we got a match.
1994 cset(rscratch1, NE);
1995
1996 Label passed;
1997 cmp(result, zr);
1998 cset(result, NE); // normalize result to 0/1 for comparison
1999
2000 cmp(rscratch1, result);
2001 br(EQ, passed);
2002 {
2003 mov(r0, r_super_klass); // r0 <- r0
2004 mov(r1, r_sub_klass); // r1 <- r4
2005 mov(r2, /*expected*/rscratch1); // r2 <- r8
2006 mov(r3, result); // r3 <- r5
2007 mov(r4, (address)("mismatch")); // r4 <- const
2008 rt_call(CAST_FROM_FN_PTR(address, Klass::on_secondary_supers_verification_failure), rscratch2);
2009 should_not_reach_here();
2010 }
2011 bind(passed);
2012
2013 BLOCK_COMMENT("} verify_secondary_supers_table");
2014 }
2015
2016 void MacroAssembler::clinit_barrier(Register klass, Register scratch, Label* L_fast_path, Label* L_slow_path) {
2017 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
2018 assert_different_registers(klass, rthread, scratch);
2019
2020 Label L_fallthrough, L_tmp;
2021 if (L_fast_path == nullptr) {
2022 L_fast_path = &L_fallthrough;
2023 } else if (L_slow_path == nullptr) {
2024 L_slow_path = &L_fallthrough;
2025 }
2026 // Fast path check: class is fully initialized
2027 lea(scratch, Address(klass, InstanceKlass::init_state_offset()));
2028 ldarb(scratch, scratch);
2029 cmp(scratch, InstanceKlass::fully_initialized);
2030 br(Assembler::EQ, *L_fast_path);
2031
2032 // Fast path check: current thread is initializer thread
2033 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
2034 cmp(rthread, scratch);
2035
2036 if (L_slow_path == &L_fallthrough) {
2037 br(Assembler::EQ, *L_fast_path);
2038 bind(*L_slow_path);
2039 } else if (L_fast_path == &L_fallthrough) {
2040 br(Assembler::NE, *L_slow_path);
2041 bind(*L_fast_path);
2042 } else {
2043 Unimplemented();
2044 }
2045 }
2046
2047 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
2048 if (!VerifyOops) return;
2049
2050 // Pass register number to verify_oop_subroutine
2051 const char* b = nullptr;
2052 {
2053 ResourceMark rm;
2054 stringStream ss;
2055 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
2056 b = code_string(ss.as_string());
2057 }
2058 BLOCK_COMMENT("verify_oop {");
2059
2060 strip_return_address(); // This might happen within a stack frame.
2061 protect_return_address();
2062 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2063 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2064
2065 mov(r0, reg);
2066 movptr(rscratch1, (uintptr_t)(address)b);
2067
2068 // call indirectly to solve generation ordering problem
2069 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2070 ldr(rscratch2, Address(rscratch2));
2071 blr(rscratch2);
2072
2073 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2074 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2075 authenticate_return_address();
2076
2077 BLOCK_COMMENT("} verify_oop");
2078 }
2079
2080 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
2081 if (!VerifyOops) return;
2082
2083 const char* b = nullptr;
2084 {
2085 ResourceMark rm;
2086 stringStream ss;
2087 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
2088 b = code_string(ss.as_string());
2089 }
2090 BLOCK_COMMENT("verify_oop_addr {");
2091
2092 strip_return_address(); // This might happen within a stack frame.
2093 protect_return_address();
2094 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2095 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2096
2097 // addr may contain sp so we will have to adjust it based on the
2098 // pushes that we just did.
2099 if (addr.uses(sp)) {
2100 lea(r0, addr);
2101 ldr(r0, Address(r0, 4 * wordSize));
2102 } else {
2103 ldr(r0, addr);
2104 }
2105 movptr(rscratch1, (uintptr_t)(address)b);
2106
2107 // call indirectly to solve generation ordering problem
2108 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2109 ldr(rscratch2, Address(rscratch2));
2110 blr(rscratch2);
2111
2112 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2113 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2114 authenticate_return_address();
2115
2116 BLOCK_COMMENT("} verify_oop_addr");
2117 }
2118
2119 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
2120 int extra_slot_offset) {
2121 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
2122 int stackElementSize = Interpreter::stackElementSize;
2123 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
2124 #ifdef ASSERT
2125 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
2126 assert(offset1 - offset == stackElementSize, "correct arithmetic");
2127 #endif
2128 if (arg_slot.is_constant()) {
2129 return Address(esp, arg_slot.as_constant() * stackElementSize
2130 + offset);
2131 } else {
2132 add(rscratch1, esp, arg_slot.as_register(),
2133 ext::uxtx, exact_log2(stackElementSize));
2134 return Address(rscratch1, offset);
2135 }
2136 }
2137
2138 // Handle the receiver type profile update given the "recv" klass.
2139 //
2140 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
2141 // If there are no matching or claimable receiver entries in RD, updates
2142 // the polymorphic counter.
2143 //
2144 // This code expected to run by either the interpreter or JIT-ed code, without
2145 // extra synchronization. For safety, receiver cells are claimed atomically, which
2146 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
2147 // counter updates are not atomic.
2148 //
2149 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
2150 assert_different_registers(recv, mdp, rscratch1, rscratch2);
2151
2152 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
2153 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
2154 int poly_count_offset = in_bytes(CounterData::count_offset());
2155 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
2156 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
2157
2158 // Adjust for MDP offsets.
2159 base_receiver_offset += mdp_offset;
2160 end_receiver_offset += mdp_offset;
2161 poly_count_offset += mdp_offset;
2162
2163 #ifdef ASSERT
2164 // We are about to walk the MDO slots without asking for offsets.
2165 // Check that our math hits all the right spots.
2166 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
2167 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
2168 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
2169 int offset = base_receiver_offset + receiver_step*c;
2170 int count_offset = offset + receiver_to_count_step;
2171 assert(offset == real_recv_offset, "receiver slot math");
2172 assert(count_offset == real_count_offset, "receiver count math");
2173 }
2174 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
2175 assert(poly_count_offset == real_poly_count_offset, "poly counter math");
2176 #endif
2177
2178 // Corner case: no profile table. Increment poly counter and exit.
2179 if (ReceiverTypeData::row_limit() == 0) {
2180 increment(Address(mdp, poly_count_offset), DataLayout::counter_increment);
2181 return;
2182 }
2183
2184 Register offset = rscratch2;
2185
2186 Label L_loop_search_receiver, L_loop_search_empty;
2187 Label L_restart, L_found_recv, L_found_empty, L_polymorphic, L_count_update;
2188
2189 // The code here recognizes three major cases:
2190 // A. Fastest: receiver found in the table
2191 // B. Fast: no receiver in the table, and the table is full
2192 // C. Slow: no receiver in the table, free slots in the table
2193 //
2194 // The case A performance is most important, as perfectly-behaved code would end up
2195 // there, especially with larger TypeProfileWidth. The case B performance is
2196 // important as well, this is where bulk of code would land for normally megamorphic
2197 // cases. The case C performance is not essential, its job is to deal with installation
2198 // races, we optimize for code density instead. Case C needs to make sure that receiver
2199 // rows are only claimed once. This makes sure we never overwrite a row for another
2200 // receiver and never duplicate the receivers in the list, making profile type-accurate.
2201 //
2202 // It is very tempting to handle these cases in a single loop, and claim the first slot
2203 // without checking the rest of the table. But, profiling code should tolerate free slots
2204 // in the table, as class unloading can clear them. After such cleanup, the receiver
2205 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
2206 // to complete, before trying to install new slots. Splitting the code in several tight
2207 // loops also helpfully optimizes for cases A and B.
2208 //
2209 // This code is effectively:
2210 //
2211 // restart:
2212 // // Fastest: receiver is already installed
2213 // for (i = 0; i < receiver_count(); i++) {
2214 // if (receiver(i) == recv) goto found_recv(i);
2215 // }
2216 //
2217 // // Fast: no receiver, but profile is full
2218 // for (i = 0; i < receiver_count(); i++) {
2219 // if (receiver(i) == null) goto found_null(i);
2220 // }
2221 // goto polymorphic
2222 //
2223 // // Slow: try to install receiver
2224 // found_null(i):
2225 // CAS(&receiver(i), null, recv);
2226 // goto restart
2227 //
2228 // polymorphic:
2229 // count++;
2230 // return
2231 //
2232 // found_recv(i):
2233 // *receiver_count(i)++
2234 //
2235
2236 bind(L_restart);
2237
2238 // Fastest: receiver is already installed
2239 mov(offset, base_receiver_offset);
2240 bind(L_loop_search_receiver);
2241 ldr(rscratch1, Address(mdp, offset));
2242 cmp(rscratch1, recv);
2243 br(Assembler::EQ, L_found_recv);
2244 add(offset, offset, receiver_step);
2245 sub(rscratch1, offset, end_receiver_offset);
2246 cbnz(rscratch1, L_loop_search_receiver);
2247
2248 // Fast: no receiver, but profile is full
2249 mov(offset, base_receiver_offset);
2250 bind(L_loop_search_empty);
2251 ldr(rscratch1, Address(mdp, offset));
2252 cbz(rscratch1, L_found_empty);
2253 add(offset, offset, receiver_step);
2254 sub(rscratch1, offset, end_receiver_offset);
2255 cbnz(rscratch1, L_loop_search_empty);
2256 b(L_polymorphic);
2257
2258 // Slow: try to install receiver
2259 bind(L_found_empty);
2260
2261 // Atomically swing receiver slot: null -> recv.
2262 //
2263 // The update uses CAS, which clobbers rscratch1. Therefore, rscratch2
2264 // is used to hold the destination address. This is safe because the
2265 // offset is no longer needed after the address is computed.
2266
2267 lea(rscratch2, Address(mdp, offset));
2268 cmpxchg(/*addr*/ rscratch2, /*expected*/ zr, /*new*/ recv, Assembler::xword,
2269 /*acquire*/ false, /*release*/ false, /*weak*/ true, noreg);
2270
2271 // CAS success means the slot now has the receiver we want. CAS failure means
2272 // something had claimed the slot concurrently: it can be the same receiver we want,
2273 // or something else. Since this is a slow path, we can optimize for code density,
2274 // and just restart the search from the beginning.
2275 b(L_restart);
2276
2277 // Counter updates:
2278
2279 // Increment polymorphic counter instead of receiver slot.
2280 bind(L_polymorphic);
2281 mov(offset, poly_count_offset);
2282 b(L_count_update);
2283
2284 // Found a receiver, convert its slot offset to corresponding count offset.
2285 bind(L_found_recv);
2286 add(offset, offset, receiver_to_count_step);
2287
2288 bind(L_count_update);
2289 increment(Address(mdp, offset), DataLayout::counter_increment);
2290 }
2291
2292
2293 void MacroAssembler::call_VM_leaf_base(address entry_point,
2294 int number_of_arguments,
2295 Label *retaddr) {
2296 Label E, L;
2297
2298 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
2299
2300 mov(rscratch1, RuntimeAddress(entry_point));
2301 blr(rscratch1);
2302 if (retaddr)
2303 bind(*retaddr);
2304
2305 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
2306 }
2307
2308 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2309 call_VM_leaf_base(entry_point, number_of_arguments);
2310 }
2311
2312 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2313 pass_arg0(this, arg_0);
2314 call_VM_leaf_base(entry_point, 1);
2315 }
2316
2317 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2318 assert_different_registers(arg_1, c_rarg0);
2319 pass_arg0(this, arg_0);
2320 pass_arg1(this, arg_1);
2321 call_VM_leaf_base(entry_point, 2);
2322 }
2323
2324 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
2325 Register arg_1, Register arg_2) {
2326 assert_different_registers(arg_1, c_rarg0);
2327 assert_different_registers(arg_2, c_rarg0, c_rarg1);
2328 pass_arg0(this, arg_0);
2329 pass_arg1(this, arg_1);
2330 pass_arg2(this, arg_2);
2331 call_VM_leaf_base(entry_point, 3);
2332 }
2333
2334 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2335 pass_arg0(this, arg_0);
2336 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2337 }
2338
2339 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2340
2341 assert_different_registers(arg_0, c_rarg1);
2342 pass_arg1(this, arg_1);
2343 pass_arg0(this, arg_0);
2344 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2345 }
2346
2347 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2348 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2349 assert_different_registers(arg_1, c_rarg2);
2350 pass_arg2(this, arg_2);
2351 pass_arg1(this, arg_1);
2352 pass_arg0(this, arg_0);
2353 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2354 }
2355
2356 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2357 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
2358 assert_different_registers(arg_1, c_rarg2, c_rarg3);
2359 assert_different_registers(arg_2, c_rarg3);
2360 pass_arg3(this, arg_3);
2361 pass_arg2(this, arg_2);
2362 pass_arg1(this, arg_1);
2363 pass_arg0(this, arg_0);
2364 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2365 }
2366
2367 void MacroAssembler::null_check(Register reg, int offset) {
2368 if (needs_explicit_null_check(offset)) {
2369 // provoke OS null exception if reg is null by
2370 // accessing M[reg] w/o changing any registers
2371 // NOTE: this is plenty to provoke a segv
2372 ldr(zr, Address(reg));
2373 } else {
2374 // nothing to do, (later) access of M[reg + offset]
2375 // will provoke OS null exception if reg is null
2376 }
2377 }
2378
2379 // MacroAssembler protected routines needed to implement
2380 // public methods
2381
2382 void MacroAssembler::mov(Register r, Address dest) {
2383 code_section()->relocate(pc(), dest.rspec());
2384 uint64_t imm64 = (uint64_t)dest.target();
2385 movptr(r, imm64);
2386 }
2387
2388 // Move a constant pointer into r. In AArch64 mode the virtual
2389 // address space is 48 bits in size, so we only need three
2390 // instructions to create a patchable instruction sequence that can
2391 // reach anywhere.
2392 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2393 #ifndef PRODUCT
2394 {
2395 char buffer[64];
2396 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2397 block_comment(buffer);
2398 }
2399 #endif
2400 assert(imm64 < (1ull << 48), "48-bit overflow in address constant");
2401 movz(r, imm64 & 0xffff);
2402 imm64 >>= 16;
2403 movk(r, imm64 & 0xffff, 16);
2404 imm64 >>= 16;
2405 movk(r, imm64 & 0xffff, 32);
2406 }
2407
2408 // Macro to mov replicated immediate to vector register.
2409 // imm64: only the lower 8/16/32 bits are considered for B/H/S type. That is,
2410 // the upper 56/48/32 bits must be zeros for B/H/S type.
2411 // Vd will get the following values for different arrangements in T
2412 // imm64 == hex 000000gh T8B: Vd = ghghghghghghghgh
2413 // imm64 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
2414 // imm64 == hex 0000efgh T4H: Vd = efghefghefghefgh
2415 // imm64 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
2416 // imm64 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
2417 // imm64 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
2418 // imm64 == hex abcdefgh T1D: Vd = 00000000abcdefgh
2419 // imm64 == hex abcdefgh T2D: Vd = 00000000abcdefgh00000000abcdefgh
2420 // Clobbers rscratch1
2421 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64) {
2422 assert(T != T1Q, "unsupported");
2423 if (T == T1D || T == T2D) {
2424 int imm = operand_valid_for_movi_immediate(imm64, T);
2425 if (-1 != imm) {
2426 movi(Vd, T, imm);
2427 } else {
2428 mov(rscratch1, imm64);
2429 dup(Vd, T, rscratch1);
2430 }
2431 return;
2432 }
2433
2434 #ifdef ASSERT
2435 if (T == T8B || T == T16B) assert((imm64 & ~0xff) == 0, "extraneous bits (T8B/T16B)");
2436 if (T == T4H || T == T8H) assert((imm64 & ~0xffff) == 0, "extraneous bits (T4H/T8H)");
2437 if (T == T2S || T == T4S) assert((imm64 & ~0xffffffff) == 0, "extraneous bits (T2S/T4S)");
2438 #endif
2439 int shift = operand_valid_for_movi_immediate(imm64, T);
2440 uint32_t imm32 = imm64 & 0xffffffffULL;
2441 if (shift >= 0) {
2442 movi(Vd, T, (imm32 >> shift) & 0xff, shift);
2443 } else {
2444 movw(rscratch1, imm32);
2445 dup(Vd, T, rscratch1);
2446 }
2447 }
2448
2449 void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64)
2450 {
2451 #ifndef PRODUCT
2452 {
2453 char buffer[64];
2454 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, imm64);
2455 block_comment(buffer);
2456 }
2457 #endif
2458 if (operand_valid_for_logical_immediate(false, imm64)) {
2459 orr(dst, zr, imm64);
2460 } else {
2461 // we can use a combination of MOVZ or MOVN with
2462 // MOVK to build up the constant
2463 uint64_t imm_h[4];
2464 int zero_count = 0;
2465 int neg_count = 0;
2466 int i;
2467 for (i = 0; i < 4; i++) {
2468 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
2469 if (imm_h[i] == 0) {
2470 zero_count++;
2471 } else if (imm_h[i] == 0xffffL) {
2472 neg_count++;
2473 }
2474 }
2475 if (zero_count == 4) {
2476 // one MOVZ will do
2477 movz(dst, 0);
2478 } else if (neg_count == 4) {
2479 // one MOVN will do
2480 movn(dst, 0);
2481 } else if (zero_count == 3) {
2482 for (i = 0; i < 4; i++) {
2483 if (imm_h[i] != 0L) {
2484 movz(dst, (uint32_t)imm_h[i], (i << 4));
2485 break;
2486 }
2487 }
2488 } else if (neg_count == 3) {
2489 // one MOVN will do
2490 for (int i = 0; i < 4; i++) {
2491 if (imm_h[i] != 0xffffL) {
2492 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2493 break;
2494 }
2495 }
2496 } else if (zero_count == 2) {
2497 // one MOVZ and one MOVK will do
2498 for (i = 0; i < 3; i++) {
2499 if (imm_h[i] != 0L) {
2500 movz(dst, (uint32_t)imm_h[i], (i << 4));
2501 i++;
2502 break;
2503 }
2504 }
2505 for (;i < 4; i++) {
2506 if (imm_h[i] != 0L) {
2507 movk(dst, (uint32_t)imm_h[i], (i << 4));
2508 }
2509 }
2510 } else if (neg_count == 2) {
2511 // one MOVN and one MOVK will do
2512 for (i = 0; i < 4; i++) {
2513 if (imm_h[i] != 0xffffL) {
2514 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2515 i++;
2516 break;
2517 }
2518 }
2519 for (;i < 4; i++) {
2520 if (imm_h[i] != 0xffffL) {
2521 movk(dst, (uint32_t)imm_h[i], (i << 4));
2522 }
2523 }
2524 } else if (zero_count == 1) {
2525 // one MOVZ and two MOVKs will do
2526 for (i = 0; i < 4; i++) {
2527 if (imm_h[i] != 0L) {
2528 movz(dst, (uint32_t)imm_h[i], (i << 4));
2529 i++;
2530 break;
2531 }
2532 }
2533 for (;i < 4; i++) {
2534 if (imm_h[i] != 0x0L) {
2535 movk(dst, (uint32_t)imm_h[i], (i << 4));
2536 }
2537 }
2538 } else if (neg_count == 1) {
2539 // one MOVN and two MOVKs will do
2540 for (i = 0; i < 4; i++) {
2541 if (imm_h[i] != 0xffffL) {
2542 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2543 i++;
2544 break;
2545 }
2546 }
2547 for (;i < 4; i++) {
2548 if (imm_h[i] != 0xffffL) {
2549 movk(dst, (uint32_t)imm_h[i], (i << 4));
2550 }
2551 }
2552 } else {
2553 // use a MOVZ and 3 MOVKs (makes it easier to debug)
2554 movz(dst, (uint32_t)imm_h[0], 0);
2555 for (i = 1; i < 4; i++) {
2556 movk(dst, (uint32_t)imm_h[i], (i << 4));
2557 }
2558 }
2559 }
2560 }
2561
2562 void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32)
2563 {
2564 #ifndef PRODUCT
2565 {
2566 char buffer[64];
2567 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX32, imm32);
2568 block_comment(buffer);
2569 }
2570 #endif
2571 if (operand_valid_for_logical_immediate(true, imm32)) {
2572 orrw(dst, zr, imm32);
2573 } else {
2574 // we can use MOVZ, MOVN or two calls to MOVK to build up the
2575 // constant
2576 uint32_t imm_h[2];
2577 imm_h[0] = imm32 & 0xffff;
2578 imm_h[1] = ((imm32 >> 16) & 0xffff);
2579 if (imm_h[0] == 0) {
2580 movzw(dst, imm_h[1], 16);
2581 } else if (imm_h[0] == 0xffff) {
2582 movnw(dst, imm_h[1] ^ 0xffff, 16);
2583 } else if (imm_h[1] == 0) {
2584 movzw(dst, imm_h[0], 0);
2585 } else if (imm_h[1] == 0xffff) {
2586 movnw(dst, imm_h[0] ^ 0xffff, 0);
2587 } else {
2588 // use a MOVZ and MOVK (makes it easier to debug)
2589 movzw(dst, imm_h[0], 0);
2590 movkw(dst, imm_h[1], 16);
2591 }
2592 }
2593 }
2594
2595 // Form an address from base + offset in Rd. Rd may or may
2596 // not actually be used: you must use the Address that is returned.
2597 // It is up to you to ensure that the shift provided matches the size
2598 // of your data.
2599 Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) {
2600 if (Address::offset_ok_for_immed(byte_offset, shift))
2601 // It fits; no need for any heroics
2602 return Address(base, byte_offset);
2603
2604 // Don't do anything clever with negative or misaligned offsets
2605 unsigned mask = (1 << shift) - 1;
2606 if (byte_offset < 0 || byte_offset & mask) {
2607 mov(Rd, byte_offset);
2608 add(Rd, base, Rd);
2609 return Address(Rd);
2610 }
2611
2612 // See if we can do this with two 12-bit offsets
2613 {
2614 uint64_t word_offset = byte_offset >> shift;
2615 uint64_t masked_offset = word_offset & 0xfff000;
2616 if (Address::offset_ok_for_immed(word_offset - masked_offset, 0)
2617 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
2618 add(Rd, base, masked_offset << shift);
2619 word_offset -= masked_offset;
2620 return Address(Rd, word_offset << shift);
2621 }
2622 }
2623
2624 // Do it the hard way
2625 mov(Rd, byte_offset);
2626 add(Rd, base, Rd);
2627 return Address(Rd);
2628 }
2629
2630 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
2631 bool want_remainder, Register scratch)
2632 {
2633 // Full implementation of Java idiv and irem. The function
2634 // returns the (pc) offset of the div instruction - may be needed
2635 // for implicit exceptions.
2636 //
2637 // constraint : ra/rb =/= scratch
2638 // normal case
2639 //
2640 // input : ra: dividend
2641 // rb: divisor
2642 //
2643 // result: either
2644 // quotient (= ra idiv rb)
2645 // remainder (= ra irem rb)
2646
2647 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2648
2649 int idivl_offset = offset();
2650 if (! want_remainder) {
2651 sdivw(result, ra, rb);
2652 } else {
2653 sdivw(scratch, ra, rb);
2654 Assembler::msubw(result, scratch, rb, ra);
2655 }
2656
2657 return idivl_offset;
2658 }
2659
2660 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
2661 bool want_remainder, Register scratch)
2662 {
2663 // Full implementation of Java ldiv and lrem. The function
2664 // returns the (pc) offset of the div instruction - may be needed
2665 // for implicit exceptions.
2666 //
2667 // constraint : ra/rb =/= scratch
2668 // normal case
2669 //
2670 // input : ra: dividend
2671 // rb: divisor
2672 //
2673 // result: either
2674 // quotient (= ra idiv rb)
2675 // remainder (= ra irem rb)
2676
2677 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2678
2679 int idivq_offset = offset();
2680 if (! want_remainder) {
2681 sdiv(result, ra, rb);
2682 } else {
2683 sdiv(scratch, ra, rb);
2684 Assembler::msub(result, scratch, rb, ra);
2685 }
2686
2687 return idivq_offset;
2688 }
2689
2690 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
2691 address prev = pc() - NativeMembar::instruction_size;
2692 address last = code()->last_insn();
2693 if (last != nullptr && nativeInstruction_at(last)->is_Membar() && prev == last) {
2694 NativeMembar *bar = NativeMembar_at(prev);
2695 if (AlwaysMergeDMB) {
2696 bar->set_kind(bar->get_kind() | order_constraint);
2697 BLOCK_COMMENT("merged membar(always)");
2698 return;
2699 }
2700 // Don't promote DMB ST|DMB LD to DMB (a full barrier) because
2701 // doing so would introduce a StoreLoad which the caller did not
2702 // intend
2703 if (bar->get_kind() == order_constraint
2704 || bar->get_kind() == AnyAny
2705 || order_constraint == AnyAny) {
2706 // We are merging two memory barrier instructions. On AArch64 we
2707 // can do this simply by ORing them together.
2708 bar->set_kind(bar->get_kind() | order_constraint);
2709 BLOCK_COMMENT("merged membar");
2710 return;
2711 } else {
2712 // A special case like "DMB ST;DMB LD;DMB ST", the last DMB can be skipped
2713 // We need check the last 2 instructions
2714 address prev2 = prev - NativeMembar::instruction_size;
2715 if (last != code()->last_label() && nativeInstruction_at(prev2)->is_Membar()) {
2716 NativeMembar *bar2 = NativeMembar_at(prev2);
2717 assert(bar2->get_kind() == order_constraint, "it should be merged before");
2718 BLOCK_COMMENT("merged membar(elided)");
2719 return;
2720 }
2721 }
2722 }
2723 code()->set_last_insn(pc());
2724 dmb(Assembler::barrier(order_constraint));
2725 }
2726
2727 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) {
2728 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) {
2729 merge_ldst(rt, adr, size_in_bytes, is_store);
2730 code()->clear_last_insn();
2731 return true;
2732 } else {
2733 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported.");
2734 const uint64_t mask = size_in_bytes - 1;
2735 if (adr.getMode() == Address::base_plus_offset &&
2736 (adr.offset() & mask) == 0) { // only supports base_plus_offset.
2737 code()->set_last_insn(pc());
2738 }
2739 return false;
2740 }
2741 }
2742
2743 void MacroAssembler::ldr(Register Rx, const Address &adr) {
2744 // We always try to merge two adjacent loads into one ldp.
2745 if (!try_merge_ldst(Rx, adr, 8, false)) {
2746 Assembler::ldr(Rx, adr);
2747 }
2748 }
2749
2750 void MacroAssembler::ldrw(Register Rw, const Address &adr) {
2751 // We always try to merge two adjacent loads into one ldp.
2752 if (!try_merge_ldst(Rw, adr, 4, false)) {
2753 Assembler::ldrw(Rw, adr);
2754 }
2755 }
2756
2757 void MacroAssembler::str(Register Rx, const Address &adr) {
2758 // We always try to merge two adjacent stores into one stp.
2759 if (!try_merge_ldst(Rx, adr, 8, true)) {
2760 Assembler::str(Rx, adr);
2761 }
2762 }
2763
2764 void MacroAssembler::strw(Register Rw, const Address &adr) {
2765 // We always try to merge two adjacent stores into one stp.
2766 if (!try_merge_ldst(Rw, adr, 4, true)) {
2767 Assembler::strw(Rw, adr);
2768 }
2769 }
2770
2771 // MacroAssembler routines found actually to be needed
2772
2773 void MacroAssembler::push(Register src)
2774 {
2775 str(src, Address(pre(esp, -1 * wordSize)));
2776 }
2777
2778 void MacroAssembler::pop(Register dst)
2779 {
2780 ldr(dst, Address(post(esp, 1 * wordSize)));
2781 }
2782
2783 // Note: load_unsigned_short used to be called load_unsigned_word.
2784 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2785 int off = offset();
2786 ldrh(dst, src);
2787 return off;
2788 }
2789
2790 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2791 int off = offset();
2792 ldrb(dst, src);
2793 return off;
2794 }
2795
2796 int MacroAssembler::load_signed_short(Register dst, Address src) {
2797 int off = offset();
2798 ldrsh(dst, src);
2799 return off;
2800 }
2801
2802 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2803 int off = offset();
2804 ldrsb(dst, src);
2805 return off;
2806 }
2807
2808 int MacroAssembler::load_signed_short32(Register dst, Address src) {
2809 int off = offset();
2810 ldrshw(dst, src);
2811 return off;
2812 }
2813
2814 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
2815 int off = offset();
2816 ldrsbw(dst, src);
2817 return off;
2818 }
2819
2820 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) {
2821 switch (size_in_bytes) {
2822 case 8: ldr(dst, src); break;
2823 case 4: ldrw(dst, src); break;
2824 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2825 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2826 default: ShouldNotReachHere();
2827 }
2828 }
2829
2830 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes) {
2831 switch (size_in_bytes) {
2832 case 8: str(src, dst); break;
2833 case 4: strw(src, dst); break;
2834 case 2: strh(src, dst); break;
2835 case 1: strb(src, dst); break;
2836 default: ShouldNotReachHere();
2837 }
2838 }
2839
2840 void MacroAssembler::decrementw(Register reg, int value)
2841 {
2842 if (value < 0) { incrementw(reg, -value); return; }
2843 if (value == 0) { return; }
2844 if (value < (1 << 12)) { subw(reg, reg, value); return; }
2845 /* else */ {
2846 guarantee(reg != rscratch2, "invalid dst for register decrement");
2847 movw(rscratch2, (unsigned)value);
2848 subw(reg, reg, rscratch2);
2849 }
2850 }
2851
2852 void MacroAssembler::decrement(Register reg, int value)
2853 {
2854 if (value < 0) { increment(reg, -value); return; }
2855 if (value == 0) { return; }
2856 if (value < (1 << 12)) { sub(reg, reg, value); return; }
2857 /* else */ {
2858 assert(reg != rscratch2, "invalid dst for register decrement");
2859 mov(rscratch2, (uint64_t)value);
2860 sub(reg, reg, rscratch2);
2861 }
2862 }
2863
2864 void MacroAssembler::decrementw(Address dst, int value)
2865 {
2866 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
2867 if (dst.getMode() == Address::literal) {
2868 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2869 lea(rscratch2, dst);
2870 dst = Address(rscratch2);
2871 }
2872 ldrw(rscratch1, dst);
2873 decrementw(rscratch1, value);
2874 strw(rscratch1, dst);
2875 }
2876
2877 void MacroAssembler::decrement(Address dst, int value)
2878 {
2879 assert(!dst.uses(rscratch1), "invalid address for decrement");
2880 if (dst.getMode() == Address::literal) {
2881 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2882 lea(rscratch2, dst);
2883 dst = Address(rscratch2);
2884 }
2885 ldr(rscratch1, dst);
2886 decrement(rscratch1, value);
2887 str(rscratch1, dst);
2888 }
2889
2890 void MacroAssembler::incrementw(Register reg, int value)
2891 {
2892 if (value < 0) { decrementw(reg, -value); return; }
2893 if (value == 0) { return; }
2894 if (value < (1 << 12)) { addw(reg, reg, value); return; }
2895 /* else */ {
2896 assert(reg != rscratch2, "invalid dst for register increment");
2897 movw(rscratch2, (unsigned)value);
2898 addw(reg, reg, rscratch2);
2899 }
2900 }
2901
2902 void MacroAssembler::increment(Register reg, int value)
2903 {
2904 if (value < 0) { decrement(reg, -value); return; }
2905 if (value == 0) { return; }
2906 if (value < (1 << 12)) { add(reg, reg, value); return; }
2907 /* else */ {
2908 assert(reg != rscratch2, "invalid dst for register increment");
2909 movw(rscratch2, (unsigned)value);
2910 add(reg, reg, rscratch2);
2911 }
2912 }
2913
2914 void MacroAssembler::incrementw(Address dst, int value)
2915 {
2916 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2917 if (dst.getMode() == Address::literal) {
2918 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2919 lea(rscratch2, dst);
2920 dst = Address(rscratch2);
2921 }
2922 ldrw(rscratch1, dst);
2923 incrementw(rscratch1, value);
2924 strw(rscratch1, dst);
2925 }
2926
2927 void MacroAssembler::increment(Address dst, int value)
2928 {
2929 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2930 if (dst.getMode() == Address::literal) {
2931 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2932 lea(rscratch2, dst);
2933 dst = Address(rscratch2);
2934 }
2935 ldr(rscratch1, dst);
2936 increment(rscratch1, value);
2937 str(rscratch1, dst);
2938 }
2939
2940 // Push lots of registers in the bit set supplied. Don't push sp.
2941 // Return the number of words pushed
2942 int MacroAssembler::push(unsigned int bitset, Register stack) {
2943 int words_pushed = 0;
2944
2945 // Scan bitset to accumulate register pairs
2946 unsigned char regs[32];
2947 int count = 0;
2948 for (int reg = 0; reg <= 30; reg++) {
2949 if (1 & bitset)
2950 regs[count++] = reg;
2951 bitset >>= 1;
2952 }
2953 regs[count++] = zr->raw_encoding();
2954 count &= ~1; // Only push an even number of regs
2955
2956 if (count) {
2957 stp(as_Register(regs[0]), as_Register(regs[1]),
2958 Address(pre(stack, -count * wordSize)));
2959 words_pushed += 2;
2960 }
2961 for (int i = 2; i < count; i += 2) {
2962 stp(as_Register(regs[i]), as_Register(regs[i+1]),
2963 Address(stack, i * wordSize));
2964 words_pushed += 2;
2965 }
2966
2967 assert(words_pushed == count, "oops, pushed != count");
2968
2969 return count;
2970 }
2971
2972 int MacroAssembler::pop(unsigned int bitset, Register stack) {
2973 int words_pushed = 0;
2974
2975 // Scan bitset to accumulate register pairs
2976 unsigned char regs[32];
2977 int count = 0;
2978 for (int reg = 0; reg <= 30; reg++) {
2979 if (1 & bitset)
2980 regs[count++] = reg;
2981 bitset >>= 1;
2982 }
2983 regs[count++] = zr->raw_encoding();
2984 count &= ~1;
2985
2986 for (int i = 2; i < count; i += 2) {
2987 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
2988 Address(stack, i * wordSize));
2989 words_pushed += 2;
2990 }
2991 if (count) {
2992 ldp(as_Register(regs[0]), as_Register(regs[1]),
2993 Address(post(stack, count * wordSize)));
2994 words_pushed += 2;
2995 }
2996
2997 assert(words_pushed == count, "oops, pushed != count");
2998
2999 return count;
3000 }
3001
3002 // Push lots of registers in the bit set supplied. Don't push sp.
3003 // Return the number of dwords pushed
3004 int MacroAssembler::push_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
3005 int words_pushed = 0;
3006 bool use_sve = false;
3007 int sve_vector_size_in_bytes = 0;
3008
3009 #ifdef COMPILER2
3010 use_sve = Matcher::supports_scalable_vector();
3011 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
3012 #endif
3013
3014 // Scan bitset to accumulate register pairs
3015 unsigned char regs[32];
3016 int count = 0;
3017 for (int reg = 0; reg <= 31; reg++) {
3018 if (1 & bitset)
3019 regs[count++] = reg;
3020 bitset >>= 1;
3021 }
3022
3023 if (count == 0) {
3024 return 0;
3025 }
3026
3027 if (mode == PushPopFull) {
3028 if (use_sve && sve_vector_size_in_bytes > 16) {
3029 mode = PushPopSVE;
3030 } else {
3031 mode = PushPopNeon;
3032 }
3033 }
3034
3035 #ifndef PRODUCT
3036 {
3037 char buffer[48];
3038 if (mode == PushPopSVE) {
3039 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d SVE registers", count);
3040 } else if (mode == PushPopNeon) {
3041 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d Neon registers", count);
3042 } else {
3043 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d fp registers", count);
3044 }
3045 block_comment(buffer);
3046 }
3047 #endif
3048
3049 if (mode == PushPopSVE) {
3050 sub(stack, stack, sve_vector_size_in_bytes * count);
3051 for (int i = 0; i < count; i++) {
3052 sve_str(as_FloatRegister(regs[i]), Address(stack, i));
3053 }
3054 return count * sve_vector_size_in_bytes / 8;
3055 }
3056
3057 if (mode == PushPopNeon) {
3058 if (count == 1) {
3059 strq(as_FloatRegister(regs[0]), Address(pre(stack, -wordSize * 2)));
3060 return 2;
3061 }
3062
3063 bool odd = (count & 1) == 1;
3064 int push_slots = count + (odd ? 1 : 0);
3065
3066 // Always pushing full 128 bit registers.
3067 stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize * 2)));
3068 words_pushed += 2;
3069
3070 for (int i = 2; i + 1 < count; i += 2) {
3071 stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3072 words_pushed += 2;
3073 }
3074
3075 if (odd) {
3076 strq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3077 words_pushed++;
3078 }
3079
3080 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3081 return count * 2;
3082 }
3083
3084 if (mode == PushPopFp) {
3085 bool odd = (count & 1) == 1;
3086 int push_slots = count + (odd ? 1 : 0);
3087
3088 if (count == 1) {
3089 // Stack pointer must be 16 bytes aligned
3090 strd(as_FloatRegister(regs[0]), Address(pre(stack, -push_slots * wordSize)));
3091 return 1;
3092 }
3093
3094 stpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize)));
3095 words_pushed += 2;
3096
3097 for (int i = 2; i + 1 < count; i += 2) {
3098 stpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3099 words_pushed += 2;
3100 }
3101
3102 if (odd) {
3103 // Stack pointer must be 16 bytes aligned
3104 strd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3105 words_pushed++;
3106 }
3107
3108 assert(words_pushed == count, "oops, pushed != count");
3109
3110 return count;
3111 }
3112
3113 return 0;
3114 }
3115
3116 // Return the number of dwords popped
3117 int MacroAssembler::pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
3118 int words_pushed = 0;
3119 bool use_sve = false;
3120 int sve_vector_size_in_bytes = 0;
3121
3122 #ifdef COMPILER2
3123 use_sve = Matcher::supports_scalable_vector();
3124 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
3125 #endif
3126 // Scan bitset to accumulate register pairs
3127 unsigned char regs[32];
3128 int count = 0;
3129 for (int reg = 0; reg <= 31; reg++) {
3130 if (1 & bitset)
3131 regs[count++] = reg;
3132 bitset >>= 1;
3133 }
3134
3135 if (count == 0) {
3136 return 0;
3137 }
3138
3139 if (mode == PushPopFull) {
3140 if (use_sve && sve_vector_size_in_bytes > 16) {
3141 mode = PushPopSVE;
3142 } else {
3143 mode = PushPopNeon;
3144 }
3145 }
3146
3147 #ifndef PRODUCT
3148 {
3149 char buffer[48];
3150 if (mode == PushPopSVE) {
3151 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d SVE registers", count);
3152 } else if (mode == PushPopNeon) {
3153 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d Neon registers", count);
3154 } else {
3155 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d fp registers", count);
3156 }
3157 block_comment(buffer);
3158 }
3159 #endif
3160
3161 if (mode == PushPopSVE) {
3162 for (int i = count - 1; i >= 0; i--) {
3163 sve_ldr(as_FloatRegister(regs[i]), Address(stack, i));
3164 }
3165 add(stack, stack, sve_vector_size_in_bytes * count);
3166 return count * sve_vector_size_in_bytes / 8;
3167 }
3168
3169 if (mode == PushPopNeon) {
3170 if (count == 1) {
3171 ldrq(as_FloatRegister(regs[0]), Address(post(stack, wordSize * 2)));
3172 return 2;
3173 }
3174
3175 bool odd = (count & 1) == 1;
3176 int push_slots = count + (odd ? 1 : 0);
3177
3178 if (odd) {
3179 ldrq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3180 words_pushed++;
3181 }
3182
3183 for (int i = 2; i + 1 < count; i += 2) {
3184 ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3185 words_pushed += 2;
3186 }
3187
3188 ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize * 2)));
3189 words_pushed += 2;
3190
3191 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3192
3193 return count * 2;
3194 }
3195
3196 if (mode == PushPopFp) {
3197 bool odd = (count & 1) == 1;
3198 int push_slots = count + (odd ? 1 : 0);
3199
3200 if (count == 1) {
3201 ldrd(as_FloatRegister(regs[0]), Address(post(stack, push_slots * wordSize)));
3202 return 1;
3203 }
3204
3205 if (odd) {
3206 ldrd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3207 words_pushed++;
3208 }
3209
3210 for (int i = 2; i + 1 < count; i += 2) {
3211 ldpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3212 words_pushed += 2;
3213 }
3214
3215 ldpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize)));
3216 words_pushed += 2;
3217
3218 assert(words_pushed == count, "oops, pushed != count");
3219
3220 return count;
3221 }
3222
3223 return 0;
3224 }
3225
3226 // Return the number of dwords pushed
3227 int MacroAssembler::push_p(unsigned int bitset, Register stack) {
3228 bool use_sve = false;
3229 int sve_predicate_size_in_slots = 0;
3230
3231 #ifdef COMPILER2
3232 use_sve = Matcher::supports_scalable_vector();
3233 if (use_sve) {
3234 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3235 }
3236 #endif
3237
3238 if (!use_sve) {
3239 return 0;
3240 }
3241
3242 unsigned char regs[PRegister::number_of_registers];
3243 int count = 0;
3244 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3245 if (1 & bitset)
3246 regs[count++] = reg;
3247 bitset >>= 1;
3248 }
3249
3250 if (count == 0) {
3251 return 0;
3252 }
3253
3254 int total_push_bytes = align_up(sve_predicate_size_in_slots *
3255 VMRegImpl::stack_slot_size * count, 16);
3256 sub(stack, stack, total_push_bytes);
3257 for (int i = 0; i < count; i++) {
3258 sve_str(as_PRegister(regs[i]), Address(stack, i));
3259 }
3260 return total_push_bytes / 8;
3261 }
3262
3263 // Return the number of dwords popped
3264 int MacroAssembler::pop_p(unsigned int bitset, Register stack) {
3265 bool use_sve = false;
3266 int sve_predicate_size_in_slots = 0;
3267
3268 #ifdef COMPILER2
3269 use_sve = Matcher::supports_scalable_vector();
3270 if (use_sve) {
3271 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3272 }
3273 #endif
3274
3275 if (!use_sve) {
3276 return 0;
3277 }
3278
3279 unsigned char regs[PRegister::number_of_registers];
3280 int count = 0;
3281 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3282 if (1 & bitset)
3283 regs[count++] = reg;
3284 bitset >>= 1;
3285 }
3286
3287 if (count == 0) {
3288 return 0;
3289 }
3290
3291 int total_pop_bytes = align_up(sve_predicate_size_in_slots *
3292 VMRegImpl::stack_slot_size * count, 16);
3293 for (int i = count - 1; i >= 0; i--) {
3294 sve_ldr(as_PRegister(regs[i]), Address(stack, i));
3295 }
3296 add(stack, stack, total_pop_bytes);
3297 return total_pop_bytes / 8;
3298 }
3299
3300 #ifdef ASSERT
3301 void MacroAssembler::verify_heapbase(const char* msg) {
3302 #if 0
3303 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
3304 assert (Universe::heap() != nullptr, "java heap should be initialized");
3305 if (!UseCompressedOops || Universe::ptr_base() == nullptr) {
3306 // rheapbase is allocated as general register
3307 return;
3308 }
3309 if (CheckCompressedOops) {
3310 Label ok;
3311 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
3312 cmpptr(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3313 br(Assembler::EQ, ok);
3314 stop(msg);
3315 bind(ok);
3316 pop(1 << rscratch1->encoding(), sp);
3317 }
3318 #endif
3319 }
3320 #endif
3321
3322 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2) {
3323 assert_different_registers(value, tmp1, tmp2);
3324 Label done, tagged, weak_tagged;
3325
3326 cbz(value, done); // Use null as-is.
3327 tst(value, JNIHandles::tag_mask); // Test for tag.
3328 br(Assembler::NE, tagged);
3329
3330 // Resolve local handle
3331 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp1, tmp2);
3332 verify_oop(value);
3333 b(done);
3334
3335 bind(tagged);
3336 STATIC_ASSERT(JNIHandles::TypeTag::weak_global == 0b1);
3337 tbnz(value, 0, weak_tagged); // Test for weak tag.
3338
3339 // Resolve global handle
3340 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3341 verify_oop(value);
3342 b(done);
3343
3344 bind(weak_tagged);
3345 // Resolve jweak.
3346 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3347 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp1, tmp2);
3348 verify_oop(value);
3349
3350 bind(done);
3351 }
3352
3353 void MacroAssembler::resolve_global_jobject(Register value, Register tmp1, Register tmp2) {
3354 assert_different_registers(value, tmp1, tmp2);
3355 Label done;
3356
3357 cbz(value, done); // Use null as-is.
3358
3359 #ifdef ASSERT
3360 {
3361 STATIC_ASSERT(JNIHandles::TypeTag::global == 0b10);
3362 Label valid_global_tag;
3363 tbnz(value, 1, valid_global_tag); // Test for global tag
3364 stop("non global jobject using resolve_global_jobject");
3365 bind(valid_global_tag);
3366 }
3367 #endif
3368
3369 // Resolve global handle
3370 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3371 verify_oop(value);
3372
3373 bind(done);
3374 }
3375
3376 void MacroAssembler::stop(const char* msg) {
3377 // Skip AOT caching C strings in scratch buffer.
3378 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
3379 BLOCK_COMMENT(str);
3380 // load msg into r0 so we can access it from the signal handler
3381 // ExternalAddress enables saving and restoring via the code cache
3382 lea(c_rarg0, ExternalAddress((address) str));
3383 dcps1(0xdeae);
3384 }
3385
3386 void MacroAssembler::unimplemented(const char* what) {
3387 const char* buf = nullptr;
3388 {
3389 ResourceMark rm;
3390 stringStream ss;
3391 ss.print("unimplemented: %s", what);
3392 buf = code_string(ss.as_string());
3393 }
3394 stop(buf);
3395 }
3396
3397 void MacroAssembler::_assert_asm(Assembler::Condition cc, const char* msg) {
3398 #ifdef ASSERT
3399 Label OK;
3400 br(cc, OK);
3401 stop(msg);
3402 bind(OK);
3403 #endif
3404 }
3405
3406 // If a constant does not fit in an immediate field, generate some
3407 // number of MOV instructions and then perform the operation.
3408 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
3409 add_sub_imm_insn insn1,
3410 add_sub_reg_insn insn2,
3411 bool is32) {
3412 assert(Rd != zr, "Rd = zr and not setting flags?");
3413 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3414 if (fits) {
3415 (this->*insn1)(Rd, Rn, imm);
3416 } else {
3417 if (g_uabs(imm) < (1 << 24)) {
3418 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
3419 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
3420 } else {
3421 assert_different_registers(Rd, Rn);
3422 mov(Rd, imm);
3423 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3424 }
3425 }
3426 }
3427
3428 // Separate vsn which sets the flags. Optimisations are more restricted
3429 // because we must set the flags correctly.
3430 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
3431 add_sub_imm_insn insn1,
3432 add_sub_reg_insn insn2,
3433 bool is32) {
3434 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3435 if (fits) {
3436 (this->*insn1)(Rd, Rn, imm);
3437 } else {
3438 assert_different_registers(Rd, Rn);
3439 assert(Rd != zr, "overflow in immediate operand");
3440 mov(Rd, imm);
3441 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3442 }
3443 }
3444
3445
3446 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
3447 if (increment.is_register()) {
3448 add(Rd, Rn, increment.as_register());
3449 } else {
3450 add(Rd, Rn, increment.as_constant());
3451 }
3452 }
3453
3454 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
3455 if (increment.is_register()) {
3456 addw(Rd, Rn, increment.as_register());
3457 } else {
3458 addw(Rd, Rn, increment.as_constant());
3459 }
3460 }
3461
3462 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
3463 if (decrement.is_register()) {
3464 sub(Rd, Rn, decrement.as_register());
3465 } else {
3466 sub(Rd, Rn, decrement.as_constant());
3467 }
3468 }
3469
3470 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
3471 if (decrement.is_register()) {
3472 subw(Rd, Rn, decrement.as_register());
3473 } else {
3474 subw(Rd, Rn, decrement.as_constant());
3475 }
3476 }
3477
3478 void MacroAssembler::reinit_heapbase()
3479 {
3480 if (UseCompressedOops) {
3481 if (Universe::is_fully_initialized() && !AOTCodeCache::is_on_for_dump()) {
3482 mov(rheapbase, CompressedOops::base());
3483 } else {
3484 lea(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3485 ldr(rheapbase, Address(rheapbase));
3486 }
3487 }
3488 }
3489
3490 // A generic CAS; success or failure is in the EQ flag. A weak CAS
3491 // doesn't retry and may fail spuriously. If the oldval is wanted,
3492 // Pass a register for the result, otherwise pass noreg.
3493
3494 // Clobbers rscratch1
3495 void MacroAssembler::cmpxchg(Register addr, Register expected,
3496 Register new_val,
3497 enum operand_size size,
3498 bool acquire, bool release,
3499 bool weak,
3500 Register result) {
3501 if (result == noreg) result = rscratch1;
3502 BLOCK_COMMENT("cmpxchg {");
3503 if (UseLSE) {
3504 mov(result, expected);
3505 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
3506 compare_eq(result, expected, size);
3507 #ifdef ASSERT
3508 // Poison rscratch1 which is written on !UseLSE branch
3509 mov(rscratch1, 0x1f1f1f1f1f1f1f1f);
3510 #endif
3511 } else {
3512 Label retry_load, done;
3513 prfm(Address(addr), PSTL1STRM);
3514 bind(retry_load);
3515 load_exclusive(result, addr, size, acquire);
3516 compare_eq(result, expected, size);
3517 br(Assembler::NE, done);
3518 store_exclusive(rscratch1, new_val, addr, size, release);
3519 if (weak) {
3520 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
3521 } else {
3522 cbnzw(rscratch1, retry_load);
3523 }
3524 bind(done);
3525 }
3526 BLOCK_COMMENT("} cmpxchg");
3527 }
3528
3529 // A generic comparison. Only compares for equality, clobbers rscratch1.
3530 void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) {
3531 if (size == xword) {
3532 cmp(rm, rn);
3533 } else if (size == word) {
3534 cmpw(rm, rn);
3535 } else if (size == halfword) {
3536 eorw(rscratch1, rm, rn);
3537 ands(zr, rscratch1, 0xffff);
3538 } else if (size == byte) {
3539 eorw(rscratch1, rm, rn);
3540 ands(zr, rscratch1, 0xff);
3541 } else {
3542 ShouldNotReachHere();
3543 }
3544 }
3545
3546
3547 static bool different(Register a, RegisterOrConstant b, Register c) {
3548 if (b.is_constant())
3549 return a != c;
3550 else
3551 return a != b.as_register() && a != c && b.as_register() != c;
3552 }
3553
3554 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \
3555 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \
3556 if (UseLSE) { \
3557 prev = prev->is_valid() ? prev : zr; \
3558 if (incr.is_register()) { \
3559 AOP(sz, incr.as_register(), prev, addr); \
3560 } else { \
3561 mov(rscratch2, incr.as_constant()); \
3562 AOP(sz, rscratch2, prev, addr); \
3563 } \
3564 return; \
3565 } \
3566 Register result = rscratch2; \
3567 if (prev->is_valid()) \
3568 result = different(prev, incr, addr) ? prev : rscratch2; \
3569 \
3570 Label retry_load; \
3571 prfm(Address(addr), PSTL1STRM); \
3572 bind(retry_load); \
3573 LDXR(result, addr); \
3574 OP(rscratch1, result, incr); \
3575 STXR(rscratch2, rscratch1, addr); \
3576 cbnzw(rscratch2, retry_load); \
3577 if (prev->is_valid() && prev != result) { \
3578 IOP(prev, rscratch1, incr); \
3579 } \
3580 }
3581
3582 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword)
3583 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
3584 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword)
3585 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word)
3586
3587 #undef ATOMIC_OP
3588
3589 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \
3590 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
3591 if (UseLSE) { \
3592 prev = prev->is_valid() ? prev : zr; \
3593 AOP(sz, newv, prev, addr); \
3594 return; \
3595 } \
3596 Register result = rscratch2; \
3597 if (prev->is_valid()) \
3598 result = different(prev, newv, addr) ? prev : rscratch2; \
3599 \
3600 Label retry_load; \
3601 prfm(Address(addr), PSTL1STRM); \
3602 bind(retry_load); \
3603 LDXR(result, addr); \
3604 STXR(rscratch1, newv, addr); \
3605 cbnzw(rscratch1, retry_load); \
3606 if (prev->is_valid() && prev != result) \
3607 mov(prev, result); \
3608 }
3609
3610 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
3611 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
3612 ATOMIC_XCHG(xchgl, swpl, ldxr, stlxr, Assembler::xword)
3613 ATOMIC_XCHG(xchglw, swpl, ldxrw, stlxrw, Assembler::word)
3614 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
3615 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
3616
3617 #undef ATOMIC_XCHG
3618
3619 #ifndef PRODUCT
3620 extern "C" void findpc(intptr_t x);
3621 #endif
3622
3623 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
3624 {
3625 // In order to get locks to work, we need to fake a in_VM state
3626 if (ShowMessageBoxOnError ) {
3627 JavaThread* thread = JavaThread::current();
3628 JavaThreadState saved_state = thread->thread_state();
3629 thread->set_thread_state(_thread_in_vm);
3630 #ifndef PRODUCT
3631 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
3632 ttyLocker ttyl;
3633 BytecodeCounter::print();
3634 }
3635 #endif
3636 if (os::message_box(msg, "Execution stopped, print registers?")) {
3637 ttyLocker ttyl;
3638 tty->print_cr(" pc = 0x%016" PRIx64, pc);
3639 #ifndef PRODUCT
3640 tty->cr();
3641 findpc(pc);
3642 tty->cr();
3643 #endif
3644 tty->print_cr(" r0 = 0x%016" PRIx64, regs[0]);
3645 tty->print_cr(" r1 = 0x%016" PRIx64, regs[1]);
3646 tty->print_cr(" r2 = 0x%016" PRIx64, regs[2]);
3647 tty->print_cr(" r3 = 0x%016" PRIx64, regs[3]);
3648 tty->print_cr(" r4 = 0x%016" PRIx64, regs[4]);
3649 tty->print_cr(" r5 = 0x%016" PRIx64, regs[5]);
3650 tty->print_cr(" r6 = 0x%016" PRIx64, regs[6]);
3651 tty->print_cr(" r7 = 0x%016" PRIx64, regs[7]);
3652 tty->print_cr(" r8 = 0x%016" PRIx64, regs[8]);
3653 tty->print_cr(" r9 = 0x%016" PRIx64, regs[9]);
3654 tty->print_cr("r10 = 0x%016" PRIx64, regs[10]);
3655 tty->print_cr("r11 = 0x%016" PRIx64, regs[11]);
3656 tty->print_cr("r12 = 0x%016" PRIx64, regs[12]);
3657 tty->print_cr("r13 = 0x%016" PRIx64, regs[13]);
3658 tty->print_cr("r14 = 0x%016" PRIx64, regs[14]);
3659 tty->print_cr("r15 = 0x%016" PRIx64, regs[15]);
3660 tty->print_cr("r16 = 0x%016" PRIx64, regs[16]);
3661 tty->print_cr("r17 = 0x%016" PRIx64, regs[17]);
3662 tty->print_cr("r18 = 0x%016" PRIx64, regs[18]);
3663 tty->print_cr("r19 = 0x%016" PRIx64, regs[19]);
3664 tty->print_cr("r20 = 0x%016" PRIx64, regs[20]);
3665 tty->print_cr("r21 = 0x%016" PRIx64, regs[21]);
3666 tty->print_cr("r22 = 0x%016" PRIx64, regs[22]);
3667 tty->print_cr("r23 = 0x%016" PRIx64, regs[23]);
3668 tty->print_cr("r24 = 0x%016" PRIx64, regs[24]);
3669 tty->print_cr("r25 = 0x%016" PRIx64, regs[25]);
3670 tty->print_cr("r26 = 0x%016" PRIx64, regs[26]);
3671 tty->print_cr("r27 = 0x%016" PRIx64, regs[27]);
3672 tty->print_cr("r28 = 0x%016" PRIx64, regs[28]);
3673 tty->print_cr("r30 = 0x%016" PRIx64, regs[30]);
3674 tty->print_cr("r31 = 0x%016" PRIx64, regs[31]);
3675 BREAKPOINT;
3676 }
3677 }
3678 fatal("DEBUG MESSAGE: %s", msg);
3679 }
3680
3681 RegSet MacroAssembler::call_clobbered_gp_registers() {
3682 RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2);
3683 #ifndef R18_RESERVED
3684 regs += r18_tls;
3685 #endif
3686 return regs;
3687 }
3688
3689 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
3690 int step = 4 * wordSize;
3691 push(call_clobbered_gp_registers() - exclude, sp);
3692 sub(sp, sp, step);
3693 mov(rscratch1, -step);
3694 // Push v0-v7, v16-v31.
3695 for (int i = 31; i>= 4; i -= 4) {
3696 if (i <= v7->encoding() || i >= v16->encoding())
3697 st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1),
3698 as_FloatRegister(i), T1D, Address(post(sp, rscratch1)));
3699 }
3700 st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2),
3701 as_FloatRegister(3), T1D, Address(sp));
3702 }
3703
3704 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
3705 for (int i = 0; i < 32; i += 4) {
3706 if (i <= v7->encoding() || i >= v16->encoding())
3707 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3708 as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
3709 }
3710
3711 reinitialize_ptrue();
3712
3713 pop(call_clobbered_gp_registers() - exclude, sp);
3714 }
3715
3716 void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve,
3717 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3718 push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
3719 if (save_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3720 sub(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3721 for (int i = 0; i < FloatRegister::number_of_registers; i++) {
3722 sve_str(as_FloatRegister(i), Address(sp, i));
3723 }
3724 } else {
3725 int step = (save_vectors ? 8 : 4) * wordSize;
3726 mov(rscratch1, -step);
3727 sub(sp, sp, step);
3728 for (int i = 28; i >= 4; i -= 4) {
3729 st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3730 as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1)));
3731 }
3732 st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp);
3733 }
3734 if (save_vectors && use_sve && total_predicate_in_bytes > 0) {
3735 sub(sp, sp, total_predicate_in_bytes);
3736 for (int i = 0; i < PRegister::number_of_registers; i++) {
3737 sve_str(as_PRegister(i), Address(sp, i));
3738 }
3739 }
3740 }
3741
3742 void MacroAssembler::pop_CPU_state(bool restore_vectors, bool use_sve,
3743 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3744 if (restore_vectors && use_sve && total_predicate_in_bytes > 0) {
3745 for (int i = PRegister::number_of_registers - 1; i >= 0; i--) {
3746 sve_ldr(as_PRegister(i), Address(sp, i));
3747 }
3748 add(sp, sp, total_predicate_in_bytes);
3749 }
3750 if (restore_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3751 for (int i = FloatRegister::number_of_registers - 1; i >= 0; i--) {
3752 sve_ldr(as_FloatRegister(i), Address(sp, i));
3753 }
3754 add(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3755 } else {
3756 int step = (restore_vectors ? 8 : 4) * wordSize;
3757 for (int i = 0; i <= 28; i += 4)
3758 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3759 as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step)));
3760 }
3761
3762 // We may use predicate registers and rely on ptrue with SVE,
3763 // regardless of wide vector (> 8 bytes) used or not.
3764 if (use_sve) {
3765 reinitialize_ptrue();
3766 }
3767
3768 // integer registers except lr & sp
3769 pop(RegSet::range(r0, r17), sp);
3770 #ifdef R18_RESERVED
3771 ldp(zr, r19, Address(post(sp, 2 * wordSize)));
3772 pop(RegSet::range(r20, r29), sp);
3773 #else
3774 pop(RegSet::range(r18_tls, r29), sp);
3775 #endif
3776 }
3777
3778 /**
3779 * Helpers for multiply_to_len().
3780 */
3781 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
3782 Register src1, Register src2) {
3783 adds(dest_lo, dest_lo, src1);
3784 adc(dest_hi, dest_hi, zr);
3785 adds(dest_lo, dest_lo, src2);
3786 adc(final_dest_hi, dest_hi, zr);
3787 }
3788
3789 // Generate an address from (r + r1 extend offset). "size" is the
3790 // size of the operand. The result may be in rscratch2.
3791 Address MacroAssembler::offsetted_address(Register r, Register r1,
3792 Address::extend ext, int offset, int size) {
3793 if (offset || (ext.shift() % size != 0)) {
3794 lea(rscratch2, Address(r, r1, ext));
3795 return Address(rscratch2, offset);
3796 } else {
3797 return Address(r, r1, ext);
3798 }
3799 }
3800
3801 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
3802 {
3803 assert(offset >= 0, "spill to negative address?");
3804 // Offset reachable ?
3805 // Not aligned - 9 bits signed offset
3806 // Aligned - 12 bits unsigned offset shifted
3807 Register base = sp;
3808 if ((offset & (size-1)) && offset >= (1<<8)) {
3809 add(tmp, base, offset & ((1<<12)-1));
3810 base = tmp;
3811 offset &= -1u<<12;
3812 }
3813
3814 if (offset >= (1<<12) * size) {
3815 add(tmp, base, offset & (((1<<12)-1)<<12));
3816 base = tmp;
3817 offset &= ~(((1<<12)-1)<<12);
3818 }
3819
3820 return Address(base, offset);
3821 }
3822
3823 Address MacroAssembler::sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp) {
3824 assert(offset >= 0, "spill to negative address?");
3825
3826 Register base = sp;
3827
3828 // An immediate offset in the range 0 to 255 which is multiplied
3829 // by the current vector or predicate register size in bytes.
3830 if (offset % sve_reg_size_in_bytes == 0 && offset < ((1<<8)*sve_reg_size_in_bytes)) {
3831 return Address(base, offset / sve_reg_size_in_bytes);
3832 }
3833
3834 add(tmp, base, offset);
3835 return Address(tmp);
3836 }
3837
3838 // Checks whether offset is aligned.
3839 // Returns true if it is, else false.
3840 bool MacroAssembler::merge_alignment_check(Register base,
3841 size_t size,
3842 int64_t cur_offset,
3843 int64_t prev_offset) const {
3844 if (AvoidUnalignedAccesses) {
3845 if (base == sp) {
3846 // Checks whether low offset if aligned to pair of registers.
3847 int64_t pair_mask = size * 2 - 1;
3848 int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3849 return (offset & pair_mask) == 0;
3850 } else { // If base is not sp, we can't guarantee the access is aligned.
3851 return false;
3852 }
3853 } else {
3854 int64_t mask = size - 1;
3855 // Load/store pair instruction only supports element size aligned offset.
3856 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
3857 }
3858 }
3859
3860 // Checks whether current and previous loads/stores can be merged.
3861 // Returns true if it can be merged, else false.
3862 bool MacroAssembler::ldst_can_merge(Register rt,
3863 const Address &adr,
3864 size_t cur_size_in_bytes,
3865 bool is_store) const {
3866 address prev = pc() - NativeInstruction::instruction_size;
3867 address last = code()->last_insn();
3868
3869 if (last == nullptr || !nativeInstruction_at(last)->is_Imm_LdSt()) {
3870 return false;
3871 }
3872
3873 if (adr.getMode() != Address::base_plus_offset || prev != last) {
3874 return false;
3875 }
3876
3877 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3878 size_t prev_size_in_bytes = prev_ldst->size_in_bytes();
3879
3880 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging.");
3881 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging.");
3882
3883 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) {
3884 return false;
3885 }
3886
3887 int64_t max_offset = 63 * prev_size_in_bytes;
3888 int64_t min_offset = -64 * prev_size_in_bytes;
3889
3890 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
3891
3892 // Only same base can be merged.
3893 if (adr.base() != prev_ldst->base()) {
3894 return false;
3895 }
3896
3897 int64_t cur_offset = adr.offset();
3898 int64_t prev_offset = prev_ldst->offset();
3899 size_t diff = abs(cur_offset - prev_offset);
3900 if (diff != prev_size_in_bytes) {
3901 return false;
3902 }
3903
3904 // Following cases can not be merged:
3905 // ldr x2, [x2, #8]
3906 // ldr x3, [x2, #16]
3907 // or:
3908 // ldr x2, [x3, #8]
3909 // ldr x2, [x3, #16]
3910 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL.
3911 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) {
3912 return false;
3913 }
3914
3915 int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3916 // Offset range must be in ldp/stp instruction's range.
3917 if (low_offset > max_offset || low_offset < min_offset) {
3918 return false;
3919 }
3920
3921 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) {
3922 return true;
3923 }
3924
3925 return false;
3926 }
3927
3928 // Merge current load/store with previous load/store into ldp/stp.
3929 void MacroAssembler::merge_ldst(Register rt,
3930 const Address &adr,
3931 size_t cur_size_in_bytes,
3932 bool is_store) {
3933
3934 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged.");
3935
3936 Register rt_low, rt_high;
3937 address prev = pc() - NativeInstruction::instruction_size;
3938 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3939
3940 int64_t offset;
3941
3942 if (adr.offset() < prev_ldst->offset()) {
3943 offset = adr.offset();
3944 rt_low = rt;
3945 rt_high = prev_ldst->target();
3946 } else {
3947 offset = prev_ldst->offset();
3948 rt_low = prev_ldst->target();
3949 rt_high = rt;
3950 }
3951
3952 Address adr_p = Address(prev_ldst->base(), offset);
3953 // Overwrite previous generated binary.
3954 code_section()->set_end(prev);
3955
3956 const size_t sz = prev_ldst->size_in_bytes();
3957 assert(sz == 8 || sz == 4, "only supports 64/32bit merging.");
3958 if (!is_store) {
3959 BLOCK_COMMENT("merged ldr pair");
3960 if (sz == 8) {
3961 ldp(rt_low, rt_high, adr_p);
3962 } else {
3963 ldpw(rt_low, rt_high, adr_p);
3964 }
3965 } else {
3966 BLOCK_COMMENT("merged str pair");
3967 if (sz == 8) {
3968 stp(rt_low, rt_high, adr_p);
3969 } else {
3970 stpw(rt_low, rt_high, adr_p);
3971 }
3972 }
3973 }
3974
3975 /**
3976 * Multiply 64 bit by 64 bit first loop.
3977 */
3978 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
3979 Register y, Register y_idx, Register z,
3980 Register carry, Register product,
3981 Register idx, Register kdx) {
3982 //
3983 // jlong carry, x[], y[], z[];
3984 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
3985 // huge_128 product = y[idx] * x[xstart] + carry;
3986 // z[kdx] = (jlong)product;
3987 // carry = (jlong)(product >>> 64);
3988 // }
3989 // z[xstart] = carry;
3990 //
3991
3992 Label L_first_loop, L_first_loop_exit;
3993 Label L_one_x, L_one_y, L_multiply;
3994
3995 subsw(xstart, xstart, 1);
3996 br(Assembler::MI, L_one_x);
3997
3998 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
3999 ldr(x_xstart, Address(rscratch1));
4000 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
4001
4002 bind(L_first_loop);
4003 subsw(idx, idx, 1);
4004 br(Assembler::MI, L_first_loop_exit);
4005 subsw(idx, idx, 1);
4006 br(Assembler::MI, L_one_y);
4007 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4008 ldr(y_idx, Address(rscratch1));
4009 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
4010 bind(L_multiply);
4011
4012 // AArch64 has a multiply-accumulate instruction that we can't use
4013 // here because it has no way to process carries, so we have to use
4014 // separate add and adc instructions. Bah.
4015 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
4016 mul(product, x_xstart, y_idx);
4017 adds(product, product, carry);
4018 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
4019
4020 subw(kdx, kdx, 2);
4021 ror(product, product, 32); // back to big-endian
4022 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
4023
4024 b(L_first_loop);
4025
4026 bind(L_one_y);
4027 ldrw(y_idx, Address(y, 0));
4028 b(L_multiply);
4029
4030 bind(L_one_x);
4031 ldrw(x_xstart, Address(x, 0));
4032 b(L_first_loop);
4033
4034 bind(L_first_loop_exit);
4035 }
4036
4037 /**
4038 * Multiply 128 bit by 128. Unrolled inner loop.
4039 *
4040 */
4041 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
4042 Register carry, Register carry2,
4043 Register idx, Register jdx,
4044 Register yz_idx1, Register yz_idx2,
4045 Register tmp, Register tmp3, Register tmp4,
4046 Register tmp6, Register product_hi) {
4047
4048 // jlong carry, x[], y[], z[];
4049 // int kdx = ystart+1;
4050 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
4051 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
4052 // jlong carry2 = (jlong)(tmp3 >>> 64);
4053 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
4054 // carry = (jlong)(tmp4 >>> 64);
4055 // z[kdx+idx+1] = (jlong)tmp3;
4056 // z[kdx+idx] = (jlong)tmp4;
4057 // }
4058 // idx += 2;
4059 // if (idx > 0) {
4060 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
4061 // z[kdx+idx] = (jlong)yz_idx1;
4062 // carry = (jlong)(yz_idx1 >>> 64);
4063 // }
4064 //
4065
4066 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
4067
4068 lsrw(jdx, idx, 2);
4069
4070 bind(L_third_loop);
4071
4072 subsw(jdx, jdx, 1);
4073 br(Assembler::MI, L_third_loop_exit);
4074 subw(idx, idx, 4);
4075
4076 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4077
4078 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
4079
4080 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4081
4082 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
4083 ror(yz_idx2, yz_idx2, 32);
4084
4085 ldp(rscratch2, rscratch1, Address(tmp6, 0));
4086
4087 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4088 umulh(tmp4, product_hi, yz_idx1);
4089
4090 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
4091 ror(rscratch2, rscratch2, 32);
4092
4093 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
4094 umulh(carry2, product_hi, yz_idx2);
4095
4096 // propagate sum of both multiplications into carry:tmp4:tmp3
4097 adds(tmp3, tmp3, carry);
4098 adc(tmp4, tmp4, zr);
4099 adds(tmp3, tmp3, rscratch1);
4100 adcs(tmp4, tmp4, tmp);
4101 adc(carry, carry2, zr);
4102 adds(tmp4, tmp4, rscratch2);
4103 adc(carry, carry, zr);
4104
4105 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
4106 ror(tmp4, tmp4, 32);
4107 stp(tmp4, tmp3, Address(tmp6, 0));
4108
4109 b(L_third_loop);
4110 bind (L_third_loop_exit);
4111
4112 andw (idx, idx, 0x3);
4113 cbz(idx, L_post_third_loop_done);
4114
4115 Label L_check_1;
4116 subsw(idx, idx, 2);
4117 br(Assembler::MI, L_check_1);
4118
4119 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4120 ldr(yz_idx1, Address(rscratch1, 0));
4121 ror(yz_idx1, yz_idx1, 32);
4122 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4123 umulh(tmp4, product_hi, yz_idx1);
4124 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4125 ldr(yz_idx2, Address(rscratch1, 0));
4126 ror(yz_idx2, yz_idx2, 32);
4127
4128 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
4129
4130 ror(tmp3, tmp3, 32);
4131 str(tmp3, Address(rscratch1, 0));
4132
4133 bind (L_check_1);
4134
4135 andw (idx, idx, 0x1);
4136 subsw(idx, idx, 1);
4137 br(Assembler::MI, L_post_third_loop_done);
4138 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4139 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
4140 umulh(carry2, tmp4, product_hi);
4141 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4142
4143 add2_with_carry(carry2, tmp3, tmp4, carry);
4144
4145 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4146 extr(carry, carry2, tmp3, 32);
4147
4148 bind(L_post_third_loop_done);
4149 }
4150
4151 /**
4152 * Code for BigInteger::multiplyToLen() intrinsic.
4153 *
4154 * r0: x
4155 * r1: xlen
4156 * r2: y
4157 * r3: ylen
4158 * r4: z
4159 * r5: tmp0
4160 * r10: tmp1
4161 * r11: tmp2
4162 * r12: tmp3
4163 * r13: tmp4
4164 * r14: tmp5
4165 * r15: tmp6
4166 * r16: tmp7
4167 *
4168 */
4169 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
4170 Register z, Register tmp0,
4171 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
4172 Register tmp5, Register tmp6, Register product_hi) {
4173
4174 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, product_hi);
4175
4176 const Register idx = tmp1;
4177 const Register kdx = tmp2;
4178 const Register xstart = tmp3;
4179
4180 const Register y_idx = tmp4;
4181 const Register carry = tmp5;
4182 const Register product = xlen;
4183 const Register x_xstart = tmp0;
4184
4185 // First Loop.
4186 //
4187 // final static long LONG_MASK = 0xffffffffL;
4188 // int xstart = xlen - 1;
4189 // int ystart = ylen - 1;
4190 // long carry = 0;
4191 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
4192 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
4193 // z[kdx] = (int)product;
4194 // carry = product >>> 32;
4195 // }
4196 // z[xstart] = (int)carry;
4197 //
4198
4199 movw(idx, ylen); // idx = ylen;
4200 addw(kdx, xlen, ylen); // kdx = xlen+ylen;
4201 mov(carry, zr); // carry = 0;
4202
4203 Label L_done;
4204
4205 movw(xstart, xlen);
4206 subsw(xstart, xstart, 1);
4207 br(Assembler::MI, L_done);
4208
4209 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
4210
4211 Label L_second_loop;
4212 cbzw(kdx, L_second_loop);
4213
4214 Label L_carry;
4215 subw(kdx, kdx, 1);
4216 cbzw(kdx, L_carry);
4217
4218 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4219 lsr(carry, carry, 32);
4220 subw(kdx, kdx, 1);
4221
4222 bind(L_carry);
4223 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4224
4225 // Second and third (nested) loops.
4226 //
4227 // for (int i = xstart-1; i >= 0; i--) { // Second loop
4228 // carry = 0;
4229 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
4230 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
4231 // (z[k] & LONG_MASK) + carry;
4232 // z[k] = (int)product;
4233 // carry = product >>> 32;
4234 // }
4235 // z[i] = (int)carry;
4236 // }
4237 //
4238 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
4239
4240 const Register jdx = tmp1;
4241
4242 bind(L_second_loop);
4243 mov(carry, zr); // carry = 0;
4244 movw(jdx, ylen); // j = ystart+1
4245
4246 subsw(xstart, xstart, 1); // i = xstart-1;
4247 br(Assembler::MI, L_done);
4248
4249 str(z, Address(pre(sp, -4 * wordSize)));
4250
4251 Label L_last_x;
4252 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
4253 subsw(xstart, xstart, 1); // i = xstart-1;
4254 br(Assembler::MI, L_last_x);
4255
4256 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
4257 ldr(product_hi, Address(rscratch1));
4258 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
4259
4260 Label L_third_loop_prologue;
4261 bind(L_third_loop_prologue);
4262
4263 str(ylen, Address(sp, wordSize));
4264 stp(x, xstart, Address(sp, 2 * wordSize));
4265 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
4266 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
4267 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
4268 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
4269
4270 addw(tmp3, xlen, 1);
4271 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4272 subsw(tmp3, tmp3, 1);
4273 br(Assembler::MI, L_done);
4274
4275 lsr(carry, carry, 32);
4276 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4277 b(L_second_loop);
4278
4279 // Next infrequent code is moved outside loops.
4280 bind(L_last_x);
4281 ldrw(product_hi, Address(x, 0));
4282 b(L_third_loop_prologue);
4283
4284 bind(L_done);
4285 }
4286
4287 // Code for BigInteger::mulAdd intrinsic
4288 // out = r0
4289 // in = r1
4290 // offset = r2 (already out.length-offset)
4291 // len = r3
4292 // k = r4
4293 //
4294 // pseudo code from java implementation:
4295 // carry = 0;
4296 // offset = out.length-offset - 1;
4297 // for (int j=len-1; j >= 0; j--) {
4298 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry;
4299 // out[offset--] = (int)product;
4300 // carry = product >>> 32;
4301 // }
4302 // return (int)carry;
4303 void MacroAssembler::mul_add(Register out, Register in, Register offset,
4304 Register len, Register k) {
4305 Label LOOP, END;
4306 // pre-loop
4307 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches
4308 csel(out, zr, out, Assembler::EQ);
4309 br(Assembler::EQ, END);
4310 add(in, in, len, LSL, 2); // in[j+1] address
4311 add(offset, out, offset, LSL, 2); // out[offset + 1] address
4312 mov(out, zr); // used to keep carry now
4313 BIND(LOOP);
4314 ldrw(rscratch1, Address(pre(in, -4)));
4315 madd(rscratch1, rscratch1, k, out);
4316 ldrw(rscratch2, Address(pre(offset, -4)));
4317 add(rscratch1, rscratch1, rscratch2);
4318 strw(rscratch1, Address(offset));
4319 lsr(out, rscratch1, 32);
4320 subs(len, len, 1);
4321 br(Assembler::NE, LOOP);
4322 BIND(END);
4323 }
4324
4325 /**
4326 * Emits code to update CRC-32 with a byte value according to constants in table
4327 *
4328 * @param [in,out]crc Register containing the crc.
4329 * @param [in]val Register containing the byte to fold into the CRC.
4330 * @param [in]table Register containing the table of crc constants.
4331 *
4332 * uint32_t crc;
4333 * val = crc_table[(val ^ crc) & 0xFF];
4334 * crc = val ^ (crc >> 8);
4335 *
4336 */
4337 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
4338 eor(val, val, crc);
4339 andr(val, val, 0xff);
4340 ldrw(val, Address(table, val, Address::lsl(2)));
4341 eor(crc, val, crc, Assembler::LSR, 8);
4342 }
4343
4344 /**
4345 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
4346 *
4347 * @param [in,out]crc Register containing the crc.
4348 * @param [in]v Register containing the 32-bit to fold into the CRC.
4349 * @param [in]table0 Register containing table 0 of crc constants.
4350 * @param [in]table1 Register containing table 1 of crc constants.
4351 * @param [in]table2 Register containing table 2 of crc constants.
4352 * @param [in]table3 Register containing table 3 of crc constants.
4353 *
4354 * uint32_t crc;
4355 * v = crc ^ v
4356 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
4357 *
4358 */
4359 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
4360 Register table0, Register table1, Register table2, Register table3,
4361 bool upper) {
4362 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
4363 uxtb(tmp, v);
4364 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
4365 ubfx(tmp, v, 8, 8);
4366 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
4367 eor(crc, crc, tmp);
4368 ubfx(tmp, v, 16, 8);
4369 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
4370 eor(crc, crc, tmp);
4371 ubfx(tmp, v, 24, 8);
4372 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
4373 eor(crc, crc, tmp);
4374 }
4375
4376 void MacroAssembler::kernel_crc32_using_crypto_pmull(Register crc, Register buf,
4377 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4378 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4379 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4380
4381 subs(tmp0, len, 384);
4382 mvnw(crc, crc);
4383 br(Assembler::GE, CRC_by128_pre);
4384 BIND(CRC_less128);
4385 subs(len, len, 32);
4386 br(Assembler::GE, CRC_by32_loop);
4387 BIND(CRC_less32);
4388 adds(len, len, 32 - 4);
4389 br(Assembler::GE, CRC_by4_loop);
4390 adds(len, len, 4);
4391 br(Assembler::GT, CRC_by1_loop);
4392 b(L_exit);
4393
4394 BIND(CRC_by32_loop);
4395 ldp(tmp0, tmp1, Address(buf));
4396 crc32x(crc, crc, tmp0);
4397 ldp(tmp2, tmp3, Address(buf, 16));
4398 crc32x(crc, crc, tmp1);
4399 add(buf, buf, 32);
4400 crc32x(crc, crc, tmp2);
4401 subs(len, len, 32);
4402 crc32x(crc, crc, tmp3);
4403 br(Assembler::GE, CRC_by32_loop);
4404 cmn(len, (u1)32);
4405 br(Assembler::NE, CRC_less32);
4406 b(L_exit);
4407
4408 BIND(CRC_by4_loop);
4409 ldrw(tmp0, Address(post(buf, 4)));
4410 subs(len, len, 4);
4411 crc32w(crc, crc, tmp0);
4412 br(Assembler::GE, CRC_by4_loop);
4413 adds(len, len, 4);
4414 br(Assembler::LE, L_exit);
4415 BIND(CRC_by1_loop);
4416 ldrb(tmp0, Address(post(buf, 1)));
4417 subs(len, len, 1);
4418 crc32b(crc, crc, tmp0);
4419 br(Assembler::GT, CRC_by1_loop);
4420 b(L_exit);
4421
4422 BIND(CRC_by128_pre);
4423 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4424 4*256*sizeof(juint) + 8*sizeof(juint));
4425 mov(crc, 0);
4426 crc32x(crc, crc, tmp0);
4427 crc32x(crc, crc, tmp1);
4428
4429 cbnz(len, CRC_less128);
4430
4431 BIND(L_exit);
4432 mvnw(crc, crc);
4433 }
4434
4435 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf,
4436 Register len, Register tmp0, Register tmp1, Register tmp2,
4437 Register tmp3) {
4438 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4439 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4440
4441 mvnw(crc, crc);
4442
4443 subs(len, len, 128);
4444 br(Assembler::GE, CRC_by64_pre);
4445 BIND(CRC_less64);
4446 adds(len, len, 128-32);
4447 br(Assembler::GE, CRC_by32_loop);
4448 BIND(CRC_less32);
4449 adds(len, len, 32-4);
4450 br(Assembler::GE, CRC_by4_loop);
4451 adds(len, len, 4);
4452 br(Assembler::GT, CRC_by1_loop);
4453 b(L_exit);
4454
4455 BIND(CRC_by32_loop);
4456 ldp(tmp0, tmp1, Address(post(buf, 16)));
4457 subs(len, len, 32);
4458 crc32x(crc, crc, tmp0);
4459 ldr(tmp2, Address(post(buf, 8)));
4460 crc32x(crc, crc, tmp1);
4461 ldr(tmp3, Address(post(buf, 8)));
4462 crc32x(crc, crc, tmp2);
4463 crc32x(crc, crc, tmp3);
4464 br(Assembler::GE, CRC_by32_loop);
4465 cmn(len, (u1)32);
4466 br(Assembler::NE, CRC_less32);
4467 b(L_exit);
4468
4469 BIND(CRC_by4_loop);
4470 ldrw(tmp0, Address(post(buf, 4)));
4471 subs(len, len, 4);
4472 crc32w(crc, crc, tmp0);
4473 br(Assembler::GE, CRC_by4_loop);
4474 adds(len, len, 4);
4475 br(Assembler::LE, L_exit);
4476 BIND(CRC_by1_loop);
4477 ldrb(tmp0, Address(post(buf, 1)));
4478 subs(len, len, 1);
4479 crc32b(crc, crc, tmp0);
4480 br(Assembler::GT, CRC_by1_loop);
4481 b(L_exit);
4482
4483 BIND(CRC_by64_pre);
4484 sub(buf, buf, 8);
4485 ldp(tmp0, tmp1, Address(buf, 8));
4486 crc32x(crc, crc, tmp0);
4487 ldr(tmp2, Address(buf, 24));
4488 crc32x(crc, crc, tmp1);
4489 ldr(tmp3, Address(buf, 32));
4490 crc32x(crc, crc, tmp2);
4491 ldr(tmp0, Address(buf, 40));
4492 crc32x(crc, crc, tmp3);
4493 ldr(tmp1, Address(buf, 48));
4494 crc32x(crc, crc, tmp0);
4495 ldr(tmp2, Address(buf, 56));
4496 crc32x(crc, crc, tmp1);
4497 ldr(tmp3, Address(pre(buf, 64)));
4498
4499 b(CRC_by64_loop);
4500
4501 align(CodeEntryAlignment);
4502 BIND(CRC_by64_loop);
4503 subs(len, len, 64);
4504 crc32x(crc, crc, tmp2);
4505 ldr(tmp0, Address(buf, 8));
4506 crc32x(crc, crc, tmp3);
4507 ldr(tmp1, Address(buf, 16));
4508 crc32x(crc, crc, tmp0);
4509 ldr(tmp2, Address(buf, 24));
4510 crc32x(crc, crc, tmp1);
4511 ldr(tmp3, Address(buf, 32));
4512 crc32x(crc, crc, tmp2);
4513 ldr(tmp0, Address(buf, 40));
4514 crc32x(crc, crc, tmp3);
4515 ldr(tmp1, Address(buf, 48));
4516 crc32x(crc, crc, tmp0);
4517 ldr(tmp2, Address(buf, 56));
4518 crc32x(crc, crc, tmp1);
4519 ldr(tmp3, Address(pre(buf, 64)));
4520 br(Assembler::GE, CRC_by64_loop);
4521
4522 // post-loop
4523 crc32x(crc, crc, tmp2);
4524 crc32x(crc, crc, tmp3);
4525
4526 sub(len, len, 64);
4527 add(buf, buf, 8);
4528 cmn(len, (u1)128);
4529 br(Assembler::NE, CRC_less64);
4530 BIND(L_exit);
4531 mvnw(crc, crc);
4532 }
4533
4534 /**
4535 * @param crc register containing existing CRC (32-bit)
4536 * @param buf register pointing to input byte buffer (byte*)
4537 * @param len register containing number of bytes
4538 * @param table register that will contain address of CRC table
4539 * @param tmp scratch register
4540 */
4541 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
4542 Register table0, Register table1, Register table2, Register table3,
4543 Register tmp, Register tmp2, Register tmp3) {
4544 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
4545
4546 if (UseCryptoPmullForCRC32) {
4547 kernel_crc32_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4548 return;
4549 }
4550
4551 if (UseCRC32) {
4552 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
4553 return;
4554 }
4555
4556 mvnw(crc, crc);
4557
4558 {
4559 uint64_t offset;
4560 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4561 add(table0, table0, offset);
4562 }
4563 add(table1, table0, 1*256*sizeof(juint));
4564 add(table2, table0, 2*256*sizeof(juint));
4565 add(table3, table0, 3*256*sizeof(juint));
4566
4567 { // Neon code start
4568 cmp(len, (u1)64);
4569 br(Assembler::LT, L_by16);
4570 eor(v16, T16B, v16, v16);
4571
4572 Label L_fold;
4573
4574 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
4575
4576 ld1(v0, v1, T2D, post(buf, 32));
4577 ld1r(v4, T2D, post(tmp, 8));
4578 ld1r(v5, T2D, post(tmp, 8));
4579 ld1r(v6, T2D, post(tmp, 8));
4580 ld1r(v7, T2D, post(tmp, 8));
4581 mov(v16, S, 0, crc);
4582
4583 eor(v0, T16B, v0, v16);
4584 sub(len, len, 64);
4585
4586 BIND(L_fold);
4587 pmull(v22, T8H, v0, v5, T8B);
4588 pmull(v20, T8H, v0, v7, T8B);
4589 pmull(v23, T8H, v0, v4, T8B);
4590 pmull(v21, T8H, v0, v6, T8B);
4591
4592 pmull2(v18, T8H, v0, v5, T16B);
4593 pmull2(v16, T8H, v0, v7, T16B);
4594 pmull2(v19, T8H, v0, v4, T16B);
4595 pmull2(v17, T8H, v0, v6, T16B);
4596
4597 uzp1(v24, T8H, v20, v22);
4598 uzp2(v25, T8H, v20, v22);
4599 eor(v20, T16B, v24, v25);
4600
4601 uzp1(v26, T8H, v16, v18);
4602 uzp2(v27, T8H, v16, v18);
4603 eor(v16, T16B, v26, v27);
4604
4605 ushll2(v22, T4S, v20, T8H, 8);
4606 ushll(v20, T4S, v20, T4H, 8);
4607
4608 ushll2(v18, T4S, v16, T8H, 8);
4609 ushll(v16, T4S, v16, T4H, 8);
4610
4611 eor(v22, T16B, v23, v22);
4612 eor(v18, T16B, v19, v18);
4613 eor(v20, T16B, v21, v20);
4614 eor(v16, T16B, v17, v16);
4615
4616 uzp1(v17, T2D, v16, v20);
4617 uzp2(v21, T2D, v16, v20);
4618 eor(v17, T16B, v17, v21);
4619
4620 ushll2(v20, T2D, v17, T4S, 16);
4621 ushll(v16, T2D, v17, T2S, 16);
4622
4623 eor(v20, T16B, v20, v22);
4624 eor(v16, T16B, v16, v18);
4625
4626 uzp1(v17, T2D, v20, v16);
4627 uzp2(v21, T2D, v20, v16);
4628 eor(v28, T16B, v17, v21);
4629
4630 pmull(v22, T8H, v1, v5, T8B);
4631 pmull(v20, T8H, v1, v7, T8B);
4632 pmull(v23, T8H, v1, v4, T8B);
4633 pmull(v21, T8H, v1, v6, T8B);
4634
4635 pmull2(v18, T8H, v1, v5, T16B);
4636 pmull2(v16, T8H, v1, v7, T16B);
4637 pmull2(v19, T8H, v1, v4, T16B);
4638 pmull2(v17, T8H, v1, v6, T16B);
4639
4640 ld1(v0, v1, T2D, post(buf, 32));
4641
4642 uzp1(v24, T8H, v20, v22);
4643 uzp2(v25, T8H, v20, v22);
4644 eor(v20, T16B, v24, v25);
4645
4646 uzp1(v26, T8H, v16, v18);
4647 uzp2(v27, T8H, v16, v18);
4648 eor(v16, T16B, v26, v27);
4649
4650 ushll2(v22, T4S, v20, T8H, 8);
4651 ushll(v20, T4S, v20, T4H, 8);
4652
4653 ushll2(v18, T4S, v16, T8H, 8);
4654 ushll(v16, T4S, v16, T4H, 8);
4655
4656 eor(v22, T16B, v23, v22);
4657 eor(v18, T16B, v19, v18);
4658 eor(v20, T16B, v21, v20);
4659 eor(v16, T16B, v17, v16);
4660
4661 uzp1(v17, T2D, v16, v20);
4662 uzp2(v21, T2D, v16, v20);
4663 eor(v16, T16B, v17, v21);
4664
4665 ushll2(v20, T2D, v16, T4S, 16);
4666 ushll(v16, T2D, v16, T2S, 16);
4667
4668 eor(v20, T16B, v22, v20);
4669 eor(v16, T16B, v16, v18);
4670
4671 uzp1(v17, T2D, v20, v16);
4672 uzp2(v21, T2D, v20, v16);
4673 eor(v20, T16B, v17, v21);
4674
4675 shl(v16, T2D, v28, 1);
4676 shl(v17, T2D, v20, 1);
4677
4678 eor(v0, T16B, v0, v16);
4679 eor(v1, T16B, v1, v17);
4680
4681 subs(len, len, 32);
4682 br(Assembler::GE, L_fold);
4683
4684 mov(crc, 0);
4685 mov(tmp, v0, D, 0);
4686 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4687 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4688 mov(tmp, v0, D, 1);
4689 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4690 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4691 mov(tmp, v1, D, 0);
4692 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4693 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4694 mov(tmp, v1, D, 1);
4695 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4696 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4697
4698 add(len, len, 32);
4699 } // Neon code end
4700
4701 BIND(L_by16);
4702 subs(len, len, 16);
4703 br(Assembler::GE, L_by16_loop);
4704 adds(len, len, 16-4);
4705 br(Assembler::GE, L_by4_loop);
4706 adds(len, len, 4);
4707 br(Assembler::GT, L_by1_loop);
4708 b(L_exit);
4709
4710 BIND(L_by4_loop);
4711 ldrw(tmp, Address(post(buf, 4)));
4712 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
4713 subs(len, len, 4);
4714 br(Assembler::GE, L_by4_loop);
4715 adds(len, len, 4);
4716 br(Assembler::LE, L_exit);
4717 BIND(L_by1_loop);
4718 subs(len, len, 1);
4719 ldrb(tmp, Address(post(buf, 1)));
4720 update_byte_crc32(crc, tmp, table0);
4721 br(Assembler::GT, L_by1_loop);
4722 b(L_exit);
4723
4724 align(CodeEntryAlignment);
4725 BIND(L_by16_loop);
4726 subs(len, len, 16);
4727 ldp(tmp, tmp3, Address(post(buf, 16)));
4728 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4729 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4730 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
4731 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
4732 br(Assembler::GE, L_by16_loop);
4733 adds(len, len, 16-4);
4734 br(Assembler::GE, L_by4_loop);
4735 adds(len, len, 4);
4736 br(Assembler::GT, L_by1_loop);
4737 BIND(L_exit);
4738 mvnw(crc, crc);
4739 }
4740
4741 void MacroAssembler::kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
4742 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4743 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4744 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4745
4746 subs(tmp0, len, 384);
4747 br(Assembler::GE, CRC_by128_pre);
4748 BIND(CRC_less128);
4749 subs(len, len, 32);
4750 br(Assembler::GE, CRC_by32_loop);
4751 BIND(CRC_less32);
4752 adds(len, len, 32 - 4);
4753 br(Assembler::GE, CRC_by4_loop);
4754 adds(len, len, 4);
4755 br(Assembler::GT, CRC_by1_loop);
4756 b(L_exit);
4757
4758 BIND(CRC_by32_loop);
4759 ldp(tmp0, tmp1, Address(buf));
4760 crc32cx(crc, crc, tmp0);
4761 ldr(tmp2, Address(buf, 16));
4762 crc32cx(crc, crc, tmp1);
4763 ldr(tmp3, Address(buf, 24));
4764 crc32cx(crc, crc, tmp2);
4765 add(buf, buf, 32);
4766 subs(len, len, 32);
4767 crc32cx(crc, crc, tmp3);
4768 br(Assembler::GE, CRC_by32_loop);
4769 cmn(len, (u1)32);
4770 br(Assembler::NE, CRC_less32);
4771 b(L_exit);
4772
4773 BIND(CRC_by4_loop);
4774 ldrw(tmp0, Address(post(buf, 4)));
4775 subs(len, len, 4);
4776 crc32cw(crc, crc, tmp0);
4777 br(Assembler::GE, CRC_by4_loop);
4778 adds(len, len, 4);
4779 br(Assembler::LE, L_exit);
4780 BIND(CRC_by1_loop);
4781 ldrb(tmp0, Address(post(buf, 1)));
4782 subs(len, len, 1);
4783 crc32cb(crc, crc, tmp0);
4784 br(Assembler::GT, CRC_by1_loop);
4785 b(L_exit);
4786
4787 BIND(CRC_by128_pre);
4788 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4789 4*256*sizeof(juint) + 8*sizeof(juint) + 0x50);
4790 mov(crc, 0);
4791 crc32cx(crc, crc, tmp0);
4792 crc32cx(crc, crc, tmp1);
4793
4794 cbnz(len, CRC_less128);
4795
4796 BIND(L_exit);
4797 }
4798
4799 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf,
4800 Register len, Register tmp0, Register tmp1, Register tmp2,
4801 Register tmp3) {
4802 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4803 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4804
4805 subs(len, len, 128);
4806 br(Assembler::GE, CRC_by64_pre);
4807 BIND(CRC_less64);
4808 adds(len, len, 128-32);
4809 br(Assembler::GE, CRC_by32_loop);
4810 BIND(CRC_less32);
4811 adds(len, len, 32-4);
4812 br(Assembler::GE, CRC_by4_loop);
4813 adds(len, len, 4);
4814 br(Assembler::GT, CRC_by1_loop);
4815 b(L_exit);
4816
4817 BIND(CRC_by32_loop);
4818 ldp(tmp0, tmp1, Address(post(buf, 16)));
4819 subs(len, len, 32);
4820 crc32cx(crc, crc, tmp0);
4821 ldr(tmp2, Address(post(buf, 8)));
4822 crc32cx(crc, crc, tmp1);
4823 ldr(tmp3, Address(post(buf, 8)));
4824 crc32cx(crc, crc, tmp2);
4825 crc32cx(crc, crc, tmp3);
4826 br(Assembler::GE, CRC_by32_loop);
4827 cmn(len, (u1)32);
4828 br(Assembler::NE, CRC_less32);
4829 b(L_exit);
4830
4831 BIND(CRC_by4_loop);
4832 ldrw(tmp0, Address(post(buf, 4)));
4833 subs(len, len, 4);
4834 crc32cw(crc, crc, tmp0);
4835 br(Assembler::GE, CRC_by4_loop);
4836 adds(len, len, 4);
4837 br(Assembler::LE, L_exit);
4838 BIND(CRC_by1_loop);
4839 ldrb(tmp0, Address(post(buf, 1)));
4840 subs(len, len, 1);
4841 crc32cb(crc, crc, tmp0);
4842 br(Assembler::GT, CRC_by1_loop);
4843 b(L_exit);
4844
4845 BIND(CRC_by64_pre);
4846 sub(buf, buf, 8);
4847 ldp(tmp0, tmp1, Address(buf, 8));
4848 crc32cx(crc, crc, tmp0);
4849 ldr(tmp2, Address(buf, 24));
4850 crc32cx(crc, crc, tmp1);
4851 ldr(tmp3, Address(buf, 32));
4852 crc32cx(crc, crc, tmp2);
4853 ldr(tmp0, Address(buf, 40));
4854 crc32cx(crc, crc, tmp3);
4855 ldr(tmp1, Address(buf, 48));
4856 crc32cx(crc, crc, tmp0);
4857 ldr(tmp2, Address(buf, 56));
4858 crc32cx(crc, crc, tmp1);
4859 ldr(tmp3, Address(pre(buf, 64)));
4860
4861 b(CRC_by64_loop);
4862
4863 align(CodeEntryAlignment);
4864 BIND(CRC_by64_loop);
4865 subs(len, len, 64);
4866 crc32cx(crc, crc, tmp2);
4867 ldr(tmp0, Address(buf, 8));
4868 crc32cx(crc, crc, tmp3);
4869 ldr(tmp1, Address(buf, 16));
4870 crc32cx(crc, crc, tmp0);
4871 ldr(tmp2, Address(buf, 24));
4872 crc32cx(crc, crc, tmp1);
4873 ldr(tmp3, Address(buf, 32));
4874 crc32cx(crc, crc, tmp2);
4875 ldr(tmp0, Address(buf, 40));
4876 crc32cx(crc, crc, tmp3);
4877 ldr(tmp1, Address(buf, 48));
4878 crc32cx(crc, crc, tmp0);
4879 ldr(tmp2, Address(buf, 56));
4880 crc32cx(crc, crc, tmp1);
4881 ldr(tmp3, Address(pre(buf, 64)));
4882 br(Assembler::GE, CRC_by64_loop);
4883
4884 // post-loop
4885 crc32cx(crc, crc, tmp2);
4886 crc32cx(crc, crc, tmp3);
4887
4888 sub(len, len, 64);
4889 add(buf, buf, 8);
4890 cmn(len, (u1)128);
4891 br(Assembler::NE, CRC_less64);
4892 BIND(L_exit);
4893 }
4894
4895 /**
4896 * @param crc register containing existing CRC (32-bit)
4897 * @param buf register pointing to input byte buffer (byte*)
4898 * @param len register containing number of bytes
4899 * @param table register that will contain address of CRC table
4900 * @param tmp scratch register
4901 */
4902 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
4903 Register table0, Register table1, Register table2, Register table3,
4904 Register tmp, Register tmp2, Register tmp3) {
4905 if (UseCryptoPmullForCRC32) {
4906 kernel_crc32c_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4907 } else {
4908 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3);
4909 }
4910 }
4911
4912 void MacroAssembler::kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
4913 Register len, Register tmp0, Register tmp1, Register tmp2, size_t table_offset) {
4914 Label CRC_by128_loop;
4915 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4916
4917 sub(len, len, 256);
4918 Register table = tmp0;
4919 {
4920 uint64_t offset;
4921 adrp(table, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4922 add(table, table, offset);
4923 }
4924 add(table, table, table_offset);
4925
4926 // Registers v0..v7 are used as data registers.
4927 // Registers v16..v31 are used as tmp registers.
4928 sub(buf, buf, 0x10);
4929 ldrq(v0, Address(buf, 0x10));
4930 ldrq(v1, Address(buf, 0x20));
4931 ldrq(v2, Address(buf, 0x30));
4932 ldrq(v3, Address(buf, 0x40));
4933 ldrq(v4, Address(buf, 0x50));
4934 ldrq(v5, Address(buf, 0x60));
4935 ldrq(v6, Address(buf, 0x70));
4936 ldrq(v7, Address(pre(buf, 0x80)));
4937
4938 movi(v31, T4S, 0);
4939 mov(v31, S, 0, crc);
4940 eor(v0, T16B, v0, v31);
4941
4942 // Register v16 contains constants from the crc table.
4943 ldrq(v16, Address(table));
4944 b(CRC_by128_loop);
4945
4946 align(OptoLoopAlignment);
4947 BIND(CRC_by128_loop);
4948 pmull (v17, T1Q, v0, v16, T1D);
4949 pmull2(v18, T1Q, v0, v16, T2D);
4950 ldrq(v0, Address(buf, 0x10));
4951 eor3(v0, T16B, v17, v18, v0);
4952
4953 pmull (v19, T1Q, v1, v16, T1D);
4954 pmull2(v20, T1Q, v1, v16, T2D);
4955 ldrq(v1, Address(buf, 0x20));
4956 eor3(v1, T16B, v19, v20, v1);
4957
4958 pmull (v21, T1Q, v2, v16, T1D);
4959 pmull2(v22, T1Q, v2, v16, T2D);
4960 ldrq(v2, Address(buf, 0x30));
4961 eor3(v2, T16B, v21, v22, v2);
4962
4963 pmull (v23, T1Q, v3, v16, T1D);
4964 pmull2(v24, T1Q, v3, v16, T2D);
4965 ldrq(v3, Address(buf, 0x40));
4966 eor3(v3, T16B, v23, v24, v3);
4967
4968 pmull (v25, T1Q, v4, v16, T1D);
4969 pmull2(v26, T1Q, v4, v16, T2D);
4970 ldrq(v4, Address(buf, 0x50));
4971 eor3(v4, T16B, v25, v26, v4);
4972
4973 pmull (v27, T1Q, v5, v16, T1D);
4974 pmull2(v28, T1Q, v5, v16, T2D);
4975 ldrq(v5, Address(buf, 0x60));
4976 eor3(v5, T16B, v27, v28, v5);
4977
4978 pmull (v29, T1Q, v6, v16, T1D);
4979 pmull2(v30, T1Q, v6, v16, T2D);
4980 ldrq(v6, Address(buf, 0x70));
4981 eor3(v6, T16B, v29, v30, v6);
4982
4983 // Reuse registers v23, v24.
4984 // Using them won't block the first instruction of the next iteration.
4985 pmull (v23, T1Q, v7, v16, T1D);
4986 pmull2(v24, T1Q, v7, v16, T2D);
4987 ldrq(v7, Address(pre(buf, 0x80)));
4988 eor3(v7, T16B, v23, v24, v7);
4989
4990 subs(len, len, 0x80);
4991 br(Assembler::GE, CRC_by128_loop);
4992
4993 // fold into 512 bits
4994 // Use v31 for constants because v16 can be still in use.
4995 ldrq(v31, Address(table, 0x10));
4996
4997 pmull (v17, T1Q, v0, v31, T1D);
4998 pmull2(v18, T1Q, v0, v31, T2D);
4999 eor3(v0, T16B, v17, v18, v4);
5000
5001 pmull (v19, T1Q, v1, v31, T1D);
5002 pmull2(v20, T1Q, v1, v31, T2D);
5003 eor3(v1, T16B, v19, v20, v5);
5004
5005 pmull (v21, T1Q, v2, v31, T1D);
5006 pmull2(v22, T1Q, v2, v31, T2D);
5007 eor3(v2, T16B, v21, v22, v6);
5008
5009 pmull (v23, T1Q, v3, v31, T1D);
5010 pmull2(v24, T1Q, v3, v31, T2D);
5011 eor3(v3, T16B, v23, v24, v7);
5012
5013 // fold into 128 bits
5014 // Use v17 for constants because v31 can be still in use.
5015 ldrq(v17, Address(table, 0x20));
5016 pmull (v25, T1Q, v0, v17, T1D);
5017 pmull2(v26, T1Q, v0, v17, T2D);
5018 eor3(v3, T16B, v3, v25, v26);
5019
5020 // Use v18 for constants because v17 can be still in use.
5021 ldrq(v18, Address(table, 0x30));
5022 pmull (v27, T1Q, v1, v18, T1D);
5023 pmull2(v28, T1Q, v1, v18, T2D);
5024 eor3(v3, T16B, v3, v27, v28);
5025
5026 // Use v19 for constants because v18 can be still in use.
5027 ldrq(v19, Address(table, 0x40));
5028 pmull (v29, T1Q, v2, v19, T1D);
5029 pmull2(v30, T1Q, v2, v19, T2D);
5030 eor3(v0, T16B, v3, v29, v30);
5031
5032 add(len, len, 0x80);
5033 add(buf, buf, 0x10);
5034
5035 mov(tmp0, v0, D, 0);
5036 mov(tmp1, v0, D, 1);
5037 }
5038
5039 void MacroAssembler::addptr(const Address &dst, int32_t src) {
5040 Address adr;
5041 switch(dst.getMode()) {
5042 case Address::base_plus_offset:
5043 // This is the expected mode, although we allow all the other
5044 // forms below.
5045 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
5046 break;
5047 default:
5048 lea(rscratch2, dst);
5049 adr = Address(rscratch2);
5050 break;
5051 }
5052 ldr(rscratch1, adr);
5053 add(rscratch1, rscratch1, src);
5054 str(rscratch1, adr);
5055 }
5056
5057 void MacroAssembler::cmpptr(Register src1, Address src2) {
5058 uint64_t offset;
5059 adrp(rscratch1, src2, offset);
5060 ldr(rscratch1, Address(rscratch1, offset));
5061 cmp(src1, rscratch1);
5062 }
5063
5064 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
5065 cmp(obj1, obj2);
5066 }
5067
5068 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5069 load_method_holder(rresult, rmethod);
5070 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5071 }
5072
5073 void MacroAssembler::load_method_holder(Register holder, Register method) {
5074 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
5075 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5076 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5077 }
5078
5079 // Loads the obj's Klass* into dst.
5080 // Preserves all registers (incl src, rscratch1 and rscratch2).
5081 // Input:
5082 // src - the oop we want to load the klass from.
5083 // dst - output narrow klass.
5084 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5085 assert(UseCompactObjectHeaders, "expects UseCompactObjectHeaders");
5086 ldr(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5087 lsr(dst, dst, markWord::klass_shift);
5088 }
5089
5090 void MacroAssembler::load_klass(Register dst, Register src) {
5091 if (UseCompactObjectHeaders) {
5092 load_narrow_klass_compact(dst, src);
5093 decode_klass_not_null(dst);
5094 } else if (UseCompressedClassPointers) {
5095 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5096 decode_klass_not_null(dst);
5097 } else {
5098 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5099 }
5100 }
5101
5102 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
5103 if (RestoreMXCSROnJNICalls) {
5104 Label OK;
5105 get_fpcr(tmp1);
5106 mov(tmp2, tmp1);
5107 // Set FPCR to the state we need. We do want Round to Nearest. We
5108 // don't want non-IEEE rounding modes or floating-point traps.
5109 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
5110 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
5111 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
5112 eor(tmp2, tmp1, tmp2);
5113 cbz(tmp2, OK); // Only reset FPCR if it's wrong
5114 set_fpcr(tmp1);
5115 bind(OK);
5116 }
5117 }
5118
5119 // ((OopHandle)result).resolve();
5120 void MacroAssembler::resolve_oop_handle(Register result, Register tmp1, Register tmp2) {
5121 // OopHandle::resolve is an indirection.
5122 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp1, tmp2);
5123 }
5124
5125 // ((WeakHandle)result).resolve();
5126 void MacroAssembler::resolve_weak_handle(Register result, Register tmp1, Register tmp2) {
5127 assert_different_registers(result, tmp1, tmp2);
5128 Label resolved;
5129
5130 // A null weak handle resolves to null.
5131 cbz(result, resolved);
5132
5133 // Only 64 bit platforms support GCs that require a tmp register
5134 // WeakHandle::resolve is an indirection like jweak.
5135 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5136 result, Address(result), tmp1, tmp2);
5137 bind(resolved);
5138 }
5139
5140 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp1, Register tmp2) {
5141 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5142 ldr(dst, Address(rmethod, Method::const_offset()));
5143 ldr(dst, Address(dst, ConstMethod::constants_offset()));
5144 ldr(dst, Address(dst, ConstantPool::pool_holder_offset()));
5145 ldr(dst, Address(dst, mirror_offset));
5146 resolve_oop_handle(dst, tmp1, tmp2);
5147 }
5148
5149 void MacroAssembler::cmp_klass(Register obj, Register klass, Register tmp) {
5150 assert_different_registers(obj, klass, tmp);
5151 if (UseCompressedClassPointers) {
5152 if (UseCompactObjectHeaders) {
5153 load_narrow_klass_compact(tmp, obj);
5154 } else {
5155 ldrw(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5156 }
5157 if (CompressedKlassPointers::base() == nullptr) {
5158 cmp(klass, tmp, LSL, CompressedKlassPointers::shift());
5159 return;
5160 } else if (!AOTCodeCache::is_on_for_dump() &&
5161 ((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
5162 && CompressedKlassPointers::shift() == 0) {
5163 // Only the bottom 32 bits matter
5164 cmpw(klass, tmp);
5165 return;
5166 }
5167 decode_klass_not_null(tmp);
5168 } else {
5169 ldr(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5170 }
5171 cmp(klass, tmp);
5172 }
5173
5174 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5175 if (UseCompactObjectHeaders) {
5176 load_narrow_klass_compact(tmp1, obj1);
5177 load_narrow_klass_compact(tmp2, obj2);
5178 cmpw(tmp1, tmp2);
5179 } else if (UseCompressedClassPointers) {
5180 ldrw(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5181 ldrw(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5182 cmpw(tmp1, tmp2);
5183 } else {
5184 ldr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5185 ldr(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5186 cmp(tmp1, tmp2);
5187 }
5188 }
5189
5190 void MacroAssembler::store_klass(Register dst, Register src) {
5191 // FIXME: Should this be a store release? concurrent gcs assumes
5192 // klass length is valid if klass field is not null.
5193 assert(!UseCompactObjectHeaders, "not with compact headers");
5194 if (UseCompressedClassPointers) {
5195 encode_klass_not_null(src);
5196 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5197 } else {
5198 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5199 }
5200 }
5201
5202 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5203 assert(!UseCompactObjectHeaders, "not with compact headers");
5204 if (UseCompressedClassPointers) {
5205 // Store to klass gap in destination
5206 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
5207 }
5208 }
5209
5210 // Algorithm must match CompressedOops::encode.
5211 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5212 #ifdef ASSERT
5213 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5214 #endif
5215 verify_oop_msg(s, "broken oop in encode_heap_oop");
5216 if (CompressedOops::base() == nullptr) {
5217 if (CompressedOops::shift() != 0) {
5218 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5219 lsr(d, s, LogMinObjAlignmentInBytes);
5220 } else {
5221 mov(d, s);
5222 }
5223 } else {
5224 subs(d, s, rheapbase);
5225 csel(d, d, zr, Assembler::HS);
5226 lsr(d, d, LogMinObjAlignmentInBytes);
5227
5228 /* Old algorithm: is this any worse?
5229 Label nonnull;
5230 cbnz(r, nonnull);
5231 sub(r, r, rheapbase);
5232 bind(nonnull);
5233 lsr(r, r, LogMinObjAlignmentInBytes);
5234 */
5235 }
5236 }
5237
5238 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5239 #ifdef ASSERT
5240 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5241 if (CheckCompressedOops) {
5242 Label ok;
5243 cbnz(r, ok);
5244 stop("null oop passed to encode_heap_oop_not_null");
5245 bind(ok);
5246 }
5247 #endif
5248 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5249 if (CompressedOops::base() != nullptr) {
5250 sub(r, r, rheapbase);
5251 }
5252 if (CompressedOops::shift() != 0) {
5253 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5254 lsr(r, r, LogMinObjAlignmentInBytes);
5255 }
5256 }
5257
5258 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5259 #ifdef ASSERT
5260 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5261 if (CheckCompressedOops) {
5262 Label ok;
5263 cbnz(src, ok);
5264 stop("null oop passed to encode_heap_oop_not_null2");
5265 bind(ok);
5266 }
5267 #endif
5268 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5269
5270 Register data = src;
5271 if (CompressedOops::base() != nullptr) {
5272 sub(dst, src, rheapbase);
5273 data = dst;
5274 }
5275 if (CompressedOops::shift() != 0) {
5276 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5277 lsr(dst, data, LogMinObjAlignmentInBytes);
5278 data = dst;
5279 }
5280 if (data == src)
5281 mov(dst, src);
5282 }
5283
5284 void MacroAssembler::decode_heap_oop(Register d, Register s) {
5285 #ifdef ASSERT
5286 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5287 #endif
5288 if (CompressedOops::base() == nullptr) {
5289 if (CompressedOops::shift() != 0) {
5290 lsl(d, s, CompressedOops::shift());
5291 } else if (d != s) {
5292 mov(d, s);
5293 }
5294 } else {
5295 Label done;
5296 if (d != s)
5297 mov(d, s);
5298 cbz(s, done);
5299 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
5300 bind(done);
5301 }
5302 verify_oop_msg(d, "broken oop in decode_heap_oop");
5303 }
5304
5305 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5306 assert (UseCompressedOops, "should only be used for compressed headers");
5307 assert (Universe::heap() != nullptr, "java heap should be initialized");
5308 // Cannot assert, unverified entry point counts instructions (see .ad file)
5309 // vtableStubs also counts instructions in pd_code_size_limit.
5310 // Also do not verify_oop as this is called by verify_oop.
5311 if (CompressedOops::shift() != 0) {
5312 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5313 if (CompressedOops::base() != nullptr) {
5314 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5315 } else {
5316 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5317 }
5318 } else {
5319 assert (CompressedOops::base() == nullptr, "sanity");
5320 }
5321 }
5322
5323 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5324 assert (UseCompressedOops, "should only be used for compressed headers");
5325 assert (Universe::heap() != nullptr, "java heap should be initialized");
5326 // Cannot assert, unverified entry point counts instructions (see .ad file)
5327 // vtableStubs also counts instructions in pd_code_size_limit.
5328 // Also do not verify_oop as this is called by verify_oop.
5329 if (CompressedOops::shift() != 0) {
5330 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5331 if (CompressedOops::base() != nullptr) {
5332 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5333 } else {
5334 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5335 }
5336 } else {
5337 assert (CompressedOops::base() == nullptr, "sanity");
5338 if (dst != src) {
5339 mov(dst, src);
5340 }
5341 }
5342 }
5343
5344 MacroAssembler::KlassDecodeMode MacroAssembler::_klass_decode_mode(KlassDecodeNone);
5345
5346 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() {
5347 assert(Metaspace::initialized(), "metaspace not initialized yet");
5348 assert(_klass_decode_mode != KlassDecodeNone, "should be initialized");
5349 return _klass_decode_mode;
5350 }
5351
5352 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode(address base, int shift, const size_t range) {
5353 assert(UseCompressedClassPointers, "not using compressed class pointers");
5354
5355 // KlassDecodeMode shouldn't be set already.
5356 assert(_klass_decode_mode == KlassDecodeNone, "set once");
5357
5358 if (base == nullptr) {
5359 return KlassDecodeZero;
5360 }
5361
5362 if (operand_valid_for_logical_immediate(
5363 /*is32*/false, (uint64_t)base)) {
5364 const uint64_t range_mask = right_n_bits(log2i_ceil(range));
5365 if (((uint64_t)base & range_mask) == 0) {
5366 return KlassDecodeXor;
5367 }
5368 }
5369
5370 const uint64_t shifted_base =
5371 (uint64_t)base >> shift;
5372 if ((shifted_base & 0xffff0000ffffffff) == 0) {
5373 return KlassDecodeMovk;
5374 }
5375
5376 // No valid encoding.
5377 return KlassDecodeNone;
5378 }
5379
5380 // Check if one of the above decoding modes will work for given base, shift and range.
5381 bool MacroAssembler::check_klass_decode_mode(address base, int shift, const size_t range) {
5382 return klass_decode_mode(base, shift, range) != KlassDecodeNone;
5383 }
5384
5385 bool MacroAssembler::set_klass_decode_mode(address base, int shift, const size_t range) {
5386 _klass_decode_mode = klass_decode_mode(base, shift, range);
5387 return _klass_decode_mode != KlassDecodeNone;
5388 }
5389
5390 static Register pick_different_tmp(Register dst, Register src) {
5391 auto tmps = RegSet::of(r0, r1, r2) - RegSet::of(src, dst);
5392 return *tmps.begin();
5393 }
5394
5395 void MacroAssembler::encode_klass_not_null_for_aot(Register dst, Register src) {
5396 // we have to load the klass base from the AOT constants area but
5397 // not the shift because it is not allowed to change
5398 int shift = CompressedKlassPointers::shift();
5399 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5400 if (dst != src) {
5401 // we can load the base into dst, subtract it formthe src and shift down
5402 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5403 ldr(dst, dst);
5404 sub(dst, src, dst);
5405 lsr(dst, dst, shift);
5406 } else {
5407 // we need an extra register in order to load the coop base
5408 Register tmp = pick_different_tmp(dst, src);
5409 RegSet regs = RegSet::of(tmp);
5410 push(regs, sp);
5411 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5412 ldr(tmp, tmp);
5413 sub(dst, src, tmp);
5414 lsr(dst, dst, shift);
5415 pop(regs, sp);
5416 }
5417 }
5418
5419 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5420 if (CompressedKlassPointers::base() != nullptr && AOTCodeCache::is_on_for_dump()) {
5421 encode_klass_not_null_for_aot(dst, src);
5422 return;
5423 }
5424
5425 switch (klass_decode_mode()) {
5426 case KlassDecodeZero:
5427 if (CompressedKlassPointers::shift() != 0) {
5428 lsr(dst, src, CompressedKlassPointers::shift());
5429 } else {
5430 if (dst != src) mov(dst, src);
5431 }
5432 break;
5433
5434 case KlassDecodeXor:
5435 if (CompressedKlassPointers::shift() != 0) {
5436 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5437 lsr(dst, dst, CompressedKlassPointers::shift());
5438 } else {
5439 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5440 }
5441 break;
5442
5443 case KlassDecodeMovk:
5444 if (CompressedKlassPointers::shift() != 0) {
5445 ubfx(dst, src, CompressedKlassPointers::shift(), 32);
5446 } else {
5447 movw(dst, src);
5448 }
5449 break;
5450
5451 case KlassDecodeNone:
5452 ShouldNotReachHere();
5453 break;
5454 }
5455 }
5456
5457 void MacroAssembler::encode_klass_not_null(Register r) {
5458 encode_klass_not_null(r, r);
5459 }
5460
5461 void MacroAssembler::decode_klass_not_null_for_aot(Register dst, Register src) {
5462 // we have to load the klass base from the AOT constants area but
5463 // not the shift because it is not allowed to change
5464 int shift = CompressedKlassPointers::shift();
5465 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5466 if (dst != src) {
5467 // we can load the base into dst then add the offset with a suitable shift
5468 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5469 ldr(dst, dst);
5470 add(dst, dst, src, LSL, shift);
5471 } else {
5472 // we need an extra register in order to load the coop base
5473 Register tmp = pick_different_tmp(dst, src);
5474 RegSet regs = RegSet::of(tmp);
5475 push(regs, sp);
5476 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5477 ldr(tmp, tmp);
5478 add(dst, tmp, src, LSL, shift);
5479 pop(regs, sp);
5480 }
5481 }
5482
5483 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5484 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5485
5486 if (CompressedKlassPointers::base() != nullptr && AOTCodeCache::is_on_for_dump()) {
5487 decode_klass_not_null_for_aot(dst, src);
5488 return;
5489 }
5490
5491 switch (klass_decode_mode()) {
5492 case KlassDecodeZero:
5493 if (CompressedKlassPointers::shift() != 0) {
5494 lsl(dst, src, CompressedKlassPointers::shift());
5495 } else {
5496 if (dst != src) mov(dst, src);
5497 }
5498 break;
5499
5500 case KlassDecodeXor:
5501 if (CompressedKlassPointers::shift() != 0) {
5502 lsl(dst, src, CompressedKlassPointers::shift());
5503 eor(dst, dst, (uint64_t)CompressedKlassPointers::base());
5504 } else {
5505 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5506 }
5507 break;
5508
5509 case KlassDecodeMovk: {
5510 const uint64_t shifted_base =
5511 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5512
5513 if (dst != src) movw(dst, src);
5514 movk(dst, shifted_base >> 32, 32);
5515
5516 if (CompressedKlassPointers::shift() != 0) {
5517 lsl(dst, dst, CompressedKlassPointers::shift());
5518 }
5519
5520 break;
5521 }
5522
5523 case KlassDecodeNone:
5524 ShouldNotReachHere();
5525 break;
5526 }
5527 }
5528
5529 void MacroAssembler::decode_klass_not_null(Register r) {
5530 decode_klass_not_null(r, r);
5531 }
5532
5533 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5534 #ifdef ASSERT
5535 {
5536 ThreadInVMfromUnknown tiv;
5537 assert (UseCompressedOops, "should only be used for compressed oops");
5538 assert (Universe::heap() != nullptr, "java heap should be initialized");
5539 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5540 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5541 }
5542 #endif
5543 int oop_index = oop_recorder()->find_index(obj);
5544 InstructionMark im(this);
5545 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5546 code_section()->relocate(inst_mark(), rspec);
5547 movz(dst, 0xDEAD, 16);
5548 movk(dst, 0xBEEF);
5549 }
5550
5551 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5552 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5553 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5554 int index = oop_recorder()->find_index(k);
5555
5556 InstructionMark im(this);
5557 RelocationHolder rspec = metadata_Relocation::spec(index);
5558 code_section()->relocate(inst_mark(), rspec);
5559 narrowKlass nk = CompressedKlassPointers::encode(k);
5560 movz(dst, (nk >> 16), 16);
5561 movk(dst, nk & 0xffff);
5562 }
5563
5564 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
5565 Register dst, Address src,
5566 Register tmp1, Register tmp2) {
5567 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5568 decorators = AccessInternal::decorator_fixup(decorators, type);
5569 bool as_raw = (decorators & AS_RAW) != 0;
5570 if (as_raw) {
5571 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5572 } else {
5573 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5574 }
5575 }
5576
5577 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5578 Address dst, Register val,
5579 Register tmp1, Register tmp2, Register tmp3) {
5580 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5581 decorators = AccessInternal::decorator_fixup(decorators, type);
5582 bool as_raw = (decorators & AS_RAW) != 0;
5583 if (as_raw) {
5584 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5585 } else {
5586 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5587 }
5588 }
5589
5590 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5591 Register tmp2, DecoratorSet decorators) {
5592 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5593 }
5594
5595 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5596 Register tmp2, DecoratorSet decorators) {
5597 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5598 }
5599
5600 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5601 Register tmp2, Register tmp3, DecoratorSet decorators) {
5602 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5603 }
5604
5605 // Used for storing nulls.
5606 void MacroAssembler::store_heap_oop_null(Address dst) {
5607 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5608 }
5609
5610 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
5611 assert(oop_recorder() != nullptr, "this assembler needs a Recorder");
5612 int index = oop_recorder()->allocate_metadata_index(obj);
5613 RelocationHolder rspec = metadata_Relocation::spec(index);
5614 return Address((address)obj, rspec);
5615 }
5616
5617 // Move an oop into a register.
5618 void MacroAssembler::movoop(Register dst, jobject obj) {
5619 int oop_index;
5620 if (obj == nullptr) {
5621 oop_index = oop_recorder()->allocate_oop_index(obj);
5622 } else {
5623 #ifdef ASSERT
5624 {
5625 ThreadInVMfromUnknown tiv;
5626 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5627 }
5628 #endif
5629 oop_index = oop_recorder()->find_index(obj);
5630 }
5631 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5632
5633 if (BarrierSet::barrier_set()->barrier_set_assembler()->supports_instruction_patching()) {
5634 mov(dst, Address((address)obj, rspec));
5635 } else {
5636 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
5637 ldr(dst, Address(dummy, rspec));
5638 }
5639 }
5640
5641 // Move a metadata address into a register.
5642 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
5643 int oop_index;
5644 if (obj == nullptr) {
5645 oop_index = oop_recorder()->allocate_metadata_index(obj);
5646 } else {
5647 oop_index = oop_recorder()->find_index(obj);
5648 }
5649 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5650 mov(dst, Address((address)obj, rspec));
5651 }
5652
5653 Address MacroAssembler::constant_oop_address(jobject obj) {
5654 #ifdef ASSERT
5655 {
5656 ThreadInVMfromUnknown tiv;
5657 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5658 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5659 }
5660 #endif
5661 int oop_index = oop_recorder()->find_index(obj);
5662 return Address((address)obj, oop_Relocation::spec(oop_index));
5663 }
5664
5665 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5666 void MacroAssembler::tlab_allocate(Register obj,
5667 Register var_size_in_bytes,
5668 int con_size_in_bytes,
5669 Register t1,
5670 Register t2,
5671 Label& slow_case) {
5672 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5673 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5674 }
5675
5676 void MacroAssembler::verify_tlab() {
5677 #ifdef ASSERT
5678 if (UseTLAB && VerifyOops) {
5679 Label next, ok;
5680
5681 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5682
5683 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5684 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5685 cmp(rscratch2, rscratch1);
5686 br(Assembler::HS, next);
5687 STOP("assert(top >= start)");
5688 should_not_reach_here();
5689
5690 bind(next);
5691 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5692 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5693 cmp(rscratch2, rscratch1);
5694 br(Assembler::HS, ok);
5695 STOP("assert(top <= end)");
5696 should_not_reach_here();
5697
5698 bind(ok);
5699 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5700 }
5701 #endif
5702 }
5703
5704 // Writes to stack successive pages until offset reached to check for
5705 // stack overflow + shadow pages. This clobbers tmp.
5706 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5707 assert_different_registers(tmp, size, rscratch1);
5708 mov(tmp, sp);
5709 // Bang stack for total size given plus shadow page size.
5710 // Bang one page at a time because large size can bang beyond yellow and
5711 // red zones.
5712 Label loop;
5713 mov(rscratch1, (int)os::vm_page_size());
5714 bind(loop);
5715 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5716 subsw(size, size, rscratch1);
5717 str(size, Address(tmp));
5718 br(Assembler::GT, loop);
5719
5720 // Bang down shadow pages too.
5721 // At this point, (tmp-0) is the last address touched, so don't
5722 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5723 // was post-decremented.) Skip this address by starting at i=1, and
5724 // touch a few more pages below. N.B. It is important to touch all
5725 // the way down to and including i=StackShadowPages.
5726 for (int i = 0; i < (int)(StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()) - 1; i++) {
5727 // this could be any sized move but this is can be a debugging crumb
5728 // so the bigger the better.
5729 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5730 str(size, Address(tmp));
5731 }
5732 }
5733
5734 // Move the address of the polling page into dest.
5735 void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype) {
5736 ldr(dest, Address(rthread, JavaThread::polling_page_offset()));
5737 }
5738
5739 // Read the polling page. The address of the polling page must
5740 // already be in r.
5741 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
5742 address mark;
5743 {
5744 InstructionMark im(this);
5745 code_section()->relocate(inst_mark(), rtype);
5746 ldrw(zr, Address(r, 0));
5747 mark = inst_mark();
5748 }
5749 verify_cross_modify_fence_not_required();
5750 return mark;
5751 }
5752
5753 void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
5754 relocInfo::relocType rtype = dest.rspec().reloc()->type();
5755 uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12;
5756 uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12;
5757 uint64_t dest_page = (uint64_t)dest.target() >> 12;
5758 int64_t offset_low = dest_page - low_page;
5759 int64_t offset_high = dest_page - high_page;
5760
5761 assert(is_valid_AArch64_address(dest.target()), "bad address");
5762 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
5763
5764 InstructionMark im(this);
5765 code_section()->relocate(inst_mark(), dest.rspec());
5766 // 8143067: Ensure that the adrp can reach the dest from anywhere within
5767 // the code cache so that if it is relocated we know it will still reach
5768 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
5769 _adrp(reg1, dest.target());
5770 } else {
5771 uint64_t target = (uint64_t)dest.target();
5772 uint64_t adrp_target
5773 = (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL);
5774
5775 _adrp(reg1, (address)adrp_target);
5776 movk(reg1, target >> 32, 32);
5777 }
5778 byte_offset = (uint64_t)dest.target() & 0xfff;
5779 }
5780
5781 void MacroAssembler::load_byte_map_base(Register reg) {
5782 #if INCLUDE_CDS
5783 if (AOTCodeCache::is_on_for_dump()) {
5784 address byte_map_base_adr = AOTRuntimeConstants::card_table_address();
5785 lea(reg, ExternalAddress(byte_map_base_adr));
5786 ldr(reg, Address(reg));
5787 return;
5788 }
5789 #endif
5790 CardTableBarrierSet* ctbs = CardTableBarrierSet::barrier_set();
5791
5792 // Strictly speaking the card table base isn't an address at all, and it might
5793 // even be negative. It is thus materialised as a constant.
5794 mov(reg, (uint64_t)ctbs->card_table_base_const());
5795 }
5796
5797 void MacroAssembler::load_aotrc_address(Register reg, address a) {
5798 #if INCLUDE_CDS
5799 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
5800 if (AOTCodeCache::is_on_for_dump()) {
5801 // all aotrc field addresses should be registered in the AOTCodeCache address table
5802 lea(reg, ExternalAddress(a));
5803 } else {
5804 mov(reg, (uint64_t)a);
5805 }
5806 #else
5807 ShouldNotReachHere();
5808 #endif
5809 }
5810
5811 void MacroAssembler::build_frame(int framesize) {
5812 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5813 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5814 protect_return_address();
5815 if (framesize < ((1 << 9) + 2 * wordSize)) {
5816 sub(sp, sp, framesize);
5817 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5818 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
5819 } else {
5820 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
5821 if (PreserveFramePointer) mov(rfp, sp);
5822 if (framesize < ((1 << 12) + 2 * wordSize))
5823 sub(sp, sp, framesize - 2 * wordSize);
5824 else {
5825 mov(rscratch1, framesize - 2 * wordSize);
5826 sub(sp, sp, rscratch1);
5827 }
5828 }
5829 verify_cross_modify_fence_not_required();
5830 }
5831
5832 void MacroAssembler::remove_frame(int framesize) {
5833 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5834 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5835 if (framesize < ((1 << 9) + 2 * wordSize)) {
5836 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5837 add(sp, sp, framesize);
5838 } else {
5839 if (framesize < ((1 << 12) + 2 * wordSize))
5840 add(sp, sp, framesize - 2 * wordSize);
5841 else {
5842 mov(rscratch1, framesize - 2 * wordSize);
5843 add(sp, sp, rscratch1);
5844 }
5845 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5846 }
5847 authenticate_return_address();
5848 }
5849
5850
5851 // This method counts leading positive bytes (highest bit not set) in provided byte array
5852 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5853 // Simple and most common case of aligned small array which is not at the
5854 // end of memory page is placed here. All other cases are in stub.
5855 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5856 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5857 assert_different_registers(ary1, len, result);
5858
5859 mov(result, len);
5860 cmpw(len, 0);
5861 br(LE, DONE);
5862 cmpw(len, 4 * wordSize);
5863 br(GE, STUB_LONG); // size > 32 then go to stub
5864
5865 int shift = 64 - exact_log2(os::vm_page_size());
5866 lsl(rscratch1, ary1, shift);
5867 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5868 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5869 br(CS, STUB); // at the end of page then go to stub
5870 subs(len, len, wordSize);
5871 br(LT, END);
5872
5873 BIND(LOOP);
5874 ldr(rscratch1, Address(post(ary1, wordSize)));
5875 tst(rscratch1, UPPER_BIT_MASK);
5876 br(NE, SET_RESULT);
5877 subs(len, len, wordSize);
5878 br(GE, LOOP);
5879 cmpw(len, -wordSize);
5880 br(EQ, DONE);
5881
5882 BIND(END);
5883 ldr(rscratch1, Address(ary1));
5884 sub(rscratch2, zr, len, LSL, 3); // LSL 3 is to get bits from bytes
5885 lslv(rscratch1, rscratch1, rscratch2);
5886 tst(rscratch1, UPPER_BIT_MASK);
5887 br(NE, SET_RESULT);
5888 b(DONE);
5889
5890 BIND(STUB);
5891 RuntimeAddress count_pos = RuntimeAddress(StubRoutines::aarch64::count_positives());
5892 assert(count_pos.target() != nullptr, "count_positives stub has not been generated");
5893 address tpc1 = trampoline_call(count_pos);
5894 if (tpc1 == nullptr) {
5895 DEBUG_ONLY(reset_labels(STUB_LONG, SET_RESULT, DONE));
5896 postcond(pc() == badAddress);
5897 return nullptr;
5898 }
5899 b(DONE);
5900
5901 BIND(STUB_LONG);
5902 RuntimeAddress count_pos_long = RuntimeAddress(StubRoutines::aarch64::count_positives_long());
5903 assert(count_pos_long.target() != nullptr, "count_positives_long stub has not been generated");
5904 address tpc2 = trampoline_call(count_pos_long);
5905 if (tpc2 == nullptr) {
5906 DEBUG_ONLY(reset_labels(SET_RESULT, DONE));
5907 postcond(pc() == badAddress);
5908 return nullptr;
5909 }
5910 b(DONE);
5911
5912 BIND(SET_RESULT);
5913
5914 add(len, len, wordSize);
5915 sub(result, result, len);
5916
5917 BIND(DONE);
5918 postcond(pc() != badAddress);
5919 return pc();
5920 }
5921
5922 // Clobbers: rscratch1, rscratch2, rflags
5923 // May also clobber v0-v7 when (!UseSimpleArrayEquals && UseSIMDForArrayEquals)
5924 address MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
5925 Register tmp4, Register tmp5, Register result,
5926 Register cnt1, int elem_size) {
5927 Label DONE, SAME;
5928 Register tmp1 = rscratch1;
5929 Register tmp2 = rscratch2;
5930 int elem_per_word = wordSize/elem_size;
5931 int log_elem_size = exact_log2(elem_size);
5932 int klass_offset = arrayOopDesc::klass_offset_in_bytes();
5933 int length_offset = arrayOopDesc::length_offset_in_bytes();
5934 int base_offset
5935 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
5936 // When the length offset is not aligned to 8 bytes,
5937 // then we align it down. This is valid because the new
5938 // offset will always be the klass which is the same
5939 // for type arrays.
5940 int start_offset = align_down(length_offset, BytesPerWord);
5941 int extra_length = base_offset - start_offset;
5942 assert(start_offset == length_offset || start_offset == klass_offset,
5943 "start offset must be 8-byte-aligned or be the klass offset");
5944 assert(base_offset != start_offset, "must include the length field");
5945 extra_length = extra_length / elem_size; // We count in elements, not bytes.
5946 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16);
5947
5948 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
5949 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5950
5951 #ifndef PRODUCT
5952 {
5953 const char kind = (elem_size == 2) ? 'U' : 'L';
5954 char comment[64];
5955 os::snprintf_checked(comment, sizeof comment, "array_equals%c{", kind);
5956 BLOCK_COMMENT(comment);
5957 }
5958 #endif
5959
5960 // if (a1 == a2)
5961 // return true;
5962 cmpoop(a1, a2); // May have read barriers for a1 and a2.
5963 br(EQ, SAME);
5964
5965 if (UseSimpleArrayEquals) {
5966 Label NEXT_WORD, SHORT, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL;
5967 // if (a1 == nullptr || a2 == nullptr)
5968 // return false;
5969 // a1 & a2 == 0 means (some-pointer is null) or
5970 // (very-rare-or-even-probably-impossible-pointer-values)
5971 // so, we can save one branch in most cases
5972 tst(a1, a2);
5973 mov(result, false);
5974 br(EQ, A_MIGHT_BE_NULL);
5975 // if (a1.length != a2.length)
5976 // return false;
5977 bind(A_IS_NOT_NULL);
5978 ldrw(cnt1, Address(a1, length_offset));
5979 ldrw(tmp5, Address(a2, length_offset));
5980 cmp(cnt1, tmp5);
5981 br(NE, DONE); // If lengths differ, return false
5982 // Increase loop counter by diff between base- and actual start-offset.
5983 addw(cnt1, cnt1, extra_length);
5984 lea(a1, Address(a1, start_offset));
5985 lea(a2, Address(a2, start_offset));
5986 // Check for short strings, i.e. smaller than wordSize.
5987 subs(cnt1, cnt1, elem_per_word);
5988 br(Assembler::LT, SHORT);
5989 // Main 8 byte comparison loop.
5990 bind(NEXT_WORD); {
5991 ldr(tmp1, Address(post(a1, wordSize)));
5992 ldr(tmp2, Address(post(a2, wordSize)));
5993 subs(cnt1, cnt1, elem_per_word);
5994 eor(tmp5, tmp1, tmp2);
5995 cbnz(tmp5, DONE);
5996 } br(GT, NEXT_WORD);
5997 // Last longword. In the case where length == 4 we compare the
5998 // same longword twice, but that's still faster than another
5999 // conditional branch.
6000 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
6001 // length == 4.
6002 if (log_elem_size > 0)
6003 lsl(cnt1, cnt1, log_elem_size);
6004 ldr(tmp3, Address(a1, cnt1));
6005 ldr(tmp4, Address(a2, cnt1));
6006 eor(tmp5, tmp3, tmp4);
6007 cbnz(tmp5, DONE);
6008 b(SAME);
6009 bind(A_MIGHT_BE_NULL);
6010 // in case both a1 and a2 are not-null, proceed with loads
6011 cbz(a1, DONE);
6012 cbz(a2, DONE);
6013 b(A_IS_NOT_NULL);
6014 bind(SHORT);
6015
6016 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
6017 {
6018 ldrw(tmp1, Address(post(a1, 4)));
6019 ldrw(tmp2, Address(post(a2, 4)));
6020 eorw(tmp5, tmp1, tmp2);
6021 cbnzw(tmp5, DONE);
6022 }
6023 bind(TAIL03);
6024 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
6025 {
6026 ldrh(tmp3, Address(post(a1, 2)));
6027 ldrh(tmp4, Address(post(a2, 2)));
6028 eorw(tmp5, tmp3, tmp4);
6029 cbnzw(tmp5, DONE);
6030 }
6031 bind(TAIL01);
6032 if (elem_size == 1) { // Only needed when comparing byte arrays.
6033 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6034 {
6035 ldrb(tmp1, a1);
6036 ldrb(tmp2, a2);
6037 eorw(tmp5, tmp1, tmp2);
6038 cbnzw(tmp5, DONE);
6039 }
6040 }
6041 } else {
6042 Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB,
6043 CSET_EQ, LAST_CHECK;
6044 mov(result, false);
6045 cbz(a1, DONE);
6046 ldrw(cnt1, Address(a1, length_offset));
6047 cbz(a2, DONE);
6048 ldrw(tmp5, Address(a2, length_offset));
6049 cmp(cnt1, tmp5);
6050 br(NE, DONE); // If lengths differ, return false
6051 // Increase loop counter by diff between base- and actual start-offset.
6052 addw(cnt1, cnt1, extra_length);
6053
6054 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's
6055 // faster to perform another branch before comparing a1 and a2
6056 cmp(cnt1, (u1)elem_per_word);
6057 br(LE, SHORT); // short or same
6058 ldr(tmp3, Address(pre(a1, start_offset)));
6059 subs(zr, cnt1, stubBytesThreshold);
6060 br(GE, STUB);
6061 ldr(tmp4, Address(pre(a2, start_offset)));
6062 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6063
6064 // Main 16 byte comparison loop with 2 exits
6065 bind(NEXT_DWORD); {
6066 ldr(tmp1, Address(pre(a1, wordSize)));
6067 ldr(tmp2, Address(pre(a2, wordSize)));
6068 subs(cnt1, cnt1, 2 * elem_per_word);
6069 br(LE, TAIL);
6070 eor(tmp4, tmp3, tmp4);
6071 cbnz(tmp4, DONE);
6072 ldr(tmp3, Address(pre(a1, wordSize)));
6073 ldr(tmp4, Address(pre(a2, wordSize)));
6074 cmp(cnt1, (u1)elem_per_word);
6075 br(LE, TAIL2);
6076 cmp(tmp1, tmp2);
6077 } br(EQ, NEXT_DWORD);
6078 b(DONE);
6079
6080 bind(TAIL);
6081 eor(tmp4, tmp3, tmp4);
6082 eor(tmp2, tmp1, tmp2);
6083 lslv(tmp2, tmp2, tmp5);
6084 orr(tmp5, tmp4, tmp2);
6085 cmp(tmp5, zr);
6086 b(CSET_EQ);
6087
6088 bind(TAIL2);
6089 eor(tmp2, tmp1, tmp2);
6090 cbnz(tmp2, DONE);
6091 b(LAST_CHECK);
6092
6093 bind(STUB);
6094 ldr(tmp4, Address(pre(a2, start_offset)));
6095 if (elem_size == 2) { // convert to byte counter
6096 lsl(cnt1, cnt1, 1);
6097 }
6098 eor(tmp5, tmp3, tmp4);
6099 cbnz(tmp5, DONE);
6100 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
6101 assert(stub.target() != nullptr, "array_equals_long stub has not been generated");
6102 address tpc = trampoline_call(stub);
6103 if (tpc == nullptr) {
6104 DEBUG_ONLY(reset_labels(SHORT, LAST_CHECK, CSET_EQ, SAME, DONE));
6105 postcond(pc() == badAddress);
6106 return nullptr;
6107 }
6108 b(DONE);
6109
6110 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
6111 // so, if a2 == null => return false(0), else return true, so we can return a2
6112 mov(result, a2);
6113 b(DONE);
6114 bind(SHORT);
6115 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6116 ldr(tmp3, Address(a1, start_offset));
6117 ldr(tmp4, Address(a2, start_offset));
6118 bind(LAST_CHECK);
6119 eor(tmp4, tmp3, tmp4);
6120 lslv(tmp5, tmp4, tmp5);
6121 cmp(tmp5, zr);
6122 bind(CSET_EQ);
6123 cset(result, EQ);
6124 b(DONE);
6125 }
6126
6127 bind(SAME);
6128 mov(result, true);
6129 // That's it.
6130 bind(DONE);
6131
6132 BLOCK_COMMENT("} array_equals");
6133 postcond(pc() != badAddress);
6134 return pc();
6135 }
6136
6137 // Compare Strings
6138
6139 // For Strings we're passed the address of the first characters in a1
6140 // and a2 and the length in cnt1.
6141 // There are two implementations. For arrays >= 8 bytes, all
6142 // comparisons (including the final one, which may overlap) are
6143 // performed 8 bytes at a time. For strings < 8 bytes, we compare a
6144 // halfword, then a short, and then a byte.
6145
6146 void MacroAssembler::string_equals(Register a1, Register a2,
6147 Register result, Register cnt1)
6148 {
6149 Label SAME, DONE, SHORT, NEXT_WORD;
6150 Register tmp1 = rscratch1;
6151 Register tmp2 = rscratch2;
6152 Register cnt2 = tmp2; // cnt2 only used in array length compare
6153
6154 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
6155
6156 #ifndef PRODUCT
6157 {
6158 char comment[64];
6159 os::snprintf_checked(comment, sizeof comment, "{string_equalsL");
6160 BLOCK_COMMENT(comment);
6161 }
6162 #endif
6163
6164 mov(result, false);
6165
6166 // Check for short strings, i.e. smaller than wordSize.
6167 subs(cnt1, cnt1, wordSize);
6168 br(Assembler::LT, SHORT);
6169 // Main 8 byte comparison loop.
6170 bind(NEXT_WORD); {
6171 ldr(tmp1, Address(post(a1, wordSize)));
6172 ldr(tmp2, Address(post(a2, wordSize)));
6173 subs(cnt1, cnt1, wordSize);
6174 eor(tmp1, tmp1, tmp2);
6175 cbnz(tmp1, DONE);
6176 } br(GT, NEXT_WORD);
6177 // Last longword. In the case where length == 4 we compare the
6178 // same longword twice, but that's still faster than another
6179 // conditional branch.
6180 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
6181 // length == 4.
6182 ldr(tmp1, Address(a1, cnt1));
6183 ldr(tmp2, Address(a2, cnt1));
6184 eor(tmp2, tmp1, tmp2);
6185 cbnz(tmp2, DONE);
6186 b(SAME);
6187
6188 bind(SHORT);
6189 Label TAIL03, TAIL01;
6190
6191 tbz(cnt1, 2, TAIL03); // 0-7 bytes left.
6192 {
6193 ldrw(tmp1, Address(post(a1, 4)));
6194 ldrw(tmp2, Address(post(a2, 4)));
6195 eorw(tmp1, tmp1, tmp2);
6196 cbnzw(tmp1, DONE);
6197 }
6198 bind(TAIL03);
6199 tbz(cnt1, 1, TAIL01); // 0-3 bytes left.
6200 {
6201 ldrh(tmp1, Address(post(a1, 2)));
6202 ldrh(tmp2, Address(post(a2, 2)));
6203 eorw(tmp1, tmp1, tmp2);
6204 cbnzw(tmp1, DONE);
6205 }
6206 bind(TAIL01);
6207 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6208 {
6209 ldrb(tmp1, a1);
6210 ldrb(tmp2, a2);
6211 eorw(tmp1, tmp1, tmp2);
6212 cbnzw(tmp1, DONE);
6213 }
6214 // Arrays are equal.
6215 bind(SAME);
6216 mov(result, true);
6217
6218 // That's it.
6219 bind(DONE);
6220 BLOCK_COMMENT("} string_equals");
6221 }
6222
6223
6224 // The size of the blocks erased by the zero_blocks stub. We must
6225 // handle anything smaller than this ourselves in zero_words().
6226 const int MacroAssembler::zero_words_block_size = 8;
6227
6228 // zero_words() is used by C2 ClearArray patterns and by
6229 // C1_MacroAssembler. It is as small as possible, handling small word
6230 // counts locally and delegating anything larger to the zero_blocks
6231 // stub. It is expanded many times in compiled code, so it is
6232 // important to keep it short.
6233
6234 // ptr: Address of a buffer to be zeroed.
6235 // cnt: Count in HeapWords.
6236 //
6237 // ptr, cnt, rscratch1, and rscratch2 are clobbered.
6238 address MacroAssembler::zero_words(Register ptr, Register cnt)
6239 {
6240 assert(is_power_of_2(zero_words_block_size), "adjust this");
6241
6242 BLOCK_COMMENT("zero_words {");
6243 assert(ptr == r10 && cnt == r11, "mismatch in register usage");
6244 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6245 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6246
6247 subs(rscratch1, cnt, zero_words_block_size);
6248 Label around;
6249 br(LO, around);
6250 {
6251 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6252 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6253 // Make sure this is a C2 compilation. C1 allocates space only for
6254 // trampoline stubs generated by Call LIR ops, and in any case it
6255 // makes sense for a C1 compilation task to proceed as quickly as
6256 // possible.
6257 CompileTask* task;
6258 if (StubRoutines::aarch64::complete()
6259 && Thread::current()->is_Compiler_thread()
6260 && (task = ciEnv::current()->task())
6261 && is_c2_compile(task->comp_level())) {
6262 address tpc = trampoline_call(zero_blocks);
6263 if (tpc == nullptr) {
6264 DEBUG_ONLY(reset_labels(around));
6265 return nullptr;
6266 }
6267 } else {
6268 far_call(zero_blocks);
6269 }
6270 }
6271 bind(around);
6272
6273 // We have a few words left to do. zero_blocks has adjusted r10 and r11
6274 // for us.
6275 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) {
6276 Label l;
6277 tbz(cnt, exact_log2(i), l);
6278 for (int j = 0; j < i; j += 2) {
6279 stp(zr, zr, post(ptr, 2 * BytesPerWord));
6280 }
6281 bind(l);
6282 }
6283 {
6284 Label l;
6285 tbz(cnt, 0, l);
6286 str(zr, Address(ptr));
6287 bind(l);
6288 }
6289
6290 BLOCK_COMMENT("} zero_words");
6291 return pc();
6292 }
6293
6294 // base: Address of a buffer to be zeroed, 8 bytes aligned.
6295 // cnt: Immediate count in HeapWords.
6296 //
6297 // r10, r11, rscratch1, and rscratch2 are clobbered.
6298 address MacroAssembler::zero_words(Register base, uint64_t cnt)
6299 {
6300 assert(wordSize <= BlockZeroingLowLimit,
6301 "increase BlockZeroingLowLimit");
6302 address result = nullptr;
6303 if (cnt <= (uint64_t)BlockZeroingLowLimit / BytesPerWord) {
6304 #ifndef PRODUCT
6305 {
6306 char buf[64];
6307 os::snprintf_checked(buf, sizeof buf, "zero_words (count = %" PRIu64 ") {", cnt);
6308 BLOCK_COMMENT(buf);
6309 }
6310 #endif
6311 if (cnt >= 16) {
6312 uint64_t loops = cnt/16;
6313 if (loops > 1) {
6314 mov(rscratch2, loops - 1);
6315 }
6316 {
6317 Label loop;
6318 bind(loop);
6319 for (int i = 0; i < 16; i += 2) {
6320 stp(zr, zr, Address(base, i * BytesPerWord));
6321 }
6322 add(base, base, 16 * BytesPerWord);
6323 if (loops > 1) {
6324 subs(rscratch2, rscratch2, 1);
6325 br(GE, loop);
6326 }
6327 }
6328 }
6329 cnt %= 16;
6330 int i = cnt & 1; // store any odd word to start
6331 if (i) str(zr, Address(base));
6332 for (; i < (int)cnt; i += 2) {
6333 stp(zr, zr, Address(base, i * wordSize));
6334 }
6335 BLOCK_COMMENT("} zero_words");
6336 result = pc();
6337 } else {
6338 mov(r10, base); mov(r11, cnt);
6339 result = zero_words(r10, r11);
6340 }
6341 return result;
6342 }
6343
6344 // Zero blocks of memory by using DC ZVA.
6345 //
6346 // Aligns the base address first sufficiently for DC ZVA, then uses
6347 // DC ZVA repeatedly for every full block. cnt is the size to be
6348 // zeroed in HeapWords. Returns the count of words left to be zeroed
6349 // in cnt.
6350 //
6351 // NOTE: This is intended to be used in the zero_blocks() stub. If
6352 // you want to use it elsewhere, note that cnt must be >= 2*zva_length.
6353 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) {
6354 Register tmp = rscratch1;
6355 Register tmp2 = rscratch2;
6356 int zva_length = VM_Version::zva_length();
6357 Label initial_table_end, loop_zva;
6358 Label fini;
6359
6360 // Base must be 16 byte aligned. If not just return and let caller handle it
6361 tst(base, 0x0f);
6362 br(Assembler::NE, fini);
6363 // Align base with ZVA length.
6364 neg(tmp, base);
6365 andr(tmp, tmp, zva_length - 1);
6366
6367 // tmp: the number of bytes to be filled to align the base with ZVA length.
6368 add(base, base, tmp);
6369 sub(cnt, cnt, tmp, Assembler::ASR, 3);
6370 adr(tmp2, initial_table_end);
6371 sub(tmp2, tmp2, tmp, Assembler::LSR, 2);
6372 br(tmp2);
6373
6374 for (int i = -zva_length + 16; i < 0; i += 16)
6375 stp(zr, zr, Address(base, i));
6376 bind(initial_table_end);
6377
6378 sub(cnt, cnt, zva_length >> 3);
6379 bind(loop_zva);
6380 dc(Assembler::ZVA, base);
6381 subs(cnt, cnt, zva_length >> 3);
6382 add(base, base, zva_length);
6383 br(Assembler::GE, loop_zva);
6384 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA
6385 bind(fini);
6386 }
6387
6388 // base: Address of a buffer to be filled, 8 bytes aligned.
6389 // cnt: Count in 8-byte unit.
6390 // value: Value to be filled with.
6391 // base will point to the end of the buffer after filling.
6392 void MacroAssembler::fill_words(Register base, Register cnt, Register value)
6393 {
6394 // Algorithm:
6395 //
6396 // if (cnt == 0) {
6397 // return;
6398 // }
6399 // if ((p & 8) != 0) {
6400 // *p++ = v;
6401 // }
6402 //
6403 // scratch1 = cnt & 14;
6404 // cnt -= scratch1;
6405 // p += scratch1;
6406 // switch (scratch1 / 2) {
6407 // do {
6408 // cnt -= 16;
6409 // p[-16] = v;
6410 // p[-15] = v;
6411 // case 7:
6412 // p[-14] = v;
6413 // p[-13] = v;
6414 // case 6:
6415 // p[-12] = v;
6416 // p[-11] = v;
6417 // // ...
6418 // case 1:
6419 // p[-2] = v;
6420 // p[-1] = v;
6421 // case 0:
6422 // p += 16;
6423 // } while (cnt);
6424 // }
6425 // if ((cnt & 1) == 1) {
6426 // *p++ = v;
6427 // }
6428
6429 assert_different_registers(base, cnt, value, rscratch1, rscratch2);
6430
6431 Label fini, skip, entry, loop;
6432 const int unroll = 8; // Number of stp instructions we'll unroll
6433
6434 cbz(cnt, fini);
6435 tbz(base, 3, skip);
6436 str(value, Address(post(base, 8)));
6437 sub(cnt, cnt, 1);
6438 bind(skip);
6439
6440 andr(rscratch1, cnt, (unroll-1) * 2);
6441 sub(cnt, cnt, rscratch1);
6442 add(base, base, rscratch1, Assembler::LSL, 3);
6443 adr(rscratch2, entry);
6444 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1);
6445 br(rscratch2);
6446
6447 bind(loop);
6448 add(base, base, unroll * 16);
6449 for (int i = -unroll; i < 0; i++)
6450 stp(value, value, Address(base, i * 16));
6451 bind(entry);
6452 subs(cnt, cnt, unroll * 2);
6453 br(Assembler::GE, loop);
6454
6455 tbz(cnt, 0, fini);
6456 str(value, Address(post(base, 8)));
6457 bind(fini);
6458 }
6459
6460 // Intrinsic for
6461 //
6462 // - sun/nio/cs/ISO_8859_1$Encoder.implEncodeISOArray
6463 // return the number of characters copied.
6464 // - java/lang/StringUTF16.compress
6465 // return index of non-latin1 character if copy fails, otherwise 'len'.
6466 //
6467 // This version always returns the number of characters copied, and does not
6468 // clobber the 'len' register. A successful copy will complete with the post-
6469 // condition: 'res' == 'len', while an unsuccessful copy will exit with the
6470 // post-condition: 0 <= 'res' < 'len'.
6471 //
6472 // NOTE: Attempts to use 'ld2' (and 'umaxv' in the ISO part) has proven to
6473 // degrade performance (on Ampere Altra - Neoverse N1), to an extent
6474 // beyond the acceptable, even though the footprint would be smaller.
6475 // Using 'umaxv' in the ASCII-case comes with a small penalty but does
6476 // avoid additional bloat.
6477 //
6478 // Clobbers: src, dst, res, rscratch1, rscratch2, rflags
6479 void MacroAssembler::encode_iso_array(Register src, Register dst,
6480 Register len, Register res, bool ascii,
6481 FloatRegister vtmp0, FloatRegister vtmp1,
6482 FloatRegister vtmp2, FloatRegister vtmp3,
6483 FloatRegister vtmp4, FloatRegister vtmp5)
6484 {
6485 Register cnt = res;
6486 Register max = rscratch1;
6487 Register chk = rscratch2;
6488
6489 prfm(Address(src), PLDL1STRM);
6490 movw(cnt, len);
6491
6492 #define ASCII(insn) do { if (ascii) { insn; } } while (0)
6493
6494 Label LOOP_32, DONE_32, FAIL_32;
6495
6496 BIND(LOOP_32);
6497 {
6498 cmpw(cnt, 32);
6499 br(LT, DONE_32);
6500 ld1(vtmp0, vtmp1, vtmp2, vtmp3, T8H, Address(post(src, 64)));
6501 // Extract lower bytes.
6502 FloatRegister vlo0 = vtmp4;
6503 FloatRegister vlo1 = vtmp5;
6504 uzp1(vlo0, T16B, vtmp0, vtmp1);
6505 uzp1(vlo1, T16B, vtmp2, vtmp3);
6506 // Merge bits...
6507 orr(vtmp0, T16B, vtmp0, vtmp1);
6508 orr(vtmp2, T16B, vtmp2, vtmp3);
6509 // Extract merged upper bytes.
6510 FloatRegister vhix = vtmp0;
6511 uzp2(vhix, T16B, vtmp0, vtmp2);
6512 // ISO-check on hi-parts (all zero).
6513 // ASCII-check on lo-parts (no sign).
6514 FloatRegister vlox = vtmp1; // Merge lower bytes.
6515 ASCII(orr(vlox, T16B, vlo0, vlo1));
6516 umov(chk, vhix, D, 1); ASCII(cm(LT, vlox, T16B, vlox));
6517 fmovd(max, vhix); ASCII(umaxv(vlox, T16B, vlox));
6518 orr(chk, chk, max); ASCII(umov(max, vlox, B, 0));
6519 ASCII(orr(chk, chk, max));
6520 cbnz(chk, FAIL_32);
6521 subw(cnt, cnt, 32);
6522 st1(vlo0, vlo1, T16B, Address(post(dst, 32)));
6523 b(LOOP_32);
6524 }
6525 BIND(FAIL_32);
6526 sub(src, src, 64);
6527 BIND(DONE_32);
6528
6529 Label LOOP_8, SKIP_8;
6530
6531 BIND(LOOP_8);
6532 {
6533 cmpw(cnt, 8);
6534 br(LT, SKIP_8);
6535 FloatRegister vhi = vtmp0;
6536 FloatRegister vlo = vtmp1;
6537 ld1(vtmp3, T8H, src);
6538 uzp1(vlo, T16B, vtmp3, vtmp3);
6539 uzp2(vhi, T16B, vtmp3, vtmp3);
6540 // ISO-check on hi-parts (all zero).
6541 // ASCII-check on lo-parts (no sign).
6542 ASCII(cm(LT, vtmp2, T16B, vlo));
6543 fmovd(chk, vhi); ASCII(umaxv(vtmp2, T16B, vtmp2));
6544 ASCII(umov(max, vtmp2, B, 0));
6545 ASCII(orr(chk, chk, max));
6546 cbnz(chk, SKIP_8);
6547
6548 strd(vlo, Address(post(dst, 8)));
6549 subw(cnt, cnt, 8);
6550 add(src, src, 16);
6551 b(LOOP_8);
6552 }
6553 BIND(SKIP_8);
6554
6555 #undef ASCII
6556
6557 Label LOOP, DONE;
6558
6559 cbz(cnt, DONE);
6560 BIND(LOOP);
6561 {
6562 Register chr = rscratch1;
6563 ldrh(chr, Address(post(src, 2)));
6564 tst(chr, ascii ? 0xff80 : 0xff00);
6565 br(NE, DONE);
6566 strb(chr, Address(post(dst, 1)));
6567 subs(cnt, cnt, 1);
6568 br(GT, LOOP);
6569 }
6570 BIND(DONE);
6571 // Return index where we stopped.
6572 subw(res, len, cnt);
6573 }
6574
6575 // Inflate byte[] array to char[].
6576 // Clobbers: src, dst, len, rflags, rscratch1, v0-v6
6577 address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
6578 FloatRegister vtmp1, FloatRegister vtmp2,
6579 FloatRegister vtmp3, Register tmp4) {
6580 Label big, done, after_init, to_stub;
6581
6582 assert_different_registers(src, dst, len, tmp4, rscratch1);
6583
6584 fmovd(vtmp1, 0.0);
6585 lsrw(tmp4, len, 3);
6586 bind(after_init);
6587 cbnzw(tmp4, big);
6588 // Short string: less than 8 bytes.
6589 {
6590 Label loop, tiny;
6591
6592 cmpw(len, 4);
6593 br(LT, tiny);
6594 // Use SIMD to do 4 bytes.
6595 ldrs(vtmp2, post(src, 4));
6596 zip1(vtmp3, T8B, vtmp2, vtmp1);
6597 subw(len, len, 4);
6598 strd(vtmp3, post(dst, 8));
6599
6600 cbzw(len, done);
6601
6602 // Do the remaining bytes by steam.
6603 bind(loop);
6604 ldrb(tmp4, post(src, 1));
6605 strh(tmp4, post(dst, 2));
6606 subw(len, len, 1);
6607
6608 bind(tiny);
6609 cbnz(len, loop);
6610
6611 b(done);
6612 }
6613
6614 if (SoftwarePrefetchHintDistance >= 0) {
6615 bind(to_stub);
6616 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate());
6617 assert(stub.target() != nullptr, "large_byte_array_inflate stub has not been generated");
6618 address tpc = trampoline_call(stub);
6619 if (tpc == nullptr) {
6620 DEBUG_ONLY(reset_labels(big, done));
6621 postcond(pc() == badAddress);
6622 return nullptr;
6623 }
6624 b(after_init);
6625 }
6626
6627 // Unpack the bytes 8 at a time.
6628 bind(big);
6629 {
6630 Label loop, around, loop_last, loop_start;
6631
6632 if (SoftwarePrefetchHintDistance >= 0) {
6633 const int large_loop_threshold = (64 + 16)/8;
6634 ldrd(vtmp2, post(src, 8));
6635 andw(len, len, 7);
6636 cmp(tmp4, (u1)large_loop_threshold);
6637 br(GE, to_stub);
6638 b(loop_start);
6639
6640 bind(loop);
6641 ldrd(vtmp2, post(src, 8));
6642 bind(loop_start);
6643 subs(tmp4, tmp4, 1);
6644 br(EQ, loop_last);
6645 zip1(vtmp2, T16B, vtmp2, vtmp1);
6646 ldrd(vtmp3, post(src, 8));
6647 st1(vtmp2, T8H, post(dst, 16));
6648 subs(tmp4, tmp4, 1);
6649 zip1(vtmp3, T16B, vtmp3, vtmp1);
6650 st1(vtmp3, T8H, post(dst, 16));
6651 br(NE, loop);
6652 b(around);
6653 bind(loop_last);
6654 zip1(vtmp2, T16B, vtmp2, vtmp1);
6655 st1(vtmp2, T8H, post(dst, 16));
6656 bind(around);
6657 cbz(len, done);
6658 } else {
6659 andw(len, len, 7);
6660 bind(loop);
6661 ldrd(vtmp2, post(src, 8));
6662 sub(tmp4, tmp4, 1);
6663 zip1(vtmp3, T16B, vtmp2, vtmp1);
6664 st1(vtmp3, T8H, post(dst, 16));
6665 cbnz(tmp4, loop);
6666 }
6667 }
6668
6669 // Do the tail of up to 8 bytes.
6670 add(src, src, len);
6671 ldrd(vtmp3, Address(src, -8));
6672 add(dst, dst, len, ext::uxtw, 1);
6673 zip1(vtmp3, T16B, vtmp3, vtmp1);
6674 strq(vtmp3, Address(dst, -16));
6675
6676 bind(done);
6677 postcond(pc() != badAddress);
6678 return pc();
6679 }
6680
6681 // Compress char[] array to byte[].
6682 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
6683 // Return the array length if every element in array can be encoded,
6684 // otherwise, the index of first non-latin1 (> 0xff) character.
6685 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
6686 Register res,
6687 FloatRegister tmp0, FloatRegister tmp1,
6688 FloatRegister tmp2, FloatRegister tmp3,
6689 FloatRegister tmp4, FloatRegister tmp5) {
6690 encode_iso_array(src, dst, len, res, false, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5);
6691 }
6692
6693 // java.math.round(double a)
6694 // Returns the closest long to the argument, with ties rounding to
6695 // positive infinity. This requires some fiddling for corner
6696 // cases. We take care to avoid double rounding in e.g. (jlong)(a + 0.5).
6697 void MacroAssembler::java_round_double(Register dst, FloatRegister src,
6698 FloatRegister ftmp) {
6699 Label DONE;
6700 BLOCK_COMMENT("java_round_double: { ");
6701 fmovd(rscratch1, src);
6702 // Use RoundToNearestTiesAway unless src small and -ve.
6703 fcvtasd(dst, src);
6704 // Test if src >= 0 || abs(src) >= 0x1.0p52
6705 eor(rscratch1, rscratch1, UCONST64(1) << 63); // flip sign bit
6706 mov(rscratch2, julong_cast(0x1.0p52));
6707 cmp(rscratch1, rscratch2);
6708 br(HS, DONE); {
6709 // src < 0 && abs(src) < 0x1.0p52
6710 // src may have a fractional part, so add 0.5
6711 fmovd(ftmp, 0.5);
6712 faddd(ftmp, src, ftmp);
6713 // Convert double to jlong, use RoundTowardsNegative
6714 fcvtmsd(dst, ftmp);
6715 }
6716 bind(DONE);
6717 BLOCK_COMMENT("} java_round_double");
6718 }
6719
6720 void MacroAssembler::java_round_float(Register dst, FloatRegister src,
6721 FloatRegister ftmp) {
6722 Label DONE;
6723 BLOCK_COMMENT("java_round_float: { ");
6724 fmovs(rscratch1, src);
6725 // Use RoundToNearestTiesAway unless src small and -ve.
6726 fcvtassw(dst, src);
6727 // Test if src >= 0 || abs(src) >= 0x1.0p23
6728 eor(rscratch1, rscratch1, 0x80000000); // flip sign bit
6729 mov(rscratch2, jint_cast(0x1.0p23f));
6730 cmp(rscratch1, rscratch2);
6731 br(HS, DONE); {
6732 // src < 0 && |src| < 0x1.0p23
6733 // src may have a fractional part, so add 0.5
6734 fmovs(ftmp, 0.5f);
6735 fadds(ftmp, src, ftmp);
6736 // Convert float to jint, use RoundTowardsNegative
6737 fcvtmssw(dst, ftmp);
6738 }
6739 bind(DONE);
6740 BLOCK_COMMENT("} java_round_float");
6741 }
6742
6743 // get_thread() can be called anywhere inside generated code so we
6744 // need to save whatever non-callee save context might get clobbered
6745 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
6746 // the call setup code.
6747 //
6748 // On Linux, aarch64_get_thread_helper() clobbers only r0, r1, and flags.
6749 // On other systems, the helper is a usual C function.
6750 //
6751 void MacroAssembler::get_thread(Register dst) {
6752 RegSet saved_regs =
6753 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6754 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6755
6756 protect_return_address();
6757 push(saved_regs, sp);
6758
6759 mov(lr, ExternalAddress(CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)));
6760 blr(lr);
6761 if (dst != c_rarg0) {
6762 mov(dst, c_rarg0);
6763 }
6764
6765 pop(saved_regs, sp);
6766 authenticate_return_address();
6767 }
6768
6769 void MacroAssembler::cache_wb(Address line) {
6770 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
6771 assert(line.index() == noreg, "index should be noreg");
6772 assert(line.offset() == 0, "offset should be 0");
6773 // would like to assert this
6774 // assert(line._ext.shift == 0, "shift should be zero");
6775 if (VM_Version::supports_dcpop()) {
6776 // writeback using clear virtual address to point of persistence
6777 dc(Assembler::CVAP, line.base());
6778 } else {
6779 // no need to generate anything as Unsafe.writebackMemory should
6780 // never invoke this stub
6781 }
6782 }
6783
6784 void MacroAssembler::cache_wbsync(bool is_pre) {
6785 // we only need a barrier post sync
6786 if (!is_pre) {
6787 membar(Assembler::AnyAny);
6788 }
6789 }
6790
6791 void MacroAssembler::verify_sve_vector_length(Register tmp) {
6792 if (!UseSVE || VM_Version::get_max_supported_sve_vector_length() == FloatRegister::sve_vl_min) {
6793 return;
6794 }
6795 // Make sure that native code does not change SVE vector length.
6796 Label verify_ok;
6797 movw(tmp, zr);
6798 sve_inc(tmp, B);
6799 subsw(zr, tmp, VM_Version::get_initial_sve_vector_length());
6800 br(EQ, verify_ok);
6801 stop("Error: SVE vector length has changed since jvm startup");
6802 bind(verify_ok);
6803 }
6804
6805 void MacroAssembler::verify_ptrue() {
6806 Label verify_ok;
6807 if (!UseSVE) {
6808 return;
6809 }
6810 sve_cntp(rscratch1, B, ptrue, ptrue); // get true elements count.
6811 sve_dec(rscratch1, B);
6812 cbz(rscratch1, verify_ok);
6813 stop("Error: the preserved predicate register (p7) elements are not all true");
6814 bind(verify_ok);
6815 }
6816
6817 void MacroAssembler::safepoint_isb() {
6818 isb();
6819 #ifndef PRODUCT
6820 if (VerifyCrossModifyFence) {
6821 // Clear the thread state.
6822 strb(zr, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6823 }
6824 #endif
6825 }
6826
6827 #ifndef PRODUCT
6828 void MacroAssembler::verify_cross_modify_fence_not_required() {
6829 if (VerifyCrossModifyFence) {
6830 // Check if thread needs a cross modify fence.
6831 ldrb(rscratch1, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6832 Label fence_not_required;
6833 cbz(rscratch1, fence_not_required);
6834 // If it does then fail.
6835 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::verify_cross_modify_fence_failure)));
6836 mov(c_rarg0, rthread);
6837 blr(rscratch1);
6838 bind(fence_not_required);
6839 }
6840 }
6841 #endif
6842
6843 void MacroAssembler::spin_wait() {
6844 block_comment("spin_wait {");
6845 for (int i = 0; i < VM_Version::spin_wait_desc().inst_count(); ++i) {
6846 switch (VM_Version::spin_wait_desc().inst()) {
6847 case SpinWait::NOP:
6848 nop();
6849 break;
6850 case SpinWait::ISB:
6851 isb();
6852 break;
6853 case SpinWait::YIELD:
6854 yield();
6855 break;
6856 case SpinWait::SB:
6857 assert(VM_Version::supports_sb(), "current CPU does not support SB instruction");
6858 sb();
6859 break;
6860 default:
6861 ShouldNotReachHere();
6862 }
6863 }
6864 block_comment("}");
6865 }
6866
6867 // Stack frame creation/removal
6868
6869 void MacroAssembler::enter(bool strip_ret_addr) {
6870 if (strip_ret_addr) {
6871 // Addresses can only be signed once. If there are multiple nested frames being created
6872 // in the same function, then the return address needs stripping first.
6873 strip_return_address();
6874 }
6875 protect_return_address();
6876 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
6877 mov(rfp, sp);
6878 }
6879
6880 void MacroAssembler::leave() {
6881 mov(sp, rfp);
6882 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
6883 authenticate_return_address();
6884 }
6885
6886 // ROP Protection
6887 // Use the AArch64 PAC feature to add ROP protection for generated code. Use whenever creating/
6888 // destroying stack frames or whenever directly loading/storing the LR to memory.
6889 // If ROP protection is not set then these functions are no-ops.
6890 // For more details on PAC see pauth_aarch64.hpp.
6891
6892 // Sign the LR. Use during construction of a stack frame, before storing the LR to memory.
6893 // Uses value zero as the modifier.
6894 //
6895 void MacroAssembler::protect_return_address() {
6896 if (VM_Version::use_rop_protection()) {
6897 check_return_address();
6898 paciaz();
6899 }
6900 }
6901
6902 // Sign the return value in the given register. Use before updating the LR in the existing stack
6903 // frame for the current function.
6904 // Uses value zero as the modifier.
6905 //
6906 void MacroAssembler::protect_return_address(Register return_reg) {
6907 if (VM_Version::use_rop_protection()) {
6908 check_return_address(return_reg);
6909 paciza(return_reg);
6910 }
6911 }
6912
6913 // Authenticate the LR. Use before function return, after restoring FP and loading LR from memory.
6914 // Uses value zero as the modifier.
6915 //
6916 void MacroAssembler::authenticate_return_address() {
6917 if (VM_Version::use_rop_protection()) {
6918 autiaz();
6919 check_return_address();
6920 }
6921 }
6922
6923 // Authenticate the return value in the given register. Use before updating the LR in the existing
6924 // stack frame for the current function.
6925 // Uses value zero as the modifier.
6926 //
6927 void MacroAssembler::authenticate_return_address(Register return_reg) {
6928 if (VM_Version::use_rop_protection()) {
6929 autiza(return_reg);
6930 check_return_address(return_reg);
6931 }
6932 }
6933
6934 // Strip any PAC data from LR without performing any authentication. Use with caution - only if
6935 // there is no guaranteed way of authenticating the LR.
6936 //
6937 void MacroAssembler::strip_return_address() {
6938 if (VM_Version::use_rop_protection()) {
6939 xpaclri();
6940 }
6941 }
6942
6943 #ifndef PRODUCT
6944 // PAC failures can be difficult to debug. After an authentication failure, a segfault will only
6945 // occur when the pointer is used - ie when the program returns to the invalid LR. At this point
6946 // it is difficult to debug back to the callee function.
6947 // This function simply loads from the address in the given register.
6948 // Use directly after authentication to catch authentication failures.
6949 // Also use before signing to check that the pointer is valid and hasn't already been signed.
6950 //
6951 void MacroAssembler::check_return_address(Register return_reg) {
6952 if (VM_Version::use_rop_protection()) {
6953 ldr(zr, Address(return_reg));
6954 }
6955 }
6956 #endif
6957
6958 // The java_calling_convention describes stack locations as ideal slots on
6959 // a frame with no abi restrictions. Since we must observe abi restrictions
6960 // (like the placement of the register window) the slots must be biased by
6961 // the following value.
6962 static int reg2offset_in(VMReg r) {
6963 // Account for saved rfp and lr
6964 // This should really be in_preserve_stack_slots
6965 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
6966 }
6967
6968 static int reg2offset_out(VMReg r) {
6969 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
6970 }
6971
6972 // On 64bit we will store integer like items to the stack as
6973 // 64bits items (AArch64 ABI) even though java would only store
6974 // 32bits for a parameter. On 32bit it will simply be 32bits
6975 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
6976 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp) {
6977 if (src.first()->is_stack()) {
6978 if (dst.first()->is_stack()) {
6979 // stack to stack
6980 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
6981 str(tmp, Address(sp, reg2offset_out(dst.first())));
6982 } else {
6983 // stack to reg
6984 ldrsw(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
6985 }
6986 } else if (dst.first()->is_stack()) {
6987 // reg to stack
6988 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
6989 } else {
6990 if (dst.first() != src.first()) {
6991 sxtw(dst.first()->as_Register(), src.first()->as_Register());
6992 }
6993 }
6994 }
6995
6996 // An oop arg. Must pass a handle not the oop itself
6997 void MacroAssembler::object_move(
6998 OopMap* map,
6999 int oop_handle_offset,
7000 int framesize_in_slots,
7001 VMRegPair src,
7002 VMRegPair dst,
7003 bool is_receiver,
7004 int* receiver_offset) {
7005
7006 // must pass a handle. First figure out the location we use as a handle
7007
7008 Register rHandle = dst.first()->is_stack() ? rscratch2 : dst.first()->as_Register();
7009
7010 // See if oop is null if it is we need no handle
7011
7012 if (src.first()->is_stack()) {
7013
7014 // Oop is already on the stack as an argument
7015 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
7016 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
7017 if (is_receiver) {
7018 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
7019 }
7020
7021 ldr(rscratch1, Address(rfp, reg2offset_in(src.first())));
7022 lea(rHandle, Address(rfp, reg2offset_in(src.first())));
7023 // conditionally move a null
7024 cmp(rscratch1, zr);
7025 csel(rHandle, zr, rHandle, Assembler::EQ);
7026 } else {
7027
7028 // Oop is in an a register we must store it to the space we reserve
7029 // on the stack for oop_handles and pass a handle if oop is non-null
7030
7031 const Register rOop = src.first()->as_Register();
7032 int oop_slot;
7033 if (rOop == j_rarg0)
7034 oop_slot = 0;
7035 else if (rOop == j_rarg1)
7036 oop_slot = 1;
7037 else if (rOop == j_rarg2)
7038 oop_slot = 2;
7039 else if (rOop == j_rarg3)
7040 oop_slot = 3;
7041 else if (rOop == j_rarg4)
7042 oop_slot = 4;
7043 else if (rOop == j_rarg5)
7044 oop_slot = 5;
7045 else if (rOop == j_rarg6)
7046 oop_slot = 6;
7047 else {
7048 assert(rOop == j_rarg7, "wrong register");
7049 oop_slot = 7;
7050 }
7051
7052 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
7053 int offset = oop_slot*VMRegImpl::stack_slot_size;
7054
7055 map->set_oop(VMRegImpl::stack2reg(oop_slot));
7056 // Store oop in handle area, may be null
7057 str(rOop, Address(sp, offset));
7058 if (is_receiver) {
7059 *receiver_offset = offset;
7060 }
7061
7062 cmp(rOop, zr);
7063 lea(rHandle, Address(sp, offset));
7064 // conditionally move a null
7065 csel(rHandle, zr, rHandle, Assembler::EQ);
7066 }
7067
7068 // If arg is on the stack then place it otherwise it is already in correct reg.
7069 if (dst.first()->is_stack()) {
7070 str(rHandle, Address(sp, reg2offset_out(dst.first())));
7071 }
7072 }
7073
7074 // A float arg may have to do float reg int reg conversion
7075 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp) {
7076 if (src.first()->is_stack()) {
7077 if (dst.first()->is_stack()) {
7078 ldrw(tmp, Address(rfp, reg2offset_in(src.first())));
7079 strw(tmp, Address(sp, reg2offset_out(dst.first())));
7080 } else {
7081 ldrs(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7082 }
7083 } else if (src.first() != dst.first()) {
7084 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7085 fmovs(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7086 else
7087 strs(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7088 }
7089 }
7090
7091 // A long move
7092 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp) {
7093 if (src.first()->is_stack()) {
7094 if (dst.first()->is_stack()) {
7095 // stack to stack
7096 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7097 str(tmp, Address(sp, reg2offset_out(dst.first())));
7098 } else {
7099 // stack to reg
7100 ldr(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
7101 }
7102 } else if (dst.first()->is_stack()) {
7103 // reg to stack
7104 // Do we really have to sign extend???
7105 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
7106 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
7107 } else {
7108 if (dst.first() != src.first()) {
7109 mov(dst.first()->as_Register(), src.first()->as_Register());
7110 }
7111 }
7112 }
7113
7114
7115 // A double move
7116 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp) {
7117 if (src.first()->is_stack()) {
7118 if (dst.first()->is_stack()) {
7119 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7120 str(tmp, Address(sp, reg2offset_out(dst.first())));
7121 } else {
7122 ldrd(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7123 }
7124 } else if (src.first() != dst.first()) {
7125 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7126 fmovd(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7127 else
7128 strd(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7129 }
7130 }
7131
7132 // Implements fast-locking.
7133 //
7134 // - obj: the object to be locked
7135 // - t1, t2, t3: temporary registers, will be destroyed
7136 // - slow: branched to if locking fails, absolute offset may larger than 32KB (imm14 encoding).
7137 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow) {
7138 assert_different_registers(basic_lock, obj, t1, t2, t3, rscratch1);
7139
7140 Label push;
7141 const Register top = t1;
7142 const Register mark = t2;
7143 const Register t = t3;
7144
7145 // Preload the markWord. It is important that this is the first
7146 // instruction emitted as it is part of C1's null check semantics.
7147 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7148
7149 if (UseObjectMonitorTable) {
7150 // Clear cache in case fast locking succeeds or we need to take the slow-path.
7151 str(zr, Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))));
7152 }
7153
7154 if (DiagnoseSyncOnValueBasedClasses != 0) {
7155 load_klass(t1, obj);
7156 ldrb(t1, Address(t1, Klass::misc_flags_offset()));
7157 tst(t1, KlassFlags::_misc_is_value_based_class);
7158 br(Assembler::NE, slow);
7159 }
7160
7161 // Check if the lock-stack is full.
7162 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7163 cmpw(top, (unsigned)LockStack::end_offset());
7164 br(Assembler::GE, slow);
7165
7166 // Check for recursion.
7167 subw(t, top, oopSize);
7168 ldr(t, Address(rthread, t));
7169 cmp(obj, t);
7170 br(Assembler::EQ, push);
7171
7172 // Check header for monitor (0b10).
7173 tst(mark, markWord::monitor_value);
7174 br(Assembler::NE, slow);
7175
7176 // Try to lock. Transition lock bits 0b01 => 0b00
7177 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7178 orr(mark, mark, markWord::unlocked_value);
7179 eor(t, mark, markWord::unlocked_value);
7180 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
7181 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
7182 br(Assembler::NE, slow);
7183
7184 bind(push);
7185 // After successful lock, push object on lock-stack.
7186 str(obj, Address(rthread, top));
7187 addw(top, top, oopSize);
7188 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7189 }
7190
7191 // Implements fast-unlocking.
7192 //
7193 // - obj: the object to be unlocked
7194 // - t1, t2, t3: temporary registers
7195 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
7196 void MacroAssembler::fast_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
7197 // cmpxchg clobbers rscratch1.
7198 assert_different_registers(obj, t1, t2, t3, rscratch1);
7199
7200 #ifdef ASSERT
7201 {
7202 // Check for lock-stack underflow.
7203 Label stack_ok;
7204 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
7205 cmpw(t1, (unsigned)LockStack::start_offset());
7206 br(Assembler::GE, stack_ok);
7207 STOP("Lock-stack underflow");
7208 bind(stack_ok);
7209 }
7210 #endif
7211
7212 Label unlocked, push_and_slow;
7213 const Register top = t1;
7214 const Register mark = t2;
7215 const Register t = t3;
7216
7217 // Check if obj is top of lock-stack.
7218 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7219 subw(top, top, oopSize);
7220 ldr(t, Address(rthread, top));
7221 cmp(obj, t);
7222 br(Assembler::NE, slow);
7223
7224 // Pop lock-stack.
7225 DEBUG_ONLY(str(zr, Address(rthread, top));)
7226 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7227
7228 // Check if recursive.
7229 subw(t, top, oopSize);
7230 ldr(t, Address(rthread, t));
7231 cmp(obj, t);
7232 br(Assembler::EQ, unlocked);
7233
7234 // Not recursive. Check header for monitor (0b10).
7235 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7236 tbnz(mark, log2i_exact(markWord::monitor_value), push_and_slow);
7237
7238 #ifdef ASSERT
7239 // Check header not unlocked (0b01).
7240 Label not_unlocked;
7241 tbz(mark, log2i_exact(markWord::unlocked_value), not_unlocked);
7242 stop("fast_unlock already unlocked");
7243 bind(not_unlocked);
7244 #endif
7245
7246 // Try to unlock. Transition lock bits 0b00 => 0b01
7247 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7248 orr(t, mark, markWord::unlocked_value);
7249 cmpxchg(obj, mark, t, Assembler::xword,
7250 /*acquire*/ false, /*release*/ true, /*weak*/ false, noreg);
7251 br(Assembler::EQ, unlocked);
7252
7253 bind(push_and_slow);
7254 // Restore lock-stack and handle the unlock in runtime.
7255 DEBUG_ONLY(str(obj, Address(rthread, top));)
7256 addw(top, top, oopSize);
7257 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7258 b(slow);
7259
7260 bind(unlocked);
7261 }