1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "ci/ciEnv.hpp"
29 #include "ci/ciUtilities.hpp"
30 #include "code/compiledIC.hpp"
31 #include "compiler/compileTask.hpp"
32 #include "compiler/disassembler.hpp"
33 #include "compiler/oopMap.hpp"
34 #include "gc/shared/barrierSet.hpp"
35 #include "gc/shared/barrierSetAssembler.hpp"
36 #include "gc/shared/cardTableBarrierSet.hpp"
37 #include "gc/shared/cardTable.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/tlab_globals.hpp"
40 #include "interpreter/bytecodeHistogram.hpp"
41 #include "interpreter/interpreter.hpp"
42 #include "interpreter/interpreterRuntime.hpp"
43 #include "jvm.h"
44 #include "memory/resourceArea.hpp"
45 #include "memory/universe.hpp"
46 #include "nativeInst_aarch64.hpp"
47 #include "oops/accessDecorators.hpp"
48 #include "oops/compressedKlass.inline.hpp"
49 #include "oops/compressedOops.inline.hpp"
50 #include "oops/klass.inline.hpp"
51 #include "runtime/continuation.hpp"
52 #include "runtime/icache.hpp"
53 #include "runtime/interfaceSupport.inline.hpp"
54 #include "runtime/javaThread.hpp"
55 #include "runtime/jniHandles.inline.hpp"
56 #include "runtime/sharedRuntime.hpp"
57 #include "runtime/stubRoutines.hpp"
58 #include "utilities/globalDefinitions.hpp"
59 #include "utilities/powerOfTwo.hpp"
60 #ifdef COMPILER1
61 #include "c1/c1_LIRAssembler.hpp"
62 #endif
63 #ifdef COMPILER2
64 #include "oops/oop.hpp"
65 #include "opto/compile.hpp"
66 #include "opto/node.hpp"
67 #include "opto/output.hpp"
68 #endif
69
70 #include <sys/types.h>
71
72 #ifdef PRODUCT
73 #define BLOCK_COMMENT(str) /* nothing */
74 #else
75 #define BLOCK_COMMENT(str) block_comment(str)
76 #endif
77 #define STOP(str) stop(str);
78 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
79
80 #ifdef ASSERT
81 extern "C" void disnm(intptr_t p);
82 #endif
83 // Target-dependent relocation processing
84 //
85 // Instruction sequences whose target may need to be retrieved or
86 // patched are distinguished by their leading instruction, sorting
87 // them into three main instruction groups and related subgroups.
88 //
89 // 1) Branch, Exception and System (insn count = 1)
90 // 1a) Unconditional branch (immediate):
91 // b/bl imm19
92 // 1b) Compare & branch (immediate):
93 // cbz/cbnz Rt imm19
94 // 1c) Test & branch (immediate):
95 // tbz/tbnz Rt imm14
96 // 1d) Conditional branch (immediate):
97 // b.cond imm19
98 //
99 // 2) Loads and Stores (insn count = 1)
100 // 2a) Load register literal:
101 // ldr Rt imm19
102 //
103 // 3) Data Processing Immediate (insn count = 2 or 3)
104 // 3a) PC-rel. addressing
105 // adr/adrp Rx imm21; ldr/str Ry Rx #imm12
106 // adr/adrp Rx imm21; add Ry Rx #imm12
107 // adr/adrp Rx imm21; movk Rx #imm16<<32; ldr/str Ry, [Rx, #offset_in_page]
108 // adr/adrp Rx imm21
109 // adr/adrp Rx imm21; movk Rx #imm16<<32
110 // adr/adrp Rx imm21; movk Rx #imm16<<32; add Ry, Rx, #offset_in_page
111 // The latter form can only happen when the target is an
112 // ExternalAddress, and (by definition) ExternalAddresses don't
113 // move. Because of that property, there is never any need to
114 // patch the last of the three instructions. However,
115 // MacroAssembler::target_addr_for_insn takes all three
116 // instructions into account and returns the correct address.
117 // 3b) Move wide (immediate)
118 // movz Rx #imm16; movk Rx #imm16 << 16; movk Rx #imm16 << 32;
119 //
120 // A switch on a subset of the instruction's bits provides an
121 // efficient dispatch to these subcases.
122 //
123 // insn[28:26] -> main group ('x' == don't care)
124 // 00x -> UNALLOCATED
125 // 100 -> Data Processing Immediate
126 // 101 -> Branch, Exception and System
127 // x1x -> Loads and Stores
128 //
129 // insn[30:25] -> subgroup ('_' == group, 'x' == don't care).
130 // n.b. in some cases extra bits need to be checked to verify the
131 // instruction is as expected
132 //
133 // 1) ... xx101x Branch, Exception and System
134 // 1a) 00___x Unconditional branch (immediate)
135 // 1b) 01___0 Compare & branch (immediate)
136 // 1c) 01___1 Test & branch (immediate)
137 // 1d) 10___0 Conditional branch (immediate)
138 // other Should not happen
139 //
140 // 2) ... xxx1x0 Loads and Stores
141 // 2a) xx1__00 Load/Store register (insn[28] == 1 && insn[24] == 0)
142 // 2aa) x01__00 Load register literal (i.e. requires insn[29] == 0)
143 // strictly should be 64 bit non-FP/SIMD i.e.
144 // 0101_000 (i.e. requires insn[31:24] == 01011000)
145 //
146 // 3) ... xx100x Data Processing Immediate
147 // 3a) xx___00 PC-rel. addressing (n.b. requires insn[24] == 0)
148 // 3b) xx___101 Move wide (immediate) (n.b. requires insn[24:23] == 01)
149 // strictly should be 64 bit movz #imm16<<0
150 // 110___10100 (i.e. requires insn[31:21] == 11010010100)
151 //
152
153 static uint32_t insn_at(address insn_addr, int n) {
154 return ((uint32_t*)insn_addr)[n];
155 }
156
157 template<typename T>
158 class RelocActions : public AllStatic {
159
160 public:
161
162 static int ALWAYSINLINE run(address insn_addr, address &target) {
163 int instructions = 1;
164 uint32_t insn = insn_at(insn_addr, 0);
165
166 uint32_t dispatch = Instruction_aarch64::extract(insn, 30, 25);
167 switch(dispatch) {
168 case 0b001010:
169 case 0b001011: {
170 instructions = T::unconditionalBranch(insn_addr, target);
171 break;
172 }
173 case 0b101010: // Conditional branch (immediate)
174 case 0b011010: { // Compare & branch (immediate)
175 instructions = T::conditionalBranch(insn_addr, target);
176 break;
177 }
178 case 0b011011: {
179 instructions = T::testAndBranch(insn_addr, target);
180 break;
181 }
182 case 0b001100:
183 case 0b001110:
184 case 0b011100:
185 case 0b011110:
186 case 0b101100:
187 case 0b101110:
188 case 0b111100:
189 case 0b111110: {
190 // load/store
191 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
192 // Load register (literal)
193 instructions = T::loadStore(insn_addr, target);
194 break;
195 } else {
196 // nothing to do
197 assert(target == nullptr, "did not expect to relocate target for polling page load");
198 }
199 break;
200 }
201 case 0b001000:
202 case 0b011000:
203 case 0b101000:
204 case 0b111000: {
205 // adr/adrp
206 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
207 int shift = Instruction_aarch64::extract(insn, 31, 31);
208 if (shift) {
209 uint32_t insn2 = insn_at(insn_addr, 1);
210 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
211 Instruction_aarch64::extract(insn, 4, 0) ==
212 Instruction_aarch64::extract(insn2, 9, 5)) {
213 instructions = T::adrp(insn_addr, target, T::adrpMem);
214 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
215 Instruction_aarch64::extract(insn, 4, 0) ==
216 Instruction_aarch64::extract(insn2, 4, 0)) {
217 instructions = T::adrp(insn_addr, target, T::adrpAdd);
218 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
219 Instruction_aarch64::extract(insn, 4, 0) ==
220 Instruction_aarch64::extract(insn2, 4, 0)) {
221 instructions = T::adrp(insn_addr, target, T::adrpMovk);
222 } else {
223 ShouldNotReachHere();
224 }
225 } else {
226 instructions = T::adr(insn_addr, target);
227 }
228 break;
229 }
230 case 0b001001:
231 case 0b011001:
232 case 0b101001:
233 case 0b111001: {
234 instructions = T::immediate(insn_addr, target);
235 break;
236 }
237 default: {
238 ShouldNotReachHere();
239 }
240 }
241
242 T::verify(insn_addr, target);
243 return instructions * NativeInstruction::instruction_size;
244 }
245 };
246
247 class Patcher : public AllStatic {
248 public:
249 static int unconditionalBranch(address insn_addr, address &target) {
250 intptr_t offset = (target - insn_addr) >> 2;
251 Instruction_aarch64::spatch(insn_addr, 25, 0, offset);
252 return 1;
253 }
254 static int conditionalBranch(address insn_addr, address &target) {
255 intptr_t offset = (target - insn_addr) >> 2;
256 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
257 return 1;
258 }
259 static int testAndBranch(address insn_addr, address &target) {
260 intptr_t offset = (target - insn_addr) >> 2;
261 Instruction_aarch64::spatch(insn_addr, 18, 5, offset);
262 return 1;
263 }
264 static int loadStore(address insn_addr, address &target) {
265 intptr_t offset = (target - insn_addr) >> 2;
266 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
267 return 1;
268 }
269 static int adr(address insn_addr, address &target) {
270 #ifdef ASSERT
271 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
272 #endif
273 // PC-rel. addressing
274 ptrdiff_t offset = target - insn_addr;
275 int offset_lo = offset & 3;
276 offset >>= 2;
277 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
278 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
279 return 1;
280 }
281 template<typename U>
282 static int adrp(address insn_addr, address &target, U inner) {
283 int instructions = 1;
284 #ifdef ASSERT
285 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
286 #endif
287 ptrdiff_t offset = target - insn_addr;
288 instructions = 2;
289 precond(inner != nullptr);
290 // Give the inner reloc a chance to modify the target.
291 address adjusted_target = target;
292 instructions = inner(insn_addr, adjusted_target);
293 uintptr_t pc_page = (uintptr_t)insn_addr >> 12;
294 uintptr_t adr_page = (uintptr_t)adjusted_target >> 12;
295 offset = adr_page - pc_page;
296 int offset_lo = offset & 3;
297 offset >>= 2;
298 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
299 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
300 return instructions;
301 }
302 static int adrpMem(address insn_addr, address &target) {
303 uintptr_t dest = (uintptr_t)target;
304 int offset_lo = dest & 0xfff;
305 uint32_t insn2 = insn_at(insn_addr, 1);
306 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
307 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo >> size);
308 guarantee(((dest >> size) << size) == dest, "misaligned target");
309 return 2;
310 }
311 static int adrpAdd(address insn_addr, address &target) {
312 uintptr_t dest = (uintptr_t)target;
313 int offset_lo = dest & 0xfff;
314 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo);
315 return 2;
316 }
317 static int adrpMovk(address insn_addr, address &target) {
318 uintptr_t dest = uintptr_t(target);
319 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 20, 5, (uintptr_t)target >> 32);
320 dest = (dest & 0xffffffffULL) | (uintptr_t(insn_addr) & 0xffff00000000ULL);
321 target = address(dest);
322 return 2;
323 }
324 static int immediate(address insn_addr, address &target) {
325 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
326 // We encode narrow ones by setting the upper 16 bits in the first
327 // instruction.
328 if (Instruction_aarch64::extract(insn_at(insn_addr, 0), 31, 21) == 0b11010010101) {
329 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
330 narrowKlass nk = CompressedKlassPointers::encode((Klass*)target);
331 Instruction_aarch64::patch(insn_addr, 20, 5, nk >> 16);
332 Instruction_aarch64::patch(insn_addr+4, 20, 5, nk & 0xffff);
333 return 2;
334 }
335 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 31, 21) == 0b11010010100, "must be");
336 uint64_t dest = (uint64_t)target;
337 // Move wide constant
338 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
339 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
340 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
341 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
342 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
343 return 3;
344 }
345 static void verify(address insn_addr, address &target) {
346 #ifdef ASSERT
347 address address_is = MacroAssembler::target_addr_for_insn(insn_addr);
348 if (!(address_is == target)) {
349 tty->print_cr("%p at %p should be %p", address_is, insn_addr, target);
350 disnm((intptr_t)insn_addr);
351 assert(address_is == target, "should be");
352 }
353 #endif
354 }
355 };
356
357 // If insn1 and insn2 use the same register to form an address, either
358 // by an offsetted LDR or a simple ADD, return the offset. If the
359 // second instruction is an LDR, the offset may be scaled.
360 static bool offset_for(uint32_t insn1, uint32_t insn2, ptrdiff_t &byte_offset) {
361 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
362 Instruction_aarch64::extract(insn1, 4, 0) ==
363 Instruction_aarch64::extract(insn2, 9, 5)) {
364 // Load/store register (unsigned immediate)
365 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
366 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
367 byte_offset <<= size;
368 return true;
369 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
370 Instruction_aarch64::extract(insn1, 4, 0) ==
371 Instruction_aarch64::extract(insn2, 4, 0)) {
372 // add (immediate)
373 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
374 return true;
375 }
376 return false;
377 }
378
379 class AArch64Decoder : public AllStatic {
380 public:
381
382 static int loadStore(address insn_addr, address &target) {
383 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
384 target = insn_addr + (offset << 2);
385 return 1;
386 }
387 static int unconditionalBranch(address insn_addr, address &target) {
388 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 25, 0);
389 target = insn_addr + (offset << 2);
390 return 1;
391 }
392 static int conditionalBranch(address insn_addr, address &target) {
393 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
394 target = address(((uint64_t)insn_addr + (offset << 2)));
395 return 1;
396 }
397 static int testAndBranch(address insn_addr, address &target) {
398 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 18, 5);
399 target = address(((uint64_t)insn_addr + (offset << 2)));
400 return 1;
401 }
402 static int adr(address insn_addr, address &target) {
403 // PC-rel. addressing
404 uint32_t insn = insn_at(insn_addr, 0);
405 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
406 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
407 target = address((uint64_t)insn_addr + offset);
408 return 1;
409 }
410 template<typename U>
411 static int adrp(address insn_addr, address &target, U inner) {
412 uint32_t insn = insn_at(insn_addr, 0);
413 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
414 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
415 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
416 int shift = 12;
417 offset <<= shift;
418 uint64_t target_page = ((uint64_t)insn_addr) + offset;
419 target_page &= ((uint64_t)-1) << shift;
420 uint32_t insn2 = insn_at(insn_addr, 1);
421 target = address(target_page);
422 precond(inner != nullptr);
423 inner(insn_addr, target);
424 return 2;
425 }
426 static int adrpMem(address insn_addr, address &target) {
427 uint32_t insn2 = insn_at(insn_addr, 1);
428 // Load/store register (unsigned immediate)
429 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
430 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
431 byte_offset <<= size;
432 target += byte_offset;
433 return 2;
434 }
435 static int adrpAdd(address insn_addr, address &target) {
436 uint32_t insn2 = insn_at(insn_addr, 1);
437 // add (immediate)
438 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
439 target += byte_offset;
440 return 2;
441 }
442 static int adrpMovk(address insn_addr, address &target) {
443 uint32_t insn2 = insn_at(insn_addr, 1);
444 uint64_t dest = uint64_t(target);
445 dest = (dest & 0xffff0000ffffffff) |
446 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
447 target = address(dest);
448
449 // We know the destination 4k page. Maybe we have a third
450 // instruction.
451 uint32_t insn = insn_at(insn_addr, 0);
452 uint32_t insn3 = insn_at(insn_addr, 2);
453 ptrdiff_t byte_offset;
454 if (offset_for(insn, insn3, byte_offset)) {
455 target += byte_offset;
456 return 3;
457 } else {
458 return 2;
459 }
460 }
461 static int immediate(address insn_addr, address &target) {
462 uint32_t *insns = (uint32_t *)insn_addr;
463 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
464 // We encode narrow ones by setting the upper 16 bits in the first
465 // instruction.
466 if (Instruction_aarch64::extract(insns[0], 31, 21) == 0b11010010101) {
467 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
468 narrowKlass nk = (narrowKlass)((uint32_t(Instruction_aarch64::extract(insns[0], 20, 5)) << 16)
469 + uint32_t(Instruction_aarch64::extract(insns[1], 20, 5)));
470 target = (address)CompressedKlassPointers::decode(nk);
471 return 2;
472 }
473 assert(Instruction_aarch64::extract(insns[0], 31, 21) == 0b11010010100, "must be");
474 // Move wide constant: movz, movk, movk. See movptr().
475 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
476 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
477 target = address(uint64_t(Instruction_aarch64::extract(insns[0], 20, 5))
478 + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
479 + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
480 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
481 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
482 return 3;
483 }
484 static void verify(address insn_addr, address &target) {
485 }
486 };
487
488 address MacroAssembler::target_addr_for_insn(address insn_addr) {
489 address target;
490 RelocActions<AArch64Decoder>::run(insn_addr, target);
491 return target;
492 }
493
494 // Patch any kind of instruction; there may be several instructions.
495 // Return the total length (in bytes) of the instructions.
496 int MacroAssembler::pd_patch_instruction_size(address insn_addr, address target) {
497 return RelocActions<Patcher>::run(insn_addr, target);
498 }
499
500 int MacroAssembler::patch_oop(address insn_addr, address o) {
501 int instructions;
502 unsigned insn = *(unsigned*)insn_addr;
503 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
504
505 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
506 // narrow OOPs by setting the upper 16 bits in the first
507 // instruction.
508 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
509 // Move narrow OOP
510 uint32_t n = CompressedOops::narrow_oop_value(cast_to_oop(o));
511 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
512 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
513 instructions = 2;
514 } else {
515 // Move wide OOP
516 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
517 uintptr_t dest = (uintptr_t)o;
518 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
519 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
520 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
521 instructions = 3;
522 }
523 return instructions * NativeInstruction::instruction_size;
524 }
525
526 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
527 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
528 // We encode narrow ones by setting the upper 16 bits in the first
529 // instruction.
530 NativeInstruction *insn = nativeInstruction_at(insn_addr);
531 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 &&
532 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
533
534 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
535 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
536 return 2 * NativeInstruction::instruction_size;
537 }
538
539 address MacroAssembler::target_addr_for_insn_or_null(address insn_addr) {
540 if (NativeInstruction::is_ldrw_to_zr(insn_addr)) {
541 return nullptr;
542 }
543 return MacroAssembler::target_addr_for_insn(insn_addr);
544 }
545
546 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp) {
547 ldr(tmp, Address(rthread, JavaThread::polling_word_offset()));
548 if (at_return) {
549 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
550 // we may safely use the sp instead to perform the stack watermark check.
551 cmp(in_nmethod ? sp : rfp, tmp);
552 br(Assembler::HI, slow_path);
553 } else {
554 tbnz(tmp, log2i_exact(SafepointMechanism::poll_bit()), slow_path);
555 }
556 }
557
558 void MacroAssembler::rt_call(address dest, Register tmp) {
559 CodeBlob *cb = CodeCache::find_blob(dest);
560 if (cb) {
561 far_call(RuntimeAddress(dest));
562 } else {
563 lea(tmp, RuntimeAddress(dest));
564 blr(tmp);
565 }
566 }
567
568 void MacroAssembler::push_cont_fastpath(Register java_thread) {
569 if (!Continuations::enabled()) return;
570 Label done;
571 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
572 cmp(sp, rscratch1);
573 br(Assembler::LS, done);
574 mov(rscratch1, sp); // we can't use sp as the source in str
575 str(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
576 bind(done);
577 }
578
579 void MacroAssembler::pop_cont_fastpath(Register java_thread) {
580 if (!Continuations::enabled()) return;
581 Label done;
582 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
583 cmp(sp, rscratch1);
584 br(Assembler::LO, done);
585 str(zr, Address(java_thread, JavaThread::cont_fastpath_offset()));
586 bind(done);
587 }
588
589 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
590 // we must set sp to zero to clear frame
591 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
592
593 // must clear fp, so that compiled frames are not confused; it is
594 // possible that we need it only for debugging
595 if (clear_fp) {
596 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
597 }
598
599 // Always clear the pc because it could have been set by make_walkable()
600 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
601 }
602
603 // Calls to C land
604 //
605 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
606 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
607 // has to be reset to 0. This is required to allow proper stack traversal.
608 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
609 Register last_java_fp,
610 Register last_java_pc,
611 Register scratch) {
612
613 if (last_java_pc->is_valid()) {
614 str(last_java_pc, Address(rthread,
615 JavaThread::frame_anchor_offset()
616 + JavaFrameAnchor::last_Java_pc_offset()));
617 }
618
619 // determine last_java_sp register
620 if (last_java_sp == sp) {
621 mov(scratch, sp);
622 last_java_sp = scratch;
623 } else if (!last_java_sp->is_valid()) {
624 last_java_sp = esp;
625 }
626
627 // last_java_fp is optional
628 if (last_java_fp->is_valid()) {
629 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
630 }
631
632 // We must set sp last.
633 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
634 }
635
636 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
637 Register last_java_fp,
638 address last_java_pc,
639 Register scratch) {
640 assert(last_java_pc != nullptr, "must provide a valid PC");
641
642 adr(scratch, last_java_pc);
643 str(scratch, Address(rthread,
644 JavaThread::frame_anchor_offset()
645 + JavaFrameAnchor::last_Java_pc_offset()));
646
647 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
648 }
649
650 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
651 Register last_java_fp,
652 Label &L,
653 Register scratch) {
654 if (L.is_bound()) {
655 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
656 } else {
657 InstructionMark im(this);
658 L.add_patch_at(code(), locator());
659 set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, scratch);
660 }
661 }
662
663 static inline bool target_needs_far_branch(address addr) {
664 if (AOTCodeCache::is_on_for_dump()) {
665 return true;
666 }
667 // codecache size <= 128M
668 if (!MacroAssembler::far_branches()) {
669 return false;
670 }
671 // codecache size > 240M
672 if (MacroAssembler::codestub_branch_needs_far_jump()) {
673 return true;
674 }
675 // codecache size: 128M..240M
676 return !CodeCache::is_non_nmethod(addr);
677 }
678
679 void MacroAssembler::far_call(Address entry, Register tmp) {
680 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
681 assert(CodeCache::find_blob(entry.target()) != nullptr,
682 "destination of far call not found in code cache");
683 assert(entry.rspec().type() == relocInfo::external_word_type
684 || entry.rspec().type() == relocInfo::runtime_call_type
685 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
686 if (target_needs_far_branch(entry.target())) {
687 uint64_t offset;
688 // We can use ADRP here because we know that the total size of
689 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
690 adrp(tmp, entry, offset);
691 add(tmp, tmp, offset);
692 blr(tmp);
693 } else {
694 bl(entry);
695 }
696 }
697
698 int MacroAssembler::far_jump(Address entry, Register tmp) {
699 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
700 assert(CodeCache::find_blob(entry.target()) != nullptr,
701 "destination of far call not found in code cache");
702 assert(entry.rspec().type() == relocInfo::external_word_type
703 || entry.rspec().type() == relocInfo::runtime_call_type
704 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
705 address start = pc();
706 if (target_needs_far_branch(entry.target())) {
707 uint64_t offset;
708 // We can use ADRP here because we know that the total size of
709 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
710 adrp(tmp, entry, offset);
711 add(tmp, tmp, offset);
712 br(tmp);
713 } else {
714 b(entry);
715 }
716 return pc() - start;
717 }
718
719 void MacroAssembler::reserved_stack_check() {
720 // testing if reserved zone needs to be enabled
721 Label no_reserved_zone_enabling;
722
723 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset()));
724 cmp(sp, rscratch1);
725 br(Assembler::LO, no_reserved_zone_enabling);
726
727 enter(); // LR and FP are live.
728 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone)));
729 mov(c_rarg0, rthread);
730 blr(rscratch1);
731 leave();
732
733 // We have already removed our own frame.
734 // throw_delayed_StackOverflowError will think that it's been
735 // called by our caller.
736 lea(rscratch1, RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
737 br(rscratch1);
738 should_not_reach_here();
739
740 bind(no_reserved_zone_enabling);
741 }
742
743 static void pass_arg0(MacroAssembler* masm, Register arg) {
744 if (c_rarg0 != arg ) {
745 masm->mov(c_rarg0, arg);
746 }
747 }
748
749 static void pass_arg1(MacroAssembler* masm, Register arg) {
750 if (c_rarg1 != arg ) {
751 masm->mov(c_rarg1, arg);
752 }
753 }
754
755 static void pass_arg2(MacroAssembler* masm, Register arg) {
756 if (c_rarg2 != arg ) {
757 masm->mov(c_rarg2, arg);
758 }
759 }
760
761 static void pass_arg3(MacroAssembler* masm, Register arg) {
762 if (c_rarg3 != arg ) {
763 masm->mov(c_rarg3, arg);
764 }
765 }
766
767 void MacroAssembler::call_VM_base(Register oop_result,
768 Register java_thread,
769 Register last_java_sp,
770 Label* return_pc,
771 address entry_point,
772 int number_of_arguments,
773 bool check_exceptions) {
774 // determine java_thread register
775 if (!java_thread->is_valid()) {
776 java_thread = rthread;
777 }
778
779 // determine last_java_sp register
780 if (!last_java_sp->is_valid()) {
781 last_java_sp = esp;
782 }
783
784 // debugging support
785 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
786 assert(java_thread == rthread, "unexpected register");
787 #ifdef ASSERT
788 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
789 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
790 #endif // ASSERT
791
792 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
793 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
794
795 // push java thread (becomes first argument of C function)
796
797 mov(c_rarg0, java_thread);
798
799 // set last Java frame before call
800 assert(last_java_sp != rfp, "can't use rfp");
801
802 Label l;
803 set_last_Java_frame(last_java_sp, rfp, return_pc != nullptr ? *return_pc : l, rscratch1);
804
805 // do the call, remove parameters
806 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
807
808 // lr could be poisoned with PAC signature during throw_pending_exception
809 // if it was tail-call optimized by compiler, since lr is not callee-saved
810 // reload it with proper value
811 adr(lr, l);
812
813 // reset last Java frame
814 // Only interpreter should have to clear fp
815 reset_last_Java_frame(true);
816
817 // C++ interp handles this in the interpreter
818 check_and_handle_popframe(java_thread);
819 check_and_handle_earlyret(java_thread);
820
821 if (check_exceptions) {
822 // check for pending exceptions (java_thread is set upon return)
823 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
824 Label ok;
825 cbz(rscratch1, ok);
826 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
827 br(rscratch1);
828 bind(ok);
829 }
830
831 // get oop result if there is one and reset the value in the thread
832 if (oop_result->is_valid()) {
833 get_vm_result_oop(oop_result, java_thread);
834 }
835 }
836
837 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
838 call_VM_base(oop_result, noreg, noreg, nullptr, entry_point, number_of_arguments, check_exceptions);
839 }
840
841 // Check the entry target is always reachable from any branch.
842 static bool is_always_within_branch_range(Address entry) {
843 if (AOTCodeCache::is_on_for_dump()) {
844 return false;
845 }
846 const address target = entry.target();
847
848 if (!CodeCache::contains(target)) {
849 // We always use trampolines for callees outside CodeCache.
850 assert(entry.rspec().type() == relocInfo::runtime_call_type, "non-runtime call of an external target");
851 return false;
852 }
853
854 if (!MacroAssembler::far_branches()) {
855 return true;
856 }
857
858 if (entry.rspec().type() == relocInfo::runtime_call_type) {
859 // Runtime calls are calls of a non-compiled method (stubs, adapters).
860 // Non-compiled methods stay forever in CodeCache.
861 // We check whether the longest possible branch is within the branch range.
862 assert(CodeCache::find_blob(target) != nullptr &&
863 !CodeCache::find_blob(target)->is_nmethod(),
864 "runtime call of compiled method");
865 const address right_longest_branch_start = CodeCache::high_bound() - NativeInstruction::instruction_size;
866 const address left_longest_branch_start = CodeCache::low_bound();
867 const bool is_reachable = Assembler::reachable_from_branch_at(left_longest_branch_start, target) &&
868 Assembler::reachable_from_branch_at(right_longest_branch_start, target);
869 return is_reachable;
870 }
871
872 return false;
873 }
874
875 // Maybe emit a call via a trampoline. If the code cache is small
876 // trampolines won't be emitted.
877 address MacroAssembler::trampoline_call(Address entry) {
878 assert(entry.rspec().type() == relocInfo::runtime_call_type
879 || entry.rspec().type() == relocInfo::opt_virtual_call_type
880 || entry.rspec().type() == relocInfo::static_call_type
881 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
882
883 address target = entry.target();
884
885 if (!is_always_within_branch_range(entry)) {
886 if (!in_scratch_emit_size()) {
887 // We don't want to emit a trampoline if C2 is generating dummy
888 // code during its branch shortening phase.
889 if (entry.rspec().type() == relocInfo::runtime_call_type) {
890 assert(CodeBuffer::supports_shared_stubs(), "must support shared stubs");
891 code()->share_trampoline_for(entry.target(), offset());
892 } else {
893 address stub = emit_trampoline_stub(offset(), target);
894 if (stub == nullptr) {
895 postcond(pc() == badAddress);
896 return nullptr; // CodeCache is full
897 }
898 }
899 }
900 target = pc();
901 }
902
903 address call_pc = pc();
904 relocate(entry.rspec());
905 bl(target);
906
907 postcond(pc() != badAddress);
908 return call_pc;
909 }
910
911 // Emit a trampoline stub for a call to a target which is too far away.
912 //
913 // code sequences:
914 //
915 // call-site:
916 // branch-and-link to <destination> or <trampoline stub>
917 //
918 // Related trampoline stub for this call site in the stub section:
919 // load the call target from the constant pool
920 // branch (LR still points to the call site above)
921
922 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
923 address dest) {
924 // Max stub size: alignment nop, TrampolineStub.
925 address stub = start_a_stub(max_trampoline_stub_size());
926 if (stub == nullptr) {
927 return nullptr; // CodeBuffer::expand failed
928 }
929
930 // Create a trampoline stub relocation which relates this trampoline stub
931 // with the call instruction at insts_call_instruction_offset in the
932 // instructions code-section.
933 align(wordSize);
934 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
935 + insts_call_instruction_offset));
936 const int stub_start_offset = offset();
937
938 // Now, create the trampoline stub's code:
939 // - load the call
940 // - call
941 Label target;
942 ldr(rscratch1, target);
943 br(rscratch1);
944 bind(target);
945 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
946 "should be");
947 emit_int64((int64_t)dest);
948
949 const address stub_start_addr = addr_at(stub_start_offset);
950
951 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
952
953 end_a_stub();
954 return stub_start_addr;
955 }
956
957 int MacroAssembler::max_trampoline_stub_size() {
958 // Max stub size: alignment nop, TrampolineStub.
959 return NativeInstruction::instruction_size + NativeCallTrampolineStub::instruction_size;
960 }
961
962 void MacroAssembler::emit_static_call_stub() {
963 // CompiledDirectCall::set_to_interpreted knows the
964 // exact layout of this stub.
965
966 isb();
967 mov_metadata(rmethod, nullptr);
968
969 // Jump to the entry point of the c2i stub.
970 if (codestub_branch_needs_far_jump()) {
971 movptr(rscratch1, 0);
972 br(rscratch1);
973 } else {
974 b(pc());
975 }
976 }
977
978 int MacroAssembler::max_static_call_stub_size() {
979 // isb; movk; movz; movz; movk; movz; movz; br
980 return 8 * NativeInstruction::instruction_size;
981 }
982
983 void MacroAssembler::c2bool(Register x) {
984 // implements x == 0 ? 0 : 1
985 // note: must only look at least-significant byte of x
986 // since C-style booleans are stored in one byte
987 // only! (was bug)
988 tst(x, 0xff);
989 cset(x, Assembler::NE);
990 }
991
992 address MacroAssembler::ic_call(address entry, jint method_index) {
993 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
994 movptr(rscratch2, (intptr_t)Universe::non_oop_word());
995 return trampoline_call(Address(entry, rh));
996 }
997
998 int MacroAssembler::ic_check_size() {
999 int extra_instructions = UseCompactObjectHeaders ? 1 : 0;
1000 if (target_needs_far_branch(CAST_FROM_FN_PTR(address, SharedRuntime::get_ic_miss_stub()))) {
1001 return NativeInstruction::instruction_size * (7 + extra_instructions);
1002 } else {
1003 return NativeInstruction::instruction_size * (5 + extra_instructions);
1004 }
1005 }
1006
1007 int MacroAssembler::ic_check(int end_alignment) {
1008 Register receiver = j_rarg0;
1009 Register data = rscratch2;
1010 Register tmp1 = rscratch1;
1011 Register tmp2 = r10;
1012
1013 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1014 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1015 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1016 // before the inline cache check here, and not after
1017 align(end_alignment, offset() + ic_check_size());
1018
1019 int uep_offset = offset();
1020
1021 if (UseCompactObjectHeaders) {
1022 load_narrow_klass_compact(tmp1, receiver);
1023 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1024 cmpw(tmp1, tmp2);
1025 } else if (UseCompressedClassPointers) {
1026 ldrw(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1027 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1028 cmpw(tmp1, tmp2);
1029 } else {
1030 ldr(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1031 ldr(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1032 cmp(tmp1, tmp2);
1033 }
1034
1035 Label dont;
1036 br(Assembler::EQ, dont);
1037 far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1038 bind(dont);
1039 assert((offset() % end_alignment) == 0, "Misaligned verified entry point");
1040
1041 return uep_offset;
1042 }
1043
1044 // Implementation of call_VM versions
1045
1046 void MacroAssembler::call_VM(Register oop_result,
1047 address entry_point,
1048 bool check_exceptions) {
1049 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1050 }
1051
1052 void MacroAssembler::call_VM(Register oop_result,
1053 address entry_point,
1054 Register arg_1,
1055 bool check_exceptions) {
1056 pass_arg1(this, arg_1);
1057 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1058 }
1059
1060 void MacroAssembler::call_VM(Register oop_result,
1061 address entry_point,
1062 Register arg_1,
1063 Register arg_2,
1064 bool check_exceptions) {
1065 assert_different_registers(arg_1, c_rarg2);
1066 pass_arg2(this, arg_2);
1067 pass_arg1(this, arg_1);
1068 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1069 }
1070
1071 void MacroAssembler::call_VM(Register oop_result,
1072 address entry_point,
1073 Register arg_1,
1074 Register arg_2,
1075 Register arg_3,
1076 bool check_exceptions) {
1077 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1078 assert_different_registers(arg_2, c_rarg3);
1079 pass_arg3(this, arg_3);
1080
1081 pass_arg2(this, arg_2);
1082
1083 pass_arg1(this, arg_1);
1084 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1085 }
1086
1087 void MacroAssembler::call_VM(Register oop_result,
1088 Register last_java_sp,
1089 address entry_point,
1090 int number_of_arguments,
1091 bool check_exceptions) {
1092 call_VM_base(oop_result, rthread, last_java_sp, nullptr, entry_point, number_of_arguments, check_exceptions);
1093 }
1094
1095 void MacroAssembler::call_VM(Register oop_result,
1096 Register last_java_sp,
1097 address entry_point,
1098 Register arg_1,
1099 bool check_exceptions) {
1100 pass_arg1(this, arg_1);
1101 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1102 }
1103
1104 void MacroAssembler::call_VM(Register oop_result,
1105 Register last_java_sp,
1106 address entry_point,
1107 Register arg_1,
1108 Register arg_2,
1109 bool check_exceptions) {
1110
1111 assert_different_registers(arg_1, c_rarg2);
1112 pass_arg2(this, arg_2);
1113 pass_arg1(this, arg_1);
1114 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1115 }
1116
1117 void MacroAssembler::call_VM(Register oop_result,
1118 Register last_java_sp,
1119 address entry_point,
1120 Register arg_1,
1121 Register arg_2,
1122 Register arg_3,
1123 bool check_exceptions) {
1124 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1125 assert_different_registers(arg_2, c_rarg3);
1126 pass_arg3(this, arg_3);
1127 pass_arg2(this, arg_2);
1128 pass_arg1(this, arg_1);
1129 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1130 }
1131
1132
1133 void MacroAssembler::get_vm_result_oop(Register oop_result, Register java_thread) {
1134 ldr(oop_result, Address(java_thread, JavaThread::vm_result_oop_offset()));
1135 str(zr, Address(java_thread, JavaThread::vm_result_oop_offset()));
1136 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1137 }
1138
1139 void MacroAssembler::get_vm_result_metadata(Register metadata_result, Register java_thread) {
1140 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1141 str(zr, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1142 }
1143
1144 void MacroAssembler::align(int modulus) {
1145 align(modulus, offset());
1146 }
1147
1148 // Ensure that the code at target bytes offset from the current offset() is aligned
1149 // according to modulus.
1150 void MacroAssembler::align(int modulus, int target) {
1151 int delta = target - offset();
1152 while ((offset() + delta) % modulus != 0) nop();
1153 }
1154
1155 void MacroAssembler::post_call_nop() {
1156 if (!Continuations::enabled()) {
1157 return;
1158 }
1159 InstructionMark im(this);
1160 relocate(post_call_nop_Relocation::spec());
1161 InlineSkippedInstructionsCounter skipCounter(this);
1162 nop();
1163 movk(zr, 0);
1164 movk(zr, 0);
1165 }
1166
1167 // these are no-ops overridden by InterpreterMacroAssembler
1168
1169 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1170
1171 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1172
1173 // Look up the method for a megamorphic invokeinterface call.
1174 // The target method is determined by <intf_klass, itable_index>.
1175 // The receiver klass is in recv_klass.
1176 // On success, the result will be in method_result, and execution falls through.
1177 // On failure, execution transfers to the given label.
1178 void MacroAssembler::lookup_interface_method(Register recv_klass,
1179 Register intf_klass,
1180 RegisterOrConstant itable_index,
1181 Register method_result,
1182 Register scan_temp,
1183 Label& L_no_such_interface,
1184 bool return_method) {
1185 assert_different_registers(recv_klass, intf_klass, scan_temp);
1186 assert_different_registers(method_result, intf_klass, scan_temp);
1187 assert(recv_klass != method_result || !return_method,
1188 "recv_klass can be destroyed when method isn't needed");
1189 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1190 "caller must use same register for non-constant itable index as for method");
1191
1192 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1193 int vtable_base = in_bytes(Klass::vtable_start_offset());
1194 int itentry_off = in_bytes(itableMethodEntry::method_offset());
1195 int scan_step = itableOffsetEntry::size() * wordSize;
1196 int vte_size = vtableEntry::size_in_bytes();
1197 assert(vte_size == wordSize, "else adjust times_vte_scale");
1198
1199 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1200
1201 // Could store the aligned, prescaled offset in the klass.
1202 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
1203 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
1204 add(scan_temp, scan_temp, vtable_base);
1205
1206 if (return_method) {
1207 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1208 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1209 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
1210 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
1211 if (itentry_off)
1212 add(recv_klass, recv_klass, itentry_off);
1213 }
1214
1215 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
1216 // if (scan->interface() == intf) {
1217 // result = (klass + scan->offset() + itable_index);
1218 // }
1219 // }
1220 Label search, found_method;
1221
1222 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1223 cmp(intf_klass, method_result);
1224 br(Assembler::EQ, found_method);
1225 bind(search);
1226 // Check that the previous entry is non-null. A null entry means that
1227 // the receiver class doesn't implement the interface, and wasn't the
1228 // same as when the caller was compiled.
1229 cbz(method_result, L_no_such_interface);
1230 if (itableOffsetEntry::interface_offset() != 0) {
1231 add(scan_temp, scan_temp, scan_step);
1232 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1233 } else {
1234 ldr(method_result, Address(pre(scan_temp, scan_step)));
1235 }
1236 cmp(intf_klass, method_result);
1237 br(Assembler::NE, search);
1238
1239 bind(found_method);
1240
1241 // Got a hit.
1242 if (return_method) {
1243 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
1244 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0)));
1245 }
1246 }
1247
1248 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
1249 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
1250 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
1251 // The target method is determined by <holder_klass, itable_index>.
1252 // The receiver klass is in recv_klass.
1253 // On success, the result will be in method_result, and execution falls through.
1254 // On failure, execution transfers to the given label.
1255 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
1256 Register holder_klass,
1257 Register resolved_klass,
1258 Register method_result,
1259 Register temp_itbl_klass,
1260 Register scan_temp,
1261 int itable_index,
1262 Label& L_no_such_interface) {
1263 // 'method_result' is only used as output register at the very end of this method.
1264 // Until then we can reuse it as 'holder_offset'.
1265 Register holder_offset = method_result;
1266 assert_different_registers(resolved_klass, recv_klass, holder_klass, temp_itbl_klass, scan_temp, holder_offset);
1267
1268 int vtable_start_offset = in_bytes(Klass::vtable_start_offset());
1269 int itable_offset_entry_size = itableOffsetEntry::size() * wordSize;
1270 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
1271 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
1272
1273 Label L_loop_search_resolved_entry, L_resolved_found, L_holder_found;
1274
1275 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1276 add(recv_klass, recv_klass, vtable_start_offset + ioffset);
1277 // itableOffsetEntry[] itable = recv_klass + Klass::vtable_start_offset() + sizeof(vtableEntry) * recv_klass->_vtable_len;
1278 // temp_itbl_klass = itable[0]._interface;
1279 int vtblEntrySize = vtableEntry::size_in_bytes();
1280 assert(vtblEntrySize == wordSize, "ldr lsl shift amount must be 3");
1281 ldr(temp_itbl_klass, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1282 mov(holder_offset, zr);
1283 // scan_temp = &(itable[0]._interface)
1284 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1285
1286 // Initial checks:
1287 // - if (holder_klass != resolved_klass), go to "scan for resolved"
1288 // - if (itable[0] == holder_klass), shortcut to "holder found"
1289 // - if (itable[0] == 0), no such interface
1290 cmp(resolved_klass, holder_klass);
1291 br(Assembler::NE, L_loop_search_resolved_entry);
1292 cmp(holder_klass, temp_itbl_klass);
1293 br(Assembler::EQ, L_holder_found);
1294 cbz(temp_itbl_klass, L_no_such_interface);
1295
1296 // Loop: Look for holder_klass record in itable
1297 // do {
1298 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1299 // if (temp_itbl_klass == holder_klass) {
1300 // goto L_holder_found; // Found!
1301 // }
1302 // } while (temp_itbl_klass != 0);
1303 // goto L_no_such_interface // Not found.
1304 Label L_search_holder;
1305 bind(L_search_holder);
1306 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1307 cmp(holder_klass, temp_itbl_klass);
1308 br(Assembler::EQ, L_holder_found);
1309 cbnz(temp_itbl_klass, L_search_holder);
1310
1311 b(L_no_such_interface);
1312
1313 // Loop: Look for resolved_class record in itable
1314 // while (true) {
1315 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1316 // if (temp_itbl_klass == 0) {
1317 // goto L_no_such_interface;
1318 // }
1319 // if (temp_itbl_klass == resolved_klass) {
1320 // goto L_resolved_found; // Found!
1321 // }
1322 // if (temp_itbl_klass == holder_klass) {
1323 // holder_offset = scan_temp;
1324 // }
1325 // }
1326 //
1327 Label L_loop_search_resolved;
1328 bind(L_loop_search_resolved);
1329 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1330 bind(L_loop_search_resolved_entry);
1331 cbz(temp_itbl_klass, L_no_such_interface);
1332 cmp(resolved_klass, temp_itbl_klass);
1333 br(Assembler::EQ, L_resolved_found);
1334 cmp(holder_klass, temp_itbl_klass);
1335 br(Assembler::NE, L_loop_search_resolved);
1336 mov(holder_offset, scan_temp);
1337 b(L_loop_search_resolved);
1338
1339 // See if we already have a holder klass. If not, go and scan for it.
1340 bind(L_resolved_found);
1341 cbz(holder_offset, L_search_holder);
1342 mov(scan_temp, holder_offset);
1343
1344 // Finally, scan_temp contains holder_klass vtable offset
1345 bind(L_holder_found);
1346 ldrw(method_result, Address(scan_temp, ooffset - ioffset));
1347 add(recv_klass, recv_klass, itable_index * wordSize + in_bytes(itableMethodEntry::method_offset())
1348 - vtable_start_offset - ioffset); // substract offsets to restore the original value of recv_klass
1349 ldr(method_result, Address(recv_klass, method_result, Address::uxtw(0)));
1350 }
1351
1352 // virtual method calling
1353 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1354 RegisterOrConstant vtable_index,
1355 Register method_result) {
1356 assert(vtableEntry::size() * wordSize == 8,
1357 "adjust the scaling in the code below");
1358 int64_t vtable_offset_in_bytes = in_bytes(Klass::vtable_start_offset() + vtableEntry::method_offset());
1359
1360 if (vtable_index.is_register()) {
1361 lea(method_result, Address(recv_klass,
1362 vtable_index.as_register(),
1363 Address::lsl(LogBytesPerWord)));
1364 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
1365 } else {
1366 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
1367 ldr(method_result,
1368 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0));
1369 }
1370 }
1371
1372 void MacroAssembler::check_klass_subtype(Register sub_klass,
1373 Register super_klass,
1374 Register temp_reg,
1375 Label& L_success) {
1376 Label L_failure;
1377 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
1378 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
1379 bind(L_failure);
1380 }
1381
1382
1383 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1384 Register super_klass,
1385 Register temp_reg,
1386 Label* L_success,
1387 Label* L_failure,
1388 Label* L_slow_path,
1389 Register super_check_offset) {
1390 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset);
1391 bool must_load_sco = ! super_check_offset->is_valid();
1392 if (must_load_sco) {
1393 assert(temp_reg != noreg, "supply either a temp or a register offset");
1394 }
1395
1396 Label L_fallthrough;
1397 int label_nulls = 0;
1398 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1399 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1400 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
1401 assert(label_nulls <= 1, "at most one null in the batch");
1402
1403 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1404 Address super_check_offset_addr(super_klass, sco_offset);
1405
1406 // Hacked jmp, which may only be used just before L_fallthrough.
1407 #define final_jmp(label) \
1408 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1409 else b(label) /*omit semi*/
1410
1411 // If the pointers are equal, we are done (e.g., String[] elements).
1412 // This self-check enables sharing of secondary supertype arrays among
1413 // non-primary types such as array-of-interface. Otherwise, each such
1414 // type would need its own customized SSA.
1415 // We move this check to the front of the fast path because many
1416 // type checks are in fact trivially successful in this manner,
1417 // so we get a nicely predicted branch right at the start of the check.
1418 cmp(sub_klass, super_klass);
1419 br(Assembler::EQ, *L_success);
1420
1421 // Check the supertype display:
1422 if (must_load_sco) {
1423 ldrw(temp_reg, super_check_offset_addr);
1424 super_check_offset = temp_reg;
1425 }
1426
1427 Address super_check_addr(sub_klass, super_check_offset);
1428 ldr(rscratch1, super_check_addr);
1429 cmp(super_klass, rscratch1); // load displayed supertype
1430 br(Assembler::EQ, *L_success);
1431
1432 // This check has worked decisively for primary supers.
1433 // Secondary supers are sought in the super_cache ('super_cache_addr').
1434 // (Secondary supers are interfaces and very deeply nested subtypes.)
1435 // This works in the same check above because of a tricky aliasing
1436 // between the super_cache and the primary super display elements.
1437 // (The 'super_check_addr' can address either, as the case requires.)
1438 // Note that the cache is updated below if it does not help us find
1439 // what we need immediately.
1440 // So if it was a primary super, we can just fail immediately.
1441 // Otherwise, it's the slow path for us (no success at this point).
1442
1443 sub(rscratch1, super_check_offset, in_bytes(Klass::secondary_super_cache_offset()));
1444 if (L_failure == &L_fallthrough) {
1445 cbz(rscratch1, *L_slow_path);
1446 } else {
1447 cbnz(rscratch1, *L_failure);
1448 final_jmp(*L_slow_path);
1449 }
1450
1451 bind(L_fallthrough);
1452
1453 #undef final_jmp
1454 }
1455
1456 // These two are taken from x86, but they look generally useful
1457
1458 // scans count pointer sized words at [addr] for occurrence of value,
1459 // generic
1460 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1461 Register scratch) {
1462 Label Lloop, Lexit;
1463 cbz(count, Lexit);
1464 bind(Lloop);
1465 ldr(scratch, post(addr, wordSize));
1466 cmp(value, scratch);
1467 br(EQ, Lexit);
1468 sub(count, count, 1);
1469 cbnz(count, Lloop);
1470 bind(Lexit);
1471 }
1472
1473 // scans count 4 byte words at [addr] for occurrence of value,
1474 // generic
1475 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1476 Register scratch) {
1477 Label Lloop, Lexit;
1478 cbz(count, Lexit);
1479 bind(Lloop);
1480 ldrw(scratch, post(addr, wordSize));
1481 cmpw(value, scratch);
1482 br(EQ, Lexit);
1483 sub(count, count, 1);
1484 cbnz(count, Lloop);
1485 bind(Lexit);
1486 }
1487
1488 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
1489 Register super_klass,
1490 Register temp_reg,
1491 Register temp2_reg,
1492 Label* L_success,
1493 Label* L_failure,
1494 bool set_cond_codes) {
1495 // NB! Callers may assume that, when temp2_reg is a valid register,
1496 // this code sets it to a nonzero value.
1497
1498 assert_different_registers(sub_klass, super_klass, temp_reg);
1499 if (temp2_reg != noreg)
1500 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1501 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1502
1503 Label L_fallthrough;
1504 int label_nulls = 0;
1505 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1506 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1507 assert(label_nulls <= 1, "at most one null in the batch");
1508
1509 // a couple of useful fields in sub_klass:
1510 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1511 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1512 Address secondary_supers_addr(sub_klass, ss_offset);
1513 Address super_cache_addr( sub_klass, sc_offset);
1514
1515 BLOCK_COMMENT("check_klass_subtype_slow_path");
1516
1517 // Do a linear scan of the secondary super-klass chain.
1518 // This code is rarely used, so simplicity is a virtue here.
1519 // The repne_scan instruction uses fixed registers, which we must spill.
1520 // Don't worry too much about pre-existing connections with the input regs.
1521
1522 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1523 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1524
1525 RegSet pushed_registers;
1526 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1527 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1528
1529 if (super_klass != r0) {
1530 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1531 }
1532
1533 push(pushed_registers, sp);
1534
1535 // Get super_klass value into r0 (even if it was in r5 or r2).
1536 if (super_klass != r0) {
1537 mov(r0, super_klass);
1538 }
1539
1540 #ifndef PRODUCT
1541 incrementw(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
1542 #endif //PRODUCT
1543
1544 // We will consult the secondary-super array.
1545 ldr(r5, secondary_supers_addr);
1546 // Load the array length.
1547 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1548 // Skip to start of data.
1549 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1550
1551 cmp(sp, zr); // Clear Z flag; SP is never zero
1552 // Scan R2 words at [R5] for an occurrence of R0.
1553 // Set NZ/Z based on last compare.
1554 repne_scan(r5, r0, r2, rscratch1);
1555
1556 // Unspill the temp. registers:
1557 pop(pushed_registers, sp);
1558
1559 br(Assembler::NE, *L_failure);
1560
1561 // Success. Cache the super we found and proceed in triumph.
1562
1563 if (UseSecondarySupersCache) {
1564 str(super_klass, super_cache_addr);
1565 }
1566
1567 if (L_success != &L_fallthrough) {
1568 b(*L_success);
1569 }
1570
1571 #undef IS_A_TEMP
1572
1573 bind(L_fallthrough);
1574 }
1575
1576 // If Register r is invalid, remove a new register from
1577 // available_regs, and add new register to regs_to_push.
1578 Register MacroAssembler::allocate_if_noreg(Register r,
1579 RegSetIterator<Register> &available_regs,
1580 RegSet ®s_to_push) {
1581 if (!r->is_valid()) {
1582 r = *available_regs++;
1583 regs_to_push += r;
1584 }
1585 return r;
1586 }
1587
1588 // check_klass_subtype_slow_path_table() looks for super_klass in the
1589 // hash table belonging to super_klass, branching to L_success or
1590 // L_failure as appropriate. This is essentially a shim which
1591 // allocates registers as necessary then calls
1592 // lookup_secondary_supers_table() to do the work. Any of the temp
1593 // regs may be noreg, in which case this logic will chooses some
1594 // registers push and pop them from the stack.
1595 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
1596 Register super_klass,
1597 Register temp_reg,
1598 Register temp2_reg,
1599 Register temp3_reg,
1600 Register result_reg,
1601 FloatRegister vtemp,
1602 Label* L_success,
1603 Label* L_failure,
1604 bool set_cond_codes) {
1605 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
1606
1607 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1608
1609 Label L_fallthrough;
1610 int label_nulls = 0;
1611 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1612 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1613 assert(label_nulls <= 1, "at most one null in the batch");
1614
1615 BLOCK_COMMENT("check_klass_subtype_slow_path");
1616
1617 RegSetIterator<Register> available_regs
1618 = (RegSet::range(r0, r15) - temps - sub_klass - super_klass).begin();
1619
1620 RegSet pushed_regs;
1621
1622 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
1623 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
1624 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
1625 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
1626
1627 push(pushed_regs, sp);
1628
1629 lookup_secondary_supers_table_var(sub_klass,
1630 super_klass,
1631 temp_reg, temp2_reg, temp3_reg, vtemp, result_reg,
1632 nullptr);
1633 cmp(result_reg, zr);
1634
1635 // Unspill the temp. registers:
1636 pop(pushed_regs, sp);
1637
1638 // NB! Callers may assume that, when set_cond_codes is true, this
1639 // code sets temp2_reg to a nonzero value.
1640 if (set_cond_codes) {
1641 mov(temp2_reg, 1);
1642 }
1643
1644 br(Assembler::NE, *L_failure);
1645
1646 if (L_success != &L_fallthrough) {
1647 b(*L_success);
1648 }
1649
1650 bind(L_fallthrough);
1651 }
1652
1653 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1654 Register super_klass,
1655 Register temp_reg,
1656 Register temp2_reg,
1657 Label* L_success,
1658 Label* L_failure,
1659 bool set_cond_codes) {
1660 if (UseSecondarySupersTable) {
1661 check_klass_subtype_slow_path_table
1662 (sub_klass, super_klass, temp_reg, temp2_reg, /*temp3*/noreg, /*result*/noreg,
1663 /*vtemp*/fnoreg,
1664 L_success, L_failure, set_cond_codes);
1665 } else {
1666 check_klass_subtype_slow_path_linear
1667 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
1668 }
1669 }
1670
1671
1672 // Ensure that the inline code and the stub are using the same registers.
1673 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
1674 do { \
1675 assert(r_super_klass == r0 && \
1676 r_array_base == r1 && \
1677 r_array_length == r2 && \
1678 (r_array_index == r3 || r_array_index == noreg) && \
1679 (r_sub_klass == r4 || r_sub_klass == noreg) && \
1680 (r_bitmap == rscratch2 || r_bitmap == noreg) && \
1681 (result == r5 || result == noreg), "registers must match aarch64.ad"); \
1682 } while(0)
1683
1684 bool MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
1685 Register r_super_klass,
1686 Register temp1,
1687 Register temp2,
1688 Register temp3,
1689 FloatRegister vtemp,
1690 Register result,
1691 u1 super_klass_slot,
1692 bool stub_is_near) {
1693 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1694
1695 Label L_fallthrough;
1696
1697 BLOCK_COMMENT("lookup_secondary_supers_table {");
1698
1699 const Register
1700 r_array_base = temp1, // r1
1701 r_array_length = temp2, // r2
1702 r_array_index = temp3, // r3
1703 r_bitmap = rscratch2;
1704
1705 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1706
1707 u1 bit = super_klass_slot;
1708
1709 // Make sure that result is nonzero if the TBZ below misses.
1710 mov(result, 1);
1711
1712 // We're going to need the bitmap in a vector reg and in a core reg,
1713 // so load both now.
1714 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1715 if (bit != 0) {
1716 ldrd(vtemp, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1717 }
1718 // First check the bitmap to see if super_klass might be present. If
1719 // the bit is zero, we are certain that super_klass is not one of
1720 // the secondary supers.
1721 tbz(r_bitmap, bit, L_fallthrough);
1722
1723 // Get the first array index that can contain super_klass into r_array_index.
1724 if (bit != 0) {
1725 shld(vtemp, vtemp, Klass::SECONDARY_SUPERS_TABLE_MASK - bit);
1726 cnt(vtemp, T8B, vtemp);
1727 addv(vtemp, T8B, vtemp);
1728 fmovd(r_array_index, vtemp);
1729 } else {
1730 mov(r_array_index, (u1)1);
1731 }
1732 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1733
1734 // We will consult the secondary-super array.
1735 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1736
1737 // The value i in r_array_index is >= 1, so even though r_array_base
1738 // points to the length, we don't need to adjust it to point to the
1739 // data.
1740 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1741 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1742
1743 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1744 eor(result, result, r_super_klass);
1745 cbz(result, L_fallthrough); // Found a match
1746
1747 // Is there another entry to check? Consult the bitmap.
1748 tbz(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK, L_fallthrough);
1749
1750 // Linear probe.
1751 if (bit != 0) {
1752 ror(r_bitmap, r_bitmap, bit);
1753 }
1754
1755 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1756 // The next slot to be inspected, by the stub we're about to call,
1757 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1758 // have been checked.
1759 Address stub = RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub());
1760 if (stub_is_near) {
1761 bl(stub);
1762 } else {
1763 address call = trampoline_call(stub);
1764 if (call == nullptr) {
1765 return false; // trampoline allocation failed
1766 }
1767 }
1768
1769 BLOCK_COMMENT("} lookup_secondary_supers_table");
1770
1771 bind(L_fallthrough);
1772
1773 if (VerifySecondarySupers) {
1774 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1775 temp1, temp2, result); // r1, r2, r5
1776 }
1777 return true;
1778 }
1779
1780 // At runtime, return 0 in result if r_super_klass is a superclass of
1781 // r_sub_klass, otherwise return nonzero. Use this version of
1782 // lookup_secondary_supers_table() if you don't know ahead of time
1783 // which superclass will be searched for. Used by interpreter and
1784 // runtime stubs. It is larger and has somewhat greater latency than
1785 // the version above, which takes a constant super_klass_slot.
1786 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
1787 Register r_super_klass,
1788 Register temp1,
1789 Register temp2,
1790 Register temp3,
1791 FloatRegister vtemp,
1792 Register result,
1793 Label *L_success) {
1794 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1795
1796 Label L_fallthrough;
1797
1798 BLOCK_COMMENT("lookup_secondary_supers_table {");
1799
1800 const Register
1801 r_array_index = temp3,
1802 slot = rscratch1,
1803 r_bitmap = rscratch2;
1804
1805 ldrb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
1806
1807 // Make sure that result is nonzero if the test below misses.
1808 mov(result, 1);
1809
1810 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1811
1812 // First check the bitmap to see if super_klass might be present. If
1813 // the bit is zero, we are certain that super_klass is not one of
1814 // the secondary supers.
1815
1816 // This next instruction is equivalent to:
1817 // mov(tmp_reg, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1818 // sub(temp2, tmp_reg, slot);
1819 eor(temp2, slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1820 lslv(temp2, r_bitmap, temp2);
1821 tbz(temp2, Klass::SECONDARY_SUPERS_TABLE_SIZE - 1, L_fallthrough);
1822
1823 bool must_save_v0 = (vtemp == fnoreg);
1824 if (must_save_v0) {
1825 // temp1 and result are free, so use them to preserve vtemp
1826 vtemp = v0;
1827 mov(temp1, vtemp, D, 0);
1828 mov(result, vtemp, D, 1);
1829 }
1830
1831 // Get the first array index that can contain super_klass into r_array_index.
1832 mov(vtemp, D, 0, temp2);
1833 cnt(vtemp, T8B, vtemp);
1834 addv(vtemp, T8B, vtemp);
1835 mov(r_array_index, vtemp, D, 0);
1836
1837 if (must_save_v0) {
1838 mov(vtemp, D, 0, temp1 );
1839 mov(vtemp, D, 1, result);
1840 }
1841
1842 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1843
1844 const Register
1845 r_array_base = temp1,
1846 r_array_length = temp2;
1847
1848 // The value i in r_array_index is >= 1, so even though r_array_base
1849 // points to the length, we don't need to adjust it to point to the
1850 // data.
1851 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1852 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1853
1854 // We will consult the secondary-super array.
1855 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1856
1857 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1858 eor(result, result, r_super_klass);
1859 cbz(result, L_success ? *L_success : L_fallthrough); // Found a match
1860
1861 // Is there another entry to check? Consult the bitmap.
1862 rorv(r_bitmap, r_bitmap, slot);
1863 // rol(r_bitmap, r_bitmap, 1);
1864 tbz(r_bitmap, 1, L_fallthrough);
1865
1866 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1867 // The next slot to be inspected, by the logic we're about to call,
1868 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1869 // have been checked.
1870 lookup_secondary_supers_table_slow_path(r_super_klass, r_array_base, r_array_index,
1871 r_bitmap, r_array_length, result, /*is_stub*/false);
1872
1873 BLOCK_COMMENT("} lookup_secondary_supers_table");
1874
1875 bind(L_fallthrough);
1876
1877 if (VerifySecondarySupers) {
1878 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1879 temp1, temp2, result); // r1, r2, r5
1880 }
1881
1882 if (L_success) {
1883 cbz(result, *L_success);
1884 }
1885 }
1886
1887 // Called by code generated by check_klass_subtype_slow_path
1888 // above. This is called when there is a collision in the hashed
1889 // lookup in the secondary supers array.
1890 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
1891 Register r_array_base,
1892 Register r_array_index,
1893 Register r_bitmap,
1894 Register temp1,
1895 Register result,
1896 bool is_stub) {
1897 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, result, rscratch1);
1898
1899 const Register
1900 r_array_length = temp1,
1901 r_sub_klass = noreg; // unused
1902
1903 if (is_stub) {
1904 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1905 }
1906
1907 Label L_fallthrough, L_huge;
1908
1909 // Load the array length.
1910 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1911 // And adjust the array base to point to the data.
1912 // NB! Effectively increments current slot index by 1.
1913 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
1914 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1915
1916 // The bitmap is full to bursting.
1917 // Implicit invariant: BITMAP_FULL implies (length > 0)
1918 assert(Klass::SECONDARY_SUPERS_BITMAP_FULL == ~uintx(0), "");
1919 cmpw(r_array_length, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 2));
1920 br(GT, L_huge);
1921
1922 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
1923 // current slot (at secondary_supers[r_array_index]) has not yet
1924 // been inspected, and r_array_index may be out of bounds if we
1925 // wrapped around the end of the array.
1926
1927 { // This is conventional linear probing, but instead of terminating
1928 // when a null entry is found in the table, we maintain a bitmap
1929 // in which a 0 indicates missing entries.
1930 // As long as the bitmap is not completely full,
1931 // array_length == popcount(bitmap). The array_length check above
1932 // guarantees there are 0s in the bitmap, so the loop eventually
1933 // terminates.
1934 Label L_loop;
1935 bind(L_loop);
1936
1937 // Check for wraparound.
1938 cmp(r_array_index, r_array_length);
1939 csel(r_array_index, zr, r_array_index, GE);
1940
1941 ldr(rscratch1, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1942 eor(result, rscratch1, r_super_klass);
1943 cbz(result, L_fallthrough);
1944
1945 tbz(r_bitmap, 2, L_fallthrough); // look-ahead check (Bit 2); result is non-zero
1946
1947 ror(r_bitmap, r_bitmap, 1);
1948 add(r_array_index, r_array_index, 1);
1949 b(L_loop);
1950 }
1951
1952 { // Degenerate case: more than 64 secondary supers.
1953 // FIXME: We could do something smarter here, maybe a vectorized
1954 // comparison or a binary search, but is that worth any added
1955 // complexity?
1956 bind(L_huge);
1957 cmp(sp, zr); // Clear Z flag; SP is never zero
1958 repne_scan(r_array_base, r_super_klass, r_array_length, rscratch1);
1959 cset(result, NE); // result == 0 iff we got a match.
1960 }
1961
1962 bind(L_fallthrough);
1963 }
1964
1965 // Make sure that the hashed lookup and a linear scan agree.
1966 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
1967 Register r_super_klass,
1968 Register temp1,
1969 Register temp2,
1970 Register result) {
1971 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, result, rscratch1);
1972
1973 const Register
1974 r_array_base = temp1,
1975 r_array_length = temp2,
1976 r_array_index = noreg, // unused
1977 r_bitmap = noreg; // unused
1978
1979 BLOCK_COMMENT("verify_secondary_supers_table {");
1980
1981 // We will consult the secondary-super array.
1982 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1983
1984 // Load the array length.
1985 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1986 // And adjust the array base to point to the data.
1987 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1988
1989 cmp(sp, zr); // Clear Z flag; SP is never zero
1990 // Scan R2 words at [R5] for an occurrence of R0.
1991 // Set NZ/Z based on last compare.
1992 repne_scan(/*addr*/r_array_base, /*value*/r_super_klass, /*count*/r_array_length, rscratch2);
1993 // rscratch1 == 0 iff we got a match.
1994 cset(rscratch1, NE);
1995
1996 Label passed;
1997 cmp(result, zr);
1998 cset(result, NE); // normalize result to 0/1 for comparison
1999
2000 cmp(rscratch1, result);
2001 br(EQ, passed);
2002 {
2003 mov(r0, r_super_klass); // r0 <- r0
2004 mov(r1, r_sub_klass); // r1 <- r4
2005 mov(r2, /*expected*/rscratch1); // r2 <- r8
2006 mov(r3, result); // r3 <- r5
2007 mov(r4, (address)("mismatch")); // r4 <- const
2008 rt_call(CAST_FROM_FN_PTR(address, Klass::on_secondary_supers_verification_failure), rscratch2);
2009 should_not_reach_here();
2010 }
2011 bind(passed);
2012
2013 BLOCK_COMMENT("} verify_secondary_supers_table");
2014 }
2015
2016 void MacroAssembler::clinit_barrier(Register klass, Register scratch, Label* L_fast_path, Label* L_slow_path) {
2017 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
2018 assert_different_registers(klass, rthread, scratch);
2019
2020 Label L_fallthrough, L_tmp;
2021 if (L_fast_path == nullptr) {
2022 L_fast_path = &L_fallthrough;
2023 } else if (L_slow_path == nullptr) {
2024 L_slow_path = &L_fallthrough;
2025 }
2026 // Fast path check: class is fully initialized
2027 lea(scratch, Address(klass, InstanceKlass::init_state_offset()));
2028 ldarb(scratch, scratch);
2029 cmp(scratch, InstanceKlass::fully_initialized);
2030 br(Assembler::EQ, *L_fast_path);
2031
2032 // Fast path check: current thread is initializer thread
2033 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
2034 cmp(rthread, scratch);
2035
2036 if (L_slow_path == &L_fallthrough) {
2037 br(Assembler::EQ, *L_fast_path);
2038 bind(*L_slow_path);
2039 } else if (L_fast_path == &L_fallthrough) {
2040 br(Assembler::NE, *L_slow_path);
2041 bind(*L_fast_path);
2042 } else {
2043 Unimplemented();
2044 }
2045 }
2046
2047 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
2048 if (!VerifyOops) return;
2049
2050 // Pass register number to verify_oop_subroutine
2051 const char* b = nullptr;
2052 {
2053 ResourceMark rm;
2054 stringStream ss;
2055 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
2056 b = code_string(ss.as_string());
2057 }
2058 BLOCK_COMMENT("verify_oop {");
2059
2060 strip_return_address(); // This might happen within a stack frame.
2061 protect_return_address();
2062 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2063 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2064
2065 mov(r0, reg);
2066 movptr(rscratch1, (uintptr_t)(address)b);
2067
2068 // call indirectly to solve generation ordering problem
2069 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2070 ldr(rscratch2, Address(rscratch2));
2071 blr(rscratch2);
2072
2073 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2074 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2075 authenticate_return_address();
2076
2077 BLOCK_COMMENT("} verify_oop");
2078 }
2079
2080 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
2081 if (!VerifyOops) return;
2082
2083 const char* b = nullptr;
2084 {
2085 ResourceMark rm;
2086 stringStream ss;
2087 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
2088 b = code_string(ss.as_string());
2089 }
2090 BLOCK_COMMENT("verify_oop_addr {");
2091
2092 strip_return_address(); // This might happen within a stack frame.
2093 protect_return_address();
2094 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2095 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2096
2097 // addr may contain sp so we will have to adjust it based on the
2098 // pushes that we just did.
2099 if (addr.uses(sp)) {
2100 lea(r0, addr);
2101 ldr(r0, Address(r0, 4 * wordSize));
2102 } else {
2103 ldr(r0, addr);
2104 }
2105 movptr(rscratch1, (uintptr_t)(address)b);
2106
2107 // call indirectly to solve generation ordering problem
2108 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2109 ldr(rscratch2, Address(rscratch2));
2110 blr(rscratch2);
2111
2112 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2113 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2114 authenticate_return_address();
2115
2116 BLOCK_COMMENT("} verify_oop_addr");
2117 }
2118
2119 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
2120 int extra_slot_offset) {
2121 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
2122 int stackElementSize = Interpreter::stackElementSize;
2123 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
2124 #ifdef ASSERT
2125 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
2126 assert(offset1 - offset == stackElementSize, "correct arithmetic");
2127 #endif
2128 if (arg_slot.is_constant()) {
2129 return Address(esp, arg_slot.as_constant() * stackElementSize
2130 + offset);
2131 } else {
2132 add(rscratch1, esp, arg_slot.as_register(),
2133 ext::uxtx, exact_log2(stackElementSize));
2134 return Address(rscratch1, offset);
2135 }
2136 }
2137
2138 void MacroAssembler::call_VM_leaf_base(address entry_point,
2139 int number_of_arguments,
2140 Label *retaddr) {
2141 Label E, L;
2142
2143 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
2144
2145 mov(rscratch1, RuntimeAddress(entry_point));
2146 blr(rscratch1);
2147 if (retaddr)
2148 bind(*retaddr);
2149
2150 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
2151 }
2152
2153 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2154 call_VM_leaf_base(entry_point, number_of_arguments);
2155 }
2156
2157 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2158 pass_arg0(this, arg_0);
2159 call_VM_leaf_base(entry_point, 1);
2160 }
2161
2162 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2163 assert_different_registers(arg_1, c_rarg0);
2164 pass_arg0(this, arg_0);
2165 pass_arg1(this, arg_1);
2166 call_VM_leaf_base(entry_point, 2);
2167 }
2168
2169 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
2170 Register arg_1, Register arg_2) {
2171 assert_different_registers(arg_1, c_rarg0);
2172 assert_different_registers(arg_2, c_rarg0, c_rarg1);
2173 pass_arg0(this, arg_0);
2174 pass_arg1(this, arg_1);
2175 pass_arg2(this, arg_2);
2176 call_VM_leaf_base(entry_point, 3);
2177 }
2178
2179 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2180 pass_arg0(this, arg_0);
2181 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2182 }
2183
2184 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2185
2186 assert_different_registers(arg_0, c_rarg1);
2187 pass_arg1(this, arg_1);
2188 pass_arg0(this, arg_0);
2189 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2190 }
2191
2192 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2193 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2194 assert_different_registers(arg_1, c_rarg2);
2195 pass_arg2(this, arg_2);
2196 pass_arg1(this, arg_1);
2197 pass_arg0(this, arg_0);
2198 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2199 }
2200
2201 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2202 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
2203 assert_different_registers(arg_1, c_rarg2, c_rarg3);
2204 assert_different_registers(arg_2, c_rarg3);
2205 pass_arg3(this, arg_3);
2206 pass_arg2(this, arg_2);
2207 pass_arg1(this, arg_1);
2208 pass_arg0(this, arg_0);
2209 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2210 }
2211
2212 void MacroAssembler::null_check(Register reg, int offset) {
2213 if (needs_explicit_null_check(offset)) {
2214 // provoke OS null exception if reg is null by
2215 // accessing M[reg] w/o changing any registers
2216 // NOTE: this is plenty to provoke a segv
2217 ldr(zr, Address(reg));
2218 } else {
2219 // nothing to do, (later) access of M[reg + offset]
2220 // will provoke OS null exception if reg is null
2221 }
2222 }
2223
2224 // MacroAssembler protected routines needed to implement
2225 // public methods
2226
2227 void MacroAssembler::mov(Register r, Address dest) {
2228 code_section()->relocate(pc(), dest.rspec());
2229 uint64_t imm64 = (uint64_t)dest.target();
2230 movptr(r, imm64);
2231 }
2232
2233 // Move a constant pointer into r. In AArch64 mode the virtual
2234 // address space is 48 bits in size, so we only need three
2235 // instructions to create a patchable instruction sequence that can
2236 // reach anywhere.
2237 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2238 #ifndef PRODUCT
2239 {
2240 char buffer[64];
2241 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2242 block_comment(buffer);
2243 }
2244 #endif
2245 assert(imm64 < (1ull << 48), "48-bit overflow in address constant");
2246 movz(r, imm64 & 0xffff);
2247 imm64 >>= 16;
2248 movk(r, imm64 & 0xffff, 16);
2249 imm64 >>= 16;
2250 movk(r, imm64 & 0xffff, 32);
2251 }
2252
2253 // Macro to mov replicated immediate to vector register.
2254 // imm64: only the lower 8/16/32 bits are considered for B/H/S type. That is,
2255 // the upper 56/48/32 bits must be zeros for B/H/S type.
2256 // Vd will get the following values for different arrangements in T
2257 // imm64 == hex 000000gh T8B: Vd = ghghghghghghghgh
2258 // imm64 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
2259 // imm64 == hex 0000efgh T4H: Vd = efghefghefghefgh
2260 // imm64 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
2261 // imm64 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
2262 // imm64 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
2263 // imm64 == hex abcdefgh T1D: Vd = 00000000abcdefgh
2264 // imm64 == hex abcdefgh T2D: Vd = 00000000abcdefgh00000000abcdefgh
2265 // Clobbers rscratch1
2266 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64) {
2267 assert(T != T1Q, "unsupported");
2268 if (T == T1D || T == T2D) {
2269 int imm = operand_valid_for_movi_immediate(imm64, T);
2270 if (-1 != imm) {
2271 movi(Vd, T, imm);
2272 } else {
2273 mov(rscratch1, imm64);
2274 dup(Vd, T, rscratch1);
2275 }
2276 return;
2277 }
2278
2279 #ifdef ASSERT
2280 if (T == T8B || T == T16B) assert((imm64 & ~0xff) == 0, "extraneous bits (T8B/T16B)");
2281 if (T == T4H || T == T8H) assert((imm64 & ~0xffff) == 0, "extraneous bits (T4H/T8H)");
2282 if (T == T2S || T == T4S) assert((imm64 & ~0xffffffff) == 0, "extraneous bits (T2S/T4S)");
2283 #endif
2284 int shift = operand_valid_for_movi_immediate(imm64, T);
2285 uint32_t imm32 = imm64 & 0xffffffffULL;
2286 if (shift >= 0) {
2287 movi(Vd, T, (imm32 >> shift) & 0xff, shift);
2288 } else {
2289 movw(rscratch1, imm32);
2290 dup(Vd, T, rscratch1);
2291 }
2292 }
2293
2294 void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64)
2295 {
2296 #ifndef PRODUCT
2297 {
2298 char buffer[64];
2299 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, imm64);
2300 block_comment(buffer);
2301 }
2302 #endif
2303 if (operand_valid_for_logical_immediate(false, imm64)) {
2304 orr(dst, zr, imm64);
2305 } else {
2306 // we can use a combination of MOVZ or MOVN with
2307 // MOVK to build up the constant
2308 uint64_t imm_h[4];
2309 int zero_count = 0;
2310 int neg_count = 0;
2311 int i;
2312 for (i = 0; i < 4; i++) {
2313 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
2314 if (imm_h[i] == 0) {
2315 zero_count++;
2316 } else if (imm_h[i] == 0xffffL) {
2317 neg_count++;
2318 }
2319 }
2320 if (zero_count == 4) {
2321 // one MOVZ will do
2322 movz(dst, 0);
2323 } else if (neg_count == 4) {
2324 // one MOVN will do
2325 movn(dst, 0);
2326 } else if (zero_count == 3) {
2327 for (i = 0; i < 4; i++) {
2328 if (imm_h[i] != 0L) {
2329 movz(dst, (uint32_t)imm_h[i], (i << 4));
2330 break;
2331 }
2332 }
2333 } else if (neg_count == 3) {
2334 // one MOVN will do
2335 for (int i = 0; i < 4; i++) {
2336 if (imm_h[i] != 0xffffL) {
2337 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2338 break;
2339 }
2340 }
2341 } else if (zero_count == 2) {
2342 // one MOVZ and one MOVK will do
2343 for (i = 0; i < 3; i++) {
2344 if (imm_h[i] != 0L) {
2345 movz(dst, (uint32_t)imm_h[i], (i << 4));
2346 i++;
2347 break;
2348 }
2349 }
2350 for (;i < 4; i++) {
2351 if (imm_h[i] != 0L) {
2352 movk(dst, (uint32_t)imm_h[i], (i << 4));
2353 }
2354 }
2355 } else if (neg_count == 2) {
2356 // one MOVN and one MOVK will do
2357 for (i = 0; i < 4; i++) {
2358 if (imm_h[i] != 0xffffL) {
2359 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2360 i++;
2361 break;
2362 }
2363 }
2364 for (;i < 4; i++) {
2365 if (imm_h[i] != 0xffffL) {
2366 movk(dst, (uint32_t)imm_h[i], (i << 4));
2367 }
2368 }
2369 } else if (zero_count == 1) {
2370 // one MOVZ and two MOVKs will do
2371 for (i = 0; i < 4; i++) {
2372 if (imm_h[i] != 0L) {
2373 movz(dst, (uint32_t)imm_h[i], (i << 4));
2374 i++;
2375 break;
2376 }
2377 }
2378 for (;i < 4; i++) {
2379 if (imm_h[i] != 0x0L) {
2380 movk(dst, (uint32_t)imm_h[i], (i << 4));
2381 }
2382 }
2383 } else if (neg_count == 1) {
2384 // one MOVN and two MOVKs will do
2385 for (i = 0; i < 4; i++) {
2386 if (imm_h[i] != 0xffffL) {
2387 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2388 i++;
2389 break;
2390 }
2391 }
2392 for (;i < 4; i++) {
2393 if (imm_h[i] != 0xffffL) {
2394 movk(dst, (uint32_t)imm_h[i], (i << 4));
2395 }
2396 }
2397 } else {
2398 // use a MOVZ and 3 MOVKs (makes it easier to debug)
2399 movz(dst, (uint32_t)imm_h[0], 0);
2400 for (i = 1; i < 4; i++) {
2401 movk(dst, (uint32_t)imm_h[i], (i << 4));
2402 }
2403 }
2404 }
2405 }
2406
2407 void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32)
2408 {
2409 #ifndef PRODUCT
2410 {
2411 char buffer[64];
2412 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX32, imm32);
2413 block_comment(buffer);
2414 }
2415 #endif
2416 if (operand_valid_for_logical_immediate(true, imm32)) {
2417 orrw(dst, zr, imm32);
2418 } else {
2419 // we can use MOVZ, MOVN or two calls to MOVK to build up the
2420 // constant
2421 uint32_t imm_h[2];
2422 imm_h[0] = imm32 & 0xffff;
2423 imm_h[1] = ((imm32 >> 16) & 0xffff);
2424 if (imm_h[0] == 0) {
2425 movzw(dst, imm_h[1], 16);
2426 } else if (imm_h[0] == 0xffff) {
2427 movnw(dst, imm_h[1] ^ 0xffff, 16);
2428 } else if (imm_h[1] == 0) {
2429 movzw(dst, imm_h[0], 0);
2430 } else if (imm_h[1] == 0xffff) {
2431 movnw(dst, imm_h[0] ^ 0xffff, 0);
2432 } else {
2433 // use a MOVZ and MOVK (makes it easier to debug)
2434 movzw(dst, imm_h[0], 0);
2435 movkw(dst, imm_h[1], 16);
2436 }
2437 }
2438 }
2439
2440 // Form an address from base + offset in Rd. Rd may or may
2441 // not actually be used: you must use the Address that is returned.
2442 // It is up to you to ensure that the shift provided matches the size
2443 // of your data.
2444 Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) {
2445 if (Address::offset_ok_for_immed(byte_offset, shift))
2446 // It fits; no need for any heroics
2447 return Address(base, byte_offset);
2448
2449 // Don't do anything clever with negative or misaligned offsets
2450 unsigned mask = (1 << shift) - 1;
2451 if (byte_offset < 0 || byte_offset & mask) {
2452 mov(Rd, byte_offset);
2453 add(Rd, base, Rd);
2454 return Address(Rd);
2455 }
2456
2457 // See if we can do this with two 12-bit offsets
2458 {
2459 uint64_t word_offset = byte_offset >> shift;
2460 uint64_t masked_offset = word_offset & 0xfff000;
2461 if (Address::offset_ok_for_immed(word_offset - masked_offset, 0)
2462 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
2463 add(Rd, base, masked_offset << shift);
2464 word_offset -= masked_offset;
2465 return Address(Rd, word_offset << shift);
2466 }
2467 }
2468
2469 // Do it the hard way
2470 mov(Rd, byte_offset);
2471 add(Rd, base, Rd);
2472 return Address(Rd);
2473 }
2474
2475 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
2476 bool want_remainder, Register scratch)
2477 {
2478 // Full implementation of Java idiv and irem. The function
2479 // returns the (pc) offset of the div instruction - may be needed
2480 // for implicit exceptions.
2481 //
2482 // constraint : ra/rb =/= scratch
2483 // normal case
2484 //
2485 // input : ra: dividend
2486 // rb: divisor
2487 //
2488 // result: either
2489 // quotient (= ra idiv rb)
2490 // remainder (= ra irem rb)
2491
2492 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2493
2494 int idivl_offset = offset();
2495 if (! want_remainder) {
2496 sdivw(result, ra, rb);
2497 } else {
2498 sdivw(scratch, ra, rb);
2499 Assembler::msubw(result, scratch, rb, ra);
2500 }
2501
2502 return idivl_offset;
2503 }
2504
2505 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
2506 bool want_remainder, Register scratch)
2507 {
2508 // Full implementation of Java ldiv and lrem. The function
2509 // returns the (pc) offset of the div instruction - may be needed
2510 // for implicit exceptions.
2511 //
2512 // constraint : ra/rb =/= scratch
2513 // normal case
2514 //
2515 // input : ra: dividend
2516 // rb: divisor
2517 //
2518 // result: either
2519 // quotient (= ra idiv rb)
2520 // remainder (= ra irem rb)
2521
2522 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2523
2524 int idivq_offset = offset();
2525 if (! want_remainder) {
2526 sdiv(result, ra, rb);
2527 } else {
2528 sdiv(scratch, ra, rb);
2529 Assembler::msub(result, scratch, rb, ra);
2530 }
2531
2532 return idivq_offset;
2533 }
2534
2535 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
2536 address prev = pc() - NativeMembar::instruction_size;
2537 address last = code()->last_insn();
2538 if (last != nullptr && nativeInstruction_at(last)->is_Membar() && prev == last) {
2539 NativeMembar *bar = NativeMembar_at(prev);
2540 if (AlwaysMergeDMB) {
2541 bar->set_kind(bar->get_kind() | order_constraint);
2542 BLOCK_COMMENT("merged membar(always)");
2543 return;
2544 }
2545 // Don't promote DMB ST|DMB LD to DMB (a full barrier) because
2546 // doing so would introduce a StoreLoad which the caller did not
2547 // intend
2548 if (bar->get_kind() == order_constraint
2549 || bar->get_kind() == AnyAny
2550 || order_constraint == AnyAny) {
2551 // We are merging two memory barrier instructions. On AArch64 we
2552 // can do this simply by ORing them together.
2553 bar->set_kind(bar->get_kind() | order_constraint);
2554 BLOCK_COMMENT("merged membar");
2555 return;
2556 } else {
2557 // A special case like "DMB ST;DMB LD;DMB ST", the last DMB can be skipped
2558 // We need check the last 2 instructions
2559 address prev2 = prev - NativeMembar::instruction_size;
2560 if (last != code()->last_label() && nativeInstruction_at(prev2)->is_Membar()) {
2561 NativeMembar *bar2 = NativeMembar_at(prev2);
2562 assert(bar2->get_kind() == order_constraint, "it should be merged before");
2563 BLOCK_COMMENT("merged membar(elided)");
2564 return;
2565 }
2566 }
2567 }
2568 code()->set_last_insn(pc());
2569 dmb(Assembler::barrier(order_constraint));
2570 }
2571
2572 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) {
2573 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) {
2574 merge_ldst(rt, adr, size_in_bytes, is_store);
2575 code()->clear_last_insn();
2576 return true;
2577 } else {
2578 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported.");
2579 const uint64_t mask = size_in_bytes - 1;
2580 if (adr.getMode() == Address::base_plus_offset &&
2581 (adr.offset() & mask) == 0) { // only supports base_plus_offset.
2582 code()->set_last_insn(pc());
2583 }
2584 return false;
2585 }
2586 }
2587
2588 void MacroAssembler::ldr(Register Rx, const Address &adr) {
2589 // We always try to merge two adjacent loads into one ldp.
2590 if (!try_merge_ldst(Rx, adr, 8, false)) {
2591 Assembler::ldr(Rx, adr);
2592 }
2593 }
2594
2595 void MacroAssembler::ldrw(Register Rw, const Address &adr) {
2596 // We always try to merge two adjacent loads into one ldp.
2597 if (!try_merge_ldst(Rw, adr, 4, false)) {
2598 Assembler::ldrw(Rw, adr);
2599 }
2600 }
2601
2602 void MacroAssembler::str(Register Rx, const Address &adr) {
2603 // We always try to merge two adjacent stores into one stp.
2604 if (!try_merge_ldst(Rx, adr, 8, true)) {
2605 Assembler::str(Rx, adr);
2606 }
2607 }
2608
2609 void MacroAssembler::strw(Register Rw, const Address &adr) {
2610 // We always try to merge two adjacent stores into one stp.
2611 if (!try_merge_ldst(Rw, adr, 4, true)) {
2612 Assembler::strw(Rw, adr);
2613 }
2614 }
2615
2616 // MacroAssembler routines found actually to be needed
2617
2618 void MacroAssembler::push(Register src)
2619 {
2620 str(src, Address(pre(esp, -1 * wordSize)));
2621 }
2622
2623 void MacroAssembler::pop(Register dst)
2624 {
2625 ldr(dst, Address(post(esp, 1 * wordSize)));
2626 }
2627
2628 // Note: load_unsigned_short used to be called load_unsigned_word.
2629 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2630 int off = offset();
2631 ldrh(dst, src);
2632 return off;
2633 }
2634
2635 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2636 int off = offset();
2637 ldrb(dst, src);
2638 return off;
2639 }
2640
2641 int MacroAssembler::load_signed_short(Register dst, Address src) {
2642 int off = offset();
2643 ldrsh(dst, src);
2644 return off;
2645 }
2646
2647 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2648 int off = offset();
2649 ldrsb(dst, src);
2650 return off;
2651 }
2652
2653 int MacroAssembler::load_signed_short32(Register dst, Address src) {
2654 int off = offset();
2655 ldrshw(dst, src);
2656 return off;
2657 }
2658
2659 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
2660 int off = offset();
2661 ldrsbw(dst, src);
2662 return off;
2663 }
2664
2665 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) {
2666 switch (size_in_bytes) {
2667 case 8: ldr(dst, src); break;
2668 case 4: ldrw(dst, src); break;
2669 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2670 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2671 default: ShouldNotReachHere();
2672 }
2673 }
2674
2675 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes) {
2676 switch (size_in_bytes) {
2677 case 8: str(src, dst); break;
2678 case 4: strw(src, dst); break;
2679 case 2: strh(src, dst); break;
2680 case 1: strb(src, dst); break;
2681 default: ShouldNotReachHere();
2682 }
2683 }
2684
2685 void MacroAssembler::decrementw(Register reg, int value)
2686 {
2687 if (value < 0) { incrementw(reg, -value); return; }
2688 if (value == 0) { return; }
2689 if (value < (1 << 12)) { subw(reg, reg, value); return; }
2690 /* else */ {
2691 guarantee(reg != rscratch2, "invalid dst for register decrement");
2692 movw(rscratch2, (unsigned)value);
2693 subw(reg, reg, rscratch2);
2694 }
2695 }
2696
2697 void MacroAssembler::decrement(Register reg, int value)
2698 {
2699 if (value < 0) { increment(reg, -value); return; }
2700 if (value == 0) { return; }
2701 if (value < (1 << 12)) { sub(reg, reg, value); return; }
2702 /* else */ {
2703 assert(reg != rscratch2, "invalid dst for register decrement");
2704 mov(rscratch2, (uint64_t)value);
2705 sub(reg, reg, rscratch2);
2706 }
2707 }
2708
2709 void MacroAssembler::decrementw(Address dst, int value)
2710 {
2711 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
2712 if (dst.getMode() == Address::literal) {
2713 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2714 lea(rscratch2, dst);
2715 dst = Address(rscratch2);
2716 }
2717 ldrw(rscratch1, dst);
2718 decrementw(rscratch1, value);
2719 strw(rscratch1, dst);
2720 }
2721
2722 void MacroAssembler::decrement(Address dst, int value)
2723 {
2724 assert(!dst.uses(rscratch1), "invalid address for decrement");
2725 if (dst.getMode() == Address::literal) {
2726 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2727 lea(rscratch2, dst);
2728 dst = Address(rscratch2);
2729 }
2730 ldr(rscratch1, dst);
2731 decrement(rscratch1, value);
2732 str(rscratch1, dst);
2733 }
2734
2735 void MacroAssembler::incrementw(Register reg, int value)
2736 {
2737 if (value < 0) { decrementw(reg, -value); return; }
2738 if (value == 0) { return; }
2739 if (value < (1 << 12)) { addw(reg, reg, value); return; }
2740 /* else */ {
2741 assert(reg != rscratch2, "invalid dst for register increment");
2742 movw(rscratch2, (unsigned)value);
2743 addw(reg, reg, rscratch2);
2744 }
2745 }
2746
2747 void MacroAssembler::increment(Register reg, int value)
2748 {
2749 if (value < 0) { decrement(reg, -value); return; }
2750 if (value == 0) { return; }
2751 if (value < (1 << 12)) { add(reg, reg, value); return; }
2752 /* else */ {
2753 assert(reg != rscratch2, "invalid dst for register increment");
2754 movw(rscratch2, (unsigned)value);
2755 add(reg, reg, rscratch2);
2756 }
2757 }
2758
2759 void MacroAssembler::incrementw(Address dst, int value)
2760 {
2761 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2762 if (dst.getMode() == Address::literal) {
2763 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2764 lea(rscratch2, dst);
2765 dst = Address(rscratch2);
2766 }
2767 ldrw(rscratch1, dst);
2768 incrementw(rscratch1, value);
2769 strw(rscratch1, dst);
2770 }
2771
2772 void MacroAssembler::increment(Address dst, int value)
2773 {
2774 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2775 if (dst.getMode() == Address::literal) {
2776 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2777 lea(rscratch2, dst);
2778 dst = Address(rscratch2);
2779 }
2780 ldr(rscratch1, dst);
2781 increment(rscratch1, value);
2782 str(rscratch1, dst);
2783 }
2784
2785 // Push lots of registers in the bit set supplied. Don't push sp.
2786 // Return the number of words pushed
2787 int MacroAssembler::push(unsigned int bitset, Register stack) {
2788 int words_pushed = 0;
2789
2790 // Scan bitset to accumulate register pairs
2791 unsigned char regs[32];
2792 int count = 0;
2793 for (int reg = 0; reg <= 30; reg++) {
2794 if (1 & bitset)
2795 regs[count++] = reg;
2796 bitset >>= 1;
2797 }
2798 regs[count++] = zr->raw_encoding();
2799 count &= ~1; // Only push an even number of regs
2800
2801 if (count) {
2802 stp(as_Register(regs[0]), as_Register(regs[1]),
2803 Address(pre(stack, -count * wordSize)));
2804 words_pushed += 2;
2805 }
2806 for (int i = 2; i < count; i += 2) {
2807 stp(as_Register(regs[i]), as_Register(regs[i+1]),
2808 Address(stack, i * wordSize));
2809 words_pushed += 2;
2810 }
2811
2812 assert(words_pushed == count, "oops, pushed != count");
2813
2814 return count;
2815 }
2816
2817 int MacroAssembler::pop(unsigned int bitset, Register stack) {
2818 int words_pushed = 0;
2819
2820 // Scan bitset to accumulate register pairs
2821 unsigned char regs[32];
2822 int count = 0;
2823 for (int reg = 0; reg <= 30; reg++) {
2824 if (1 & bitset)
2825 regs[count++] = reg;
2826 bitset >>= 1;
2827 }
2828 regs[count++] = zr->raw_encoding();
2829 count &= ~1;
2830
2831 for (int i = 2; i < count; i += 2) {
2832 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
2833 Address(stack, i * wordSize));
2834 words_pushed += 2;
2835 }
2836 if (count) {
2837 ldp(as_Register(regs[0]), as_Register(regs[1]),
2838 Address(post(stack, count * wordSize)));
2839 words_pushed += 2;
2840 }
2841
2842 assert(words_pushed == count, "oops, pushed != count");
2843
2844 return count;
2845 }
2846
2847 // Push lots of registers in the bit set supplied. Don't push sp.
2848 // Return the number of dwords pushed
2849 int MacroAssembler::push_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
2850 int words_pushed = 0;
2851 bool use_sve = false;
2852 int sve_vector_size_in_bytes = 0;
2853
2854 #ifdef COMPILER2
2855 use_sve = Matcher::supports_scalable_vector();
2856 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
2857 #endif
2858
2859 // Scan bitset to accumulate register pairs
2860 unsigned char regs[32];
2861 int count = 0;
2862 for (int reg = 0; reg <= 31; reg++) {
2863 if (1 & bitset)
2864 regs[count++] = reg;
2865 bitset >>= 1;
2866 }
2867
2868 if (count == 0) {
2869 return 0;
2870 }
2871
2872 if (mode == PushPopFull) {
2873 if (use_sve && sve_vector_size_in_bytes > 16) {
2874 mode = PushPopSVE;
2875 } else {
2876 mode = PushPopNeon;
2877 }
2878 }
2879
2880 #ifndef PRODUCT
2881 {
2882 char buffer[48];
2883 if (mode == PushPopSVE) {
2884 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d SVE registers", count);
2885 } else if (mode == PushPopNeon) {
2886 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d Neon registers", count);
2887 } else {
2888 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d fp registers", count);
2889 }
2890 block_comment(buffer);
2891 }
2892 #endif
2893
2894 if (mode == PushPopSVE) {
2895 sub(stack, stack, sve_vector_size_in_bytes * count);
2896 for (int i = 0; i < count; i++) {
2897 sve_str(as_FloatRegister(regs[i]), Address(stack, i));
2898 }
2899 return count * sve_vector_size_in_bytes / 8;
2900 }
2901
2902 if (mode == PushPopNeon) {
2903 if (count == 1) {
2904 strq(as_FloatRegister(regs[0]), Address(pre(stack, -wordSize * 2)));
2905 return 2;
2906 }
2907
2908 bool odd = (count & 1) == 1;
2909 int push_slots = count + (odd ? 1 : 0);
2910
2911 // Always pushing full 128 bit registers.
2912 stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize * 2)));
2913 words_pushed += 2;
2914
2915 for (int i = 2; i + 1 < count; i += 2) {
2916 stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
2917 words_pushed += 2;
2918 }
2919
2920 if (odd) {
2921 strq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
2922 words_pushed++;
2923 }
2924
2925 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
2926 return count * 2;
2927 }
2928
2929 if (mode == PushPopFp) {
2930 bool odd = (count & 1) == 1;
2931 int push_slots = count + (odd ? 1 : 0);
2932
2933 if (count == 1) {
2934 // Stack pointer must be 16 bytes aligned
2935 strd(as_FloatRegister(regs[0]), Address(pre(stack, -push_slots * wordSize)));
2936 return 1;
2937 }
2938
2939 stpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize)));
2940 words_pushed += 2;
2941
2942 for (int i = 2; i + 1 < count; i += 2) {
2943 stpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
2944 words_pushed += 2;
2945 }
2946
2947 if (odd) {
2948 // Stack pointer must be 16 bytes aligned
2949 strd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
2950 words_pushed++;
2951 }
2952
2953 assert(words_pushed == count, "oops, pushed != count");
2954
2955 return count;
2956 }
2957
2958 return 0;
2959 }
2960
2961 // Return the number of dwords popped
2962 int MacroAssembler::pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
2963 int words_pushed = 0;
2964 bool use_sve = false;
2965 int sve_vector_size_in_bytes = 0;
2966
2967 #ifdef COMPILER2
2968 use_sve = Matcher::supports_scalable_vector();
2969 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
2970 #endif
2971 // Scan bitset to accumulate register pairs
2972 unsigned char regs[32];
2973 int count = 0;
2974 for (int reg = 0; reg <= 31; reg++) {
2975 if (1 & bitset)
2976 regs[count++] = reg;
2977 bitset >>= 1;
2978 }
2979
2980 if (count == 0) {
2981 return 0;
2982 }
2983
2984 if (mode == PushPopFull) {
2985 if (use_sve && sve_vector_size_in_bytes > 16) {
2986 mode = PushPopSVE;
2987 } else {
2988 mode = PushPopNeon;
2989 }
2990 }
2991
2992 #ifndef PRODUCT
2993 {
2994 char buffer[48];
2995 if (mode == PushPopSVE) {
2996 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d SVE registers", count);
2997 } else if (mode == PushPopNeon) {
2998 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d Neon registers", count);
2999 } else {
3000 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d fp registers", count);
3001 }
3002 block_comment(buffer);
3003 }
3004 #endif
3005
3006 if (mode == PushPopSVE) {
3007 for (int i = count - 1; i >= 0; i--) {
3008 sve_ldr(as_FloatRegister(regs[i]), Address(stack, i));
3009 }
3010 add(stack, stack, sve_vector_size_in_bytes * count);
3011 return count * sve_vector_size_in_bytes / 8;
3012 }
3013
3014 if (mode == PushPopNeon) {
3015 if (count == 1) {
3016 ldrq(as_FloatRegister(regs[0]), Address(post(stack, wordSize * 2)));
3017 return 2;
3018 }
3019
3020 bool odd = (count & 1) == 1;
3021 int push_slots = count + (odd ? 1 : 0);
3022
3023 if (odd) {
3024 ldrq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3025 words_pushed++;
3026 }
3027
3028 for (int i = 2; i + 1 < count; i += 2) {
3029 ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3030 words_pushed += 2;
3031 }
3032
3033 ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize * 2)));
3034 words_pushed += 2;
3035
3036 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3037
3038 return count * 2;
3039 }
3040
3041 if (mode == PushPopFp) {
3042 bool odd = (count & 1) == 1;
3043 int push_slots = count + (odd ? 1 : 0);
3044
3045 if (count == 1) {
3046 ldrd(as_FloatRegister(regs[0]), Address(post(stack, push_slots * wordSize)));
3047 return 1;
3048 }
3049
3050 if (odd) {
3051 ldrd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3052 words_pushed++;
3053 }
3054
3055 for (int i = 2; i + 1 < count; i += 2) {
3056 ldpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3057 words_pushed += 2;
3058 }
3059
3060 ldpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize)));
3061 words_pushed += 2;
3062
3063 assert(words_pushed == count, "oops, pushed != count");
3064
3065 return count;
3066 }
3067
3068 return 0;
3069 }
3070
3071 // Return the number of dwords pushed
3072 int MacroAssembler::push_p(unsigned int bitset, Register stack) {
3073 bool use_sve = false;
3074 int sve_predicate_size_in_slots = 0;
3075
3076 #ifdef COMPILER2
3077 use_sve = Matcher::supports_scalable_vector();
3078 if (use_sve) {
3079 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3080 }
3081 #endif
3082
3083 if (!use_sve) {
3084 return 0;
3085 }
3086
3087 unsigned char regs[PRegister::number_of_registers];
3088 int count = 0;
3089 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3090 if (1 & bitset)
3091 regs[count++] = reg;
3092 bitset >>= 1;
3093 }
3094
3095 if (count == 0) {
3096 return 0;
3097 }
3098
3099 int total_push_bytes = align_up(sve_predicate_size_in_slots *
3100 VMRegImpl::stack_slot_size * count, 16);
3101 sub(stack, stack, total_push_bytes);
3102 for (int i = 0; i < count; i++) {
3103 sve_str(as_PRegister(regs[i]), Address(stack, i));
3104 }
3105 return total_push_bytes / 8;
3106 }
3107
3108 // Return the number of dwords popped
3109 int MacroAssembler::pop_p(unsigned int bitset, Register stack) {
3110 bool use_sve = false;
3111 int sve_predicate_size_in_slots = 0;
3112
3113 #ifdef COMPILER2
3114 use_sve = Matcher::supports_scalable_vector();
3115 if (use_sve) {
3116 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3117 }
3118 #endif
3119
3120 if (!use_sve) {
3121 return 0;
3122 }
3123
3124 unsigned char regs[PRegister::number_of_registers];
3125 int count = 0;
3126 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3127 if (1 & bitset)
3128 regs[count++] = reg;
3129 bitset >>= 1;
3130 }
3131
3132 if (count == 0) {
3133 return 0;
3134 }
3135
3136 int total_pop_bytes = align_up(sve_predicate_size_in_slots *
3137 VMRegImpl::stack_slot_size * count, 16);
3138 for (int i = count - 1; i >= 0; i--) {
3139 sve_ldr(as_PRegister(regs[i]), Address(stack, i));
3140 }
3141 add(stack, stack, total_pop_bytes);
3142 return total_pop_bytes / 8;
3143 }
3144
3145 #ifdef ASSERT
3146 void MacroAssembler::verify_heapbase(const char* msg) {
3147 #if 0
3148 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
3149 assert (Universe::heap() != nullptr, "java heap should be initialized");
3150 if (!UseCompressedOops || Universe::ptr_base() == nullptr) {
3151 // rheapbase is allocated as general register
3152 return;
3153 }
3154 if (CheckCompressedOops) {
3155 Label ok;
3156 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
3157 cmpptr(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3158 br(Assembler::EQ, ok);
3159 stop(msg);
3160 bind(ok);
3161 pop(1 << rscratch1->encoding(), sp);
3162 }
3163 #endif
3164 }
3165 #endif
3166
3167 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2) {
3168 assert_different_registers(value, tmp1, tmp2);
3169 Label done, tagged, weak_tagged;
3170
3171 cbz(value, done); // Use null as-is.
3172 tst(value, JNIHandles::tag_mask); // Test for tag.
3173 br(Assembler::NE, tagged);
3174
3175 // Resolve local handle
3176 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp1, tmp2);
3177 verify_oop(value);
3178 b(done);
3179
3180 bind(tagged);
3181 STATIC_ASSERT(JNIHandles::TypeTag::weak_global == 0b1);
3182 tbnz(value, 0, weak_tagged); // Test for weak tag.
3183
3184 // Resolve global handle
3185 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3186 verify_oop(value);
3187 b(done);
3188
3189 bind(weak_tagged);
3190 // Resolve jweak.
3191 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3192 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp1, tmp2);
3193 verify_oop(value);
3194
3195 bind(done);
3196 }
3197
3198 void MacroAssembler::resolve_global_jobject(Register value, Register tmp1, Register tmp2) {
3199 assert_different_registers(value, tmp1, tmp2);
3200 Label done;
3201
3202 cbz(value, done); // Use null as-is.
3203
3204 #ifdef ASSERT
3205 {
3206 STATIC_ASSERT(JNIHandles::TypeTag::global == 0b10);
3207 Label valid_global_tag;
3208 tbnz(value, 1, valid_global_tag); // Test for global tag
3209 stop("non global jobject using resolve_global_jobject");
3210 bind(valid_global_tag);
3211 }
3212 #endif
3213
3214 // Resolve global handle
3215 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3216 verify_oop(value);
3217
3218 bind(done);
3219 }
3220
3221 void MacroAssembler::stop(const char* msg) {
3222 // Skip AOT caching C strings in scratch buffer.
3223 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
3224 BLOCK_COMMENT(str);
3225 // load msg into r0 so we can access it from the signal handler
3226 // ExternalAddress enables saving and restoring via the code cache
3227 lea(c_rarg0, ExternalAddress((address) str));
3228 dcps1(0xdeae);
3229 }
3230
3231 void MacroAssembler::unimplemented(const char* what) {
3232 const char* buf = nullptr;
3233 {
3234 ResourceMark rm;
3235 stringStream ss;
3236 ss.print("unimplemented: %s", what);
3237 buf = code_string(ss.as_string());
3238 }
3239 stop(buf);
3240 }
3241
3242 void MacroAssembler::_assert_asm(Assembler::Condition cc, const char* msg) {
3243 #ifdef ASSERT
3244 Label OK;
3245 br(cc, OK);
3246 stop(msg);
3247 bind(OK);
3248 #endif
3249 }
3250
3251 // If a constant does not fit in an immediate field, generate some
3252 // number of MOV instructions and then perform the operation.
3253 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
3254 add_sub_imm_insn insn1,
3255 add_sub_reg_insn insn2,
3256 bool is32) {
3257 assert(Rd != zr, "Rd = zr and not setting flags?");
3258 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3259 if (fits) {
3260 (this->*insn1)(Rd, Rn, imm);
3261 } else {
3262 if (g_uabs(imm) < (1 << 24)) {
3263 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
3264 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
3265 } else {
3266 assert_different_registers(Rd, Rn);
3267 mov(Rd, imm);
3268 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3269 }
3270 }
3271 }
3272
3273 // Separate vsn which sets the flags. Optimisations are more restricted
3274 // because we must set the flags correctly.
3275 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
3276 add_sub_imm_insn insn1,
3277 add_sub_reg_insn insn2,
3278 bool is32) {
3279 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3280 if (fits) {
3281 (this->*insn1)(Rd, Rn, imm);
3282 } else {
3283 assert_different_registers(Rd, Rn);
3284 assert(Rd != zr, "overflow in immediate operand");
3285 mov(Rd, imm);
3286 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3287 }
3288 }
3289
3290
3291 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
3292 if (increment.is_register()) {
3293 add(Rd, Rn, increment.as_register());
3294 } else {
3295 add(Rd, Rn, increment.as_constant());
3296 }
3297 }
3298
3299 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
3300 if (increment.is_register()) {
3301 addw(Rd, Rn, increment.as_register());
3302 } else {
3303 addw(Rd, Rn, increment.as_constant());
3304 }
3305 }
3306
3307 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
3308 if (decrement.is_register()) {
3309 sub(Rd, Rn, decrement.as_register());
3310 } else {
3311 sub(Rd, Rn, decrement.as_constant());
3312 }
3313 }
3314
3315 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
3316 if (decrement.is_register()) {
3317 subw(Rd, Rn, decrement.as_register());
3318 } else {
3319 subw(Rd, Rn, decrement.as_constant());
3320 }
3321 }
3322
3323 void MacroAssembler::reinit_heapbase()
3324 {
3325 if (UseCompressedOops) {
3326 if (Universe::is_fully_initialized() && !AOTCodeCache::is_on_for_dump()) {
3327 mov(rheapbase, CompressedOops::base());
3328 } else {
3329 lea(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3330 ldr(rheapbase, Address(rheapbase));
3331 }
3332 }
3333 }
3334
3335 // A generic CAS; success or failure is in the EQ flag. A weak CAS
3336 // doesn't retry and may fail spuriously. If the oldval is wanted,
3337 // Pass a register for the result, otherwise pass noreg.
3338
3339 // Clobbers rscratch1
3340 void MacroAssembler::cmpxchg(Register addr, Register expected,
3341 Register new_val,
3342 enum operand_size size,
3343 bool acquire, bool release,
3344 bool weak,
3345 Register result) {
3346 if (result == noreg) result = rscratch1;
3347 BLOCK_COMMENT("cmpxchg {");
3348 if (UseLSE) {
3349 mov(result, expected);
3350 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
3351 compare_eq(result, expected, size);
3352 #ifdef ASSERT
3353 // Poison rscratch1 which is written on !UseLSE branch
3354 mov(rscratch1, 0x1f1f1f1f1f1f1f1f);
3355 #endif
3356 } else {
3357 Label retry_load, done;
3358 prfm(Address(addr), PSTL1STRM);
3359 bind(retry_load);
3360 load_exclusive(result, addr, size, acquire);
3361 compare_eq(result, expected, size);
3362 br(Assembler::NE, done);
3363 store_exclusive(rscratch1, new_val, addr, size, release);
3364 if (weak) {
3365 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
3366 } else {
3367 cbnzw(rscratch1, retry_load);
3368 }
3369 bind(done);
3370 }
3371 BLOCK_COMMENT("} cmpxchg");
3372 }
3373
3374 // A generic comparison. Only compares for equality, clobbers rscratch1.
3375 void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) {
3376 if (size == xword) {
3377 cmp(rm, rn);
3378 } else if (size == word) {
3379 cmpw(rm, rn);
3380 } else if (size == halfword) {
3381 eorw(rscratch1, rm, rn);
3382 ands(zr, rscratch1, 0xffff);
3383 } else if (size == byte) {
3384 eorw(rscratch1, rm, rn);
3385 ands(zr, rscratch1, 0xff);
3386 } else {
3387 ShouldNotReachHere();
3388 }
3389 }
3390
3391
3392 static bool different(Register a, RegisterOrConstant b, Register c) {
3393 if (b.is_constant())
3394 return a != c;
3395 else
3396 return a != b.as_register() && a != c && b.as_register() != c;
3397 }
3398
3399 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \
3400 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \
3401 if (UseLSE) { \
3402 prev = prev->is_valid() ? prev : zr; \
3403 if (incr.is_register()) { \
3404 AOP(sz, incr.as_register(), prev, addr); \
3405 } else { \
3406 mov(rscratch2, incr.as_constant()); \
3407 AOP(sz, rscratch2, prev, addr); \
3408 } \
3409 return; \
3410 } \
3411 Register result = rscratch2; \
3412 if (prev->is_valid()) \
3413 result = different(prev, incr, addr) ? prev : rscratch2; \
3414 \
3415 Label retry_load; \
3416 prfm(Address(addr), PSTL1STRM); \
3417 bind(retry_load); \
3418 LDXR(result, addr); \
3419 OP(rscratch1, result, incr); \
3420 STXR(rscratch2, rscratch1, addr); \
3421 cbnzw(rscratch2, retry_load); \
3422 if (prev->is_valid() && prev != result) { \
3423 IOP(prev, rscratch1, incr); \
3424 } \
3425 }
3426
3427 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword)
3428 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
3429 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword)
3430 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word)
3431
3432 #undef ATOMIC_OP
3433
3434 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \
3435 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
3436 if (UseLSE) { \
3437 prev = prev->is_valid() ? prev : zr; \
3438 AOP(sz, newv, prev, addr); \
3439 return; \
3440 } \
3441 Register result = rscratch2; \
3442 if (prev->is_valid()) \
3443 result = different(prev, newv, addr) ? prev : rscratch2; \
3444 \
3445 Label retry_load; \
3446 prfm(Address(addr), PSTL1STRM); \
3447 bind(retry_load); \
3448 LDXR(result, addr); \
3449 STXR(rscratch1, newv, addr); \
3450 cbnzw(rscratch1, retry_load); \
3451 if (prev->is_valid() && prev != result) \
3452 mov(prev, result); \
3453 }
3454
3455 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
3456 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
3457 ATOMIC_XCHG(xchgl, swpl, ldxr, stlxr, Assembler::xword)
3458 ATOMIC_XCHG(xchglw, swpl, ldxrw, stlxrw, Assembler::word)
3459 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
3460 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
3461
3462 #undef ATOMIC_XCHG
3463
3464 #ifndef PRODUCT
3465 extern "C" void findpc(intptr_t x);
3466 #endif
3467
3468 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
3469 {
3470 // In order to get locks to work, we need to fake a in_VM state
3471 if (ShowMessageBoxOnError ) {
3472 JavaThread* thread = JavaThread::current();
3473 JavaThreadState saved_state = thread->thread_state();
3474 thread->set_thread_state(_thread_in_vm);
3475 #ifndef PRODUCT
3476 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
3477 ttyLocker ttyl;
3478 BytecodeCounter::print();
3479 }
3480 #endif
3481 if (os::message_box(msg, "Execution stopped, print registers?")) {
3482 ttyLocker ttyl;
3483 tty->print_cr(" pc = 0x%016" PRIx64, pc);
3484 #ifndef PRODUCT
3485 tty->cr();
3486 findpc(pc);
3487 tty->cr();
3488 #endif
3489 tty->print_cr(" r0 = 0x%016" PRIx64, regs[0]);
3490 tty->print_cr(" r1 = 0x%016" PRIx64, regs[1]);
3491 tty->print_cr(" r2 = 0x%016" PRIx64, regs[2]);
3492 tty->print_cr(" r3 = 0x%016" PRIx64, regs[3]);
3493 tty->print_cr(" r4 = 0x%016" PRIx64, regs[4]);
3494 tty->print_cr(" r5 = 0x%016" PRIx64, regs[5]);
3495 tty->print_cr(" r6 = 0x%016" PRIx64, regs[6]);
3496 tty->print_cr(" r7 = 0x%016" PRIx64, regs[7]);
3497 tty->print_cr(" r8 = 0x%016" PRIx64, regs[8]);
3498 tty->print_cr(" r9 = 0x%016" PRIx64, regs[9]);
3499 tty->print_cr("r10 = 0x%016" PRIx64, regs[10]);
3500 tty->print_cr("r11 = 0x%016" PRIx64, regs[11]);
3501 tty->print_cr("r12 = 0x%016" PRIx64, regs[12]);
3502 tty->print_cr("r13 = 0x%016" PRIx64, regs[13]);
3503 tty->print_cr("r14 = 0x%016" PRIx64, regs[14]);
3504 tty->print_cr("r15 = 0x%016" PRIx64, regs[15]);
3505 tty->print_cr("r16 = 0x%016" PRIx64, regs[16]);
3506 tty->print_cr("r17 = 0x%016" PRIx64, regs[17]);
3507 tty->print_cr("r18 = 0x%016" PRIx64, regs[18]);
3508 tty->print_cr("r19 = 0x%016" PRIx64, regs[19]);
3509 tty->print_cr("r20 = 0x%016" PRIx64, regs[20]);
3510 tty->print_cr("r21 = 0x%016" PRIx64, regs[21]);
3511 tty->print_cr("r22 = 0x%016" PRIx64, regs[22]);
3512 tty->print_cr("r23 = 0x%016" PRIx64, regs[23]);
3513 tty->print_cr("r24 = 0x%016" PRIx64, regs[24]);
3514 tty->print_cr("r25 = 0x%016" PRIx64, regs[25]);
3515 tty->print_cr("r26 = 0x%016" PRIx64, regs[26]);
3516 tty->print_cr("r27 = 0x%016" PRIx64, regs[27]);
3517 tty->print_cr("r28 = 0x%016" PRIx64, regs[28]);
3518 tty->print_cr("r30 = 0x%016" PRIx64, regs[30]);
3519 tty->print_cr("r31 = 0x%016" PRIx64, regs[31]);
3520 BREAKPOINT;
3521 }
3522 }
3523 fatal("DEBUG MESSAGE: %s", msg);
3524 }
3525
3526 RegSet MacroAssembler::call_clobbered_gp_registers() {
3527 RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2);
3528 #ifndef R18_RESERVED
3529 regs += r18_tls;
3530 #endif
3531 return regs;
3532 }
3533
3534 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
3535 int step = 4 * wordSize;
3536 push(call_clobbered_gp_registers() - exclude, sp);
3537 sub(sp, sp, step);
3538 mov(rscratch1, -step);
3539 // Push v0-v7, v16-v31.
3540 for (int i = 31; i>= 4; i -= 4) {
3541 if (i <= v7->encoding() || i >= v16->encoding())
3542 st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1),
3543 as_FloatRegister(i), T1D, Address(post(sp, rscratch1)));
3544 }
3545 st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2),
3546 as_FloatRegister(3), T1D, Address(sp));
3547 }
3548
3549 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
3550 for (int i = 0; i < 32; i += 4) {
3551 if (i <= v7->encoding() || i >= v16->encoding())
3552 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3553 as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
3554 }
3555
3556 reinitialize_ptrue();
3557
3558 pop(call_clobbered_gp_registers() - exclude, sp);
3559 }
3560
3561 void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve,
3562 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3563 push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
3564 if (save_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3565 sub(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3566 for (int i = 0; i < FloatRegister::number_of_registers; i++) {
3567 sve_str(as_FloatRegister(i), Address(sp, i));
3568 }
3569 } else {
3570 int step = (save_vectors ? 8 : 4) * wordSize;
3571 mov(rscratch1, -step);
3572 sub(sp, sp, step);
3573 for (int i = 28; i >= 4; i -= 4) {
3574 st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3575 as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1)));
3576 }
3577 st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp);
3578 }
3579 if (save_vectors && use_sve && total_predicate_in_bytes > 0) {
3580 sub(sp, sp, total_predicate_in_bytes);
3581 for (int i = 0; i < PRegister::number_of_registers; i++) {
3582 sve_str(as_PRegister(i), Address(sp, i));
3583 }
3584 }
3585 }
3586
3587 void MacroAssembler::pop_CPU_state(bool restore_vectors, bool use_sve,
3588 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3589 if (restore_vectors && use_sve && total_predicate_in_bytes > 0) {
3590 for (int i = PRegister::number_of_registers - 1; i >= 0; i--) {
3591 sve_ldr(as_PRegister(i), Address(sp, i));
3592 }
3593 add(sp, sp, total_predicate_in_bytes);
3594 }
3595 if (restore_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3596 for (int i = FloatRegister::number_of_registers - 1; i >= 0; i--) {
3597 sve_ldr(as_FloatRegister(i), Address(sp, i));
3598 }
3599 add(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3600 } else {
3601 int step = (restore_vectors ? 8 : 4) * wordSize;
3602 for (int i = 0; i <= 28; i += 4)
3603 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3604 as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step)));
3605 }
3606
3607 // We may use predicate registers and rely on ptrue with SVE,
3608 // regardless of wide vector (> 8 bytes) used or not.
3609 if (use_sve) {
3610 reinitialize_ptrue();
3611 }
3612
3613 // integer registers except lr & sp
3614 pop(RegSet::range(r0, r17), sp);
3615 #ifdef R18_RESERVED
3616 ldp(zr, r19, Address(post(sp, 2 * wordSize)));
3617 pop(RegSet::range(r20, r29), sp);
3618 #else
3619 pop(RegSet::range(r18_tls, r29), sp);
3620 #endif
3621 }
3622
3623 /**
3624 * Helpers for multiply_to_len().
3625 */
3626 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
3627 Register src1, Register src2) {
3628 adds(dest_lo, dest_lo, src1);
3629 adc(dest_hi, dest_hi, zr);
3630 adds(dest_lo, dest_lo, src2);
3631 adc(final_dest_hi, dest_hi, zr);
3632 }
3633
3634 // Generate an address from (r + r1 extend offset). "size" is the
3635 // size of the operand. The result may be in rscratch2.
3636 Address MacroAssembler::offsetted_address(Register r, Register r1,
3637 Address::extend ext, int offset, int size) {
3638 if (offset || (ext.shift() % size != 0)) {
3639 lea(rscratch2, Address(r, r1, ext));
3640 return Address(rscratch2, offset);
3641 } else {
3642 return Address(r, r1, ext);
3643 }
3644 }
3645
3646 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
3647 {
3648 assert(offset >= 0, "spill to negative address?");
3649 // Offset reachable ?
3650 // Not aligned - 9 bits signed offset
3651 // Aligned - 12 bits unsigned offset shifted
3652 Register base = sp;
3653 if ((offset & (size-1)) && offset >= (1<<8)) {
3654 add(tmp, base, offset & ((1<<12)-1));
3655 base = tmp;
3656 offset &= -1u<<12;
3657 }
3658
3659 if (offset >= (1<<12) * size) {
3660 add(tmp, base, offset & (((1<<12)-1)<<12));
3661 base = tmp;
3662 offset &= ~(((1<<12)-1)<<12);
3663 }
3664
3665 return Address(base, offset);
3666 }
3667
3668 Address MacroAssembler::sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp) {
3669 assert(offset >= 0, "spill to negative address?");
3670
3671 Register base = sp;
3672
3673 // An immediate offset in the range 0 to 255 which is multiplied
3674 // by the current vector or predicate register size in bytes.
3675 if (offset % sve_reg_size_in_bytes == 0 && offset < ((1<<8)*sve_reg_size_in_bytes)) {
3676 return Address(base, offset / sve_reg_size_in_bytes);
3677 }
3678
3679 add(tmp, base, offset);
3680 return Address(tmp);
3681 }
3682
3683 // Checks whether offset is aligned.
3684 // Returns true if it is, else false.
3685 bool MacroAssembler::merge_alignment_check(Register base,
3686 size_t size,
3687 int64_t cur_offset,
3688 int64_t prev_offset) const {
3689 if (AvoidUnalignedAccesses) {
3690 if (base == sp) {
3691 // Checks whether low offset if aligned to pair of registers.
3692 int64_t pair_mask = size * 2 - 1;
3693 int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3694 return (offset & pair_mask) == 0;
3695 } else { // If base is not sp, we can't guarantee the access is aligned.
3696 return false;
3697 }
3698 } else {
3699 int64_t mask = size - 1;
3700 // Load/store pair instruction only supports element size aligned offset.
3701 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
3702 }
3703 }
3704
3705 // Checks whether current and previous loads/stores can be merged.
3706 // Returns true if it can be merged, else false.
3707 bool MacroAssembler::ldst_can_merge(Register rt,
3708 const Address &adr,
3709 size_t cur_size_in_bytes,
3710 bool is_store) const {
3711 address prev = pc() - NativeInstruction::instruction_size;
3712 address last = code()->last_insn();
3713
3714 if (last == nullptr || !nativeInstruction_at(last)->is_Imm_LdSt()) {
3715 return false;
3716 }
3717
3718 if (adr.getMode() != Address::base_plus_offset || prev != last) {
3719 return false;
3720 }
3721
3722 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3723 size_t prev_size_in_bytes = prev_ldst->size_in_bytes();
3724
3725 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging.");
3726 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging.");
3727
3728 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) {
3729 return false;
3730 }
3731
3732 int64_t max_offset = 63 * prev_size_in_bytes;
3733 int64_t min_offset = -64 * prev_size_in_bytes;
3734
3735 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
3736
3737 // Only same base can be merged.
3738 if (adr.base() != prev_ldst->base()) {
3739 return false;
3740 }
3741
3742 int64_t cur_offset = adr.offset();
3743 int64_t prev_offset = prev_ldst->offset();
3744 size_t diff = abs(cur_offset - prev_offset);
3745 if (diff != prev_size_in_bytes) {
3746 return false;
3747 }
3748
3749 // Following cases can not be merged:
3750 // ldr x2, [x2, #8]
3751 // ldr x3, [x2, #16]
3752 // or:
3753 // ldr x2, [x3, #8]
3754 // ldr x2, [x3, #16]
3755 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL.
3756 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) {
3757 return false;
3758 }
3759
3760 int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3761 // Offset range must be in ldp/stp instruction's range.
3762 if (low_offset > max_offset || low_offset < min_offset) {
3763 return false;
3764 }
3765
3766 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) {
3767 return true;
3768 }
3769
3770 return false;
3771 }
3772
3773 // Merge current load/store with previous load/store into ldp/stp.
3774 void MacroAssembler::merge_ldst(Register rt,
3775 const Address &adr,
3776 size_t cur_size_in_bytes,
3777 bool is_store) {
3778
3779 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged.");
3780
3781 Register rt_low, rt_high;
3782 address prev = pc() - NativeInstruction::instruction_size;
3783 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3784
3785 int64_t offset;
3786
3787 if (adr.offset() < prev_ldst->offset()) {
3788 offset = adr.offset();
3789 rt_low = rt;
3790 rt_high = prev_ldst->target();
3791 } else {
3792 offset = prev_ldst->offset();
3793 rt_low = prev_ldst->target();
3794 rt_high = rt;
3795 }
3796
3797 Address adr_p = Address(prev_ldst->base(), offset);
3798 // Overwrite previous generated binary.
3799 code_section()->set_end(prev);
3800
3801 const size_t sz = prev_ldst->size_in_bytes();
3802 assert(sz == 8 || sz == 4, "only supports 64/32bit merging.");
3803 if (!is_store) {
3804 BLOCK_COMMENT("merged ldr pair");
3805 if (sz == 8) {
3806 ldp(rt_low, rt_high, adr_p);
3807 } else {
3808 ldpw(rt_low, rt_high, adr_p);
3809 }
3810 } else {
3811 BLOCK_COMMENT("merged str pair");
3812 if (sz == 8) {
3813 stp(rt_low, rt_high, adr_p);
3814 } else {
3815 stpw(rt_low, rt_high, adr_p);
3816 }
3817 }
3818 }
3819
3820 /**
3821 * Multiply 64 bit by 64 bit first loop.
3822 */
3823 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
3824 Register y, Register y_idx, Register z,
3825 Register carry, Register product,
3826 Register idx, Register kdx) {
3827 //
3828 // jlong carry, x[], y[], z[];
3829 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
3830 // huge_128 product = y[idx] * x[xstart] + carry;
3831 // z[kdx] = (jlong)product;
3832 // carry = (jlong)(product >>> 64);
3833 // }
3834 // z[xstart] = carry;
3835 //
3836
3837 Label L_first_loop, L_first_loop_exit;
3838 Label L_one_x, L_one_y, L_multiply;
3839
3840 subsw(xstart, xstart, 1);
3841 br(Assembler::MI, L_one_x);
3842
3843 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
3844 ldr(x_xstart, Address(rscratch1));
3845 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
3846
3847 bind(L_first_loop);
3848 subsw(idx, idx, 1);
3849 br(Assembler::MI, L_first_loop_exit);
3850 subsw(idx, idx, 1);
3851 br(Assembler::MI, L_one_y);
3852 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3853 ldr(y_idx, Address(rscratch1));
3854 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
3855 bind(L_multiply);
3856
3857 // AArch64 has a multiply-accumulate instruction that we can't use
3858 // here because it has no way to process carries, so we have to use
3859 // separate add and adc instructions. Bah.
3860 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
3861 mul(product, x_xstart, y_idx);
3862 adds(product, product, carry);
3863 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
3864
3865 subw(kdx, kdx, 2);
3866 ror(product, product, 32); // back to big-endian
3867 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
3868
3869 b(L_first_loop);
3870
3871 bind(L_one_y);
3872 ldrw(y_idx, Address(y, 0));
3873 b(L_multiply);
3874
3875 bind(L_one_x);
3876 ldrw(x_xstart, Address(x, 0));
3877 b(L_first_loop);
3878
3879 bind(L_first_loop_exit);
3880 }
3881
3882 /**
3883 * Multiply 128 bit by 128. Unrolled inner loop.
3884 *
3885 */
3886 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
3887 Register carry, Register carry2,
3888 Register idx, Register jdx,
3889 Register yz_idx1, Register yz_idx2,
3890 Register tmp, Register tmp3, Register tmp4,
3891 Register tmp6, Register product_hi) {
3892
3893 // jlong carry, x[], y[], z[];
3894 // int kdx = ystart+1;
3895 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
3896 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
3897 // jlong carry2 = (jlong)(tmp3 >>> 64);
3898 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
3899 // carry = (jlong)(tmp4 >>> 64);
3900 // z[kdx+idx+1] = (jlong)tmp3;
3901 // z[kdx+idx] = (jlong)tmp4;
3902 // }
3903 // idx += 2;
3904 // if (idx > 0) {
3905 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
3906 // z[kdx+idx] = (jlong)yz_idx1;
3907 // carry = (jlong)(yz_idx1 >>> 64);
3908 // }
3909 //
3910
3911 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
3912
3913 lsrw(jdx, idx, 2);
3914
3915 bind(L_third_loop);
3916
3917 subsw(jdx, jdx, 1);
3918 br(Assembler::MI, L_third_loop_exit);
3919 subw(idx, idx, 4);
3920
3921 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3922
3923 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
3924
3925 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
3926
3927 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
3928 ror(yz_idx2, yz_idx2, 32);
3929
3930 ldp(rscratch2, rscratch1, Address(tmp6, 0));
3931
3932 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
3933 umulh(tmp4, product_hi, yz_idx1);
3934
3935 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
3936 ror(rscratch2, rscratch2, 32);
3937
3938 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
3939 umulh(carry2, product_hi, yz_idx2);
3940
3941 // propagate sum of both multiplications into carry:tmp4:tmp3
3942 adds(tmp3, tmp3, carry);
3943 adc(tmp4, tmp4, zr);
3944 adds(tmp3, tmp3, rscratch1);
3945 adcs(tmp4, tmp4, tmp);
3946 adc(carry, carry2, zr);
3947 adds(tmp4, tmp4, rscratch2);
3948 adc(carry, carry, zr);
3949
3950 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
3951 ror(tmp4, tmp4, 32);
3952 stp(tmp4, tmp3, Address(tmp6, 0));
3953
3954 b(L_third_loop);
3955 bind (L_third_loop_exit);
3956
3957 andw (idx, idx, 0x3);
3958 cbz(idx, L_post_third_loop_done);
3959
3960 Label L_check_1;
3961 subsw(idx, idx, 2);
3962 br(Assembler::MI, L_check_1);
3963
3964 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3965 ldr(yz_idx1, Address(rscratch1, 0));
3966 ror(yz_idx1, yz_idx1, 32);
3967 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
3968 umulh(tmp4, product_hi, yz_idx1);
3969 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
3970 ldr(yz_idx2, Address(rscratch1, 0));
3971 ror(yz_idx2, yz_idx2, 32);
3972
3973 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
3974
3975 ror(tmp3, tmp3, 32);
3976 str(tmp3, Address(rscratch1, 0));
3977
3978 bind (L_check_1);
3979
3980 andw (idx, idx, 0x1);
3981 subsw(idx, idx, 1);
3982 br(Assembler::MI, L_post_third_loop_done);
3983 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3984 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
3985 umulh(carry2, tmp4, product_hi);
3986 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
3987
3988 add2_with_carry(carry2, tmp3, tmp4, carry);
3989
3990 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
3991 extr(carry, carry2, tmp3, 32);
3992
3993 bind(L_post_third_loop_done);
3994 }
3995
3996 /**
3997 * Code for BigInteger::multiplyToLen() intrinsic.
3998 *
3999 * r0: x
4000 * r1: xlen
4001 * r2: y
4002 * r3: ylen
4003 * r4: z
4004 * r5: tmp0
4005 * r10: tmp1
4006 * r11: tmp2
4007 * r12: tmp3
4008 * r13: tmp4
4009 * r14: tmp5
4010 * r15: tmp6
4011 * r16: tmp7
4012 *
4013 */
4014 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
4015 Register z, Register tmp0,
4016 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
4017 Register tmp5, Register tmp6, Register product_hi) {
4018
4019 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, product_hi);
4020
4021 const Register idx = tmp1;
4022 const Register kdx = tmp2;
4023 const Register xstart = tmp3;
4024
4025 const Register y_idx = tmp4;
4026 const Register carry = tmp5;
4027 const Register product = xlen;
4028 const Register x_xstart = tmp0;
4029
4030 // First Loop.
4031 //
4032 // final static long LONG_MASK = 0xffffffffL;
4033 // int xstart = xlen - 1;
4034 // int ystart = ylen - 1;
4035 // long carry = 0;
4036 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
4037 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
4038 // z[kdx] = (int)product;
4039 // carry = product >>> 32;
4040 // }
4041 // z[xstart] = (int)carry;
4042 //
4043
4044 movw(idx, ylen); // idx = ylen;
4045 addw(kdx, xlen, ylen); // kdx = xlen+ylen;
4046 mov(carry, zr); // carry = 0;
4047
4048 Label L_done;
4049
4050 movw(xstart, xlen);
4051 subsw(xstart, xstart, 1);
4052 br(Assembler::MI, L_done);
4053
4054 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
4055
4056 Label L_second_loop;
4057 cbzw(kdx, L_second_loop);
4058
4059 Label L_carry;
4060 subw(kdx, kdx, 1);
4061 cbzw(kdx, L_carry);
4062
4063 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4064 lsr(carry, carry, 32);
4065 subw(kdx, kdx, 1);
4066
4067 bind(L_carry);
4068 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4069
4070 // Second and third (nested) loops.
4071 //
4072 // for (int i = xstart-1; i >= 0; i--) { // Second loop
4073 // carry = 0;
4074 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
4075 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
4076 // (z[k] & LONG_MASK) + carry;
4077 // z[k] = (int)product;
4078 // carry = product >>> 32;
4079 // }
4080 // z[i] = (int)carry;
4081 // }
4082 //
4083 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
4084
4085 const Register jdx = tmp1;
4086
4087 bind(L_second_loop);
4088 mov(carry, zr); // carry = 0;
4089 movw(jdx, ylen); // j = ystart+1
4090
4091 subsw(xstart, xstart, 1); // i = xstart-1;
4092 br(Assembler::MI, L_done);
4093
4094 str(z, Address(pre(sp, -4 * wordSize)));
4095
4096 Label L_last_x;
4097 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
4098 subsw(xstart, xstart, 1); // i = xstart-1;
4099 br(Assembler::MI, L_last_x);
4100
4101 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
4102 ldr(product_hi, Address(rscratch1));
4103 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
4104
4105 Label L_third_loop_prologue;
4106 bind(L_third_loop_prologue);
4107
4108 str(ylen, Address(sp, wordSize));
4109 stp(x, xstart, Address(sp, 2 * wordSize));
4110 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
4111 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
4112 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
4113 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
4114
4115 addw(tmp3, xlen, 1);
4116 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4117 subsw(tmp3, tmp3, 1);
4118 br(Assembler::MI, L_done);
4119
4120 lsr(carry, carry, 32);
4121 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4122 b(L_second_loop);
4123
4124 // Next infrequent code is moved outside loops.
4125 bind(L_last_x);
4126 ldrw(product_hi, Address(x, 0));
4127 b(L_third_loop_prologue);
4128
4129 bind(L_done);
4130 }
4131
4132 // Code for BigInteger::mulAdd intrinsic
4133 // out = r0
4134 // in = r1
4135 // offset = r2 (already out.length-offset)
4136 // len = r3
4137 // k = r4
4138 //
4139 // pseudo code from java implementation:
4140 // carry = 0;
4141 // offset = out.length-offset - 1;
4142 // for (int j=len-1; j >= 0; j--) {
4143 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry;
4144 // out[offset--] = (int)product;
4145 // carry = product >>> 32;
4146 // }
4147 // return (int)carry;
4148 void MacroAssembler::mul_add(Register out, Register in, Register offset,
4149 Register len, Register k) {
4150 Label LOOP, END;
4151 // pre-loop
4152 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches
4153 csel(out, zr, out, Assembler::EQ);
4154 br(Assembler::EQ, END);
4155 add(in, in, len, LSL, 2); // in[j+1] address
4156 add(offset, out, offset, LSL, 2); // out[offset + 1] address
4157 mov(out, zr); // used to keep carry now
4158 BIND(LOOP);
4159 ldrw(rscratch1, Address(pre(in, -4)));
4160 madd(rscratch1, rscratch1, k, out);
4161 ldrw(rscratch2, Address(pre(offset, -4)));
4162 add(rscratch1, rscratch1, rscratch2);
4163 strw(rscratch1, Address(offset));
4164 lsr(out, rscratch1, 32);
4165 subs(len, len, 1);
4166 br(Assembler::NE, LOOP);
4167 BIND(END);
4168 }
4169
4170 /**
4171 * Emits code to update CRC-32 with a byte value according to constants in table
4172 *
4173 * @param [in,out]crc Register containing the crc.
4174 * @param [in]val Register containing the byte to fold into the CRC.
4175 * @param [in]table Register containing the table of crc constants.
4176 *
4177 * uint32_t crc;
4178 * val = crc_table[(val ^ crc) & 0xFF];
4179 * crc = val ^ (crc >> 8);
4180 *
4181 */
4182 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
4183 eor(val, val, crc);
4184 andr(val, val, 0xff);
4185 ldrw(val, Address(table, val, Address::lsl(2)));
4186 eor(crc, val, crc, Assembler::LSR, 8);
4187 }
4188
4189 /**
4190 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
4191 *
4192 * @param [in,out]crc Register containing the crc.
4193 * @param [in]v Register containing the 32-bit to fold into the CRC.
4194 * @param [in]table0 Register containing table 0 of crc constants.
4195 * @param [in]table1 Register containing table 1 of crc constants.
4196 * @param [in]table2 Register containing table 2 of crc constants.
4197 * @param [in]table3 Register containing table 3 of crc constants.
4198 *
4199 * uint32_t crc;
4200 * v = crc ^ v
4201 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
4202 *
4203 */
4204 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
4205 Register table0, Register table1, Register table2, Register table3,
4206 bool upper) {
4207 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
4208 uxtb(tmp, v);
4209 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
4210 ubfx(tmp, v, 8, 8);
4211 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
4212 eor(crc, crc, tmp);
4213 ubfx(tmp, v, 16, 8);
4214 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
4215 eor(crc, crc, tmp);
4216 ubfx(tmp, v, 24, 8);
4217 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
4218 eor(crc, crc, tmp);
4219 }
4220
4221 void MacroAssembler::kernel_crc32_using_crypto_pmull(Register crc, Register buf,
4222 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4223 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4224 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4225
4226 subs(tmp0, len, 384);
4227 mvnw(crc, crc);
4228 br(Assembler::GE, CRC_by128_pre);
4229 BIND(CRC_less128);
4230 subs(len, len, 32);
4231 br(Assembler::GE, CRC_by32_loop);
4232 BIND(CRC_less32);
4233 adds(len, len, 32 - 4);
4234 br(Assembler::GE, CRC_by4_loop);
4235 adds(len, len, 4);
4236 br(Assembler::GT, CRC_by1_loop);
4237 b(L_exit);
4238
4239 BIND(CRC_by32_loop);
4240 ldp(tmp0, tmp1, Address(buf));
4241 crc32x(crc, crc, tmp0);
4242 ldp(tmp2, tmp3, Address(buf, 16));
4243 crc32x(crc, crc, tmp1);
4244 add(buf, buf, 32);
4245 crc32x(crc, crc, tmp2);
4246 subs(len, len, 32);
4247 crc32x(crc, crc, tmp3);
4248 br(Assembler::GE, CRC_by32_loop);
4249 cmn(len, (u1)32);
4250 br(Assembler::NE, CRC_less32);
4251 b(L_exit);
4252
4253 BIND(CRC_by4_loop);
4254 ldrw(tmp0, Address(post(buf, 4)));
4255 subs(len, len, 4);
4256 crc32w(crc, crc, tmp0);
4257 br(Assembler::GE, CRC_by4_loop);
4258 adds(len, len, 4);
4259 br(Assembler::LE, L_exit);
4260 BIND(CRC_by1_loop);
4261 ldrb(tmp0, Address(post(buf, 1)));
4262 subs(len, len, 1);
4263 crc32b(crc, crc, tmp0);
4264 br(Assembler::GT, CRC_by1_loop);
4265 b(L_exit);
4266
4267 BIND(CRC_by128_pre);
4268 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4269 4*256*sizeof(juint) + 8*sizeof(juint));
4270 mov(crc, 0);
4271 crc32x(crc, crc, tmp0);
4272 crc32x(crc, crc, tmp1);
4273
4274 cbnz(len, CRC_less128);
4275
4276 BIND(L_exit);
4277 mvnw(crc, crc);
4278 }
4279
4280 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf,
4281 Register len, Register tmp0, Register tmp1, Register tmp2,
4282 Register tmp3) {
4283 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4284 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4285
4286 mvnw(crc, crc);
4287
4288 subs(len, len, 128);
4289 br(Assembler::GE, CRC_by64_pre);
4290 BIND(CRC_less64);
4291 adds(len, len, 128-32);
4292 br(Assembler::GE, CRC_by32_loop);
4293 BIND(CRC_less32);
4294 adds(len, len, 32-4);
4295 br(Assembler::GE, CRC_by4_loop);
4296 adds(len, len, 4);
4297 br(Assembler::GT, CRC_by1_loop);
4298 b(L_exit);
4299
4300 BIND(CRC_by32_loop);
4301 ldp(tmp0, tmp1, Address(post(buf, 16)));
4302 subs(len, len, 32);
4303 crc32x(crc, crc, tmp0);
4304 ldr(tmp2, Address(post(buf, 8)));
4305 crc32x(crc, crc, tmp1);
4306 ldr(tmp3, Address(post(buf, 8)));
4307 crc32x(crc, crc, tmp2);
4308 crc32x(crc, crc, tmp3);
4309 br(Assembler::GE, CRC_by32_loop);
4310 cmn(len, (u1)32);
4311 br(Assembler::NE, CRC_less32);
4312 b(L_exit);
4313
4314 BIND(CRC_by4_loop);
4315 ldrw(tmp0, Address(post(buf, 4)));
4316 subs(len, len, 4);
4317 crc32w(crc, crc, tmp0);
4318 br(Assembler::GE, CRC_by4_loop);
4319 adds(len, len, 4);
4320 br(Assembler::LE, L_exit);
4321 BIND(CRC_by1_loop);
4322 ldrb(tmp0, Address(post(buf, 1)));
4323 subs(len, len, 1);
4324 crc32b(crc, crc, tmp0);
4325 br(Assembler::GT, CRC_by1_loop);
4326 b(L_exit);
4327
4328 BIND(CRC_by64_pre);
4329 sub(buf, buf, 8);
4330 ldp(tmp0, tmp1, Address(buf, 8));
4331 crc32x(crc, crc, tmp0);
4332 ldr(tmp2, Address(buf, 24));
4333 crc32x(crc, crc, tmp1);
4334 ldr(tmp3, Address(buf, 32));
4335 crc32x(crc, crc, tmp2);
4336 ldr(tmp0, Address(buf, 40));
4337 crc32x(crc, crc, tmp3);
4338 ldr(tmp1, Address(buf, 48));
4339 crc32x(crc, crc, tmp0);
4340 ldr(tmp2, Address(buf, 56));
4341 crc32x(crc, crc, tmp1);
4342 ldr(tmp3, Address(pre(buf, 64)));
4343
4344 b(CRC_by64_loop);
4345
4346 align(CodeEntryAlignment);
4347 BIND(CRC_by64_loop);
4348 subs(len, len, 64);
4349 crc32x(crc, crc, tmp2);
4350 ldr(tmp0, Address(buf, 8));
4351 crc32x(crc, crc, tmp3);
4352 ldr(tmp1, Address(buf, 16));
4353 crc32x(crc, crc, tmp0);
4354 ldr(tmp2, Address(buf, 24));
4355 crc32x(crc, crc, tmp1);
4356 ldr(tmp3, Address(buf, 32));
4357 crc32x(crc, crc, tmp2);
4358 ldr(tmp0, Address(buf, 40));
4359 crc32x(crc, crc, tmp3);
4360 ldr(tmp1, Address(buf, 48));
4361 crc32x(crc, crc, tmp0);
4362 ldr(tmp2, Address(buf, 56));
4363 crc32x(crc, crc, tmp1);
4364 ldr(tmp3, Address(pre(buf, 64)));
4365 br(Assembler::GE, CRC_by64_loop);
4366
4367 // post-loop
4368 crc32x(crc, crc, tmp2);
4369 crc32x(crc, crc, tmp3);
4370
4371 sub(len, len, 64);
4372 add(buf, buf, 8);
4373 cmn(len, (u1)128);
4374 br(Assembler::NE, CRC_less64);
4375 BIND(L_exit);
4376 mvnw(crc, crc);
4377 }
4378
4379 /**
4380 * @param crc register containing existing CRC (32-bit)
4381 * @param buf register pointing to input byte buffer (byte*)
4382 * @param len register containing number of bytes
4383 * @param table register that will contain address of CRC table
4384 * @param tmp scratch register
4385 */
4386 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
4387 Register table0, Register table1, Register table2, Register table3,
4388 Register tmp, Register tmp2, Register tmp3) {
4389 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
4390
4391 if (UseCryptoPmullForCRC32) {
4392 kernel_crc32_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4393 return;
4394 }
4395
4396 if (UseCRC32) {
4397 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
4398 return;
4399 }
4400
4401 mvnw(crc, crc);
4402
4403 {
4404 uint64_t offset;
4405 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4406 add(table0, table0, offset);
4407 }
4408 add(table1, table0, 1*256*sizeof(juint));
4409 add(table2, table0, 2*256*sizeof(juint));
4410 add(table3, table0, 3*256*sizeof(juint));
4411
4412 { // Neon code start
4413 cmp(len, (u1)64);
4414 br(Assembler::LT, L_by16);
4415 eor(v16, T16B, v16, v16);
4416
4417 Label L_fold;
4418
4419 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
4420
4421 ld1(v0, v1, T2D, post(buf, 32));
4422 ld1r(v4, T2D, post(tmp, 8));
4423 ld1r(v5, T2D, post(tmp, 8));
4424 ld1r(v6, T2D, post(tmp, 8));
4425 ld1r(v7, T2D, post(tmp, 8));
4426 mov(v16, S, 0, crc);
4427
4428 eor(v0, T16B, v0, v16);
4429 sub(len, len, 64);
4430
4431 BIND(L_fold);
4432 pmull(v22, T8H, v0, v5, T8B);
4433 pmull(v20, T8H, v0, v7, T8B);
4434 pmull(v23, T8H, v0, v4, T8B);
4435 pmull(v21, T8H, v0, v6, T8B);
4436
4437 pmull2(v18, T8H, v0, v5, T16B);
4438 pmull2(v16, T8H, v0, v7, T16B);
4439 pmull2(v19, T8H, v0, v4, T16B);
4440 pmull2(v17, T8H, v0, v6, T16B);
4441
4442 uzp1(v24, T8H, v20, v22);
4443 uzp2(v25, T8H, v20, v22);
4444 eor(v20, T16B, v24, v25);
4445
4446 uzp1(v26, T8H, v16, v18);
4447 uzp2(v27, T8H, v16, v18);
4448 eor(v16, T16B, v26, v27);
4449
4450 ushll2(v22, T4S, v20, T8H, 8);
4451 ushll(v20, T4S, v20, T4H, 8);
4452
4453 ushll2(v18, T4S, v16, T8H, 8);
4454 ushll(v16, T4S, v16, T4H, 8);
4455
4456 eor(v22, T16B, v23, v22);
4457 eor(v18, T16B, v19, v18);
4458 eor(v20, T16B, v21, v20);
4459 eor(v16, T16B, v17, v16);
4460
4461 uzp1(v17, T2D, v16, v20);
4462 uzp2(v21, T2D, v16, v20);
4463 eor(v17, T16B, v17, v21);
4464
4465 ushll2(v20, T2D, v17, T4S, 16);
4466 ushll(v16, T2D, v17, T2S, 16);
4467
4468 eor(v20, T16B, v20, v22);
4469 eor(v16, T16B, v16, v18);
4470
4471 uzp1(v17, T2D, v20, v16);
4472 uzp2(v21, T2D, v20, v16);
4473 eor(v28, T16B, v17, v21);
4474
4475 pmull(v22, T8H, v1, v5, T8B);
4476 pmull(v20, T8H, v1, v7, T8B);
4477 pmull(v23, T8H, v1, v4, T8B);
4478 pmull(v21, T8H, v1, v6, T8B);
4479
4480 pmull2(v18, T8H, v1, v5, T16B);
4481 pmull2(v16, T8H, v1, v7, T16B);
4482 pmull2(v19, T8H, v1, v4, T16B);
4483 pmull2(v17, T8H, v1, v6, T16B);
4484
4485 ld1(v0, v1, T2D, post(buf, 32));
4486
4487 uzp1(v24, T8H, v20, v22);
4488 uzp2(v25, T8H, v20, v22);
4489 eor(v20, T16B, v24, v25);
4490
4491 uzp1(v26, T8H, v16, v18);
4492 uzp2(v27, T8H, v16, v18);
4493 eor(v16, T16B, v26, v27);
4494
4495 ushll2(v22, T4S, v20, T8H, 8);
4496 ushll(v20, T4S, v20, T4H, 8);
4497
4498 ushll2(v18, T4S, v16, T8H, 8);
4499 ushll(v16, T4S, v16, T4H, 8);
4500
4501 eor(v22, T16B, v23, v22);
4502 eor(v18, T16B, v19, v18);
4503 eor(v20, T16B, v21, v20);
4504 eor(v16, T16B, v17, v16);
4505
4506 uzp1(v17, T2D, v16, v20);
4507 uzp2(v21, T2D, v16, v20);
4508 eor(v16, T16B, v17, v21);
4509
4510 ushll2(v20, T2D, v16, T4S, 16);
4511 ushll(v16, T2D, v16, T2S, 16);
4512
4513 eor(v20, T16B, v22, v20);
4514 eor(v16, T16B, v16, v18);
4515
4516 uzp1(v17, T2D, v20, v16);
4517 uzp2(v21, T2D, v20, v16);
4518 eor(v20, T16B, v17, v21);
4519
4520 shl(v16, T2D, v28, 1);
4521 shl(v17, T2D, v20, 1);
4522
4523 eor(v0, T16B, v0, v16);
4524 eor(v1, T16B, v1, v17);
4525
4526 subs(len, len, 32);
4527 br(Assembler::GE, L_fold);
4528
4529 mov(crc, 0);
4530 mov(tmp, v0, D, 0);
4531 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4532 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4533 mov(tmp, v0, D, 1);
4534 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4535 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4536 mov(tmp, v1, D, 0);
4537 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4538 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4539 mov(tmp, v1, D, 1);
4540 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4541 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4542
4543 add(len, len, 32);
4544 } // Neon code end
4545
4546 BIND(L_by16);
4547 subs(len, len, 16);
4548 br(Assembler::GE, L_by16_loop);
4549 adds(len, len, 16-4);
4550 br(Assembler::GE, L_by4_loop);
4551 adds(len, len, 4);
4552 br(Assembler::GT, L_by1_loop);
4553 b(L_exit);
4554
4555 BIND(L_by4_loop);
4556 ldrw(tmp, Address(post(buf, 4)));
4557 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
4558 subs(len, len, 4);
4559 br(Assembler::GE, L_by4_loop);
4560 adds(len, len, 4);
4561 br(Assembler::LE, L_exit);
4562 BIND(L_by1_loop);
4563 subs(len, len, 1);
4564 ldrb(tmp, Address(post(buf, 1)));
4565 update_byte_crc32(crc, tmp, table0);
4566 br(Assembler::GT, L_by1_loop);
4567 b(L_exit);
4568
4569 align(CodeEntryAlignment);
4570 BIND(L_by16_loop);
4571 subs(len, len, 16);
4572 ldp(tmp, tmp3, Address(post(buf, 16)));
4573 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4574 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4575 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
4576 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
4577 br(Assembler::GE, L_by16_loop);
4578 adds(len, len, 16-4);
4579 br(Assembler::GE, L_by4_loop);
4580 adds(len, len, 4);
4581 br(Assembler::GT, L_by1_loop);
4582 BIND(L_exit);
4583 mvnw(crc, crc);
4584 }
4585
4586 void MacroAssembler::kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
4587 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4588 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4589 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4590
4591 subs(tmp0, len, 384);
4592 br(Assembler::GE, CRC_by128_pre);
4593 BIND(CRC_less128);
4594 subs(len, len, 32);
4595 br(Assembler::GE, CRC_by32_loop);
4596 BIND(CRC_less32);
4597 adds(len, len, 32 - 4);
4598 br(Assembler::GE, CRC_by4_loop);
4599 adds(len, len, 4);
4600 br(Assembler::GT, CRC_by1_loop);
4601 b(L_exit);
4602
4603 BIND(CRC_by32_loop);
4604 ldp(tmp0, tmp1, Address(buf));
4605 crc32cx(crc, crc, tmp0);
4606 ldr(tmp2, Address(buf, 16));
4607 crc32cx(crc, crc, tmp1);
4608 ldr(tmp3, Address(buf, 24));
4609 crc32cx(crc, crc, tmp2);
4610 add(buf, buf, 32);
4611 subs(len, len, 32);
4612 crc32cx(crc, crc, tmp3);
4613 br(Assembler::GE, CRC_by32_loop);
4614 cmn(len, (u1)32);
4615 br(Assembler::NE, CRC_less32);
4616 b(L_exit);
4617
4618 BIND(CRC_by4_loop);
4619 ldrw(tmp0, Address(post(buf, 4)));
4620 subs(len, len, 4);
4621 crc32cw(crc, crc, tmp0);
4622 br(Assembler::GE, CRC_by4_loop);
4623 adds(len, len, 4);
4624 br(Assembler::LE, L_exit);
4625 BIND(CRC_by1_loop);
4626 ldrb(tmp0, Address(post(buf, 1)));
4627 subs(len, len, 1);
4628 crc32cb(crc, crc, tmp0);
4629 br(Assembler::GT, CRC_by1_loop);
4630 b(L_exit);
4631
4632 BIND(CRC_by128_pre);
4633 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4634 4*256*sizeof(juint) + 8*sizeof(juint) + 0x50);
4635 mov(crc, 0);
4636 crc32cx(crc, crc, tmp0);
4637 crc32cx(crc, crc, tmp1);
4638
4639 cbnz(len, CRC_less128);
4640
4641 BIND(L_exit);
4642 }
4643
4644 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf,
4645 Register len, Register tmp0, Register tmp1, Register tmp2,
4646 Register tmp3) {
4647 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4648 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4649
4650 subs(len, len, 128);
4651 br(Assembler::GE, CRC_by64_pre);
4652 BIND(CRC_less64);
4653 adds(len, len, 128-32);
4654 br(Assembler::GE, CRC_by32_loop);
4655 BIND(CRC_less32);
4656 adds(len, len, 32-4);
4657 br(Assembler::GE, CRC_by4_loop);
4658 adds(len, len, 4);
4659 br(Assembler::GT, CRC_by1_loop);
4660 b(L_exit);
4661
4662 BIND(CRC_by32_loop);
4663 ldp(tmp0, tmp1, Address(post(buf, 16)));
4664 subs(len, len, 32);
4665 crc32cx(crc, crc, tmp0);
4666 ldr(tmp2, Address(post(buf, 8)));
4667 crc32cx(crc, crc, tmp1);
4668 ldr(tmp3, Address(post(buf, 8)));
4669 crc32cx(crc, crc, tmp2);
4670 crc32cx(crc, crc, tmp3);
4671 br(Assembler::GE, CRC_by32_loop);
4672 cmn(len, (u1)32);
4673 br(Assembler::NE, CRC_less32);
4674 b(L_exit);
4675
4676 BIND(CRC_by4_loop);
4677 ldrw(tmp0, Address(post(buf, 4)));
4678 subs(len, len, 4);
4679 crc32cw(crc, crc, tmp0);
4680 br(Assembler::GE, CRC_by4_loop);
4681 adds(len, len, 4);
4682 br(Assembler::LE, L_exit);
4683 BIND(CRC_by1_loop);
4684 ldrb(tmp0, Address(post(buf, 1)));
4685 subs(len, len, 1);
4686 crc32cb(crc, crc, tmp0);
4687 br(Assembler::GT, CRC_by1_loop);
4688 b(L_exit);
4689
4690 BIND(CRC_by64_pre);
4691 sub(buf, buf, 8);
4692 ldp(tmp0, tmp1, Address(buf, 8));
4693 crc32cx(crc, crc, tmp0);
4694 ldr(tmp2, Address(buf, 24));
4695 crc32cx(crc, crc, tmp1);
4696 ldr(tmp3, Address(buf, 32));
4697 crc32cx(crc, crc, tmp2);
4698 ldr(tmp0, Address(buf, 40));
4699 crc32cx(crc, crc, tmp3);
4700 ldr(tmp1, Address(buf, 48));
4701 crc32cx(crc, crc, tmp0);
4702 ldr(tmp2, Address(buf, 56));
4703 crc32cx(crc, crc, tmp1);
4704 ldr(tmp3, Address(pre(buf, 64)));
4705
4706 b(CRC_by64_loop);
4707
4708 align(CodeEntryAlignment);
4709 BIND(CRC_by64_loop);
4710 subs(len, len, 64);
4711 crc32cx(crc, crc, tmp2);
4712 ldr(tmp0, Address(buf, 8));
4713 crc32cx(crc, crc, tmp3);
4714 ldr(tmp1, Address(buf, 16));
4715 crc32cx(crc, crc, tmp0);
4716 ldr(tmp2, Address(buf, 24));
4717 crc32cx(crc, crc, tmp1);
4718 ldr(tmp3, Address(buf, 32));
4719 crc32cx(crc, crc, tmp2);
4720 ldr(tmp0, Address(buf, 40));
4721 crc32cx(crc, crc, tmp3);
4722 ldr(tmp1, Address(buf, 48));
4723 crc32cx(crc, crc, tmp0);
4724 ldr(tmp2, Address(buf, 56));
4725 crc32cx(crc, crc, tmp1);
4726 ldr(tmp3, Address(pre(buf, 64)));
4727 br(Assembler::GE, CRC_by64_loop);
4728
4729 // post-loop
4730 crc32cx(crc, crc, tmp2);
4731 crc32cx(crc, crc, tmp3);
4732
4733 sub(len, len, 64);
4734 add(buf, buf, 8);
4735 cmn(len, (u1)128);
4736 br(Assembler::NE, CRC_less64);
4737 BIND(L_exit);
4738 }
4739
4740 /**
4741 * @param crc register containing existing CRC (32-bit)
4742 * @param buf register pointing to input byte buffer (byte*)
4743 * @param len register containing number of bytes
4744 * @param table register that will contain address of CRC table
4745 * @param tmp scratch register
4746 */
4747 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
4748 Register table0, Register table1, Register table2, Register table3,
4749 Register tmp, Register tmp2, Register tmp3) {
4750 if (UseCryptoPmullForCRC32) {
4751 kernel_crc32c_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4752 } else {
4753 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3);
4754 }
4755 }
4756
4757 void MacroAssembler::kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
4758 Register len, Register tmp0, Register tmp1, Register tmp2, size_t table_offset) {
4759 Label CRC_by128_loop;
4760 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4761
4762 sub(len, len, 256);
4763 Register table = tmp0;
4764 {
4765 uint64_t offset;
4766 adrp(table, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4767 add(table, table, offset);
4768 }
4769 add(table, table, table_offset);
4770
4771 // Registers v0..v7 are used as data registers.
4772 // Registers v16..v31 are used as tmp registers.
4773 sub(buf, buf, 0x10);
4774 ldrq(v0, Address(buf, 0x10));
4775 ldrq(v1, Address(buf, 0x20));
4776 ldrq(v2, Address(buf, 0x30));
4777 ldrq(v3, Address(buf, 0x40));
4778 ldrq(v4, Address(buf, 0x50));
4779 ldrq(v5, Address(buf, 0x60));
4780 ldrq(v6, Address(buf, 0x70));
4781 ldrq(v7, Address(pre(buf, 0x80)));
4782
4783 movi(v31, T4S, 0);
4784 mov(v31, S, 0, crc);
4785 eor(v0, T16B, v0, v31);
4786
4787 // Register v16 contains constants from the crc table.
4788 ldrq(v16, Address(table));
4789 b(CRC_by128_loop);
4790
4791 align(OptoLoopAlignment);
4792 BIND(CRC_by128_loop);
4793 pmull (v17, T1Q, v0, v16, T1D);
4794 pmull2(v18, T1Q, v0, v16, T2D);
4795 ldrq(v0, Address(buf, 0x10));
4796 eor3(v0, T16B, v17, v18, v0);
4797
4798 pmull (v19, T1Q, v1, v16, T1D);
4799 pmull2(v20, T1Q, v1, v16, T2D);
4800 ldrq(v1, Address(buf, 0x20));
4801 eor3(v1, T16B, v19, v20, v1);
4802
4803 pmull (v21, T1Q, v2, v16, T1D);
4804 pmull2(v22, T1Q, v2, v16, T2D);
4805 ldrq(v2, Address(buf, 0x30));
4806 eor3(v2, T16B, v21, v22, v2);
4807
4808 pmull (v23, T1Q, v3, v16, T1D);
4809 pmull2(v24, T1Q, v3, v16, T2D);
4810 ldrq(v3, Address(buf, 0x40));
4811 eor3(v3, T16B, v23, v24, v3);
4812
4813 pmull (v25, T1Q, v4, v16, T1D);
4814 pmull2(v26, T1Q, v4, v16, T2D);
4815 ldrq(v4, Address(buf, 0x50));
4816 eor3(v4, T16B, v25, v26, v4);
4817
4818 pmull (v27, T1Q, v5, v16, T1D);
4819 pmull2(v28, T1Q, v5, v16, T2D);
4820 ldrq(v5, Address(buf, 0x60));
4821 eor3(v5, T16B, v27, v28, v5);
4822
4823 pmull (v29, T1Q, v6, v16, T1D);
4824 pmull2(v30, T1Q, v6, v16, T2D);
4825 ldrq(v6, Address(buf, 0x70));
4826 eor3(v6, T16B, v29, v30, v6);
4827
4828 // Reuse registers v23, v24.
4829 // Using them won't block the first instruction of the next iteration.
4830 pmull (v23, T1Q, v7, v16, T1D);
4831 pmull2(v24, T1Q, v7, v16, T2D);
4832 ldrq(v7, Address(pre(buf, 0x80)));
4833 eor3(v7, T16B, v23, v24, v7);
4834
4835 subs(len, len, 0x80);
4836 br(Assembler::GE, CRC_by128_loop);
4837
4838 // fold into 512 bits
4839 // Use v31 for constants because v16 can be still in use.
4840 ldrq(v31, Address(table, 0x10));
4841
4842 pmull (v17, T1Q, v0, v31, T1D);
4843 pmull2(v18, T1Q, v0, v31, T2D);
4844 eor3(v0, T16B, v17, v18, v4);
4845
4846 pmull (v19, T1Q, v1, v31, T1D);
4847 pmull2(v20, T1Q, v1, v31, T2D);
4848 eor3(v1, T16B, v19, v20, v5);
4849
4850 pmull (v21, T1Q, v2, v31, T1D);
4851 pmull2(v22, T1Q, v2, v31, T2D);
4852 eor3(v2, T16B, v21, v22, v6);
4853
4854 pmull (v23, T1Q, v3, v31, T1D);
4855 pmull2(v24, T1Q, v3, v31, T2D);
4856 eor3(v3, T16B, v23, v24, v7);
4857
4858 // fold into 128 bits
4859 // Use v17 for constants because v31 can be still in use.
4860 ldrq(v17, Address(table, 0x20));
4861 pmull (v25, T1Q, v0, v17, T1D);
4862 pmull2(v26, T1Q, v0, v17, T2D);
4863 eor3(v3, T16B, v3, v25, v26);
4864
4865 // Use v18 for constants because v17 can be still in use.
4866 ldrq(v18, Address(table, 0x30));
4867 pmull (v27, T1Q, v1, v18, T1D);
4868 pmull2(v28, T1Q, v1, v18, T2D);
4869 eor3(v3, T16B, v3, v27, v28);
4870
4871 // Use v19 for constants because v18 can be still in use.
4872 ldrq(v19, Address(table, 0x40));
4873 pmull (v29, T1Q, v2, v19, T1D);
4874 pmull2(v30, T1Q, v2, v19, T2D);
4875 eor3(v0, T16B, v3, v29, v30);
4876
4877 add(len, len, 0x80);
4878 add(buf, buf, 0x10);
4879
4880 mov(tmp0, v0, D, 0);
4881 mov(tmp1, v0, D, 1);
4882 }
4883
4884 void MacroAssembler::addptr(const Address &dst, int32_t src) {
4885 Address adr;
4886 switch(dst.getMode()) {
4887 case Address::base_plus_offset:
4888 // This is the expected mode, although we allow all the other
4889 // forms below.
4890 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
4891 break;
4892 default:
4893 lea(rscratch2, dst);
4894 adr = Address(rscratch2);
4895 break;
4896 }
4897 ldr(rscratch1, adr);
4898 add(rscratch1, rscratch1, src);
4899 str(rscratch1, adr);
4900 }
4901
4902 void MacroAssembler::cmpptr(Register src1, Address src2) {
4903 uint64_t offset;
4904 adrp(rscratch1, src2, offset);
4905 ldr(rscratch1, Address(rscratch1, offset));
4906 cmp(src1, rscratch1);
4907 }
4908
4909 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
4910 cmp(obj1, obj2);
4911 }
4912
4913 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4914 load_method_holder(rresult, rmethod);
4915 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4916 }
4917
4918 void MacroAssembler::load_method_holder(Register holder, Register method) {
4919 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
4920 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
4921 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
4922 }
4923
4924 // Loads the obj's Klass* into dst.
4925 // Preserves all registers (incl src, rscratch1 and rscratch2).
4926 // Input:
4927 // src - the oop we want to load the klass from.
4928 // dst - output narrow klass.
4929 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
4930 assert(UseCompactObjectHeaders, "expects UseCompactObjectHeaders");
4931 ldr(dst, Address(src, oopDesc::mark_offset_in_bytes()));
4932 lsr(dst, dst, markWord::klass_shift);
4933 }
4934
4935 void MacroAssembler::load_klass(Register dst, Register src) {
4936 if (UseCompactObjectHeaders) {
4937 load_narrow_klass_compact(dst, src);
4938 decode_klass_not_null(dst);
4939 } else if (UseCompressedClassPointers) {
4940 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4941 decode_klass_not_null(dst);
4942 } else {
4943 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4944 }
4945 }
4946
4947 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
4948 if (RestoreMXCSROnJNICalls) {
4949 Label OK;
4950 get_fpcr(tmp1);
4951 mov(tmp2, tmp1);
4952 // Set FPCR to the state we need. We do want Round to Nearest. We
4953 // don't want non-IEEE rounding modes or floating-point traps.
4954 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
4955 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
4956 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
4957 eor(tmp2, tmp1, tmp2);
4958 cbz(tmp2, OK); // Only reset FPCR if it's wrong
4959 set_fpcr(tmp1);
4960 bind(OK);
4961 }
4962 }
4963
4964 // ((OopHandle)result).resolve();
4965 void MacroAssembler::resolve_oop_handle(Register result, Register tmp1, Register tmp2) {
4966 // OopHandle::resolve is an indirection.
4967 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp1, tmp2);
4968 }
4969
4970 // ((WeakHandle)result).resolve();
4971 void MacroAssembler::resolve_weak_handle(Register result, Register tmp1, Register tmp2) {
4972 assert_different_registers(result, tmp1, tmp2);
4973 Label resolved;
4974
4975 // A null weak handle resolves to null.
4976 cbz(result, resolved);
4977
4978 // Only 64 bit platforms support GCs that require a tmp register
4979 // WeakHandle::resolve is an indirection like jweak.
4980 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4981 result, Address(result), tmp1, tmp2);
4982 bind(resolved);
4983 }
4984
4985 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp1, Register tmp2) {
4986 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
4987 ldr(dst, Address(rmethod, Method::const_offset()));
4988 ldr(dst, Address(dst, ConstMethod::constants_offset()));
4989 ldr(dst, Address(dst, ConstantPool::pool_holder_offset()));
4990 ldr(dst, Address(dst, mirror_offset));
4991 resolve_oop_handle(dst, tmp1, tmp2);
4992 }
4993
4994 void MacroAssembler::cmp_klass(Register obj, Register klass, Register tmp) {
4995 assert_different_registers(obj, klass, tmp);
4996 if (UseCompressedClassPointers) {
4997 if (UseCompactObjectHeaders) {
4998 load_narrow_klass_compact(tmp, obj);
4999 } else {
5000 ldrw(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5001 }
5002 if (CompressedKlassPointers::base() == nullptr) {
5003 cmp(klass, tmp, LSL, CompressedKlassPointers::shift());
5004 return;
5005 } else if (!AOTCodeCache::is_on_for_dump() &&
5006 ((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
5007 && CompressedKlassPointers::shift() == 0) {
5008 // Only the bottom 32 bits matter
5009 cmpw(klass, tmp);
5010 return;
5011 }
5012 decode_klass_not_null(tmp);
5013 } else {
5014 ldr(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5015 }
5016 cmp(klass, tmp);
5017 }
5018
5019 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5020 if (UseCompactObjectHeaders) {
5021 load_narrow_klass_compact(tmp1, obj1);
5022 load_narrow_klass_compact(tmp2, obj2);
5023 cmpw(tmp1, tmp2);
5024 } else if (UseCompressedClassPointers) {
5025 ldrw(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5026 ldrw(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5027 cmpw(tmp1, tmp2);
5028 } else {
5029 ldr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5030 ldr(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5031 cmp(tmp1, tmp2);
5032 }
5033 }
5034
5035 void MacroAssembler::store_klass(Register dst, Register src) {
5036 // FIXME: Should this be a store release? concurrent gcs assumes
5037 // klass length is valid if klass field is not null.
5038 assert(!UseCompactObjectHeaders, "not with compact headers");
5039 if (UseCompressedClassPointers) {
5040 encode_klass_not_null(src);
5041 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5042 } else {
5043 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5044 }
5045 }
5046
5047 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5048 assert(!UseCompactObjectHeaders, "not with compact headers");
5049 if (UseCompressedClassPointers) {
5050 // Store to klass gap in destination
5051 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
5052 }
5053 }
5054
5055 // Algorithm must match CompressedOops::encode.
5056 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5057 #ifdef ASSERT
5058 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5059 #endif
5060 verify_oop_msg(s, "broken oop in encode_heap_oop");
5061 if (CompressedOops::base() == nullptr) {
5062 if (CompressedOops::shift() != 0) {
5063 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5064 lsr(d, s, LogMinObjAlignmentInBytes);
5065 } else {
5066 mov(d, s);
5067 }
5068 } else {
5069 subs(d, s, rheapbase);
5070 csel(d, d, zr, Assembler::HS);
5071 lsr(d, d, LogMinObjAlignmentInBytes);
5072
5073 /* Old algorithm: is this any worse?
5074 Label nonnull;
5075 cbnz(r, nonnull);
5076 sub(r, r, rheapbase);
5077 bind(nonnull);
5078 lsr(r, r, LogMinObjAlignmentInBytes);
5079 */
5080 }
5081 }
5082
5083 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5084 #ifdef ASSERT
5085 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5086 if (CheckCompressedOops) {
5087 Label ok;
5088 cbnz(r, ok);
5089 stop("null oop passed to encode_heap_oop_not_null");
5090 bind(ok);
5091 }
5092 #endif
5093 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5094 if (CompressedOops::base() != nullptr) {
5095 sub(r, r, rheapbase);
5096 }
5097 if (CompressedOops::shift() != 0) {
5098 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5099 lsr(r, r, LogMinObjAlignmentInBytes);
5100 }
5101 }
5102
5103 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5104 #ifdef ASSERT
5105 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5106 if (CheckCompressedOops) {
5107 Label ok;
5108 cbnz(src, ok);
5109 stop("null oop passed to encode_heap_oop_not_null2");
5110 bind(ok);
5111 }
5112 #endif
5113 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5114
5115 Register data = src;
5116 if (CompressedOops::base() != nullptr) {
5117 sub(dst, src, rheapbase);
5118 data = dst;
5119 }
5120 if (CompressedOops::shift() != 0) {
5121 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5122 lsr(dst, data, LogMinObjAlignmentInBytes);
5123 data = dst;
5124 }
5125 if (data == src)
5126 mov(dst, src);
5127 }
5128
5129 void MacroAssembler::decode_heap_oop(Register d, Register s) {
5130 #ifdef ASSERT
5131 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5132 #endif
5133 if (CompressedOops::base() == nullptr) {
5134 if (CompressedOops::shift() != 0) {
5135 lsl(d, s, CompressedOops::shift());
5136 } else if (d != s) {
5137 mov(d, s);
5138 }
5139 } else {
5140 Label done;
5141 if (d != s)
5142 mov(d, s);
5143 cbz(s, done);
5144 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
5145 bind(done);
5146 }
5147 verify_oop_msg(d, "broken oop in decode_heap_oop");
5148 }
5149
5150 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5151 assert (UseCompressedOops, "should only be used for compressed headers");
5152 assert (Universe::heap() != nullptr, "java heap should be initialized");
5153 // Cannot assert, unverified entry point counts instructions (see .ad file)
5154 // vtableStubs also counts instructions in pd_code_size_limit.
5155 // Also do not verify_oop as this is called by verify_oop.
5156 if (CompressedOops::shift() != 0) {
5157 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5158 if (CompressedOops::base() != nullptr) {
5159 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5160 } else {
5161 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5162 }
5163 } else {
5164 assert (CompressedOops::base() == nullptr, "sanity");
5165 }
5166 }
5167
5168 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5169 assert (UseCompressedOops, "should only be used for compressed headers");
5170 assert (Universe::heap() != nullptr, "java heap should be initialized");
5171 // Cannot assert, unverified entry point counts instructions (see .ad file)
5172 // vtableStubs also counts instructions in pd_code_size_limit.
5173 // Also do not verify_oop as this is called by verify_oop.
5174 if (CompressedOops::shift() != 0) {
5175 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5176 if (CompressedOops::base() != nullptr) {
5177 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5178 } else {
5179 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5180 }
5181 } else {
5182 assert (CompressedOops::base() == nullptr, "sanity");
5183 if (dst != src) {
5184 mov(dst, src);
5185 }
5186 }
5187 }
5188
5189 MacroAssembler::KlassDecodeMode MacroAssembler::_klass_decode_mode(KlassDecodeNone);
5190
5191 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() {
5192 assert(Metaspace::initialized(), "metaspace not initialized yet");
5193 assert(_klass_decode_mode != KlassDecodeNone, "should be initialized");
5194 return _klass_decode_mode;
5195 }
5196
5197 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode(address base, int shift, const size_t range) {
5198 assert(UseCompressedClassPointers, "not using compressed class pointers");
5199
5200 // KlassDecodeMode shouldn't be set already.
5201 assert(_klass_decode_mode == KlassDecodeNone, "set once");
5202
5203 if (base == nullptr) {
5204 return KlassDecodeZero;
5205 }
5206
5207 if (operand_valid_for_logical_immediate(
5208 /*is32*/false, (uint64_t)base)) {
5209 const uint64_t range_mask = right_n_bits(log2i_ceil(range));
5210 if (((uint64_t)base & range_mask) == 0) {
5211 return KlassDecodeXor;
5212 }
5213 }
5214
5215 const uint64_t shifted_base =
5216 (uint64_t)base >> shift;
5217 if ((shifted_base & 0xffff0000ffffffff) == 0) {
5218 return KlassDecodeMovk;
5219 }
5220
5221 // No valid encoding.
5222 return KlassDecodeNone;
5223 }
5224
5225 // Check if one of the above decoding modes will work for given base, shift and range.
5226 bool MacroAssembler::check_klass_decode_mode(address base, int shift, const size_t range) {
5227 return klass_decode_mode(base, shift, range) != KlassDecodeNone;
5228 }
5229
5230 bool MacroAssembler::set_klass_decode_mode(address base, int shift, const size_t range) {
5231 _klass_decode_mode = klass_decode_mode(base, shift, range);
5232 return _klass_decode_mode != KlassDecodeNone;
5233 }
5234
5235 static Register pick_different_tmp(Register dst, Register src) {
5236 auto tmps = RegSet::of(r0, r1, r2) - RegSet::of(src, dst);
5237 return *tmps.begin();
5238 }
5239
5240 void MacroAssembler::encode_klass_not_null_for_aot(Register dst, Register src) {
5241 // we have to load the klass base from the AOT constants area but
5242 // not the shift because it is not allowed to change
5243 int shift = CompressedKlassPointers::shift();
5244 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5245 if (dst != src) {
5246 // we can load the base into dst, subtract it formthe src and shift down
5247 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5248 ldr(dst, dst);
5249 sub(dst, src, dst);
5250 lsr(dst, dst, shift);
5251 } else {
5252 // we need an extra register in order to load the coop base
5253 Register tmp = pick_different_tmp(dst, src);
5254 RegSet regs = RegSet::of(tmp);
5255 push(regs, sp);
5256 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5257 ldr(tmp, tmp);
5258 sub(dst, src, tmp);
5259 lsr(dst, dst, shift);
5260 pop(regs, sp);
5261 }
5262 }
5263
5264 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5265 if (CompressedKlassPointers::base() != nullptr && AOTCodeCache::is_on_for_dump()) {
5266 encode_klass_not_null_for_aot(dst, src);
5267 return;
5268 }
5269
5270 switch (klass_decode_mode()) {
5271 case KlassDecodeZero:
5272 if (CompressedKlassPointers::shift() != 0) {
5273 lsr(dst, src, CompressedKlassPointers::shift());
5274 } else {
5275 if (dst != src) mov(dst, src);
5276 }
5277 break;
5278
5279 case KlassDecodeXor:
5280 if (CompressedKlassPointers::shift() != 0) {
5281 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5282 lsr(dst, dst, CompressedKlassPointers::shift());
5283 } else {
5284 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5285 }
5286 break;
5287
5288 case KlassDecodeMovk:
5289 if (CompressedKlassPointers::shift() != 0) {
5290 ubfx(dst, src, CompressedKlassPointers::shift(), 32);
5291 } else {
5292 movw(dst, src);
5293 }
5294 break;
5295
5296 case KlassDecodeNone:
5297 ShouldNotReachHere();
5298 break;
5299 }
5300 }
5301
5302 void MacroAssembler::encode_klass_not_null(Register r) {
5303 encode_klass_not_null(r, r);
5304 }
5305
5306 void MacroAssembler::decode_klass_not_null_for_aot(Register dst, Register src) {
5307 // we have to load the klass base from the AOT constants area but
5308 // not the shift because it is not allowed to change
5309 int shift = CompressedKlassPointers::shift();
5310 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5311 if (dst != src) {
5312 // we can load the base into dst then add the offset with a suitable shift
5313 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5314 ldr(dst, dst);
5315 add(dst, dst, src, LSL, shift);
5316 } else {
5317 // we need an extra register in order to load the coop base
5318 Register tmp = pick_different_tmp(dst, src);
5319 RegSet regs = RegSet::of(tmp);
5320 push(regs, sp);
5321 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5322 ldr(tmp, tmp);
5323 add(dst, tmp, src, LSL, shift);
5324 pop(regs, sp);
5325 }
5326 }
5327
5328 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5329 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5330
5331 if (CompressedKlassPointers::base() != nullptr && AOTCodeCache::is_on_for_dump()) {
5332 decode_klass_not_null_for_aot(dst, src);
5333 return;
5334 }
5335
5336 switch (klass_decode_mode()) {
5337 case KlassDecodeZero:
5338 if (CompressedKlassPointers::shift() != 0) {
5339 lsl(dst, src, CompressedKlassPointers::shift());
5340 } else {
5341 if (dst != src) mov(dst, src);
5342 }
5343 break;
5344
5345 case KlassDecodeXor:
5346 if (CompressedKlassPointers::shift() != 0) {
5347 lsl(dst, src, CompressedKlassPointers::shift());
5348 eor(dst, dst, (uint64_t)CompressedKlassPointers::base());
5349 } else {
5350 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5351 }
5352 break;
5353
5354 case KlassDecodeMovk: {
5355 const uint64_t shifted_base =
5356 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5357
5358 if (dst != src) movw(dst, src);
5359 movk(dst, shifted_base >> 32, 32);
5360
5361 if (CompressedKlassPointers::shift() != 0) {
5362 lsl(dst, dst, CompressedKlassPointers::shift());
5363 }
5364
5365 break;
5366 }
5367
5368 case KlassDecodeNone:
5369 ShouldNotReachHere();
5370 break;
5371 }
5372 }
5373
5374 void MacroAssembler::decode_klass_not_null(Register r) {
5375 decode_klass_not_null(r, r);
5376 }
5377
5378 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5379 #ifdef ASSERT
5380 {
5381 ThreadInVMfromUnknown tiv;
5382 assert (UseCompressedOops, "should only be used for compressed oops");
5383 assert (Universe::heap() != nullptr, "java heap should be initialized");
5384 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5385 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5386 }
5387 #endif
5388 int oop_index = oop_recorder()->find_index(obj);
5389 InstructionMark im(this);
5390 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5391 code_section()->relocate(inst_mark(), rspec);
5392 movz(dst, 0xDEAD, 16);
5393 movk(dst, 0xBEEF);
5394 }
5395
5396 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5397 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5398 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5399 int index = oop_recorder()->find_index(k);
5400 assert(! Universe::heap()->is_in(k), "should not be an oop");
5401
5402 InstructionMark im(this);
5403 RelocationHolder rspec = metadata_Relocation::spec(index);
5404 code_section()->relocate(inst_mark(), rspec);
5405 narrowKlass nk = CompressedKlassPointers::encode(k);
5406 movz(dst, (nk >> 16), 16);
5407 movk(dst, nk & 0xffff);
5408 }
5409
5410 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
5411 Register dst, Address src,
5412 Register tmp1, Register tmp2) {
5413 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5414 decorators = AccessInternal::decorator_fixup(decorators, type);
5415 bool as_raw = (decorators & AS_RAW) != 0;
5416 if (as_raw) {
5417 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5418 } else {
5419 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5420 }
5421 }
5422
5423 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5424 Address dst, Register val,
5425 Register tmp1, Register tmp2, Register tmp3) {
5426 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5427 decorators = AccessInternal::decorator_fixup(decorators, type);
5428 bool as_raw = (decorators & AS_RAW) != 0;
5429 if (as_raw) {
5430 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5431 } else {
5432 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5433 }
5434 }
5435
5436 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5437 Register tmp2, DecoratorSet decorators) {
5438 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5439 }
5440
5441 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5442 Register tmp2, DecoratorSet decorators) {
5443 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5444 }
5445
5446 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5447 Register tmp2, Register tmp3, DecoratorSet decorators) {
5448 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5449 }
5450
5451 // Used for storing nulls.
5452 void MacroAssembler::store_heap_oop_null(Address dst) {
5453 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5454 }
5455
5456 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
5457 assert(oop_recorder() != nullptr, "this assembler needs a Recorder");
5458 int index = oop_recorder()->allocate_metadata_index(obj);
5459 RelocationHolder rspec = metadata_Relocation::spec(index);
5460 return Address((address)obj, rspec);
5461 }
5462
5463 // Move an oop into a register.
5464 void MacroAssembler::movoop(Register dst, jobject obj) {
5465 int oop_index;
5466 if (obj == nullptr) {
5467 oop_index = oop_recorder()->allocate_oop_index(obj);
5468 } else {
5469 #ifdef ASSERT
5470 {
5471 ThreadInVMfromUnknown tiv;
5472 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5473 }
5474 #endif
5475 oop_index = oop_recorder()->find_index(obj);
5476 }
5477 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5478
5479 if (BarrierSet::barrier_set()->barrier_set_assembler()->supports_instruction_patching()) {
5480 mov(dst, Address((address)obj, rspec));
5481 } else {
5482 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
5483 ldr(dst, Address(dummy, rspec));
5484 }
5485 }
5486
5487 // Move a metadata address into a register.
5488 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
5489 int oop_index;
5490 if (obj == nullptr) {
5491 oop_index = oop_recorder()->allocate_metadata_index(obj);
5492 } else {
5493 oop_index = oop_recorder()->find_index(obj);
5494 }
5495 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5496 mov(dst, Address((address)obj, rspec));
5497 }
5498
5499 Address MacroAssembler::constant_oop_address(jobject obj) {
5500 #ifdef ASSERT
5501 {
5502 ThreadInVMfromUnknown tiv;
5503 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5504 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5505 }
5506 #endif
5507 int oop_index = oop_recorder()->find_index(obj);
5508 return Address((address)obj, oop_Relocation::spec(oop_index));
5509 }
5510
5511 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5512 void MacroAssembler::tlab_allocate(Register obj,
5513 Register var_size_in_bytes,
5514 int con_size_in_bytes,
5515 Register t1,
5516 Register t2,
5517 Label& slow_case) {
5518 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5519 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5520 }
5521
5522 void MacroAssembler::verify_tlab() {
5523 #ifdef ASSERT
5524 if (UseTLAB && VerifyOops) {
5525 Label next, ok;
5526
5527 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5528
5529 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5530 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5531 cmp(rscratch2, rscratch1);
5532 br(Assembler::HS, next);
5533 STOP("assert(top >= start)");
5534 should_not_reach_here();
5535
5536 bind(next);
5537 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5538 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5539 cmp(rscratch2, rscratch1);
5540 br(Assembler::HS, ok);
5541 STOP("assert(top <= end)");
5542 should_not_reach_here();
5543
5544 bind(ok);
5545 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5546 }
5547 #endif
5548 }
5549
5550 // Writes to stack successive pages until offset reached to check for
5551 // stack overflow + shadow pages. This clobbers tmp.
5552 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5553 assert_different_registers(tmp, size, rscratch1);
5554 mov(tmp, sp);
5555 // Bang stack for total size given plus shadow page size.
5556 // Bang one page at a time because large size can bang beyond yellow and
5557 // red zones.
5558 Label loop;
5559 mov(rscratch1, (int)os::vm_page_size());
5560 bind(loop);
5561 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5562 subsw(size, size, rscratch1);
5563 str(size, Address(tmp));
5564 br(Assembler::GT, loop);
5565
5566 // Bang down shadow pages too.
5567 // At this point, (tmp-0) is the last address touched, so don't
5568 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5569 // was post-decremented.) Skip this address by starting at i=1, and
5570 // touch a few more pages below. N.B. It is important to touch all
5571 // the way down to and including i=StackShadowPages.
5572 for (int i = 0; i < (int)(StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()) - 1; i++) {
5573 // this could be any sized move but this is can be a debugging crumb
5574 // so the bigger the better.
5575 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5576 str(size, Address(tmp));
5577 }
5578 }
5579
5580 // Move the address of the polling page into dest.
5581 void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype) {
5582 ldr(dest, Address(rthread, JavaThread::polling_page_offset()));
5583 }
5584
5585 // Read the polling page. The address of the polling page must
5586 // already be in r.
5587 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
5588 address mark;
5589 {
5590 InstructionMark im(this);
5591 code_section()->relocate(inst_mark(), rtype);
5592 ldrw(zr, Address(r, 0));
5593 mark = inst_mark();
5594 }
5595 verify_cross_modify_fence_not_required();
5596 return mark;
5597 }
5598
5599 void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
5600 relocInfo::relocType rtype = dest.rspec().reloc()->type();
5601 uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12;
5602 uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12;
5603 uint64_t dest_page = (uint64_t)dest.target() >> 12;
5604 int64_t offset_low = dest_page - low_page;
5605 int64_t offset_high = dest_page - high_page;
5606
5607 assert(is_valid_AArch64_address(dest.target()), "bad address");
5608 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
5609
5610 InstructionMark im(this);
5611 code_section()->relocate(inst_mark(), dest.rspec());
5612 // 8143067: Ensure that the adrp can reach the dest from anywhere within
5613 // the code cache so that if it is relocated we know it will still reach
5614 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
5615 _adrp(reg1, dest.target());
5616 } else {
5617 uint64_t target = (uint64_t)dest.target();
5618 uint64_t adrp_target
5619 = (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL);
5620
5621 _adrp(reg1, (address)adrp_target);
5622 movk(reg1, target >> 32, 32);
5623 }
5624 byte_offset = (uint64_t)dest.target() & 0xfff;
5625 }
5626
5627 void MacroAssembler::load_byte_map_base(Register reg) {
5628 #if INCLUDE_CDS
5629 if (AOTCodeCache::is_on_for_dump()) {
5630 address byte_map_base_adr = AOTRuntimeConstants::card_table_address();
5631 lea(reg, ExternalAddress(byte_map_base_adr));
5632 ldr(reg, Address(reg));
5633 return;
5634 }
5635 #endif
5636 CardTable::CardValue* byte_map_base =
5637 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base();
5638
5639 // Strictly speaking the byte_map_base isn't an address at all, and it might
5640 // even be negative. It is thus materialised as a constant.
5641 mov(reg, (uint64_t)byte_map_base);
5642 }
5643
5644 void MacroAssembler::load_aotrc_address(Register reg, address a) {
5645 #if INCLUDE_CDS
5646 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
5647 if (AOTCodeCache::is_on_for_dump()) {
5648 // all aotrc field addresses should be registered in the AOTCodeCache address table
5649 lea(reg, ExternalAddress(a));
5650 } else {
5651 mov(reg, (uint64_t)a);
5652 }
5653 #else
5654 ShouldNotReachHere();
5655 #endif
5656 }
5657
5658 void MacroAssembler::build_frame(int framesize) {
5659 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5660 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5661 protect_return_address();
5662 if (framesize < ((1 << 9) + 2 * wordSize)) {
5663 sub(sp, sp, framesize);
5664 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5665 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
5666 } else {
5667 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
5668 if (PreserveFramePointer) mov(rfp, sp);
5669 if (framesize < ((1 << 12) + 2 * wordSize))
5670 sub(sp, sp, framesize - 2 * wordSize);
5671 else {
5672 mov(rscratch1, framesize - 2 * wordSize);
5673 sub(sp, sp, rscratch1);
5674 }
5675 }
5676 verify_cross_modify_fence_not_required();
5677 }
5678
5679 void MacroAssembler::remove_frame(int framesize) {
5680 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5681 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5682 if (framesize < ((1 << 9) + 2 * wordSize)) {
5683 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5684 add(sp, sp, framesize);
5685 } else {
5686 if (framesize < ((1 << 12) + 2 * wordSize))
5687 add(sp, sp, framesize - 2 * wordSize);
5688 else {
5689 mov(rscratch1, framesize - 2 * wordSize);
5690 add(sp, sp, rscratch1);
5691 }
5692 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5693 }
5694 authenticate_return_address();
5695 }
5696
5697
5698 // This method counts leading positive bytes (highest bit not set) in provided byte array
5699 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5700 // Simple and most common case of aligned small array which is not at the
5701 // end of memory page is placed here. All other cases are in stub.
5702 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5703 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5704 assert_different_registers(ary1, len, result);
5705
5706 mov(result, len);
5707 cmpw(len, 0);
5708 br(LE, DONE);
5709 cmpw(len, 4 * wordSize);
5710 br(GE, STUB_LONG); // size > 32 then go to stub
5711
5712 int shift = 64 - exact_log2(os::vm_page_size());
5713 lsl(rscratch1, ary1, shift);
5714 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5715 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5716 br(CS, STUB); // at the end of page then go to stub
5717 subs(len, len, wordSize);
5718 br(LT, END);
5719
5720 BIND(LOOP);
5721 ldr(rscratch1, Address(post(ary1, wordSize)));
5722 tst(rscratch1, UPPER_BIT_MASK);
5723 br(NE, SET_RESULT);
5724 subs(len, len, wordSize);
5725 br(GE, LOOP);
5726 cmpw(len, -wordSize);
5727 br(EQ, DONE);
5728
5729 BIND(END);
5730 ldr(rscratch1, Address(ary1));
5731 sub(rscratch2, zr, len, LSL, 3); // LSL 3 is to get bits from bytes
5732 lslv(rscratch1, rscratch1, rscratch2);
5733 tst(rscratch1, UPPER_BIT_MASK);
5734 br(NE, SET_RESULT);
5735 b(DONE);
5736
5737 BIND(STUB);
5738 RuntimeAddress count_pos = RuntimeAddress(StubRoutines::aarch64::count_positives());
5739 assert(count_pos.target() != nullptr, "count_positives stub has not been generated");
5740 address tpc1 = trampoline_call(count_pos);
5741 if (tpc1 == nullptr) {
5742 DEBUG_ONLY(reset_labels(STUB_LONG, SET_RESULT, DONE));
5743 postcond(pc() == badAddress);
5744 return nullptr;
5745 }
5746 b(DONE);
5747
5748 BIND(STUB_LONG);
5749 RuntimeAddress count_pos_long = RuntimeAddress(StubRoutines::aarch64::count_positives_long());
5750 assert(count_pos_long.target() != nullptr, "count_positives_long stub has not been generated");
5751 address tpc2 = trampoline_call(count_pos_long);
5752 if (tpc2 == nullptr) {
5753 DEBUG_ONLY(reset_labels(SET_RESULT, DONE));
5754 postcond(pc() == badAddress);
5755 return nullptr;
5756 }
5757 b(DONE);
5758
5759 BIND(SET_RESULT);
5760
5761 add(len, len, wordSize);
5762 sub(result, result, len);
5763
5764 BIND(DONE);
5765 postcond(pc() != badAddress);
5766 return pc();
5767 }
5768
5769 // Clobbers: rscratch1, rscratch2, rflags
5770 // May also clobber v0-v7 when (!UseSimpleArrayEquals && UseSIMDForArrayEquals)
5771 address MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
5772 Register tmp4, Register tmp5, Register result,
5773 Register cnt1, int elem_size) {
5774 Label DONE, SAME;
5775 Register tmp1 = rscratch1;
5776 Register tmp2 = rscratch2;
5777 int elem_per_word = wordSize/elem_size;
5778 int log_elem_size = exact_log2(elem_size);
5779 int klass_offset = arrayOopDesc::klass_offset_in_bytes();
5780 int length_offset = arrayOopDesc::length_offset_in_bytes();
5781 int base_offset
5782 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
5783 // When the length offset is not aligned to 8 bytes,
5784 // then we align it down. This is valid because the new
5785 // offset will always be the klass which is the same
5786 // for type arrays.
5787 int start_offset = align_down(length_offset, BytesPerWord);
5788 int extra_length = base_offset - start_offset;
5789 assert(start_offset == length_offset || start_offset == klass_offset,
5790 "start offset must be 8-byte-aligned or be the klass offset");
5791 assert(base_offset != start_offset, "must include the length field");
5792 extra_length = extra_length / elem_size; // We count in elements, not bytes.
5793 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16);
5794
5795 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
5796 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5797
5798 #ifndef PRODUCT
5799 {
5800 const char kind = (elem_size == 2) ? 'U' : 'L';
5801 char comment[64];
5802 os::snprintf_checked(comment, sizeof comment, "array_equals%c{", kind);
5803 BLOCK_COMMENT(comment);
5804 }
5805 #endif
5806
5807 // if (a1 == a2)
5808 // return true;
5809 cmpoop(a1, a2); // May have read barriers for a1 and a2.
5810 br(EQ, SAME);
5811
5812 if (UseSimpleArrayEquals) {
5813 Label NEXT_WORD, SHORT, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL;
5814 // if (a1 == nullptr || a2 == nullptr)
5815 // return false;
5816 // a1 & a2 == 0 means (some-pointer is null) or
5817 // (very-rare-or-even-probably-impossible-pointer-values)
5818 // so, we can save one branch in most cases
5819 tst(a1, a2);
5820 mov(result, false);
5821 br(EQ, A_MIGHT_BE_NULL);
5822 // if (a1.length != a2.length)
5823 // return false;
5824 bind(A_IS_NOT_NULL);
5825 ldrw(cnt1, Address(a1, length_offset));
5826 // Increase loop counter by diff between base- and actual start-offset.
5827 addw(cnt1, cnt1, extra_length);
5828 lea(a1, Address(a1, start_offset));
5829 lea(a2, Address(a2, start_offset));
5830 // Check for short strings, i.e. smaller than wordSize.
5831 subs(cnt1, cnt1, elem_per_word);
5832 br(Assembler::LT, SHORT);
5833 // Main 8 byte comparison loop.
5834 bind(NEXT_WORD); {
5835 ldr(tmp1, Address(post(a1, wordSize)));
5836 ldr(tmp2, Address(post(a2, wordSize)));
5837 subs(cnt1, cnt1, elem_per_word);
5838 eor(tmp5, tmp1, tmp2);
5839 cbnz(tmp5, DONE);
5840 } br(GT, NEXT_WORD);
5841 // Last longword. In the case where length == 4 we compare the
5842 // same longword twice, but that's still faster than another
5843 // conditional branch.
5844 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
5845 // length == 4.
5846 if (log_elem_size > 0)
5847 lsl(cnt1, cnt1, log_elem_size);
5848 ldr(tmp3, Address(a1, cnt1));
5849 ldr(tmp4, Address(a2, cnt1));
5850 eor(tmp5, tmp3, tmp4);
5851 cbnz(tmp5, DONE);
5852 b(SAME);
5853 bind(A_MIGHT_BE_NULL);
5854 // in case both a1 and a2 are not-null, proceed with loads
5855 cbz(a1, DONE);
5856 cbz(a2, DONE);
5857 b(A_IS_NOT_NULL);
5858 bind(SHORT);
5859
5860 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
5861 {
5862 ldrw(tmp1, Address(post(a1, 4)));
5863 ldrw(tmp2, Address(post(a2, 4)));
5864 eorw(tmp5, tmp1, tmp2);
5865 cbnzw(tmp5, DONE);
5866 }
5867 bind(TAIL03);
5868 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
5869 {
5870 ldrh(tmp3, Address(post(a1, 2)));
5871 ldrh(tmp4, Address(post(a2, 2)));
5872 eorw(tmp5, tmp3, tmp4);
5873 cbnzw(tmp5, DONE);
5874 }
5875 bind(TAIL01);
5876 if (elem_size == 1) { // Only needed when comparing byte arrays.
5877 tbz(cnt1, 0, SAME); // 0-1 bytes left.
5878 {
5879 ldrb(tmp1, a1);
5880 ldrb(tmp2, a2);
5881 eorw(tmp5, tmp1, tmp2);
5882 cbnzw(tmp5, DONE);
5883 }
5884 }
5885 } else {
5886 Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB,
5887 CSET_EQ, LAST_CHECK;
5888 mov(result, false);
5889 cbz(a1, DONE);
5890 ldrw(cnt1, Address(a1, length_offset));
5891 cbz(a2, DONE);
5892 // Increase loop counter by diff between base- and actual start-offset.
5893 addw(cnt1, cnt1, extra_length);
5894
5895 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's
5896 // faster to perform another branch before comparing a1 and a2
5897 cmp(cnt1, (u1)elem_per_word);
5898 br(LE, SHORT); // short or same
5899 ldr(tmp3, Address(pre(a1, start_offset)));
5900 subs(zr, cnt1, stubBytesThreshold);
5901 br(GE, STUB);
5902 ldr(tmp4, Address(pre(a2, start_offset)));
5903 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
5904
5905 // Main 16 byte comparison loop with 2 exits
5906 bind(NEXT_DWORD); {
5907 ldr(tmp1, Address(pre(a1, wordSize)));
5908 ldr(tmp2, Address(pre(a2, wordSize)));
5909 subs(cnt1, cnt1, 2 * elem_per_word);
5910 br(LE, TAIL);
5911 eor(tmp4, tmp3, tmp4);
5912 cbnz(tmp4, DONE);
5913 ldr(tmp3, Address(pre(a1, wordSize)));
5914 ldr(tmp4, Address(pre(a2, wordSize)));
5915 cmp(cnt1, (u1)elem_per_word);
5916 br(LE, TAIL2);
5917 cmp(tmp1, tmp2);
5918 } br(EQ, NEXT_DWORD);
5919 b(DONE);
5920
5921 bind(TAIL);
5922 eor(tmp4, tmp3, tmp4);
5923 eor(tmp2, tmp1, tmp2);
5924 lslv(tmp2, tmp2, tmp5);
5925 orr(tmp5, tmp4, tmp2);
5926 cmp(tmp5, zr);
5927 b(CSET_EQ);
5928
5929 bind(TAIL2);
5930 eor(tmp2, tmp1, tmp2);
5931 cbnz(tmp2, DONE);
5932 b(LAST_CHECK);
5933
5934 bind(STUB);
5935 ldr(tmp4, Address(pre(a2, start_offset)));
5936 if (elem_size == 2) { // convert to byte counter
5937 lsl(cnt1, cnt1, 1);
5938 }
5939 eor(tmp5, tmp3, tmp4);
5940 cbnz(tmp5, DONE);
5941 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
5942 assert(stub.target() != nullptr, "array_equals_long stub has not been generated");
5943 address tpc = trampoline_call(stub);
5944 if (tpc == nullptr) {
5945 DEBUG_ONLY(reset_labels(SHORT, LAST_CHECK, CSET_EQ, SAME, DONE));
5946 postcond(pc() == badAddress);
5947 return nullptr;
5948 }
5949 b(DONE);
5950
5951 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
5952 // so, if a2 == null => return false(0), else return true, so we can return a2
5953 mov(result, a2);
5954 b(DONE);
5955 bind(SHORT);
5956 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
5957 ldr(tmp3, Address(a1, start_offset));
5958 ldr(tmp4, Address(a2, start_offset));
5959 bind(LAST_CHECK);
5960 eor(tmp4, tmp3, tmp4);
5961 lslv(tmp5, tmp4, tmp5);
5962 cmp(tmp5, zr);
5963 bind(CSET_EQ);
5964 cset(result, EQ);
5965 b(DONE);
5966 }
5967
5968 bind(SAME);
5969 mov(result, true);
5970 // That's it.
5971 bind(DONE);
5972
5973 BLOCK_COMMENT("} array_equals");
5974 postcond(pc() != badAddress);
5975 return pc();
5976 }
5977
5978 // Compare Strings
5979
5980 // For Strings we're passed the address of the first characters in a1
5981 // and a2 and the length in cnt1.
5982 // There are two implementations. For arrays >= 8 bytes, all
5983 // comparisons (including the final one, which may overlap) are
5984 // performed 8 bytes at a time. For strings < 8 bytes, we compare a
5985 // halfword, then a short, and then a byte.
5986
5987 void MacroAssembler::string_equals(Register a1, Register a2,
5988 Register result, Register cnt1)
5989 {
5990 Label SAME, DONE, SHORT, NEXT_WORD;
5991 Register tmp1 = rscratch1;
5992 Register tmp2 = rscratch2;
5993 Register cnt2 = tmp2; // cnt2 only used in array length compare
5994
5995 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5996
5997 #ifndef PRODUCT
5998 {
5999 char comment[64];
6000 os::snprintf_checked(comment, sizeof comment, "{string_equalsL");
6001 BLOCK_COMMENT(comment);
6002 }
6003 #endif
6004
6005 mov(result, false);
6006
6007 // Check for short strings, i.e. smaller than wordSize.
6008 subs(cnt1, cnt1, wordSize);
6009 br(Assembler::LT, SHORT);
6010 // Main 8 byte comparison loop.
6011 bind(NEXT_WORD); {
6012 ldr(tmp1, Address(post(a1, wordSize)));
6013 ldr(tmp2, Address(post(a2, wordSize)));
6014 subs(cnt1, cnt1, wordSize);
6015 eor(tmp1, tmp1, tmp2);
6016 cbnz(tmp1, DONE);
6017 } br(GT, NEXT_WORD);
6018 // Last longword. In the case where length == 4 we compare the
6019 // same longword twice, but that's still faster than another
6020 // conditional branch.
6021 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
6022 // length == 4.
6023 ldr(tmp1, Address(a1, cnt1));
6024 ldr(tmp2, Address(a2, cnt1));
6025 eor(tmp2, tmp1, tmp2);
6026 cbnz(tmp2, DONE);
6027 b(SAME);
6028
6029 bind(SHORT);
6030 Label TAIL03, TAIL01;
6031
6032 tbz(cnt1, 2, TAIL03); // 0-7 bytes left.
6033 {
6034 ldrw(tmp1, Address(post(a1, 4)));
6035 ldrw(tmp2, Address(post(a2, 4)));
6036 eorw(tmp1, tmp1, tmp2);
6037 cbnzw(tmp1, DONE);
6038 }
6039 bind(TAIL03);
6040 tbz(cnt1, 1, TAIL01); // 0-3 bytes left.
6041 {
6042 ldrh(tmp1, Address(post(a1, 2)));
6043 ldrh(tmp2, Address(post(a2, 2)));
6044 eorw(tmp1, tmp1, tmp2);
6045 cbnzw(tmp1, DONE);
6046 }
6047 bind(TAIL01);
6048 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6049 {
6050 ldrb(tmp1, a1);
6051 ldrb(tmp2, a2);
6052 eorw(tmp1, tmp1, tmp2);
6053 cbnzw(tmp1, DONE);
6054 }
6055 // Arrays are equal.
6056 bind(SAME);
6057 mov(result, true);
6058
6059 // That's it.
6060 bind(DONE);
6061 BLOCK_COMMENT("} string_equals");
6062 }
6063
6064
6065 // The size of the blocks erased by the zero_blocks stub. We must
6066 // handle anything smaller than this ourselves in zero_words().
6067 const int MacroAssembler::zero_words_block_size = 8;
6068
6069 // zero_words() is used by C2 ClearArray patterns and by
6070 // C1_MacroAssembler. It is as small as possible, handling small word
6071 // counts locally and delegating anything larger to the zero_blocks
6072 // stub. It is expanded many times in compiled code, so it is
6073 // important to keep it short.
6074
6075 // ptr: Address of a buffer to be zeroed.
6076 // cnt: Count in HeapWords.
6077 //
6078 // ptr, cnt, rscratch1, and rscratch2 are clobbered.
6079 address MacroAssembler::zero_words(Register ptr, Register cnt)
6080 {
6081 assert(is_power_of_2(zero_words_block_size), "adjust this");
6082
6083 BLOCK_COMMENT("zero_words {");
6084 assert(ptr == r10 && cnt == r11, "mismatch in register usage");
6085 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6086 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6087
6088 subs(rscratch1, cnt, zero_words_block_size);
6089 Label around;
6090 br(LO, around);
6091 {
6092 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6093 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6094 // Make sure this is a C2 compilation. C1 allocates space only for
6095 // trampoline stubs generated by Call LIR ops, and in any case it
6096 // makes sense for a C1 compilation task to proceed as quickly as
6097 // possible.
6098 CompileTask* task;
6099 if (StubRoutines::aarch64::complete()
6100 && Thread::current()->is_Compiler_thread()
6101 && (task = ciEnv::current()->task())
6102 && is_c2_compile(task->comp_level())) {
6103 address tpc = trampoline_call(zero_blocks);
6104 if (tpc == nullptr) {
6105 DEBUG_ONLY(reset_labels(around));
6106 return nullptr;
6107 }
6108 } else {
6109 far_call(zero_blocks);
6110 }
6111 }
6112 bind(around);
6113
6114 // We have a few words left to do. zero_blocks has adjusted r10 and r11
6115 // for us.
6116 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) {
6117 Label l;
6118 tbz(cnt, exact_log2(i), l);
6119 for (int j = 0; j < i; j += 2) {
6120 stp(zr, zr, post(ptr, 2 * BytesPerWord));
6121 }
6122 bind(l);
6123 }
6124 {
6125 Label l;
6126 tbz(cnt, 0, l);
6127 str(zr, Address(ptr));
6128 bind(l);
6129 }
6130
6131 BLOCK_COMMENT("} zero_words");
6132 return pc();
6133 }
6134
6135 // base: Address of a buffer to be zeroed, 8 bytes aligned.
6136 // cnt: Immediate count in HeapWords.
6137 //
6138 // r10, r11, rscratch1, and rscratch2 are clobbered.
6139 address MacroAssembler::zero_words(Register base, uint64_t cnt)
6140 {
6141 assert(wordSize <= BlockZeroingLowLimit,
6142 "increase BlockZeroingLowLimit");
6143 address result = nullptr;
6144 if (cnt <= (uint64_t)BlockZeroingLowLimit / BytesPerWord) {
6145 #ifndef PRODUCT
6146 {
6147 char buf[64];
6148 os::snprintf_checked(buf, sizeof buf, "zero_words (count = %" PRIu64 ") {", cnt);
6149 BLOCK_COMMENT(buf);
6150 }
6151 #endif
6152 if (cnt >= 16) {
6153 uint64_t loops = cnt/16;
6154 if (loops > 1) {
6155 mov(rscratch2, loops - 1);
6156 }
6157 {
6158 Label loop;
6159 bind(loop);
6160 for (int i = 0; i < 16; i += 2) {
6161 stp(zr, zr, Address(base, i * BytesPerWord));
6162 }
6163 add(base, base, 16 * BytesPerWord);
6164 if (loops > 1) {
6165 subs(rscratch2, rscratch2, 1);
6166 br(GE, loop);
6167 }
6168 }
6169 }
6170 cnt %= 16;
6171 int i = cnt & 1; // store any odd word to start
6172 if (i) str(zr, Address(base));
6173 for (; i < (int)cnt; i += 2) {
6174 stp(zr, zr, Address(base, i * wordSize));
6175 }
6176 BLOCK_COMMENT("} zero_words");
6177 result = pc();
6178 } else {
6179 mov(r10, base); mov(r11, cnt);
6180 result = zero_words(r10, r11);
6181 }
6182 return result;
6183 }
6184
6185 // Zero blocks of memory by using DC ZVA.
6186 //
6187 // Aligns the base address first sufficiently for DC ZVA, then uses
6188 // DC ZVA repeatedly for every full block. cnt is the size to be
6189 // zeroed in HeapWords. Returns the count of words left to be zeroed
6190 // in cnt.
6191 //
6192 // NOTE: This is intended to be used in the zero_blocks() stub. If
6193 // you want to use it elsewhere, note that cnt must be >= 2*zva_length.
6194 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) {
6195 Register tmp = rscratch1;
6196 Register tmp2 = rscratch2;
6197 int zva_length = VM_Version::zva_length();
6198 Label initial_table_end, loop_zva;
6199 Label fini;
6200
6201 // Base must be 16 byte aligned. If not just return and let caller handle it
6202 tst(base, 0x0f);
6203 br(Assembler::NE, fini);
6204 // Align base with ZVA length.
6205 neg(tmp, base);
6206 andr(tmp, tmp, zva_length - 1);
6207
6208 // tmp: the number of bytes to be filled to align the base with ZVA length.
6209 add(base, base, tmp);
6210 sub(cnt, cnt, tmp, Assembler::ASR, 3);
6211 adr(tmp2, initial_table_end);
6212 sub(tmp2, tmp2, tmp, Assembler::LSR, 2);
6213 br(tmp2);
6214
6215 for (int i = -zva_length + 16; i < 0; i += 16)
6216 stp(zr, zr, Address(base, i));
6217 bind(initial_table_end);
6218
6219 sub(cnt, cnt, zva_length >> 3);
6220 bind(loop_zva);
6221 dc(Assembler::ZVA, base);
6222 subs(cnt, cnt, zva_length >> 3);
6223 add(base, base, zva_length);
6224 br(Assembler::GE, loop_zva);
6225 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA
6226 bind(fini);
6227 }
6228
6229 // base: Address of a buffer to be filled, 8 bytes aligned.
6230 // cnt: Count in 8-byte unit.
6231 // value: Value to be filled with.
6232 // base will point to the end of the buffer after filling.
6233 void MacroAssembler::fill_words(Register base, Register cnt, Register value)
6234 {
6235 // Algorithm:
6236 //
6237 // if (cnt == 0) {
6238 // return;
6239 // }
6240 // if ((p & 8) != 0) {
6241 // *p++ = v;
6242 // }
6243 //
6244 // scratch1 = cnt & 14;
6245 // cnt -= scratch1;
6246 // p += scratch1;
6247 // switch (scratch1 / 2) {
6248 // do {
6249 // cnt -= 16;
6250 // p[-16] = v;
6251 // p[-15] = v;
6252 // case 7:
6253 // p[-14] = v;
6254 // p[-13] = v;
6255 // case 6:
6256 // p[-12] = v;
6257 // p[-11] = v;
6258 // // ...
6259 // case 1:
6260 // p[-2] = v;
6261 // p[-1] = v;
6262 // case 0:
6263 // p += 16;
6264 // } while (cnt);
6265 // }
6266 // if ((cnt & 1) == 1) {
6267 // *p++ = v;
6268 // }
6269
6270 assert_different_registers(base, cnt, value, rscratch1, rscratch2);
6271
6272 Label fini, skip, entry, loop;
6273 const int unroll = 8; // Number of stp instructions we'll unroll
6274
6275 cbz(cnt, fini);
6276 tbz(base, 3, skip);
6277 str(value, Address(post(base, 8)));
6278 sub(cnt, cnt, 1);
6279 bind(skip);
6280
6281 andr(rscratch1, cnt, (unroll-1) * 2);
6282 sub(cnt, cnt, rscratch1);
6283 add(base, base, rscratch1, Assembler::LSL, 3);
6284 adr(rscratch2, entry);
6285 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1);
6286 br(rscratch2);
6287
6288 bind(loop);
6289 add(base, base, unroll * 16);
6290 for (int i = -unroll; i < 0; i++)
6291 stp(value, value, Address(base, i * 16));
6292 bind(entry);
6293 subs(cnt, cnt, unroll * 2);
6294 br(Assembler::GE, loop);
6295
6296 tbz(cnt, 0, fini);
6297 str(value, Address(post(base, 8)));
6298 bind(fini);
6299 }
6300
6301 // Intrinsic for
6302 //
6303 // - sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6304 // Encodes char[] to byte[] in ISO-8859-1
6305 //
6306 // - java.lang.StringCoding#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6307 // Encodes byte[] (containing UTF-16) to byte[] in ISO-8859-1
6308 //
6309 // - java.lang.StringCoding#encodeAsciiArray0(char[] sa, int sp, byte[] da, int dp, int len)
6310 // Encodes char[] to byte[] in ASCII
6311 //
6312 // This version always returns the number of characters copied, and does not
6313 // clobber the 'len' register. A successful copy will complete with the post-
6314 // condition: 'res' == 'len', while an unsuccessful copy will exit with the
6315 // post-condition: 0 <= 'res' < 'len'.
6316 //
6317 // NOTE: Attempts to use 'ld2' (and 'umaxv' in the ISO part) has proven to
6318 // degrade performance (on Ampere Altra - Neoverse N1), to an extent
6319 // beyond the acceptable, even though the footprint would be smaller.
6320 // Using 'umaxv' in the ASCII-case comes with a small penalty but does
6321 // avoid additional bloat.
6322 //
6323 // Clobbers: src, dst, res, rscratch1, rscratch2, rflags
6324 void MacroAssembler::encode_iso_array(Register src, Register dst,
6325 Register len, Register res, bool ascii,
6326 FloatRegister vtmp0, FloatRegister vtmp1,
6327 FloatRegister vtmp2, FloatRegister vtmp3,
6328 FloatRegister vtmp4, FloatRegister vtmp5)
6329 {
6330 Register cnt = res;
6331 Register max = rscratch1;
6332 Register chk = rscratch2;
6333
6334 prfm(Address(src), PLDL1STRM);
6335 movw(cnt, len);
6336
6337 #define ASCII(insn) do { if (ascii) { insn; } } while (0)
6338
6339 Label LOOP_32, DONE_32, FAIL_32;
6340
6341 BIND(LOOP_32);
6342 {
6343 cmpw(cnt, 32);
6344 br(LT, DONE_32);
6345 ld1(vtmp0, vtmp1, vtmp2, vtmp3, T8H, Address(post(src, 64)));
6346 // Extract lower bytes.
6347 FloatRegister vlo0 = vtmp4;
6348 FloatRegister vlo1 = vtmp5;
6349 uzp1(vlo0, T16B, vtmp0, vtmp1);
6350 uzp1(vlo1, T16B, vtmp2, vtmp3);
6351 // Merge bits...
6352 orr(vtmp0, T16B, vtmp0, vtmp1);
6353 orr(vtmp2, T16B, vtmp2, vtmp3);
6354 // Extract merged upper bytes.
6355 FloatRegister vhix = vtmp0;
6356 uzp2(vhix, T16B, vtmp0, vtmp2);
6357 // ISO-check on hi-parts (all zero).
6358 // ASCII-check on lo-parts (no sign).
6359 FloatRegister vlox = vtmp1; // Merge lower bytes.
6360 ASCII(orr(vlox, T16B, vlo0, vlo1));
6361 umov(chk, vhix, D, 1); ASCII(cm(LT, vlox, T16B, vlox));
6362 fmovd(max, vhix); ASCII(umaxv(vlox, T16B, vlox));
6363 orr(chk, chk, max); ASCII(umov(max, vlox, B, 0));
6364 ASCII(orr(chk, chk, max));
6365 cbnz(chk, FAIL_32);
6366 subw(cnt, cnt, 32);
6367 st1(vlo0, vlo1, T16B, Address(post(dst, 32)));
6368 b(LOOP_32);
6369 }
6370 BIND(FAIL_32);
6371 sub(src, src, 64);
6372 BIND(DONE_32);
6373
6374 Label LOOP_8, SKIP_8;
6375
6376 BIND(LOOP_8);
6377 {
6378 cmpw(cnt, 8);
6379 br(LT, SKIP_8);
6380 FloatRegister vhi = vtmp0;
6381 FloatRegister vlo = vtmp1;
6382 ld1(vtmp3, T8H, src);
6383 uzp1(vlo, T16B, vtmp3, vtmp3);
6384 uzp2(vhi, T16B, vtmp3, vtmp3);
6385 // ISO-check on hi-parts (all zero).
6386 // ASCII-check on lo-parts (no sign).
6387 ASCII(cm(LT, vtmp2, T16B, vlo));
6388 fmovd(chk, vhi); ASCII(umaxv(vtmp2, T16B, vtmp2));
6389 ASCII(umov(max, vtmp2, B, 0));
6390 ASCII(orr(chk, chk, max));
6391 cbnz(chk, SKIP_8);
6392
6393 strd(vlo, Address(post(dst, 8)));
6394 subw(cnt, cnt, 8);
6395 add(src, src, 16);
6396 b(LOOP_8);
6397 }
6398 BIND(SKIP_8);
6399
6400 #undef ASCII
6401
6402 Label LOOP, DONE;
6403
6404 cbz(cnt, DONE);
6405 BIND(LOOP);
6406 {
6407 Register chr = rscratch1;
6408 ldrh(chr, Address(post(src, 2)));
6409 tst(chr, ascii ? 0xff80 : 0xff00);
6410 br(NE, DONE);
6411 strb(chr, Address(post(dst, 1)));
6412 subs(cnt, cnt, 1);
6413 br(GT, LOOP);
6414 }
6415 BIND(DONE);
6416 // Return index where we stopped.
6417 subw(res, len, cnt);
6418 }
6419
6420 // Inflate byte[] array to char[].
6421 // Clobbers: src, dst, len, rflags, rscratch1, v0-v6
6422 address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
6423 FloatRegister vtmp1, FloatRegister vtmp2,
6424 FloatRegister vtmp3, Register tmp4) {
6425 Label big, done, after_init, to_stub;
6426
6427 assert_different_registers(src, dst, len, tmp4, rscratch1);
6428
6429 fmovd(vtmp1, 0.0);
6430 lsrw(tmp4, len, 3);
6431 bind(after_init);
6432 cbnzw(tmp4, big);
6433 // Short string: less than 8 bytes.
6434 {
6435 Label loop, tiny;
6436
6437 cmpw(len, 4);
6438 br(LT, tiny);
6439 // Use SIMD to do 4 bytes.
6440 ldrs(vtmp2, post(src, 4));
6441 zip1(vtmp3, T8B, vtmp2, vtmp1);
6442 subw(len, len, 4);
6443 strd(vtmp3, post(dst, 8));
6444
6445 cbzw(len, done);
6446
6447 // Do the remaining bytes by steam.
6448 bind(loop);
6449 ldrb(tmp4, post(src, 1));
6450 strh(tmp4, post(dst, 2));
6451 subw(len, len, 1);
6452
6453 bind(tiny);
6454 cbnz(len, loop);
6455
6456 b(done);
6457 }
6458
6459 if (SoftwarePrefetchHintDistance >= 0) {
6460 bind(to_stub);
6461 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate());
6462 assert(stub.target() != nullptr, "large_byte_array_inflate stub has not been generated");
6463 address tpc = trampoline_call(stub);
6464 if (tpc == nullptr) {
6465 DEBUG_ONLY(reset_labels(big, done));
6466 postcond(pc() == badAddress);
6467 return nullptr;
6468 }
6469 b(after_init);
6470 }
6471
6472 // Unpack the bytes 8 at a time.
6473 bind(big);
6474 {
6475 Label loop, around, loop_last, loop_start;
6476
6477 if (SoftwarePrefetchHintDistance >= 0) {
6478 const int large_loop_threshold = (64 + 16)/8;
6479 ldrd(vtmp2, post(src, 8));
6480 andw(len, len, 7);
6481 cmp(tmp4, (u1)large_loop_threshold);
6482 br(GE, to_stub);
6483 b(loop_start);
6484
6485 bind(loop);
6486 ldrd(vtmp2, post(src, 8));
6487 bind(loop_start);
6488 subs(tmp4, tmp4, 1);
6489 br(EQ, loop_last);
6490 zip1(vtmp2, T16B, vtmp2, vtmp1);
6491 ldrd(vtmp3, post(src, 8));
6492 st1(vtmp2, T8H, post(dst, 16));
6493 subs(tmp4, tmp4, 1);
6494 zip1(vtmp3, T16B, vtmp3, vtmp1);
6495 st1(vtmp3, T8H, post(dst, 16));
6496 br(NE, loop);
6497 b(around);
6498 bind(loop_last);
6499 zip1(vtmp2, T16B, vtmp2, vtmp1);
6500 st1(vtmp2, T8H, post(dst, 16));
6501 bind(around);
6502 cbz(len, done);
6503 } else {
6504 andw(len, len, 7);
6505 bind(loop);
6506 ldrd(vtmp2, post(src, 8));
6507 sub(tmp4, tmp4, 1);
6508 zip1(vtmp3, T16B, vtmp2, vtmp1);
6509 st1(vtmp3, T8H, post(dst, 16));
6510 cbnz(tmp4, loop);
6511 }
6512 }
6513
6514 // Do the tail of up to 8 bytes.
6515 add(src, src, len);
6516 ldrd(vtmp3, Address(src, -8));
6517 add(dst, dst, len, ext::uxtw, 1);
6518 zip1(vtmp3, T16B, vtmp3, vtmp1);
6519 strq(vtmp3, Address(dst, -16));
6520
6521 bind(done);
6522 postcond(pc() != badAddress);
6523 return pc();
6524 }
6525
6526 // Compress char[] array to byte[].
6527 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
6528 // Return the array length if every element in array can be encoded,
6529 // otherwise, the index of first non-latin1 (> 0xff) character.
6530 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
6531 Register res,
6532 FloatRegister tmp0, FloatRegister tmp1,
6533 FloatRegister tmp2, FloatRegister tmp3,
6534 FloatRegister tmp4, FloatRegister tmp5) {
6535 encode_iso_array(src, dst, len, res, false, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5);
6536 }
6537
6538 // java.math.round(double a)
6539 // Returns the closest long to the argument, with ties rounding to
6540 // positive infinity. This requires some fiddling for corner
6541 // cases. We take care to avoid double rounding in e.g. (jlong)(a + 0.5).
6542 void MacroAssembler::java_round_double(Register dst, FloatRegister src,
6543 FloatRegister ftmp) {
6544 Label DONE;
6545 BLOCK_COMMENT("java_round_double: { ");
6546 fmovd(rscratch1, src);
6547 // Use RoundToNearestTiesAway unless src small and -ve.
6548 fcvtasd(dst, src);
6549 // Test if src >= 0 || abs(src) >= 0x1.0p52
6550 eor(rscratch1, rscratch1, UCONST64(1) << 63); // flip sign bit
6551 mov(rscratch2, julong_cast(0x1.0p52));
6552 cmp(rscratch1, rscratch2);
6553 br(HS, DONE); {
6554 // src < 0 && abs(src) < 0x1.0p52
6555 // src may have a fractional part, so add 0.5
6556 fmovd(ftmp, 0.5);
6557 faddd(ftmp, src, ftmp);
6558 // Convert double to jlong, use RoundTowardsNegative
6559 fcvtmsd(dst, ftmp);
6560 }
6561 bind(DONE);
6562 BLOCK_COMMENT("} java_round_double");
6563 }
6564
6565 void MacroAssembler::java_round_float(Register dst, FloatRegister src,
6566 FloatRegister ftmp) {
6567 Label DONE;
6568 BLOCK_COMMENT("java_round_float: { ");
6569 fmovs(rscratch1, src);
6570 // Use RoundToNearestTiesAway unless src small and -ve.
6571 fcvtassw(dst, src);
6572 // Test if src >= 0 || abs(src) >= 0x1.0p23
6573 eor(rscratch1, rscratch1, 0x80000000); // flip sign bit
6574 mov(rscratch2, jint_cast(0x1.0p23f));
6575 cmp(rscratch1, rscratch2);
6576 br(HS, DONE); {
6577 // src < 0 && |src| < 0x1.0p23
6578 // src may have a fractional part, so add 0.5
6579 fmovs(ftmp, 0.5f);
6580 fadds(ftmp, src, ftmp);
6581 // Convert float to jint, use RoundTowardsNegative
6582 fcvtmssw(dst, ftmp);
6583 }
6584 bind(DONE);
6585 BLOCK_COMMENT("} java_round_float");
6586 }
6587
6588 // get_thread() can be called anywhere inside generated code so we
6589 // need to save whatever non-callee save context might get clobbered
6590 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
6591 // the call setup code.
6592 //
6593 // On Linux, aarch64_get_thread_helper() clobbers only r0, r1, and flags.
6594 // On other systems, the helper is a usual C function.
6595 //
6596 void MacroAssembler::get_thread(Register dst) {
6597 RegSet saved_regs =
6598 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6599 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6600
6601 protect_return_address();
6602 push(saved_regs, sp);
6603
6604 mov(lr, ExternalAddress(CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)));
6605 blr(lr);
6606 if (dst != c_rarg0) {
6607 mov(dst, c_rarg0);
6608 }
6609
6610 pop(saved_regs, sp);
6611 authenticate_return_address();
6612 }
6613
6614 void MacroAssembler::cache_wb(Address line) {
6615 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
6616 assert(line.index() == noreg, "index should be noreg");
6617 assert(line.offset() == 0, "offset should be 0");
6618 // would like to assert this
6619 // assert(line._ext.shift == 0, "shift should be zero");
6620 if (VM_Version::supports_dcpop()) {
6621 // writeback using clear virtual address to point of persistence
6622 dc(Assembler::CVAP, line.base());
6623 } else {
6624 // no need to generate anything as Unsafe.writebackMemory should
6625 // never invoke this stub
6626 }
6627 }
6628
6629 void MacroAssembler::cache_wbsync(bool is_pre) {
6630 // we only need a barrier post sync
6631 if (!is_pre) {
6632 membar(Assembler::AnyAny);
6633 }
6634 }
6635
6636 void MacroAssembler::verify_sve_vector_length(Register tmp) {
6637 if (!UseSVE || VM_Version::get_max_supported_sve_vector_length() == FloatRegister::sve_vl_min) {
6638 return;
6639 }
6640 // Make sure that native code does not change SVE vector length.
6641 Label verify_ok;
6642 movw(tmp, zr);
6643 sve_inc(tmp, B);
6644 subsw(zr, tmp, VM_Version::get_initial_sve_vector_length());
6645 br(EQ, verify_ok);
6646 stop("Error: SVE vector length has changed since jvm startup");
6647 bind(verify_ok);
6648 }
6649
6650 void MacroAssembler::verify_ptrue() {
6651 Label verify_ok;
6652 if (!UseSVE) {
6653 return;
6654 }
6655 sve_cntp(rscratch1, B, ptrue, ptrue); // get true elements count.
6656 sve_dec(rscratch1, B);
6657 cbz(rscratch1, verify_ok);
6658 stop("Error: the preserved predicate register (p7) elements are not all true");
6659 bind(verify_ok);
6660 }
6661
6662 void MacroAssembler::safepoint_isb() {
6663 isb();
6664 #ifndef PRODUCT
6665 if (VerifyCrossModifyFence) {
6666 // Clear the thread state.
6667 strb(zr, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6668 }
6669 #endif
6670 }
6671
6672 #ifndef PRODUCT
6673 void MacroAssembler::verify_cross_modify_fence_not_required() {
6674 if (VerifyCrossModifyFence) {
6675 // Check if thread needs a cross modify fence.
6676 ldrb(rscratch1, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6677 Label fence_not_required;
6678 cbz(rscratch1, fence_not_required);
6679 // If it does then fail.
6680 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::verify_cross_modify_fence_failure)));
6681 mov(c_rarg0, rthread);
6682 blr(rscratch1);
6683 bind(fence_not_required);
6684 }
6685 }
6686 #endif
6687
6688 void MacroAssembler::spin_wait() {
6689 block_comment("spin_wait {");
6690 for (int i = 0; i < VM_Version::spin_wait_desc().inst_count(); ++i) {
6691 switch (VM_Version::spin_wait_desc().inst()) {
6692 case SpinWait::NOP:
6693 nop();
6694 break;
6695 case SpinWait::ISB:
6696 isb();
6697 break;
6698 case SpinWait::YIELD:
6699 yield();
6700 break;
6701 case SpinWait::SB:
6702 assert(VM_Version::supports_sb(), "current CPU does not support SB instruction");
6703 sb();
6704 break;
6705 default:
6706 ShouldNotReachHere();
6707 }
6708 }
6709 block_comment("}");
6710 }
6711
6712 // Stack frame creation/removal
6713
6714 void MacroAssembler::enter(bool strip_ret_addr) {
6715 if (strip_ret_addr) {
6716 // Addresses can only be signed once. If there are multiple nested frames being created
6717 // in the same function, then the return address needs stripping first.
6718 strip_return_address();
6719 }
6720 protect_return_address();
6721 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
6722 mov(rfp, sp);
6723 }
6724
6725 void MacroAssembler::leave() {
6726 mov(sp, rfp);
6727 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
6728 authenticate_return_address();
6729 }
6730
6731 // ROP Protection
6732 // Use the AArch64 PAC feature to add ROP protection for generated code. Use whenever creating/
6733 // destroying stack frames or whenever directly loading/storing the LR to memory.
6734 // If ROP protection is not set then these functions are no-ops.
6735 // For more details on PAC see pauth_aarch64.hpp.
6736
6737 // Sign the LR. Use during construction of a stack frame, before storing the LR to memory.
6738 // Uses value zero as the modifier.
6739 //
6740 void MacroAssembler::protect_return_address() {
6741 if (VM_Version::use_rop_protection()) {
6742 check_return_address();
6743 paciaz();
6744 }
6745 }
6746
6747 // Sign the return value in the given register. Use before updating the LR in the existing stack
6748 // frame for the current function.
6749 // Uses value zero as the modifier.
6750 //
6751 void MacroAssembler::protect_return_address(Register return_reg) {
6752 if (VM_Version::use_rop_protection()) {
6753 check_return_address(return_reg);
6754 paciza(return_reg);
6755 }
6756 }
6757
6758 // Authenticate the LR. Use before function return, after restoring FP and loading LR from memory.
6759 // Uses value zero as the modifier.
6760 //
6761 void MacroAssembler::authenticate_return_address() {
6762 if (VM_Version::use_rop_protection()) {
6763 autiaz();
6764 check_return_address();
6765 }
6766 }
6767
6768 // Authenticate the return value in the given register. Use before updating the LR in the existing
6769 // stack frame for the current function.
6770 // Uses value zero as the modifier.
6771 //
6772 void MacroAssembler::authenticate_return_address(Register return_reg) {
6773 if (VM_Version::use_rop_protection()) {
6774 autiza(return_reg);
6775 check_return_address(return_reg);
6776 }
6777 }
6778
6779 // Strip any PAC data from LR without performing any authentication. Use with caution - only if
6780 // there is no guaranteed way of authenticating the LR.
6781 //
6782 void MacroAssembler::strip_return_address() {
6783 if (VM_Version::use_rop_protection()) {
6784 xpaclri();
6785 }
6786 }
6787
6788 #ifndef PRODUCT
6789 // PAC failures can be difficult to debug. After an authentication failure, a segfault will only
6790 // occur when the pointer is used - ie when the program returns to the invalid LR. At this point
6791 // it is difficult to debug back to the callee function.
6792 // This function simply loads from the address in the given register.
6793 // Use directly after authentication to catch authentication failures.
6794 // Also use before signing to check that the pointer is valid and hasn't already been signed.
6795 //
6796 void MacroAssembler::check_return_address(Register return_reg) {
6797 if (VM_Version::use_rop_protection()) {
6798 ldr(zr, Address(return_reg));
6799 }
6800 }
6801 #endif
6802
6803 // The java_calling_convention describes stack locations as ideal slots on
6804 // a frame with no abi restrictions. Since we must observe abi restrictions
6805 // (like the placement of the register window) the slots must be biased by
6806 // the following value.
6807 static int reg2offset_in(VMReg r) {
6808 // Account for saved rfp and lr
6809 // This should really be in_preserve_stack_slots
6810 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
6811 }
6812
6813 static int reg2offset_out(VMReg r) {
6814 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
6815 }
6816
6817 // On 64bit we will store integer like items to the stack as
6818 // 64bits items (AArch64 ABI) even though java would only store
6819 // 32bits for a parameter. On 32bit it will simply be 32bits
6820 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
6821 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp) {
6822 if (src.first()->is_stack()) {
6823 if (dst.first()->is_stack()) {
6824 // stack to stack
6825 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
6826 str(tmp, Address(sp, reg2offset_out(dst.first())));
6827 } else {
6828 // stack to reg
6829 ldrsw(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
6830 }
6831 } else if (dst.first()->is_stack()) {
6832 // reg to stack
6833 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
6834 } else {
6835 if (dst.first() != src.first()) {
6836 sxtw(dst.first()->as_Register(), src.first()->as_Register());
6837 }
6838 }
6839 }
6840
6841 // An oop arg. Must pass a handle not the oop itself
6842 void MacroAssembler::object_move(
6843 OopMap* map,
6844 int oop_handle_offset,
6845 int framesize_in_slots,
6846 VMRegPair src,
6847 VMRegPair dst,
6848 bool is_receiver,
6849 int* receiver_offset) {
6850
6851 // must pass a handle. First figure out the location we use as a handle
6852
6853 Register rHandle = dst.first()->is_stack() ? rscratch2 : dst.first()->as_Register();
6854
6855 // See if oop is null if it is we need no handle
6856
6857 if (src.first()->is_stack()) {
6858
6859 // Oop is already on the stack as an argument
6860 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
6861 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
6862 if (is_receiver) {
6863 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
6864 }
6865
6866 ldr(rscratch1, Address(rfp, reg2offset_in(src.first())));
6867 lea(rHandle, Address(rfp, reg2offset_in(src.first())));
6868 // conditionally move a null
6869 cmp(rscratch1, zr);
6870 csel(rHandle, zr, rHandle, Assembler::EQ);
6871 } else {
6872
6873 // Oop is in an a register we must store it to the space we reserve
6874 // on the stack for oop_handles and pass a handle if oop is non-null
6875
6876 const Register rOop = src.first()->as_Register();
6877 int oop_slot;
6878 if (rOop == j_rarg0)
6879 oop_slot = 0;
6880 else if (rOop == j_rarg1)
6881 oop_slot = 1;
6882 else if (rOop == j_rarg2)
6883 oop_slot = 2;
6884 else if (rOop == j_rarg3)
6885 oop_slot = 3;
6886 else if (rOop == j_rarg4)
6887 oop_slot = 4;
6888 else if (rOop == j_rarg5)
6889 oop_slot = 5;
6890 else if (rOop == j_rarg6)
6891 oop_slot = 6;
6892 else {
6893 assert(rOop == j_rarg7, "wrong register");
6894 oop_slot = 7;
6895 }
6896
6897 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
6898 int offset = oop_slot*VMRegImpl::stack_slot_size;
6899
6900 map->set_oop(VMRegImpl::stack2reg(oop_slot));
6901 // Store oop in handle area, may be null
6902 str(rOop, Address(sp, offset));
6903 if (is_receiver) {
6904 *receiver_offset = offset;
6905 }
6906
6907 cmp(rOop, zr);
6908 lea(rHandle, Address(sp, offset));
6909 // conditionally move a null
6910 csel(rHandle, zr, rHandle, Assembler::EQ);
6911 }
6912
6913 // If arg is on the stack then place it otherwise it is already in correct reg.
6914 if (dst.first()->is_stack()) {
6915 str(rHandle, Address(sp, reg2offset_out(dst.first())));
6916 }
6917 }
6918
6919 // A float arg may have to do float reg int reg conversion
6920 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp) {
6921 if (src.first()->is_stack()) {
6922 if (dst.first()->is_stack()) {
6923 ldrw(tmp, Address(rfp, reg2offset_in(src.first())));
6924 strw(tmp, Address(sp, reg2offset_out(dst.first())));
6925 } else {
6926 ldrs(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
6927 }
6928 } else if (src.first() != dst.first()) {
6929 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
6930 fmovs(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
6931 else
6932 strs(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
6933 }
6934 }
6935
6936 // A long move
6937 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp) {
6938 if (src.first()->is_stack()) {
6939 if (dst.first()->is_stack()) {
6940 // stack to stack
6941 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
6942 str(tmp, Address(sp, reg2offset_out(dst.first())));
6943 } else {
6944 // stack to reg
6945 ldr(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
6946 }
6947 } else if (dst.first()->is_stack()) {
6948 // reg to stack
6949 // Do we really have to sign extend???
6950 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
6951 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
6952 } else {
6953 if (dst.first() != src.first()) {
6954 mov(dst.first()->as_Register(), src.first()->as_Register());
6955 }
6956 }
6957 }
6958
6959
6960 // A double move
6961 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp) {
6962 if (src.first()->is_stack()) {
6963 if (dst.first()->is_stack()) {
6964 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
6965 str(tmp, Address(sp, reg2offset_out(dst.first())));
6966 } else {
6967 ldrd(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
6968 }
6969 } else if (src.first() != dst.first()) {
6970 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
6971 fmovd(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
6972 else
6973 strd(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
6974 }
6975 }
6976
6977 // Implements fast-locking.
6978 //
6979 // - obj: the object to be locked
6980 // - t1, t2, t3: temporary registers, will be destroyed
6981 // - slow: branched to if locking fails, absolute offset may larger than 32KB (imm14 encoding).
6982 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow) {
6983 assert_different_registers(basic_lock, obj, t1, t2, t3, rscratch1);
6984
6985 Label push;
6986 const Register top = t1;
6987 const Register mark = t2;
6988 const Register t = t3;
6989
6990 // Preload the markWord. It is important that this is the first
6991 // instruction emitted as it is part of C1's null check semantics.
6992 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
6993
6994 if (UseObjectMonitorTable) {
6995 // Clear cache in case fast locking succeeds or we need to take the slow-path.
6996 str(zr, Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))));
6997 }
6998
6999 if (DiagnoseSyncOnValueBasedClasses != 0) {
7000 load_klass(t1, obj);
7001 ldrb(t1, Address(t1, Klass::misc_flags_offset()));
7002 tst(t1, KlassFlags::_misc_is_value_based_class);
7003 br(Assembler::NE, slow);
7004 }
7005
7006 // Check if the lock-stack is full.
7007 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7008 cmpw(top, (unsigned)LockStack::end_offset());
7009 br(Assembler::GE, slow);
7010
7011 // Check for recursion.
7012 subw(t, top, oopSize);
7013 ldr(t, Address(rthread, t));
7014 cmp(obj, t);
7015 br(Assembler::EQ, push);
7016
7017 // Check header for monitor (0b10).
7018 tst(mark, markWord::monitor_value);
7019 br(Assembler::NE, slow);
7020
7021 // Try to lock. Transition lock bits 0b01 => 0b00
7022 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7023 orr(mark, mark, markWord::unlocked_value);
7024 eor(t, mark, markWord::unlocked_value);
7025 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
7026 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
7027 br(Assembler::NE, slow);
7028
7029 bind(push);
7030 // After successful lock, push object on lock-stack.
7031 str(obj, Address(rthread, top));
7032 addw(top, top, oopSize);
7033 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7034 }
7035
7036 // Implements fast-unlocking.
7037 //
7038 // - obj: the object to be unlocked
7039 // - t1, t2, t3: temporary registers
7040 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
7041 void MacroAssembler::fast_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
7042 // cmpxchg clobbers rscratch1.
7043 assert_different_registers(obj, t1, t2, t3, rscratch1);
7044
7045 #ifdef ASSERT
7046 {
7047 // Check for lock-stack underflow.
7048 Label stack_ok;
7049 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
7050 cmpw(t1, (unsigned)LockStack::start_offset());
7051 br(Assembler::GE, stack_ok);
7052 STOP("Lock-stack underflow");
7053 bind(stack_ok);
7054 }
7055 #endif
7056
7057 Label unlocked, push_and_slow;
7058 const Register top = t1;
7059 const Register mark = t2;
7060 const Register t = t3;
7061
7062 // Check if obj is top of lock-stack.
7063 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7064 subw(top, top, oopSize);
7065 ldr(t, Address(rthread, top));
7066 cmp(obj, t);
7067 br(Assembler::NE, slow);
7068
7069 // Pop lock-stack.
7070 DEBUG_ONLY(str(zr, Address(rthread, top));)
7071 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7072
7073 // Check if recursive.
7074 subw(t, top, oopSize);
7075 ldr(t, Address(rthread, t));
7076 cmp(obj, t);
7077 br(Assembler::EQ, unlocked);
7078
7079 // Not recursive. Check header for monitor (0b10).
7080 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7081 tbnz(mark, log2i_exact(markWord::monitor_value), push_and_slow);
7082
7083 #ifdef ASSERT
7084 // Check header not unlocked (0b01).
7085 Label not_unlocked;
7086 tbz(mark, log2i_exact(markWord::unlocked_value), not_unlocked);
7087 stop("fast_unlock already unlocked");
7088 bind(not_unlocked);
7089 #endif
7090
7091 // Try to unlock. Transition lock bits 0b00 => 0b01
7092 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7093 orr(t, mark, markWord::unlocked_value);
7094 cmpxchg(obj, mark, t, Assembler::xword,
7095 /*acquire*/ false, /*release*/ true, /*weak*/ false, noreg);
7096 br(Assembler::EQ, unlocked);
7097
7098 bind(push_and_slow);
7099 // Restore lock-stack and handle the unlock in runtime.
7100 DEBUG_ONLY(str(obj, Address(rthread, top));)
7101 addw(top, top, oopSize);
7102 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7103 b(slow);
7104
7105 bind(unlocked);
7106 }