1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "ci/ciEnv.hpp"
29 #include "ci/ciUtilities.hpp"
30 #include "code/compiledIC.hpp"
31 #include "compiler/compileTask.hpp"
32 #include "compiler/disassembler.hpp"
33 #include "compiler/oopMap.hpp"
34 #include "gc/shared/barrierSet.hpp"
35 #include "gc/shared/barrierSetAssembler.hpp"
36 #include "gc/shared/cardTableBarrierSet.hpp"
37 #include "gc/shared/cardTable.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/tlab_globals.hpp"
40 #include "interpreter/bytecodeHistogram.hpp"
41 #include "interpreter/interpreter.hpp"
42 #include "interpreter/interpreterRuntime.hpp"
43 #include "jvm.h"
44 #include "memory/resourceArea.hpp"
45 #include "memory/universe.hpp"
46 #include "nativeInst_aarch64.hpp"
47 #include "oops/accessDecorators.hpp"
48 #include "oops/compressedKlass.inline.hpp"
49 #include "oops/compressedOops.inline.hpp"
50 #include "oops/klass.inline.hpp"
51 #include "runtime/continuation.hpp"
52 #include "runtime/icache.hpp"
53 #include "runtime/interfaceSupport.inline.hpp"
54 #include "runtime/javaThread.hpp"
55 #include "runtime/jniHandles.inline.hpp"
56 #include "runtime/sharedRuntime.hpp"
57 #include "runtime/stubRoutines.hpp"
58 #include "utilities/globalDefinitions.hpp"
59 #include "utilities/powerOfTwo.hpp"
60 #ifdef COMPILER1
61 #include "c1/c1_LIRAssembler.hpp"
62 #endif
63 #ifdef COMPILER2
64 #include "oops/oop.hpp"
65 #include "opto/compile.hpp"
66 #include "opto/node.hpp"
67 #include "opto/output.hpp"
68 #endif
69
70 #include <sys/types.h>
71
72 #ifdef PRODUCT
73 #define BLOCK_COMMENT(str) /* nothing */
74 #else
75 #define BLOCK_COMMENT(str) block_comment(str)
76 #endif
77 #define STOP(str) stop(str);
78 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
79
80 #ifdef ASSERT
81 extern "C" void disnm(intptr_t p);
82 #endif
83 // Target-dependent relocation processing
84 //
85 // Instruction sequences whose target may need to be retrieved or
86 // patched are distinguished by their leading instruction, sorting
87 // them into three main instruction groups and related subgroups.
88 //
89 // 1) Branch, Exception and System (insn count = 1)
90 // 1a) Unconditional branch (immediate):
91 // b/bl imm19
92 // 1b) Compare & branch (immediate):
93 // cbz/cbnz Rt imm19
94 // 1c) Test & branch (immediate):
95 // tbz/tbnz Rt imm14
96 // 1d) Conditional branch (immediate):
97 // b.cond imm19
98 //
99 // 2) Loads and Stores (insn count = 1)
100 // 2a) Load register literal:
101 // ldr Rt imm19
102 //
103 // 3) Data Processing Immediate (insn count = 2 or 3)
104 // 3a) PC-rel. addressing
105 // adr/adrp Rx imm21; ldr/str Ry Rx #imm12
106 // adr/adrp Rx imm21; add Ry Rx #imm12
107 // adr/adrp Rx imm21; movk Rx #imm16<<32; ldr/str Ry, [Rx, #offset_in_page]
108 // adr/adrp Rx imm21
109 // adr/adrp Rx imm21; movk Rx #imm16<<32
110 // adr/adrp Rx imm21; movk Rx #imm16<<32; add Ry, Rx, #offset_in_page
111 // The latter form can only happen when the target is an
112 // ExternalAddress, and (by definition) ExternalAddresses don't
113 // move. Because of that property, there is never any need to
114 // patch the last of the three instructions. However,
115 // MacroAssembler::target_addr_for_insn takes all three
116 // instructions into account and returns the correct address.
117 // 3b) Move wide (immediate)
118 // movz Rx #imm16; movk Rx #imm16 << 16; movk Rx #imm16 << 32;
119 //
120 // A switch on a subset of the instruction's bits provides an
121 // efficient dispatch to these subcases.
122 //
123 // insn[28:26] -> main group ('x' == don't care)
124 // 00x -> UNALLOCATED
125 // 100 -> Data Processing Immediate
126 // 101 -> Branch, Exception and System
127 // x1x -> Loads and Stores
128 //
129 // insn[30:25] -> subgroup ('_' == group, 'x' == don't care).
130 // n.b. in some cases extra bits need to be checked to verify the
131 // instruction is as expected
132 //
133 // 1) ... xx101x Branch, Exception and System
134 // 1a) 00___x Unconditional branch (immediate)
135 // 1b) 01___0 Compare & branch (immediate)
136 // 1c) 01___1 Test & branch (immediate)
137 // 1d) 10___0 Conditional branch (immediate)
138 // other Should not happen
139 //
140 // 2) ... xxx1x0 Loads and Stores
141 // 2a) xx1__00 Load/Store register (insn[28] == 1 && insn[24] == 0)
142 // 2aa) x01__00 Load register literal (i.e. requires insn[29] == 0)
143 // strictly should be 64 bit non-FP/SIMD i.e.
144 // 0101_000 (i.e. requires insn[31:24] == 01011000)
145 //
146 // 3) ... xx100x Data Processing Immediate
147 // 3a) xx___00 PC-rel. addressing (n.b. requires insn[24] == 0)
148 // 3b) xx___101 Move wide (immediate) (n.b. requires insn[24:23] == 01)
149 // strictly should be 64 bit movz #imm16<<0
150 // 110___10100 (i.e. requires insn[31:21] == 11010010100)
151 //
152
153 static uint32_t insn_at(address insn_addr, int n) {
154 return ((uint32_t*)insn_addr)[n];
155 }
156
157 template<typename T>
158 class RelocActions : public AllStatic {
159
160 public:
161
162 static int ALWAYSINLINE run(address insn_addr, address &target) {
163 int instructions = 1;
164 uint32_t insn = insn_at(insn_addr, 0);
165
166 uint32_t dispatch = Instruction_aarch64::extract(insn, 30, 25);
167 switch(dispatch) {
168 case 0b001010:
169 case 0b001011: {
170 instructions = T::unconditionalBranch(insn_addr, target);
171 break;
172 }
173 case 0b101010: // Conditional branch (immediate)
174 case 0b011010: { // Compare & branch (immediate)
175 instructions = T::conditionalBranch(insn_addr, target);
176 break;
177 }
178 case 0b011011: {
179 instructions = T::testAndBranch(insn_addr, target);
180 break;
181 }
182 case 0b001100:
183 case 0b001110:
184 case 0b011100:
185 case 0b011110:
186 case 0b101100:
187 case 0b101110:
188 case 0b111100:
189 case 0b111110: {
190 // load/store
191 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
192 // Load register (literal)
193 instructions = T::loadStore(insn_addr, target);
194 break;
195 } else {
196 // nothing to do
197 assert(target == nullptr, "did not expect to relocate target for polling page load");
198 }
199 break;
200 }
201 case 0b001000:
202 case 0b011000:
203 case 0b101000:
204 case 0b111000: {
205 // adr/adrp
206 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
207 int shift = Instruction_aarch64::extract(insn, 31, 31);
208 if (shift) {
209 uint32_t insn2 = insn_at(insn_addr, 1);
210 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
211 Instruction_aarch64::extract(insn, 4, 0) ==
212 Instruction_aarch64::extract(insn2, 9, 5)) {
213 instructions = T::adrp(insn_addr, target, T::adrpMem);
214 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
215 Instruction_aarch64::extract(insn, 4, 0) ==
216 Instruction_aarch64::extract(insn2, 4, 0)) {
217 instructions = T::adrp(insn_addr, target, T::adrpAdd);
218 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
219 Instruction_aarch64::extract(insn, 4, 0) ==
220 Instruction_aarch64::extract(insn2, 4, 0)) {
221 instructions = T::adrp(insn_addr, target, T::adrpMovk);
222 } else {
223 ShouldNotReachHere();
224 }
225 } else {
226 instructions = T::adr(insn_addr, target);
227 }
228 break;
229 }
230 case 0b001001:
231 case 0b011001:
232 case 0b101001:
233 case 0b111001: {
234 instructions = T::immediate(insn_addr, target);
235 break;
236 }
237 default: {
238 ShouldNotReachHere();
239 }
240 }
241
242 T::verify(insn_addr, target);
243 return instructions * NativeInstruction::instruction_size;
244 }
245 };
246
247 class Patcher : public AllStatic {
248 public:
249 static int unconditionalBranch(address insn_addr, address &target) {
250 intptr_t offset = (target - insn_addr) >> 2;
251 Instruction_aarch64::spatch(insn_addr, 25, 0, offset);
252 return 1;
253 }
254 static int conditionalBranch(address insn_addr, address &target) {
255 intptr_t offset = (target - insn_addr) >> 2;
256 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
257 return 1;
258 }
259 static int testAndBranch(address insn_addr, address &target) {
260 intptr_t offset = (target - insn_addr) >> 2;
261 Instruction_aarch64::spatch(insn_addr, 18, 5, offset);
262 return 1;
263 }
264 static int loadStore(address insn_addr, address &target) {
265 intptr_t offset = (target - insn_addr) >> 2;
266 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
267 return 1;
268 }
269 static int adr(address insn_addr, address &target) {
270 #ifdef ASSERT
271 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
272 #endif
273 // PC-rel. addressing
274 ptrdiff_t offset = target - insn_addr;
275 int offset_lo = offset & 3;
276 offset >>= 2;
277 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
278 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
279 return 1;
280 }
281 template<typename U>
282 static int adrp(address insn_addr, address &target, U inner) {
283 int instructions = 1;
284 #ifdef ASSERT
285 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
286 #endif
287 ptrdiff_t offset = target - insn_addr;
288 instructions = 2;
289 precond(inner != nullptr);
290 // Give the inner reloc a chance to modify the target.
291 address adjusted_target = target;
292 instructions = inner(insn_addr, adjusted_target);
293 uintptr_t pc_page = (uintptr_t)insn_addr >> 12;
294 uintptr_t adr_page = (uintptr_t)adjusted_target >> 12;
295 offset = adr_page - pc_page;
296 int offset_lo = offset & 3;
297 offset >>= 2;
298 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
299 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
300 return instructions;
301 }
302 static int adrpMem(address insn_addr, address &target) {
303 uintptr_t dest = (uintptr_t)target;
304 int offset_lo = dest & 0xfff;
305 uint32_t insn2 = insn_at(insn_addr, 1);
306 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
307 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo >> size);
308 guarantee(((dest >> size) << size) == dest, "misaligned target");
309 return 2;
310 }
311 static int adrpAdd(address insn_addr, address &target) {
312 uintptr_t dest = (uintptr_t)target;
313 int offset_lo = dest & 0xfff;
314 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo);
315 return 2;
316 }
317 static int adrpMovk(address insn_addr, address &target) {
318 uintptr_t dest = uintptr_t(target);
319 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 20, 5, (uintptr_t)target >> 32);
320 dest = (dest & 0xffffffffULL) | (uintptr_t(insn_addr) & 0xffff00000000ULL);
321 target = address(dest);
322 return 2;
323 }
324 static int immediate(address insn_addr, address &target) {
325 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
326 // We encode narrow ones by setting the upper 16 bits in the first
327 // instruction.
328 if (Instruction_aarch64::extract(insn_at(insn_addr, 0), 31, 21) == 0b11010010101) {
329 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
330 narrowKlass nk = CompressedKlassPointers::encode((Klass*)target);
331 Instruction_aarch64::patch(insn_addr, 20, 5, nk >> 16);
332 Instruction_aarch64::patch(insn_addr+4, 20, 5, nk & 0xffff);
333 return 2;
334 }
335 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 31, 21) == 0b11010010100, "must be");
336 uint64_t dest = (uint64_t)target;
337 // Move wide constant
338 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
339 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
340 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
341 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
342 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
343 return 3;
344 }
345 static void verify(address insn_addr, address &target) {
346 #ifdef ASSERT
347 address address_is = MacroAssembler::target_addr_for_insn(insn_addr);
348 if (!(address_is == target)) {
349 tty->print_cr("%p at %p should be %p", address_is, insn_addr, target);
350 disnm((intptr_t)insn_addr);
351 assert(address_is == target, "should be");
352 }
353 #endif
354 }
355 };
356
357 // If insn1 and insn2 use the same register to form an address, either
358 // by an offsetted LDR or a simple ADD, return the offset. If the
359 // second instruction is an LDR, the offset may be scaled.
360 static bool offset_for(uint32_t insn1, uint32_t insn2, ptrdiff_t &byte_offset) {
361 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
362 Instruction_aarch64::extract(insn1, 4, 0) ==
363 Instruction_aarch64::extract(insn2, 9, 5)) {
364 // Load/store register (unsigned immediate)
365 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
366 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
367 byte_offset <<= size;
368 return true;
369 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
370 Instruction_aarch64::extract(insn1, 4, 0) ==
371 Instruction_aarch64::extract(insn2, 4, 0)) {
372 // add (immediate)
373 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
374 return true;
375 }
376 return false;
377 }
378
379 class AArch64Decoder : public AllStatic {
380 public:
381
382 static int loadStore(address insn_addr, address &target) {
383 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
384 target = insn_addr + (offset << 2);
385 return 1;
386 }
387 static int unconditionalBranch(address insn_addr, address &target) {
388 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 25, 0);
389 target = insn_addr + (offset << 2);
390 return 1;
391 }
392 static int conditionalBranch(address insn_addr, address &target) {
393 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
394 target = address(((uint64_t)insn_addr + (offset << 2)));
395 return 1;
396 }
397 static int testAndBranch(address insn_addr, address &target) {
398 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 18, 5);
399 target = address(((uint64_t)insn_addr + (offset << 2)));
400 return 1;
401 }
402 static int adr(address insn_addr, address &target) {
403 // PC-rel. addressing
404 uint32_t insn = insn_at(insn_addr, 0);
405 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
406 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
407 target = address((uint64_t)insn_addr + offset);
408 return 1;
409 }
410 template<typename U>
411 static int adrp(address insn_addr, address &target, U inner) {
412 uint32_t insn = insn_at(insn_addr, 0);
413 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
414 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
415 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
416 int shift = 12;
417 offset <<= shift;
418 uint64_t target_page = ((uint64_t)insn_addr) + offset;
419 target_page &= ((uint64_t)-1) << shift;
420 target = address(target_page);
421 precond(inner != nullptr);
422 inner(insn_addr, target);
423 return 2;
424 }
425 static int adrpMem(address insn_addr, address &target) {
426 uint32_t insn2 = insn_at(insn_addr, 1);
427 // Load/store register (unsigned immediate)
428 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
429 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
430 byte_offset <<= size;
431 target += byte_offset;
432 return 2;
433 }
434 static int adrpAdd(address insn_addr, address &target) {
435 uint32_t insn2 = insn_at(insn_addr, 1);
436 // add (immediate)
437 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
438 target += byte_offset;
439 return 2;
440 }
441 static int adrpMovk(address insn_addr, address &target) {
442 uint32_t insn2 = insn_at(insn_addr, 1);
443 uint64_t dest = uint64_t(target);
444 dest = (dest & 0xffff0000ffffffff) |
445 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
446 target = address(dest);
447
448 // We know the destination 4k page. Maybe we have a third
449 // instruction.
450 uint32_t insn = insn_at(insn_addr, 0);
451 uint32_t insn3 = insn_at(insn_addr, 2);
452 ptrdiff_t byte_offset;
453 if (offset_for(insn, insn3, byte_offset)) {
454 target += byte_offset;
455 return 3;
456 } else {
457 return 2;
458 }
459 }
460 static int immediate(address insn_addr, address &target) {
461 uint32_t *insns = (uint32_t *)insn_addr;
462 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
463 // We encode narrow ones by setting the upper 16 bits in the first
464 // instruction.
465 if (Instruction_aarch64::extract(insns[0], 31, 21) == 0b11010010101) {
466 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
467 narrowKlass nk = (narrowKlass)((uint32_t(Instruction_aarch64::extract(insns[0], 20, 5)) << 16)
468 + uint32_t(Instruction_aarch64::extract(insns[1], 20, 5)));
469 target = (address)CompressedKlassPointers::decode(nk);
470 return 2;
471 }
472 assert(Instruction_aarch64::extract(insns[0], 31, 21) == 0b11010010100, "must be");
473 // Move wide constant: movz, movk, movk. See movptr().
474 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
475 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
476 target = address(uint64_t(Instruction_aarch64::extract(insns[0], 20, 5))
477 + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
478 + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
479 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
480 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
481 return 3;
482 }
483 static void verify(address insn_addr, address &target) {
484 }
485 };
486
487 address MacroAssembler::target_addr_for_insn(address insn_addr) {
488 address target;
489 RelocActions<AArch64Decoder>::run(insn_addr, target);
490 return target;
491 }
492
493 // Patch any kind of instruction; there may be several instructions.
494 // Return the total length (in bytes) of the instructions.
495 int MacroAssembler::pd_patch_instruction_size(address insn_addr, address target) {
496 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
497 return RelocActions<Patcher>::run(insn_addr, target);
498 }
499
500 int MacroAssembler::patch_oop(address insn_addr, address o) {
501 int instructions;
502 unsigned insn = *(unsigned*)insn_addr;
503 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
504
505 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
506
507 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
508 // narrow OOPs by setting the upper 16 bits in the first
509 // instruction.
510 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
511 // Move narrow OOP
512 uint32_t n = CompressedOops::narrow_oop_value(cast_to_oop(o));
513 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
514 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
515 instructions = 2;
516 } else {
517 // Move wide OOP
518 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
519 uintptr_t dest = (uintptr_t)o;
520 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
521 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
522 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
523 instructions = 3;
524 }
525 return instructions * NativeInstruction::instruction_size;
526 }
527
528 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
529 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
530 // We encode narrow ones by setting the upper 16 bits in the first
531 // instruction.
532 NativeInstruction *insn = nativeInstruction_at(insn_addr);
533 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 &&
534 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
535
536 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
537
538 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
539 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
540 return 2 * NativeInstruction::instruction_size;
541 }
542
543 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp) {
544 ldr(tmp, Address(rthread, JavaThread::polling_word_offset()));
545 if (at_return) {
546 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
547 // we may safely use the sp instead to perform the stack watermark check.
548 cmp(in_nmethod ? sp : rfp, tmp);
549 br(Assembler::HI, slow_path);
550 } else {
551 tbnz(tmp, log2i_exact(SafepointMechanism::poll_bit()), slow_path);
552 }
553 }
554
555 void MacroAssembler::rt_call(address dest, Register tmp) {
556 CodeBlob *cb = CodeCache::find_blob(dest);
557 if (cb) {
558 far_call(RuntimeAddress(dest));
559 } else {
560 lea(tmp, RuntimeAddress(dest));
561 blr(tmp);
562 }
563 }
564
565 void MacroAssembler::push_cont_fastpath(Register java_thread) {
566 if (!Continuations::enabled()) return;
567 Label done;
568 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
569 cmp(sp, rscratch1);
570 br(Assembler::LS, done);
571 mov(rscratch1, sp); // we can't use sp as the source in str
572 str(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
573 bind(done);
574 }
575
576 void MacroAssembler::pop_cont_fastpath(Register java_thread) {
577 if (!Continuations::enabled()) return;
578 Label done;
579 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
580 cmp(sp, rscratch1);
581 br(Assembler::LO, done);
582 str(zr, Address(java_thread, JavaThread::cont_fastpath_offset()));
583 bind(done);
584 }
585
586 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
587 // we must set sp to zero to clear frame
588 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
589
590 // must clear fp, so that compiled frames are not confused; it is
591 // possible that we need it only for debugging
592 if (clear_fp) {
593 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
594 }
595
596 // Always clear the pc because it could have been set by make_walkable()
597 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
598 }
599
600 // Calls to C land
601 //
602 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
603 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
604 // has to be reset to 0. This is required to allow proper stack traversal.
605 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
606 Register last_java_fp,
607 Register last_java_pc,
608 Register scratch) {
609
610 if (last_java_pc->is_valid()) {
611 str(last_java_pc, Address(rthread,
612 JavaThread::frame_anchor_offset()
613 + JavaFrameAnchor::last_Java_pc_offset()));
614 }
615
616 // determine last_java_sp register
617 if (last_java_sp == sp) {
618 mov(scratch, sp);
619 last_java_sp = scratch;
620 } else if (!last_java_sp->is_valid()) {
621 last_java_sp = esp;
622 }
623
624 // last_java_fp is optional
625 if (last_java_fp->is_valid()) {
626 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
627 }
628
629 // We must set sp last.
630 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
631 }
632
633 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
634 Register last_java_fp,
635 address last_java_pc,
636 Register scratch) {
637 assert(last_java_pc != nullptr, "must provide a valid PC");
638
639 adr(scratch, last_java_pc);
640 str(scratch, Address(rthread,
641 JavaThread::frame_anchor_offset()
642 + JavaFrameAnchor::last_Java_pc_offset()));
643
644 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
645 }
646
647 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
648 Register last_java_fp,
649 Label &L,
650 Register scratch) {
651 if (L.is_bound()) {
652 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
653 } else {
654 InstructionMark im(this);
655 L.add_patch_at(code(), locator());
656 set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, scratch);
657 }
658 }
659
660 static inline bool target_needs_far_branch(address addr) {
661 if (AOTCodeCache::is_on_for_dump()) {
662 return true;
663 }
664 // codecache size <= 128M
665 if (!MacroAssembler::far_branches()) {
666 return false;
667 }
668 // codecache size > 240M
669 if (MacroAssembler::codestub_branch_needs_far_jump()) {
670 return true;
671 }
672 // codecache size: 128M..240M
673 return !CodeCache::is_non_nmethod(addr);
674 }
675
676 void MacroAssembler::far_call(Address entry, Register tmp) {
677 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
678 assert(CodeCache::find_blob(entry.target()) != nullptr,
679 "destination of far call not found in code cache");
680 assert(entry.rspec().type() == relocInfo::external_word_type
681 || entry.rspec().type() == relocInfo::runtime_call_type
682 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
683 if (target_needs_far_branch(entry.target())) {
684 uint64_t offset;
685 // We can use ADRP here because we know that the total size of
686 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
687 adrp(tmp, entry, offset);
688 add(tmp, tmp, offset);
689 blr(tmp);
690 } else {
691 bl(entry);
692 }
693 }
694
695 int MacroAssembler::far_jump(Address entry, Register tmp) {
696 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
697 assert(CodeCache::find_blob(entry.target()) != nullptr,
698 "destination of far call not found in code cache");
699 assert(entry.rspec().type() == relocInfo::external_word_type
700 || entry.rspec().type() == relocInfo::runtime_call_type
701 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
702 address start = pc();
703 if (target_needs_far_branch(entry.target())) {
704 uint64_t offset;
705 // We can use ADRP here because we know that the total size of
706 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
707 adrp(tmp, entry, offset);
708 add(tmp, tmp, offset);
709 br(tmp);
710 } else {
711 b(entry);
712 }
713 return pc() - start;
714 }
715
716 void MacroAssembler::reserved_stack_check() {
717 // testing if reserved zone needs to be enabled
718 Label no_reserved_zone_enabling;
719
720 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset()));
721 cmp(sp, rscratch1);
722 br(Assembler::LO, no_reserved_zone_enabling);
723
724 enter(); // LR and FP are live.
725 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone)));
726 mov(c_rarg0, rthread);
727 blr(rscratch1);
728 leave();
729
730 // We have already removed our own frame.
731 // throw_delayed_StackOverflowError will think that it's been
732 // called by our caller.
733 lea(rscratch1, RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
734 br(rscratch1);
735 should_not_reach_here();
736
737 bind(no_reserved_zone_enabling);
738 }
739
740 static void pass_arg0(MacroAssembler* masm, Register arg) {
741 if (c_rarg0 != arg ) {
742 masm->mov(c_rarg0, arg);
743 }
744 }
745
746 static void pass_arg1(MacroAssembler* masm, Register arg) {
747 if (c_rarg1 != arg ) {
748 masm->mov(c_rarg1, arg);
749 }
750 }
751
752 static void pass_arg2(MacroAssembler* masm, Register arg) {
753 if (c_rarg2 != arg ) {
754 masm->mov(c_rarg2, arg);
755 }
756 }
757
758 static void pass_arg3(MacroAssembler* masm, Register arg) {
759 if (c_rarg3 != arg ) {
760 masm->mov(c_rarg3, arg);
761 }
762 }
763
764 void MacroAssembler::call_VM_base(Register oop_result,
765 Register java_thread,
766 Register last_java_sp,
767 Label* return_pc,
768 address entry_point,
769 int number_of_arguments,
770 bool check_exceptions) {
771 // determine java_thread register
772 if (!java_thread->is_valid()) {
773 java_thread = rthread;
774 }
775
776 // determine last_java_sp register
777 if (!last_java_sp->is_valid()) {
778 last_java_sp = esp;
779 }
780
781 // debugging support
782 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
783 assert(java_thread == rthread, "unexpected register");
784 #ifdef ASSERT
785 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
786 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
787 #endif // ASSERT
788
789 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
790 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
791
792 // push java thread (becomes first argument of C function)
793
794 mov(c_rarg0, java_thread);
795
796 // set last Java frame before call
797 assert(last_java_sp != rfp, "can't use rfp");
798
799 Label l;
800 set_last_Java_frame(last_java_sp, rfp, return_pc != nullptr ? *return_pc : l, rscratch1);
801
802 // do the call, remove parameters
803 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
804
805 // lr could be poisoned with PAC signature during throw_pending_exception
806 // if it was tail-call optimized by compiler, since lr is not callee-saved
807 // reload it with proper value
808 adr(lr, l);
809
810 // reset last Java frame
811 // Only interpreter should have to clear fp
812 reset_last_Java_frame(true);
813
814 // C++ interp handles this in the interpreter
815 check_and_handle_popframe(java_thread);
816 check_and_handle_earlyret(java_thread);
817
818 if (check_exceptions) {
819 // check for pending exceptions (java_thread is set upon return)
820 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
821 Label ok;
822 cbz(rscratch1, ok);
823 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
824 br(rscratch1);
825 bind(ok);
826 }
827
828 // get oop result if there is one and reset the value in the thread
829 if (oop_result->is_valid()) {
830 get_vm_result_oop(oop_result, java_thread);
831 }
832 }
833
834 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
835 call_VM_base(oop_result, noreg, noreg, nullptr, entry_point, number_of_arguments, check_exceptions);
836 }
837
838 // Check the entry target is always reachable from any branch.
839 static bool is_always_within_branch_range(Address entry) {
840 if (AOTCodeCache::is_on_for_dump()) {
841 return false;
842 }
843 const address target = entry.target();
844
845 if (!CodeCache::contains(target)) {
846 // We always use trampolines for callees outside CodeCache.
847 assert(entry.rspec().type() == relocInfo::runtime_call_type, "non-runtime call of an external target");
848 return false;
849 }
850
851 if (!MacroAssembler::far_branches()) {
852 return true;
853 }
854
855 if (entry.rspec().type() == relocInfo::runtime_call_type) {
856 // Runtime calls are calls of a non-compiled method (stubs, adapters).
857 // Non-compiled methods stay forever in CodeCache.
858 // We check whether the longest possible branch is within the branch range.
859 assert(CodeCache::find_blob(target) != nullptr &&
860 !CodeCache::find_blob(target)->is_nmethod(),
861 "runtime call of compiled method");
862 const address right_longest_branch_start = CodeCache::high_bound() - NativeInstruction::instruction_size;
863 const address left_longest_branch_start = CodeCache::low_bound();
864 const bool is_reachable = Assembler::reachable_from_branch_at(left_longest_branch_start, target) &&
865 Assembler::reachable_from_branch_at(right_longest_branch_start, target);
866 return is_reachable;
867 }
868
869 return false;
870 }
871
872 // Maybe emit a call via a trampoline. If the code cache is small
873 // trampolines won't be emitted.
874 address MacroAssembler::trampoline_call(Address entry) {
875 assert(entry.rspec().type() == relocInfo::runtime_call_type
876 || entry.rspec().type() == relocInfo::opt_virtual_call_type
877 || entry.rspec().type() == relocInfo::static_call_type
878 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
879
880 address target = entry.target();
881
882 if (!is_always_within_branch_range(entry)) {
883 if (!in_scratch_emit_size()) {
884 // We don't want to emit a trampoline if C2 is generating dummy
885 // code during its branch shortening phase.
886 if (entry.rspec().type() == relocInfo::runtime_call_type) {
887 assert(CodeBuffer::supports_shared_stubs(), "must support shared stubs");
888 code()->share_trampoline_for(entry.target(), offset());
889 } else {
890 address stub = emit_trampoline_stub(offset(), target);
891 if (stub == nullptr) {
892 postcond(pc() == badAddress);
893 return nullptr; // CodeCache is full
894 }
895 }
896 }
897 target = pc();
898 }
899
900 address call_pc = pc();
901 relocate(entry.rspec());
902 bl(target);
903
904 postcond(pc() != badAddress);
905 return call_pc;
906 }
907
908 // Emit a trampoline stub for a call to a target which is too far away.
909 //
910 // code sequences:
911 //
912 // call-site:
913 // branch-and-link to <destination> or <trampoline stub>
914 //
915 // Related trampoline stub for this call site in the stub section:
916 // load the call target from the constant pool
917 // branch (LR still points to the call site above)
918
919 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
920 address dest) {
921 // Max stub size: alignment nop, TrampolineStub.
922 address stub = start_a_stub(max_trampoline_stub_size());
923 if (stub == nullptr) {
924 return nullptr; // CodeBuffer::expand failed
925 }
926
927 // Create a trampoline stub relocation which relates this trampoline stub
928 // with the call instruction at insts_call_instruction_offset in the
929 // instructions code-section.
930 align(wordSize);
931 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
932 + insts_call_instruction_offset));
933 const int stub_start_offset = offset();
934
935 // Now, create the trampoline stub's code:
936 // - load the call
937 // - call
938 Label target;
939 ldr(rscratch1, target);
940 br(rscratch1);
941 bind(target);
942 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
943 "should be");
944 emit_int64((int64_t)dest);
945
946 const address stub_start_addr = addr_at(stub_start_offset);
947
948 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
949
950 end_a_stub();
951 return stub_start_addr;
952 }
953
954 int MacroAssembler::max_trampoline_stub_size() {
955 // Max stub size: alignment nop, TrampolineStub.
956 return NativeInstruction::instruction_size + NativeCallTrampolineStub::instruction_size;
957 }
958
959 void MacroAssembler::emit_static_call_stub() {
960 // CompiledDirectCall::set_to_interpreted knows the
961 // exact layout of this stub.
962
963 isb();
964 mov_metadata(rmethod, nullptr);
965
966 // Jump to the entry point of the c2i stub.
967 if (codestub_branch_needs_far_jump()) {
968 movptr(rscratch1, 0);
969 br(rscratch1);
970 } else {
971 b(pc());
972 }
973 }
974
975 int MacroAssembler::max_static_call_stub_size() {
976 // isb; movk; movz; movz; movk; movz; movz; br
977 return 8 * NativeInstruction::instruction_size;
978 }
979
980 void MacroAssembler::c2bool(Register x) {
981 // implements x == 0 ? 0 : 1
982 // note: must only look at least-significant byte of x
983 // since C-style booleans are stored in one byte
984 // only! (was bug)
985 tst(x, 0xff);
986 cset(x, Assembler::NE);
987 }
988
989 address MacroAssembler::ic_call(address entry, jint method_index) {
990 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
991 movptr(rscratch2, (intptr_t)Universe::non_oop_word());
992 return trampoline_call(Address(entry, rh));
993 }
994
995 int MacroAssembler::ic_check_size() {
996 int extra_instructions = UseCompactObjectHeaders ? 1 : 0;
997 if (target_needs_far_branch(CAST_FROM_FN_PTR(address, SharedRuntime::get_ic_miss_stub()))) {
998 return NativeInstruction::instruction_size * (7 + extra_instructions);
999 } else {
1000 return NativeInstruction::instruction_size * (5 + extra_instructions);
1001 }
1002 }
1003
1004 int MacroAssembler::ic_check(int end_alignment) {
1005 Register receiver = j_rarg0;
1006 Register data = rscratch2;
1007 Register tmp1 = rscratch1;
1008 Register tmp2 = r10;
1009
1010 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1011 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1012 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1013 // before the inline cache check here, and not after
1014 align(end_alignment, offset() + ic_check_size());
1015
1016 int uep_offset = offset();
1017
1018 if (UseCompactObjectHeaders) {
1019 load_narrow_klass_compact(tmp1, receiver);
1020 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1021 cmpw(tmp1, tmp2);
1022 } else if (UseCompressedClassPointers) {
1023 ldrw(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1024 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1025 cmpw(tmp1, tmp2);
1026 } else {
1027 ldr(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1028 ldr(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1029 cmp(tmp1, tmp2);
1030 }
1031
1032 Label dont;
1033 br(Assembler::EQ, dont);
1034 far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1035 bind(dont);
1036 assert((offset() % end_alignment) == 0, "Misaligned verified entry point");
1037
1038 return uep_offset;
1039 }
1040
1041 // Implementation of call_VM versions
1042
1043 void MacroAssembler::call_VM(Register oop_result,
1044 address entry_point,
1045 bool check_exceptions) {
1046 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1047 }
1048
1049 void MacroAssembler::call_VM(Register oop_result,
1050 address entry_point,
1051 Register arg_1,
1052 bool check_exceptions) {
1053 pass_arg1(this, arg_1);
1054 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1055 }
1056
1057 void MacroAssembler::call_VM(Register oop_result,
1058 address entry_point,
1059 Register arg_1,
1060 Register arg_2,
1061 bool check_exceptions) {
1062 assert_different_registers(arg_1, c_rarg2);
1063 pass_arg2(this, arg_2);
1064 pass_arg1(this, arg_1);
1065 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1066 }
1067
1068 void MacroAssembler::call_VM(Register oop_result,
1069 address entry_point,
1070 Register arg_1,
1071 Register arg_2,
1072 Register arg_3,
1073 bool check_exceptions) {
1074 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1075 assert_different_registers(arg_2, c_rarg3);
1076 pass_arg3(this, arg_3);
1077
1078 pass_arg2(this, arg_2);
1079
1080 pass_arg1(this, arg_1);
1081 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1082 }
1083
1084 void MacroAssembler::call_VM(Register oop_result,
1085 Register last_java_sp,
1086 address entry_point,
1087 int number_of_arguments,
1088 bool check_exceptions) {
1089 call_VM_base(oop_result, rthread, last_java_sp, nullptr, entry_point, number_of_arguments, check_exceptions);
1090 }
1091
1092 void MacroAssembler::call_VM(Register oop_result,
1093 Register last_java_sp,
1094 address entry_point,
1095 Register arg_1,
1096 bool check_exceptions) {
1097 pass_arg1(this, arg_1);
1098 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1099 }
1100
1101 void MacroAssembler::call_VM(Register oop_result,
1102 Register last_java_sp,
1103 address entry_point,
1104 Register arg_1,
1105 Register arg_2,
1106 bool check_exceptions) {
1107
1108 assert_different_registers(arg_1, c_rarg2);
1109 pass_arg2(this, arg_2);
1110 pass_arg1(this, arg_1);
1111 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1112 }
1113
1114 void MacroAssembler::call_VM(Register oop_result,
1115 Register last_java_sp,
1116 address entry_point,
1117 Register arg_1,
1118 Register arg_2,
1119 Register arg_3,
1120 bool check_exceptions) {
1121 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1122 assert_different_registers(arg_2, c_rarg3);
1123 pass_arg3(this, arg_3);
1124 pass_arg2(this, arg_2);
1125 pass_arg1(this, arg_1);
1126 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1127 }
1128
1129
1130 void MacroAssembler::get_vm_result_oop(Register oop_result, Register java_thread) {
1131 ldr(oop_result, Address(java_thread, JavaThread::vm_result_oop_offset()));
1132 str(zr, Address(java_thread, JavaThread::vm_result_oop_offset()));
1133 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1134 }
1135
1136 void MacroAssembler::get_vm_result_metadata(Register metadata_result, Register java_thread) {
1137 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1138 str(zr, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1139 }
1140
1141 void MacroAssembler::align(int modulus) {
1142 align(modulus, offset());
1143 }
1144
1145 // Ensure that the code at target bytes offset from the current offset() is aligned
1146 // according to modulus.
1147 void MacroAssembler::align(int modulus, int target) {
1148 int delta = target - offset();
1149 while ((offset() + delta) % modulus != 0) nop();
1150 }
1151
1152 void MacroAssembler::post_call_nop() {
1153 if (!Continuations::enabled()) {
1154 return;
1155 }
1156 InstructionMark im(this);
1157 relocate(post_call_nop_Relocation::spec());
1158 InlineSkippedInstructionsCounter skipCounter(this);
1159 nop();
1160 movk(zr, 0);
1161 movk(zr, 0);
1162 }
1163
1164 // these are no-ops overridden by InterpreterMacroAssembler
1165
1166 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1167
1168 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1169
1170 // Look up the method for a megamorphic invokeinterface call.
1171 // The target method is determined by <intf_klass, itable_index>.
1172 // The receiver klass is in recv_klass.
1173 // On success, the result will be in method_result, and execution falls through.
1174 // On failure, execution transfers to the given label.
1175 void MacroAssembler::lookup_interface_method(Register recv_klass,
1176 Register intf_klass,
1177 RegisterOrConstant itable_index,
1178 Register method_result,
1179 Register scan_temp,
1180 Label& L_no_such_interface,
1181 bool return_method) {
1182 assert_different_registers(recv_klass, intf_klass, scan_temp);
1183 assert_different_registers(method_result, intf_klass, scan_temp);
1184 assert(recv_klass != method_result || !return_method,
1185 "recv_klass can be destroyed when method isn't needed");
1186 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1187 "caller must use same register for non-constant itable index as for method");
1188
1189 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1190 int vtable_base = in_bytes(Klass::vtable_start_offset());
1191 int itentry_off = in_bytes(itableMethodEntry::method_offset());
1192 int scan_step = itableOffsetEntry::size() * wordSize;
1193 int vte_size = vtableEntry::size_in_bytes();
1194 assert(vte_size == wordSize, "else adjust times_vte_scale");
1195
1196 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1197
1198 // Could store the aligned, prescaled offset in the klass.
1199 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
1200 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
1201 add(scan_temp, scan_temp, vtable_base);
1202
1203 if (return_method) {
1204 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1205 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1206 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
1207 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
1208 if (itentry_off)
1209 add(recv_klass, recv_klass, itentry_off);
1210 }
1211
1212 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
1213 // if (scan->interface() == intf) {
1214 // result = (klass + scan->offset() + itable_index);
1215 // }
1216 // }
1217 Label search, found_method;
1218
1219 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1220 cmp(intf_klass, method_result);
1221 br(Assembler::EQ, found_method);
1222 bind(search);
1223 // Check that the previous entry is non-null. A null entry means that
1224 // the receiver class doesn't implement the interface, and wasn't the
1225 // same as when the caller was compiled.
1226 cbz(method_result, L_no_such_interface);
1227 if (itableOffsetEntry::interface_offset() != 0) {
1228 add(scan_temp, scan_temp, scan_step);
1229 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1230 } else {
1231 ldr(method_result, Address(pre(scan_temp, scan_step)));
1232 }
1233 cmp(intf_klass, method_result);
1234 br(Assembler::NE, search);
1235
1236 bind(found_method);
1237
1238 // Got a hit.
1239 if (return_method) {
1240 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
1241 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0)));
1242 }
1243 }
1244
1245 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
1246 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
1247 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
1248 // The target method is determined by <holder_klass, itable_index>.
1249 // The receiver klass is in recv_klass.
1250 // On success, the result will be in method_result, and execution falls through.
1251 // On failure, execution transfers to the given label.
1252 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
1253 Register holder_klass,
1254 Register resolved_klass,
1255 Register method_result,
1256 Register temp_itbl_klass,
1257 Register scan_temp,
1258 int itable_index,
1259 Label& L_no_such_interface) {
1260 // 'method_result' is only used as output register at the very end of this method.
1261 // Until then we can reuse it as 'holder_offset'.
1262 Register holder_offset = method_result;
1263 assert_different_registers(resolved_klass, recv_klass, holder_klass, temp_itbl_klass, scan_temp, holder_offset);
1264
1265 int vtable_start_offset = in_bytes(Klass::vtable_start_offset());
1266 int itable_offset_entry_size = itableOffsetEntry::size() * wordSize;
1267 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
1268 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
1269
1270 Label L_loop_search_resolved_entry, L_resolved_found, L_holder_found;
1271
1272 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1273 add(recv_klass, recv_klass, vtable_start_offset + ioffset);
1274 // itableOffsetEntry[] itable = recv_klass + Klass::vtable_start_offset() + sizeof(vtableEntry) * recv_klass->_vtable_len;
1275 // temp_itbl_klass = itable[0]._interface;
1276 int vtblEntrySize = vtableEntry::size_in_bytes();
1277 assert(vtblEntrySize == wordSize, "ldr lsl shift amount must be 3");
1278 ldr(temp_itbl_klass, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1279 mov(holder_offset, zr);
1280 // scan_temp = &(itable[0]._interface)
1281 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1282
1283 // Initial checks:
1284 // - if (holder_klass != resolved_klass), go to "scan for resolved"
1285 // - if (itable[0] == holder_klass), shortcut to "holder found"
1286 // - if (itable[0] == 0), no such interface
1287 cmp(resolved_klass, holder_klass);
1288 br(Assembler::NE, L_loop_search_resolved_entry);
1289 cmp(holder_klass, temp_itbl_klass);
1290 br(Assembler::EQ, L_holder_found);
1291 cbz(temp_itbl_klass, L_no_such_interface);
1292
1293 // Loop: Look for holder_klass record in itable
1294 // do {
1295 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1296 // if (temp_itbl_klass == holder_klass) {
1297 // goto L_holder_found; // Found!
1298 // }
1299 // } while (temp_itbl_klass != 0);
1300 // goto L_no_such_interface // Not found.
1301 Label L_search_holder;
1302 bind(L_search_holder);
1303 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1304 cmp(holder_klass, temp_itbl_klass);
1305 br(Assembler::EQ, L_holder_found);
1306 cbnz(temp_itbl_klass, L_search_holder);
1307
1308 b(L_no_such_interface);
1309
1310 // Loop: Look for resolved_class record in itable
1311 // while (true) {
1312 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1313 // if (temp_itbl_klass == 0) {
1314 // goto L_no_such_interface;
1315 // }
1316 // if (temp_itbl_klass == resolved_klass) {
1317 // goto L_resolved_found; // Found!
1318 // }
1319 // if (temp_itbl_klass == holder_klass) {
1320 // holder_offset = scan_temp;
1321 // }
1322 // }
1323 //
1324 Label L_loop_search_resolved;
1325 bind(L_loop_search_resolved);
1326 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1327 bind(L_loop_search_resolved_entry);
1328 cbz(temp_itbl_klass, L_no_such_interface);
1329 cmp(resolved_klass, temp_itbl_klass);
1330 br(Assembler::EQ, L_resolved_found);
1331 cmp(holder_klass, temp_itbl_klass);
1332 br(Assembler::NE, L_loop_search_resolved);
1333 mov(holder_offset, scan_temp);
1334 b(L_loop_search_resolved);
1335
1336 // See if we already have a holder klass. If not, go and scan for it.
1337 bind(L_resolved_found);
1338 cbz(holder_offset, L_search_holder);
1339 mov(scan_temp, holder_offset);
1340
1341 // Finally, scan_temp contains holder_klass vtable offset
1342 bind(L_holder_found);
1343 ldrw(method_result, Address(scan_temp, ooffset - ioffset));
1344 add(recv_klass, recv_klass, itable_index * wordSize + in_bytes(itableMethodEntry::method_offset())
1345 - vtable_start_offset - ioffset); // substract offsets to restore the original value of recv_klass
1346 ldr(method_result, Address(recv_klass, method_result, Address::uxtw(0)));
1347 }
1348
1349 // virtual method calling
1350 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1351 RegisterOrConstant vtable_index,
1352 Register method_result) {
1353 assert(vtableEntry::size() * wordSize == 8,
1354 "adjust the scaling in the code below");
1355 int64_t vtable_offset_in_bytes = in_bytes(Klass::vtable_start_offset() + vtableEntry::method_offset());
1356
1357 if (vtable_index.is_register()) {
1358 lea(method_result, Address(recv_klass,
1359 vtable_index.as_register(),
1360 Address::lsl(LogBytesPerWord)));
1361 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
1362 } else {
1363 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
1364 ldr(method_result,
1365 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0));
1366 }
1367 }
1368
1369 void MacroAssembler::check_klass_subtype(Register sub_klass,
1370 Register super_klass,
1371 Register temp_reg,
1372 Label& L_success) {
1373 Label L_failure;
1374 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
1375 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
1376 bind(L_failure);
1377 }
1378
1379
1380 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1381 Register super_klass,
1382 Register temp_reg,
1383 Label* L_success,
1384 Label* L_failure,
1385 Label* L_slow_path,
1386 Register super_check_offset) {
1387 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset);
1388 bool must_load_sco = ! super_check_offset->is_valid();
1389 if (must_load_sco) {
1390 assert(temp_reg != noreg, "supply either a temp or a register offset");
1391 }
1392
1393 Label L_fallthrough;
1394 int label_nulls = 0;
1395 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1396 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1397 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
1398 assert(label_nulls <= 1, "at most one null in the batch");
1399
1400 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1401 Address super_check_offset_addr(super_klass, sco_offset);
1402
1403 // Hacked jmp, which may only be used just before L_fallthrough.
1404 #define final_jmp(label) \
1405 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1406 else b(label) /*omit semi*/
1407
1408 // If the pointers are equal, we are done (e.g., String[] elements).
1409 // This self-check enables sharing of secondary supertype arrays among
1410 // non-primary types such as array-of-interface. Otherwise, each such
1411 // type would need its own customized SSA.
1412 // We move this check to the front of the fast path because many
1413 // type checks are in fact trivially successful in this manner,
1414 // so we get a nicely predicted branch right at the start of the check.
1415 cmp(sub_klass, super_klass);
1416 br(Assembler::EQ, *L_success);
1417
1418 // Check the supertype display:
1419 if (must_load_sco) {
1420 ldrw(temp_reg, super_check_offset_addr);
1421 super_check_offset = temp_reg;
1422 }
1423
1424 Address super_check_addr(sub_klass, super_check_offset);
1425 ldr(rscratch1, super_check_addr);
1426 cmp(super_klass, rscratch1); // load displayed supertype
1427 br(Assembler::EQ, *L_success);
1428
1429 // This check has worked decisively for primary supers.
1430 // Secondary supers are sought in the super_cache ('super_cache_addr').
1431 // (Secondary supers are interfaces and very deeply nested subtypes.)
1432 // This works in the same check above because of a tricky aliasing
1433 // between the super_cache and the primary super display elements.
1434 // (The 'super_check_addr' can address either, as the case requires.)
1435 // Note that the cache is updated below if it does not help us find
1436 // what we need immediately.
1437 // So if it was a primary super, we can just fail immediately.
1438 // Otherwise, it's the slow path for us (no success at this point).
1439
1440 sub(rscratch1, super_check_offset, in_bytes(Klass::secondary_super_cache_offset()));
1441 if (L_failure == &L_fallthrough) {
1442 cbz(rscratch1, *L_slow_path);
1443 } else {
1444 cbnz(rscratch1, *L_failure);
1445 final_jmp(*L_slow_path);
1446 }
1447
1448 bind(L_fallthrough);
1449
1450 #undef final_jmp
1451 }
1452
1453 // These two are taken from x86, but they look generally useful
1454
1455 // scans count pointer sized words at [addr] for occurrence of value,
1456 // generic
1457 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1458 Register scratch) {
1459 Label Lloop, Lexit;
1460 cbz(count, Lexit);
1461 bind(Lloop);
1462 ldr(scratch, post(addr, wordSize));
1463 cmp(value, scratch);
1464 br(EQ, Lexit);
1465 sub(count, count, 1);
1466 cbnz(count, Lloop);
1467 bind(Lexit);
1468 }
1469
1470 // scans count 4 byte words at [addr] for occurrence of value,
1471 // generic
1472 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1473 Register scratch) {
1474 Label Lloop, Lexit;
1475 cbz(count, Lexit);
1476 bind(Lloop);
1477 ldrw(scratch, post(addr, wordSize));
1478 cmpw(value, scratch);
1479 br(EQ, Lexit);
1480 sub(count, count, 1);
1481 cbnz(count, Lloop);
1482 bind(Lexit);
1483 }
1484
1485 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
1486 Register super_klass,
1487 Register temp_reg,
1488 Register temp2_reg,
1489 Label* L_success,
1490 Label* L_failure,
1491 bool set_cond_codes) {
1492 // NB! Callers may assume that, when temp2_reg is a valid register,
1493 // this code sets it to a nonzero value.
1494
1495 assert_different_registers(sub_klass, super_klass, temp_reg);
1496 if (temp2_reg != noreg)
1497 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1498 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1499
1500 Label L_fallthrough;
1501 int label_nulls = 0;
1502 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1503 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1504 assert(label_nulls <= 1, "at most one null in the batch");
1505
1506 // a couple of useful fields in sub_klass:
1507 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1508 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1509 Address secondary_supers_addr(sub_klass, ss_offset);
1510 Address super_cache_addr( sub_klass, sc_offset);
1511
1512 BLOCK_COMMENT("check_klass_subtype_slow_path");
1513
1514 // Do a linear scan of the secondary super-klass chain.
1515 // This code is rarely used, so simplicity is a virtue here.
1516 // The repne_scan instruction uses fixed registers, which we must spill.
1517 // Don't worry too much about pre-existing connections with the input regs.
1518
1519 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1520 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1521
1522 RegSet pushed_registers;
1523 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1524 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1525
1526 if (super_klass != r0) {
1527 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1528 }
1529
1530 push(pushed_registers, sp);
1531
1532 // Get super_klass value into r0 (even if it was in r5 or r2).
1533 if (super_klass != r0) {
1534 mov(r0, super_klass);
1535 }
1536
1537 #ifndef PRODUCT
1538 incrementw(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
1539 #endif //PRODUCT
1540
1541 // We will consult the secondary-super array.
1542 ldr(r5, secondary_supers_addr);
1543 // Load the array length.
1544 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1545 // Skip to start of data.
1546 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1547
1548 cmp(sp, zr); // Clear Z flag; SP is never zero
1549 // Scan R2 words at [R5] for an occurrence of R0.
1550 // Set NZ/Z based on last compare.
1551 repne_scan(r5, r0, r2, rscratch1);
1552
1553 // Unspill the temp. registers:
1554 pop(pushed_registers, sp);
1555
1556 br(Assembler::NE, *L_failure);
1557
1558 // Success. Cache the super we found and proceed in triumph.
1559
1560 if (UseSecondarySupersCache) {
1561 str(super_klass, super_cache_addr);
1562 }
1563
1564 if (L_success != &L_fallthrough) {
1565 b(*L_success);
1566 }
1567
1568 #undef IS_A_TEMP
1569
1570 bind(L_fallthrough);
1571 }
1572
1573 // If Register r is invalid, remove a new register from
1574 // available_regs, and add new register to regs_to_push.
1575 Register MacroAssembler::allocate_if_noreg(Register r,
1576 RegSetIterator<Register> &available_regs,
1577 RegSet ®s_to_push) {
1578 if (!r->is_valid()) {
1579 r = *available_regs++;
1580 regs_to_push += r;
1581 }
1582 return r;
1583 }
1584
1585 // check_klass_subtype_slow_path_table() looks for super_klass in the
1586 // hash table belonging to super_klass, branching to L_success or
1587 // L_failure as appropriate. This is essentially a shim which
1588 // allocates registers as necessary then calls
1589 // lookup_secondary_supers_table() to do the work. Any of the temp
1590 // regs may be noreg, in which case this logic will chooses some
1591 // registers push and pop them from the stack.
1592 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
1593 Register super_klass,
1594 Register temp_reg,
1595 Register temp2_reg,
1596 Register temp3_reg,
1597 Register result_reg,
1598 FloatRegister vtemp,
1599 Label* L_success,
1600 Label* L_failure,
1601 bool set_cond_codes) {
1602 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
1603
1604 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1605
1606 Label L_fallthrough;
1607 int label_nulls = 0;
1608 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1609 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1610 assert(label_nulls <= 1, "at most one null in the batch");
1611
1612 BLOCK_COMMENT("check_klass_subtype_slow_path");
1613
1614 RegSetIterator<Register> available_regs
1615 = (RegSet::range(r0, r15) - temps - sub_klass - super_klass).begin();
1616
1617 RegSet pushed_regs;
1618
1619 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
1620 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
1621 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
1622 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
1623
1624 push(pushed_regs, sp);
1625
1626 lookup_secondary_supers_table_var(sub_klass,
1627 super_klass,
1628 temp_reg, temp2_reg, temp3_reg, vtemp, result_reg,
1629 nullptr);
1630 cmp(result_reg, zr);
1631
1632 // Unspill the temp. registers:
1633 pop(pushed_regs, sp);
1634
1635 // NB! Callers may assume that, when set_cond_codes is true, this
1636 // code sets temp2_reg to a nonzero value.
1637 if (set_cond_codes) {
1638 mov(temp2_reg, 1);
1639 }
1640
1641 br(Assembler::NE, *L_failure);
1642
1643 if (L_success != &L_fallthrough) {
1644 b(*L_success);
1645 }
1646
1647 bind(L_fallthrough);
1648 }
1649
1650 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1651 Register super_klass,
1652 Register temp_reg,
1653 Register temp2_reg,
1654 Label* L_success,
1655 Label* L_failure,
1656 bool set_cond_codes) {
1657 if (UseSecondarySupersTable) {
1658 check_klass_subtype_slow_path_table
1659 (sub_klass, super_klass, temp_reg, temp2_reg, /*temp3*/noreg, /*result*/noreg,
1660 /*vtemp*/fnoreg,
1661 L_success, L_failure, set_cond_codes);
1662 } else {
1663 check_klass_subtype_slow_path_linear
1664 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
1665 }
1666 }
1667
1668
1669 // Ensure that the inline code and the stub are using the same registers.
1670 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
1671 do { \
1672 assert(r_super_klass == r0 && \
1673 r_array_base == r1 && \
1674 r_array_length == r2 && \
1675 (r_array_index == r3 || r_array_index == noreg) && \
1676 (r_sub_klass == r4 || r_sub_klass == noreg) && \
1677 (r_bitmap == rscratch2 || r_bitmap == noreg) && \
1678 (result == r5 || result == noreg), "registers must match aarch64.ad"); \
1679 } while(0)
1680
1681 bool MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
1682 Register r_super_klass,
1683 Register temp1,
1684 Register temp2,
1685 Register temp3,
1686 FloatRegister vtemp,
1687 Register result,
1688 u1 super_klass_slot,
1689 bool stub_is_near) {
1690 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1691
1692 Label L_fallthrough;
1693
1694 BLOCK_COMMENT("lookup_secondary_supers_table {");
1695
1696 const Register
1697 r_array_base = temp1, // r1
1698 r_array_length = temp2, // r2
1699 r_array_index = temp3, // r3
1700 r_bitmap = rscratch2;
1701
1702 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1703
1704 u1 bit = super_klass_slot;
1705
1706 // Make sure that result is nonzero if the TBZ below misses.
1707 mov(result, 1);
1708
1709 // We're going to need the bitmap in a vector reg and in a core reg,
1710 // so load both now.
1711 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1712 if (bit != 0) {
1713 ldrd(vtemp, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1714 }
1715 // First check the bitmap to see if super_klass might be present. If
1716 // the bit is zero, we are certain that super_klass is not one of
1717 // the secondary supers.
1718 tbz(r_bitmap, bit, L_fallthrough);
1719
1720 // Get the first array index that can contain super_klass into r_array_index.
1721 if (bit != 0) {
1722 shld(vtemp, vtemp, Klass::SECONDARY_SUPERS_TABLE_MASK - bit);
1723 cnt(vtemp, T8B, vtemp);
1724 addv(vtemp, T8B, vtemp);
1725 fmovd(r_array_index, vtemp);
1726 } else {
1727 mov(r_array_index, (u1)1);
1728 }
1729 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1730
1731 // We will consult the secondary-super array.
1732 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1733
1734 // The value i in r_array_index is >= 1, so even though r_array_base
1735 // points to the length, we don't need to adjust it to point to the
1736 // data.
1737 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1738 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1739
1740 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1741 eor(result, result, r_super_klass);
1742 cbz(result, L_fallthrough); // Found a match
1743
1744 // Is there another entry to check? Consult the bitmap.
1745 tbz(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK, L_fallthrough);
1746
1747 // Linear probe.
1748 if (bit != 0) {
1749 ror(r_bitmap, r_bitmap, bit);
1750 }
1751
1752 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1753 // The next slot to be inspected, by the stub we're about to call,
1754 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1755 // have been checked.
1756 Address stub = RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub());
1757 if (stub_is_near) {
1758 bl(stub);
1759 } else {
1760 address call = trampoline_call(stub);
1761 if (call == nullptr) {
1762 return false; // trampoline allocation failed
1763 }
1764 }
1765
1766 BLOCK_COMMENT("} lookup_secondary_supers_table");
1767
1768 bind(L_fallthrough);
1769
1770 if (VerifySecondarySupers) {
1771 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1772 temp1, temp2, result); // r1, r2, r5
1773 }
1774 return true;
1775 }
1776
1777 // At runtime, return 0 in result if r_super_klass is a superclass of
1778 // r_sub_klass, otherwise return nonzero. Use this version of
1779 // lookup_secondary_supers_table() if you don't know ahead of time
1780 // which superclass will be searched for. Used by interpreter and
1781 // runtime stubs. It is larger and has somewhat greater latency than
1782 // the version above, which takes a constant super_klass_slot.
1783 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
1784 Register r_super_klass,
1785 Register temp1,
1786 Register temp2,
1787 Register temp3,
1788 FloatRegister vtemp,
1789 Register result,
1790 Label *L_success) {
1791 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1792
1793 Label L_fallthrough;
1794
1795 BLOCK_COMMENT("lookup_secondary_supers_table {");
1796
1797 const Register
1798 r_array_index = temp3,
1799 slot = rscratch1,
1800 r_bitmap = rscratch2;
1801
1802 ldrb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
1803
1804 // Make sure that result is nonzero if the test below misses.
1805 mov(result, 1);
1806
1807 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1808
1809 // First check the bitmap to see if super_klass might be present. If
1810 // the bit is zero, we are certain that super_klass is not one of
1811 // the secondary supers.
1812
1813 // This next instruction is equivalent to:
1814 // mov(tmp_reg, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1815 // sub(temp2, tmp_reg, slot);
1816 eor(temp2, slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1817 lslv(temp2, r_bitmap, temp2);
1818 tbz(temp2, Klass::SECONDARY_SUPERS_TABLE_SIZE - 1, L_fallthrough);
1819
1820 bool must_save_v0 = (vtemp == fnoreg);
1821 if (must_save_v0) {
1822 // temp1 and result are free, so use them to preserve vtemp
1823 vtemp = v0;
1824 mov(temp1, vtemp, D, 0);
1825 mov(result, vtemp, D, 1);
1826 }
1827
1828 // Get the first array index that can contain super_klass into r_array_index.
1829 mov(vtemp, D, 0, temp2);
1830 cnt(vtemp, T8B, vtemp);
1831 addv(vtemp, T8B, vtemp);
1832 mov(r_array_index, vtemp, D, 0);
1833
1834 if (must_save_v0) {
1835 mov(vtemp, D, 0, temp1 );
1836 mov(vtemp, D, 1, result);
1837 }
1838
1839 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1840
1841 const Register
1842 r_array_base = temp1,
1843 r_array_length = temp2;
1844
1845 // The value i in r_array_index is >= 1, so even though r_array_base
1846 // points to the length, we don't need to adjust it to point to the
1847 // data.
1848 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1849 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1850
1851 // We will consult the secondary-super array.
1852 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1853
1854 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1855 eor(result, result, r_super_klass);
1856 cbz(result, L_success ? *L_success : L_fallthrough); // Found a match
1857
1858 // Is there another entry to check? Consult the bitmap.
1859 rorv(r_bitmap, r_bitmap, slot);
1860 // rol(r_bitmap, r_bitmap, 1);
1861 tbz(r_bitmap, 1, L_fallthrough);
1862
1863 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1864 // The next slot to be inspected, by the logic we're about to call,
1865 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1866 // have been checked.
1867 lookup_secondary_supers_table_slow_path(r_super_klass, r_array_base, r_array_index,
1868 r_bitmap, r_array_length, result, /*is_stub*/false);
1869
1870 BLOCK_COMMENT("} lookup_secondary_supers_table");
1871
1872 bind(L_fallthrough);
1873
1874 if (VerifySecondarySupers) {
1875 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1876 temp1, temp2, result); // r1, r2, r5
1877 }
1878
1879 if (L_success) {
1880 cbz(result, *L_success);
1881 }
1882 }
1883
1884 // Called by code generated by check_klass_subtype_slow_path
1885 // above. This is called when there is a collision in the hashed
1886 // lookup in the secondary supers array.
1887 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
1888 Register r_array_base,
1889 Register r_array_index,
1890 Register r_bitmap,
1891 Register temp1,
1892 Register result,
1893 bool is_stub) {
1894 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, result, rscratch1);
1895
1896 const Register
1897 r_array_length = temp1,
1898 r_sub_klass = noreg; // unused
1899
1900 if (is_stub) {
1901 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1902 }
1903
1904 Label L_fallthrough, L_huge;
1905
1906 // Load the array length.
1907 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1908 // And adjust the array base to point to the data.
1909 // NB! Effectively increments current slot index by 1.
1910 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
1911 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1912
1913 // The bitmap is full to bursting.
1914 // Implicit invariant: BITMAP_FULL implies (length > 0)
1915 assert(Klass::SECONDARY_SUPERS_BITMAP_FULL == ~uintx(0), "");
1916 cmpw(r_array_length, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 2));
1917 br(GT, L_huge);
1918
1919 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
1920 // current slot (at secondary_supers[r_array_index]) has not yet
1921 // been inspected, and r_array_index may be out of bounds if we
1922 // wrapped around the end of the array.
1923
1924 { // This is conventional linear probing, but instead of terminating
1925 // when a null entry is found in the table, we maintain a bitmap
1926 // in which a 0 indicates missing entries.
1927 // As long as the bitmap is not completely full,
1928 // array_length == popcount(bitmap). The array_length check above
1929 // guarantees there are 0s in the bitmap, so the loop eventually
1930 // terminates.
1931 Label L_loop;
1932 bind(L_loop);
1933
1934 // Check for wraparound.
1935 cmp(r_array_index, r_array_length);
1936 csel(r_array_index, zr, r_array_index, GE);
1937
1938 ldr(rscratch1, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1939 eor(result, rscratch1, r_super_klass);
1940 cbz(result, L_fallthrough);
1941
1942 tbz(r_bitmap, 2, L_fallthrough); // look-ahead check (Bit 2); result is non-zero
1943
1944 ror(r_bitmap, r_bitmap, 1);
1945 add(r_array_index, r_array_index, 1);
1946 b(L_loop);
1947 }
1948
1949 { // Degenerate case: more than 64 secondary supers.
1950 // FIXME: We could do something smarter here, maybe a vectorized
1951 // comparison or a binary search, but is that worth any added
1952 // complexity?
1953 bind(L_huge);
1954 cmp(sp, zr); // Clear Z flag; SP is never zero
1955 repne_scan(r_array_base, r_super_klass, r_array_length, rscratch1);
1956 cset(result, NE); // result == 0 iff we got a match.
1957 }
1958
1959 bind(L_fallthrough);
1960 }
1961
1962 // Make sure that the hashed lookup and a linear scan agree.
1963 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
1964 Register r_super_klass,
1965 Register temp1,
1966 Register temp2,
1967 Register result) {
1968 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, result, rscratch1);
1969
1970 const Register
1971 r_array_base = temp1,
1972 r_array_length = temp2;
1973
1974 BLOCK_COMMENT("verify_secondary_supers_table {");
1975
1976 // We will consult the secondary-super array.
1977 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1978
1979 // Load the array length.
1980 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1981 // And adjust the array base to point to the data.
1982 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1983
1984 cmp(sp, zr); // Clear Z flag; SP is never zero
1985 // Scan R2 words at [R5] for an occurrence of R0.
1986 // Set NZ/Z based on last compare.
1987 repne_scan(/*addr*/r_array_base, /*value*/r_super_klass, /*count*/r_array_length, rscratch2);
1988 // rscratch1 == 0 iff we got a match.
1989 cset(rscratch1, NE);
1990
1991 Label passed;
1992 cmp(result, zr);
1993 cset(result, NE); // normalize result to 0/1 for comparison
1994
1995 cmp(rscratch1, result);
1996 br(EQ, passed);
1997 {
1998 mov(r0, r_super_klass); // r0 <- r0
1999 mov(r1, r_sub_klass); // r1 <- r4
2000 mov(r2, /*expected*/rscratch1); // r2 <- r8
2001 mov(r3, result); // r3 <- r5
2002 mov(r4, (address)("mismatch")); // r4 <- const
2003 rt_call(CAST_FROM_FN_PTR(address, Klass::on_secondary_supers_verification_failure), rscratch2);
2004 should_not_reach_here();
2005 }
2006 bind(passed);
2007
2008 BLOCK_COMMENT("} verify_secondary_supers_table");
2009 }
2010
2011 void MacroAssembler::clinit_barrier(Register klass, Register scratch, Label* L_fast_path, Label* L_slow_path) {
2012 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
2013 assert_different_registers(klass, rthread, scratch);
2014
2015 Label L_fallthrough, L_tmp;
2016 if (L_fast_path == nullptr) {
2017 L_fast_path = &L_fallthrough;
2018 } else if (L_slow_path == nullptr) {
2019 L_slow_path = &L_fallthrough;
2020 }
2021 // Fast path check: class is fully initialized
2022 lea(scratch, Address(klass, InstanceKlass::init_state_offset()));
2023 ldarb(scratch, scratch);
2024 cmp(scratch, InstanceKlass::fully_initialized);
2025 br(Assembler::EQ, *L_fast_path);
2026
2027 // Fast path check: current thread is initializer thread
2028 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
2029 cmp(rthread, scratch);
2030
2031 if (L_slow_path == &L_fallthrough) {
2032 br(Assembler::EQ, *L_fast_path);
2033 bind(*L_slow_path);
2034 } else if (L_fast_path == &L_fallthrough) {
2035 br(Assembler::NE, *L_slow_path);
2036 bind(*L_fast_path);
2037 } else {
2038 Unimplemented();
2039 }
2040 }
2041
2042 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
2043 if (!VerifyOops) return;
2044
2045 // Pass register number to verify_oop_subroutine
2046 const char* b = nullptr;
2047 {
2048 ResourceMark rm;
2049 stringStream ss;
2050 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
2051 b = code_string(ss.as_string());
2052 }
2053 BLOCK_COMMENT("verify_oop {");
2054
2055 strip_return_address(); // This might happen within a stack frame.
2056 protect_return_address();
2057 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2058 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2059
2060 mov(r0, reg);
2061 movptr(rscratch1, (uintptr_t)(address)b);
2062
2063 // call indirectly to solve generation ordering problem
2064 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2065 ldr(rscratch2, Address(rscratch2));
2066 blr(rscratch2);
2067
2068 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2069 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2070 authenticate_return_address();
2071
2072 BLOCK_COMMENT("} verify_oop");
2073 }
2074
2075 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
2076 if (!VerifyOops) return;
2077
2078 const char* b = nullptr;
2079 {
2080 ResourceMark rm;
2081 stringStream ss;
2082 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
2083 b = code_string(ss.as_string());
2084 }
2085 BLOCK_COMMENT("verify_oop_addr {");
2086
2087 strip_return_address(); // This might happen within a stack frame.
2088 protect_return_address();
2089 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2090 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2091
2092 // addr may contain sp so we will have to adjust it based on the
2093 // pushes that we just did.
2094 if (addr.uses(sp)) {
2095 lea(r0, addr);
2096 ldr(r0, Address(r0, 4 * wordSize));
2097 } else {
2098 ldr(r0, addr);
2099 }
2100 movptr(rscratch1, (uintptr_t)(address)b);
2101
2102 // call indirectly to solve generation ordering problem
2103 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2104 ldr(rscratch2, Address(rscratch2));
2105 blr(rscratch2);
2106
2107 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2108 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2109 authenticate_return_address();
2110
2111 BLOCK_COMMENT("} verify_oop_addr");
2112 }
2113
2114 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
2115 int extra_slot_offset) {
2116 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
2117 int stackElementSize = Interpreter::stackElementSize;
2118 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
2119 #ifdef ASSERT
2120 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
2121 assert(offset1 - offset == stackElementSize, "correct arithmetic");
2122 #endif
2123 if (arg_slot.is_constant()) {
2124 return Address(esp, arg_slot.as_constant() * stackElementSize
2125 + offset);
2126 } else {
2127 add(rscratch1, esp, arg_slot.as_register(),
2128 ext::uxtx, exact_log2(stackElementSize));
2129 return Address(rscratch1, offset);
2130 }
2131 }
2132
2133 // Handle the receiver type profile update given the "recv" klass.
2134 //
2135 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
2136 // If there are no matching or claimable receiver entries in RD, updates
2137 // the polymorphic counter.
2138 //
2139 // This code expected to run by either the interpreter or JIT-ed code, without
2140 // extra synchronization. For safety, receiver cells are claimed atomically, which
2141 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
2142 // counter updates are not atomic.
2143 //
2144 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
2145 assert_different_registers(recv, mdp, rscratch1, rscratch2);
2146
2147 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
2148 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
2149 int poly_count_offset = in_bytes(CounterData::count_offset());
2150 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
2151 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
2152
2153 // Adjust for MDP offsets.
2154 base_receiver_offset += mdp_offset;
2155 end_receiver_offset += mdp_offset;
2156 poly_count_offset += mdp_offset;
2157
2158 #ifdef ASSERT
2159 // We are about to walk the MDO slots without asking for offsets.
2160 // Check that our math hits all the right spots.
2161 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
2162 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
2163 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
2164 int offset = base_receiver_offset + receiver_step*c;
2165 int count_offset = offset + receiver_to_count_step;
2166 assert(offset == real_recv_offset, "receiver slot math");
2167 assert(count_offset == real_count_offset, "receiver count math");
2168 }
2169 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
2170 assert(poly_count_offset == real_poly_count_offset, "poly counter math");
2171 #endif
2172
2173 // Corner case: no profile table. Increment poly counter and exit.
2174 if (ReceiverTypeData::row_limit() == 0) {
2175 increment(Address(mdp, poly_count_offset), DataLayout::counter_increment);
2176 return;
2177 }
2178
2179 Register offset = rscratch2;
2180
2181 Label L_loop_search_receiver, L_loop_search_empty;
2182 Label L_restart, L_found_recv, L_found_empty, L_polymorphic, L_count_update;
2183
2184 // The code here recognizes three major cases:
2185 // A. Fastest: receiver found in the table
2186 // B. Fast: no receiver in the table, and the table is full
2187 // C. Slow: no receiver in the table, free slots in the table
2188 //
2189 // The case A performance is most important, as perfectly-behaved code would end up
2190 // there, especially with larger TypeProfileWidth. The case B performance is
2191 // important as well, this is where bulk of code would land for normally megamorphic
2192 // cases. The case C performance is not essential, its job is to deal with installation
2193 // races, we optimize for code density instead. Case C needs to make sure that receiver
2194 // rows are only claimed once. This makes sure we never overwrite a row for another
2195 // receiver and never duplicate the receivers in the list, making profile type-accurate.
2196 //
2197 // It is very tempting to handle these cases in a single loop, and claim the first slot
2198 // without checking the rest of the table. But, profiling code should tolerate free slots
2199 // in the table, as class unloading can clear them. After such cleanup, the receiver
2200 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
2201 // to complete, before trying to install new slots. Splitting the code in several tight
2202 // loops also helpfully optimizes for cases A and B.
2203 //
2204 // This code is effectively:
2205 //
2206 // restart:
2207 // // Fastest: receiver is already installed
2208 // for (i = 0; i < receiver_count(); i++) {
2209 // if (receiver(i) == recv) goto found_recv(i);
2210 // }
2211 //
2212 // // Fast: no receiver, but profile is full
2213 // for (i = 0; i < receiver_count(); i++) {
2214 // if (receiver(i) == null) goto found_null(i);
2215 // }
2216 // goto polymorphic
2217 //
2218 // // Slow: try to install receiver
2219 // found_null(i):
2220 // CAS(&receiver(i), null, recv);
2221 // goto restart
2222 //
2223 // polymorphic:
2224 // count++;
2225 // return
2226 //
2227 // found_recv(i):
2228 // *receiver_count(i)++
2229 //
2230
2231 bind(L_restart);
2232
2233 // Fastest: receiver is already installed
2234 mov(offset, base_receiver_offset);
2235 bind(L_loop_search_receiver);
2236 ldr(rscratch1, Address(mdp, offset));
2237 cmp(rscratch1, recv);
2238 br(Assembler::EQ, L_found_recv);
2239 add(offset, offset, receiver_step);
2240 sub(rscratch1, offset, end_receiver_offset);
2241 cbnz(rscratch1, L_loop_search_receiver);
2242
2243 // Fast: no receiver, but profile is full
2244 mov(offset, base_receiver_offset);
2245 bind(L_loop_search_empty);
2246 ldr(rscratch1, Address(mdp, offset));
2247 cbz(rscratch1, L_found_empty);
2248 add(offset, offset, receiver_step);
2249 sub(rscratch1, offset, end_receiver_offset);
2250 cbnz(rscratch1, L_loop_search_empty);
2251 b(L_polymorphic);
2252
2253 // Slow: try to install receiver
2254 bind(L_found_empty);
2255
2256 // Atomically swing receiver slot: null -> recv.
2257 //
2258 // The update uses CAS, which clobbers rscratch1. Therefore, rscratch2
2259 // is used to hold the destination address. This is safe because the
2260 // offset is no longer needed after the address is computed.
2261
2262 lea(rscratch2, Address(mdp, offset));
2263 cmpxchg(/*addr*/ rscratch2, /*expected*/ zr, /*new*/ recv, Assembler::xword,
2264 /*acquire*/ false, /*release*/ false, /*weak*/ true, noreg);
2265
2266 // CAS success means the slot now has the receiver we want. CAS failure means
2267 // something had claimed the slot concurrently: it can be the same receiver we want,
2268 // or something else. Since this is a slow path, we can optimize for code density,
2269 // and just restart the search from the beginning.
2270 b(L_restart);
2271
2272 // Counter updates:
2273
2274 // Increment polymorphic counter instead of receiver slot.
2275 bind(L_polymorphic);
2276 mov(offset, poly_count_offset);
2277 b(L_count_update);
2278
2279 // Found a receiver, convert its slot offset to corresponding count offset.
2280 bind(L_found_recv);
2281 add(offset, offset, receiver_to_count_step);
2282
2283 bind(L_count_update);
2284 increment(Address(mdp, offset), DataLayout::counter_increment);
2285 }
2286
2287
2288 void MacroAssembler::call_VM_leaf_base(address entry_point,
2289 int number_of_arguments,
2290 Label *retaddr) {
2291 Label E, L;
2292
2293 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
2294
2295 mov(rscratch1, RuntimeAddress(entry_point));
2296 blr(rscratch1);
2297 if (retaddr)
2298 bind(*retaddr);
2299
2300 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
2301 }
2302
2303 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2304 call_VM_leaf_base(entry_point, number_of_arguments);
2305 }
2306
2307 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2308 pass_arg0(this, arg_0);
2309 call_VM_leaf_base(entry_point, 1);
2310 }
2311
2312 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2313 assert_different_registers(arg_1, c_rarg0);
2314 pass_arg0(this, arg_0);
2315 pass_arg1(this, arg_1);
2316 call_VM_leaf_base(entry_point, 2);
2317 }
2318
2319 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
2320 Register arg_1, Register arg_2) {
2321 assert_different_registers(arg_1, c_rarg0);
2322 assert_different_registers(arg_2, c_rarg0, c_rarg1);
2323 pass_arg0(this, arg_0);
2324 pass_arg1(this, arg_1);
2325 pass_arg2(this, arg_2);
2326 call_VM_leaf_base(entry_point, 3);
2327 }
2328
2329 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2330 pass_arg0(this, arg_0);
2331 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2332 }
2333
2334 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2335
2336 assert_different_registers(arg_0, c_rarg1);
2337 pass_arg1(this, arg_1);
2338 pass_arg0(this, arg_0);
2339 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2340 }
2341
2342 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2343 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2344 assert_different_registers(arg_1, c_rarg2);
2345 pass_arg2(this, arg_2);
2346 pass_arg1(this, arg_1);
2347 pass_arg0(this, arg_0);
2348 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2349 }
2350
2351 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2352 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
2353 assert_different_registers(arg_1, c_rarg2, c_rarg3);
2354 assert_different_registers(arg_2, c_rarg3);
2355 pass_arg3(this, arg_3);
2356 pass_arg2(this, arg_2);
2357 pass_arg1(this, arg_1);
2358 pass_arg0(this, arg_0);
2359 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2360 }
2361
2362 void MacroAssembler::null_check(Register reg, int offset) {
2363 if (needs_explicit_null_check(offset)) {
2364 // provoke OS null exception if reg is null by
2365 // accessing M[reg] w/o changing any registers
2366 // NOTE: this is plenty to provoke a segv
2367 ldr(zr, Address(reg));
2368 } else {
2369 // nothing to do, (later) access of M[reg + offset]
2370 // will provoke OS null exception if reg is null
2371 }
2372 }
2373
2374 // MacroAssembler protected routines needed to implement
2375 // public methods
2376
2377 void MacroAssembler::mov(Register r, Address dest) {
2378 code_section()->relocate(pc(), dest.rspec());
2379 uint64_t imm64 = (uint64_t)dest.target();
2380 movptr(r, imm64);
2381 }
2382
2383 // Move a constant pointer into r. In AArch64 mode the virtual
2384 // address space is 48 bits in size, so we only need three
2385 // instructions to create a patchable instruction sequence that can
2386 // reach anywhere.
2387 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2388 #ifndef PRODUCT
2389 {
2390 char buffer[64];
2391 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2392 block_comment(buffer);
2393 }
2394 #endif
2395 assert(imm64 < (1ull << 48), "48-bit overflow in address constant");
2396 movz(r, imm64 & 0xffff);
2397 imm64 >>= 16;
2398 movk(r, imm64 & 0xffff, 16);
2399 imm64 >>= 16;
2400 movk(r, imm64 & 0xffff, 32);
2401 }
2402
2403 // Macro to mov replicated immediate to vector register.
2404 // imm64: only the lower 8/16/32 bits are considered for B/H/S type. That is,
2405 // the upper 56/48/32 bits must be zeros for B/H/S type.
2406 // Vd will get the following values for different arrangements in T
2407 // imm64 == hex 000000gh T8B: Vd = ghghghghghghghgh
2408 // imm64 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
2409 // imm64 == hex 0000efgh T4H: Vd = efghefghefghefgh
2410 // imm64 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
2411 // imm64 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
2412 // imm64 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
2413 // imm64 == hex abcdefgh T1D: Vd = 00000000abcdefgh
2414 // imm64 == hex abcdefgh T2D: Vd = 00000000abcdefgh00000000abcdefgh
2415 // Clobbers rscratch1
2416 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64) {
2417 assert(T != T1Q, "unsupported");
2418 if (T == T1D || T == T2D) {
2419 int imm = operand_valid_for_movi_immediate(imm64, T);
2420 if (-1 != imm) {
2421 movi(Vd, T, imm);
2422 } else {
2423 mov(rscratch1, imm64);
2424 dup(Vd, T, rscratch1);
2425 }
2426 return;
2427 }
2428
2429 #ifdef ASSERT
2430 if (T == T8B || T == T16B) assert((imm64 & ~0xff) == 0, "extraneous bits (T8B/T16B)");
2431 if (T == T4H || T == T8H) assert((imm64 & ~0xffff) == 0, "extraneous bits (T4H/T8H)");
2432 if (T == T2S || T == T4S) assert((imm64 & ~0xffffffff) == 0, "extraneous bits (T2S/T4S)");
2433 #endif
2434 int shift = operand_valid_for_movi_immediate(imm64, T);
2435 uint32_t imm32 = imm64 & 0xffffffffULL;
2436 if (shift >= 0) {
2437 movi(Vd, T, (imm32 >> shift) & 0xff, shift);
2438 } else {
2439 movw(rscratch1, imm32);
2440 dup(Vd, T, rscratch1);
2441 }
2442 }
2443
2444 void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64)
2445 {
2446 #ifndef PRODUCT
2447 {
2448 char buffer[64];
2449 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, imm64);
2450 block_comment(buffer);
2451 }
2452 #endif
2453 if (operand_valid_for_logical_immediate(false, imm64)) {
2454 orr(dst, zr, imm64);
2455 } else {
2456 // we can use a combination of MOVZ or MOVN with
2457 // MOVK to build up the constant
2458 uint64_t imm_h[4];
2459 int zero_count = 0;
2460 int neg_count = 0;
2461 int i;
2462 for (i = 0; i < 4; i++) {
2463 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
2464 if (imm_h[i] == 0) {
2465 zero_count++;
2466 } else if (imm_h[i] == 0xffffL) {
2467 neg_count++;
2468 }
2469 }
2470 if (zero_count == 4) {
2471 // one MOVZ will do
2472 movz(dst, 0);
2473 } else if (neg_count == 4) {
2474 // one MOVN will do
2475 movn(dst, 0);
2476 } else if (zero_count == 3) {
2477 for (i = 0; i < 4; i++) {
2478 if (imm_h[i] != 0L) {
2479 movz(dst, (uint32_t)imm_h[i], (i << 4));
2480 break;
2481 }
2482 }
2483 } else if (neg_count == 3) {
2484 // one MOVN will do
2485 for (int i = 0; i < 4; i++) {
2486 if (imm_h[i] != 0xffffL) {
2487 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2488 break;
2489 }
2490 }
2491 } else if (zero_count == 2) {
2492 // one MOVZ and one MOVK will do
2493 for (i = 0; i < 3; i++) {
2494 if (imm_h[i] != 0L) {
2495 movz(dst, (uint32_t)imm_h[i], (i << 4));
2496 i++;
2497 break;
2498 }
2499 }
2500 for (;i < 4; i++) {
2501 if (imm_h[i] != 0L) {
2502 movk(dst, (uint32_t)imm_h[i], (i << 4));
2503 }
2504 }
2505 } else if (neg_count == 2) {
2506 // one MOVN and one MOVK will do
2507 for (i = 0; i < 4; i++) {
2508 if (imm_h[i] != 0xffffL) {
2509 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2510 i++;
2511 break;
2512 }
2513 }
2514 for (;i < 4; i++) {
2515 if (imm_h[i] != 0xffffL) {
2516 movk(dst, (uint32_t)imm_h[i], (i << 4));
2517 }
2518 }
2519 } else if (zero_count == 1) {
2520 // one MOVZ and two MOVKs will do
2521 for (i = 0; i < 4; i++) {
2522 if (imm_h[i] != 0L) {
2523 movz(dst, (uint32_t)imm_h[i], (i << 4));
2524 i++;
2525 break;
2526 }
2527 }
2528 for (;i < 4; i++) {
2529 if (imm_h[i] != 0x0L) {
2530 movk(dst, (uint32_t)imm_h[i], (i << 4));
2531 }
2532 }
2533 } else if (neg_count == 1) {
2534 // one MOVN and two MOVKs will do
2535 for (i = 0; i < 4; i++) {
2536 if (imm_h[i] != 0xffffL) {
2537 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2538 i++;
2539 break;
2540 }
2541 }
2542 for (;i < 4; i++) {
2543 if (imm_h[i] != 0xffffL) {
2544 movk(dst, (uint32_t)imm_h[i], (i << 4));
2545 }
2546 }
2547 } else {
2548 // use a MOVZ and 3 MOVKs (makes it easier to debug)
2549 movz(dst, (uint32_t)imm_h[0], 0);
2550 for (i = 1; i < 4; i++) {
2551 movk(dst, (uint32_t)imm_h[i], (i << 4));
2552 }
2553 }
2554 }
2555 }
2556
2557 void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32)
2558 {
2559 #ifndef PRODUCT
2560 {
2561 char buffer[64];
2562 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX32, imm32);
2563 block_comment(buffer);
2564 }
2565 #endif
2566 if (operand_valid_for_logical_immediate(true, imm32)) {
2567 orrw(dst, zr, imm32);
2568 } else {
2569 // we can use MOVZ, MOVN or two calls to MOVK to build up the
2570 // constant
2571 uint32_t imm_h[2];
2572 imm_h[0] = imm32 & 0xffff;
2573 imm_h[1] = ((imm32 >> 16) & 0xffff);
2574 if (imm_h[0] == 0) {
2575 movzw(dst, imm_h[1], 16);
2576 } else if (imm_h[0] == 0xffff) {
2577 movnw(dst, imm_h[1] ^ 0xffff, 16);
2578 } else if (imm_h[1] == 0) {
2579 movzw(dst, imm_h[0], 0);
2580 } else if (imm_h[1] == 0xffff) {
2581 movnw(dst, imm_h[0] ^ 0xffff, 0);
2582 } else {
2583 // use a MOVZ and MOVK (makes it easier to debug)
2584 movzw(dst, imm_h[0], 0);
2585 movkw(dst, imm_h[1], 16);
2586 }
2587 }
2588 }
2589
2590 // Form an address from base + offset in Rd. Rd may or may
2591 // not actually be used: you must use the Address that is returned.
2592 // It is up to you to ensure that the shift provided matches the size
2593 // of your data.
2594 Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) {
2595 if (Address::offset_ok_for_immed(byte_offset, shift))
2596 // It fits; no need for any heroics
2597 return Address(base, byte_offset);
2598
2599 // Don't do anything clever with negative or misaligned offsets
2600 unsigned mask = (1 << shift) - 1;
2601 if (byte_offset < 0 || byte_offset & mask) {
2602 mov(Rd, byte_offset);
2603 add(Rd, base, Rd);
2604 return Address(Rd);
2605 }
2606
2607 // See if we can do this with two 12-bit offsets
2608 {
2609 uint64_t word_offset = byte_offset >> shift;
2610 uint64_t masked_offset = word_offset & 0xfff000;
2611 if (Address::offset_ok_for_immed(word_offset - masked_offset, 0)
2612 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
2613 add(Rd, base, masked_offset << shift);
2614 word_offset -= masked_offset;
2615 return Address(Rd, word_offset << shift);
2616 }
2617 }
2618
2619 // Do it the hard way
2620 mov(Rd, byte_offset);
2621 add(Rd, base, Rd);
2622 return Address(Rd);
2623 }
2624
2625 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
2626 bool want_remainder, Register scratch)
2627 {
2628 // Full implementation of Java idiv and irem. The function
2629 // returns the (pc) offset of the div instruction - may be needed
2630 // for implicit exceptions.
2631 //
2632 // constraint : ra/rb =/= scratch
2633 // normal case
2634 //
2635 // input : ra: dividend
2636 // rb: divisor
2637 //
2638 // result: either
2639 // quotient (= ra idiv rb)
2640 // remainder (= ra irem rb)
2641
2642 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2643
2644 int idivl_offset = offset();
2645 if (! want_remainder) {
2646 sdivw(result, ra, rb);
2647 } else {
2648 sdivw(scratch, ra, rb);
2649 Assembler::msubw(result, scratch, rb, ra);
2650 }
2651
2652 return idivl_offset;
2653 }
2654
2655 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
2656 bool want_remainder, Register scratch)
2657 {
2658 // Full implementation of Java ldiv and lrem. The function
2659 // returns the (pc) offset of the div instruction - may be needed
2660 // for implicit exceptions.
2661 //
2662 // constraint : ra/rb =/= scratch
2663 // normal case
2664 //
2665 // input : ra: dividend
2666 // rb: divisor
2667 //
2668 // result: either
2669 // quotient (= ra idiv rb)
2670 // remainder (= ra irem rb)
2671
2672 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2673
2674 int idivq_offset = offset();
2675 if (! want_remainder) {
2676 sdiv(result, ra, rb);
2677 } else {
2678 sdiv(scratch, ra, rb);
2679 Assembler::msub(result, scratch, rb, ra);
2680 }
2681
2682 return idivq_offset;
2683 }
2684
2685 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
2686 address prev = pc() - NativeMembar::instruction_size;
2687 address last = code()->last_insn();
2688 if (last != nullptr && nativeInstruction_at(last)->is_Membar() && prev == last) {
2689 NativeMembar *bar = NativeMembar_at(prev);
2690 if (AlwaysMergeDMB) {
2691 bar->set_kind(bar->get_kind() | order_constraint);
2692 BLOCK_COMMENT("merged membar(always)");
2693 return;
2694 }
2695 // Don't promote DMB ST|DMB LD to DMB (a full barrier) because
2696 // doing so would introduce a StoreLoad which the caller did not
2697 // intend
2698 if (bar->get_kind() == order_constraint
2699 || bar->get_kind() == AnyAny
2700 || order_constraint == AnyAny) {
2701 // We are merging two memory barrier instructions. On AArch64 we
2702 // can do this simply by ORing them together.
2703 bar->set_kind(bar->get_kind() | order_constraint);
2704 BLOCK_COMMENT("merged membar");
2705 return;
2706 } else {
2707 // A special case like "DMB ST;DMB LD;DMB ST", the last DMB can be skipped
2708 // We need check the last 2 instructions
2709 address prev2 = prev - NativeMembar::instruction_size;
2710 if (last != code()->last_label() && nativeInstruction_at(prev2)->is_Membar()) {
2711 NativeMembar *bar2 = NativeMembar_at(prev2);
2712 assert(bar2->get_kind() == order_constraint, "it should be merged before");
2713 BLOCK_COMMENT("merged membar(elided)");
2714 return;
2715 }
2716 }
2717 }
2718 code()->set_last_insn(pc());
2719 dmb(Assembler::barrier(order_constraint));
2720 }
2721
2722 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) {
2723 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) {
2724 merge_ldst(rt, adr, size_in_bytes, is_store);
2725 code()->clear_last_insn();
2726 return true;
2727 } else {
2728 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported.");
2729 const uint64_t mask = size_in_bytes - 1;
2730 if (adr.getMode() == Address::base_plus_offset &&
2731 (adr.offset() & mask) == 0) { // only supports base_plus_offset.
2732 code()->set_last_insn(pc());
2733 }
2734 return false;
2735 }
2736 }
2737
2738 void MacroAssembler::ldr(Register Rx, const Address &adr) {
2739 // We always try to merge two adjacent loads into one ldp.
2740 if (!try_merge_ldst(Rx, adr, 8, false)) {
2741 Assembler::ldr(Rx, adr);
2742 }
2743 }
2744
2745 void MacroAssembler::ldrw(Register Rw, const Address &adr) {
2746 // We always try to merge two adjacent loads into one ldp.
2747 if (!try_merge_ldst(Rw, adr, 4, false)) {
2748 Assembler::ldrw(Rw, adr);
2749 }
2750 }
2751
2752 void MacroAssembler::str(Register Rx, const Address &adr) {
2753 // We always try to merge two adjacent stores into one stp.
2754 if (!try_merge_ldst(Rx, adr, 8, true)) {
2755 Assembler::str(Rx, adr);
2756 }
2757 }
2758
2759 void MacroAssembler::strw(Register Rw, const Address &adr) {
2760 // We always try to merge two adjacent stores into one stp.
2761 if (!try_merge_ldst(Rw, adr, 4, true)) {
2762 Assembler::strw(Rw, adr);
2763 }
2764 }
2765
2766 // MacroAssembler routines found actually to be needed
2767
2768 void MacroAssembler::push(Register src)
2769 {
2770 str(src, Address(pre(esp, -1 * wordSize)));
2771 }
2772
2773 void MacroAssembler::pop(Register dst)
2774 {
2775 ldr(dst, Address(post(esp, 1 * wordSize)));
2776 }
2777
2778 // Note: load_unsigned_short used to be called load_unsigned_word.
2779 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2780 int off = offset();
2781 ldrh(dst, src);
2782 return off;
2783 }
2784
2785 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2786 int off = offset();
2787 ldrb(dst, src);
2788 return off;
2789 }
2790
2791 int MacroAssembler::load_signed_short(Register dst, Address src) {
2792 int off = offset();
2793 ldrsh(dst, src);
2794 return off;
2795 }
2796
2797 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2798 int off = offset();
2799 ldrsb(dst, src);
2800 return off;
2801 }
2802
2803 int MacroAssembler::load_signed_short32(Register dst, Address src) {
2804 int off = offset();
2805 ldrshw(dst, src);
2806 return off;
2807 }
2808
2809 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
2810 int off = offset();
2811 ldrsbw(dst, src);
2812 return off;
2813 }
2814
2815 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) {
2816 switch (size_in_bytes) {
2817 case 8: ldr(dst, src); break;
2818 case 4: ldrw(dst, src); break;
2819 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2820 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2821 default: ShouldNotReachHere();
2822 }
2823 }
2824
2825 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes) {
2826 switch (size_in_bytes) {
2827 case 8: str(src, dst); break;
2828 case 4: strw(src, dst); break;
2829 case 2: strh(src, dst); break;
2830 case 1: strb(src, dst); break;
2831 default: ShouldNotReachHere();
2832 }
2833 }
2834
2835 void MacroAssembler::decrementw(Register reg, int value)
2836 {
2837 if (value < 0) { incrementw(reg, -value); return; }
2838 if (value == 0) { return; }
2839 if (value < (1 << 12)) { subw(reg, reg, value); return; }
2840 /* else */ {
2841 guarantee(reg != rscratch2, "invalid dst for register decrement");
2842 movw(rscratch2, (unsigned)value);
2843 subw(reg, reg, rscratch2);
2844 }
2845 }
2846
2847 void MacroAssembler::decrement(Register reg, int value)
2848 {
2849 if (value < 0) { increment(reg, -value); return; }
2850 if (value == 0) { return; }
2851 if (value < (1 << 12)) { sub(reg, reg, value); return; }
2852 /* else */ {
2853 assert(reg != rscratch2, "invalid dst for register decrement");
2854 mov(rscratch2, (uint64_t)value);
2855 sub(reg, reg, rscratch2);
2856 }
2857 }
2858
2859 void MacroAssembler::decrementw(Address dst, int value)
2860 {
2861 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
2862 if (dst.getMode() == Address::literal) {
2863 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2864 lea(rscratch2, dst);
2865 dst = Address(rscratch2);
2866 }
2867 ldrw(rscratch1, dst);
2868 decrementw(rscratch1, value);
2869 strw(rscratch1, dst);
2870 }
2871
2872 void MacroAssembler::decrement(Address dst, int value)
2873 {
2874 assert(!dst.uses(rscratch1), "invalid address for decrement");
2875 if (dst.getMode() == Address::literal) {
2876 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2877 lea(rscratch2, dst);
2878 dst = Address(rscratch2);
2879 }
2880 ldr(rscratch1, dst);
2881 decrement(rscratch1, value);
2882 str(rscratch1, dst);
2883 }
2884
2885 void MacroAssembler::incrementw(Register reg, int value)
2886 {
2887 if (value < 0) { decrementw(reg, -value); return; }
2888 if (value == 0) { return; }
2889 if (value < (1 << 12)) { addw(reg, reg, value); return; }
2890 /* else */ {
2891 assert(reg != rscratch2, "invalid dst for register increment");
2892 movw(rscratch2, (unsigned)value);
2893 addw(reg, reg, rscratch2);
2894 }
2895 }
2896
2897 void MacroAssembler::increment(Register reg, int value)
2898 {
2899 if (value < 0) { decrement(reg, -value); return; }
2900 if (value == 0) { return; }
2901 if (value < (1 << 12)) { add(reg, reg, value); return; }
2902 /* else */ {
2903 assert(reg != rscratch2, "invalid dst for register increment");
2904 movw(rscratch2, (unsigned)value);
2905 add(reg, reg, rscratch2);
2906 }
2907 }
2908
2909 void MacroAssembler::incrementw(Address dst, int value)
2910 {
2911 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2912 if (dst.getMode() == Address::literal) {
2913 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2914 lea(rscratch2, dst);
2915 dst = Address(rscratch2);
2916 }
2917 ldrw(rscratch1, dst);
2918 incrementw(rscratch1, value);
2919 strw(rscratch1, dst);
2920 }
2921
2922 void MacroAssembler::increment(Address dst, int value)
2923 {
2924 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2925 if (dst.getMode() == Address::literal) {
2926 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2927 lea(rscratch2, dst);
2928 dst = Address(rscratch2);
2929 }
2930 ldr(rscratch1, dst);
2931 increment(rscratch1, value);
2932 str(rscratch1, dst);
2933 }
2934
2935 // Push lots of registers in the bit set supplied. Don't push sp.
2936 // Return the number of words pushed
2937 int MacroAssembler::push(unsigned int bitset, Register stack) {
2938 int words_pushed = 0;
2939
2940 // Scan bitset to accumulate register pairs
2941 unsigned char regs[32];
2942 int count = 0;
2943 for (int reg = 0; reg <= 30; reg++) {
2944 if (1 & bitset)
2945 regs[count++] = reg;
2946 bitset >>= 1;
2947 }
2948 regs[count++] = zr->raw_encoding();
2949 count &= ~1; // Only push an even number of regs
2950
2951 if (count) {
2952 stp(as_Register(regs[0]), as_Register(regs[1]),
2953 Address(pre(stack, -count * wordSize)));
2954 words_pushed += 2;
2955 }
2956 for (int i = 2; i < count; i += 2) {
2957 stp(as_Register(regs[i]), as_Register(regs[i+1]),
2958 Address(stack, i * wordSize));
2959 words_pushed += 2;
2960 }
2961
2962 assert(words_pushed == count, "oops, pushed != count");
2963
2964 return count;
2965 }
2966
2967 int MacroAssembler::pop(unsigned int bitset, Register stack) {
2968 int words_pushed = 0;
2969
2970 // Scan bitset to accumulate register pairs
2971 unsigned char regs[32];
2972 int count = 0;
2973 for (int reg = 0; reg <= 30; reg++) {
2974 if (1 & bitset)
2975 regs[count++] = reg;
2976 bitset >>= 1;
2977 }
2978 regs[count++] = zr->raw_encoding();
2979 count &= ~1;
2980
2981 for (int i = 2; i < count; i += 2) {
2982 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
2983 Address(stack, i * wordSize));
2984 words_pushed += 2;
2985 }
2986 if (count) {
2987 ldp(as_Register(regs[0]), as_Register(regs[1]),
2988 Address(post(stack, count * wordSize)));
2989 words_pushed += 2;
2990 }
2991
2992 assert(words_pushed == count, "oops, pushed != count");
2993
2994 return count;
2995 }
2996
2997 // Push lots of registers in the bit set supplied. Don't push sp.
2998 // Return the number of dwords pushed
2999 int MacroAssembler::push_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
3000 int words_pushed = 0;
3001 bool use_sve = false;
3002 int sve_vector_size_in_bytes = 0;
3003
3004 #ifdef COMPILER2
3005 use_sve = Matcher::supports_scalable_vector();
3006 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
3007 #endif
3008
3009 // Scan bitset to accumulate register pairs
3010 unsigned char regs[32];
3011 int count = 0;
3012 for (int reg = 0; reg <= 31; reg++) {
3013 if (1 & bitset)
3014 regs[count++] = reg;
3015 bitset >>= 1;
3016 }
3017
3018 if (count == 0) {
3019 return 0;
3020 }
3021
3022 if (mode == PushPopFull) {
3023 if (use_sve && sve_vector_size_in_bytes > 16) {
3024 mode = PushPopSVE;
3025 } else {
3026 mode = PushPopNeon;
3027 }
3028 }
3029
3030 #ifndef PRODUCT
3031 {
3032 char buffer[48];
3033 if (mode == PushPopSVE) {
3034 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d SVE registers", count);
3035 } else if (mode == PushPopNeon) {
3036 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d Neon registers", count);
3037 } else {
3038 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d fp registers", count);
3039 }
3040 block_comment(buffer);
3041 }
3042 #endif
3043
3044 if (mode == PushPopSVE) {
3045 sub(stack, stack, sve_vector_size_in_bytes * count);
3046 for (int i = 0; i < count; i++) {
3047 sve_str(as_FloatRegister(regs[i]), Address(stack, i));
3048 }
3049 return count * sve_vector_size_in_bytes / 8;
3050 }
3051
3052 if (mode == PushPopNeon) {
3053 if (count == 1) {
3054 strq(as_FloatRegister(regs[0]), Address(pre(stack, -wordSize * 2)));
3055 return 2;
3056 }
3057
3058 bool odd = (count & 1) == 1;
3059 int push_slots = count + (odd ? 1 : 0);
3060
3061 // Always pushing full 128 bit registers.
3062 stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize * 2)));
3063 words_pushed += 2;
3064
3065 for (int i = 2; i + 1 < count; i += 2) {
3066 stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3067 words_pushed += 2;
3068 }
3069
3070 if (odd) {
3071 strq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3072 words_pushed++;
3073 }
3074
3075 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3076 return count * 2;
3077 }
3078
3079 if (mode == PushPopFp) {
3080 bool odd = (count & 1) == 1;
3081 int push_slots = count + (odd ? 1 : 0);
3082
3083 if (count == 1) {
3084 // Stack pointer must be 16 bytes aligned
3085 strd(as_FloatRegister(regs[0]), Address(pre(stack, -push_slots * wordSize)));
3086 return 1;
3087 }
3088
3089 stpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize)));
3090 words_pushed += 2;
3091
3092 for (int i = 2; i + 1 < count; i += 2) {
3093 stpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3094 words_pushed += 2;
3095 }
3096
3097 if (odd) {
3098 // Stack pointer must be 16 bytes aligned
3099 strd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3100 words_pushed++;
3101 }
3102
3103 assert(words_pushed == count, "oops, pushed != count");
3104
3105 return count;
3106 }
3107
3108 return 0;
3109 }
3110
3111 // Return the number of dwords popped
3112 int MacroAssembler::pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
3113 int words_pushed = 0;
3114 bool use_sve = false;
3115 int sve_vector_size_in_bytes = 0;
3116
3117 #ifdef COMPILER2
3118 use_sve = Matcher::supports_scalable_vector();
3119 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
3120 #endif
3121 // Scan bitset to accumulate register pairs
3122 unsigned char regs[32];
3123 int count = 0;
3124 for (int reg = 0; reg <= 31; reg++) {
3125 if (1 & bitset)
3126 regs[count++] = reg;
3127 bitset >>= 1;
3128 }
3129
3130 if (count == 0) {
3131 return 0;
3132 }
3133
3134 if (mode == PushPopFull) {
3135 if (use_sve && sve_vector_size_in_bytes > 16) {
3136 mode = PushPopSVE;
3137 } else {
3138 mode = PushPopNeon;
3139 }
3140 }
3141
3142 #ifndef PRODUCT
3143 {
3144 char buffer[48];
3145 if (mode == PushPopSVE) {
3146 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d SVE registers", count);
3147 } else if (mode == PushPopNeon) {
3148 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d Neon registers", count);
3149 } else {
3150 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d fp registers", count);
3151 }
3152 block_comment(buffer);
3153 }
3154 #endif
3155
3156 if (mode == PushPopSVE) {
3157 for (int i = count - 1; i >= 0; i--) {
3158 sve_ldr(as_FloatRegister(regs[i]), Address(stack, i));
3159 }
3160 add(stack, stack, sve_vector_size_in_bytes * count);
3161 return count * sve_vector_size_in_bytes / 8;
3162 }
3163
3164 if (mode == PushPopNeon) {
3165 if (count == 1) {
3166 ldrq(as_FloatRegister(regs[0]), Address(post(stack, wordSize * 2)));
3167 return 2;
3168 }
3169
3170 bool odd = (count & 1) == 1;
3171 int push_slots = count + (odd ? 1 : 0);
3172
3173 if (odd) {
3174 ldrq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3175 words_pushed++;
3176 }
3177
3178 for (int i = 2; i + 1 < count; i += 2) {
3179 ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3180 words_pushed += 2;
3181 }
3182
3183 ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize * 2)));
3184 words_pushed += 2;
3185
3186 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3187
3188 return count * 2;
3189 }
3190
3191 if (mode == PushPopFp) {
3192 bool odd = (count & 1) == 1;
3193 int push_slots = count + (odd ? 1 : 0);
3194
3195 if (count == 1) {
3196 ldrd(as_FloatRegister(regs[0]), Address(post(stack, push_slots * wordSize)));
3197 return 1;
3198 }
3199
3200 if (odd) {
3201 ldrd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3202 words_pushed++;
3203 }
3204
3205 for (int i = 2; i + 1 < count; i += 2) {
3206 ldpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3207 words_pushed += 2;
3208 }
3209
3210 ldpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize)));
3211 words_pushed += 2;
3212
3213 assert(words_pushed == count, "oops, pushed != count");
3214
3215 return count;
3216 }
3217
3218 return 0;
3219 }
3220
3221 // Return the number of dwords pushed
3222 int MacroAssembler::push_p(unsigned int bitset, Register stack) {
3223 bool use_sve = false;
3224 int sve_predicate_size_in_slots = 0;
3225
3226 #ifdef COMPILER2
3227 use_sve = Matcher::supports_scalable_vector();
3228 if (use_sve) {
3229 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3230 }
3231 #endif
3232
3233 if (!use_sve) {
3234 return 0;
3235 }
3236
3237 unsigned char regs[PRegister::number_of_registers];
3238 int count = 0;
3239 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3240 if (1 & bitset)
3241 regs[count++] = reg;
3242 bitset >>= 1;
3243 }
3244
3245 if (count == 0) {
3246 return 0;
3247 }
3248
3249 int total_push_bytes = align_up(sve_predicate_size_in_slots *
3250 VMRegImpl::stack_slot_size * count, 16);
3251 sub(stack, stack, total_push_bytes);
3252 for (int i = 0; i < count; i++) {
3253 sve_str(as_PRegister(regs[i]), Address(stack, i));
3254 }
3255 return total_push_bytes / 8;
3256 }
3257
3258 // Return the number of dwords popped
3259 int MacroAssembler::pop_p(unsigned int bitset, Register stack) {
3260 bool use_sve = false;
3261 int sve_predicate_size_in_slots = 0;
3262
3263 #ifdef COMPILER2
3264 use_sve = Matcher::supports_scalable_vector();
3265 if (use_sve) {
3266 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3267 }
3268 #endif
3269
3270 if (!use_sve) {
3271 return 0;
3272 }
3273
3274 unsigned char regs[PRegister::number_of_registers];
3275 int count = 0;
3276 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3277 if (1 & bitset)
3278 regs[count++] = reg;
3279 bitset >>= 1;
3280 }
3281
3282 if (count == 0) {
3283 return 0;
3284 }
3285
3286 int total_pop_bytes = align_up(sve_predicate_size_in_slots *
3287 VMRegImpl::stack_slot_size * count, 16);
3288 for (int i = count - 1; i >= 0; i--) {
3289 sve_ldr(as_PRegister(regs[i]), Address(stack, i));
3290 }
3291 add(stack, stack, total_pop_bytes);
3292 return total_pop_bytes / 8;
3293 }
3294
3295 #ifdef ASSERT
3296 void MacroAssembler::verify_heapbase(const char* msg) {
3297 #if 0
3298 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
3299 assert (Universe::heap() != nullptr, "java heap should be initialized");
3300 if (!UseCompressedOops || Universe::ptr_base() == nullptr) {
3301 // rheapbase is allocated as general register
3302 return;
3303 }
3304 if (CheckCompressedOops) {
3305 Label ok;
3306 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
3307 cmpptr(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3308 br(Assembler::EQ, ok);
3309 stop(msg);
3310 bind(ok);
3311 pop(1 << rscratch1->encoding(), sp);
3312 }
3313 #endif
3314 }
3315 #endif
3316
3317 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2) {
3318 assert_different_registers(value, tmp1, tmp2);
3319 Label done, tagged, weak_tagged;
3320
3321 cbz(value, done); // Use null as-is.
3322 tst(value, JNIHandles::tag_mask); // Test for tag.
3323 br(Assembler::NE, tagged);
3324
3325 // Resolve local handle
3326 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp1, tmp2);
3327 verify_oop(value);
3328 b(done);
3329
3330 bind(tagged);
3331 STATIC_ASSERT(JNIHandles::TypeTag::weak_global == 0b1);
3332 tbnz(value, 0, weak_tagged); // Test for weak tag.
3333
3334 // Resolve global handle
3335 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3336 verify_oop(value);
3337 b(done);
3338
3339 bind(weak_tagged);
3340 // Resolve jweak.
3341 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3342 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp1, tmp2);
3343 verify_oop(value);
3344
3345 bind(done);
3346 }
3347
3348 void MacroAssembler::resolve_global_jobject(Register value, Register tmp1, Register tmp2) {
3349 assert_different_registers(value, tmp1, tmp2);
3350 Label done;
3351
3352 cbz(value, done); // Use null as-is.
3353
3354 #ifdef ASSERT
3355 {
3356 STATIC_ASSERT(JNIHandles::TypeTag::global == 0b10);
3357 Label valid_global_tag;
3358 tbnz(value, 1, valid_global_tag); // Test for global tag
3359 stop("non global jobject using resolve_global_jobject");
3360 bind(valid_global_tag);
3361 }
3362 #endif
3363
3364 // Resolve global handle
3365 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3366 verify_oop(value);
3367
3368 bind(done);
3369 }
3370
3371 void MacroAssembler::stop(const char* msg) {
3372 // Skip AOT caching C strings in scratch buffer.
3373 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
3374 BLOCK_COMMENT(str);
3375 // load msg into r0 so we can access it from the signal handler
3376 // ExternalAddress enables saving and restoring via the code cache
3377 lea(c_rarg0, ExternalAddress((address) str));
3378 dcps1(0xdeae);
3379 }
3380
3381 void MacroAssembler::unimplemented(const char* what) {
3382 const char* buf = nullptr;
3383 {
3384 ResourceMark rm;
3385 stringStream ss;
3386 ss.print("unimplemented: %s", what);
3387 buf = code_string(ss.as_string());
3388 }
3389 stop(buf);
3390 }
3391
3392 void MacroAssembler::_assert_asm(Assembler::Condition cc, const char* msg) {
3393 #ifdef ASSERT
3394 Label OK;
3395 br(cc, OK);
3396 stop(msg);
3397 bind(OK);
3398 #endif
3399 }
3400
3401 // If a constant does not fit in an immediate field, generate some
3402 // number of MOV instructions and then perform the operation.
3403 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
3404 add_sub_imm_insn insn1,
3405 add_sub_reg_insn insn2,
3406 bool is32) {
3407 assert(Rd != zr, "Rd = zr and not setting flags?");
3408 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3409 if (fits) {
3410 (this->*insn1)(Rd, Rn, imm);
3411 } else {
3412 if (g_uabs(imm) < (1 << 24)) {
3413 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
3414 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
3415 } else {
3416 assert_different_registers(Rd, Rn);
3417 mov(Rd, imm);
3418 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3419 }
3420 }
3421 }
3422
3423 // Separate vsn which sets the flags. Optimisations are more restricted
3424 // because we must set the flags correctly.
3425 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
3426 add_sub_imm_insn insn1,
3427 add_sub_reg_insn insn2,
3428 bool is32) {
3429 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3430 if (fits) {
3431 (this->*insn1)(Rd, Rn, imm);
3432 } else {
3433 assert_different_registers(Rd, Rn);
3434 assert(Rd != zr, "overflow in immediate operand");
3435 mov(Rd, imm);
3436 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3437 }
3438 }
3439
3440
3441 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
3442 if (increment.is_register()) {
3443 add(Rd, Rn, increment.as_register());
3444 } else {
3445 add(Rd, Rn, increment.as_constant());
3446 }
3447 }
3448
3449 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
3450 if (increment.is_register()) {
3451 addw(Rd, Rn, increment.as_register());
3452 } else {
3453 addw(Rd, Rn, increment.as_constant());
3454 }
3455 }
3456
3457 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
3458 if (decrement.is_register()) {
3459 sub(Rd, Rn, decrement.as_register());
3460 } else {
3461 sub(Rd, Rn, decrement.as_constant());
3462 }
3463 }
3464
3465 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
3466 if (decrement.is_register()) {
3467 subw(Rd, Rn, decrement.as_register());
3468 } else {
3469 subw(Rd, Rn, decrement.as_constant());
3470 }
3471 }
3472
3473 void MacroAssembler::reinit_heapbase()
3474 {
3475 if (UseCompressedOops) {
3476 if (Universe::is_fully_initialized() && !AOTCodeCache::is_on_for_dump()) {
3477 mov(rheapbase, CompressedOops::base());
3478 } else {
3479 lea(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3480 ldr(rheapbase, Address(rheapbase));
3481 }
3482 }
3483 }
3484
3485 // A generic CAS; success or failure is in the EQ flag. A weak CAS
3486 // doesn't retry and may fail spuriously. If the oldval is wanted,
3487 // Pass a register for the result, otherwise pass noreg.
3488
3489 // Clobbers rscratch1
3490 void MacroAssembler::cmpxchg(Register addr, Register expected,
3491 Register new_val,
3492 enum operand_size size,
3493 bool acquire, bool release,
3494 bool weak,
3495 Register result) {
3496 if (result == noreg) result = rscratch1;
3497 BLOCK_COMMENT("cmpxchg {");
3498 if (UseLSE) {
3499 mov(result, expected);
3500 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
3501 compare_eq(result, expected, size);
3502 #ifdef ASSERT
3503 // Poison rscratch1 which is written on !UseLSE branch
3504 mov(rscratch1, 0x1f1f1f1f1f1f1f1f);
3505 #endif
3506 } else {
3507 Label retry_load, done;
3508 prfm(Address(addr), PSTL1STRM);
3509 bind(retry_load);
3510 load_exclusive(result, addr, size, acquire);
3511 compare_eq(result, expected, size);
3512 br(Assembler::NE, done);
3513 store_exclusive(rscratch1, new_val, addr, size, release);
3514 if (weak) {
3515 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
3516 } else {
3517 cbnzw(rscratch1, retry_load);
3518 }
3519 bind(done);
3520 }
3521 BLOCK_COMMENT("} cmpxchg");
3522 }
3523
3524 // A generic comparison. Only compares for equality, clobbers rscratch1.
3525 void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) {
3526 if (size == xword) {
3527 cmp(rm, rn);
3528 } else if (size == word) {
3529 cmpw(rm, rn);
3530 } else if (size == halfword) {
3531 eorw(rscratch1, rm, rn);
3532 ands(zr, rscratch1, 0xffff);
3533 } else if (size == byte) {
3534 eorw(rscratch1, rm, rn);
3535 ands(zr, rscratch1, 0xff);
3536 } else {
3537 ShouldNotReachHere();
3538 }
3539 }
3540
3541
3542 static bool different(Register a, RegisterOrConstant b, Register c) {
3543 if (b.is_constant())
3544 return a != c;
3545 else
3546 return a != b.as_register() && a != c && b.as_register() != c;
3547 }
3548
3549 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \
3550 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \
3551 if (UseLSE) { \
3552 prev = prev->is_valid() ? prev : zr; \
3553 if (incr.is_register()) { \
3554 AOP(sz, incr.as_register(), prev, addr); \
3555 } else { \
3556 mov(rscratch2, incr.as_constant()); \
3557 AOP(sz, rscratch2, prev, addr); \
3558 } \
3559 return; \
3560 } \
3561 Register result = rscratch2; \
3562 if (prev->is_valid()) \
3563 result = different(prev, incr, addr) ? prev : rscratch2; \
3564 \
3565 Label retry_load; \
3566 prfm(Address(addr), PSTL1STRM); \
3567 bind(retry_load); \
3568 LDXR(result, addr); \
3569 OP(rscratch1, result, incr); \
3570 STXR(rscratch2, rscratch1, addr); \
3571 cbnzw(rscratch2, retry_load); \
3572 if (prev->is_valid() && prev != result) { \
3573 IOP(prev, rscratch1, incr); \
3574 } \
3575 }
3576
3577 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword)
3578 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
3579 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword)
3580 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word)
3581
3582 #undef ATOMIC_OP
3583
3584 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \
3585 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
3586 if (UseLSE) { \
3587 prev = prev->is_valid() ? prev : zr; \
3588 AOP(sz, newv, prev, addr); \
3589 return; \
3590 } \
3591 Register result = rscratch2; \
3592 if (prev->is_valid()) \
3593 result = different(prev, newv, addr) ? prev : rscratch2; \
3594 \
3595 Label retry_load; \
3596 prfm(Address(addr), PSTL1STRM); \
3597 bind(retry_load); \
3598 LDXR(result, addr); \
3599 STXR(rscratch1, newv, addr); \
3600 cbnzw(rscratch1, retry_load); \
3601 if (prev->is_valid() && prev != result) \
3602 mov(prev, result); \
3603 }
3604
3605 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
3606 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
3607 ATOMIC_XCHG(xchgl, swpl, ldxr, stlxr, Assembler::xword)
3608 ATOMIC_XCHG(xchglw, swpl, ldxrw, stlxrw, Assembler::word)
3609 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
3610 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
3611
3612 #undef ATOMIC_XCHG
3613
3614 #ifndef PRODUCT
3615 extern "C" void findpc(intptr_t x);
3616 #endif
3617
3618 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
3619 {
3620 // In order to get locks to work, we need to fake a in_VM state
3621 if (ShowMessageBoxOnError) {
3622 JavaThread* thread = JavaThread::current();
3623 thread->set_thread_state(_thread_in_vm);
3624 #ifndef PRODUCT
3625 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
3626 ttyLocker ttyl;
3627 BytecodeCounter::print();
3628 }
3629 #endif
3630 if (os::message_box(msg, "Execution stopped, print registers?")) {
3631 ttyLocker ttyl;
3632 tty->print_cr(" pc = 0x%016" PRIx64, pc);
3633 #ifndef PRODUCT
3634 tty->cr();
3635 findpc(pc);
3636 tty->cr();
3637 #endif
3638 tty->print_cr(" r0 = 0x%016" PRIx64, regs[0]);
3639 tty->print_cr(" r1 = 0x%016" PRIx64, regs[1]);
3640 tty->print_cr(" r2 = 0x%016" PRIx64, regs[2]);
3641 tty->print_cr(" r3 = 0x%016" PRIx64, regs[3]);
3642 tty->print_cr(" r4 = 0x%016" PRIx64, regs[4]);
3643 tty->print_cr(" r5 = 0x%016" PRIx64, regs[5]);
3644 tty->print_cr(" r6 = 0x%016" PRIx64, regs[6]);
3645 tty->print_cr(" r7 = 0x%016" PRIx64, regs[7]);
3646 tty->print_cr(" r8 = 0x%016" PRIx64, regs[8]);
3647 tty->print_cr(" r9 = 0x%016" PRIx64, regs[9]);
3648 tty->print_cr("r10 = 0x%016" PRIx64, regs[10]);
3649 tty->print_cr("r11 = 0x%016" PRIx64, regs[11]);
3650 tty->print_cr("r12 = 0x%016" PRIx64, regs[12]);
3651 tty->print_cr("r13 = 0x%016" PRIx64, regs[13]);
3652 tty->print_cr("r14 = 0x%016" PRIx64, regs[14]);
3653 tty->print_cr("r15 = 0x%016" PRIx64, regs[15]);
3654 tty->print_cr("r16 = 0x%016" PRIx64, regs[16]);
3655 tty->print_cr("r17 = 0x%016" PRIx64, regs[17]);
3656 tty->print_cr("r18 = 0x%016" PRIx64, regs[18]);
3657 tty->print_cr("r19 = 0x%016" PRIx64, regs[19]);
3658 tty->print_cr("r20 = 0x%016" PRIx64, regs[20]);
3659 tty->print_cr("r21 = 0x%016" PRIx64, regs[21]);
3660 tty->print_cr("r22 = 0x%016" PRIx64, regs[22]);
3661 tty->print_cr("r23 = 0x%016" PRIx64, regs[23]);
3662 tty->print_cr("r24 = 0x%016" PRIx64, regs[24]);
3663 tty->print_cr("r25 = 0x%016" PRIx64, regs[25]);
3664 tty->print_cr("r26 = 0x%016" PRIx64, regs[26]);
3665 tty->print_cr("r27 = 0x%016" PRIx64, regs[27]);
3666 tty->print_cr("r28 = 0x%016" PRIx64, regs[28]);
3667 tty->print_cr("r30 = 0x%016" PRIx64, regs[30]);
3668 tty->print_cr("r31 = 0x%016" PRIx64, regs[31]);
3669 BREAKPOINT;
3670 }
3671 }
3672 fatal("DEBUG MESSAGE: %s", msg);
3673 }
3674
3675 RegSet MacroAssembler::call_clobbered_gp_registers() {
3676 RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2);
3677 #ifndef R18_RESERVED
3678 regs += r18_tls;
3679 #endif
3680 return regs;
3681 }
3682
3683 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
3684 int step = 4 * wordSize;
3685 push(call_clobbered_gp_registers() - exclude, sp);
3686 sub(sp, sp, step);
3687 mov(rscratch1, -step);
3688 // Push v0-v7, v16-v31.
3689 for (int i = 31; i>= 4; i -= 4) {
3690 if (i <= v7->encoding() || i >= v16->encoding())
3691 st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1),
3692 as_FloatRegister(i), T1D, Address(post(sp, rscratch1)));
3693 }
3694 st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2),
3695 as_FloatRegister(3), T1D, Address(sp));
3696 }
3697
3698 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
3699 for (int i = 0; i < 32; i += 4) {
3700 if (i <= v7->encoding() || i >= v16->encoding())
3701 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3702 as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
3703 }
3704
3705 reinitialize_ptrue();
3706
3707 pop(call_clobbered_gp_registers() - exclude, sp);
3708 }
3709
3710 void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve,
3711 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3712 push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
3713 if (save_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3714 sub(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3715 for (int i = 0; i < FloatRegister::number_of_registers; i++) {
3716 sve_str(as_FloatRegister(i), Address(sp, i));
3717 }
3718 } else {
3719 int step = (save_vectors ? 8 : 4) * wordSize;
3720 mov(rscratch1, -step);
3721 sub(sp, sp, step);
3722 for (int i = 28; i >= 4; i -= 4) {
3723 st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3724 as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1)));
3725 }
3726 st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp);
3727 }
3728 if (save_vectors && use_sve && total_predicate_in_bytes > 0) {
3729 sub(sp, sp, total_predicate_in_bytes);
3730 for (int i = 0; i < PRegister::number_of_registers; i++) {
3731 sve_str(as_PRegister(i), Address(sp, i));
3732 }
3733 }
3734 }
3735
3736 void MacroAssembler::pop_CPU_state(bool restore_vectors, bool use_sve,
3737 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3738 if (restore_vectors && use_sve && total_predicate_in_bytes > 0) {
3739 for (int i = PRegister::number_of_registers - 1; i >= 0; i--) {
3740 sve_ldr(as_PRegister(i), Address(sp, i));
3741 }
3742 add(sp, sp, total_predicate_in_bytes);
3743 }
3744 if (restore_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3745 for (int i = FloatRegister::number_of_registers - 1; i >= 0; i--) {
3746 sve_ldr(as_FloatRegister(i), Address(sp, i));
3747 }
3748 add(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3749 } else {
3750 int step = (restore_vectors ? 8 : 4) * wordSize;
3751 for (int i = 0; i <= 28; i += 4)
3752 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3753 as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step)));
3754 }
3755
3756 // We may use predicate registers and rely on ptrue with SVE,
3757 // regardless of wide vector (> 8 bytes) used or not.
3758 if (use_sve) {
3759 reinitialize_ptrue();
3760 }
3761
3762 // integer registers except lr & sp
3763 pop(RegSet::range(r0, r17), sp);
3764 #ifdef R18_RESERVED
3765 ldp(zr, r19, Address(post(sp, 2 * wordSize)));
3766 pop(RegSet::range(r20, r29), sp);
3767 #else
3768 pop(RegSet::range(r18_tls, r29), sp);
3769 #endif
3770 }
3771
3772 /**
3773 * Helpers for multiply_to_len().
3774 */
3775 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
3776 Register src1, Register src2) {
3777 adds(dest_lo, dest_lo, src1);
3778 adc(dest_hi, dest_hi, zr);
3779 adds(dest_lo, dest_lo, src2);
3780 adc(final_dest_hi, dest_hi, zr);
3781 }
3782
3783 // Generate an address from (r + r1 extend offset). "size" is the
3784 // size of the operand. The result may be in rscratch2.
3785 Address MacroAssembler::offsetted_address(Register r, Register r1,
3786 Address::extend ext, int offset, int size) {
3787 if (offset || (ext.shift() % size != 0)) {
3788 lea(rscratch2, Address(r, r1, ext));
3789 return Address(rscratch2, offset);
3790 } else {
3791 return Address(r, r1, ext);
3792 }
3793 }
3794
3795 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
3796 {
3797 assert(offset >= 0, "spill to negative address?");
3798 // Offset reachable ?
3799 // Not aligned - 9 bits signed offset
3800 // Aligned - 12 bits unsigned offset shifted
3801 Register base = sp;
3802 if ((offset & (size-1)) && offset >= (1<<8)) {
3803 add(tmp, base, offset & ((1<<12)-1));
3804 base = tmp;
3805 offset &= -1u<<12;
3806 }
3807
3808 if (offset >= (1<<12) * size) {
3809 add(tmp, base, offset & (((1<<12)-1)<<12));
3810 base = tmp;
3811 offset &= ~(((1<<12)-1)<<12);
3812 }
3813
3814 return Address(base, offset);
3815 }
3816
3817 Address MacroAssembler::sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp) {
3818 assert(offset >= 0, "spill to negative address?");
3819
3820 Register base = sp;
3821
3822 // An immediate offset in the range 0 to 255 which is multiplied
3823 // by the current vector or predicate register size in bytes.
3824 if (offset % sve_reg_size_in_bytes == 0 && offset < ((1<<8)*sve_reg_size_in_bytes)) {
3825 return Address(base, offset / sve_reg_size_in_bytes);
3826 }
3827
3828 add(tmp, base, offset);
3829 return Address(tmp);
3830 }
3831
3832 // Checks whether offset is aligned.
3833 // Returns true if it is, else false.
3834 bool MacroAssembler::merge_alignment_check(Register base,
3835 size_t size,
3836 int64_t cur_offset,
3837 int64_t prev_offset) const {
3838 if (AvoidUnalignedAccesses) {
3839 if (base == sp) {
3840 // Checks whether low offset if aligned to pair of registers.
3841 int64_t pair_mask = size * 2 - 1;
3842 int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3843 return (offset & pair_mask) == 0;
3844 } else { // If base is not sp, we can't guarantee the access is aligned.
3845 return false;
3846 }
3847 } else {
3848 int64_t mask = size - 1;
3849 // Load/store pair instruction only supports element size aligned offset.
3850 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
3851 }
3852 }
3853
3854 // Checks whether current and previous loads/stores can be merged.
3855 // Returns true if it can be merged, else false.
3856 bool MacroAssembler::ldst_can_merge(Register rt,
3857 const Address &adr,
3858 size_t cur_size_in_bytes,
3859 bool is_store) const {
3860 address prev = pc() - NativeInstruction::instruction_size;
3861 address last = code()->last_insn();
3862
3863 if (last == nullptr || !nativeInstruction_at(last)->is_Imm_LdSt()) {
3864 return false;
3865 }
3866
3867 if (adr.getMode() != Address::base_plus_offset || prev != last) {
3868 return false;
3869 }
3870
3871 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3872 size_t prev_size_in_bytes = prev_ldst->size_in_bytes();
3873
3874 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging.");
3875 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging.");
3876
3877 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) {
3878 return false;
3879 }
3880
3881 int64_t max_offset = 63 * prev_size_in_bytes;
3882 int64_t min_offset = -64 * prev_size_in_bytes;
3883
3884 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
3885
3886 // Only same base can be merged.
3887 if (adr.base() != prev_ldst->base()) {
3888 return false;
3889 }
3890
3891 int64_t cur_offset = adr.offset();
3892 int64_t prev_offset = prev_ldst->offset();
3893 size_t diff = abs(cur_offset - prev_offset);
3894 if (diff != prev_size_in_bytes) {
3895 return false;
3896 }
3897
3898 // Following cases can not be merged:
3899 // ldr x2, [x2, #8]
3900 // ldr x3, [x2, #16]
3901 // or:
3902 // ldr x2, [x3, #8]
3903 // ldr x2, [x3, #16]
3904 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL.
3905 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) {
3906 return false;
3907 }
3908
3909 int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3910 // Offset range must be in ldp/stp instruction's range.
3911 if (low_offset > max_offset || low_offset < min_offset) {
3912 return false;
3913 }
3914
3915 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) {
3916 return true;
3917 }
3918
3919 return false;
3920 }
3921
3922 // Merge current load/store with previous load/store into ldp/stp.
3923 void MacroAssembler::merge_ldst(Register rt,
3924 const Address &adr,
3925 size_t cur_size_in_bytes,
3926 bool is_store) {
3927
3928 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged.");
3929
3930 Register rt_low, rt_high;
3931 address prev = pc() - NativeInstruction::instruction_size;
3932 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3933
3934 int64_t offset;
3935
3936 if (adr.offset() < prev_ldst->offset()) {
3937 offset = adr.offset();
3938 rt_low = rt;
3939 rt_high = prev_ldst->target();
3940 } else {
3941 offset = prev_ldst->offset();
3942 rt_low = prev_ldst->target();
3943 rt_high = rt;
3944 }
3945
3946 Address adr_p = Address(prev_ldst->base(), offset);
3947 // Overwrite previous generated binary.
3948 code_section()->set_end(prev);
3949
3950 const size_t sz = prev_ldst->size_in_bytes();
3951 assert(sz == 8 || sz == 4, "only supports 64/32bit merging.");
3952 if (!is_store) {
3953 BLOCK_COMMENT("merged ldr pair");
3954 if (sz == 8) {
3955 ldp(rt_low, rt_high, adr_p);
3956 } else {
3957 ldpw(rt_low, rt_high, adr_p);
3958 }
3959 } else {
3960 BLOCK_COMMENT("merged str pair");
3961 if (sz == 8) {
3962 stp(rt_low, rt_high, adr_p);
3963 } else {
3964 stpw(rt_low, rt_high, adr_p);
3965 }
3966 }
3967 }
3968
3969 /**
3970 * Multiply 64 bit by 64 bit first loop.
3971 */
3972 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
3973 Register y, Register y_idx, Register z,
3974 Register carry, Register product,
3975 Register idx, Register kdx) {
3976 //
3977 // jlong carry, x[], y[], z[];
3978 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
3979 // huge_128 product = y[idx] * x[xstart] + carry;
3980 // z[kdx] = (jlong)product;
3981 // carry = (jlong)(product >>> 64);
3982 // }
3983 // z[xstart] = carry;
3984 //
3985
3986 Label L_first_loop, L_first_loop_exit;
3987 Label L_one_x, L_one_y, L_multiply;
3988
3989 subsw(xstart, xstart, 1);
3990 br(Assembler::MI, L_one_x);
3991
3992 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
3993 ldr(x_xstart, Address(rscratch1));
3994 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
3995
3996 bind(L_first_loop);
3997 subsw(idx, idx, 1);
3998 br(Assembler::MI, L_first_loop_exit);
3999 subsw(idx, idx, 1);
4000 br(Assembler::MI, L_one_y);
4001 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4002 ldr(y_idx, Address(rscratch1));
4003 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
4004 bind(L_multiply);
4005
4006 // AArch64 has a multiply-accumulate instruction that we can't use
4007 // here because it has no way to process carries, so we have to use
4008 // separate add and adc instructions. Bah.
4009 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
4010 mul(product, x_xstart, y_idx);
4011 adds(product, product, carry);
4012 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
4013
4014 subw(kdx, kdx, 2);
4015 ror(product, product, 32); // back to big-endian
4016 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
4017
4018 b(L_first_loop);
4019
4020 bind(L_one_y);
4021 ldrw(y_idx, Address(y, 0));
4022 b(L_multiply);
4023
4024 bind(L_one_x);
4025 ldrw(x_xstart, Address(x, 0));
4026 b(L_first_loop);
4027
4028 bind(L_first_loop_exit);
4029 }
4030
4031 /**
4032 * Multiply 128 bit by 128. Unrolled inner loop.
4033 *
4034 */
4035 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
4036 Register carry, Register carry2,
4037 Register idx, Register jdx,
4038 Register yz_idx1, Register yz_idx2,
4039 Register tmp, Register tmp3, Register tmp4,
4040 Register tmp6, Register product_hi) {
4041
4042 // jlong carry, x[], y[], z[];
4043 // int kdx = ystart+1;
4044 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
4045 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
4046 // jlong carry2 = (jlong)(tmp3 >>> 64);
4047 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
4048 // carry = (jlong)(tmp4 >>> 64);
4049 // z[kdx+idx+1] = (jlong)tmp3;
4050 // z[kdx+idx] = (jlong)tmp4;
4051 // }
4052 // idx += 2;
4053 // if (idx > 0) {
4054 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
4055 // z[kdx+idx] = (jlong)yz_idx1;
4056 // carry = (jlong)(yz_idx1 >>> 64);
4057 // }
4058 //
4059
4060 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
4061
4062 lsrw(jdx, idx, 2);
4063
4064 bind(L_third_loop);
4065
4066 subsw(jdx, jdx, 1);
4067 br(Assembler::MI, L_third_loop_exit);
4068 subw(idx, idx, 4);
4069
4070 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4071
4072 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
4073
4074 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4075
4076 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
4077 ror(yz_idx2, yz_idx2, 32);
4078
4079 ldp(rscratch2, rscratch1, Address(tmp6, 0));
4080
4081 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4082 umulh(tmp4, product_hi, yz_idx1);
4083
4084 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
4085 ror(rscratch2, rscratch2, 32);
4086
4087 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
4088 umulh(carry2, product_hi, yz_idx2);
4089
4090 // propagate sum of both multiplications into carry:tmp4:tmp3
4091 adds(tmp3, tmp3, carry);
4092 adc(tmp4, tmp4, zr);
4093 adds(tmp3, tmp3, rscratch1);
4094 adcs(tmp4, tmp4, tmp);
4095 adc(carry, carry2, zr);
4096 adds(tmp4, tmp4, rscratch2);
4097 adc(carry, carry, zr);
4098
4099 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
4100 ror(tmp4, tmp4, 32);
4101 stp(tmp4, tmp3, Address(tmp6, 0));
4102
4103 b(L_third_loop);
4104 bind (L_third_loop_exit);
4105
4106 andw (idx, idx, 0x3);
4107 cbz(idx, L_post_third_loop_done);
4108
4109 Label L_check_1;
4110 subsw(idx, idx, 2);
4111 br(Assembler::MI, L_check_1);
4112
4113 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4114 ldr(yz_idx1, Address(rscratch1, 0));
4115 ror(yz_idx1, yz_idx1, 32);
4116 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4117 umulh(tmp4, product_hi, yz_idx1);
4118 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4119 ldr(yz_idx2, Address(rscratch1, 0));
4120 ror(yz_idx2, yz_idx2, 32);
4121
4122 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
4123
4124 ror(tmp3, tmp3, 32);
4125 str(tmp3, Address(rscratch1, 0));
4126
4127 bind (L_check_1);
4128
4129 andw (idx, idx, 0x1);
4130 subsw(idx, idx, 1);
4131 br(Assembler::MI, L_post_third_loop_done);
4132 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4133 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
4134 umulh(carry2, tmp4, product_hi);
4135 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4136
4137 add2_with_carry(carry2, tmp3, tmp4, carry);
4138
4139 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4140 extr(carry, carry2, tmp3, 32);
4141
4142 bind(L_post_third_loop_done);
4143 }
4144
4145 /**
4146 * Code for BigInteger::multiplyToLen() intrinsic.
4147 *
4148 * r0: x
4149 * r1: xlen
4150 * r2: y
4151 * r3: ylen
4152 * r4: z
4153 * r5: tmp0
4154 * r10: tmp1
4155 * r11: tmp2
4156 * r12: tmp3
4157 * r13: tmp4
4158 * r14: tmp5
4159 * r15: tmp6
4160 * r16: tmp7
4161 *
4162 */
4163 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
4164 Register z, Register tmp0,
4165 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
4166 Register tmp5, Register tmp6, Register product_hi) {
4167
4168 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, product_hi);
4169
4170 const Register idx = tmp1;
4171 const Register kdx = tmp2;
4172 const Register xstart = tmp3;
4173
4174 const Register y_idx = tmp4;
4175 const Register carry = tmp5;
4176 const Register product = xlen;
4177 const Register x_xstart = tmp0;
4178
4179 // First Loop.
4180 //
4181 // final static long LONG_MASK = 0xffffffffL;
4182 // int xstart = xlen - 1;
4183 // int ystart = ylen - 1;
4184 // long carry = 0;
4185 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
4186 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
4187 // z[kdx] = (int)product;
4188 // carry = product >>> 32;
4189 // }
4190 // z[xstart] = (int)carry;
4191 //
4192
4193 movw(idx, ylen); // idx = ylen;
4194 addw(kdx, xlen, ylen); // kdx = xlen+ylen;
4195 mov(carry, zr); // carry = 0;
4196
4197 Label L_done;
4198
4199 movw(xstart, xlen);
4200 subsw(xstart, xstart, 1);
4201 br(Assembler::MI, L_done);
4202
4203 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
4204
4205 Label L_second_loop;
4206 cbzw(kdx, L_second_loop);
4207
4208 Label L_carry;
4209 subw(kdx, kdx, 1);
4210 cbzw(kdx, L_carry);
4211
4212 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4213 lsr(carry, carry, 32);
4214 subw(kdx, kdx, 1);
4215
4216 bind(L_carry);
4217 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4218
4219 // Second and third (nested) loops.
4220 //
4221 // for (int i = xstart-1; i >= 0; i--) { // Second loop
4222 // carry = 0;
4223 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
4224 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
4225 // (z[k] & LONG_MASK) + carry;
4226 // z[k] = (int)product;
4227 // carry = product >>> 32;
4228 // }
4229 // z[i] = (int)carry;
4230 // }
4231 //
4232 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
4233
4234 const Register jdx = tmp1;
4235
4236 bind(L_second_loop);
4237 mov(carry, zr); // carry = 0;
4238 movw(jdx, ylen); // j = ystart+1
4239
4240 subsw(xstart, xstart, 1); // i = xstart-1;
4241 br(Assembler::MI, L_done);
4242
4243 str(z, Address(pre(sp, -4 * wordSize)));
4244
4245 Label L_last_x;
4246 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
4247 subsw(xstart, xstart, 1); // i = xstart-1;
4248 br(Assembler::MI, L_last_x);
4249
4250 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
4251 ldr(product_hi, Address(rscratch1));
4252 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
4253
4254 Label L_third_loop_prologue;
4255 bind(L_third_loop_prologue);
4256
4257 str(ylen, Address(sp, wordSize));
4258 stp(x, xstart, Address(sp, 2 * wordSize));
4259 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
4260 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
4261 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
4262 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
4263
4264 addw(tmp3, xlen, 1);
4265 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4266 subsw(tmp3, tmp3, 1);
4267 br(Assembler::MI, L_done);
4268
4269 lsr(carry, carry, 32);
4270 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4271 b(L_second_loop);
4272
4273 // Next infrequent code is moved outside loops.
4274 bind(L_last_x);
4275 ldrw(product_hi, Address(x, 0));
4276 b(L_third_loop_prologue);
4277
4278 bind(L_done);
4279 }
4280
4281 // Code for BigInteger::mulAdd intrinsic
4282 // out = r0
4283 // in = r1
4284 // offset = r2 (already out.length-offset)
4285 // len = r3
4286 // k = r4
4287 //
4288 // pseudo code from java implementation:
4289 // carry = 0;
4290 // offset = out.length-offset - 1;
4291 // for (int j=len-1; j >= 0; j--) {
4292 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry;
4293 // out[offset--] = (int)product;
4294 // carry = product >>> 32;
4295 // }
4296 // return (int)carry;
4297 void MacroAssembler::mul_add(Register out, Register in, Register offset,
4298 Register len, Register k) {
4299 Label LOOP, END;
4300 // pre-loop
4301 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches
4302 csel(out, zr, out, Assembler::EQ);
4303 br(Assembler::EQ, END);
4304 add(in, in, len, LSL, 2); // in[j+1] address
4305 add(offset, out, offset, LSL, 2); // out[offset + 1] address
4306 mov(out, zr); // used to keep carry now
4307 BIND(LOOP);
4308 ldrw(rscratch1, Address(pre(in, -4)));
4309 madd(rscratch1, rscratch1, k, out);
4310 ldrw(rscratch2, Address(pre(offset, -4)));
4311 add(rscratch1, rscratch1, rscratch2);
4312 strw(rscratch1, Address(offset));
4313 lsr(out, rscratch1, 32);
4314 subs(len, len, 1);
4315 br(Assembler::NE, LOOP);
4316 BIND(END);
4317 }
4318
4319 /**
4320 * Emits code to update CRC-32 with a byte value according to constants in table
4321 *
4322 * @param [in,out]crc Register containing the crc.
4323 * @param [in]val Register containing the byte to fold into the CRC.
4324 * @param [in]table Register containing the table of crc constants.
4325 *
4326 * uint32_t crc;
4327 * val = crc_table[(val ^ crc) & 0xFF];
4328 * crc = val ^ (crc >> 8);
4329 *
4330 */
4331 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
4332 eor(val, val, crc);
4333 andr(val, val, 0xff);
4334 ldrw(val, Address(table, val, Address::lsl(2)));
4335 eor(crc, val, crc, Assembler::LSR, 8);
4336 }
4337
4338 /**
4339 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
4340 *
4341 * @param [in,out]crc Register containing the crc.
4342 * @param [in]v Register containing the 32-bit to fold into the CRC.
4343 * @param [in]table0 Register containing table 0 of crc constants.
4344 * @param [in]table1 Register containing table 1 of crc constants.
4345 * @param [in]table2 Register containing table 2 of crc constants.
4346 * @param [in]table3 Register containing table 3 of crc constants.
4347 *
4348 * uint32_t crc;
4349 * v = crc ^ v
4350 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
4351 *
4352 */
4353 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
4354 Register table0, Register table1, Register table2, Register table3,
4355 bool upper) {
4356 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
4357 uxtb(tmp, v);
4358 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
4359 ubfx(tmp, v, 8, 8);
4360 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
4361 eor(crc, crc, tmp);
4362 ubfx(tmp, v, 16, 8);
4363 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
4364 eor(crc, crc, tmp);
4365 ubfx(tmp, v, 24, 8);
4366 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
4367 eor(crc, crc, tmp);
4368 }
4369
4370 void MacroAssembler::kernel_crc32_using_crypto_pmull(Register crc, Register buf,
4371 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4372 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4373 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4374
4375 subs(tmp0, len, 384);
4376 mvnw(crc, crc);
4377 br(Assembler::GE, CRC_by128_pre);
4378 BIND(CRC_less128);
4379 subs(len, len, 32);
4380 br(Assembler::GE, CRC_by32_loop);
4381 BIND(CRC_less32);
4382 adds(len, len, 32 - 4);
4383 br(Assembler::GE, CRC_by4_loop);
4384 adds(len, len, 4);
4385 br(Assembler::GT, CRC_by1_loop);
4386 b(L_exit);
4387
4388 BIND(CRC_by32_loop);
4389 ldp(tmp0, tmp1, Address(buf));
4390 crc32x(crc, crc, tmp0);
4391 ldp(tmp2, tmp3, Address(buf, 16));
4392 crc32x(crc, crc, tmp1);
4393 add(buf, buf, 32);
4394 crc32x(crc, crc, tmp2);
4395 subs(len, len, 32);
4396 crc32x(crc, crc, tmp3);
4397 br(Assembler::GE, CRC_by32_loop);
4398 cmn(len, (u1)32);
4399 br(Assembler::NE, CRC_less32);
4400 b(L_exit);
4401
4402 BIND(CRC_by4_loop);
4403 ldrw(tmp0, Address(post(buf, 4)));
4404 subs(len, len, 4);
4405 crc32w(crc, crc, tmp0);
4406 br(Assembler::GE, CRC_by4_loop);
4407 adds(len, len, 4);
4408 br(Assembler::LE, L_exit);
4409 BIND(CRC_by1_loop);
4410 ldrb(tmp0, Address(post(buf, 1)));
4411 subs(len, len, 1);
4412 crc32b(crc, crc, tmp0);
4413 br(Assembler::GT, CRC_by1_loop);
4414 b(L_exit);
4415
4416 BIND(CRC_by128_pre);
4417 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4418 4*256*sizeof(juint) + 8*sizeof(juint));
4419 mov(crc, 0);
4420 crc32x(crc, crc, tmp0);
4421 crc32x(crc, crc, tmp1);
4422
4423 cbnz(len, CRC_less128);
4424
4425 BIND(L_exit);
4426 mvnw(crc, crc);
4427 }
4428
4429 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf,
4430 Register len, Register tmp0, Register tmp1, Register tmp2,
4431 Register tmp3) {
4432 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4433 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4434
4435 mvnw(crc, crc);
4436
4437 subs(len, len, 128);
4438 br(Assembler::GE, CRC_by64_pre);
4439 BIND(CRC_less64);
4440 adds(len, len, 128-32);
4441 br(Assembler::GE, CRC_by32_loop);
4442 BIND(CRC_less32);
4443 adds(len, len, 32-4);
4444 br(Assembler::GE, CRC_by4_loop);
4445 adds(len, len, 4);
4446 br(Assembler::GT, CRC_by1_loop);
4447 b(L_exit);
4448
4449 BIND(CRC_by32_loop);
4450 ldp(tmp0, tmp1, Address(post(buf, 16)));
4451 subs(len, len, 32);
4452 crc32x(crc, crc, tmp0);
4453 ldr(tmp2, Address(post(buf, 8)));
4454 crc32x(crc, crc, tmp1);
4455 ldr(tmp3, Address(post(buf, 8)));
4456 crc32x(crc, crc, tmp2);
4457 crc32x(crc, crc, tmp3);
4458 br(Assembler::GE, CRC_by32_loop);
4459 cmn(len, (u1)32);
4460 br(Assembler::NE, CRC_less32);
4461 b(L_exit);
4462
4463 BIND(CRC_by4_loop);
4464 ldrw(tmp0, Address(post(buf, 4)));
4465 subs(len, len, 4);
4466 crc32w(crc, crc, tmp0);
4467 br(Assembler::GE, CRC_by4_loop);
4468 adds(len, len, 4);
4469 br(Assembler::LE, L_exit);
4470 BIND(CRC_by1_loop);
4471 ldrb(tmp0, Address(post(buf, 1)));
4472 subs(len, len, 1);
4473 crc32b(crc, crc, tmp0);
4474 br(Assembler::GT, CRC_by1_loop);
4475 b(L_exit);
4476
4477 BIND(CRC_by64_pre);
4478 sub(buf, buf, 8);
4479 ldp(tmp0, tmp1, Address(buf, 8));
4480 crc32x(crc, crc, tmp0);
4481 ldr(tmp2, Address(buf, 24));
4482 crc32x(crc, crc, tmp1);
4483 ldr(tmp3, Address(buf, 32));
4484 crc32x(crc, crc, tmp2);
4485 ldr(tmp0, Address(buf, 40));
4486 crc32x(crc, crc, tmp3);
4487 ldr(tmp1, Address(buf, 48));
4488 crc32x(crc, crc, tmp0);
4489 ldr(tmp2, Address(buf, 56));
4490 crc32x(crc, crc, tmp1);
4491 ldr(tmp3, Address(pre(buf, 64)));
4492
4493 b(CRC_by64_loop);
4494
4495 align(CodeEntryAlignment);
4496 BIND(CRC_by64_loop);
4497 subs(len, len, 64);
4498 crc32x(crc, crc, tmp2);
4499 ldr(tmp0, Address(buf, 8));
4500 crc32x(crc, crc, tmp3);
4501 ldr(tmp1, Address(buf, 16));
4502 crc32x(crc, crc, tmp0);
4503 ldr(tmp2, Address(buf, 24));
4504 crc32x(crc, crc, tmp1);
4505 ldr(tmp3, Address(buf, 32));
4506 crc32x(crc, crc, tmp2);
4507 ldr(tmp0, Address(buf, 40));
4508 crc32x(crc, crc, tmp3);
4509 ldr(tmp1, Address(buf, 48));
4510 crc32x(crc, crc, tmp0);
4511 ldr(tmp2, Address(buf, 56));
4512 crc32x(crc, crc, tmp1);
4513 ldr(tmp3, Address(pre(buf, 64)));
4514 br(Assembler::GE, CRC_by64_loop);
4515
4516 // post-loop
4517 crc32x(crc, crc, tmp2);
4518 crc32x(crc, crc, tmp3);
4519
4520 sub(len, len, 64);
4521 add(buf, buf, 8);
4522 cmn(len, (u1)128);
4523 br(Assembler::NE, CRC_less64);
4524 BIND(L_exit);
4525 mvnw(crc, crc);
4526 }
4527
4528 /**
4529 * @param crc register containing existing CRC (32-bit)
4530 * @param buf register pointing to input byte buffer (byte*)
4531 * @param len register containing number of bytes
4532 * @param table register that will contain address of CRC table
4533 * @param tmp scratch register
4534 */
4535 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
4536 Register table0, Register table1, Register table2, Register table3,
4537 Register tmp, Register tmp2, Register tmp3) {
4538 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
4539
4540 if (UseCryptoPmullForCRC32) {
4541 kernel_crc32_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4542 return;
4543 }
4544
4545 if (UseCRC32) {
4546 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
4547 return;
4548 }
4549
4550 mvnw(crc, crc);
4551
4552 {
4553 uint64_t offset;
4554 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4555 add(table0, table0, offset);
4556 }
4557 add(table1, table0, 1*256*sizeof(juint));
4558 add(table2, table0, 2*256*sizeof(juint));
4559 add(table3, table0, 3*256*sizeof(juint));
4560
4561 { // Neon code start
4562 cmp(len, (u1)64);
4563 br(Assembler::LT, L_by16);
4564 eor(v16, T16B, v16, v16);
4565
4566 Label L_fold;
4567
4568 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
4569
4570 ld1(v0, v1, T2D, post(buf, 32));
4571 ld1r(v4, T2D, post(tmp, 8));
4572 ld1r(v5, T2D, post(tmp, 8));
4573 ld1r(v6, T2D, post(tmp, 8));
4574 ld1r(v7, T2D, post(tmp, 8));
4575 mov(v16, S, 0, crc);
4576
4577 eor(v0, T16B, v0, v16);
4578 sub(len, len, 64);
4579
4580 BIND(L_fold);
4581 pmull(v22, T8H, v0, v5, T8B);
4582 pmull(v20, T8H, v0, v7, T8B);
4583 pmull(v23, T8H, v0, v4, T8B);
4584 pmull(v21, T8H, v0, v6, T8B);
4585
4586 pmull2(v18, T8H, v0, v5, T16B);
4587 pmull2(v16, T8H, v0, v7, T16B);
4588 pmull2(v19, T8H, v0, v4, T16B);
4589 pmull2(v17, T8H, v0, v6, T16B);
4590
4591 uzp1(v24, T8H, v20, v22);
4592 uzp2(v25, T8H, v20, v22);
4593 eor(v20, T16B, v24, v25);
4594
4595 uzp1(v26, T8H, v16, v18);
4596 uzp2(v27, T8H, v16, v18);
4597 eor(v16, T16B, v26, v27);
4598
4599 ushll2(v22, T4S, v20, T8H, 8);
4600 ushll(v20, T4S, v20, T4H, 8);
4601
4602 ushll2(v18, T4S, v16, T8H, 8);
4603 ushll(v16, T4S, v16, T4H, 8);
4604
4605 eor(v22, T16B, v23, v22);
4606 eor(v18, T16B, v19, v18);
4607 eor(v20, T16B, v21, v20);
4608 eor(v16, T16B, v17, v16);
4609
4610 uzp1(v17, T2D, v16, v20);
4611 uzp2(v21, T2D, v16, v20);
4612 eor(v17, T16B, v17, v21);
4613
4614 ushll2(v20, T2D, v17, T4S, 16);
4615 ushll(v16, T2D, v17, T2S, 16);
4616
4617 eor(v20, T16B, v20, v22);
4618 eor(v16, T16B, v16, v18);
4619
4620 uzp1(v17, T2D, v20, v16);
4621 uzp2(v21, T2D, v20, v16);
4622 eor(v28, T16B, v17, v21);
4623
4624 pmull(v22, T8H, v1, v5, T8B);
4625 pmull(v20, T8H, v1, v7, T8B);
4626 pmull(v23, T8H, v1, v4, T8B);
4627 pmull(v21, T8H, v1, v6, T8B);
4628
4629 pmull2(v18, T8H, v1, v5, T16B);
4630 pmull2(v16, T8H, v1, v7, T16B);
4631 pmull2(v19, T8H, v1, v4, T16B);
4632 pmull2(v17, T8H, v1, v6, T16B);
4633
4634 ld1(v0, v1, T2D, post(buf, 32));
4635
4636 uzp1(v24, T8H, v20, v22);
4637 uzp2(v25, T8H, v20, v22);
4638 eor(v20, T16B, v24, v25);
4639
4640 uzp1(v26, T8H, v16, v18);
4641 uzp2(v27, T8H, v16, v18);
4642 eor(v16, T16B, v26, v27);
4643
4644 ushll2(v22, T4S, v20, T8H, 8);
4645 ushll(v20, T4S, v20, T4H, 8);
4646
4647 ushll2(v18, T4S, v16, T8H, 8);
4648 ushll(v16, T4S, v16, T4H, 8);
4649
4650 eor(v22, T16B, v23, v22);
4651 eor(v18, T16B, v19, v18);
4652 eor(v20, T16B, v21, v20);
4653 eor(v16, T16B, v17, v16);
4654
4655 uzp1(v17, T2D, v16, v20);
4656 uzp2(v21, T2D, v16, v20);
4657 eor(v16, T16B, v17, v21);
4658
4659 ushll2(v20, T2D, v16, T4S, 16);
4660 ushll(v16, T2D, v16, T2S, 16);
4661
4662 eor(v20, T16B, v22, v20);
4663 eor(v16, T16B, v16, v18);
4664
4665 uzp1(v17, T2D, v20, v16);
4666 uzp2(v21, T2D, v20, v16);
4667 eor(v20, T16B, v17, v21);
4668
4669 shl(v16, T2D, v28, 1);
4670 shl(v17, T2D, v20, 1);
4671
4672 eor(v0, T16B, v0, v16);
4673 eor(v1, T16B, v1, v17);
4674
4675 subs(len, len, 32);
4676 br(Assembler::GE, L_fold);
4677
4678 mov(crc, 0);
4679 mov(tmp, v0, D, 0);
4680 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4681 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4682 mov(tmp, v0, D, 1);
4683 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4684 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4685 mov(tmp, v1, D, 0);
4686 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4687 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4688 mov(tmp, v1, D, 1);
4689 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4690 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4691
4692 add(len, len, 32);
4693 } // Neon code end
4694
4695 BIND(L_by16);
4696 subs(len, len, 16);
4697 br(Assembler::GE, L_by16_loop);
4698 adds(len, len, 16-4);
4699 br(Assembler::GE, L_by4_loop);
4700 adds(len, len, 4);
4701 br(Assembler::GT, L_by1_loop);
4702 b(L_exit);
4703
4704 BIND(L_by4_loop);
4705 ldrw(tmp, Address(post(buf, 4)));
4706 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
4707 subs(len, len, 4);
4708 br(Assembler::GE, L_by4_loop);
4709 adds(len, len, 4);
4710 br(Assembler::LE, L_exit);
4711 BIND(L_by1_loop);
4712 subs(len, len, 1);
4713 ldrb(tmp, Address(post(buf, 1)));
4714 update_byte_crc32(crc, tmp, table0);
4715 br(Assembler::GT, L_by1_loop);
4716 b(L_exit);
4717
4718 align(CodeEntryAlignment);
4719 BIND(L_by16_loop);
4720 subs(len, len, 16);
4721 ldp(tmp, tmp3, Address(post(buf, 16)));
4722 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4723 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4724 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
4725 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
4726 br(Assembler::GE, L_by16_loop);
4727 adds(len, len, 16-4);
4728 br(Assembler::GE, L_by4_loop);
4729 adds(len, len, 4);
4730 br(Assembler::GT, L_by1_loop);
4731 BIND(L_exit);
4732 mvnw(crc, crc);
4733 }
4734
4735 void MacroAssembler::kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
4736 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4737 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4738 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4739
4740 subs(tmp0, len, 384);
4741 br(Assembler::GE, CRC_by128_pre);
4742 BIND(CRC_less128);
4743 subs(len, len, 32);
4744 br(Assembler::GE, CRC_by32_loop);
4745 BIND(CRC_less32);
4746 adds(len, len, 32 - 4);
4747 br(Assembler::GE, CRC_by4_loop);
4748 adds(len, len, 4);
4749 br(Assembler::GT, CRC_by1_loop);
4750 b(L_exit);
4751
4752 BIND(CRC_by32_loop);
4753 ldp(tmp0, tmp1, Address(buf));
4754 crc32cx(crc, crc, tmp0);
4755 ldr(tmp2, Address(buf, 16));
4756 crc32cx(crc, crc, tmp1);
4757 ldr(tmp3, Address(buf, 24));
4758 crc32cx(crc, crc, tmp2);
4759 add(buf, buf, 32);
4760 subs(len, len, 32);
4761 crc32cx(crc, crc, tmp3);
4762 br(Assembler::GE, CRC_by32_loop);
4763 cmn(len, (u1)32);
4764 br(Assembler::NE, CRC_less32);
4765 b(L_exit);
4766
4767 BIND(CRC_by4_loop);
4768 ldrw(tmp0, Address(post(buf, 4)));
4769 subs(len, len, 4);
4770 crc32cw(crc, crc, tmp0);
4771 br(Assembler::GE, CRC_by4_loop);
4772 adds(len, len, 4);
4773 br(Assembler::LE, L_exit);
4774 BIND(CRC_by1_loop);
4775 ldrb(tmp0, Address(post(buf, 1)));
4776 subs(len, len, 1);
4777 crc32cb(crc, crc, tmp0);
4778 br(Assembler::GT, CRC_by1_loop);
4779 b(L_exit);
4780
4781 BIND(CRC_by128_pre);
4782 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4783 4*256*sizeof(juint) + 8*sizeof(juint) + 0x50);
4784 mov(crc, 0);
4785 crc32cx(crc, crc, tmp0);
4786 crc32cx(crc, crc, tmp1);
4787
4788 cbnz(len, CRC_less128);
4789
4790 BIND(L_exit);
4791 }
4792
4793 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf,
4794 Register len, Register tmp0, Register tmp1, Register tmp2,
4795 Register tmp3) {
4796 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4797 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4798
4799 subs(len, len, 128);
4800 br(Assembler::GE, CRC_by64_pre);
4801 BIND(CRC_less64);
4802 adds(len, len, 128-32);
4803 br(Assembler::GE, CRC_by32_loop);
4804 BIND(CRC_less32);
4805 adds(len, len, 32-4);
4806 br(Assembler::GE, CRC_by4_loop);
4807 adds(len, len, 4);
4808 br(Assembler::GT, CRC_by1_loop);
4809 b(L_exit);
4810
4811 BIND(CRC_by32_loop);
4812 ldp(tmp0, tmp1, Address(post(buf, 16)));
4813 subs(len, len, 32);
4814 crc32cx(crc, crc, tmp0);
4815 ldr(tmp2, Address(post(buf, 8)));
4816 crc32cx(crc, crc, tmp1);
4817 ldr(tmp3, Address(post(buf, 8)));
4818 crc32cx(crc, crc, tmp2);
4819 crc32cx(crc, crc, tmp3);
4820 br(Assembler::GE, CRC_by32_loop);
4821 cmn(len, (u1)32);
4822 br(Assembler::NE, CRC_less32);
4823 b(L_exit);
4824
4825 BIND(CRC_by4_loop);
4826 ldrw(tmp0, Address(post(buf, 4)));
4827 subs(len, len, 4);
4828 crc32cw(crc, crc, tmp0);
4829 br(Assembler::GE, CRC_by4_loop);
4830 adds(len, len, 4);
4831 br(Assembler::LE, L_exit);
4832 BIND(CRC_by1_loop);
4833 ldrb(tmp0, Address(post(buf, 1)));
4834 subs(len, len, 1);
4835 crc32cb(crc, crc, tmp0);
4836 br(Assembler::GT, CRC_by1_loop);
4837 b(L_exit);
4838
4839 BIND(CRC_by64_pre);
4840 sub(buf, buf, 8);
4841 ldp(tmp0, tmp1, Address(buf, 8));
4842 crc32cx(crc, crc, tmp0);
4843 ldr(tmp2, Address(buf, 24));
4844 crc32cx(crc, crc, tmp1);
4845 ldr(tmp3, Address(buf, 32));
4846 crc32cx(crc, crc, tmp2);
4847 ldr(tmp0, Address(buf, 40));
4848 crc32cx(crc, crc, tmp3);
4849 ldr(tmp1, Address(buf, 48));
4850 crc32cx(crc, crc, tmp0);
4851 ldr(tmp2, Address(buf, 56));
4852 crc32cx(crc, crc, tmp1);
4853 ldr(tmp3, Address(pre(buf, 64)));
4854
4855 b(CRC_by64_loop);
4856
4857 align(CodeEntryAlignment);
4858 BIND(CRC_by64_loop);
4859 subs(len, len, 64);
4860 crc32cx(crc, crc, tmp2);
4861 ldr(tmp0, Address(buf, 8));
4862 crc32cx(crc, crc, tmp3);
4863 ldr(tmp1, Address(buf, 16));
4864 crc32cx(crc, crc, tmp0);
4865 ldr(tmp2, Address(buf, 24));
4866 crc32cx(crc, crc, tmp1);
4867 ldr(tmp3, Address(buf, 32));
4868 crc32cx(crc, crc, tmp2);
4869 ldr(tmp0, Address(buf, 40));
4870 crc32cx(crc, crc, tmp3);
4871 ldr(tmp1, Address(buf, 48));
4872 crc32cx(crc, crc, tmp0);
4873 ldr(tmp2, Address(buf, 56));
4874 crc32cx(crc, crc, tmp1);
4875 ldr(tmp3, Address(pre(buf, 64)));
4876 br(Assembler::GE, CRC_by64_loop);
4877
4878 // post-loop
4879 crc32cx(crc, crc, tmp2);
4880 crc32cx(crc, crc, tmp3);
4881
4882 sub(len, len, 64);
4883 add(buf, buf, 8);
4884 cmn(len, (u1)128);
4885 br(Assembler::NE, CRC_less64);
4886 BIND(L_exit);
4887 }
4888
4889 /**
4890 * @param crc register containing existing CRC (32-bit)
4891 * @param buf register pointing to input byte buffer (byte*)
4892 * @param len register containing number of bytes
4893 * @param table register that will contain address of CRC table
4894 * @param tmp scratch register
4895 */
4896 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
4897 Register table0, Register table1, Register table2, Register table3,
4898 Register tmp, Register tmp2, Register tmp3) {
4899 if (UseCryptoPmullForCRC32) {
4900 kernel_crc32c_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4901 } else {
4902 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3);
4903 }
4904 }
4905
4906 void MacroAssembler::kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
4907 Register len, Register tmp0, Register tmp1, Register tmp2, size_t table_offset) {
4908 Label CRC_by128_loop;
4909 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4910
4911 sub(len, len, 256);
4912 Register table = tmp0;
4913 {
4914 uint64_t offset;
4915 adrp(table, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4916 add(table, table, offset);
4917 }
4918 add(table, table, table_offset);
4919
4920 // Registers v0..v7 are used as data registers.
4921 // Registers v16..v31 are used as tmp registers.
4922 sub(buf, buf, 0x10);
4923 ldrq(v0, Address(buf, 0x10));
4924 ldrq(v1, Address(buf, 0x20));
4925 ldrq(v2, Address(buf, 0x30));
4926 ldrq(v3, Address(buf, 0x40));
4927 ldrq(v4, Address(buf, 0x50));
4928 ldrq(v5, Address(buf, 0x60));
4929 ldrq(v6, Address(buf, 0x70));
4930 ldrq(v7, Address(pre(buf, 0x80)));
4931
4932 movi(v31, T4S, 0);
4933 mov(v31, S, 0, crc);
4934 eor(v0, T16B, v0, v31);
4935
4936 // Register v16 contains constants from the crc table.
4937 ldrq(v16, Address(table));
4938 b(CRC_by128_loop);
4939
4940 align(OptoLoopAlignment);
4941 BIND(CRC_by128_loop);
4942 pmull (v17, T1Q, v0, v16, T1D);
4943 pmull2(v18, T1Q, v0, v16, T2D);
4944 ldrq(v0, Address(buf, 0x10));
4945 eor3(v0, T16B, v17, v18, v0);
4946
4947 pmull (v19, T1Q, v1, v16, T1D);
4948 pmull2(v20, T1Q, v1, v16, T2D);
4949 ldrq(v1, Address(buf, 0x20));
4950 eor3(v1, T16B, v19, v20, v1);
4951
4952 pmull (v21, T1Q, v2, v16, T1D);
4953 pmull2(v22, T1Q, v2, v16, T2D);
4954 ldrq(v2, Address(buf, 0x30));
4955 eor3(v2, T16B, v21, v22, v2);
4956
4957 pmull (v23, T1Q, v3, v16, T1D);
4958 pmull2(v24, T1Q, v3, v16, T2D);
4959 ldrq(v3, Address(buf, 0x40));
4960 eor3(v3, T16B, v23, v24, v3);
4961
4962 pmull (v25, T1Q, v4, v16, T1D);
4963 pmull2(v26, T1Q, v4, v16, T2D);
4964 ldrq(v4, Address(buf, 0x50));
4965 eor3(v4, T16B, v25, v26, v4);
4966
4967 pmull (v27, T1Q, v5, v16, T1D);
4968 pmull2(v28, T1Q, v5, v16, T2D);
4969 ldrq(v5, Address(buf, 0x60));
4970 eor3(v5, T16B, v27, v28, v5);
4971
4972 pmull (v29, T1Q, v6, v16, T1D);
4973 pmull2(v30, T1Q, v6, v16, T2D);
4974 ldrq(v6, Address(buf, 0x70));
4975 eor3(v6, T16B, v29, v30, v6);
4976
4977 // Reuse registers v23, v24.
4978 // Using them won't block the first instruction of the next iteration.
4979 pmull (v23, T1Q, v7, v16, T1D);
4980 pmull2(v24, T1Q, v7, v16, T2D);
4981 ldrq(v7, Address(pre(buf, 0x80)));
4982 eor3(v7, T16B, v23, v24, v7);
4983
4984 subs(len, len, 0x80);
4985 br(Assembler::GE, CRC_by128_loop);
4986
4987 // fold into 512 bits
4988 // Use v31 for constants because v16 can be still in use.
4989 ldrq(v31, Address(table, 0x10));
4990
4991 pmull (v17, T1Q, v0, v31, T1D);
4992 pmull2(v18, T1Q, v0, v31, T2D);
4993 eor3(v0, T16B, v17, v18, v4);
4994
4995 pmull (v19, T1Q, v1, v31, T1D);
4996 pmull2(v20, T1Q, v1, v31, T2D);
4997 eor3(v1, T16B, v19, v20, v5);
4998
4999 pmull (v21, T1Q, v2, v31, T1D);
5000 pmull2(v22, T1Q, v2, v31, T2D);
5001 eor3(v2, T16B, v21, v22, v6);
5002
5003 pmull (v23, T1Q, v3, v31, T1D);
5004 pmull2(v24, T1Q, v3, v31, T2D);
5005 eor3(v3, T16B, v23, v24, v7);
5006
5007 // fold into 128 bits
5008 // Use v17 for constants because v31 can be still in use.
5009 ldrq(v17, Address(table, 0x20));
5010 pmull (v25, T1Q, v0, v17, T1D);
5011 pmull2(v26, T1Q, v0, v17, T2D);
5012 eor3(v3, T16B, v3, v25, v26);
5013
5014 // Use v18 for constants because v17 can be still in use.
5015 ldrq(v18, Address(table, 0x30));
5016 pmull (v27, T1Q, v1, v18, T1D);
5017 pmull2(v28, T1Q, v1, v18, T2D);
5018 eor3(v3, T16B, v3, v27, v28);
5019
5020 // Use v19 for constants because v18 can be still in use.
5021 ldrq(v19, Address(table, 0x40));
5022 pmull (v29, T1Q, v2, v19, T1D);
5023 pmull2(v30, T1Q, v2, v19, T2D);
5024 eor3(v0, T16B, v3, v29, v30);
5025
5026 add(len, len, 0x80);
5027 add(buf, buf, 0x10);
5028
5029 mov(tmp0, v0, D, 0);
5030 mov(tmp1, v0, D, 1);
5031 }
5032
5033 void MacroAssembler::addptr(const Address &dst, int32_t src) {
5034 Address adr;
5035 switch(dst.getMode()) {
5036 case Address::base_plus_offset:
5037 // This is the expected mode, although we allow all the other
5038 // forms below.
5039 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
5040 break;
5041 default:
5042 lea(rscratch2, dst);
5043 adr = Address(rscratch2);
5044 break;
5045 }
5046 ldr(rscratch1, adr);
5047 add(rscratch1, rscratch1, src);
5048 str(rscratch1, adr);
5049 }
5050
5051 void MacroAssembler::cmpptr(Register src1, Address src2) {
5052 uint64_t offset;
5053 adrp(rscratch1, src2, offset);
5054 ldr(rscratch1, Address(rscratch1, offset));
5055 cmp(src1, rscratch1);
5056 }
5057
5058 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
5059 cmp(obj1, obj2);
5060 }
5061
5062 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5063 load_method_holder(rresult, rmethod);
5064 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5065 }
5066
5067 void MacroAssembler::load_method_holder(Register holder, Register method) {
5068 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
5069 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5070 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5071 }
5072
5073 // Loads the obj's Klass* into dst.
5074 // Preserves all registers (incl src, rscratch1 and rscratch2).
5075 // Input:
5076 // src - the oop we want to load the klass from.
5077 // dst - output narrow klass.
5078 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5079 assert(UseCompactObjectHeaders, "expects UseCompactObjectHeaders");
5080 ldr(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5081 lsr(dst, dst, markWord::klass_shift);
5082 }
5083
5084 void MacroAssembler::load_klass(Register dst, Register src) {
5085 if (UseCompactObjectHeaders) {
5086 load_narrow_klass_compact(dst, src);
5087 decode_klass_not_null(dst);
5088 } else if (UseCompressedClassPointers) {
5089 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5090 decode_klass_not_null(dst);
5091 } else {
5092 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5093 }
5094 }
5095
5096 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
5097 if (RestoreMXCSROnJNICalls) {
5098 Label OK;
5099 get_fpcr(tmp1);
5100 mov(tmp2, tmp1);
5101 // Set FPCR to the state we need. We do want Round to Nearest. We
5102 // don't want non-IEEE rounding modes or floating-point traps.
5103 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
5104 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
5105 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
5106 eor(tmp2, tmp1, tmp2);
5107 cbz(tmp2, OK); // Only reset FPCR if it's wrong
5108 set_fpcr(tmp1);
5109 bind(OK);
5110 }
5111 }
5112
5113 // ((OopHandle)result).resolve();
5114 void MacroAssembler::resolve_oop_handle(Register result, Register tmp1, Register tmp2) {
5115 // OopHandle::resolve is an indirection.
5116 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp1, tmp2);
5117 }
5118
5119 // ((WeakHandle)result).resolve();
5120 void MacroAssembler::resolve_weak_handle(Register result, Register tmp1, Register tmp2) {
5121 assert_different_registers(result, tmp1, tmp2);
5122 Label resolved;
5123
5124 // A null weak handle resolves to null.
5125 cbz(result, resolved);
5126
5127 // Only 64 bit platforms support GCs that require a tmp register
5128 // WeakHandle::resolve is an indirection like jweak.
5129 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5130 result, Address(result), tmp1, tmp2);
5131 bind(resolved);
5132 }
5133
5134 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp1, Register tmp2) {
5135 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5136 ldr(dst, Address(rmethod, Method::const_offset()));
5137 ldr(dst, Address(dst, ConstMethod::constants_offset()));
5138 ldr(dst, Address(dst, ConstantPool::pool_holder_offset()));
5139 ldr(dst, Address(dst, mirror_offset));
5140 resolve_oop_handle(dst, tmp1, tmp2);
5141 }
5142
5143 void MacroAssembler::cmp_klass(Register obj, Register klass, Register tmp) {
5144 assert_different_registers(obj, klass, tmp);
5145 if (UseCompressedClassPointers) {
5146 if (UseCompactObjectHeaders) {
5147 load_narrow_klass_compact(tmp, obj);
5148 } else {
5149 ldrw(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5150 }
5151 if (CompressedKlassPointers::base() == nullptr) {
5152 cmp(klass, tmp, LSL, CompressedKlassPointers::shift());
5153 return;
5154 } else if (!AOTCodeCache::is_on_for_dump() &&
5155 ((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
5156 && CompressedKlassPointers::shift() == 0) {
5157 // Only the bottom 32 bits matter
5158 cmpw(klass, tmp);
5159 return;
5160 }
5161 decode_klass_not_null(tmp);
5162 } else {
5163 ldr(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5164 }
5165 cmp(klass, tmp);
5166 }
5167
5168 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5169 if (UseCompactObjectHeaders) {
5170 load_narrow_klass_compact(tmp1, obj1);
5171 load_narrow_klass_compact(tmp2, obj2);
5172 cmpw(tmp1, tmp2);
5173 } else if (UseCompressedClassPointers) {
5174 ldrw(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5175 ldrw(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5176 cmpw(tmp1, tmp2);
5177 } else {
5178 ldr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5179 ldr(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5180 cmp(tmp1, tmp2);
5181 }
5182 }
5183
5184 void MacroAssembler::store_klass(Register dst, Register src) {
5185 // FIXME: Should this be a store release? concurrent gcs assumes
5186 // klass length is valid if klass field is not null.
5187 assert(!UseCompactObjectHeaders, "not with compact headers");
5188 if (UseCompressedClassPointers) {
5189 encode_klass_not_null(src);
5190 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5191 } else {
5192 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5193 }
5194 }
5195
5196 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5197 assert(!UseCompactObjectHeaders, "not with compact headers");
5198 if (UseCompressedClassPointers) {
5199 // Store to klass gap in destination
5200 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
5201 }
5202 }
5203
5204 // Algorithm must match CompressedOops::encode.
5205 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5206 #ifdef ASSERT
5207 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5208 #endif
5209 verify_oop_msg(s, "broken oop in encode_heap_oop");
5210 if (CompressedOops::base() == nullptr) {
5211 if (CompressedOops::shift() != 0) {
5212 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5213 lsr(d, s, LogMinObjAlignmentInBytes);
5214 } else {
5215 mov(d, s);
5216 }
5217 } else {
5218 subs(d, s, rheapbase);
5219 csel(d, d, zr, Assembler::HS);
5220 lsr(d, d, LogMinObjAlignmentInBytes);
5221
5222 /* Old algorithm: is this any worse?
5223 Label nonnull;
5224 cbnz(r, nonnull);
5225 sub(r, r, rheapbase);
5226 bind(nonnull);
5227 lsr(r, r, LogMinObjAlignmentInBytes);
5228 */
5229 }
5230 }
5231
5232 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5233 #ifdef ASSERT
5234 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5235 if (CheckCompressedOops) {
5236 Label ok;
5237 cbnz(r, ok);
5238 stop("null oop passed to encode_heap_oop_not_null");
5239 bind(ok);
5240 }
5241 #endif
5242 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5243 if (CompressedOops::base() != nullptr) {
5244 sub(r, r, rheapbase);
5245 }
5246 if (CompressedOops::shift() != 0) {
5247 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5248 lsr(r, r, LogMinObjAlignmentInBytes);
5249 }
5250 }
5251
5252 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5253 #ifdef ASSERT
5254 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5255 if (CheckCompressedOops) {
5256 Label ok;
5257 cbnz(src, ok);
5258 stop("null oop passed to encode_heap_oop_not_null2");
5259 bind(ok);
5260 }
5261 #endif
5262 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5263
5264 Register data = src;
5265 if (CompressedOops::base() != nullptr) {
5266 sub(dst, src, rheapbase);
5267 data = dst;
5268 }
5269 if (CompressedOops::shift() != 0) {
5270 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5271 lsr(dst, data, LogMinObjAlignmentInBytes);
5272 data = dst;
5273 }
5274 if (data == src)
5275 mov(dst, src);
5276 }
5277
5278 void MacroAssembler::decode_heap_oop(Register d, Register s) {
5279 #ifdef ASSERT
5280 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5281 #endif
5282 if (CompressedOops::base() == nullptr) {
5283 if (CompressedOops::shift() != 0) {
5284 lsl(d, s, CompressedOops::shift());
5285 } else if (d != s) {
5286 mov(d, s);
5287 }
5288 } else {
5289 Label done;
5290 if (d != s)
5291 mov(d, s);
5292 cbz(s, done);
5293 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
5294 bind(done);
5295 }
5296 verify_oop_msg(d, "broken oop in decode_heap_oop");
5297 }
5298
5299 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5300 assert (UseCompressedOops, "should only be used for compressed headers");
5301 assert (Universe::heap() != nullptr, "java heap should be initialized");
5302 // Cannot assert, unverified entry point counts instructions (see .ad file)
5303 // vtableStubs also counts instructions in pd_code_size_limit.
5304 // Also do not verify_oop as this is called by verify_oop.
5305 if (CompressedOops::shift() != 0) {
5306 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5307 if (CompressedOops::base() != nullptr) {
5308 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5309 } else {
5310 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5311 }
5312 } else {
5313 assert (CompressedOops::base() == nullptr, "sanity");
5314 }
5315 }
5316
5317 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5318 assert (UseCompressedOops, "should only be used for compressed headers");
5319 assert (Universe::heap() != nullptr, "java heap should be initialized");
5320 // Cannot assert, unverified entry point counts instructions (see .ad file)
5321 // vtableStubs also counts instructions in pd_code_size_limit.
5322 // Also do not verify_oop as this is called by verify_oop.
5323 if (CompressedOops::shift() != 0) {
5324 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5325 if (CompressedOops::base() != nullptr) {
5326 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5327 } else {
5328 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5329 }
5330 } else {
5331 assert (CompressedOops::base() == nullptr, "sanity");
5332 if (dst != src) {
5333 mov(dst, src);
5334 }
5335 }
5336 }
5337
5338 MacroAssembler::KlassDecodeMode MacroAssembler::_klass_decode_mode(KlassDecodeNone);
5339
5340 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() {
5341 assert(Metaspace::initialized(), "metaspace not initialized yet");
5342 assert(_klass_decode_mode != KlassDecodeNone, "should be initialized");
5343 return _klass_decode_mode;
5344 }
5345
5346 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode(address base, int shift, const size_t range) {
5347 assert(UseCompressedClassPointers, "not using compressed class pointers");
5348
5349 // KlassDecodeMode shouldn't be set already.
5350 assert(_klass_decode_mode == KlassDecodeNone, "set once");
5351
5352 if (base == nullptr) {
5353 return KlassDecodeZero;
5354 }
5355
5356 if (operand_valid_for_logical_immediate(
5357 /*is32*/false, (uint64_t)base)) {
5358 const uint64_t range_mask = right_n_bits(log2i_ceil(range));
5359 if (((uint64_t)base & range_mask) == 0) {
5360 return KlassDecodeXor;
5361 }
5362 }
5363
5364 const uint64_t shifted_base =
5365 (uint64_t)base >> shift;
5366 if ((shifted_base & 0xffff0000ffffffff) == 0) {
5367 return KlassDecodeMovk;
5368 }
5369
5370 // No valid encoding.
5371 return KlassDecodeNone;
5372 }
5373
5374 // Check if one of the above decoding modes will work for given base, shift and range.
5375 bool MacroAssembler::check_klass_decode_mode(address base, int shift, const size_t range) {
5376 return klass_decode_mode(base, shift, range) != KlassDecodeNone;
5377 }
5378
5379 bool MacroAssembler::set_klass_decode_mode(address base, int shift, const size_t range) {
5380 _klass_decode_mode = klass_decode_mode(base, shift, range);
5381 return _klass_decode_mode != KlassDecodeNone;
5382 }
5383
5384 static Register pick_different_tmp(Register dst, Register src) {
5385 auto tmps = RegSet::of(r0, r1, r2) - RegSet::of(src, dst);
5386 return *tmps.begin();
5387 }
5388
5389 void MacroAssembler::encode_klass_not_null_for_aot(Register dst, Register src) {
5390 // we have to load the klass base from the AOT constants area but
5391 // not the shift because it is not allowed to change
5392 int shift = CompressedKlassPointers::shift();
5393 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5394 if (dst != src) {
5395 // we can load the base into dst, subtract it formthe src and shift down
5396 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5397 ldr(dst, dst);
5398 sub(dst, src, dst);
5399 lsr(dst, dst, shift);
5400 } else {
5401 // we need an extra register in order to load the coop base
5402 Register tmp = pick_different_tmp(dst, src);
5403 RegSet regs = RegSet::of(tmp);
5404 push(regs, sp);
5405 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5406 ldr(tmp, tmp);
5407 sub(dst, src, tmp);
5408 lsr(dst, dst, shift);
5409 pop(regs, sp);
5410 }
5411 }
5412
5413 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5414 if (CompressedKlassPointers::base() != nullptr && AOTCodeCache::is_on_for_dump()) {
5415 encode_klass_not_null_for_aot(dst, src);
5416 return;
5417 }
5418
5419 switch (klass_decode_mode()) {
5420 case KlassDecodeZero:
5421 if (CompressedKlassPointers::shift() != 0) {
5422 lsr(dst, src, CompressedKlassPointers::shift());
5423 } else {
5424 if (dst != src) mov(dst, src);
5425 }
5426 break;
5427
5428 case KlassDecodeXor:
5429 if (CompressedKlassPointers::shift() != 0) {
5430 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5431 lsr(dst, dst, CompressedKlassPointers::shift());
5432 } else {
5433 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5434 }
5435 break;
5436
5437 case KlassDecodeMovk:
5438 if (CompressedKlassPointers::shift() != 0) {
5439 ubfx(dst, src, CompressedKlassPointers::shift(), 32);
5440 } else {
5441 movw(dst, src);
5442 }
5443 break;
5444
5445 case KlassDecodeNone:
5446 ShouldNotReachHere();
5447 break;
5448 }
5449 }
5450
5451 void MacroAssembler::encode_klass_not_null(Register r) {
5452 encode_klass_not_null(r, r);
5453 }
5454
5455 void MacroAssembler::decode_klass_not_null_for_aot(Register dst, Register src) {
5456 // we have to load the klass base from the AOT constants area but
5457 // not the shift because it is not allowed to change
5458 int shift = CompressedKlassPointers::shift();
5459 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5460 if (dst != src) {
5461 // we can load the base into dst then add the offset with a suitable shift
5462 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5463 ldr(dst, dst);
5464 add(dst, dst, src, LSL, shift);
5465 } else {
5466 // we need an extra register in order to load the coop base
5467 Register tmp = pick_different_tmp(dst, src);
5468 RegSet regs = RegSet::of(tmp);
5469 push(regs, sp);
5470 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5471 ldr(tmp, tmp);
5472 add(dst, tmp, src, LSL, shift);
5473 pop(regs, sp);
5474 }
5475 }
5476
5477 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5478 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5479
5480 if (CompressedKlassPointers::base() != nullptr && AOTCodeCache::is_on_for_dump()) {
5481 decode_klass_not_null_for_aot(dst, src);
5482 return;
5483 }
5484
5485 switch (klass_decode_mode()) {
5486 case KlassDecodeZero:
5487 if (CompressedKlassPointers::shift() != 0) {
5488 lsl(dst, src, CompressedKlassPointers::shift());
5489 } else {
5490 if (dst != src) mov(dst, src);
5491 }
5492 break;
5493
5494 case KlassDecodeXor:
5495 if (CompressedKlassPointers::shift() != 0) {
5496 lsl(dst, src, CompressedKlassPointers::shift());
5497 eor(dst, dst, (uint64_t)CompressedKlassPointers::base());
5498 } else {
5499 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5500 }
5501 break;
5502
5503 case KlassDecodeMovk: {
5504 const uint64_t shifted_base =
5505 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5506
5507 if (dst != src) movw(dst, src);
5508 movk(dst, shifted_base >> 32, 32);
5509
5510 if (CompressedKlassPointers::shift() != 0) {
5511 lsl(dst, dst, CompressedKlassPointers::shift());
5512 }
5513
5514 break;
5515 }
5516
5517 case KlassDecodeNone:
5518 ShouldNotReachHere();
5519 break;
5520 }
5521 }
5522
5523 void MacroAssembler::decode_klass_not_null(Register r) {
5524 decode_klass_not_null(r, r);
5525 }
5526
5527 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5528 #ifdef ASSERT
5529 {
5530 ThreadInVMfromUnknown tiv;
5531 assert (UseCompressedOops, "should only be used for compressed oops");
5532 assert (Universe::heap() != nullptr, "java heap should be initialized");
5533 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5534 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5535 }
5536 #endif
5537 int oop_index = oop_recorder()->find_index(obj);
5538 InstructionMark im(this);
5539 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5540 code_section()->relocate(inst_mark(), rspec);
5541 movz(dst, 0xDEAD, 16);
5542 movk(dst, 0xBEEF);
5543 }
5544
5545 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5546 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5547 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5548 int index = oop_recorder()->find_index(k);
5549
5550 InstructionMark im(this);
5551 RelocationHolder rspec = metadata_Relocation::spec(index);
5552 code_section()->relocate(inst_mark(), rspec);
5553 narrowKlass nk = CompressedKlassPointers::encode(k);
5554 movz(dst, (nk >> 16), 16);
5555 movk(dst, nk & 0xffff);
5556 }
5557
5558 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
5559 Register dst, Address src,
5560 Register tmp1, Register tmp2) {
5561 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5562 decorators = AccessInternal::decorator_fixup(decorators, type);
5563 bool as_raw = (decorators & AS_RAW) != 0;
5564 if (as_raw) {
5565 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5566 } else {
5567 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5568 }
5569 }
5570
5571 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5572 Address dst, Register val,
5573 Register tmp1, Register tmp2, Register tmp3) {
5574 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5575 decorators = AccessInternal::decorator_fixup(decorators, type);
5576 bool as_raw = (decorators & AS_RAW) != 0;
5577 if (as_raw) {
5578 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5579 } else {
5580 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5581 }
5582 }
5583
5584 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5585 Register tmp2, DecoratorSet decorators) {
5586 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5587 }
5588
5589 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5590 Register tmp2, DecoratorSet decorators) {
5591 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5592 }
5593
5594 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5595 Register tmp2, Register tmp3, DecoratorSet decorators) {
5596 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5597 }
5598
5599 // Used for storing nulls.
5600 void MacroAssembler::store_heap_oop_null(Address dst) {
5601 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5602 }
5603
5604 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
5605 assert(oop_recorder() != nullptr, "this assembler needs a Recorder");
5606 int index = oop_recorder()->allocate_metadata_index(obj);
5607 RelocationHolder rspec = metadata_Relocation::spec(index);
5608 return Address((address)obj, rspec);
5609 }
5610
5611 // Move an oop into a register.
5612 void MacroAssembler::movoop(Register dst, jobject obj) {
5613 int oop_index;
5614 if (obj == nullptr) {
5615 oop_index = oop_recorder()->allocate_oop_index(obj);
5616 } else {
5617 #ifdef ASSERT
5618 {
5619 ThreadInVMfromUnknown tiv;
5620 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5621 }
5622 #endif
5623 oop_index = oop_recorder()->find_index(obj);
5624 }
5625 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5626
5627 if (BarrierSet::barrier_set()->barrier_set_assembler()->supports_instruction_patching()) {
5628 mov(dst, Address((address)obj, rspec));
5629 } else {
5630 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
5631 ldr(dst, Address(dummy, rspec));
5632 }
5633 }
5634
5635 // Move a metadata address into a register.
5636 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
5637 int oop_index;
5638 if (obj == nullptr) {
5639 oop_index = oop_recorder()->allocate_metadata_index(obj);
5640 } else {
5641 oop_index = oop_recorder()->find_index(obj);
5642 }
5643 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5644 mov(dst, Address((address)obj, rspec));
5645 }
5646
5647 Address MacroAssembler::constant_oop_address(jobject obj) {
5648 #ifdef ASSERT
5649 {
5650 ThreadInVMfromUnknown tiv;
5651 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5652 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5653 }
5654 #endif
5655 int oop_index = oop_recorder()->find_index(obj);
5656 return Address((address)obj, oop_Relocation::spec(oop_index));
5657 }
5658
5659 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5660 void MacroAssembler::tlab_allocate(Register obj,
5661 Register var_size_in_bytes,
5662 int con_size_in_bytes,
5663 Register t1,
5664 Register t2,
5665 Label& slow_case) {
5666 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5667 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5668 }
5669
5670 void MacroAssembler::verify_tlab() {
5671 #ifdef ASSERT
5672 if (UseTLAB && VerifyOops) {
5673 Label next, ok;
5674
5675 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5676
5677 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5678 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5679 cmp(rscratch2, rscratch1);
5680 br(Assembler::HS, next);
5681 STOP("assert(top >= start)");
5682 should_not_reach_here();
5683
5684 bind(next);
5685 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5686 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5687 cmp(rscratch2, rscratch1);
5688 br(Assembler::HS, ok);
5689 STOP("assert(top <= end)");
5690 should_not_reach_here();
5691
5692 bind(ok);
5693 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5694 }
5695 #endif
5696 }
5697
5698 // Writes to stack successive pages until offset reached to check for
5699 // stack overflow + shadow pages. This clobbers tmp.
5700 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5701 assert_different_registers(tmp, size, rscratch1);
5702 mov(tmp, sp);
5703 // Bang stack for total size given plus shadow page size.
5704 // Bang one page at a time because large size can bang beyond yellow and
5705 // red zones.
5706 Label loop;
5707 mov(rscratch1, (int)os::vm_page_size());
5708 bind(loop);
5709 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5710 subsw(size, size, rscratch1);
5711 str(size, Address(tmp));
5712 br(Assembler::GT, loop);
5713
5714 // Bang down shadow pages too.
5715 // At this point, (tmp-0) is the last address touched, so don't
5716 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5717 // was post-decremented.) Skip this address by starting at i=1, and
5718 // touch a few more pages below. N.B. It is important to touch all
5719 // the way down to and including i=StackShadowPages.
5720 for (int i = 0; i < (int)(StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()) - 1; i++) {
5721 // this could be any sized move but this is can be a debugging crumb
5722 // so the bigger the better.
5723 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5724 str(size, Address(tmp));
5725 }
5726 }
5727
5728 // Move the address of the polling page into dest.
5729 void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype) {
5730 ldr(dest, Address(rthread, JavaThread::polling_page_offset()));
5731 }
5732
5733 // Read the polling page. The address of the polling page must
5734 // already be in r.
5735 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
5736 address mark;
5737 {
5738 InstructionMark im(this);
5739 code_section()->relocate(inst_mark(), rtype);
5740 ldrw(zr, Address(r, 0));
5741 mark = inst_mark();
5742 }
5743 verify_cross_modify_fence_not_required();
5744 return mark;
5745 }
5746
5747 void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
5748 uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12;
5749 uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12;
5750 uint64_t dest_page = (uint64_t)dest.target() >> 12;
5751 int64_t offset_low = dest_page - low_page;
5752 int64_t offset_high = dest_page - high_page;
5753
5754 assert(is_valid_AArch64_address(dest.target()), "bad address");
5755 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
5756
5757 InstructionMark im(this);
5758 code_section()->relocate(inst_mark(), dest.rspec());
5759 // 8143067: Ensure that the adrp can reach the dest from anywhere within
5760 // the code cache so that if it is relocated we know it will still reach
5761 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
5762 _adrp(reg1, dest.target());
5763 } else {
5764 uint64_t target = (uint64_t)dest.target();
5765 uint64_t adrp_target
5766 = (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL);
5767
5768 _adrp(reg1, (address)adrp_target);
5769 movk(reg1, target >> 32, 32);
5770 }
5771 byte_offset = (uint64_t)dest.target() & 0xfff;
5772 }
5773
5774 void MacroAssembler::load_byte_map_base(Register reg) {
5775 #if INCLUDE_CDS
5776 if (AOTCodeCache::is_on_for_dump()) {
5777 address byte_map_base_adr = AOTRuntimeConstants::card_table_base_address();
5778 lea(reg, ExternalAddress(byte_map_base_adr));
5779 ldr(reg, Address(reg));
5780 return;
5781 }
5782 #endif
5783 CardTableBarrierSet* ctbs = CardTableBarrierSet::barrier_set();
5784
5785 // Strictly speaking the card table base isn't an address at all, and it might
5786 // even be negative. It is thus materialised as a constant.
5787 mov(reg, (uint64_t)ctbs->card_table_base_const());
5788 }
5789
5790 void MacroAssembler::load_aotrc_address(Register reg, address a) {
5791 #if INCLUDE_CDS
5792 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
5793 if (AOTCodeCache::is_on_for_dump()) {
5794 // all aotrc field addresses should be registered in the AOTCodeCache address table
5795 lea(reg, ExternalAddress(a));
5796 } else {
5797 mov(reg, (uint64_t)a);
5798 }
5799 #else
5800 ShouldNotReachHere();
5801 #endif
5802 }
5803
5804 void MacroAssembler::build_frame(int framesize) {
5805 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5806 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5807 protect_return_address();
5808 if (framesize < ((1 << 9) + 2 * wordSize)) {
5809 sub(sp, sp, framesize);
5810 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5811 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
5812 } else {
5813 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
5814 if (PreserveFramePointer) mov(rfp, sp);
5815 if (framesize < ((1 << 12) + 2 * wordSize))
5816 sub(sp, sp, framesize - 2 * wordSize);
5817 else {
5818 mov(rscratch1, framesize - 2 * wordSize);
5819 sub(sp, sp, rscratch1);
5820 }
5821 }
5822 verify_cross_modify_fence_not_required();
5823 }
5824
5825 void MacroAssembler::remove_frame(int framesize) {
5826 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5827 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5828 if (framesize < ((1 << 9) + 2 * wordSize)) {
5829 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5830 add(sp, sp, framesize);
5831 } else {
5832 if (framesize < ((1 << 12) + 2 * wordSize))
5833 add(sp, sp, framesize - 2 * wordSize);
5834 else {
5835 mov(rscratch1, framesize - 2 * wordSize);
5836 add(sp, sp, rscratch1);
5837 }
5838 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5839 }
5840 authenticate_return_address();
5841 }
5842
5843
5844 // This method counts leading positive bytes (highest bit not set) in provided byte array
5845 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5846 // Simple and most common case of aligned small array which is not at the
5847 // end of memory page is placed here. All other cases are in stub.
5848 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5849 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5850 assert_different_registers(ary1, len, result);
5851
5852 mov(result, len);
5853 cmpw(len, 0);
5854 br(LE, DONE);
5855 cmpw(len, 4 * wordSize);
5856 br(GE, STUB_LONG); // size > 32 then go to stub
5857
5858 int shift = 64 - exact_log2(os::vm_page_size());
5859 lsl(rscratch1, ary1, shift);
5860 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5861 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5862 br(CS, STUB); // at the end of page then go to stub
5863 subs(len, len, wordSize);
5864 br(LT, END);
5865
5866 BIND(LOOP);
5867 ldr(rscratch1, Address(post(ary1, wordSize)));
5868 tst(rscratch1, UPPER_BIT_MASK);
5869 br(NE, SET_RESULT);
5870 subs(len, len, wordSize);
5871 br(GE, LOOP);
5872 cmpw(len, -wordSize);
5873 br(EQ, DONE);
5874
5875 BIND(END);
5876 ldr(rscratch1, Address(ary1));
5877 sub(rscratch2, zr, len, LSL, 3); // LSL 3 is to get bits from bytes
5878 lslv(rscratch1, rscratch1, rscratch2);
5879 tst(rscratch1, UPPER_BIT_MASK);
5880 br(NE, SET_RESULT);
5881 b(DONE);
5882
5883 BIND(STUB);
5884 RuntimeAddress count_pos = RuntimeAddress(StubRoutines::aarch64::count_positives());
5885 assert(count_pos.target() != nullptr, "count_positives stub has not been generated");
5886 address tpc1 = trampoline_call(count_pos);
5887 if (tpc1 == nullptr) {
5888 DEBUG_ONLY(reset_labels(STUB_LONG, SET_RESULT, DONE));
5889 postcond(pc() == badAddress);
5890 return nullptr;
5891 }
5892 b(DONE);
5893
5894 BIND(STUB_LONG);
5895 RuntimeAddress count_pos_long = RuntimeAddress(StubRoutines::aarch64::count_positives_long());
5896 assert(count_pos_long.target() != nullptr, "count_positives_long stub has not been generated");
5897 address tpc2 = trampoline_call(count_pos_long);
5898 if (tpc2 == nullptr) {
5899 DEBUG_ONLY(reset_labels(SET_RESULT, DONE));
5900 postcond(pc() == badAddress);
5901 return nullptr;
5902 }
5903 b(DONE);
5904
5905 BIND(SET_RESULT);
5906
5907 add(len, len, wordSize);
5908 sub(result, result, len);
5909
5910 BIND(DONE);
5911 postcond(pc() != badAddress);
5912 return pc();
5913 }
5914
5915 // Clobbers: rscratch1, rscratch2, rflags
5916 // May also clobber v0-v7 when (!UseSimpleArrayEquals && UseSIMDForArrayEquals)
5917 address MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
5918 Register tmp4, Register tmp5, Register result,
5919 Register cnt1, int elem_size) {
5920 Label DONE, SAME;
5921 Register tmp1 = rscratch1;
5922 Register tmp2 = rscratch2;
5923 int elem_per_word = wordSize/elem_size;
5924 int log_elem_size = exact_log2(elem_size);
5925 int klass_offset = arrayOopDesc::klass_offset_in_bytes();
5926 int length_offset = arrayOopDesc::length_offset_in_bytes();
5927 int base_offset
5928 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
5929 // When the length offset is not aligned to 8 bytes,
5930 // then we align it down. This is valid because the new
5931 // offset will always be the klass which is the same
5932 // for type arrays.
5933 int start_offset = align_down(length_offset, BytesPerWord);
5934 int extra_length = base_offset - start_offset;
5935 assert(start_offset == length_offset || start_offset == klass_offset,
5936 "start offset must be 8-byte-aligned or be the klass offset");
5937 assert(base_offset != start_offset, "must include the length field");
5938 extra_length = extra_length / elem_size; // We count in elements, not bytes.
5939 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16);
5940
5941 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
5942 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5943
5944 #ifndef PRODUCT
5945 {
5946 const char kind = (elem_size == 2) ? 'U' : 'L';
5947 char comment[64];
5948 os::snprintf_checked(comment, sizeof comment, "array_equals%c{", kind);
5949 BLOCK_COMMENT(comment);
5950 }
5951 #endif
5952
5953 // if (a1 == a2)
5954 // return true;
5955 cmpoop(a1, a2); // May have read barriers for a1 and a2.
5956 br(EQ, SAME);
5957
5958 if (UseSimpleArrayEquals) {
5959 Label NEXT_WORD, SHORT, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL;
5960 // if (a1 == nullptr || a2 == nullptr)
5961 // return false;
5962 // a1 & a2 == 0 means (some-pointer is null) or
5963 // (very-rare-or-even-probably-impossible-pointer-values)
5964 // so, we can save one branch in most cases
5965 tst(a1, a2);
5966 mov(result, false);
5967 br(EQ, A_MIGHT_BE_NULL);
5968 // if (a1.length != a2.length)
5969 // return false;
5970 bind(A_IS_NOT_NULL);
5971 ldrw(cnt1, Address(a1, length_offset));
5972 ldrw(tmp5, Address(a2, length_offset));
5973 cmp(cnt1, tmp5);
5974 br(NE, DONE); // If lengths differ, return false
5975 // Increase loop counter by diff between base- and actual start-offset.
5976 addw(cnt1, cnt1, extra_length);
5977 lea(a1, Address(a1, start_offset));
5978 lea(a2, Address(a2, start_offset));
5979 // Check for short strings, i.e. smaller than wordSize.
5980 subs(cnt1, cnt1, elem_per_word);
5981 br(Assembler::LT, SHORT);
5982 // Main 8 byte comparison loop.
5983 bind(NEXT_WORD); {
5984 ldr(tmp1, Address(post(a1, wordSize)));
5985 ldr(tmp2, Address(post(a2, wordSize)));
5986 subs(cnt1, cnt1, elem_per_word);
5987 eor(tmp5, tmp1, tmp2);
5988 cbnz(tmp5, DONE);
5989 } br(GT, NEXT_WORD);
5990 // Last longword. In the case where length == 4 we compare the
5991 // same longword twice, but that's still faster than another
5992 // conditional branch.
5993 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
5994 // length == 4.
5995 if (log_elem_size > 0)
5996 lsl(cnt1, cnt1, log_elem_size);
5997 ldr(tmp3, Address(a1, cnt1));
5998 ldr(tmp4, Address(a2, cnt1));
5999 eor(tmp5, tmp3, tmp4);
6000 cbnz(tmp5, DONE);
6001 b(SAME);
6002 bind(A_MIGHT_BE_NULL);
6003 // in case both a1 and a2 are not-null, proceed with loads
6004 cbz(a1, DONE);
6005 cbz(a2, DONE);
6006 b(A_IS_NOT_NULL);
6007 bind(SHORT);
6008
6009 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
6010 {
6011 ldrw(tmp1, Address(post(a1, 4)));
6012 ldrw(tmp2, Address(post(a2, 4)));
6013 eorw(tmp5, tmp1, tmp2);
6014 cbnzw(tmp5, DONE);
6015 }
6016 bind(TAIL03);
6017 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
6018 {
6019 ldrh(tmp3, Address(post(a1, 2)));
6020 ldrh(tmp4, Address(post(a2, 2)));
6021 eorw(tmp5, tmp3, tmp4);
6022 cbnzw(tmp5, DONE);
6023 }
6024 bind(TAIL01);
6025 if (elem_size == 1) { // Only needed when comparing byte arrays.
6026 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6027 {
6028 ldrb(tmp1, a1);
6029 ldrb(tmp2, a2);
6030 eorw(tmp5, tmp1, tmp2);
6031 cbnzw(tmp5, DONE);
6032 }
6033 }
6034 } else {
6035 Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB,
6036 CSET_EQ, LAST_CHECK;
6037 mov(result, false);
6038 cbz(a1, DONE);
6039 ldrw(cnt1, Address(a1, length_offset));
6040 cbz(a2, DONE);
6041 ldrw(tmp5, Address(a2, length_offset));
6042 cmp(cnt1, tmp5);
6043 br(NE, DONE); // If lengths differ, return false
6044 // Increase loop counter by diff between base- and actual start-offset.
6045 addw(cnt1, cnt1, extra_length);
6046
6047 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's
6048 // faster to perform another branch before comparing a1 and a2
6049 cmp(cnt1, (u1)elem_per_word);
6050 br(LE, SHORT); // short or same
6051 ldr(tmp3, Address(pre(a1, start_offset)));
6052 subs(zr, cnt1, stubBytesThreshold);
6053 br(GE, STUB);
6054 ldr(tmp4, Address(pre(a2, start_offset)));
6055 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6056
6057 // Main 16 byte comparison loop with 2 exits
6058 bind(NEXT_DWORD); {
6059 ldr(tmp1, Address(pre(a1, wordSize)));
6060 ldr(tmp2, Address(pre(a2, wordSize)));
6061 subs(cnt1, cnt1, 2 * elem_per_word);
6062 br(LE, TAIL);
6063 eor(tmp4, tmp3, tmp4);
6064 cbnz(tmp4, DONE);
6065 ldr(tmp3, Address(pre(a1, wordSize)));
6066 ldr(tmp4, Address(pre(a2, wordSize)));
6067 cmp(cnt1, (u1)elem_per_word);
6068 br(LE, TAIL2);
6069 cmp(tmp1, tmp2);
6070 } br(EQ, NEXT_DWORD);
6071 b(DONE);
6072
6073 bind(TAIL);
6074 eor(tmp4, tmp3, tmp4);
6075 eor(tmp2, tmp1, tmp2);
6076 lslv(tmp2, tmp2, tmp5);
6077 orr(tmp5, tmp4, tmp2);
6078 cmp(tmp5, zr);
6079 b(CSET_EQ);
6080
6081 bind(TAIL2);
6082 eor(tmp2, tmp1, tmp2);
6083 cbnz(tmp2, DONE);
6084 b(LAST_CHECK);
6085
6086 bind(STUB);
6087 ldr(tmp4, Address(pre(a2, start_offset)));
6088 if (elem_size == 2) { // convert to byte counter
6089 lsl(cnt1, cnt1, 1);
6090 }
6091 eor(tmp5, tmp3, tmp4);
6092 cbnz(tmp5, DONE);
6093 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
6094 assert(stub.target() != nullptr, "array_equals_long stub has not been generated");
6095 address tpc = trampoline_call(stub);
6096 if (tpc == nullptr) {
6097 DEBUG_ONLY(reset_labels(SHORT, LAST_CHECK, CSET_EQ, SAME, DONE));
6098 postcond(pc() == badAddress);
6099 return nullptr;
6100 }
6101 b(DONE);
6102
6103 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
6104 // so, if a2 == null => return false(0), else return true, so we can return a2
6105 mov(result, a2);
6106 b(DONE);
6107 bind(SHORT);
6108 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6109 ldr(tmp3, Address(a1, start_offset));
6110 ldr(tmp4, Address(a2, start_offset));
6111 bind(LAST_CHECK);
6112 eor(tmp4, tmp3, tmp4);
6113 lslv(tmp5, tmp4, tmp5);
6114 cmp(tmp5, zr);
6115 bind(CSET_EQ);
6116 cset(result, EQ);
6117 b(DONE);
6118 }
6119
6120 bind(SAME);
6121 mov(result, true);
6122 // That's it.
6123 bind(DONE);
6124
6125 BLOCK_COMMENT("} array_equals");
6126 postcond(pc() != badAddress);
6127 return pc();
6128 }
6129
6130 // Compare Strings
6131
6132 // For Strings we're passed the address of the first characters in a1
6133 // and a2 and the length in cnt1.
6134 // There are two implementations. For arrays >= 8 bytes, all
6135 // comparisons (including the final one, which may overlap) are
6136 // performed 8 bytes at a time. For strings < 8 bytes, we compare a
6137 // halfword, then a short, and then a byte.
6138
6139 void MacroAssembler::string_equals(Register a1, Register a2,
6140 Register result, Register cnt1)
6141 {
6142 Label SAME, DONE, SHORT, NEXT_WORD;
6143 Register tmp1 = rscratch1;
6144 Register tmp2 = rscratch2;
6145
6146 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
6147
6148 #ifndef PRODUCT
6149 {
6150 char comment[64];
6151 os::snprintf_checked(comment, sizeof comment, "{string_equalsL");
6152 BLOCK_COMMENT(comment);
6153 }
6154 #endif
6155
6156 mov(result, false);
6157
6158 // Check for short strings, i.e. smaller than wordSize.
6159 subs(cnt1, cnt1, wordSize);
6160 br(Assembler::LT, SHORT);
6161 // Main 8 byte comparison loop.
6162 bind(NEXT_WORD); {
6163 ldr(tmp1, Address(post(a1, wordSize)));
6164 ldr(tmp2, Address(post(a2, wordSize)));
6165 subs(cnt1, cnt1, wordSize);
6166 eor(tmp1, tmp1, tmp2);
6167 cbnz(tmp1, DONE);
6168 } br(GT, NEXT_WORD);
6169 // Last longword. In the case where length == 4 we compare the
6170 // same longword twice, but that's still faster than another
6171 // conditional branch.
6172 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
6173 // length == 4.
6174 ldr(tmp1, Address(a1, cnt1));
6175 ldr(tmp2, Address(a2, cnt1));
6176 eor(tmp2, tmp1, tmp2);
6177 cbnz(tmp2, DONE);
6178 b(SAME);
6179
6180 bind(SHORT);
6181 Label TAIL03, TAIL01;
6182
6183 tbz(cnt1, 2, TAIL03); // 0-7 bytes left.
6184 {
6185 ldrw(tmp1, Address(post(a1, 4)));
6186 ldrw(tmp2, Address(post(a2, 4)));
6187 eorw(tmp1, tmp1, tmp2);
6188 cbnzw(tmp1, DONE);
6189 }
6190 bind(TAIL03);
6191 tbz(cnt1, 1, TAIL01); // 0-3 bytes left.
6192 {
6193 ldrh(tmp1, Address(post(a1, 2)));
6194 ldrh(tmp2, Address(post(a2, 2)));
6195 eorw(tmp1, tmp1, tmp2);
6196 cbnzw(tmp1, DONE);
6197 }
6198 bind(TAIL01);
6199 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6200 {
6201 ldrb(tmp1, a1);
6202 ldrb(tmp2, a2);
6203 eorw(tmp1, tmp1, tmp2);
6204 cbnzw(tmp1, DONE);
6205 }
6206 // Arrays are equal.
6207 bind(SAME);
6208 mov(result, true);
6209
6210 // That's it.
6211 bind(DONE);
6212 BLOCK_COMMENT("} string_equals");
6213 }
6214
6215
6216 // The size of the blocks erased by the zero_blocks stub. We must
6217 // handle anything smaller than this ourselves in zero_words().
6218 const int MacroAssembler::zero_words_block_size = 8;
6219
6220 // zero_words() is used by C2 ClearArray patterns and by
6221 // C1_MacroAssembler. It is as small as possible, handling small word
6222 // counts locally and delegating anything larger to the zero_blocks
6223 // stub. It is expanded many times in compiled code, so it is
6224 // important to keep it short.
6225
6226 // ptr: Address of a buffer to be zeroed.
6227 // cnt: Count in HeapWords.
6228 //
6229 // ptr, cnt, rscratch1, and rscratch2 are clobbered.
6230 address MacroAssembler::zero_words(Register ptr, Register cnt)
6231 {
6232 assert(is_power_of_2(zero_words_block_size), "adjust this");
6233
6234 BLOCK_COMMENT("zero_words {");
6235 assert(ptr == r10 && cnt == r11, "mismatch in register usage");
6236 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6237 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6238
6239 subs(rscratch1, cnt, zero_words_block_size);
6240 Label around;
6241 br(LO, around);
6242 {
6243 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6244 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6245 // Make sure this is a C2 compilation. C1 allocates space only for
6246 // trampoline stubs generated by Call LIR ops, and in any case it
6247 // makes sense for a C1 compilation task to proceed as quickly as
6248 // possible.
6249 CompileTask* task;
6250 if (StubRoutines::aarch64::complete()
6251 && Thread::current()->is_Compiler_thread()
6252 && (task = ciEnv::current()->task())
6253 && is_c2_compile(task->comp_level())) {
6254 address tpc = trampoline_call(zero_blocks);
6255 if (tpc == nullptr) {
6256 DEBUG_ONLY(reset_labels(around));
6257 return nullptr;
6258 }
6259 } else {
6260 far_call(zero_blocks);
6261 }
6262 }
6263 bind(around);
6264
6265 // We have a few words left to do. zero_blocks has adjusted r10 and r11
6266 // for us.
6267 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) {
6268 Label l;
6269 tbz(cnt, exact_log2(i), l);
6270 for (int j = 0; j < i; j += 2) {
6271 stp(zr, zr, post(ptr, 2 * BytesPerWord));
6272 }
6273 bind(l);
6274 }
6275 {
6276 Label l;
6277 tbz(cnt, 0, l);
6278 str(zr, Address(ptr));
6279 bind(l);
6280 }
6281
6282 BLOCK_COMMENT("} zero_words");
6283 return pc();
6284 }
6285
6286 // base: Address of a buffer to be zeroed, 8 bytes aligned.
6287 // cnt: Immediate count in HeapWords.
6288 //
6289 // r10, r11, rscratch1, and rscratch2 are clobbered.
6290 address MacroAssembler::zero_words(Register base, uint64_t cnt)
6291 {
6292 assert(wordSize <= BlockZeroingLowLimit,
6293 "increase BlockZeroingLowLimit");
6294 address result = nullptr;
6295 if (cnt <= (uint64_t)BlockZeroingLowLimit / BytesPerWord) {
6296 #ifndef PRODUCT
6297 {
6298 char buf[64];
6299 os::snprintf_checked(buf, sizeof buf, "zero_words (count = %" PRIu64 ") {", cnt);
6300 BLOCK_COMMENT(buf);
6301 }
6302 #endif
6303 if (cnt >= 16) {
6304 uint64_t loops = cnt/16;
6305 if (loops > 1) {
6306 mov(rscratch2, loops - 1);
6307 }
6308 {
6309 Label loop;
6310 bind(loop);
6311 for (int i = 0; i < 16; i += 2) {
6312 stp(zr, zr, Address(base, i * BytesPerWord));
6313 }
6314 add(base, base, 16 * BytesPerWord);
6315 if (loops > 1) {
6316 subs(rscratch2, rscratch2, 1);
6317 br(GE, loop);
6318 }
6319 }
6320 }
6321 cnt %= 16;
6322 int i = cnt & 1; // store any odd word to start
6323 if (i) str(zr, Address(base));
6324 for (; i < (int)cnt; i += 2) {
6325 stp(zr, zr, Address(base, i * wordSize));
6326 }
6327 BLOCK_COMMENT("} zero_words");
6328 result = pc();
6329 } else {
6330 mov(r10, base); mov(r11, cnt);
6331 result = zero_words(r10, r11);
6332 }
6333 return result;
6334 }
6335
6336 // Zero blocks of memory by using DC ZVA.
6337 //
6338 // Aligns the base address first sufficiently for DC ZVA, then uses
6339 // DC ZVA repeatedly for every full block. cnt is the size to be
6340 // zeroed in HeapWords. Returns the count of words left to be zeroed
6341 // in cnt.
6342 //
6343 // NOTE: This is intended to be used in the zero_blocks() stub. If
6344 // you want to use it elsewhere, note that cnt must be >= 2*zva_length.
6345 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) {
6346 Register tmp = rscratch1;
6347 Register tmp2 = rscratch2;
6348 int zva_length = VM_Version::zva_length();
6349 Label initial_table_end, loop_zva;
6350 Label fini;
6351
6352 // Base must be 16 byte aligned. If not just return and let caller handle it
6353 tst(base, 0x0f);
6354 br(Assembler::NE, fini);
6355 // Align base with ZVA length.
6356 neg(tmp, base);
6357 andr(tmp, tmp, zva_length - 1);
6358
6359 // tmp: the number of bytes to be filled to align the base with ZVA length.
6360 add(base, base, tmp);
6361 sub(cnt, cnt, tmp, Assembler::ASR, 3);
6362 adr(tmp2, initial_table_end);
6363 sub(tmp2, tmp2, tmp, Assembler::LSR, 2);
6364 br(tmp2);
6365
6366 for (int i = -zva_length + 16; i < 0; i += 16)
6367 stp(zr, zr, Address(base, i));
6368 bind(initial_table_end);
6369
6370 sub(cnt, cnt, zva_length >> 3);
6371 bind(loop_zva);
6372 dc(Assembler::ZVA, base);
6373 subs(cnt, cnt, zva_length >> 3);
6374 add(base, base, zva_length);
6375 br(Assembler::GE, loop_zva);
6376 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA
6377 bind(fini);
6378 }
6379
6380 // base: Address of a buffer to be filled, 8 bytes aligned.
6381 // cnt: Count in 8-byte unit.
6382 // value: Value to be filled with.
6383 // base will point to the end of the buffer after filling.
6384 void MacroAssembler::fill_words(Register base, Register cnt, Register value)
6385 {
6386 // Algorithm:
6387 //
6388 // if (cnt == 0) {
6389 // return;
6390 // }
6391 // if ((p & 8) != 0) {
6392 // *p++ = v;
6393 // }
6394 //
6395 // scratch1 = cnt & 14;
6396 // cnt -= scratch1;
6397 // p += scratch1;
6398 // switch (scratch1 / 2) {
6399 // do {
6400 // cnt -= 16;
6401 // p[-16] = v;
6402 // p[-15] = v;
6403 // case 7:
6404 // p[-14] = v;
6405 // p[-13] = v;
6406 // case 6:
6407 // p[-12] = v;
6408 // p[-11] = v;
6409 // // ...
6410 // case 1:
6411 // p[-2] = v;
6412 // p[-1] = v;
6413 // case 0:
6414 // p += 16;
6415 // } while (cnt);
6416 // }
6417 // if ((cnt & 1) == 1) {
6418 // *p++ = v;
6419 // }
6420
6421 assert_different_registers(base, cnt, value, rscratch1, rscratch2);
6422
6423 Label fini, skip, entry, loop;
6424 const int unroll = 8; // Number of stp instructions we'll unroll
6425
6426 cbz(cnt, fini);
6427 tbz(base, 3, skip);
6428 str(value, Address(post(base, 8)));
6429 sub(cnt, cnt, 1);
6430 bind(skip);
6431
6432 andr(rscratch1, cnt, (unroll-1) * 2);
6433 sub(cnt, cnt, rscratch1);
6434 add(base, base, rscratch1, Assembler::LSL, 3);
6435 adr(rscratch2, entry);
6436 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1);
6437 br(rscratch2);
6438
6439 bind(loop);
6440 add(base, base, unroll * 16);
6441 for (int i = -unroll; i < 0; i++)
6442 stp(value, value, Address(base, i * 16));
6443 bind(entry);
6444 subs(cnt, cnt, unroll * 2);
6445 br(Assembler::GE, loop);
6446
6447 tbz(cnt, 0, fini);
6448 str(value, Address(post(base, 8)));
6449 bind(fini);
6450 }
6451
6452 // Intrinsic for
6453 //
6454 // - sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6455 // Encodes char[] to byte[] in ISO-8859-1
6456 //
6457 // - java.lang.StringCoding#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6458 // Encodes byte[] (containing UTF-16) to byte[] in ISO-8859-1
6459 //
6460 // - java.lang.StringCoding#encodeAsciiArray0(char[] sa, int sp, byte[] da, int dp, int len)
6461 // Encodes char[] to byte[] in ASCII
6462 //
6463 // This version always returns the number of characters copied, and does not
6464 // clobber the 'len' register. A successful copy will complete with the post-
6465 // condition: 'res' == 'len', while an unsuccessful copy will exit with the
6466 // post-condition: 0 <= 'res' < 'len'.
6467 //
6468 // NOTE: Attempts to use 'ld2' (and 'umaxv' in the ISO part) has proven to
6469 // degrade performance (on Ampere Altra - Neoverse N1), to an extent
6470 // beyond the acceptable, even though the footprint would be smaller.
6471 // Using 'umaxv' in the ASCII-case comes with a small penalty but does
6472 // avoid additional bloat.
6473 //
6474 // Clobbers: src, dst, res, rscratch1, rscratch2, rflags
6475 void MacroAssembler::encode_iso_array(Register src, Register dst,
6476 Register len, Register res, bool ascii,
6477 FloatRegister vtmp0, FloatRegister vtmp1,
6478 FloatRegister vtmp2, FloatRegister vtmp3,
6479 FloatRegister vtmp4, FloatRegister vtmp5)
6480 {
6481 Register cnt = res;
6482 Register max = rscratch1;
6483 Register chk = rscratch2;
6484
6485 prfm(Address(src), PLDL1STRM);
6486 movw(cnt, len);
6487
6488 #define ASCII(insn) do { if (ascii) { insn; } } while (0)
6489
6490 Label LOOP_32, DONE_32, FAIL_32;
6491
6492 BIND(LOOP_32);
6493 {
6494 cmpw(cnt, 32);
6495 br(LT, DONE_32);
6496 ld1(vtmp0, vtmp1, vtmp2, vtmp3, T8H, Address(post(src, 64)));
6497 // Extract lower bytes.
6498 FloatRegister vlo0 = vtmp4;
6499 FloatRegister vlo1 = vtmp5;
6500 uzp1(vlo0, T16B, vtmp0, vtmp1);
6501 uzp1(vlo1, T16B, vtmp2, vtmp3);
6502 // Merge bits...
6503 orr(vtmp0, T16B, vtmp0, vtmp1);
6504 orr(vtmp2, T16B, vtmp2, vtmp3);
6505 // Extract merged upper bytes.
6506 FloatRegister vhix = vtmp0;
6507 uzp2(vhix, T16B, vtmp0, vtmp2);
6508 // ISO-check on hi-parts (all zero).
6509 // ASCII-check on lo-parts (no sign).
6510 FloatRegister vlox = vtmp1; // Merge lower bytes.
6511 ASCII(orr(vlox, T16B, vlo0, vlo1));
6512 umov(chk, vhix, D, 1); ASCII(cm(LT, vlox, T16B, vlox));
6513 fmovd(max, vhix); ASCII(umaxv(vlox, T16B, vlox));
6514 orr(chk, chk, max); ASCII(umov(max, vlox, B, 0));
6515 ASCII(orr(chk, chk, max));
6516 cbnz(chk, FAIL_32);
6517 subw(cnt, cnt, 32);
6518 st1(vlo0, vlo1, T16B, Address(post(dst, 32)));
6519 b(LOOP_32);
6520 }
6521 BIND(FAIL_32);
6522 sub(src, src, 64);
6523 BIND(DONE_32);
6524
6525 Label LOOP_8, SKIP_8;
6526
6527 BIND(LOOP_8);
6528 {
6529 cmpw(cnt, 8);
6530 br(LT, SKIP_8);
6531 FloatRegister vhi = vtmp0;
6532 FloatRegister vlo = vtmp1;
6533 ld1(vtmp3, T8H, src);
6534 uzp1(vlo, T16B, vtmp3, vtmp3);
6535 uzp2(vhi, T16B, vtmp3, vtmp3);
6536 // ISO-check on hi-parts (all zero).
6537 // ASCII-check on lo-parts (no sign).
6538 ASCII(cm(LT, vtmp2, T16B, vlo));
6539 fmovd(chk, vhi); ASCII(umaxv(vtmp2, T16B, vtmp2));
6540 ASCII(umov(max, vtmp2, B, 0));
6541 ASCII(orr(chk, chk, max));
6542 cbnz(chk, SKIP_8);
6543
6544 strd(vlo, Address(post(dst, 8)));
6545 subw(cnt, cnt, 8);
6546 add(src, src, 16);
6547 b(LOOP_8);
6548 }
6549 BIND(SKIP_8);
6550
6551 #undef ASCII
6552
6553 Label LOOP, DONE;
6554
6555 cbz(cnt, DONE);
6556 BIND(LOOP);
6557 {
6558 Register chr = rscratch1;
6559 ldrh(chr, Address(post(src, 2)));
6560 tst(chr, ascii ? 0xff80 : 0xff00);
6561 br(NE, DONE);
6562 strb(chr, Address(post(dst, 1)));
6563 subs(cnt, cnt, 1);
6564 br(GT, LOOP);
6565 }
6566 BIND(DONE);
6567 // Return index where we stopped.
6568 subw(res, len, cnt);
6569 }
6570
6571 // Inflate byte[] array to char[].
6572 // Clobbers: src, dst, len, rflags, rscratch1, v0-v6
6573 address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
6574 FloatRegister vtmp1, FloatRegister vtmp2,
6575 FloatRegister vtmp3, Register tmp4) {
6576 Label big, done, after_init, to_stub;
6577
6578 assert_different_registers(src, dst, len, tmp4, rscratch1);
6579
6580 fmovd(vtmp1, 0.0);
6581 lsrw(tmp4, len, 3);
6582 bind(after_init);
6583 cbnzw(tmp4, big);
6584 // Short string: less than 8 bytes.
6585 {
6586 Label loop, tiny;
6587
6588 cmpw(len, 4);
6589 br(LT, tiny);
6590 // Use SIMD to do 4 bytes.
6591 ldrs(vtmp2, post(src, 4));
6592 zip1(vtmp3, T8B, vtmp2, vtmp1);
6593 subw(len, len, 4);
6594 strd(vtmp3, post(dst, 8));
6595
6596 cbzw(len, done);
6597
6598 // Do the remaining bytes by steam.
6599 bind(loop);
6600 ldrb(tmp4, post(src, 1));
6601 strh(tmp4, post(dst, 2));
6602 subw(len, len, 1);
6603
6604 bind(tiny);
6605 cbnz(len, loop);
6606
6607 b(done);
6608 }
6609
6610 if (SoftwarePrefetchHintDistance >= 0) {
6611 bind(to_stub);
6612 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate());
6613 assert(stub.target() != nullptr, "large_byte_array_inflate stub has not been generated");
6614 address tpc = trampoline_call(stub);
6615 if (tpc == nullptr) {
6616 DEBUG_ONLY(reset_labels(big, done));
6617 postcond(pc() == badAddress);
6618 return nullptr;
6619 }
6620 b(after_init);
6621 }
6622
6623 // Unpack the bytes 8 at a time.
6624 bind(big);
6625 {
6626 Label loop, around, loop_last, loop_start;
6627
6628 if (SoftwarePrefetchHintDistance >= 0) {
6629 const int large_loop_threshold = (64 + 16)/8;
6630 ldrd(vtmp2, post(src, 8));
6631 andw(len, len, 7);
6632 cmp(tmp4, (u1)large_loop_threshold);
6633 br(GE, to_stub);
6634 b(loop_start);
6635
6636 bind(loop);
6637 ldrd(vtmp2, post(src, 8));
6638 bind(loop_start);
6639 subs(tmp4, tmp4, 1);
6640 br(EQ, loop_last);
6641 zip1(vtmp2, T16B, vtmp2, vtmp1);
6642 ldrd(vtmp3, post(src, 8));
6643 st1(vtmp2, T8H, post(dst, 16));
6644 subs(tmp4, tmp4, 1);
6645 zip1(vtmp3, T16B, vtmp3, vtmp1);
6646 st1(vtmp3, T8H, post(dst, 16));
6647 br(NE, loop);
6648 b(around);
6649 bind(loop_last);
6650 zip1(vtmp2, T16B, vtmp2, vtmp1);
6651 st1(vtmp2, T8H, post(dst, 16));
6652 bind(around);
6653 cbz(len, done);
6654 } else {
6655 andw(len, len, 7);
6656 bind(loop);
6657 ldrd(vtmp2, post(src, 8));
6658 sub(tmp4, tmp4, 1);
6659 zip1(vtmp3, T16B, vtmp2, vtmp1);
6660 st1(vtmp3, T8H, post(dst, 16));
6661 cbnz(tmp4, loop);
6662 }
6663 }
6664
6665 // Do the tail of up to 8 bytes.
6666 add(src, src, len);
6667 ldrd(vtmp3, Address(src, -8));
6668 add(dst, dst, len, ext::uxtw, 1);
6669 zip1(vtmp3, T16B, vtmp3, vtmp1);
6670 strq(vtmp3, Address(dst, -16));
6671
6672 bind(done);
6673 postcond(pc() != badAddress);
6674 return pc();
6675 }
6676
6677 // Compress char[] array to byte[].
6678 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
6679 // Return the array length if every element in array can be encoded,
6680 // otherwise, the index of first non-latin1 (> 0xff) character.
6681 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
6682 Register res,
6683 FloatRegister tmp0, FloatRegister tmp1,
6684 FloatRegister tmp2, FloatRegister tmp3,
6685 FloatRegister tmp4, FloatRegister tmp5) {
6686 encode_iso_array(src, dst, len, res, false, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5);
6687 }
6688
6689 // java.math.round(double a)
6690 // Returns the closest long to the argument, with ties rounding to
6691 // positive infinity. This requires some fiddling for corner
6692 // cases. We take care to avoid double rounding in e.g. (jlong)(a + 0.5).
6693 void MacroAssembler::java_round_double(Register dst, FloatRegister src,
6694 FloatRegister ftmp) {
6695 Label DONE;
6696 BLOCK_COMMENT("java_round_double: { ");
6697 fmovd(rscratch1, src);
6698 // Use RoundToNearestTiesAway unless src small and -ve.
6699 fcvtasd(dst, src);
6700 // Test if src >= 0 || abs(src) >= 0x1.0p52
6701 eor(rscratch1, rscratch1, UCONST64(1) << 63); // flip sign bit
6702 mov(rscratch2, julong_cast(0x1.0p52));
6703 cmp(rscratch1, rscratch2);
6704 br(HS, DONE); {
6705 // src < 0 && abs(src) < 0x1.0p52
6706 // src may have a fractional part, so add 0.5
6707 fmovd(ftmp, 0.5);
6708 faddd(ftmp, src, ftmp);
6709 // Convert double to jlong, use RoundTowardsNegative
6710 fcvtmsd(dst, ftmp);
6711 }
6712 bind(DONE);
6713 BLOCK_COMMENT("} java_round_double");
6714 }
6715
6716 void MacroAssembler::java_round_float(Register dst, FloatRegister src,
6717 FloatRegister ftmp) {
6718 Label DONE;
6719 BLOCK_COMMENT("java_round_float: { ");
6720 fmovs(rscratch1, src);
6721 // Use RoundToNearestTiesAway unless src small and -ve.
6722 fcvtassw(dst, src);
6723 // Test if src >= 0 || abs(src) >= 0x1.0p23
6724 eor(rscratch1, rscratch1, 0x80000000); // flip sign bit
6725 mov(rscratch2, jint_cast(0x1.0p23f));
6726 cmp(rscratch1, rscratch2);
6727 br(HS, DONE); {
6728 // src < 0 && |src| < 0x1.0p23
6729 // src may have a fractional part, so add 0.5
6730 fmovs(ftmp, 0.5f);
6731 fadds(ftmp, src, ftmp);
6732 // Convert float to jint, use RoundTowardsNegative
6733 fcvtmssw(dst, ftmp);
6734 }
6735 bind(DONE);
6736 BLOCK_COMMENT("} java_round_float");
6737 }
6738
6739 // get_thread() can be called anywhere inside generated code so we
6740 // need to save whatever non-callee save context might get clobbered
6741 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
6742 // the call setup code.
6743 //
6744 // On Linux, aarch64_get_thread_helper() clobbers only r0, r1, and flags.
6745 // On other systems, the helper is a usual C function.
6746 //
6747 void MacroAssembler::get_thread(Register dst) {
6748 RegSet saved_regs =
6749 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6750 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6751
6752 protect_return_address();
6753 push(saved_regs, sp);
6754
6755 mov(lr, ExternalAddress(CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)));
6756 blr(lr);
6757 if (dst != c_rarg0) {
6758 mov(dst, c_rarg0);
6759 }
6760
6761 pop(saved_regs, sp);
6762 authenticate_return_address();
6763 }
6764
6765 void MacroAssembler::cache_wb(Address line) {
6766 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
6767 assert(line.index() == noreg, "index should be noreg");
6768 assert(line.offset() == 0, "offset should be 0");
6769 // would like to assert this
6770 // assert(line._ext.shift == 0, "shift should be zero");
6771 if (VM_Version::supports_dcpop()) {
6772 // writeback using clear virtual address to point of persistence
6773 dc(Assembler::CVAP, line.base());
6774 } else {
6775 // no need to generate anything as Unsafe.writebackMemory should
6776 // never invoke this stub
6777 }
6778 }
6779
6780 void MacroAssembler::cache_wbsync(bool is_pre) {
6781 // we only need a barrier post sync
6782 if (!is_pre) {
6783 membar(Assembler::AnyAny);
6784 }
6785 }
6786
6787 void MacroAssembler::verify_sve_vector_length(Register tmp) {
6788 if (!UseSVE || VM_Version::get_max_supported_sve_vector_length() == FloatRegister::sve_vl_min) {
6789 return;
6790 }
6791 // Make sure that native code does not change SVE vector length.
6792 Label verify_ok;
6793 movw(tmp, zr);
6794 sve_inc(tmp, B);
6795 subsw(zr, tmp, VM_Version::get_initial_sve_vector_length());
6796 br(EQ, verify_ok);
6797 stop("Error: SVE vector length has changed since jvm startup");
6798 bind(verify_ok);
6799 }
6800
6801 void MacroAssembler::verify_ptrue() {
6802 Label verify_ok;
6803 if (!UseSVE) {
6804 return;
6805 }
6806 sve_cntp(rscratch1, B, ptrue, ptrue); // get true elements count.
6807 sve_dec(rscratch1, B);
6808 cbz(rscratch1, verify_ok);
6809 stop("Error: the preserved predicate register (p7) elements are not all true");
6810 bind(verify_ok);
6811 }
6812
6813 void MacroAssembler::safepoint_isb() {
6814 isb();
6815 #ifndef PRODUCT
6816 if (VerifyCrossModifyFence) {
6817 // Clear the thread state.
6818 strb(zr, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6819 }
6820 #endif
6821 }
6822
6823 #ifndef PRODUCT
6824 void MacroAssembler::verify_cross_modify_fence_not_required() {
6825 if (VerifyCrossModifyFence) {
6826 // Check if thread needs a cross modify fence.
6827 ldrb(rscratch1, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6828 Label fence_not_required;
6829 cbz(rscratch1, fence_not_required);
6830 // If it does then fail.
6831 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::verify_cross_modify_fence_failure)));
6832 mov(c_rarg0, rthread);
6833 blr(rscratch1);
6834 bind(fence_not_required);
6835 }
6836 }
6837 #endif
6838
6839 void MacroAssembler::spin_wait() {
6840 block_comment("spin_wait {");
6841 for (int i = 0; i < VM_Version::spin_wait_desc().inst_count(); ++i) {
6842 switch (VM_Version::spin_wait_desc().inst()) {
6843 case SpinWait::NOP:
6844 nop();
6845 break;
6846 case SpinWait::ISB:
6847 isb();
6848 break;
6849 case SpinWait::YIELD:
6850 yield();
6851 break;
6852 case SpinWait::SB:
6853 assert(VM_Version::supports_sb(), "current CPU does not support SB instruction");
6854 sb();
6855 break;
6856 default:
6857 ShouldNotReachHere();
6858 }
6859 }
6860 block_comment("}");
6861 }
6862
6863 // Stack frame creation/removal
6864
6865 void MacroAssembler::enter(bool strip_ret_addr) {
6866 if (strip_ret_addr) {
6867 // Addresses can only be signed once. If there are multiple nested frames being created
6868 // in the same function, then the return address needs stripping first.
6869 strip_return_address();
6870 }
6871 protect_return_address();
6872 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
6873 mov(rfp, sp);
6874 }
6875
6876 void MacroAssembler::leave() {
6877 mov(sp, rfp);
6878 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
6879 authenticate_return_address();
6880 }
6881
6882 // ROP Protection
6883 // Use the AArch64 PAC feature to add ROP protection for generated code. Use whenever creating/
6884 // destroying stack frames or whenever directly loading/storing the LR to memory.
6885 // If ROP protection is not set then these functions are no-ops.
6886 // For more details on PAC see pauth_aarch64.hpp.
6887
6888 // Sign the LR. Use during construction of a stack frame, before storing the LR to memory.
6889 // Uses value zero as the modifier.
6890 //
6891 void MacroAssembler::protect_return_address() {
6892 if (VM_Version::use_rop_protection()) {
6893 check_return_address();
6894 paciaz();
6895 }
6896 }
6897
6898 // Sign the return value in the given register. Use before updating the LR in the existing stack
6899 // frame for the current function.
6900 // Uses value zero as the modifier.
6901 //
6902 void MacroAssembler::protect_return_address(Register return_reg) {
6903 if (VM_Version::use_rop_protection()) {
6904 check_return_address(return_reg);
6905 paciza(return_reg);
6906 }
6907 }
6908
6909 // Authenticate the LR. Use before function return, after restoring FP and loading LR from memory.
6910 // Uses value zero as the modifier.
6911 //
6912 void MacroAssembler::authenticate_return_address() {
6913 if (VM_Version::use_rop_protection()) {
6914 autiaz();
6915 check_return_address();
6916 }
6917 }
6918
6919 // Authenticate the return value in the given register. Use before updating the LR in the existing
6920 // stack frame for the current function.
6921 // Uses value zero as the modifier.
6922 //
6923 void MacroAssembler::authenticate_return_address(Register return_reg) {
6924 if (VM_Version::use_rop_protection()) {
6925 autiza(return_reg);
6926 check_return_address(return_reg);
6927 }
6928 }
6929
6930 // Strip any PAC data from LR without performing any authentication. Use with caution - only if
6931 // there is no guaranteed way of authenticating the LR.
6932 //
6933 void MacroAssembler::strip_return_address() {
6934 if (VM_Version::use_rop_protection()) {
6935 xpaclri();
6936 }
6937 }
6938
6939 #ifndef PRODUCT
6940 // PAC failures can be difficult to debug. After an authentication failure, a segfault will only
6941 // occur when the pointer is used - ie when the program returns to the invalid LR. At this point
6942 // it is difficult to debug back to the callee function.
6943 // This function simply loads from the address in the given register.
6944 // Use directly after authentication to catch authentication failures.
6945 // Also use before signing to check that the pointer is valid and hasn't already been signed.
6946 //
6947 void MacroAssembler::check_return_address(Register return_reg) {
6948 if (VM_Version::use_rop_protection()) {
6949 ldr(zr, Address(return_reg));
6950 }
6951 }
6952 #endif
6953
6954 // The java_calling_convention describes stack locations as ideal slots on
6955 // a frame with no abi restrictions. Since we must observe abi restrictions
6956 // (like the placement of the register window) the slots must be biased by
6957 // the following value.
6958 static int reg2offset_in(VMReg r) {
6959 // Account for saved rfp and lr
6960 // This should really be in_preserve_stack_slots
6961 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
6962 }
6963
6964 static int reg2offset_out(VMReg r) {
6965 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
6966 }
6967
6968 // On 64bit we will store integer like items to the stack as
6969 // 64bits items (AArch64 ABI) even though java would only store
6970 // 32bits for a parameter. On 32bit it will simply be 32bits
6971 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
6972 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp) {
6973 if (src.first()->is_stack()) {
6974 if (dst.first()->is_stack()) {
6975 // stack to stack
6976 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
6977 str(tmp, Address(sp, reg2offset_out(dst.first())));
6978 } else {
6979 // stack to reg
6980 ldrsw(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
6981 }
6982 } else if (dst.first()->is_stack()) {
6983 // reg to stack
6984 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
6985 } else {
6986 if (dst.first() != src.first()) {
6987 sxtw(dst.first()->as_Register(), src.first()->as_Register());
6988 }
6989 }
6990 }
6991
6992 // An oop arg. Must pass a handle not the oop itself
6993 void MacroAssembler::object_move(
6994 OopMap* map,
6995 int oop_handle_offset,
6996 int framesize_in_slots,
6997 VMRegPair src,
6998 VMRegPair dst,
6999 bool is_receiver,
7000 int* receiver_offset) {
7001
7002 // must pass a handle. First figure out the location we use as a handle
7003
7004 Register rHandle = dst.first()->is_stack() ? rscratch2 : dst.first()->as_Register();
7005
7006 // See if oop is null if it is we need no handle
7007
7008 if (src.first()->is_stack()) {
7009
7010 // Oop is already on the stack as an argument
7011 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
7012 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
7013 if (is_receiver) {
7014 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
7015 }
7016
7017 ldr(rscratch1, Address(rfp, reg2offset_in(src.first())));
7018 lea(rHandle, Address(rfp, reg2offset_in(src.first())));
7019 // conditionally move a null
7020 cmp(rscratch1, zr);
7021 csel(rHandle, zr, rHandle, Assembler::EQ);
7022 } else {
7023
7024 // Oop is in an a register we must store it to the space we reserve
7025 // on the stack for oop_handles and pass a handle if oop is non-null
7026
7027 const Register rOop = src.first()->as_Register();
7028 int oop_slot;
7029 if (rOop == j_rarg0)
7030 oop_slot = 0;
7031 else if (rOop == j_rarg1)
7032 oop_slot = 1;
7033 else if (rOop == j_rarg2)
7034 oop_slot = 2;
7035 else if (rOop == j_rarg3)
7036 oop_slot = 3;
7037 else if (rOop == j_rarg4)
7038 oop_slot = 4;
7039 else if (rOop == j_rarg5)
7040 oop_slot = 5;
7041 else if (rOop == j_rarg6)
7042 oop_slot = 6;
7043 else {
7044 assert(rOop == j_rarg7, "wrong register");
7045 oop_slot = 7;
7046 }
7047
7048 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
7049 int offset = oop_slot*VMRegImpl::stack_slot_size;
7050
7051 map->set_oop(VMRegImpl::stack2reg(oop_slot));
7052 // Store oop in handle area, may be null
7053 str(rOop, Address(sp, offset));
7054 if (is_receiver) {
7055 *receiver_offset = offset;
7056 }
7057
7058 cmp(rOop, zr);
7059 lea(rHandle, Address(sp, offset));
7060 // conditionally move a null
7061 csel(rHandle, zr, rHandle, Assembler::EQ);
7062 }
7063
7064 // If arg is on the stack then place it otherwise it is already in correct reg.
7065 if (dst.first()->is_stack()) {
7066 str(rHandle, Address(sp, reg2offset_out(dst.first())));
7067 }
7068 }
7069
7070 // A float arg may have to do float reg int reg conversion
7071 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp) {
7072 if (src.first()->is_stack()) {
7073 if (dst.first()->is_stack()) {
7074 ldrw(tmp, Address(rfp, reg2offset_in(src.first())));
7075 strw(tmp, Address(sp, reg2offset_out(dst.first())));
7076 } else {
7077 ldrs(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7078 }
7079 } else if (src.first() != dst.first()) {
7080 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7081 fmovs(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7082 else
7083 strs(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7084 }
7085 }
7086
7087 // A long move
7088 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp) {
7089 if (src.first()->is_stack()) {
7090 if (dst.first()->is_stack()) {
7091 // stack to stack
7092 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7093 str(tmp, Address(sp, reg2offset_out(dst.first())));
7094 } else {
7095 // stack to reg
7096 ldr(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
7097 }
7098 } else if (dst.first()->is_stack()) {
7099 // reg to stack
7100 // Do we really have to sign extend???
7101 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
7102 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
7103 } else {
7104 if (dst.first() != src.first()) {
7105 mov(dst.first()->as_Register(), src.first()->as_Register());
7106 }
7107 }
7108 }
7109
7110
7111 // A double move
7112 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp) {
7113 if (src.first()->is_stack()) {
7114 if (dst.first()->is_stack()) {
7115 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7116 str(tmp, Address(sp, reg2offset_out(dst.first())));
7117 } else {
7118 ldrd(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7119 }
7120 } else if (src.first() != dst.first()) {
7121 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7122 fmovd(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7123 else
7124 strd(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7125 }
7126 }
7127
7128 // Implements fast-locking.
7129 //
7130 // - obj: the object to be locked
7131 // - t1, t2, t3: temporary registers, will be destroyed
7132 // - slow: branched to if locking fails, absolute offset may larger than 32KB (imm14 encoding).
7133 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow) {
7134 assert_different_registers(basic_lock, obj, t1, t2, t3, rscratch1);
7135
7136 Label push;
7137 const Register top = t1;
7138 const Register mark = t2;
7139 const Register t = t3;
7140
7141 // Preload the markWord. It is important that this is the first
7142 // instruction emitted as it is part of C1's null check semantics.
7143 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7144
7145 if (UseObjectMonitorTable) {
7146 // Clear cache in case fast locking succeeds or we need to take the slow-path.
7147 str(zr, Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))));
7148 }
7149
7150 if (DiagnoseSyncOnValueBasedClasses != 0) {
7151 load_klass(t1, obj);
7152 ldrb(t1, Address(t1, Klass::misc_flags_offset()));
7153 tst(t1, KlassFlags::_misc_is_value_based_class);
7154 br(Assembler::NE, slow);
7155 }
7156
7157 // Check if the lock-stack is full.
7158 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7159 cmpw(top, (unsigned)LockStack::end_offset());
7160 br(Assembler::GE, slow);
7161
7162 // Check for recursion.
7163 subw(t, top, oopSize);
7164 ldr(t, Address(rthread, t));
7165 cmp(obj, t);
7166 br(Assembler::EQ, push);
7167
7168 // Check header for monitor (0b10).
7169 tst(mark, markWord::monitor_value);
7170 br(Assembler::NE, slow);
7171
7172 // Try to lock. Transition lock bits 0b01 => 0b00
7173 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7174 orr(mark, mark, markWord::unlocked_value);
7175 eor(t, mark, markWord::unlocked_value);
7176 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
7177 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
7178 br(Assembler::NE, slow);
7179
7180 bind(push);
7181 // After successful lock, push object on lock-stack.
7182 str(obj, Address(rthread, top));
7183 addw(top, top, oopSize);
7184 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7185 }
7186
7187 // Implements fast-unlocking.
7188 //
7189 // - obj: the object to be unlocked
7190 // - t1, t2, t3: temporary registers
7191 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
7192 void MacroAssembler::fast_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
7193 // cmpxchg clobbers rscratch1.
7194 assert_different_registers(obj, t1, t2, t3, rscratch1);
7195
7196 #ifdef ASSERT
7197 {
7198 // Check for lock-stack underflow.
7199 Label stack_ok;
7200 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
7201 cmpw(t1, (unsigned)LockStack::start_offset());
7202 br(Assembler::GE, stack_ok);
7203 STOP("Lock-stack underflow");
7204 bind(stack_ok);
7205 }
7206 #endif
7207
7208 Label unlocked, push_and_slow;
7209 const Register top = t1;
7210 const Register mark = t2;
7211 const Register t = t3;
7212
7213 // Check if obj is top of lock-stack.
7214 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7215 subw(top, top, oopSize);
7216 ldr(t, Address(rthread, top));
7217 cmp(obj, t);
7218 br(Assembler::NE, slow);
7219
7220 // Pop lock-stack.
7221 DEBUG_ONLY(str(zr, Address(rthread, top));)
7222 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7223
7224 // Check if recursive.
7225 subw(t, top, oopSize);
7226 ldr(t, Address(rthread, t));
7227 cmp(obj, t);
7228 br(Assembler::EQ, unlocked);
7229
7230 // Not recursive. Check header for monitor (0b10).
7231 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7232 tbnz(mark, log2i_exact(markWord::monitor_value), push_and_slow);
7233
7234 #ifdef ASSERT
7235 // Check header not unlocked (0b01).
7236 Label not_unlocked;
7237 tbz(mark, log2i_exact(markWord::unlocked_value), not_unlocked);
7238 stop("fast_unlock already unlocked");
7239 bind(not_unlocked);
7240 #endif
7241
7242 // Try to unlock. Transition lock bits 0b00 => 0b01
7243 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7244 orr(t, mark, markWord::unlocked_value);
7245 cmpxchg(obj, mark, t, Assembler::xword,
7246 /*acquire*/ false, /*release*/ true, /*weak*/ false, noreg);
7247 br(Assembler::EQ, unlocked);
7248
7249 bind(push_and_slow);
7250 // Restore lock-stack and handle the unlock in runtime.
7251 DEBUG_ONLY(str(obj, Address(rthread, top));)
7252 addw(top, top, oopSize);
7253 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7254 b(slow);
7255
7256 bind(unlocked);
7257 }