1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/powerOfTwo.hpp"
37
38 class OopMap;
39
40 // MacroAssembler extends Assembler by frequently used macros.
41 //
42 // Instructions for which a 'better' code sequence exists depending
43 // on arguments should also go in here.
44
45 class MacroAssembler: public Assembler {
46 friend class LIR_Assembler;
47
48 public:
49 using Assembler::mov;
50 using Assembler::movi;
51
52 protected:
53
54 // Support for VM calls
55 //
56 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
57 // may customize this version by overriding it for its purposes (e.g., to save/restore
58 // additional registers when doing a VM call).
59 virtual void call_VM_leaf_base(
60 address entry_point, // the entry point
61 int number_of_arguments, // the number of arguments to pop after the call
62 Label *retaddr = nullptr
63 );
64
65 virtual void call_VM_leaf_base(
66 address entry_point, // the entry point
67 int number_of_arguments, // the number of arguments to pop after the call
68 Label &retaddr) {
69 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
70 }
71
72 // This is the base routine called by the different versions of call_VM. The interpreter
73 // may customize this version by overriding it for its purposes (e.g., to save/restore
74 // additional registers when doing a VM call).
75 //
76 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
77 // returns the register which contains the thread upon return. If a thread register has been
78 // specified, the return value will correspond to that register. If no last_java_sp is specified
79 // (noreg) than rsp will be used instead.
80 virtual void call_VM_base( // returns the register containing the thread upon return
81 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
82 Register java_thread, // the thread if computed before ; use noreg otherwise
83 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
84 address entry_point, // the entry point
85 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
86 bool check_exceptions // whether to check for pending exceptions after return
87 );
88
89 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
90
91 enum KlassDecodeMode {
92 KlassDecodeNone,
93 KlassDecodeZero,
94 KlassDecodeXor,
95 KlassDecodeMovk
96 };
97
98 // Calculate decoding mode based on given parameters, used for checking then ultimately setting.
99 static KlassDecodeMode klass_decode_mode(address base, int shift, const size_t range);
100
101 private:
102 static KlassDecodeMode _klass_decode_mode;
103
104 // Returns above setting with asserts
105 static KlassDecodeMode klass_decode_mode();
106
107 public:
108 // Checks the decode mode and returns false if not compatible with preferred decoding mode.
109 static bool check_klass_decode_mode(address base, int shift, const size_t range);
110
111 // Sets the decode mode and returns false if cannot be set.
112 static bool set_klass_decode_mode(address base, int shift, const size_t range);
113
114 public:
115 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
116
117 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
118 // The implementation is only non-empty for the InterpreterMacroAssembler,
119 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
120 virtual void check_and_handle_popframe(Register java_thread);
121 virtual void check_and_handle_earlyret(Register java_thread);
122
123 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp = rscratch1);
124 void rt_call(address dest, Register tmp = rscratch1);
125
126 // Load Effective Address
127 void lea(Register r, const Address &a) {
128 InstructionMark im(this);
129 a.lea(this, r);
130 }
131
132 // Whether materializing the given address for a LDR/STR requires an
133 // additional lea instruction.
134 static bool legitimize_address_requires_lea(const Address &a, int size) {
135 return a.getMode() == Address::base_plus_offset &&
136 !Address::offset_ok_for_immed(a.offset(), exact_log2(size));
137 }
138
139 /* Sometimes we get misaligned loads and stores, usually from Unsafe
140 accesses, and these can exceed the offset range. */
141 Address legitimize_address(const Address &a, int size, Register scratch) {
142 if (legitimize_address_requires_lea(a, size)) {
143 block_comment("legitimize_address {");
144 lea(scratch, a);
145 block_comment("} legitimize_address");
146 return Address(scratch);
147 }
148 return a;
149 }
150
151 void addmw(Address a, Register incr, Register scratch) {
152 ldrw(scratch, a);
153 addw(scratch, scratch, incr);
154 strw(scratch, a);
155 }
156
157 // Add constant to memory word
158 void addmw(Address a, int imm, Register scratch) {
159 ldrw(scratch, a);
160 if (imm > 0)
161 addw(scratch, scratch, (unsigned)imm);
162 else
163 subw(scratch, scratch, (unsigned)-imm);
164 strw(scratch, a);
165 }
166
167 void bind(Label& L) {
168 Assembler::bind(L);
169 code()->clear_last_insn();
170 code()->set_last_label(pc());
171 }
172
173 void membar(Membar_mask_bits order_constraint);
174
175 using Assembler::ldr;
176 using Assembler::str;
177 using Assembler::ldrw;
178 using Assembler::strw;
179
180 void ldr(Register Rx, const Address &adr);
181 void ldrw(Register Rw, const Address &adr);
182 void str(Register Rx, const Address &adr);
183 void strw(Register Rx, const Address &adr);
184
185 // Frame creation and destruction shared between JITs.
186 void build_frame(int framesize);
187 void remove_frame(int framesize);
188
189 virtual void _call_Unimplemented(address call_site) {
190 mov(rscratch2, call_site);
191 }
192
193 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
194 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
195 // https://reviews.llvm.org/D3311
196
197 #ifdef _WIN64
198 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
199 #else
200 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
201 #endif
202
203 // aliases defined in AARCH64 spec
204
205 template<class T>
206 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
207
208 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
209 inline void cmp(Register Rd, unsigned imm) = delete;
210
211 template<class T>
212 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
213
214 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); }
215 inline void cmn(Register Rd, unsigned imm) = delete;
216
217 void cset(Register Rd, Assembler::Condition cond) {
218 csinc(Rd, zr, zr, ~cond);
219 }
220 void csetw(Register Rd, Assembler::Condition cond) {
221 csincw(Rd, zr, zr, ~cond);
222 }
223
224 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
225 csneg(Rd, Rn, Rn, ~cond);
226 }
227 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
228 csnegw(Rd, Rn, Rn, ~cond);
229 }
230
231 inline void movw(Register Rd, Register Rn) {
232 if (Rd == sp || Rn == sp) {
233 Assembler::addw(Rd, Rn, 0U);
234 } else {
235 orrw(Rd, zr, Rn);
236 }
237 }
238 inline void mov(Register Rd, Register Rn) {
239 assert(Rd != r31_sp && Rn != r31_sp, "should be");
240 if (Rd == Rn) {
241 } else if (Rd == sp || Rn == sp) {
242 Assembler::add(Rd, Rn, 0U);
243 } else {
244 orr(Rd, zr, Rn);
245 }
246 }
247
248 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
249 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
250
251 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
252 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
253
254 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
255 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
256
257 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
258 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
259 }
260 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
261 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
262 }
263
264 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
265 bfmw(Rd, Rn, lsb, (lsb + width - 1));
266 }
267 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
268 bfm(Rd, Rn, lsb , (lsb + width - 1));
269 }
270
271 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
272 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
273 }
274 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
275 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
276 }
277
278 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
279 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
280 }
281 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
282 sbfm(Rd, Rn, lsb , (lsb + width - 1));
283 }
284
285 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
286 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
287 }
288 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
289 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
290 }
291
292 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
293 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
294 }
295 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
296 ubfm(Rd, Rn, lsb , (lsb + width - 1));
297 }
298
299 inline void asrw(Register Rd, Register Rn, unsigned imm) {
300 sbfmw(Rd, Rn, imm, 31);
301 }
302
303 inline void asr(Register Rd, Register Rn, unsigned imm) {
304 sbfm(Rd, Rn, imm, 63);
305 }
306
307 inline void lslw(Register Rd, Register Rn, unsigned imm) {
308 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
309 }
310
311 inline void lsl(Register Rd, Register Rn, unsigned imm) {
312 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
313 }
314
315 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
316 ubfmw(Rd, Rn, imm, 31);
317 }
318
319 inline void lsr(Register Rd, Register Rn, unsigned imm) {
320 ubfm(Rd, Rn, imm, 63);
321 }
322
323 inline void rorw(Register Rd, Register Rn, unsigned imm) {
324 extrw(Rd, Rn, Rn, imm);
325 }
326
327 inline void ror(Register Rd, Register Rn, unsigned imm) {
328 extr(Rd, Rn, Rn, imm);
329 }
330
331 inline void rolw(Register Rd, Register Rn, unsigned imm) {
332 extrw(Rd, Rn, Rn, (32 - imm));
333 }
334
335 inline void rol(Register Rd, Register Rn, unsigned imm) {
336 extr(Rd, Rn, Rn, (64 - imm));
337 }
338
339 using Assembler::rax1;
340 using Assembler::eor3;
341
342 inline void rax1(Register Rd, Register Rn, Register Rm) {
343 eor(Rd, Rn, Rm, ROR, 63); // Rd = Rn ^ rol(Rm, 1)
344 }
345
346 inline void eor3(Register Rd, Register Rn, Register Rm, Register Rk) {
347 assert(Rd != Rn, "Use tmp register");
348 eor(Rd, Rm, Rk);
349 eor(Rd, Rd, Rn);
350 }
351
352 inline void sxtbw(Register Rd, Register Rn) {
353 sbfmw(Rd, Rn, 0, 7);
354 }
355 inline void sxthw(Register Rd, Register Rn) {
356 sbfmw(Rd, Rn, 0, 15);
357 }
358 inline void sxtb(Register Rd, Register Rn) {
359 sbfm(Rd, Rn, 0, 7);
360 }
361 inline void sxth(Register Rd, Register Rn) {
362 sbfm(Rd, Rn, 0, 15);
363 }
364 inline void sxtw(Register Rd, Register Rn) {
365 sbfm(Rd, Rn, 0, 31);
366 }
367
368 inline void uxtbw(Register Rd, Register Rn) {
369 ubfmw(Rd, Rn, 0, 7);
370 }
371 inline void uxthw(Register Rd, Register Rn) {
372 ubfmw(Rd, Rn, 0, 15);
373 }
374 inline void uxtb(Register Rd, Register Rn) {
375 ubfm(Rd, Rn, 0, 7);
376 }
377 inline void uxth(Register Rd, Register Rn) {
378 ubfm(Rd, Rn, 0, 15);
379 }
380 inline void uxtw(Register Rd, Register Rn) {
381 ubfm(Rd, Rn, 0, 31);
382 }
383
384 inline void cmnw(Register Rn, Register Rm) {
385 addsw(zr, Rn, Rm);
386 }
387 inline void cmn(Register Rn, Register Rm) {
388 adds(zr, Rn, Rm);
389 }
390
391 inline void cmpw(Register Rn, Register Rm) {
392 subsw(zr, Rn, Rm);
393 }
394 inline void cmp(Register Rn, Register Rm) {
395 subs(zr, Rn, Rm);
396 }
397
398 inline void negw(Register Rd, Register Rn) {
399 subw(Rd, zr, Rn);
400 }
401
402 inline void neg(Register Rd, Register Rn) {
403 sub(Rd, zr, Rn);
404 }
405
406 inline void negsw(Register Rd, Register Rn) {
407 subsw(Rd, zr, Rn);
408 }
409
410 inline void negs(Register Rd, Register Rn) {
411 subs(Rd, zr, Rn);
412 }
413
414 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
415 addsw(zr, Rn, Rm, kind, shift);
416 }
417 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
418 adds(zr, Rn, Rm, kind, shift);
419 }
420
421 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
422 subsw(zr, Rn, Rm, kind, shift);
423 }
424 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
425 subs(zr, Rn, Rm, kind, shift);
426 }
427
428 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
429 subw(Rd, zr, Rn, kind, shift);
430 }
431
432 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
433 sub(Rd, zr, Rn, kind, shift);
434 }
435
436 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
437 subsw(Rd, zr, Rn, kind, shift);
438 }
439
440 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
441 subs(Rd, zr, Rn, kind, shift);
442 }
443
444 inline void mnegw(Register Rd, Register Rn, Register Rm) {
445 msubw(Rd, Rn, Rm, zr);
446 }
447 inline void mneg(Register Rd, Register Rn, Register Rm) {
448 msub(Rd, Rn, Rm, zr);
449 }
450
451 inline void mulw(Register Rd, Register Rn, Register Rm) {
452 maddw(Rd, Rn, Rm, zr);
453 }
454 inline void mul(Register Rd, Register Rn, Register Rm) {
455 madd(Rd, Rn, Rm, zr);
456 }
457
458 inline void smnegl(Register Rd, Register Rn, Register Rm) {
459 smsubl(Rd, Rn, Rm, zr);
460 }
461 inline void smull(Register Rd, Register Rn, Register Rm) {
462 smaddl(Rd, Rn, Rm, zr);
463 }
464
465 inline void umnegl(Register Rd, Register Rn, Register Rm) {
466 umsubl(Rd, Rn, Rm, zr);
467 }
468 inline void umull(Register Rd, Register Rn, Register Rm) {
469 umaddl(Rd, Rn, Rm, zr);
470 }
471
472 #define WRAP(INSN) \
473 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
474 if (VM_Version::supports_a53mac() && Ra != zr) \
475 nop(); \
476 Assembler::INSN(Rd, Rn, Rm, Ra); \
477 }
478
479 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
480 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
481 #undef WRAP
482
483
484 // macro assembly operations needed for aarch64
485
486 public:
487
488 enum FpPushPopMode {
489 PushPopFull,
490 PushPopSVE,
491 PushPopNeon,
492 PushPopFp
493 };
494
495 // first two private routines for loading 32 bit or 64 bit constants
496 private:
497
498 void mov_immediate64(Register dst, uint64_t imm64);
499 void mov_immediate32(Register dst, uint32_t imm32);
500
501 int push(unsigned int bitset, Register stack);
502 int pop(unsigned int bitset, Register stack);
503
504 int push_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
505 int pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
506
507 int push_p(unsigned int bitset, Register stack);
508 int pop_p(unsigned int bitset, Register stack);
509
510 void mov(Register dst, Address a);
511
512 public:
513
514 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
515 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
516
517 void push_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) push_fp(regs.bits(), stack, mode); }
518 void pop_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) pop_fp(regs.bits(), stack, mode); }
519
520 static RegSet call_clobbered_gp_registers();
521
522 void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
523 void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
524
525 // Push and pop everything that might be clobbered by a native
526 // runtime call except rscratch1 and rscratch2. (They are always
527 // scratch, so we don't have to protect them.) Only save the lower
528 // 64 bits of each vector register. Additional registers can be excluded
529 // in a passed RegSet.
530 void push_call_clobbered_registers_except(RegSet exclude);
531 void pop_call_clobbered_registers_except(RegSet exclude);
532
533 void push_call_clobbered_registers() {
534 push_call_clobbered_registers_except(RegSet());
535 }
536 void pop_call_clobbered_registers() {
537 pop_call_clobbered_registers_except(RegSet());
538 }
539
540
541 // now mov instructions for loading absolute addresses and 32 or
542 // 64 bit integers
543
544 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
545
546 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
547 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); }
548
549 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); }
550
551 void mov(Register dst, RegisterOrConstant src) {
552 if (src.is_register())
553 mov(dst, src.as_register());
554 else
555 mov(dst, src.as_constant());
556 }
557
558 void movptr(Register r, uintptr_t imm64);
559
560 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
561
562 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
563 orr(Vd, T, Vn, Vn);
564 }
565
566 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
567 fcvtsh(tmp, src);
568 smov(dst, tmp, H, 0);
569 }
570
571 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
572 mov(tmp, H, 0, src);
573 fcvths(dst, tmp);
574 }
575
576 // Generalized Test Bit And Branch, including a "far" variety which
577 // spans more than 32KiB.
578 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
579 assert(cond == EQ || cond == NE, "must be");
580
581 if (isfar)
582 cond = ~cond;
583
584 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
585 if (cond == Assembler::EQ)
586 branch = &Assembler::tbz;
587 else
588 branch = &Assembler::tbnz;
589
590 if (isfar) {
591 Label L;
592 (this->*branch)(Rt, bitpos, L);
593 b(dest);
594 bind(L);
595 } else {
596 (this->*branch)(Rt, bitpos, dest);
597 }
598 }
599
600 // macro instructions for accessing and updating floating point
601 // status register
602 //
603 // FPSR : op1 == 011
604 // CRn == 0100
605 // CRm == 0100
606 // op2 == 001
607
608 inline void get_fpsr(Register reg)
609 {
610 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
611 }
612
613 inline void set_fpsr(Register reg)
614 {
615 msr(0b011, 0b0100, 0b0100, 0b001, reg);
616 }
617
618 inline void clear_fpsr()
619 {
620 msr(0b011, 0b0100, 0b0100, 0b001, zr);
621 }
622
623 // FPCR : op1 == 011
624 // CRn == 0100
625 // CRm == 0100
626 // op2 == 000
627
628 inline void get_fpcr(Register reg) {
629 mrs(0b11, 0b0100, 0b0100, 0b000, reg);
630 }
631
632 inline void set_fpcr(Register reg) {
633 msr(0b011, 0b0100, 0b0100, 0b000, reg);
634 }
635
636 // DCZID_EL0: op1 == 011
637 // CRn == 0000
638 // CRm == 0000
639 // op2 == 111
640 inline void get_dczid_el0(Register reg)
641 {
642 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
643 }
644
645 // CTR_EL0: op1 == 011
646 // CRn == 0000
647 // CRm == 0000
648 // op2 == 001
649 inline void get_ctr_el0(Register reg)
650 {
651 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
652 }
653
654 inline void get_nzcv(Register reg) {
655 mrs(0b011, 0b0100, 0b0010, 0b000, reg);
656 }
657
658 inline void set_nzcv(Register reg) {
659 msr(0b011, 0b0100, 0b0010, 0b000, reg);
660 }
661
662 // idiv variant which deals with MINLONG as dividend and -1 as divisor
663 int corrected_idivl(Register result, Register ra, Register rb,
664 bool want_remainder, Register tmp = rscratch1);
665 int corrected_idivq(Register result, Register ra, Register rb,
666 bool want_remainder, Register tmp = rscratch1);
667
668 // Support for null-checks
669 //
670 // Generates code that causes a null OS exception if the content of reg is null.
671 // If the accessed location is M[reg + offset] and the offset is known, provide the
672 // offset. No explicit code generation is needed if the offset is within a certain
673 // range (0 <= offset <= page_size).
674
675 virtual void null_check(Register reg, int offset = -1);
676 static bool needs_explicit_null_check(intptr_t offset);
677 static bool uses_implicit_null_check(void* address);
678
679 static address target_addr_for_insn(address insn_addr, unsigned insn);
680 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
681 static address target_addr_for_insn(address insn_addr) {
682 unsigned insn = *(unsigned*)insn_addr;
683 return target_addr_for_insn(insn_addr, insn);
684 }
685 static address target_addr_for_insn_or_null(address insn_addr) {
686 unsigned insn = *(unsigned*)insn_addr;
687 return target_addr_for_insn_or_null(insn_addr, insn);
688 }
689
690 // Required platform-specific helpers for Label::patch_instructions.
691 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
692 static int pd_patch_instruction_size(address branch, address target);
693 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
694 pd_patch_instruction_size(branch, target);
695 }
696 static address pd_call_destination(address branch) {
697 return target_addr_for_insn(branch);
698 }
699 #ifndef PRODUCT
700 static void pd_print_patched_instruction(address branch);
701 #endif
702
703 static int patch_oop(address insn_addr, address o);
704 static int patch_narrow_klass(address insn_addr, narrowKlass n);
705
706 // Return whether code is emitted to a scratch blob.
707 virtual bool in_scratch_emit_size() {
708 return false;
709 }
710 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
711 static int max_trampoline_stub_size();
712 void emit_static_call_stub();
713 static int static_call_stub_size();
714
715 // The following 4 methods return the offset of the appropriate move instruction
716
717 // Support for fast byte/short loading with zero extension (depending on particular CPU)
718 int load_unsigned_byte(Register dst, Address src);
719 int load_unsigned_short(Register dst, Address src);
720
721 // Support for fast byte/short loading with sign extension (depending on particular CPU)
722 int load_signed_byte(Register dst, Address src);
723 int load_signed_short(Register dst, Address src);
724
725 int load_signed_byte32(Register dst, Address src);
726 int load_signed_short32(Register dst, Address src);
727
728 // Support for sign-extension (hi:lo = extend_sign(lo))
729 void extend_sign(Register hi, Register lo);
730
731 // Load and store values by size and signed-ness
732 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
733 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
734
735 // Support for inc/dec with optimal instruction selection depending on value
736
737 // x86_64 aliases an unqualified register/address increment and
738 // decrement to call incrementq and decrementq but also supports
739 // explicitly sized calls to incrementq/decrementq or
740 // incrementl/decrementl
741
742 // for aarch64 the proper convention would be to use
743 // increment/decrement for 64 bit operations and
744 // incrementw/decrementw for 32 bit operations. so when porting
745 // x86_64 code we can leave calls to increment/decrement as is,
746 // replace incrementq/decrementq with increment/decrement and
747 // replace incrementl/decrementl with incrementw/decrementw.
748
749 // n.b. increment/decrement calls with an Address destination will
750 // need to use a scratch register to load the value to be
751 // incremented. increment/decrement calls which add or subtract a
752 // constant value greater than 2^12 will need to use a 2nd scratch
753 // register to hold the constant. so, a register increment/decrement
754 // may trash rscratch2 and an address increment/decrement trash
755 // rscratch and rscratch2
756
757 void decrementw(Address dst, int value = 1);
758 void decrementw(Register reg, int value = 1);
759
760 void decrement(Register reg, int value = 1);
761 void decrement(Address dst, int value = 1);
762
763 void incrementw(Address dst, int value = 1);
764 void incrementw(Register reg, int value = 1);
765
766 void increment(Register reg, int value = 1);
767 void increment(Address dst, int value = 1);
768
769
770 // Alignment
771 void align(int modulus);
772 void align(int modulus, int target);
773
774 // nop
775 void post_call_nop();
776
777 // Stack frame creation/removal
778 void enter(bool strip_ret_addr = false);
779 void leave();
780
781 // ROP Protection
782 void protect_return_address();
783 void protect_return_address(Register return_reg);
784 void authenticate_return_address();
785 void authenticate_return_address(Register return_reg);
786 void strip_return_address();
787 void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
788
789 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
790 // The pointer will be loaded into the thread register.
791 void get_thread(Register thread);
792
793 // support for argument shuffling
794 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
795 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
796 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
797 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
798 void object_move(
799 OopMap* map,
800 int oop_handle_offset,
801 int framesize_in_slots,
802 VMRegPair src,
803 VMRegPair dst,
804 bool is_receiver,
805 int* receiver_offset);
806
807
808 // Support for VM calls
809 //
810 // It is imperative that all calls into the VM are handled via the call_VM macros.
811 // They make sure that the stack linkage is setup correctly. call_VM's correspond
812 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
813
814
815 void call_VM(Register oop_result,
816 address entry_point,
817 bool check_exceptions = true);
818 void call_VM(Register oop_result,
819 address entry_point,
820 Register arg_1,
821 bool check_exceptions = true);
822 void call_VM(Register oop_result,
823 address entry_point,
824 Register arg_1, Register arg_2,
825 bool check_exceptions = true);
826 void call_VM(Register oop_result,
827 address entry_point,
828 Register arg_1, Register arg_2, Register arg_3,
829 bool check_exceptions = true);
830
831 // Overloadings with last_Java_sp
832 void call_VM(Register oop_result,
833 Register last_java_sp,
834 address entry_point,
835 int number_of_arguments = 0,
836 bool check_exceptions = true);
837 void call_VM(Register oop_result,
838 Register last_java_sp,
839 address entry_point,
840 Register arg_1, bool
841 check_exceptions = true);
842 void call_VM(Register oop_result,
843 Register last_java_sp,
844 address entry_point,
845 Register arg_1, Register arg_2,
846 bool check_exceptions = true);
847 void call_VM(Register oop_result,
848 Register last_java_sp,
849 address entry_point,
850 Register arg_1, Register arg_2, Register arg_3,
851 bool check_exceptions = true);
852
853 void get_vm_result_oop(Register oop_result, Register thread);
854 void get_vm_result_metadata(Register metadata_result, Register thread);
855
856 // These always tightly bind to MacroAssembler::call_VM_base
857 // bypassing the virtual implementation
858 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
859 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
860 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
861 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
862 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
863
864 void call_VM_leaf(address entry_point,
865 int number_of_arguments = 0);
866 void call_VM_leaf(address entry_point,
867 Register arg_1);
868 void call_VM_leaf(address entry_point,
869 Register arg_1, Register arg_2);
870 void call_VM_leaf(address entry_point,
871 Register arg_1, Register arg_2, Register arg_3);
872
873 // These always tightly bind to MacroAssembler::call_VM_leaf_base
874 // bypassing the virtual implementation
875 void super_call_VM_leaf(address entry_point);
876 void super_call_VM_leaf(address entry_point, Register arg_1);
877 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
878 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
879 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
880
881 // last Java Frame (fills frame anchor)
882 void set_last_Java_frame(Register last_java_sp,
883 Register last_java_fp,
884 address last_java_pc,
885 Register scratch);
886
887 void set_last_Java_frame(Register last_java_sp,
888 Register last_java_fp,
889 Label &last_java_pc,
890 Register scratch);
891
892 void set_last_Java_frame(Register last_java_sp,
893 Register last_java_fp,
894 Register last_java_pc,
895 Register scratch);
896
897 void reset_last_Java_frame(Register thread);
898
899 // thread in the default location (rthread)
900 void reset_last_Java_frame(bool clear_fp);
901
902 // Stores
903 void store_check(Register obj); // store check for obj - register is destroyed afterwards
904 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
905
906 void resolve_jobject(Register value, Register tmp1, Register tmp2);
907 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
908
909 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
910 void c2bool(Register x);
911
912 void load_method_holder_cld(Register rresult, Register rmethod);
913 void load_method_holder(Register holder, Register method);
914
915 // oop manipulations
916 void load_narrow_klass_compact(Register dst, Register src);
917 void load_klass(Register dst, Register src);
918 void store_klass(Register dst, Register src);
919 void cmp_klass(Register obj, Register klass, Register tmp);
920 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
921
922 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
923 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
924 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
925
926 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
927 Register tmp1, Register tmp2);
928
929 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
930 Register tmp1, Register tmp2, Register tmp3);
931
932 void load_heap_oop(Register dst, Address src, Register tmp1,
933 Register tmp2, DecoratorSet decorators = 0);
934
935 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
936 Register tmp2, DecoratorSet decorators = 0);
937 void store_heap_oop(Address dst, Register val, Register tmp1,
938 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
939
940 // currently unimplemented
941 // Used for storing null. All other oop constants should be
942 // stored using routines that take a jobject.
943 void store_heap_oop_null(Address dst);
944
945 void store_klass_gap(Register dst, Register src);
946
947 // This dummy is to prevent a call to store_heap_oop from
948 // converting a zero (like null) into a Register by giving
949 // the compiler two choices it can't resolve
950
951 void store_heap_oop(Address dst, void* dummy);
952
953 void encode_heap_oop(Register d, Register s);
954 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
955 void decode_heap_oop(Register d, Register s);
956 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
957 void encode_heap_oop_not_null(Register r);
958 void decode_heap_oop_not_null(Register r);
959 void encode_heap_oop_not_null(Register dst, Register src);
960 void decode_heap_oop_not_null(Register dst, Register src);
961
962 void set_narrow_oop(Register dst, jobject obj);
963
964 void decode_klass_not_null_for_aot(Register dst, Register src);
965 void encode_klass_not_null_for_aot(Register dst, Register src);
966 void encode_klass_not_null(Register r);
967 void decode_klass_not_null(Register r);
968 void encode_klass_not_null(Register dst, Register src);
969 void decode_klass_not_null(Register dst, Register src);
970
971 void set_narrow_klass(Register dst, Klass* k);
972
973 // if heap base register is used - reinit it with the correct value
974 void reinit_heapbase();
975
976 DEBUG_ONLY(void verify_heapbase(const char* msg);)
977
978 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
979 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
980 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
981 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
982
983 void push_cont_fastpath(Register java_thread = rthread);
984 void pop_cont_fastpath(Register java_thread = rthread);
985
986 void inc_held_monitor_count(Register tmp);
987 void dec_held_monitor_count(Register tmp);
988
989 // Round up to a power of two
990 void round_to(Register reg, int modulus);
991
992 // java.lang.Math::round intrinsics
993 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
994 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
995
996 // allocation
997 void tlab_allocate(
998 Register obj, // result: pointer to object after successful allocation
999 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1000 int con_size_in_bytes, // object size in bytes if known at compile time
1001 Register t1, // temp register
1002 Register t2, // temp register
1003 Label& slow_case // continuation point if fast allocation fails
1004 );
1005 void verify_tlab();
1006
1007 // interface method calling
1008 void lookup_interface_method(Register recv_klass,
1009 Register intf_klass,
1010 RegisterOrConstant itable_index,
1011 Register method_result,
1012 Register scan_temp,
1013 Label& no_such_interface,
1014 bool return_method = true);
1015
1016 void lookup_interface_method_stub(Register recv_klass,
1017 Register holder_klass,
1018 Register resolved_klass,
1019 Register method_result,
1020 Register temp_reg,
1021 Register temp_reg2,
1022 int itable_index,
1023 Label& L_no_such_interface);
1024
1025 // virtual method calling
1026 // n.b. x86 allows RegisterOrConstant for vtable_index
1027 void lookup_virtual_method(Register recv_klass,
1028 RegisterOrConstant vtable_index,
1029 Register method_result);
1030
1031 // Test sub_klass against super_klass, with fast and slow paths.
1032
1033 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1034 // One of the three labels can be null, meaning take the fall-through.
1035 // If super_check_offset is -1, the value is loaded up from super_klass.
1036 // No registers are killed, except temp_reg.
1037 void check_klass_subtype_fast_path(Register sub_klass,
1038 Register super_klass,
1039 Register temp_reg,
1040 Label* L_success,
1041 Label* L_failure,
1042 Label* L_slow_path,
1043 Register super_check_offset = noreg);
1044
1045 // The rest of the type check; must be wired to a corresponding fast path.
1046 // It does not repeat the fast path logic, so don't use it standalone.
1047 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1048 // Updates the sub's secondary super cache as necessary.
1049 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1050 void check_klass_subtype_slow_path(Register sub_klass,
1051 Register super_klass,
1052 Register temp_reg,
1053 Register temp2_reg,
1054 Label* L_success,
1055 Label* L_failure,
1056 bool set_cond_codes = false);
1057
1058 void check_klass_subtype_slow_path_linear(Register sub_klass,
1059 Register super_klass,
1060 Register temp_reg,
1061 Register temp2_reg,
1062 Label* L_success,
1063 Label* L_failure,
1064 bool set_cond_codes = false);
1065
1066 void check_klass_subtype_slow_path_table(Register sub_klass,
1067 Register super_klass,
1068 Register temp_reg,
1069 Register temp2_reg,
1070 Register temp3_reg,
1071 Register result_reg,
1072 FloatRegister vtemp_reg,
1073 Label* L_success,
1074 Label* L_failure,
1075 bool set_cond_codes = false);
1076
1077 // If r is valid, return r.
1078 // If r is invalid, remove a register r2 from available_regs, add r2
1079 // to regs_to_push, then return r2.
1080 Register allocate_if_noreg(const Register r,
1081 RegSetIterator<Register> &available_regs,
1082 RegSet ®s_to_push);
1083
1084 // Secondary subtype checking
1085 void lookup_secondary_supers_table_var(Register sub_klass,
1086 Register r_super_klass,
1087 Register temp1,
1088 Register temp2,
1089 Register temp3,
1090 FloatRegister vtemp,
1091 Register result,
1092 Label *L_success);
1093
1094
1095 // As above, but with a constant super_klass.
1096 // The result is in Register result, not the condition codes.
1097 bool lookup_secondary_supers_table_const(Register r_sub_klass,
1098 Register r_super_klass,
1099 Register temp1,
1100 Register temp2,
1101 Register temp3,
1102 FloatRegister vtemp,
1103 Register result,
1104 u1 super_klass_slot,
1105 bool stub_is_near = false);
1106
1107 void verify_secondary_supers_table(Register r_sub_klass,
1108 Register r_super_klass,
1109 Register temp1,
1110 Register temp2,
1111 Register result);
1112
1113 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
1114 Register r_array_base,
1115 Register r_array_index,
1116 Register r_bitmap,
1117 Register temp1,
1118 Register result,
1119 bool is_stub = true);
1120
1121 // Simplified, combined version, good for typical uses.
1122 // Falls through on failure.
1123 void check_klass_subtype(Register sub_klass,
1124 Register super_klass,
1125 Register temp_reg,
1126 Label& L_success);
1127
1128 void clinit_barrier(Register klass,
1129 Register thread,
1130 Label* L_fast_path = nullptr,
1131 Label* L_slow_path = nullptr);
1132
1133 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1134
1135 void verify_sve_vector_length(Register tmp = rscratch1);
1136 void reinitialize_ptrue() {
1137 if (UseSVE > 0) {
1138 sve_ptrue(ptrue, B);
1139 }
1140 }
1141 void verify_ptrue();
1142
1143 // Debugging
1144
1145 // only if +VerifyOops
1146 void _verify_oop(Register reg, const char* s, const char* file, int line);
1147 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1148
1149 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1150 if (VerifyOops) {
1151 _verify_oop(reg, s, file, line);
1152 }
1153 }
1154 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1155 if (VerifyOops) {
1156 _verify_oop_addr(reg, s, file, line);
1157 }
1158 }
1159
1160 // TODO: verify method and klass metadata (compare against vptr?)
1161 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1162 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1163
1164 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1165 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1166 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1167 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1168 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1169
1170 // Restore cpu control state after JNI call
1171 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2);
1172
1173 // prints msg, dumps registers and stops execution
1174 void stop(const char* msg);
1175
1176 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1177
1178 void untested() { stop("untested"); }
1179
1180 void unimplemented(const char* what = "");
1181
1182 void should_not_reach_here() { stop("should not reach here"); }
1183
1184 void _assert_asm(Condition cc, const char* msg);
1185 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1186 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1187
1188 // Stack overflow checking
1189 void bang_stack_with_offset(int offset) {
1190 // stack grows down, caller passes positive offset
1191 assert(offset > 0, "must bang with negative offset");
1192 sub(rscratch2, sp, offset);
1193 str(zr, Address(rscratch2));
1194 }
1195
1196 // Writes to stack successive pages until offset reached to check for
1197 // stack overflow + shadow pages. Also, clobbers tmp
1198 void bang_stack_size(Register size, Register tmp);
1199
1200 // Check for reserved stack access in method being exited (for JIT)
1201 void reserved_stack_check();
1202
1203 // Arithmetics
1204
1205 // Clobber: rscratch1, rscratch2
1206 void addptr(const Address &dst, int32_t src);
1207
1208 // Clobber: rscratch1
1209 void cmpptr(Register src1, Address src2);
1210
1211 void cmpoop(Register obj1, Register obj2);
1212
1213 // Various forms of CAS
1214
1215 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1216 Label &succeed, Label *fail);
1217 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1218 Label &succeed, Label *fail);
1219
1220 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1221 Label &succeed, Label *fail);
1222
1223 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1224 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1225 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1226 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1227
1228 void atomic_xchg(Register prev, Register newv, Register addr);
1229 void atomic_xchgw(Register prev, Register newv, Register addr);
1230 void atomic_xchgl(Register prev, Register newv, Register addr);
1231 void atomic_xchglw(Register prev, Register newv, Register addr);
1232 void atomic_xchgal(Register prev, Register newv, Register addr);
1233 void atomic_xchgalw(Register prev, Register newv, Register addr);
1234
1235 void orptr(Address adr, RegisterOrConstant src) {
1236 ldr(rscratch1, adr);
1237 if (src.is_register())
1238 orr(rscratch1, rscratch1, src.as_register());
1239 else
1240 orr(rscratch1, rscratch1, src.as_constant());
1241 str(rscratch1, adr);
1242 }
1243
1244 // A generic CAS; success or failure is in the EQ flag.
1245 // Clobbers rscratch1
1246 void cmpxchg(Register addr, Register expected, Register new_val,
1247 enum operand_size size,
1248 bool acquire, bool release, bool weak,
1249 Register result);
1250
1251 #ifdef ASSERT
1252 // Template short-hand support to clean-up after a failed call to trampoline
1253 // call generation (see trampoline_call() below), when a set of Labels must
1254 // be reset (before returning).
1255 template<typename Label, typename... More>
1256 void reset_labels(Label &lbl, More&... more) {
1257 lbl.reset(); reset_labels(more...);
1258 }
1259 template<typename Label>
1260 void reset_labels(Label &lbl) {
1261 lbl.reset();
1262 }
1263 #endif
1264
1265 private:
1266 void compare_eq(Register rn, Register rm, enum operand_size size);
1267
1268 public:
1269 // AArch64 OpenJDK uses four different types of calls:
1270 // - direct call: bl pc_relative_offset
1271 // This is the shortest and the fastest, but the offset has the range:
1272 // +/-128MB for the release build, +/-2MB for the debug build.
1273 //
1274 // - far call: adrp reg, pc_relative_offset; add; bl reg
1275 // This is longer than a direct call. The offset has
1276 // the range +/-4GB. As the code cache size is limited to 4GB,
1277 // far calls can reach anywhere in the code cache. If a jump is
1278 // needed rather than a call, a far jump 'b reg' can be used instead.
1279 // All instructions are embedded at a call site.
1280 //
1281 // - trampoline call:
1282 // This is only available in C1/C2-generated code (nmethod). It is a combination
1283 // of a direct call, which is used if the destination of a call is in range,
1284 // and a register-indirect call. It has the advantages of reaching anywhere in
1285 // the AArch64 address space and being patchable at runtime when the generated
1286 // code is being executed by other threads.
1287 //
1288 // [Main code section]
1289 // bl trampoline
1290 // [Stub code section]
1291 // trampoline:
1292 // ldr reg, pc + 8
1293 // br reg
1294 // <64-bit destination address>
1295 //
1296 // If the destination is in range when the generated code is moved to the code
1297 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1298 // is not used.
1299 // The optimization does not remove the trampoline from the stub section.
1300 // This is necessary because the trampoline may well be redirected later when
1301 // code is patched, and the new destination may not be reachable by a simple BR
1302 // instruction.
1303 //
1304 // - indirect call: move reg, address; blr reg
1305 // This too can reach anywhere in the address space, but it cannot be
1306 // patched while code is running, so it must only be modified at a safepoint.
1307 // This form of call is most suitable for targets at fixed addresses, which
1308 // will never be patched.
1309 //
1310 // The patching we do conforms to the "Concurrent modification and
1311 // execution of instructions" section of the Arm Architectural
1312 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1313 // or SVC instructions to be modified while another thread is
1314 // executing them.
1315 //
1316 // To patch a trampoline call when the BL can't reach, we first modify
1317 // the 64-bit destination address in the trampoline, then modify the
1318 // BL to point to the trampoline, then flush the instruction cache to
1319 // broadcast the change to all executing threads. See
1320 // NativeCall::set_destination_mt_safe for the details.
1321 //
1322 // There is a benign race in that the other thread might observe the
1323 // modified BL before it observes the modified 64-bit destination
1324 // address. That does not matter because the destination method has been
1325 // invalidated, so there will be a trap at its start.
1326 // For this to work, the destination address in the trampoline is
1327 // always updated, even if we're not using the trampoline.
1328
1329 // Emit a direct call if the entry address will always be in range,
1330 // otherwise a trampoline call.
1331 // Supported entry.rspec():
1332 // - relocInfo::runtime_call_type
1333 // - relocInfo::opt_virtual_call_type
1334 // - relocInfo::static_call_type
1335 // - relocInfo::virtual_call_type
1336 //
1337 // Return: the call PC or null if CodeCache is full.
1338 // Clobbers: rscratch1
1339 address trampoline_call(Address entry);
1340
1341 static bool far_branches() {
1342 return ReservedCodeCacheSize > branch_range;
1343 }
1344
1345 // Check if branches to the non nmethod section require a far jump
1346 static bool codestub_branch_needs_far_jump() {
1347 if (AOTCodeCache::is_on_for_dump()) {
1348 // To calculate far_codestub_branch_size correctly.
1349 return true;
1350 }
1351 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1352 }
1353
1354 // Emit a direct call/jump if the entry address will always be in range,
1355 // otherwise a far call/jump.
1356 // The address must be inside the code cache.
1357 // Supported entry.rspec():
1358 // - relocInfo::external_word_type
1359 // - relocInfo::runtime_call_type
1360 // - relocInfo::none
1361 // In the case of a far call/jump, the entry address is put in the tmp register.
1362 // The tmp register is invalidated.
1363 //
1364 // Far_jump returns the amount of the emitted code.
1365 void far_call(Address entry, Register tmp = rscratch1);
1366 int far_jump(Address entry, Register tmp = rscratch1);
1367
1368 static int far_codestub_branch_size() {
1369 if (codestub_branch_needs_far_jump()) {
1370 return 3 * 4; // adrp, add, br
1371 } else {
1372 return 4;
1373 }
1374 }
1375
1376 // Emit the CompiledIC call idiom
1377 address ic_call(address entry, jint method_index = 0);
1378 static int ic_check_size();
1379 int ic_check(int end_alignment);
1380
1381 public:
1382
1383 // Data
1384
1385 void mov_metadata(Register dst, Metadata* obj);
1386 Address allocate_metadata_address(Metadata* obj);
1387 Address constant_oop_address(jobject obj);
1388
1389 void movoop(Register dst, jobject obj);
1390
1391 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1392 void kernel_crc32(Register crc, Register buf, Register len,
1393 Register table0, Register table1, Register table2, Register table3,
1394 Register tmp, Register tmp2, Register tmp3);
1395 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1396 void kernel_crc32c(Register crc, Register buf, Register len,
1397 Register table0, Register table1, Register table2, Register table3,
1398 Register tmp, Register tmp2, Register tmp3);
1399
1400 // Stack push and pop individual 64 bit registers
1401 void push(Register src);
1402 void pop(Register dst);
1403
1404 void repne_scan(Register addr, Register value, Register count,
1405 Register scratch);
1406 void repne_scanw(Register addr, Register value, Register count,
1407 Register scratch);
1408
1409 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1410 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1411
1412 // If a constant does not fit in an immediate field, generate some
1413 // number of MOV instructions and then perform the operation
1414 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1415 add_sub_imm_insn insn1,
1416 add_sub_reg_insn insn2, bool is32);
1417 // Separate vsn which sets the flags
1418 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1419 add_sub_imm_insn insn1,
1420 add_sub_reg_insn insn2, bool is32);
1421
1422 #define WRAP(INSN, is32) \
1423 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1424 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1425 } \
1426 \
1427 void INSN(Register Rd, Register Rn, Register Rm, \
1428 enum shift_kind kind, unsigned shift = 0) { \
1429 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1430 } \
1431 \
1432 void INSN(Register Rd, Register Rn, Register Rm) { \
1433 Assembler::INSN(Rd, Rn, Rm); \
1434 } \
1435 \
1436 void INSN(Register Rd, Register Rn, Register Rm, \
1437 ext::operation option, int amount = 0) { \
1438 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1439 }
1440
1441 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1442
1443 #undef WRAP
1444 #define WRAP(INSN, is32) \
1445 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1446 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1447 } \
1448 \
1449 void INSN(Register Rd, Register Rn, Register Rm, \
1450 enum shift_kind kind, unsigned shift = 0) { \
1451 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1452 } \
1453 \
1454 void INSN(Register Rd, Register Rn, Register Rm) { \
1455 Assembler::INSN(Rd, Rn, Rm); \
1456 } \
1457 \
1458 void INSN(Register Rd, Register Rn, Register Rm, \
1459 ext::operation option, int amount = 0) { \
1460 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1461 }
1462
1463 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1464
1465 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1466 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1467 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1468 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1469
1470 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1471
1472 void tableswitch(Register index, jint lowbound, jint highbound,
1473 Label &jumptable, Label &jumptable_end, int stride = 1) {
1474 adr(rscratch1, jumptable);
1475 subsw(rscratch2, index, lowbound);
1476 subsw(zr, rscratch2, highbound - lowbound);
1477 br(Assembler::HS, jumptable_end);
1478 add(rscratch1, rscratch1, rscratch2,
1479 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1480 br(rscratch1);
1481 }
1482
1483 // Form an address from base + offset in Rd. Rd may or may not
1484 // actually be used: you must use the Address that is returned. It
1485 // is up to you to ensure that the shift provided matches the size
1486 // of your data.
1487 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1488
1489 // Return true iff an address is within the 48-bit AArch64 address
1490 // space.
1491 bool is_valid_AArch64_address(address a) {
1492 return ((uint64_t)a >> 48) == 0;
1493 }
1494
1495 // Load the base of the cardtable byte map into reg.
1496 void load_byte_map_base(Register reg);
1497
1498 // Prolog generator routines to support switch between x86 code and
1499 // generated ARM code
1500
1501 // routine to generate an x86 prolog for a stub function which
1502 // bootstraps into the generated ARM code which directly follows the
1503 // stub
1504 //
1505
1506 public:
1507
1508 address read_polling_page(Register r, relocInfo::relocType rtype);
1509 void get_polling_page(Register dest, relocInfo::relocType rtype);
1510
1511 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1512 void update_byte_crc32(Register crc, Register val, Register table);
1513 void update_word_crc32(Register crc, Register v, Register tmp,
1514 Register table0, Register table1, Register table2, Register table3,
1515 bool upper = false);
1516
1517 address count_positives(Register ary1, Register len, Register result);
1518
1519 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1520 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1521
1522 // Ensure that the inline code and the stub use the same registers.
1523 #define ARRAYS_HASHCODE_REGISTERS \
1524 do { \
1525 assert(result == r0 && \
1526 ary == r1 && \
1527 cnt == r2 && \
1528 vdata0 == v3 && \
1529 vdata1 == v2 && \
1530 vdata2 == v1 && \
1531 vdata3 == v0 && \
1532 vmul0 == v4 && \
1533 vmul1 == v5 && \
1534 vmul2 == v6 && \
1535 vmul3 == v7 && \
1536 vpow == v12 && \
1537 vpowm == v13, "registers must match aarch64.ad"); \
1538 } while (0)
1539
1540 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1541
1542 void fill_words(Register base, Register cnt, Register value);
1543 address zero_words(Register base, uint64_t cnt);
1544 address zero_words(Register ptr, Register cnt);
1545 void zero_dcache_blocks(Register base, Register cnt);
1546
1547 static const int zero_words_block_size;
1548
1549 address byte_array_inflate(Register src, Register dst, Register len,
1550 FloatRegister vtmp1, FloatRegister vtmp2,
1551 FloatRegister vtmp3, Register tmp4);
1552
1553 void char_array_compress(Register src, Register dst, Register len,
1554 Register res,
1555 FloatRegister vtmp0, FloatRegister vtmp1,
1556 FloatRegister vtmp2, FloatRegister vtmp3,
1557 FloatRegister vtmp4, FloatRegister vtmp5);
1558
1559 void encode_iso_array(Register src, Register dst,
1560 Register len, Register res, bool ascii,
1561 FloatRegister vtmp0, FloatRegister vtmp1,
1562 FloatRegister vtmp2, FloatRegister vtmp3,
1563 FloatRegister vtmp4, FloatRegister vtmp5);
1564
1565 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1566 address pio2, address dsin_coef, address dcos_coef);
1567 private:
1568 // begin trigonometric functions support block
1569 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1570 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1571 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1572 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1573 // end trigonometric functions support block
1574 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1575 Register src1, Register src2);
1576 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1577 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1578 }
1579 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1580 Register y, Register y_idx, Register z,
1581 Register carry, Register product,
1582 Register idx, Register kdx);
1583 void multiply_128_x_128_loop(Register y, Register z,
1584 Register carry, Register carry2,
1585 Register idx, Register jdx,
1586 Register yz_idx1, Register yz_idx2,
1587 Register tmp, Register tmp3, Register tmp4,
1588 Register tmp7, Register product_hi);
1589 void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1590 Register len, Register tmp0, Register tmp1, Register tmp2,
1591 Register tmp3);
1592 void kernel_crc32_using_crc32(Register crc, Register buf,
1593 Register len, Register tmp0, Register tmp1, Register tmp2,
1594 Register tmp3);
1595 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1596 Register len, Register tmp0, Register tmp1, Register tmp2,
1597 Register tmp3);
1598 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1599 Register len, Register tmp0, Register tmp1, Register tmp2,
1600 Register tmp3);
1601 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1602 Register len, Register tmp0, Register tmp1, Register tmp2,
1603 size_t table_offset);
1604
1605 void ghash_modmul (FloatRegister result,
1606 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1607 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1608 FloatRegister t1, FloatRegister t2, FloatRegister t3);
1609 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1610 public:
1611 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1612 Register tmp0, Register tmp1, Register tmp2, Register tmp3,
1613 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1614 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1615 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1616 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1617 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1618 void ghash_multiply_wide(int index,
1619 FloatRegister result_lo, FloatRegister result_hi,
1620 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1621 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1622 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1623 FloatRegister p, FloatRegister z, FloatRegister t1);
1624 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1625 FloatRegister p, FloatRegister z, FloatRegister t1);
1626 void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1627 Register data, Register blocks, int unrolls);
1628
1629
1630 void aesenc_loadkeys(Register key, Register keylen);
1631 void aesecb_encrypt(Register from, Register to, Register keylen,
1632 FloatRegister data = v0, int unrolls = 1);
1633 void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1634 void aes_round(FloatRegister input, FloatRegister subkey);
1635
1636 // ChaCha20 functions support block
1637 void cc20_qr_add4(FloatRegister (&addFirst)[4],
1638 FloatRegister (&addSecond)[4]);
1639 void cc20_qr_xor4(FloatRegister (&firstElem)[4],
1640 FloatRegister (&secondElem)[4], FloatRegister (&result)[4]);
1641 void cc20_qr_lrot4(FloatRegister (&sourceReg)[4],
1642 FloatRegister (&destReg)[4], int bits, FloatRegister table);
1643 void cc20_set_qr_registers(FloatRegister (&vectorSet)[4],
1644 const FloatRegister (&stateVectors)[16], int idx1, int idx2,
1645 int idx3, int idx4);
1646
1647 // Place an ISB after code may have been modified due to a safepoint.
1648 void safepoint_isb();
1649
1650 private:
1651 // Return the effective address r + (r1 << ext) + offset.
1652 // Uses rscratch2.
1653 Address offsetted_address(Register r, Register r1, Address::extend ext,
1654 int offset, int size);
1655
1656 private:
1657 // Returns an address on the stack which is reachable with a ldr/str of size
1658 // Uses rscratch2 if the address is not directly reachable
1659 Address spill_address(int size, int offset, Register tmp=rscratch2);
1660 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1661
1662 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1663
1664 // Check whether two loads/stores can be merged into ldp/stp.
1665 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1666
1667 // Merge current load/store with previous load/store into ldp/stp.
1668 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1669
1670 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1671 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1672
1673 public:
1674 void spill(Register Rx, bool is64, int offset) {
1675 if (is64) {
1676 str(Rx, spill_address(8, offset));
1677 } else {
1678 strw(Rx, spill_address(4, offset));
1679 }
1680 }
1681 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1682 str(Vx, T, spill_address(1 << (int)T, offset));
1683 }
1684
1685 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1686 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1687 }
1688 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1689 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1690 }
1691
1692 void unspill(Register Rx, bool is64, int offset) {
1693 if (is64) {
1694 ldr(Rx, spill_address(8, offset));
1695 } else {
1696 ldrw(Rx, spill_address(4, offset));
1697 }
1698 }
1699 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1700 ldr(Vx, T, spill_address(1 << (int)T, offset));
1701 }
1702
1703 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1704 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1705 }
1706 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1707 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1708 }
1709
1710 void spill_copy128(int src_offset, int dst_offset,
1711 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1712 if (src_offset < 512 && (src_offset & 7) == 0 &&
1713 dst_offset < 512 && (dst_offset & 7) == 0) {
1714 ldp(tmp1, tmp2, Address(sp, src_offset));
1715 stp(tmp1, tmp2, Address(sp, dst_offset));
1716 } else {
1717 unspill(tmp1, true, src_offset);
1718 spill(tmp1, true, dst_offset);
1719 unspill(tmp1, true, src_offset+8);
1720 spill(tmp1, true, dst_offset+8);
1721 }
1722 }
1723 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1724 int sve_vec_reg_size_in_bytes) {
1725 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1726 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1727 spill_copy128(src_offset, dst_offset);
1728 src_offset += 16;
1729 dst_offset += 16;
1730 }
1731 }
1732 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1733 int sve_predicate_reg_size_in_bytes) {
1734 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1735 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1736 reinitialize_ptrue();
1737 }
1738 void cache_wb(Address line);
1739 void cache_wbsync(bool is_pre);
1740
1741 // Code for java.lang.Thread::onSpinWait() intrinsic.
1742 void spin_wait();
1743
1744 void lightweight_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow);
1745 void lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow);
1746
1747 private:
1748 // Check the current thread doesn't need a cross modify fence.
1749 void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1750
1751 };
1752
1753 #ifdef ASSERT
1754 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1755 #endif
1756
1757 struct tableswitch {
1758 Register _reg;
1759 int _insn_index; jint _first_key; jint _last_key;
1760 Label _after;
1761 Label _branches;
1762 };
1763
1764 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP