1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/vmreg.hpp"
31 #include "metaprogramming/enableIf.hpp"
32 #include "oops/compressedOops.hpp"
33 #include "oops/compressedKlass.hpp"
34 #include "runtime/vm_version.hpp"
35 #include "utilities/powerOfTwo.hpp"
36
37 class OopMap;
38
39 // MacroAssembler extends Assembler by frequently used macros.
40 //
41 // Instructions for which a 'better' code sequence exists depending
42 // on arguments should also go in here.
43
44 class MacroAssembler: public Assembler {
45 friend class LIR_Assembler;
46
47 public:
48 using Assembler::mov;
49 using Assembler::movi;
50
51 protected:
52
53 // Support for VM calls
54 //
55 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
56 // may customize this version by overriding it for its purposes (e.g., to save/restore
57 // additional registers when doing a VM call).
58 virtual void call_VM_leaf_base(
59 address entry_point, // the entry point
60 int number_of_arguments, // the number of arguments to pop after the call
61 Label *retaddr = nullptr
62 );
63
64 virtual void call_VM_leaf_base(
65 address entry_point, // the entry point
66 int number_of_arguments, // the number of arguments to pop after the call
67 Label &retaddr) {
68 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
69 }
70
71 // This is the base routine called by the different versions of call_VM. The interpreter
72 // may customize this version by overriding it for its purposes (e.g., to save/restore
73 // additional registers when doing a VM call).
74 //
75 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
76 // returns the register which contains the thread upon return. If a thread register has been
77 // specified, the return value will correspond to that register. If no last_java_sp is specified
78 // (noreg) than rsp will be used instead.
79 virtual void call_VM_base( // returns the register containing the thread upon return
80 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
81 Register java_thread, // the thread if computed before ; use noreg otherwise
82 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
83 address entry_point, // the entry point
84 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
85 bool check_exceptions // whether to check for pending exceptions after return
86 );
87
88 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
89
90 enum KlassDecodeMode {
91 KlassDecodeNone,
92 KlassDecodeZero,
93 KlassDecodeXor,
94 KlassDecodeMovk
95 };
96
97 // Calculate decoding mode based on given parameters, used for checking then ultimately setting.
98 static KlassDecodeMode klass_decode_mode(address base, int shift, const size_t range);
99
100 private:
101 static KlassDecodeMode _klass_decode_mode;
102
103 // Returns above setting with asserts
104 static KlassDecodeMode klass_decode_mode();
105
106 public:
107 // Checks the decode mode and returns false if not compatible with preferred decoding mode.
108 static bool check_klass_decode_mode(address base, int shift, const size_t range);
109
110 // Sets the decode mode and returns false if cannot be set.
111 static bool set_klass_decode_mode(address base, int shift, const size_t range);
112
113 public:
114 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
115
116 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
117 // The implementation is only non-empty for the InterpreterMacroAssembler,
118 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
119 virtual void check_and_handle_popframe(Register java_thread);
120 virtual void check_and_handle_earlyret(Register java_thread);
121
122 void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp = rscratch1);
123 void rt_call(address dest, Register tmp = rscratch1);
124
125 // Load Effective Address
126 void lea(Register r, const Address &a) {
127 InstructionMark im(this);
128 a.lea(this, r);
129 }
130
131 /* Sometimes we get misaligned loads and stores, usually from Unsafe
132 accesses, and these can exceed the offset range. */
133 Address legitimize_address(const Address &a, int size, Register scratch) {
134 if (a.getMode() == Address::base_plus_offset) {
135 if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
136 block_comment("legitimize_address {");
137 lea(scratch, a);
138 block_comment("} legitimize_address");
139 return Address(scratch);
140 }
141 }
142 return a;
143 }
144
145 void addmw(Address a, Register incr, Register scratch) {
146 ldrw(scratch, a);
147 addw(scratch, scratch, incr);
148 strw(scratch, a);
149 }
150
151 // Add constant to memory word
152 void addmw(Address a, int imm, Register scratch) {
153 ldrw(scratch, a);
154 if (imm > 0)
155 addw(scratch, scratch, (unsigned)imm);
156 else
157 subw(scratch, scratch, (unsigned)-imm);
158 strw(scratch, a);
159 }
160
161 void bind(Label& L) {
162 Assembler::bind(L);
163 code()->clear_last_insn();
164 code()->set_last_label(pc());
165 }
166
167 void membar(Membar_mask_bits order_constraint);
168
169 using Assembler::ldr;
170 using Assembler::str;
171 using Assembler::ldrw;
172 using Assembler::strw;
173
174 void ldr(Register Rx, const Address &adr);
175 void ldrw(Register Rw, const Address &adr);
176 void str(Register Rx, const Address &adr);
177 void strw(Register Rx, const Address &adr);
178
179 // Frame creation and destruction shared between JITs.
180 void build_frame(int framesize);
181 void remove_frame(int framesize);
182
183 virtual void _call_Unimplemented(address call_site) {
184 mov(rscratch2, call_site);
185 }
186
187 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
188 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
189 // https://reviews.llvm.org/D3311
190
191 #ifdef _WIN64
192 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
193 #else
194 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
195 #endif
196
197 // aliases defined in AARCH64 spec
198
199 template<class T>
200 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
201
202 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
203 inline void cmp(Register Rd, unsigned imm) = delete;
204
205 template<class T>
206 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
207
208 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); }
209 inline void cmn(Register Rd, unsigned imm) = delete;
210
211 void cset(Register Rd, Assembler::Condition cond) {
212 csinc(Rd, zr, zr, ~cond);
213 }
214 void csetw(Register Rd, Assembler::Condition cond) {
215 csincw(Rd, zr, zr, ~cond);
216 }
217
218 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
219 csneg(Rd, Rn, Rn, ~cond);
220 }
221 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
222 csnegw(Rd, Rn, Rn, ~cond);
223 }
224
225 inline void movw(Register Rd, Register Rn) {
226 if (Rd == sp || Rn == sp) {
227 Assembler::addw(Rd, Rn, 0U);
228 } else {
229 orrw(Rd, zr, Rn);
230 }
231 }
232 inline void mov(Register Rd, Register Rn) {
233 assert(Rd != r31_sp && Rn != r31_sp, "should be");
234 if (Rd == Rn) {
235 } else if (Rd == sp || Rn == sp) {
236 Assembler::add(Rd, Rn, 0U);
237 } else {
238 orr(Rd, zr, Rn);
239 }
240 }
241
242 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
243 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
244
245 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
246 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
247
248 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
249 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
250
251 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
252 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
253 }
254 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
255 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
256 }
257
258 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
259 bfmw(Rd, Rn, lsb, (lsb + width - 1));
260 }
261 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
262 bfm(Rd, Rn, lsb , (lsb + width - 1));
263 }
264
265 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
266 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
267 }
268 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
269 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
270 }
271
272 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
273 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
274 }
275 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
276 sbfm(Rd, Rn, lsb , (lsb + width - 1));
277 }
278
279 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
280 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
281 }
282 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
283 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
284 }
285
286 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
287 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
288 }
289 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
290 ubfm(Rd, Rn, lsb , (lsb + width - 1));
291 }
292
293 inline void asrw(Register Rd, Register Rn, unsigned imm) {
294 sbfmw(Rd, Rn, imm, 31);
295 }
296
297 inline void asr(Register Rd, Register Rn, unsigned imm) {
298 sbfm(Rd, Rn, imm, 63);
299 }
300
301 inline void lslw(Register Rd, Register Rn, unsigned imm) {
302 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
303 }
304
305 inline void lsl(Register Rd, Register Rn, unsigned imm) {
306 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
307 }
308
309 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
310 ubfmw(Rd, Rn, imm, 31);
311 }
312
313 inline void lsr(Register Rd, Register Rn, unsigned imm) {
314 ubfm(Rd, Rn, imm, 63);
315 }
316
317 inline void rorw(Register Rd, Register Rn, unsigned imm) {
318 extrw(Rd, Rn, Rn, imm);
319 }
320
321 inline void ror(Register Rd, Register Rn, unsigned imm) {
322 extr(Rd, Rn, Rn, imm);
323 }
324
325 inline void sxtbw(Register Rd, Register Rn) {
326 sbfmw(Rd, Rn, 0, 7);
327 }
328 inline void sxthw(Register Rd, Register Rn) {
329 sbfmw(Rd, Rn, 0, 15);
330 }
331 inline void sxtb(Register Rd, Register Rn) {
332 sbfm(Rd, Rn, 0, 7);
333 }
334 inline void sxth(Register Rd, Register Rn) {
335 sbfm(Rd, Rn, 0, 15);
336 }
337 inline void sxtw(Register Rd, Register Rn) {
338 sbfm(Rd, Rn, 0, 31);
339 }
340
341 inline void uxtbw(Register Rd, Register Rn) {
342 ubfmw(Rd, Rn, 0, 7);
343 }
344 inline void uxthw(Register Rd, Register Rn) {
345 ubfmw(Rd, Rn, 0, 15);
346 }
347 inline void uxtb(Register Rd, Register Rn) {
348 ubfm(Rd, Rn, 0, 7);
349 }
350 inline void uxth(Register Rd, Register Rn) {
351 ubfm(Rd, Rn, 0, 15);
352 }
353 inline void uxtw(Register Rd, Register Rn) {
354 ubfm(Rd, Rn, 0, 31);
355 }
356
357 inline void cmnw(Register Rn, Register Rm) {
358 addsw(zr, Rn, Rm);
359 }
360 inline void cmn(Register Rn, Register Rm) {
361 adds(zr, Rn, Rm);
362 }
363
364 inline void cmpw(Register Rn, Register Rm) {
365 subsw(zr, Rn, Rm);
366 }
367 inline void cmp(Register Rn, Register Rm) {
368 subs(zr, Rn, Rm);
369 }
370
371 inline void negw(Register Rd, Register Rn) {
372 subw(Rd, zr, Rn);
373 }
374
375 inline void neg(Register Rd, Register Rn) {
376 sub(Rd, zr, Rn);
377 }
378
379 inline void negsw(Register Rd, Register Rn) {
380 subsw(Rd, zr, Rn);
381 }
382
383 inline void negs(Register Rd, Register Rn) {
384 subs(Rd, zr, Rn);
385 }
386
387 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
388 addsw(zr, Rn, Rm, kind, shift);
389 }
390 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
391 adds(zr, Rn, Rm, kind, shift);
392 }
393
394 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
395 subsw(zr, Rn, Rm, kind, shift);
396 }
397 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
398 subs(zr, Rn, Rm, kind, shift);
399 }
400
401 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
402 subw(Rd, zr, Rn, kind, shift);
403 }
404
405 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
406 sub(Rd, zr, Rn, kind, shift);
407 }
408
409 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
410 subsw(Rd, zr, Rn, kind, shift);
411 }
412
413 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
414 subs(Rd, zr, Rn, kind, shift);
415 }
416
417 inline void mnegw(Register Rd, Register Rn, Register Rm) {
418 msubw(Rd, Rn, Rm, zr);
419 }
420 inline void mneg(Register Rd, Register Rn, Register Rm) {
421 msub(Rd, Rn, Rm, zr);
422 }
423
424 inline void mulw(Register Rd, Register Rn, Register Rm) {
425 maddw(Rd, Rn, Rm, zr);
426 }
427 inline void mul(Register Rd, Register Rn, Register Rm) {
428 madd(Rd, Rn, Rm, zr);
429 }
430
431 inline void smnegl(Register Rd, Register Rn, Register Rm) {
432 smsubl(Rd, Rn, Rm, zr);
433 }
434 inline void smull(Register Rd, Register Rn, Register Rm) {
435 smaddl(Rd, Rn, Rm, zr);
436 }
437
438 inline void umnegl(Register Rd, Register Rn, Register Rm) {
439 umsubl(Rd, Rn, Rm, zr);
440 }
441 inline void umull(Register Rd, Register Rn, Register Rm) {
442 umaddl(Rd, Rn, Rm, zr);
443 }
444
445 #define WRAP(INSN) \
446 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
447 if (VM_Version::supports_a53mac() && Ra != zr) \
448 nop(); \
449 Assembler::INSN(Rd, Rn, Rm, Ra); \
450 }
451
452 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
453 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
454 #undef WRAP
455
456
457 // macro assembly operations needed for aarch64
458
459 public:
460
461 enum FpPushPopMode {
462 PushPopFull,
463 PushPopSVE,
464 PushPopNeon,
465 PushPopFp
466 };
467
468 // first two private routines for loading 32 bit or 64 bit constants
469 private:
470
471 void mov_immediate64(Register dst, uint64_t imm64);
472 void mov_immediate32(Register dst, uint32_t imm32);
473
474 int push(unsigned int bitset, Register stack);
475 int pop(unsigned int bitset, Register stack);
476
477 int push_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
478 int pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
479
480 int push_p(unsigned int bitset, Register stack);
481 int pop_p(unsigned int bitset, Register stack);
482
483 void mov(Register dst, Address a);
484
485 public:
486
487 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
488 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
489
490 void push_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) push_fp(regs.bits(), stack, mode); }
491 void pop_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) pop_fp(regs.bits(), stack, mode); }
492
493 static RegSet call_clobbered_gp_registers();
494
495 void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
496 void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
497
498 // Push and pop everything that might be clobbered by a native
499 // runtime call except rscratch1 and rscratch2. (They are always
500 // scratch, so we don't have to protect them.) Only save the lower
501 // 64 bits of each vector register. Additional registers can be excluded
502 // in a passed RegSet.
503 void push_call_clobbered_registers_except(RegSet exclude);
504 void pop_call_clobbered_registers_except(RegSet exclude);
505
506 void push_call_clobbered_registers() {
507 push_call_clobbered_registers_except(RegSet());
508 }
509 void pop_call_clobbered_registers() {
510 pop_call_clobbered_registers_except(RegSet());
511 }
512
513
514 // now mov instructions for loading absolute addresses and 32 or
515 // 64 bit integers
516
517 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
518
519 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
520 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); }
521
522 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); }
523
524 void mov(Register dst, RegisterOrConstant src) {
525 if (src.is_register())
526 mov(dst, src.as_register());
527 else
528 mov(dst, src.as_constant());
529 }
530
531 void movptr(Register r, uintptr_t imm64);
532
533 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
534
535 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
536 orr(Vd, T, Vn, Vn);
537 }
538
539 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
540 fcvtsh(tmp, src);
541 smov(dst, tmp, H, 0);
542 }
543
544 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
545 mov(tmp, H, 0, src);
546 fcvths(dst, tmp);
547 }
548
549 // Generalized Test Bit And Branch, including a "far" variety which
550 // spans more than 32KiB.
551 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
552 assert(cond == EQ || cond == NE, "must be");
553
554 if (isfar)
555 cond = ~cond;
556
557 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
558 if (cond == Assembler::EQ)
559 branch = &Assembler::tbz;
560 else
561 branch = &Assembler::tbnz;
562
563 if (isfar) {
564 Label L;
565 (this->*branch)(Rt, bitpos, L);
566 b(dest);
567 bind(L);
568 } else {
569 (this->*branch)(Rt, bitpos, dest);
570 }
571 }
572
573 // macro instructions for accessing and updating floating point
574 // status register
575 //
576 // FPSR : op1 == 011
577 // CRn == 0100
578 // CRm == 0100
579 // op2 == 001
580
581 inline void get_fpsr(Register reg)
582 {
583 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
584 }
585
586 inline void set_fpsr(Register reg)
587 {
588 msr(0b011, 0b0100, 0b0100, 0b001, reg);
589 }
590
591 inline void clear_fpsr()
592 {
593 msr(0b011, 0b0100, 0b0100, 0b001, zr);
594 }
595
596 // FPCR : op1 == 011
597 // CRn == 0100
598 // CRm == 0100
599 // op2 == 000
600
601 inline void get_fpcr(Register reg) {
602 mrs(0b11, 0b0100, 0b0100, 0b000, reg);
603 }
604
605 inline void set_fpcr(Register reg) {
606 msr(0b011, 0b0100, 0b0100, 0b000, reg);
607 }
608
609 // DCZID_EL0: op1 == 011
610 // CRn == 0000
611 // CRm == 0000
612 // op2 == 111
613 inline void get_dczid_el0(Register reg)
614 {
615 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
616 }
617
618 // CTR_EL0: op1 == 011
619 // CRn == 0000
620 // CRm == 0000
621 // op2 == 001
622 inline void get_ctr_el0(Register reg)
623 {
624 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
625 }
626
627 inline void get_nzcv(Register reg) {
628 mrs(0b011, 0b0100, 0b0010, 0b000, reg);
629 }
630
631 inline void set_nzcv(Register reg) {
632 msr(0b011, 0b0100, 0b0010, 0b000, reg);
633 }
634
635 // idiv variant which deals with MINLONG as dividend and -1 as divisor
636 int corrected_idivl(Register result, Register ra, Register rb,
637 bool want_remainder, Register tmp = rscratch1);
638 int corrected_idivq(Register result, Register ra, Register rb,
639 bool want_remainder, Register tmp = rscratch1);
640
641 // Support for null-checks
642 //
643 // Generates code that causes a null OS exception if the content of reg is null.
644 // If the accessed location is M[reg + offset] and the offset is known, provide the
645 // offset. No explicit code generation is needed if the offset is within a certain
646 // range (0 <= offset <= page_size).
647
648 virtual void null_check(Register reg, int offset = -1);
649 static bool needs_explicit_null_check(intptr_t offset);
650 static bool uses_implicit_null_check(void* address);
651
652 static address target_addr_for_insn(address insn_addr, unsigned insn);
653 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
654 static address target_addr_for_insn(address insn_addr) {
655 unsigned insn = *(unsigned*)insn_addr;
656 return target_addr_for_insn(insn_addr, insn);
657 }
658 static address target_addr_for_insn_or_null(address insn_addr) {
659 unsigned insn = *(unsigned*)insn_addr;
660 return target_addr_for_insn_or_null(insn_addr, insn);
661 }
662
663 // Required platform-specific helpers for Label::patch_instructions.
664 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
665 static int pd_patch_instruction_size(address branch, address target);
666 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
667 pd_patch_instruction_size(branch, target);
668 }
669 static address pd_call_destination(address branch) {
670 return target_addr_for_insn(branch);
671 }
672 #ifndef PRODUCT
673 static void pd_print_patched_instruction(address branch);
674 #endif
675
676 static int patch_oop(address insn_addr, address o);
677 static int patch_narrow_klass(address insn_addr, narrowKlass n);
678
679 // Return whether code is emitted to a scratch blob.
680 virtual bool in_scratch_emit_size() {
681 return false;
682 }
683 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
684 static int max_trampoline_stub_size();
685 void emit_static_call_stub();
686 static int static_call_stub_size();
687
688 // The following 4 methods return the offset of the appropriate move instruction
689
690 // Support for fast byte/short loading with zero extension (depending on particular CPU)
691 int load_unsigned_byte(Register dst, Address src);
692 int load_unsigned_short(Register dst, Address src);
693
694 // Support for fast byte/short loading with sign extension (depending on particular CPU)
695 int load_signed_byte(Register dst, Address src);
696 int load_signed_short(Register dst, Address src);
697
698 int load_signed_byte32(Register dst, Address src);
699 int load_signed_short32(Register dst, Address src);
700
701 // Support for sign-extension (hi:lo = extend_sign(lo))
702 void extend_sign(Register hi, Register lo);
703
704 // Load and store values by size and signed-ness
705 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
706 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
707
708 // Support for inc/dec with optimal instruction selection depending on value
709
710 // x86_64 aliases an unqualified register/address increment and
711 // decrement to call incrementq and decrementq but also supports
712 // explicitly sized calls to incrementq/decrementq or
713 // incrementl/decrementl
714
715 // for aarch64 the proper convention would be to use
716 // increment/decrement for 64 bit operations and
717 // incrementw/decrementw for 32 bit operations. so when porting
718 // x86_64 code we can leave calls to increment/decrement as is,
719 // replace incrementq/decrementq with increment/decrement and
720 // replace incrementl/decrementl with incrementw/decrementw.
721
722 // n.b. increment/decrement calls with an Address destination will
723 // need to use a scratch register to load the value to be
724 // incremented. increment/decrement calls which add or subtract a
725 // constant value greater than 2^12 will need to use a 2nd scratch
726 // register to hold the constant. so, a register increment/decrement
727 // may trash rscratch2 and an address increment/decrement trash
728 // rscratch and rscratch2
729
730 void decrementw(Address dst, int value = 1);
731 void decrementw(Register reg, int value = 1);
732
733 void decrement(Register reg, int value = 1);
734 void decrement(Address dst, int value = 1);
735
736 void incrementw(Address dst, int value = 1);
737 void incrementw(Register reg, int value = 1);
738
739 void increment(Register reg, int value = 1);
740 void increment(Address dst, int value = 1);
741
742
743 // Alignment
744 void align(int modulus);
745 void align(int modulus, int target);
746
747 // nop
748 void post_call_nop();
749
750 // Stack frame creation/removal
751 void enter(bool strip_ret_addr = false);
752 void leave();
753
754 // ROP Protection
755 void protect_return_address();
756 void protect_return_address(Register return_reg);
757 void authenticate_return_address();
758 void authenticate_return_address(Register return_reg);
759 void strip_return_address();
760 void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
761
762 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
763 // The pointer will be loaded into the thread register.
764 void get_thread(Register thread);
765
766 // support for argument shuffling
767 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
768 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
769 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
770 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
771 void object_move(
772 OopMap* map,
773 int oop_handle_offset,
774 int framesize_in_slots,
775 VMRegPair src,
776 VMRegPair dst,
777 bool is_receiver,
778 int* receiver_offset);
779
780
781 // Support for VM calls
782 //
783 // It is imperative that all calls into the VM are handled via the call_VM macros.
784 // They make sure that the stack linkage is setup correctly. call_VM's correspond
785 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
786
787
788 void call_VM(Register oop_result,
789 address entry_point,
790 bool check_exceptions = true);
791 void call_VM(Register oop_result,
792 address entry_point,
793 Register arg_1,
794 bool check_exceptions = true);
795 void call_VM(Register oop_result,
796 address entry_point,
797 Register arg_1, Register arg_2,
798 bool check_exceptions = true);
799 void call_VM(Register oop_result,
800 address entry_point,
801 Register arg_1, Register arg_2, Register arg_3,
802 bool check_exceptions = true);
803
804 // Overloadings with last_Java_sp
805 void call_VM(Register oop_result,
806 Register last_java_sp,
807 address entry_point,
808 int number_of_arguments = 0,
809 bool check_exceptions = true);
810 void call_VM(Register oop_result,
811 Register last_java_sp,
812 address entry_point,
813 Register arg_1, bool
814 check_exceptions = true);
815 void call_VM(Register oop_result,
816 Register last_java_sp,
817 address entry_point,
818 Register arg_1, Register arg_2,
819 bool check_exceptions = true);
820 void call_VM(Register oop_result,
821 Register last_java_sp,
822 address entry_point,
823 Register arg_1, Register arg_2, Register arg_3,
824 bool check_exceptions = true);
825
826 void get_vm_result (Register oop_result, Register thread);
827 void get_vm_result_2(Register metadata_result, Register thread);
828
829 // These always tightly bind to MacroAssembler::call_VM_base
830 // bypassing the virtual implementation
831 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
832 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
833 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
834 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
835 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
836
837 void call_VM_leaf(address entry_point,
838 int number_of_arguments = 0);
839 void call_VM_leaf(address entry_point,
840 Register arg_1);
841 void call_VM_leaf(address entry_point,
842 Register arg_1, Register arg_2);
843 void call_VM_leaf(address entry_point,
844 Register arg_1, Register arg_2, Register arg_3);
845
846 // These always tightly bind to MacroAssembler::call_VM_leaf_base
847 // bypassing the virtual implementation
848 void super_call_VM_leaf(address entry_point);
849 void super_call_VM_leaf(address entry_point, Register arg_1);
850 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
851 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
852 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
853
854 // last Java Frame (fills frame anchor)
855 void set_last_Java_frame(Register last_java_sp,
856 Register last_java_fp,
857 address last_java_pc,
858 Register scratch);
859
860 void set_last_Java_frame(Register last_java_sp,
861 Register last_java_fp,
862 Label &last_java_pc,
863 Register scratch);
864
865 void set_last_Java_frame(Register last_java_sp,
866 Register last_java_fp,
867 Register last_java_pc,
868 Register scratch);
869
870 void reset_last_Java_frame(Register thread);
871
872 // thread in the default location (rthread)
873 void reset_last_Java_frame(bool clear_fp);
874
875 // Stores
876 void store_check(Register obj); // store check for obj - register is destroyed afterwards
877 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
878
879 void resolve_jobject(Register value, Register tmp1, Register tmp2);
880 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
881
882 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
883 void c2bool(Register x);
884
885 void load_method_holder_cld(Register rresult, Register rmethod);
886 void load_method_holder(Register holder, Register method);
887
888 // oop manipulations
889 void load_narrow_klass_compact(Register dst, Register src);
890 void load_klass(Register dst, Register src);
891 void store_klass(Register dst, Register src);
892 void cmp_klass(Register obj, Register klass, Register tmp);
893 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
894
895 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
896 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
897 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
898
899 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
900 Register tmp1, Register tmp2);
901
902 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
903 Register tmp1, Register tmp2, Register tmp3);
904
905 void load_heap_oop(Register dst, Address src, Register tmp1,
906 Register tmp2, DecoratorSet decorators = 0);
907
908 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
909 Register tmp2, DecoratorSet decorators = 0);
910 void store_heap_oop(Address dst, Register val, Register tmp1,
911 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
912
913 // currently unimplemented
914 // Used for storing null. All other oop constants should be
915 // stored using routines that take a jobject.
916 void store_heap_oop_null(Address dst);
917
918 void store_klass_gap(Register dst, Register src);
919
920 // This dummy is to prevent a call to store_heap_oop from
921 // converting a zero (like null) into a Register by giving
922 // the compiler two choices it can't resolve
923
924 void store_heap_oop(Address dst, void* dummy);
925
926 void encode_heap_oop(Register d, Register s);
927 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
928 void decode_heap_oop(Register d, Register s);
929 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
930 void encode_heap_oop_not_null(Register r);
931 void decode_heap_oop_not_null(Register r);
932 void encode_heap_oop_not_null(Register dst, Register src);
933 void decode_heap_oop_not_null(Register dst, Register src);
934
935 void set_narrow_oop(Register dst, jobject obj);
936
937 void encode_klass_not_null(Register r);
938 void decode_klass_not_null(Register r);
939 void encode_klass_not_null(Register dst, Register src);
940 void decode_klass_not_null(Register dst, Register src);
941
942 void set_narrow_klass(Register dst, Klass* k);
943
944 // if heap base register is used - reinit it with the correct value
945 void reinit_heapbase();
946
947 DEBUG_ONLY(void verify_heapbase(const char* msg);)
948
949 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
950 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
951 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
952 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
953
954 void push_cont_fastpath(Register java_thread = rthread);
955 void pop_cont_fastpath(Register java_thread = rthread);
956
957 void inc_held_monitor_count(Register tmp);
958 void dec_held_monitor_count(Register tmp);
959
960 // Round up to a power of two
961 void round_to(Register reg, int modulus);
962
963 // java.lang.Math::round intrinsics
964 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
965 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
966
967 // allocation
968 void tlab_allocate(
969 Register obj, // result: pointer to object after successful allocation
970 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
971 int con_size_in_bytes, // object size in bytes if known at compile time
972 Register t1, // temp register
973 Register t2, // temp register
974 Label& slow_case // continuation point if fast allocation fails
975 );
976 void verify_tlab();
977
978 // interface method calling
979 void lookup_interface_method(Register recv_klass,
980 Register intf_klass,
981 RegisterOrConstant itable_index,
982 Register method_result,
983 Register scan_temp,
984 Label& no_such_interface,
985 bool return_method = true);
986
987 void lookup_interface_method_stub(Register recv_klass,
988 Register holder_klass,
989 Register resolved_klass,
990 Register method_result,
991 Register temp_reg,
992 Register temp_reg2,
993 int itable_index,
994 Label& L_no_such_interface);
995
996 // virtual method calling
997 // n.b. x86 allows RegisterOrConstant for vtable_index
998 void lookup_virtual_method(Register recv_klass,
999 RegisterOrConstant vtable_index,
1000 Register method_result);
1001
1002 // Test sub_klass against super_klass, with fast and slow paths.
1003
1004 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1005 // One of the three labels can be null, meaning take the fall-through.
1006 // If super_check_offset is -1, the value is loaded up from super_klass.
1007 // No registers are killed, except temp_reg.
1008 void check_klass_subtype_fast_path(Register sub_klass,
1009 Register super_klass,
1010 Register temp_reg,
1011 Label* L_success,
1012 Label* L_failure,
1013 Label* L_slow_path,
1014 Register super_check_offset = noreg);
1015
1016 // The rest of the type check; must be wired to a corresponding fast path.
1017 // It does not repeat the fast path logic, so don't use it standalone.
1018 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1019 // Updates the sub's secondary super cache as necessary.
1020 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1021 void check_klass_subtype_slow_path(Register sub_klass,
1022 Register super_klass,
1023 Register temp_reg,
1024 Register temp2_reg,
1025 Label* L_success,
1026 Label* L_failure,
1027 bool set_cond_codes = false);
1028
1029 void check_klass_subtype_slow_path_linear(Register sub_klass,
1030 Register super_klass,
1031 Register temp_reg,
1032 Register temp2_reg,
1033 Label* L_success,
1034 Label* L_failure,
1035 bool set_cond_codes = false);
1036
1037 void check_klass_subtype_slow_path_table(Register sub_klass,
1038 Register super_klass,
1039 Register temp_reg,
1040 Register temp2_reg,
1041 Register temp3_reg,
1042 Register result_reg,
1043 FloatRegister vtemp_reg,
1044 Label* L_success,
1045 Label* L_failure,
1046 bool set_cond_codes = false);
1047
1048 // If r is valid, return r.
1049 // If r is invalid, remove a register r2 from available_regs, add r2
1050 // to regs_to_push, then return r2.
1051 Register allocate_if_noreg(const Register r,
1052 RegSetIterator<Register> &available_regs,
1053 RegSet ®s_to_push);
1054
1055 // Secondary subtype checking
1056 void lookup_secondary_supers_table_var(Register sub_klass,
1057 Register r_super_klass,
1058 Register temp1,
1059 Register temp2,
1060 Register temp3,
1061 FloatRegister vtemp,
1062 Register result,
1063 Label *L_success);
1064
1065
1066 // As above, but with a constant super_klass.
1067 // The result is in Register result, not the condition codes.
1068 bool lookup_secondary_supers_table_const(Register r_sub_klass,
1069 Register r_super_klass,
1070 Register temp1,
1071 Register temp2,
1072 Register temp3,
1073 FloatRegister vtemp,
1074 Register result,
1075 u1 super_klass_slot,
1076 bool stub_is_near = false);
1077
1078 void verify_secondary_supers_table(Register r_sub_klass,
1079 Register r_super_klass,
1080 Register temp1,
1081 Register temp2,
1082 Register result);
1083
1084 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
1085 Register r_array_base,
1086 Register r_array_index,
1087 Register r_bitmap,
1088 Register temp1,
1089 Register result,
1090 bool is_stub = true);
1091
1092 // Simplified, combined version, good for typical uses.
1093 // Falls through on failure.
1094 void check_klass_subtype(Register sub_klass,
1095 Register super_klass,
1096 Register temp_reg,
1097 Label& L_success);
1098
1099 void clinit_barrier(Register klass,
1100 Register thread,
1101 Label* L_fast_path = nullptr,
1102 Label* L_slow_path = nullptr);
1103
1104 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1105
1106 void verify_sve_vector_length(Register tmp = rscratch1);
1107 void reinitialize_ptrue() {
1108 if (UseSVE > 0) {
1109 sve_ptrue(ptrue, B);
1110 }
1111 }
1112 void verify_ptrue();
1113
1114 // Debugging
1115
1116 // only if +VerifyOops
1117 void _verify_oop(Register reg, const char* s, const char* file, int line);
1118 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1119
1120 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1121 if (VerifyOops) {
1122 _verify_oop(reg, s, file, line);
1123 }
1124 }
1125 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1126 if (VerifyOops) {
1127 _verify_oop_addr(reg, s, file, line);
1128 }
1129 }
1130
1131 // TODO: verify method and klass metadata (compare against vptr?)
1132 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1133 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1134
1135 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1136 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1137 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1138 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1139 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1140
1141 // Restore cpu control state after JNI call
1142 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2);
1143
1144 // prints msg, dumps registers and stops execution
1145 void stop(const char* msg);
1146
1147 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1148
1149 void untested() { stop("untested"); }
1150
1151 void unimplemented(const char* what = "");
1152
1153 void should_not_reach_here() { stop("should not reach here"); }
1154
1155 void _assert_asm(Condition cc, const char* msg);
1156 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1157 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1158
1159 // Stack overflow checking
1160 void bang_stack_with_offset(int offset) {
1161 // stack grows down, caller passes positive offset
1162 assert(offset > 0, "must bang with negative offset");
1163 sub(rscratch2, sp, offset);
1164 str(zr, Address(rscratch2));
1165 }
1166
1167 // Writes to stack successive pages until offset reached to check for
1168 // stack overflow + shadow pages. Also, clobbers tmp
1169 void bang_stack_size(Register size, Register tmp);
1170
1171 // Check for reserved stack access in method being exited (for JIT)
1172 void reserved_stack_check();
1173
1174 // Arithmetics
1175
1176 void addptr(const Address &dst, int32_t src);
1177 void cmpptr(Register src1, Address src2);
1178
1179 void cmpoop(Register obj1, Register obj2);
1180
1181 // Various forms of CAS
1182
1183 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1184 Label &succeed, Label *fail);
1185 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1186 Label &succeed, Label *fail);
1187
1188 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1189 Label &succeed, Label *fail);
1190
1191 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1192 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1193 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1194 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1195
1196 void atomic_xchg(Register prev, Register newv, Register addr);
1197 void atomic_xchgw(Register prev, Register newv, Register addr);
1198 void atomic_xchgl(Register prev, Register newv, Register addr);
1199 void atomic_xchglw(Register prev, Register newv, Register addr);
1200 void atomic_xchgal(Register prev, Register newv, Register addr);
1201 void atomic_xchgalw(Register prev, Register newv, Register addr);
1202
1203 void orptr(Address adr, RegisterOrConstant src) {
1204 ldr(rscratch1, adr);
1205 if (src.is_register())
1206 orr(rscratch1, rscratch1, src.as_register());
1207 else
1208 orr(rscratch1, rscratch1, src.as_constant());
1209 str(rscratch1, adr);
1210 }
1211
1212 // A generic CAS; success or failure is in the EQ flag.
1213 // Clobbers rscratch1
1214 void cmpxchg(Register addr, Register expected, Register new_val,
1215 enum operand_size size,
1216 bool acquire, bool release, bool weak,
1217 Register result);
1218
1219 #ifdef ASSERT
1220 // Template short-hand support to clean-up after a failed call to trampoline
1221 // call generation (see trampoline_call() below), when a set of Labels must
1222 // be reset (before returning).
1223 template<typename Label, typename... More>
1224 void reset_labels(Label &lbl, More&... more) {
1225 lbl.reset(); reset_labels(more...);
1226 }
1227 template<typename Label>
1228 void reset_labels(Label &lbl) {
1229 lbl.reset();
1230 }
1231 #endif
1232
1233 private:
1234 void compare_eq(Register rn, Register rm, enum operand_size size);
1235
1236 public:
1237 // AArch64 OpenJDK uses four different types of calls:
1238 // - direct call: bl pc_relative_offset
1239 // This is the shortest and the fastest, but the offset has the range:
1240 // +/-128MB for the release build, +/-2MB for the debug build.
1241 //
1242 // - far call: adrp reg, pc_relative_offset; add; bl reg
1243 // This is longer than a direct call. The offset has
1244 // the range +/-4GB. As the code cache size is limited to 4GB,
1245 // far calls can reach anywhere in the code cache. If a jump is
1246 // needed rather than a call, a far jump 'b reg' can be used instead.
1247 // All instructions are embedded at a call site.
1248 //
1249 // - trampoline call:
1250 // This is only available in C1/C2-generated code (nmethod). It is a combination
1251 // of a direct call, which is used if the destination of a call is in range,
1252 // and a register-indirect call. It has the advantages of reaching anywhere in
1253 // the AArch64 address space and being patchable at runtime when the generated
1254 // code is being executed by other threads.
1255 //
1256 // [Main code section]
1257 // bl trampoline
1258 // [Stub code section]
1259 // trampoline:
1260 // ldr reg, pc + 8
1261 // br reg
1262 // <64-bit destination address>
1263 //
1264 // If the destination is in range when the generated code is moved to the code
1265 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1266 // is not used.
1267 // The optimization does not remove the trampoline from the stub section.
1268 // This is necessary because the trampoline may well be redirected later when
1269 // code is patched, and the new destination may not be reachable by a simple BR
1270 // instruction.
1271 //
1272 // - indirect call: move reg, address; blr reg
1273 // This too can reach anywhere in the address space, but it cannot be
1274 // patched while code is running, so it must only be modified at a safepoint.
1275 // This form of call is most suitable for targets at fixed addresses, which
1276 // will never be patched.
1277 //
1278 // The patching we do conforms to the "Concurrent modification and
1279 // execution of instructions" section of the Arm Architectural
1280 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1281 // or SVC instructions to be modified while another thread is
1282 // executing them.
1283 //
1284 // To patch a trampoline call when the BL can't reach, we first modify
1285 // the 64-bit destination address in the trampoline, then modify the
1286 // BL to point to the trampoline, then flush the instruction cache to
1287 // broadcast the change to all executing threads. See
1288 // NativeCall::set_destination_mt_safe for the details.
1289 //
1290 // There is a benign race in that the other thread might observe the
1291 // modified BL before it observes the modified 64-bit destination
1292 // address. That does not matter because the destination method has been
1293 // invalidated, so there will be a trap at its start.
1294 // For this to work, the destination address in the trampoline is
1295 // always updated, even if we're not using the trampoline.
1296
1297 // Emit a direct call if the entry address will always be in range,
1298 // otherwise a trampoline call.
1299 // Supported entry.rspec():
1300 // - relocInfo::runtime_call_type
1301 // - relocInfo::opt_virtual_call_type
1302 // - relocInfo::static_call_type
1303 // - relocInfo::virtual_call_type
1304 //
1305 // Return: the call PC or null if CodeCache is full.
1306 // Clobbers: rscratch1
1307 address trampoline_call(Address entry);
1308
1309 static bool far_branches() {
1310 return ReservedCodeCacheSize > branch_range;
1311 }
1312
1313 // Check if branches to the non nmethod section require a far jump
1314 static bool codestub_branch_needs_far_jump() {
1315 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1316 }
1317
1318 // Emit a direct call/jump if the entry address will always be in range,
1319 // otherwise a far call/jump.
1320 // The address must be inside the code cache.
1321 // Supported entry.rspec():
1322 // - relocInfo::external_word_type
1323 // - relocInfo::runtime_call_type
1324 // - relocInfo::none
1325 // In the case of a far call/jump, the entry address is put in the tmp register.
1326 // The tmp register is invalidated.
1327 //
1328 // Far_jump returns the amount of the emitted code.
1329 void far_call(Address entry, Register tmp = rscratch1);
1330 int far_jump(Address entry, Register tmp = rscratch1);
1331
1332 static int far_codestub_branch_size() {
1333 if (codestub_branch_needs_far_jump()) {
1334 return 3 * 4; // adrp, add, br
1335 } else {
1336 return 4;
1337 }
1338 }
1339
1340 // Emit the CompiledIC call idiom
1341 address ic_call(address entry, jint method_index = 0);
1342 static int ic_check_size();
1343 int ic_check(int end_alignment);
1344
1345 public:
1346
1347 // Data
1348
1349 void mov_metadata(Register dst, Metadata* obj);
1350 Address allocate_metadata_address(Metadata* obj);
1351 Address constant_oop_address(jobject obj);
1352
1353 void movoop(Register dst, jobject obj);
1354
1355 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1356 void kernel_crc32(Register crc, Register buf, Register len,
1357 Register table0, Register table1, Register table2, Register table3,
1358 Register tmp, Register tmp2, Register tmp3);
1359 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1360 void kernel_crc32c(Register crc, Register buf, Register len,
1361 Register table0, Register table1, Register table2, Register table3,
1362 Register tmp, Register tmp2, Register tmp3);
1363
1364 // Stack push and pop individual 64 bit registers
1365 void push(Register src);
1366 void pop(Register dst);
1367
1368 void repne_scan(Register addr, Register value, Register count,
1369 Register scratch);
1370 void repne_scanw(Register addr, Register value, Register count,
1371 Register scratch);
1372
1373 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1374 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1375
1376 // If a constant does not fit in an immediate field, generate some
1377 // number of MOV instructions and then perform the operation
1378 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1379 add_sub_imm_insn insn1,
1380 add_sub_reg_insn insn2, bool is32);
1381 // Separate vsn which sets the flags
1382 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1383 add_sub_imm_insn insn1,
1384 add_sub_reg_insn insn2, bool is32);
1385
1386 #define WRAP(INSN, is32) \
1387 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1388 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1389 } \
1390 \
1391 void INSN(Register Rd, Register Rn, Register Rm, \
1392 enum shift_kind kind, unsigned shift = 0) { \
1393 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1394 } \
1395 \
1396 void INSN(Register Rd, Register Rn, Register Rm) { \
1397 Assembler::INSN(Rd, Rn, Rm); \
1398 } \
1399 \
1400 void INSN(Register Rd, Register Rn, Register Rm, \
1401 ext::operation option, int amount = 0) { \
1402 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1403 }
1404
1405 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1406
1407 #undef WRAP
1408 #define WRAP(INSN, is32) \
1409 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1410 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1411 } \
1412 \
1413 void INSN(Register Rd, Register Rn, Register Rm, \
1414 enum shift_kind kind, unsigned shift = 0) { \
1415 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1416 } \
1417 \
1418 void INSN(Register Rd, Register Rn, Register Rm) { \
1419 Assembler::INSN(Rd, Rn, Rm); \
1420 } \
1421 \
1422 void INSN(Register Rd, Register Rn, Register Rm, \
1423 ext::operation option, int amount = 0) { \
1424 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1425 }
1426
1427 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1428
1429 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1430 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1431 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1432 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1433
1434 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1435
1436 void tableswitch(Register index, jint lowbound, jint highbound,
1437 Label &jumptable, Label &jumptable_end, int stride = 1) {
1438 adr(rscratch1, jumptable);
1439 subsw(rscratch2, index, lowbound);
1440 subsw(zr, rscratch2, highbound - lowbound);
1441 br(Assembler::HS, jumptable_end);
1442 add(rscratch1, rscratch1, rscratch2,
1443 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1444 br(rscratch1);
1445 }
1446
1447 // Form an address from base + offset in Rd. Rd may or may not
1448 // actually be used: you must use the Address that is returned. It
1449 // is up to you to ensure that the shift provided matches the size
1450 // of your data.
1451 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1452
1453 // Return true iff an address is within the 48-bit AArch64 address
1454 // space.
1455 bool is_valid_AArch64_address(address a) {
1456 return ((uint64_t)a >> 48) == 0;
1457 }
1458
1459 // Load the base of the cardtable byte map into reg.
1460 void load_byte_map_base(Register reg);
1461
1462 // Prolog generator routines to support switch between x86 code and
1463 // generated ARM code
1464
1465 // routine to generate an x86 prolog for a stub function which
1466 // bootstraps into the generated ARM code which directly follows the
1467 // stub
1468 //
1469
1470 public:
1471
1472 void ldr_constant(Register dest, const Address &const_addr) {
1473 if (NearCpool) {
1474 ldr(dest, const_addr);
1475 } else {
1476 uint64_t offset;
1477 adrp(dest, InternalAddress(const_addr.target()), offset);
1478 ldr(dest, Address(dest, offset));
1479 }
1480 }
1481
1482 address read_polling_page(Register r, relocInfo::relocType rtype);
1483 void get_polling_page(Register dest, relocInfo::relocType rtype);
1484
1485 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1486 void update_byte_crc32(Register crc, Register val, Register table);
1487 void update_word_crc32(Register crc, Register v, Register tmp,
1488 Register table0, Register table1, Register table2, Register table3,
1489 bool upper = false);
1490
1491 address count_positives(Register ary1, Register len, Register result);
1492
1493 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1494 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1495
1496 // Ensure that the inline code and the stub use the same registers.
1497 #define ARRAYS_HASHCODE_REGISTERS \
1498 do { \
1499 assert(result == r0 && \
1500 ary == r1 && \
1501 cnt == r2 && \
1502 vdata0 == v3 && \
1503 vdata1 == v2 && \
1504 vdata2 == v1 && \
1505 vdata3 == v0 && \
1506 vmul0 == v4 && \
1507 vmul1 == v5 && \
1508 vmul2 == v6 && \
1509 vmul3 == v7 && \
1510 vpow == v12 && \
1511 vpowm == v13, "registers must match aarch64.ad"); \
1512 } while (0)
1513
1514 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1515
1516 void fill_words(Register base, Register cnt, Register value);
1517 address zero_words(Register base, uint64_t cnt);
1518 address zero_words(Register ptr, Register cnt);
1519 void zero_dcache_blocks(Register base, Register cnt);
1520
1521 static const int zero_words_block_size;
1522
1523 address byte_array_inflate(Register src, Register dst, Register len,
1524 FloatRegister vtmp1, FloatRegister vtmp2,
1525 FloatRegister vtmp3, Register tmp4);
1526
1527 void char_array_compress(Register src, Register dst, Register len,
1528 Register res,
1529 FloatRegister vtmp0, FloatRegister vtmp1,
1530 FloatRegister vtmp2, FloatRegister vtmp3,
1531 FloatRegister vtmp4, FloatRegister vtmp5);
1532
1533 void encode_iso_array(Register src, Register dst,
1534 Register len, Register res, bool ascii,
1535 FloatRegister vtmp0, FloatRegister vtmp1,
1536 FloatRegister vtmp2, FloatRegister vtmp3,
1537 FloatRegister vtmp4, FloatRegister vtmp5);
1538
1539 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1540 address pio2, address dsin_coef, address dcos_coef);
1541 private:
1542 // begin trigonometric functions support block
1543 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1544 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1545 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1546 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1547 // end trigonometric functions support block
1548 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1549 Register src1, Register src2);
1550 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1551 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1552 }
1553 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1554 Register y, Register y_idx, Register z,
1555 Register carry, Register product,
1556 Register idx, Register kdx);
1557 void multiply_128_x_128_loop(Register y, Register z,
1558 Register carry, Register carry2,
1559 Register idx, Register jdx,
1560 Register yz_idx1, Register yz_idx2,
1561 Register tmp, Register tmp3, Register tmp4,
1562 Register tmp7, Register product_hi);
1563 void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1564 Register len, Register tmp0, Register tmp1, Register tmp2,
1565 Register tmp3);
1566 void kernel_crc32_using_crc32(Register crc, Register buf,
1567 Register len, Register tmp0, Register tmp1, Register tmp2,
1568 Register tmp3);
1569 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1570 Register len, Register tmp0, Register tmp1, Register tmp2,
1571 Register tmp3);
1572 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1573 Register len, Register tmp0, Register tmp1, Register tmp2,
1574 Register tmp3);
1575 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1576 Register len, Register tmp0, Register tmp1, Register tmp2,
1577 size_t table_offset);
1578
1579 void ghash_modmul (FloatRegister result,
1580 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1581 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1582 FloatRegister t1, FloatRegister t2, FloatRegister t3);
1583 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1584 public:
1585 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1586 Register tmp0, Register tmp1, Register tmp2, Register tmp3,
1587 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1588 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1589 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1590 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1591 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1592 void ghash_multiply_wide(int index,
1593 FloatRegister result_lo, FloatRegister result_hi,
1594 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1595 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1596 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1597 FloatRegister p, FloatRegister z, FloatRegister t1);
1598 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1599 FloatRegister p, FloatRegister z, FloatRegister t1);
1600 void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1601 Register data, Register blocks, int unrolls);
1602
1603
1604 void aesenc_loadkeys(Register key, Register keylen);
1605 void aesecb_encrypt(Register from, Register to, Register keylen,
1606 FloatRegister data = v0, int unrolls = 1);
1607 void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1608 void aes_round(FloatRegister input, FloatRegister subkey);
1609
1610 // ChaCha20 functions support block
1611 void cc20_quarter_round(FloatRegister aVec, FloatRegister bVec,
1612 FloatRegister cVec, FloatRegister dVec, FloatRegister scratch,
1613 FloatRegister tbl);
1614 void cc20_shift_lane_org(FloatRegister bVec, FloatRegister cVec,
1615 FloatRegister dVec, bool colToDiag);
1616
1617 // Place an ISB after code may have been modified due to a safepoint.
1618 void safepoint_isb();
1619
1620 private:
1621 // Return the effective address r + (r1 << ext) + offset.
1622 // Uses rscratch2.
1623 Address offsetted_address(Register r, Register r1, Address::extend ext,
1624 int offset, int size);
1625
1626 private:
1627 // Returns an address on the stack which is reachable with a ldr/str of size
1628 // Uses rscratch2 if the address is not directly reachable
1629 Address spill_address(int size, int offset, Register tmp=rscratch2);
1630 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1631
1632 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1633
1634 // Check whether two loads/stores can be merged into ldp/stp.
1635 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1636
1637 // Merge current load/store with previous load/store into ldp/stp.
1638 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1639
1640 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1641 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1642
1643 public:
1644 void spill(Register Rx, bool is64, int offset) {
1645 if (is64) {
1646 str(Rx, spill_address(8, offset));
1647 } else {
1648 strw(Rx, spill_address(4, offset));
1649 }
1650 }
1651 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1652 str(Vx, T, spill_address(1 << (int)T, offset));
1653 }
1654
1655 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1656 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1657 }
1658 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1659 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1660 }
1661
1662 void unspill(Register Rx, bool is64, int offset) {
1663 if (is64) {
1664 ldr(Rx, spill_address(8, offset));
1665 } else {
1666 ldrw(Rx, spill_address(4, offset));
1667 }
1668 }
1669 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1670 ldr(Vx, T, spill_address(1 << (int)T, offset));
1671 }
1672
1673 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1674 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1675 }
1676 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1677 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1678 }
1679
1680 void spill_copy128(int src_offset, int dst_offset,
1681 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1682 if (src_offset < 512 && (src_offset & 7) == 0 &&
1683 dst_offset < 512 && (dst_offset & 7) == 0) {
1684 ldp(tmp1, tmp2, Address(sp, src_offset));
1685 stp(tmp1, tmp2, Address(sp, dst_offset));
1686 } else {
1687 unspill(tmp1, true, src_offset);
1688 spill(tmp1, true, dst_offset);
1689 unspill(tmp1, true, src_offset+8);
1690 spill(tmp1, true, dst_offset+8);
1691 }
1692 }
1693 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1694 int sve_vec_reg_size_in_bytes) {
1695 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1696 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1697 spill_copy128(src_offset, dst_offset);
1698 src_offset += 16;
1699 dst_offset += 16;
1700 }
1701 }
1702 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1703 int sve_predicate_reg_size_in_bytes) {
1704 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1705 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1706 reinitialize_ptrue();
1707 }
1708 void cache_wb(Address line);
1709 void cache_wbsync(bool is_pre);
1710
1711 // Code for java.lang.Thread::onSpinWait() intrinsic.
1712 void spin_wait();
1713
1714 void lightweight_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow);
1715 void lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow);
1716
1717 private:
1718 // Check the current thread doesn't need a cross modify fence.
1719 void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1720
1721 };
1722
1723 #ifdef ASSERT
1724 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1725 #endif
1726
1727 struct tableswitch {
1728 Register _reg;
1729 int _insn_index; jint _first_key; jint _last_key;
1730 Label _after;
1731 Label _branches;
1732 };
1733
1734 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP