1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/vmreg.hpp"
31 #include "metaprogramming/enableIf.hpp"
32 #include "oops/compressedOops.hpp"
33 #include "oops/compressedKlass.hpp"
34 #include "runtime/vm_version.hpp"
35 #include "utilities/powerOfTwo.hpp"
36
37 class OopMap;
38
39 // MacroAssembler extends Assembler by frequently used macros.
40 //
41 // Instructions for which a 'better' code sequence exists depending
42 // on arguments should also go in here.
43
44 class MacroAssembler: public Assembler {
45 friend class LIR_Assembler;
46
47 public:
48 using Assembler::mov;
49 using Assembler::movi;
50
51 protected:
52
53 // Support for VM calls
54 //
55 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
56 // may customize this version by overriding it for its purposes (e.g., to save/restore
57 // additional registers when doing a VM call).
58 virtual void call_VM_leaf_base(
59 address entry_point, // the entry point
60 int number_of_arguments, // the number of arguments to pop after the call
61 Label *retaddr = nullptr
62 );
63
64 virtual void call_VM_leaf_base(
65 address entry_point, // the entry point
66 int number_of_arguments, // the number of arguments to pop after the call
67 Label &retaddr) {
68 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
69 }
70
71 // This is the base routine called by the different versions of call_VM. The interpreter
72 // may customize this version by overriding it for its purposes (e.g., to save/restore
73 // additional registers when doing a VM call).
74 //
75 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
76 // returns the register which contains the thread upon return. If a thread register has been
77 // specified, the return value will correspond to that register. If no last_java_sp is specified
78 // (noreg) than rsp will be used instead.
79 virtual void call_VM_base( // returns the register containing the thread upon return
80 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
81 Register java_thread, // the thread if computed before ; use noreg otherwise
82 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
83 address entry_point, // the entry point
84 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
85 bool check_exceptions // whether to check for pending exceptions after return
86 );
87
88 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
89
90 enum KlassDecodeMode {
91 KlassDecodeNone,
92 KlassDecodeZero,
93 KlassDecodeXor,
94 KlassDecodeMovk
95 };
96
97 KlassDecodeMode klass_decode_mode();
98
99 private:
100 static KlassDecodeMode _klass_decode_mode;
101
102 public:
103 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
104
105 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
106 // The implementation is only non-empty for the InterpreterMacroAssembler,
107 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
108 virtual void check_and_handle_popframe(Register java_thread);
109 virtual void check_and_handle_earlyret(Register java_thread);
110
111 void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp = rscratch1);
112 void rt_call(address dest, Register tmp = rscratch1);
113
114 // Load Effective Address
115 void lea(Register r, const Address &a) {
116 InstructionMark im(this);
117 a.lea(this, r);
118 }
119
120 /* Sometimes we get misaligned loads and stores, usually from Unsafe
121 accesses, and these can exceed the offset range. */
122 Address legitimize_address(const Address &a, int size, Register scratch) {
123 if (a.getMode() == Address::base_plus_offset) {
124 if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
125 block_comment("legitimize_address {");
126 lea(scratch, a);
127 block_comment("} legitimize_address");
128 return Address(scratch);
129 }
130 }
131 return a;
132 }
133
134 void addmw(Address a, Register incr, Register scratch) {
135 ldrw(scratch, a);
136 addw(scratch, scratch, incr);
137 strw(scratch, a);
138 }
139
140 // Add constant to memory word
141 void addmw(Address a, int imm, Register scratch) {
142 ldrw(scratch, a);
143 if (imm > 0)
144 addw(scratch, scratch, (unsigned)imm);
145 else
146 subw(scratch, scratch, (unsigned)-imm);
147 strw(scratch, a);
148 }
149
150 void bind(Label& L) {
151 Assembler::bind(L);
152 code()->clear_last_insn();
153 code()->set_last_label(pc());
154 }
155
156 void membar(Membar_mask_bits order_constraint);
157
158 using Assembler::ldr;
159 using Assembler::str;
160 using Assembler::ldrw;
161 using Assembler::strw;
162
163 void ldr(Register Rx, const Address &adr);
164 void ldrw(Register Rw, const Address &adr);
165 void str(Register Rx, const Address &adr);
166 void strw(Register Rx, const Address &adr);
167
168 // Frame creation and destruction shared between JITs.
169 void build_frame(int framesize);
170 void remove_frame(int framesize);
171
172 virtual void _call_Unimplemented(address call_site) {
173 mov(rscratch2, call_site);
174 }
175
176 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
177 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
178 // https://reviews.llvm.org/D3311
179
180 #ifdef _WIN64
181 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
182 #else
183 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
184 #endif
185
186 // aliases defined in AARCH64 spec
187
188 template<class T>
189 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
190
191 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
192 inline void cmp(Register Rd, unsigned imm) = delete;
193
194 template<class T>
195 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
196
197 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); }
198 inline void cmn(Register Rd, unsigned imm) = delete;
199
200 void cset(Register Rd, Assembler::Condition cond) {
201 csinc(Rd, zr, zr, ~cond);
202 }
203 void csetw(Register Rd, Assembler::Condition cond) {
204 csincw(Rd, zr, zr, ~cond);
205 }
206
207 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
208 csneg(Rd, Rn, Rn, ~cond);
209 }
210 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
211 csnegw(Rd, Rn, Rn, ~cond);
212 }
213
214 inline void movw(Register Rd, Register Rn) {
215 if (Rd == sp || Rn == sp) {
216 Assembler::addw(Rd, Rn, 0U);
217 } else {
218 orrw(Rd, zr, Rn);
219 }
220 }
221 inline void mov(Register Rd, Register Rn) {
222 assert(Rd != r31_sp && Rn != r31_sp, "should be");
223 if (Rd == Rn) {
224 } else if (Rd == sp || Rn == sp) {
225 Assembler::add(Rd, Rn, 0U);
226 } else {
227 orr(Rd, zr, Rn);
228 }
229 }
230
231 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
232 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
233
234 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
235 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
236
237 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
238 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
239
240 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
241 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
242 }
243 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
244 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
245 }
246
247 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
248 bfmw(Rd, Rn, lsb, (lsb + width - 1));
249 }
250 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
251 bfm(Rd, Rn, lsb , (lsb + width - 1));
252 }
253
254 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
255 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
256 }
257 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
258 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
259 }
260
261 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
262 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
263 }
264 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
265 sbfm(Rd, Rn, lsb , (lsb + width - 1));
266 }
267
268 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
269 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
270 }
271 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
272 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
273 }
274
275 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
276 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
277 }
278 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
279 ubfm(Rd, Rn, lsb , (lsb + width - 1));
280 }
281
282 inline void asrw(Register Rd, Register Rn, unsigned imm) {
283 sbfmw(Rd, Rn, imm, 31);
284 }
285
286 inline void asr(Register Rd, Register Rn, unsigned imm) {
287 sbfm(Rd, Rn, imm, 63);
288 }
289
290 inline void lslw(Register Rd, Register Rn, unsigned imm) {
291 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
292 }
293
294 inline void lsl(Register Rd, Register Rn, unsigned imm) {
295 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
296 }
297
298 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
299 ubfmw(Rd, Rn, imm, 31);
300 }
301
302 inline void lsr(Register Rd, Register Rn, unsigned imm) {
303 ubfm(Rd, Rn, imm, 63);
304 }
305
306 inline void rorw(Register Rd, Register Rn, unsigned imm) {
307 extrw(Rd, Rn, Rn, imm);
308 }
309
310 inline void ror(Register Rd, Register Rn, unsigned imm) {
311 extr(Rd, Rn, Rn, imm);
312 }
313
314 inline void sxtbw(Register Rd, Register Rn) {
315 sbfmw(Rd, Rn, 0, 7);
316 }
317 inline void sxthw(Register Rd, Register Rn) {
318 sbfmw(Rd, Rn, 0, 15);
319 }
320 inline void sxtb(Register Rd, Register Rn) {
321 sbfm(Rd, Rn, 0, 7);
322 }
323 inline void sxth(Register Rd, Register Rn) {
324 sbfm(Rd, Rn, 0, 15);
325 }
326 inline void sxtw(Register Rd, Register Rn) {
327 sbfm(Rd, Rn, 0, 31);
328 }
329
330 inline void uxtbw(Register Rd, Register Rn) {
331 ubfmw(Rd, Rn, 0, 7);
332 }
333 inline void uxthw(Register Rd, Register Rn) {
334 ubfmw(Rd, Rn, 0, 15);
335 }
336 inline void uxtb(Register Rd, Register Rn) {
337 ubfm(Rd, Rn, 0, 7);
338 }
339 inline void uxth(Register Rd, Register Rn) {
340 ubfm(Rd, Rn, 0, 15);
341 }
342 inline void uxtw(Register Rd, Register Rn) {
343 ubfm(Rd, Rn, 0, 31);
344 }
345
346 inline void cmnw(Register Rn, Register Rm) {
347 addsw(zr, Rn, Rm);
348 }
349 inline void cmn(Register Rn, Register Rm) {
350 adds(zr, Rn, Rm);
351 }
352
353 inline void cmpw(Register Rn, Register Rm) {
354 subsw(zr, Rn, Rm);
355 }
356 inline void cmp(Register Rn, Register Rm) {
357 subs(zr, Rn, Rm);
358 }
359
360 inline void negw(Register Rd, Register Rn) {
361 subw(Rd, zr, Rn);
362 }
363
364 inline void neg(Register Rd, Register Rn) {
365 sub(Rd, zr, Rn);
366 }
367
368 inline void negsw(Register Rd, Register Rn) {
369 subsw(Rd, zr, Rn);
370 }
371
372 inline void negs(Register Rd, Register Rn) {
373 subs(Rd, zr, Rn);
374 }
375
376 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
377 addsw(zr, Rn, Rm, kind, shift);
378 }
379 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
380 adds(zr, Rn, Rm, kind, shift);
381 }
382
383 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
384 subsw(zr, Rn, Rm, kind, shift);
385 }
386 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
387 subs(zr, Rn, Rm, kind, shift);
388 }
389
390 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
391 subw(Rd, zr, Rn, kind, shift);
392 }
393
394 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
395 sub(Rd, zr, Rn, kind, shift);
396 }
397
398 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
399 subsw(Rd, zr, Rn, kind, shift);
400 }
401
402 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
403 subs(Rd, zr, Rn, kind, shift);
404 }
405
406 inline void mnegw(Register Rd, Register Rn, Register Rm) {
407 msubw(Rd, Rn, Rm, zr);
408 }
409 inline void mneg(Register Rd, Register Rn, Register Rm) {
410 msub(Rd, Rn, Rm, zr);
411 }
412
413 inline void mulw(Register Rd, Register Rn, Register Rm) {
414 maddw(Rd, Rn, Rm, zr);
415 }
416 inline void mul(Register Rd, Register Rn, Register Rm) {
417 madd(Rd, Rn, Rm, zr);
418 }
419
420 inline void smnegl(Register Rd, Register Rn, Register Rm) {
421 smsubl(Rd, Rn, Rm, zr);
422 }
423 inline void smull(Register Rd, Register Rn, Register Rm) {
424 smaddl(Rd, Rn, Rm, zr);
425 }
426
427 inline void umnegl(Register Rd, Register Rn, Register Rm) {
428 umsubl(Rd, Rn, Rm, zr);
429 }
430 inline void umull(Register Rd, Register Rn, Register Rm) {
431 umaddl(Rd, Rn, Rm, zr);
432 }
433
434 #define WRAP(INSN) \
435 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
436 if (VM_Version::supports_a53mac() && Ra != zr) \
437 nop(); \
438 Assembler::INSN(Rd, Rn, Rm, Ra); \
439 }
440
441 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
442 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
443 #undef WRAP
444
445
446 // macro assembly operations needed for aarch64
447
448 public:
449
450 enum FpPushPopMode {
451 PushPopFull,
452 PushPopSVE,
453 PushPopNeon,
454 PushPopFp
455 };
456
457 // first two private routines for loading 32 bit or 64 bit constants
458 private:
459
460 void mov_immediate64(Register dst, uint64_t imm64);
461 void mov_immediate32(Register dst, uint32_t imm32);
462
463 int push(unsigned int bitset, Register stack);
464 int pop(unsigned int bitset, Register stack);
465
466 int push_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
467 int pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
468
469 int push_p(unsigned int bitset, Register stack);
470 int pop_p(unsigned int bitset, Register stack);
471
472 void mov(Register dst, Address a);
473
474 public:
475
476 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
477 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
478
479 void push_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) push_fp(regs.bits(), stack, mode); }
480 void pop_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) pop_fp(regs.bits(), stack, mode); }
481
482 static RegSet call_clobbered_gp_registers();
483
484 void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
485 void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
486
487 // Push and pop everything that might be clobbered by a native
488 // runtime call except rscratch1 and rscratch2. (They are always
489 // scratch, so we don't have to protect them.) Only save the lower
490 // 64 bits of each vector register. Additional registers can be excluded
491 // in a passed RegSet.
492 void push_call_clobbered_registers_except(RegSet exclude);
493 void pop_call_clobbered_registers_except(RegSet exclude);
494
495 void push_call_clobbered_registers() {
496 push_call_clobbered_registers_except(RegSet());
497 }
498 void pop_call_clobbered_registers() {
499 pop_call_clobbered_registers_except(RegSet());
500 }
501
502
503 // now mov instructions for loading absolute addresses and 32 or
504 // 64 bit integers
505
506 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
507
508 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
509 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); }
510
511 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); }
512
513 void mov(Register dst, RegisterOrConstant src) {
514 if (src.is_register())
515 mov(dst, src.as_register());
516 else
517 mov(dst, src.as_constant());
518 }
519
520 void movptr(Register r, uintptr_t imm64);
521
522 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
523
524 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
525 orr(Vd, T, Vn, Vn);
526 }
527
528 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
529 fcvtsh(tmp, src);
530 smov(dst, tmp, H, 0);
531 }
532
533 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
534 mov(tmp, H, 0, src);
535 fcvths(dst, tmp);
536 }
537
538 // Generalized Test Bit And Branch, including a "far" variety which
539 // spans more than 32KiB.
540 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
541 assert(cond == EQ || cond == NE, "must be");
542
543 if (isfar)
544 cond = ~cond;
545
546 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
547 if (cond == Assembler::EQ)
548 branch = &Assembler::tbz;
549 else
550 branch = &Assembler::tbnz;
551
552 if (isfar) {
553 Label L;
554 (this->*branch)(Rt, bitpos, L);
555 b(dest);
556 bind(L);
557 } else {
558 (this->*branch)(Rt, bitpos, dest);
559 }
560 }
561
562 // macro instructions for accessing and updating floating point
563 // status register
564 //
565 // FPSR : op1 == 011
566 // CRn == 0100
567 // CRm == 0100
568 // op2 == 001
569
570 inline void get_fpsr(Register reg)
571 {
572 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
573 }
574
575 inline void set_fpsr(Register reg)
576 {
577 msr(0b011, 0b0100, 0b0100, 0b001, reg);
578 }
579
580 inline void clear_fpsr()
581 {
582 msr(0b011, 0b0100, 0b0100, 0b001, zr);
583 }
584
585 // FPCR : op1 == 011
586 // CRn == 0100
587 // CRm == 0100
588 // op2 == 000
589
590 inline void get_fpcr(Register reg) {
591 mrs(0b11, 0b0100, 0b0100, 0b000, reg);
592 }
593
594 inline void set_fpcr(Register reg) {
595 msr(0b011, 0b0100, 0b0100, 0b000, reg);
596 }
597
598 // DCZID_EL0: op1 == 011
599 // CRn == 0000
600 // CRm == 0000
601 // op2 == 111
602 inline void get_dczid_el0(Register reg)
603 {
604 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
605 }
606
607 // CTR_EL0: op1 == 011
608 // CRn == 0000
609 // CRm == 0000
610 // op2 == 001
611 inline void get_ctr_el0(Register reg)
612 {
613 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
614 }
615
616 inline void get_nzcv(Register reg) {
617 mrs(0b011, 0b0100, 0b0010, 0b000, reg);
618 }
619
620 inline void set_nzcv(Register reg) {
621 msr(0b011, 0b0100, 0b0010, 0b000, reg);
622 }
623
624 // idiv variant which deals with MINLONG as dividend and -1 as divisor
625 int corrected_idivl(Register result, Register ra, Register rb,
626 bool want_remainder, Register tmp = rscratch1);
627 int corrected_idivq(Register result, Register ra, Register rb,
628 bool want_remainder, Register tmp = rscratch1);
629
630 // Support for null-checks
631 //
632 // Generates code that causes a null OS exception if the content of reg is null.
633 // If the accessed location is M[reg + offset] and the offset is known, provide the
634 // offset. No explicit code generation is needed if the offset is within a certain
635 // range (0 <= offset <= page_size).
636
637 virtual void null_check(Register reg, int offset = -1);
638 static bool needs_explicit_null_check(intptr_t offset);
639 static bool uses_implicit_null_check(void* address);
640
641 static address target_addr_for_insn(address insn_addr, unsigned insn);
642 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
643 static address target_addr_for_insn(address insn_addr) {
644 unsigned insn = *(unsigned*)insn_addr;
645 return target_addr_for_insn(insn_addr, insn);
646 }
647 static address target_addr_for_insn_or_null(address insn_addr) {
648 unsigned insn = *(unsigned*)insn_addr;
649 return target_addr_for_insn_or_null(insn_addr, insn);
650 }
651
652 // Required platform-specific helpers for Label::patch_instructions.
653 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
654 static int pd_patch_instruction_size(address branch, address target);
655 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
656 pd_patch_instruction_size(branch, target);
657 }
658 static address pd_call_destination(address branch) {
659 return target_addr_for_insn(branch);
660 }
661 #ifndef PRODUCT
662 static void pd_print_patched_instruction(address branch);
663 #endif
664
665 static int patch_oop(address insn_addr, address o);
666 static int patch_narrow_klass(address insn_addr, narrowKlass n);
667
668 // Return whether code is emitted to a scratch blob.
669 virtual bool in_scratch_emit_size() {
670 return false;
671 }
672 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
673 static int max_trampoline_stub_size();
674 void emit_static_call_stub();
675 static int static_call_stub_size();
676
677 // The following 4 methods return the offset of the appropriate move instruction
678
679 // Support for fast byte/short loading with zero extension (depending on particular CPU)
680 int load_unsigned_byte(Register dst, Address src);
681 int load_unsigned_short(Register dst, Address src);
682
683 // Support for fast byte/short loading with sign extension (depending on particular CPU)
684 int load_signed_byte(Register dst, Address src);
685 int load_signed_short(Register dst, Address src);
686
687 int load_signed_byte32(Register dst, Address src);
688 int load_signed_short32(Register dst, Address src);
689
690 // Support for sign-extension (hi:lo = extend_sign(lo))
691 void extend_sign(Register hi, Register lo);
692
693 // Load and store values by size and signed-ness
694 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
695 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
696
697 // Support for inc/dec with optimal instruction selection depending on value
698
699 // x86_64 aliases an unqualified register/address increment and
700 // decrement to call incrementq and decrementq but also supports
701 // explicitly sized calls to incrementq/decrementq or
702 // incrementl/decrementl
703
704 // for aarch64 the proper convention would be to use
705 // increment/decrement for 64 bit operations and
706 // incrementw/decrementw for 32 bit operations. so when porting
707 // x86_64 code we can leave calls to increment/decrement as is,
708 // replace incrementq/decrementq with increment/decrement and
709 // replace incrementl/decrementl with incrementw/decrementw.
710
711 // n.b. increment/decrement calls with an Address destination will
712 // need to use a scratch register to load the value to be
713 // incremented. increment/decrement calls which add or subtract a
714 // constant value greater than 2^12 will need to use a 2nd scratch
715 // register to hold the constant. so, a register increment/decrement
716 // may trash rscratch2 and an address increment/decrement trash
717 // rscratch and rscratch2
718
719 void decrementw(Address dst, int value = 1);
720 void decrementw(Register reg, int value = 1);
721
722 void decrement(Register reg, int value = 1);
723 void decrement(Address dst, int value = 1);
724
725 void incrementw(Address dst, int value = 1);
726 void incrementw(Register reg, int value = 1);
727
728 void increment(Register reg, int value = 1);
729 void increment(Address dst, int value = 1);
730
731
732 // Alignment
733 void align(int modulus);
734 void align(int modulus, int target);
735
736 // nop
737 void post_call_nop();
738
739 // Stack frame creation/removal
740 void enter(bool strip_ret_addr = false);
741 void leave();
742
743 // ROP Protection
744 void protect_return_address();
745 void protect_return_address(Register return_reg);
746 void authenticate_return_address();
747 void authenticate_return_address(Register return_reg);
748 void strip_return_address();
749 void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
750
751 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
752 // The pointer will be loaded into the thread register.
753 void get_thread(Register thread);
754
755 // support for argument shuffling
756 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
757 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
758 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
759 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
760 void object_move(
761 OopMap* map,
762 int oop_handle_offset,
763 int framesize_in_slots,
764 VMRegPair src,
765 VMRegPair dst,
766 bool is_receiver,
767 int* receiver_offset);
768
769
770 // Support for VM calls
771 //
772 // It is imperative that all calls into the VM are handled via the call_VM macros.
773 // They make sure that the stack linkage is setup correctly. call_VM's correspond
774 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
775
776
777 void call_VM(Register oop_result,
778 address entry_point,
779 bool check_exceptions = true);
780 void call_VM(Register oop_result,
781 address entry_point,
782 Register arg_1,
783 bool check_exceptions = true);
784 void call_VM(Register oop_result,
785 address entry_point,
786 Register arg_1, Register arg_2,
787 bool check_exceptions = true);
788 void call_VM(Register oop_result,
789 address entry_point,
790 Register arg_1, Register arg_2, Register arg_3,
791 bool check_exceptions = true);
792
793 // Overloadings with last_Java_sp
794 void call_VM(Register oop_result,
795 Register last_java_sp,
796 address entry_point,
797 int number_of_arguments = 0,
798 bool check_exceptions = true);
799 void call_VM(Register oop_result,
800 Register last_java_sp,
801 address entry_point,
802 Register arg_1, bool
803 check_exceptions = true);
804 void call_VM(Register oop_result,
805 Register last_java_sp,
806 address entry_point,
807 Register arg_1, Register arg_2,
808 bool check_exceptions = true);
809 void call_VM(Register oop_result,
810 Register last_java_sp,
811 address entry_point,
812 Register arg_1, Register arg_2, Register arg_3,
813 bool check_exceptions = true);
814
815 void get_vm_result (Register oop_result, Register thread);
816 void get_vm_result_2(Register metadata_result, Register thread);
817
818 // These always tightly bind to MacroAssembler::call_VM_base
819 // bypassing the virtual implementation
820 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
821 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
822 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
823 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
824 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
825
826 void call_VM_leaf(address entry_point,
827 int number_of_arguments = 0);
828 void call_VM_leaf(address entry_point,
829 Register arg_1);
830 void call_VM_leaf(address entry_point,
831 Register arg_1, Register arg_2);
832 void call_VM_leaf(address entry_point,
833 Register arg_1, Register arg_2, Register arg_3);
834
835 // These always tightly bind to MacroAssembler::call_VM_leaf_base
836 // bypassing the virtual implementation
837 void super_call_VM_leaf(address entry_point);
838 void super_call_VM_leaf(address entry_point, Register arg_1);
839 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
840 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
841 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
842
843 // last Java Frame (fills frame anchor)
844 void set_last_Java_frame(Register last_java_sp,
845 Register last_java_fp,
846 address last_java_pc,
847 Register scratch);
848
849 void set_last_Java_frame(Register last_java_sp,
850 Register last_java_fp,
851 Label &last_java_pc,
852 Register scratch);
853
854 void set_last_Java_frame(Register last_java_sp,
855 Register last_java_fp,
856 Register last_java_pc,
857 Register scratch);
858
859 void reset_last_Java_frame(Register thread);
860
861 // thread in the default location (rthread)
862 void reset_last_Java_frame(bool clear_fp);
863
864 // Stores
865 void store_check(Register obj); // store check for obj - register is destroyed afterwards
866 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
867
868 void resolve_jobject(Register value, Register tmp1, Register tmp2);
869 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
870
871 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
872 void c2bool(Register x);
873
874 void load_method_holder_cld(Register rresult, Register rmethod);
875 void load_method_holder(Register holder, Register method);
876
877 // oop manipulations
878 void load_narrow_klass_compact(Register dst, Register src);
879 void load_klass(Register dst, Register src);
880 void store_klass(Register dst, Register src);
881 void cmp_klass(Register obj, Register klass, Register tmp);
882 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
883
884 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
885 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
886 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
887
888 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
889 Register tmp1, Register tmp2);
890
891 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
892 Register tmp1, Register tmp2, Register tmp3);
893
894 void load_heap_oop(Register dst, Address src, Register tmp1,
895 Register tmp2, DecoratorSet decorators = 0);
896
897 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
898 Register tmp2, DecoratorSet decorators = 0);
899 void store_heap_oop(Address dst, Register val, Register tmp1,
900 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
901
902 // currently unimplemented
903 // Used for storing null. All other oop constants should be
904 // stored using routines that take a jobject.
905 void store_heap_oop_null(Address dst);
906
907 void store_klass_gap(Register dst, Register src);
908
909 // This dummy is to prevent a call to store_heap_oop from
910 // converting a zero (like null) into a Register by giving
911 // the compiler two choices it can't resolve
912
913 void store_heap_oop(Address dst, void* dummy);
914
915 void encode_heap_oop(Register d, Register s);
916 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
917 void decode_heap_oop(Register d, Register s);
918 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
919 void encode_heap_oop_not_null(Register r);
920 void decode_heap_oop_not_null(Register r);
921 void encode_heap_oop_not_null(Register dst, Register src);
922 void decode_heap_oop_not_null(Register dst, Register src);
923
924 void set_narrow_oop(Register dst, jobject obj);
925
926 void encode_klass_not_null(Register r);
927 void decode_klass_not_null(Register r);
928 void encode_klass_not_null(Register dst, Register src);
929 void decode_klass_not_null(Register dst, Register src);
930
931 void set_narrow_klass(Register dst, Klass* k);
932
933 // if heap base register is used - reinit it with the correct value
934 void reinit_heapbase();
935
936 DEBUG_ONLY(void verify_heapbase(const char* msg);)
937
938 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
939 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
940 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
941 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
942
943 void push_cont_fastpath(Register java_thread = rthread);
944 void pop_cont_fastpath(Register java_thread = rthread);
945
946 void inc_held_monitor_count(Register tmp);
947 void dec_held_monitor_count(Register tmp);
948
949 // Round up to a power of two
950 void round_to(Register reg, int modulus);
951
952 // java.lang.Math::round intrinsics
953 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
954 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
955
956 // allocation
957 void tlab_allocate(
958 Register obj, // result: pointer to object after successful allocation
959 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
960 int con_size_in_bytes, // object size in bytes if known at compile time
961 Register t1, // temp register
962 Register t2, // temp register
963 Label& slow_case // continuation point if fast allocation fails
964 );
965 void verify_tlab();
966
967 // interface method calling
968 void lookup_interface_method(Register recv_klass,
969 Register intf_klass,
970 RegisterOrConstant itable_index,
971 Register method_result,
972 Register scan_temp,
973 Label& no_such_interface,
974 bool return_method = true);
975
976 void lookup_interface_method_stub(Register recv_klass,
977 Register holder_klass,
978 Register resolved_klass,
979 Register method_result,
980 Register temp_reg,
981 Register temp_reg2,
982 int itable_index,
983 Label& L_no_such_interface);
984
985 // virtual method calling
986 // n.b. x86 allows RegisterOrConstant for vtable_index
987 void lookup_virtual_method(Register recv_klass,
988 RegisterOrConstant vtable_index,
989 Register method_result);
990
991 // Test sub_klass against super_klass, with fast and slow paths.
992
993 // The fast path produces a tri-state answer: yes / no / maybe-slow.
994 // One of the three labels can be null, meaning take the fall-through.
995 // If super_check_offset is -1, the value is loaded up from super_klass.
996 // No registers are killed, except temp_reg.
997 void check_klass_subtype_fast_path(Register sub_klass,
998 Register super_klass,
999 Register temp_reg,
1000 Label* L_success,
1001 Label* L_failure,
1002 Label* L_slow_path,
1003 Register super_check_offset = noreg);
1004
1005 // The rest of the type check; must be wired to a corresponding fast path.
1006 // It does not repeat the fast path logic, so don't use it standalone.
1007 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1008 // Updates the sub's secondary super cache as necessary.
1009 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1010 void check_klass_subtype_slow_path(Register sub_klass,
1011 Register super_klass,
1012 Register temp_reg,
1013 Register temp2_reg,
1014 Label* L_success,
1015 Label* L_failure,
1016 bool set_cond_codes = false);
1017
1018 void check_klass_subtype_slow_path_linear(Register sub_klass,
1019 Register super_klass,
1020 Register temp_reg,
1021 Register temp2_reg,
1022 Label* L_success,
1023 Label* L_failure,
1024 bool set_cond_codes = false);
1025
1026 void check_klass_subtype_slow_path_table(Register sub_klass,
1027 Register super_klass,
1028 Register temp_reg,
1029 Register temp2_reg,
1030 Register temp3_reg,
1031 Register result_reg,
1032 FloatRegister vtemp_reg,
1033 Label* L_success,
1034 Label* L_failure,
1035 bool set_cond_codes = false);
1036
1037 // If r is valid, return r.
1038 // If r is invalid, remove a register r2 from available_regs, add r2
1039 // to regs_to_push, then return r2.
1040 Register allocate_if_noreg(const Register r,
1041 RegSetIterator<Register> &available_regs,
1042 RegSet ®s_to_push);
1043
1044 // Secondary subtype checking
1045 void lookup_secondary_supers_table_var(Register sub_klass,
1046 Register r_super_klass,
1047 Register temp1,
1048 Register temp2,
1049 Register temp3,
1050 FloatRegister vtemp,
1051 Register result,
1052 Label *L_success);
1053
1054
1055 // As above, but with a constant super_klass.
1056 // The result is in Register result, not the condition codes.
1057 bool lookup_secondary_supers_table_const(Register r_sub_klass,
1058 Register r_super_klass,
1059 Register temp1,
1060 Register temp2,
1061 Register temp3,
1062 FloatRegister vtemp,
1063 Register result,
1064 u1 super_klass_slot,
1065 bool stub_is_near = false);
1066
1067 void verify_secondary_supers_table(Register r_sub_klass,
1068 Register r_super_klass,
1069 Register temp1,
1070 Register temp2,
1071 Register result);
1072
1073 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
1074 Register r_array_base,
1075 Register r_array_index,
1076 Register r_bitmap,
1077 Register temp1,
1078 Register result,
1079 bool is_stub = true);
1080
1081 // Simplified, combined version, good for typical uses.
1082 // Falls through on failure.
1083 void check_klass_subtype(Register sub_klass,
1084 Register super_klass,
1085 Register temp_reg,
1086 Label& L_success);
1087
1088 void clinit_barrier(Register klass,
1089 Register thread,
1090 Label* L_fast_path = nullptr,
1091 Label* L_slow_path = nullptr);
1092
1093 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1094
1095 void verify_sve_vector_length(Register tmp = rscratch1);
1096 void reinitialize_ptrue() {
1097 if (UseSVE > 0) {
1098 sve_ptrue(ptrue, B);
1099 }
1100 }
1101 void verify_ptrue();
1102
1103 // Debugging
1104
1105 // only if +VerifyOops
1106 void _verify_oop(Register reg, const char* s, const char* file, int line);
1107 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1108
1109 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1110 if (VerifyOops) {
1111 _verify_oop(reg, s, file, line);
1112 }
1113 }
1114 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1115 if (VerifyOops) {
1116 _verify_oop_addr(reg, s, file, line);
1117 }
1118 }
1119
1120 // TODO: verify method and klass metadata (compare against vptr?)
1121 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1122 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1123
1124 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1125 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1126 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1127 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1128 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1129
1130 // Restore cpu control state after JNI call
1131 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2);
1132
1133 // prints msg, dumps registers and stops execution
1134 void stop(const char* msg);
1135
1136 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1137
1138 void untested() { stop("untested"); }
1139
1140 void unimplemented(const char* what = "");
1141
1142 void should_not_reach_here() { stop("should not reach here"); }
1143
1144 void _assert_asm(Condition cc, const char* msg);
1145 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1146 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1147
1148 // Stack overflow checking
1149 void bang_stack_with_offset(int offset) {
1150 // stack grows down, caller passes positive offset
1151 assert(offset > 0, "must bang with negative offset");
1152 sub(rscratch2, sp, offset);
1153 str(zr, Address(rscratch2));
1154 }
1155
1156 // Writes to stack successive pages until offset reached to check for
1157 // stack overflow + shadow pages. Also, clobbers tmp
1158 void bang_stack_size(Register size, Register tmp);
1159
1160 // Check for reserved stack access in method being exited (for JIT)
1161 void reserved_stack_check();
1162
1163 // Arithmetics
1164
1165 void addptr(const Address &dst, int32_t src);
1166 void cmpptr(Register src1, Address src2);
1167
1168 void cmpoop(Register obj1, Register obj2);
1169
1170 // Various forms of CAS
1171
1172 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1173 Label &succeed, Label *fail);
1174 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1175 Label &succeed, Label *fail);
1176
1177 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1178 Label &succeed, Label *fail);
1179
1180 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1181 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1182 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1183 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1184
1185 void atomic_xchg(Register prev, Register newv, Register addr);
1186 void atomic_xchgw(Register prev, Register newv, Register addr);
1187 void atomic_xchgl(Register prev, Register newv, Register addr);
1188 void atomic_xchglw(Register prev, Register newv, Register addr);
1189 void atomic_xchgal(Register prev, Register newv, Register addr);
1190 void atomic_xchgalw(Register prev, Register newv, Register addr);
1191
1192 void orptr(Address adr, RegisterOrConstant src) {
1193 ldr(rscratch1, adr);
1194 if (src.is_register())
1195 orr(rscratch1, rscratch1, src.as_register());
1196 else
1197 orr(rscratch1, rscratch1, src.as_constant());
1198 str(rscratch1, adr);
1199 }
1200
1201 // A generic CAS; success or failure is in the EQ flag.
1202 // Clobbers rscratch1
1203 void cmpxchg(Register addr, Register expected, Register new_val,
1204 enum operand_size size,
1205 bool acquire, bool release, bool weak,
1206 Register result);
1207
1208 #ifdef ASSERT
1209 // Template short-hand support to clean-up after a failed call to trampoline
1210 // call generation (see trampoline_call() below), when a set of Labels must
1211 // be reset (before returning).
1212 template<typename Label, typename... More>
1213 void reset_labels(Label &lbl, More&... more) {
1214 lbl.reset(); reset_labels(more...);
1215 }
1216 template<typename Label>
1217 void reset_labels(Label &lbl) {
1218 lbl.reset();
1219 }
1220 #endif
1221
1222 private:
1223 void compare_eq(Register rn, Register rm, enum operand_size size);
1224
1225 public:
1226 // AArch64 OpenJDK uses four different types of calls:
1227 // - direct call: bl pc_relative_offset
1228 // This is the shortest and the fastest, but the offset has the range:
1229 // +/-128MB for the release build, +/-2MB for the debug build.
1230 //
1231 // - far call: adrp reg, pc_relative_offset; add; bl reg
1232 // This is longer than a direct call. The offset has
1233 // the range +/-4GB. As the code cache size is limited to 4GB,
1234 // far calls can reach anywhere in the code cache. If a jump is
1235 // needed rather than a call, a far jump 'b reg' can be used instead.
1236 // All instructions are embedded at a call site.
1237 //
1238 // - trampoline call:
1239 // This is only available in C1/C2-generated code (nmethod). It is a combination
1240 // of a direct call, which is used if the destination of a call is in range,
1241 // and a register-indirect call. It has the advantages of reaching anywhere in
1242 // the AArch64 address space and being patchable at runtime when the generated
1243 // code is being executed by other threads.
1244 //
1245 // [Main code section]
1246 // bl trampoline
1247 // [Stub code section]
1248 // trampoline:
1249 // ldr reg, pc + 8
1250 // br reg
1251 // <64-bit destination address>
1252 //
1253 // If the destination is in range when the generated code is moved to the code
1254 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1255 // is not used.
1256 // The optimization does not remove the trampoline from the stub section.
1257 // This is necessary because the trampoline may well be redirected later when
1258 // code is patched, and the new destination may not be reachable by a simple BR
1259 // instruction.
1260 //
1261 // - indirect call: move reg, address; blr reg
1262 // This too can reach anywhere in the address space, but it cannot be
1263 // patched while code is running, so it must only be modified at a safepoint.
1264 // This form of call is most suitable for targets at fixed addresses, which
1265 // will never be patched.
1266 //
1267 // The patching we do conforms to the "Concurrent modification and
1268 // execution of instructions" section of the Arm Architectural
1269 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1270 // or SVC instructions to be modified while another thread is
1271 // executing them.
1272 //
1273 // To patch a trampoline call when the BL can't reach, we first modify
1274 // the 64-bit destination address in the trampoline, then modify the
1275 // BL to point to the trampoline, then flush the instruction cache to
1276 // broadcast the change to all executing threads. See
1277 // NativeCall::set_destination_mt_safe for the details.
1278 //
1279 // There is a benign race in that the other thread might observe the
1280 // modified BL before it observes the modified 64-bit destination
1281 // address. That does not matter because the destination method has been
1282 // invalidated, so there will be a trap at its start.
1283 // For this to work, the destination address in the trampoline is
1284 // always updated, even if we're not using the trampoline.
1285
1286 // Emit a direct call if the entry address will always be in range,
1287 // otherwise a trampoline call.
1288 // Supported entry.rspec():
1289 // - relocInfo::runtime_call_type
1290 // - relocInfo::opt_virtual_call_type
1291 // - relocInfo::static_call_type
1292 // - relocInfo::virtual_call_type
1293 //
1294 // Return: the call PC or null if CodeCache is full.
1295 // Clobbers: rscratch1
1296 address trampoline_call(Address entry);
1297
1298 static bool far_branches() {
1299 return ReservedCodeCacheSize > branch_range;
1300 }
1301
1302 // Check if branches to the non nmethod section require a far jump
1303 static bool codestub_branch_needs_far_jump() {
1304 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1305 }
1306
1307 // Emit a direct call/jump if the entry address will always be in range,
1308 // otherwise a far call/jump.
1309 // The address must be inside the code cache.
1310 // Supported entry.rspec():
1311 // - relocInfo::external_word_type
1312 // - relocInfo::runtime_call_type
1313 // - relocInfo::none
1314 // In the case of a far call/jump, the entry address is put in the tmp register.
1315 // The tmp register is invalidated.
1316 //
1317 // Far_jump returns the amount of the emitted code.
1318 void far_call(Address entry, Register tmp = rscratch1);
1319 int far_jump(Address entry, Register tmp = rscratch1);
1320
1321 static int far_codestub_branch_size() {
1322 if (codestub_branch_needs_far_jump()) {
1323 return 3 * 4; // adrp, add, br
1324 } else {
1325 return 4;
1326 }
1327 }
1328
1329 // Emit the CompiledIC call idiom
1330 address ic_call(address entry, jint method_index = 0);
1331 static int ic_check_size();
1332 int ic_check(int end_alignment);
1333
1334 public:
1335
1336 // Data
1337
1338 void mov_metadata(Register dst, Metadata* obj);
1339 Address allocate_metadata_address(Metadata* obj);
1340 Address constant_oop_address(jobject obj);
1341
1342 void movoop(Register dst, jobject obj);
1343
1344 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1345 void kernel_crc32(Register crc, Register buf, Register len,
1346 Register table0, Register table1, Register table2, Register table3,
1347 Register tmp, Register tmp2, Register tmp3);
1348 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1349 void kernel_crc32c(Register crc, Register buf, Register len,
1350 Register table0, Register table1, Register table2, Register table3,
1351 Register tmp, Register tmp2, Register tmp3);
1352
1353 // Stack push and pop individual 64 bit registers
1354 void push(Register src);
1355 void pop(Register dst);
1356
1357 void repne_scan(Register addr, Register value, Register count,
1358 Register scratch);
1359 void repne_scanw(Register addr, Register value, Register count,
1360 Register scratch);
1361
1362 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1363 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1364
1365 // If a constant does not fit in an immediate field, generate some
1366 // number of MOV instructions and then perform the operation
1367 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1368 add_sub_imm_insn insn1,
1369 add_sub_reg_insn insn2, bool is32);
1370 // Separate vsn which sets the flags
1371 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1372 add_sub_imm_insn insn1,
1373 add_sub_reg_insn insn2, bool is32);
1374
1375 #define WRAP(INSN, is32) \
1376 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1377 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1378 } \
1379 \
1380 void INSN(Register Rd, Register Rn, Register Rm, \
1381 enum shift_kind kind, unsigned shift = 0) { \
1382 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1383 } \
1384 \
1385 void INSN(Register Rd, Register Rn, Register Rm) { \
1386 Assembler::INSN(Rd, Rn, Rm); \
1387 } \
1388 \
1389 void INSN(Register Rd, Register Rn, Register Rm, \
1390 ext::operation option, int amount = 0) { \
1391 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1392 }
1393
1394 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1395
1396 #undef WRAP
1397 #define WRAP(INSN, is32) \
1398 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1399 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1400 } \
1401 \
1402 void INSN(Register Rd, Register Rn, Register Rm, \
1403 enum shift_kind kind, unsigned shift = 0) { \
1404 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1405 } \
1406 \
1407 void INSN(Register Rd, Register Rn, Register Rm) { \
1408 Assembler::INSN(Rd, Rn, Rm); \
1409 } \
1410 \
1411 void INSN(Register Rd, Register Rn, Register Rm, \
1412 ext::operation option, int amount = 0) { \
1413 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1414 }
1415
1416 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1417
1418 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1419 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1420 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1421 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1422
1423 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1424
1425 void tableswitch(Register index, jint lowbound, jint highbound,
1426 Label &jumptable, Label &jumptable_end, int stride = 1) {
1427 adr(rscratch1, jumptable);
1428 subsw(rscratch2, index, lowbound);
1429 subsw(zr, rscratch2, highbound - lowbound);
1430 br(Assembler::HS, jumptable_end);
1431 add(rscratch1, rscratch1, rscratch2,
1432 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1433 br(rscratch1);
1434 }
1435
1436 // Form an address from base + offset in Rd. Rd may or may not
1437 // actually be used: you must use the Address that is returned. It
1438 // is up to you to ensure that the shift provided matches the size
1439 // of your data.
1440 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1441
1442 // Return true iff an address is within the 48-bit AArch64 address
1443 // space.
1444 bool is_valid_AArch64_address(address a) {
1445 return ((uint64_t)a >> 48) == 0;
1446 }
1447
1448 // Load the base of the cardtable byte map into reg.
1449 void load_byte_map_base(Register reg);
1450
1451 // Prolog generator routines to support switch between x86 code and
1452 // generated ARM code
1453
1454 // routine to generate an x86 prolog for a stub function which
1455 // bootstraps into the generated ARM code which directly follows the
1456 // stub
1457 //
1458
1459 public:
1460
1461 void ldr_constant(Register dest, const Address &const_addr) {
1462 if (NearCpool) {
1463 ldr(dest, const_addr);
1464 } else {
1465 uint64_t offset;
1466 adrp(dest, InternalAddress(const_addr.target()), offset);
1467 ldr(dest, Address(dest, offset));
1468 }
1469 }
1470
1471 address read_polling_page(Register r, relocInfo::relocType rtype);
1472 void get_polling_page(Register dest, relocInfo::relocType rtype);
1473
1474 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1475 void update_byte_crc32(Register crc, Register val, Register table);
1476 void update_word_crc32(Register crc, Register v, Register tmp,
1477 Register table0, Register table1, Register table2, Register table3,
1478 bool upper = false);
1479
1480 address count_positives(Register ary1, Register len, Register result);
1481
1482 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1483 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1484
1485 // Ensure that the inline code and the stub use the same registers.
1486 #define ARRAYS_HASHCODE_REGISTERS \
1487 do { \
1488 assert(result == r0 && \
1489 ary == r1 && \
1490 cnt == r2 && \
1491 vdata0 == v3 && \
1492 vdata1 == v2 && \
1493 vdata2 == v1 && \
1494 vdata3 == v0 && \
1495 vmul0 == v4 && \
1496 vmul1 == v5 && \
1497 vmul2 == v6 && \
1498 vmul3 == v7 && \
1499 vpow == v12 && \
1500 vpowm == v13, "registers must match aarch64.ad"); \
1501 } while (0)
1502
1503 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1504
1505 void fill_words(Register base, Register cnt, Register value);
1506 address zero_words(Register base, uint64_t cnt);
1507 address zero_words(Register ptr, Register cnt);
1508 void zero_dcache_blocks(Register base, Register cnt);
1509
1510 static const int zero_words_block_size;
1511
1512 address byte_array_inflate(Register src, Register dst, Register len,
1513 FloatRegister vtmp1, FloatRegister vtmp2,
1514 FloatRegister vtmp3, Register tmp4);
1515
1516 void char_array_compress(Register src, Register dst, Register len,
1517 Register res,
1518 FloatRegister vtmp0, FloatRegister vtmp1,
1519 FloatRegister vtmp2, FloatRegister vtmp3,
1520 FloatRegister vtmp4, FloatRegister vtmp5);
1521
1522 void encode_iso_array(Register src, Register dst,
1523 Register len, Register res, bool ascii,
1524 FloatRegister vtmp0, FloatRegister vtmp1,
1525 FloatRegister vtmp2, FloatRegister vtmp3,
1526 FloatRegister vtmp4, FloatRegister vtmp5);
1527
1528 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1529 address pio2, address dsin_coef, address dcos_coef);
1530 private:
1531 // begin trigonometric functions support block
1532 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1533 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1534 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1535 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1536 // end trigonometric functions support block
1537 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1538 Register src1, Register src2);
1539 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1540 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1541 }
1542 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1543 Register y, Register y_idx, Register z,
1544 Register carry, Register product,
1545 Register idx, Register kdx);
1546 void multiply_128_x_128_loop(Register y, Register z,
1547 Register carry, Register carry2,
1548 Register idx, Register jdx,
1549 Register yz_idx1, Register yz_idx2,
1550 Register tmp, Register tmp3, Register tmp4,
1551 Register tmp7, Register product_hi);
1552 void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1553 Register len, Register tmp0, Register tmp1, Register tmp2,
1554 Register tmp3);
1555 void kernel_crc32_using_crc32(Register crc, Register buf,
1556 Register len, Register tmp0, Register tmp1, Register tmp2,
1557 Register tmp3);
1558 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1559 Register len, Register tmp0, Register tmp1, Register tmp2,
1560 Register tmp3);
1561 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1562 Register len, Register tmp0, Register tmp1, Register tmp2,
1563 Register tmp3);
1564 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1565 Register len, Register tmp0, Register tmp1, Register tmp2,
1566 size_t table_offset);
1567
1568 void ghash_modmul (FloatRegister result,
1569 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1570 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1571 FloatRegister t1, FloatRegister t2, FloatRegister t3);
1572 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1573 public:
1574 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1575 Register tmp0, Register tmp1, Register tmp2, Register tmp3,
1576 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1577 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1578 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1579 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1580 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1581 void ghash_multiply_wide(int index,
1582 FloatRegister result_lo, FloatRegister result_hi,
1583 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1584 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1585 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1586 FloatRegister p, FloatRegister z, FloatRegister t1);
1587 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1588 FloatRegister p, FloatRegister z, FloatRegister t1);
1589 void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1590 Register data, Register blocks, int unrolls);
1591
1592
1593 void aesenc_loadkeys(Register key, Register keylen);
1594 void aesecb_encrypt(Register from, Register to, Register keylen,
1595 FloatRegister data = v0, int unrolls = 1);
1596 void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1597 void aes_round(FloatRegister input, FloatRegister subkey);
1598
1599 // ChaCha20 functions support block
1600 void cc20_quarter_round(FloatRegister aVec, FloatRegister bVec,
1601 FloatRegister cVec, FloatRegister dVec, FloatRegister scratch,
1602 FloatRegister tbl);
1603 void cc20_shift_lane_org(FloatRegister bVec, FloatRegister cVec,
1604 FloatRegister dVec, bool colToDiag);
1605
1606 // Place an ISB after code may have been modified due to a safepoint.
1607 void safepoint_isb();
1608
1609 private:
1610 // Return the effective address r + (r1 << ext) + offset.
1611 // Uses rscratch2.
1612 Address offsetted_address(Register r, Register r1, Address::extend ext,
1613 int offset, int size);
1614
1615 private:
1616 // Returns an address on the stack which is reachable with a ldr/str of size
1617 // Uses rscratch2 if the address is not directly reachable
1618 Address spill_address(int size, int offset, Register tmp=rscratch2);
1619 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1620
1621 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1622
1623 // Check whether two loads/stores can be merged into ldp/stp.
1624 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1625
1626 // Merge current load/store with previous load/store into ldp/stp.
1627 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1628
1629 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1630 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1631
1632 public:
1633 void spill(Register Rx, bool is64, int offset) {
1634 if (is64) {
1635 str(Rx, spill_address(8, offset));
1636 } else {
1637 strw(Rx, spill_address(4, offset));
1638 }
1639 }
1640 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1641 str(Vx, T, spill_address(1 << (int)T, offset));
1642 }
1643
1644 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1645 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1646 }
1647 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1648 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1649 }
1650
1651 void unspill(Register Rx, bool is64, int offset) {
1652 if (is64) {
1653 ldr(Rx, spill_address(8, offset));
1654 } else {
1655 ldrw(Rx, spill_address(4, offset));
1656 }
1657 }
1658 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1659 ldr(Vx, T, spill_address(1 << (int)T, offset));
1660 }
1661
1662 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1663 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1664 }
1665 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1666 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1667 }
1668
1669 void spill_copy128(int src_offset, int dst_offset,
1670 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1671 if (src_offset < 512 && (src_offset & 7) == 0 &&
1672 dst_offset < 512 && (dst_offset & 7) == 0) {
1673 ldp(tmp1, tmp2, Address(sp, src_offset));
1674 stp(tmp1, tmp2, Address(sp, dst_offset));
1675 } else {
1676 unspill(tmp1, true, src_offset);
1677 spill(tmp1, true, dst_offset);
1678 unspill(tmp1, true, src_offset+8);
1679 spill(tmp1, true, dst_offset+8);
1680 }
1681 }
1682 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1683 int sve_vec_reg_size_in_bytes) {
1684 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1685 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1686 spill_copy128(src_offset, dst_offset);
1687 src_offset += 16;
1688 dst_offset += 16;
1689 }
1690 }
1691 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1692 int sve_predicate_reg_size_in_bytes) {
1693 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1694 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1695 reinitialize_ptrue();
1696 }
1697 void cache_wb(Address line);
1698 void cache_wbsync(bool is_pre);
1699
1700 // Code for java.lang.Thread::onSpinWait() intrinsic.
1701 void spin_wait();
1702
1703 void lightweight_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow);
1704 void lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow);
1705
1706 private:
1707 // Check the current thread doesn't need a cross modify fence.
1708 void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1709
1710 };
1711
1712 #ifdef ASSERT
1713 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1714 #endif
1715
1716 struct tableswitch {
1717 Register _reg;
1718 int _insn_index; jint _first_key; jint _last_key;
1719 Label _after;
1720 Label _branches;
1721 };
1722
1723 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP