1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/vmreg.hpp"
31 #include "code/SCCache.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/powerOfTwo.hpp"
37
38 class OopMap;
39
40 // MacroAssembler extends Assembler by frequently used macros.
41 //
42 // Instructions for which a 'better' code sequence exists depending
43 // on arguments should also go in here.
44
45 class MacroAssembler: public Assembler {
46 friend class LIR_Assembler;
47
48 public:
49 using Assembler::mov;
50 using Assembler::movi;
51
52 protected:
53
54 // Support for VM calls
55 //
56 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
57 // may customize this version by overriding it for its purposes (e.g., to save/restore
58 // additional registers when doing a VM call).
59 virtual void call_VM_leaf_base(
60 address entry_point, // the entry point
61 int number_of_arguments, // the number of arguments to pop after the call
62 Label *retaddr = nullptr
63 );
64
65 virtual void call_VM_leaf_base(
66 address entry_point, // the entry point
67 int number_of_arguments, // the number of arguments to pop after the call
68 Label &retaddr) {
69 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
70 }
71
72 // This is the base routine called by the different versions of call_VM. The interpreter
73 // may customize this version by overriding it for its purposes (e.g., to save/restore
74 // additional registers when doing a VM call).
75 //
76 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
77 // returns the register which contains the thread upon return. If a thread register has been
78 // specified, the return value will correspond to that register. If no last_java_sp is specified
79 // (noreg) than rsp will be used instead.
80 virtual void call_VM_base( // returns the register containing the thread upon return
81 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
82 Register java_thread, // the thread if computed before ; use noreg otherwise
83 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
84 address entry_point, // the entry point
85 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
86 bool check_exceptions // whether to check for pending exceptions after return
87 );
88
89 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
90
91 enum KlassDecodeMode {
92 KlassDecodeNone,
93 KlassDecodeZero,
94 KlassDecodeXor,
95 KlassDecodeMovk
96 };
97
98 // Calculate decoding mode based on given parameters, used for checking then ultimately setting.
99 static KlassDecodeMode klass_decode_mode(address base, int shift, const size_t range);
100
101 private:
102 static KlassDecodeMode _klass_decode_mode;
103
104 // Returns above setting with asserts
105 static KlassDecodeMode klass_decode_mode();
106
107 public:
108 // Checks the decode mode and returns false if not compatible with preferred decoding mode.
109 static bool check_klass_decode_mode(address base, int shift, const size_t range);
110
111 // Sets the decode mode and returns false if cannot be set.
112 static bool set_klass_decode_mode(address base, int shift, const size_t range);
113
114 public:
115 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
116
117 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
118 // The implementation is only non-empty for the InterpreterMacroAssembler,
119 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
120 virtual void check_and_handle_popframe(Register java_thread);
121 virtual void check_and_handle_earlyret(Register java_thread);
122
123 void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp = rscratch1);
124 void rt_call(address dest, Register tmp = rscratch1);
125
126 // Load Effective Address
127 void lea(Register r, const Address &a) {
128 InstructionMark im(this);
129 a.lea(this, r);
130 }
131
132 /* Sometimes we get misaligned loads and stores, usually from Unsafe
133 accesses, and these can exceed the offset range. */
134 Address legitimize_address(const Address &a, int size, Register scratch) {
135 if (a.getMode() == Address::base_plus_offset) {
136 if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
137 block_comment("legitimize_address {");
138 lea(scratch, a);
139 block_comment("} legitimize_address");
140 return Address(scratch);
141 }
142 }
143 return a;
144 }
145
146 void addmw(Address a, Register incr, Register scratch) {
147 ldrw(scratch, a);
148 addw(scratch, scratch, incr);
149 strw(scratch, a);
150 }
151
152 // Add constant to memory word
153 void addmw(Address a, int imm, Register scratch) {
154 ldrw(scratch, a);
155 if (imm > 0)
156 addw(scratch, scratch, (unsigned)imm);
157 else
158 subw(scratch, scratch, (unsigned)-imm);
159 strw(scratch, a);
160 }
161
162 void bind(Label& L) {
163 Assembler::bind(L);
164 code()->clear_last_insn();
165 code()->set_last_label(pc());
166 }
167
168 void membar(Membar_mask_bits order_constraint);
169
170 using Assembler::ldr;
171 using Assembler::str;
172 using Assembler::ldrw;
173 using Assembler::strw;
174
175 void ldr(Register Rx, const Address &adr);
176 void ldrw(Register Rw, const Address &adr);
177 void str(Register Rx, const Address &adr);
178 void strw(Register Rx, const Address &adr);
179
180 // Frame creation and destruction shared between JITs.
181 void build_frame(int framesize);
182 void remove_frame(int framesize);
183
184 virtual void _call_Unimplemented(address call_site) {
185 mov(rscratch2, call_site);
186 }
187
188 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
189 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
190 // https://reviews.llvm.org/D3311
191
192 #ifdef _WIN64
193 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
194 #else
195 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
196 #endif
197
198 // aliases defined in AARCH64 spec
199
200 template<class T>
201 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
202
203 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
204 inline void cmp(Register Rd, unsigned imm) = delete;
205
206 template<class T>
207 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
208
209 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); }
210 inline void cmn(Register Rd, unsigned imm) = delete;
211
212 void cset(Register Rd, Assembler::Condition cond) {
213 csinc(Rd, zr, zr, ~cond);
214 }
215 void csetw(Register Rd, Assembler::Condition cond) {
216 csincw(Rd, zr, zr, ~cond);
217 }
218
219 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
220 csneg(Rd, Rn, Rn, ~cond);
221 }
222 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
223 csnegw(Rd, Rn, Rn, ~cond);
224 }
225
226 inline void movw(Register Rd, Register Rn) {
227 if (Rd == sp || Rn == sp) {
228 Assembler::addw(Rd, Rn, 0U);
229 } else {
230 orrw(Rd, zr, Rn);
231 }
232 }
233 inline void mov(Register Rd, Register Rn) {
234 assert(Rd != r31_sp && Rn != r31_sp, "should be");
235 if (Rd == Rn) {
236 } else if (Rd == sp || Rn == sp) {
237 Assembler::add(Rd, Rn, 0U);
238 } else {
239 orr(Rd, zr, Rn);
240 }
241 }
242
243 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
244 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
245
246 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
247 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
248
249 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
250 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
251
252 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
253 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
254 }
255 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
256 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
257 }
258
259 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
260 bfmw(Rd, Rn, lsb, (lsb + width - 1));
261 }
262 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
263 bfm(Rd, Rn, lsb , (lsb + width - 1));
264 }
265
266 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
267 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
268 }
269 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
270 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
271 }
272
273 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
274 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
275 }
276 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
277 sbfm(Rd, Rn, lsb , (lsb + width - 1));
278 }
279
280 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
281 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
282 }
283 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
284 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
285 }
286
287 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
288 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
289 }
290 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
291 ubfm(Rd, Rn, lsb , (lsb + width - 1));
292 }
293
294 inline void asrw(Register Rd, Register Rn, unsigned imm) {
295 sbfmw(Rd, Rn, imm, 31);
296 }
297
298 inline void asr(Register Rd, Register Rn, unsigned imm) {
299 sbfm(Rd, Rn, imm, 63);
300 }
301
302 inline void lslw(Register Rd, Register Rn, unsigned imm) {
303 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
304 }
305
306 inline void lsl(Register Rd, Register Rn, unsigned imm) {
307 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
308 }
309
310 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
311 ubfmw(Rd, Rn, imm, 31);
312 }
313
314 inline void lsr(Register Rd, Register Rn, unsigned imm) {
315 ubfm(Rd, Rn, imm, 63);
316 }
317
318 inline void rorw(Register Rd, Register Rn, unsigned imm) {
319 extrw(Rd, Rn, Rn, imm);
320 }
321
322 inline void ror(Register Rd, Register Rn, unsigned imm) {
323 extr(Rd, Rn, Rn, imm);
324 }
325
326 inline void sxtbw(Register Rd, Register Rn) {
327 sbfmw(Rd, Rn, 0, 7);
328 }
329 inline void sxthw(Register Rd, Register Rn) {
330 sbfmw(Rd, Rn, 0, 15);
331 }
332 inline void sxtb(Register Rd, Register Rn) {
333 sbfm(Rd, Rn, 0, 7);
334 }
335 inline void sxth(Register Rd, Register Rn) {
336 sbfm(Rd, Rn, 0, 15);
337 }
338 inline void sxtw(Register Rd, Register Rn) {
339 sbfm(Rd, Rn, 0, 31);
340 }
341
342 inline void uxtbw(Register Rd, Register Rn) {
343 ubfmw(Rd, Rn, 0, 7);
344 }
345 inline void uxthw(Register Rd, Register Rn) {
346 ubfmw(Rd, Rn, 0, 15);
347 }
348 inline void uxtb(Register Rd, Register Rn) {
349 ubfm(Rd, Rn, 0, 7);
350 }
351 inline void uxth(Register Rd, Register Rn) {
352 ubfm(Rd, Rn, 0, 15);
353 }
354 inline void uxtw(Register Rd, Register Rn) {
355 ubfm(Rd, Rn, 0, 31);
356 }
357
358 inline void cmnw(Register Rn, Register Rm) {
359 addsw(zr, Rn, Rm);
360 }
361 inline void cmn(Register Rn, Register Rm) {
362 adds(zr, Rn, Rm);
363 }
364
365 inline void cmpw(Register Rn, Register Rm) {
366 subsw(zr, Rn, Rm);
367 }
368 inline void cmp(Register Rn, Register Rm) {
369 subs(zr, Rn, Rm);
370 }
371
372 inline void negw(Register Rd, Register Rn) {
373 subw(Rd, zr, Rn);
374 }
375
376 inline void neg(Register Rd, Register Rn) {
377 sub(Rd, zr, Rn);
378 }
379
380 inline void negsw(Register Rd, Register Rn) {
381 subsw(Rd, zr, Rn);
382 }
383
384 inline void negs(Register Rd, Register Rn) {
385 subs(Rd, zr, Rn);
386 }
387
388 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
389 addsw(zr, Rn, Rm, kind, shift);
390 }
391 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
392 adds(zr, Rn, Rm, kind, shift);
393 }
394
395 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
396 subsw(zr, Rn, Rm, kind, shift);
397 }
398 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
399 subs(zr, Rn, Rm, kind, shift);
400 }
401
402 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
403 subw(Rd, zr, Rn, kind, shift);
404 }
405
406 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
407 sub(Rd, zr, Rn, kind, shift);
408 }
409
410 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
411 subsw(Rd, zr, Rn, kind, shift);
412 }
413
414 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
415 subs(Rd, zr, Rn, kind, shift);
416 }
417
418 inline void mnegw(Register Rd, Register Rn, Register Rm) {
419 msubw(Rd, Rn, Rm, zr);
420 }
421 inline void mneg(Register Rd, Register Rn, Register Rm) {
422 msub(Rd, Rn, Rm, zr);
423 }
424
425 inline void mulw(Register Rd, Register Rn, Register Rm) {
426 maddw(Rd, Rn, Rm, zr);
427 }
428 inline void mul(Register Rd, Register Rn, Register Rm) {
429 madd(Rd, Rn, Rm, zr);
430 }
431
432 inline void smnegl(Register Rd, Register Rn, Register Rm) {
433 smsubl(Rd, Rn, Rm, zr);
434 }
435 inline void smull(Register Rd, Register Rn, Register Rm) {
436 smaddl(Rd, Rn, Rm, zr);
437 }
438
439 inline void umnegl(Register Rd, Register Rn, Register Rm) {
440 umsubl(Rd, Rn, Rm, zr);
441 }
442 inline void umull(Register Rd, Register Rn, Register Rm) {
443 umaddl(Rd, Rn, Rm, zr);
444 }
445
446 #define WRAP(INSN) \
447 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
448 if (VM_Version::supports_a53mac() && Ra != zr) \
449 nop(); \
450 Assembler::INSN(Rd, Rn, Rm, Ra); \
451 }
452
453 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
454 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
455 #undef WRAP
456
457
458 // macro assembly operations needed for aarch64
459
460 public:
461
462 enum FpPushPopMode {
463 PushPopFull,
464 PushPopSVE,
465 PushPopNeon,
466 PushPopFp
467 };
468
469 // first two private routines for loading 32 bit or 64 bit constants
470 private:
471
472 void mov_immediate64(Register dst, uint64_t imm64);
473 void mov_immediate32(Register dst, uint32_t imm32);
474
475 int push(unsigned int bitset, Register stack);
476 int pop(unsigned int bitset, Register stack);
477
478 int push_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
479 int pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
480
481 int push_p(unsigned int bitset, Register stack);
482 int pop_p(unsigned int bitset, Register stack);
483
484 void mov(Register dst, Address a);
485
486 public:
487
488 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
489 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
490
491 void push_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) push_fp(regs.bits(), stack, mode); }
492 void pop_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) pop_fp(regs.bits(), stack, mode); }
493
494 static RegSet call_clobbered_gp_registers();
495
496 void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
497 void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
498
499 // Push and pop everything that might be clobbered by a native
500 // runtime call except rscratch1 and rscratch2. (They are always
501 // scratch, so we don't have to protect them.) Only save the lower
502 // 64 bits of each vector register. Additional registers can be excluded
503 // in a passed RegSet.
504 void push_call_clobbered_registers_except(RegSet exclude);
505 void pop_call_clobbered_registers_except(RegSet exclude);
506
507 void push_call_clobbered_registers() {
508 push_call_clobbered_registers_except(RegSet());
509 }
510 void pop_call_clobbered_registers() {
511 pop_call_clobbered_registers_except(RegSet());
512 }
513
514
515 // now mov instructions for loading absolute addresses and 32 or
516 // 64 bit integers
517
518 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
519
520 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
521 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); }
522
523 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); }
524
525 void mov(Register dst, RegisterOrConstant src) {
526 if (src.is_register())
527 mov(dst, src.as_register());
528 else
529 mov(dst, src.as_constant());
530 }
531
532 void movptr(Register r, uintptr_t imm64);
533
534 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
535
536 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
537 orr(Vd, T, Vn, Vn);
538 }
539
540 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
541 fcvtsh(tmp, src);
542 smov(dst, tmp, H, 0);
543 }
544
545 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
546 mov(tmp, H, 0, src);
547 fcvths(dst, tmp);
548 }
549
550 // Generalized Test Bit And Branch, including a "far" variety which
551 // spans more than 32KiB.
552 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
553 assert(cond == EQ || cond == NE, "must be");
554
555 if (isfar)
556 cond = ~cond;
557
558 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
559 if (cond == Assembler::EQ)
560 branch = &Assembler::tbz;
561 else
562 branch = &Assembler::tbnz;
563
564 if (isfar) {
565 Label L;
566 (this->*branch)(Rt, bitpos, L);
567 b(dest);
568 bind(L);
569 } else {
570 (this->*branch)(Rt, bitpos, dest);
571 }
572 }
573
574 // macro instructions for accessing and updating floating point
575 // status register
576 //
577 // FPSR : op1 == 011
578 // CRn == 0100
579 // CRm == 0100
580 // op2 == 001
581
582 inline void get_fpsr(Register reg)
583 {
584 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
585 }
586
587 inline void set_fpsr(Register reg)
588 {
589 msr(0b011, 0b0100, 0b0100, 0b001, reg);
590 }
591
592 inline void clear_fpsr()
593 {
594 msr(0b011, 0b0100, 0b0100, 0b001, zr);
595 }
596
597 // FPCR : op1 == 011
598 // CRn == 0100
599 // CRm == 0100
600 // op2 == 000
601
602 inline void get_fpcr(Register reg) {
603 mrs(0b11, 0b0100, 0b0100, 0b000, reg);
604 }
605
606 inline void set_fpcr(Register reg) {
607 msr(0b011, 0b0100, 0b0100, 0b000, reg);
608 }
609
610 // DCZID_EL0: op1 == 011
611 // CRn == 0000
612 // CRm == 0000
613 // op2 == 111
614 inline void get_dczid_el0(Register reg)
615 {
616 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
617 }
618
619 // CTR_EL0: op1 == 011
620 // CRn == 0000
621 // CRm == 0000
622 // op2 == 001
623 inline void get_ctr_el0(Register reg)
624 {
625 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
626 }
627
628 inline void get_nzcv(Register reg) {
629 mrs(0b011, 0b0100, 0b0010, 0b000, reg);
630 }
631
632 inline void set_nzcv(Register reg) {
633 msr(0b011, 0b0100, 0b0010, 0b000, reg);
634 }
635
636 // idiv variant which deals with MINLONG as dividend and -1 as divisor
637 int corrected_idivl(Register result, Register ra, Register rb,
638 bool want_remainder, Register tmp = rscratch1);
639 int corrected_idivq(Register result, Register ra, Register rb,
640 bool want_remainder, Register tmp = rscratch1);
641
642 // Support for null-checks
643 //
644 // Generates code that causes a null OS exception if the content of reg is null.
645 // If the accessed location is M[reg + offset] and the offset is known, provide the
646 // offset. No explicit code generation is needed if the offset is within a certain
647 // range (0 <= offset <= page_size).
648
649 virtual void null_check(Register reg, int offset = -1);
650 static bool needs_explicit_null_check(intptr_t offset);
651 static bool uses_implicit_null_check(void* address);
652
653 static address target_addr_for_insn(address insn_addr, unsigned insn);
654 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
655 static address target_addr_for_insn(address insn_addr) {
656 unsigned insn = *(unsigned*)insn_addr;
657 return target_addr_for_insn(insn_addr, insn);
658 }
659 static address target_addr_for_insn_or_null(address insn_addr) {
660 unsigned insn = *(unsigned*)insn_addr;
661 return target_addr_for_insn_or_null(insn_addr, insn);
662 }
663
664 // Required platform-specific helpers for Label::patch_instructions.
665 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
666 static int pd_patch_instruction_size(address branch, address target);
667 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
668 pd_patch_instruction_size(branch, target);
669 }
670 static address pd_call_destination(address branch) {
671 return target_addr_for_insn(branch);
672 }
673 #ifndef PRODUCT
674 static void pd_print_patched_instruction(address branch);
675 #endif
676
677 static int patch_oop(address insn_addr, address o);
678 static int patch_narrow_klass(address insn_addr, narrowKlass n);
679
680 // Return whether code is emitted to a scratch blob.
681 virtual bool in_scratch_emit_size() {
682 return false;
683 }
684 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
685 static int max_trampoline_stub_size();
686 void emit_static_call_stub();
687 static int static_call_stub_size();
688
689 // The following 4 methods return the offset of the appropriate move instruction
690
691 // Support for fast byte/short loading with zero extension (depending on particular CPU)
692 int load_unsigned_byte(Register dst, Address src);
693 int load_unsigned_short(Register dst, Address src);
694
695 // Support for fast byte/short loading with sign extension (depending on particular CPU)
696 int load_signed_byte(Register dst, Address src);
697 int load_signed_short(Register dst, Address src);
698
699 int load_signed_byte32(Register dst, Address src);
700 int load_signed_short32(Register dst, Address src);
701
702 // Support for sign-extension (hi:lo = extend_sign(lo))
703 void extend_sign(Register hi, Register lo);
704
705 // Load and store values by size and signed-ness
706 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
707 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
708
709 // Support for inc/dec with optimal instruction selection depending on value
710
711 // x86_64 aliases an unqualified register/address increment and
712 // decrement to call incrementq and decrementq but also supports
713 // explicitly sized calls to incrementq/decrementq or
714 // incrementl/decrementl
715
716 // for aarch64 the proper convention would be to use
717 // increment/decrement for 64 bit operations and
718 // incrementw/decrementw for 32 bit operations. so when porting
719 // x86_64 code we can leave calls to increment/decrement as is,
720 // replace incrementq/decrementq with increment/decrement and
721 // replace incrementl/decrementl with incrementw/decrementw.
722
723 // n.b. increment/decrement calls with an Address destination will
724 // need to use a scratch register to load the value to be
725 // incremented. increment/decrement calls which add or subtract a
726 // constant value greater than 2^12 will need to use a 2nd scratch
727 // register to hold the constant. so, a register increment/decrement
728 // may trash rscratch2 and an address increment/decrement trash
729 // rscratch and rscratch2
730
731 void decrementw(Address dst, int value = 1);
732 void decrementw(Register reg, int value = 1);
733
734 void decrement(Register reg, int value = 1);
735 void decrement(Address dst, int value = 1);
736
737 void incrementw(Address dst, int value = 1);
738 void incrementw(Register reg, int value = 1);
739
740 void increment(Register reg, int value = 1);
741 void increment(Address dst, int value = 1);
742
743
744 // Alignment
745 void align(int modulus);
746 void align(int modulus, int target);
747
748 // nop
749 void post_call_nop();
750
751 // Stack frame creation/removal
752 void enter(bool strip_ret_addr = false);
753 void leave();
754
755 // ROP Protection
756 void protect_return_address();
757 void protect_return_address(Register return_reg);
758 void authenticate_return_address();
759 void authenticate_return_address(Register return_reg);
760 void strip_return_address();
761 void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
762
763 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
764 // The pointer will be loaded into the thread register.
765 void get_thread(Register thread);
766
767 // support for argument shuffling
768 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
769 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
770 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
771 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
772 void object_move(
773 OopMap* map,
774 int oop_handle_offset,
775 int framesize_in_slots,
776 VMRegPair src,
777 VMRegPair dst,
778 bool is_receiver,
779 int* receiver_offset);
780
781
782 // Support for VM calls
783 //
784 // It is imperative that all calls into the VM are handled via the call_VM macros.
785 // They make sure that the stack linkage is setup correctly. call_VM's correspond
786 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
787
788
789 void call_VM(Register oop_result,
790 address entry_point,
791 bool check_exceptions = true);
792 void call_VM(Register oop_result,
793 address entry_point,
794 Register arg_1,
795 bool check_exceptions = true);
796 void call_VM(Register oop_result,
797 address entry_point,
798 Register arg_1, Register arg_2,
799 bool check_exceptions = true);
800 void call_VM(Register oop_result,
801 address entry_point,
802 Register arg_1, Register arg_2, Register arg_3,
803 bool check_exceptions = true);
804
805 // Overloadings with last_Java_sp
806 void call_VM(Register oop_result,
807 Register last_java_sp,
808 address entry_point,
809 int number_of_arguments = 0,
810 bool check_exceptions = true);
811 void call_VM(Register oop_result,
812 Register last_java_sp,
813 address entry_point,
814 Register arg_1, bool
815 check_exceptions = true);
816 void call_VM(Register oop_result,
817 Register last_java_sp,
818 address entry_point,
819 Register arg_1, Register arg_2,
820 bool check_exceptions = true);
821 void call_VM(Register oop_result,
822 Register last_java_sp,
823 address entry_point,
824 Register arg_1, Register arg_2, Register arg_3,
825 bool check_exceptions = true);
826
827 void get_vm_result (Register oop_result, Register thread);
828 void get_vm_result_2(Register metadata_result, Register thread);
829
830 // These always tightly bind to MacroAssembler::call_VM_base
831 // bypassing the virtual implementation
832 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
833 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
834 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
835 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
836 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
837
838 void call_VM_leaf(address entry_point,
839 int number_of_arguments = 0);
840 void call_VM_leaf(address entry_point,
841 Register arg_1);
842 void call_VM_leaf(address entry_point,
843 Register arg_1, Register arg_2);
844 void call_VM_leaf(address entry_point,
845 Register arg_1, Register arg_2, Register arg_3);
846
847 // These always tightly bind to MacroAssembler::call_VM_leaf_base
848 // bypassing the virtual implementation
849 void super_call_VM_leaf(address entry_point);
850 void super_call_VM_leaf(address entry_point, Register arg_1);
851 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
852 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
853 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
854
855 // last Java Frame (fills frame anchor)
856 void set_last_Java_frame(Register last_java_sp,
857 Register last_java_fp,
858 address last_java_pc,
859 Register scratch);
860
861 void set_last_Java_frame(Register last_java_sp,
862 Register last_java_fp,
863 Label &last_java_pc,
864 Register scratch);
865
866 void set_last_Java_frame(Register last_java_sp,
867 Register last_java_fp,
868 Register last_java_pc,
869 Register scratch);
870
871 void reset_last_Java_frame(Register thread);
872
873 // thread in the default location (rthread)
874 void reset_last_Java_frame(bool clear_fp);
875
876 // Stores
877 void store_check(Register obj); // store check for obj - register is destroyed afterwards
878 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
879
880 void resolve_jobject(Register value, Register tmp1, Register tmp2);
881 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
882
883 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
884 void c2bool(Register x);
885
886 void load_method_holder_cld(Register rresult, Register rmethod);
887 void load_method_holder(Register holder, Register method);
888
889 // oop manipulations
890 void load_narrow_klass_compact(Register dst, Register src);
891 void load_klass(Register dst, Register src);
892 void store_klass(Register dst, Register src);
893 void cmp_klass(Register obj, Register klass, Register tmp);
894 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
895
896 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
897 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
898 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
899
900 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
901 Register tmp1, Register tmp2);
902
903 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
904 Register tmp1, Register tmp2, Register tmp3);
905
906 void load_heap_oop(Register dst, Address src, Register tmp1,
907 Register tmp2, DecoratorSet decorators = 0);
908
909 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
910 Register tmp2, DecoratorSet decorators = 0);
911 void store_heap_oop(Address dst, Register val, Register tmp1,
912 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
913
914 // currently unimplemented
915 // Used for storing null. All other oop constants should be
916 // stored using routines that take a jobject.
917 void store_heap_oop_null(Address dst);
918
919 void store_klass_gap(Register dst, Register src);
920
921 // This dummy is to prevent a call to store_heap_oop from
922 // converting a zero (like null) into a Register by giving
923 // the compiler two choices it can't resolve
924
925 void store_heap_oop(Address dst, void* dummy);
926
927 void encode_heap_oop(Register d, Register s);
928 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
929 void decode_heap_oop(Register d, Register s);
930 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
931 void encode_heap_oop_not_null(Register r);
932 void decode_heap_oop_not_null(Register r);
933 void encode_heap_oop_not_null(Register dst, Register src);
934 void decode_heap_oop_not_null(Register dst, Register src);
935
936 void set_narrow_oop(Register dst, jobject obj);
937
938 void encode_klass_not_null(Register r);
939 void decode_klass_not_null(Register r);
940 void encode_klass_not_null(Register dst, Register src);
941 void decode_klass_not_null(Register dst, Register src);
942
943 void set_narrow_klass(Register dst, Klass* k);
944
945 // if heap base register is used - reinit it with the correct value
946 void reinit_heapbase();
947
948 DEBUG_ONLY(void verify_heapbase(const char* msg);)
949
950 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
951 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
952 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
953 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
954
955 void push_cont_fastpath(Register java_thread = rthread);
956 void pop_cont_fastpath(Register java_thread = rthread);
957
958 void inc_held_monitor_count(Register tmp);
959 void dec_held_monitor_count(Register tmp);
960
961 // Round up to a power of two
962 void round_to(Register reg, int modulus);
963
964 // java.lang.Math::round intrinsics
965 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
966 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
967
968 // allocation
969 void tlab_allocate(
970 Register obj, // result: pointer to object after successful allocation
971 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
972 int con_size_in_bytes, // object size in bytes if known at compile time
973 Register t1, // temp register
974 Register t2, // temp register
975 Label& slow_case // continuation point if fast allocation fails
976 );
977 void verify_tlab();
978
979 // interface method calling
980 void lookup_interface_method(Register recv_klass,
981 Register intf_klass,
982 RegisterOrConstant itable_index,
983 Register method_result,
984 Register scan_temp,
985 Label& no_such_interface,
986 bool return_method = true);
987
988 void lookup_interface_method_stub(Register recv_klass,
989 Register holder_klass,
990 Register resolved_klass,
991 Register method_result,
992 Register temp_reg,
993 Register temp_reg2,
994 int itable_index,
995 Label& L_no_such_interface);
996
997 // virtual method calling
998 // n.b. x86 allows RegisterOrConstant for vtable_index
999 void lookup_virtual_method(Register recv_klass,
1000 RegisterOrConstant vtable_index,
1001 Register method_result);
1002
1003 // Test sub_klass against super_klass, with fast and slow paths.
1004
1005 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1006 // One of the three labels can be null, meaning take the fall-through.
1007 // If super_check_offset is -1, the value is loaded up from super_klass.
1008 // No registers are killed, except temp_reg.
1009 void check_klass_subtype_fast_path(Register sub_klass,
1010 Register super_klass,
1011 Register temp_reg,
1012 Label* L_success,
1013 Label* L_failure,
1014 Label* L_slow_path,
1015 Register super_check_offset = noreg);
1016
1017 // The rest of the type check; must be wired to a corresponding fast path.
1018 // It does not repeat the fast path logic, so don't use it standalone.
1019 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1020 // Updates the sub's secondary super cache as necessary.
1021 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1022 void check_klass_subtype_slow_path(Register sub_klass,
1023 Register super_klass,
1024 Register temp_reg,
1025 Register temp2_reg,
1026 Label* L_success,
1027 Label* L_failure,
1028 bool set_cond_codes = false);
1029
1030 void check_klass_subtype_slow_path_linear(Register sub_klass,
1031 Register super_klass,
1032 Register temp_reg,
1033 Register temp2_reg,
1034 Label* L_success,
1035 Label* L_failure,
1036 bool set_cond_codes = false);
1037
1038 void check_klass_subtype_slow_path_table(Register sub_klass,
1039 Register super_klass,
1040 Register temp_reg,
1041 Register temp2_reg,
1042 Register temp3_reg,
1043 Register result_reg,
1044 FloatRegister vtemp_reg,
1045 Label* L_success,
1046 Label* L_failure,
1047 bool set_cond_codes = false);
1048
1049 // If r is valid, return r.
1050 // If r is invalid, remove a register r2 from available_regs, add r2
1051 // to regs_to_push, then return r2.
1052 Register allocate_if_noreg(const Register r,
1053 RegSetIterator<Register> &available_regs,
1054 RegSet ®s_to_push);
1055
1056 // Secondary subtype checking
1057 void lookup_secondary_supers_table_var(Register sub_klass,
1058 Register r_super_klass,
1059 Register temp1,
1060 Register temp2,
1061 Register temp3,
1062 FloatRegister vtemp,
1063 Register result,
1064 Label *L_success);
1065
1066
1067 // As above, but with a constant super_klass.
1068 // The result is in Register result, not the condition codes.
1069 bool lookup_secondary_supers_table_const(Register r_sub_klass,
1070 Register r_super_klass,
1071 Register temp1,
1072 Register temp2,
1073 Register temp3,
1074 FloatRegister vtemp,
1075 Register result,
1076 u1 super_klass_slot,
1077 bool stub_is_near = false);
1078
1079 void verify_secondary_supers_table(Register r_sub_klass,
1080 Register r_super_klass,
1081 Register temp1,
1082 Register temp2,
1083 Register result);
1084
1085 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
1086 Register r_array_base,
1087 Register r_array_index,
1088 Register r_bitmap,
1089 Register temp1,
1090 Register result,
1091 bool is_stub = true);
1092
1093 // Simplified, combined version, good for typical uses.
1094 // Falls through on failure.
1095 void check_klass_subtype(Register sub_klass,
1096 Register super_klass,
1097 Register temp_reg,
1098 Label& L_success);
1099
1100 void clinit_barrier(Register klass,
1101 Register thread,
1102 Label* L_fast_path = nullptr,
1103 Label* L_slow_path = nullptr);
1104
1105 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1106
1107 void verify_sve_vector_length(Register tmp = rscratch1);
1108 void reinitialize_ptrue() {
1109 if (UseSVE > 0) {
1110 sve_ptrue(ptrue, B);
1111 }
1112 }
1113 void verify_ptrue();
1114
1115 // Debugging
1116
1117 // only if +VerifyOops
1118 void _verify_oop(Register reg, const char* s, const char* file, int line);
1119 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1120
1121 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1122 if (VerifyOops) {
1123 _verify_oop(reg, s, file, line);
1124 }
1125 }
1126 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1127 if (VerifyOops) {
1128 _verify_oop_addr(reg, s, file, line);
1129 }
1130 }
1131
1132 // TODO: verify method and klass metadata (compare against vptr?)
1133 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1134 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1135
1136 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1137 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1138 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1139 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1140 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1141
1142 // Restore cpu control state after JNI call
1143 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2);
1144
1145 // prints msg, dumps registers and stops execution
1146 void stop(const char* msg);
1147
1148 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1149
1150 void untested() { stop("untested"); }
1151
1152 void unimplemented(const char* what = "");
1153
1154 void should_not_reach_here() { stop("should not reach here"); }
1155
1156 void _assert_asm(Condition cc, const char* msg);
1157 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1158 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1159
1160 // Stack overflow checking
1161 void bang_stack_with_offset(int offset) {
1162 // stack grows down, caller passes positive offset
1163 assert(offset > 0, "must bang with negative offset");
1164 sub(rscratch2, sp, offset);
1165 str(zr, Address(rscratch2));
1166 }
1167
1168 // Writes to stack successive pages until offset reached to check for
1169 // stack overflow + shadow pages. Also, clobbers tmp
1170 void bang_stack_size(Register size, Register tmp);
1171
1172 // Check for reserved stack access in method being exited (for JIT)
1173 void reserved_stack_check();
1174
1175 // Arithmetics
1176
1177 void addptr(const Address &dst, int32_t src);
1178 void cmpptr(Register src1, Address src2);
1179
1180 void cmpoop(Register obj1, Register obj2);
1181
1182 // Various forms of CAS
1183
1184 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1185 Label &succeed, Label *fail);
1186 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1187 Label &succeed, Label *fail);
1188
1189 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1190 Label &succeed, Label *fail);
1191
1192 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1193 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1194 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1195 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1196
1197 void atomic_xchg(Register prev, Register newv, Register addr);
1198 void atomic_xchgw(Register prev, Register newv, Register addr);
1199 void atomic_xchgl(Register prev, Register newv, Register addr);
1200 void atomic_xchglw(Register prev, Register newv, Register addr);
1201 void atomic_xchgal(Register prev, Register newv, Register addr);
1202 void atomic_xchgalw(Register prev, Register newv, Register addr);
1203
1204 void orptr(Address adr, RegisterOrConstant src) {
1205 ldr(rscratch1, adr);
1206 if (src.is_register())
1207 orr(rscratch1, rscratch1, src.as_register());
1208 else
1209 orr(rscratch1, rscratch1, src.as_constant());
1210 str(rscratch1, adr);
1211 }
1212
1213 // A generic CAS; success or failure is in the EQ flag.
1214 // Clobbers rscratch1
1215 void cmpxchg(Register addr, Register expected, Register new_val,
1216 enum operand_size size,
1217 bool acquire, bool release, bool weak,
1218 Register result);
1219
1220 #ifdef ASSERT
1221 // Template short-hand support to clean-up after a failed call to trampoline
1222 // call generation (see trampoline_call() below), when a set of Labels must
1223 // be reset (before returning).
1224 template<typename Label, typename... More>
1225 void reset_labels(Label &lbl, More&... more) {
1226 lbl.reset(); reset_labels(more...);
1227 }
1228 template<typename Label>
1229 void reset_labels(Label &lbl) {
1230 lbl.reset();
1231 }
1232 #endif
1233
1234 private:
1235 void compare_eq(Register rn, Register rm, enum operand_size size);
1236
1237 public:
1238 // AArch64 OpenJDK uses four different types of calls:
1239 // - direct call: bl pc_relative_offset
1240 // This is the shortest and the fastest, but the offset has the range:
1241 // +/-128MB for the release build, +/-2MB for the debug build.
1242 //
1243 // - far call: adrp reg, pc_relative_offset; add; bl reg
1244 // This is longer than a direct call. The offset has
1245 // the range +/-4GB. As the code cache size is limited to 4GB,
1246 // far calls can reach anywhere in the code cache. If a jump is
1247 // needed rather than a call, a far jump 'b reg' can be used instead.
1248 // All instructions are embedded at a call site.
1249 //
1250 // - trampoline call:
1251 // This is only available in C1/C2-generated code (nmethod). It is a combination
1252 // of a direct call, which is used if the destination of a call is in range,
1253 // and a register-indirect call. It has the advantages of reaching anywhere in
1254 // the AArch64 address space and being patchable at runtime when the generated
1255 // code is being executed by other threads.
1256 //
1257 // [Main code section]
1258 // bl trampoline
1259 // [Stub code section]
1260 // trampoline:
1261 // ldr reg, pc + 8
1262 // br reg
1263 // <64-bit destination address>
1264 //
1265 // If the destination is in range when the generated code is moved to the code
1266 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1267 // is not used.
1268 // The optimization does not remove the trampoline from the stub section.
1269 // This is necessary because the trampoline may well be redirected later when
1270 // code is patched, and the new destination may not be reachable by a simple BR
1271 // instruction.
1272 //
1273 // - indirect call: move reg, address; blr reg
1274 // This too can reach anywhere in the address space, but it cannot be
1275 // patched while code is running, so it must only be modified at a safepoint.
1276 // This form of call is most suitable for targets at fixed addresses, which
1277 // will never be patched.
1278 //
1279 // The patching we do conforms to the "Concurrent modification and
1280 // execution of instructions" section of the Arm Architectural
1281 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1282 // or SVC instructions to be modified while another thread is
1283 // executing them.
1284 //
1285 // To patch a trampoline call when the BL can't reach, we first modify
1286 // the 64-bit destination address in the trampoline, then modify the
1287 // BL to point to the trampoline, then flush the instruction cache to
1288 // broadcast the change to all executing threads. See
1289 // NativeCall::set_destination_mt_safe for the details.
1290 //
1291 // There is a benign race in that the other thread might observe the
1292 // modified BL before it observes the modified 64-bit destination
1293 // address. That does not matter because the destination method has been
1294 // invalidated, so there will be a trap at its start.
1295 // For this to work, the destination address in the trampoline is
1296 // always updated, even if we're not using the trampoline.
1297
1298 // Emit a direct call if the entry address will always be in range,
1299 // otherwise a trampoline call.
1300 // Supported entry.rspec():
1301 // - relocInfo::runtime_call_type
1302 // - relocInfo::opt_virtual_call_type
1303 // - relocInfo::static_call_type
1304 // - relocInfo::virtual_call_type
1305 //
1306 // Return: the call PC or null if CodeCache is full.
1307 // Clobbers: rscratch1
1308 address trampoline_call(Address entry);
1309
1310 static bool far_branches() {
1311 return ReservedCodeCacheSize > branch_range;
1312 }
1313
1314 // Check if branches to the non nmethod section require a far jump
1315 static bool codestub_branch_needs_far_jump() {
1316 if (SCCache::is_on_for_write()) {
1317 // To calculate far_codestub_branch_size correctly.
1318 return true;
1319 }
1320 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1321 }
1322
1323 // Emit a direct call/jump if the entry address will always be in range,
1324 // otherwise a far call/jump.
1325 // The address must be inside the code cache.
1326 // Supported entry.rspec():
1327 // - relocInfo::external_word_type
1328 // - relocInfo::runtime_call_type
1329 // - relocInfo::none
1330 // In the case of a far call/jump, the entry address is put in the tmp register.
1331 // The tmp register is invalidated.
1332 //
1333 // Far_jump returns the amount of the emitted code.
1334 void far_call(Address entry, Register tmp = rscratch1);
1335 int far_jump(Address entry, Register tmp = rscratch1);
1336
1337 static int far_codestub_branch_size() {
1338 if (codestub_branch_needs_far_jump()) {
1339 return 3 * 4; // adrp, add, br
1340 } else {
1341 return 4;
1342 }
1343 }
1344
1345 // Emit the CompiledIC call idiom
1346 address ic_call(address entry, jint method_index = 0);
1347 static int ic_check_size();
1348 int ic_check(int end_alignment);
1349
1350 public:
1351
1352 // Data
1353
1354 void mov_metadata(Register dst, Metadata* obj);
1355 Address allocate_metadata_address(Metadata* obj);
1356 Address constant_oop_address(jobject obj);
1357
1358 void movoop(Register dst, jobject obj);
1359
1360 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1361 void kernel_crc32(Register crc, Register buf, Register len,
1362 Register table0, Register table1, Register table2, Register table3,
1363 Register tmp, Register tmp2, Register tmp3);
1364 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1365 void kernel_crc32c(Register crc, Register buf, Register len,
1366 Register table0, Register table1, Register table2, Register table3,
1367 Register tmp, Register tmp2, Register tmp3);
1368
1369 // Stack push and pop individual 64 bit registers
1370 void push(Register src);
1371 void pop(Register dst);
1372
1373 void repne_scan(Register addr, Register value, Register count,
1374 Register scratch);
1375 void repne_scanw(Register addr, Register value, Register count,
1376 Register scratch);
1377
1378 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1379 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1380
1381 // If a constant does not fit in an immediate field, generate some
1382 // number of MOV instructions and then perform the operation
1383 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1384 add_sub_imm_insn insn1,
1385 add_sub_reg_insn insn2, bool is32);
1386 // Separate vsn which sets the flags
1387 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1388 add_sub_imm_insn insn1,
1389 add_sub_reg_insn insn2, bool is32);
1390
1391 #define WRAP(INSN, is32) \
1392 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1393 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1394 } \
1395 \
1396 void INSN(Register Rd, Register Rn, Register Rm, \
1397 enum shift_kind kind, unsigned shift = 0) { \
1398 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1399 } \
1400 \
1401 void INSN(Register Rd, Register Rn, Register Rm) { \
1402 Assembler::INSN(Rd, Rn, Rm); \
1403 } \
1404 \
1405 void INSN(Register Rd, Register Rn, Register Rm, \
1406 ext::operation option, int amount = 0) { \
1407 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1408 }
1409
1410 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1411
1412 #undef WRAP
1413 #define WRAP(INSN, is32) \
1414 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1415 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1416 } \
1417 \
1418 void INSN(Register Rd, Register Rn, Register Rm, \
1419 enum shift_kind kind, unsigned shift = 0) { \
1420 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1421 } \
1422 \
1423 void INSN(Register Rd, Register Rn, Register Rm) { \
1424 Assembler::INSN(Rd, Rn, Rm); \
1425 } \
1426 \
1427 void INSN(Register Rd, Register Rn, Register Rm, \
1428 ext::operation option, int amount = 0) { \
1429 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1430 }
1431
1432 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1433
1434 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1435 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1436 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1437 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1438
1439 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1440
1441 void tableswitch(Register index, jint lowbound, jint highbound,
1442 Label &jumptable, Label &jumptable_end, int stride = 1) {
1443 adr(rscratch1, jumptable);
1444 subsw(rscratch2, index, lowbound);
1445 subsw(zr, rscratch2, highbound - lowbound);
1446 br(Assembler::HS, jumptable_end);
1447 add(rscratch1, rscratch1, rscratch2,
1448 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1449 br(rscratch1);
1450 }
1451
1452 // Form an address from base + offset in Rd. Rd may or may not
1453 // actually be used: you must use the Address that is returned. It
1454 // is up to you to ensure that the shift provided matches the size
1455 // of your data.
1456 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1457
1458 // Return true iff an address is within the 48-bit AArch64 address
1459 // space.
1460 bool is_valid_AArch64_address(address a) {
1461 return ((uint64_t)a >> 48) == 0;
1462 }
1463
1464 // Load the base of the cardtable byte map into reg.
1465 void load_byte_map_base(Register reg);
1466
1467 // Load a constant address in the AOT Runtime Constants area
1468 void load_aotrc_address(Register reg, address a);
1469
1470 // Prolog generator routines to support switch between x86 code and
1471 // generated ARM code
1472
1473 // routine to generate an x86 prolog for a stub function which
1474 // bootstraps into the generated ARM code which directly follows the
1475 // stub
1476 //
1477
1478 public:
1479
1480 void ldr_constant(Register dest, const Address &const_addr) {
1481 if (NearCpool) {
1482 ldr(dest, const_addr);
1483 } else {
1484 uint64_t offset;
1485 adrp(dest, InternalAddress(const_addr.target()), offset);
1486 ldr(dest, Address(dest, offset));
1487 }
1488 }
1489
1490 address read_polling_page(Register r, relocInfo::relocType rtype);
1491 void get_polling_page(Register dest, relocInfo::relocType rtype);
1492
1493 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1494 void update_byte_crc32(Register crc, Register val, Register table);
1495 void update_word_crc32(Register crc, Register v, Register tmp,
1496 Register table0, Register table1, Register table2, Register table3,
1497 bool upper = false);
1498
1499 address count_positives(Register ary1, Register len, Register result);
1500
1501 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1502 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1503
1504 // Ensure that the inline code and the stub use the same registers.
1505 #define ARRAYS_HASHCODE_REGISTERS \
1506 do { \
1507 assert(result == r0 && \
1508 ary == r1 && \
1509 cnt == r2 && \
1510 vdata0 == v3 && \
1511 vdata1 == v2 && \
1512 vdata2 == v1 && \
1513 vdata3 == v0 && \
1514 vmul0 == v4 && \
1515 vmul1 == v5 && \
1516 vmul2 == v6 && \
1517 vmul3 == v7 && \
1518 vpow == v12 && \
1519 vpowm == v13, "registers must match aarch64.ad"); \
1520 } while (0)
1521
1522 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1523
1524 void fill_words(Register base, Register cnt, Register value);
1525 address zero_words(Register base, uint64_t cnt);
1526 address zero_words(Register ptr, Register cnt);
1527 void zero_dcache_blocks(Register base, Register cnt);
1528
1529 static const int zero_words_block_size;
1530
1531 address byte_array_inflate(Register src, Register dst, Register len,
1532 FloatRegister vtmp1, FloatRegister vtmp2,
1533 FloatRegister vtmp3, Register tmp4);
1534
1535 void char_array_compress(Register src, Register dst, Register len,
1536 Register res,
1537 FloatRegister vtmp0, FloatRegister vtmp1,
1538 FloatRegister vtmp2, FloatRegister vtmp3,
1539 FloatRegister vtmp4, FloatRegister vtmp5);
1540
1541 void encode_iso_array(Register src, Register dst,
1542 Register len, Register res, bool ascii,
1543 FloatRegister vtmp0, FloatRegister vtmp1,
1544 FloatRegister vtmp2, FloatRegister vtmp3,
1545 FloatRegister vtmp4, FloatRegister vtmp5);
1546
1547 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1548 address pio2, address dsin_coef, address dcos_coef);
1549 private:
1550 // begin trigonometric functions support block
1551 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1552 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1553 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1554 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1555 // end trigonometric functions support block
1556 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1557 Register src1, Register src2);
1558 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1559 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1560 }
1561 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1562 Register y, Register y_idx, Register z,
1563 Register carry, Register product,
1564 Register idx, Register kdx);
1565 void multiply_128_x_128_loop(Register y, Register z,
1566 Register carry, Register carry2,
1567 Register idx, Register jdx,
1568 Register yz_idx1, Register yz_idx2,
1569 Register tmp, Register tmp3, Register tmp4,
1570 Register tmp7, Register product_hi);
1571 void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1572 Register len, Register tmp0, Register tmp1, Register tmp2,
1573 Register tmp3);
1574 void kernel_crc32_using_crc32(Register crc, Register buf,
1575 Register len, Register tmp0, Register tmp1, Register tmp2,
1576 Register tmp3);
1577 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1578 Register len, Register tmp0, Register tmp1, Register tmp2,
1579 Register tmp3);
1580 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1581 Register len, Register tmp0, Register tmp1, Register tmp2,
1582 Register tmp3);
1583 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1584 Register len, Register tmp0, Register tmp1, Register tmp2,
1585 size_t table_offset);
1586
1587 void ghash_modmul (FloatRegister result,
1588 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1589 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1590 FloatRegister t1, FloatRegister t2, FloatRegister t3);
1591 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1592 public:
1593 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1594 Register tmp0, Register tmp1, Register tmp2, Register tmp3,
1595 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1596 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1597 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1598 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1599 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1600 void ghash_multiply_wide(int index,
1601 FloatRegister result_lo, FloatRegister result_hi,
1602 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1603 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1604 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1605 FloatRegister p, FloatRegister z, FloatRegister t1);
1606 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1607 FloatRegister p, FloatRegister z, FloatRegister t1);
1608 void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1609 Register data, Register blocks, int unrolls);
1610
1611
1612 void aesenc_loadkeys(Register key, Register keylen);
1613 void aesecb_encrypt(Register from, Register to, Register keylen,
1614 FloatRegister data = v0, int unrolls = 1);
1615 void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1616 void aes_round(FloatRegister input, FloatRegister subkey);
1617
1618 // ChaCha20 functions support block
1619 void cc20_quarter_round(FloatRegister aVec, FloatRegister bVec,
1620 FloatRegister cVec, FloatRegister dVec, FloatRegister scratch,
1621 FloatRegister tbl);
1622 void cc20_shift_lane_org(FloatRegister bVec, FloatRegister cVec,
1623 FloatRegister dVec, bool colToDiag);
1624
1625 // Place an ISB after code may have been modified due to a safepoint.
1626 void safepoint_isb();
1627
1628 private:
1629 // Return the effective address r + (r1 << ext) + offset.
1630 // Uses rscratch2.
1631 Address offsetted_address(Register r, Register r1, Address::extend ext,
1632 int offset, int size);
1633
1634 private:
1635 // Returns an address on the stack which is reachable with a ldr/str of size
1636 // Uses rscratch2 if the address is not directly reachable
1637 Address spill_address(int size, int offset, Register tmp=rscratch2);
1638 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1639
1640 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1641
1642 // Check whether two loads/stores can be merged into ldp/stp.
1643 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1644
1645 // Merge current load/store with previous load/store into ldp/stp.
1646 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1647
1648 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1649 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1650
1651 public:
1652 void spill(Register Rx, bool is64, int offset) {
1653 if (is64) {
1654 str(Rx, spill_address(8, offset));
1655 } else {
1656 strw(Rx, spill_address(4, offset));
1657 }
1658 }
1659 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1660 str(Vx, T, spill_address(1 << (int)T, offset));
1661 }
1662
1663 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1664 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1665 }
1666 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1667 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1668 }
1669
1670 void unspill(Register Rx, bool is64, int offset) {
1671 if (is64) {
1672 ldr(Rx, spill_address(8, offset));
1673 } else {
1674 ldrw(Rx, spill_address(4, offset));
1675 }
1676 }
1677 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1678 ldr(Vx, T, spill_address(1 << (int)T, offset));
1679 }
1680
1681 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1682 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1683 }
1684 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1685 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1686 }
1687
1688 void spill_copy128(int src_offset, int dst_offset,
1689 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1690 if (src_offset < 512 && (src_offset & 7) == 0 &&
1691 dst_offset < 512 && (dst_offset & 7) == 0) {
1692 ldp(tmp1, tmp2, Address(sp, src_offset));
1693 stp(tmp1, tmp2, Address(sp, dst_offset));
1694 } else {
1695 unspill(tmp1, true, src_offset);
1696 spill(tmp1, true, dst_offset);
1697 unspill(tmp1, true, src_offset+8);
1698 spill(tmp1, true, dst_offset+8);
1699 }
1700 }
1701 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1702 int sve_vec_reg_size_in_bytes) {
1703 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1704 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1705 spill_copy128(src_offset, dst_offset);
1706 src_offset += 16;
1707 dst_offset += 16;
1708 }
1709 }
1710 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1711 int sve_predicate_reg_size_in_bytes) {
1712 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1713 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1714 reinitialize_ptrue();
1715 }
1716 void cache_wb(Address line);
1717 void cache_wbsync(bool is_pre);
1718
1719 // Code for java.lang.Thread::onSpinWait() intrinsic.
1720 void spin_wait();
1721
1722 void lightweight_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow);
1723 void lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow);
1724
1725 private:
1726 // Check the current thread doesn't need a cross modify fence.
1727 void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1728
1729 };
1730
1731 #ifdef ASSERT
1732 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1733 #endif
1734
1735 struct tableswitch {
1736 Register _reg;
1737 int _insn_index; jint _first_key; jint _last_key;
1738 Label _after;
1739 Label _branches;
1740 };
1741
1742 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP