1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/vmreg.hpp"
31 #include "code/SCCache.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/powerOfTwo.hpp"
37
38 class OopMap;
39
40 // MacroAssembler extends Assembler by frequently used macros.
41 //
42 // Instructions for which a 'better' code sequence exists depending
43 // on arguments should also go in here.
44
45 class MacroAssembler: public Assembler {
46 friend class LIR_Assembler;
47
48 public:
49 using Assembler::mov;
50 using Assembler::movi;
51
52 protected:
53
54 // Support for VM calls
55 //
56 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
57 // may customize this version by overriding it for its purposes (e.g., to save/restore
58 // additional registers when doing a VM call).
59 virtual void call_VM_leaf_base(
60 address entry_point, // the entry point
61 int number_of_arguments, // the number of arguments to pop after the call
62 Label *retaddr = nullptr
63 );
64
65 virtual void call_VM_leaf_base(
66 address entry_point, // the entry point
67 int number_of_arguments, // the number of arguments to pop after the call
68 Label &retaddr) {
69 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
70 }
71
72 // This is the base routine called by the different versions of call_VM. The interpreter
73 // may customize this version by overriding it for its purposes (e.g., to save/restore
74 // additional registers when doing a VM call).
75 //
76 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
77 // returns the register which contains the thread upon return. If a thread register has been
78 // specified, the return value will correspond to that register. If no last_java_sp is specified
79 // (noreg) than rsp will be used instead.
80 virtual void call_VM_base( // returns the register containing the thread upon return
81 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
82 Register java_thread, // the thread if computed before ; use noreg otherwise
83 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
84 address entry_point, // the entry point
85 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
86 bool check_exceptions // whether to check for pending exceptions after return
87 );
88
89 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
90
91 enum KlassDecodeMode {
92 KlassDecodeNone,
93 KlassDecodeZero,
94 KlassDecodeXor,
95 KlassDecodeMovk
96 };
97
98 KlassDecodeMode klass_decode_mode();
99
100 private:
101 static KlassDecodeMode _klass_decode_mode;
102
103 public:
104 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
105
106 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
107 // The implementation is only non-empty for the InterpreterMacroAssembler,
108 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
109 virtual void check_and_handle_popframe(Register java_thread);
110 virtual void check_and_handle_earlyret(Register java_thread);
111
112 void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod, Register tmp = rscratch1);
113 void rt_call(address dest, Register tmp = rscratch1);
114
115 // Load Effective Address
116 void lea(Register r, const Address &a) {
117 InstructionMark im(this);
118 a.lea(this, r);
119 }
120
121 /* Sometimes we get misaligned loads and stores, usually from Unsafe
122 accesses, and these can exceed the offset range. */
123 Address legitimize_address(const Address &a, int size, Register scratch) {
124 if (a.getMode() == Address::base_plus_offset) {
125 if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
126 block_comment("legitimize_address {");
127 lea(scratch, a);
128 block_comment("} legitimize_address");
129 return Address(scratch);
130 }
131 }
132 return a;
133 }
134
135 void addmw(Address a, Register incr, Register scratch) {
136 ldrw(scratch, a);
137 addw(scratch, scratch, incr);
138 strw(scratch, a);
139 }
140
141 // Add constant to memory word
142 void addmw(Address a, int imm, Register scratch) {
143 ldrw(scratch, a);
144 if (imm > 0)
145 addw(scratch, scratch, (unsigned)imm);
146 else
147 subw(scratch, scratch, (unsigned)-imm);
148 strw(scratch, a);
149 }
150
151 void bind(Label& L) {
152 Assembler::bind(L);
153 code()->clear_last_insn();
154 code()->set_last_label(pc());
155 }
156
157 void membar(Membar_mask_bits order_constraint);
158
159 using Assembler::ldr;
160 using Assembler::str;
161 using Assembler::ldrw;
162 using Assembler::strw;
163
164 void ldr(Register Rx, const Address &adr);
165 void ldrw(Register Rw, const Address &adr);
166 void str(Register Rx, const Address &adr);
167 void strw(Register Rx, const Address &adr);
168
169 // Frame creation and destruction shared between JITs.
170 void build_frame(int framesize);
171 void remove_frame(int framesize);
172
173 virtual void _call_Unimplemented(address call_site) {
174 mov(rscratch2, call_site);
175 }
176
177 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
178 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
179 // https://reviews.llvm.org/D3311
180
181 #ifdef _WIN64
182 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
183 #else
184 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
185 #endif
186
187 // aliases defined in AARCH64 spec
188
189 template<class T>
190 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
191
192 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
193 inline void cmp(Register Rd, unsigned imm) = delete;
194
195 template<class T>
196 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
197
198 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); }
199 inline void cmn(Register Rd, unsigned imm) = delete;
200
201 void cset(Register Rd, Assembler::Condition cond) {
202 csinc(Rd, zr, zr, ~cond);
203 }
204 void csetw(Register Rd, Assembler::Condition cond) {
205 csincw(Rd, zr, zr, ~cond);
206 }
207
208 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
209 csneg(Rd, Rn, Rn, ~cond);
210 }
211 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
212 csnegw(Rd, Rn, Rn, ~cond);
213 }
214
215 inline void movw(Register Rd, Register Rn) {
216 if (Rd == sp || Rn == sp) {
217 Assembler::addw(Rd, Rn, 0U);
218 } else {
219 orrw(Rd, zr, Rn);
220 }
221 }
222 inline void mov(Register Rd, Register Rn) {
223 assert(Rd != r31_sp && Rn != r31_sp, "should be");
224 if (Rd == Rn) {
225 } else if (Rd == sp || Rn == sp) {
226 Assembler::add(Rd, Rn, 0U);
227 } else {
228 orr(Rd, zr, Rn);
229 }
230 }
231
232 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
233 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
234
235 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
236 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
237
238 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
239 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
240
241 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
242 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
243 }
244 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
245 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
246 }
247
248 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
249 bfmw(Rd, Rn, lsb, (lsb + width - 1));
250 }
251 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
252 bfm(Rd, Rn, lsb , (lsb + width - 1));
253 }
254
255 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
256 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
257 }
258 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
259 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
260 }
261
262 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
263 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
264 }
265 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
266 sbfm(Rd, Rn, lsb , (lsb + width - 1));
267 }
268
269 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
270 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
271 }
272 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
273 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
274 }
275
276 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
277 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
278 }
279 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
280 ubfm(Rd, Rn, lsb , (lsb + width - 1));
281 }
282
283 inline void asrw(Register Rd, Register Rn, unsigned imm) {
284 sbfmw(Rd, Rn, imm, 31);
285 }
286
287 inline void asr(Register Rd, Register Rn, unsigned imm) {
288 sbfm(Rd, Rn, imm, 63);
289 }
290
291 inline void lslw(Register Rd, Register Rn, unsigned imm) {
292 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
293 }
294
295 inline void lsl(Register Rd, Register Rn, unsigned imm) {
296 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
297 }
298
299 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
300 ubfmw(Rd, Rn, imm, 31);
301 }
302
303 inline void lsr(Register Rd, Register Rn, unsigned imm) {
304 ubfm(Rd, Rn, imm, 63);
305 }
306
307 inline void rorw(Register Rd, Register Rn, unsigned imm) {
308 extrw(Rd, Rn, Rn, imm);
309 }
310
311 inline void ror(Register Rd, Register Rn, unsigned imm) {
312 extr(Rd, Rn, Rn, imm);
313 }
314
315 inline void sxtbw(Register Rd, Register Rn) {
316 sbfmw(Rd, Rn, 0, 7);
317 }
318 inline void sxthw(Register Rd, Register Rn) {
319 sbfmw(Rd, Rn, 0, 15);
320 }
321 inline void sxtb(Register Rd, Register Rn) {
322 sbfm(Rd, Rn, 0, 7);
323 }
324 inline void sxth(Register Rd, Register Rn) {
325 sbfm(Rd, Rn, 0, 15);
326 }
327 inline void sxtw(Register Rd, Register Rn) {
328 sbfm(Rd, Rn, 0, 31);
329 }
330
331 inline void uxtbw(Register Rd, Register Rn) {
332 ubfmw(Rd, Rn, 0, 7);
333 }
334 inline void uxthw(Register Rd, Register Rn) {
335 ubfmw(Rd, Rn, 0, 15);
336 }
337 inline void uxtb(Register Rd, Register Rn) {
338 ubfm(Rd, Rn, 0, 7);
339 }
340 inline void uxth(Register Rd, Register Rn) {
341 ubfm(Rd, Rn, 0, 15);
342 }
343 inline void uxtw(Register Rd, Register Rn) {
344 ubfm(Rd, Rn, 0, 31);
345 }
346
347 inline void cmnw(Register Rn, Register Rm) {
348 addsw(zr, Rn, Rm);
349 }
350 inline void cmn(Register Rn, Register Rm) {
351 adds(zr, Rn, Rm);
352 }
353
354 inline void cmpw(Register Rn, Register Rm) {
355 subsw(zr, Rn, Rm);
356 }
357 inline void cmp(Register Rn, Register Rm) {
358 subs(zr, Rn, Rm);
359 }
360
361 inline void negw(Register Rd, Register Rn) {
362 subw(Rd, zr, Rn);
363 }
364
365 inline void neg(Register Rd, Register Rn) {
366 sub(Rd, zr, Rn);
367 }
368
369 inline void negsw(Register Rd, Register Rn) {
370 subsw(Rd, zr, Rn);
371 }
372
373 inline void negs(Register Rd, Register Rn) {
374 subs(Rd, zr, Rn);
375 }
376
377 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
378 addsw(zr, Rn, Rm, kind, shift);
379 }
380 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
381 adds(zr, Rn, Rm, kind, shift);
382 }
383
384 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
385 subsw(zr, Rn, Rm, kind, shift);
386 }
387 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
388 subs(zr, Rn, Rm, kind, shift);
389 }
390
391 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
392 subw(Rd, zr, Rn, kind, shift);
393 }
394
395 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
396 sub(Rd, zr, Rn, kind, shift);
397 }
398
399 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
400 subsw(Rd, zr, Rn, kind, shift);
401 }
402
403 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
404 subs(Rd, zr, Rn, kind, shift);
405 }
406
407 inline void mnegw(Register Rd, Register Rn, Register Rm) {
408 msubw(Rd, Rn, Rm, zr);
409 }
410 inline void mneg(Register Rd, Register Rn, Register Rm) {
411 msub(Rd, Rn, Rm, zr);
412 }
413
414 inline void mulw(Register Rd, Register Rn, Register Rm) {
415 maddw(Rd, Rn, Rm, zr);
416 }
417 inline void mul(Register Rd, Register Rn, Register Rm) {
418 madd(Rd, Rn, Rm, zr);
419 }
420
421 inline void smnegl(Register Rd, Register Rn, Register Rm) {
422 smsubl(Rd, Rn, Rm, zr);
423 }
424 inline void smull(Register Rd, Register Rn, Register Rm) {
425 smaddl(Rd, Rn, Rm, zr);
426 }
427
428 inline void umnegl(Register Rd, Register Rn, Register Rm) {
429 umsubl(Rd, Rn, Rm, zr);
430 }
431 inline void umull(Register Rd, Register Rn, Register Rm) {
432 umaddl(Rd, Rn, Rm, zr);
433 }
434
435 #define WRAP(INSN) \
436 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
437 if (VM_Version::supports_a53mac() && Ra != zr) \
438 nop(); \
439 Assembler::INSN(Rd, Rn, Rm, Ra); \
440 }
441
442 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
443 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
444 #undef WRAP
445
446
447 // macro assembly operations needed for aarch64
448
449 public:
450
451 enum FpPushPopMode {
452 PushPopFull,
453 PushPopSVE,
454 PushPopNeon,
455 PushPopFp
456 };
457
458 // first two private routines for loading 32 bit or 64 bit constants
459 private:
460
461 void mov_immediate64(Register dst, uint64_t imm64);
462 void mov_immediate32(Register dst, uint32_t imm32);
463
464 int push(unsigned int bitset, Register stack);
465 int pop(unsigned int bitset, Register stack);
466
467 int push_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
468 int pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
469
470 int push_p(unsigned int bitset, Register stack);
471 int pop_p(unsigned int bitset, Register stack);
472
473 void mov(Register dst, Address a);
474
475 public:
476
477 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
478 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
479
480 void push_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) push_fp(regs.bits(), stack, mode); }
481 void pop_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) pop_fp(regs.bits(), stack, mode); }
482
483 static RegSet call_clobbered_gp_registers();
484
485 void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
486 void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
487
488 // Push and pop everything that might be clobbered by a native
489 // runtime call except rscratch1 and rscratch2. (They are always
490 // scratch, so we don't have to protect them.) Only save the lower
491 // 64 bits of each vector register. Additional registers can be excluded
492 // in a passed RegSet.
493 void push_call_clobbered_registers_except(RegSet exclude);
494 void pop_call_clobbered_registers_except(RegSet exclude);
495
496 void push_call_clobbered_registers() {
497 push_call_clobbered_registers_except(RegSet());
498 }
499 void pop_call_clobbered_registers() {
500 pop_call_clobbered_registers_except(RegSet());
501 }
502
503
504 // now mov instructions for loading absolute addresses and 32 or
505 // 64 bit integers
506
507 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
508
509 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
510 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); }
511
512 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); }
513
514 void mov(Register dst, RegisterOrConstant src) {
515 if (src.is_register())
516 mov(dst, src.as_register());
517 else
518 mov(dst, src.as_constant());
519 }
520
521 void movptr(Register r, uintptr_t imm64);
522
523 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
524
525 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
526 orr(Vd, T, Vn, Vn);
527 }
528
529 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
530 fcvtsh(tmp, src);
531 smov(dst, tmp, H, 0);
532 }
533
534 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
535 mov(tmp, H, 0, src);
536 fcvths(dst, tmp);
537 }
538
539 // Generalized Test Bit And Branch, including a "far" variety which
540 // spans more than 32KiB.
541 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
542 assert(cond == EQ || cond == NE, "must be");
543
544 if (isfar)
545 cond = ~cond;
546
547 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
548 if (cond == Assembler::EQ)
549 branch = &Assembler::tbz;
550 else
551 branch = &Assembler::tbnz;
552
553 if (isfar) {
554 Label L;
555 (this->*branch)(Rt, bitpos, L);
556 b(dest);
557 bind(L);
558 } else {
559 (this->*branch)(Rt, bitpos, dest);
560 }
561 }
562
563 // macro instructions for accessing and updating floating point
564 // status register
565 //
566 // FPSR : op1 == 011
567 // CRn == 0100
568 // CRm == 0100
569 // op2 == 001
570
571 inline void get_fpsr(Register reg)
572 {
573 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
574 }
575
576 inline void set_fpsr(Register reg)
577 {
578 msr(0b011, 0b0100, 0b0100, 0b001, reg);
579 }
580
581 inline void clear_fpsr()
582 {
583 msr(0b011, 0b0100, 0b0100, 0b001, zr);
584 }
585
586 // FPCR : op1 == 011
587 // CRn == 0100
588 // CRm == 0100
589 // op2 == 000
590
591 inline void get_fpcr(Register reg) {
592 mrs(0b11, 0b0100, 0b0100, 0b000, reg);
593 }
594
595 inline void set_fpcr(Register reg) {
596 msr(0b011, 0b0100, 0b0100, 0b000, reg);
597 }
598
599 // DCZID_EL0: op1 == 011
600 // CRn == 0000
601 // CRm == 0000
602 // op2 == 111
603 inline void get_dczid_el0(Register reg)
604 {
605 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
606 }
607
608 // CTR_EL0: op1 == 011
609 // CRn == 0000
610 // CRm == 0000
611 // op2 == 001
612 inline void get_ctr_el0(Register reg)
613 {
614 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
615 }
616
617 inline void get_nzcv(Register reg) {
618 mrs(0b011, 0b0100, 0b0010, 0b000, reg);
619 }
620
621 inline void set_nzcv(Register reg) {
622 msr(0b011, 0b0100, 0b0010, 0b000, reg);
623 }
624
625 // idiv variant which deals with MINLONG as dividend and -1 as divisor
626 int corrected_idivl(Register result, Register ra, Register rb,
627 bool want_remainder, Register tmp = rscratch1);
628 int corrected_idivq(Register result, Register ra, Register rb,
629 bool want_remainder, Register tmp = rscratch1);
630
631 // Support for null-checks
632 //
633 // Generates code that causes a null OS exception if the content of reg is null.
634 // If the accessed location is M[reg + offset] and the offset is known, provide the
635 // offset. No explicit code generation is needed if the offset is within a certain
636 // range (0 <= offset <= page_size).
637
638 virtual void null_check(Register reg, int offset = -1);
639 static bool needs_explicit_null_check(intptr_t offset);
640 static bool uses_implicit_null_check(void* address);
641
642 static address target_addr_for_insn(address insn_addr, unsigned insn);
643 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
644 static address target_addr_for_insn(address insn_addr) {
645 unsigned insn = *(unsigned*)insn_addr;
646 return target_addr_for_insn(insn_addr, insn);
647 }
648 static address target_addr_for_insn_or_null(address insn_addr) {
649 unsigned insn = *(unsigned*)insn_addr;
650 return target_addr_for_insn_or_null(insn_addr, insn);
651 }
652
653 // Required platform-specific helpers for Label::patch_instructions.
654 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
655 static int pd_patch_instruction_size(address branch, address target);
656 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
657 pd_patch_instruction_size(branch, target);
658 }
659 static address pd_call_destination(address branch) {
660 return target_addr_for_insn(branch);
661 }
662 #ifndef PRODUCT
663 static void pd_print_patched_instruction(address branch);
664 #endif
665
666 static int patch_oop(address insn_addr, address o);
667 static int patch_narrow_klass(address insn_addr, narrowKlass n);
668
669 // Return whether code is emitted to a scratch blob.
670 virtual bool in_scratch_emit_size() {
671 return false;
672 }
673 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
674 static int max_trampoline_stub_size();
675 void emit_static_call_stub();
676 static int static_call_stub_size();
677
678 // The following 4 methods return the offset of the appropriate move instruction
679
680 // Support for fast byte/short loading with zero extension (depending on particular CPU)
681 int load_unsigned_byte(Register dst, Address src);
682 int load_unsigned_short(Register dst, Address src);
683
684 // Support for fast byte/short loading with sign extension (depending on particular CPU)
685 int load_signed_byte(Register dst, Address src);
686 int load_signed_short(Register dst, Address src);
687
688 int load_signed_byte32(Register dst, Address src);
689 int load_signed_short32(Register dst, Address src);
690
691 // Support for sign-extension (hi:lo = extend_sign(lo))
692 void extend_sign(Register hi, Register lo);
693
694 // Load and store values by size and signed-ness
695 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
696 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
697
698 // Support for inc/dec with optimal instruction selection depending on value
699
700 // x86_64 aliases an unqualified register/address increment and
701 // decrement to call incrementq and decrementq but also supports
702 // explicitly sized calls to incrementq/decrementq or
703 // incrementl/decrementl
704
705 // for aarch64 the proper convention would be to use
706 // increment/decrement for 64 bit operations and
707 // incrementw/decrementw for 32 bit operations. so when porting
708 // x86_64 code we can leave calls to increment/decrement as is,
709 // replace incrementq/decrementq with increment/decrement and
710 // replace incrementl/decrementl with incrementw/decrementw.
711
712 // n.b. increment/decrement calls with an Address destination will
713 // need to use a scratch register to load the value to be
714 // incremented. increment/decrement calls which add or subtract a
715 // constant value greater than 2^12 will need to use a 2nd scratch
716 // register to hold the constant. so, a register increment/decrement
717 // may trash rscratch2 and an address increment/decrement trash
718 // rscratch and rscratch2
719
720 void decrementw(Address dst, int value = 1);
721 void decrementw(Register reg, int value = 1);
722
723 void decrement(Register reg, int value = 1);
724 void decrement(Address dst, int value = 1);
725
726 void incrementw(Address dst, int value = 1);
727 void incrementw(Register reg, int value = 1);
728
729 void increment(Register reg, int value = 1);
730 void increment(Address dst, int value = 1);
731
732
733 // Alignment
734 void align(int modulus);
735 void align(int modulus, int target);
736
737 // nop
738 void post_call_nop();
739
740 // Stack frame creation/removal
741 void enter(bool strip_ret_addr = false);
742 void leave();
743
744 // ROP Protection
745 void protect_return_address();
746 void protect_return_address(Register return_reg);
747 void authenticate_return_address();
748 void authenticate_return_address(Register return_reg);
749 void strip_return_address();
750 void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
751
752 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
753 // The pointer will be loaded into the thread register.
754 void get_thread(Register thread);
755
756 // support for argument shuffling
757 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
758 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
759 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
760 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
761 void object_move(
762 OopMap* map,
763 int oop_handle_offset,
764 int framesize_in_slots,
765 VMRegPair src,
766 VMRegPair dst,
767 bool is_receiver,
768 int* receiver_offset);
769
770
771 // Support for VM calls
772 //
773 // It is imperative that all calls into the VM are handled via the call_VM macros.
774 // They make sure that the stack linkage is setup correctly. call_VM's correspond
775 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
776
777
778 void call_VM(Register oop_result,
779 address entry_point,
780 bool check_exceptions = true);
781 void call_VM(Register oop_result,
782 address entry_point,
783 Register arg_1,
784 bool check_exceptions = true);
785 void call_VM(Register oop_result,
786 address entry_point,
787 Register arg_1, Register arg_2,
788 bool check_exceptions = true);
789 void call_VM(Register oop_result,
790 address entry_point,
791 Register arg_1, Register arg_2, Register arg_3,
792 bool check_exceptions = true);
793
794 // Overloadings with last_Java_sp
795 void call_VM(Register oop_result,
796 Register last_java_sp,
797 address entry_point,
798 int number_of_arguments = 0,
799 bool check_exceptions = true);
800 void call_VM(Register oop_result,
801 Register last_java_sp,
802 address entry_point,
803 Register arg_1, bool
804 check_exceptions = true);
805 void call_VM(Register oop_result,
806 Register last_java_sp,
807 address entry_point,
808 Register arg_1, Register arg_2,
809 bool check_exceptions = true);
810 void call_VM(Register oop_result,
811 Register last_java_sp,
812 address entry_point,
813 Register arg_1, Register arg_2, Register arg_3,
814 bool check_exceptions = true);
815
816 void get_vm_result (Register oop_result, Register thread);
817 void get_vm_result_2(Register metadata_result, Register thread);
818
819 // These always tightly bind to MacroAssembler::call_VM_base
820 // bypassing the virtual implementation
821 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
822 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
823 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
824 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
825 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
826
827 void call_VM_leaf(address entry_point,
828 int number_of_arguments = 0);
829 void call_VM_leaf(address entry_point,
830 Register arg_1);
831 void call_VM_leaf(address entry_point,
832 Register arg_1, Register arg_2);
833 void call_VM_leaf(address entry_point,
834 Register arg_1, Register arg_2, Register arg_3);
835
836 // These always tightly bind to MacroAssembler::call_VM_leaf_base
837 // bypassing the virtual implementation
838 void super_call_VM_leaf(address entry_point);
839 void super_call_VM_leaf(address entry_point, Register arg_1);
840 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
841 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
842 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
843
844 // last Java Frame (fills frame anchor)
845 void set_last_Java_frame(Register last_java_sp,
846 Register last_java_fp,
847 address last_java_pc,
848 Register scratch);
849
850 void set_last_Java_frame(Register last_java_sp,
851 Register last_java_fp,
852 Label &last_java_pc,
853 Register scratch);
854
855 void set_last_Java_frame(Register last_java_sp,
856 Register last_java_fp,
857 Register last_java_pc,
858 Register scratch);
859
860 void reset_last_Java_frame(Register thread);
861
862 // thread in the default location (rthread)
863 void reset_last_Java_frame(bool clear_fp);
864
865 // Stores
866 void store_check(Register obj); // store check for obj - register is destroyed afterwards
867 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
868
869 void resolve_jobject(Register value, Register tmp1, Register tmp2);
870 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
871
872 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
873 void c2bool(Register x);
874
875 void load_method_holder_cld(Register rresult, Register rmethod);
876 void load_method_holder(Register holder, Register method);
877
878 // oop manipulations
879 void load_narrow_klass_compact(Register dst, Register src);
880 void load_klass(Register dst, Register src);
881 void store_klass(Register dst, Register src);
882 void cmp_klass(Register obj, Register klass, Register tmp);
883 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
884
885 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
886 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
887 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
888
889 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
890 Register tmp1, Register tmp2);
891
892 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
893 Register tmp1, Register tmp2, Register tmp3);
894
895 void load_heap_oop(Register dst, Address src, Register tmp1,
896 Register tmp2, DecoratorSet decorators = 0);
897
898 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
899 Register tmp2, DecoratorSet decorators = 0);
900 void store_heap_oop(Address dst, Register val, Register tmp1,
901 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
902
903 // currently unimplemented
904 // Used for storing null. All other oop constants should be
905 // stored using routines that take a jobject.
906 void store_heap_oop_null(Address dst);
907
908 void store_klass_gap(Register dst, Register src);
909
910 // This dummy is to prevent a call to store_heap_oop from
911 // converting a zero (like null) into a Register by giving
912 // the compiler two choices it can't resolve
913
914 void store_heap_oop(Address dst, void* dummy);
915
916 void encode_heap_oop(Register d, Register s);
917 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
918 void decode_heap_oop(Register d, Register s);
919 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
920 void encode_heap_oop_not_null(Register r);
921 void decode_heap_oop_not_null(Register r);
922 void encode_heap_oop_not_null(Register dst, Register src);
923 void decode_heap_oop_not_null(Register dst, Register src);
924
925 void set_narrow_oop(Register dst, jobject obj);
926
927 void encode_klass_not_null(Register r);
928 void decode_klass_not_null(Register r);
929 void encode_klass_not_null(Register dst, Register src);
930 void decode_klass_not_null(Register dst, Register src);
931
932 void set_narrow_klass(Register dst, Klass* k);
933
934 // if heap base register is used - reinit it with the correct value
935 void reinit_heapbase();
936
937 DEBUG_ONLY(void verify_heapbase(const char* msg);)
938
939 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
940 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
941 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
942 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
943
944 void push_cont_fastpath(Register java_thread = rthread);
945 void pop_cont_fastpath(Register java_thread = rthread);
946
947 void inc_held_monitor_count(Register tmp);
948 void dec_held_monitor_count(Register tmp);
949
950 // Round up to a power of two
951 void round_to(Register reg, int modulus);
952
953 // java.lang.Math::round intrinsics
954 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
955 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
956
957 // allocation
958 void tlab_allocate(
959 Register obj, // result: pointer to object after successful allocation
960 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
961 int con_size_in_bytes, // object size in bytes if known at compile time
962 Register t1, // temp register
963 Register t2, // temp register
964 Label& slow_case // continuation point if fast allocation fails
965 );
966 void verify_tlab();
967
968 // interface method calling
969 void lookup_interface_method(Register recv_klass,
970 Register intf_klass,
971 RegisterOrConstant itable_index,
972 Register method_result,
973 Register scan_temp,
974 Label& no_such_interface,
975 bool return_method = true);
976
977 void lookup_interface_method_stub(Register recv_klass,
978 Register holder_klass,
979 Register resolved_klass,
980 Register method_result,
981 Register temp_reg,
982 Register temp_reg2,
983 int itable_index,
984 Label& L_no_such_interface);
985
986 // virtual method calling
987 // n.b. x86 allows RegisterOrConstant for vtable_index
988 void lookup_virtual_method(Register recv_klass,
989 RegisterOrConstant vtable_index,
990 Register method_result);
991
992 // Test sub_klass against super_klass, with fast and slow paths.
993
994 // The fast path produces a tri-state answer: yes / no / maybe-slow.
995 // One of the three labels can be null, meaning take the fall-through.
996 // If super_check_offset is -1, the value is loaded up from super_klass.
997 // No registers are killed, except temp_reg.
998 void check_klass_subtype_fast_path(Register sub_klass,
999 Register super_klass,
1000 Register temp_reg,
1001 Label* L_success,
1002 Label* L_failure,
1003 Label* L_slow_path,
1004 Register super_check_offset = noreg);
1005
1006 // The rest of the type check; must be wired to a corresponding fast path.
1007 // It does not repeat the fast path logic, so don't use it standalone.
1008 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1009 // Updates the sub's secondary super cache as necessary.
1010 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1011 void check_klass_subtype_slow_path(Register sub_klass,
1012 Register super_klass,
1013 Register temp_reg,
1014 Register temp2_reg,
1015 Label* L_success,
1016 Label* L_failure,
1017 bool set_cond_codes = false);
1018
1019 void check_klass_subtype_slow_path_linear(Register sub_klass,
1020 Register super_klass,
1021 Register temp_reg,
1022 Register temp2_reg,
1023 Label* L_success,
1024 Label* L_failure,
1025 bool set_cond_codes = false);
1026
1027 void check_klass_subtype_slow_path_table(Register sub_klass,
1028 Register super_klass,
1029 Register temp_reg,
1030 Register temp2_reg,
1031 Register temp3_reg,
1032 Register result_reg,
1033 FloatRegister vtemp_reg,
1034 Label* L_success,
1035 Label* L_failure,
1036 bool set_cond_codes = false);
1037
1038 // If r is valid, return r.
1039 // If r is invalid, remove a register r2 from available_regs, add r2
1040 // to regs_to_push, then return r2.
1041 Register allocate_if_noreg(const Register r,
1042 RegSetIterator<Register> &available_regs,
1043 RegSet ®s_to_push);
1044
1045 // Secondary subtype checking
1046 void lookup_secondary_supers_table_var(Register sub_klass,
1047 Register r_super_klass,
1048 Register temp1,
1049 Register temp2,
1050 Register temp3,
1051 FloatRegister vtemp,
1052 Register result,
1053 Label *L_success);
1054
1055
1056 // As above, but with a constant super_klass.
1057 // The result is in Register result, not the condition codes.
1058 bool lookup_secondary_supers_table_const(Register r_sub_klass,
1059 Register r_super_klass,
1060 Register temp1,
1061 Register temp2,
1062 Register temp3,
1063 FloatRegister vtemp,
1064 Register result,
1065 u1 super_klass_slot,
1066 bool stub_is_near = false);
1067
1068 void verify_secondary_supers_table(Register r_sub_klass,
1069 Register r_super_klass,
1070 Register temp1,
1071 Register temp2,
1072 Register result);
1073
1074 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
1075 Register r_array_base,
1076 Register r_array_index,
1077 Register r_bitmap,
1078 Register temp1,
1079 Register result,
1080 bool is_stub = true);
1081
1082 // Simplified, combined version, good for typical uses.
1083 // Falls through on failure.
1084 void check_klass_subtype(Register sub_klass,
1085 Register super_klass,
1086 Register temp_reg,
1087 Label& L_success);
1088
1089 void clinit_barrier(Register klass,
1090 Register thread,
1091 Label* L_fast_path = nullptr,
1092 Label* L_slow_path = nullptr);
1093
1094 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1095
1096 void verify_sve_vector_length(Register tmp = rscratch1);
1097 void reinitialize_ptrue() {
1098 if (UseSVE > 0) {
1099 sve_ptrue(ptrue, B);
1100 }
1101 }
1102 void verify_ptrue();
1103
1104 // Debugging
1105
1106 // only if +VerifyOops
1107 void _verify_oop(Register reg, const char* s, const char* file, int line);
1108 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1109
1110 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1111 if (VerifyOops) {
1112 _verify_oop(reg, s, file, line);
1113 }
1114 }
1115 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1116 if (VerifyOops) {
1117 _verify_oop_addr(reg, s, file, line);
1118 }
1119 }
1120
1121 // TODO: verify method and klass metadata (compare against vptr?)
1122 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1123 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1124
1125 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1126 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1127 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1128 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1129 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1130
1131 // Restore cpu control state after JNI call
1132 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2);
1133
1134 // prints msg, dumps registers and stops execution
1135 void stop(const char* msg);
1136
1137 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1138
1139 void untested() { stop("untested"); }
1140
1141 void unimplemented(const char* what = "");
1142
1143 void should_not_reach_here() { stop("should not reach here"); }
1144
1145 void _assert_asm(Condition cc, const char* msg);
1146 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1147 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1148
1149 // Stack overflow checking
1150 void bang_stack_with_offset(int offset) {
1151 // stack grows down, caller passes positive offset
1152 assert(offset > 0, "must bang with negative offset");
1153 sub(rscratch2, sp, offset);
1154 str(zr, Address(rscratch2));
1155 }
1156
1157 // Writes to stack successive pages until offset reached to check for
1158 // stack overflow + shadow pages. Also, clobbers tmp
1159 void bang_stack_size(Register size, Register tmp);
1160
1161 // Check for reserved stack access in method being exited (for JIT)
1162 void reserved_stack_check();
1163
1164 // Arithmetics
1165
1166 void addptr(const Address &dst, int32_t src);
1167 void cmpptr(Register src1, Address src2);
1168
1169 void cmpoop(Register obj1, Register obj2);
1170
1171 // Various forms of CAS
1172
1173 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1174 Label &succeed, Label *fail);
1175 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1176 Label &succeed, Label *fail);
1177
1178 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1179 Label &succeed, Label *fail);
1180
1181 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1182 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1183 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1184 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1185
1186 void atomic_xchg(Register prev, Register newv, Register addr);
1187 void atomic_xchgw(Register prev, Register newv, Register addr);
1188 void atomic_xchgl(Register prev, Register newv, Register addr);
1189 void atomic_xchglw(Register prev, Register newv, Register addr);
1190 void atomic_xchgal(Register prev, Register newv, Register addr);
1191 void atomic_xchgalw(Register prev, Register newv, Register addr);
1192
1193 void orptr(Address adr, RegisterOrConstant src) {
1194 ldr(rscratch1, adr);
1195 if (src.is_register())
1196 orr(rscratch1, rscratch1, src.as_register());
1197 else
1198 orr(rscratch1, rscratch1, src.as_constant());
1199 str(rscratch1, adr);
1200 }
1201
1202 // A generic CAS; success or failure is in the EQ flag.
1203 // Clobbers rscratch1
1204 void cmpxchg(Register addr, Register expected, Register new_val,
1205 enum operand_size size,
1206 bool acquire, bool release, bool weak,
1207 Register result);
1208
1209 #ifdef ASSERT
1210 // Template short-hand support to clean-up after a failed call to trampoline
1211 // call generation (see trampoline_call() below), when a set of Labels must
1212 // be reset (before returning).
1213 template<typename Label, typename... More>
1214 void reset_labels(Label &lbl, More&... more) {
1215 lbl.reset(); reset_labels(more...);
1216 }
1217 template<typename Label>
1218 void reset_labels(Label &lbl) {
1219 lbl.reset();
1220 }
1221 #endif
1222
1223 private:
1224 void compare_eq(Register rn, Register rm, enum operand_size size);
1225
1226 public:
1227 // AArch64 OpenJDK uses four different types of calls:
1228 // - direct call: bl pc_relative_offset
1229 // This is the shortest and the fastest, but the offset has the range:
1230 // +/-128MB for the release build, +/-2MB for the debug build.
1231 //
1232 // - far call: adrp reg, pc_relative_offset; add; bl reg
1233 // This is longer than a direct call. The offset has
1234 // the range +/-4GB. As the code cache size is limited to 4GB,
1235 // far calls can reach anywhere in the code cache. If a jump is
1236 // needed rather than a call, a far jump 'b reg' can be used instead.
1237 // All instructions are embedded at a call site.
1238 //
1239 // - trampoline call:
1240 // This is only available in C1/C2-generated code (nmethod). It is a combination
1241 // of a direct call, which is used if the destination of a call is in range,
1242 // and a register-indirect call. It has the advantages of reaching anywhere in
1243 // the AArch64 address space and being patchable at runtime when the generated
1244 // code is being executed by other threads.
1245 //
1246 // [Main code section]
1247 // bl trampoline
1248 // [Stub code section]
1249 // trampoline:
1250 // ldr reg, pc + 8
1251 // br reg
1252 // <64-bit destination address>
1253 //
1254 // If the destination is in range when the generated code is moved to the code
1255 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1256 // is not used.
1257 // The optimization does not remove the trampoline from the stub section.
1258 // This is necessary because the trampoline may well be redirected later when
1259 // code is patched, and the new destination may not be reachable by a simple BR
1260 // instruction.
1261 //
1262 // - indirect call: move reg, address; blr reg
1263 // This too can reach anywhere in the address space, but it cannot be
1264 // patched while code is running, so it must only be modified at a safepoint.
1265 // This form of call is most suitable for targets at fixed addresses, which
1266 // will never be patched.
1267 //
1268 // The patching we do conforms to the "Concurrent modification and
1269 // execution of instructions" section of the Arm Architectural
1270 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1271 // or SVC instructions to be modified while another thread is
1272 // executing them.
1273 //
1274 // To patch a trampoline call when the BL can't reach, we first modify
1275 // the 64-bit destination address in the trampoline, then modify the
1276 // BL to point to the trampoline, then flush the instruction cache to
1277 // broadcast the change to all executing threads. See
1278 // NativeCall::set_destination_mt_safe for the details.
1279 //
1280 // There is a benign race in that the other thread might observe the
1281 // modified BL before it observes the modified 64-bit destination
1282 // address. That does not matter because the destination method has been
1283 // invalidated, so there will be a trap at its start.
1284 // For this to work, the destination address in the trampoline is
1285 // always updated, even if we're not using the trampoline.
1286
1287 // Emit a direct call if the entry address will always be in range,
1288 // otherwise a trampoline call.
1289 // Supported entry.rspec():
1290 // - relocInfo::runtime_call_type
1291 // - relocInfo::opt_virtual_call_type
1292 // - relocInfo::static_call_type
1293 // - relocInfo::virtual_call_type
1294 //
1295 // Return: the call PC or null if CodeCache is full.
1296 // Clobbers: rscratch1
1297 address trampoline_call(Address entry);
1298
1299 static bool far_branches() {
1300 return ReservedCodeCacheSize > branch_range;
1301 }
1302
1303 // Check if branches to the non nmethod section require a far jump
1304 static bool codestub_branch_needs_far_jump() {
1305 if (SCCache::is_on_for_write()) {
1306 // To calculate far_codestub_branch_size correctly.
1307 return true;
1308 }
1309 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1310 }
1311
1312 // Emit a direct call/jump if the entry address will always be in range,
1313 // otherwise a far call/jump.
1314 // The address must be inside the code cache.
1315 // Supported entry.rspec():
1316 // - relocInfo::external_word_type
1317 // - relocInfo::runtime_call_type
1318 // - relocInfo::none
1319 // In the case of a far call/jump, the entry address is put in the tmp register.
1320 // The tmp register is invalidated.
1321 //
1322 // Far_jump returns the amount of the emitted code.
1323 void far_call(Address entry, Register tmp = rscratch1);
1324 int far_jump(Address entry, Register tmp = rscratch1);
1325
1326 static int far_codestub_branch_size() {
1327 if (codestub_branch_needs_far_jump()) {
1328 return 3 * 4; // adrp, add, br
1329 } else {
1330 return 4;
1331 }
1332 }
1333
1334 // Emit the CompiledIC call idiom
1335 address ic_call(address entry, jint method_index = 0);
1336 static int ic_check_size();
1337 int ic_check(int end_alignment);
1338
1339 public:
1340
1341 // Data
1342
1343 void mov_metadata(Register dst, Metadata* obj);
1344 Address allocate_metadata_address(Metadata* obj);
1345 Address constant_oop_address(jobject obj);
1346
1347 void movoop(Register dst, jobject obj);
1348
1349 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1350 void kernel_crc32(Register crc, Register buf, Register len,
1351 Register table0, Register table1, Register table2, Register table3,
1352 Register tmp, Register tmp2, Register tmp3);
1353 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1354 void kernel_crc32c(Register crc, Register buf, Register len,
1355 Register table0, Register table1, Register table2, Register table3,
1356 Register tmp, Register tmp2, Register tmp3);
1357
1358 // Stack push and pop individual 64 bit registers
1359 void push(Register src);
1360 void pop(Register dst);
1361
1362 void repne_scan(Register addr, Register value, Register count,
1363 Register scratch);
1364 void repne_scanw(Register addr, Register value, Register count,
1365 Register scratch);
1366
1367 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1368 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1369
1370 // If a constant does not fit in an immediate field, generate some
1371 // number of MOV instructions and then perform the operation
1372 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1373 add_sub_imm_insn insn1,
1374 add_sub_reg_insn insn2, bool is32);
1375 // Separate vsn which sets the flags
1376 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1377 add_sub_imm_insn insn1,
1378 add_sub_reg_insn insn2, bool is32);
1379
1380 #define WRAP(INSN, is32) \
1381 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1382 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1383 } \
1384 \
1385 void INSN(Register Rd, Register Rn, Register Rm, \
1386 enum shift_kind kind, unsigned shift = 0) { \
1387 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1388 } \
1389 \
1390 void INSN(Register Rd, Register Rn, Register Rm) { \
1391 Assembler::INSN(Rd, Rn, Rm); \
1392 } \
1393 \
1394 void INSN(Register Rd, Register Rn, Register Rm, \
1395 ext::operation option, int amount = 0) { \
1396 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1397 }
1398
1399 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1400
1401 #undef WRAP
1402 #define WRAP(INSN, is32) \
1403 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1404 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1405 } \
1406 \
1407 void INSN(Register Rd, Register Rn, Register Rm, \
1408 enum shift_kind kind, unsigned shift = 0) { \
1409 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1410 } \
1411 \
1412 void INSN(Register Rd, Register Rn, Register Rm) { \
1413 Assembler::INSN(Rd, Rn, Rm); \
1414 } \
1415 \
1416 void INSN(Register Rd, Register Rn, Register Rm, \
1417 ext::operation option, int amount = 0) { \
1418 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1419 }
1420
1421 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1422
1423 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1424 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1425 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1426 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1427
1428 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1429
1430 void tableswitch(Register index, jint lowbound, jint highbound,
1431 Label &jumptable, Label &jumptable_end, int stride = 1) {
1432 adr(rscratch1, jumptable);
1433 subsw(rscratch2, index, lowbound);
1434 subsw(zr, rscratch2, highbound - lowbound);
1435 br(Assembler::HS, jumptable_end);
1436 add(rscratch1, rscratch1, rscratch2,
1437 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1438 br(rscratch1);
1439 }
1440
1441 // Form an address from base + offset in Rd. Rd may or may not
1442 // actually be used: you must use the Address that is returned. It
1443 // is up to you to ensure that the shift provided matches the size
1444 // of your data.
1445 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1446
1447 // Return true iff an address is within the 48-bit AArch64 address
1448 // space.
1449 bool is_valid_AArch64_address(address a) {
1450 return ((uint64_t)a >> 48) == 0;
1451 }
1452
1453 // Load the base of the cardtable byte map into reg.
1454 void load_byte_map_base(Register reg);
1455
1456 // Load a constant address in the AOT Runtime Constants area
1457 void load_aotrc_address(Register reg, address a);
1458
1459 // Prolog generator routines to support switch between x86 code and
1460 // generated ARM code
1461
1462 // routine to generate an x86 prolog for a stub function which
1463 // bootstraps into the generated ARM code which directly follows the
1464 // stub
1465 //
1466
1467 public:
1468
1469 void ldr_constant(Register dest, const Address &const_addr) {
1470 if (NearCpool) {
1471 ldr(dest, const_addr);
1472 } else {
1473 uint64_t offset;
1474 adrp(dest, InternalAddress(const_addr.target()), offset);
1475 ldr(dest, Address(dest, offset));
1476 }
1477 }
1478
1479 address read_polling_page(Register r, relocInfo::relocType rtype);
1480 void get_polling_page(Register dest, relocInfo::relocType rtype);
1481
1482 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1483 void update_byte_crc32(Register crc, Register val, Register table);
1484 void update_word_crc32(Register crc, Register v, Register tmp,
1485 Register table0, Register table1, Register table2, Register table3,
1486 bool upper = false);
1487
1488 address count_positives(Register ary1, Register len, Register result);
1489
1490 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1491 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1492
1493 // Ensure that the inline code and the stub use the same registers.
1494 #define ARRAYS_HASHCODE_REGISTERS \
1495 do { \
1496 assert(result == r0 && \
1497 ary == r1 && \
1498 cnt == r2 && \
1499 vdata0 == v3 && \
1500 vdata1 == v2 && \
1501 vdata2 == v1 && \
1502 vdata3 == v0 && \
1503 vmul0 == v4 && \
1504 vmul1 == v5 && \
1505 vmul2 == v6 && \
1506 vmul3 == v7 && \
1507 vpow == v12 && \
1508 vpowm == v13, "registers must match aarch64.ad"); \
1509 } while (0)
1510
1511 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1512
1513 void fill_words(Register base, Register cnt, Register value);
1514 address zero_words(Register base, uint64_t cnt);
1515 address zero_words(Register ptr, Register cnt);
1516 void zero_dcache_blocks(Register base, Register cnt);
1517
1518 static const int zero_words_block_size;
1519
1520 address byte_array_inflate(Register src, Register dst, Register len,
1521 FloatRegister vtmp1, FloatRegister vtmp2,
1522 FloatRegister vtmp3, Register tmp4);
1523
1524 void char_array_compress(Register src, Register dst, Register len,
1525 Register res,
1526 FloatRegister vtmp0, FloatRegister vtmp1,
1527 FloatRegister vtmp2, FloatRegister vtmp3,
1528 FloatRegister vtmp4, FloatRegister vtmp5);
1529
1530 void encode_iso_array(Register src, Register dst,
1531 Register len, Register res, bool ascii,
1532 FloatRegister vtmp0, FloatRegister vtmp1,
1533 FloatRegister vtmp2, FloatRegister vtmp3,
1534 FloatRegister vtmp4, FloatRegister vtmp5);
1535
1536 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1537 address pio2, address dsin_coef, address dcos_coef);
1538 private:
1539 // begin trigonometric functions support block
1540 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1541 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1542 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1543 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1544 // end trigonometric functions support block
1545 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1546 Register src1, Register src2);
1547 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1548 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1549 }
1550 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1551 Register y, Register y_idx, Register z,
1552 Register carry, Register product,
1553 Register idx, Register kdx);
1554 void multiply_128_x_128_loop(Register y, Register z,
1555 Register carry, Register carry2,
1556 Register idx, Register jdx,
1557 Register yz_idx1, Register yz_idx2,
1558 Register tmp, Register tmp3, Register tmp4,
1559 Register tmp7, Register product_hi);
1560 void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1561 Register len, Register tmp0, Register tmp1, Register tmp2,
1562 Register tmp3);
1563 void kernel_crc32_using_crc32(Register crc, Register buf,
1564 Register len, Register tmp0, Register tmp1, Register tmp2,
1565 Register tmp3);
1566 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1567 Register len, Register tmp0, Register tmp1, Register tmp2,
1568 Register tmp3);
1569 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1570 Register len, Register tmp0, Register tmp1, Register tmp2,
1571 Register tmp3);
1572 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1573 Register len, Register tmp0, Register tmp1, Register tmp2,
1574 size_t table_offset);
1575
1576 void ghash_modmul (FloatRegister result,
1577 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1578 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1579 FloatRegister t1, FloatRegister t2, FloatRegister t3);
1580 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1581 public:
1582 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1583 Register tmp0, Register tmp1, Register tmp2, Register tmp3,
1584 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1585 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1586 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1587 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1588 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1589 void ghash_multiply_wide(int index,
1590 FloatRegister result_lo, FloatRegister result_hi,
1591 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1592 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1593 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1594 FloatRegister p, FloatRegister z, FloatRegister t1);
1595 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1596 FloatRegister p, FloatRegister z, FloatRegister t1);
1597 void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1598 Register data, Register blocks, int unrolls);
1599
1600
1601 void aesenc_loadkeys(Register key, Register keylen);
1602 void aesecb_encrypt(Register from, Register to, Register keylen,
1603 FloatRegister data = v0, int unrolls = 1);
1604 void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1605 void aes_round(FloatRegister input, FloatRegister subkey);
1606
1607 // ChaCha20 functions support block
1608 void cc20_quarter_round(FloatRegister aVec, FloatRegister bVec,
1609 FloatRegister cVec, FloatRegister dVec, FloatRegister scratch,
1610 FloatRegister tbl);
1611 void cc20_shift_lane_org(FloatRegister bVec, FloatRegister cVec,
1612 FloatRegister dVec, bool colToDiag);
1613
1614 // Place an ISB after code may have been modified due to a safepoint.
1615 void safepoint_isb();
1616
1617 private:
1618 // Return the effective address r + (r1 << ext) + offset.
1619 // Uses rscratch2.
1620 Address offsetted_address(Register r, Register r1, Address::extend ext,
1621 int offset, int size);
1622
1623 private:
1624 // Returns an address on the stack which is reachable with a ldr/str of size
1625 // Uses rscratch2 if the address is not directly reachable
1626 Address spill_address(int size, int offset, Register tmp=rscratch2);
1627 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1628
1629 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1630
1631 // Check whether two loads/stores can be merged into ldp/stp.
1632 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1633
1634 // Merge current load/store with previous load/store into ldp/stp.
1635 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1636
1637 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1638 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1639
1640 public:
1641 void spill(Register Rx, bool is64, int offset) {
1642 if (is64) {
1643 str(Rx, spill_address(8, offset));
1644 } else {
1645 strw(Rx, spill_address(4, offset));
1646 }
1647 }
1648 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1649 str(Vx, T, spill_address(1 << (int)T, offset));
1650 }
1651
1652 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1653 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1654 }
1655 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1656 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1657 }
1658
1659 void unspill(Register Rx, bool is64, int offset) {
1660 if (is64) {
1661 ldr(Rx, spill_address(8, offset));
1662 } else {
1663 ldrw(Rx, spill_address(4, offset));
1664 }
1665 }
1666 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1667 ldr(Vx, T, spill_address(1 << (int)T, offset));
1668 }
1669
1670 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1671 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1672 }
1673 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1674 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1675 }
1676
1677 void spill_copy128(int src_offset, int dst_offset,
1678 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1679 if (src_offset < 512 && (src_offset & 7) == 0 &&
1680 dst_offset < 512 && (dst_offset & 7) == 0) {
1681 ldp(tmp1, tmp2, Address(sp, src_offset));
1682 stp(tmp1, tmp2, Address(sp, dst_offset));
1683 } else {
1684 unspill(tmp1, true, src_offset);
1685 spill(tmp1, true, dst_offset);
1686 unspill(tmp1, true, src_offset+8);
1687 spill(tmp1, true, dst_offset+8);
1688 }
1689 }
1690 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1691 int sve_vec_reg_size_in_bytes) {
1692 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1693 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1694 spill_copy128(src_offset, dst_offset);
1695 src_offset += 16;
1696 dst_offset += 16;
1697 }
1698 }
1699 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1700 int sve_predicate_reg_size_in_bytes) {
1701 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1702 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1703 reinitialize_ptrue();
1704 }
1705 void cache_wb(Address line);
1706 void cache_wbsync(bool is_pre);
1707
1708 // Code for java.lang.Thread::onSpinWait() intrinsic.
1709 void spin_wait();
1710
1711 void lightweight_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow);
1712 void lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow);
1713
1714 private:
1715 // Check the current thread doesn't need a cross modify fence.
1716 void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1717
1718 };
1719
1720 #ifdef ASSERT
1721 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1722 #endif
1723
1724 struct tableswitch {
1725 Register _reg;
1726 int _insn_index; jint _first_key; jint _last_key;
1727 Label _after;
1728 Label _branches;
1729 };
1730
1731 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP