1450     add(rscratch1, rscratch1, rscratch2,
1451         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1452     br(rscratch1);
1453   }
1454 
1455   // Form an address from base + offset in Rd.  Rd may or may not
1456   // actually be used: you must use the Address that is returned.  It
1457   // is up to you to ensure that the shift provided matches the size
1458   // of your data.
1459   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1460 
1461   // Return true iff an address is within the 48-bit AArch64 address
1462   // space.
1463   bool is_valid_AArch64_address(address a) {
1464     return ((uint64_t)a >> 48) == 0;
1465   }
1466 
1467   // Load the base of the cardtable byte map into reg.
1468   void load_byte_map_base(Register reg);
1469 



1470   // Prolog generator routines to support switch between x86 code and
1471   // generated ARM code
1472 
1473   // routine to generate an x86 prolog for a stub function which
1474   // bootstraps into the generated ARM code which directly follows the
1475   // stub
1476   //
1477 
1478   public:
1479 
1480   address read_polling_page(Register r, relocInfo::relocType rtype);
1481   void get_polling_page(Register dest, relocInfo::relocType rtype);
1482 
1483   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1484   void update_byte_crc32(Register crc, Register val, Register table);
1485   void update_word_crc32(Register crc, Register v, Register tmp,
1486         Register table0, Register table1, Register table2, Register table3,
1487         bool upper = false);
1488 
1489   address count_positives(Register ary1, Register len, Register result);

1450     add(rscratch1, rscratch1, rscratch2,
1451         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1452     br(rscratch1);
1453   }
1454 
1455   // Form an address from base + offset in Rd.  Rd may or may not
1456   // actually be used: you must use the Address that is returned.  It
1457   // is up to you to ensure that the shift provided matches the size
1458   // of your data.
1459   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1460 
1461   // Return true iff an address is within the 48-bit AArch64 address
1462   // space.
1463   bool is_valid_AArch64_address(address a) {
1464     return ((uint64_t)a >> 48) == 0;
1465   }
1466 
1467   // Load the base of the cardtable byte map into reg.
1468   void load_byte_map_base(Register reg);
1469 
1470   // Load a constant address in the AOT Runtime Constants area
1471   void load_aotrc_address(Register reg, address a);
1472 
1473   // Prolog generator routines to support switch between x86 code and
1474   // generated ARM code
1475 
1476   // routine to generate an x86 prolog for a stub function which
1477   // bootstraps into the generated ARM code which directly follows the
1478   // stub
1479   //
1480 
1481   public:
1482 
1483   address read_polling_page(Register r, relocInfo::relocType rtype);
1484   void get_polling_page(Register dest, relocInfo::relocType rtype);
1485 
1486   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1487   void update_byte_crc32(Register crc, Register val, Register table);
1488   void update_word_crc32(Register crc, Register v, Register tmp,
1489         Register table0, Register table1, Register table2, Register table3,
1490         bool upper = false);
1491 
1492   address count_positives(Register ary1, Register len, Register result);