693 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
694 pd_patch_instruction_size(branch, target);
695 }
696 static address pd_call_destination(address branch) {
697 return target_addr_for_insn(branch);
698 }
699 #ifndef PRODUCT
700 static void pd_print_patched_instruction(address branch);
701 #endif
702
703 static int patch_oop(address insn_addr, address o);
704 static int patch_narrow_klass(address insn_addr, narrowKlass n);
705
706 // Return whether code is emitted to a scratch blob.
707 virtual bool in_scratch_emit_size() {
708 return false;
709 }
710 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
711 static int max_trampoline_stub_size();
712 void emit_static_call_stub();
713 static int static_call_stub_size();
714
715 // The following 4 methods return the offset of the appropriate move instruction
716
717 // Support for fast byte/short loading with zero extension (depending on particular CPU)
718 int load_unsigned_byte(Register dst, Address src);
719 int load_unsigned_short(Register dst, Address src);
720
721 // Support for fast byte/short loading with sign extension (depending on particular CPU)
722 int load_signed_byte(Register dst, Address src);
723 int load_signed_short(Register dst, Address src);
724
725 int load_signed_byte32(Register dst, Address src);
726 int load_signed_short32(Register dst, Address src);
727
728 // Support for sign-extension (hi:lo = extend_sign(lo))
729 void extend_sign(Register hi, Register lo);
730
731 // Load and store values by size and signed-ness
732 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
733 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
1478 add(rscratch1, rscratch1, rscratch2,
1479 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1480 br(rscratch1);
1481 }
1482
1483 // Form an address from base + offset in Rd. Rd may or may not
1484 // actually be used: you must use the Address that is returned. It
1485 // is up to you to ensure that the shift provided matches the size
1486 // of your data.
1487 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1488
1489 // Return true iff an address is within the 48-bit AArch64 address
1490 // space.
1491 bool is_valid_AArch64_address(address a) {
1492 return ((uint64_t)a >> 48) == 0;
1493 }
1494
1495 // Load the base of the cardtable byte map into reg.
1496 void load_byte_map_base(Register reg);
1497
1498 // Prolog generator routines to support switch between x86 code and
1499 // generated ARM code
1500
1501 // routine to generate an x86 prolog for a stub function which
1502 // bootstraps into the generated ARM code which directly follows the
1503 // stub
1504 //
1505
1506 public:
1507
1508 address read_polling_page(Register r, relocInfo::relocType rtype);
1509 void get_polling_page(Register dest, relocInfo::relocType rtype);
1510
1511 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1512 void update_byte_crc32(Register crc, Register val, Register table);
1513 void update_word_crc32(Register crc, Register v, Register tmp,
1514 Register table0, Register table1, Register table2, Register table3,
1515 bool upper = false);
1516
1517 address count_positives(Register ary1, Register len, Register result);
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693 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
694 pd_patch_instruction_size(branch, target);
695 }
696 static address pd_call_destination(address branch) {
697 return target_addr_for_insn(branch);
698 }
699 #ifndef PRODUCT
700 static void pd_print_patched_instruction(address branch);
701 #endif
702
703 static int patch_oop(address insn_addr, address o);
704 static int patch_narrow_klass(address insn_addr, narrowKlass n);
705
706 // Return whether code is emitted to a scratch blob.
707 virtual bool in_scratch_emit_size() {
708 return false;
709 }
710 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
711 static int max_trampoline_stub_size();
712 void emit_static_call_stub();
713 static int max_static_call_stub_size();
714
715 // The following 4 methods return the offset of the appropriate move instruction
716
717 // Support for fast byte/short loading with zero extension (depending on particular CPU)
718 int load_unsigned_byte(Register dst, Address src);
719 int load_unsigned_short(Register dst, Address src);
720
721 // Support for fast byte/short loading with sign extension (depending on particular CPU)
722 int load_signed_byte(Register dst, Address src);
723 int load_signed_short(Register dst, Address src);
724
725 int load_signed_byte32(Register dst, Address src);
726 int load_signed_short32(Register dst, Address src);
727
728 // Support for sign-extension (hi:lo = extend_sign(lo))
729 void extend_sign(Register hi, Register lo);
730
731 // Load and store values by size and signed-ness
732 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
733 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
1478 add(rscratch1, rscratch1, rscratch2,
1479 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1480 br(rscratch1);
1481 }
1482
1483 // Form an address from base + offset in Rd. Rd may or may not
1484 // actually be used: you must use the Address that is returned. It
1485 // is up to you to ensure that the shift provided matches the size
1486 // of your data.
1487 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1488
1489 // Return true iff an address is within the 48-bit AArch64 address
1490 // space.
1491 bool is_valid_AArch64_address(address a) {
1492 return ((uint64_t)a >> 48) == 0;
1493 }
1494
1495 // Load the base of the cardtable byte map into reg.
1496 void load_byte_map_base(Register reg);
1497
1498 // Load a constant address in the AOT Runtime Constants area
1499 void load_aotrc_address(Register reg, address a);
1500
1501 // Prolog generator routines to support switch between x86 code and
1502 // generated ARM code
1503
1504 // routine to generate an x86 prolog for a stub function which
1505 // bootstraps into the generated ARM code which directly follows the
1506 // stub
1507 //
1508
1509 public:
1510
1511 address read_polling_page(Register r, relocInfo::relocType rtype);
1512 void get_polling_page(Register dest, relocInfo::relocType rtype);
1513
1514 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1515 void update_byte_crc32(Register crc, Register val, Register table);
1516 void update_word_crc32(Register crc, Register v, Register tmp,
1517 Register table0, Register table1, Register table2, Register table3,
1518 bool upper = false);
1519
1520 address count_positives(Register ary1, Register len, Register result);
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