11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/vmreg.hpp"
31 #include "metaprogramming/enableIf.hpp"
32 #include "oops/compressedOops.hpp"
33 #include "oops/compressedKlass.hpp"
34 #include "runtime/vm_version.hpp"
35 #include "utilities/powerOfTwo.hpp"
36
37 class OopMap;
38
39 // MacroAssembler extends Assembler by frequently used macros.
40 //
41 // Instructions for which a 'better' code sequence exists depending
42 // on arguments should also go in here.
43
44 class MacroAssembler: public Assembler {
45 friend class LIR_Assembler;
46
47 public:
48 using Assembler::mov;
49 using Assembler::movi;
50
1241 // always updated, even if we're not using the trampoline.
1242
1243 // Emit a direct call if the entry address will always be in range,
1244 // otherwise a trampoline call.
1245 // Supported entry.rspec():
1246 // - relocInfo::runtime_call_type
1247 // - relocInfo::opt_virtual_call_type
1248 // - relocInfo::static_call_type
1249 // - relocInfo::virtual_call_type
1250 //
1251 // Return: the call PC or null if CodeCache is full.
1252 // Clobbers: rscratch1
1253 address trampoline_call(Address entry);
1254
1255 static bool far_branches() {
1256 return ReservedCodeCacheSize > branch_range;
1257 }
1258
1259 // Check if branches to the non nmethod section require a far jump
1260 static bool codestub_branch_needs_far_jump() {
1261 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1262 }
1263
1264 // Emit a direct call/jump if the entry address will always be in range,
1265 // otherwise a far call/jump.
1266 // The address must be inside the code cache.
1267 // Supported entry.rspec():
1268 // - relocInfo::external_word_type
1269 // - relocInfo::runtime_call_type
1270 // - relocInfo::none
1271 // In the case of a far call/jump, the entry address is put in the tmp register.
1272 // The tmp register is invalidated.
1273 //
1274 // Far_jump returns the amount of the emitted code.
1275 void far_call(Address entry, Register tmp = rscratch1);
1276 int far_jump(Address entry, Register tmp = rscratch1);
1277
1278 static int far_codestub_branch_size() {
1279 if (codestub_branch_needs_far_jump()) {
1280 return 3 * 4; // adrp, add, br
1388 add(rscratch1, rscratch1, rscratch2,
1389 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1390 br(rscratch1);
1391 }
1392
1393 // Form an address from base + offset in Rd. Rd may or may not
1394 // actually be used: you must use the Address that is returned. It
1395 // is up to you to ensure that the shift provided matches the size
1396 // of your data.
1397 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1398
1399 // Return true iff an address is within the 48-bit AArch64 address
1400 // space.
1401 bool is_valid_AArch64_address(address a) {
1402 return ((uint64_t)a >> 48) == 0;
1403 }
1404
1405 // Load the base of the cardtable byte map into reg.
1406 void load_byte_map_base(Register reg);
1407
1408 // Prolog generator routines to support switch between x86 code and
1409 // generated ARM code
1410
1411 // routine to generate an x86 prolog for a stub function which
1412 // bootstraps into the generated ARM code which directly follows the
1413 // stub
1414 //
1415
1416 public:
1417
1418 void ldr_constant(Register dest, const Address &const_addr) {
1419 if (NearCpool) {
1420 ldr(dest, const_addr);
1421 } else {
1422 uint64_t offset;
1423 adrp(dest, InternalAddress(const_addr.target()), offset);
1424 ldr(dest, Address(dest, offset));
1425 }
1426 }
1427
|
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/vmreg.hpp"
31 #include "code/SCCache.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/powerOfTwo.hpp"
37
38 class OopMap;
39
40 // MacroAssembler extends Assembler by frequently used macros.
41 //
42 // Instructions for which a 'better' code sequence exists depending
43 // on arguments should also go in here.
44
45 class MacroAssembler: public Assembler {
46 friend class LIR_Assembler;
47
48 public:
49 using Assembler::mov;
50 using Assembler::movi;
51
1242 // always updated, even if we're not using the trampoline.
1243
1244 // Emit a direct call if the entry address will always be in range,
1245 // otherwise a trampoline call.
1246 // Supported entry.rspec():
1247 // - relocInfo::runtime_call_type
1248 // - relocInfo::opt_virtual_call_type
1249 // - relocInfo::static_call_type
1250 // - relocInfo::virtual_call_type
1251 //
1252 // Return: the call PC or null if CodeCache is full.
1253 // Clobbers: rscratch1
1254 address trampoline_call(Address entry);
1255
1256 static bool far_branches() {
1257 return ReservedCodeCacheSize > branch_range;
1258 }
1259
1260 // Check if branches to the non nmethod section require a far jump
1261 static bool codestub_branch_needs_far_jump() {
1262 if (SCCache::is_on_for_write()) {
1263 // To calculate far_codestub_branch_size correctly.
1264 return true;
1265 }
1266 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1267 }
1268
1269 // Emit a direct call/jump if the entry address will always be in range,
1270 // otherwise a far call/jump.
1271 // The address must be inside the code cache.
1272 // Supported entry.rspec():
1273 // - relocInfo::external_word_type
1274 // - relocInfo::runtime_call_type
1275 // - relocInfo::none
1276 // In the case of a far call/jump, the entry address is put in the tmp register.
1277 // The tmp register is invalidated.
1278 //
1279 // Far_jump returns the amount of the emitted code.
1280 void far_call(Address entry, Register tmp = rscratch1);
1281 int far_jump(Address entry, Register tmp = rscratch1);
1282
1283 static int far_codestub_branch_size() {
1284 if (codestub_branch_needs_far_jump()) {
1285 return 3 * 4; // adrp, add, br
1393 add(rscratch1, rscratch1, rscratch2,
1394 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1395 br(rscratch1);
1396 }
1397
1398 // Form an address from base + offset in Rd. Rd may or may not
1399 // actually be used: you must use the Address that is returned. It
1400 // is up to you to ensure that the shift provided matches the size
1401 // of your data.
1402 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1403
1404 // Return true iff an address is within the 48-bit AArch64 address
1405 // space.
1406 bool is_valid_AArch64_address(address a) {
1407 return ((uint64_t)a >> 48) == 0;
1408 }
1409
1410 // Load the base of the cardtable byte map into reg.
1411 void load_byte_map_base(Register reg);
1412
1413 // Load a constant address in the AOT Runtime Constants area
1414 void load_aotrc_address(Register reg, address a);
1415
1416 // Prolog generator routines to support switch between x86 code and
1417 // generated ARM code
1418
1419 // routine to generate an x86 prolog for a stub function which
1420 // bootstraps into the generated ARM code which directly follows the
1421 // stub
1422 //
1423
1424 public:
1425
1426 void ldr_constant(Register dest, const Address &const_addr) {
1427 if (NearCpool) {
1428 ldr(dest, const_addr);
1429 } else {
1430 uint64_t offset;
1431 adrp(dest, InternalAddress(const_addr.target()), offset);
1432 ldr(dest, Address(dest, offset));
1433 }
1434 }
1435
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