686 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
687 pd_patch_instruction_size(branch, target);
688 }
689 static address pd_call_destination(address branch) {
690 return target_addr_for_insn(branch);
691 }
692 #ifndef PRODUCT
693 static void pd_print_patched_instruction(address branch);
694 #endif
695
696 static int patch_oop(address insn_addr, address o);
697 static int patch_narrow_klass(address insn_addr, narrowKlass n);
698
699 // Return whether code is emitted to a scratch blob.
700 virtual bool in_scratch_emit_size() {
701 return false;
702 }
703 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
704 static int max_trampoline_stub_size();
705 void emit_static_call_stub();
706 static int static_call_stub_size();
707
708 // The following 4 methods return the offset of the appropriate move instruction
709
710 // Support for fast byte/short loading with zero extension (depending on particular CPU)
711 int load_unsigned_byte(Register dst, Address src);
712 int load_unsigned_short(Register dst, Address src);
713
714 // Support for fast byte/short loading with sign extension (depending on particular CPU)
715 int load_signed_byte(Register dst, Address src);
716 int load_signed_short(Register dst, Address src);
717
718 int load_signed_byte32(Register dst, Address src);
719 int load_signed_short32(Register dst, Address src);
720
721 // Support for sign-extension (hi:lo = extend_sign(lo))
722 void extend_sign(Register hi, Register lo);
723
724 // Load and store values by size and signed-ness
725 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
726 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
1460 add(rscratch1, rscratch1, rscratch2,
1461 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1462 br(rscratch1);
1463 }
1464
1465 // Form an address from base + offset in Rd. Rd may or may not
1466 // actually be used: you must use the Address that is returned. It
1467 // is up to you to ensure that the shift provided matches the size
1468 // of your data.
1469 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1470
1471 // Return true iff an address is within the 48-bit AArch64 address
1472 // space.
1473 bool is_valid_AArch64_address(address a) {
1474 return ((uint64_t)a >> 48) == 0;
1475 }
1476
1477 // Load the base of the cardtable byte map into reg.
1478 void load_byte_map_base(Register reg);
1479
1480 // Prolog generator routines to support switch between x86 code and
1481 // generated ARM code
1482
1483 // routine to generate an x86 prolog for a stub function which
1484 // bootstraps into the generated ARM code which directly follows the
1485 // stub
1486 //
1487
1488 public:
1489
1490 address read_polling_page(Register r, relocInfo::relocType rtype);
1491 void get_polling_page(Register dest, relocInfo::relocType rtype);
1492
1493 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1494 void update_byte_crc32(Register crc, Register val, Register table);
1495 void update_word_crc32(Register crc, Register v, Register tmp,
1496 Register table0, Register table1, Register table2, Register table3,
1497 bool upper = false);
1498
1499 address count_positives(Register ary1, Register len, Register result);
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686 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
687 pd_patch_instruction_size(branch, target);
688 }
689 static address pd_call_destination(address branch) {
690 return target_addr_for_insn(branch);
691 }
692 #ifndef PRODUCT
693 static void pd_print_patched_instruction(address branch);
694 #endif
695
696 static int patch_oop(address insn_addr, address o);
697 static int patch_narrow_klass(address insn_addr, narrowKlass n);
698
699 // Return whether code is emitted to a scratch blob.
700 virtual bool in_scratch_emit_size() {
701 return false;
702 }
703 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
704 static int max_trampoline_stub_size();
705 void emit_static_call_stub();
706 static int max_static_call_stub_size();
707
708 // The following 4 methods return the offset of the appropriate move instruction
709
710 // Support for fast byte/short loading with zero extension (depending on particular CPU)
711 int load_unsigned_byte(Register dst, Address src);
712 int load_unsigned_short(Register dst, Address src);
713
714 // Support for fast byte/short loading with sign extension (depending on particular CPU)
715 int load_signed_byte(Register dst, Address src);
716 int load_signed_short(Register dst, Address src);
717
718 int load_signed_byte32(Register dst, Address src);
719 int load_signed_short32(Register dst, Address src);
720
721 // Support for sign-extension (hi:lo = extend_sign(lo))
722 void extend_sign(Register hi, Register lo);
723
724 // Load and store values by size and signed-ness
725 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
726 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
1460 add(rscratch1, rscratch1, rscratch2,
1461 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1462 br(rscratch1);
1463 }
1464
1465 // Form an address from base + offset in Rd. Rd may or may not
1466 // actually be used: you must use the Address that is returned. It
1467 // is up to you to ensure that the shift provided matches the size
1468 // of your data.
1469 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1470
1471 // Return true iff an address is within the 48-bit AArch64 address
1472 // space.
1473 bool is_valid_AArch64_address(address a) {
1474 return ((uint64_t)a >> 48) == 0;
1475 }
1476
1477 // Load the base of the cardtable byte map into reg.
1478 void load_byte_map_base(Register reg);
1479
1480 // Load a constant address in the AOT Runtime Constants area
1481 void load_aotrc_address(Register reg, address a);
1482
1483 // Prolog generator routines to support switch between x86 code and
1484 // generated ARM code
1485
1486 // routine to generate an x86 prolog for a stub function which
1487 // bootstraps into the generated ARM code which directly follows the
1488 // stub
1489 //
1490
1491 public:
1492
1493 address read_polling_page(Register r, relocInfo::relocType rtype);
1494 void get_polling_page(Register dest, relocInfo::relocType rtype);
1495
1496 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1497 void update_byte_crc32(Register crc, Register val, Register table);
1498 void update_word_crc32(Register crc, Register v, Register tmp,
1499 Register table0, Register table1, Register table2, Register table3,
1500 bool upper = false);
1501
1502 address count_positives(Register ary1, Register len, Register result);
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