1452     add(rscratch1, rscratch1, rscratch2,
1453         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1454     br(rscratch1);
1455   }
1456 
1457   // Form an address from base + offset in Rd.  Rd may or may not
1458   // actually be used: you must use the Address that is returned.  It
1459   // is up to you to ensure that the shift provided matches the size
1460   // of your data.
1461   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1462 
1463   // Return true iff an address is within the 48-bit AArch64 address
1464   // space.
1465   bool is_valid_AArch64_address(address a) {
1466     return ((uint64_t)a >> 48) == 0;
1467   }
1468 
1469   // Load the base of the cardtable byte map into reg.
1470   void load_byte_map_base(Register reg);
1471 



1472   // Prolog generator routines to support switch between x86 code and
1473   // generated ARM code
1474 
1475   // routine to generate an x86 prolog for a stub function which
1476   // bootstraps into the generated ARM code which directly follows the
1477   // stub
1478   //
1479 
1480   public:
1481 
1482   address read_polling_page(Register r, relocInfo::relocType rtype);
1483   void get_polling_page(Register dest, relocInfo::relocType rtype);
1484 
1485   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1486   void update_byte_crc32(Register crc, Register val, Register table);
1487   void update_word_crc32(Register crc, Register v, Register tmp,
1488         Register table0, Register table1, Register table2, Register table3,
1489         bool upper = false);
1490 
1491   address count_positives(Register ary1, Register len, Register result);

1452     add(rscratch1, rscratch1, rscratch2,
1453         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1454     br(rscratch1);
1455   }
1456 
1457   // Form an address from base + offset in Rd.  Rd may or may not
1458   // actually be used: you must use the Address that is returned.  It
1459   // is up to you to ensure that the shift provided matches the size
1460   // of your data.
1461   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1462 
1463   // Return true iff an address is within the 48-bit AArch64 address
1464   // space.
1465   bool is_valid_AArch64_address(address a) {
1466     return ((uint64_t)a >> 48) == 0;
1467   }
1468 
1469   // Load the base of the cardtable byte map into reg.
1470   void load_byte_map_base(Register reg);
1471 
1472   // Load a constant address in the AOT Runtime Constants area
1473   void load_aotrc_address(Register reg, address a);
1474 
1475   // Prolog generator routines to support switch between x86 code and
1476   // generated ARM code
1477 
1478   // routine to generate an x86 prolog for a stub function which
1479   // bootstraps into the generated ARM code which directly follows the
1480   // stub
1481   //
1482 
1483   public:
1484 
1485   address read_polling_page(Register r, relocInfo::relocType rtype);
1486   void get_polling_page(Register dest, relocInfo::relocType rtype);
1487 
1488   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1489   void update_byte_crc32(Register crc, Register val, Register table);
1490   void update_word_crc32(Register crc, Register v, Register tmp,
1491         Register table0, Register table1, Register table2, Register table3,
1492         bool upper = false);
1493 
1494   address count_positives(Register ary1, Register len, Register result);