1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "pauth_aarch64.hpp"
27 #include "register_aarch64.hpp"
28 #include "runtime/arguments.hpp"
29 #include "runtime/globals_extension.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/os.inline.hpp"
32 #include "runtime/vm_version.hpp"
33 #include "utilities/formatBuffer.hpp"
34 #include "utilities/macros.hpp"
35 #include "utilities/ostream.hpp"
36
37 int VM_Version::_cpu;
38 int VM_Version::_model;
39 int VM_Version::_model2;
40 int VM_Version::_variant;
41 int VM_Version::_revision;
42 int VM_Version::_stepping;
43
44 int VM_Version::_zva_length;
45 int VM_Version::_dcache_line_size;
46 int VM_Version::_icache_line_size;
47 int VM_Version::_initial_sve_vector_length;
48 int VM_Version::_max_supported_sve_vector_length;
49 bool VM_Version::_rop_protection;
50 uintptr_t VM_Version::_pac_mask;
51
52 SpinWait VM_Version::_spin_wait;
53
54 const char* VM_Version::_features_names[MAX_CPU_FEATURES] = { nullptr };
55
56 static SpinWait get_spin_wait_desc() {
57 SpinWait spin_wait(OnSpinWaitInst, OnSpinWaitInstCount);
58 if (spin_wait.inst() == SpinWait::SB && !VM_Version::supports_sb()) {
59 vm_exit_during_initialization("OnSpinWaitInst is SB but current CPU does not support SB instruction");
60 }
61
62 return spin_wait;
63 }
64
65 void VM_Version::initialize() {
66 #define SET_CPU_FEATURE_NAME(id, name, bit) \
67 _features_names[bit] = XSTR(name);
68 CPU_FEATURE_FLAGS(SET_CPU_FEATURE_NAME)
69 #undef SET_CPU_FEATURE_NAME
70
71 _supports_atomic_getset4 = true;
72 _supports_atomic_getadd4 = true;
73 _supports_atomic_getset8 = true;
74 _supports_atomic_getadd8 = true;
75
76 get_os_cpu_info();
77
78 int dcache_line = VM_Version::dcache_line_size();
79
80 // Limit AllocatePrefetchDistance so that it does not exceed the
81 // static constraint of 512 defined in runtime/globals.hpp.
82 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
83 FLAG_SET_DEFAULT(AllocatePrefetchDistance, MIN2(512, 3*dcache_line));
84
85 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
86 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
87 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
88 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
89 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
90 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
91 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
92 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
93
94 if (PrefetchCopyIntervalInBytes != -1 &&
95 ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
96 warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
97 PrefetchCopyIntervalInBytes &= ~7;
98 if (PrefetchCopyIntervalInBytes >= 32768)
99 PrefetchCopyIntervalInBytes = 32760;
100 }
101
102 if (AllocatePrefetchDistance != -1 && (AllocatePrefetchDistance & 7)) {
103 warning("AllocatePrefetchDistance must be multiple of 8");
104 AllocatePrefetchDistance &= ~7;
105 }
106
107 if (AllocatePrefetchStepSize & 7) {
108 warning("AllocatePrefetchStepSize must be multiple of 8");
109 AllocatePrefetchStepSize &= ~7;
110 }
111
112 if (SoftwarePrefetchHintDistance != -1 &&
113 (SoftwarePrefetchHintDistance & 7)) {
114 warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
115 SoftwarePrefetchHintDistance &= ~7;
116 }
117
118 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (dcache_line > ContendedPaddingWidth)) {
119 ContendedPaddingWidth = dcache_line;
120 }
121
122 if (os::supports_map_sync()) {
123 // if dcpop is available publish data cache line flush size via
124 // generic field, otherwise let if default to zero thereby
125 // disabling writeback
126 if (VM_Version::supports_dcpop()) {
127 _data_cache_line_flush_size = dcache_line;
128 }
129 }
130
131 // Enable vendor specific features
132
133 // Ampere eMAG
134 if (_cpu == CPU_AMCC && (_model == CPU_MODEL_EMAG) && (_variant == 0x3)) {
135 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
136 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
137 }
138 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
139 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
140 }
141 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
142 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, !(_revision == 1 || _revision == 2));
143 }
144 }
145
146 // Ampere CPUs
147 if (_cpu == CPU_AMPERE && ((_model == CPU_MODEL_AMPERE_1) ||
148 (_model == CPU_MODEL_AMPERE_1A) ||
149 (_model == CPU_MODEL_AMPERE_1B))) {
150 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
151 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
152 }
153 if (FLAG_IS_DEFAULT(OnSpinWaitInst)) {
154 FLAG_SET_DEFAULT(OnSpinWaitInst, "isb");
155 }
156 if (FLAG_IS_DEFAULT(OnSpinWaitInstCount)) {
157 FLAG_SET_DEFAULT(OnSpinWaitInstCount, 2);
158 }
159 if (FLAG_IS_DEFAULT(CodeEntryAlignment) &&
160 (_model == CPU_MODEL_AMPERE_1A || _model == CPU_MODEL_AMPERE_1B)) {
161 FLAG_SET_DEFAULT(CodeEntryAlignment, 32);
162 }
163 if (FLAG_IS_DEFAULT(AlwaysMergeDMB)) {
164 FLAG_SET_DEFAULT(AlwaysMergeDMB, false);
165 }
166 }
167
168 // ThunderX
169 if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
170 guarantee(_variant != 0, "Pre-release hardware no longer supported.");
171 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
172 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
173 }
174 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
175 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
176 }
177 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
178 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
179 }
180 }
181
182 // ThunderX2
183 if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
184 (_cpu == CPU_BROADCOM && (_model == 0x516))) {
185 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
186 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
187 }
188 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
189 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
190 }
191 }
192
193 // HiSilicon TSV110
194 if (_cpu == CPU_HISILICON && _model == 0xd01) {
195 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
196 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
197 }
198 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
199 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
200 }
201 }
202
203 // Cortex A53
204 if (_cpu == CPU_ARM && model_is(0xd03)) {
205 set_feature(CPU_A53MAC);
206 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
207 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
208 }
209 }
210
211 // Cortex A73
212 if (_cpu == CPU_ARM && model_is(0xd09)) {
213 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
214 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
215 }
216 // A73 is faster with short-and-easy-for-speculative-execution-loop
217 if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
218 FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
219 }
220 }
221
222 // Neoverse
223 // N1: 0xd0c
224 // N2: 0xd49
225 // V1: 0xd40
226 // V2: 0xd4f
227 if (_cpu == CPU_ARM && (model_is(0xd0c) || model_is(0xd49) ||
228 model_is(0xd40) || model_is(0xd4f))) {
229 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
230 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
231 }
232
233 if (FLAG_IS_DEFAULT(OnSpinWaitInst)) {
234 FLAG_SET_DEFAULT(OnSpinWaitInst, "isb");
235 }
236
237 if (FLAG_IS_DEFAULT(OnSpinWaitInstCount)) {
238 FLAG_SET_DEFAULT(OnSpinWaitInstCount, 1);
239 }
240 if (FLAG_IS_DEFAULT(AlwaysMergeDMB)) {
241 FLAG_SET_DEFAULT(AlwaysMergeDMB, false);
242 }
243 }
244
245 if (supports_feature(CPU_FP) || supports_feature(CPU_ASIMD)) {
246 if (FLAG_IS_DEFAULT(UseSignumIntrinsic)) {
247 FLAG_SET_DEFAULT(UseSignumIntrinsic, true);
248 }
249 }
250
251 if (FLAG_IS_DEFAULT(UseCRC32)) {
252 UseCRC32 = VM_Version::supports_crc32();
253 }
254
255 if (UseCRC32 && !VM_Version::supports_crc32()) {
256 warning("UseCRC32 specified, but not supported on this CPU");
257 FLAG_SET_DEFAULT(UseCRC32, false);
258 }
259
260 // Neoverse
261 // V1: 0xd40
262 // V2: 0xd4f
263 if (_cpu == CPU_ARM && (model_is(0xd40) || model_is(0xd4f))) {
264 if (FLAG_IS_DEFAULT(UseCryptoPmullForCRC32)) {
265 FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, true);
266 }
267 if (FLAG_IS_DEFAULT(CodeEntryAlignment)) {
268 FLAG_SET_DEFAULT(CodeEntryAlignment, 32);
269 }
270 }
271
272 if (UseCryptoPmullForCRC32 && (!VM_Version::supports_pmull() || !VM_Version::supports_sha3() || !VM_Version::supports_crc32())) {
273 warning("UseCryptoPmullForCRC32 specified, but not supported on this CPU");
274 FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, false);
275 }
276
277 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
278 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
279 }
280
281 if (UseVectorizedMismatchIntrinsic) {
282 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
283 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
284 }
285
286 if (VM_Version::supports_lse()) {
287 if (FLAG_IS_DEFAULT(UseLSE))
288 FLAG_SET_DEFAULT(UseLSE, true);
289 } else {
290 if (UseLSE) {
291 warning("UseLSE specified, but not supported on this CPU");
292 FLAG_SET_DEFAULT(UseLSE, false);
293 }
294 }
295
296 if (VM_Version::supports_aes()) {
297 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
298 UseAESIntrinsics =
299 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
300 if (UseAESIntrinsics && !UseAES) {
301 warning("UseAESIntrinsics enabled, but UseAES not, enabling");
302 UseAES = true;
303 }
304 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
305 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
306 }
307 } else {
308 if (UseAES) {
309 warning("AES instructions are not available on this CPU");
310 FLAG_SET_DEFAULT(UseAES, false);
311 }
312 if (UseAESIntrinsics) {
313 warning("AES intrinsics are not available on this CPU");
314 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
315 }
316 if (UseAESCTRIntrinsics) {
317 warning("AES/CTR intrinsics are not available on this CPU");
318 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
319 }
320 }
321
322
323 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
324 UseCRC32Intrinsics = true;
325 }
326
327 if (VM_Version::supports_crc32()) {
328 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
329 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
330 }
331 } else if (UseCRC32CIntrinsics) {
332 warning("CRC32C is not available on the CPU");
333 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
334 }
335
336 if (FLAG_IS_DEFAULT(UseFMA)) {
337 FLAG_SET_DEFAULT(UseFMA, true);
338 }
339
340 if (FLAG_IS_DEFAULT(UseMD5Intrinsics)) {
341 UseMD5Intrinsics = true;
342 }
343
344 if (VM_Version::supports_sha1() || VM_Version::supports_sha256() ||
345 VM_Version::supports_sha3() || VM_Version::supports_sha512()) {
346 if (FLAG_IS_DEFAULT(UseSHA)) {
347 FLAG_SET_DEFAULT(UseSHA, true);
348 }
349 } else if (UseSHA) {
350 warning("SHA instructions are not available on this CPU");
351 FLAG_SET_DEFAULT(UseSHA, false);
352 }
353
354 if (UseSHA && VM_Version::supports_sha1()) {
355 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
356 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
357 }
358 } else if (UseSHA1Intrinsics) {
359 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
360 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
361 }
362
363 if (UseSHA && VM_Version::supports_sha256()) {
364 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
365 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
366 }
367 } else if (UseSHA256Intrinsics) {
368 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
369 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
370 }
371
372 if (UseSHA && VM_Version::supports_sha3()) {
373 // Auto-enable UseSHA3Intrinsics on hardware with performance benefit.
374 // Note that the evaluation of UseSHA3Intrinsics shows better performance
375 // on Apple silicon but worse performance on Neoverse V1 and N2.
376 if (_cpu == CPU_APPLE) { // Apple silicon
377 if (FLAG_IS_DEFAULT(UseSHA3Intrinsics)) {
378 FLAG_SET_DEFAULT(UseSHA3Intrinsics, true);
379 }
380 }
381 } else if (UseSHA3Intrinsics && UseSIMDForSHA3Intrinsic) {
382 warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU.");
383 FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
384 }
385
386 if (UseSHA && VM_Version::supports_sha512()) {
387 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
388 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
389 }
390 } else if (UseSHA512Intrinsics) {
391 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
392 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
393 }
394
395 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA3Intrinsics || UseSHA512Intrinsics)) {
396 FLAG_SET_DEFAULT(UseSHA, false);
397 }
398
399 if (VM_Version::supports_pmull()) {
400 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
401 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
402 }
403 } else if (UseGHASHIntrinsics) {
404 warning("GHASH intrinsics are not available on this CPU");
405 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
406 }
407
408 if (supports_feature(CPU_ASIMD)) {
409 if (FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
410 UseChaCha20Intrinsics = true;
411 }
412 } else if (UseChaCha20Intrinsics) {
413 if (!FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
414 warning("ChaCha20 intrinsic requires ASIMD instructions");
415 }
416 FLAG_SET_DEFAULT(UseChaCha20Intrinsics, false);
417 }
418
419 if (supports_feature(CPU_ASIMD)) {
420 if (FLAG_IS_DEFAULT(UseKyberIntrinsics)) {
421 UseKyberIntrinsics = true;
422 }
423 } else if (UseKyberIntrinsics) {
424 if (!FLAG_IS_DEFAULT(UseKyberIntrinsics)) {
425 warning("Kyber intrinsics require ASIMD instructions");
426 }
427 FLAG_SET_DEFAULT(UseKyberIntrinsics, false);
428 }
429
430 if (supports_feature(CPU_ASIMD)) {
431 if (FLAG_IS_DEFAULT(UseDilithiumIntrinsics)) {
432 UseDilithiumIntrinsics = true;
433 }
434 } else if (UseDilithiumIntrinsics) {
435 if (!FLAG_IS_DEFAULT(UseDilithiumIntrinsics)) {
436 warning("Dilithium intrinsics require ASIMD instructions");
437 }
438 FLAG_SET_DEFAULT(UseDilithiumIntrinsics, false);
439 }
440
441 if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
442 UseBASE64Intrinsics = true;
443 }
444
445 if (is_zva_enabled()) {
446 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
447 FLAG_SET_DEFAULT(UseBlockZeroing, true);
448 }
449 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
450 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
451 }
452 } else if (UseBlockZeroing) {
453 warning("DC ZVA is not available on this CPU");
454 FLAG_SET_DEFAULT(UseBlockZeroing, false);
455 }
456
457 if (VM_Version::supports_sve2()) {
458 if (FLAG_IS_DEFAULT(UseSVE)) {
459 FLAG_SET_DEFAULT(UseSVE, 2);
460 }
461 } else if (VM_Version::supports_sve()) {
462 if (FLAG_IS_DEFAULT(UseSVE)) {
463 FLAG_SET_DEFAULT(UseSVE, 1);
464 } else if (UseSVE > 1) {
465 warning("SVE2 specified, but not supported on current CPU. Using SVE.");
466 FLAG_SET_DEFAULT(UseSVE, 1);
467 }
468 } else if (UseSVE > 0) {
469 warning("UseSVE specified, but not supported on current CPU. Disabling SVE.");
470 FLAG_SET_DEFAULT(UseSVE, 0);
471 }
472
473 if (UseSVE > 0) {
474 int vl = get_current_sve_vector_length();
475 if (vl < 0) {
476 warning("Unable to get SVE vector length on this system. "
477 "Disabling SVE. Specify -XX:UseSVE=0 to shun this warning.");
478 FLAG_SET_DEFAULT(UseSVE, 0);
479 } else if ((vl == 0) || ((vl % FloatRegister::sve_vl_min) != 0) || !is_power_of_2(vl)) {
480 warning("Detected SVE vector length (%d) should be a power of two and a multiple of %d. "
481 "Disabling SVE. Specify -XX:UseSVE=0 to shun this warning.",
482 vl, FloatRegister::sve_vl_min);
483 FLAG_SET_DEFAULT(UseSVE, 0);
484 } else {
485 _initial_sve_vector_length = vl;
486 }
487 }
488
489 // This machine allows unaligned memory accesses
490 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
491 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
492 }
493
494 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
495 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
496 }
497
498 if (!UsePopCountInstruction) {
499 warning("UsePopCountInstruction is always enabled on this CPU");
500 UsePopCountInstruction = true;
501 }
502
503 if (UseBranchProtection == nullptr || strcmp(UseBranchProtection, "none") == 0) {
504 _rop_protection = false;
505 } else if (strcmp(UseBranchProtection, "standard") == 0 ||
506 strcmp(UseBranchProtection, "pac-ret") == 0) {
507 _rop_protection = false;
508 // Enable ROP-protection if
509 // 1) this code has been built with branch-protection and
510 // 2) the CPU/OS supports it
511 #ifdef __ARM_FEATURE_PAC_DEFAULT
512 if (!VM_Version::supports_paca()) {
513 // Disable PAC to prevent illegal instruction crashes.
514 warning("ROP-protection specified, but not supported on this CPU. Disabling ROP-protection.");
515 } else {
516 _rop_protection = true;
517 }
518 #else
519 warning("ROP-protection specified, but this VM was built without ROP-protection support. Disabling ROP-protection.");
520 #endif
521 } else {
522 vm_exit_during_initialization(err_msg("Unsupported UseBranchProtection: %s", UseBranchProtection));
523 }
524
525 if (_rop_protection == true) {
526 // Determine the mask of address bits used for PAC. Clear bit 55 of
527 // the input to make it look like a user address.
528 _pac_mask = (uintptr_t)pauth_strip_pointer((address)~(UINT64_C(1) << 55));
529 }
530
531 #ifdef COMPILER2
532 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
533 UseMultiplyToLenIntrinsic = true;
534 }
535
536 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
537 UseSquareToLenIntrinsic = true;
538 }
539
540 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
541 UseMulAddIntrinsic = true;
542 }
543
544 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
545 UseMontgomeryMultiplyIntrinsic = true;
546 }
547 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
548 UseMontgomerySquareIntrinsic = true;
549 }
550
551 if (UseSVE > 0) {
552 if (FLAG_IS_DEFAULT(MaxVectorSize)) {
553 MaxVectorSize = _initial_sve_vector_length;
554 } else if (MaxVectorSize < FloatRegister::sve_vl_min) {
555 warning("SVE does not support vector length less than %d bytes. Disabling SVE.",
556 FloatRegister::sve_vl_min);
557 UseSVE = 0;
558 } else if (!((MaxVectorSize % FloatRegister::sve_vl_min) == 0 && is_power_of_2(MaxVectorSize))) {
559 vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize));
560 }
561
562 if (UseSVE > 0) {
563 // Acquire the largest supported vector length of this machine
564 _max_supported_sve_vector_length = set_and_get_current_sve_vector_length(FloatRegister::sve_vl_max);
565
566 if (MaxVectorSize != _max_supported_sve_vector_length) {
567 int new_vl = set_and_get_current_sve_vector_length(MaxVectorSize);
568 if (new_vl < 0) {
569 vm_exit_during_initialization(
570 err_msg("Current system does not support SVE vector length for MaxVectorSize: %d",
571 (int)MaxVectorSize));
572 } else if (new_vl != MaxVectorSize) {
573 warning("Current system only supports max SVE vector length %d. Set MaxVectorSize to %d",
574 new_vl, new_vl);
575 }
576 MaxVectorSize = new_vl;
577 }
578 _initial_sve_vector_length = MaxVectorSize;
579 }
580 }
581
582 if (UseSVE == 0) { // NEON
583 int min_vector_size = 8;
584 int max_vector_size = FloatRegister::neon_vl;
585 if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
586 if (!is_power_of_2(MaxVectorSize)) {
587 vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize));
588 } else if (MaxVectorSize < min_vector_size) {
589 warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
590 FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
591 } else if (MaxVectorSize > max_vector_size) {
592 warning("MaxVectorSize must be at most %i on this platform", max_vector_size);
593 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
594 }
595 } else {
596 FLAG_SET_DEFAULT(MaxVectorSize, FloatRegister::neon_vl);
597 }
598 }
599
600 int inline_size = (UseSVE > 0 && MaxVectorSize >= FloatRegister::sve_vl_min) ? MaxVectorSize : 0;
601 if (FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize)) {
602 FLAG_SET_DEFAULT(ArrayOperationPartialInlineSize, inline_size);
603 } else if (ArrayOperationPartialInlineSize != 0 && ArrayOperationPartialInlineSize != inline_size) {
604 warning("Setting ArrayOperationPartialInlineSize to %d", inline_size);
605 ArrayOperationPartialInlineSize = inline_size;
606 }
607
608 if (FLAG_IS_DEFAULT(OptoScheduling)) {
609 OptoScheduling = true;
610 }
611
612 if (FLAG_IS_DEFAULT(AlignVector)) {
613 AlignVector = AvoidUnalignedAccesses;
614 }
615
616 if (FLAG_IS_DEFAULT(UsePoly1305Intrinsics)) {
617 FLAG_SET_DEFAULT(UsePoly1305Intrinsics, true);
618 }
619
620 if (FLAG_IS_DEFAULT(UseVectorizedHashCodeIntrinsic)) {
621 FLAG_SET_DEFAULT(UseVectorizedHashCodeIntrinsic, true);
622 }
623 #endif
624
625 _spin_wait = get_spin_wait_desc();
626
627 check_virtualizations();
628
629 // Sync SVE related CPU features with flags
630 if (UseSVE < 2) {
631 clear_feature(CPU_SVE2);
632 clear_feature(CPU_SVEBITPERM);
633 }
634 if (UseSVE < 1) {
635 clear_feature(CPU_SVE);
636 }
637
638 // Construct the "features" string
639 stringStream ss(512);
640 ss.print("0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
641 if (_model2) {
642 ss.print("(0x%03x)", _model2);
643 }
644 ss.print(", ");
645 int features_offset = (int)ss.size();
646 insert_features_names(_features, ss);
647
648 _cpu_info_string = ss.as_string(true);
649 _features_string = _cpu_info_string + features_offset;
650 }
651
652 void VM_Version::insert_features_names(uint64_t features, stringStream& ss) {
653 int i = 0;
654 ss.join([&]() {
655 while (i < MAX_CPU_FEATURES) {
656 if (supports_feature((VM_Version::Feature_Flag)i)) {
657 return _features_names[i++];
658 }
659 i += 1;
660 }
661 return (const char*)nullptr;
662 }, ", ");
663 }
664
665 #if defined(LINUX)
666 static bool check_info_file(const char* fpath,
667 const char* virt1, VirtualizationType vt1,
668 const char* virt2, VirtualizationType vt2) {
669 char line[500];
670 FILE* fp = os::fopen(fpath, "r");
671 if (fp == nullptr) {
672 return false;
673 }
674 while (fgets(line, sizeof(line), fp) != nullptr) {
675 if (strcasestr(line, virt1) != nullptr) {
676 Abstract_VM_Version::_detected_virtualization = vt1;
677 fclose(fp);
678 return true;
679 }
680 if (virt2 != nullptr && strcasestr(line, virt2) != nullptr) {
681 Abstract_VM_Version::_detected_virtualization = vt2;
682 fclose(fp);
683 return true;
684 }
685 }
686 fclose(fp);
687 return false;
688 }
689 #endif
690
691 void VM_Version::check_virtualizations() {
692 #if defined(LINUX)
693 const char* pname_file = "/sys/devices/virtual/dmi/id/product_name";
694 const char* tname_file = "/sys/hypervisor/type";
695 if (check_info_file(pname_file, "KVM", KVM, "VMWare", VMWare)) {
696 return;
697 }
698 check_info_file(tname_file, "Xen", XenPVHVM, nullptr, NoDetectedVirtualization);
699 #endif
700 }
701
702 void VM_Version::print_platform_virtualization_info(outputStream* st) {
703 #if defined(LINUX)
704 VirtualizationType vrt = VM_Version::get_detected_virtualization();
705 if (vrt == KVM) {
706 st->print_cr("KVM virtualization detected");
707 } else if (vrt == VMWare) {
708 st->print_cr("VMWare virtualization detected");
709 } else if (vrt == XenPVHVM) {
710 st->print_cr("Xen virtualization detected");
711 }
712 #endif
713 }
714
715 void VM_Version::initialize_cpu_information(void) {
716 // do nothing if cpu info has been initialized
717 if (_initialized) {
718 return;
719 }
720
721 _no_of_cores = os::processor_count();
722 _no_of_threads = _no_of_cores;
723 _no_of_sockets = _no_of_cores;
724 os::snprintf_checked(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "AArch64");
725
726 int desc_len = os::snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "AArch64 ");
727 get_compatible_board(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len);
728 desc_len = (int)strlen(_cpu_desc);
729 os::snprintf_checked(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len, " %s", _cpu_info_string);
730
731 _initialized = true;
732 }