1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2020, Red Hat Inc. All rights reserved.
4 * Copyright 2025 Arm Limited and/or its affiliates.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #include "pauth_aarch64.hpp"
28 #include "register_aarch64.hpp"
29 #include "runtime/arguments.hpp"
30 #include "runtime/globals_extension.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/os.inline.hpp"
33 #include "runtime/vm_version.hpp"
34 #include "utilities/formatBuffer.hpp"
35 #include "utilities/macros.hpp"
36 #include "utilities/ostream.hpp"
37
38 int VM_Version::_cpu;
39 int VM_Version::_model;
40 int VM_Version::_model2;
41 int VM_Version::_variant;
42 int VM_Version::_revision;
43 int VM_Version::_stepping;
44
45 int VM_Version::_zva_length;
46 int VM_Version::_dcache_line_size;
47 int VM_Version::_icache_line_size;
48 int VM_Version::_initial_sve_vector_length;
49 int VM_Version::_max_supported_sve_vector_length;
50 bool VM_Version::_rop_protection;
51 uintptr_t VM_Version::_pac_mask;
52
53 const char* VM_Version::_features_names[MAX_CPU_FEATURES] = { nullptr };
54
55 SpinWait VM_Version::_spin_wait;
56
57 static SpinWait get_spin_wait_desc() {
58 SpinWait spin_wait(OnSpinWaitInst, OnSpinWaitInstCount);
59 if (spin_wait.inst() == SpinWait::SB && !VM_Version::supports_sb()) {
60 vm_exit_during_initialization("OnSpinWaitInst is SB but current CPU does not support SB instruction");
61 }
62
63 return spin_wait;
64 }
65
66 void VM_Version::initialize() {
67 #define SET_CPU_FEATURE_NAME(id, name, bit) \
68 _features_names[bit] = XSTR(name);
69 CPU_FEATURE_FLAGS(SET_CPU_FEATURE_NAME)
70 #undef SET_CPU_FEATURE_NAME
71
72 _supports_atomic_getset4 = true;
73 _supports_atomic_getadd4 = true;
74 _supports_atomic_getset8 = true;
75 _supports_atomic_getadd8 = true;
76
77 get_os_cpu_info();
78
79 int dcache_line = VM_Version::dcache_line_size();
80
81 // Limit AllocatePrefetchDistance so that it does not exceed the
82 // static constraint of 512 defined in runtime/globals.hpp.
83 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
84 FLAG_SET_DEFAULT(AllocatePrefetchDistance, MIN2(512, 3*dcache_line));
85
86 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
87 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
88 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
89 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
90 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
91 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
92 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
93 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
94
95 if (PrefetchCopyIntervalInBytes != -1 &&
96 ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
97 warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
98 PrefetchCopyIntervalInBytes &= ~7;
99 if (PrefetchCopyIntervalInBytes >= 32768)
100 PrefetchCopyIntervalInBytes = 32760;
101 }
102
103 if (AllocatePrefetchDistance != -1 && (AllocatePrefetchDistance & 7)) {
104 warning("AllocatePrefetchDistance must be multiple of 8");
105 AllocatePrefetchDistance &= ~7;
106 }
107
108 if (AllocatePrefetchStepSize & 7) {
109 warning("AllocatePrefetchStepSize must be multiple of 8");
110 AllocatePrefetchStepSize &= ~7;
111 }
112
113 if (SoftwarePrefetchHintDistance != -1 &&
114 (SoftwarePrefetchHintDistance & 7)) {
115 warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
116 SoftwarePrefetchHintDistance &= ~7;
117 }
118
119 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (dcache_line > ContendedPaddingWidth)) {
120 ContendedPaddingWidth = dcache_line;
121 }
122
123 if (os::supports_map_sync()) {
124 // if dcpop is available publish data cache line flush size via
125 // generic field, otherwise let if default to zero thereby
126 // disabling writeback
127 if (VM_Version::supports_dcpop()) {
128 _data_cache_line_flush_size = dcache_line;
129 }
130 }
131
132 // Enable vendor specific features
133
134 // Ampere eMAG
135 if (_cpu == CPU_AMCC && (_model == CPU_MODEL_EMAG) && (_variant == 0x3)) {
136 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
137 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
138 }
139 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
140 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
141 }
142 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
143 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, !(_revision == 1 || _revision == 2));
144 }
145 }
146
147 // Ampere CPUs
148 if (_cpu == CPU_AMPERE && ((_model == CPU_MODEL_AMPERE_1) ||
149 (_model == CPU_MODEL_AMPERE_1A) ||
150 (_model == CPU_MODEL_AMPERE_1B))) {
151 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
152 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
153 }
154 if (FLAG_IS_DEFAULT(OnSpinWaitInst)) {
155 FLAG_SET_DEFAULT(OnSpinWaitInst, "isb");
156 }
157 if (FLAG_IS_DEFAULT(OnSpinWaitInstCount)) {
158 FLAG_SET_DEFAULT(OnSpinWaitInstCount, 2);
159 }
160 if (FLAG_IS_DEFAULT(CodeEntryAlignment) &&
161 (_model == CPU_MODEL_AMPERE_1A || _model == CPU_MODEL_AMPERE_1B)) {
162 FLAG_SET_DEFAULT(CodeEntryAlignment, 32);
163 }
164 if (FLAG_IS_DEFAULT(AlwaysMergeDMB)) {
165 FLAG_SET_DEFAULT(AlwaysMergeDMB, false);
166 }
167 }
168
169 // ThunderX
170 if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
171 guarantee(_variant != 0, "Pre-release hardware no longer supported.");
172 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
173 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
174 }
175 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
176 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
177 }
178 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
179 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
180 }
181 }
182
183 // ThunderX2
184 if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
185 (_cpu == CPU_BROADCOM && (_model == 0x516))) {
186 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
187 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
188 }
189 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
190 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
191 }
192 }
193
194 // HiSilicon TSV110
195 if (_cpu == CPU_HISILICON && _model == 0xd01) {
196 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
197 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
198 }
199 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
200 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
201 }
202 }
203
204 if (_cpu == CPU_ARM && model_is(CPU_MODEL_ARM_CORTEX_A53)) {
205 set_feature(CPU_A53MAC);
206 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
207 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
208 }
209 }
210
211 if (_cpu == CPU_ARM && model_is(CPU_MODEL_ARM_CORTEX_A73)) {
212 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
213 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
214 }
215 // A73 is faster with short-and-easy-for-speculative-execution-loop
216 if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
217 FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
218 }
219 }
220
221 if (_cpu == CPU_ARM &&
222 model_is_in({ CPU_MODEL_ARM_NEOVERSE_N1, CPU_MODEL_ARM_NEOVERSE_V1,
223 CPU_MODEL_ARM_NEOVERSE_N2, CPU_MODEL_ARM_NEOVERSE_V2,
224 CPU_MODEL_ARM_NEOVERSE_N3, CPU_MODEL_ARM_NEOVERSE_V3,
225 CPU_MODEL_ARM_NEOVERSE_V3AE })) {
226 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
227 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
228 }
229
230 if (FLAG_IS_DEFAULT(OnSpinWaitInst)) {
231 FLAG_SET_DEFAULT(OnSpinWaitInst, "isb");
232 }
233
234 if (FLAG_IS_DEFAULT(OnSpinWaitInstCount)) {
235 FLAG_SET_DEFAULT(OnSpinWaitInstCount, 1);
236 }
237 if (FLAG_IS_DEFAULT(AlwaysMergeDMB)) {
238 FLAG_SET_DEFAULT(AlwaysMergeDMB, false);
239 }
240 }
241
242 if (supports_feature(CPU_FP) || supports_feature(CPU_ASIMD)) {
243 if (FLAG_IS_DEFAULT(UseSignumIntrinsic)) {
244 FLAG_SET_DEFAULT(UseSignumIntrinsic, true);
245 }
246 }
247
248 if (FLAG_IS_DEFAULT(UseCRC32)) {
249 UseCRC32 = VM_Version::supports_crc32();
250 }
251
252 if (UseCRC32 && !VM_Version::supports_crc32()) {
253 warning("UseCRC32 specified, but not supported on this CPU");
254 FLAG_SET_DEFAULT(UseCRC32, false);
255 }
256
257 if (_cpu == CPU_ARM &&
258 model_is_in({ CPU_MODEL_ARM_NEOVERSE_V1, CPU_MODEL_ARM_NEOVERSE_V2,
259 CPU_MODEL_ARM_NEOVERSE_V3, CPU_MODEL_ARM_NEOVERSE_V3AE })) {
260 if (FLAG_IS_DEFAULT(UseCryptoPmullForCRC32)) {
261 FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, true);
262 }
263 if (FLAG_IS_DEFAULT(CodeEntryAlignment)) {
264 FLAG_SET_DEFAULT(CodeEntryAlignment, 32);
265 }
266 }
267
268 if (UseCryptoPmullForCRC32 && (!VM_Version::supports_pmull() || !VM_Version::supports_sha3() || !VM_Version::supports_crc32())) {
269 warning("UseCryptoPmullForCRC32 specified, but not supported on this CPU");
270 FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, false);
271 }
272
273 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
274 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
275 }
276
277 if (UseVectorizedMismatchIntrinsic) {
278 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
279 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
280 }
281
282 if (VM_Version::supports_lse()) {
283 if (FLAG_IS_DEFAULT(UseLSE))
284 FLAG_SET_DEFAULT(UseLSE, true);
285 } else {
286 if (UseLSE) {
287 warning("UseLSE specified, but not supported on this CPU");
288 FLAG_SET_DEFAULT(UseLSE, false);
289 }
290 }
291
292 if (VM_Version::supports_aes()) {
293 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
294 UseAESIntrinsics =
295 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
296 if (UseAESIntrinsics && !UseAES) {
297 warning("UseAESIntrinsics enabled, but UseAES not, enabling");
298 UseAES = true;
299 }
300 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
301 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
302 }
303 } else {
304 if (UseAES) {
305 warning("AES instructions are not available on this CPU");
306 FLAG_SET_DEFAULT(UseAES, false);
307 }
308 if (UseAESIntrinsics) {
309 warning("AES intrinsics are not available on this CPU");
310 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
311 }
312 if (UseAESCTRIntrinsics) {
313 warning("AES/CTR intrinsics are not available on this CPU");
314 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
315 }
316 }
317
318
319 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
320 UseCRC32Intrinsics = true;
321 }
322
323 if (VM_Version::supports_crc32()) {
324 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
325 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
326 }
327 } else if (UseCRC32CIntrinsics) {
328 warning("CRC32C is not available on the CPU");
329 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
330 }
331
332 if (FLAG_IS_DEFAULT(UseFMA)) {
333 FLAG_SET_DEFAULT(UseFMA, true);
334 }
335
336 if (FLAG_IS_DEFAULT(UseMD5Intrinsics)) {
337 UseMD5Intrinsics = true;
338 }
339
340 if (VM_Version::supports_sha1() || VM_Version::supports_sha256() ||
341 VM_Version::supports_sha3() || VM_Version::supports_sha512()) {
342 if (FLAG_IS_DEFAULT(UseSHA)) {
343 FLAG_SET_DEFAULT(UseSHA, true);
344 }
345 } else if (UseSHA) {
346 warning("SHA instructions are not available on this CPU");
347 FLAG_SET_DEFAULT(UseSHA, false);
348 }
349
350 if (UseSHA && VM_Version::supports_sha1()) {
351 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
352 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
353 }
354 } else if (UseSHA1Intrinsics) {
355 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
356 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
357 }
358
359 if (UseSHA && VM_Version::supports_sha256()) {
360 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
361 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
362 }
363 } else if (UseSHA256Intrinsics) {
364 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
365 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
366 }
367
368 if (UseSHA) {
369 // No need to check VM_Version::supports_sha3(), since a fallback GPR intrinsic implementation is provided.
370 if (FLAG_IS_DEFAULT(UseSHA3Intrinsics)) {
371 FLAG_SET_DEFAULT(UseSHA3Intrinsics, true);
372 }
373 } else if (UseSHA3Intrinsics) {
374 // Matches the documented and tested behavior: the -UseSHA option disables all SHA intrinsics.
375 warning("UseSHA3Intrinsics requires that UseSHA is enabled.");
376 FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
377 }
378
379 if (UseSHA3Intrinsics && VM_Version::supports_sha3()) {
380 // Auto-enable UseSIMDForSHA3Intrinsic on hardware with performance benefit.
381 // Note that the evaluation of SHA3 extension Intrinsics shows better performance
382 // on Apple and Qualcomm silicon but worse performance on Neoverse V1 and N2.
383 if (_cpu == CPU_APPLE || _cpu == CPU_QUALCOMM) { // Apple or Qualcomm silicon
384 if (FLAG_IS_DEFAULT(UseSIMDForSHA3Intrinsic)) {
385 FLAG_SET_DEFAULT(UseSIMDForSHA3Intrinsic, true);
386 }
387 }
388 }
389 if (UseSHA3Intrinsics && UseSIMDForSHA3Intrinsic && !VM_Version::supports_sha3()) {
390 warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU.");
391 FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
392 }
393
394 if (UseSHA && VM_Version::supports_sha512()) {
395 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
396 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
397 }
398 } else if (UseSHA512Intrinsics) {
399 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
400 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
401 }
402
403 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA3Intrinsics || UseSHA512Intrinsics)) {
404 FLAG_SET_DEFAULT(UseSHA, false);
405 }
406
407 if (VM_Version::supports_pmull()) {
408 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
409 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
410 }
411 } else if (UseGHASHIntrinsics) {
412 warning("GHASH intrinsics are not available on this CPU");
413 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
414 }
415
416 if (supports_feature(CPU_ASIMD)) {
417 if (FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
418 UseChaCha20Intrinsics = true;
419 }
420 } else if (UseChaCha20Intrinsics) {
421 if (!FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
422 warning("ChaCha20 intrinsic requires ASIMD instructions");
423 }
424 FLAG_SET_DEFAULT(UseChaCha20Intrinsics, false);
425 }
426
427 if (supports_feature(CPU_ASIMD)) {
428 if (FLAG_IS_DEFAULT(UseKyberIntrinsics)) {
429 UseKyberIntrinsics = true;
430 }
431 } else if (UseKyberIntrinsics) {
432 if (!FLAG_IS_DEFAULT(UseKyberIntrinsics)) {
433 warning("Kyber intrinsics require ASIMD instructions");
434 }
435 FLAG_SET_DEFAULT(UseKyberIntrinsics, false);
436 }
437
438 if (supports_feature(CPU_ASIMD)) {
439 if (FLAG_IS_DEFAULT(UseDilithiumIntrinsics)) {
440 UseDilithiumIntrinsics = true;
441 }
442 } else if (UseDilithiumIntrinsics) {
443 if (!FLAG_IS_DEFAULT(UseDilithiumIntrinsics)) {
444 warning("Dilithium intrinsics require ASIMD instructions");
445 }
446 FLAG_SET_DEFAULT(UseDilithiumIntrinsics, false);
447 }
448
449 if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
450 UseBASE64Intrinsics = true;
451 }
452
453 if (is_zva_enabled()) {
454 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
455 FLAG_SET_DEFAULT(UseBlockZeroing, true);
456 }
457 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
458 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
459 }
460 } else if (UseBlockZeroing) {
461 if (!FLAG_IS_DEFAULT(UseBlockZeroing)) {
462 warning("DC ZVA is not available on this CPU");
463 }
464 FLAG_SET_DEFAULT(UseBlockZeroing, false);
465 }
466
467 if (VM_Version::supports_sve2()) {
468 if (FLAG_IS_DEFAULT(UseSVE)) {
469 FLAG_SET_DEFAULT(UseSVE, 2);
470 }
471 } else if (VM_Version::supports_sve()) {
472 if (FLAG_IS_DEFAULT(UseSVE)) {
473 FLAG_SET_DEFAULT(UseSVE, 1);
474 } else if (UseSVE > 1) {
475 warning("SVE2 specified, but not supported on current CPU. Using SVE.");
476 FLAG_SET_DEFAULT(UseSVE, 1);
477 }
478 } else if (UseSVE > 0) {
479 warning("UseSVE specified, but not supported on current CPU. Disabling SVE.");
480 FLAG_SET_DEFAULT(UseSVE, 0);
481 }
482
483 if (UseSVE > 0) {
484 int vl = get_current_sve_vector_length();
485 if (vl < 0) {
486 warning("Unable to get SVE vector length on this system. "
487 "Disabling SVE. Specify -XX:UseSVE=0 to shun this warning.");
488 FLAG_SET_DEFAULT(UseSVE, 0);
489 } else if ((vl == 0) || ((vl % FloatRegister::sve_vl_min) != 0) || !is_power_of_2(vl)) {
490 warning("Detected SVE vector length (%d) should be a power of two and a multiple of %d. "
491 "Disabling SVE. Specify -XX:UseSVE=0 to shun this warning.",
492 vl, FloatRegister::sve_vl_min);
493 FLAG_SET_DEFAULT(UseSVE, 0);
494 } else {
495 _initial_sve_vector_length = vl;
496 }
497 }
498
499 // This machine allows unaligned memory accesses
500 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
501 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
502 }
503
504 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
505 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
506 }
507
508 if (!UsePopCountInstruction) {
509 warning("UsePopCountInstruction is always enabled on this CPU");
510 UsePopCountInstruction = true;
511 }
512
513 if (UseBranchProtection == nullptr || strcmp(UseBranchProtection, "none") == 0) {
514 _rop_protection = false;
515 } else if (strcmp(UseBranchProtection, "standard") == 0 ||
516 strcmp(UseBranchProtection, "pac-ret") == 0) {
517 _rop_protection = false;
518 // Enable ROP-protection if
519 // 1) this code has been built with branch-protection and
520 // 2) the CPU/OS supports it
521 #ifdef __ARM_FEATURE_PAC_DEFAULT
522 if (!VM_Version::supports_paca()) {
523 // Disable PAC to prevent illegal instruction crashes.
524 warning("ROP-protection specified, but not supported on this CPU. Disabling ROP-protection.");
525 } else {
526 _rop_protection = true;
527 }
528 #else
529 warning("ROP-protection specified, but this VM was built without ROP-protection support. Disabling ROP-protection.");
530 #endif
531 } else {
532 vm_exit_during_initialization(err_msg("Unsupported UseBranchProtection: %s", UseBranchProtection));
533 }
534
535 if (_rop_protection == true) {
536 // Determine the mask of address bits used for PAC. Clear bit 55 of
537 // the input to make it look like a user address.
538 _pac_mask = (uintptr_t)pauth_strip_pointer((address)~(UINT64_C(1) << 55));
539 }
540
541 #ifdef COMPILER2
542 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
543 UseMultiplyToLenIntrinsic = true;
544 }
545
546 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
547 UseSquareToLenIntrinsic = true;
548 }
549
550 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
551 UseMulAddIntrinsic = true;
552 }
553
554 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
555 UseMontgomeryMultiplyIntrinsic = true;
556 }
557 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
558 UseMontgomerySquareIntrinsic = true;
559 }
560
561 if (UseSVE > 0) {
562 if (FLAG_IS_DEFAULT(MaxVectorSize)) {
563 MaxVectorSize = _initial_sve_vector_length;
564 } else if (MaxVectorSize < FloatRegister::sve_vl_min) {
565 warning("SVE does not support vector length less than %d bytes. Disabling SVE.",
566 FloatRegister::sve_vl_min);
567 UseSVE = 0;
568 } else if (!((MaxVectorSize % FloatRegister::sve_vl_min) == 0 && is_power_of_2(MaxVectorSize))) {
569 vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize));
570 }
571
572 if (UseSVE > 0) {
573 // Acquire the largest supported vector length of this machine
574 _max_supported_sve_vector_length = set_and_get_current_sve_vector_length(FloatRegister::sve_vl_max);
575
576 if (MaxVectorSize != _max_supported_sve_vector_length) {
577 int new_vl = set_and_get_current_sve_vector_length(MaxVectorSize);
578 if (new_vl < 0) {
579 vm_exit_during_initialization(
580 err_msg("Current system does not support SVE vector length for MaxVectorSize: %d",
581 (int)MaxVectorSize));
582 } else if (new_vl != MaxVectorSize) {
583 warning("Current system only supports max SVE vector length %d. Set MaxVectorSize to %d",
584 new_vl, new_vl);
585 }
586 MaxVectorSize = new_vl;
587 }
588 _initial_sve_vector_length = MaxVectorSize;
589 }
590 }
591
592 if (UseSVE == 0) { // NEON
593 int min_vector_size = 8;
594 int max_vector_size = FloatRegister::neon_vl;
595 if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
596 if (!is_power_of_2(MaxVectorSize)) {
597 vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize));
598 } else if (MaxVectorSize < min_vector_size) {
599 warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
600 FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
601 } else if (MaxVectorSize > max_vector_size) {
602 warning("MaxVectorSize must be at most %i on this platform", max_vector_size);
603 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
604 }
605 } else {
606 FLAG_SET_DEFAULT(MaxVectorSize, FloatRegister::neon_vl);
607 }
608 }
609
610 int inline_size = (UseSVE > 0 && MaxVectorSize >= FloatRegister::sve_vl_min) ? MaxVectorSize : 0;
611 if (FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize)) {
612 FLAG_SET_DEFAULT(ArrayOperationPartialInlineSize, inline_size);
613 } else if (ArrayOperationPartialInlineSize != 0 && ArrayOperationPartialInlineSize != inline_size) {
614 warning("Setting ArrayOperationPartialInlineSize to %d", inline_size);
615 ArrayOperationPartialInlineSize = inline_size;
616 }
617
618 if (FLAG_IS_DEFAULT(OptoScheduling)) {
619 OptoScheduling = true;
620 }
621
622 if (FLAG_IS_DEFAULT(AlignVector)) {
623 AlignVector = AvoidUnalignedAccesses;
624 }
625
626 if (FLAG_IS_DEFAULT(UsePoly1305Intrinsics)) {
627 FLAG_SET_DEFAULT(UsePoly1305Intrinsics, true);
628 }
629
630 if (FLAG_IS_DEFAULT(UseVectorizedHashCodeIntrinsic)) {
631 FLAG_SET_DEFAULT(UseVectorizedHashCodeIntrinsic, true);
632 }
633 #endif
634
635 _spin_wait = get_spin_wait_desc();
636
637 check_virtualizations();
638
639 #ifdef __APPLE__
640 DefaultWXWriteMode = UseOldWX ? WXWrite : WXArmedForWrite;
641
642 if (TraceWXHealing) {
643 if (pthread_jit_write_protect_supported_np()) {
644 tty->print_cr("### TraceWXHealing is in use");
645 if (StressWXHealing) {
646 tty->print_cr("### StressWXHealing is in use");
647 }
648 } else {
649 tty->print_cr("WX Healing is not in use because MAP_JIT write protection "
650 "does not work on this system.");
651 }
652 }
653 #endif
654
655 // Sync SVE related CPU features with flags
656 if (UseSVE < 2) {
657 clear_feature(CPU_SVE2);
658 clear_feature(CPU_SVEBITPERM);
659 }
660 if (UseSVE < 1) {
661 clear_feature(CPU_SVE);
662 }
663
664 // Construct the "features" string
665 stringStream ss(512);
666 ss.print("0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
667 if (_model2) {
668 ss.print("(0x%03x)", _model2);
669 }
670 ss.print(", ");
671 int features_offset = (int)ss.size();
672 insert_features_names(_features, ss);
673
674 _cpu_info_string = ss.as_string(true);
675 _features_string = _cpu_info_string + features_offset;
676 }
677
678 void VM_Version::insert_features_names(uint64_t features, stringStream& ss) {
679 int i = 0;
680 ss.join([&]() {
681 const char* str = nullptr;
682 while ((i < MAX_CPU_FEATURES) && (str == nullptr)) {
683 if (supports_feature(features, (VM_Version::Feature_Flag)i)) {
684 str = _features_names[i];
685 }
686 i += 1;
687 }
688 return str;
689 }, ", ");
690 }
691
692 void VM_Version::get_cpu_features_name(void* features_buffer, stringStream& ss) {
693 uint64_t features = *(uint64_t*)features_buffer;
694 insert_features_names(features, ss);
695 }
696
697 void VM_Version::get_missing_features_name(void* features_set1, void* features_set2, stringStream& ss) {
698 uint64_t vm_features_set1 = *(uint64_t*)features_set1;
699 uint64_t vm_features_set2 = *(uint64_t*)features_set2;
700 int i = 0;
701 ss.join([&]() {
702 const char* str = nullptr;
703 while ((i < MAX_CPU_FEATURES) && (str == nullptr)) {
704 Feature_Flag flag = (Feature_Flag)i;
705 if (supports_feature(vm_features_set1, flag) && !supports_feature(vm_features_set2, flag)) {
706 str = _features_names[i];
707 }
708 i += 1;
709 }
710 return str;
711 }, ", ");
712 }
713
714 int VM_Version::cpu_features_size() {
715 return sizeof(_features);
716 }
717
718 void VM_Version::store_cpu_features(void* buf) {
719 *(uint64_t*)buf = _features;
720 }
721
722 bool VM_Version::supports_features(void* features_buffer) {
723 uint64_t features_to_test = *(uint64_t*)features_buffer;
724 return (_features & features_to_test) == features_to_test;
725 }
726
727 #if defined(LINUX)
728 static bool check_info_file(const char* fpath,
729 const char* virt1, VirtualizationType vt1,
730 const char* virt2, VirtualizationType vt2) {
731 char line[500];
732 FILE* fp = os::fopen(fpath, "r");
733 if (fp == nullptr) {
734 return false;
735 }
736 while (fgets(line, sizeof(line), fp) != nullptr) {
737 if (strcasestr(line, virt1) != nullptr) {
738 Abstract_VM_Version::_detected_virtualization = vt1;
739 fclose(fp);
740 return true;
741 }
742 if (virt2 != nullptr && strcasestr(line, virt2) != nullptr) {
743 Abstract_VM_Version::_detected_virtualization = vt2;
744 fclose(fp);
745 return true;
746 }
747 }
748 fclose(fp);
749 return false;
750 }
751 #endif
752
753 void VM_Version::check_virtualizations() {
754 #if defined(LINUX)
755 const char* pname_file = "/sys/devices/virtual/dmi/id/product_name";
756 const char* tname_file = "/sys/hypervisor/type";
757 if (check_info_file(pname_file, "KVM", KVM, "VMWare", VMWare)) {
758 return;
759 }
760 check_info_file(tname_file, "Xen", XenPVHVM, nullptr, NoDetectedVirtualization);
761 #endif
762 }
763
764 void VM_Version::print_platform_virtualization_info(outputStream* st) {
765 #if defined(LINUX)
766 VirtualizationType vrt = VM_Version::get_detected_virtualization();
767 if (vrt == KVM) {
768 st->print_cr("KVM virtualization detected");
769 } else if (vrt == VMWare) {
770 st->print_cr("VMWare virtualization detected");
771 } else if (vrt == XenPVHVM) {
772 st->print_cr("Xen virtualization detected");
773 }
774 #endif
775 }
776
777 void VM_Version::initialize_cpu_information(void) {
778 // do nothing if cpu info has been initialized
779 if (_initialized) {
780 return;
781 }
782
783 _no_of_cores = os::processor_count();
784 _no_of_threads = _no_of_cores;
785 _no_of_sockets = _no_of_cores;
786 os::snprintf_checked(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "AArch64");
787
788 int desc_len = os::snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "AArch64 ");
789 get_compatible_board(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len);
790 desc_len = (int)strlen(_cpu_desc);
791 os::snprintf_checked(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len, " %s", _cpu_info_string);
792
793 _initialized = true;
794 }