1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2020, Red Hat Inc. All rights reserved.
4 * Copyright 2025 Arm Limited and/or its affiliates.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #include "pauth_aarch64.hpp"
28 #include "register_aarch64.hpp"
29 #include "runtime/arguments.hpp"
30 #include "runtime/globals_extension.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/os.inline.hpp"
33 #include "runtime/vm_version.hpp"
34 #include "utilities/formatBuffer.hpp"
35 #include "utilities/macros.hpp"
36 #include "utilities/ostream.hpp"
37
38 int VM_Version::_cpu;
39 int VM_Version::_model;
40 int VM_Version::_model2;
41 int VM_Version::_variant;
42 int VM_Version::_revision;
43 int VM_Version::_stepping;
44
45 int VM_Version::_zva_length;
46 int VM_Version::_dcache_line_size;
47 int VM_Version::_icache_line_size;
48 int VM_Version::_initial_sve_vector_length;
49 int VM_Version::_max_supported_sve_vector_length;
50 bool VM_Version::_rop_protection;
51 uintptr_t VM_Version::_pac_mask;
52
53 const char* VM_Version::_features_names[MAX_CPU_FEATURES] = { nullptr };
54
55 SpinWait VM_Version::_spin_wait;
56
57 static SpinWait get_spin_wait_desc() {
58 SpinWait spin_wait(OnSpinWaitInst, OnSpinWaitInstCount);
59 if (spin_wait.inst() == SpinWait::SB && !VM_Version::supports_sb()) {
60 vm_exit_during_initialization("OnSpinWaitInst is SB but current CPU does not support SB instruction");
61 }
62
63 return spin_wait;
64 }
65
66 void VM_Version::initialize() {
67 #define SET_CPU_FEATURE_NAME(id, name, bit) \
68 _features_names[bit] = XSTR(name);
69 CPU_FEATURE_FLAGS(SET_CPU_FEATURE_NAME)
70 #undef SET_CPU_FEATURE_NAME
71
72 _supports_atomic_getset4 = true;
73 _supports_atomic_getadd4 = true;
74 _supports_atomic_getset8 = true;
75 _supports_atomic_getadd8 = true;
76
77 get_os_cpu_info();
78
79 int dcache_line = VM_Version::dcache_line_size();
80
81 // Limit AllocatePrefetchDistance so that it does not exceed the
82 // static constraint of 512 defined in runtime/globals.hpp.
83 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
84 FLAG_SET_DEFAULT(AllocatePrefetchDistance, MIN2(512, 3*dcache_line));
85
86 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
87 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
88 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
89 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
90 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
91 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
92 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
93 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
94
95 if (PrefetchCopyIntervalInBytes != -1 &&
96 ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
97 warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
98 PrefetchCopyIntervalInBytes &= ~7;
99 if (PrefetchCopyIntervalInBytes >= 32768)
100 PrefetchCopyIntervalInBytes = 32760;
101 }
102
103 if (AllocatePrefetchDistance != -1 && (AllocatePrefetchDistance & 7)) {
104 warning("AllocatePrefetchDistance must be multiple of 8");
105 AllocatePrefetchDistance &= ~7;
106 }
107
108 if (AllocatePrefetchStepSize & 7) {
109 warning("AllocatePrefetchStepSize must be multiple of 8");
110 AllocatePrefetchStepSize &= ~7;
111 }
112
113 if (SoftwarePrefetchHintDistance != -1 &&
114 (SoftwarePrefetchHintDistance & 7)) {
115 warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
116 SoftwarePrefetchHintDistance &= ~7;
117 }
118
119 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (dcache_line > ContendedPaddingWidth)) {
120 ContendedPaddingWidth = dcache_line;
121 }
122
123 if (os::supports_map_sync()) {
124 // if dcpop is available publish data cache line flush size via
125 // generic field, otherwise let if default to zero thereby
126 // disabling writeback
127 if (VM_Version::supports_dcpop()) {
128 _data_cache_line_flush_size = dcache_line;
129 }
130 }
131
132 // Enable vendor specific features
133
134 // Ampere eMAG
135 if (_cpu == CPU_AMCC && (_model == CPU_MODEL_EMAG) && (_variant == 0x3)) {
136 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
137 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
138 }
139 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
140 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
141 }
142 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
143 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, !(_revision == 1 || _revision == 2));
144 }
145 }
146
147 // Ampere CPUs
148 if (_cpu == CPU_AMPERE && ((_model == CPU_MODEL_AMPERE_1) ||
149 (_model == CPU_MODEL_AMPERE_1A) ||
150 (_model == CPU_MODEL_AMPERE_1B))) {
151 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
152 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
153 }
154 if (FLAG_IS_DEFAULT(OnSpinWaitInst)) {
155 FLAG_SET_DEFAULT(OnSpinWaitInst, "isb");
156 }
157 if (FLAG_IS_DEFAULT(OnSpinWaitInstCount)) {
158 FLAG_SET_DEFAULT(OnSpinWaitInstCount, 2);
159 }
160 if (FLAG_IS_DEFAULT(CodeEntryAlignment) &&
161 (_model == CPU_MODEL_AMPERE_1A || _model == CPU_MODEL_AMPERE_1B)) {
162 FLAG_SET_DEFAULT(CodeEntryAlignment, 32);
163 }
164 if (FLAG_IS_DEFAULT(AlwaysMergeDMB)) {
165 FLAG_SET_DEFAULT(AlwaysMergeDMB, false);
166 }
167 }
168
169 // ThunderX
170 if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
171 guarantee(_variant != 0, "Pre-release hardware no longer supported.");
172 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
173 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
174 }
175 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
176 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
177 }
178 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
179 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
180 }
181 }
182
183 // ThunderX2
184 if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
185 (_cpu == CPU_BROADCOM && (_model == 0x516))) {
186 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
187 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
188 }
189 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
190 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
191 }
192 }
193
194 // HiSilicon TSV110
195 if (_cpu == CPU_HISILICON && _model == 0xd01) {
196 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
197 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
198 }
199 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
200 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
201 }
202 }
203
204 // Cortex A53
205 if (_cpu == CPU_ARM && model_is(0xd03)) {
206 set_feature(CPU_A53MAC);
207 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
208 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
209 }
210 }
211
212 // Cortex A73
213 if (_cpu == CPU_ARM && model_is(0xd09)) {
214 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
215 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
216 }
217 // A73 is faster with short-and-easy-for-speculative-execution-loop
218 if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
219 FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
220 }
221 }
222
223 // Neoverse
224 // N1: 0xd0c
225 // N2: 0xd49
226 // N3: 0xd8e
227 // V1: 0xd40
228 // V2: 0xd4f
229 // V3: 0xd84
230 if (_cpu == CPU_ARM && (model_is(0xd0c) || model_is(0xd49) ||
231 model_is(0xd40) || model_is(0xd4f) ||
232 model_is(0xd8e) || model_is(0xd84))) {
233 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
234 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
235 }
236
237 if (FLAG_IS_DEFAULT(OnSpinWaitInst)) {
238 FLAG_SET_DEFAULT(OnSpinWaitInst, "isb");
239 }
240
241 if (FLAG_IS_DEFAULT(OnSpinWaitInstCount)) {
242 FLAG_SET_DEFAULT(OnSpinWaitInstCount, 1);
243 }
244 if (FLAG_IS_DEFAULT(AlwaysMergeDMB)) {
245 FLAG_SET_DEFAULT(AlwaysMergeDMB, false);
246 }
247 }
248
249 if (supports_feature(CPU_FP) || supports_feature(CPU_ASIMD)) {
250 if (FLAG_IS_DEFAULT(UseSignumIntrinsic)) {
251 FLAG_SET_DEFAULT(UseSignumIntrinsic, true);
252 }
253 }
254
255 if (FLAG_IS_DEFAULT(UseCRC32)) {
256 UseCRC32 = VM_Version::supports_crc32();
257 }
258
259 if (UseCRC32 && !VM_Version::supports_crc32()) {
260 warning("UseCRC32 specified, but not supported on this CPU");
261 FLAG_SET_DEFAULT(UseCRC32, false);
262 }
263
264 // Neoverse
265 // V1: 0xd40
266 // V2: 0xd4f
267 // V3: 0xd84
268 if (_cpu == CPU_ARM &&
269 (model_is(0xd40) || model_is(0xd4f) || model_is(0xd84))) {
270 if (FLAG_IS_DEFAULT(UseCryptoPmullForCRC32)) {
271 FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, true);
272 }
273 if (FLAG_IS_DEFAULT(CodeEntryAlignment)) {
274 FLAG_SET_DEFAULT(CodeEntryAlignment, 32);
275 }
276 }
277
278 if (UseCryptoPmullForCRC32 && (!VM_Version::supports_pmull() || !VM_Version::supports_sha3() || !VM_Version::supports_crc32())) {
279 warning("UseCryptoPmullForCRC32 specified, but not supported on this CPU");
280 FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, false);
281 }
282
283 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
284 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
285 }
286
287 if (UseVectorizedMismatchIntrinsic) {
288 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
289 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
290 }
291
292 if (VM_Version::supports_lse()) {
293 if (FLAG_IS_DEFAULT(UseLSE))
294 FLAG_SET_DEFAULT(UseLSE, true);
295 } else {
296 if (UseLSE) {
297 warning("UseLSE specified, but not supported on this CPU");
298 FLAG_SET_DEFAULT(UseLSE, false);
299 }
300 }
301
302 if (VM_Version::supports_aes()) {
303 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
304 UseAESIntrinsics =
305 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
306 if (UseAESIntrinsics && !UseAES) {
307 warning("UseAESIntrinsics enabled, but UseAES not, enabling");
308 UseAES = true;
309 }
310 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
311 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
312 }
313 } else {
314 if (UseAES) {
315 warning("AES instructions are not available on this CPU");
316 FLAG_SET_DEFAULT(UseAES, false);
317 }
318 if (UseAESIntrinsics) {
319 warning("AES intrinsics are not available on this CPU");
320 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
321 }
322 if (UseAESCTRIntrinsics) {
323 warning("AES/CTR intrinsics are not available on this CPU");
324 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
325 }
326 }
327
328
329 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
330 UseCRC32Intrinsics = true;
331 }
332
333 if (VM_Version::supports_crc32()) {
334 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
335 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
336 }
337 } else if (UseCRC32CIntrinsics) {
338 warning("CRC32C is not available on the CPU");
339 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
340 }
341
342 if (FLAG_IS_DEFAULT(UseFMA)) {
343 FLAG_SET_DEFAULT(UseFMA, true);
344 }
345
346 if (FLAG_IS_DEFAULT(UseMD5Intrinsics)) {
347 UseMD5Intrinsics = true;
348 }
349
350 if (VM_Version::supports_sha1() || VM_Version::supports_sha256() ||
351 VM_Version::supports_sha3() || VM_Version::supports_sha512()) {
352 if (FLAG_IS_DEFAULT(UseSHA)) {
353 FLAG_SET_DEFAULT(UseSHA, true);
354 }
355 } else if (UseSHA) {
356 warning("SHA instructions are not available on this CPU");
357 FLAG_SET_DEFAULT(UseSHA, false);
358 }
359
360 if (UseSHA && VM_Version::supports_sha1()) {
361 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
362 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
363 }
364 } else if (UseSHA1Intrinsics) {
365 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
366 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
367 }
368
369 if (UseSHA && VM_Version::supports_sha256()) {
370 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
371 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
372 }
373 } else if (UseSHA256Intrinsics) {
374 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
375 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
376 }
377
378 if (UseSHA && VM_Version::supports_sha3()) {
379 // Auto-enable UseSHA3Intrinsics on hardware with performance benefit.
380 // Note that the evaluation of UseSHA3Intrinsics shows better performance
381 // on Apple silicon but worse performance on Neoverse V1 and N2.
382 if (_cpu == CPU_APPLE) { // Apple silicon
383 if (FLAG_IS_DEFAULT(UseSHA3Intrinsics)) {
384 FLAG_SET_DEFAULT(UseSHA3Intrinsics, true);
385 }
386 }
387 } else if (UseSHA3Intrinsics && UseSIMDForSHA3Intrinsic) {
388 warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU.");
389 FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
390 }
391
392 if (UseSHA && VM_Version::supports_sha512()) {
393 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
394 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
395 }
396 } else if (UseSHA512Intrinsics) {
397 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
398 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
399 }
400
401 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA3Intrinsics || UseSHA512Intrinsics)) {
402 FLAG_SET_DEFAULT(UseSHA, false);
403 }
404
405 if (VM_Version::supports_pmull()) {
406 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
407 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
408 }
409 } else if (UseGHASHIntrinsics) {
410 warning("GHASH intrinsics are not available on this CPU");
411 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
412 }
413
414 if (supports_feature(CPU_ASIMD)) {
415 if (FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
416 UseChaCha20Intrinsics = true;
417 }
418 } else if (UseChaCha20Intrinsics) {
419 if (!FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
420 warning("ChaCha20 intrinsic requires ASIMD instructions");
421 }
422 FLAG_SET_DEFAULT(UseChaCha20Intrinsics, false);
423 }
424
425 if (supports_feature(CPU_ASIMD)) {
426 if (FLAG_IS_DEFAULT(UseKyberIntrinsics)) {
427 UseKyberIntrinsics = true;
428 }
429 } else if (UseKyberIntrinsics) {
430 if (!FLAG_IS_DEFAULT(UseKyberIntrinsics)) {
431 warning("Kyber intrinsics require ASIMD instructions");
432 }
433 FLAG_SET_DEFAULT(UseKyberIntrinsics, false);
434 }
435
436 if (supports_feature(CPU_ASIMD)) {
437 if (FLAG_IS_DEFAULT(UseDilithiumIntrinsics)) {
438 UseDilithiumIntrinsics = true;
439 }
440 } else if (UseDilithiumIntrinsics) {
441 if (!FLAG_IS_DEFAULT(UseDilithiumIntrinsics)) {
442 warning("Dilithium intrinsics require ASIMD instructions");
443 }
444 FLAG_SET_DEFAULT(UseDilithiumIntrinsics, false);
445 }
446
447 if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
448 UseBASE64Intrinsics = true;
449 }
450
451 if (is_zva_enabled()) {
452 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
453 FLAG_SET_DEFAULT(UseBlockZeroing, true);
454 }
455 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
456 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
457 }
458 } else if (UseBlockZeroing) {
459 warning("DC ZVA is not available on this CPU");
460 FLAG_SET_DEFAULT(UseBlockZeroing, false);
461 }
462
463 if (VM_Version::supports_sve2()) {
464 if (FLAG_IS_DEFAULT(UseSVE)) {
465 FLAG_SET_DEFAULT(UseSVE, 2);
466 }
467 } else if (VM_Version::supports_sve()) {
468 if (FLAG_IS_DEFAULT(UseSVE)) {
469 FLAG_SET_DEFAULT(UseSVE, 1);
470 } else if (UseSVE > 1) {
471 warning("SVE2 specified, but not supported on current CPU. Using SVE.");
472 FLAG_SET_DEFAULT(UseSVE, 1);
473 }
474 } else if (UseSVE > 0) {
475 warning("UseSVE specified, but not supported on current CPU. Disabling SVE.");
476 FLAG_SET_DEFAULT(UseSVE, 0);
477 }
478
479 if (UseSVE > 0) {
480 int vl = get_current_sve_vector_length();
481 if (vl < 0) {
482 warning("Unable to get SVE vector length on this system. "
483 "Disabling SVE. Specify -XX:UseSVE=0 to shun this warning.");
484 FLAG_SET_DEFAULT(UseSVE, 0);
485 } else if ((vl == 0) || ((vl % FloatRegister::sve_vl_min) != 0) || !is_power_of_2(vl)) {
486 warning("Detected SVE vector length (%d) should be a power of two and a multiple of %d. "
487 "Disabling SVE. Specify -XX:UseSVE=0 to shun this warning.",
488 vl, FloatRegister::sve_vl_min);
489 FLAG_SET_DEFAULT(UseSVE, 0);
490 } else {
491 _initial_sve_vector_length = vl;
492 }
493 }
494
495 // This machine allows unaligned memory accesses
496 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
497 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
498 }
499
500 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
501 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
502 }
503
504 if (!UsePopCountInstruction) {
505 warning("UsePopCountInstruction is always enabled on this CPU");
506 UsePopCountInstruction = true;
507 }
508
509 if (UseBranchProtection == nullptr || strcmp(UseBranchProtection, "none") == 0) {
510 _rop_protection = false;
511 } else if (strcmp(UseBranchProtection, "standard") == 0 ||
512 strcmp(UseBranchProtection, "pac-ret") == 0) {
513 _rop_protection = false;
514 // Enable ROP-protection if
515 // 1) this code has been built with branch-protection and
516 // 2) the CPU/OS supports it
517 #ifdef __ARM_FEATURE_PAC_DEFAULT
518 if (!VM_Version::supports_paca()) {
519 // Disable PAC to prevent illegal instruction crashes.
520 warning("ROP-protection specified, but not supported on this CPU. Disabling ROP-protection.");
521 } else {
522 _rop_protection = true;
523 }
524 #else
525 warning("ROP-protection specified, but this VM was built without ROP-protection support. Disabling ROP-protection.");
526 #endif
527 } else {
528 vm_exit_during_initialization(err_msg("Unsupported UseBranchProtection: %s", UseBranchProtection));
529 }
530
531 if (_rop_protection == true) {
532 // Determine the mask of address bits used for PAC. Clear bit 55 of
533 // the input to make it look like a user address.
534 _pac_mask = (uintptr_t)pauth_strip_pointer((address)~(UINT64_C(1) << 55));
535 }
536
537 #ifdef COMPILER2
538 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
539 UseMultiplyToLenIntrinsic = true;
540 }
541
542 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
543 UseSquareToLenIntrinsic = true;
544 }
545
546 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
547 UseMulAddIntrinsic = true;
548 }
549
550 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
551 UseMontgomeryMultiplyIntrinsic = true;
552 }
553 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
554 UseMontgomerySquareIntrinsic = true;
555 }
556
557 if (UseSVE > 0) {
558 if (FLAG_IS_DEFAULT(MaxVectorSize)) {
559 MaxVectorSize = _initial_sve_vector_length;
560 } else if (MaxVectorSize < FloatRegister::sve_vl_min) {
561 warning("SVE does not support vector length less than %d bytes. Disabling SVE.",
562 FloatRegister::sve_vl_min);
563 UseSVE = 0;
564 } else if (!((MaxVectorSize % FloatRegister::sve_vl_min) == 0 && is_power_of_2(MaxVectorSize))) {
565 vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize));
566 }
567
568 if (UseSVE > 0) {
569 // Acquire the largest supported vector length of this machine
570 _max_supported_sve_vector_length = set_and_get_current_sve_vector_length(FloatRegister::sve_vl_max);
571
572 if (MaxVectorSize != _max_supported_sve_vector_length) {
573 int new_vl = set_and_get_current_sve_vector_length(MaxVectorSize);
574 if (new_vl < 0) {
575 vm_exit_during_initialization(
576 err_msg("Current system does not support SVE vector length for MaxVectorSize: %d",
577 (int)MaxVectorSize));
578 } else if (new_vl != MaxVectorSize) {
579 warning("Current system only supports max SVE vector length %d. Set MaxVectorSize to %d",
580 new_vl, new_vl);
581 }
582 MaxVectorSize = new_vl;
583 }
584 _initial_sve_vector_length = MaxVectorSize;
585 }
586 }
587
588 if (UseSVE == 0) { // NEON
589 int min_vector_size = 8;
590 int max_vector_size = FloatRegister::neon_vl;
591 if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
592 if (!is_power_of_2(MaxVectorSize)) {
593 vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize));
594 } else if (MaxVectorSize < min_vector_size) {
595 warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
596 FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
597 } else if (MaxVectorSize > max_vector_size) {
598 warning("MaxVectorSize must be at most %i on this platform", max_vector_size);
599 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
600 }
601 } else {
602 FLAG_SET_DEFAULT(MaxVectorSize, FloatRegister::neon_vl);
603 }
604 }
605
606 int inline_size = (UseSVE > 0 && MaxVectorSize >= FloatRegister::sve_vl_min) ? MaxVectorSize : 0;
607 if (FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize)) {
608 FLAG_SET_DEFAULT(ArrayOperationPartialInlineSize, inline_size);
609 } else if (ArrayOperationPartialInlineSize != 0 && ArrayOperationPartialInlineSize != inline_size) {
610 warning("Setting ArrayOperationPartialInlineSize to %d", inline_size);
611 ArrayOperationPartialInlineSize = inline_size;
612 }
613
614 if (FLAG_IS_DEFAULT(OptoScheduling)) {
615 OptoScheduling = true;
616 }
617
618 if (FLAG_IS_DEFAULT(AlignVector)) {
619 AlignVector = AvoidUnalignedAccesses;
620 }
621
622 if (FLAG_IS_DEFAULT(UsePoly1305Intrinsics)) {
623 FLAG_SET_DEFAULT(UsePoly1305Intrinsics, true);
624 }
625
626 if (FLAG_IS_DEFAULT(UseVectorizedHashCodeIntrinsic)) {
627 FLAG_SET_DEFAULT(UseVectorizedHashCodeIntrinsic, true);
628 }
629 #endif
630
631 _spin_wait = get_spin_wait_desc();
632
633 check_virtualizations();
634
635 // Sync SVE related CPU features with flags
636 if (UseSVE < 2) {
637 clear_feature(CPU_SVE2);
638 clear_feature(CPU_SVEBITPERM);
639 }
640 if (UseSVE < 1) {
641 clear_feature(CPU_SVE);
642 }
643
644 // Construct the "features" string
645 stringStream ss(512);
646 ss.print("0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
647 if (_model2) {
648 ss.print("(0x%03x)", _model2);
649 }
650 ss.print(", ");
651 int features_offset = (int)ss.size();
652 insert_features_names(_features, ss);
653
654 _cpu_info_string = ss.as_string(true);
655 _features_string = _cpu_info_string + features_offset;
656 }
657
658 #if defined(LINUX)
659 static bool check_info_file(const char* fpath,
660 const char* virt1, VirtualizationType vt1,
661 const char* virt2, VirtualizationType vt2) {
662 char line[500];
663 FILE* fp = os::fopen(fpath, "r");
664 if (fp == nullptr) {
665 return false;
666 }
667 while (fgets(line, sizeof(line), fp) != nullptr) {
668 if (strcasestr(line, virt1) != nullptr) {
669 Abstract_VM_Version::_detected_virtualization = vt1;
670 fclose(fp);
671 return true;
672 }
673 if (virt2 != nullptr && strcasestr(line, virt2) != nullptr) {
674 Abstract_VM_Version::_detected_virtualization = vt2;
675 fclose(fp);
676 return true;
677 }
678 }
679 fclose(fp);
680 return false;
681 }
682 #endif
683
684 void VM_Version::check_virtualizations() {
685 #if defined(LINUX)
686 const char* pname_file = "/sys/devices/virtual/dmi/id/product_name";
687 const char* tname_file = "/sys/hypervisor/type";
688 if (check_info_file(pname_file, "KVM", KVM, "VMWare", VMWare)) {
689 return;
690 }
691 check_info_file(tname_file, "Xen", XenPVHVM, nullptr, NoDetectedVirtualization);
692 #endif
693 }
694
695 void VM_Version::print_platform_virtualization_info(outputStream* st) {
696 #if defined(LINUX)
697 VirtualizationType vrt = VM_Version::get_detected_virtualization();
698 if (vrt == KVM) {
699 st->print_cr("KVM virtualization detected");
700 } else if (vrt == VMWare) {
701 st->print_cr("VMWare virtualization detected");
702 } else if (vrt == XenPVHVM) {
703 st->print_cr("Xen virtualization detected");
704 }
705 #endif
706 }
707
708 void VM_Version::initialize_cpu_information(void) {
709 // do nothing if cpu info has been initialized
710 if (_initialized) {
711 return;
712 }
713
714 _no_of_cores = os::processor_count();
715 _no_of_threads = _no_of_cores;
716 _no_of_sockets = _no_of_cores;
717 os::snprintf_checked(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "AArch64");
718
719 int desc_len = os::snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "AArch64 ");
720 get_compatible_board(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len);
721 desc_len = (int)strlen(_cpu_desc);
722 os::snprintf_checked(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len, " %s", _cpu_info_string);
723
724 _initialized = true;
725 }
726
727 void VM_Version::insert_features_names(uint64_t features, stringStream& ss) {
728 int i = 0;
729 ss.join([&]() {
730 const char* str = nullptr;
731 while ((i < MAX_CPU_FEATURES) && (str == nullptr)) {
732 if (supports_feature((VM_Version::Feature_Flag)i)) {
733 str = _features_names[i];
734 }
735 i += 1;
736 }
737 return str;
738 }, ", ");
739 }
740
741 void VM_Version::get_cpu_features_name(void* features_buffer, stringStream& ss) {
742 uint64_t features = *(uint64_t*)features_buffer;
743 insert_features_names(features, ss);
744 }
745
746 void VM_Version::get_missing_features_name(void* features_buffer, stringStream& ss) {
747 uint64_t features_to_test = *(uint64_t*)features_buffer;
748 int i = 0;
749 ss.join([&]() {
750 const char* str = nullptr;
751 while ((i < MAX_CPU_FEATURES) && (str == nullptr)) {
752 Feature_Flag flag = (Feature_Flag)i;
753 if (supports_feature(features_to_test, flag) && !supports_feature(flag)) {
754 str = _features_names[i];
755 }
756 i += 1;
757 }
758 return str;
759 }, ", ");
760 }
761
762 int VM_Version::cpu_features_size() {
763 return sizeof(_features);
764 }
765
766 void VM_Version::store_cpu_features(void* buf) {
767 *(uint64_t*)buf = _features;
768 }
769
770 bool VM_Version::supports_features(void* features_buffer) {
771 uint64_t features_to_test = *(uint64_t*)features_buffer;
772 return (_features & features_to_test) == features_to_test;
773 }