1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "pauth_aarch64.hpp"
27 #include "register_aarch64.hpp"
28 #include "runtime/arguments.hpp"
29 #include "runtime/globals_extension.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/os.inline.hpp"
32 #include "runtime/vm_version.hpp"
33 #include "utilities/formatBuffer.hpp"
34 #include "utilities/macros.hpp"
35 #include "utilities/ostream.hpp"
36
37 int VM_Version::_cpu;
38 int VM_Version::_model;
39 int VM_Version::_model2;
40 int VM_Version::_variant;
41 int VM_Version::_revision;
42 int VM_Version::_stepping;
43
44 int VM_Version::_zva_length;
45 int VM_Version::_dcache_line_size;
46 int VM_Version::_icache_line_size;
47 int VM_Version::_initial_sve_vector_length;
48 int VM_Version::_max_supported_sve_vector_length;
49 bool VM_Version::_rop_protection;
50 uintptr_t VM_Version::_pac_mask;
51
52 const char* VM_Version::_features_names[MAX_CPU_FEATURES] = { nullptr };
53
54 SpinWait VM_Version::_spin_wait;
55
56 static SpinWait get_spin_wait_desc() {
57 if (strcmp(OnSpinWaitInst, "nop") == 0) {
58 return SpinWait(SpinWait::NOP, OnSpinWaitInstCount);
59 } else if (strcmp(OnSpinWaitInst, "isb") == 0) {
60 return SpinWait(SpinWait::ISB, OnSpinWaitInstCount);
61 } else if (strcmp(OnSpinWaitInst, "yield") == 0) {
62 return SpinWait(SpinWait::YIELD, OnSpinWaitInstCount);
63 } else if (strcmp(OnSpinWaitInst, "none") != 0) {
64 vm_exit_during_initialization("The options for OnSpinWaitInst are nop, isb, yield, and none", OnSpinWaitInst);
65 }
66
67 if (!FLAG_IS_DEFAULT(OnSpinWaitInstCount) && OnSpinWaitInstCount > 0) {
68 vm_exit_during_initialization("OnSpinWaitInstCount cannot be used for OnSpinWaitInst 'none'");
69 }
70
71 return SpinWait{};
72 }
73
74 void VM_Version::initialize() {
75 #define SET_CPU_FEATURE_NAME(id, name, bit) \
76 _features_names[bit] = XSTR(name);
77 CPU_FEATURE_FLAGS(SET_CPU_FEATURE_NAME)
78 #undef SET_CPU_FEATURE_NAME
79
80 _supports_atomic_getset4 = true;
81 _supports_atomic_getadd4 = true;
82 _supports_atomic_getset8 = true;
83 _supports_atomic_getadd8 = true;
84
85 get_os_cpu_info();
86
87 int dcache_line = VM_Version::dcache_line_size();
88
89 // Limit AllocatePrefetchDistance so that it does not exceed the
90 // static constraint of 512 defined in runtime/globals.hpp.
91 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
92 FLAG_SET_DEFAULT(AllocatePrefetchDistance, MIN2(512, 3*dcache_line));
93
94 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
95 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
96 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
97 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
98 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
99 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
100 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
101 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
102
103 if (PrefetchCopyIntervalInBytes != -1 &&
104 ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
105 warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
106 PrefetchCopyIntervalInBytes &= ~7;
107 if (PrefetchCopyIntervalInBytes >= 32768)
108 PrefetchCopyIntervalInBytes = 32760;
109 }
110
111 if (AllocatePrefetchDistance != -1 && (AllocatePrefetchDistance & 7)) {
112 warning("AllocatePrefetchDistance must be multiple of 8");
113 AllocatePrefetchDistance &= ~7;
114 }
115
116 if (AllocatePrefetchStepSize & 7) {
117 warning("AllocatePrefetchStepSize must be multiple of 8");
118 AllocatePrefetchStepSize &= ~7;
119 }
120
121 if (SoftwarePrefetchHintDistance != -1 &&
122 (SoftwarePrefetchHintDistance & 7)) {
123 warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
124 SoftwarePrefetchHintDistance &= ~7;
125 }
126
127 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (dcache_line > ContendedPaddingWidth)) {
128 ContendedPaddingWidth = dcache_line;
129 }
130
131 if (os::supports_map_sync()) {
132 // if dcpop is available publish data cache line flush size via
133 // generic field, otherwise let if default to zero thereby
134 // disabling writeback
135 if (VM_Version::supports_dcpop()) {
136 _data_cache_line_flush_size = dcache_line;
137 }
138 }
139
140 // Enable vendor specific features
141
142 // Ampere eMAG
143 if (_cpu == CPU_AMCC && (_model == CPU_MODEL_EMAG) && (_variant == 0x3)) {
144 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
145 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
146 }
147 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
148 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
149 }
150 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
151 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, !(_revision == 1 || _revision == 2));
152 }
153 }
154
155 // Ampere CPUs
156 if (_cpu == CPU_AMPERE && ((_model == CPU_MODEL_AMPERE_1) ||
157 (_model == CPU_MODEL_AMPERE_1A) ||
158 (_model == CPU_MODEL_AMPERE_1B))) {
159 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
160 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
161 }
162 if (FLAG_IS_DEFAULT(OnSpinWaitInst)) {
163 FLAG_SET_DEFAULT(OnSpinWaitInst, "isb");
164 }
165 if (FLAG_IS_DEFAULT(OnSpinWaitInstCount)) {
166 FLAG_SET_DEFAULT(OnSpinWaitInstCount, 2);
167 }
168 if (FLAG_IS_DEFAULT(CodeEntryAlignment) &&
169 (_model == CPU_MODEL_AMPERE_1A || _model == CPU_MODEL_AMPERE_1B)) {
170 FLAG_SET_DEFAULT(CodeEntryAlignment, 32);
171 }
172 if (FLAG_IS_DEFAULT(AlwaysMergeDMB)) {
173 FLAG_SET_DEFAULT(AlwaysMergeDMB, false);
174 }
175 }
176
177 // ThunderX
178 if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
179 guarantee(_variant != 0, "Pre-release hardware no longer supported.");
180 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
181 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
182 }
183 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
184 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
185 }
186 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
187 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
188 }
189 }
190
191 // ThunderX2
192 if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
193 (_cpu == CPU_BROADCOM && (_model == 0x516))) {
194 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
195 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
196 }
197 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
198 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
199 }
200 }
201
202 // HiSilicon TSV110
203 if (_cpu == CPU_HISILICON && _model == 0xd01) {
204 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
205 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
206 }
207 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
208 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
209 }
210 }
211
212 // Cortex A53
213 if (_cpu == CPU_ARM && model_is(0xd03)) {
214 set_feature(CPU_A53MAC);
215 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
216 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
217 }
218 }
219
220 // Cortex A73
221 if (_cpu == CPU_ARM && model_is(0xd09)) {
222 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
223 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
224 }
225 // A73 is faster with short-and-easy-for-speculative-execution-loop
226 if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
227 FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
228 }
229 }
230
231 // Neoverse
232 // N1: 0xd0c
233 // N2: 0xd49
234 // V1: 0xd40
235 // V2: 0xd4f
236 if (_cpu == CPU_ARM && (model_is(0xd0c) || model_is(0xd49) ||
237 model_is(0xd40) || model_is(0xd4f))) {
238 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
239 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
240 }
241
242 if (FLAG_IS_DEFAULT(OnSpinWaitInst)) {
243 FLAG_SET_DEFAULT(OnSpinWaitInst, "isb");
244 }
245
246 if (FLAG_IS_DEFAULT(OnSpinWaitInstCount)) {
247 FLAG_SET_DEFAULT(OnSpinWaitInstCount, 1);
248 }
249 if (FLAG_IS_DEFAULT(AlwaysMergeDMB)) {
250 FLAG_SET_DEFAULT(AlwaysMergeDMB, false);
251 }
252 }
253
254 if (supports_feature(CPU_FP) || supports_feature(CPU_ASIMD)) {
255 if (FLAG_IS_DEFAULT(UseSignumIntrinsic)) {
256 FLAG_SET_DEFAULT(UseSignumIntrinsic, true);
257 }
258 }
259
260 if (FLAG_IS_DEFAULT(UseCRC32)) {
261 UseCRC32 = VM_Version::supports_crc32();
262 }
263
264 if (UseCRC32 && !VM_Version::supports_crc32()) {
265 warning("UseCRC32 specified, but not supported on this CPU");
266 FLAG_SET_DEFAULT(UseCRC32, false);
267 }
268
269 // Neoverse
270 // V1: 0xd40
271 // V2: 0xd4f
272 if (_cpu == CPU_ARM && (model_is(0xd40) || model_is(0xd4f))) {
273 if (FLAG_IS_DEFAULT(UseCryptoPmullForCRC32)) {
274 FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, true);
275 }
276 if (FLAG_IS_DEFAULT(CodeEntryAlignment)) {
277 FLAG_SET_DEFAULT(CodeEntryAlignment, 32);
278 }
279 }
280
281 if (UseCryptoPmullForCRC32 && (!VM_Version::supports_pmull() || !VM_Version::supports_sha3() || !VM_Version::supports_crc32())) {
282 warning("UseCryptoPmullForCRC32 specified, but not supported on this CPU");
283 FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, false);
284 }
285
286 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
287 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
288 }
289
290 if (UseVectorizedMismatchIntrinsic) {
291 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
292 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
293 }
294
295 if (VM_Version::supports_lse()) {
296 if (FLAG_IS_DEFAULT(UseLSE))
297 FLAG_SET_DEFAULT(UseLSE, true);
298 } else {
299 if (UseLSE) {
300 warning("UseLSE specified, but not supported on this CPU");
301 FLAG_SET_DEFAULT(UseLSE, false);
302 }
303 }
304
305 if (VM_Version::supports_aes()) {
306 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
307 UseAESIntrinsics =
308 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
309 if (UseAESIntrinsics && !UseAES) {
310 warning("UseAESIntrinsics enabled, but UseAES not, enabling");
311 UseAES = true;
312 }
313 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
314 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
315 }
316 } else {
317 if (UseAES) {
318 warning("AES instructions are not available on this CPU");
319 FLAG_SET_DEFAULT(UseAES, false);
320 }
321 if (UseAESIntrinsics) {
322 warning("AES intrinsics are not available on this CPU");
323 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
324 }
325 if (UseAESCTRIntrinsics) {
326 warning("AES/CTR intrinsics are not available on this CPU");
327 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
328 }
329 }
330
331
332 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
333 UseCRC32Intrinsics = true;
334 }
335
336 if (VM_Version::supports_crc32()) {
337 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
338 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
339 }
340 } else if (UseCRC32CIntrinsics) {
341 warning("CRC32C is not available on the CPU");
342 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
343 }
344
345 if (FLAG_IS_DEFAULT(UseFMA)) {
346 FLAG_SET_DEFAULT(UseFMA, true);
347 }
348
349 if (FLAG_IS_DEFAULT(UseMD5Intrinsics)) {
350 UseMD5Intrinsics = true;
351 }
352
353 if (VM_Version::supports_sha1() || VM_Version::supports_sha256() ||
354 VM_Version::supports_sha3() || VM_Version::supports_sha512()) {
355 if (FLAG_IS_DEFAULT(UseSHA)) {
356 FLAG_SET_DEFAULT(UseSHA, true);
357 }
358 } else if (UseSHA) {
359 warning("SHA instructions are not available on this CPU");
360 FLAG_SET_DEFAULT(UseSHA, false);
361 }
362
363 if (UseSHA && VM_Version::supports_sha1()) {
364 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
365 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
366 }
367 } else if (UseSHA1Intrinsics) {
368 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
369 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
370 }
371
372 if (UseSHA && VM_Version::supports_sha256()) {
373 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
374 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
375 }
376 } else if (UseSHA256Intrinsics) {
377 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
378 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
379 }
380
381 if (UseSHA && VM_Version::supports_sha3()) {
382 // Auto-enable UseSHA3Intrinsics on hardware with performance benefit.
383 // Note that the evaluation of UseSHA3Intrinsics shows better performance
384 // on Apple silicon but worse performance on Neoverse V1 and N2.
385 if (_cpu == CPU_APPLE) { // Apple silicon
386 if (FLAG_IS_DEFAULT(UseSHA3Intrinsics)) {
387 FLAG_SET_DEFAULT(UseSHA3Intrinsics, true);
388 }
389 }
390 } else if (UseSHA3Intrinsics) {
391 warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU.");
392 FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
393 }
394
395 if (UseSHA && VM_Version::supports_sha512()) {
396 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
397 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
398 }
399 } else if (UseSHA512Intrinsics) {
400 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
401 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
402 }
403
404 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA3Intrinsics || UseSHA512Intrinsics)) {
405 FLAG_SET_DEFAULT(UseSHA, false);
406 }
407
408 if (VM_Version::supports_pmull()) {
409 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
410 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
411 }
412 } else if (UseGHASHIntrinsics) {
413 warning("GHASH intrinsics are not available on this CPU");
414 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
415 }
416
417 if (supports_feature(CPU_ASIMD)) {
418 if (FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
419 UseChaCha20Intrinsics = true;
420 }
421 } else if (UseChaCha20Intrinsics) {
422 if (!FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
423 warning("ChaCha20 intrinsic requires ASIMD instructions");
424 }
425 FLAG_SET_DEFAULT(UseChaCha20Intrinsics, false);
426 }
427
428 if (supports_feature(CPU_ASIMD)) {
429 if (FLAG_IS_DEFAULT(UseKyberIntrinsics)) {
430 UseKyberIntrinsics = true;
431 }
432 } else if (UseKyberIntrinsics) {
433 if (!FLAG_IS_DEFAULT(UseKyberIntrinsics)) {
434 warning("Kyber intrinsics require ASIMD instructions");
435 }
436 FLAG_SET_DEFAULT(UseKyberIntrinsics, false);
437 }
438
439 if (supports_feature(CPU_ASIMD)) {
440 if (FLAG_IS_DEFAULT(UseDilithiumIntrinsics)) {
441 UseDilithiumIntrinsics = true;
442 }
443 } else if (UseDilithiumIntrinsics) {
444 if (!FLAG_IS_DEFAULT(UseDilithiumIntrinsics)) {
445 warning("Dilithium intrinsics require ASIMD instructions");
446 }
447 FLAG_SET_DEFAULT(UseDilithiumIntrinsics, false);
448 }
449
450 if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
451 UseBASE64Intrinsics = true;
452 }
453
454 if (is_zva_enabled()) {
455 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
456 FLAG_SET_DEFAULT(UseBlockZeroing, true);
457 }
458 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
459 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
460 }
461 } else if (UseBlockZeroing) {
462 warning("DC ZVA is not available on this CPU");
463 FLAG_SET_DEFAULT(UseBlockZeroing, false);
464 }
465
466 if (VM_Version::supports_sve2()) {
467 if (FLAG_IS_DEFAULT(UseSVE)) {
468 FLAG_SET_DEFAULT(UseSVE, 2);
469 }
470 } else if (VM_Version::supports_sve()) {
471 if (FLAG_IS_DEFAULT(UseSVE)) {
472 FLAG_SET_DEFAULT(UseSVE, 1);
473 } else if (UseSVE > 1) {
474 warning("SVE2 specified, but not supported on current CPU. Using SVE.");
475 FLAG_SET_DEFAULT(UseSVE, 1);
476 }
477 } else if (UseSVE > 0) {
478 warning("UseSVE specified, but not supported on current CPU. Disabling SVE.");
479 FLAG_SET_DEFAULT(UseSVE, 0);
480 }
481
482 if (UseSVE > 0) {
483 int vl = get_current_sve_vector_length();
484 if (vl < 0) {
485 warning("Unable to get SVE vector length on this system. "
486 "Disabling SVE. Specify -XX:UseSVE=0 to shun this warning.");
487 FLAG_SET_DEFAULT(UseSVE, 0);
488 } else if ((vl == 0) || ((vl % FloatRegister::sve_vl_min) != 0) || !is_power_of_2(vl)) {
489 warning("Detected SVE vector length (%d) should be a power of two and a multiple of %d. "
490 "Disabling SVE. Specify -XX:UseSVE=0 to shun this warning.",
491 vl, FloatRegister::sve_vl_min);
492 FLAG_SET_DEFAULT(UseSVE, 0);
493 } else {
494 _initial_sve_vector_length = vl;
495 }
496 }
497
498 // This machine allows unaligned memory accesses
499 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
500 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
501 }
502
503 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
504 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
505 }
506
507 if (!UsePopCountInstruction) {
508 warning("UsePopCountInstruction is always enabled on this CPU");
509 UsePopCountInstruction = true;
510 }
511
512 if (UseBranchProtection == nullptr || strcmp(UseBranchProtection, "none") == 0) {
513 _rop_protection = false;
514 } else if (strcmp(UseBranchProtection, "standard") == 0 ||
515 strcmp(UseBranchProtection, "pac-ret") == 0) {
516 _rop_protection = false;
517 // Enable ROP-protection if
518 // 1) this code has been built with branch-protection and
519 // 2) the CPU/OS supports it
520 #ifdef __ARM_FEATURE_PAC_DEFAULT
521 if (!VM_Version::supports_paca()) {
522 // Disable PAC to prevent illegal instruction crashes.
523 warning("ROP-protection specified, but not supported on this CPU. Disabling ROP-protection.");
524 } else {
525 _rop_protection = true;
526 }
527 #else
528 warning("ROP-protection specified, but this VM was built without ROP-protection support. Disabling ROP-protection.");
529 #endif
530 } else {
531 vm_exit_during_initialization(err_msg("Unsupported UseBranchProtection: %s", UseBranchProtection));
532 }
533
534 if (_rop_protection == true) {
535 // Determine the mask of address bits used for PAC. Clear bit 55 of
536 // the input to make it look like a user address.
537 _pac_mask = (uintptr_t)pauth_strip_pointer((address)~(UINT64_C(1) << 55));
538 }
539
540 #ifdef COMPILER2
541 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
542 UseMultiplyToLenIntrinsic = true;
543 }
544
545 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
546 UseSquareToLenIntrinsic = true;
547 }
548
549 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
550 UseMulAddIntrinsic = true;
551 }
552
553 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
554 UseMontgomeryMultiplyIntrinsic = true;
555 }
556 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
557 UseMontgomerySquareIntrinsic = true;
558 }
559
560 if (UseSVE > 0) {
561 if (FLAG_IS_DEFAULT(MaxVectorSize)) {
562 MaxVectorSize = _initial_sve_vector_length;
563 } else if (MaxVectorSize < FloatRegister::sve_vl_min) {
564 warning("SVE does not support vector length less than %d bytes. Disabling SVE.",
565 FloatRegister::sve_vl_min);
566 UseSVE = 0;
567 } else if (!((MaxVectorSize % FloatRegister::sve_vl_min) == 0 && is_power_of_2(MaxVectorSize))) {
568 vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize));
569 }
570
571 if (UseSVE > 0) {
572 // Acquire the largest supported vector length of this machine
573 _max_supported_sve_vector_length = set_and_get_current_sve_vector_length(FloatRegister::sve_vl_max);
574
575 if (MaxVectorSize != _max_supported_sve_vector_length) {
576 int new_vl = set_and_get_current_sve_vector_length(MaxVectorSize);
577 if (new_vl < 0) {
578 vm_exit_during_initialization(
579 err_msg("Current system does not support SVE vector length for MaxVectorSize: %d",
580 (int)MaxVectorSize));
581 } else if (new_vl != MaxVectorSize) {
582 warning("Current system only supports max SVE vector length %d. Set MaxVectorSize to %d",
583 new_vl, new_vl);
584 }
585 MaxVectorSize = new_vl;
586 }
587 _initial_sve_vector_length = MaxVectorSize;
588 }
589 }
590
591 if (UseSVE == 0) { // NEON
592 int min_vector_size = 8;
593 int max_vector_size = FloatRegister::neon_vl;
594 if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
595 if (!is_power_of_2(MaxVectorSize)) {
596 vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize));
597 } else if (MaxVectorSize < min_vector_size) {
598 warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
599 FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
600 } else if (MaxVectorSize > max_vector_size) {
601 warning("MaxVectorSize must be at most %i on this platform", max_vector_size);
602 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
603 }
604 } else {
605 FLAG_SET_DEFAULT(MaxVectorSize, FloatRegister::neon_vl);
606 }
607 }
608
609 int inline_size = (UseSVE > 0 && MaxVectorSize >= FloatRegister::sve_vl_min) ? MaxVectorSize : 0;
610 if (FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize)) {
611 FLAG_SET_DEFAULT(ArrayOperationPartialInlineSize, inline_size);
612 } else if (ArrayOperationPartialInlineSize != 0 && ArrayOperationPartialInlineSize != inline_size) {
613 warning("Setting ArrayOperationPartialInlineSize to %d", inline_size);
614 ArrayOperationPartialInlineSize = inline_size;
615 }
616
617 if (FLAG_IS_DEFAULT(OptoScheduling)) {
618 OptoScheduling = true;
619 }
620
621 if (FLAG_IS_DEFAULT(AlignVector)) {
622 AlignVector = AvoidUnalignedAccesses;
623 }
624
625 if (FLAG_IS_DEFAULT(UsePoly1305Intrinsics)) {
626 FLAG_SET_DEFAULT(UsePoly1305Intrinsics, true);
627 }
628
629 if (FLAG_IS_DEFAULT(UseVectorizedHashCodeIntrinsic)) {
630 FLAG_SET_DEFAULT(UseVectorizedHashCodeIntrinsic, true);
631 }
632 #endif
633
634 _spin_wait = get_spin_wait_desc();
635
636 check_virtualizations();
637
638 // Sync SVE related CPU features with flags
639 if (UseSVE < 2) {
640 clear_feature(CPU_SVE2);
641 clear_feature(CPU_SVEBITPERM);
642 }
643 if (UseSVE < 1) {
644 clear_feature(CPU_SVE);
645 }
646
647 // Construct the "features" string
648 stringStream ss(512);
649 ss.print("0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
650 if (_model2) {
651 ss.print("(0x%03x)", _model2);
652 }
653 ss.print(", ");
654 int features_offset = (int)ss.size();
655 insert_features_names(_features, ss);
656
657 _cpu_info_string = ss.as_string(true);
658 _features_string = _cpu_info_string + features_offset;
659 }
660
661 #if defined(LINUX)
662 static bool check_info_file(const char* fpath,
663 const char* virt1, VirtualizationType vt1,
664 const char* virt2, VirtualizationType vt2) {
665 char line[500];
666 FILE* fp = os::fopen(fpath, "r");
667 if (fp == nullptr) {
668 return false;
669 }
670 while (fgets(line, sizeof(line), fp) != nullptr) {
671 if (strcasestr(line, virt1) != nullptr) {
672 Abstract_VM_Version::_detected_virtualization = vt1;
673 fclose(fp);
674 return true;
675 }
676 if (virt2 != nullptr && strcasestr(line, virt2) != nullptr) {
677 Abstract_VM_Version::_detected_virtualization = vt2;
678 fclose(fp);
679 return true;
680 }
681 }
682 fclose(fp);
683 return false;
684 }
685 #endif
686
687 void VM_Version::check_virtualizations() {
688 #if defined(LINUX)
689 const char* pname_file = "/sys/devices/virtual/dmi/id/product_name";
690 const char* tname_file = "/sys/hypervisor/type";
691 if (check_info_file(pname_file, "KVM", KVM, "VMWare", VMWare)) {
692 return;
693 }
694 check_info_file(tname_file, "Xen", XenPVHVM, nullptr, NoDetectedVirtualization);
695 #endif
696 }
697
698 void VM_Version::print_platform_virtualization_info(outputStream* st) {
699 #if defined(LINUX)
700 VirtualizationType vrt = VM_Version::get_detected_virtualization();
701 if (vrt == KVM) {
702 st->print_cr("KVM virtualization detected");
703 } else if (vrt == VMWare) {
704 st->print_cr("VMWare virtualization detected");
705 } else if (vrt == XenPVHVM) {
706 st->print_cr("Xen virtualization detected");
707 }
708 #endif
709 }
710
711 void VM_Version::initialize_cpu_information(void) {
712 // do nothing if cpu info has been initialized
713 if (_initialized) {
714 return;
715 }
716
717 _no_of_cores = os::processor_count();
718 _no_of_threads = _no_of_cores;
719 _no_of_sockets = _no_of_cores;
720 snprintf(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "AArch64");
721
722 int desc_len = snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "AArch64 ");
723 get_compatible_board(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len);
724 desc_len = (int)strlen(_cpu_desc);
725 snprintf(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len, " %s", _cpu_info_string);
726
727 _initialized = true;
728 }
729
730 void VM_Version::insert_features_names(uint64_t features, stringStream& ss) {
731 int i = 0;
732 ss.join([&]() {
733 const char* str = nullptr;
734 while ((i < MAX_CPU_FEATURES) && (str == nullptr)) {
735 if (supports_feature((VM_Version::Feature_Flag)i)) {
736 str = _features_names[i];
737 }
738 i += 1;
739 }
740 return str;
741 }, ", ");
742 }
743
744 void VM_Version::get_cpu_features_name(void* features_buffer, stringStream& ss) {
745 uint64_t features = *(uint64_t*)features_buffer;
746 insert_features_names(features, ss);
747 }
748
749 void VM_Version::get_missing_features_name(void* features_buffer, stringStream& ss) {
750 uint64_t features_to_test = *(uint64_t*)features_buffer;
751 int i = 0;
752 ss.join([&]() {
753 const char* str = nullptr;
754 while ((i < MAX_CPU_FEATURES) && (str == nullptr)) {
755 Feature_Flag flag = (Feature_Flag)i;
756 if (supports_feature(features_to_test, flag) && !supports_feature(flag)) {
757 str = _features_names[i];
758 }
759 i += 1;
760 }
761 return str;
762 }, ", ");
763 }
764
765 int VM_Version::cpu_features_size() {
766 return sizeof(_features);
767 }
768
769 void VM_Version::store_cpu_features(void* buf) {
770 *(uint64_t*)buf = _features;
771 }
772
773 bool VM_Version::supports_features(void* features_buffer) {
774 uint64_t features_to_test = *(uint64_t*)features_buffer;
775 return (_features & features_to_test) == features_to_test;
776 }