1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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24 */
25
26 #ifndef CPU_AARCH64_VM_VERSION_AARCH64_HPP
27 #define CPU_AARCH64_VM_VERSION_AARCH64_HPP
28
29 #include "spin_wait_aarch64.hpp"
30 #include "runtime/abstract_vm_version.hpp"
31 #include "utilities/sizes.hpp"
32
33 #include <initializer_list>
34
35 class stringStream;
36
37 #define BIT_MASK(flag) (1ULL<<(flag))
38
39 class VM_Version : public Abstract_VM_Version {
40 friend class VMStructs;
41 friend class JVMCIVMStructs;
42
43 protected:
44 static int _cpu;
45 static int _model;
46 static int _model2;
47 static int _variant;
48 static int _revision;
49 static int _stepping;
50
51 static int _zva_length;
52 static int _dcache_line_size;
53 static int _icache_line_size;
54 static int _initial_sve_vector_length;
55 static int _max_supported_sve_vector_length;
56 static bool _rop_protection;
57 static uintptr_t _pac_mask;
58
59 static SpinWait _spin_wait;
60
61 // Read additional info using OS-specific interfaces
62 static void get_os_cpu_info();
63
64 // Sets the SVE length and returns a new actual value or negative on error.
65 // If the len is larger than the system largest supported SVE vector length,
66 // the function sets the largest supported value.
67 static int set_and_get_current_sve_vector_length(int len);
68 static int get_current_sve_vector_length();
69
70 public:
71 // Initialization
72 static void initialize();
73 static void check_virtualizations();
74
75 static void insert_features_names(uint64_t features, stringStream& ss);
76
77 static void print_platform_virtualization_info(outputStream*);
78
79 // Asserts
80 static void assert_is_initialized() {
81 }
82
83 static bool expensive_load(int ld_size, int scale) {
84 if (cpu_family() == CPU_ARM) {
85 // Half-word load with index shift by 1 (aka scale is 2) has
86 // extra cycle latency, e.g. ldrsh w0, [x1,w2,sxtw #1].
87 if (ld_size == 2 && scale == 2) {
88 return true;
89 }
90 }
91 return false;
92 }
93
94 // The CPU implementer codes can be found in
95 // ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile
96 // https://developer.arm.com/docs/ddi0487/latest
97 // Arm can assign codes that are not published in the manual.
98 // Apple's code is defined in
99 // https://github.com/apple/darwin-xnu/blob/33eb983/osfmk/arm/cpuid.h#L62
100 enum Family {
101 CPU_AMPERE = 0xC0,
102 CPU_ARM = 'A',
103 CPU_BROADCOM = 'B',
104 CPU_CAVIUM = 'C',
105 CPU_DEC = 'D',
106 CPU_HISILICON = 'H',
107 CPU_INFINEON = 'I',
108 CPU_MOTOROLA = 'M',
109 CPU_NVIDIA = 'N',
110 CPU_AMCC = 'P',
111 CPU_QUALCOMM = 'Q',
112 CPU_MARVELL = 'V',
113 CPU_INTEL = 'i',
114 CPU_APPLE = 'a',
115 };
116
117 enum Ampere_CPU_Model {
118 CPU_MODEL_EMAG = 0x0, /* CPU implementer is CPU_AMCC */
119 CPU_MODEL_ALTRA = 0xd0c, /* CPU implementer is CPU_ARM, Neoverse N1 */
120 CPU_MODEL_ALTRAMAX = 0xd0c, /* CPU implementer is CPU_ARM, Neoverse N1 */
121 CPU_MODEL_AMPERE_1 = 0xac3, /* CPU implementer is CPU_AMPERE */
122 CPU_MODEL_AMPERE_1A = 0xac4, /* CPU implementer is CPU_AMPERE */
123 CPU_MODEL_AMPERE_1B = 0xac5 /* AMPERE_1B core Implements ARMv8.7 with CSSC, MTE, SM3/SM4 extensions */
124 };
125
126 enum ARM_CPU_Model {
127 CPU_MODEL_ARM_CORTEX_A53 = 0xd03,
128 CPU_MODEL_ARM_CORTEX_A73 = 0xd09,
129 CPU_MODEL_ARM_NEOVERSE_N1 = 0xd0c,
130 CPU_MODEL_ARM_NEOVERSE_V1 = 0xd40,
131 CPU_MODEL_ARM_NEOVERSE_N2 = 0xd49,
132 CPU_MODEL_ARM_NEOVERSE_V2 = 0xd4f,
133 CPU_MODEL_ARM_NEOVERSE_V3AE = 0xd83,
134 CPU_MODEL_ARM_NEOVERSE_V3 = 0xd84,
135 CPU_MODEL_ARM_NEOVERSE_N3 = 0xd8e,
136 };
137
138 #define CPU_FEATURE_FLAGS(decl) \
139 decl(FP, fp, 0) \
140 decl(ASIMD, asimd, 1) \
141 decl(EVTSTRM, evtstrm, 2) \
142 decl(AES, aes, 3) \
143 decl(PMULL, pmull, 4) \
144 decl(SHA1, sha1, 5) \
145 decl(SHA2, sha256, 6) \
146 decl(CRC32, crc32, 7) \
147 decl(LSE, lse, 8) \
148 decl(FPHP, fphp, 9) \
149 decl(ASIMDHP, asimdhp, 10) \
150 decl(DCPOP, dcpop, 16) \
151 decl(SHA3, sha3, 17) \
152 decl(SHA512, sha512, 21) \
153 decl(SVE, sve, 22) \
154 decl(SB, sb, 29) \
155 decl(PACA, paca, 30) \
156 /* flags above must follow Linux HWCAP */ \
157 decl(SVEBITPERM, svebitperm, 27) \
158 decl(SVE2, sve2, 28) \
159 decl(A53MAC, a53mac, 31)
160
161 enum Feature_Flag {
162 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = bit,
163 CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
164 #undef DECLARE_CPU_FEATURE_FLAG
165 MAX_CPU_FEATURES
166 };
167
168 STATIC_ASSERT(sizeof(_features) * BitsPerByte >= MAX_CPU_FEATURES);
169
170 static const char* _features_names[MAX_CPU_FEATURES];
171
172 // Feature identification
173 #define CPU_FEATURE_DETECTION(id, name, bit) \
174 static bool supports_##name() { return supports_feature(CPU_##id); }
175 CPU_FEATURE_FLAGS(CPU_FEATURE_DETECTION)
176 #undef CPU_FEATURE_DETECTION
177
178 static void set_feature(Feature_Flag flag) {
179 _features |= BIT_MASK(flag);
180 }
181 static void clear_feature(Feature_Flag flag) {
182 _features &= (~BIT_MASK(flag));
183 }
184 static bool supports_feature(Feature_Flag flag) {
185 return (_features & BIT_MASK(flag)) != 0;
186 }
187 static bool supports_feature(uint64_t features, Feature_Flag flag) {
188 return (features & BIT_MASK(flag)) != 0;
189 }
190
191 static int cpu_family() { return _cpu; }
192 static int cpu_model() { return _model; }
193 static int cpu_model2() { return _model2; }
194 static int cpu_variant() { return _variant; }
195 static int cpu_revision() { return _revision; }
196
197 static bool model_is(int cpu_model) {
198 return _model == cpu_model || _model2 == cpu_model;
199 }
200
201 static bool model_is_in(std::initializer_list<int> cpu_models) {
202 for (const int& cpu_model : cpu_models) {
203 if (_model == cpu_model || _model2 == cpu_model) {
204 return true;
205 }
206 }
207 return false;
208 }
209
210 static bool is_zva_enabled() { return 0 < _zva_length; }
211 static int zva_length() {
212 assert(is_zva_enabled(), "ZVA not available");
213 return _zva_length;
214 }
215
216 static int icache_line_size() { return _icache_line_size; }
217 static int dcache_line_size() { return _dcache_line_size; }
218 static int get_initial_sve_vector_length() { return _initial_sve_vector_length; };
219 static int get_max_supported_sve_vector_length() { return _max_supported_sve_vector_length; };
220
221 // Aarch64 supports fast class initialization checks
222 static bool supports_fast_class_init_checks() { return true; }
223 constexpr static bool supports_stack_watermark_barrier() { return true; }
224 constexpr static bool supports_recursive_fast_locking() { return true; }
225
226 constexpr static bool supports_secondary_supers_table() { return true; }
227
228 static void get_compatible_board(char *buf, int buflen);
229
230 static const SpinWait& spin_wait_desc() { return _spin_wait; }
231
232 static bool supports_on_spin_wait() { return _spin_wait.inst() != SpinWait::NONE; }
233
234 static bool supports_float16() { return true; }
235
236 #ifdef __APPLE__
237 // Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64)
238 static bool is_cpu_emulated();
239 #endif
240
241 static void initialize_cpu_information(void);
242
243 static bool use_rop_protection() { return _rop_protection; }
244
245 // For common 64/128-bit unpredicated vector operations, we may prefer
246 // emitting NEON instructions rather than the corresponding SVE instructions.
247 static bool use_neon_for_vector(int vector_length_in_bytes) {
248 return vector_length_in_bytes <= 16;
249 }
250
251 static void get_cpu_features_name(void* features_buffer, stringStream& ss);
252
253 // Returns names of features present in features_set1 but not in features_set2
254 static void get_missing_features_name(void* features_set1, void* features_set2, stringStream& ss);
255
256 // Returns number of bytes required to store cpu features representation
257 static int cpu_features_size();
258
259 // Stores cpu features representation in the provided buffer. This representation is arch dependent.
260 // Size of the buffer must be same as returned by cpu_features_size()
261 static void store_cpu_features(void* buf);
262
263 static bool supports_features(void* features_to_test);
264 };
265
266 #endif // CPU_AARCH64_VM_VERSION_AARCH64_HPP