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generate_and_dispatch(t);
}
//-----------------------------------------------------------------------------
+ // Make feasible for old CPUs.
+ void TemplateInterpreterGenerator::count_bytecode() {
+ __ load_absolute_address(Z_R1_scratch, (address) &BytecodeCounter::_counter_value);
+ __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
+ }
+
+ void TemplateInterpreterGenerator::histogram_bytecode(Template * t) {
+ __ load_absolute_address(Z_R1_scratch, (address)&BytecodeHistogram::_counters[ t->bytecode() ]);
+ __ add2mem_32(Address(Z_R1_scratch), 1, Z_tmp_1);
+ }
+
#ifndef PRODUCT
address TemplateInterpreterGenerator::generate_trace_code(TosState state) {
address entry = __ pc();
NearLabel counter_below_trace_threshold;
__ z_br(Z_R14); // return
return entry;
}
- // Make feasible for old CPUs.
- void TemplateInterpreterGenerator::count_bytecode() {
- __ load_absolute_address(Z_R1_scratch, (address) &BytecodeCounter::_counter_value);
- __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
- }
-
- void TemplateInterpreterGenerator::histogram_bytecode(Template * t) {
- __ load_absolute_address(Z_R1_scratch, (address)&BytecodeHistogram::_counters[ t->bytecode() ]);
- __ add2mem_32(Address(Z_R1_scratch), 1, Z_tmp_1);
- }
-
void TemplateInterpreterGenerator::histogram_bytecode_pair(Template * t) {
Address index_addr(Z_tmp_1, (intptr_t) 0);
Register index = Z_tmp_2;
// Load previous index.
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