1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/macroAssembler.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "c1/c1_CodeStubs.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "compiler/oopMap.hpp"
36 #include "gc/shared/collectedHeap.hpp"
37 #include "gc/shared/gc_globals.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/frame.inline.hpp"
41 #include "runtime/safepointMechanism.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "runtime/stubRoutines.hpp"
44 #include "utilities/powerOfTwo.hpp"
45 #include "vmreg_x86.inline.hpp"
46
47
48 // These masks are used to provide 128-bit aligned bitmasks to the XMM
49 // instructions, to allow sign-masking or sign-bit flipping. They allow
50 // fast versions of NegF/NegD and AbsF/AbsD.
51
52 // Note: 'double' and 'long long' have 32-bits alignment on x86.
53 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
54 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
55 // of 128-bits operands for SSE instructions.
56 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
57 // Store the value to a 128-bits operand.
58 operand[0] = lo;
59 operand[1] = hi;
60 return operand;
61 }
62
63 // Buffer for 128-bits masks used by SSE instructions.
64 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
65
66 // Static initialization during VM startup.
67 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
68 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
69 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
70 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
71
72
73 NEEDS_CLEANUP // remove this definitions ?
74 const Register SYNC_header = rax; // synchronization header
75 const Register SHIFT_count = rcx; // where count for shift operations must be
76
77 #define __ _masm->
78
79
80 static void select_different_registers(Register preserve,
81 Register extra,
82 Register &tmp1,
83 Register &tmp2) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, extra);
89 tmp2 = extra;
90 }
91 assert_different_registers(preserve, tmp1, tmp2);
92 }
93
94
95
96 static void select_different_registers(Register preserve,
97 Register extra,
98 Register &tmp1,
99 Register &tmp2,
100 Register &tmp3) {
101 if (tmp1 == preserve) {
102 assert_different_registers(tmp1, tmp2, tmp3, extra);
103 tmp1 = extra;
104 } else if (tmp2 == preserve) {
105 assert_different_registers(tmp1, tmp2, tmp3, extra);
106 tmp2 = extra;
107 } else if (tmp3 == preserve) {
108 assert_different_registers(tmp1, tmp2, tmp3, extra);
109 tmp3 = extra;
110 }
111 assert_different_registers(preserve, tmp1, tmp2, tmp3);
112 }
113
114
115
116 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
117 if (opr->is_constant()) {
118 LIR_Const* constant = opr->as_constant_ptr();
119 switch (constant->type()) {
120 case T_INT: {
121 return true;
122 }
123
124 default:
125 return false;
126 }
127 }
128 return false;
129 }
130
131
132 LIR_Opr LIR_Assembler::receiverOpr() {
133 return FrameMap::receiver_opr;
134 }
135
136 LIR_Opr LIR_Assembler::osrBufferPointer() {
137 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
138 }
139
140 //--------------fpu register translations-----------------------
141
142
143 address LIR_Assembler::float_constant(float f) {
144 address const_addr = __ float_constant(f);
145 if (const_addr == nullptr) {
146 bailout("const section overflow");
147 return __ code()->consts()->start();
148 } else {
149 return const_addr;
150 }
151 }
152
153
154 address LIR_Assembler::double_constant(double d) {
155 address const_addr = __ double_constant(d);
156 if (const_addr == nullptr) {
157 bailout("const section overflow");
158 return __ code()->consts()->start();
159 } else {
160 return const_addr;
161 }
162 }
163
164 #ifndef _LP64
165 void LIR_Assembler::fpop() {
166 __ fpop();
167 }
168
169 void LIR_Assembler::fxch(int i) {
170 __ fxch(i);
171 }
172
173 void LIR_Assembler::fld(int i) {
174 __ fld_s(i);
175 }
176
177 void LIR_Assembler::ffree(int i) {
178 __ ffree(i);
179 }
180 #endif // !_LP64
181
182 void LIR_Assembler::breakpoint() {
183 __ int3();
184 }
185
186 void LIR_Assembler::push(LIR_Opr opr) {
187 if (opr->is_single_cpu()) {
188 __ push_reg(opr->as_register());
189 } else if (opr->is_double_cpu()) {
190 NOT_LP64(__ push_reg(opr->as_register_hi()));
191 __ push_reg(opr->as_register_lo());
192 } else if (opr->is_stack()) {
193 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
194 } else if (opr->is_constant()) {
195 LIR_Const* const_opr = opr->as_constant_ptr();
196 if (const_opr->type() == T_OBJECT) {
197 __ push_oop(const_opr->as_jobject(), rscratch1);
198 } else if (const_opr->type() == T_INT) {
199 __ push_jint(const_opr->as_jint());
200 } else {
201 ShouldNotReachHere();
202 }
203
204 } else {
205 ShouldNotReachHere();
206 }
207 }
208
209 void LIR_Assembler::pop(LIR_Opr opr) {
210 if (opr->is_single_cpu()) {
211 __ pop_reg(opr->as_register());
212 } else {
213 ShouldNotReachHere();
214 }
215 }
216
217 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
218 return addr->base()->is_illegal() && addr->index()->is_illegal();
219 }
220
221 //-------------------------------------------
222
223 Address LIR_Assembler::as_Address(LIR_Address* addr) {
224 return as_Address(addr, rscratch1);
225 }
226
227 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
228 if (addr->base()->is_illegal()) {
229 assert(addr->index()->is_illegal(), "must be illegal too");
230 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
231 if (! __ reachable(laddr)) {
232 __ movptr(tmp, laddr.addr());
233 Address res(tmp, 0);
234 return res;
235 } else {
236 return __ as_Address(laddr);
237 }
238 }
239
240 Register base = addr->base()->as_pointer_register();
241
242 if (addr->index()->is_illegal()) {
243 return Address( base, addr->disp());
244 } else if (addr->index()->is_cpu_register()) {
245 Register index = addr->index()->as_pointer_register();
246 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
247 } else if (addr->index()->is_constant()) {
248 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
249 assert(Assembler::is_simm32(addr_offset), "must be");
250
251 return Address(base, addr_offset);
252 } else {
253 Unimplemented();
254 return Address();
255 }
256 }
257
258
259 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
260 Address base = as_Address(addr);
261 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
262 }
263
264
265 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
266 return as_Address(addr);
267 }
268
269
270 void LIR_Assembler::osr_entry() {
271 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
272 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
273 ValueStack* entry_state = osr_entry->state();
274 int number_of_locks = entry_state->locks_size();
275
276 // we jump here if osr happens with the interpreter
277 // state set up to continue at the beginning of the
278 // loop that triggered osr - in particular, we have
279 // the following registers setup:
280 //
281 // rcx: osr buffer
282 //
283
284 // build frame
285 ciMethod* m = compilation()->method();
286 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
287
288 // OSR buffer is
289 //
290 // locals[nlocals-1..0]
291 // monitors[0..number_of_locks]
292 //
293 // locals is a direct copy of the interpreter frame so in the osr buffer
294 // so first slot in the local array is the last local from the interpreter
295 // and last slot is local[0] (receiver) from the interpreter
296 //
297 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
298 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
299 // in the interpreter frame (the method lock if a sync method)
300
301 // Initialize monitors in the compiled activation.
302 // rcx: pointer to osr buffer
303 //
304 // All other registers are dead at this point and the locals will be
305 // copied into place by code emitted in the IR.
306
307 Register OSR_buf = osrBufferPointer()->as_pointer_register();
308 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
309 int monitor_offset = BytesPerWord * method()->max_locals() +
310 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
311 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
312 // the OSR buffer using 2 word entries: first the lock and then
313 // the oop.
314 for (int i = 0; i < number_of_locks; i++) {
315 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
316 #ifdef ASSERT
317 // verify the interpreter's monitor has a non-null object
318 {
319 Label L;
320 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD);
321 __ jcc(Assembler::notZero, L);
322 __ stop("locked object is null");
323 __ bind(L);
324 }
325 #endif
326 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
327 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
328 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
329 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
330 }
331 }
332 }
333
334
335 // inline cache check; done before the frame is built.
336 int LIR_Assembler::check_icache() {
337 return __ ic_check(CodeEntryAlignment);
338 }
339
340 void LIR_Assembler::clinit_barrier(ciMethod* method) {
341 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
342 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
343
344 Label L_skip_barrier;
345 Register klass = rscratch1;
346 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
347 assert(thread != noreg, "x86_32 not implemented");
348
349 __ mov_metadata(klass, method->holder()->constant_encoding());
350 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
351
352 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
353
354 __ bind(L_skip_barrier);
355 }
356
357 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
358 jobject o = nullptr;
359 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
360 __ movoop(reg, o);
361 patching_epilog(patch, lir_patch_normal, reg, info);
362 }
363
364 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
365 Metadata* o = nullptr;
366 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
367 __ mov_metadata(reg, o);
368 patching_epilog(patch, lir_patch_normal, reg, info);
369 }
370
371 // This specifies the rsp decrement needed to build the frame
372 int LIR_Assembler::initial_frame_size_in_bytes() const {
373 // if rounding, must let FrameMap know!
374
375 // The frame_map records size in slots (32bit word)
376
377 // subtract two words to account for return address and link
378 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
379 }
380
381
382 int LIR_Assembler::emit_exception_handler() {
383 // generate code for exception handler
384 address handler_base = __ start_a_stub(exception_handler_size());
385 if (handler_base == nullptr) {
386 // not enough space left for the handler
387 bailout("exception handler overflow");
388 return -1;
389 }
390
391 int offset = code_offset();
392
393 // the exception oop and pc are in rax, and rdx
394 // no other registers need to be preserved, so invalidate them
395 __ invalidate_registers(false, true, true, false, true, true);
396
397 // check that there is really an exception
398 __ verify_not_null_oop(rax);
399
400 // search an exception handler (rax: exception oop, rdx: throwing pc)
401 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
402 __ should_not_reach_here();
403 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
404 __ end_a_stub();
405
406 return offset;
407 }
408
409
410 // Emit the code to remove the frame from the stack in the exception
411 // unwind path.
412 int LIR_Assembler::emit_unwind_handler() {
413 #ifndef PRODUCT
414 if (CommentedAssembly) {
415 _masm->block_comment("Unwind handler");
416 }
417 #endif
418
419 int offset = code_offset();
420
421 // Fetch the exception from TLS and clear out exception related thread state
422 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
423 NOT_LP64(__ get_thread(thread));
424 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
425 __ movptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
426 __ movptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
427
428 __ bind(_unwind_handler_entry);
429 __ verify_not_null_oop(rax);
430 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
431 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
432 }
433
434 // Perform needed unlocking
435 MonitorExitStub* stub = nullptr;
436 if (method()->is_synchronized()) {
437 monitor_address(0, FrameMap::rax_opr);
438 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
439 if (LockingMode == LM_MONITOR) {
440 __ jmp(*stub->entry());
441 } else {
442 __ unlock_object(rdi, rsi, rax, *stub->entry());
443 }
444 __ bind(*stub->continuation());
445 }
446
447 if (compilation()->env()->dtrace_method_probes()) {
448 #ifdef _LP64
449 __ mov(rdi, r15_thread);
450 __ mov_metadata(rsi, method()->constant_encoding());
451 #else
452 __ get_thread(rax);
453 __ movptr(Address(rsp, 0), rax);
454 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding(), noreg);
455 #endif
456 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
457 }
458
459 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
460 __ mov(rax, rbx); // Restore the exception
461 }
462
463 // remove the activation and dispatch to the unwind handler
464 __ remove_frame(initial_frame_size_in_bytes());
465 __ jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
466
467 // Emit the slow path assembly
468 if (stub != nullptr) {
469 stub->emit_code(this);
470 }
471
472 return offset;
473 }
474
475
476 int LIR_Assembler::emit_deopt_handler() {
477 // generate code for exception handler
478 address handler_base = __ start_a_stub(deopt_handler_size());
479 if (handler_base == nullptr) {
480 // not enough space left for the handler
481 bailout("deopt handler overflow");
482 return -1;
483 }
484
485 int offset = code_offset();
486 InternalAddress here(__ pc());
487
488 __ pushptr(here.addr(), rscratch1);
489 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
490 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
491 __ end_a_stub();
492
493 return offset;
494 }
495
496 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
497 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
498 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
499 assert(result->fpu() == 0, "result must already be on TOS");
500 }
501
502 // Pop the stack before the safepoint code
503 __ remove_frame(initial_frame_size_in_bytes());
504
505 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
506 __ reserved_stack_check();
507 }
508
509 // Note: we do not need to round double result; float result has the right precision
510 // the poll sets the condition code, but no data registers
511
512 #ifdef _LP64
513 const Register thread = r15_thread;
514 #else
515 const Register thread = rbx;
516 __ get_thread(thread);
517 #endif
518 code_stub->set_safepoint_offset(__ offset());
519 __ relocate(relocInfo::poll_return_type);
520 __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */);
521 __ ret(0);
522 }
523
524
525 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
526 guarantee(info != nullptr, "Shouldn't be null");
527 int offset = __ offset();
528 #ifdef _LP64
529 const Register poll_addr = rscratch1;
530 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
531 #else
532 assert(tmp->is_cpu_register(), "needed");
533 const Register poll_addr = tmp->as_register();
534 __ get_thread(poll_addr);
535 __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset())));
536 #endif
537 add_debug_info_for_branch(info);
538 __ relocate(relocInfo::poll_type);
539 address pre_pc = __ pc();
540 __ testl(rax, Address(poll_addr, 0));
541 address post_pc = __ pc();
542 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
543 return offset;
544 }
545
546
547 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
548 if (from_reg != to_reg) __ mov(to_reg, from_reg);
549 }
550
551 void LIR_Assembler::swap_reg(Register a, Register b) {
552 __ xchgptr(a, b);
553 }
554
555
556 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
557 assert(src->is_constant(), "should not call otherwise");
558 assert(dest->is_register(), "should not call otherwise");
559 LIR_Const* c = src->as_constant_ptr();
560
561 switch (c->type()) {
562 case T_INT: {
563 assert(patch_code == lir_patch_none, "no patching handled here");
564 __ movl(dest->as_register(), c->as_jint());
565 break;
566 }
567
568 case T_ADDRESS: {
569 assert(patch_code == lir_patch_none, "no patching handled here");
570 __ movptr(dest->as_register(), c->as_jint());
571 break;
572 }
573
574 case T_LONG: {
575 assert(patch_code == lir_patch_none, "no patching handled here");
576 #ifdef _LP64
577 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
578 #else
579 __ movptr(dest->as_register_lo(), c->as_jint_lo());
580 __ movptr(dest->as_register_hi(), c->as_jint_hi());
581 #endif // _LP64
582 break;
583 }
584
585 case T_OBJECT: {
586 if (patch_code != lir_patch_none) {
587 jobject2reg_with_patching(dest->as_register(), info);
588 } else {
589 __ movoop(dest->as_register(), c->as_jobject());
590 }
591 break;
592 }
593
594 case T_METADATA: {
595 if (patch_code != lir_patch_none) {
596 klass2reg_with_patching(dest->as_register(), info);
597 } else {
598 __ mov_metadata(dest->as_register(), c->as_metadata());
599 }
600 break;
601 }
602
603 case T_FLOAT: {
604 if (dest->is_single_xmm()) {
605 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
606 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
607 } else {
608 __ movflt(dest->as_xmm_float_reg(),
609 InternalAddress(float_constant(c->as_jfloat())));
610 }
611 } else {
612 #ifndef _LP64
613 assert(dest->is_single_fpu(), "must be");
614 assert(dest->fpu_regnr() == 0, "dest must be TOS");
615 if (c->is_zero_float()) {
616 __ fldz();
617 } else if (c->is_one_float()) {
618 __ fld1();
619 } else {
620 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
621 }
622 #else
623 ShouldNotReachHere();
624 #endif // !_LP64
625 }
626 break;
627 }
628
629 case T_DOUBLE: {
630 if (dest->is_double_xmm()) {
631 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
632 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
633 } else {
634 __ movdbl(dest->as_xmm_double_reg(),
635 InternalAddress(double_constant(c->as_jdouble())));
636 }
637 } else {
638 #ifndef _LP64
639 assert(dest->is_double_fpu(), "must be");
640 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
641 if (c->is_zero_double()) {
642 __ fldz();
643 } else if (c->is_one_double()) {
644 __ fld1();
645 } else {
646 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
647 }
648 #else
649 ShouldNotReachHere();
650 #endif // !_LP64
651 }
652 break;
653 }
654
655 default:
656 ShouldNotReachHere();
657 }
658 }
659
660 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
661 assert(src->is_constant(), "should not call otherwise");
662 assert(dest->is_stack(), "should not call otherwise");
663 LIR_Const* c = src->as_constant_ptr();
664
665 switch (c->type()) {
666 case T_INT: // fall through
667 case T_FLOAT:
668 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
669 break;
670
671 case T_ADDRESS:
672 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
673 break;
674
675 case T_OBJECT:
676 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1);
677 break;
678
679 case T_LONG: // fall through
680 case T_DOUBLE:
681 #ifdef _LP64
682 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
683 lo_word_offset_in_bytes),
684 (intptr_t)c->as_jlong_bits(),
685 rscratch1);
686 #else
687 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
688 lo_word_offset_in_bytes), c->as_jint_lo_bits());
689 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
690 hi_word_offset_in_bytes), c->as_jint_hi_bits());
691 #endif // _LP64
692 break;
693
694 default:
695 ShouldNotReachHere();
696 }
697 }
698
699 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
700 assert(src->is_constant(), "should not call otherwise");
701 assert(dest->is_address(), "should not call otherwise");
702 LIR_Const* c = src->as_constant_ptr();
703 LIR_Address* addr = dest->as_address_ptr();
704
705 int null_check_here = code_offset();
706 switch (type) {
707 case T_INT: // fall through
708 case T_FLOAT:
709 __ movl(as_Address(addr), c->as_jint_bits());
710 break;
711
712 case T_ADDRESS:
713 __ movptr(as_Address(addr), c->as_jint_bits());
714 break;
715
716 case T_OBJECT: // fall through
717 case T_ARRAY:
718 if (c->as_jobject() == nullptr) {
719 if (UseCompressedOops && !wide) {
720 __ movl(as_Address(addr), NULL_WORD);
721 } else {
722 #ifdef _LP64
723 __ xorptr(rscratch1, rscratch1);
724 null_check_here = code_offset();
725 __ movptr(as_Address(addr), rscratch1);
726 #else
727 __ movptr(as_Address(addr), NULL_WORD);
728 #endif
729 }
730 } else {
731 if (is_literal_address(addr)) {
732 ShouldNotReachHere();
733 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1);
734 } else {
735 #ifdef _LP64
736 __ movoop(rscratch1, c->as_jobject());
737 if (UseCompressedOops && !wide) {
738 __ encode_heap_oop(rscratch1);
739 null_check_here = code_offset();
740 __ movl(as_Address_lo(addr), rscratch1);
741 } else {
742 null_check_here = code_offset();
743 __ movptr(as_Address_lo(addr), rscratch1);
744 }
745 #else
746 __ movoop(as_Address(addr), c->as_jobject(), noreg);
747 #endif
748 }
749 }
750 break;
751
752 case T_LONG: // fall through
753 case T_DOUBLE:
754 #ifdef _LP64
755 if (is_literal_address(addr)) {
756 ShouldNotReachHere();
757 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
758 } else {
759 __ movptr(r10, (intptr_t)c->as_jlong_bits());
760 null_check_here = code_offset();
761 __ movptr(as_Address_lo(addr), r10);
762 }
763 #else
764 // Always reachable in 32bit so this doesn't produce useless move literal
765 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
766 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
767 #endif // _LP64
768 break;
769
770 case T_BOOLEAN: // fall through
771 case T_BYTE:
772 __ movb(as_Address(addr), c->as_jint() & 0xFF);
773 break;
774
775 case T_CHAR: // fall through
776 case T_SHORT:
777 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
778 break;
779
780 default:
781 ShouldNotReachHere();
782 };
783
784 if (info != nullptr) {
785 add_debug_info_for_null_check(null_check_here, info);
786 }
787 }
788
789
790 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
791 assert(src->is_register(), "should not call otherwise");
792 assert(dest->is_register(), "should not call otherwise");
793
794 // move between cpu-registers
795 if (dest->is_single_cpu()) {
796 #ifdef _LP64
797 if (src->type() == T_LONG) {
798 // Can do LONG -> OBJECT
799 move_regs(src->as_register_lo(), dest->as_register());
800 return;
801 }
802 #endif
803 assert(src->is_single_cpu(), "must match");
804 if (src->type() == T_OBJECT) {
805 __ verify_oop(src->as_register());
806 }
807 move_regs(src->as_register(), dest->as_register());
808
809 } else if (dest->is_double_cpu()) {
810 #ifdef _LP64
811 if (is_reference_type(src->type())) {
812 // Surprising to me but we can see move of a long to t_object
813 __ verify_oop(src->as_register());
814 move_regs(src->as_register(), dest->as_register_lo());
815 return;
816 }
817 #endif
818 assert(src->is_double_cpu(), "must match");
819 Register f_lo = src->as_register_lo();
820 Register f_hi = src->as_register_hi();
821 Register t_lo = dest->as_register_lo();
822 Register t_hi = dest->as_register_hi();
823 #ifdef _LP64
824 assert(f_hi == f_lo, "must be same");
825 assert(t_hi == t_lo, "must be same");
826 move_regs(f_lo, t_lo);
827 #else
828 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
829
830
831 if (f_lo == t_hi && f_hi == t_lo) {
832 swap_reg(f_lo, f_hi);
833 } else if (f_hi == t_lo) {
834 assert(f_lo != t_hi, "overwriting register");
835 move_regs(f_hi, t_hi);
836 move_regs(f_lo, t_lo);
837 } else {
838 assert(f_hi != t_lo, "overwriting register");
839 move_regs(f_lo, t_lo);
840 move_regs(f_hi, t_hi);
841 }
842 #endif // LP64
843
844 #ifndef _LP64
845 // special moves from fpu-register to xmm-register
846 // necessary for method results
847 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
848 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
849 __ fld_s(Address(rsp, 0));
850 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
851 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
852 __ fld_d(Address(rsp, 0));
853 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
854 __ fstp_s(Address(rsp, 0));
855 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
856 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
857 __ fstp_d(Address(rsp, 0));
858 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
859 #endif // !_LP64
860
861 // move between xmm-registers
862 } else if (dest->is_single_xmm()) {
863 assert(src->is_single_xmm(), "must match");
864 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
865 } else if (dest->is_double_xmm()) {
866 assert(src->is_double_xmm(), "must match");
867 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
868
869 #ifndef _LP64
870 // move between fpu-registers (no instruction necessary because of fpu-stack)
871 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
872 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
873 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
874 #endif // !_LP64
875
876 } else {
877 ShouldNotReachHere();
878 }
879 }
880
881 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
882 assert(src->is_register(), "should not call otherwise");
883 assert(dest->is_stack(), "should not call otherwise");
884
885 if (src->is_single_cpu()) {
886 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
887 if (is_reference_type(type)) {
888 __ verify_oop(src->as_register());
889 __ movptr (dst, src->as_register());
890 } else if (type == T_METADATA || type == T_ADDRESS) {
891 __ movptr (dst, src->as_register());
892 } else {
893 __ movl (dst, src->as_register());
894 }
895
896 } else if (src->is_double_cpu()) {
897 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
898 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
899 __ movptr (dstLO, src->as_register_lo());
900 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
901
902 } else if (src->is_single_xmm()) {
903 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
904 __ movflt(dst_addr, src->as_xmm_float_reg());
905
906 } else if (src->is_double_xmm()) {
907 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
908 __ movdbl(dst_addr, src->as_xmm_double_reg());
909
910 #ifndef _LP64
911 } else if (src->is_single_fpu()) {
912 assert(src->fpu_regnr() == 0, "argument must be on TOS");
913 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
914 if (pop_fpu_stack) __ fstp_s (dst_addr);
915 else __ fst_s (dst_addr);
916
917 } else if (src->is_double_fpu()) {
918 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
919 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
920 if (pop_fpu_stack) __ fstp_d (dst_addr);
921 else __ fst_d (dst_addr);
922 #endif // !_LP64
923
924 } else {
925 ShouldNotReachHere();
926 }
927 }
928
929
930 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
931 LIR_Address* to_addr = dest->as_address_ptr();
932 PatchingStub* patch = nullptr;
933 Register compressed_src = rscratch1;
934
935 if (is_reference_type(type)) {
936 __ verify_oop(src->as_register());
937 #ifdef _LP64
938 if (UseCompressedOops && !wide) {
939 __ movptr(compressed_src, src->as_register());
940 __ encode_heap_oop(compressed_src);
941 if (patch_code != lir_patch_none) {
942 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
943 }
944 }
945 #endif
946 }
947
948 if (patch_code != lir_patch_none) {
949 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
950 Address toa = as_Address(to_addr);
951 assert(toa.disp() != 0, "must have");
952 }
953
954 int null_check_here = code_offset();
955 switch (type) {
956 case T_FLOAT: {
957 #ifdef _LP64
958 assert(src->is_single_xmm(), "not a float");
959 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
960 #else
961 if (src->is_single_xmm()) {
962 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
963 } else {
964 assert(src->is_single_fpu(), "must be");
965 assert(src->fpu_regnr() == 0, "argument must be on TOS");
966 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
967 else __ fst_s (as_Address(to_addr));
968 }
969 #endif // _LP64
970 break;
971 }
972
973 case T_DOUBLE: {
974 #ifdef _LP64
975 assert(src->is_double_xmm(), "not a double");
976 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
977 #else
978 if (src->is_double_xmm()) {
979 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
980 } else {
981 assert(src->is_double_fpu(), "must be");
982 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
983 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
984 else __ fst_d (as_Address(to_addr));
985 }
986 #endif // _LP64
987 break;
988 }
989
990 case T_ARRAY: // fall through
991 case T_OBJECT: // fall through
992 if (UseCompressedOops && !wide) {
993 __ movl(as_Address(to_addr), compressed_src);
994 } else {
995 __ movptr(as_Address(to_addr), src->as_register());
996 }
997 break;
998 case T_METADATA:
999 // We get here to store a method pointer to the stack to pass to
1000 // a dtrace runtime call. This can't work on 64 bit with
1001 // compressed klass ptrs: T_METADATA can be a compressed klass
1002 // ptr or a 64 bit method pointer.
1003 LP64_ONLY(ShouldNotReachHere());
1004 __ movptr(as_Address(to_addr), src->as_register());
1005 break;
1006 case T_ADDRESS:
1007 __ movptr(as_Address(to_addr), src->as_register());
1008 break;
1009 case T_INT:
1010 __ movl(as_Address(to_addr), src->as_register());
1011 break;
1012
1013 case T_LONG: {
1014 Register from_lo = src->as_register_lo();
1015 Register from_hi = src->as_register_hi();
1016 #ifdef _LP64
1017 __ movptr(as_Address_lo(to_addr), from_lo);
1018 #else
1019 Register base = to_addr->base()->as_register();
1020 Register index = noreg;
1021 if (to_addr->index()->is_register()) {
1022 index = to_addr->index()->as_register();
1023 }
1024 if (base == from_lo || index == from_lo) {
1025 assert(base != from_hi, "can't be");
1026 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1027 __ movl(as_Address_hi(to_addr), from_hi);
1028 if (patch != nullptr) {
1029 patching_epilog(patch, lir_patch_high, base, info);
1030 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1031 patch_code = lir_patch_low;
1032 }
1033 __ movl(as_Address_lo(to_addr), from_lo);
1034 } else {
1035 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1036 __ movl(as_Address_lo(to_addr), from_lo);
1037 if (patch != nullptr) {
1038 patching_epilog(patch, lir_patch_low, base, info);
1039 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1040 patch_code = lir_patch_high;
1041 }
1042 __ movl(as_Address_hi(to_addr), from_hi);
1043 }
1044 #endif // _LP64
1045 break;
1046 }
1047
1048 case T_BYTE: // fall through
1049 case T_BOOLEAN: {
1050 Register src_reg = src->as_register();
1051 Address dst_addr = as_Address(to_addr);
1052 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1053 __ movb(dst_addr, src_reg);
1054 break;
1055 }
1056
1057 case T_CHAR: // fall through
1058 case T_SHORT:
1059 __ movw(as_Address(to_addr), src->as_register());
1060 break;
1061
1062 default:
1063 ShouldNotReachHere();
1064 }
1065 if (info != nullptr) {
1066 add_debug_info_for_null_check(null_check_here, info);
1067 }
1068
1069 if (patch_code != lir_patch_none) {
1070 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1071 }
1072 }
1073
1074
1075 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1076 assert(src->is_stack(), "should not call otherwise");
1077 assert(dest->is_register(), "should not call otherwise");
1078
1079 if (dest->is_single_cpu()) {
1080 if (is_reference_type(type)) {
1081 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1082 __ verify_oop(dest->as_register());
1083 } else if (type == T_METADATA || type == T_ADDRESS) {
1084 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1085 } else {
1086 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1087 }
1088
1089 } else if (dest->is_double_cpu()) {
1090 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1091 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1092 __ movptr(dest->as_register_lo(), src_addr_LO);
1093 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1094
1095 } else if (dest->is_single_xmm()) {
1096 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1097 __ movflt(dest->as_xmm_float_reg(), src_addr);
1098
1099 } else if (dest->is_double_xmm()) {
1100 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1101 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1102
1103 #ifndef _LP64
1104 } else if (dest->is_single_fpu()) {
1105 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1106 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1107 __ fld_s(src_addr);
1108
1109 } else if (dest->is_double_fpu()) {
1110 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1111 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1112 __ fld_d(src_addr);
1113 #endif // _LP64
1114
1115 } else {
1116 ShouldNotReachHere();
1117 }
1118 }
1119
1120
1121 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1122 if (src->is_single_stack()) {
1123 if (is_reference_type(type)) {
1124 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1125 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1126 } else {
1127 #ifndef _LP64
1128 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1129 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1130 #else
1131 //no pushl on 64bits
1132 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1133 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1134 #endif
1135 }
1136
1137 } else if (src->is_double_stack()) {
1138 #ifdef _LP64
1139 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1140 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1141 #else
1142 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1143 // push and pop the part at src + wordSize, adding wordSize for the previous push
1144 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1145 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1146 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1147 #endif // _LP64
1148
1149 } else {
1150 ShouldNotReachHere();
1151 }
1152 }
1153
1154
1155 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1156 assert(src->is_address(), "should not call otherwise");
1157 assert(dest->is_register(), "should not call otherwise");
1158
1159 LIR_Address* addr = src->as_address_ptr();
1160 Address from_addr = as_Address(addr);
1161
1162 if (addr->base()->type() == T_OBJECT) {
1163 __ verify_oop(addr->base()->as_pointer_register());
1164 }
1165
1166 switch (type) {
1167 case T_BOOLEAN: // fall through
1168 case T_BYTE: // fall through
1169 case T_CHAR: // fall through
1170 case T_SHORT:
1171 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1172 // on pre P6 processors we may get partial register stalls
1173 // so blow away the value of to_rinfo before loading a
1174 // partial word into it. Do it here so that it precedes
1175 // the potential patch point below.
1176 __ xorptr(dest->as_register(), dest->as_register());
1177 }
1178 break;
1179 default:
1180 break;
1181 }
1182
1183 PatchingStub* patch = nullptr;
1184 if (patch_code != lir_patch_none) {
1185 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1186 assert(from_addr.disp() != 0, "must have");
1187 }
1188 if (info != nullptr) {
1189 add_debug_info_for_null_check_here(info);
1190 }
1191
1192 switch (type) {
1193 case T_FLOAT: {
1194 if (dest->is_single_xmm()) {
1195 __ movflt(dest->as_xmm_float_reg(), from_addr);
1196 } else {
1197 #ifndef _LP64
1198 assert(dest->is_single_fpu(), "must be");
1199 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1200 __ fld_s(from_addr);
1201 #else
1202 ShouldNotReachHere();
1203 #endif // !LP64
1204 }
1205 break;
1206 }
1207
1208 case T_DOUBLE: {
1209 if (dest->is_double_xmm()) {
1210 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1211 } else {
1212 #ifndef _LP64
1213 assert(dest->is_double_fpu(), "must be");
1214 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1215 __ fld_d(from_addr);
1216 #else
1217 ShouldNotReachHere();
1218 #endif // !LP64
1219 }
1220 break;
1221 }
1222
1223 case T_OBJECT: // fall through
1224 case T_ARRAY: // fall through
1225 if (UseCompressedOops && !wide) {
1226 __ movl(dest->as_register(), from_addr);
1227 } else {
1228 __ movptr(dest->as_register(), from_addr);
1229 }
1230 break;
1231
1232 case T_ADDRESS:
1233 __ movptr(dest->as_register(), from_addr);
1234 break;
1235 case T_INT:
1236 __ movl(dest->as_register(), from_addr);
1237 break;
1238
1239 case T_LONG: {
1240 Register to_lo = dest->as_register_lo();
1241 Register to_hi = dest->as_register_hi();
1242 #ifdef _LP64
1243 __ movptr(to_lo, as_Address_lo(addr));
1244 #else
1245 Register base = addr->base()->as_register();
1246 Register index = noreg;
1247 if (addr->index()->is_register()) {
1248 index = addr->index()->as_register();
1249 }
1250 if ((base == to_lo && index == to_hi) ||
1251 (base == to_hi && index == to_lo)) {
1252 // addresses with 2 registers are only formed as a result of
1253 // array access so this code will never have to deal with
1254 // patches or null checks.
1255 assert(info == nullptr && patch == nullptr, "must be");
1256 __ lea(to_hi, as_Address(addr));
1257 __ movl(to_lo, Address(to_hi, 0));
1258 __ movl(to_hi, Address(to_hi, BytesPerWord));
1259 } else if (base == to_lo || index == to_lo) {
1260 assert(base != to_hi, "can't be");
1261 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1262 __ movl(to_hi, as_Address_hi(addr));
1263 if (patch != nullptr) {
1264 patching_epilog(patch, lir_patch_high, base, info);
1265 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1266 patch_code = lir_patch_low;
1267 }
1268 __ movl(to_lo, as_Address_lo(addr));
1269 } else {
1270 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1271 __ movl(to_lo, as_Address_lo(addr));
1272 if (patch != nullptr) {
1273 patching_epilog(patch, lir_patch_low, base, info);
1274 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1275 patch_code = lir_patch_high;
1276 }
1277 __ movl(to_hi, as_Address_hi(addr));
1278 }
1279 #endif // _LP64
1280 break;
1281 }
1282
1283 case T_BOOLEAN: // fall through
1284 case T_BYTE: {
1285 Register dest_reg = dest->as_register();
1286 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1287 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1288 __ movsbl(dest_reg, from_addr);
1289 } else {
1290 __ movb(dest_reg, from_addr);
1291 __ shll(dest_reg, 24);
1292 __ sarl(dest_reg, 24);
1293 }
1294 break;
1295 }
1296
1297 case T_CHAR: {
1298 Register dest_reg = dest->as_register();
1299 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1300 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1301 __ movzwl(dest_reg, from_addr);
1302 } else {
1303 __ movw(dest_reg, from_addr);
1304 }
1305 break;
1306 }
1307
1308 case T_SHORT: {
1309 Register dest_reg = dest->as_register();
1310 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1311 __ movswl(dest_reg, from_addr);
1312 } else {
1313 __ movw(dest_reg, from_addr);
1314 __ shll(dest_reg, 16);
1315 __ sarl(dest_reg, 16);
1316 }
1317 break;
1318 }
1319
1320 default:
1321 ShouldNotReachHere();
1322 }
1323
1324 if (patch != nullptr) {
1325 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1326 }
1327
1328 if (is_reference_type(type)) {
1329 #ifdef _LP64
1330 if (UseCompressedOops && !wide) {
1331 __ decode_heap_oop(dest->as_register());
1332 }
1333 #endif
1334
1335 __ verify_oop(dest->as_register());
1336 }
1337 }
1338
1339
1340 NEEDS_CLEANUP; // This could be static?
1341 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1342 int elem_size = type2aelembytes(type);
1343 switch (elem_size) {
1344 case 1: return Address::times_1;
1345 case 2: return Address::times_2;
1346 case 4: return Address::times_4;
1347 case 8: return Address::times_8;
1348 }
1349 ShouldNotReachHere();
1350 return Address::no_scale;
1351 }
1352
1353
1354 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1355 switch (op->code()) {
1356 case lir_idiv:
1357 case lir_irem:
1358 arithmetic_idiv(op->code(),
1359 op->in_opr1(),
1360 op->in_opr2(),
1361 op->in_opr3(),
1362 op->result_opr(),
1363 op->info());
1364 break;
1365 case lir_fmad:
1366 __ fmad(op->result_opr()->as_xmm_double_reg(),
1367 op->in_opr1()->as_xmm_double_reg(),
1368 op->in_opr2()->as_xmm_double_reg(),
1369 op->in_opr3()->as_xmm_double_reg());
1370 break;
1371 case lir_fmaf:
1372 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1373 op->in_opr1()->as_xmm_float_reg(),
1374 op->in_opr2()->as_xmm_float_reg(),
1375 op->in_opr3()->as_xmm_float_reg());
1376 break;
1377 default: ShouldNotReachHere(); break;
1378 }
1379 }
1380
1381 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1382 #ifdef ASSERT
1383 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1384 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1385 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1386 #endif
1387
1388 if (op->cond() == lir_cond_always) {
1389 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1390 __ jmp (*(op->label()));
1391 } else {
1392 Assembler::Condition acond = Assembler::zero;
1393 if (op->code() == lir_cond_float_branch) {
1394 assert(op->ublock() != nullptr, "must have unordered successor");
1395 __ jcc(Assembler::parity, *(op->ublock()->label()));
1396 switch(op->cond()) {
1397 case lir_cond_equal: acond = Assembler::equal; break;
1398 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1399 case lir_cond_less: acond = Assembler::below; break;
1400 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1401 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1402 case lir_cond_greater: acond = Assembler::above; break;
1403 default: ShouldNotReachHere();
1404 }
1405 } else {
1406 switch (op->cond()) {
1407 case lir_cond_equal: acond = Assembler::equal; break;
1408 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1409 case lir_cond_less: acond = Assembler::less; break;
1410 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1411 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1412 case lir_cond_greater: acond = Assembler::greater; break;
1413 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1414 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1415 default: ShouldNotReachHere();
1416 }
1417 }
1418 __ jcc(acond,*(op->label()));
1419 }
1420 }
1421
1422 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1423 LIR_Opr src = op->in_opr();
1424 LIR_Opr dest = op->result_opr();
1425
1426 switch (op->bytecode()) {
1427 case Bytecodes::_i2l:
1428 #ifdef _LP64
1429 __ movl2ptr(dest->as_register_lo(), src->as_register());
1430 #else
1431 move_regs(src->as_register(), dest->as_register_lo());
1432 move_regs(src->as_register(), dest->as_register_hi());
1433 __ sarl(dest->as_register_hi(), 31);
1434 #endif // LP64
1435 break;
1436
1437 case Bytecodes::_l2i:
1438 #ifdef _LP64
1439 __ movl(dest->as_register(), src->as_register_lo());
1440 #else
1441 move_regs(src->as_register_lo(), dest->as_register());
1442 #endif
1443 break;
1444
1445 case Bytecodes::_i2b:
1446 move_regs(src->as_register(), dest->as_register());
1447 __ sign_extend_byte(dest->as_register());
1448 break;
1449
1450 case Bytecodes::_i2c:
1451 move_regs(src->as_register(), dest->as_register());
1452 __ andl(dest->as_register(), 0xFFFF);
1453 break;
1454
1455 case Bytecodes::_i2s:
1456 move_regs(src->as_register(), dest->as_register());
1457 __ sign_extend_short(dest->as_register());
1458 break;
1459
1460
1461 #ifdef _LP64
1462 case Bytecodes::_f2d:
1463 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1464 break;
1465
1466 case Bytecodes::_d2f:
1467 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1468 break;
1469
1470 case Bytecodes::_i2f:
1471 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1472 break;
1473
1474 case Bytecodes::_i2d:
1475 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1476 break;
1477
1478 case Bytecodes::_l2f:
1479 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1480 break;
1481
1482 case Bytecodes::_l2d:
1483 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1484 break;
1485
1486 case Bytecodes::_f2i:
1487 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1488 break;
1489
1490 case Bytecodes::_d2i:
1491 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1492 break;
1493
1494 case Bytecodes::_f2l:
1495 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1496 break;
1497
1498 case Bytecodes::_d2l:
1499 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1500 break;
1501 #else
1502 case Bytecodes::_f2d:
1503 case Bytecodes::_d2f:
1504 if (dest->is_single_xmm()) {
1505 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1506 } else if (dest->is_double_xmm()) {
1507 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1508 } else {
1509 assert(src->fpu() == dest->fpu(), "register must be equal");
1510 // do nothing (float result is rounded later through spilling)
1511 }
1512 break;
1513
1514 case Bytecodes::_i2f:
1515 case Bytecodes::_i2d:
1516 if (dest->is_single_xmm()) {
1517 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1518 } else if (dest->is_double_xmm()) {
1519 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1520 } else {
1521 assert(dest->fpu() == 0, "result must be on TOS");
1522 __ movl(Address(rsp, 0), src->as_register());
1523 __ fild_s(Address(rsp, 0));
1524 }
1525 break;
1526
1527 case Bytecodes::_l2f:
1528 case Bytecodes::_l2d:
1529 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1530 assert(dest->fpu() == 0, "result must be on TOS");
1531 __ movptr(Address(rsp, 0), src->as_register_lo());
1532 __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1533 __ fild_d(Address(rsp, 0));
1534 // float result is rounded later through spilling
1535 break;
1536
1537 case Bytecodes::_f2i:
1538 case Bytecodes::_d2i:
1539 if (src->is_single_xmm()) {
1540 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1541 } else if (src->is_double_xmm()) {
1542 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1543 } else {
1544 assert(src->fpu() == 0, "input must be on TOS");
1545 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc()));
1546 __ fist_s(Address(rsp, 0));
1547 __ movl(dest->as_register(), Address(rsp, 0));
1548 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
1549 }
1550 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1551 assert(op->stub() != nullptr, "stub required");
1552 __ cmpl(dest->as_register(), 0x80000000);
1553 __ jcc(Assembler::equal, *op->stub()->entry());
1554 __ bind(*op->stub()->continuation());
1555 break;
1556
1557 case Bytecodes::_f2l:
1558 case Bytecodes::_d2l:
1559 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1560 assert(src->fpu() == 0, "input must be on TOS");
1561 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1562
1563 // instruction sequence too long to inline it here
1564 {
1565 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::fpu2long_stub_id)));
1566 }
1567 break;
1568 #endif // _LP64
1569
1570 default: ShouldNotReachHere();
1571 }
1572 }
1573
1574 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1575 if (op->init_check()) {
1576 add_debug_info_for_null_check_here(op->stub()->info());
1577 // init_state needs acquire, but x86 is TSO, and so we are already good.
1578 __ cmpb(Address(op->klass()->as_register(),
1579 InstanceKlass::init_state_offset()),
1580 InstanceKlass::fully_initialized);
1581 __ jcc(Assembler::notEqual, *op->stub()->entry());
1582 }
1583 __ allocate_object(op->obj()->as_register(),
1584 op->tmp1()->as_register(),
1585 op->tmp2()->as_register(),
1586 op->header_size(),
1587 op->object_size(),
1588 op->klass()->as_register(),
1589 *op->stub()->entry());
1590 __ bind(*op->stub()->continuation());
1591 }
1592
1593 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1594 Register len = op->len()->as_register();
1595 LP64_ONLY( __ movslq(len, len); )
1596
1597 if (UseSlowPath ||
1598 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1599 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1600 __ jmp(*op->stub()->entry());
1601 } else {
1602 Register tmp1 = op->tmp1()->as_register();
1603 Register tmp2 = op->tmp2()->as_register();
1604 Register tmp3 = op->tmp3()->as_register();
1605 if (len == tmp1) {
1606 tmp1 = tmp3;
1607 } else if (len == tmp2) {
1608 tmp2 = tmp3;
1609 } else if (len == tmp3) {
1610 // everything is ok
1611 } else {
1612 __ mov(tmp3, len);
1613 }
1614 __ allocate_array(op->obj()->as_register(),
1615 len,
1616 tmp1,
1617 tmp2,
1618 arrayOopDesc::base_offset_in_bytes(op->type()),
1619 array_element_size(op->type()),
1620 op->klass()->as_register(),
1621 *op->stub()->entry(),
1622 op->zero_array());
1623 }
1624 __ bind(*op->stub()->continuation());
1625 }
1626
1627 void LIR_Assembler::type_profile_helper(Register mdo,
1628 ciMethodData *md, ciProfileData *data,
1629 Register recv, Label* update_done) {
1630 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1631 Label next_test;
1632 // See if the receiver is receiver[n].
1633 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1634 __ jccb(Assembler::notEqual, next_test);
1635 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1636 __ addptr(data_addr, DataLayout::counter_increment);
1637 __ jmp(*update_done);
1638 __ bind(next_test);
1639 }
1640
1641 // Didn't find receiver; find next empty slot and fill it in
1642 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1643 Label next_test;
1644 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1645 __ cmpptr(recv_addr, NULL_WORD);
1646 __ jccb(Assembler::notEqual, next_test);
1647 __ movptr(recv_addr, recv);
1648 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1649 __ jmp(*update_done);
1650 __ bind(next_test);
1651 }
1652 }
1653
1654 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1655 // we always need a stub for the failure case.
1656 CodeStub* stub = op->stub();
1657 Register obj = op->object()->as_register();
1658 Register k_RInfo = op->tmp1()->as_register();
1659 Register klass_RInfo = op->tmp2()->as_register();
1660 Register dst = op->result_opr()->as_register();
1661 ciKlass* k = op->klass();
1662 Register Rtmp1 = noreg;
1663 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1664
1665 // check if it needs to be profiled
1666 ciMethodData* md = nullptr;
1667 ciProfileData* data = nullptr;
1668
1669 if (op->should_profile()) {
1670 ciMethod* method = op->profiled_method();
1671 assert(method != nullptr, "Should have method");
1672 int bci = op->profiled_bci();
1673 md = method->method_data_or_null();
1674 assert(md != nullptr, "Sanity");
1675 data = md->bci_to_data(bci);
1676 assert(data != nullptr, "need data for type check");
1677 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1678 }
1679 Label* success_target = success;
1680 Label* failure_target = failure;
1681
1682 if (obj == k_RInfo) {
1683 k_RInfo = dst;
1684 } else if (obj == klass_RInfo) {
1685 klass_RInfo = dst;
1686 }
1687 if (k->is_loaded() && !UseCompressedClassPointers) {
1688 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1689 } else {
1690 Rtmp1 = op->tmp3()->as_register();
1691 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1692 }
1693
1694 assert_different_registers(obj, k_RInfo, klass_RInfo);
1695
1696 __ testptr(obj, obj);
1697 if (op->should_profile()) {
1698 Label not_null;
1699 Register mdo = klass_RInfo;
1700 __ mov_metadata(mdo, md->constant_encoding());
1701 __ jccb(Assembler::notEqual, not_null);
1702 // Object is null; update MDO and exit
1703 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1704 int header_bits = BitData::null_seen_byte_constant();
1705 __ orb(data_addr, header_bits);
1706 __ jmp(*obj_is_null);
1707 __ bind(not_null);
1708
1709 Label update_done;
1710 Register recv = k_RInfo;
1711 __ load_klass(recv, obj, tmp_load_klass);
1712 type_profile_helper(mdo, md, data, recv, &update_done);
1713
1714 Address nonprofiled_receiver_count_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1715 __ addptr(nonprofiled_receiver_count_addr, DataLayout::counter_increment);
1716
1717 __ bind(update_done);
1718 } else {
1719 __ jcc(Assembler::equal, *obj_is_null);
1720 }
1721
1722 if (!k->is_loaded()) {
1723 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1724 } else {
1725 #ifdef _LP64
1726 __ mov_metadata(k_RInfo, k->constant_encoding());
1727 #endif // _LP64
1728 }
1729 __ verify_oop(obj);
1730
1731 if (op->fast_check()) {
1732 // get object class
1733 // not a safepoint as obj null check happens earlier
1734 #ifdef _LP64
1735 if (UseCompressedClassPointers) {
1736 __ load_klass(Rtmp1, obj, tmp_load_klass);
1737 __ cmpptr(k_RInfo, Rtmp1);
1738 } else {
1739 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1740 }
1741 #else
1742 if (k->is_loaded()) {
1743 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1744 } else {
1745 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1746 }
1747 #endif
1748 __ jcc(Assembler::notEqual, *failure_target);
1749 // successful cast, fall through to profile or jump
1750 } else {
1751 // get object class
1752 // not a safepoint as obj null check happens earlier
1753 __ load_klass(klass_RInfo, obj, tmp_load_klass);
1754 if (k->is_loaded()) {
1755 // See if we get an immediate positive hit
1756 #ifdef _LP64
1757 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1758 #else
1759 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1760 #endif // _LP64
1761 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1762 __ jcc(Assembler::notEqual, *failure_target);
1763 // successful cast, fall through to profile or jump
1764 } else {
1765 // See if we get an immediate positive hit
1766 __ jcc(Assembler::equal, *success_target);
1767 // check for self
1768 #ifdef _LP64
1769 __ cmpptr(klass_RInfo, k_RInfo);
1770 #else
1771 __ cmpklass(klass_RInfo, k->constant_encoding());
1772 #endif // _LP64
1773 __ jcc(Assembler::equal, *success_target);
1774
1775 __ push(klass_RInfo);
1776 #ifdef _LP64
1777 __ push(k_RInfo);
1778 #else
1779 __ pushklass(k->constant_encoding(), noreg);
1780 #endif // _LP64
1781 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1782 __ pop(klass_RInfo);
1783 __ pop(klass_RInfo);
1784 // result is a boolean
1785 __ testl(klass_RInfo, klass_RInfo);
1786 __ jcc(Assembler::equal, *failure_target);
1787 // successful cast, fall through to profile or jump
1788 }
1789 } else {
1790 // perform the fast part of the checking logic
1791 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1792 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1793 __ push(klass_RInfo);
1794 __ push(k_RInfo);
1795 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1796 __ pop(klass_RInfo);
1797 __ pop(k_RInfo);
1798 // result is a boolean
1799 __ testl(k_RInfo, k_RInfo);
1800 __ jcc(Assembler::equal, *failure_target);
1801 // successful cast, fall through to profile or jump
1802 }
1803 }
1804 __ jmp(*success);
1805 }
1806
1807
1808 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1809 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1810 LIR_Code code = op->code();
1811 if (code == lir_store_check) {
1812 Register value = op->object()->as_register();
1813 Register array = op->array()->as_register();
1814 Register k_RInfo = op->tmp1()->as_register();
1815 Register klass_RInfo = op->tmp2()->as_register();
1816 Register Rtmp1 = op->tmp3()->as_register();
1817
1818 CodeStub* stub = op->stub();
1819
1820 // check if it needs to be profiled
1821 ciMethodData* md = nullptr;
1822 ciProfileData* data = nullptr;
1823
1824 if (op->should_profile()) {
1825 ciMethod* method = op->profiled_method();
1826 assert(method != nullptr, "Should have method");
1827 int bci = op->profiled_bci();
1828 md = method->method_data_or_null();
1829 assert(md != nullptr, "Sanity");
1830 data = md->bci_to_data(bci);
1831 assert(data != nullptr, "need data for type check");
1832 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1833 }
1834 Label done;
1835 Label* success_target = &done;
1836 Label* failure_target = stub->entry();
1837
1838 __ testptr(value, value);
1839 if (op->should_profile()) {
1840 Label not_null;
1841 Register mdo = klass_RInfo;
1842 __ mov_metadata(mdo, md->constant_encoding());
1843 __ jccb(Assembler::notEqual, not_null);
1844 // Object is null; update MDO and exit
1845 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1846 int header_bits = BitData::null_seen_byte_constant();
1847 __ orb(data_addr, header_bits);
1848 __ jmp(done);
1849 __ bind(not_null);
1850
1851 Label update_done;
1852 Register recv = k_RInfo;
1853 __ load_klass(recv, value, tmp_load_klass);
1854 type_profile_helper(mdo, md, data, recv, &update_done);
1855
1856 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1857 __ addptr(counter_addr, DataLayout::counter_increment);
1858 __ bind(update_done);
1859 } else {
1860 __ jcc(Assembler::equal, done);
1861 }
1862
1863 add_debug_info_for_null_check_here(op->info_for_exception());
1864 __ load_klass(k_RInfo, array, tmp_load_klass);
1865 __ load_klass(klass_RInfo, value, tmp_load_klass);
1866
1867 // get instance klass (it's already uncompressed)
1868 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1869 // perform the fast part of the checking logic
1870 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1871 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1872 __ push(klass_RInfo);
1873 __ push(k_RInfo);
1874 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1875 __ pop(klass_RInfo);
1876 __ pop(k_RInfo);
1877 // result is a boolean
1878 __ testl(k_RInfo, k_RInfo);
1879 __ jcc(Assembler::equal, *failure_target);
1880 // fall through to the success case
1881
1882 __ bind(done);
1883 } else
1884 if (code == lir_checkcast) {
1885 Register obj = op->object()->as_register();
1886 Register dst = op->result_opr()->as_register();
1887 Label success;
1888 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1889 __ bind(success);
1890 if (dst != obj) {
1891 __ mov(dst, obj);
1892 }
1893 } else
1894 if (code == lir_instanceof) {
1895 Register obj = op->object()->as_register();
1896 Register dst = op->result_opr()->as_register();
1897 Label success, failure, done;
1898 emit_typecheck_helper(op, &success, &failure, &failure);
1899 __ bind(failure);
1900 __ xorptr(dst, dst);
1901 __ jmpb(done);
1902 __ bind(success);
1903 __ movptr(dst, 1);
1904 __ bind(done);
1905 } else {
1906 ShouldNotReachHere();
1907 }
1908
1909 }
1910
1911
1912 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1913 if (LP64_ONLY(false &&) op->code() == lir_cas_long) {
1914 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1915 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1916 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1917 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1918 Register addr = op->addr()->as_register();
1919 __ lock();
1920 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1921
1922 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1923 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1924 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1925 Register newval = op->new_value()->as_register();
1926 Register cmpval = op->cmp_value()->as_register();
1927 assert(cmpval == rax, "wrong register");
1928 assert(newval != noreg, "new val must be register");
1929 assert(cmpval != newval, "cmp and new values must be in different registers");
1930 assert(cmpval != addr, "cmp and addr must be in different registers");
1931 assert(newval != addr, "new value and addr must be in different registers");
1932
1933 if ( op->code() == lir_cas_obj) {
1934 #ifdef _LP64
1935 if (UseCompressedOops) {
1936 __ encode_heap_oop(cmpval);
1937 __ mov(rscratch1, newval);
1938 __ encode_heap_oop(rscratch1);
1939 __ lock();
1940 // cmpval (rax) is implicitly used by this instruction
1941 __ cmpxchgl(rscratch1, Address(addr, 0));
1942 } else
1943 #endif
1944 {
1945 __ lock();
1946 __ cmpxchgptr(newval, Address(addr, 0));
1947 }
1948 } else {
1949 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1950 __ lock();
1951 __ cmpxchgl(newval, Address(addr, 0));
1952 }
1953 #ifdef _LP64
1954 } else if (op->code() == lir_cas_long) {
1955 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1956 Register newval = op->new_value()->as_register_lo();
1957 Register cmpval = op->cmp_value()->as_register_lo();
1958 assert(cmpval == rax, "wrong register");
1959 assert(newval != noreg, "new val must be register");
1960 assert(cmpval != newval, "cmp and new values must be in different registers");
1961 assert(cmpval != addr, "cmp and addr must be in different registers");
1962 assert(newval != addr, "new value and addr must be in different registers");
1963 __ lock();
1964 __ cmpxchgq(newval, Address(addr, 0));
1965 #endif // _LP64
1966 } else {
1967 Unimplemented();
1968 }
1969 }
1970
1971 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1972 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1973 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
1974
1975 Assembler::Condition acond, ncond;
1976 switch (condition) {
1977 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1978 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1979 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1980 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1981 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1982 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1983 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1984 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1985 default: acond = Assembler::equal; ncond = Assembler::notEqual;
1986 ShouldNotReachHere();
1987 }
1988
1989 if (opr1->is_cpu_register()) {
1990 reg2reg(opr1, result);
1991 } else if (opr1->is_stack()) {
1992 stack2reg(opr1, result, result->type());
1993 } else if (opr1->is_constant()) {
1994 const2reg(opr1, result, lir_patch_none, nullptr);
1995 } else {
1996 ShouldNotReachHere();
1997 }
1998
1999 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2000 // optimized version that does not require a branch
2001 if (opr2->is_single_cpu()) {
2002 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2003 __ cmov(ncond, result->as_register(), opr2->as_register());
2004 } else if (opr2->is_double_cpu()) {
2005 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2006 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2007 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2008 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2009 } else if (opr2->is_single_stack()) {
2010 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2011 } else if (opr2->is_double_stack()) {
2012 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2013 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2014 } else {
2015 ShouldNotReachHere();
2016 }
2017
2018 } else {
2019 Label skip;
2020 __ jccb(acond, skip);
2021 if (opr2->is_cpu_register()) {
2022 reg2reg(opr2, result);
2023 } else if (opr2->is_stack()) {
2024 stack2reg(opr2, result, result->type());
2025 } else if (opr2->is_constant()) {
2026 const2reg(opr2, result, lir_patch_none, nullptr);
2027 } else {
2028 ShouldNotReachHere();
2029 }
2030 __ bind(skip);
2031 }
2032 }
2033
2034
2035 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2036 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2037
2038 if (left->is_single_cpu()) {
2039 assert(left == dest, "left and dest must be equal");
2040 Register lreg = left->as_register();
2041
2042 if (right->is_single_cpu()) {
2043 // cpu register - cpu register
2044 Register rreg = right->as_register();
2045 switch (code) {
2046 case lir_add: __ addl (lreg, rreg); break;
2047 case lir_sub: __ subl (lreg, rreg); break;
2048 case lir_mul: __ imull(lreg, rreg); break;
2049 default: ShouldNotReachHere();
2050 }
2051
2052 } else if (right->is_stack()) {
2053 // cpu register - stack
2054 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2055 switch (code) {
2056 case lir_add: __ addl(lreg, raddr); break;
2057 case lir_sub: __ subl(lreg, raddr); break;
2058 default: ShouldNotReachHere();
2059 }
2060
2061 } else if (right->is_constant()) {
2062 // cpu register - constant
2063 jint c = right->as_constant_ptr()->as_jint();
2064 switch (code) {
2065 case lir_add: {
2066 __ incrementl(lreg, c);
2067 break;
2068 }
2069 case lir_sub: {
2070 __ decrementl(lreg, c);
2071 break;
2072 }
2073 default: ShouldNotReachHere();
2074 }
2075
2076 } else {
2077 ShouldNotReachHere();
2078 }
2079
2080 } else if (left->is_double_cpu()) {
2081 assert(left == dest, "left and dest must be equal");
2082 Register lreg_lo = left->as_register_lo();
2083 Register lreg_hi = left->as_register_hi();
2084
2085 if (right->is_double_cpu()) {
2086 // cpu register - cpu register
2087 Register rreg_lo = right->as_register_lo();
2088 Register rreg_hi = right->as_register_hi();
2089 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2090 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2091 switch (code) {
2092 case lir_add:
2093 __ addptr(lreg_lo, rreg_lo);
2094 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2095 break;
2096 case lir_sub:
2097 __ subptr(lreg_lo, rreg_lo);
2098 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2099 break;
2100 case lir_mul:
2101 #ifdef _LP64
2102 __ imulq(lreg_lo, rreg_lo);
2103 #else
2104 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2105 __ imull(lreg_hi, rreg_lo);
2106 __ imull(rreg_hi, lreg_lo);
2107 __ addl (rreg_hi, lreg_hi);
2108 __ mull (rreg_lo);
2109 __ addl (lreg_hi, rreg_hi);
2110 #endif // _LP64
2111 break;
2112 default:
2113 ShouldNotReachHere();
2114 }
2115
2116 } else if (right->is_constant()) {
2117 // cpu register - constant
2118 #ifdef _LP64
2119 jlong c = right->as_constant_ptr()->as_jlong_bits();
2120 __ movptr(r10, (intptr_t) c);
2121 switch (code) {
2122 case lir_add:
2123 __ addptr(lreg_lo, r10);
2124 break;
2125 case lir_sub:
2126 __ subptr(lreg_lo, r10);
2127 break;
2128 default:
2129 ShouldNotReachHere();
2130 }
2131 #else
2132 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2133 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2134 switch (code) {
2135 case lir_add:
2136 __ addptr(lreg_lo, c_lo);
2137 __ adcl(lreg_hi, c_hi);
2138 break;
2139 case lir_sub:
2140 __ subptr(lreg_lo, c_lo);
2141 __ sbbl(lreg_hi, c_hi);
2142 break;
2143 default:
2144 ShouldNotReachHere();
2145 }
2146 #endif // _LP64
2147
2148 } else {
2149 ShouldNotReachHere();
2150 }
2151
2152 } else if (left->is_single_xmm()) {
2153 assert(left == dest, "left and dest must be equal");
2154 XMMRegister lreg = left->as_xmm_float_reg();
2155
2156 if (right->is_single_xmm()) {
2157 XMMRegister rreg = right->as_xmm_float_reg();
2158 switch (code) {
2159 case lir_add: __ addss(lreg, rreg); break;
2160 case lir_sub: __ subss(lreg, rreg); break;
2161 case lir_mul: __ mulss(lreg, rreg); break;
2162 case lir_div: __ divss(lreg, rreg); break;
2163 default: ShouldNotReachHere();
2164 }
2165 } else {
2166 Address raddr;
2167 if (right->is_single_stack()) {
2168 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2169 } else if (right->is_constant()) {
2170 // hack for now
2171 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2172 } else {
2173 ShouldNotReachHere();
2174 }
2175 switch (code) {
2176 case lir_add: __ addss(lreg, raddr); break;
2177 case lir_sub: __ subss(lreg, raddr); break;
2178 case lir_mul: __ mulss(lreg, raddr); break;
2179 case lir_div: __ divss(lreg, raddr); break;
2180 default: ShouldNotReachHere();
2181 }
2182 }
2183
2184 } else if (left->is_double_xmm()) {
2185 assert(left == dest, "left and dest must be equal");
2186
2187 XMMRegister lreg = left->as_xmm_double_reg();
2188 if (right->is_double_xmm()) {
2189 XMMRegister rreg = right->as_xmm_double_reg();
2190 switch (code) {
2191 case lir_add: __ addsd(lreg, rreg); break;
2192 case lir_sub: __ subsd(lreg, rreg); break;
2193 case lir_mul: __ mulsd(lreg, rreg); break;
2194 case lir_div: __ divsd(lreg, rreg); break;
2195 default: ShouldNotReachHere();
2196 }
2197 } else {
2198 Address raddr;
2199 if (right->is_double_stack()) {
2200 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2201 } else if (right->is_constant()) {
2202 // hack for now
2203 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2204 } else {
2205 ShouldNotReachHere();
2206 }
2207 switch (code) {
2208 case lir_add: __ addsd(lreg, raddr); break;
2209 case lir_sub: __ subsd(lreg, raddr); break;
2210 case lir_mul: __ mulsd(lreg, raddr); break;
2211 case lir_div: __ divsd(lreg, raddr); break;
2212 default: ShouldNotReachHere();
2213 }
2214 }
2215
2216 #ifndef _LP64
2217 } else if (left->is_single_fpu()) {
2218 assert(dest->is_single_fpu(), "fpu stack allocation required");
2219
2220 if (right->is_single_fpu()) {
2221 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2222
2223 } else {
2224 assert(left->fpu_regnr() == 0, "left must be on TOS");
2225 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2226
2227 Address raddr;
2228 if (right->is_single_stack()) {
2229 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2230 } else if (right->is_constant()) {
2231 address const_addr = float_constant(right->as_jfloat());
2232 assert(const_addr != nullptr, "incorrect float/double constant maintenance");
2233 // hack for now
2234 raddr = __ as_Address(InternalAddress(const_addr));
2235 } else {
2236 ShouldNotReachHere();
2237 }
2238
2239 switch (code) {
2240 case lir_add: __ fadd_s(raddr); break;
2241 case lir_sub: __ fsub_s(raddr); break;
2242 case lir_mul: __ fmul_s(raddr); break;
2243 case lir_div: __ fdiv_s(raddr); break;
2244 default: ShouldNotReachHere();
2245 }
2246 }
2247
2248 } else if (left->is_double_fpu()) {
2249 assert(dest->is_double_fpu(), "fpu stack allocation required");
2250
2251 if (code == lir_mul || code == lir_div) {
2252 // Double values require special handling for strictfp mul/div on x86
2253 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1()));
2254 __ fmulp(left->fpu_regnrLo() + 1);
2255 }
2256
2257 if (right->is_double_fpu()) {
2258 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2259
2260 } else {
2261 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2262 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2263
2264 Address raddr;
2265 if (right->is_double_stack()) {
2266 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2267 } else if (right->is_constant()) {
2268 // hack for now
2269 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2270 } else {
2271 ShouldNotReachHere();
2272 }
2273
2274 switch (code) {
2275 case lir_add: __ fadd_d(raddr); break;
2276 case lir_sub: __ fsub_d(raddr); break;
2277 case lir_mul: __ fmul_d(raddr); break;
2278 case lir_div: __ fdiv_d(raddr); break;
2279 default: ShouldNotReachHere();
2280 }
2281 }
2282
2283 if (code == lir_mul || code == lir_div) {
2284 // Double values require special handling for strictfp mul/div on x86
2285 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2()));
2286 __ fmulp(dest->fpu_regnrLo() + 1);
2287 }
2288 #endif // !_LP64
2289
2290 } else if (left->is_single_stack() || left->is_address()) {
2291 assert(left == dest, "left and dest must be equal");
2292
2293 Address laddr;
2294 if (left->is_single_stack()) {
2295 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2296 } else if (left->is_address()) {
2297 laddr = as_Address(left->as_address_ptr());
2298 } else {
2299 ShouldNotReachHere();
2300 }
2301
2302 if (right->is_single_cpu()) {
2303 Register rreg = right->as_register();
2304 switch (code) {
2305 case lir_add: __ addl(laddr, rreg); break;
2306 case lir_sub: __ subl(laddr, rreg); break;
2307 default: ShouldNotReachHere();
2308 }
2309 } else if (right->is_constant()) {
2310 jint c = right->as_constant_ptr()->as_jint();
2311 switch (code) {
2312 case lir_add: {
2313 __ incrementl(laddr, c);
2314 break;
2315 }
2316 case lir_sub: {
2317 __ decrementl(laddr, c);
2318 break;
2319 }
2320 default: ShouldNotReachHere();
2321 }
2322 } else {
2323 ShouldNotReachHere();
2324 }
2325
2326 } else {
2327 ShouldNotReachHere();
2328 }
2329 }
2330
2331 #ifndef _LP64
2332 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2333 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2334 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2335 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2336
2337 bool left_is_tos = (left_index == 0);
2338 bool dest_is_tos = (dest_index == 0);
2339 int non_tos_index = (left_is_tos ? right_index : left_index);
2340
2341 switch (code) {
2342 case lir_add:
2343 if (pop_fpu_stack) __ faddp(non_tos_index);
2344 else if (dest_is_tos) __ fadd (non_tos_index);
2345 else __ fadda(non_tos_index);
2346 break;
2347
2348 case lir_sub:
2349 if (left_is_tos) {
2350 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2351 else if (dest_is_tos) __ fsub (non_tos_index);
2352 else __ fsubra(non_tos_index);
2353 } else {
2354 if (pop_fpu_stack) __ fsubp (non_tos_index);
2355 else if (dest_is_tos) __ fsubr (non_tos_index);
2356 else __ fsuba (non_tos_index);
2357 }
2358 break;
2359
2360 case lir_mul:
2361 if (pop_fpu_stack) __ fmulp(non_tos_index);
2362 else if (dest_is_tos) __ fmul (non_tos_index);
2363 else __ fmula(non_tos_index);
2364 break;
2365
2366 case lir_div:
2367 if (left_is_tos) {
2368 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2369 else if (dest_is_tos) __ fdiv (non_tos_index);
2370 else __ fdivra(non_tos_index);
2371 } else {
2372 if (pop_fpu_stack) __ fdivp (non_tos_index);
2373 else if (dest_is_tos) __ fdivr (non_tos_index);
2374 else __ fdiva (non_tos_index);
2375 }
2376 break;
2377
2378 case lir_rem:
2379 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2380 __ fremr(noreg);
2381 break;
2382
2383 default:
2384 ShouldNotReachHere();
2385 }
2386 }
2387 #endif // _LP64
2388
2389
2390 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2391 if (value->is_double_xmm()) {
2392 switch(code) {
2393 case lir_abs :
2394 {
2395 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2396 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2397 }
2398 assert(!tmp->is_valid(), "do not need temporary");
2399 __ andpd(dest->as_xmm_double_reg(),
2400 ExternalAddress((address)double_signmask_pool),
2401 rscratch1);
2402 }
2403 break;
2404
2405 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2406 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2407 default : ShouldNotReachHere();
2408 }
2409
2410 #ifndef _LP64
2411 } else if (value->is_double_fpu()) {
2412 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2413 switch(code) {
2414 case lir_abs : __ fabs() ; break;
2415 case lir_sqrt : __ fsqrt(); break;
2416 default : ShouldNotReachHere();
2417 }
2418 #endif // !_LP64
2419 } else if (code == lir_f2hf) {
2420 __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg());
2421 } else if (code == lir_hf2f) {
2422 __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register());
2423 } else {
2424 Unimplemented();
2425 }
2426 }
2427
2428 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2429 // assert(left->destroys_register(), "check");
2430 if (left->is_single_cpu()) {
2431 Register reg = left->as_register();
2432 if (right->is_constant()) {
2433 int val = right->as_constant_ptr()->as_jint();
2434 switch (code) {
2435 case lir_logic_and: __ andl (reg, val); break;
2436 case lir_logic_or: __ orl (reg, val); break;
2437 case lir_logic_xor: __ xorl (reg, val); break;
2438 default: ShouldNotReachHere();
2439 }
2440 } else if (right->is_stack()) {
2441 // added support for stack operands
2442 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2443 switch (code) {
2444 case lir_logic_and: __ andl (reg, raddr); break;
2445 case lir_logic_or: __ orl (reg, raddr); break;
2446 case lir_logic_xor: __ xorl (reg, raddr); break;
2447 default: ShouldNotReachHere();
2448 }
2449 } else {
2450 Register rright = right->as_register();
2451 switch (code) {
2452 case lir_logic_and: __ andptr (reg, rright); break;
2453 case lir_logic_or : __ orptr (reg, rright); break;
2454 case lir_logic_xor: __ xorptr (reg, rright); break;
2455 default: ShouldNotReachHere();
2456 }
2457 }
2458 move_regs(reg, dst->as_register());
2459 } else {
2460 Register l_lo = left->as_register_lo();
2461 Register l_hi = left->as_register_hi();
2462 if (right->is_constant()) {
2463 #ifdef _LP64
2464 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2465 switch (code) {
2466 case lir_logic_and:
2467 __ andq(l_lo, rscratch1);
2468 break;
2469 case lir_logic_or:
2470 __ orq(l_lo, rscratch1);
2471 break;
2472 case lir_logic_xor:
2473 __ xorq(l_lo, rscratch1);
2474 break;
2475 default: ShouldNotReachHere();
2476 }
2477 #else
2478 int r_lo = right->as_constant_ptr()->as_jint_lo();
2479 int r_hi = right->as_constant_ptr()->as_jint_hi();
2480 switch (code) {
2481 case lir_logic_and:
2482 __ andl(l_lo, r_lo);
2483 __ andl(l_hi, r_hi);
2484 break;
2485 case lir_logic_or:
2486 __ orl(l_lo, r_lo);
2487 __ orl(l_hi, r_hi);
2488 break;
2489 case lir_logic_xor:
2490 __ xorl(l_lo, r_lo);
2491 __ xorl(l_hi, r_hi);
2492 break;
2493 default: ShouldNotReachHere();
2494 }
2495 #endif // _LP64
2496 } else {
2497 #ifdef _LP64
2498 Register r_lo;
2499 if (is_reference_type(right->type())) {
2500 r_lo = right->as_register();
2501 } else {
2502 r_lo = right->as_register_lo();
2503 }
2504 #else
2505 Register r_lo = right->as_register_lo();
2506 Register r_hi = right->as_register_hi();
2507 assert(l_lo != r_hi, "overwriting registers");
2508 #endif
2509 switch (code) {
2510 case lir_logic_and:
2511 __ andptr(l_lo, r_lo);
2512 NOT_LP64(__ andptr(l_hi, r_hi);)
2513 break;
2514 case lir_logic_or:
2515 __ orptr(l_lo, r_lo);
2516 NOT_LP64(__ orptr(l_hi, r_hi);)
2517 break;
2518 case lir_logic_xor:
2519 __ xorptr(l_lo, r_lo);
2520 NOT_LP64(__ xorptr(l_hi, r_hi);)
2521 break;
2522 default: ShouldNotReachHere();
2523 }
2524 }
2525
2526 Register dst_lo = dst->as_register_lo();
2527 Register dst_hi = dst->as_register_hi();
2528
2529 #ifdef _LP64
2530 move_regs(l_lo, dst_lo);
2531 #else
2532 if (dst_lo == l_hi) {
2533 assert(dst_hi != l_lo, "overwriting registers");
2534 move_regs(l_hi, dst_hi);
2535 move_regs(l_lo, dst_lo);
2536 } else {
2537 assert(dst_lo != l_hi, "overwriting registers");
2538 move_regs(l_lo, dst_lo);
2539 move_regs(l_hi, dst_hi);
2540 }
2541 #endif // _LP64
2542 }
2543 }
2544
2545
2546 // we assume that rax, and rdx can be overwritten
2547 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2548
2549 assert(left->is_single_cpu(), "left must be register");
2550 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2551 assert(result->is_single_cpu(), "result must be register");
2552
2553 // assert(left->destroys_register(), "check");
2554 // assert(right->destroys_register(), "check");
2555
2556 Register lreg = left->as_register();
2557 Register dreg = result->as_register();
2558
2559 if (right->is_constant()) {
2560 jint divisor = right->as_constant_ptr()->as_jint();
2561 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2562 if (code == lir_idiv) {
2563 assert(lreg == rax, "must be rax,");
2564 assert(temp->as_register() == rdx, "tmp register must be rdx");
2565 __ cdql(); // sign extend into rdx:rax
2566 if (divisor == 2) {
2567 __ subl(lreg, rdx);
2568 } else {
2569 __ andl(rdx, divisor - 1);
2570 __ addl(lreg, rdx);
2571 }
2572 __ sarl(lreg, log2i_exact(divisor));
2573 move_regs(lreg, dreg);
2574 } else if (code == lir_irem) {
2575 Label done;
2576 __ mov(dreg, lreg);
2577 __ andl(dreg, 0x80000000 | (divisor - 1));
2578 __ jcc(Assembler::positive, done);
2579 __ decrement(dreg);
2580 __ orl(dreg, ~(divisor - 1));
2581 __ increment(dreg);
2582 __ bind(done);
2583 } else {
2584 ShouldNotReachHere();
2585 }
2586 } else {
2587 Register rreg = right->as_register();
2588 assert(lreg == rax, "left register must be rax,");
2589 assert(rreg != rdx, "right register must not be rdx");
2590 assert(temp->as_register() == rdx, "tmp register must be rdx");
2591
2592 move_regs(lreg, rax);
2593
2594 int idivl_offset = __ corrected_idivl(rreg);
2595 if (ImplicitDiv0Checks) {
2596 add_debug_info_for_div0(idivl_offset, info);
2597 }
2598 if (code == lir_irem) {
2599 move_regs(rdx, dreg); // result is in rdx
2600 } else {
2601 move_regs(rax, dreg);
2602 }
2603 }
2604 }
2605
2606
2607 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2608 if (opr1->is_single_cpu()) {
2609 Register reg1 = opr1->as_register();
2610 if (opr2->is_single_cpu()) {
2611 // cpu register - cpu register
2612 if (is_reference_type(opr1->type())) {
2613 __ cmpoop(reg1, opr2->as_register());
2614 } else {
2615 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2616 __ cmpl(reg1, opr2->as_register());
2617 }
2618 } else if (opr2->is_stack()) {
2619 // cpu register - stack
2620 if (is_reference_type(opr1->type())) {
2621 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2622 } else {
2623 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2624 }
2625 } else if (opr2->is_constant()) {
2626 // cpu register - constant
2627 LIR_Const* c = opr2->as_constant_ptr();
2628 if (c->type() == T_INT) {
2629 jint i = c->as_jint();
2630 if (i == 0) {
2631 __ testl(reg1, reg1);
2632 } else {
2633 __ cmpl(reg1, i);
2634 }
2635 } else if (c->type() == T_METADATA) {
2636 // All we need for now is a comparison with null for equality.
2637 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2638 Metadata* m = c->as_metadata();
2639 if (m == nullptr) {
2640 __ testptr(reg1, reg1);
2641 } else {
2642 ShouldNotReachHere();
2643 }
2644 } else if (is_reference_type(c->type())) {
2645 // In 64bit oops are single register
2646 jobject o = c->as_jobject();
2647 if (o == nullptr) {
2648 __ testptr(reg1, reg1);
2649 } else {
2650 __ cmpoop(reg1, o, rscratch1);
2651 }
2652 } else {
2653 fatal("unexpected type: %s", basictype_to_str(c->type()));
2654 }
2655 // cpu register - address
2656 } else if (opr2->is_address()) {
2657 if (op->info() != nullptr) {
2658 add_debug_info_for_null_check_here(op->info());
2659 }
2660 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2661 } else {
2662 ShouldNotReachHere();
2663 }
2664
2665 } else if(opr1->is_double_cpu()) {
2666 Register xlo = opr1->as_register_lo();
2667 Register xhi = opr1->as_register_hi();
2668 if (opr2->is_double_cpu()) {
2669 #ifdef _LP64
2670 __ cmpptr(xlo, opr2->as_register_lo());
2671 #else
2672 // cpu register - cpu register
2673 Register ylo = opr2->as_register_lo();
2674 Register yhi = opr2->as_register_hi();
2675 __ subl(xlo, ylo);
2676 __ sbbl(xhi, yhi);
2677 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2678 __ orl(xhi, xlo);
2679 }
2680 #endif // _LP64
2681 } else if (opr2->is_constant()) {
2682 // cpu register - constant 0
2683 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2684 #ifdef _LP64
2685 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2686 #else
2687 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2688 __ orl(xhi, xlo);
2689 #endif // _LP64
2690 } else {
2691 ShouldNotReachHere();
2692 }
2693
2694 } else if (opr1->is_single_xmm()) {
2695 XMMRegister reg1 = opr1->as_xmm_float_reg();
2696 if (opr2->is_single_xmm()) {
2697 // xmm register - xmm register
2698 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2699 } else if (opr2->is_stack()) {
2700 // xmm register - stack
2701 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2702 } else if (opr2->is_constant()) {
2703 // xmm register - constant
2704 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2705 } else if (opr2->is_address()) {
2706 // xmm register - address
2707 if (op->info() != nullptr) {
2708 add_debug_info_for_null_check_here(op->info());
2709 }
2710 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2711 } else {
2712 ShouldNotReachHere();
2713 }
2714
2715 } else if (opr1->is_double_xmm()) {
2716 XMMRegister reg1 = opr1->as_xmm_double_reg();
2717 if (opr2->is_double_xmm()) {
2718 // xmm register - xmm register
2719 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2720 } else if (opr2->is_stack()) {
2721 // xmm register - stack
2722 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2723 } else if (opr2->is_constant()) {
2724 // xmm register - constant
2725 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2726 } else if (opr2->is_address()) {
2727 // xmm register - address
2728 if (op->info() != nullptr) {
2729 add_debug_info_for_null_check_here(op->info());
2730 }
2731 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2732 } else {
2733 ShouldNotReachHere();
2734 }
2735
2736 #ifndef _LP64
2737 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2738 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2739 assert(opr2->is_fpu_register(), "both must be registers");
2740 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2741 #endif // LP64
2742
2743 } else if (opr1->is_address() && opr2->is_constant()) {
2744 LIR_Const* c = opr2->as_constant_ptr();
2745 #ifdef _LP64
2746 if (is_reference_type(c->type())) {
2747 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2748 __ movoop(rscratch1, c->as_jobject());
2749 }
2750 #endif // LP64
2751 if (op->info() != nullptr) {
2752 add_debug_info_for_null_check_here(op->info());
2753 }
2754 // special case: address - constant
2755 LIR_Address* addr = opr1->as_address_ptr();
2756 if (c->type() == T_INT) {
2757 __ cmpl(as_Address(addr), c->as_jint());
2758 } else if (is_reference_type(c->type())) {
2759 #ifdef _LP64
2760 // %%% Make this explode if addr isn't reachable until we figure out a
2761 // better strategy by giving noreg as the temp for as_Address
2762 __ cmpoop(rscratch1, as_Address(addr, noreg));
2763 #else
2764 __ cmpoop(as_Address(addr), c->as_jobject());
2765 #endif // _LP64
2766 } else {
2767 ShouldNotReachHere();
2768 }
2769
2770 } else {
2771 ShouldNotReachHere();
2772 }
2773 }
2774
2775 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2776 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2777 if (left->is_single_xmm()) {
2778 assert(right->is_single_xmm(), "must match");
2779 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2780 } else if (left->is_double_xmm()) {
2781 assert(right->is_double_xmm(), "must match");
2782 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2783
2784 } else {
2785 #ifdef _LP64
2786 ShouldNotReachHere();
2787 #else
2788 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2789 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2790
2791 assert(left->fpu() == 0, "left must be on TOS");
2792 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2793 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2794 #endif // LP64
2795 }
2796 } else {
2797 assert(code == lir_cmp_l2i, "check");
2798 #ifdef _LP64
2799 Label done;
2800 Register dest = dst->as_register();
2801 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2802 __ movl(dest, -1);
2803 __ jccb(Assembler::less, done);
2804 __ setb(Assembler::notZero, dest);
2805 __ movzbl(dest, dest);
2806 __ bind(done);
2807 #else
2808 __ lcmp2int(left->as_register_hi(),
2809 left->as_register_lo(),
2810 right->as_register_hi(),
2811 right->as_register_lo());
2812 move_regs(left->as_register_hi(), dst->as_register());
2813 #endif // _LP64
2814 }
2815 }
2816
2817
2818 void LIR_Assembler::align_call(LIR_Code code) {
2819 // make sure that the displacement word of the call ends up word aligned
2820 int offset = __ offset();
2821 switch (code) {
2822 case lir_static_call:
2823 case lir_optvirtual_call:
2824 case lir_dynamic_call:
2825 offset += NativeCall::displacement_offset;
2826 break;
2827 case lir_icvirtual_call:
2828 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size_rex;
2829 break;
2830 default: ShouldNotReachHere();
2831 }
2832 __ align(BytesPerWord, offset);
2833 }
2834
2835
2836 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2837 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2838 "must be aligned");
2839 __ call(AddressLiteral(op->addr(), rtype));
2840 add_call_info(code_offset(), op->info());
2841 __ post_call_nop();
2842 }
2843
2844
2845 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2846 __ ic_call(op->addr());
2847 add_call_info(code_offset(), op->info());
2848 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2849 "must be aligned");
2850 __ post_call_nop();
2851 }
2852
2853
2854 void LIR_Assembler::emit_static_call_stub() {
2855 address call_pc = __ pc();
2856 address stub = __ start_a_stub(call_stub_size());
2857 if (stub == nullptr) {
2858 bailout("static call stub overflow");
2859 return;
2860 }
2861
2862 int start = __ offset();
2863
2864 // make sure that the displacement word of the call ends up word aligned
2865 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size_rex + NativeCall::displacement_offset);
2866 __ relocate(static_stub_Relocation::spec(call_pc));
2867 __ mov_metadata(rbx, (Metadata*)nullptr);
2868 // must be set to -1 at code generation time
2869 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2870 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2871 __ jump(RuntimeAddress(__ pc()));
2872
2873 assert(__ offset() - start <= call_stub_size(), "stub too big");
2874 __ end_a_stub();
2875 }
2876
2877
2878 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2879 assert(exceptionOop->as_register() == rax, "must match");
2880 assert(exceptionPC->as_register() == rdx, "must match");
2881
2882 // exception object is not added to oop map by LinearScan
2883 // (LinearScan assumes that no oops are in fixed registers)
2884 info->add_register_oop(exceptionOop);
2885 C1StubId unwind_id;
2886
2887 // get current pc information
2888 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2889 int pc_for_athrow_offset = __ offset();
2890 InternalAddress pc_for_athrow(__ pc());
2891 __ lea(exceptionPC->as_register(), pc_for_athrow);
2892 add_call_info(pc_for_athrow_offset, info); // for exception handler
2893
2894 __ verify_not_null_oop(rax);
2895 // search an exception handler (rax: exception oop, rdx: throwing pc)
2896 if (compilation()->has_fpu_code()) {
2897 unwind_id = C1StubId::handle_exception_id;
2898 } else {
2899 unwind_id = C1StubId::handle_exception_nofpu_id;
2900 }
2901 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2902
2903 // enough room for two byte trap
2904 __ nop();
2905 }
2906
2907
2908 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2909 assert(exceptionOop->as_register() == rax, "must match");
2910
2911 __ jmp(_unwind_handler_entry);
2912 }
2913
2914
2915 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2916
2917 // optimized version for linear scan:
2918 // * count must be already in ECX (guaranteed by LinearScan)
2919 // * left and dest must be equal
2920 // * tmp must be unused
2921 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2922 assert(left == dest, "left and dest must be equal");
2923 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2924
2925 if (left->is_single_cpu()) {
2926 Register value = left->as_register();
2927 assert(value != SHIFT_count, "left cannot be ECX");
2928
2929 switch (code) {
2930 case lir_shl: __ shll(value); break;
2931 case lir_shr: __ sarl(value); break;
2932 case lir_ushr: __ shrl(value); break;
2933 default: ShouldNotReachHere();
2934 }
2935 } else if (left->is_double_cpu()) {
2936 Register lo = left->as_register_lo();
2937 Register hi = left->as_register_hi();
2938 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2939 #ifdef _LP64
2940 switch (code) {
2941 case lir_shl: __ shlptr(lo); break;
2942 case lir_shr: __ sarptr(lo); break;
2943 case lir_ushr: __ shrptr(lo); break;
2944 default: ShouldNotReachHere();
2945 }
2946 #else
2947
2948 switch (code) {
2949 case lir_shl: __ lshl(hi, lo); break;
2950 case lir_shr: __ lshr(hi, lo, true); break;
2951 case lir_ushr: __ lshr(hi, lo, false); break;
2952 default: ShouldNotReachHere();
2953 }
2954 #endif // LP64
2955 } else {
2956 ShouldNotReachHere();
2957 }
2958 }
2959
2960
2961 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2962 if (dest->is_single_cpu()) {
2963 // first move left into dest so that left is not destroyed by the shift
2964 Register value = dest->as_register();
2965 count = count & 0x1F; // Java spec
2966
2967 move_regs(left->as_register(), value);
2968 switch (code) {
2969 case lir_shl: __ shll(value, count); break;
2970 case lir_shr: __ sarl(value, count); break;
2971 case lir_ushr: __ shrl(value, count); break;
2972 default: ShouldNotReachHere();
2973 }
2974 } else if (dest->is_double_cpu()) {
2975 #ifndef _LP64
2976 Unimplemented();
2977 #else
2978 // first move left into dest so that left is not destroyed by the shift
2979 Register value = dest->as_register_lo();
2980 count = count & 0x1F; // Java spec
2981
2982 move_regs(left->as_register_lo(), value);
2983 switch (code) {
2984 case lir_shl: __ shlptr(value, count); break;
2985 case lir_shr: __ sarptr(value, count); break;
2986 case lir_ushr: __ shrptr(value, count); break;
2987 default: ShouldNotReachHere();
2988 }
2989 #endif // _LP64
2990 } else {
2991 ShouldNotReachHere();
2992 }
2993 }
2994
2995
2996 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2997 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2998 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2999 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3000 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3001 }
3002
3003
3004 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3005 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3006 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3007 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3008 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3009 }
3010
3011
3012 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3013 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3014 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3015 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3016 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1);
3017 }
3018
3019
3020 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3021 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3022 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3023 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3024 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1);
3025 }
3026
3027
3028 // This code replaces a call to arraycopy; no exception may
3029 // be thrown in this code, they must be thrown in the System.arraycopy
3030 // activation frame; we could save some checks if this would not be the case
3031 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3032 ciArrayKlass* default_type = op->expected_type();
3033 Register src = op->src()->as_register();
3034 Register dst = op->dst()->as_register();
3035 Register src_pos = op->src_pos()->as_register();
3036 Register dst_pos = op->dst_pos()->as_register();
3037 Register length = op->length()->as_register();
3038 Register tmp = op->tmp()->as_register();
3039 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3040 Register tmp2 = UseCompactObjectHeaders ? rscratch2 : noreg;
3041
3042 CodeStub* stub = op->stub();
3043 int flags = op->flags();
3044 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
3045 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3046
3047 // if we don't know anything, just go through the generic arraycopy
3048 if (default_type == nullptr) {
3049 // save outgoing arguments on stack in case call to System.arraycopy is needed
3050 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3051 // for interpreter calling conventions. Now we have to do it in new style conventions.
3052 // For the moment until C1 gets the new register allocator I just force all the
3053 // args to the right place (except the register args) and then on the back side
3054 // reload the register args properly if we go slow path. Yuck
3055
3056 // These are proper for the calling convention
3057 store_parameter(length, 2);
3058 store_parameter(dst_pos, 1);
3059 store_parameter(dst, 0);
3060
3061 // these are just temporary placements until we need to reload
3062 store_parameter(src_pos, 3);
3063 store_parameter(src, 4);
3064 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3065
3066 address copyfunc_addr = StubRoutines::generic_arraycopy();
3067 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
3068
3069 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3070 #ifdef _LP64
3071 // The arguments are in java calling convention so we can trivially shift them to C
3072 // convention
3073 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3074 __ mov(c_rarg0, j_rarg0);
3075 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3076 __ mov(c_rarg1, j_rarg1);
3077 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3078 __ mov(c_rarg2, j_rarg2);
3079 assert_different_registers(c_rarg3, j_rarg4);
3080 __ mov(c_rarg3, j_rarg3);
3081 #ifdef _WIN64
3082 // Allocate abi space for args but be sure to keep stack aligned
3083 __ subptr(rsp, 6*wordSize);
3084 store_parameter(j_rarg4, 4);
3085 #ifndef PRODUCT
3086 if (PrintC1Statistics) {
3087 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3088 }
3089 #endif
3090 __ call(RuntimeAddress(copyfunc_addr));
3091 __ addptr(rsp, 6*wordSize);
3092 #else
3093 __ mov(c_rarg4, j_rarg4);
3094 #ifndef PRODUCT
3095 if (PrintC1Statistics) {
3096 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3097 }
3098 #endif
3099 __ call(RuntimeAddress(copyfunc_addr));
3100 #endif // _WIN64
3101 #else
3102 __ push(length);
3103 __ push(dst_pos);
3104 __ push(dst);
3105 __ push(src_pos);
3106 __ push(src);
3107
3108 #ifndef PRODUCT
3109 if (PrintC1Statistics) {
3110 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3111 }
3112 #endif
3113 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3114
3115 #endif // _LP64
3116
3117 __ testl(rax, rax);
3118 __ jcc(Assembler::equal, *stub->continuation());
3119
3120 __ mov(tmp, rax);
3121 __ xorl(tmp, -1);
3122
3123 // Reload values from the stack so they are where the stub
3124 // expects them.
3125 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3126 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3127 __ movptr (length, Address(rsp, 2*BytesPerWord));
3128 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3129 __ movptr (src, Address(rsp, 4*BytesPerWord));
3130
3131 __ subl(length, tmp);
3132 __ addl(src_pos, tmp);
3133 __ addl(dst_pos, tmp);
3134 __ jmp(*stub->entry());
3135
3136 __ bind(*stub->continuation());
3137 return;
3138 }
3139
3140 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3141
3142 int elem_size = type2aelembytes(basic_type);
3143 Address::ScaleFactor scale;
3144
3145 switch (elem_size) {
3146 case 1 :
3147 scale = Address::times_1;
3148 break;
3149 case 2 :
3150 scale = Address::times_2;
3151 break;
3152 case 4 :
3153 scale = Address::times_4;
3154 break;
3155 case 8 :
3156 scale = Address::times_8;
3157 break;
3158 default:
3159 scale = Address::no_scale;
3160 ShouldNotReachHere();
3161 }
3162
3163 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3164 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3165
3166 // length and pos's are all sign extended at this point on 64bit
3167
3168 // test for null
3169 if (flags & LIR_OpArrayCopy::src_null_check) {
3170 __ testptr(src, src);
3171 __ jcc(Assembler::zero, *stub->entry());
3172 }
3173 if (flags & LIR_OpArrayCopy::dst_null_check) {
3174 __ testptr(dst, dst);
3175 __ jcc(Assembler::zero, *stub->entry());
3176 }
3177
3178 // If the compiler was not able to prove that exact type of the source or the destination
3179 // of the arraycopy is an array type, check at runtime if the source or the destination is
3180 // an instance type.
3181 if (flags & LIR_OpArrayCopy::type_check) {
3182 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3183 __ load_klass(tmp, dst, tmp_load_klass);
3184 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3185 __ jcc(Assembler::greaterEqual, *stub->entry());
3186 }
3187
3188 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3189 __ load_klass(tmp, src, tmp_load_klass);
3190 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3191 __ jcc(Assembler::greaterEqual, *stub->entry());
3192 }
3193 }
3194
3195 // check if negative
3196 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3197 __ testl(src_pos, src_pos);
3198 __ jcc(Assembler::less, *stub->entry());
3199 }
3200 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3201 __ testl(dst_pos, dst_pos);
3202 __ jcc(Assembler::less, *stub->entry());
3203 }
3204
3205 if (flags & LIR_OpArrayCopy::src_range_check) {
3206 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3207 __ cmpl(tmp, src_length_addr);
3208 __ jcc(Assembler::above, *stub->entry());
3209 }
3210 if (flags & LIR_OpArrayCopy::dst_range_check) {
3211 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3212 __ cmpl(tmp, dst_length_addr);
3213 __ jcc(Assembler::above, *stub->entry());
3214 }
3215
3216 if (flags & LIR_OpArrayCopy::length_positive_check) {
3217 __ testl(length, length);
3218 __ jcc(Assembler::less, *stub->entry());
3219 }
3220
3221 #ifdef _LP64
3222 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3223 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3224 #endif
3225
3226 if (flags & LIR_OpArrayCopy::type_check) {
3227 // We don't know the array types are compatible
3228 if (basic_type != T_OBJECT) {
3229 // Simple test for basic type arrays
3230 __ cmp_klasses_from_objects(src, dst, tmp, tmp2);
3231 __ jcc(Assembler::notEqual, *stub->entry());
3232 } else {
3233 // For object arrays, if src is a sub class of dst then we can
3234 // safely do the copy.
3235 Label cont, slow;
3236
3237 __ push(src);
3238 __ push(dst);
3239
3240 __ load_klass(src, src, tmp_load_klass);
3241 __ load_klass(dst, dst, tmp_load_klass);
3242
3243 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
3244
3245 __ push(src);
3246 __ push(dst);
3247 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
3248 __ pop(dst);
3249 __ pop(src);
3250
3251 __ testl(src, src);
3252 __ jcc(Assembler::notEqual, cont);
3253
3254 __ bind(slow);
3255 __ pop(dst);
3256 __ pop(src);
3257
3258 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3259 if (copyfunc_addr != nullptr) { // use stub if available
3260 // src is not a sub class of dst so we have to do a
3261 // per-element check.
3262
3263 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3264 if ((flags & mask) != mask) {
3265 // Check that at least both of them object arrays.
3266 assert(flags & mask, "one of the two should be known to be an object array");
3267
3268 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3269 __ load_klass(tmp, src, tmp_load_klass);
3270 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3271 __ load_klass(tmp, dst, tmp_load_klass);
3272 }
3273 int lh_offset = in_bytes(Klass::layout_helper_offset());
3274 Address klass_lh_addr(tmp, lh_offset);
3275 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3276 __ cmpl(klass_lh_addr, objArray_lh);
3277 __ jcc(Assembler::notEqual, *stub->entry());
3278 }
3279
3280 // Spill because stubs can use any register they like and it's
3281 // easier to restore just those that we care about.
3282 store_parameter(dst, 0);
3283 store_parameter(dst_pos, 1);
3284 store_parameter(length, 2);
3285 store_parameter(src_pos, 3);
3286 store_parameter(src, 4);
3287
3288 #ifndef _LP64
3289 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3290 __ movptr(tmp, dst_klass_addr);
3291 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3292 __ push(tmp);
3293 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3294 __ push(tmp);
3295 __ push(length);
3296 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3297 __ push(tmp);
3298 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3299 __ push(tmp);
3300
3301 __ call_VM_leaf(copyfunc_addr, 5);
3302 #else
3303 __ movl2ptr(length, length); //higher 32bits must be null
3304
3305 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3306 assert_different_registers(c_rarg0, dst, dst_pos, length);
3307 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3308 assert_different_registers(c_rarg1, dst, length);
3309
3310 __ mov(c_rarg2, length);
3311 assert_different_registers(c_rarg2, dst);
3312
3313 #ifdef _WIN64
3314 // Allocate abi space for args but be sure to keep stack aligned
3315 __ subptr(rsp, 6*wordSize);
3316 __ load_klass(c_rarg3, dst, tmp_load_klass);
3317 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3318 store_parameter(c_rarg3, 4);
3319 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3320 __ call(RuntimeAddress(copyfunc_addr));
3321 __ addptr(rsp, 6*wordSize);
3322 #else
3323 __ load_klass(c_rarg4, dst, tmp_load_klass);
3324 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3325 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3326 __ call(RuntimeAddress(copyfunc_addr));
3327 #endif
3328
3329 #endif
3330
3331 #ifndef PRODUCT
3332 if (PrintC1Statistics) {
3333 Label failed;
3334 __ testl(rax, rax);
3335 __ jcc(Assembler::notZero, failed);
3336 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1);
3337 __ bind(failed);
3338 }
3339 #endif
3340
3341 __ testl(rax, rax);
3342 __ jcc(Assembler::zero, *stub->continuation());
3343
3344 #ifndef PRODUCT
3345 if (PrintC1Statistics) {
3346 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1);
3347 }
3348 #endif
3349
3350 __ mov(tmp, rax);
3351
3352 __ xorl(tmp, -1);
3353
3354 // Restore previously spilled arguments
3355 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3356 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3357 __ movptr (length, Address(rsp, 2*BytesPerWord));
3358 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3359 __ movptr (src, Address(rsp, 4*BytesPerWord));
3360
3361
3362 __ subl(length, tmp);
3363 __ addl(src_pos, tmp);
3364 __ addl(dst_pos, tmp);
3365 }
3366
3367 __ jmp(*stub->entry());
3368
3369 __ bind(cont);
3370 __ pop(dst);
3371 __ pop(src);
3372 }
3373 }
3374
3375 #ifdef ASSERT
3376 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3377 // Sanity check the known type with the incoming class. For the
3378 // primitive case the types must match exactly with src.klass and
3379 // dst.klass each exactly matching the default type. For the
3380 // object array case, if no type check is needed then either the
3381 // dst type is exactly the expected type and the src type is a
3382 // subtype which we can't check or src is the same array as dst
3383 // but not necessarily exactly of type default_type.
3384 Label known_ok, halt;
3385 __ mov_metadata(tmp, default_type->constant_encoding());
3386 #ifdef _LP64
3387 if (UseCompressedClassPointers) {
3388 __ encode_klass_not_null(tmp, rscratch1);
3389 }
3390 #endif
3391
3392 if (basic_type != T_OBJECT) {
3393 __ cmp_klass(tmp, dst, tmp2);
3394 __ jcc(Assembler::notEqual, halt);
3395 __ cmp_klass(tmp, src, tmp2);
3396 __ jcc(Assembler::equal, known_ok);
3397 } else {
3398 __ cmp_klass(tmp, dst, tmp2);
3399 __ jcc(Assembler::equal, known_ok);
3400 __ cmpptr(src, dst);
3401 __ jcc(Assembler::equal, known_ok);
3402 }
3403 __ bind(halt);
3404 __ stop("incorrect type information in arraycopy");
3405 __ bind(known_ok);
3406 }
3407 #endif
3408
3409 #ifndef PRODUCT
3410 if (PrintC1Statistics) {
3411 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1);
3412 }
3413 #endif
3414
3415 #ifdef _LP64
3416 assert_different_registers(c_rarg0, dst, dst_pos, length);
3417 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3418 assert_different_registers(c_rarg1, length);
3419 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3420 __ mov(c_rarg2, length);
3421
3422 #else
3423 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3424 store_parameter(tmp, 0);
3425 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3426 store_parameter(tmp, 1);
3427 store_parameter(length, 2);
3428 #endif // _LP64
3429
3430 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3431 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3432 const char *name;
3433 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3434 __ call_VM_leaf(entry, 0);
3435
3436 if (stub != nullptr) {
3437 __ bind(*stub->continuation());
3438 }
3439 }
3440
3441 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3442 assert(op->crc()->is_single_cpu(), "crc must be register");
3443 assert(op->val()->is_single_cpu(), "byte value must be register");
3444 assert(op->result_opr()->is_single_cpu(), "result must be register");
3445 Register crc = op->crc()->as_register();
3446 Register val = op->val()->as_register();
3447 Register res = op->result_opr()->as_register();
3448
3449 assert_different_registers(val, crc, res);
3450
3451 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3452 __ notl(crc); // ~crc
3453 __ update_byte_crc32(crc, val, res);
3454 __ notl(crc); // ~crc
3455 __ mov(res, crc);
3456 }
3457
3458 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3459 Register obj = op->obj_opr()->as_register(); // may not be an oop
3460 Register hdr = op->hdr_opr()->as_register();
3461 Register lock = op->lock_opr()->as_register();
3462 if (LockingMode == LM_MONITOR) {
3463 if (op->info() != nullptr) {
3464 add_debug_info_for_null_check_here(op->info());
3465 __ null_check(obj);
3466 }
3467 __ jmp(*op->stub()->entry());
3468 } else if (op->code() == lir_lock) {
3469 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3470 Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg;
3471 // add debug info for NullPointerException only if one is possible
3472 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
3473 if (op->info() != nullptr) {
3474 add_debug_info_for_null_check(null_check_offset, op->info());
3475 }
3476 // done
3477 } else if (op->code() == lir_unlock) {
3478 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3479 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3480 } else {
3481 Unimplemented();
3482 }
3483 __ bind(*op->stub()->continuation());
3484 }
3485
3486 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
3487 Register obj = op->obj()->as_pointer_register();
3488 Register result = op->result_opr()->as_pointer_register();
3489
3490 CodeEmitInfo* info = op->info();
3491 if (info != nullptr) {
3492 add_debug_info_for_null_check_here(info);
3493 }
3494
3495 __ load_klass(result, obj, rscratch1);
3496 }
3497
3498 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3499 ciMethod* method = op->profiled_method();
3500 int bci = op->profiled_bci();
3501 ciMethod* callee = op->profiled_callee();
3502 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3503
3504 // Update counter for all call types
3505 ciMethodData* md = method->method_data_or_null();
3506 assert(md != nullptr, "Sanity");
3507 ciProfileData* data = md->bci_to_data(bci);
3508 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
3509 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3510 Register mdo = op->mdo()->as_register();
3511 __ mov_metadata(mdo, md->constant_encoding());
3512 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3513 // Perform additional virtual call profiling for invokevirtual and
3514 // invokeinterface bytecodes
3515 if (op->should_profile_receiver_type()) {
3516 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3517 Register recv = op->recv()->as_register();
3518 assert_different_registers(mdo, recv);
3519 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3520 ciKlass* known_klass = op->known_holder();
3521 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
3522 // We know the type that will be seen at this call site; we can
3523 // statically update the MethodData* rather than needing to do
3524 // dynamic tests on the receiver type
3525
3526 // NOTE: we should probably put a lock around this search to
3527 // avoid collisions by concurrent compilations
3528 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3529 uint i;
3530 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3531 ciKlass* receiver = vc_data->receiver(i);
3532 if (known_klass->equals(receiver)) {
3533 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3534 __ addptr(data_addr, DataLayout::counter_increment);
3535 return;
3536 }
3537 }
3538
3539 // Receiver type not found in profile data; select an empty slot
3540
3541 // Note that this is less efficient than it should be because it
3542 // always does a write to the receiver part of the
3543 // VirtualCallData rather than just the first time
3544 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3545 ciKlass* receiver = vc_data->receiver(i);
3546 if (receiver == nullptr) {
3547 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3548 __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1);
3549 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3550 __ addptr(data_addr, DataLayout::counter_increment);
3551 return;
3552 }
3553 }
3554 } else {
3555 __ load_klass(recv, recv, tmp_load_klass);
3556 Label update_done;
3557 type_profile_helper(mdo, md, data, recv, &update_done);
3558 // Receiver did not match any saved receiver and there is no empty row for it.
3559 // Increment total counter to indicate polymorphic case.
3560 __ addptr(counter_addr, DataLayout::counter_increment);
3561
3562 __ bind(update_done);
3563 }
3564 } else {
3565 // Static call
3566 __ addptr(counter_addr, DataLayout::counter_increment);
3567 }
3568 }
3569
3570 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3571 Register obj = op->obj()->as_register();
3572 Register tmp = op->tmp()->as_pointer_register();
3573 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3574 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3575 ciKlass* exact_klass = op->exact_klass();
3576 intptr_t current_klass = op->current_klass();
3577 bool not_null = op->not_null();
3578 bool no_conflict = op->no_conflict();
3579
3580 Label update, next, none;
3581
3582 bool do_null = !not_null;
3583 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3584 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3585
3586 assert(do_null || do_update, "why are we here?");
3587 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3588
3589 __ verify_oop(obj);
3590
3591 #ifdef ASSERT
3592 if (obj == tmp) {
3593 #ifdef _LP64
3594 assert_different_registers(obj, rscratch1, mdo_addr.base(), mdo_addr.index());
3595 #else
3596 assert_different_registers(obj, mdo_addr.base(), mdo_addr.index());
3597 #endif
3598 } else {
3599 #ifdef _LP64
3600 assert_different_registers(obj, tmp, rscratch1, mdo_addr.base(), mdo_addr.index());
3601 #else
3602 assert_different_registers(obj, tmp, mdo_addr.base(), mdo_addr.index());
3603 #endif
3604 }
3605 #endif
3606 if (do_null) {
3607 __ testptr(obj, obj);
3608 __ jccb(Assembler::notZero, update);
3609 if (!TypeEntries::was_null_seen(current_klass)) {
3610 __ testptr(mdo_addr, TypeEntries::null_seen);
3611 #ifndef ASSERT
3612 __ jccb(Assembler::notZero, next); // already set
3613 #else
3614 __ jcc(Assembler::notZero, next); // already set
3615 #endif
3616 // atomic update to prevent overwriting Klass* with 0
3617 __ lock();
3618 __ orptr(mdo_addr, TypeEntries::null_seen);
3619 }
3620 if (do_update) {
3621 #ifndef ASSERT
3622 __ jmpb(next);
3623 }
3624 #else
3625 __ jmp(next);
3626 }
3627 } else {
3628 __ testptr(obj, obj);
3629 __ jcc(Assembler::notZero, update);
3630 __ stop("unexpected null obj");
3631 #endif
3632 }
3633
3634 __ bind(update);
3635
3636 if (do_update) {
3637 #ifdef ASSERT
3638 if (exact_klass != nullptr) {
3639 Label ok;
3640 __ load_klass(tmp, obj, tmp_load_klass);
3641 __ push(tmp);
3642 __ mov_metadata(tmp, exact_klass->constant_encoding());
3643 __ cmpptr(tmp, Address(rsp, 0));
3644 __ jcc(Assembler::equal, ok);
3645 __ stop("exact klass and actual klass differ");
3646 __ bind(ok);
3647 __ pop(tmp);
3648 }
3649 #endif
3650 if (!no_conflict) {
3651 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3652 if (exact_klass != nullptr) {
3653 __ mov_metadata(tmp, exact_klass->constant_encoding());
3654 } else {
3655 __ load_klass(tmp, obj, tmp_load_klass);
3656 }
3657 #ifdef _LP64
3658 __ mov(rscratch1, tmp); // save original value before XOR
3659 #endif
3660 __ xorptr(tmp, mdo_addr);
3661 __ testptr(tmp, TypeEntries::type_klass_mask);
3662 // klass seen before, nothing to do. The unknown bit may have been
3663 // set already but no need to check.
3664 __ jccb(Assembler::zero, next);
3665
3666 __ testptr(tmp, TypeEntries::type_unknown);
3667 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3668
3669 if (TypeEntries::is_type_none(current_klass)) {
3670 __ testptr(mdo_addr, TypeEntries::type_mask);
3671 __ jccb(Assembler::zero, none);
3672 #ifdef _LP64
3673 // There is a chance that the checks above (re-reading profiling
3674 // data from memory) fail if another thread has just set the
3675 // profiling to this obj's klass
3676 __ mov(tmp, rscratch1); // get back original value before XOR
3677 __ xorptr(tmp, mdo_addr);
3678 __ testptr(tmp, TypeEntries::type_klass_mask);
3679 __ jccb(Assembler::zero, next);
3680 #endif
3681 }
3682 } else {
3683 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3684 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3685
3686 __ testptr(mdo_addr, TypeEntries::type_unknown);
3687 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3688 }
3689
3690 // different than before. Cannot keep accurate profile.
3691 __ orptr(mdo_addr, TypeEntries::type_unknown);
3692
3693 if (TypeEntries::is_type_none(current_klass)) {
3694 __ jmpb(next);
3695
3696 __ bind(none);
3697 // first time here. Set profile type.
3698 __ movptr(mdo_addr, tmp);
3699 #ifdef ASSERT
3700 __ andptr(tmp, TypeEntries::type_klass_mask);
3701 __ verify_klass_ptr(tmp);
3702 #endif
3703 }
3704 } else {
3705 // There's a single possible klass at this profile point
3706 assert(exact_klass != nullptr, "should be");
3707 if (TypeEntries::is_type_none(current_klass)) {
3708 __ mov_metadata(tmp, exact_klass->constant_encoding());
3709 __ xorptr(tmp, mdo_addr);
3710 __ testptr(tmp, TypeEntries::type_klass_mask);
3711 #ifdef ASSERT
3712 __ jcc(Assembler::zero, next);
3713
3714 {
3715 Label ok;
3716 __ push(tmp);
3717 __ testptr(mdo_addr, TypeEntries::type_mask);
3718 __ jcc(Assembler::zero, ok);
3719 // may have been set by another thread
3720 __ mov_metadata(tmp, exact_klass->constant_encoding());
3721 __ xorptr(tmp, mdo_addr);
3722 __ testptr(tmp, TypeEntries::type_mask);
3723 __ jcc(Assembler::zero, ok);
3724
3725 __ stop("unexpected profiling mismatch");
3726 __ bind(ok);
3727 __ pop(tmp);
3728 }
3729 #else
3730 __ jccb(Assembler::zero, next);
3731 #endif
3732 // first time here. Set profile type.
3733 __ movptr(mdo_addr, tmp);
3734 #ifdef ASSERT
3735 __ andptr(tmp, TypeEntries::type_klass_mask);
3736 __ verify_klass_ptr(tmp);
3737 #endif
3738 } else {
3739 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3740 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3741
3742 __ testptr(mdo_addr, TypeEntries::type_unknown);
3743 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3744
3745 __ orptr(mdo_addr, TypeEntries::type_unknown);
3746 }
3747 }
3748 }
3749 __ bind(next);
3750 }
3751
3752 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3753 Unimplemented();
3754 }
3755
3756
3757 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3758 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3759 }
3760
3761
3762 void LIR_Assembler::align_backward_branch_target() {
3763 __ align(BytesPerWord);
3764 }
3765
3766
3767 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3768 if (left->is_single_cpu()) {
3769 __ negl(left->as_register());
3770 move_regs(left->as_register(), dest->as_register());
3771
3772 } else if (left->is_double_cpu()) {
3773 Register lo = left->as_register_lo();
3774 #ifdef _LP64
3775 Register dst = dest->as_register_lo();
3776 __ movptr(dst, lo);
3777 __ negptr(dst);
3778 #else
3779 Register hi = left->as_register_hi();
3780 __ lneg(hi, lo);
3781 if (dest->as_register_lo() == hi) {
3782 assert(dest->as_register_hi() != lo, "destroying register");
3783 move_regs(hi, dest->as_register_hi());
3784 move_regs(lo, dest->as_register_lo());
3785 } else {
3786 move_regs(lo, dest->as_register_lo());
3787 move_regs(hi, dest->as_register_hi());
3788 }
3789 #endif // _LP64
3790
3791 } else if (dest->is_single_xmm()) {
3792 assert(!tmp->is_valid(), "do not need temporary");
3793 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3794 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3795 }
3796 __ xorps(dest->as_xmm_float_reg(),
3797 ExternalAddress((address)float_signflip_pool),
3798 rscratch1);
3799 } else if (dest->is_double_xmm()) {
3800 assert(!tmp->is_valid(), "do not need temporary");
3801 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3802 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3803 }
3804 __ xorpd(dest->as_xmm_double_reg(),
3805 ExternalAddress((address)double_signflip_pool),
3806 rscratch1);
3807 #ifndef _LP64
3808 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3809 assert(left->fpu() == 0, "arg must be on TOS");
3810 assert(dest->fpu() == 0, "dest must be TOS");
3811 __ fchs();
3812 #endif // !_LP64
3813
3814 } else {
3815 ShouldNotReachHere();
3816 }
3817 }
3818
3819
3820 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3821 assert(src->is_address(), "must be an address");
3822 assert(dest->is_register(), "must be a register");
3823
3824 PatchingStub* patch = nullptr;
3825 if (patch_code != lir_patch_none) {
3826 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3827 }
3828
3829 Register reg = dest->as_pointer_register();
3830 LIR_Address* addr = src->as_address_ptr();
3831 __ lea(reg, as_Address(addr));
3832
3833 if (patch != nullptr) {
3834 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3835 }
3836 }
3837
3838
3839
3840 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3841 assert(!tmp->is_valid(), "don't need temporary");
3842 __ call(RuntimeAddress(dest));
3843 if (info != nullptr) {
3844 add_call_info_here(info);
3845 }
3846 __ post_call_nop();
3847 }
3848
3849
3850 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3851 assert(type == T_LONG, "only for volatile long fields");
3852
3853 if (info != nullptr) {
3854 add_debug_info_for_null_check_here(info);
3855 }
3856
3857 if (src->is_double_xmm()) {
3858 if (dest->is_double_cpu()) {
3859 #ifdef _LP64
3860 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3861 #else
3862 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3863 __ psrlq(src->as_xmm_double_reg(), 32);
3864 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3865 #endif // _LP64
3866 } else if (dest->is_double_stack()) {
3867 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3868 } else if (dest->is_address()) {
3869 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3870 } else {
3871 ShouldNotReachHere();
3872 }
3873
3874 } else if (dest->is_double_xmm()) {
3875 if (src->is_double_stack()) {
3876 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3877 } else if (src->is_address()) {
3878 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3879 } else {
3880 ShouldNotReachHere();
3881 }
3882
3883 #ifndef _LP64
3884 } else if (src->is_double_fpu()) {
3885 assert(src->fpu_regnrLo() == 0, "must be TOS");
3886 if (dest->is_double_stack()) {
3887 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3888 } else if (dest->is_address()) {
3889 __ fistp_d(as_Address(dest->as_address_ptr()));
3890 } else {
3891 ShouldNotReachHere();
3892 }
3893
3894 } else if (dest->is_double_fpu()) {
3895 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3896 if (src->is_double_stack()) {
3897 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3898 } else if (src->is_address()) {
3899 __ fild_d(as_Address(src->as_address_ptr()));
3900 } else {
3901 ShouldNotReachHere();
3902 }
3903 #endif // !_LP64
3904
3905 } else {
3906 ShouldNotReachHere();
3907 }
3908 }
3909
3910 #ifdef ASSERT
3911 // emit run-time assertion
3912 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3913 assert(op->code() == lir_assert, "must be");
3914
3915 if (op->in_opr1()->is_valid()) {
3916 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3917 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3918 } else {
3919 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3920 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3921 }
3922
3923 Label ok;
3924 if (op->condition() != lir_cond_always) {
3925 Assembler::Condition acond = Assembler::zero;
3926 switch (op->condition()) {
3927 case lir_cond_equal: acond = Assembler::equal; break;
3928 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3929 case lir_cond_less: acond = Assembler::less; break;
3930 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3931 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3932 case lir_cond_greater: acond = Assembler::greater; break;
3933 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3934 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3935 default: ShouldNotReachHere();
3936 }
3937 __ jcc(acond, ok);
3938 }
3939 if (op->halt()) {
3940 const char* str = __ code_string(op->msg());
3941 __ stop(str);
3942 } else {
3943 breakpoint();
3944 }
3945 __ bind(ok);
3946 }
3947 #endif
3948
3949 void LIR_Assembler::membar() {
3950 // QQQ sparc TSO uses this,
3951 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3952 }
3953
3954 void LIR_Assembler::membar_acquire() {
3955 // No x86 machines currently require load fences
3956 }
3957
3958 void LIR_Assembler::membar_release() {
3959 // No x86 machines currently require store fences
3960 }
3961
3962 void LIR_Assembler::membar_loadload() {
3963 // no-op
3964 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3965 }
3966
3967 void LIR_Assembler::membar_storestore() {
3968 // no-op
3969 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3970 }
3971
3972 void LIR_Assembler::membar_loadstore() {
3973 // no-op
3974 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3975 }
3976
3977 void LIR_Assembler::membar_storeload() {
3978 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3979 }
3980
3981 void LIR_Assembler::on_spin_wait() {
3982 __ pause ();
3983 }
3984
3985 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3986 assert(result_reg->is_register(), "check");
3987 #ifdef _LP64
3988 // __ get_thread(result_reg->as_register_lo());
3989 __ mov(result_reg->as_register(), r15_thread);
3990 #else
3991 __ get_thread(result_reg->as_register());
3992 #endif // _LP64
3993 }
3994
3995
3996 void LIR_Assembler::peephole(LIR_List*) {
3997 // do nothing for now
3998 }
3999
4000 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4001 assert(data == dest, "xchg/xadd uses only 2 operands");
4002
4003 if (data->type() == T_INT) {
4004 if (code == lir_xadd) {
4005 __ lock();
4006 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4007 } else {
4008 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4009 }
4010 } else if (data->is_oop()) {
4011 assert (code == lir_xchg, "xadd for oops");
4012 Register obj = data->as_register();
4013 #ifdef _LP64
4014 if (UseCompressedOops) {
4015 __ encode_heap_oop(obj);
4016 __ xchgl(obj, as_Address(src->as_address_ptr()));
4017 __ decode_heap_oop(obj);
4018 } else {
4019 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4020 }
4021 #else
4022 __ xchgl(obj, as_Address(src->as_address_ptr()));
4023 #endif
4024 } else if (data->type() == T_LONG) {
4025 #ifdef _LP64
4026 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4027 if (code == lir_xadd) {
4028 __ lock();
4029 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4030 } else {
4031 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4032 }
4033 #else
4034 ShouldNotReachHere();
4035 #endif
4036 } else {
4037 ShouldNotReachHere();
4038 }
4039 }
4040
4041 #undef __