1 /*
   2  * Copyright (c) 2000, 2023, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "c1/c1_CodeStubs.hpp"
  29 #include "c1/c1_Compilation.hpp"
  30 #include "c1/c1_LIRAssembler.hpp"
  31 #include "c1/c1_MacroAssembler.hpp"
  32 #include "c1/c1_Runtime1.hpp"
  33 #include "c1/c1_ValueStack.hpp"
  34 #include "ci/ciArrayKlass.hpp"
  35 #include "ci/ciInstance.hpp"
  36 #include "compiler/oopMap.hpp"
  37 #include "gc/shared/collectedHeap.hpp"
  38 #include "gc/shared/gc_globals.hpp"
  39 #include "nativeInst_x86.hpp"
  40 #include "oops/objArrayKlass.hpp"
  41 #include "runtime/frame.inline.hpp"
  42 #include "runtime/safepointMechanism.hpp"
  43 #include "runtime/sharedRuntime.hpp"
  44 #include "runtime/stubRoutines.hpp"
  45 #include "utilities/powerOfTwo.hpp"
  46 #include "vmreg_x86.inline.hpp"
  47 
  48 
  49 // These masks are used to provide 128-bit aligned bitmasks to the XMM
  50 // instructions, to allow sign-masking or sign-bit flipping.  They allow
  51 // fast versions of NegF/NegD and AbsF/AbsD.
  52 
  53 // Note: 'double' and 'long long' have 32-bits alignment on x86.
  54 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
  55   // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
  56   // of 128-bits operands for SSE instructions.
  57   jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
  58   // Store the value to a 128-bits operand.
  59   operand[0] = lo;
  60   operand[1] = hi;
  61   return operand;
  62 }
  63 
  64 // Buffer for 128-bits masks used by SSE instructions.
  65 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
  66 
  67 // Static initialization during VM startup.
  68 static jlong *float_signmask_pool  = double_quadword(&fp_signmask_pool[1*2],         CONST64(0x7FFFFFFF7FFFFFFF),         CONST64(0x7FFFFFFF7FFFFFFF));
  69 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2],         CONST64(0x7FFFFFFFFFFFFFFF),         CONST64(0x7FFFFFFFFFFFFFFF));
  70 static jlong *float_signflip_pool  = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
  71 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
  72 
  73 
  74 NEEDS_CLEANUP // remove this definitions ?
  75 const Register SYNC_header = rax;   // synchronization header
  76 const Register SHIFT_count = rcx;   // where count for shift operations must be
  77 
  78 #define __ _masm->
  79 
  80 
  81 static void select_different_registers(Register preserve,
  82                                        Register extra,
  83                                        Register &tmp1,
  84                                        Register &tmp2) {
  85   if (tmp1 == preserve) {
  86     assert_different_registers(tmp1, tmp2, extra);
  87     tmp1 = extra;
  88   } else if (tmp2 == preserve) {
  89     assert_different_registers(tmp1, tmp2, extra);
  90     tmp2 = extra;
  91   }
  92   assert_different_registers(preserve, tmp1, tmp2);
  93 }
  94 
  95 
  96 
  97 static void select_different_registers(Register preserve,
  98                                        Register extra,
  99                                        Register &tmp1,
 100                                        Register &tmp2,
 101                                        Register &tmp3) {
 102   if (tmp1 == preserve) {
 103     assert_different_registers(tmp1, tmp2, tmp3, extra);
 104     tmp1 = extra;
 105   } else if (tmp2 == preserve) {
 106     assert_different_registers(tmp1, tmp2, tmp3, extra);
 107     tmp2 = extra;
 108   } else if (tmp3 == preserve) {
 109     assert_different_registers(tmp1, tmp2, tmp3, extra);
 110     tmp3 = extra;
 111   }
 112   assert_different_registers(preserve, tmp1, tmp2, tmp3);
 113 }
 114 
 115 
 116 
 117 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
 118   if (opr->is_constant()) {
 119     LIR_Const* constant = opr->as_constant_ptr();
 120     switch (constant->type()) {
 121       case T_INT: {
 122         return true;
 123       }
 124 
 125       default:
 126         return false;
 127     }
 128   }
 129   return false;
 130 }
 131 
 132 
 133 LIR_Opr LIR_Assembler::receiverOpr() {
 134   return FrameMap::receiver_opr;
 135 }
 136 
 137 LIR_Opr LIR_Assembler::osrBufferPointer() {
 138   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 139 }
 140 
 141 //--------------fpu register translations-----------------------
 142 
 143 
 144 address LIR_Assembler::float_constant(float f) {
 145   address const_addr = __ float_constant(f);
 146   if (const_addr == nullptr) {
 147     bailout("const section overflow");
 148     return __ code()->consts()->start();
 149   } else {
 150     return const_addr;
 151   }
 152 }
 153 
 154 
 155 address LIR_Assembler::double_constant(double d) {
 156   address const_addr = __ double_constant(d);
 157   if (const_addr == nullptr) {
 158     bailout("const section overflow");
 159     return __ code()->consts()->start();
 160   } else {
 161     return const_addr;
 162   }
 163 }
 164 
 165 #ifndef _LP64
 166 void LIR_Assembler::fpop() {
 167   __ fpop();
 168 }
 169 
 170 void LIR_Assembler::fxch(int i) {
 171   __ fxch(i);
 172 }
 173 
 174 void LIR_Assembler::fld(int i) {
 175   __ fld_s(i);
 176 }
 177 
 178 void LIR_Assembler::ffree(int i) {
 179   __ ffree(i);
 180 }
 181 #endif // !_LP64
 182 
 183 void LIR_Assembler::breakpoint() {
 184   __ int3();
 185 }
 186 
 187 void LIR_Assembler::push(LIR_Opr opr) {
 188   if (opr->is_single_cpu()) {
 189     __ push_reg(opr->as_register());
 190   } else if (opr->is_double_cpu()) {
 191     NOT_LP64(__ push_reg(opr->as_register_hi()));
 192     __ push_reg(opr->as_register_lo());
 193   } else if (opr->is_stack()) {
 194     __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
 195   } else if (opr->is_constant()) {
 196     LIR_Const* const_opr = opr->as_constant_ptr();
 197     if (const_opr->type() == T_OBJECT) {
 198       __ push_oop(const_opr->as_jobject(), rscratch1);
 199     } else if (const_opr->type() == T_INT) {
 200       __ push_jint(const_opr->as_jint());
 201     } else {
 202       ShouldNotReachHere();
 203     }
 204 
 205   } else {
 206     ShouldNotReachHere();
 207   }
 208 }
 209 
 210 void LIR_Assembler::pop(LIR_Opr opr) {
 211   if (opr->is_single_cpu()) {
 212     __ pop_reg(opr->as_register());
 213   } else {
 214     ShouldNotReachHere();
 215   }
 216 }
 217 
 218 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
 219   return addr->base()->is_illegal() && addr->index()->is_illegal();
 220 }
 221 
 222 //-------------------------------------------
 223 
 224 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 225   return as_Address(addr, rscratch1);
 226 }
 227 
 228 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 229   if (addr->base()->is_illegal()) {
 230     assert(addr->index()->is_illegal(), "must be illegal too");
 231     AddressLiteral laddr((address)addr->disp(), relocInfo::none);
 232     if (! __ reachable(laddr)) {
 233       __ movptr(tmp, laddr.addr());
 234       Address res(tmp, 0);
 235       return res;
 236     } else {
 237       return __ as_Address(laddr);
 238     }
 239   }
 240 
 241   Register base = addr->base()->as_pointer_register();
 242 
 243   if (addr->index()->is_illegal()) {
 244     return Address( base, addr->disp());
 245   } else if (addr->index()->is_cpu_register()) {
 246     Register index = addr->index()->as_pointer_register();
 247     return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
 248   } else if (addr->index()->is_constant()) {
 249     intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
 250     assert(Assembler::is_simm32(addr_offset), "must be");
 251 
 252     return Address(base, addr_offset);
 253   } else {
 254     Unimplemented();
 255     return Address();
 256   }
 257 }
 258 
 259 
 260 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 261   Address base = as_Address(addr);
 262   return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
 263 }
 264 
 265 
 266 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 267   return as_Address(addr);
 268 }
 269 
 270 
 271 void LIR_Assembler::osr_entry() {
 272   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 273   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 274   ValueStack* entry_state = osr_entry->state();
 275   int number_of_locks = entry_state->locks_size();
 276 
 277   // we jump here if osr happens with the interpreter
 278   // state set up to continue at the beginning of the
 279   // loop that triggered osr - in particular, we have
 280   // the following registers setup:
 281   //
 282   // rcx: osr buffer
 283   //
 284 
 285   // build frame
 286   ciMethod* m = compilation()->method();
 287   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 288 
 289   // OSR buffer is
 290   //
 291   // locals[nlocals-1..0]
 292   // monitors[0..number_of_locks]
 293   //
 294   // locals is a direct copy of the interpreter frame so in the osr buffer
 295   // so first slot in the local array is the last local from the interpreter
 296   // and last slot is local[0] (receiver) from the interpreter
 297   //
 298   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 299   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 300   // in the interpreter frame (the method lock if a sync method)
 301 
 302   // Initialize monitors in the compiled activation.
 303   //   rcx: pointer to osr buffer
 304   //
 305   // All other registers are dead at this point and the locals will be
 306   // copied into place by code emitted in the IR.
 307 
 308   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 309   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 310     int monitor_offset = BytesPerWord * method()->max_locals() +
 311       (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
 312     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 313     // the OSR buffer using 2 word entries: first the lock and then
 314     // the oop.
 315     for (int i = 0; i < number_of_locks; i++) {
 316       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 317 #ifdef ASSERT
 318       // verify the interpreter's monitor has a non-null object
 319       {
 320         Label L;
 321         __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD);
 322         __ jcc(Assembler::notZero, L);
 323         __ stop("locked object is null");
 324         __ bind(L);
 325       }
 326 #endif
 327       __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
 328       __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
 329       __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 330       __ movptr(frame_map()->address_for_monitor_object(i), rbx);
 331     }
 332   }
 333 }
 334 
 335 
 336 // inline cache check; done before the frame is built.
 337 int LIR_Assembler::check_icache() {
 338   return __ ic_check(CodeEntryAlignment);
 339 }
 340 
 341 void LIR_Assembler::clinit_barrier(ciMethod* method) {
 342   assert(VM_Version::supports_fast_class_init_checks(), "sanity");
 343   assert(!method->holder()->is_not_initialized(), "initialization should have been started");
 344 
 345   Label L_skip_barrier;
 346   Register klass = rscratch1;
 347   Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
 348   assert(thread != noreg, "x86_32 not implemented");
 349 
 350   __ mov_metadata(klass, method->holder()->constant_encoding());
 351   __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
 352 
 353   __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
 354 
 355   __ bind(L_skip_barrier);
 356 }
 357 
 358 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
 359   jobject o = nullptr;
 360   PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
 361   __ movoop(reg, o);
 362   patching_epilog(patch, lir_patch_normal, reg, info);
 363 }
 364 
 365 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 366   Metadata* o = nullptr;
 367   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
 368   __ mov_metadata(reg, o);
 369   patching_epilog(patch, lir_patch_normal, reg, info);
 370 }
 371 
 372 // This specifies the rsp decrement needed to build the frame
 373 int LIR_Assembler::initial_frame_size_in_bytes() const {
 374   // if rounding, must let FrameMap know!
 375 
 376   // The frame_map records size in slots (32bit word)
 377 
 378   // subtract two words to account for return address and link
 379   return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word))  * VMRegImpl::stack_slot_size;
 380 }
 381 
 382 
 383 int LIR_Assembler::emit_exception_handler() {
 384   // generate code for exception handler
 385   address handler_base = __ start_a_stub(exception_handler_size());
 386   if (handler_base == nullptr) {
 387     // not enough space left for the handler
 388     bailout("exception handler overflow");
 389     return -1;
 390   }
 391 
 392   int offset = code_offset();
 393 
 394   // the exception oop and pc are in rax, and rdx
 395   // no other registers need to be preserved, so invalidate them
 396   __ invalidate_registers(false, true, true, false, true, true);
 397 
 398   // check that there is really an exception
 399   __ verify_not_null_oop(rax);
 400 
 401   // search an exception handler (rax: exception oop, rdx: throwing pc)
 402   __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
 403   __ should_not_reach_here();
 404   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 405   __ end_a_stub();
 406 
 407   return offset;
 408 }
 409 
 410 
 411 // Emit the code to remove the frame from the stack in the exception
 412 // unwind path.
 413 int LIR_Assembler::emit_unwind_handler() {
 414 #ifndef PRODUCT
 415   if (CommentedAssembly) {
 416     _masm->block_comment("Unwind handler");
 417   }
 418 #endif
 419 
 420   int offset = code_offset();
 421 
 422   // Fetch the exception from TLS and clear out exception related thread state
 423   Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
 424   NOT_LP64(__ get_thread(thread));
 425   __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
 426   __ movptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
 427   __ movptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
 428 
 429   __ bind(_unwind_handler_entry);
 430   __ verify_not_null_oop(rax);
 431   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 432     __ mov(rbx, rax);  // Preserve the exception (rbx is always callee-saved)
 433   }
 434 
 435   // Perform needed unlocking
 436   MonitorExitStub* stub = nullptr;
 437   if (method()->is_synchronized()) {
 438     monitor_address(0, FrameMap::rax_opr);
 439     stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
 440     if (LockingMode == LM_MONITOR) {
 441       __ jmp(*stub->entry());
 442     } else {
 443       __ unlock_object(rdi, rsi, rax, *stub->entry());
 444     }
 445     __ bind(*stub->continuation());
 446   }
 447 
 448   if (compilation()->env()->dtrace_method_probes()) {
 449 #ifdef _LP64
 450     __ mov(rdi, r15_thread);
 451     __ mov_metadata(rsi, method()->constant_encoding());
 452 #else
 453     __ get_thread(rax);
 454     __ movptr(Address(rsp, 0), rax);
 455     __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding(), noreg);
 456 #endif
 457     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
 458   }
 459 
 460   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 461     __ mov(rax, rbx);  // Restore the exception
 462   }
 463 
 464   // remove the activation and dispatch to the unwind handler
 465   __ remove_frame(initial_frame_size_in_bytes());
 466   __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 467 
 468   // Emit the slow path assembly
 469   if (stub != nullptr) {
 470     stub->emit_code(this);
 471   }
 472 
 473   return offset;
 474 }
 475 
 476 
 477 int LIR_Assembler::emit_deopt_handler() {
 478   // generate code for exception handler
 479   address handler_base = __ start_a_stub(deopt_handler_size());
 480   if (handler_base == nullptr) {
 481     // not enough space left for the handler
 482     bailout("deopt handler overflow");
 483     return -1;
 484   }
 485 
 486   int offset = code_offset();
 487   InternalAddress here(__ pc());
 488 
 489   __ pushptr(here.addr(), rscratch1);
 490   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 491   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 492   __ end_a_stub();
 493 
 494   return offset;
 495 }
 496 
 497 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
 498   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
 499   if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
 500     assert(result->fpu() == 0, "result must already be on TOS");
 501   }
 502 
 503   // Pop the stack before the safepoint code
 504   __ remove_frame(initial_frame_size_in_bytes());
 505 
 506   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 507     __ reserved_stack_check();
 508   }
 509 
 510   // Note: we do not need to round double result; float result has the right precision
 511   // the poll sets the condition code, but no data registers
 512 
 513 #ifdef _LP64
 514   const Register thread = r15_thread;
 515 #else
 516   const Register thread = rbx;
 517   __ get_thread(thread);
 518 #endif
 519   code_stub->set_safepoint_offset(__ offset());
 520   __ relocate(relocInfo::poll_return_type);
 521   __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */);
 522   __ ret(0);
 523 }
 524 
 525 
 526 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 527   guarantee(info != nullptr, "Shouldn't be null");
 528   int offset = __ offset();
 529 #ifdef _LP64
 530   const Register poll_addr = rscratch1;
 531   __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
 532 #else
 533   assert(tmp->is_cpu_register(), "needed");
 534   const Register poll_addr = tmp->as_register();
 535   __ get_thread(poll_addr);
 536   __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset())));
 537 #endif
 538   add_debug_info_for_branch(info);
 539   __ relocate(relocInfo::poll_type);
 540   address pre_pc = __ pc();
 541   __ testl(rax, Address(poll_addr, 0));
 542   address post_pc = __ pc();
 543   guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
 544   return offset;
 545 }
 546 
 547 
 548 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 549   if (from_reg != to_reg) __ mov(to_reg, from_reg);
 550 }
 551 
 552 void LIR_Assembler::swap_reg(Register a, Register b) {
 553   __ xchgptr(a, b);
 554 }
 555 
 556 
 557 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 558   assert(src->is_constant(), "should not call otherwise");
 559   assert(dest->is_register(), "should not call otherwise");
 560   LIR_Const* c = src->as_constant_ptr();
 561 
 562   switch (c->type()) {
 563     case T_INT: {
 564       assert(patch_code == lir_patch_none, "no patching handled here");
 565       __ movl(dest->as_register(), c->as_jint());
 566       break;
 567     }
 568 
 569     case T_ADDRESS: {
 570       assert(patch_code == lir_patch_none, "no patching handled here");
 571       __ movptr(dest->as_register(), c->as_jint());
 572       break;
 573     }
 574 
 575     case T_LONG: {
 576       assert(patch_code == lir_patch_none, "no patching handled here");
 577 #ifdef _LP64
 578       __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
 579 #else
 580       __ movptr(dest->as_register_lo(), c->as_jint_lo());
 581       __ movptr(dest->as_register_hi(), c->as_jint_hi());
 582 #endif // _LP64
 583       break;
 584     }
 585 
 586     case T_OBJECT: {
 587       if (patch_code != lir_patch_none) {
 588         jobject2reg_with_patching(dest->as_register(), info);
 589       } else {
 590         __ movoop(dest->as_register(), c->as_jobject());
 591       }
 592       break;
 593     }
 594 
 595     case T_METADATA: {
 596       if (patch_code != lir_patch_none) {
 597         klass2reg_with_patching(dest->as_register(), info);
 598       } else {
 599         __ mov_metadata(dest->as_register(), c->as_metadata());
 600       }
 601       break;
 602     }
 603 
 604     case T_FLOAT: {
 605       if (dest->is_single_xmm()) {
 606         if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
 607           __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
 608         } else {
 609           __ movflt(dest->as_xmm_float_reg(),
 610                    InternalAddress(float_constant(c->as_jfloat())));
 611         }
 612       } else {
 613 #ifndef _LP64
 614         assert(dest->is_single_fpu(), "must be");
 615         assert(dest->fpu_regnr() == 0, "dest must be TOS");
 616         if (c->is_zero_float()) {
 617           __ fldz();
 618         } else if (c->is_one_float()) {
 619           __ fld1();
 620         } else {
 621           __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
 622         }
 623 #else
 624         ShouldNotReachHere();
 625 #endif // !_LP64
 626       }
 627       break;
 628     }
 629 
 630     case T_DOUBLE: {
 631       if (dest->is_double_xmm()) {
 632         if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
 633           __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
 634         } else {
 635           __ movdbl(dest->as_xmm_double_reg(),
 636                     InternalAddress(double_constant(c->as_jdouble())));
 637         }
 638       } else {
 639 #ifndef _LP64
 640         assert(dest->is_double_fpu(), "must be");
 641         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
 642         if (c->is_zero_double()) {
 643           __ fldz();
 644         } else if (c->is_one_double()) {
 645           __ fld1();
 646         } else {
 647           __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
 648         }
 649 #else
 650         ShouldNotReachHere();
 651 #endif // !_LP64
 652       }
 653       break;
 654     }
 655 
 656     default:
 657       ShouldNotReachHere();
 658   }
 659 }
 660 
 661 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 662   assert(src->is_constant(), "should not call otherwise");
 663   assert(dest->is_stack(), "should not call otherwise");
 664   LIR_Const* c = src->as_constant_ptr();
 665 
 666   switch (c->type()) {
 667     case T_INT:  // fall through
 668     case T_FLOAT:
 669       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 670       break;
 671 
 672     case T_ADDRESS:
 673       __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 674       break;
 675 
 676     case T_OBJECT:
 677       __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1);
 678       break;
 679 
 680     case T_LONG:  // fall through
 681     case T_DOUBLE:
 682 #ifdef _LP64
 683       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 684                                               lo_word_offset_in_bytes),
 685                 (intptr_t)c->as_jlong_bits(),
 686                 rscratch1);
 687 #else
 688       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 689                                               lo_word_offset_in_bytes), c->as_jint_lo_bits());
 690       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 691                                               hi_word_offset_in_bytes), c->as_jint_hi_bits());
 692 #endif // _LP64
 693       break;
 694 
 695     default:
 696       ShouldNotReachHere();
 697   }
 698 }
 699 
 700 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 701   assert(src->is_constant(), "should not call otherwise");
 702   assert(dest->is_address(), "should not call otherwise");
 703   LIR_Const* c = src->as_constant_ptr();
 704   LIR_Address* addr = dest->as_address_ptr();
 705 
 706   int null_check_here = code_offset();
 707   switch (type) {
 708     case T_INT:    // fall through
 709     case T_FLOAT:
 710       __ movl(as_Address(addr), c->as_jint_bits());
 711       break;
 712 
 713     case T_ADDRESS:
 714       __ movptr(as_Address(addr), c->as_jint_bits());
 715       break;
 716 
 717     case T_OBJECT:  // fall through
 718     case T_ARRAY:
 719       if (c->as_jobject() == nullptr) {
 720         if (UseCompressedOops && !wide) {
 721           __ movl(as_Address(addr), NULL_WORD);
 722         } else {
 723 #ifdef _LP64
 724           __ xorptr(rscratch1, rscratch1);
 725           null_check_here = code_offset();
 726           __ movptr(as_Address(addr), rscratch1);
 727 #else
 728           __ movptr(as_Address(addr), NULL_WORD);
 729 #endif
 730         }
 731       } else {
 732         if (is_literal_address(addr)) {
 733           ShouldNotReachHere();
 734           __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1);
 735         } else {
 736 #ifdef _LP64
 737           __ movoop(rscratch1, c->as_jobject());
 738           if (UseCompressedOops && !wide) {
 739             __ encode_heap_oop(rscratch1);
 740             null_check_here = code_offset();
 741             __ movl(as_Address_lo(addr), rscratch1);
 742           } else {
 743             null_check_here = code_offset();
 744             __ movptr(as_Address_lo(addr), rscratch1);
 745           }
 746 #else
 747           __ movoop(as_Address(addr), c->as_jobject(), noreg);
 748 #endif
 749         }
 750       }
 751       break;
 752 
 753     case T_LONG:    // fall through
 754     case T_DOUBLE:
 755 #ifdef _LP64
 756       if (is_literal_address(addr)) {
 757         ShouldNotReachHere();
 758         __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
 759       } else {
 760         __ movptr(r10, (intptr_t)c->as_jlong_bits());
 761         null_check_here = code_offset();
 762         __ movptr(as_Address_lo(addr), r10);
 763       }
 764 #else
 765       // Always reachable in 32bit so this doesn't produce useless move literal
 766       __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
 767       __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
 768 #endif // _LP64
 769       break;
 770 
 771     case T_BOOLEAN: // fall through
 772     case T_BYTE:
 773       __ movb(as_Address(addr), c->as_jint() & 0xFF);
 774       break;
 775 
 776     case T_CHAR:    // fall through
 777     case T_SHORT:
 778       __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
 779       break;
 780 
 781     default:
 782       ShouldNotReachHere();
 783   };
 784 
 785   if (info != nullptr) {
 786     add_debug_info_for_null_check(null_check_here, info);
 787   }
 788 }
 789 
 790 
 791 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 792   assert(src->is_register(), "should not call otherwise");
 793   assert(dest->is_register(), "should not call otherwise");
 794 
 795   // move between cpu-registers
 796   if (dest->is_single_cpu()) {
 797 #ifdef _LP64
 798     if (src->type() == T_LONG) {
 799       // Can do LONG -> OBJECT
 800       move_regs(src->as_register_lo(), dest->as_register());
 801       return;
 802     }
 803 #endif
 804     assert(src->is_single_cpu(), "must match");
 805     if (src->type() == T_OBJECT) {
 806       __ verify_oop(src->as_register());
 807     }
 808     move_regs(src->as_register(), dest->as_register());
 809 
 810   } else if (dest->is_double_cpu()) {
 811 #ifdef _LP64
 812     if (is_reference_type(src->type())) {
 813       // Surprising to me but we can see move of a long to t_object
 814       __ verify_oop(src->as_register());
 815       move_regs(src->as_register(), dest->as_register_lo());
 816       return;
 817     }
 818 #endif
 819     assert(src->is_double_cpu(), "must match");
 820     Register f_lo = src->as_register_lo();
 821     Register f_hi = src->as_register_hi();
 822     Register t_lo = dest->as_register_lo();
 823     Register t_hi = dest->as_register_hi();
 824 #ifdef _LP64
 825     assert(f_hi == f_lo, "must be same");
 826     assert(t_hi == t_lo, "must be same");
 827     move_regs(f_lo, t_lo);
 828 #else
 829     assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
 830 
 831 
 832     if (f_lo == t_hi && f_hi == t_lo) {
 833       swap_reg(f_lo, f_hi);
 834     } else if (f_hi == t_lo) {
 835       assert(f_lo != t_hi, "overwriting register");
 836       move_regs(f_hi, t_hi);
 837       move_regs(f_lo, t_lo);
 838     } else {
 839       assert(f_hi != t_lo, "overwriting register");
 840       move_regs(f_lo, t_lo);
 841       move_regs(f_hi, t_hi);
 842     }
 843 #endif // LP64
 844 
 845 #ifndef _LP64
 846     // special moves from fpu-register to xmm-register
 847     // necessary for method results
 848   } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
 849     __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
 850     __ fld_s(Address(rsp, 0));
 851   } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
 852     __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
 853     __ fld_d(Address(rsp, 0));
 854   } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
 855     __ fstp_s(Address(rsp, 0));
 856     __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
 857   } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
 858     __ fstp_d(Address(rsp, 0));
 859     __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
 860 #endif // !_LP64
 861 
 862     // move between xmm-registers
 863   } else if (dest->is_single_xmm()) {
 864     assert(src->is_single_xmm(), "must match");
 865     __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
 866   } else if (dest->is_double_xmm()) {
 867     assert(src->is_double_xmm(), "must match");
 868     __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
 869 
 870 #ifndef _LP64
 871     // move between fpu-registers (no instruction necessary because of fpu-stack)
 872   } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
 873     assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
 874     assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
 875 #endif // !_LP64
 876 
 877   } else {
 878     ShouldNotReachHere();
 879   }
 880 }
 881 
 882 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 883   assert(src->is_register(), "should not call otherwise");
 884   assert(dest->is_stack(), "should not call otherwise");
 885 
 886   if (src->is_single_cpu()) {
 887     Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
 888     if (is_reference_type(type)) {
 889       __ verify_oop(src->as_register());
 890       __ movptr (dst, src->as_register());
 891     } else if (type == T_METADATA || type == T_ADDRESS) {
 892       __ movptr (dst, src->as_register());
 893     } else {
 894       __ movl (dst, src->as_register());
 895     }
 896 
 897   } else if (src->is_double_cpu()) {
 898     Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
 899     Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
 900     __ movptr (dstLO, src->as_register_lo());
 901     NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
 902 
 903   } else if (src->is_single_xmm()) {
 904     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 905     __ movflt(dst_addr, src->as_xmm_float_reg());
 906 
 907   } else if (src->is_double_xmm()) {
 908     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 909     __ movdbl(dst_addr, src->as_xmm_double_reg());
 910 
 911 #ifndef _LP64
 912   } else if (src->is_single_fpu()) {
 913     assert(src->fpu_regnr() == 0, "argument must be on TOS");
 914     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 915     if (pop_fpu_stack)     __ fstp_s (dst_addr);
 916     else                   __ fst_s  (dst_addr);
 917 
 918   } else if (src->is_double_fpu()) {
 919     assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
 920     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 921     if (pop_fpu_stack)     __ fstp_d (dst_addr);
 922     else                   __ fst_d  (dst_addr);
 923 #endif // !_LP64
 924 
 925   } else {
 926     ShouldNotReachHere();
 927   }
 928 }
 929 
 930 
 931 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
 932   LIR_Address* to_addr = dest->as_address_ptr();
 933   PatchingStub* patch = nullptr;
 934   Register compressed_src = rscratch1;
 935 
 936   if (is_reference_type(type)) {
 937     __ verify_oop(src->as_register());
 938 #ifdef _LP64
 939     if (UseCompressedOops && !wide) {
 940       __ movptr(compressed_src, src->as_register());
 941       __ encode_heap_oop(compressed_src);
 942       if (patch_code != lir_patch_none) {
 943         info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
 944       }
 945     }
 946 #endif
 947   }
 948 
 949   if (patch_code != lir_patch_none) {
 950     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 951     Address toa = as_Address(to_addr);
 952     assert(toa.disp() != 0, "must have");
 953   }
 954 
 955   int null_check_here = code_offset();
 956   switch (type) {
 957     case T_FLOAT: {
 958 #ifdef _LP64
 959       assert(src->is_single_xmm(), "not a float");
 960       __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
 961 #else
 962       if (src->is_single_xmm()) {
 963         __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
 964       } else {
 965         assert(src->is_single_fpu(), "must be");
 966         assert(src->fpu_regnr() == 0, "argument must be on TOS");
 967         if (pop_fpu_stack)      __ fstp_s(as_Address(to_addr));
 968         else                    __ fst_s (as_Address(to_addr));
 969       }
 970 #endif // _LP64
 971       break;
 972     }
 973 
 974     case T_DOUBLE: {
 975 #ifdef _LP64
 976       assert(src->is_double_xmm(), "not a double");
 977       __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
 978 #else
 979       if (src->is_double_xmm()) {
 980         __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
 981       } else {
 982         assert(src->is_double_fpu(), "must be");
 983         assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
 984         if (pop_fpu_stack)      __ fstp_d(as_Address(to_addr));
 985         else                    __ fst_d (as_Address(to_addr));
 986       }
 987 #endif // _LP64
 988       break;
 989     }
 990 
 991     case T_ARRAY:   // fall through
 992     case T_OBJECT:  // fall through
 993       if (UseCompressedOops && !wide) {
 994         __ movl(as_Address(to_addr), compressed_src);
 995       } else {
 996         __ movptr(as_Address(to_addr), src->as_register());
 997       }
 998       break;
 999     case T_METADATA:
1000       // We get here to store a method pointer to the stack to pass to
1001       // a dtrace runtime call. This can't work on 64 bit with
1002       // compressed klass ptrs: T_METADATA can be a compressed klass
1003       // ptr or a 64 bit method pointer.
1004       LP64_ONLY(ShouldNotReachHere());
1005       __ movptr(as_Address(to_addr), src->as_register());
1006       break;
1007     case T_ADDRESS:
1008       __ movptr(as_Address(to_addr), src->as_register());
1009       break;
1010     case T_INT:
1011       __ movl(as_Address(to_addr), src->as_register());
1012       break;
1013 
1014     case T_LONG: {
1015       Register from_lo = src->as_register_lo();
1016       Register from_hi = src->as_register_hi();
1017 #ifdef _LP64
1018       __ movptr(as_Address_lo(to_addr), from_lo);
1019 #else
1020       Register base = to_addr->base()->as_register();
1021       Register index = noreg;
1022       if (to_addr->index()->is_register()) {
1023         index = to_addr->index()->as_register();
1024       }
1025       if (base == from_lo || index == from_lo) {
1026         assert(base != from_hi, "can't be");
1027         assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1028         __ movl(as_Address_hi(to_addr), from_hi);
1029         if (patch != nullptr) {
1030           patching_epilog(patch, lir_patch_high, base, info);
1031           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1032           patch_code = lir_patch_low;
1033         }
1034         __ movl(as_Address_lo(to_addr), from_lo);
1035       } else {
1036         assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1037         __ movl(as_Address_lo(to_addr), from_lo);
1038         if (patch != nullptr) {
1039           patching_epilog(patch, lir_patch_low, base, info);
1040           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1041           patch_code = lir_patch_high;
1042         }
1043         __ movl(as_Address_hi(to_addr), from_hi);
1044       }
1045 #endif // _LP64
1046       break;
1047     }
1048 
1049     case T_BYTE:    // fall through
1050     case T_BOOLEAN: {
1051       Register src_reg = src->as_register();
1052       Address dst_addr = as_Address(to_addr);
1053       assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1054       __ movb(dst_addr, src_reg);
1055       break;
1056     }
1057 
1058     case T_CHAR:    // fall through
1059     case T_SHORT:
1060       __ movw(as_Address(to_addr), src->as_register());
1061       break;
1062 
1063     default:
1064       ShouldNotReachHere();
1065   }
1066   if (info != nullptr) {
1067     add_debug_info_for_null_check(null_check_here, info);
1068   }
1069 
1070   if (patch_code != lir_patch_none) {
1071     patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1072   }
1073 }
1074 
1075 
1076 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1077   assert(src->is_stack(), "should not call otherwise");
1078   assert(dest->is_register(), "should not call otherwise");
1079 
1080   if (dest->is_single_cpu()) {
1081     if (is_reference_type(type)) {
1082       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1083       __ verify_oop(dest->as_register());
1084     } else if (type == T_METADATA || type == T_ADDRESS) {
1085       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1086     } else {
1087       __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1088     }
1089 
1090   } else if (dest->is_double_cpu()) {
1091     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1092     Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1093     __ movptr(dest->as_register_lo(), src_addr_LO);
1094     NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1095 
1096   } else if (dest->is_single_xmm()) {
1097     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1098     __ movflt(dest->as_xmm_float_reg(), src_addr);
1099 
1100   } else if (dest->is_double_xmm()) {
1101     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1102     __ movdbl(dest->as_xmm_double_reg(), src_addr);
1103 
1104 #ifndef _LP64
1105   } else if (dest->is_single_fpu()) {
1106     assert(dest->fpu_regnr() == 0, "dest must be TOS");
1107     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1108     __ fld_s(src_addr);
1109 
1110   } else if (dest->is_double_fpu()) {
1111     assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1112     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1113     __ fld_d(src_addr);
1114 #endif // _LP64
1115 
1116   } else {
1117     ShouldNotReachHere();
1118   }
1119 }
1120 
1121 
1122 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1123   if (src->is_single_stack()) {
1124     if (is_reference_type(type)) {
1125       __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1126       __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1127     } else {
1128 #ifndef _LP64
1129       __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1130       __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1131 #else
1132       //no pushl on 64bits
1133       __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1134       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1135 #endif
1136     }
1137 
1138   } else if (src->is_double_stack()) {
1139 #ifdef _LP64
1140     __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1141     __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1142 #else
1143     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1144     // push and pop the part at src + wordSize, adding wordSize for the previous push
1145     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1146     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1147     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1148 #endif // _LP64
1149 
1150   } else {
1151     ShouldNotReachHere();
1152   }
1153 }
1154 
1155 
1156 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1157   assert(src->is_address(), "should not call otherwise");
1158   assert(dest->is_register(), "should not call otherwise");
1159 
1160   LIR_Address* addr = src->as_address_ptr();
1161   Address from_addr = as_Address(addr);
1162 
1163   if (addr->base()->type() == T_OBJECT) {
1164     __ verify_oop(addr->base()->as_pointer_register());
1165   }
1166 
1167   switch (type) {
1168     case T_BOOLEAN: // fall through
1169     case T_BYTE:    // fall through
1170     case T_CHAR:    // fall through
1171     case T_SHORT:
1172       if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1173         // on pre P6 processors we may get partial register stalls
1174         // so blow away the value of to_rinfo before loading a
1175         // partial word into it.  Do it here so that it precedes
1176         // the potential patch point below.
1177         __ xorptr(dest->as_register(), dest->as_register());
1178       }
1179       break;
1180    default:
1181      break;
1182   }
1183 
1184   PatchingStub* patch = nullptr;
1185   if (patch_code != lir_patch_none) {
1186     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1187     assert(from_addr.disp() != 0, "must have");
1188   }
1189   if (info != nullptr) {
1190     add_debug_info_for_null_check_here(info);
1191   }
1192 
1193   switch (type) {
1194     case T_FLOAT: {
1195       if (dest->is_single_xmm()) {
1196         __ movflt(dest->as_xmm_float_reg(), from_addr);
1197       } else {
1198 #ifndef _LP64
1199         assert(dest->is_single_fpu(), "must be");
1200         assert(dest->fpu_regnr() == 0, "dest must be TOS");
1201         __ fld_s(from_addr);
1202 #else
1203         ShouldNotReachHere();
1204 #endif // !LP64
1205       }
1206       break;
1207     }
1208 
1209     case T_DOUBLE: {
1210       if (dest->is_double_xmm()) {
1211         __ movdbl(dest->as_xmm_double_reg(), from_addr);
1212       } else {
1213 #ifndef _LP64
1214         assert(dest->is_double_fpu(), "must be");
1215         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1216         __ fld_d(from_addr);
1217 #else
1218         ShouldNotReachHere();
1219 #endif // !LP64
1220       }
1221       break;
1222     }
1223 
1224     case T_OBJECT:  // fall through
1225     case T_ARRAY:   // fall through
1226       if (UseCompressedOops && !wide) {
1227         __ movl(dest->as_register(), from_addr);
1228       } else {
1229         __ movptr(dest->as_register(), from_addr);
1230       }
1231       break;
1232 
1233     case T_ADDRESS:
1234       __ movptr(dest->as_register(), from_addr);
1235       break;
1236     case T_INT:
1237       __ movl(dest->as_register(), from_addr);
1238       break;
1239 
1240     case T_LONG: {
1241       Register to_lo = dest->as_register_lo();
1242       Register to_hi = dest->as_register_hi();
1243 #ifdef _LP64
1244       __ movptr(to_lo, as_Address_lo(addr));
1245 #else
1246       Register base = addr->base()->as_register();
1247       Register index = noreg;
1248       if (addr->index()->is_register()) {
1249         index = addr->index()->as_register();
1250       }
1251       if ((base == to_lo && index == to_hi) ||
1252           (base == to_hi && index == to_lo)) {
1253         // addresses with 2 registers are only formed as a result of
1254         // array access so this code will never have to deal with
1255         // patches or null checks.
1256         assert(info == nullptr && patch == nullptr, "must be");
1257         __ lea(to_hi, as_Address(addr));
1258         __ movl(to_lo, Address(to_hi, 0));
1259         __ movl(to_hi, Address(to_hi, BytesPerWord));
1260       } else if (base == to_lo || index == to_lo) {
1261         assert(base != to_hi, "can't be");
1262         assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1263         __ movl(to_hi, as_Address_hi(addr));
1264         if (patch != nullptr) {
1265           patching_epilog(patch, lir_patch_high, base, info);
1266           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1267           patch_code = lir_patch_low;
1268         }
1269         __ movl(to_lo, as_Address_lo(addr));
1270       } else {
1271         assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1272         __ movl(to_lo, as_Address_lo(addr));
1273         if (patch != nullptr) {
1274           patching_epilog(patch, lir_patch_low, base, info);
1275           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1276           patch_code = lir_patch_high;
1277         }
1278         __ movl(to_hi, as_Address_hi(addr));
1279       }
1280 #endif // _LP64
1281       break;
1282     }
1283 
1284     case T_BOOLEAN: // fall through
1285     case T_BYTE: {
1286       Register dest_reg = dest->as_register();
1287       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1288       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1289         __ movsbl(dest_reg, from_addr);
1290       } else {
1291         __ movb(dest_reg, from_addr);
1292         __ shll(dest_reg, 24);
1293         __ sarl(dest_reg, 24);
1294       }
1295       break;
1296     }
1297 
1298     case T_CHAR: {
1299       Register dest_reg = dest->as_register();
1300       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1301       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1302         __ movzwl(dest_reg, from_addr);
1303       } else {
1304         __ movw(dest_reg, from_addr);
1305       }
1306       break;
1307     }
1308 
1309     case T_SHORT: {
1310       Register dest_reg = dest->as_register();
1311       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1312         __ movswl(dest_reg, from_addr);
1313       } else {
1314         __ movw(dest_reg, from_addr);
1315         __ shll(dest_reg, 16);
1316         __ sarl(dest_reg, 16);
1317       }
1318       break;
1319     }
1320 
1321     default:
1322       ShouldNotReachHere();
1323   }
1324 
1325   if (patch != nullptr) {
1326     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1327   }
1328 
1329   if (is_reference_type(type)) {
1330 #ifdef _LP64
1331     if (UseCompressedOops && !wide) {
1332       __ decode_heap_oop(dest->as_register());
1333     }
1334 #endif
1335 
1336     if (!(UseZGC && !ZGenerational)) {
1337       // Load barrier has not yet been applied, so ZGC can't verify the oop here
1338       __ verify_oop(dest->as_register());
1339     }
1340   }
1341 }
1342 
1343 
1344 NEEDS_CLEANUP; // This could be static?
1345 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1346   int elem_size = type2aelembytes(type);
1347   switch (elem_size) {
1348     case 1: return Address::times_1;
1349     case 2: return Address::times_2;
1350     case 4: return Address::times_4;
1351     case 8: return Address::times_8;
1352   }
1353   ShouldNotReachHere();
1354   return Address::no_scale;
1355 }
1356 
1357 
1358 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1359   switch (op->code()) {
1360     case lir_idiv:
1361     case lir_irem:
1362       arithmetic_idiv(op->code(),
1363                       op->in_opr1(),
1364                       op->in_opr2(),
1365                       op->in_opr3(),
1366                       op->result_opr(),
1367                       op->info());
1368       break;
1369     case lir_fmad:
1370       __ fmad(op->result_opr()->as_xmm_double_reg(),
1371               op->in_opr1()->as_xmm_double_reg(),
1372               op->in_opr2()->as_xmm_double_reg(),
1373               op->in_opr3()->as_xmm_double_reg());
1374       break;
1375     case lir_fmaf:
1376       __ fmaf(op->result_opr()->as_xmm_float_reg(),
1377               op->in_opr1()->as_xmm_float_reg(),
1378               op->in_opr2()->as_xmm_float_reg(),
1379               op->in_opr3()->as_xmm_float_reg());
1380       break;
1381     default:      ShouldNotReachHere(); break;
1382   }
1383 }
1384 
1385 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1386 #ifdef ASSERT
1387   assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1388   if (op->block() != nullptr)  _branch_target_blocks.append(op->block());
1389   if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1390 #endif
1391 
1392   if (op->cond() == lir_cond_always) {
1393     if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1394     __ jmp (*(op->label()));
1395   } else {
1396     Assembler::Condition acond = Assembler::zero;
1397     if (op->code() == lir_cond_float_branch) {
1398       assert(op->ublock() != nullptr, "must have unordered successor");
1399       __ jcc(Assembler::parity, *(op->ublock()->label()));
1400       switch(op->cond()) {
1401         case lir_cond_equal:        acond = Assembler::equal;      break;
1402         case lir_cond_notEqual:     acond = Assembler::notEqual;   break;
1403         case lir_cond_less:         acond = Assembler::below;      break;
1404         case lir_cond_lessEqual:    acond = Assembler::belowEqual; break;
1405         case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1406         case lir_cond_greater:      acond = Assembler::above;      break;
1407         default:                         ShouldNotReachHere();
1408       }
1409     } else {
1410       switch (op->cond()) {
1411         case lir_cond_equal:        acond = Assembler::equal;       break;
1412         case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
1413         case lir_cond_less:         acond = Assembler::less;        break;
1414         case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
1415         case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1416         case lir_cond_greater:      acond = Assembler::greater;     break;
1417         case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
1418         case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
1419         default:                         ShouldNotReachHere();
1420       }
1421     }
1422     __ jcc(acond,*(op->label()));
1423   }
1424 }
1425 
1426 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1427   LIR_Opr src  = op->in_opr();
1428   LIR_Opr dest = op->result_opr();
1429 
1430   switch (op->bytecode()) {
1431     case Bytecodes::_i2l:
1432 #ifdef _LP64
1433       __ movl2ptr(dest->as_register_lo(), src->as_register());
1434 #else
1435       move_regs(src->as_register(), dest->as_register_lo());
1436       move_regs(src->as_register(), dest->as_register_hi());
1437       __ sarl(dest->as_register_hi(), 31);
1438 #endif // LP64
1439       break;
1440 
1441     case Bytecodes::_l2i:
1442 #ifdef _LP64
1443       __ movl(dest->as_register(), src->as_register_lo());
1444 #else
1445       move_regs(src->as_register_lo(), dest->as_register());
1446 #endif
1447       break;
1448 
1449     case Bytecodes::_i2b:
1450       move_regs(src->as_register(), dest->as_register());
1451       __ sign_extend_byte(dest->as_register());
1452       break;
1453 
1454     case Bytecodes::_i2c:
1455       move_regs(src->as_register(), dest->as_register());
1456       __ andl(dest->as_register(), 0xFFFF);
1457       break;
1458 
1459     case Bytecodes::_i2s:
1460       move_regs(src->as_register(), dest->as_register());
1461       __ sign_extend_short(dest->as_register());
1462       break;
1463 
1464 
1465 #ifdef _LP64
1466     case Bytecodes::_f2d:
1467       __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1468       break;
1469 
1470     case Bytecodes::_d2f:
1471       __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1472       break;
1473 
1474     case Bytecodes::_i2f:
1475       __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1476       break;
1477 
1478     case Bytecodes::_i2d:
1479       __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1480       break;
1481 
1482     case Bytecodes::_l2f:
1483       __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1484       break;
1485 
1486     case Bytecodes::_l2d:
1487       __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1488       break;
1489 
1490     case Bytecodes::_f2i:
1491       __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1492       break;
1493 
1494     case Bytecodes::_d2i:
1495       __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1496       break;
1497 
1498     case Bytecodes::_f2l:
1499       __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1500       break;
1501 
1502     case Bytecodes::_d2l:
1503       __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1504       break;
1505 #else
1506     case Bytecodes::_f2d:
1507     case Bytecodes::_d2f:
1508       if (dest->is_single_xmm()) {
1509         __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1510       } else if (dest->is_double_xmm()) {
1511         __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1512       } else {
1513         assert(src->fpu() == dest->fpu(), "register must be equal");
1514         // do nothing (float result is rounded later through spilling)
1515       }
1516       break;
1517 
1518     case Bytecodes::_i2f:
1519     case Bytecodes::_i2d:
1520       if (dest->is_single_xmm()) {
1521         __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1522       } else if (dest->is_double_xmm()) {
1523         __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1524       } else {
1525         assert(dest->fpu() == 0, "result must be on TOS");
1526         __ movl(Address(rsp, 0), src->as_register());
1527         __ fild_s(Address(rsp, 0));
1528       }
1529       break;
1530 
1531     case Bytecodes::_l2f:
1532     case Bytecodes::_l2d:
1533       assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1534       assert(dest->fpu() == 0, "result must be on TOS");
1535       __ movptr(Address(rsp, 0),          src->as_register_lo());
1536       __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1537       __ fild_d(Address(rsp, 0));
1538       // float result is rounded later through spilling
1539       break;
1540 
1541     case Bytecodes::_f2i:
1542     case Bytecodes::_d2i:
1543       if (src->is_single_xmm()) {
1544         __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1545       } else if (src->is_double_xmm()) {
1546         __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1547       } else {
1548         assert(src->fpu() == 0, "input must be on TOS");
1549         __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc()));
1550         __ fist_s(Address(rsp, 0));
1551         __ movl(dest->as_register(), Address(rsp, 0));
1552         __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
1553       }
1554       // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1555       assert(op->stub() != nullptr, "stub required");
1556       __ cmpl(dest->as_register(), 0x80000000);
1557       __ jcc(Assembler::equal, *op->stub()->entry());
1558       __ bind(*op->stub()->continuation());
1559       break;
1560 
1561     case Bytecodes::_f2l:
1562     case Bytecodes::_d2l:
1563       assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1564       assert(src->fpu() == 0, "input must be on TOS");
1565       assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1566 
1567       // instruction sequence too long to inline it here
1568       {
1569         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1570       }
1571       break;
1572 #endif // _LP64
1573 
1574     default: ShouldNotReachHere();
1575   }
1576 }
1577 
1578 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1579   if (op->init_check()) {
1580     add_debug_info_for_null_check_here(op->stub()->info());
1581     __ cmpb(Address(op->klass()->as_register(),
1582                     InstanceKlass::init_state_offset()),
1583                     InstanceKlass::fully_initialized);
1584     __ jcc(Assembler::notEqual, *op->stub()->entry());
1585   }
1586   __ allocate_object(op->obj()->as_register(),
1587                      op->tmp1()->as_register(),
1588                      op->tmp2()->as_register(),
1589                      op->header_size(),
1590                      op->object_size(),
1591                      op->klass()->as_register(),
1592                      *op->stub()->entry());
1593   __ bind(*op->stub()->continuation());
1594 }
1595 
1596 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1597   Register len =  op->len()->as_register();
1598   LP64_ONLY( __ movslq(len, len); )
1599 
1600   if (UseSlowPath ||
1601       (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1602       (!UseFastNewTypeArray   && !is_reference_type(op->type()))) {
1603     __ jmp(*op->stub()->entry());
1604   } else {
1605     Register tmp1 = op->tmp1()->as_register();
1606     Register tmp2 = op->tmp2()->as_register();
1607     Register tmp3 = op->tmp3()->as_register();
1608     if (len == tmp1) {
1609       tmp1 = tmp3;
1610     } else if (len == tmp2) {
1611       tmp2 = tmp3;
1612     } else if (len == tmp3) {
1613       // everything is ok
1614     } else {
1615       __ mov(tmp3, len);
1616     }
1617     __ allocate_array(op->obj()->as_register(),
1618                       len,
1619                       tmp1,
1620                       tmp2,
1621                       arrayOopDesc::header_size(op->type()),
1622                       array_element_size(op->type()),
1623                       op->klass()->as_register(),
1624                       *op->stub()->entry());
1625   }
1626   __ bind(*op->stub()->continuation());
1627 }
1628 
1629 void LIR_Assembler::type_profile_helper(Register mdo,
1630                                         ciMethodData *md, ciProfileData *data,
1631                                         Register recv, Label* update_done) {
1632   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1633     Label next_test;
1634     // See if the receiver is receiver[n].
1635     __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1636     __ jccb(Assembler::notEqual, next_test);
1637     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1638     __ addptr(data_addr, DataLayout::counter_increment);
1639     __ jmp(*update_done);
1640     __ bind(next_test);
1641   }
1642 
1643   // Didn't find receiver; find next empty slot and fill it in
1644   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1645     Label next_test;
1646     Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1647     __ cmpptr(recv_addr, NULL_WORD);
1648     __ jccb(Assembler::notEqual, next_test);
1649     __ movptr(recv_addr, recv);
1650     __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1651     __ jmp(*update_done);
1652     __ bind(next_test);
1653   }
1654 }
1655 
1656 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1657   // we always need a stub for the failure case.
1658   CodeStub* stub = op->stub();
1659   Register obj = op->object()->as_register();
1660   Register k_RInfo = op->tmp1()->as_register();
1661   Register klass_RInfo = op->tmp2()->as_register();
1662   Register dst = op->result_opr()->as_register();
1663   ciKlass* k = op->klass();
1664   Register Rtmp1 = noreg;
1665   Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1666 
1667   // check if it needs to be profiled
1668   ciMethodData* md = nullptr;
1669   ciProfileData* data = nullptr;
1670 
1671   if (op->should_profile()) {
1672     ciMethod* method = op->profiled_method();
1673     assert(method != nullptr, "Should have method");
1674     int bci = op->profiled_bci();
1675     md = method->method_data_or_null();
1676     assert(md != nullptr, "Sanity");
1677     data = md->bci_to_data(bci);
1678     assert(data != nullptr,                "need data for type check");
1679     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1680   }
1681   Label* success_target = success;
1682   Label* failure_target = failure;
1683 
1684   if (obj == k_RInfo) {
1685     k_RInfo = dst;
1686   } else if (obj == klass_RInfo) {
1687     klass_RInfo = dst;
1688   }
1689   if (k->is_loaded() && !UseCompressedClassPointers) {
1690     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1691   } else {
1692     Rtmp1 = op->tmp3()->as_register();
1693     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1694   }
1695 
1696   assert_different_registers(obj, k_RInfo, klass_RInfo);
1697 
1698   __ testptr(obj, obj);
1699   if (op->should_profile()) {
1700     Label not_null;
1701     Register mdo  = klass_RInfo;
1702     __ mov_metadata(mdo, md->constant_encoding());
1703     __ jccb(Assembler::notEqual, not_null);
1704     // Object is null; update MDO and exit
1705     Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1706     int header_bits = BitData::null_seen_byte_constant();
1707     __ orb(data_addr, header_bits);
1708     __ jmp(*obj_is_null);
1709     __ bind(not_null);
1710 
1711     Label update_done;
1712     Register recv = k_RInfo;
1713     __ load_klass(recv, obj, tmp_load_klass);
1714     type_profile_helper(mdo, md, data, recv, &update_done);
1715 
1716     Address nonprofiled_receiver_count_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1717     __ addptr(nonprofiled_receiver_count_addr, DataLayout::counter_increment);
1718 
1719     __ bind(update_done);
1720   } else {
1721     __ jcc(Assembler::equal, *obj_is_null);
1722   }
1723 
1724   if (!k->is_loaded()) {
1725     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1726   } else {
1727 #ifdef _LP64
1728     __ mov_metadata(k_RInfo, k->constant_encoding());
1729 #endif // _LP64
1730   }
1731   __ verify_oop(obj);
1732 
1733   if (op->fast_check()) {
1734     // get object class
1735     // not a safepoint as obj null check happens earlier
1736 #ifdef _LP64
1737     if (UseCompressedClassPointers) {
1738       __ load_klass(Rtmp1, obj, tmp_load_klass);
1739       __ cmpptr(k_RInfo, Rtmp1);
1740     } else {
1741       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1742     }
1743 #else
1744     if (k->is_loaded()) {
1745       __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1746     } else {
1747       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1748     }
1749 #endif
1750     __ jcc(Assembler::notEqual, *failure_target);
1751     // successful cast, fall through to profile or jump
1752   } else {
1753     // get object class
1754     // not a safepoint as obj null check happens earlier
1755     __ load_klass(klass_RInfo, obj, tmp_load_klass);
1756     if (k->is_loaded()) {
1757       // See if we get an immediate positive hit
1758 #ifdef _LP64
1759       __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1760 #else
1761       __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1762 #endif // _LP64
1763       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1764         __ jcc(Assembler::notEqual, *failure_target);
1765         // successful cast, fall through to profile or jump
1766       } else {
1767         // See if we get an immediate positive hit
1768         __ jcc(Assembler::equal, *success_target);
1769         // check for self
1770 #ifdef _LP64
1771         __ cmpptr(klass_RInfo, k_RInfo);
1772 #else
1773         __ cmpklass(klass_RInfo, k->constant_encoding());
1774 #endif // _LP64
1775         __ jcc(Assembler::equal, *success_target);
1776 
1777         __ push(klass_RInfo);
1778 #ifdef _LP64
1779         __ push(k_RInfo);
1780 #else
1781         __ pushklass(k->constant_encoding(), noreg);
1782 #endif // _LP64
1783         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1784         __ pop(klass_RInfo);
1785         __ pop(klass_RInfo);
1786         // result is a boolean
1787         __ testl(klass_RInfo, klass_RInfo);
1788         __ jcc(Assembler::equal, *failure_target);
1789         // successful cast, fall through to profile or jump
1790       }
1791     } else {
1792       // perform the fast part of the checking logic
1793       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1794       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1795       __ push(klass_RInfo);
1796       __ push(k_RInfo);
1797       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1798       __ pop(klass_RInfo);
1799       __ pop(k_RInfo);
1800       // result is a boolean
1801       __ testl(k_RInfo, k_RInfo);
1802       __ jcc(Assembler::equal, *failure_target);
1803       // successful cast, fall through to profile or jump
1804     }
1805   }
1806   __ jmp(*success);
1807 }
1808 
1809 
1810 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1811   Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1812   LIR_Code code = op->code();
1813   if (code == lir_store_check) {
1814     Register value = op->object()->as_register();
1815     Register array = op->array()->as_register();
1816     Register k_RInfo = op->tmp1()->as_register();
1817     Register klass_RInfo = op->tmp2()->as_register();
1818     Register Rtmp1 = op->tmp3()->as_register();
1819 
1820     CodeStub* stub = op->stub();
1821 
1822     // check if it needs to be profiled
1823     ciMethodData* md = nullptr;
1824     ciProfileData* data = nullptr;
1825 
1826     if (op->should_profile()) {
1827       ciMethod* method = op->profiled_method();
1828       assert(method != nullptr, "Should have method");
1829       int bci = op->profiled_bci();
1830       md = method->method_data_or_null();
1831       assert(md != nullptr, "Sanity");
1832       data = md->bci_to_data(bci);
1833       assert(data != nullptr,                "need data for type check");
1834       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1835     }
1836     Label done;
1837     Label* success_target = &done;
1838     Label* failure_target = stub->entry();
1839 
1840     __ testptr(value, value);
1841     if (op->should_profile()) {
1842       Label not_null;
1843       Register mdo  = klass_RInfo;
1844       __ mov_metadata(mdo, md->constant_encoding());
1845       __ jccb(Assembler::notEqual, not_null);
1846       // Object is null; update MDO and exit
1847       Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1848       int header_bits = BitData::null_seen_byte_constant();
1849       __ orb(data_addr, header_bits);
1850       __ jmp(done);
1851       __ bind(not_null);
1852 
1853       Label update_done;
1854       Register recv = k_RInfo;
1855       __ load_klass(recv, value, tmp_load_klass);
1856       type_profile_helper(mdo, md, data, recv, &update_done);
1857 
1858       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1859       __ addptr(counter_addr, DataLayout::counter_increment);
1860       __ bind(update_done);
1861     } else {
1862       __ jcc(Assembler::equal, done);
1863     }
1864 
1865     add_debug_info_for_null_check_here(op->info_for_exception());
1866     __ load_klass(k_RInfo, array, tmp_load_klass);
1867     __ load_klass(klass_RInfo, value, tmp_load_klass);
1868 
1869     // get instance klass (it's already uncompressed)
1870     __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1871     // perform the fast part of the checking logic
1872     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1873     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1874     __ push(klass_RInfo);
1875     __ push(k_RInfo);
1876     __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1877     __ pop(klass_RInfo);
1878     __ pop(k_RInfo);
1879     // result is a boolean
1880     __ testl(k_RInfo, k_RInfo);
1881     __ jcc(Assembler::equal, *failure_target);
1882     // fall through to the success case
1883 
1884     __ bind(done);
1885   } else
1886     if (code == lir_checkcast) {
1887       Register obj = op->object()->as_register();
1888       Register dst = op->result_opr()->as_register();
1889       Label success;
1890       emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1891       __ bind(success);
1892       if (dst != obj) {
1893         __ mov(dst, obj);
1894       }
1895     } else
1896       if (code == lir_instanceof) {
1897         Register obj = op->object()->as_register();
1898         Register dst = op->result_opr()->as_register();
1899         Label success, failure, done;
1900         emit_typecheck_helper(op, &success, &failure, &failure);
1901         __ bind(failure);
1902         __ xorptr(dst, dst);
1903         __ jmpb(done);
1904         __ bind(success);
1905         __ movptr(dst, 1);
1906         __ bind(done);
1907       } else {
1908         ShouldNotReachHere();
1909       }
1910 
1911 }
1912 
1913 
1914 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1915   if (LP64_ONLY(false &&) op->code() == lir_cas_long) {
1916     assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1917     assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1918     assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1919     assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1920     Register addr = op->addr()->as_register();
1921     __ lock();
1922     NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1923 
1924   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1925     NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1926     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1927     Register newval = op->new_value()->as_register();
1928     Register cmpval = op->cmp_value()->as_register();
1929     assert(cmpval == rax, "wrong register");
1930     assert(newval != noreg, "new val must be register");
1931     assert(cmpval != newval, "cmp and new values must be in different registers");
1932     assert(cmpval != addr, "cmp and addr must be in different registers");
1933     assert(newval != addr, "new value and addr must be in different registers");
1934 
1935     if ( op->code() == lir_cas_obj) {
1936 #ifdef _LP64
1937       if (UseCompressedOops) {
1938         __ encode_heap_oop(cmpval);
1939         __ mov(rscratch1, newval);
1940         __ encode_heap_oop(rscratch1);
1941         __ lock();
1942         // cmpval (rax) is implicitly used by this instruction
1943         __ cmpxchgl(rscratch1, Address(addr, 0));
1944       } else
1945 #endif
1946       {
1947         __ lock();
1948         __ cmpxchgptr(newval, Address(addr, 0));
1949       }
1950     } else {
1951       assert(op->code() == lir_cas_int, "lir_cas_int expected");
1952       __ lock();
1953       __ cmpxchgl(newval, Address(addr, 0));
1954     }
1955 #ifdef _LP64
1956   } else if (op->code() == lir_cas_long) {
1957     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1958     Register newval = op->new_value()->as_register_lo();
1959     Register cmpval = op->cmp_value()->as_register_lo();
1960     assert(cmpval == rax, "wrong register");
1961     assert(newval != noreg, "new val must be register");
1962     assert(cmpval != newval, "cmp and new values must be in different registers");
1963     assert(cmpval != addr, "cmp and addr must be in different registers");
1964     assert(newval != addr, "new value and addr must be in different registers");
1965     __ lock();
1966     __ cmpxchgq(newval, Address(addr, 0));
1967 #endif // _LP64
1968   } else {
1969     Unimplemented();
1970   }
1971 }
1972 
1973 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1974                           LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1975   assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
1976 
1977   Assembler::Condition acond, ncond;
1978   switch (condition) {
1979     case lir_cond_equal:        acond = Assembler::equal;        ncond = Assembler::notEqual;     break;
1980     case lir_cond_notEqual:     acond = Assembler::notEqual;     ncond = Assembler::equal;        break;
1981     case lir_cond_less:         acond = Assembler::less;         ncond = Assembler::greaterEqual; break;
1982     case lir_cond_lessEqual:    acond = Assembler::lessEqual;    ncond = Assembler::greater;      break;
1983     case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less;         break;
1984     case lir_cond_greater:      acond = Assembler::greater;      ncond = Assembler::lessEqual;    break;
1985     case lir_cond_belowEqual:   acond = Assembler::belowEqual;   ncond = Assembler::above;        break;
1986     case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;   ncond = Assembler::below;        break;
1987     default:                    acond = Assembler::equal;        ncond = Assembler::notEqual;
1988                                 ShouldNotReachHere();
1989   }
1990 
1991   if (opr1->is_cpu_register()) {
1992     reg2reg(opr1, result);
1993   } else if (opr1->is_stack()) {
1994     stack2reg(opr1, result, result->type());
1995   } else if (opr1->is_constant()) {
1996     const2reg(opr1, result, lir_patch_none, nullptr);
1997   } else {
1998     ShouldNotReachHere();
1999   }
2000 
2001   if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2002     // optimized version that does not require a branch
2003     if (opr2->is_single_cpu()) {
2004       assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2005       __ cmov(ncond, result->as_register(), opr2->as_register());
2006     } else if (opr2->is_double_cpu()) {
2007       assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2008       assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2009       __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2010       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2011     } else if (opr2->is_single_stack()) {
2012       __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2013     } else if (opr2->is_double_stack()) {
2014       __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2015       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2016     } else {
2017       ShouldNotReachHere();
2018     }
2019 
2020   } else {
2021     Label skip;
2022     __ jccb(acond, skip);
2023     if (opr2->is_cpu_register()) {
2024       reg2reg(opr2, result);
2025     } else if (opr2->is_stack()) {
2026       stack2reg(opr2, result, result->type());
2027     } else if (opr2->is_constant()) {
2028       const2reg(opr2, result, lir_patch_none, nullptr);
2029     } else {
2030       ShouldNotReachHere();
2031     }
2032     __ bind(skip);
2033   }
2034 }
2035 
2036 
2037 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2038   assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2039 
2040   if (left->is_single_cpu()) {
2041     assert(left == dest, "left and dest must be equal");
2042     Register lreg = left->as_register();
2043 
2044     if (right->is_single_cpu()) {
2045       // cpu register - cpu register
2046       Register rreg = right->as_register();
2047       switch (code) {
2048         case lir_add: __ addl (lreg, rreg); break;
2049         case lir_sub: __ subl (lreg, rreg); break;
2050         case lir_mul: __ imull(lreg, rreg); break;
2051         default:      ShouldNotReachHere();
2052       }
2053 
2054     } else if (right->is_stack()) {
2055       // cpu register - stack
2056       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2057       switch (code) {
2058         case lir_add: __ addl(lreg, raddr); break;
2059         case lir_sub: __ subl(lreg, raddr); break;
2060         default:      ShouldNotReachHere();
2061       }
2062 
2063     } else if (right->is_constant()) {
2064       // cpu register - constant
2065       jint c = right->as_constant_ptr()->as_jint();
2066       switch (code) {
2067         case lir_add: {
2068           __ incrementl(lreg, c);
2069           break;
2070         }
2071         case lir_sub: {
2072           __ decrementl(lreg, c);
2073           break;
2074         }
2075         default: ShouldNotReachHere();
2076       }
2077 
2078     } else {
2079       ShouldNotReachHere();
2080     }
2081 
2082   } else if (left->is_double_cpu()) {
2083     assert(left == dest, "left and dest must be equal");
2084     Register lreg_lo = left->as_register_lo();
2085     Register lreg_hi = left->as_register_hi();
2086 
2087     if (right->is_double_cpu()) {
2088       // cpu register - cpu register
2089       Register rreg_lo = right->as_register_lo();
2090       Register rreg_hi = right->as_register_hi();
2091       NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2092       LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2093       switch (code) {
2094         case lir_add:
2095           __ addptr(lreg_lo, rreg_lo);
2096           NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2097           break;
2098         case lir_sub:
2099           __ subptr(lreg_lo, rreg_lo);
2100           NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2101           break;
2102         case lir_mul:
2103 #ifdef _LP64
2104           __ imulq(lreg_lo, rreg_lo);
2105 #else
2106           assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2107           __ imull(lreg_hi, rreg_lo);
2108           __ imull(rreg_hi, lreg_lo);
2109           __ addl (rreg_hi, lreg_hi);
2110           __ mull (rreg_lo);
2111           __ addl (lreg_hi, rreg_hi);
2112 #endif // _LP64
2113           break;
2114         default:
2115           ShouldNotReachHere();
2116       }
2117 
2118     } else if (right->is_constant()) {
2119       // cpu register - constant
2120 #ifdef _LP64
2121       jlong c = right->as_constant_ptr()->as_jlong_bits();
2122       __ movptr(r10, (intptr_t) c);
2123       switch (code) {
2124         case lir_add:
2125           __ addptr(lreg_lo, r10);
2126           break;
2127         case lir_sub:
2128           __ subptr(lreg_lo, r10);
2129           break;
2130         default:
2131           ShouldNotReachHere();
2132       }
2133 #else
2134       jint c_lo = right->as_constant_ptr()->as_jint_lo();
2135       jint c_hi = right->as_constant_ptr()->as_jint_hi();
2136       switch (code) {
2137         case lir_add:
2138           __ addptr(lreg_lo, c_lo);
2139           __ adcl(lreg_hi, c_hi);
2140           break;
2141         case lir_sub:
2142           __ subptr(lreg_lo, c_lo);
2143           __ sbbl(lreg_hi, c_hi);
2144           break;
2145         default:
2146           ShouldNotReachHere();
2147       }
2148 #endif // _LP64
2149 
2150     } else {
2151       ShouldNotReachHere();
2152     }
2153 
2154   } else if (left->is_single_xmm()) {
2155     assert(left == dest, "left and dest must be equal");
2156     XMMRegister lreg = left->as_xmm_float_reg();
2157 
2158     if (right->is_single_xmm()) {
2159       XMMRegister rreg = right->as_xmm_float_reg();
2160       switch (code) {
2161         case lir_add: __ addss(lreg, rreg);  break;
2162         case lir_sub: __ subss(lreg, rreg);  break;
2163         case lir_mul: __ mulss(lreg, rreg);  break;
2164         case lir_div: __ divss(lreg, rreg);  break;
2165         default: ShouldNotReachHere();
2166       }
2167     } else {
2168       Address raddr;
2169       if (right->is_single_stack()) {
2170         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2171       } else if (right->is_constant()) {
2172         // hack for now
2173         raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2174       } else {
2175         ShouldNotReachHere();
2176       }
2177       switch (code) {
2178         case lir_add: __ addss(lreg, raddr);  break;
2179         case lir_sub: __ subss(lreg, raddr);  break;
2180         case lir_mul: __ mulss(lreg, raddr);  break;
2181         case lir_div: __ divss(lreg, raddr);  break;
2182         default: ShouldNotReachHere();
2183       }
2184     }
2185 
2186   } else if (left->is_double_xmm()) {
2187     assert(left == dest, "left and dest must be equal");
2188 
2189     XMMRegister lreg = left->as_xmm_double_reg();
2190     if (right->is_double_xmm()) {
2191       XMMRegister rreg = right->as_xmm_double_reg();
2192       switch (code) {
2193         case lir_add: __ addsd(lreg, rreg);  break;
2194         case lir_sub: __ subsd(lreg, rreg);  break;
2195         case lir_mul: __ mulsd(lreg, rreg);  break;
2196         case lir_div: __ divsd(lreg, rreg);  break;
2197         default: ShouldNotReachHere();
2198       }
2199     } else {
2200       Address raddr;
2201       if (right->is_double_stack()) {
2202         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2203       } else if (right->is_constant()) {
2204         // hack for now
2205         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2206       } else {
2207         ShouldNotReachHere();
2208       }
2209       switch (code) {
2210         case lir_add: __ addsd(lreg, raddr);  break;
2211         case lir_sub: __ subsd(lreg, raddr);  break;
2212         case lir_mul: __ mulsd(lreg, raddr);  break;
2213         case lir_div: __ divsd(lreg, raddr);  break;
2214         default: ShouldNotReachHere();
2215       }
2216     }
2217 
2218 #ifndef _LP64
2219   } else if (left->is_single_fpu()) {
2220     assert(dest->is_single_fpu(),  "fpu stack allocation required");
2221 
2222     if (right->is_single_fpu()) {
2223       arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2224 
2225     } else {
2226       assert(left->fpu_regnr() == 0, "left must be on TOS");
2227       assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2228 
2229       Address raddr;
2230       if (right->is_single_stack()) {
2231         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2232       } else if (right->is_constant()) {
2233         address const_addr = float_constant(right->as_jfloat());
2234         assert(const_addr != nullptr, "incorrect float/double constant maintenance");
2235         // hack for now
2236         raddr = __ as_Address(InternalAddress(const_addr));
2237       } else {
2238         ShouldNotReachHere();
2239       }
2240 
2241       switch (code) {
2242         case lir_add: __ fadd_s(raddr); break;
2243         case lir_sub: __ fsub_s(raddr); break;
2244         case lir_mul: __ fmul_s(raddr); break;
2245         case lir_div: __ fdiv_s(raddr); break;
2246         default:      ShouldNotReachHere();
2247       }
2248     }
2249 
2250   } else if (left->is_double_fpu()) {
2251     assert(dest->is_double_fpu(),  "fpu stack allocation required");
2252 
2253     if (code == lir_mul || code == lir_div) {
2254       // Double values require special handling for strictfp mul/div on x86
2255       __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1()));
2256       __ fmulp(left->fpu_regnrLo() + 1);
2257     }
2258 
2259     if (right->is_double_fpu()) {
2260       arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2261 
2262     } else {
2263       assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2264       assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2265 
2266       Address raddr;
2267       if (right->is_double_stack()) {
2268         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2269       } else if (right->is_constant()) {
2270         // hack for now
2271         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2272       } else {
2273         ShouldNotReachHere();
2274       }
2275 
2276       switch (code) {
2277         case lir_add: __ fadd_d(raddr); break;
2278         case lir_sub: __ fsub_d(raddr); break;
2279         case lir_mul: __ fmul_d(raddr); break;
2280         case lir_div: __ fdiv_d(raddr); break;
2281         default: ShouldNotReachHere();
2282       }
2283     }
2284 
2285     if (code == lir_mul || code == lir_div) {
2286       // Double values require special handling for strictfp mul/div on x86
2287       __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2()));
2288       __ fmulp(dest->fpu_regnrLo() + 1);
2289     }
2290 #endif // !_LP64
2291 
2292   } else if (left->is_single_stack() || left->is_address()) {
2293     assert(left == dest, "left and dest must be equal");
2294 
2295     Address laddr;
2296     if (left->is_single_stack()) {
2297       laddr = frame_map()->address_for_slot(left->single_stack_ix());
2298     } else if (left->is_address()) {
2299       laddr = as_Address(left->as_address_ptr());
2300     } else {
2301       ShouldNotReachHere();
2302     }
2303 
2304     if (right->is_single_cpu()) {
2305       Register rreg = right->as_register();
2306       switch (code) {
2307         case lir_add: __ addl(laddr, rreg); break;
2308         case lir_sub: __ subl(laddr, rreg); break;
2309         default:      ShouldNotReachHere();
2310       }
2311     } else if (right->is_constant()) {
2312       jint c = right->as_constant_ptr()->as_jint();
2313       switch (code) {
2314         case lir_add: {
2315           __ incrementl(laddr, c);
2316           break;
2317         }
2318         case lir_sub: {
2319           __ decrementl(laddr, c);
2320           break;
2321         }
2322         default: ShouldNotReachHere();
2323       }
2324     } else {
2325       ShouldNotReachHere();
2326     }
2327 
2328   } else {
2329     ShouldNotReachHere();
2330   }
2331 }
2332 
2333 #ifndef _LP64
2334 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2335   assert(pop_fpu_stack  || (left_index     == dest_index || right_index     == dest_index), "invalid LIR");
2336   assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2337   assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2338 
2339   bool left_is_tos = (left_index == 0);
2340   bool dest_is_tos = (dest_index == 0);
2341   int non_tos_index = (left_is_tos ? right_index : left_index);
2342 
2343   switch (code) {
2344     case lir_add:
2345       if (pop_fpu_stack)       __ faddp(non_tos_index);
2346       else if (dest_is_tos)    __ fadd (non_tos_index);
2347       else                     __ fadda(non_tos_index);
2348       break;
2349 
2350     case lir_sub:
2351       if (left_is_tos) {
2352         if (pop_fpu_stack)     __ fsubrp(non_tos_index);
2353         else if (dest_is_tos)  __ fsub  (non_tos_index);
2354         else                   __ fsubra(non_tos_index);
2355       } else {
2356         if (pop_fpu_stack)     __ fsubp (non_tos_index);
2357         else if (dest_is_tos)  __ fsubr (non_tos_index);
2358         else                   __ fsuba (non_tos_index);
2359       }
2360       break;
2361 
2362     case lir_mul:
2363       if (pop_fpu_stack)       __ fmulp(non_tos_index);
2364       else if (dest_is_tos)    __ fmul (non_tos_index);
2365       else                     __ fmula(non_tos_index);
2366       break;
2367 
2368     case lir_div:
2369       if (left_is_tos) {
2370         if (pop_fpu_stack)     __ fdivrp(non_tos_index);
2371         else if (dest_is_tos)  __ fdiv  (non_tos_index);
2372         else                   __ fdivra(non_tos_index);
2373       } else {
2374         if (pop_fpu_stack)     __ fdivp (non_tos_index);
2375         else if (dest_is_tos)  __ fdivr (non_tos_index);
2376         else                   __ fdiva (non_tos_index);
2377       }
2378       break;
2379 
2380     case lir_rem:
2381       assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2382       __ fremr(noreg);
2383       break;
2384 
2385     default:
2386       ShouldNotReachHere();
2387   }
2388 }
2389 #endif // _LP64
2390 
2391 
2392 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2393   if (value->is_double_xmm()) {
2394     switch(code) {
2395       case lir_abs :
2396         {
2397 #ifdef _LP64
2398           if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2399             assert(tmp->is_valid(), "need temporary");
2400             __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2401           } else
2402 #endif
2403           {
2404             if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2405               __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2406             }
2407             assert(!tmp->is_valid(), "do not need temporary");
2408             __ andpd(dest->as_xmm_double_reg(),
2409                      ExternalAddress((address)double_signmask_pool),
2410                      rscratch1);
2411           }
2412         }
2413         break;
2414 
2415       case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2416       // all other intrinsics are not available in the SSE instruction set, so FPU is used
2417       default      : ShouldNotReachHere();
2418     }
2419 
2420 #ifndef _LP64
2421   } else if (value->is_double_fpu()) {
2422     assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2423     switch(code) {
2424       case lir_abs   : __ fabs() ; break;
2425       case lir_sqrt  : __ fsqrt(); break;
2426       default      : ShouldNotReachHere();
2427     }
2428 #endif // !_LP64
2429   } else if (code == lir_f2hf) {
2430     __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg());
2431   } else if (code == lir_hf2f) {
2432     __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register());
2433   } else {
2434     Unimplemented();
2435   }
2436 }
2437 
2438 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2439   // assert(left->destroys_register(), "check");
2440   if (left->is_single_cpu()) {
2441     Register reg = left->as_register();
2442     if (right->is_constant()) {
2443       int val = right->as_constant_ptr()->as_jint();
2444       switch (code) {
2445         case lir_logic_and: __ andl (reg, val); break;
2446         case lir_logic_or:  __ orl  (reg, val); break;
2447         case lir_logic_xor: __ xorl (reg, val); break;
2448         default: ShouldNotReachHere();
2449       }
2450     } else if (right->is_stack()) {
2451       // added support for stack operands
2452       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2453       switch (code) {
2454         case lir_logic_and: __ andl (reg, raddr); break;
2455         case lir_logic_or:  __ orl  (reg, raddr); break;
2456         case lir_logic_xor: __ xorl (reg, raddr); break;
2457         default: ShouldNotReachHere();
2458       }
2459     } else {
2460       Register rright = right->as_register();
2461       switch (code) {
2462         case lir_logic_and: __ andptr (reg, rright); break;
2463         case lir_logic_or : __ orptr  (reg, rright); break;
2464         case lir_logic_xor: __ xorptr (reg, rright); break;
2465         default: ShouldNotReachHere();
2466       }
2467     }
2468     move_regs(reg, dst->as_register());
2469   } else {
2470     Register l_lo = left->as_register_lo();
2471     Register l_hi = left->as_register_hi();
2472     if (right->is_constant()) {
2473 #ifdef _LP64
2474       __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2475       switch (code) {
2476         case lir_logic_and:
2477           __ andq(l_lo, rscratch1);
2478           break;
2479         case lir_logic_or:
2480           __ orq(l_lo, rscratch1);
2481           break;
2482         case lir_logic_xor:
2483           __ xorq(l_lo, rscratch1);
2484           break;
2485         default: ShouldNotReachHere();
2486       }
2487 #else
2488       int r_lo = right->as_constant_ptr()->as_jint_lo();
2489       int r_hi = right->as_constant_ptr()->as_jint_hi();
2490       switch (code) {
2491         case lir_logic_and:
2492           __ andl(l_lo, r_lo);
2493           __ andl(l_hi, r_hi);
2494           break;
2495         case lir_logic_or:
2496           __ orl(l_lo, r_lo);
2497           __ orl(l_hi, r_hi);
2498           break;
2499         case lir_logic_xor:
2500           __ xorl(l_lo, r_lo);
2501           __ xorl(l_hi, r_hi);
2502           break;
2503         default: ShouldNotReachHere();
2504       }
2505 #endif // _LP64
2506     } else {
2507 #ifdef _LP64
2508       Register r_lo;
2509       if (is_reference_type(right->type())) {
2510         r_lo = right->as_register();
2511       } else {
2512         r_lo = right->as_register_lo();
2513       }
2514 #else
2515       Register r_lo = right->as_register_lo();
2516       Register r_hi = right->as_register_hi();
2517       assert(l_lo != r_hi, "overwriting registers");
2518 #endif
2519       switch (code) {
2520         case lir_logic_and:
2521           __ andptr(l_lo, r_lo);
2522           NOT_LP64(__ andptr(l_hi, r_hi);)
2523           break;
2524         case lir_logic_or:
2525           __ orptr(l_lo, r_lo);
2526           NOT_LP64(__ orptr(l_hi, r_hi);)
2527           break;
2528         case lir_logic_xor:
2529           __ xorptr(l_lo, r_lo);
2530           NOT_LP64(__ xorptr(l_hi, r_hi);)
2531           break;
2532         default: ShouldNotReachHere();
2533       }
2534     }
2535 
2536     Register dst_lo = dst->as_register_lo();
2537     Register dst_hi = dst->as_register_hi();
2538 
2539 #ifdef _LP64
2540     move_regs(l_lo, dst_lo);
2541 #else
2542     if (dst_lo == l_hi) {
2543       assert(dst_hi != l_lo, "overwriting registers");
2544       move_regs(l_hi, dst_hi);
2545       move_regs(l_lo, dst_lo);
2546     } else {
2547       assert(dst_lo != l_hi, "overwriting registers");
2548       move_regs(l_lo, dst_lo);
2549       move_regs(l_hi, dst_hi);
2550     }
2551 #endif // _LP64
2552   }
2553 }
2554 
2555 
2556 // we assume that rax, and rdx can be overwritten
2557 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2558 
2559   assert(left->is_single_cpu(),   "left must be register");
2560   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
2561   assert(result->is_single_cpu(), "result must be register");
2562 
2563   //  assert(left->destroys_register(), "check");
2564   //  assert(right->destroys_register(), "check");
2565 
2566   Register lreg = left->as_register();
2567   Register dreg = result->as_register();
2568 
2569   if (right->is_constant()) {
2570     jint divisor = right->as_constant_ptr()->as_jint();
2571     assert(divisor > 0 && is_power_of_2(divisor), "must be");
2572     if (code == lir_idiv) {
2573       assert(lreg == rax, "must be rax,");
2574       assert(temp->as_register() == rdx, "tmp register must be rdx");
2575       __ cdql(); // sign extend into rdx:rax
2576       if (divisor == 2) {
2577         __ subl(lreg, rdx);
2578       } else {
2579         __ andl(rdx, divisor - 1);
2580         __ addl(lreg, rdx);
2581       }
2582       __ sarl(lreg, log2i_exact(divisor));
2583       move_regs(lreg, dreg);
2584     } else if (code == lir_irem) {
2585       Label done;
2586       __ mov(dreg, lreg);
2587       __ andl(dreg, 0x80000000 | (divisor - 1));
2588       __ jcc(Assembler::positive, done);
2589       __ decrement(dreg);
2590       __ orl(dreg, ~(divisor - 1));
2591       __ increment(dreg);
2592       __ bind(done);
2593     } else {
2594       ShouldNotReachHere();
2595     }
2596   } else {
2597     Register rreg = right->as_register();
2598     assert(lreg == rax, "left register must be rax,");
2599     assert(rreg != rdx, "right register must not be rdx");
2600     assert(temp->as_register() == rdx, "tmp register must be rdx");
2601 
2602     move_regs(lreg, rax);
2603 
2604     int idivl_offset = __ corrected_idivl(rreg);
2605     if (ImplicitDiv0Checks) {
2606       add_debug_info_for_div0(idivl_offset, info);
2607     }
2608     if (code == lir_irem) {
2609       move_regs(rdx, dreg); // result is in rdx
2610     } else {
2611       move_regs(rax, dreg);
2612     }
2613   }
2614 }
2615 
2616 
2617 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2618   if (opr1->is_single_cpu()) {
2619     Register reg1 = opr1->as_register();
2620     if (opr2->is_single_cpu()) {
2621       // cpu register - cpu register
2622       if (is_reference_type(opr1->type())) {
2623         __ cmpoop(reg1, opr2->as_register());
2624       } else {
2625         assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2626         __ cmpl(reg1, opr2->as_register());
2627       }
2628     } else if (opr2->is_stack()) {
2629       // cpu register - stack
2630       if (is_reference_type(opr1->type())) {
2631         __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2632       } else {
2633         __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2634       }
2635     } else if (opr2->is_constant()) {
2636       // cpu register - constant
2637       LIR_Const* c = opr2->as_constant_ptr();
2638       if (c->type() == T_INT) {
2639         jint i = c->as_jint();
2640         if (i == 0) {
2641           __ testl(reg1, reg1);
2642         } else {
2643           __ cmpl(reg1, i);
2644         }
2645       } else if (c->type() == T_METADATA) {
2646         // All we need for now is a comparison with null for equality.
2647         assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2648         Metadata* m = c->as_metadata();
2649         if (m == nullptr) {
2650           __ testptr(reg1, reg1);
2651         } else {
2652           ShouldNotReachHere();
2653         }
2654       } else if (is_reference_type(c->type())) {
2655         // In 64bit oops are single register
2656         jobject o = c->as_jobject();
2657         if (o == nullptr) {
2658           __ testptr(reg1, reg1);
2659         } else {
2660           __ cmpoop(reg1, o, rscratch1);
2661         }
2662       } else {
2663         fatal("unexpected type: %s", basictype_to_str(c->type()));
2664       }
2665       // cpu register - address
2666     } else if (opr2->is_address()) {
2667       if (op->info() != nullptr) {
2668         add_debug_info_for_null_check_here(op->info());
2669       }
2670       __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2671     } else {
2672       ShouldNotReachHere();
2673     }
2674 
2675   } else if(opr1->is_double_cpu()) {
2676     Register xlo = opr1->as_register_lo();
2677     Register xhi = opr1->as_register_hi();
2678     if (opr2->is_double_cpu()) {
2679 #ifdef _LP64
2680       __ cmpptr(xlo, opr2->as_register_lo());
2681 #else
2682       // cpu register - cpu register
2683       Register ylo = opr2->as_register_lo();
2684       Register yhi = opr2->as_register_hi();
2685       __ subl(xlo, ylo);
2686       __ sbbl(xhi, yhi);
2687       if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2688         __ orl(xhi, xlo);
2689       }
2690 #endif // _LP64
2691     } else if (opr2->is_constant()) {
2692       // cpu register - constant 0
2693       assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2694 #ifdef _LP64
2695       __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2696 #else
2697       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2698       __ orl(xhi, xlo);
2699 #endif // _LP64
2700     } else {
2701       ShouldNotReachHere();
2702     }
2703 
2704   } else if (opr1->is_single_xmm()) {
2705     XMMRegister reg1 = opr1->as_xmm_float_reg();
2706     if (opr2->is_single_xmm()) {
2707       // xmm register - xmm register
2708       __ ucomiss(reg1, opr2->as_xmm_float_reg());
2709     } else if (opr2->is_stack()) {
2710       // xmm register - stack
2711       __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2712     } else if (opr2->is_constant()) {
2713       // xmm register - constant
2714       __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2715     } else if (opr2->is_address()) {
2716       // xmm register - address
2717       if (op->info() != nullptr) {
2718         add_debug_info_for_null_check_here(op->info());
2719       }
2720       __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2721     } else {
2722       ShouldNotReachHere();
2723     }
2724 
2725   } else if (opr1->is_double_xmm()) {
2726     XMMRegister reg1 = opr1->as_xmm_double_reg();
2727     if (opr2->is_double_xmm()) {
2728       // xmm register - xmm register
2729       __ ucomisd(reg1, opr2->as_xmm_double_reg());
2730     } else if (opr2->is_stack()) {
2731       // xmm register - stack
2732       __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2733     } else if (opr2->is_constant()) {
2734       // xmm register - constant
2735       __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2736     } else if (opr2->is_address()) {
2737       // xmm register - address
2738       if (op->info() != nullptr) {
2739         add_debug_info_for_null_check_here(op->info());
2740       }
2741       __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2742     } else {
2743       ShouldNotReachHere();
2744     }
2745 
2746 #ifndef _LP64
2747   } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2748     assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2749     assert(opr2->is_fpu_register(), "both must be registers");
2750     __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2751 #endif // LP64
2752 
2753   } else if (opr1->is_address() && opr2->is_constant()) {
2754     LIR_Const* c = opr2->as_constant_ptr();
2755 #ifdef _LP64
2756     if (is_reference_type(c->type())) {
2757       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2758       __ movoop(rscratch1, c->as_jobject());
2759     }
2760 #endif // LP64
2761     if (op->info() != nullptr) {
2762       add_debug_info_for_null_check_here(op->info());
2763     }
2764     // special case: address - constant
2765     LIR_Address* addr = opr1->as_address_ptr();
2766     if (c->type() == T_INT) {
2767       __ cmpl(as_Address(addr), c->as_jint());
2768     } else if (is_reference_type(c->type())) {
2769 #ifdef _LP64
2770       // %%% Make this explode if addr isn't reachable until we figure out a
2771       // better strategy by giving noreg as the temp for as_Address
2772       __ cmpoop(rscratch1, as_Address(addr, noreg));
2773 #else
2774       __ cmpoop(as_Address(addr), c->as_jobject());
2775 #endif // _LP64
2776     } else {
2777       ShouldNotReachHere();
2778     }
2779 
2780   } else {
2781     ShouldNotReachHere();
2782   }
2783 }
2784 
2785 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2786   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2787     if (left->is_single_xmm()) {
2788       assert(right->is_single_xmm(), "must match");
2789       __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2790     } else if (left->is_double_xmm()) {
2791       assert(right->is_double_xmm(), "must match");
2792       __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2793 
2794     } else {
2795 #ifdef _LP64
2796       ShouldNotReachHere();
2797 #else
2798       assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2799       assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2800 
2801       assert(left->fpu() == 0, "left must be on TOS");
2802       __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2803                   op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2804 #endif // LP64
2805     }
2806   } else {
2807     assert(code == lir_cmp_l2i, "check");
2808 #ifdef _LP64
2809     Label done;
2810     Register dest = dst->as_register();
2811     __ cmpptr(left->as_register_lo(), right->as_register_lo());
2812     __ movl(dest, -1);
2813     __ jccb(Assembler::less, done);
2814     __ setb(Assembler::notZero, dest);
2815     __ movzbl(dest, dest);
2816     __ bind(done);
2817 #else
2818     __ lcmp2int(left->as_register_hi(),
2819                 left->as_register_lo(),
2820                 right->as_register_hi(),
2821                 right->as_register_lo());
2822     move_regs(left->as_register_hi(), dst->as_register());
2823 #endif // _LP64
2824   }
2825 }
2826 
2827 
2828 void LIR_Assembler::align_call(LIR_Code code) {
2829   // make sure that the displacement word of the call ends up word aligned
2830   int offset = __ offset();
2831   switch (code) {
2832   case lir_static_call:
2833   case lir_optvirtual_call:
2834   case lir_dynamic_call:
2835     offset += NativeCall::displacement_offset;
2836     break;
2837   case lir_icvirtual_call:
2838     offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2839     break;
2840   default: ShouldNotReachHere();
2841   }
2842   __ align(BytesPerWord, offset);
2843 }
2844 
2845 
2846 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2847   assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2848          "must be aligned");
2849   __ call(AddressLiteral(op->addr(), rtype));
2850   add_call_info(code_offset(), op->info());
2851   __ post_call_nop();
2852 }
2853 
2854 
2855 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2856   __ ic_call(op->addr());
2857   add_call_info(code_offset(), op->info());
2858   assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2859          "must be aligned");
2860   __ post_call_nop();
2861 }
2862 
2863 
2864 void LIR_Assembler::emit_static_call_stub() {
2865   address call_pc = __ pc();
2866   address stub = __ start_a_stub(call_stub_size());
2867   if (stub == nullptr) {
2868     bailout("static call stub overflow");
2869     return;
2870   }
2871 
2872   int start = __ offset();
2873 
2874   // make sure that the displacement word of the call ends up word aligned
2875   __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2876   __ relocate(static_stub_Relocation::spec(call_pc));
2877   __ mov_metadata(rbx, (Metadata*)nullptr);
2878   // must be set to -1 at code generation time
2879   assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2880   // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2881   __ jump(RuntimeAddress(__ pc()));
2882 
2883   assert(__ offset() - start <= call_stub_size(), "stub too big");
2884   __ end_a_stub();
2885 }
2886 
2887 
2888 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2889   assert(exceptionOop->as_register() == rax, "must match");
2890   assert(exceptionPC->as_register() == rdx, "must match");
2891 
2892   // exception object is not added to oop map by LinearScan
2893   // (LinearScan assumes that no oops are in fixed registers)
2894   info->add_register_oop(exceptionOop);
2895   Runtime1::StubID unwind_id;
2896 
2897   // get current pc information
2898   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2899   int pc_for_athrow_offset = __ offset();
2900   InternalAddress pc_for_athrow(__ pc());
2901   __ lea(exceptionPC->as_register(), pc_for_athrow);
2902   add_call_info(pc_for_athrow_offset, info); // for exception handler
2903 
2904   __ verify_not_null_oop(rax);
2905   // search an exception handler (rax: exception oop, rdx: throwing pc)
2906   if (compilation()->has_fpu_code()) {
2907     unwind_id = Runtime1::handle_exception_id;
2908   } else {
2909     unwind_id = Runtime1::handle_exception_nofpu_id;
2910   }
2911   __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2912 
2913   // enough room for two byte trap
2914   __ nop();
2915 }
2916 
2917 
2918 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2919   assert(exceptionOop->as_register() == rax, "must match");
2920 
2921   __ jmp(_unwind_handler_entry);
2922 }
2923 
2924 
2925 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2926 
2927   // optimized version for linear scan:
2928   // * count must be already in ECX (guaranteed by LinearScan)
2929   // * left and dest must be equal
2930   // * tmp must be unused
2931   assert(count->as_register() == SHIFT_count, "count must be in ECX");
2932   assert(left == dest, "left and dest must be equal");
2933   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2934 
2935   if (left->is_single_cpu()) {
2936     Register value = left->as_register();
2937     assert(value != SHIFT_count, "left cannot be ECX");
2938 
2939     switch (code) {
2940       case lir_shl:  __ shll(value); break;
2941       case lir_shr:  __ sarl(value); break;
2942       case lir_ushr: __ shrl(value); break;
2943       default: ShouldNotReachHere();
2944     }
2945   } else if (left->is_double_cpu()) {
2946     Register lo = left->as_register_lo();
2947     Register hi = left->as_register_hi();
2948     assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2949 #ifdef _LP64
2950     switch (code) {
2951       case lir_shl:  __ shlptr(lo);        break;
2952       case lir_shr:  __ sarptr(lo);        break;
2953       case lir_ushr: __ shrptr(lo);        break;
2954       default: ShouldNotReachHere();
2955     }
2956 #else
2957 
2958     switch (code) {
2959       case lir_shl:  __ lshl(hi, lo);        break;
2960       case lir_shr:  __ lshr(hi, lo, true);  break;
2961       case lir_ushr: __ lshr(hi, lo, false); break;
2962       default: ShouldNotReachHere();
2963     }
2964 #endif // LP64
2965   } else {
2966     ShouldNotReachHere();
2967   }
2968 }
2969 
2970 
2971 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2972   if (dest->is_single_cpu()) {
2973     // first move left into dest so that left is not destroyed by the shift
2974     Register value = dest->as_register();
2975     count = count & 0x1F; // Java spec
2976 
2977     move_regs(left->as_register(), value);
2978     switch (code) {
2979       case lir_shl:  __ shll(value, count); break;
2980       case lir_shr:  __ sarl(value, count); break;
2981       case lir_ushr: __ shrl(value, count); break;
2982       default: ShouldNotReachHere();
2983     }
2984   } else if (dest->is_double_cpu()) {
2985 #ifndef _LP64
2986     Unimplemented();
2987 #else
2988     // first move left into dest so that left is not destroyed by the shift
2989     Register value = dest->as_register_lo();
2990     count = count & 0x1F; // Java spec
2991 
2992     move_regs(left->as_register_lo(), value);
2993     switch (code) {
2994       case lir_shl:  __ shlptr(value, count); break;
2995       case lir_shr:  __ sarptr(value, count); break;
2996       case lir_ushr: __ shrptr(value, count); break;
2997       default: ShouldNotReachHere();
2998     }
2999 #endif // _LP64
3000   } else {
3001     ShouldNotReachHere();
3002   }
3003 }
3004 
3005 
3006 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3007   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3008   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3009   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3010   __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3011 }
3012 
3013 
3014 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
3015   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3016   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3017   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3018   __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3019 }
3020 
3021 
3022 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3023   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3024   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3025   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3026   __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1);
3027 }
3028 
3029 
3030 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3031   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3032   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3033   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3034   __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1);
3035 }
3036 
3037 
3038 // This code replaces a call to arraycopy; no exception may
3039 // be thrown in this code, they must be thrown in the System.arraycopy
3040 // activation frame; we could save some checks if this would not be the case
3041 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3042   ciArrayKlass* default_type = op->expected_type();
3043   Register src = op->src()->as_register();
3044   Register dst = op->dst()->as_register();
3045   Register src_pos = op->src_pos()->as_register();
3046   Register dst_pos = op->dst_pos()->as_register();
3047   Register length  = op->length()->as_register();
3048   Register tmp = op->tmp()->as_register();
3049   Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3050 
3051   CodeStub* stub = op->stub();
3052   int flags = op->flags();
3053   BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
3054   if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3055 
3056   // if we don't know anything, just go through the generic arraycopy
3057   if (default_type == nullptr) {
3058     // save outgoing arguments on stack in case call to System.arraycopy is needed
3059     // HACK ALERT. This code used to push the parameters in a hardwired fashion
3060     // for interpreter calling conventions. Now we have to do it in new style conventions.
3061     // For the moment until C1 gets the new register allocator I just force all the
3062     // args to the right place (except the register args) and then on the back side
3063     // reload the register args properly if we go slow path. Yuck
3064 
3065     // These are proper for the calling convention
3066     store_parameter(length, 2);
3067     store_parameter(dst_pos, 1);
3068     store_parameter(dst, 0);
3069 
3070     // these are just temporary placements until we need to reload
3071     store_parameter(src_pos, 3);
3072     store_parameter(src, 4);
3073     NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3074 
3075     address copyfunc_addr = StubRoutines::generic_arraycopy();
3076     assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
3077 
3078     // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3079 #ifdef _LP64
3080     // The arguments are in java calling convention so we can trivially shift them to C
3081     // convention
3082     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3083     __ mov(c_rarg0, j_rarg0);
3084     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3085     __ mov(c_rarg1, j_rarg1);
3086     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3087     __ mov(c_rarg2, j_rarg2);
3088     assert_different_registers(c_rarg3, j_rarg4);
3089     __ mov(c_rarg3, j_rarg3);
3090 #ifdef _WIN64
3091     // Allocate abi space for args but be sure to keep stack aligned
3092     __ subptr(rsp, 6*wordSize);
3093     store_parameter(j_rarg4, 4);
3094 #ifndef PRODUCT
3095     if (PrintC1Statistics) {
3096       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3097     }
3098 #endif
3099     __ call(RuntimeAddress(copyfunc_addr));
3100     __ addptr(rsp, 6*wordSize);
3101 #else
3102     __ mov(c_rarg4, j_rarg4);
3103 #ifndef PRODUCT
3104     if (PrintC1Statistics) {
3105       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3106     }
3107 #endif
3108     __ call(RuntimeAddress(copyfunc_addr));
3109 #endif // _WIN64
3110 #else
3111     __ push(length);
3112     __ push(dst_pos);
3113     __ push(dst);
3114     __ push(src_pos);
3115     __ push(src);
3116 
3117 #ifndef PRODUCT
3118     if (PrintC1Statistics) {
3119       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3120     }
3121 #endif
3122     __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3123 
3124 #endif // _LP64
3125 
3126     __ testl(rax, rax);
3127     __ jcc(Assembler::equal, *stub->continuation());
3128 
3129     __ mov(tmp, rax);
3130     __ xorl(tmp, -1);
3131 
3132     // Reload values from the stack so they are where the stub
3133     // expects them.
3134     __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3135     __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3136     __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3137     __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3138     __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3139 
3140     __ subl(length, tmp);
3141     __ addl(src_pos, tmp);
3142     __ addl(dst_pos, tmp);
3143     __ jmp(*stub->entry());
3144 
3145     __ bind(*stub->continuation());
3146     return;
3147   }
3148 
3149   assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3150 
3151   int elem_size = type2aelembytes(basic_type);
3152   Address::ScaleFactor scale;
3153 
3154   switch (elem_size) {
3155     case 1 :
3156       scale = Address::times_1;
3157       break;
3158     case 2 :
3159       scale = Address::times_2;
3160       break;
3161     case 4 :
3162       scale = Address::times_4;
3163       break;
3164     case 8 :
3165       scale = Address::times_8;
3166       break;
3167     default:
3168       scale = Address::no_scale;
3169       ShouldNotReachHere();
3170   }
3171 
3172   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3173   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3174   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3175   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3176 
3177   // length and pos's are all sign extended at this point on 64bit
3178 
3179   // test for null
3180   if (flags & LIR_OpArrayCopy::src_null_check) {
3181     __ testptr(src, src);
3182     __ jcc(Assembler::zero, *stub->entry());
3183   }
3184   if (flags & LIR_OpArrayCopy::dst_null_check) {
3185     __ testptr(dst, dst);
3186     __ jcc(Assembler::zero, *stub->entry());
3187   }
3188 
3189   // If the compiler was not able to prove that exact type of the source or the destination
3190   // of the arraycopy is an array type, check at runtime if the source or the destination is
3191   // an instance type.
3192   if (flags & LIR_OpArrayCopy::type_check) {
3193     if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3194       __ load_klass(tmp, dst, tmp_load_klass);
3195       __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3196       __ jcc(Assembler::greaterEqual, *stub->entry());
3197     }
3198 
3199     if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3200       __ load_klass(tmp, src, tmp_load_klass);
3201       __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3202       __ jcc(Assembler::greaterEqual, *stub->entry());
3203     }
3204   }
3205 
3206   // check if negative
3207   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3208     __ testl(src_pos, src_pos);
3209     __ jcc(Assembler::less, *stub->entry());
3210   }
3211   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3212     __ testl(dst_pos, dst_pos);
3213     __ jcc(Assembler::less, *stub->entry());
3214   }
3215 
3216   if (flags & LIR_OpArrayCopy::src_range_check) {
3217     __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3218     __ cmpl(tmp, src_length_addr);
3219     __ jcc(Assembler::above, *stub->entry());
3220   }
3221   if (flags & LIR_OpArrayCopy::dst_range_check) {
3222     __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3223     __ cmpl(tmp, dst_length_addr);
3224     __ jcc(Assembler::above, *stub->entry());
3225   }
3226 
3227   if (flags & LIR_OpArrayCopy::length_positive_check) {
3228     __ testl(length, length);
3229     __ jcc(Assembler::less, *stub->entry());
3230   }
3231 
3232 #ifdef _LP64
3233   __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3234   __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3235 #endif
3236 
3237   if (flags & LIR_OpArrayCopy::type_check) {
3238     // We don't know the array types are compatible
3239     if (basic_type != T_OBJECT) {
3240       // Simple test for basic type arrays
3241       if (UseCompressedClassPointers) {
3242         __ movl(tmp, src_klass_addr);
3243         __ cmpl(tmp, dst_klass_addr);
3244       } else {
3245         __ movptr(tmp, src_klass_addr);
3246         __ cmpptr(tmp, dst_klass_addr);
3247       }
3248       __ jcc(Assembler::notEqual, *stub->entry());
3249     } else {
3250       // For object arrays, if src is a sub class of dst then we can
3251       // safely do the copy.
3252       Label cont, slow;
3253 
3254       __ push(src);
3255       __ push(dst);
3256 
3257       __ load_klass(src, src, tmp_load_klass);
3258       __ load_klass(dst, dst, tmp_load_klass);
3259 
3260       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
3261 
3262       __ push(src);
3263       __ push(dst);
3264       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3265       __ pop(dst);
3266       __ pop(src);
3267 
3268       __ testl(src, src);
3269       __ jcc(Assembler::notEqual, cont);
3270 
3271       __ bind(slow);
3272       __ pop(dst);
3273       __ pop(src);
3274 
3275       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3276       if (copyfunc_addr != nullptr) { // use stub if available
3277         // src is not a sub class of dst so we have to do a
3278         // per-element check.
3279 
3280         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3281         if ((flags & mask) != mask) {
3282           // Check that at least both of them object arrays.
3283           assert(flags & mask, "one of the two should be known to be an object array");
3284 
3285           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3286             __ load_klass(tmp, src, tmp_load_klass);
3287           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3288             __ load_klass(tmp, dst, tmp_load_klass);
3289           }
3290           int lh_offset = in_bytes(Klass::layout_helper_offset());
3291           Address klass_lh_addr(tmp, lh_offset);
3292           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3293           __ cmpl(klass_lh_addr, objArray_lh);
3294           __ jcc(Assembler::notEqual, *stub->entry());
3295         }
3296 
3297        // Spill because stubs can use any register they like and it's
3298        // easier to restore just those that we care about.
3299        store_parameter(dst, 0);
3300        store_parameter(dst_pos, 1);
3301        store_parameter(length, 2);
3302        store_parameter(src_pos, 3);
3303        store_parameter(src, 4);
3304 
3305 #ifndef _LP64
3306         __ movptr(tmp, dst_klass_addr);
3307         __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3308         __ push(tmp);
3309         __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3310         __ push(tmp);
3311         __ push(length);
3312         __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3313         __ push(tmp);
3314         __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3315         __ push(tmp);
3316 
3317         __ call_VM_leaf(copyfunc_addr, 5);
3318 #else
3319         __ movl2ptr(length, length); //higher 32bits must be null
3320 
3321         __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3322         assert_different_registers(c_rarg0, dst, dst_pos, length);
3323         __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3324         assert_different_registers(c_rarg1, dst, length);
3325 
3326         __ mov(c_rarg2, length);
3327         assert_different_registers(c_rarg2, dst);
3328 
3329 #ifdef _WIN64
3330         // Allocate abi space for args but be sure to keep stack aligned
3331         __ subptr(rsp, 6*wordSize);
3332         __ load_klass(c_rarg3, dst, tmp_load_klass);
3333         __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3334         store_parameter(c_rarg3, 4);
3335         __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3336         __ call(RuntimeAddress(copyfunc_addr));
3337         __ addptr(rsp, 6*wordSize);
3338 #else
3339         __ load_klass(c_rarg4, dst, tmp_load_klass);
3340         __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3341         __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3342         __ call(RuntimeAddress(copyfunc_addr));
3343 #endif
3344 
3345 #endif
3346 
3347 #ifndef PRODUCT
3348         if (PrintC1Statistics) {
3349           Label failed;
3350           __ testl(rax, rax);
3351           __ jcc(Assembler::notZero, failed);
3352           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1);
3353           __ bind(failed);
3354         }
3355 #endif
3356 
3357         __ testl(rax, rax);
3358         __ jcc(Assembler::zero, *stub->continuation());
3359 
3360 #ifndef PRODUCT
3361         if (PrintC1Statistics) {
3362           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1);
3363         }
3364 #endif
3365 
3366         __ mov(tmp, rax);
3367 
3368         __ xorl(tmp, -1);
3369 
3370         // Restore previously spilled arguments
3371         __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3372         __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3373         __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3374         __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3375         __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3376 
3377 
3378         __ subl(length, tmp);
3379         __ addl(src_pos, tmp);
3380         __ addl(dst_pos, tmp);
3381       }
3382 
3383       __ jmp(*stub->entry());
3384 
3385       __ bind(cont);
3386       __ pop(dst);
3387       __ pop(src);
3388     }
3389   }
3390 
3391 #ifdef ASSERT
3392   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3393     // Sanity check the known type with the incoming class.  For the
3394     // primitive case the types must match exactly with src.klass and
3395     // dst.klass each exactly matching the default type.  For the
3396     // object array case, if no type check is needed then either the
3397     // dst type is exactly the expected type and the src type is a
3398     // subtype which we can't check or src is the same array as dst
3399     // but not necessarily exactly of type default_type.
3400     Label known_ok, halt;
3401     __ mov_metadata(tmp, default_type->constant_encoding());
3402 #ifdef _LP64
3403     if (UseCompressedClassPointers) {
3404       __ encode_klass_not_null(tmp, rscratch1);
3405     }
3406 #endif
3407 
3408     if (basic_type != T_OBJECT) {
3409 
3410       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3411       else                   __ cmpptr(tmp, dst_klass_addr);
3412       __ jcc(Assembler::notEqual, halt);
3413       if (UseCompressedClassPointers)          __ cmpl(tmp, src_klass_addr);
3414       else                   __ cmpptr(tmp, src_klass_addr);
3415       __ jcc(Assembler::equal, known_ok);
3416     } else {
3417       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3418       else                   __ cmpptr(tmp, dst_klass_addr);
3419       __ jcc(Assembler::equal, known_ok);
3420       __ cmpptr(src, dst);
3421       __ jcc(Assembler::equal, known_ok);
3422     }
3423     __ bind(halt);
3424     __ stop("incorrect type information in arraycopy");
3425     __ bind(known_ok);
3426   }
3427 #endif
3428 
3429 #ifndef PRODUCT
3430   if (PrintC1Statistics) {
3431     __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1);
3432   }
3433 #endif
3434 
3435 #ifdef _LP64
3436   assert_different_registers(c_rarg0, dst, dst_pos, length);
3437   __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3438   assert_different_registers(c_rarg1, length);
3439   __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3440   __ mov(c_rarg2, length);
3441 
3442 #else
3443   __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3444   store_parameter(tmp, 0);
3445   __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3446   store_parameter(tmp, 1);
3447   store_parameter(length, 2);
3448 #endif // _LP64
3449 
3450   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3451   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3452   const char *name;
3453   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3454   __ call_VM_leaf(entry, 0);
3455 
3456   __ bind(*stub->continuation());
3457 }
3458 
3459 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3460   assert(op->crc()->is_single_cpu(),  "crc must be register");
3461   assert(op->val()->is_single_cpu(),  "byte value must be register");
3462   assert(op->result_opr()->is_single_cpu(), "result must be register");
3463   Register crc = op->crc()->as_register();
3464   Register val = op->val()->as_register();
3465   Register res = op->result_opr()->as_register();
3466 
3467   assert_different_registers(val, crc, res);
3468 
3469   __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3470   __ notl(crc); // ~crc
3471   __ update_byte_crc32(crc, val, res);
3472   __ notl(crc); // ~crc
3473   __ mov(res, crc);
3474 }
3475 
3476 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3477   Register obj = op->obj_opr()->as_register();  // may not be an oop
3478   Register hdr = op->hdr_opr()->as_register();
3479   Register lock = op->lock_opr()->as_register();
3480   if (LockingMode == LM_MONITOR) {
3481     if (op->info() != nullptr) {
3482       add_debug_info_for_null_check_here(op->info());
3483       __ null_check(obj);
3484     }
3485     __ jmp(*op->stub()->entry());
3486   } else if (op->code() == lir_lock) {
3487     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3488     Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg;
3489     // add debug info for NullPointerException only if one is possible
3490     int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
3491     if (op->info() != nullptr) {
3492       add_debug_info_for_null_check(null_check_offset, op->info());
3493     }
3494     // done
3495   } else if (op->code() == lir_unlock) {
3496     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3497     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3498   } else {
3499     Unimplemented();
3500   }
3501   __ bind(*op->stub()->continuation());
3502 }
3503 
3504 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
3505   Register obj = op->obj()->as_pointer_register();
3506   Register result = op->result_opr()->as_pointer_register();
3507 
3508   CodeEmitInfo* info = op->info();
3509   if (info != nullptr) {
3510     add_debug_info_for_null_check_here(info);
3511   }
3512 
3513 #ifdef _LP64
3514   if (UseCompressedClassPointers) {
3515     __ movl(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3516     __ decode_klass_not_null(result, rscratch1);
3517   } else
3518 #endif
3519     __ movptr(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3520 }
3521 
3522 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3523   ciMethod* method = op->profiled_method();
3524   int bci          = op->profiled_bci();
3525   ciMethod* callee = op->profiled_callee();
3526   Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3527 
3528   // Update counter for all call types
3529   ciMethodData* md = method->method_data_or_null();
3530   assert(md != nullptr, "Sanity");
3531   ciProfileData* data = md->bci_to_data(bci);
3532   assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
3533   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
3534   Register mdo  = op->mdo()->as_register();
3535   __ mov_metadata(mdo, md->constant_encoding());
3536   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3537   // Perform additional virtual call profiling for invokevirtual and
3538   // invokeinterface bytecodes
3539   if (op->should_profile_receiver_type()) {
3540     assert(op->recv()->is_single_cpu(), "recv must be allocated");
3541     Register recv = op->recv()->as_register();
3542     assert_different_registers(mdo, recv);
3543     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3544     ciKlass* known_klass = op->known_holder();
3545     if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
3546       // We know the type that will be seen at this call site; we can
3547       // statically update the MethodData* rather than needing to do
3548       // dynamic tests on the receiver type
3549 
3550       // NOTE: we should probably put a lock around this search to
3551       // avoid collisions by concurrent compilations
3552       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3553       uint i;
3554       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3555         ciKlass* receiver = vc_data->receiver(i);
3556         if (known_klass->equals(receiver)) {
3557           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3558           __ addptr(data_addr, DataLayout::counter_increment);
3559           return;
3560         }
3561       }
3562 
3563       // Receiver type not found in profile data; select an empty slot
3564 
3565       // Note that this is less efficient than it should be because it
3566       // always does a write to the receiver part of the
3567       // VirtualCallData rather than just the first time
3568       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3569         ciKlass* receiver = vc_data->receiver(i);
3570         if (receiver == nullptr) {
3571           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3572           __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1);
3573           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3574           __ addptr(data_addr, DataLayout::counter_increment);
3575           return;
3576         }
3577       }
3578     } else {
3579       __ load_klass(recv, recv, tmp_load_klass);
3580       Label update_done;
3581       type_profile_helper(mdo, md, data, recv, &update_done);
3582       // Receiver did not match any saved receiver and there is no empty row for it.
3583       // Increment total counter to indicate polymorphic case.
3584       __ addptr(counter_addr, DataLayout::counter_increment);
3585 
3586       __ bind(update_done);
3587     }
3588   } else {
3589     // Static call
3590     __ addptr(counter_addr, DataLayout::counter_increment);
3591   }
3592 }
3593 
3594 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3595   Register obj = op->obj()->as_register();
3596   Register tmp = op->tmp()->as_pointer_register();
3597   Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3598   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3599   ciKlass* exact_klass = op->exact_klass();
3600   intptr_t current_klass = op->current_klass();
3601   bool not_null = op->not_null();
3602   bool no_conflict = op->no_conflict();
3603 
3604   Label update, next, none;
3605 
3606   bool do_null = !not_null;
3607   bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3608   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3609 
3610   assert(do_null || do_update, "why are we here?");
3611   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3612 
3613   __ verify_oop(obj);
3614 
3615 #ifdef ASSERT
3616   if (obj == tmp) {
3617 #ifdef _LP64
3618     assert_different_registers(obj, rscratch1, mdo_addr.base(), mdo_addr.index());
3619 #else
3620     assert_different_registers(obj, mdo_addr.base(), mdo_addr.index());
3621 #endif
3622   } else {
3623 #ifdef _LP64
3624     assert_different_registers(obj, tmp, rscratch1, mdo_addr.base(), mdo_addr.index());
3625 #else
3626     assert_different_registers(obj, tmp, mdo_addr.base(), mdo_addr.index());
3627 #endif
3628   }
3629 #endif
3630   if (do_null) {
3631     __ testptr(obj, obj);
3632     __ jccb(Assembler::notZero, update);
3633     if (!TypeEntries::was_null_seen(current_klass)) {
3634       __ testptr(mdo_addr, TypeEntries::null_seen);
3635 #ifndef ASSERT
3636       __ jccb(Assembler::notZero, next); // already set
3637 #else
3638       __ jcc(Assembler::notZero, next); // already set
3639 #endif
3640       // atomic update to prevent overwriting Klass* with 0
3641       __ lock();
3642       __ orptr(mdo_addr, TypeEntries::null_seen);
3643     }
3644     if (do_update) {
3645 #ifndef ASSERT
3646       __ jmpb(next);
3647     }
3648 #else
3649       __ jmp(next);
3650     }
3651   } else {
3652     __ testptr(obj, obj);
3653     __ jcc(Assembler::notZero, update);
3654     __ stop("unexpected null obj");
3655 #endif
3656   }
3657 
3658   __ bind(update);
3659 
3660   if (do_update) {
3661 #ifdef ASSERT
3662     if (exact_klass != nullptr) {
3663       Label ok;
3664       __ load_klass(tmp, obj, tmp_load_klass);
3665       __ push(tmp);
3666       __ mov_metadata(tmp, exact_klass->constant_encoding());
3667       __ cmpptr(tmp, Address(rsp, 0));
3668       __ jcc(Assembler::equal, ok);
3669       __ stop("exact klass and actual klass differ");
3670       __ bind(ok);
3671       __ pop(tmp);
3672     }
3673 #endif
3674     if (!no_conflict) {
3675       if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3676         if (exact_klass != nullptr) {
3677           __ mov_metadata(tmp, exact_klass->constant_encoding());
3678         } else {
3679           __ load_klass(tmp, obj, tmp_load_klass);
3680         }
3681 #ifdef _LP64
3682         __ mov(rscratch1, tmp); // save original value before XOR
3683 #endif
3684         __ xorptr(tmp, mdo_addr);
3685         __ testptr(tmp, TypeEntries::type_klass_mask);
3686         // klass seen before, nothing to do. The unknown bit may have been
3687         // set already but no need to check.
3688         __ jccb(Assembler::zero, next);
3689 
3690         __ testptr(tmp, TypeEntries::type_unknown);
3691         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3692 
3693         if (TypeEntries::is_type_none(current_klass)) {
3694           __ testptr(mdo_addr, TypeEntries::type_mask);
3695           __ jccb(Assembler::zero, none);
3696 #ifdef _LP64
3697           // There is a chance that the checks above (re-reading profiling
3698           // data from memory) fail if another thread has just set the
3699           // profiling to this obj's klass
3700           __ mov(tmp, rscratch1); // get back original value before XOR
3701           __ xorptr(tmp, mdo_addr);
3702           __ testptr(tmp, TypeEntries::type_klass_mask);
3703           __ jccb(Assembler::zero, next);
3704 #endif
3705         }
3706       } else {
3707         assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3708                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3709 
3710         __ testptr(mdo_addr, TypeEntries::type_unknown);
3711         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3712       }
3713 
3714       // different than before. Cannot keep accurate profile.
3715       __ orptr(mdo_addr, TypeEntries::type_unknown);
3716 
3717       if (TypeEntries::is_type_none(current_klass)) {
3718         __ jmpb(next);
3719 
3720         __ bind(none);
3721         // first time here. Set profile type.
3722         __ movptr(mdo_addr, tmp);
3723 #ifdef ASSERT
3724         __ andptr(tmp, TypeEntries::type_klass_mask);
3725         __ verify_klass_ptr(tmp);
3726 #endif
3727       }
3728     } else {
3729       // There's a single possible klass at this profile point
3730       assert(exact_klass != nullptr, "should be");
3731       if (TypeEntries::is_type_none(current_klass)) {
3732         __ mov_metadata(tmp, exact_klass->constant_encoding());
3733         __ xorptr(tmp, mdo_addr);
3734         __ testptr(tmp, TypeEntries::type_klass_mask);
3735 #ifdef ASSERT
3736         __ jcc(Assembler::zero, next);
3737 
3738         {
3739           Label ok;
3740           __ push(tmp);
3741           __ testptr(mdo_addr, TypeEntries::type_mask);
3742           __ jcc(Assembler::zero, ok);
3743           // may have been set by another thread
3744           __ mov_metadata(tmp, exact_klass->constant_encoding());
3745           __ xorptr(tmp, mdo_addr);
3746           __ testptr(tmp, TypeEntries::type_mask);
3747           __ jcc(Assembler::zero, ok);
3748 
3749           __ stop("unexpected profiling mismatch");
3750           __ bind(ok);
3751           __ pop(tmp);
3752         }
3753 #else
3754         __ jccb(Assembler::zero, next);
3755 #endif
3756         // first time here. Set profile type.
3757         __ movptr(mdo_addr, tmp);
3758 #ifdef ASSERT
3759         __ andptr(tmp, TypeEntries::type_klass_mask);
3760         __ verify_klass_ptr(tmp);
3761 #endif
3762       } else {
3763         assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3764                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3765 
3766         __ testptr(mdo_addr, TypeEntries::type_unknown);
3767         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3768 
3769         __ orptr(mdo_addr, TypeEntries::type_unknown);
3770       }
3771     }
3772   }
3773   __ bind(next);
3774 }
3775 
3776 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3777   Unimplemented();
3778 }
3779 
3780 
3781 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3782   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3783 }
3784 
3785 
3786 void LIR_Assembler::align_backward_branch_target() {
3787   __ align(BytesPerWord);
3788 }
3789 
3790 
3791 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3792   if (left->is_single_cpu()) {
3793     __ negl(left->as_register());
3794     move_regs(left->as_register(), dest->as_register());
3795 
3796   } else if (left->is_double_cpu()) {
3797     Register lo = left->as_register_lo();
3798 #ifdef _LP64
3799     Register dst = dest->as_register_lo();
3800     __ movptr(dst, lo);
3801     __ negptr(dst);
3802 #else
3803     Register hi = left->as_register_hi();
3804     __ lneg(hi, lo);
3805     if (dest->as_register_lo() == hi) {
3806       assert(dest->as_register_hi() != lo, "destroying register");
3807       move_regs(hi, dest->as_register_hi());
3808       move_regs(lo, dest->as_register_lo());
3809     } else {
3810       move_regs(lo, dest->as_register_lo());
3811       move_regs(hi, dest->as_register_hi());
3812     }
3813 #endif // _LP64
3814 
3815   } else if (dest->is_single_xmm()) {
3816 #ifdef _LP64
3817     if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3818       assert(tmp->is_valid(), "need temporary");
3819       assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
3820       __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
3821     }
3822     else
3823 #endif
3824     {
3825       assert(!tmp->is_valid(), "do not need temporary");
3826       if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3827         __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3828       }
3829       __ xorps(dest->as_xmm_float_reg(),
3830                ExternalAddress((address)float_signflip_pool),
3831                rscratch1);
3832     }
3833   } else if (dest->is_double_xmm()) {
3834 #ifdef _LP64
3835     if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3836       assert(tmp->is_valid(), "need temporary");
3837       assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
3838       __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
3839     }
3840     else
3841 #endif
3842     {
3843       assert(!tmp->is_valid(), "do not need temporary");
3844       if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3845         __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3846       }
3847       __ xorpd(dest->as_xmm_double_reg(),
3848                ExternalAddress((address)double_signflip_pool),
3849                rscratch1);
3850     }
3851 #ifndef _LP64
3852   } else if (left->is_single_fpu() || left->is_double_fpu()) {
3853     assert(left->fpu() == 0, "arg must be on TOS");
3854     assert(dest->fpu() == 0, "dest must be TOS");
3855     __ fchs();
3856 #endif // !_LP64
3857 
3858   } else {
3859     ShouldNotReachHere();
3860   }
3861 }
3862 
3863 
3864 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3865   assert(src->is_address(), "must be an address");
3866   assert(dest->is_register(), "must be a register");
3867 
3868   PatchingStub* patch = nullptr;
3869   if (patch_code != lir_patch_none) {
3870     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3871   }
3872 
3873   Register reg = dest->as_pointer_register();
3874   LIR_Address* addr = src->as_address_ptr();
3875   __ lea(reg, as_Address(addr));
3876 
3877   if (patch != nullptr) {
3878     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3879   }
3880 }
3881 
3882 
3883 
3884 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3885   assert(!tmp->is_valid(), "don't need temporary");
3886   __ call(RuntimeAddress(dest));
3887   if (info != nullptr) {
3888     add_call_info_here(info);
3889   }
3890   __ post_call_nop();
3891 }
3892 
3893 
3894 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3895   assert(type == T_LONG, "only for volatile long fields");
3896 
3897   if (info != nullptr) {
3898     add_debug_info_for_null_check_here(info);
3899   }
3900 
3901   if (src->is_double_xmm()) {
3902     if (dest->is_double_cpu()) {
3903 #ifdef _LP64
3904       __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3905 #else
3906       __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3907       __ psrlq(src->as_xmm_double_reg(), 32);
3908       __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3909 #endif // _LP64
3910     } else if (dest->is_double_stack()) {
3911       __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3912     } else if (dest->is_address()) {
3913       __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3914     } else {
3915       ShouldNotReachHere();
3916     }
3917 
3918   } else if (dest->is_double_xmm()) {
3919     if (src->is_double_stack()) {
3920       __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3921     } else if (src->is_address()) {
3922       __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3923     } else {
3924       ShouldNotReachHere();
3925     }
3926 
3927 #ifndef _LP64
3928   } else if (src->is_double_fpu()) {
3929     assert(src->fpu_regnrLo() == 0, "must be TOS");
3930     if (dest->is_double_stack()) {
3931       __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3932     } else if (dest->is_address()) {
3933       __ fistp_d(as_Address(dest->as_address_ptr()));
3934     } else {
3935       ShouldNotReachHere();
3936     }
3937 
3938   } else if (dest->is_double_fpu()) {
3939     assert(dest->fpu_regnrLo() == 0, "must be TOS");
3940     if (src->is_double_stack()) {
3941       __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3942     } else if (src->is_address()) {
3943       __ fild_d(as_Address(src->as_address_ptr()));
3944     } else {
3945       ShouldNotReachHere();
3946     }
3947 #endif // !_LP64
3948 
3949   } else {
3950     ShouldNotReachHere();
3951   }
3952 }
3953 
3954 #ifdef ASSERT
3955 // emit run-time assertion
3956 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3957   assert(op->code() == lir_assert, "must be");
3958 
3959   if (op->in_opr1()->is_valid()) {
3960     assert(op->in_opr2()->is_valid(), "both operands must be valid");
3961     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3962   } else {
3963     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3964     assert(op->condition() == lir_cond_always, "no other conditions allowed");
3965   }
3966 
3967   Label ok;
3968   if (op->condition() != lir_cond_always) {
3969     Assembler::Condition acond = Assembler::zero;
3970     switch (op->condition()) {
3971       case lir_cond_equal:        acond = Assembler::equal;       break;
3972       case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
3973       case lir_cond_less:         acond = Assembler::less;        break;
3974       case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
3975       case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3976       case lir_cond_greater:      acond = Assembler::greater;     break;
3977       case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
3978       case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
3979       default:                    ShouldNotReachHere();
3980     }
3981     __ jcc(acond, ok);
3982   }
3983   if (op->halt()) {
3984     const char* str = __ code_string(op->msg());
3985     __ stop(str);
3986   } else {
3987     breakpoint();
3988   }
3989   __ bind(ok);
3990 }
3991 #endif
3992 
3993 void LIR_Assembler::membar() {
3994   // QQQ sparc TSO uses this,
3995   __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3996 }
3997 
3998 void LIR_Assembler::membar_acquire() {
3999   // No x86 machines currently require load fences
4000 }
4001 
4002 void LIR_Assembler::membar_release() {
4003   // No x86 machines currently require store fences
4004 }
4005 
4006 void LIR_Assembler::membar_loadload() {
4007   // no-op
4008   //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
4009 }
4010 
4011 void LIR_Assembler::membar_storestore() {
4012   // no-op
4013   //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4014 }
4015 
4016 void LIR_Assembler::membar_loadstore() {
4017   // no-op
4018   //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4019 }
4020 
4021 void LIR_Assembler::membar_storeload() {
4022   __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4023 }
4024 
4025 void LIR_Assembler::on_spin_wait() {
4026   __ pause ();
4027 }
4028 
4029 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4030   assert(result_reg->is_register(), "check");
4031 #ifdef _LP64
4032   // __ get_thread(result_reg->as_register_lo());
4033   __ mov(result_reg->as_register(), r15_thread);
4034 #else
4035   __ get_thread(result_reg->as_register());
4036 #endif // _LP64
4037 }
4038 
4039 
4040 void LIR_Assembler::peephole(LIR_List*) {
4041   // do nothing for now
4042 }
4043 
4044 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4045   assert(data == dest, "xchg/xadd uses only 2 operands");
4046 
4047   if (data->type() == T_INT) {
4048     if (code == lir_xadd) {
4049       __ lock();
4050       __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4051     } else {
4052       __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4053     }
4054   } else if (data->is_oop()) {
4055     assert (code == lir_xchg, "xadd for oops");
4056     Register obj = data->as_register();
4057 #ifdef _LP64
4058     if (UseCompressedOops) {
4059       __ encode_heap_oop(obj);
4060       __ xchgl(obj, as_Address(src->as_address_ptr()));
4061       __ decode_heap_oop(obj);
4062     } else {
4063       __ xchgptr(obj, as_Address(src->as_address_ptr()));
4064     }
4065 #else
4066     __ xchgl(obj, as_Address(src->as_address_ptr()));
4067 #endif
4068   } else if (data->type() == T_LONG) {
4069 #ifdef _LP64
4070     assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4071     if (code == lir_xadd) {
4072       __ lock();
4073       __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4074     } else {
4075       __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4076     }
4077 #else
4078     ShouldNotReachHere();
4079 #endif
4080   } else {
4081     ShouldNotReachHere();
4082   }
4083 }
4084 
4085 #undef __