1 /*
2 * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "compiler/oopMap.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "gc/shared/gc_globals.hpp"
39 #include "nativeInst_x86.hpp"
40 #include "oops/objArrayKlass.hpp"
41 #include "runtime/frame.inline.hpp"
42 #include "runtime/safepointMechanism.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "utilities/powerOfTwo.hpp"
46 #include "vmreg_x86.inline.hpp"
47
48
49 // These masks are used to provide 128-bit aligned bitmasks to the XMM
50 // instructions, to allow sign-masking or sign-bit flipping. They allow
51 // fast versions of NegF/NegD and AbsF/AbsD.
52
53 // Note: 'double' and 'long long' have 32-bits alignment on x86.
54 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
55 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
56 // of 128-bits operands for SSE instructions.
57 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
58 // Store the value to a 128-bits operand.
59 operand[0] = lo;
60 operand[1] = hi;
61 return operand;
62 }
63
64 // Buffer for 128-bits masks used by SSE instructions.
65 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
66
67 // Static initialization during VM startup.
68 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
69 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
70 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
71 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
72
73
74 NEEDS_CLEANUP // remove this definitions ?
75 const Register SYNC_header = rax; // synchronization header
76 const Register SHIFT_count = rcx; // where count for shift operations must be
77
78 #define __ _masm->
79
80
81 static void select_different_registers(Register preserve,
82 Register extra,
83 Register &tmp1,
84 Register &tmp2) {
85 if (tmp1 == preserve) {
86 assert_different_registers(tmp1, tmp2, extra);
87 tmp1 = extra;
88 } else if (tmp2 == preserve) {
89 assert_different_registers(tmp1, tmp2, extra);
90 tmp2 = extra;
91 }
92 assert_different_registers(preserve, tmp1, tmp2);
93 }
94
95
96
97 static void select_different_registers(Register preserve,
98 Register extra,
99 Register &tmp1,
100 Register &tmp2,
101 Register &tmp3) {
102 if (tmp1 == preserve) {
103 assert_different_registers(tmp1, tmp2, tmp3, extra);
104 tmp1 = extra;
105 } else if (tmp2 == preserve) {
106 assert_different_registers(tmp1, tmp2, tmp3, extra);
107 tmp2 = extra;
108 } else if (tmp3 == preserve) {
109 assert_different_registers(tmp1, tmp2, tmp3, extra);
110 tmp3 = extra;
111 }
112 assert_different_registers(preserve, tmp1, tmp2, tmp3);
113 }
114
115
116
117 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
118 if (opr->is_constant()) {
119 LIR_Const* constant = opr->as_constant_ptr();
120 switch (constant->type()) {
121 case T_INT: {
122 return true;
123 }
124
125 default:
126 return false;
127 }
128 }
129 return false;
130 }
131
132
133 LIR_Opr LIR_Assembler::receiverOpr() {
134 return FrameMap::receiver_opr;
135 }
136
137 LIR_Opr LIR_Assembler::osrBufferPointer() {
138 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
139 }
140
141 //--------------fpu register translations-----------------------
142
143
144 address LIR_Assembler::float_constant(float f) {
145 address const_addr = __ float_constant(f);
146 if (const_addr == nullptr) {
147 bailout("const section overflow");
148 return __ code()->consts()->start();
149 } else {
150 return const_addr;
151 }
152 }
153
154
155 address LIR_Assembler::double_constant(double d) {
156 address const_addr = __ double_constant(d);
157 if (const_addr == nullptr) {
158 bailout("const section overflow");
159 return __ code()->consts()->start();
160 } else {
161 return const_addr;
162 }
163 }
164
165 #ifndef _LP64
166 void LIR_Assembler::fpop() {
167 __ fpop();
168 }
169
170 void LIR_Assembler::fxch(int i) {
171 __ fxch(i);
172 }
173
174 void LIR_Assembler::fld(int i) {
175 __ fld_s(i);
176 }
177
178 void LIR_Assembler::ffree(int i) {
179 __ ffree(i);
180 }
181 #endif // !_LP64
182
183 void LIR_Assembler::breakpoint() {
184 __ int3();
185 }
186
187 void LIR_Assembler::push(LIR_Opr opr) {
188 if (opr->is_single_cpu()) {
189 __ push_reg(opr->as_register());
190 } else if (opr->is_double_cpu()) {
191 NOT_LP64(__ push_reg(opr->as_register_hi()));
192 __ push_reg(opr->as_register_lo());
193 } else if (opr->is_stack()) {
194 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
195 } else if (opr->is_constant()) {
196 LIR_Const* const_opr = opr->as_constant_ptr();
197 if (const_opr->type() == T_OBJECT) {
198 __ push_oop(const_opr->as_jobject(), rscratch1);
199 } else if (const_opr->type() == T_INT) {
200 __ push_jint(const_opr->as_jint());
201 } else {
202 ShouldNotReachHere();
203 }
204
205 } else {
206 ShouldNotReachHere();
207 }
208 }
209
210 void LIR_Assembler::pop(LIR_Opr opr) {
211 if (opr->is_single_cpu()) {
212 __ pop_reg(opr->as_register());
213 } else {
214 ShouldNotReachHere();
215 }
216 }
217
218 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
219 return addr->base()->is_illegal() && addr->index()->is_illegal();
220 }
221
222 //-------------------------------------------
223
224 Address LIR_Assembler::as_Address(LIR_Address* addr) {
225 return as_Address(addr, rscratch1);
226 }
227
228 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
229 if (addr->base()->is_illegal()) {
230 assert(addr->index()->is_illegal(), "must be illegal too");
231 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
232 if (! __ reachable(laddr)) {
233 __ movptr(tmp, laddr.addr());
234 Address res(tmp, 0);
235 return res;
236 } else {
237 return __ as_Address(laddr);
238 }
239 }
240
241 Register base = addr->base()->as_pointer_register();
242
243 if (addr->index()->is_illegal()) {
244 return Address( base, addr->disp());
245 } else if (addr->index()->is_cpu_register()) {
246 Register index = addr->index()->as_pointer_register();
247 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
248 } else if (addr->index()->is_constant()) {
249 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
250 assert(Assembler::is_simm32(addr_offset), "must be");
251
252 return Address(base, addr_offset);
253 } else {
254 Unimplemented();
255 return Address();
256 }
257 }
258
259
260 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
261 Address base = as_Address(addr);
262 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
263 }
264
265
266 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
267 return as_Address(addr);
268 }
269
270
271 void LIR_Assembler::osr_entry() {
272 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
273 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
274 ValueStack* entry_state = osr_entry->state();
275 int number_of_locks = entry_state->locks_size();
276
277 // we jump here if osr happens with the interpreter
278 // state set up to continue at the beginning of the
279 // loop that triggered osr - in particular, we have
280 // the following registers setup:
281 //
282 // rcx: osr buffer
283 //
284
285 // build frame
286 ciMethod* m = compilation()->method();
287 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
288
289 // OSR buffer is
290 //
291 // locals[nlocals-1..0]
292 // monitors[0..number_of_locks]
293 //
294 // locals is a direct copy of the interpreter frame so in the osr buffer
295 // so first slot in the local array is the last local from the interpreter
296 // and last slot is local[0] (receiver) from the interpreter
297 //
298 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
299 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
300 // in the interpreter frame (the method lock if a sync method)
301
302 // Initialize monitors in the compiled activation.
303 // rcx: pointer to osr buffer
304 //
305 // All other registers are dead at this point and the locals will be
306 // copied into place by code emitted in the IR.
307
308 Register OSR_buf = osrBufferPointer()->as_pointer_register();
309 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
310 int monitor_offset = BytesPerWord * method()->max_locals() +
311 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
312 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
313 // the OSR buffer using 2 word entries: first the lock and then
314 // the oop.
315 for (int i = 0; i < number_of_locks; i++) {
316 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
317 #ifdef ASSERT
318 // verify the interpreter's monitor has a non-null object
319 {
320 Label L;
321 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD);
322 __ jcc(Assembler::notZero, L);
323 __ stop("locked object is null");
324 __ bind(L);
325 }
326 #endif
327 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
328 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
329 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
330 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
331 }
332 }
333 }
334
335
336 // inline cache check; done before the frame is built.
337 int LIR_Assembler::check_icache() {
338 return __ ic_check(CodeEntryAlignment);
339 }
340
341 void LIR_Assembler::clinit_barrier(ciMethod* method) {
342 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
343 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
344
345 Label L_skip_barrier;
346 Register klass = rscratch1;
347 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
348 assert(thread != noreg, "x86_32 not implemented");
349
350 __ mov_metadata(klass, method->holder()->constant_encoding());
351 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
352
353 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
354
355 __ bind(L_skip_barrier);
356 }
357
358 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
359 jobject o = nullptr;
360 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
361 __ movoop(reg, o);
362 patching_epilog(patch, lir_patch_normal, reg, info);
363 }
364
365 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
366 Metadata* o = nullptr;
367 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
368 __ mov_metadata(reg, o);
369 patching_epilog(patch, lir_patch_normal, reg, info);
370 }
371
372 // This specifies the rsp decrement needed to build the frame
373 int LIR_Assembler::initial_frame_size_in_bytes() const {
374 // if rounding, must let FrameMap know!
375
376 // The frame_map records size in slots (32bit word)
377
378 // subtract two words to account for return address and link
379 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
380 }
381
382
383 int LIR_Assembler::emit_exception_handler() {
384 // generate code for exception handler
385 address handler_base = __ start_a_stub(exception_handler_size());
386 if (handler_base == nullptr) {
387 // not enough space left for the handler
388 bailout("exception handler overflow");
389 return -1;
390 }
391
392 int offset = code_offset();
393
394 // the exception oop and pc are in rax, and rdx
395 // no other registers need to be preserved, so invalidate them
396 __ invalidate_registers(false, true, true, false, true, true);
397
398 // check that there is really an exception
399 __ verify_not_null_oop(rax);
400
401 // search an exception handler (rax: exception oop, rdx: throwing pc)
402 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
403 __ should_not_reach_here();
404 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
405 __ end_a_stub();
406
407 return offset;
408 }
409
410
411 // Emit the code to remove the frame from the stack in the exception
412 // unwind path.
413 int LIR_Assembler::emit_unwind_handler() {
414 #ifndef PRODUCT
415 if (CommentedAssembly) {
416 _masm->block_comment("Unwind handler");
417 }
418 #endif
419
420 int offset = code_offset();
421
422 // Fetch the exception from TLS and clear out exception related thread state
423 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
424 NOT_LP64(__ get_thread(thread));
425 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
426 __ movptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
427 __ movptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
428
429 __ bind(_unwind_handler_entry);
430 __ verify_not_null_oop(rax);
431 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
432 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
433 }
434
435 // Perform needed unlocking
436 MonitorExitStub* stub = nullptr;
437 if (method()->is_synchronized()) {
438 monitor_address(0, FrameMap::rax_opr);
439 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
440 if (LockingMode == LM_MONITOR) {
441 __ jmp(*stub->entry());
442 } else {
443 __ unlock_object(rdi, rsi, rax, *stub->entry());
444 }
445 __ bind(*stub->continuation());
446 }
447
448 if (compilation()->env()->dtrace_method_probes()) {
449 #ifdef _LP64
450 __ mov(rdi, r15_thread);
451 __ mov_metadata(rsi, method()->constant_encoding());
452 #else
453 __ get_thread(rax);
454 __ movptr(Address(rsp, 0), rax);
455 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding(), noreg);
456 #endif
457 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
458 }
459
460 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
461 __ mov(rax, rbx); // Restore the exception
462 }
463
464 // remove the activation and dispatch to the unwind handler
465 __ remove_frame(initial_frame_size_in_bytes());
466 __ jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
467
468 // Emit the slow path assembly
469 if (stub != nullptr) {
470 stub->emit_code(this);
471 }
472
473 return offset;
474 }
475
476
477 int LIR_Assembler::emit_deopt_handler() {
478 // generate code for exception handler
479 address handler_base = __ start_a_stub(deopt_handler_size());
480 if (handler_base == nullptr) {
481 // not enough space left for the handler
482 bailout("deopt handler overflow");
483 return -1;
484 }
485
486 int offset = code_offset();
487 InternalAddress here(__ pc());
488
489 __ pushptr(here.addr(), rscratch1);
490 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
491 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
492 __ end_a_stub();
493
494 return offset;
495 }
496
497 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
498 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
499 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
500 assert(result->fpu() == 0, "result must already be on TOS");
501 }
502
503 // Pop the stack before the safepoint code
504 __ remove_frame(initial_frame_size_in_bytes());
505
506 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
507 __ reserved_stack_check();
508 }
509
510 // Note: we do not need to round double result; float result has the right precision
511 // the poll sets the condition code, but no data registers
512
513 #ifdef _LP64
514 const Register thread = r15_thread;
515 #else
516 const Register thread = rbx;
517 __ get_thread(thread);
518 #endif
519 code_stub->set_safepoint_offset(__ offset());
520 __ relocate(relocInfo::poll_return_type);
521 __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */);
522 __ ret(0);
523 }
524
525
526 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
527 guarantee(info != nullptr, "Shouldn't be null");
528 int offset = __ offset();
529 #ifdef _LP64
530 const Register poll_addr = rscratch1;
531 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
532 #else
533 assert(tmp->is_cpu_register(), "needed");
534 const Register poll_addr = tmp->as_register();
535 __ get_thread(poll_addr);
536 __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset())));
537 #endif
538 add_debug_info_for_branch(info);
539 __ relocate(relocInfo::poll_type);
540 address pre_pc = __ pc();
541 __ testl(rax, Address(poll_addr, 0));
542 address post_pc = __ pc();
543 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
544 return offset;
545 }
546
547
548 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
549 if (from_reg != to_reg) __ mov(to_reg, from_reg);
550 }
551
552 void LIR_Assembler::swap_reg(Register a, Register b) {
553 __ xchgptr(a, b);
554 }
555
556
557 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
558 assert(src->is_constant(), "should not call otherwise");
559 assert(dest->is_register(), "should not call otherwise");
560 LIR_Const* c = src->as_constant_ptr();
561
562 switch (c->type()) {
563 case T_INT: {
564 assert(patch_code == lir_patch_none, "no patching handled here");
565 __ movl(dest->as_register(), c->as_jint());
566 break;
567 }
568
569 case T_ADDRESS: {
570 assert(patch_code == lir_patch_none, "no patching handled here");
571 __ movptr(dest->as_register(), c->as_jint());
572 break;
573 }
574
575 case T_LONG: {
576 assert(patch_code == lir_patch_none, "no patching handled here");
577 #ifdef _LP64
578 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
579 #else
580 __ movptr(dest->as_register_lo(), c->as_jint_lo());
581 __ movptr(dest->as_register_hi(), c->as_jint_hi());
582 #endif // _LP64
583 break;
584 }
585
586 case T_OBJECT: {
587 if (patch_code != lir_patch_none) {
588 jobject2reg_with_patching(dest->as_register(), info);
589 } else {
590 __ movoop(dest->as_register(), c->as_jobject());
591 }
592 break;
593 }
594
595 case T_METADATA: {
596 if (patch_code != lir_patch_none) {
597 klass2reg_with_patching(dest->as_register(), info);
598 } else {
599 __ mov_metadata(dest->as_register(), c->as_metadata());
600 }
601 break;
602 }
603
604 case T_FLOAT: {
605 if (dest->is_single_xmm()) {
606 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
607 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
608 } else {
609 __ movflt(dest->as_xmm_float_reg(),
610 InternalAddress(float_constant(c->as_jfloat())));
611 }
612 } else {
613 #ifndef _LP64
614 assert(dest->is_single_fpu(), "must be");
615 assert(dest->fpu_regnr() == 0, "dest must be TOS");
616 if (c->is_zero_float()) {
617 __ fldz();
618 } else if (c->is_one_float()) {
619 __ fld1();
620 } else {
621 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
622 }
623 #else
624 ShouldNotReachHere();
625 #endif // !_LP64
626 }
627 break;
628 }
629
630 case T_DOUBLE: {
631 if (dest->is_double_xmm()) {
632 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
633 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
634 } else {
635 __ movdbl(dest->as_xmm_double_reg(),
636 InternalAddress(double_constant(c->as_jdouble())));
637 }
638 } else {
639 #ifndef _LP64
640 assert(dest->is_double_fpu(), "must be");
641 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
642 if (c->is_zero_double()) {
643 __ fldz();
644 } else if (c->is_one_double()) {
645 __ fld1();
646 } else {
647 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
648 }
649 #else
650 ShouldNotReachHere();
651 #endif // !_LP64
652 }
653 break;
654 }
655
656 default:
657 ShouldNotReachHere();
658 }
659 }
660
661 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
662 assert(src->is_constant(), "should not call otherwise");
663 assert(dest->is_stack(), "should not call otherwise");
664 LIR_Const* c = src->as_constant_ptr();
665
666 switch (c->type()) {
667 case T_INT: // fall through
668 case T_FLOAT:
669 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
670 break;
671
672 case T_ADDRESS:
673 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
674 break;
675
676 case T_OBJECT:
677 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1);
678 break;
679
680 case T_LONG: // fall through
681 case T_DOUBLE:
682 #ifdef _LP64
683 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
684 lo_word_offset_in_bytes),
685 (intptr_t)c->as_jlong_bits(),
686 rscratch1);
687 #else
688 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
689 lo_word_offset_in_bytes), c->as_jint_lo_bits());
690 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
691 hi_word_offset_in_bytes), c->as_jint_hi_bits());
692 #endif // _LP64
693 break;
694
695 default:
696 ShouldNotReachHere();
697 }
698 }
699
700 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
701 assert(src->is_constant(), "should not call otherwise");
702 assert(dest->is_address(), "should not call otherwise");
703 LIR_Const* c = src->as_constant_ptr();
704 LIR_Address* addr = dest->as_address_ptr();
705
706 int null_check_here = code_offset();
707 switch (type) {
708 case T_INT: // fall through
709 case T_FLOAT:
710 __ movl(as_Address(addr), c->as_jint_bits());
711 break;
712
713 case T_ADDRESS:
714 __ movptr(as_Address(addr), c->as_jint_bits());
715 break;
716
717 case T_OBJECT: // fall through
718 case T_ARRAY:
719 if (c->as_jobject() == nullptr) {
720 if (UseCompressedOops && !wide) {
721 __ movl(as_Address(addr), NULL_WORD);
722 } else {
723 #ifdef _LP64
724 __ xorptr(rscratch1, rscratch1);
725 null_check_here = code_offset();
726 __ movptr(as_Address(addr), rscratch1);
727 #else
728 __ movptr(as_Address(addr), NULL_WORD);
729 #endif
730 }
731 } else {
732 if (is_literal_address(addr)) {
733 ShouldNotReachHere();
734 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1);
735 } else {
736 #ifdef _LP64
737 __ movoop(rscratch1, c->as_jobject());
738 if (UseCompressedOops && !wide) {
739 __ encode_heap_oop(rscratch1);
740 null_check_here = code_offset();
741 __ movl(as_Address_lo(addr), rscratch1);
742 } else {
743 null_check_here = code_offset();
744 __ movptr(as_Address_lo(addr), rscratch1);
745 }
746 #else
747 __ movoop(as_Address(addr), c->as_jobject(), noreg);
748 #endif
749 }
750 }
751 break;
752
753 case T_LONG: // fall through
754 case T_DOUBLE:
755 #ifdef _LP64
756 if (is_literal_address(addr)) {
757 ShouldNotReachHere();
758 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
759 } else {
760 __ movptr(r10, (intptr_t)c->as_jlong_bits());
761 null_check_here = code_offset();
762 __ movptr(as_Address_lo(addr), r10);
763 }
764 #else
765 // Always reachable in 32bit so this doesn't produce useless move literal
766 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
767 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
768 #endif // _LP64
769 break;
770
771 case T_BOOLEAN: // fall through
772 case T_BYTE:
773 __ movb(as_Address(addr), c->as_jint() & 0xFF);
774 break;
775
776 case T_CHAR: // fall through
777 case T_SHORT:
778 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
779 break;
780
781 default:
782 ShouldNotReachHere();
783 };
784
785 if (info != nullptr) {
786 add_debug_info_for_null_check(null_check_here, info);
787 }
788 }
789
790
791 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
792 assert(src->is_register(), "should not call otherwise");
793 assert(dest->is_register(), "should not call otherwise");
794
795 // move between cpu-registers
796 if (dest->is_single_cpu()) {
797 #ifdef _LP64
798 if (src->type() == T_LONG) {
799 // Can do LONG -> OBJECT
800 move_regs(src->as_register_lo(), dest->as_register());
801 return;
802 }
803 #endif
804 assert(src->is_single_cpu(), "must match");
805 if (src->type() == T_OBJECT) {
806 __ verify_oop(src->as_register());
807 }
808 move_regs(src->as_register(), dest->as_register());
809
810 } else if (dest->is_double_cpu()) {
811 #ifdef _LP64
812 if (is_reference_type(src->type())) {
813 // Surprising to me but we can see move of a long to t_object
814 __ verify_oop(src->as_register());
815 move_regs(src->as_register(), dest->as_register_lo());
816 return;
817 }
818 #endif
819 assert(src->is_double_cpu(), "must match");
820 Register f_lo = src->as_register_lo();
821 Register f_hi = src->as_register_hi();
822 Register t_lo = dest->as_register_lo();
823 Register t_hi = dest->as_register_hi();
824 #ifdef _LP64
825 assert(f_hi == f_lo, "must be same");
826 assert(t_hi == t_lo, "must be same");
827 move_regs(f_lo, t_lo);
828 #else
829 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
830
831
832 if (f_lo == t_hi && f_hi == t_lo) {
833 swap_reg(f_lo, f_hi);
834 } else if (f_hi == t_lo) {
835 assert(f_lo != t_hi, "overwriting register");
836 move_regs(f_hi, t_hi);
837 move_regs(f_lo, t_lo);
838 } else {
839 assert(f_hi != t_lo, "overwriting register");
840 move_regs(f_lo, t_lo);
841 move_regs(f_hi, t_hi);
842 }
843 #endif // LP64
844
845 #ifndef _LP64
846 // special moves from fpu-register to xmm-register
847 // necessary for method results
848 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
849 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
850 __ fld_s(Address(rsp, 0));
851 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
852 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
853 __ fld_d(Address(rsp, 0));
854 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
855 __ fstp_s(Address(rsp, 0));
856 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
857 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
858 __ fstp_d(Address(rsp, 0));
859 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
860 #endif // !_LP64
861
862 // move between xmm-registers
863 } else if (dest->is_single_xmm()) {
864 assert(src->is_single_xmm(), "must match");
865 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
866 } else if (dest->is_double_xmm()) {
867 assert(src->is_double_xmm(), "must match");
868 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
869
870 #ifndef _LP64
871 // move between fpu-registers (no instruction necessary because of fpu-stack)
872 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
873 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
874 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
875 #endif // !_LP64
876
877 } else {
878 ShouldNotReachHere();
879 }
880 }
881
882 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
883 assert(src->is_register(), "should not call otherwise");
884 assert(dest->is_stack(), "should not call otherwise");
885
886 if (src->is_single_cpu()) {
887 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
888 if (is_reference_type(type)) {
889 __ verify_oop(src->as_register());
890 __ movptr (dst, src->as_register());
891 } else if (type == T_METADATA || type == T_ADDRESS) {
892 __ movptr (dst, src->as_register());
893 } else {
894 __ movl (dst, src->as_register());
895 }
896
897 } else if (src->is_double_cpu()) {
898 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
899 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
900 __ movptr (dstLO, src->as_register_lo());
901 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
902
903 } else if (src->is_single_xmm()) {
904 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
905 __ movflt(dst_addr, src->as_xmm_float_reg());
906
907 } else if (src->is_double_xmm()) {
908 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
909 __ movdbl(dst_addr, src->as_xmm_double_reg());
910
911 #ifndef _LP64
912 } else if (src->is_single_fpu()) {
913 assert(src->fpu_regnr() == 0, "argument must be on TOS");
914 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
915 if (pop_fpu_stack) __ fstp_s (dst_addr);
916 else __ fst_s (dst_addr);
917
918 } else if (src->is_double_fpu()) {
919 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
920 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
921 if (pop_fpu_stack) __ fstp_d (dst_addr);
922 else __ fst_d (dst_addr);
923 #endif // !_LP64
924
925 } else {
926 ShouldNotReachHere();
927 }
928 }
929
930
931 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
932 LIR_Address* to_addr = dest->as_address_ptr();
933 PatchingStub* patch = nullptr;
934 Register compressed_src = rscratch1;
935
936 if (is_reference_type(type)) {
937 __ verify_oop(src->as_register());
938 #ifdef _LP64
939 if (UseCompressedOops && !wide) {
940 __ movptr(compressed_src, src->as_register());
941 __ encode_heap_oop(compressed_src);
942 if (patch_code != lir_patch_none) {
943 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
944 }
945 }
946 #endif
947 }
948
949 if (patch_code != lir_patch_none) {
950 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
951 Address toa = as_Address(to_addr);
952 assert(toa.disp() != 0, "must have");
953 }
954
955 int null_check_here = code_offset();
956 switch (type) {
957 case T_FLOAT: {
958 #ifdef _LP64
959 assert(src->is_single_xmm(), "not a float");
960 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
961 #else
962 if (src->is_single_xmm()) {
963 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
964 } else {
965 assert(src->is_single_fpu(), "must be");
966 assert(src->fpu_regnr() == 0, "argument must be on TOS");
967 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
968 else __ fst_s (as_Address(to_addr));
969 }
970 #endif // _LP64
971 break;
972 }
973
974 case T_DOUBLE: {
975 #ifdef _LP64
976 assert(src->is_double_xmm(), "not a double");
977 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
978 #else
979 if (src->is_double_xmm()) {
980 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
981 } else {
982 assert(src->is_double_fpu(), "must be");
983 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
984 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
985 else __ fst_d (as_Address(to_addr));
986 }
987 #endif // _LP64
988 break;
989 }
990
991 case T_ARRAY: // fall through
992 case T_OBJECT: // fall through
993 if (UseCompressedOops && !wide) {
994 __ movl(as_Address(to_addr), compressed_src);
995 } else {
996 __ movptr(as_Address(to_addr), src->as_register());
997 }
998 break;
999 case T_METADATA:
1000 // We get here to store a method pointer to the stack to pass to
1001 // a dtrace runtime call. This can't work on 64 bit with
1002 // compressed klass ptrs: T_METADATA can be a compressed klass
1003 // ptr or a 64 bit method pointer.
1004 LP64_ONLY(ShouldNotReachHere());
1005 __ movptr(as_Address(to_addr), src->as_register());
1006 break;
1007 case T_ADDRESS:
1008 __ movptr(as_Address(to_addr), src->as_register());
1009 break;
1010 case T_INT:
1011 __ movl(as_Address(to_addr), src->as_register());
1012 break;
1013
1014 case T_LONG: {
1015 Register from_lo = src->as_register_lo();
1016 Register from_hi = src->as_register_hi();
1017 #ifdef _LP64
1018 __ movptr(as_Address_lo(to_addr), from_lo);
1019 #else
1020 Register base = to_addr->base()->as_register();
1021 Register index = noreg;
1022 if (to_addr->index()->is_register()) {
1023 index = to_addr->index()->as_register();
1024 }
1025 if (base == from_lo || index == from_lo) {
1026 assert(base != from_hi, "can't be");
1027 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1028 __ movl(as_Address_hi(to_addr), from_hi);
1029 if (patch != nullptr) {
1030 patching_epilog(patch, lir_patch_high, base, info);
1031 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1032 patch_code = lir_patch_low;
1033 }
1034 __ movl(as_Address_lo(to_addr), from_lo);
1035 } else {
1036 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1037 __ movl(as_Address_lo(to_addr), from_lo);
1038 if (patch != nullptr) {
1039 patching_epilog(patch, lir_patch_low, base, info);
1040 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1041 patch_code = lir_patch_high;
1042 }
1043 __ movl(as_Address_hi(to_addr), from_hi);
1044 }
1045 #endif // _LP64
1046 break;
1047 }
1048
1049 case T_BYTE: // fall through
1050 case T_BOOLEAN: {
1051 Register src_reg = src->as_register();
1052 Address dst_addr = as_Address(to_addr);
1053 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1054 __ movb(dst_addr, src_reg);
1055 break;
1056 }
1057
1058 case T_CHAR: // fall through
1059 case T_SHORT:
1060 __ movw(as_Address(to_addr), src->as_register());
1061 break;
1062
1063 default:
1064 ShouldNotReachHere();
1065 }
1066 if (info != nullptr) {
1067 add_debug_info_for_null_check(null_check_here, info);
1068 }
1069
1070 if (patch_code != lir_patch_none) {
1071 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1072 }
1073 }
1074
1075
1076 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1077 assert(src->is_stack(), "should not call otherwise");
1078 assert(dest->is_register(), "should not call otherwise");
1079
1080 if (dest->is_single_cpu()) {
1081 if (is_reference_type(type)) {
1082 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1083 __ verify_oop(dest->as_register());
1084 } else if (type == T_METADATA || type == T_ADDRESS) {
1085 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1086 } else {
1087 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1088 }
1089
1090 } else if (dest->is_double_cpu()) {
1091 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1092 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1093 __ movptr(dest->as_register_lo(), src_addr_LO);
1094 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1095
1096 } else if (dest->is_single_xmm()) {
1097 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1098 __ movflt(dest->as_xmm_float_reg(), src_addr);
1099
1100 } else if (dest->is_double_xmm()) {
1101 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1102 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1103
1104 #ifndef _LP64
1105 } else if (dest->is_single_fpu()) {
1106 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1107 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1108 __ fld_s(src_addr);
1109
1110 } else if (dest->is_double_fpu()) {
1111 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1112 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1113 __ fld_d(src_addr);
1114 #endif // _LP64
1115
1116 } else {
1117 ShouldNotReachHere();
1118 }
1119 }
1120
1121
1122 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1123 if (src->is_single_stack()) {
1124 if (is_reference_type(type)) {
1125 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1126 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1127 } else {
1128 #ifndef _LP64
1129 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1130 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1131 #else
1132 //no pushl on 64bits
1133 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1134 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1135 #endif
1136 }
1137
1138 } else if (src->is_double_stack()) {
1139 #ifdef _LP64
1140 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1141 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1142 #else
1143 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1144 // push and pop the part at src + wordSize, adding wordSize for the previous push
1145 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1146 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1147 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1148 #endif // _LP64
1149
1150 } else {
1151 ShouldNotReachHere();
1152 }
1153 }
1154
1155
1156 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1157 assert(src->is_address(), "should not call otherwise");
1158 assert(dest->is_register(), "should not call otherwise");
1159
1160 LIR_Address* addr = src->as_address_ptr();
1161 Address from_addr = as_Address(addr);
1162
1163 if (addr->base()->type() == T_OBJECT) {
1164 __ verify_oop(addr->base()->as_pointer_register());
1165 }
1166
1167 switch (type) {
1168 case T_BOOLEAN: // fall through
1169 case T_BYTE: // fall through
1170 case T_CHAR: // fall through
1171 case T_SHORT:
1172 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1173 // on pre P6 processors we may get partial register stalls
1174 // so blow away the value of to_rinfo before loading a
1175 // partial word into it. Do it here so that it precedes
1176 // the potential patch point below.
1177 __ xorptr(dest->as_register(), dest->as_register());
1178 }
1179 break;
1180 default:
1181 break;
1182 }
1183
1184 PatchingStub* patch = nullptr;
1185 if (patch_code != lir_patch_none) {
1186 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1187 assert(from_addr.disp() != 0, "must have");
1188 }
1189 if (info != nullptr) {
1190 add_debug_info_for_null_check_here(info);
1191 }
1192
1193 switch (type) {
1194 case T_FLOAT: {
1195 if (dest->is_single_xmm()) {
1196 __ movflt(dest->as_xmm_float_reg(), from_addr);
1197 } else {
1198 #ifndef _LP64
1199 assert(dest->is_single_fpu(), "must be");
1200 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1201 __ fld_s(from_addr);
1202 #else
1203 ShouldNotReachHere();
1204 #endif // !LP64
1205 }
1206 break;
1207 }
1208
1209 case T_DOUBLE: {
1210 if (dest->is_double_xmm()) {
1211 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1212 } else {
1213 #ifndef _LP64
1214 assert(dest->is_double_fpu(), "must be");
1215 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1216 __ fld_d(from_addr);
1217 #else
1218 ShouldNotReachHere();
1219 #endif // !LP64
1220 }
1221 break;
1222 }
1223
1224 case T_OBJECT: // fall through
1225 case T_ARRAY: // fall through
1226 if (UseCompressedOops && !wide) {
1227 __ movl(dest->as_register(), from_addr);
1228 } else {
1229 __ movptr(dest->as_register(), from_addr);
1230 }
1231 break;
1232
1233 case T_ADDRESS:
1234 __ movptr(dest->as_register(), from_addr);
1235 break;
1236 case T_INT:
1237 __ movl(dest->as_register(), from_addr);
1238 break;
1239
1240 case T_LONG: {
1241 Register to_lo = dest->as_register_lo();
1242 Register to_hi = dest->as_register_hi();
1243 #ifdef _LP64
1244 __ movptr(to_lo, as_Address_lo(addr));
1245 #else
1246 Register base = addr->base()->as_register();
1247 Register index = noreg;
1248 if (addr->index()->is_register()) {
1249 index = addr->index()->as_register();
1250 }
1251 if ((base == to_lo && index == to_hi) ||
1252 (base == to_hi && index == to_lo)) {
1253 // addresses with 2 registers are only formed as a result of
1254 // array access so this code will never have to deal with
1255 // patches or null checks.
1256 assert(info == nullptr && patch == nullptr, "must be");
1257 __ lea(to_hi, as_Address(addr));
1258 __ movl(to_lo, Address(to_hi, 0));
1259 __ movl(to_hi, Address(to_hi, BytesPerWord));
1260 } else if (base == to_lo || index == to_lo) {
1261 assert(base != to_hi, "can't be");
1262 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1263 __ movl(to_hi, as_Address_hi(addr));
1264 if (patch != nullptr) {
1265 patching_epilog(patch, lir_patch_high, base, info);
1266 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1267 patch_code = lir_patch_low;
1268 }
1269 __ movl(to_lo, as_Address_lo(addr));
1270 } else {
1271 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1272 __ movl(to_lo, as_Address_lo(addr));
1273 if (patch != nullptr) {
1274 patching_epilog(patch, lir_patch_low, base, info);
1275 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1276 patch_code = lir_patch_high;
1277 }
1278 __ movl(to_hi, as_Address_hi(addr));
1279 }
1280 #endif // _LP64
1281 break;
1282 }
1283
1284 case T_BOOLEAN: // fall through
1285 case T_BYTE: {
1286 Register dest_reg = dest->as_register();
1287 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1288 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1289 __ movsbl(dest_reg, from_addr);
1290 } else {
1291 __ movb(dest_reg, from_addr);
1292 __ shll(dest_reg, 24);
1293 __ sarl(dest_reg, 24);
1294 }
1295 break;
1296 }
1297
1298 case T_CHAR: {
1299 Register dest_reg = dest->as_register();
1300 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1301 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1302 __ movzwl(dest_reg, from_addr);
1303 } else {
1304 __ movw(dest_reg, from_addr);
1305 }
1306 break;
1307 }
1308
1309 case T_SHORT: {
1310 Register dest_reg = dest->as_register();
1311 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1312 __ movswl(dest_reg, from_addr);
1313 } else {
1314 __ movw(dest_reg, from_addr);
1315 __ shll(dest_reg, 16);
1316 __ sarl(dest_reg, 16);
1317 }
1318 break;
1319 }
1320
1321 default:
1322 ShouldNotReachHere();
1323 }
1324
1325 if (patch != nullptr) {
1326 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1327 }
1328
1329 if (is_reference_type(type)) {
1330 #ifdef _LP64
1331 if (UseCompressedOops && !wide) {
1332 __ decode_heap_oop(dest->as_register());
1333 }
1334 #endif
1335
1336 __ verify_oop(dest->as_register());
1337 }
1338 }
1339
1340
1341 NEEDS_CLEANUP; // This could be static?
1342 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1343 int elem_size = type2aelembytes(type);
1344 switch (elem_size) {
1345 case 1: return Address::times_1;
1346 case 2: return Address::times_2;
1347 case 4: return Address::times_4;
1348 case 8: return Address::times_8;
1349 }
1350 ShouldNotReachHere();
1351 return Address::no_scale;
1352 }
1353
1354
1355 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1356 switch (op->code()) {
1357 case lir_idiv:
1358 case lir_irem:
1359 arithmetic_idiv(op->code(),
1360 op->in_opr1(),
1361 op->in_opr2(),
1362 op->in_opr3(),
1363 op->result_opr(),
1364 op->info());
1365 break;
1366 case lir_fmad:
1367 __ fmad(op->result_opr()->as_xmm_double_reg(),
1368 op->in_opr1()->as_xmm_double_reg(),
1369 op->in_opr2()->as_xmm_double_reg(),
1370 op->in_opr3()->as_xmm_double_reg());
1371 break;
1372 case lir_fmaf:
1373 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1374 op->in_opr1()->as_xmm_float_reg(),
1375 op->in_opr2()->as_xmm_float_reg(),
1376 op->in_opr3()->as_xmm_float_reg());
1377 break;
1378 default: ShouldNotReachHere(); break;
1379 }
1380 }
1381
1382 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1383 #ifdef ASSERT
1384 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1385 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1386 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1387 #endif
1388
1389 if (op->cond() == lir_cond_always) {
1390 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1391 __ jmp (*(op->label()));
1392 } else {
1393 Assembler::Condition acond = Assembler::zero;
1394 if (op->code() == lir_cond_float_branch) {
1395 assert(op->ublock() != nullptr, "must have unordered successor");
1396 __ jcc(Assembler::parity, *(op->ublock()->label()));
1397 switch(op->cond()) {
1398 case lir_cond_equal: acond = Assembler::equal; break;
1399 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1400 case lir_cond_less: acond = Assembler::below; break;
1401 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1402 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1403 case lir_cond_greater: acond = Assembler::above; break;
1404 default: ShouldNotReachHere();
1405 }
1406 } else {
1407 switch (op->cond()) {
1408 case lir_cond_equal: acond = Assembler::equal; break;
1409 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1410 case lir_cond_less: acond = Assembler::less; break;
1411 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1412 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1413 case lir_cond_greater: acond = Assembler::greater; break;
1414 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1415 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1416 default: ShouldNotReachHere();
1417 }
1418 }
1419 __ jcc(acond,*(op->label()));
1420 }
1421 }
1422
1423 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1424 LIR_Opr src = op->in_opr();
1425 LIR_Opr dest = op->result_opr();
1426
1427 switch (op->bytecode()) {
1428 case Bytecodes::_i2l:
1429 #ifdef _LP64
1430 __ movl2ptr(dest->as_register_lo(), src->as_register());
1431 #else
1432 move_regs(src->as_register(), dest->as_register_lo());
1433 move_regs(src->as_register(), dest->as_register_hi());
1434 __ sarl(dest->as_register_hi(), 31);
1435 #endif // LP64
1436 break;
1437
1438 case Bytecodes::_l2i:
1439 #ifdef _LP64
1440 __ movl(dest->as_register(), src->as_register_lo());
1441 #else
1442 move_regs(src->as_register_lo(), dest->as_register());
1443 #endif
1444 break;
1445
1446 case Bytecodes::_i2b:
1447 move_regs(src->as_register(), dest->as_register());
1448 __ sign_extend_byte(dest->as_register());
1449 break;
1450
1451 case Bytecodes::_i2c:
1452 move_regs(src->as_register(), dest->as_register());
1453 __ andl(dest->as_register(), 0xFFFF);
1454 break;
1455
1456 case Bytecodes::_i2s:
1457 move_regs(src->as_register(), dest->as_register());
1458 __ sign_extend_short(dest->as_register());
1459 break;
1460
1461
1462 #ifdef _LP64
1463 case Bytecodes::_f2d:
1464 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1465 break;
1466
1467 case Bytecodes::_d2f:
1468 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1469 break;
1470
1471 case Bytecodes::_i2f:
1472 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1473 break;
1474
1475 case Bytecodes::_i2d:
1476 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1477 break;
1478
1479 case Bytecodes::_l2f:
1480 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1481 break;
1482
1483 case Bytecodes::_l2d:
1484 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1485 break;
1486
1487 case Bytecodes::_f2i:
1488 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1489 break;
1490
1491 case Bytecodes::_d2i:
1492 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1493 break;
1494
1495 case Bytecodes::_f2l:
1496 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1497 break;
1498
1499 case Bytecodes::_d2l:
1500 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1501 break;
1502 #else
1503 case Bytecodes::_f2d:
1504 case Bytecodes::_d2f:
1505 if (dest->is_single_xmm()) {
1506 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1507 } else if (dest->is_double_xmm()) {
1508 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1509 } else {
1510 assert(src->fpu() == dest->fpu(), "register must be equal");
1511 // do nothing (float result is rounded later through spilling)
1512 }
1513 break;
1514
1515 case Bytecodes::_i2f:
1516 case Bytecodes::_i2d:
1517 if (dest->is_single_xmm()) {
1518 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1519 } else if (dest->is_double_xmm()) {
1520 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1521 } else {
1522 assert(dest->fpu() == 0, "result must be on TOS");
1523 __ movl(Address(rsp, 0), src->as_register());
1524 __ fild_s(Address(rsp, 0));
1525 }
1526 break;
1527
1528 case Bytecodes::_l2f:
1529 case Bytecodes::_l2d:
1530 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1531 assert(dest->fpu() == 0, "result must be on TOS");
1532 __ movptr(Address(rsp, 0), src->as_register_lo());
1533 __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1534 __ fild_d(Address(rsp, 0));
1535 // float result is rounded later through spilling
1536 break;
1537
1538 case Bytecodes::_f2i:
1539 case Bytecodes::_d2i:
1540 if (src->is_single_xmm()) {
1541 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1542 } else if (src->is_double_xmm()) {
1543 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1544 } else {
1545 assert(src->fpu() == 0, "input must be on TOS");
1546 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc()));
1547 __ fist_s(Address(rsp, 0));
1548 __ movl(dest->as_register(), Address(rsp, 0));
1549 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
1550 }
1551 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1552 assert(op->stub() != nullptr, "stub required");
1553 __ cmpl(dest->as_register(), 0x80000000);
1554 __ jcc(Assembler::equal, *op->stub()->entry());
1555 __ bind(*op->stub()->continuation());
1556 break;
1557
1558 case Bytecodes::_f2l:
1559 case Bytecodes::_d2l:
1560 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1561 assert(src->fpu() == 0, "input must be on TOS");
1562 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1563
1564 // instruction sequence too long to inline it here
1565 {
1566 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::fpu2long_stub_id)));
1567 }
1568 break;
1569 #endif // _LP64
1570
1571 default: ShouldNotReachHere();
1572 }
1573 }
1574
1575 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1576 if (op->init_check()) {
1577 add_debug_info_for_null_check_here(op->stub()->info());
1578 // init_state needs acquire, but x86 is TSO, and so we are already good.
1579 __ cmpb(Address(op->klass()->as_register(),
1580 InstanceKlass::init_state_offset()),
1581 InstanceKlass::fully_initialized);
1582 __ jcc(Assembler::notEqual, *op->stub()->entry());
1583 }
1584 __ allocate_object(op->obj()->as_register(),
1585 op->tmp1()->as_register(),
1586 op->tmp2()->as_register(),
1587 op->header_size(),
1588 op->object_size(),
1589 op->klass()->as_register(),
1590 *op->stub()->entry());
1591 __ bind(*op->stub()->continuation());
1592 }
1593
1594 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1595 Register len = op->len()->as_register();
1596 LP64_ONLY( __ movslq(len, len); )
1597
1598 if (UseSlowPath ||
1599 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1600 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1601 __ jmp(*op->stub()->entry());
1602 } else {
1603 Register tmp1 = op->tmp1()->as_register();
1604 Register tmp2 = op->tmp2()->as_register();
1605 Register tmp3 = op->tmp3()->as_register();
1606 if (len == tmp1) {
1607 tmp1 = tmp3;
1608 } else if (len == tmp2) {
1609 tmp2 = tmp3;
1610 } else if (len == tmp3) {
1611 // everything is ok
1612 } else {
1613 __ mov(tmp3, len);
1614 }
1615 __ allocate_array(op->obj()->as_register(),
1616 len,
1617 tmp1,
1618 tmp2,
1619 arrayOopDesc::base_offset_in_bytes(op->type()),
1620 array_element_size(op->type()),
1621 op->klass()->as_register(),
1622 *op->stub()->entry(),
1623 op->zero_array());
1624 }
1625 __ bind(*op->stub()->continuation());
1626 }
1627
1628 void LIR_Assembler::type_profile_helper(Register mdo,
1629 ciMethodData *md, ciProfileData *data,
1630 Register recv, Label* update_done) {
1631 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1632 Label next_test;
1633 // See if the receiver is receiver[n].
1634 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1635 __ jccb(Assembler::notEqual, next_test);
1636 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1637 __ addptr(data_addr, DataLayout::counter_increment);
1638 __ jmp(*update_done);
1639 __ bind(next_test);
1640 }
1641
1642 // Didn't find receiver; find next empty slot and fill it in
1643 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1644 Label next_test;
1645 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1646 __ cmpptr(recv_addr, NULL_WORD);
1647 __ jccb(Assembler::notEqual, next_test);
1648 __ movptr(recv_addr, recv);
1649 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1650 __ jmp(*update_done);
1651 __ bind(next_test);
1652 }
1653 }
1654
1655 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1656 // we always need a stub for the failure case.
1657 CodeStub* stub = op->stub();
1658 Register obj = op->object()->as_register();
1659 Register k_RInfo = op->tmp1()->as_register();
1660 Register klass_RInfo = op->tmp2()->as_register();
1661 Register dst = op->result_opr()->as_register();
1662 ciKlass* k = op->klass();
1663 Register Rtmp1 = noreg;
1664 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1665
1666 // check if it needs to be profiled
1667 ciMethodData* md = nullptr;
1668 ciProfileData* data = nullptr;
1669
1670 if (op->should_profile()) {
1671 ciMethod* method = op->profiled_method();
1672 assert(method != nullptr, "Should have method");
1673 int bci = op->profiled_bci();
1674 md = method->method_data_or_null();
1675 assert(md != nullptr, "Sanity");
1676 data = md->bci_to_data(bci);
1677 assert(data != nullptr, "need data for type check");
1678 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1679 }
1680 Label* success_target = success;
1681 Label* failure_target = failure;
1682
1683 if (obj == k_RInfo) {
1684 k_RInfo = dst;
1685 } else if (obj == klass_RInfo) {
1686 klass_RInfo = dst;
1687 }
1688 if (k->is_loaded() && !UseCompressedClassPointers) {
1689 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1690 } else {
1691 Rtmp1 = op->tmp3()->as_register();
1692 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1693 }
1694
1695 assert_different_registers(obj, k_RInfo, klass_RInfo);
1696
1697 __ testptr(obj, obj);
1698 if (op->should_profile()) {
1699 Label not_null;
1700 Register mdo = klass_RInfo;
1701 __ mov_metadata(mdo, md->constant_encoding());
1702 __ jccb(Assembler::notEqual, not_null);
1703 // Object is null; update MDO and exit
1704 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1705 int header_bits = BitData::null_seen_byte_constant();
1706 __ orb(data_addr, header_bits);
1707 __ jmp(*obj_is_null);
1708 __ bind(not_null);
1709
1710 Label update_done;
1711 Register recv = k_RInfo;
1712 __ load_klass(recv, obj, tmp_load_klass);
1713 type_profile_helper(mdo, md, data, recv, &update_done);
1714
1715 Address nonprofiled_receiver_count_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1716 __ addptr(nonprofiled_receiver_count_addr, DataLayout::counter_increment);
1717
1718 __ bind(update_done);
1719 } else {
1720 __ jcc(Assembler::equal, *obj_is_null);
1721 }
1722
1723 if (!k->is_loaded()) {
1724 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1725 } else {
1726 #ifdef _LP64
1727 __ mov_metadata(k_RInfo, k->constant_encoding());
1728 #endif // _LP64
1729 }
1730 __ verify_oop(obj);
1731
1732 if (op->fast_check()) {
1733 // get object class
1734 // not a safepoint as obj null check happens earlier
1735 #ifdef _LP64
1736 if (UseCompressedClassPointers) {
1737 __ load_klass(Rtmp1, obj, tmp_load_klass);
1738 __ cmpptr(k_RInfo, Rtmp1);
1739 } else {
1740 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1741 }
1742 #else
1743 if (k->is_loaded()) {
1744 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1745 } else {
1746 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1747 }
1748 #endif
1749 __ jcc(Assembler::notEqual, *failure_target);
1750 // successful cast, fall through to profile or jump
1751 } else {
1752 // get object class
1753 // not a safepoint as obj null check happens earlier
1754 __ load_klass(klass_RInfo, obj, tmp_load_klass);
1755 if (k->is_loaded()) {
1756 // See if we get an immediate positive hit
1757 #ifdef _LP64
1758 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1759 #else
1760 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1761 #endif // _LP64
1762 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1763 __ jcc(Assembler::notEqual, *failure_target);
1764 // successful cast, fall through to profile or jump
1765 } else {
1766 // See if we get an immediate positive hit
1767 __ jcc(Assembler::equal, *success_target);
1768 // check for self
1769 #ifdef _LP64
1770 __ cmpptr(klass_RInfo, k_RInfo);
1771 #else
1772 __ cmpklass(klass_RInfo, k->constant_encoding());
1773 #endif // _LP64
1774 __ jcc(Assembler::equal, *success_target);
1775
1776 __ push(klass_RInfo);
1777 #ifdef _LP64
1778 __ push(k_RInfo);
1779 #else
1780 __ pushklass(k->constant_encoding(), noreg);
1781 #endif // _LP64
1782 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1783 __ pop(klass_RInfo);
1784 __ pop(klass_RInfo);
1785 // result is a boolean
1786 __ testl(klass_RInfo, klass_RInfo);
1787 __ jcc(Assembler::equal, *failure_target);
1788 // successful cast, fall through to profile or jump
1789 }
1790 } else {
1791 // perform the fast part of the checking logic
1792 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1793 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1794 __ push(klass_RInfo);
1795 __ push(k_RInfo);
1796 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1797 __ pop(klass_RInfo);
1798 __ pop(k_RInfo);
1799 // result is a boolean
1800 __ testl(k_RInfo, k_RInfo);
1801 __ jcc(Assembler::equal, *failure_target);
1802 // successful cast, fall through to profile or jump
1803 }
1804 }
1805 __ jmp(*success);
1806 }
1807
1808
1809 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1810 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1811 LIR_Code code = op->code();
1812 if (code == lir_store_check) {
1813 Register value = op->object()->as_register();
1814 Register array = op->array()->as_register();
1815 Register k_RInfo = op->tmp1()->as_register();
1816 Register klass_RInfo = op->tmp2()->as_register();
1817 Register Rtmp1 = op->tmp3()->as_register();
1818
1819 CodeStub* stub = op->stub();
1820
1821 // check if it needs to be profiled
1822 ciMethodData* md = nullptr;
1823 ciProfileData* data = nullptr;
1824
1825 if (op->should_profile()) {
1826 ciMethod* method = op->profiled_method();
1827 assert(method != nullptr, "Should have method");
1828 int bci = op->profiled_bci();
1829 md = method->method_data_or_null();
1830 assert(md != nullptr, "Sanity");
1831 data = md->bci_to_data(bci);
1832 assert(data != nullptr, "need data for type check");
1833 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1834 }
1835 Label done;
1836 Label* success_target = &done;
1837 Label* failure_target = stub->entry();
1838
1839 __ testptr(value, value);
1840 if (op->should_profile()) {
1841 Label not_null;
1842 Register mdo = klass_RInfo;
1843 __ mov_metadata(mdo, md->constant_encoding());
1844 __ jccb(Assembler::notEqual, not_null);
1845 // Object is null; update MDO and exit
1846 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1847 int header_bits = BitData::null_seen_byte_constant();
1848 __ orb(data_addr, header_bits);
1849 __ jmp(done);
1850 __ bind(not_null);
1851
1852 Label update_done;
1853 Register recv = k_RInfo;
1854 __ load_klass(recv, value, tmp_load_klass);
1855 type_profile_helper(mdo, md, data, recv, &update_done);
1856
1857 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1858 __ addptr(counter_addr, DataLayout::counter_increment);
1859 __ bind(update_done);
1860 } else {
1861 __ jcc(Assembler::equal, done);
1862 }
1863
1864 add_debug_info_for_null_check_here(op->info_for_exception());
1865 __ load_klass(k_RInfo, array, tmp_load_klass);
1866 __ load_klass(klass_RInfo, value, tmp_load_klass);
1867
1868 // get instance klass (it's already uncompressed)
1869 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1870 // perform the fast part of the checking logic
1871 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1872 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1873 __ push(klass_RInfo);
1874 __ push(k_RInfo);
1875 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1876 __ pop(klass_RInfo);
1877 __ pop(k_RInfo);
1878 // result is a boolean
1879 __ testl(k_RInfo, k_RInfo);
1880 __ jcc(Assembler::equal, *failure_target);
1881 // fall through to the success case
1882
1883 __ bind(done);
1884 } else
1885 if (code == lir_checkcast) {
1886 Register obj = op->object()->as_register();
1887 Register dst = op->result_opr()->as_register();
1888 Label success;
1889 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1890 __ bind(success);
1891 if (dst != obj) {
1892 __ mov(dst, obj);
1893 }
1894 } else
1895 if (code == lir_instanceof) {
1896 Register obj = op->object()->as_register();
1897 Register dst = op->result_opr()->as_register();
1898 Label success, failure, done;
1899 emit_typecheck_helper(op, &success, &failure, &failure);
1900 __ bind(failure);
1901 __ xorptr(dst, dst);
1902 __ jmpb(done);
1903 __ bind(success);
1904 __ movptr(dst, 1);
1905 __ bind(done);
1906 } else {
1907 ShouldNotReachHere();
1908 }
1909
1910 }
1911
1912
1913 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1914 if (LP64_ONLY(false &&) op->code() == lir_cas_long) {
1915 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1916 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1917 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1918 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1919 Register addr = op->addr()->as_register();
1920 __ lock();
1921 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1922
1923 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1924 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1925 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1926 Register newval = op->new_value()->as_register();
1927 Register cmpval = op->cmp_value()->as_register();
1928 assert(cmpval == rax, "wrong register");
1929 assert(newval != noreg, "new val must be register");
1930 assert(cmpval != newval, "cmp and new values must be in different registers");
1931 assert(cmpval != addr, "cmp and addr must be in different registers");
1932 assert(newval != addr, "new value and addr must be in different registers");
1933
1934 if ( op->code() == lir_cas_obj) {
1935 #ifdef _LP64
1936 if (UseCompressedOops) {
1937 __ encode_heap_oop(cmpval);
1938 __ mov(rscratch1, newval);
1939 __ encode_heap_oop(rscratch1);
1940 __ lock();
1941 // cmpval (rax) is implicitly used by this instruction
1942 __ cmpxchgl(rscratch1, Address(addr, 0));
1943 } else
1944 #endif
1945 {
1946 __ lock();
1947 __ cmpxchgptr(newval, Address(addr, 0));
1948 }
1949 } else {
1950 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1951 __ lock();
1952 __ cmpxchgl(newval, Address(addr, 0));
1953 }
1954 #ifdef _LP64
1955 } else if (op->code() == lir_cas_long) {
1956 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1957 Register newval = op->new_value()->as_register_lo();
1958 Register cmpval = op->cmp_value()->as_register_lo();
1959 assert(cmpval == rax, "wrong register");
1960 assert(newval != noreg, "new val must be register");
1961 assert(cmpval != newval, "cmp and new values must be in different registers");
1962 assert(cmpval != addr, "cmp and addr must be in different registers");
1963 assert(newval != addr, "new value and addr must be in different registers");
1964 __ lock();
1965 __ cmpxchgq(newval, Address(addr, 0));
1966 #endif // _LP64
1967 } else {
1968 Unimplemented();
1969 }
1970 }
1971
1972 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1973 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1974 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
1975
1976 Assembler::Condition acond, ncond;
1977 switch (condition) {
1978 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1979 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1980 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1981 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1982 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1983 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1984 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1985 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1986 default: acond = Assembler::equal; ncond = Assembler::notEqual;
1987 ShouldNotReachHere();
1988 }
1989
1990 if (opr1->is_cpu_register()) {
1991 reg2reg(opr1, result);
1992 } else if (opr1->is_stack()) {
1993 stack2reg(opr1, result, result->type());
1994 } else if (opr1->is_constant()) {
1995 const2reg(opr1, result, lir_patch_none, nullptr);
1996 } else {
1997 ShouldNotReachHere();
1998 }
1999
2000 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2001 // optimized version that does not require a branch
2002 if (opr2->is_single_cpu()) {
2003 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2004 __ cmov(ncond, result->as_register(), opr2->as_register());
2005 } else if (opr2->is_double_cpu()) {
2006 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2007 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2008 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2009 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2010 } else if (opr2->is_single_stack()) {
2011 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2012 } else if (opr2->is_double_stack()) {
2013 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2014 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2015 } else {
2016 ShouldNotReachHere();
2017 }
2018
2019 } else {
2020 Label skip;
2021 __ jccb(acond, skip);
2022 if (opr2->is_cpu_register()) {
2023 reg2reg(opr2, result);
2024 } else if (opr2->is_stack()) {
2025 stack2reg(opr2, result, result->type());
2026 } else if (opr2->is_constant()) {
2027 const2reg(opr2, result, lir_patch_none, nullptr);
2028 } else {
2029 ShouldNotReachHere();
2030 }
2031 __ bind(skip);
2032 }
2033 }
2034
2035
2036 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2037 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2038
2039 if (left->is_single_cpu()) {
2040 assert(left == dest, "left and dest must be equal");
2041 Register lreg = left->as_register();
2042
2043 if (right->is_single_cpu()) {
2044 // cpu register - cpu register
2045 Register rreg = right->as_register();
2046 switch (code) {
2047 case lir_add: __ addl (lreg, rreg); break;
2048 case lir_sub: __ subl (lreg, rreg); break;
2049 case lir_mul: __ imull(lreg, rreg); break;
2050 default: ShouldNotReachHere();
2051 }
2052
2053 } else if (right->is_stack()) {
2054 // cpu register - stack
2055 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2056 switch (code) {
2057 case lir_add: __ addl(lreg, raddr); break;
2058 case lir_sub: __ subl(lreg, raddr); break;
2059 default: ShouldNotReachHere();
2060 }
2061
2062 } else if (right->is_constant()) {
2063 // cpu register - constant
2064 jint c = right->as_constant_ptr()->as_jint();
2065 switch (code) {
2066 case lir_add: {
2067 __ incrementl(lreg, c);
2068 break;
2069 }
2070 case lir_sub: {
2071 __ decrementl(lreg, c);
2072 break;
2073 }
2074 default: ShouldNotReachHere();
2075 }
2076
2077 } else {
2078 ShouldNotReachHere();
2079 }
2080
2081 } else if (left->is_double_cpu()) {
2082 assert(left == dest, "left and dest must be equal");
2083 Register lreg_lo = left->as_register_lo();
2084 Register lreg_hi = left->as_register_hi();
2085
2086 if (right->is_double_cpu()) {
2087 // cpu register - cpu register
2088 Register rreg_lo = right->as_register_lo();
2089 Register rreg_hi = right->as_register_hi();
2090 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2091 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2092 switch (code) {
2093 case lir_add:
2094 __ addptr(lreg_lo, rreg_lo);
2095 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2096 break;
2097 case lir_sub:
2098 __ subptr(lreg_lo, rreg_lo);
2099 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2100 break;
2101 case lir_mul:
2102 #ifdef _LP64
2103 __ imulq(lreg_lo, rreg_lo);
2104 #else
2105 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2106 __ imull(lreg_hi, rreg_lo);
2107 __ imull(rreg_hi, lreg_lo);
2108 __ addl (rreg_hi, lreg_hi);
2109 __ mull (rreg_lo);
2110 __ addl (lreg_hi, rreg_hi);
2111 #endif // _LP64
2112 break;
2113 default:
2114 ShouldNotReachHere();
2115 }
2116
2117 } else if (right->is_constant()) {
2118 // cpu register - constant
2119 #ifdef _LP64
2120 jlong c = right->as_constant_ptr()->as_jlong_bits();
2121 __ movptr(r10, (intptr_t) c);
2122 switch (code) {
2123 case lir_add:
2124 __ addptr(lreg_lo, r10);
2125 break;
2126 case lir_sub:
2127 __ subptr(lreg_lo, r10);
2128 break;
2129 default:
2130 ShouldNotReachHere();
2131 }
2132 #else
2133 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2134 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2135 switch (code) {
2136 case lir_add:
2137 __ addptr(lreg_lo, c_lo);
2138 __ adcl(lreg_hi, c_hi);
2139 break;
2140 case lir_sub:
2141 __ subptr(lreg_lo, c_lo);
2142 __ sbbl(lreg_hi, c_hi);
2143 break;
2144 default:
2145 ShouldNotReachHere();
2146 }
2147 #endif // _LP64
2148
2149 } else {
2150 ShouldNotReachHere();
2151 }
2152
2153 } else if (left->is_single_xmm()) {
2154 assert(left == dest, "left and dest must be equal");
2155 XMMRegister lreg = left->as_xmm_float_reg();
2156
2157 if (right->is_single_xmm()) {
2158 XMMRegister rreg = right->as_xmm_float_reg();
2159 switch (code) {
2160 case lir_add: __ addss(lreg, rreg); break;
2161 case lir_sub: __ subss(lreg, rreg); break;
2162 case lir_mul: __ mulss(lreg, rreg); break;
2163 case lir_div: __ divss(lreg, rreg); break;
2164 default: ShouldNotReachHere();
2165 }
2166 } else {
2167 Address raddr;
2168 if (right->is_single_stack()) {
2169 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2170 } else if (right->is_constant()) {
2171 // hack for now
2172 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2173 } else {
2174 ShouldNotReachHere();
2175 }
2176 switch (code) {
2177 case lir_add: __ addss(lreg, raddr); break;
2178 case lir_sub: __ subss(lreg, raddr); break;
2179 case lir_mul: __ mulss(lreg, raddr); break;
2180 case lir_div: __ divss(lreg, raddr); break;
2181 default: ShouldNotReachHere();
2182 }
2183 }
2184
2185 } else if (left->is_double_xmm()) {
2186 assert(left == dest, "left and dest must be equal");
2187
2188 XMMRegister lreg = left->as_xmm_double_reg();
2189 if (right->is_double_xmm()) {
2190 XMMRegister rreg = right->as_xmm_double_reg();
2191 switch (code) {
2192 case lir_add: __ addsd(lreg, rreg); break;
2193 case lir_sub: __ subsd(lreg, rreg); break;
2194 case lir_mul: __ mulsd(lreg, rreg); break;
2195 case lir_div: __ divsd(lreg, rreg); break;
2196 default: ShouldNotReachHere();
2197 }
2198 } else {
2199 Address raddr;
2200 if (right->is_double_stack()) {
2201 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2202 } else if (right->is_constant()) {
2203 // hack for now
2204 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2205 } else {
2206 ShouldNotReachHere();
2207 }
2208 switch (code) {
2209 case lir_add: __ addsd(lreg, raddr); break;
2210 case lir_sub: __ subsd(lreg, raddr); break;
2211 case lir_mul: __ mulsd(lreg, raddr); break;
2212 case lir_div: __ divsd(lreg, raddr); break;
2213 default: ShouldNotReachHere();
2214 }
2215 }
2216
2217 #ifndef _LP64
2218 } else if (left->is_single_fpu()) {
2219 assert(dest->is_single_fpu(), "fpu stack allocation required");
2220
2221 if (right->is_single_fpu()) {
2222 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2223
2224 } else {
2225 assert(left->fpu_regnr() == 0, "left must be on TOS");
2226 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2227
2228 Address raddr;
2229 if (right->is_single_stack()) {
2230 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2231 } else if (right->is_constant()) {
2232 address const_addr = float_constant(right->as_jfloat());
2233 assert(const_addr != nullptr, "incorrect float/double constant maintenance");
2234 // hack for now
2235 raddr = __ as_Address(InternalAddress(const_addr));
2236 } else {
2237 ShouldNotReachHere();
2238 }
2239
2240 switch (code) {
2241 case lir_add: __ fadd_s(raddr); break;
2242 case lir_sub: __ fsub_s(raddr); break;
2243 case lir_mul: __ fmul_s(raddr); break;
2244 case lir_div: __ fdiv_s(raddr); break;
2245 default: ShouldNotReachHere();
2246 }
2247 }
2248
2249 } else if (left->is_double_fpu()) {
2250 assert(dest->is_double_fpu(), "fpu stack allocation required");
2251
2252 if (code == lir_mul || code == lir_div) {
2253 // Double values require special handling for strictfp mul/div on x86
2254 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1()));
2255 __ fmulp(left->fpu_regnrLo() + 1);
2256 }
2257
2258 if (right->is_double_fpu()) {
2259 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2260
2261 } else {
2262 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2263 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2264
2265 Address raddr;
2266 if (right->is_double_stack()) {
2267 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2268 } else if (right->is_constant()) {
2269 // hack for now
2270 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2271 } else {
2272 ShouldNotReachHere();
2273 }
2274
2275 switch (code) {
2276 case lir_add: __ fadd_d(raddr); break;
2277 case lir_sub: __ fsub_d(raddr); break;
2278 case lir_mul: __ fmul_d(raddr); break;
2279 case lir_div: __ fdiv_d(raddr); break;
2280 default: ShouldNotReachHere();
2281 }
2282 }
2283
2284 if (code == lir_mul || code == lir_div) {
2285 // Double values require special handling for strictfp mul/div on x86
2286 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2()));
2287 __ fmulp(dest->fpu_regnrLo() + 1);
2288 }
2289 #endif // !_LP64
2290
2291 } else if (left->is_single_stack() || left->is_address()) {
2292 assert(left == dest, "left and dest must be equal");
2293
2294 Address laddr;
2295 if (left->is_single_stack()) {
2296 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2297 } else if (left->is_address()) {
2298 laddr = as_Address(left->as_address_ptr());
2299 } else {
2300 ShouldNotReachHere();
2301 }
2302
2303 if (right->is_single_cpu()) {
2304 Register rreg = right->as_register();
2305 switch (code) {
2306 case lir_add: __ addl(laddr, rreg); break;
2307 case lir_sub: __ subl(laddr, rreg); break;
2308 default: ShouldNotReachHere();
2309 }
2310 } else if (right->is_constant()) {
2311 jint c = right->as_constant_ptr()->as_jint();
2312 switch (code) {
2313 case lir_add: {
2314 __ incrementl(laddr, c);
2315 break;
2316 }
2317 case lir_sub: {
2318 __ decrementl(laddr, c);
2319 break;
2320 }
2321 default: ShouldNotReachHere();
2322 }
2323 } else {
2324 ShouldNotReachHere();
2325 }
2326
2327 } else {
2328 ShouldNotReachHere();
2329 }
2330 }
2331
2332 #ifndef _LP64
2333 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2334 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2335 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2336 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2337
2338 bool left_is_tos = (left_index == 0);
2339 bool dest_is_tos = (dest_index == 0);
2340 int non_tos_index = (left_is_tos ? right_index : left_index);
2341
2342 switch (code) {
2343 case lir_add:
2344 if (pop_fpu_stack) __ faddp(non_tos_index);
2345 else if (dest_is_tos) __ fadd (non_tos_index);
2346 else __ fadda(non_tos_index);
2347 break;
2348
2349 case lir_sub:
2350 if (left_is_tos) {
2351 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2352 else if (dest_is_tos) __ fsub (non_tos_index);
2353 else __ fsubra(non_tos_index);
2354 } else {
2355 if (pop_fpu_stack) __ fsubp (non_tos_index);
2356 else if (dest_is_tos) __ fsubr (non_tos_index);
2357 else __ fsuba (non_tos_index);
2358 }
2359 break;
2360
2361 case lir_mul:
2362 if (pop_fpu_stack) __ fmulp(non_tos_index);
2363 else if (dest_is_tos) __ fmul (non_tos_index);
2364 else __ fmula(non_tos_index);
2365 break;
2366
2367 case lir_div:
2368 if (left_is_tos) {
2369 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2370 else if (dest_is_tos) __ fdiv (non_tos_index);
2371 else __ fdivra(non_tos_index);
2372 } else {
2373 if (pop_fpu_stack) __ fdivp (non_tos_index);
2374 else if (dest_is_tos) __ fdivr (non_tos_index);
2375 else __ fdiva (non_tos_index);
2376 }
2377 break;
2378
2379 case lir_rem:
2380 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2381 __ fremr(noreg);
2382 break;
2383
2384 default:
2385 ShouldNotReachHere();
2386 }
2387 }
2388 #endif // _LP64
2389
2390
2391 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2392 if (value->is_double_xmm()) {
2393 switch(code) {
2394 case lir_abs :
2395 {
2396 #ifdef _LP64
2397 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2398 assert(tmp->is_valid(), "need temporary");
2399 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2400 } else
2401 #endif
2402 {
2403 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2404 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2405 }
2406 assert(!tmp->is_valid(), "do not need temporary");
2407 __ andpd(dest->as_xmm_double_reg(),
2408 ExternalAddress((address)double_signmask_pool),
2409 rscratch1);
2410 }
2411 }
2412 break;
2413
2414 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2415 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2416 default : ShouldNotReachHere();
2417 }
2418
2419 #ifndef _LP64
2420 } else if (value->is_double_fpu()) {
2421 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2422 switch(code) {
2423 case lir_abs : __ fabs() ; break;
2424 case lir_sqrt : __ fsqrt(); break;
2425 default : ShouldNotReachHere();
2426 }
2427 #endif // !_LP64
2428 } else if (code == lir_f2hf) {
2429 __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg());
2430 } else if (code == lir_hf2f) {
2431 __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register());
2432 } else {
2433 Unimplemented();
2434 }
2435 }
2436
2437 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2438 // assert(left->destroys_register(), "check");
2439 if (left->is_single_cpu()) {
2440 Register reg = left->as_register();
2441 if (right->is_constant()) {
2442 int val = right->as_constant_ptr()->as_jint();
2443 switch (code) {
2444 case lir_logic_and: __ andl (reg, val); break;
2445 case lir_logic_or: __ orl (reg, val); break;
2446 case lir_logic_xor: __ xorl (reg, val); break;
2447 default: ShouldNotReachHere();
2448 }
2449 } else if (right->is_stack()) {
2450 // added support for stack operands
2451 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2452 switch (code) {
2453 case lir_logic_and: __ andl (reg, raddr); break;
2454 case lir_logic_or: __ orl (reg, raddr); break;
2455 case lir_logic_xor: __ xorl (reg, raddr); break;
2456 default: ShouldNotReachHere();
2457 }
2458 } else {
2459 Register rright = right->as_register();
2460 switch (code) {
2461 case lir_logic_and: __ andptr (reg, rright); break;
2462 case lir_logic_or : __ orptr (reg, rright); break;
2463 case lir_logic_xor: __ xorptr (reg, rright); break;
2464 default: ShouldNotReachHere();
2465 }
2466 }
2467 move_regs(reg, dst->as_register());
2468 } else {
2469 Register l_lo = left->as_register_lo();
2470 Register l_hi = left->as_register_hi();
2471 if (right->is_constant()) {
2472 #ifdef _LP64
2473 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2474 switch (code) {
2475 case lir_logic_and:
2476 __ andq(l_lo, rscratch1);
2477 break;
2478 case lir_logic_or:
2479 __ orq(l_lo, rscratch1);
2480 break;
2481 case lir_logic_xor:
2482 __ xorq(l_lo, rscratch1);
2483 break;
2484 default: ShouldNotReachHere();
2485 }
2486 #else
2487 int r_lo = right->as_constant_ptr()->as_jint_lo();
2488 int r_hi = right->as_constant_ptr()->as_jint_hi();
2489 switch (code) {
2490 case lir_logic_and:
2491 __ andl(l_lo, r_lo);
2492 __ andl(l_hi, r_hi);
2493 break;
2494 case lir_logic_or:
2495 __ orl(l_lo, r_lo);
2496 __ orl(l_hi, r_hi);
2497 break;
2498 case lir_logic_xor:
2499 __ xorl(l_lo, r_lo);
2500 __ xorl(l_hi, r_hi);
2501 break;
2502 default: ShouldNotReachHere();
2503 }
2504 #endif // _LP64
2505 } else {
2506 #ifdef _LP64
2507 Register r_lo;
2508 if (is_reference_type(right->type())) {
2509 r_lo = right->as_register();
2510 } else {
2511 r_lo = right->as_register_lo();
2512 }
2513 #else
2514 Register r_lo = right->as_register_lo();
2515 Register r_hi = right->as_register_hi();
2516 assert(l_lo != r_hi, "overwriting registers");
2517 #endif
2518 switch (code) {
2519 case lir_logic_and:
2520 __ andptr(l_lo, r_lo);
2521 NOT_LP64(__ andptr(l_hi, r_hi);)
2522 break;
2523 case lir_logic_or:
2524 __ orptr(l_lo, r_lo);
2525 NOT_LP64(__ orptr(l_hi, r_hi);)
2526 break;
2527 case lir_logic_xor:
2528 __ xorptr(l_lo, r_lo);
2529 NOT_LP64(__ xorptr(l_hi, r_hi);)
2530 break;
2531 default: ShouldNotReachHere();
2532 }
2533 }
2534
2535 Register dst_lo = dst->as_register_lo();
2536 Register dst_hi = dst->as_register_hi();
2537
2538 #ifdef _LP64
2539 move_regs(l_lo, dst_lo);
2540 #else
2541 if (dst_lo == l_hi) {
2542 assert(dst_hi != l_lo, "overwriting registers");
2543 move_regs(l_hi, dst_hi);
2544 move_regs(l_lo, dst_lo);
2545 } else {
2546 assert(dst_lo != l_hi, "overwriting registers");
2547 move_regs(l_lo, dst_lo);
2548 move_regs(l_hi, dst_hi);
2549 }
2550 #endif // _LP64
2551 }
2552 }
2553
2554
2555 // we assume that rax, and rdx can be overwritten
2556 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2557
2558 assert(left->is_single_cpu(), "left must be register");
2559 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2560 assert(result->is_single_cpu(), "result must be register");
2561
2562 // assert(left->destroys_register(), "check");
2563 // assert(right->destroys_register(), "check");
2564
2565 Register lreg = left->as_register();
2566 Register dreg = result->as_register();
2567
2568 if (right->is_constant()) {
2569 jint divisor = right->as_constant_ptr()->as_jint();
2570 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2571 if (code == lir_idiv) {
2572 assert(lreg == rax, "must be rax,");
2573 assert(temp->as_register() == rdx, "tmp register must be rdx");
2574 __ cdql(); // sign extend into rdx:rax
2575 if (divisor == 2) {
2576 __ subl(lreg, rdx);
2577 } else {
2578 __ andl(rdx, divisor - 1);
2579 __ addl(lreg, rdx);
2580 }
2581 __ sarl(lreg, log2i_exact(divisor));
2582 move_regs(lreg, dreg);
2583 } else if (code == lir_irem) {
2584 Label done;
2585 __ mov(dreg, lreg);
2586 __ andl(dreg, 0x80000000 | (divisor - 1));
2587 __ jcc(Assembler::positive, done);
2588 __ decrement(dreg);
2589 __ orl(dreg, ~(divisor - 1));
2590 __ increment(dreg);
2591 __ bind(done);
2592 } else {
2593 ShouldNotReachHere();
2594 }
2595 } else {
2596 Register rreg = right->as_register();
2597 assert(lreg == rax, "left register must be rax,");
2598 assert(rreg != rdx, "right register must not be rdx");
2599 assert(temp->as_register() == rdx, "tmp register must be rdx");
2600
2601 move_regs(lreg, rax);
2602
2603 int idivl_offset = __ corrected_idivl(rreg);
2604 if (ImplicitDiv0Checks) {
2605 add_debug_info_for_div0(idivl_offset, info);
2606 }
2607 if (code == lir_irem) {
2608 move_regs(rdx, dreg); // result is in rdx
2609 } else {
2610 move_regs(rax, dreg);
2611 }
2612 }
2613 }
2614
2615
2616 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2617 if (opr1->is_single_cpu()) {
2618 Register reg1 = opr1->as_register();
2619 if (opr2->is_single_cpu()) {
2620 // cpu register - cpu register
2621 if (is_reference_type(opr1->type())) {
2622 __ cmpoop(reg1, opr2->as_register());
2623 } else {
2624 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2625 __ cmpl(reg1, opr2->as_register());
2626 }
2627 } else if (opr2->is_stack()) {
2628 // cpu register - stack
2629 if (is_reference_type(opr1->type())) {
2630 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2631 } else {
2632 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2633 }
2634 } else if (opr2->is_constant()) {
2635 // cpu register - constant
2636 LIR_Const* c = opr2->as_constant_ptr();
2637 if (c->type() == T_INT) {
2638 jint i = c->as_jint();
2639 if (i == 0) {
2640 __ testl(reg1, reg1);
2641 } else {
2642 __ cmpl(reg1, i);
2643 }
2644 } else if (c->type() == T_METADATA) {
2645 // All we need for now is a comparison with null for equality.
2646 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2647 Metadata* m = c->as_metadata();
2648 if (m == nullptr) {
2649 __ testptr(reg1, reg1);
2650 } else {
2651 ShouldNotReachHere();
2652 }
2653 } else if (is_reference_type(c->type())) {
2654 // In 64bit oops are single register
2655 jobject o = c->as_jobject();
2656 if (o == nullptr) {
2657 __ testptr(reg1, reg1);
2658 } else {
2659 __ cmpoop(reg1, o, rscratch1);
2660 }
2661 } else {
2662 fatal("unexpected type: %s", basictype_to_str(c->type()));
2663 }
2664 // cpu register - address
2665 } else if (opr2->is_address()) {
2666 if (op->info() != nullptr) {
2667 add_debug_info_for_null_check_here(op->info());
2668 }
2669 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2670 } else {
2671 ShouldNotReachHere();
2672 }
2673
2674 } else if(opr1->is_double_cpu()) {
2675 Register xlo = opr1->as_register_lo();
2676 Register xhi = opr1->as_register_hi();
2677 if (opr2->is_double_cpu()) {
2678 #ifdef _LP64
2679 __ cmpptr(xlo, opr2->as_register_lo());
2680 #else
2681 // cpu register - cpu register
2682 Register ylo = opr2->as_register_lo();
2683 Register yhi = opr2->as_register_hi();
2684 __ subl(xlo, ylo);
2685 __ sbbl(xhi, yhi);
2686 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2687 __ orl(xhi, xlo);
2688 }
2689 #endif // _LP64
2690 } else if (opr2->is_constant()) {
2691 // cpu register - constant 0
2692 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2693 #ifdef _LP64
2694 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2695 #else
2696 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2697 __ orl(xhi, xlo);
2698 #endif // _LP64
2699 } else {
2700 ShouldNotReachHere();
2701 }
2702
2703 } else if (opr1->is_single_xmm()) {
2704 XMMRegister reg1 = opr1->as_xmm_float_reg();
2705 if (opr2->is_single_xmm()) {
2706 // xmm register - xmm register
2707 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2708 } else if (opr2->is_stack()) {
2709 // xmm register - stack
2710 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2711 } else if (opr2->is_constant()) {
2712 // xmm register - constant
2713 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2714 } else if (opr2->is_address()) {
2715 // xmm register - address
2716 if (op->info() != nullptr) {
2717 add_debug_info_for_null_check_here(op->info());
2718 }
2719 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2720 } else {
2721 ShouldNotReachHere();
2722 }
2723
2724 } else if (opr1->is_double_xmm()) {
2725 XMMRegister reg1 = opr1->as_xmm_double_reg();
2726 if (opr2->is_double_xmm()) {
2727 // xmm register - xmm register
2728 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2729 } else if (opr2->is_stack()) {
2730 // xmm register - stack
2731 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2732 } else if (opr2->is_constant()) {
2733 // xmm register - constant
2734 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2735 } else if (opr2->is_address()) {
2736 // xmm register - address
2737 if (op->info() != nullptr) {
2738 add_debug_info_for_null_check_here(op->info());
2739 }
2740 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2741 } else {
2742 ShouldNotReachHere();
2743 }
2744
2745 #ifndef _LP64
2746 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2747 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2748 assert(opr2->is_fpu_register(), "both must be registers");
2749 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2750 #endif // LP64
2751
2752 } else if (opr1->is_address() && opr2->is_constant()) {
2753 LIR_Const* c = opr2->as_constant_ptr();
2754 #ifdef _LP64
2755 if (is_reference_type(c->type())) {
2756 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2757 __ movoop(rscratch1, c->as_jobject());
2758 }
2759 #endif // LP64
2760 if (op->info() != nullptr) {
2761 add_debug_info_for_null_check_here(op->info());
2762 }
2763 // special case: address - constant
2764 LIR_Address* addr = opr1->as_address_ptr();
2765 if (c->type() == T_INT) {
2766 __ cmpl(as_Address(addr), c->as_jint());
2767 } else if (is_reference_type(c->type())) {
2768 #ifdef _LP64
2769 // %%% Make this explode if addr isn't reachable until we figure out a
2770 // better strategy by giving noreg as the temp for as_Address
2771 __ cmpoop(rscratch1, as_Address(addr, noreg));
2772 #else
2773 __ cmpoop(as_Address(addr), c->as_jobject());
2774 #endif // _LP64
2775 } else {
2776 ShouldNotReachHere();
2777 }
2778
2779 } else {
2780 ShouldNotReachHere();
2781 }
2782 }
2783
2784 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2785 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2786 if (left->is_single_xmm()) {
2787 assert(right->is_single_xmm(), "must match");
2788 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2789 } else if (left->is_double_xmm()) {
2790 assert(right->is_double_xmm(), "must match");
2791 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2792
2793 } else {
2794 #ifdef _LP64
2795 ShouldNotReachHere();
2796 #else
2797 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2798 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2799
2800 assert(left->fpu() == 0, "left must be on TOS");
2801 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2802 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2803 #endif // LP64
2804 }
2805 } else {
2806 assert(code == lir_cmp_l2i, "check");
2807 #ifdef _LP64
2808 Label done;
2809 Register dest = dst->as_register();
2810 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2811 __ movl(dest, -1);
2812 __ jccb(Assembler::less, done);
2813 __ setb(Assembler::notZero, dest);
2814 __ movzbl(dest, dest);
2815 __ bind(done);
2816 #else
2817 __ lcmp2int(left->as_register_hi(),
2818 left->as_register_lo(),
2819 right->as_register_hi(),
2820 right->as_register_lo());
2821 move_regs(left->as_register_hi(), dst->as_register());
2822 #endif // _LP64
2823 }
2824 }
2825
2826
2827 void LIR_Assembler::align_call(LIR_Code code) {
2828 // make sure that the displacement word of the call ends up word aligned
2829 int offset = __ offset();
2830 switch (code) {
2831 case lir_static_call:
2832 case lir_optvirtual_call:
2833 case lir_dynamic_call:
2834 offset += NativeCall::displacement_offset;
2835 break;
2836 case lir_icvirtual_call:
2837 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size_rex;
2838 break;
2839 default: ShouldNotReachHere();
2840 }
2841 __ align(BytesPerWord, offset);
2842 }
2843
2844
2845 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2846 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2847 "must be aligned");
2848 __ call(AddressLiteral(op->addr(), rtype));
2849 add_call_info(code_offset(), op->info());
2850 __ post_call_nop();
2851 }
2852
2853
2854 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2855 __ ic_call(op->addr());
2856 add_call_info(code_offset(), op->info());
2857 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2858 "must be aligned");
2859 __ post_call_nop();
2860 }
2861
2862
2863 void LIR_Assembler::emit_static_call_stub() {
2864 address call_pc = __ pc();
2865 address stub = __ start_a_stub(call_stub_size());
2866 if (stub == nullptr) {
2867 bailout("static call stub overflow");
2868 return;
2869 }
2870
2871 int start = __ offset();
2872
2873 // make sure that the displacement word of the call ends up word aligned
2874 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size_rex + NativeCall::displacement_offset);
2875 __ relocate(static_stub_Relocation::spec(call_pc));
2876 __ mov_metadata(rbx, (Metadata*)nullptr);
2877 // must be set to -1 at code generation time
2878 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2879 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2880 __ jump(RuntimeAddress(__ pc()));
2881
2882 assert(__ offset() - start <= call_stub_size(), "stub too big");
2883 __ end_a_stub();
2884 }
2885
2886
2887 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2888 assert(exceptionOop->as_register() == rax, "must match");
2889 assert(exceptionPC->as_register() == rdx, "must match");
2890
2891 // exception object is not added to oop map by LinearScan
2892 // (LinearScan assumes that no oops are in fixed registers)
2893 info->add_register_oop(exceptionOop);
2894 C1StubId unwind_id;
2895
2896 // get current pc information
2897 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2898 int pc_for_athrow_offset = __ offset();
2899 InternalAddress pc_for_athrow(__ pc());
2900 __ lea(exceptionPC->as_register(), pc_for_athrow);
2901 add_call_info(pc_for_athrow_offset, info); // for exception handler
2902
2903 __ verify_not_null_oop(rax);
2904 // search an exception handler (rax: exception oop, rdx: throwing pc)
2905 if (compilation()->has_fpu_code()) {
2906 unwind_id = C1StubId::handle_exception_id;
2907 } else {
2908 unwind_id = C1StubId::handle_exception_nofpu_id;
2909 }
2910 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2911
2912 // enough room for two byte trap
2913 __ nop();
2914 }
2915
2916
2917 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2918 assert(exceptionOop->as_register() == rax, "must match");
2919
2920 __ jmp(_unwind_handler_entry);
2921 }
2922
2923
2924 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2925
2926 // optimized version for linear scan:
2927 // * count must be already in ECX (guaranteed by LinearScan)
2928 // * left and dest must be equal
2929 // * tmp must be unused
2930 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2931 assert(left == dest, "left and dest must be equal");
2932 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2933
2934 if (left->is_single_cpu()) {
2935 Register value = left->as_register();
2936 assert(value != SHIFT_count, "left cannot be ECX");
2937
2938 switch (code) {
2939 case lir_shl: __ shll(value); break;
2940 case lir_shr: __ sarl(value); break;
2941 case lir_ushr: __ shrl(value); break;
2942 default: ShouldNotReachHere();
2943 }
2944 } else if (left->is_double_cpu()) {
2945 Register lo = left->as_register_lo();
2946 Register hi = left->as_register_hi();
2947 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2948 #ifdef _LP64
2949 switch (code) {
2950 case lir_shl: __ shlptr(lo); break;
2951 case lir_shr: __ sarptr(lo); break;
2952 case lir_ushr: __ shrptr(lo); break;
2953 default: ShouldNotReachHere();
2954 }
2955 #else
2956
2957 switch (code) {
2958 case lir_shl: __ lshl(hi, lo); break;
2959 case lir_shr: __ lshr(hi, lo, true); break;
2960 case lir_ushr: __ lshr(hi, lo, false); break;
2961 default: ShouldNotReachHere();
2962 }
2963 #endif // LP64
2964 } else {
2965 ShouldNotReachHere();
2966 }
2967 }
2968
2969
2970 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2971 if (dest->is_single_cpu()) {
2972 // first move left into dest so that left is not destroyed by the shift
2973 Register value = dest->as_register();
2974 count = count & 0x1F; // Java spec
2975
2976 move_regs(left->as_register(), value);
2977 switch (code) {
2978 case lir_shl: __ shll(value, count); break;
2979 case lir_shr: __ sarl(value, count); break;
2980 case lir_ushr: __ shrl(value, count); break;
2981 default: ShouldNotReachHere();
2982 }
2983 } else if (dest->is_double_cpu()) {
2984 #ifndef _LP64
2985 Unimplemented();
2986 #else
2987 // first move left into dest so that left is not destroyed by the shift
2988 Register value = dest->as_register_lo();
2989 count = count & 0x1F; // Java spec
2990
2991 move_regs(left->as_register_lo(), value);
2992 switch (code) {
2993 case lir_shl: __ shlptr(value, count); break;
2994 case lir_shr: __ sarptr(value, count); break;
2995 case lir_ushr: __ shrptr(value, count); break;
2996 default: ShouldNotReachHere();
2997 }
2998 #endif // _LP64
2999 } else {
3000 ShouldNotReachHere();
3001 }
3002 }
3003
3004
3005 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3006 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3007 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3008 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3009 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3010 }
3011
3012
3013 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3014 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3015 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3016 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3017 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3018 }
3019
3020
3021 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3022 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3023 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3024 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3025 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1);
3026 }
3027
3028
3029 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3030 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3031 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3032 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3033 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1);
3034 }
3035
3036
3037 // This code replaces a call to arraycopy; no exception may
3038 // be thrown in this code, they must be thrown in the System.arraycopy
3039 // activation frame; we could save some checks if this would not be the case
3040 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3041 ciArrayKlass* default_type = op->expected_type();
3042 Register src = op->src()->as_register();
3043 Register dst = op->dst()->as_register();
3044 Register src_pos = op->src_pos()->as_register();
3045 Register dst_pos = op->dst_pos()->as_register();
3046 Register length = op->length()->as_register();
3047 Register tmp = op->tmp()->as_register();
3048 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3049 Register tmp2 = UseCompactObjectHeaders ? rscratch2 : noreg;
3050
3051 CodeStub* stub = op->stub();
3052 int flags = op->flags();
3053 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
3054 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3055
3056 // if we don't know anything, just go through the generic arraycopy
3057 if (default_type == nullptr) {
3058 // save outgoing arguments on stack in case call to System.arraycopy is needed
3059 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3060 // for interpreter calling conventions. Now we have to do it in new style conventions.
3061 // For the moment until C1 gets the new register allocator I just force all the
3062 // args to the right place (except the register args) and then on the back side
3063 // reload the register args properly if we go slow path. Yuck
3064
3065 // These are proper for the calling convention
3066 store_parameter(length, 2);
3067 store_parameter(dst_pos, 1);
3068 store_parameter(dst, 0);
3069
3070 // these are just temporary placements until we need to reload
3071 store_parameter(src_pos, 3);
3072 store_parameter(src, 4);
3073 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3074
3075 address copyfunc_addr = StubRoutines::generic_arraycopy();
3076 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
3077
3078 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3079 #ifdef _LP64
3080 // The arguments are in java calling convention so we can trivially shift them to C
3081 // convention
3082 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3083 __ mov(c_rarg0, j_rarg0);
3084 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3085 __ mov(c_rarg1, j_rarg1);
3086 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3087 __ mov(c_rarg2, j_rarg2);
3088 assert_different_registers(c_rarg3, j_rarg4);
3089 __ mov(c_rarg3, j_rarg3);
3090 #ifdef _WIN64
3091 // Allocate abi space for args but be sure to keep stack aligned
3092 __ subptr(rsp, 6*wordSize);
3093 store_parameter(j_rarg4, 4);
3094 #ifndef PRODUCT
3095 if (PrintC1Statistics) {
3096 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3097 }
3098 #endif
3099 __ call(RuntimeAddress(copyfunc_addr));
3100 __ addptr(rsp, 6*wordSize);
3101 #else
3102 __ mov(c_rarg4, j_rarg4);
3103 #ifndef PRODUCT
3104 if (PrintC1Statistics) {
3105 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3106 }
3107 #endif
3108 __ call(RuntimeAddress(copyfunc_addr));
3109 #endif // _WIN64
3110 #else
3111 __ push(length);
3112 __ push(dst_pos);
3113 __ push(dst);
3114 __ push(src_pos);
3115 __ push(src);
3116
3117 #ifndef PRODUCT
3118 if (PrintC1Statistics) {
3119 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3120 }
3121 #endif
3122 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3123
3124 #endif // _LP64
3125
3126 __ testl(rax, rax);
3127 __ jcc(Assembler::equal, *stub->continuation());
3128
3129 __ mov(tmp, rax);
3130 __ xorl(tmp, -1);
3131
3132 // Reload values from the stack so they are where the stub
3133 // expects them.
3134 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3135 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3136 __ movptr (length, Address(rsp, 2*BytesPerWord));
3137 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3138 __ movptr (src, Address(rsp, 4*BytesPerWord));
3139
3140 __ subl(length, tmp);
3141 __ addl(src_pos, tmp);
3142 __ addl(dst_pos, tmp);
3143 __ jmp(*stub->entry());
3144
3145 __ bind(*stub->continuation());
3146 return;
3147 }
3148
3149 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3150
3151 int elem_size = type2aelembytes(basic_type);
3152 Address::ScaleFactor scale;
3153
3154 switch (elem_size) {
3155 case 1 :
3156 scale = Address::times_1;
3157 break;
3158 case 2 :
3159 scale = Address::times_2;
3160 break;
3161 case 4 :
3162 scale = Address::times_4;
3163 break;
3164 case 8 :
3165 scale = Address::times_8;
3166 break;
3167 default:
3168 scale = Address::no_scale;
3169 ShouldNotReachHere();
3170 }
3171
3172 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3173 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3174
3175 // length and pos's are all sign extended at this point on 64bit
3176
3177 // test for null
3178 if (flags & LIR_OpArrayCopy::src_null_check) {
3179 __ testptr(src, src);
3180 __ jcc(Assembler::zero, *stub->entry());
3181 }
3182 if (flags & LIR_OpArrayCopy::dst_null_check) {
3183 __ testptr(dst, dst);
3184 __ jcc(Assembler::zero, *stub->entry());
3185 }
3186
3187 // If the compiler was not able to prove that exact type of the source or the destination
3188 // of the arraycopy is an array type, check at runtime if the source or the destination is
3189 // an instance type.
3190 if (flags & LIR_OpArrayCopy::type_check) {
3191 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3192 __ load_klass(tmp, dst, tmp_load_klass);
3193 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3194 __ jcc(Assembler::greaterEqual, *stub->entry());
3195 }
3196
3197 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3198 __ load_klass(tmp, src, tmp_load_klass);
3199 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3200 __ jcc(Assembler::greaterEqual, *stub->entry());
3201 }
3202 }
3203
3204 // check if negative
3205 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3206 __ testl(src_pos, src_pos);
3207 __ jcc(Assembler::less, *stub->entry());
3208 }
3209 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3210 __ testl(dst_pos, dst_pos);
3211 __ jcc(Assembler::less, *stub->entry());
3212 }
3213
3214 if (flags & LIR_OpArrayCopy::src_range_check) {
3215 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3216 __ cmpl(tmp, src_length_addr);
3217 __ jcc(Assembler::above, *stub->entry());
3218 }
3219 if (flags & LIR_OpArrayCopy::dst_range_check) {
3220 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3221 __ cmpl(tmp, dst_length_addr);
3222 __ jcc(Assembler::above, *stub->entry());
3223 }
3224
3225 if (flags & LIR_OpArrayCopy::length_positive_check) {
3226 __ testl(length, length);
3227 __ jcc(Assembler::less, *stub->entry());
3228 }
3229
3230 #ifdef _LP64
3231 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3232 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3233 #endif
3234
3235 if (flags & LIR_OpArrayCopy::type_check) {
3236 // We don't know the array types are compatible
3237 if (basic_type != T_OBJECT) {
3238 // Simple test for basic type arrays
3239 __ cmp_klasses_from_objects(src, dst, tmp, tmp2);
3240 __ jcc(Assembler::notEqual, *stub->entry());
3241 } else {
3242 // For object arrays, if src is a sub class of dst then we can
3243 // safely do the copy.
3244 Label cont, slow;
3245
3246 __ push(src);
3247 __ push(dst);
3248
3249 __ load_klass(src, src, tmp_load_klass);
3250 __ load_klass(dst, dst, tmp_load_klass);
3251
3252 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
3253
3254 __ push(src);
3255 __ push(dst);
3256 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
3257 __ pop(dst);
3258 __ pop(src);
3259
3260 __ testl(src, src);
3261 __ jcc(Assembler::notEqual, cont);
3262
3263 __ bind(slow);
3264 __ pop(dst);
3265 __ pop(src);
3266
3267 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3268 if (copyfunc_addr != nullptr) { // use stub if available
3269 // src is not a sub class of dst so we have to do a
3270 // per-element check.
3271
3272 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3273 if ((flags & mask) != mask) {
3274 // Check that at least both of them object arrays.
3275 assert(flags & mask, "one of the two should be known to be an object array");
3276
3277 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3278 __ load_klass(tmp, src, tmp_load_klass);
3279 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3280 __ load_klass(tmp, dst, tmp_load_klass);
3281 }
3282 int lh_offset = in_bytes(Klass::layout_helper_offset());
3283 Address klass_lh_addr(tmp, lh_offset);
3284 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3285 __ cmpl(klass_lh_addr, objArray_lh);
3286 __ jcc(Assembler::notEqual, *stub->entry());
3287 }
3288
3289 // Spill because stubs can use any register they like and it's
3290 // easier to restore just those that we care about.
3291 store_parameter(dst, 0);
3292 store_parameter(dst_pos, 1);
3293 store_parameter(length, 2);
3294 store_parameter(src_pos, 3);
3295 store_parameter(src, 4);
3296
3297 #ifndef _LP64
3298 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3299 __ movptr(tmp, dst_klass_addr);
3300 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3301 __ push(tmp);
3302 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3303 __ push(tmp);
3304 __ push(length);
3305 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3306 __ push(tmp);
3307 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3308 __ push(tmp);
3309
3310 __ call_VM_leaf(copyfunc_addr, 5);
3311 #else
3312 __ movl2ptr(length, length); //higher 32bits must be null
3313
3314 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3315 assert_different_registers(c_rarg0, dst, dst_pos, length);
3316 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3317 assert_different_registers(c_rarg1, dst, length);
3318
3319 __ mov(c_rarg2, length);
3320 assert_different_registers(c_rarg2, dst);
3321
3322 #ifdef _WIN64
3323 // Allocate abi space for args but be sure to keep stack aligned
3324 __ subptr(rsp, 6*wordSize);
3325 __ load_klass(c_rarg3, dst, tmp_load_klass);
3326 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3327 store_parameter(c_rarg3, 4);
3328 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3329 __ call(RuntimeAddress(copyfunc_addr));
3330 __ addptr(rsp, 6*wordSize);
3331 #else
3332 __ load_klass(c_rarg4, dst, tmp_load_klass);
3333 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3334 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3335 __ call(RuntimeAddress(copyfunc_addr));
3336 #endif
3337
3338 #endif
3339
3340 #ifndef PRODUCT
3341 if (PrintC1Statistics) {
3342 Label failed;
3343 __ testl(rax, rax);
3344 __ jcc(Assembler::notZero, failed);
3345 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1);
3346 __ bind(failed);
3347 }
3348 #endif
3349
3350 __ testl(rax, rax);
3351 __ jcc(Assembler::zero, *stub->continuation());
3352
3353 #ifndef PRODUCT
3354 if (PrintC1Statistics) {
3355 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1);
3356 }
3357 #endif
3358
3359 __ mov(tmp, rax);
3360
3361 __ xorl(tmp, -1);
3362
3363 // Restore previously spilled arguments
3364 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3365 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3366 __ movptr (length, Address(rsp, 2*BytesPerWord));
3367 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3368 __ movptr (src, Address(rsp, 4*BytesPerWord));
3369
3370
3371 __ subl(length, tmp);
3372 __ addl(src_pos, tmp);
3373 __ addl(dst_pos, tmp);
3374 }
3375
3376 __ jmp(*stub->entry());
3377
3378 __ bind(cont);
3379 __ pop(dst);
3380 __ pop(src);
3381 }
3382 }
3383
3384 #ifdef ASSERT
3385 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3386 // Sanity check the known type with the incoming class. For the
3387 // primitive case the types must match exactly with src.klass and
3388 // dst.klass each exactly matching the default type. For the
3389 // object array case, if no type check is needed then either the
3390 // dst type is exactly the expected type and the src type is a
3391 // subtype which we can't check or src is the same array as dst
3392 // but not necessarily exactly of type default_type.
3393 Label known_ok, halt;
3394 __ mov_metadata(tmp, default_type->constant_encoding());
3395 #ifdef _LP64
3396 if (UseCompressedClassPointers) {
3397 __ encode_klass_not_null(tmp, rscratch1);
3398 }
3399 #endif
3400
3401 if (basic_type != T_OBJECT) {
3402 __ cmp_klass(tmp, dst, tmp2);
3403 __ jcc(Assembler::notEqual, halt);
3404 __ cmp_klass(tmp, src, tmp2);
3405 __ jcc(Assembler::equal, known_ok);
3406 } else {
3407 __ cmp_klass(tmp, dst, tmp2);
3408 __ jcc(Assembler::equal, known_ok);
3409 __ cmpptr(src, dst);
3410 __ jcc(Assembler::equal, known_ok);
3411 }
3412 __ bind(halt);
3413 __ stop("incorrect type information in arraycopy");
3414 __ bind(known_ok);
3415 }
3416 #endif
3417
3418 #ifndef PRODUCT
3419 if (PrintC1Statistics) {
3420 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1);
3421 }
3422 #endif
3423
3424 #ifdef _LP64
3425 assert_different_registers(c_rarg0, dst, dst_pos, length);
3426 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3427 assert_different_registers(c_rarg1, length);
3428 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3429 __ mov(c_rarg2, length);
3430
3431 #else
3432 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3433 store_parameter(tmp, 0);
3434 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3435 store_parameter(tmp, 1);
3436 store_parameter(length, 2);
3437 #endif // _LP64
3438
3439 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3440 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3441 const char *name;
3442 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3443 __ call_VM_leaf(entry, 0);
3444
3445 if (stub != nullptr) {
3446 __ bind(*stub->continuation());
3447 }
3448 }
3449
3450 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3451 assert(op->crc()->is_single_cpu(), "crc must be register");
3452 assert(op->val()->is_single_cpu(), "byte value must be register");
3453 assert(op->result_opr()->is_single_cpu(), "result must be register");
3454 Register crc = op->crc()->as_register();
3455 Register val = op->val()->as_register();
3456 Register res = op->result_opr()->as_register();
3457
3458 assert_different_registers(val, crc, res);
3459
3460 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3461 __ notl(crc); // ~crc
3462 __ update_byte_crc32(crc, val, res);
3463 __ notl(crc); // ~crc
3464 __ mov(res, crc);
3465 }
3466
3467 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3468 Register obj = op->obj_opr()->as_register(); // may not be an oop
3469 Register hdr = op->hdr_opr()->as_register();
3470 Register lock = op->lock_opr()->as_register();
3471 if (LockingMode == LM_MONITOR) {
3472 if (op->info() != nullptr) {
3473 add_debug_info_for_null_check_here(op->info());
3474 __ null_check(obj);
3475 }
3476 __ jmp(*op->stub()->entry());
3477 } else if (op->code() == lir_lock) {
3478 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3479 Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg;
3480 // add debug info for NullPointerException only if one is possible
3481 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
3482 if (op->info() != nullptr) {
3483 add_debug_info_for_null_check(null_check_offset, op->info());
3484 }
3485 // done
3486 } else if (op->code() == lir_unlock) {
3487 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3488 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3489 } else {
3490 Unimplemented();
3491 }
3492 __ bind(*op->stub()->continuation());
3493 }
3494
3495 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
3496 Register obj = op->obj()->as_pointer_register();
3497 Register result = op->result_opr()->as_pointer_register();
3498
3499 CodeEmitInfo* info = op->info();
3500 if (info != nullptr) {
3501 add_debug_info_for_null_check_here(info);
3502 }
3503
3504 __ load_klass(result, obj, rscratch1);
3505 }
3506
3507 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3508 ciMethod* method = op->profiled_method();
3509 int bci = op->profiled_bci();
3510 ciMethod* callee = op->profiled_callee();
3511 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3512
3513 // Update counter for all call types
3514 ciMethodData* md = method->method_data_or_null();
3515 assert(md != nullptr, "Sanity");
3516 ciProfileData* data = md->bci_to_data(bci);
3517 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
3518 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3519 Register mdo = op->mdo()->as_register();
3520 __ mov_metadata(mdo, md->constant_encoding());
3521 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3522 // Perform additional virtual call profiling for invokevirtual and
3523 // invokeinterface bytecodes
3524 if (op->should_profile_receiver_type()) {
3525 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3526 Register recv = op->recv()->as_register();
3527 assert_different_registers(mdo, recv);
3528 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3529 ciKlass* known_klass = op->known_holder();
3530 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
3531 // We know the type that will be seen at this call site; we can
3532 // statically update the MethodData* rather than needing to do
3533 // dynamic tests on the receiver type
3534
3535 // NOTE: we should probably put a lock around this search to
3536 // avoid collisions by concurrent compilations
3537 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3538 uint i;
3539 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3540 ciKlass* receiver = vc_data->receiver(i);
3541 if (known_klass->equals(receiver)) {
3542 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3543 __ addptr(data_addr, DataLayout::counter_increment);
3544 return;
3545 }
3546 }
3547
3548 // Receiver type not found in profile data; select an empty slot
3549
3550 // Note that this is less efficient than it should be because it
3551 // always does a write to the receiver part of the
3552 // VirtualCallData rather than just the first time
3553 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3554 ciKlass* receiver = vc_data->receiver(i);
3555 if (receiver == nullptr) {
3556 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3557 __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1);
3558 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3559 __ addptr(data_addr, DataLayout::counter_increment);
3560 return;
3561 }
3562 }
3563 } else {
3564 __ load_klass(recv, recv, tmp_load_klass);
3565 Label update_done;
3566 type_profile_helper(mdo, md, data, recv, &update_done);
3567 // Receiver did not match any saved receiver and there is no empty row for it.
3568 // Increment total counter to indicate polymorphic case.
3569 __ addptr(counter_addr, DataLayout::counter_increment);
3570
3571 __ bind(update_done);
3572 }
3573 } else {
3574 // Static call
3575 __ addptr(counter_addr, DataLayout::counter_increment);
3576 }
3577 }
3578
3579 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3580 Register obj = op->obj()->as_register();
3581 Register tmp = op->tmp()->as_pointer_register();
3582 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3583 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3584 ciKlass* exact_klass = op->exact_klass();
3585 intptr_t current_klass = op->current_klass();
3586 bool not_null = op->not_null();
3587 bool no_conflict = op->no_conflict();
3588
3589 Label update, next, none;
3590
3591 bool do_null = !not_null;
3592 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3593 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3594
3595 assert(do_null || do_update, "why are we here?");
3596 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3597
3598 __ verify_oop(obj);
3599
3600 #ifdef ASSERT
3601 if (obj == tmp) {
3602 #ifdef _LP64
3603 assert_different_registers(obj, rscratch1, mdo_addr.base(), mdo_addr.index());
3604 #else
3605 assert_different_registers(obj, mdo_addr.base(), mdo_addr.index());
3606 #endif
3607 } else {
3608 #ifdef _LP64
3609 assert_different_registers(obj, tmp, rscratch1, mdo_addr.base(), mdo_addr.index());
3610 #else
3611 assert_different_registers(obj, tmp, mdo_addr.base(), mdo_addr.index());
3612 #endif
3613 }
3614 #endif
3615 if (do_null) {
3616 __ testptr(obj, obj);
3617 __ jccb(Assembler::notZero, update);
3618 if (!TypeEntries::was_null_seen(current_klass)) {
3619 __ testptr(mdo_addr, TypeEntries::null_seen);
3620 #ifndef ASSERT
3621 __ jccb(Assembler::notZero, next); // already set
3622 #else
3623 __ jcc(Assembler::notZero, next); // already set
3624 #endif
3625 // atomic update to prevent overwriting Klass* with 0
3626 __ lock();
3627 __ orptr(mdo_addr, TypeEntries::null_seen);
3628 }
3629 if (do_update) {
3630 #ifndef ASSERT
3631 __ jmpb(next);
3632 }
3633 #else
3634 __ jmp(next);
3635 }
3636 } else {
3637 __ testptr(obj, obj);
3638 __ jcc(Assembler::notZero, update);
3639 __ stop("unexpected null obj");
3640 #endif
3641 }
3642
3643 __ bind(update);
3644
3645 if (do_update) {
3646 #ifdef ASSERT
3647 if (exact_klass != nullptr) {
3648 Label ok;
3649 __ load_klass(tmp, obj, tmp_load_klass);
3650 __ push(tmp);
3651 __ mov_metadata(tmp, exact_klass->constant_encoding());
3652 __ cmpptr(tmp, Address(rsp, 0));
3653 __ jcc(Assembler::equal, ok);
3654 __ stop("exact klass and actual klass differ");
3655 __ bind(ok);
3656 __ pop(tmp);
3657 }
3658 #endif
3659 if (!no_conflict) {
3660 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3661 if (exact_klass != nullptr) {
3662 __ mov_metadata(tmp, exact_klass->constant_encoding());
3663 } else {
3664 __ load_klass(tmp, obj, tmp_load_klass);
3665 }
3666 #ifdef _LP64
3667 __ mov(rscratch1, tmp); // save original value before XOR
3668 #endif
3669 __ xorptr(tmp, mdo_addr);
3670 __ testptr(tmp, TypeEntries::type_klass_mask);
3671 // klass seen before, nothing to do. The unknown bit may have been
3672 // set already but no need to check.
3673 __ jccb(Assembler::zero, next);
3674
3675 __ testptr(tmp, TypeEntries::type_unknown);
3676 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3677
3678 if (TypeEntries::is_type_none(current_klass)) {
3679 __ testptr(mdo_addr, TypeEntries::type_mask);
3680 __ jccb(Assembler::zero, none);
3681 #ifdef _LP64
3682 // There is a chance that the checks above (re-reading profiling
3683 // data from memory) fail if another thread has just set the
3684 // profiling to this obj's klass
3685 __ mov(tmp, rscratch1); // get back original value before XOR
3686 __ xorptr(tmp, mdo_addr);
3687 __ testptr(tmp, TypeEntries::type_klass_mask);
3688 __ jccb(Assembler::zero, next);
3689 #endif
3690 }
3691 } else {
3692 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3693 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3694
3695 __ testptr(mdo_addr, TypeEntries::type_unknown);
3696 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3697 }
3698
3699 // different than before. Cannot keep accurate profile.
3700 __ orptr(mdo_addr, TypeEntries::type_unknown);
3701
3702 if (TypeEntries::is_type_none(current_klass)) {
3703 __ jmpb(next);
3704
3705 __ bind(none);
3706 // first time here. Set profile type.
3707 __ movptr(mdo_addr, tmp);
3708 #ifdef ASSERT
3709 __ andptr(tmp, TypeEntries::type_klass_mask);
3710 __ verify_klass_ptr(tmp);
3711 #endif
3712 }
3713 } else {
3714 // There's a single possible klass at this profile point
3715 assert(exact_klass != nullptr, "should be");
3716 if (TypeEntries::is_type_none(current_klass)) {
3717 __ mov_metadata(tmp, exact_klass->constant_encoding());
3718 __ xorptr(tmp, mdo_addr);
3719 __ testptr(tmp, TypeEntries::type_klass_mask);
3720 #ifdef ASSERT
3721 __ jcc(Assembler::zero, next);
3722
3723 {
3724 Label ok;
3725 __ push(tmp);
3726 __ testptr(mdo_addr, TypeEntries::type_mask);
3727 __ jcc(Assembler::zero, ok);
3728 // may have been set by another thread
3729 __ mov_metadata(tmp, exact_klass->constant_encoding());
3730 __ xorptr(tmp, mdo_addr);
3731 __ testptr(tmp, TypeEntries::type_mask);
3732 __ jcc(Assembler::zero, ok);
3733
3734 __ stop("unexpected profiling mismatch");
3735 __ bind(ok);
3736 __ pop(tmp);
3737 }
3738 #else
3739 __ jccb(Assembler::zero, next);
3740 #endif
3741 // first time here. Set profile type.
3742 __ movptr(mdo_addr, tmp);
3743 #ifdef ASSERT
3744 __ andptr(tmp, TypeEntries::type_klass_mask);
3745 __ verify_klass_ptr(tmp);
3746 #endif
3747 } else {
3748 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3749 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3750
3751 __ testptr(mdo_addr, TypeEntries::type_unknown);
3752 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3753
3754 __ orptr(mdo_addr, TypeEntries::type_unknown);
3755 }
3756 }
3757 }
3758 __ bind(next);
3759 }
3760
3761 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3762 Unimplemented();
3763 }
3764
3765
3766 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3767 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3768 }
3769
3770
3771 void LIR_Assembler::align_backward_branch_target() {
3772 __ align(BytesPerWord);
3773 }
3774
3775
3776 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3777 if (left->is_single_cpu()) {
3778 __ negl(left->as_register());
3779 move_regs(left->as_register(), dest->as_register());
3780
3781 } else if (left->is_double_cpu()) {
3782 Register lo = left->as_register_lo();
3783 #ifdef _LP64
3784 Register dst = dest->as_register_lo();
3785 __ movptr(dst, lo);
3786 __ negptr(dst);
3787 #else
3788 Register hi = left->as_register_hi();
3789 __ lneg(hi, lo);
3790 if (dest->as_register_lo() == hi) {
3791 assert(dest->as_register_hi() != lo, "destroying register");
3792 move_regs(hi, dest->as_register_hi());
3793 move_regs(lo, dest->as_register_lo());
3794 } else {
3795 move_regs(lo, dest->as_register_lo());
3796 move_regs(hi, dest->as_register_hi());
3797 }
3798 #endif // _LP64
3799
3800 } else if (dest->is_single_xmm()) {
3801 #ifdef _LP64
3802 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3803 assert(tmp->is_valid(), "need temporary");
3804 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
3805 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
3806 }
3807 else
3808 #endif
3809 {
3810 assert(!tmp->is_valid(), "do not need temporary");
3811 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3812 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3813 }
3814 __ xorps(dest->as_xmm_float_reg(),
3815 ExternalAddress((address)float_signflip_pool),
3816 rscratch1);
3817 }
3818 } else if (dest->is_double_xmm()) {
3819 #ifdef _LP64
3820 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3821 assert(tmp->is_valid(), "need temporary");
3822 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
3823 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
3824 }
3825 else
3826 #endif
3827 {
3828 assert(!tmp->is_valid(), "do not need temporary");
3829 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3830 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3831 }
3832 __ xorpd(dest->as_xmm_double_reg(),
3833 ExternalAddress((address)double_signflip_pool),
3834 rscratch1);
3835 }
3836 #ifndef _LP64
3837 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3838 assert(left->fpu() == 0, "arg must be on TOS");
3839 assert(dest->fpu() == 0, "dest must be TOS");
3840 __ fchs();
3841 #endif // !_LP64
3842
3843 } else {
3844 ShouldNotReachHere();
3845 }
3846 }
3847
3848
3849 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3850 assert(src->is_address(), "must be an address");
3851 assert(dest->is_register(), "must be a register");
3852
3853 PatchingStub* patch = nullptr;
3854 if (patch_code != lir_patch_none) {
3855 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3856 }
3857
3858 Register reg = dest->as_pointer_register();
3859 LIR_Address* addr = src->as_address_ptr();
3860 __ lea(reg, as_Address(addr));
3861
3862 if (patch != nullptr) {
3863 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3864 }
3865 }
3866
3867
3868
3869 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3870 assert(!tmp->is_valid(), "don't need temporary");
3871 __ call(RuntimeAddress(dest));
3872 if (info != nullptr) {
3873 add_call_info_here(info);
3874 }
3875 __ post_call_nop();
3876 }
3877
3878
3879 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3880 assert(type == T_LONG, "only for volatile long fields");
3881
3882 if (info != nullptr) {
3883 add_debug_info_for_null_check_here(info);
3884 }
3885
3886 if (src->is_double_xmm()) {
3887 if (dest->is_double_cpu()) {
3888 #ifdef _LP64
3889 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3890 #else
3891 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3892 __ psrlq(src->as_xmm_double_reg(), 32);
3893 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3894 #endif // _LP64
3895 } else if (dest->is_double_stack()) {
3896 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3897 } else if (dest->is_address()) {
3898 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3899 } else {
3900 ShouldNotReachHere();
3901 }
3902
3903 } else if (dest->is_double_xmm()) {
3904 if (src->is_double_stack()) {
3905 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3906 } else if (src->is_address()) {
3907 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3908 } else {
3909 ShouldNotReachHere();
3910 }
3911
3912 #ifndef _LP64
3913 } else if (src->is_double_fpu()) {
3914 assert(src->fpu_regnrLo() == 0, "must be TOS");
3915 if (dest->is_double_stack()) {
3916 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3917 } else if (dest->is_address()) {
3918 __ fistp_d(as_Address(dest->as_address_ptr()));
3919 } else {
3920 ShouldNotReachHere();
3921 }
3922
3923 } else if (dest->is_double_fpu()) {
3924 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3925 if (src->is_double_stack()) {
3926 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3927 } else if (src->is_address()) {
3928 __ fild_d(as_Address(src->as_address_ptr()));
3929 } else {
3930 ShouldNotReachHere();
3931 }
3932 #endif // !_LP64
3933
3934 } else {
3935 ShouldNotReachHere();
3936 }
3937 }
3938
3939 #ifdef ASSERT
3940 // emit run-time assertion
3941 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3942 assert(op->code() == lir_assert, "must be");
3943
3944 if (op->in_opr1()->is_valid()) {
3945 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3946 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3947 } else {
3948 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3949 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3950 }
3951
3952 Label ok;
3953 if (op->condition() != lir_cond_always) {
3954 Assembler::Condition acond = Assembler::zero;
3955 switch (op->condition()) {
3956 case lir_cond_equal: acond = Assembler::equal; break;
3957 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3958 case lir_cond_less: acond = Assembler::less; break;
3959 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3960 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3961 case lir_cond_greater: acond = Assembler::greater; break;
3962 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3963 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3964 default: ShouldNotReachHere();
3965 }
3966 __ jcc(acond, ok);
3967 }
3968 if (op->halt()) {
3969 const char* str = __ code_string(op->msg());
3970 __ stop(str);
3971 } else {
3972 breakpoint();
3973 }
3974 __ bind(ok);
3975 }
3976 #endif
3977
3978 void LIR_Assembler::membar() {
3979 // QQQ sparc TSO uses this,
3980 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3981 }
3982
3983 void LIR_Assembler::membar_acquire() {
3984 // No x86 machines currently require load fences
3985 }
3986
3987 void LIR_Assembler::membar_release() {
3988 // No x86 machines currently require store fences
3989 }
3990
3991 void LIR_Assembler::membar_loadload() {
3992 // no-op
3993 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3994 }
3995
3996 void LIR_Assembler::membar_storestore() {
3997 // no-op
3998 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3999 }
4000
4001 void LIR_Assembler::membar_loadstore() {
4002 // no-op
4003 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4004 }
4005
4006 void LIR_Assembler::membar_storeload() {
4007 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4008 }
4009
4010 void LIR_Assembler::on_spin_wait() {
4011 __ pause ();
4012 }
4013
4014 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4015 assert(result_reg->is_register(), "check");
4016 #ifdef _LP64
4017 // __ get_thread(result_reg->as_register_lo());
4018 __ mov(result_reg->as_register(), r15_thread);
4019 #else
4020 __ get_thread(result_reg->as_register());
4021 #endif // _LP64
4022 }
4023
4024
4025 void LIR_Assembler::peephole(LIR_List*) {
4026 // do nothing for now
4027 }
4028
4029 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4030 assert(data == dest, "xchg/xadd uses only 2 operands");
4031
4032 if (data->type() == T_INT) {
4033 if (code == lir_xadd) {
4034 __ lock();
4035 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4036 } else {
4037 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4038 }
4039 } else if (data->is_oop()) {
4040 assert (code == lir_xchg, "xadd for oops");
4041 Register obj = data->as_register();
4042 #ifdef _LP64
4043 if (UseCompressedOops) {
4044 __ encode_heap_oop(obj);
4045 __ xchgl(obj, as_Address(src->as_address_ptr()));
4046 __ decode_heap_oop(obj);
4047 } else {
4048 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4049 }
4050 #else
4051 __ xchgl(obj, as_Address(src->as_address_ptr()));
4052 #endif
4053 } else if (data->type() == T_LONG) {
4054 #ifdef _LP64
4055 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4056 if (code == lir_xadd) {
4057 __ lock();
4058 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4059 } else {
4060 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4061 }
4062 #else
4063 ShouldNotReachHere();
4064 #endif
4065 } else {
4066 ShouldNotReachHere();
4067 }
4068 }
4069
4070 #undef __