1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/macroAssembler.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "c1/c1_CodeStubs.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "compiler/oopMap.hpp"
36 #include "gc/shared/collectedHeap.hpp"
37 #include "gc/shared/gc_globals.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/frame.inline.hpp"
41 #include "runtime/safepointMechanism.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "runtime/stubRoutines.hpp"
44 #include "utilities/powerOfTwo.hpp"
45 #include "vmreg_x86.inline.hpp"
46
47
48 // These masks are used to provide 128-bit aligned bitmasks to the XMM
49 // instructions, to allow sign-masking or sign-bit flipping. They allow
50 // fast versions of NegF/NegD and AbsF/AbsD.
51
52 // Note: 'double' and 'long long' have 32-bits alignment on x86.
53 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
54 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
55 // of 128-bits operands for SSE instructions.
56 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
57 // Store the value to a 128-bits operand.
58 operand[0] = lo;
59 operand[1] = hi;
60 return operand;
61 }
62
63 // Buffer for 128-bits masks used by SSE instructions.
64 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
65
66 // Static initialization during VM startup.
67 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
68 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
69 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
70 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
71
72
73 NEEDS_CLEANUP // remove this definitions ?
74 const Register SYNC_header = rax; // synchronization header
75 const Register SHIFT_count = rcx; // where count for shift operations must be
76
77 #define __ _masm->
78
79
80 static void select_different_registers(Register preserve,
81 Register extra,
82 Register &tmp1,
83 Register &tmp2) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, extra);
89 tmp2 = extra;
90 }
91 assert_different_registers(preserve, tmp1, tmp2);
92 }
93
94
95
96 static void select_different_registers(Register preserve,
97 Register extra,
98 Register &tmp1,
99 Register &tmp2,
100 Register &tmp3) {
101 if (tmp1 == preserve) {
102 assert_different_registers(tmp1, tmp2, tmp3, extra);
103 tmp1 = extra;
104 } else if (tmp2 == preserve) {
105 assert_different_registers(tmp1, tmp2, tmp3, extra);
106 tmp2 = extra;
107 } else if (tmp3 == preserve) {
108 assert_different_registers(tmp1, tmp2, tmp3, extra);
109 tmp3 = extra;
110 }
111 assert_different_registers(preserve, tmp1, tmp2, tmp3);
112 }
113
114
115
116 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
117 if (opr->is_constant()) {
118 LIR_Const* constant = opr->as_constant_ptr();
119 switch (constant->type()) {
120 case T_INT: {
121 return true;
122 }
123
124 default:
125 return false;
126 }
127 }
128 return false;
129 }
130
131
132 LIR_Opr LIR_Assembler::receiverOpr() {
133 return FrameMap::receiver_opr;
134 }
135
136 LIR_Opr LIR_Assembler::osrBufferPointer() {
137 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
138 }
139
140 //--------------fpu register translations-----------------------
141
142
143 address LIR_Assembler::float_constant(float f) {
144 address const_addr = __ float_constant(f);
145 if (const_addr == nullptr) {
146 bailout("const section overflow");
147 return __ code()->consts()->start();
148 } else {
149 return const_addr;
150 }
151 }
152
153
154 address LIR_Assembler::double_constant(double d) {
155 address const_addr = __ double_constant(d);
156 if (const_addr == nullptr) {
157 bailout("const section overflow");
158 return __ code()->consts()->start();
159 } else {
160 return const_addr;
161 }
162 }
163
164 void LIR_Assembler::breakpoint() {
165 __ int3();
166 }
167
168 void LIR_Assembler::push(LIR_Opr opr) {
169 if (opr->is_single_cpu()) {
170 __ push_reg(opr->as_register());
171 } else if (opr->is_double_cpu()) {
172 __ push_reg(opr->as_register_lo());
173 } else if (opr->is_stack()) {
174 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
175 } else if (opr->is_constant()) {
176 LIR_Const* const_opr = opr->as_constant_ptr();
177 if (const_opr->type() == T_OBJECT) {
178 __ push_oop(const_opr->as_jobject(), rscratch1);
179 } else if (const_opr->type() == T_INT) {
180 __ push_jint(const_opr->as_jint());
181 } else {
182 ShouldNotReachHere();
183 }
184
185 } else {
186 ShouldNotReachHere();
187 }
188 }
189
190 void LIR_Assembler::pop(LIR_Opr opr) {
191 if (opr->is_single_cpu()) {
192 __ pop_reg(opr->as_register());
193 } else {
194 ShouldNotReachHere();
195 }
196 }
197
198 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
199 return addr->base()->is_illegal() && addr->index()->is_illegal();
200 }
201
202 //-------------------------------------------
203
204 Address LIR_Assembler::as_Address(LIR_Address* addr) {
205 return as_Address(addr, rscratch1);
206 }
207
208 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
209 if (addr->base()->is_illegal()) {
210 assert(addr->index()->is_illegal(), "must be illegal too");
211 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
212 if (! __ reachable(laddr)) {
213 __ movptr(tmp, laddr.addr());
214 Address res(tmp, 0);
215 return res;
216 } else {
217 return __ as_Address(laddr);
218 }
219 }
220
221 Register base = addr->base()->as_pointer_register();
222
223 if (addr->index()->is_illegal()) {
224 return Address( base, addr->disp());
225 } else if (addr->index()->is_cpu_register()) {
226 Register index = addr->index()->as_pointer_register();
227 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
228 } else if (addr->index()->is_constant()) {
229 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
230 assert(Assembler::is_simm32(addr_offset), "must be");
231
232 return Address(base, addr_offset);
233 } else {
234 Unimplemented();
235 return Address();
236 }
237 }
238
239
240 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
241 Address base = as_Address(addr);
242 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
243 }
244
245
246 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
247 return as_Address(addr);
248 }
249
250
251 void LIR_Assembler::osr_entry() {
252 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
253 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
254 ValueStack* entry_state = osr_entry->state();
255 int number_of_locks = entry_state->locks_size();
256
257 // we jump here if osr happens with the interpreter
258 // state set up to continue at the beginning of the
259 // loop that triggered osr - in particular, we have
260 // the following registers setup:
261 //
262 // rcx: osr buffer
263 //
264
265 // build frame
266 ciMethod* m = compilation()->method();
267 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
268
269 // OSR buffer is
270 //
271 // locals[nlocals-1..0]
272 // monitors[0..number_of_locks]
273 //
274 // locals is a direct copy of the interpreter frame so in the osr buffer
275 // so first slot in the local array is the last local from the interpreter
276 // and last slot is local[0] (receiver) from the interpreter
277 //
278 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
279 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
280 // in the interpreter frame (the method lock if a sync method)
281
282 // Initialize monitors in the compiled activation.
283 // rcx: pointer to osr buffer
284 //
285 // All other registers are dead at this point and the locals will be
286 // copied into place by code emitted in the IR.
287
288 Register OSR_buf = osrBufferPointer()->as_pointer_register();
289 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
290 int monitor_offset = BytesPerWord * method()->max_locals() +
291 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
292 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
293 // the OSR buffer using 2 word entries: first the lock and then
294 // the oop.
295 for (int i = 0; i < number_of_locks; i++) {
296 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
297 #ifdef ASSERT
298 // verify the interpreter's monitor has a non-null object
299 {
300 Label L;
301 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD);
302 __ jcc(Assembler::notZero, L);
303 __ stop("locked object is null");
304 __ bind(L);
305 }
306 #endif
307 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
308 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
309 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
310 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
311 }
312 }
313 }
314
315
316 // inline cache check; done before the frame is built.
317 int LIR_Assembler::check_icache() {
318 return __ ic_check(CodeEntryAlignment);
319 }
320
321 void LIR_Assembler::clinit_barrier(ciMethod* method) {
322 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
323 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
324
325 Label L_skip_barrier;
326 Register klass = rscratch1;
327
328 __ mov_metadata(klass, method->holder()->constant_encoding());
329 __ clinit_barrier(klass, &L_skip_barrier /*L_fast_path*/);
330
331 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
332
333 __ bind(L_skip_barrier);
334 }
335
336 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
337 jobject o = nullptr;
338 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
339 __ movoop(reg, o);
340 patching_epilog(patch, lir_patch_normal, reg, info);
341 }
342
343 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
344 Metadata* o = nullptr;
345 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
346 __ mov_metadata(reg, o);
347 patching_epilog(patch, lir_patch_normal, reg, info);
348 }
349
350 // This specifies the rsp decrement needed to build the frame
351 int LIR_Assembler::initial_frame_size_in_bytes() const {
352 // if rounding, must let FrameMap know!
353
354 // The frame_map records size in slots (32bit word)
355
356 // subtract two words to account for return address and link
357 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
358 }
359
360
361 int LIR_Assembler::emit_exception_handler() {
362 // generate code for exception handler
363 address handler_base = __ start_a_stub(exception_handler_size());
364 if (handler_base == nullptr) {
365 // not enough space left for the handler
366 bailout("exception handler overflow");
367 return -1;
368 }
369
370 int offset = code_offset();
371
372 // the exception oop and pc are in rax, and rdx
373 // no other registers need to be preserved, so invalidate them
374 __ invalidate_registers(false, true, true, false, true, true);
375
376 // check that there is really an exception
377 __ verify_not_null_oop(rax);
378
379 // search an exception handler (rax: exception oop, rdx: throwing pc)
380 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
381 __ should_not_reach_here();
382 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
383 __ end_a_stub();
384
385 return offset;
386 }
387
388
389 // Emit the code to remove the frame from the stack in the exception
390 // unwind path.
391 int LIR_Assembler::emit_unwind_handler() {
392 #ifndef PRODUCT
393 if (CommentedAssembly) {
394 _masm->block_comment("Unwind handler");
395 }
396 #endif
397
398 int offset = code_offset();
399
400 // Fetch the exception from TLS and clear out exception related thread state
401 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
402 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), NULL_WORD);
403 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), NULL_WORD);
404
405 __ bind(_unwind_handler_entry);
406 __ verify_not_null_oop(rax);
407 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
408 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
409 }
410
411 // Perform needed unlocking
412 MonitorExitStub* stub = nullptr;
413 if (method()->is_synchronized()) {
414 monitor_address(0, FrameMap::rax_opr);
415 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
416 if (LockingMode == LM_MONITOR) {
417 __ jmp(*stub->entry());
418 } else {
419 __ unlock_object(rdi, rsi, rax, *stub->entry());
420 }
421 __ bind(*stub->continuation());
422 }
423
424 if (compilation()->env()->dtrace_method_probes()) {
425 __ mov(rdi, r15_thread);
426 __ mov_metadata(rsi, method()->constant_encoding());
427 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
428 }
429
430 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
431 __ mov(rax, rbx); // Restore the exception
432 }
433
434 // remove the activation and dispatch to the unwind handler
435 __ remove_frame(initial_frame_size_in_bytes());
436 __ jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
437
438 // Emit the slow path assembly
439 if (stub != nullptr) {
440 stub->emit_code(this);
441 }
442
443 return offset;
444 }
445
446
447 int LIR_Assembler::emit_deopt_handler() {
448 // generate code for exception handler
449 address handler_base = __ start_a_stub(deopt_handler_size());
450 if (handler_base == nullptr) {
451 // not enough space left for the handler
452 bailout("deopt handler overflow");
453 return -1;
454 }
455
456 int offset = code_offset();
457 InternalAddress here(__ pc());
458
459 __ pushptr(here.addr(), rscratch1);
460 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
461 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
462 __ end_a_stub();
463
464 return offset;
465 }
466
467 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
468 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
469 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
470 assert(result->fpu() == 0, "result must already be on TOS");
471 }
472
473 // Pop the stack before the safepoint code
474 __ remove_frame(initial_frame_size_in_bytes());
475
476 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
477 __ reserved_stack_check();
478 }
479
480 // Note: we do not need to round double result; float result has the right precision
481 // the poll sets the condition code, but no data registers
482
483 code_stub->set_safepoint_offset(__ offset());
484 __ relocate(relocInfo::poll_return_type);
485 __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
486 __ ret(0);
487 }
488
489
490 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
491 guarantee(info != nullptr, "Shouldn't be null");
492 int offset = __ offset();
493 const Register poll_addr = rscratch1;
494 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
495 add_debug_info_for_branch(info);
496 __ relocate(relocInfo::poll_type);
497 address pre_pc = __ pc();
498 __ testl(rax, Address(poll_addr, 0));
499 address post_pc = __ pc();
500 guarantee(pointer_delta(post_pc, pre_pc, 1) == 3, "must be exact length");
501 return offset;
502 }
503
504
505 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
506 if (from_reg != to_reg) __ mov(to_reg, from_reg);
507 }
508
509 void LIR_Assembler::swap_reg(Register a, Register b) {
510 __ xchgptr(a, b);
511 }
512
513
514 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
515 assert(src->is_constant(), "should not call otherwise");
516 assert(dest->is_register(), "should not call otherwise");
517 LIR_Const* c = src->as_constant_ptr();
518
519 switch (c->type()) {
520 case T_INT: {
521 assert(patch_code == lir_patch_none, "no patching handled here");
522 __ movl(dest->as_register(), c->as_jint());
523 break;
524 }
525
526 case T_ADDRESS: {
527 assert(patch_code == lir_patch_none, "no patching handled here");
528 __ movptr(dest->as_register(), c->as_jint());
529 break;
530 }
531
532 case T_LONG: {
533 assert(patch_code == lir_patch_none, "no patching handled here");
534 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
535 break;
536 }
537
538 case T_OBJECT: {
539 if (patch_code != lir_patch_none) {
540 jobject2reg_with_patching(dest->as_register(), info);
541 } else {
542 __ movoop(dest->as_register(), c->as_jobject());
543 }
544 break;
545 }
546
547 case T_METADATA: {
548 if (patch_code != lir_patch_none) {
549 klass2reg_with_patching(dest->as_register(), info);
550 } else {
551 __ mov_metadata(dest->as_register(), c->as_metadata());
552 }
553 break;
554 }
555
556 case T_FLOAT: {
557 if (dest->is_single_xmm()) {
558 if (UseAVX <= 2 && c->is_zero_float()) {
559 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
560 } else {
561 __ movflt(dest->as_xmm_float_reg(),
562 InternalAddress(float_constant(c->as_jfloat())));
563 }
564 } else {
565 ShouldNotReachHere();
566 }
567 break;
568 }
569
570 case T_DOUBLE: {
571 if (dest->is_double_xmm()) {
572 if (UseAVX <= 2 && c->is_zero_double()) {
573 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
574 } else {
575 __ movdbl(dest->as_xmm_double_reg(),
576 InternalAddress(double_constant(c->as_jdouble())));
577 }
578 } else {
579 ShouldNotReachHere();
580 }
581 break;
582 }
583
584 default:
585 ShouldNotReachHere();
586 }
587 }
588
589 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
590 assert(src->is_constant(), "should not call otherwise");
591 assert(dest->is_stack(), "should not call otherwise");
592 LIR_Const* c = src->as_constant_ptr();
593
594 switch (c->type()) {
595 case T_INT: // fall through
596 case T_FLOAT:
597 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
598 break;
599
600 case T_ADDRESS:
601 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
602 break;
603
604 case T_OBJECT:
605 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1);
606 break;
607
608 case T_LONG: // fall through
609 case T_DOUBLE:
610 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
611 lo_word_offset_in_bytes),
612 (intptr_t)c->as_jlong_bits(),
613 rscratch1);
614 break;
615
616 default:
617 ShouldNotReachHere();
618 }
619 }
620
621 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
622 assert(src->is_constant(), "should not call otherwise");
623 assert(dest->is_address(), "should not call otherwise");
624 LIR_Const* c = src->as_constant_ptr();
625 LIR_Address* addr = dest->as_address_ptr();
626
627 int null_check_here = code_offset();
628 switch (type) {
629 case T_INT: // fall through
630 case T_FLOAT:
631 __ movl(as_Address(addr), c->as_jint_bits());
632 break;
633
634 case T_ADDRESS:
635 __ movptr(as_Address(addr), c->as_jint_bits());
636 break;
637
638 case T_OBJECT: // fall through
639 case T_ARRAY:
640 if (c->as_jobject() == nullptr) {
641 if (UseCompressedOops && !wide) {
642 __ movl(as_Address(addr), NULL_WORD);
643 } else {
644 __ xorptr(rscratch1, rscratch1);
645 null_check_here = code_offset();
646 __ movptr(as_Address(addr), rscratch1);
647 }
648 } else {
649 if (is_literal_address(addr)) {
650 ShouldNotReachHere();
651 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1);
652 } else {
653 __ movoop(rscratch1, c->as_jobject());
654 if (UseCompressedOops && !wide) {
655 __ encode_heap_oop(rscratch1);
656 null_check_here = code_offset();
657 __ movl(as_Address_lo(addr), rscratch1);
658 } else {
659 null_check_here = code_offset();
660 __ movptr(as_Address_lo(addr), rscratch1);
661 }
662 }
663 }
664 break;
665
666 case T_LONG: // fall through
667 case T_DOUBLE:
668 if (is_literal_address(addr)) {
669 ShouldNotReachHere();
670 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
671 } else {
672 __ movptr(r10, (intptr_t)c->as_jlong_bits());
673 null_check_here = code_offset();
674 __ movptr(as_Address_lo(addr), r10);
675 }
676 break;
677
678 case T_BOOLEAN: // fall through
679 case T_BYTE:
680 __ movb(as_Address(addr), c->as_jint() & 0xFF);
681 break;
682
683 case T_CHAR: // fall through
684 case T_SHORT:
685 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
686 break;
687
688 default:
689 ShouldNotReachHere();
690 };
691
692 if (info != nullptr) {
693 add_debug_info_for_null_check(null_check_here, info);
694 }
695 }
696
697
698 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
699 assert(src->is_register(), "should not call otherwise");
700 assert(dest->is_register(), "should not call otherwise");
701
702 // move between cpu-registers
703 if (dest->is_single_cpu()) {
704 if (src->type() == T_LONG) {
705 // Can do LONG -> OBJECT
706 move_regs(src->as_register_lo(), dest->as_register());
707 return;
708 }
709 assert(src->is_single_cpu(), "must match");
710 if (src->type() == T_OBJECT) {
711 __ verify_oop(src->as_register());
712 }
713 move_regs(src->as_register(), dest->as_register());
714
715 } else if (dest->is_double_cpu()) {
716 if (is_reference_type(src->type())) {
717 // Surprising to me but we can see move of a long to t_object
718 __ verify_oop(src->as_register());
719 move_regs(src->as_register(), dest->as_register_lo());
720 return;
721 }
722 assert(src->is_double_cpu(), "must match");
723 Register f_lo = src->as_register_lo();
724 Register f_hi = src->as_register_hi();
725 Register t_lo = dest->as_register_lo();
726 Register t_hi = dest->as_register_hi();
727 assert(f_hi == f_lo, "must be same");
728 assert(t_hi == t_lo, "must be same");
729 move_regs(f_lo, t_lo);
730
731 // move between xmm-registers
732 } else if (dest->is_single_xmm()) {
733 assert(src->is_single_xmm(), "must match");
734 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
735 } else if (dest->is_double_xmm()) {
736 assert(src->is_double_xmm(), "must match");
737 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
738
739 } else {
740 ShouldNotReachHere();
741 }
742 }
743
744 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
745 assert(src->is_register(), "should not call otherwise");
746 assert(dest->is_stack(), "should not call otherwise");
747
748 if (src->is_single_cpu()) {
749 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
750 if (is_reference_type(type)) {
751 __ verify_oop(src->as_register());
752 __ movptr (dst, src->as_register());
753 } else if (type == T_METADATA || type == T_ADDRESS) {
754 __ movptr (dst, src->as_register());
755 } else {
756 __ movl (dst, src->as_register());
757 }
758
759 } else if (src->is_double_cpu()) {
760 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
761 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
762 __ movptr (dstLO, src->as_register_lo());
763
764 } else if (src->is_single_xmm()) {
765 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
766 __ movflt(dst_addr, src->as_xmm_float_reg());
767
768 } else if (src->is_double_xmm()) {
769 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
770 __ movdbl(dst_addr, src->as_xmm_double_reg());
771
772 } else {
773 ShouldNotReachHere();
774 }
775 }
776
777
778 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
779 LIR_Address* to_addr = dest->as_address_ptr();
780 PatchingStub* patch = nullptr;
781 Register compressed_src = rscratch1;
782
783 if (is_reference_type(type)) {
784 __ verify_oop(src->as_register());
785 if (UseCompressedOops && !wide) {
786 __ movptr(compressed_src, src->as_register());
787 __ encode_heap_oop(compressed_src);
788 if (patch_code != lir_patch_none) {
789 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
790 }
791 }
792 }
793
794 if (patch_code != lir_patch_none) {
795 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
796 Address toa = as_Address(to_addr);
797 assert(toa.disp() != 0, "must have");
798 }
799
800 int null_check_here = code_offset();
801 switch (type) {
802 case T_FLOAT: {
803 assert(src->is_single_xmm(), "not a float");
804 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
805 break;
806 }
807
808 case T_DOUBLE: {
809 assert(src->is_double_xmm(), "not a double");
810 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
811 break;
812 }
813
814 case T_ARRAY: // fall through
815 case T_OBJECT: // fall through
816 if (UseCompressedOops && !wide) {
817 __ movl(as_Address(to_addr), compressed_src);
818 } else {
819 __ movptr(as_Address(to_addr), src->as_register());
820 }
821 break;
822 case T_ADDRESS:
823 __ movptr(as_Address(to_addr), src->as_register());
824 break;
825 case T_INT:
826 __ movl(as_Address(to_addr), src->as_register());
827 break;
828
829 case T_LONG: {
830 Register from_lo = src->as_register_lo();
831 Register from_hi = src->as_register_hi();
832 __ movptr(as_Address_lo(to_addr), from_lo);
833 break;
834 }
835
836 case T_BYTE: // fall through
837 case T_BOOLEAN: {
838 Register src_reg = src->as_register();
839 Address dst_addr = as_Address(to_addr);
840 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
841 __ movb(dst_addr, src_reg);
842 break;
843 }
844
845 case T_CHAR: // fall through
846 case T_SHORT:
847 __ movw(as_Address(to_addr), src->as_register());
848 break;
849
850 default:
851 ShouldNotReachHere();
852 }
853 if (info != nullptr) {
854 add_debug_info_for_null_check(null_check_here, info);
855 }
856
857 if (patch_code != lir_patch_none) {
858 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
859 }
860 }
861
862
863 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
864 assert(src->is_stack(), "should not call otherwise");
865 assert(dest->is_register(), "should not call otherwise");
866
867 if (dest->is_single_cpu()) {
868 if (is_reference_type(type)) {
869 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
870 __ verify_oop(dest->as_register());
871 } else if (type == T_METADATA || type == T_ADDRESS) {
872 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
873 } else {
874 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
875 }
876
877 } else if (dest->is_double_cpu()) {
878 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
879 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
880 __ movptr(dest->as_register_lo(), src_addr_LO);
881
882 } else if (dest->is_single_xmm()) {
883 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
884 __ movflt(dest->as_xmm_float_reg(), src_addr);
885
886 } else if (dest->is_double_xmm()) {
887 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
888 __ movdbl(dest->as_xmm_double_reg(), src_addr);
889
890 } else {
891 ShouldNotReachHere();
892 }
893 }
894
895
896 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
897 if (src->is_single_stack()) {
898 if (is_reference_type(type)) {
899 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
900 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
901 } else {
902 //no pushl on 64bits
903 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
904 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
905 }
906
907 } else if (src->is_double_stack()) {
908 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
909 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
910
911 } else {
912 ShouldNotReachHere();
913 }
914 }
915
916
917 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
918 assert(src->is_address(), "should not call otherwise");
919 assert(dest->is_register(), "should not call otherwise");
920
921 LIR_Address* addr = src->as_address_ptr();
922 Address from_addr = as_Address(addr);
923
924 if (addr->base()->type() == T_OBJECT) {
925 __ verify_oop(addr->base()->as_pointer_register());
926 }
927
928 switch (type) {
929 case T_BOOLEAN: // fall through
930 case T_BYTE: // fall through
931 case T_CHAR: // fall through
932 case T_SHORT:
933 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
934 // on pre P6 processors we may get partial register stalls
935 // so blow away the value of to_rinfo before loading a
936 // partial word into it. Do it here so that it precedes
937 // the potential patch point below.
938 __ xorptr(dest->as_register(), dest->as_register());
939 }
940 break;
941 default:
942 break;
943 }
944
945 PatchingStub* patch = nullptr;
946 if (patch_code != lir_patch_none) {
947 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
948 assert(from_addr.disp() != 0, "must have");
949 }
950 if (info != nullptr) {
951 add_debug_info_for_null_check_here(info);
952 }
953
954 switch (type) {
955 case T_FLOAT: {
956 if (dest->is_single_xmm()) {
957 __ movflt(dest->as_xmm_float_reg(), from_addr);
958 } else {
959 ShouldNotReachHere();
960 }
961 break;
962 }
963
964 case T_DOUBLE: {
965 if (dest->is_double_xmm()) {
966 __ movdbl(dest->as_xmm_double_reg(), from_addr);
967 } else {
968 ShouldNotReachHere();
969 }
970 break;
971 }
972
973 case T_OBJECT: // fall through
974 case T_ARRAY: // fall through
975 if (UseCompressedOops && !wide) {
976 __ movl(dest->as_register(), from_addr);
977 } else {
978 __ movptr(dest->as_register(), from_addr);
979 }
980 break;
981
982 case T_ADDRESS:
983 __ movptr(dest->as_register(), from_addr);
984 break;
985 case T_INT:
986 __ movl(dest->as_register(), from_addr);
987 break;
988
989 case T_LONG: {
990 Register to_lo = dest->as_register_lo();
991 Register to_hi = dest->as_register_hi();
992 __ movptr(to_lo, as_Address_lo(addr));
993 break;
994 }
995
996 case T_BOOLEAN: // fall through
997 case T_BYTE: {
998 Register dest_reg = dest->as_register();
999 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1000 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1001 __ movsbl(dest_reg, from_addr);
1002 } else {
1003 __ movb(dest_reg, from_addr);
1004 __ shll(dest_reg, 24);
1005 __ sarl(dest_reg, 24);
1006 }
1007 break;
1008 }
1009
1010 case T_CHAR: {
1011 Register dest_reg = dest->as_register();
1012 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1013 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1014 __ movzwl(dest_reg, from_addr);
1015 } else {
1016 __ movw(dest_reg, from_addr);
1017 }
1018 break;
1019 }
1020
1021 case T_SHORT: {
1022 Register dest_reg = dest->as_register();
1023 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1024 __ movswl(dest_reg, from_addr);
1025 } else {
1026 __ movw(dest_reg, from_addr);
1027 __ shll(dest_reg, 16);
1028 __ sarl(dest_reg, 16);
1029 }
1030 break;
1031 }
1032
1033 default:
1034 ShouldNotReachHere();
1035 }
1036
1037 if (patch != nullptr) {
1038 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1039 }
1040
1041 if (is_reference_type(type)) {
1042 if (UseCompressedOops && !wide) {
1043 __ decode_heap_oop(dest->as_register());
1044 }
1045
1046 __ verify_oop(dest->as_register());
1047 }
1048 }
1049
1050
1051 NEEDS_CLEANUP; // This could be static?
1052 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1053 int elem_size = type2aelembytes(type);
1054 switch (elem_size) {
1055 case 1: return Address::times_1;
1056 case 2: return Address::times_2;
1057 case 4: return Address::times_4;
1058 case 8: return Address::times_8;
1059 }
1060 ShouldNotReachHere();
1061 return Address::no_scale;
1062 }
1063
1064
1065 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1066 switch (op->code()) {
1067 case lir_idiv:
1068 case lir_irem:
1069 arithmetic_idiv(op->code(),
1070 op->in_opr1(),
1071 op->in_opr2(),
1072 op->in_opr3(),
1073 op->result_opr(),
1074 op->info());
1075 break;
1076 case lir_fmad:
1077 __ fmad(op->result_opr()->as_xmm_double_reg(),
1078 op->in_opr1()->as_xmm_double_reg(),
1079 op->in_opr2()->as_xmm_double_reg(),
1080 op->in_opr3()->as_xmm_double_reg());
1081 break;
1082 case lir_fmaf:
1083 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1084 op->in_opr1()->as_xmm_float_reg(),
1085 op->in_opr2()->as_xmm_float_reg(),
1086 op->in_opr3()->as_xmm_float_reg());
1087 break;
1088 default: ShouldNotReachHere(); break;
1089 }
1090 }
1091
1092 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1093 #ifdef ASSERT
1094 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1095 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1096 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1097 #endif
1098
1099 if (op->cond() == lir_cond_always) {
1100 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1101 __ jmp (*(op->label()));
1102 } else {
1103 Assembler::Condition acond = Assembler::zero;
1104 if (op->code() == lir_cond_float_branch) {
1105 assert(op->ublock() != nullptr, "must have unordered successor");
1106 __ jcc(Assembler::parity, *(op->ublock()->label()));
1107 switch(op->cond()) {
1108 case lir_cond_equal: acond = Assembler::equal; break;
1109 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1110 case lir_cond_less: acond = Assembler::below; break;
1111 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1112 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1113 case lir_cond_greater: acond = Assembler::above; break;
1114 default: ShouldNotReachHere();
1115 }
1116 } else {
1117 switch (op->cond()) {
1118 case lir_cond_equal: acond = Assembler::equal; break;
1119 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1120 case lir_cond_less: acond = Assembler::less; break;
1121 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1122 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1123 case lir_cond_greater: acond = Assembler::greater; break;
1124 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1125 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1126 default: ShouldNotReachHere();
1127 }
1128 }
1129 __ jcc(acond,*(op->label()));
1130 }
1131 }
1132
1133 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1134 LIR_Opr src = op->in_opr();
1135 LIR_Opr dest = op->result_opr();
1136
1137 switch (op->bytecode()) {
1138 case Bytecodes::_i2l:
1139 __ movl2ptr(dest->as_register_lo(), src->as_register());
1140 break;
1141
1142 case Bytecodes::_l2i:
1143 __ movl(dest->as_register(), src->as_register_lo());
1144 break;
1145
1146 case Bytecodes::_i2b:
1147 move_regs(src->as_register(), dest->as_register());
1148 __ sign_extend_byte(dest->as_register());
1149 break;
1150
1151 case Bytecodes::_i2c:
1152 move_regs(src->as_register(), dest->as_register());
1153 __ andl(dest->as_register(), 0xFFFF);
1154 break;
1155
1156 case Bytecodes::_i2s:
1157 move_regs(src->as_register(), dest->as_register());
1158 __ sign_extend_short(dest->as_register());
1159 break;
1160
1161 case Bytecodes::_f2d:
1162 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1163 break;
1164
1165 case Bytecodes::_d2f:
1166 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1167 break;
1168
1169 case Bytecodes::_i2f:
1170 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1171 break;
1172
1173 case Bytecodes::_i2d:
1174 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1175 break;
1176
1177 case Bytecodes::_l2f:
1178 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1179 break;
1180
1181 case Bytecodes::_l2d:
1182 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1183 break;
1184
1185 case Bytecodes::_f2i:
1186 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1187 break;
1188
1189 case Bytecodes::_d2i:
1190 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1191 break;
1192
1193 case Bytecodes::_f2l:
1194 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1195 break;
1196
1197 case Bytecodes::_d2l:
1198 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1199 break;
1200
1201 default: ShouldNotReachHere();
1202 }
1203 }
1204
1205 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1206 if (op->init_check()) {
1207 add_debug_info_for_null_check_here(op->stub()->info());
1208 // init_state needs acquire, but x86 is TSO, and so we are already good.
1209 __ cmpb(Address(op->klass()->as_register(),
1210 InstanceKlass::init_state_offset()),
1211 InstanceKlass::fully_initialized);
1212 __ jcc(Assembler::notEqual, *op->stub()->entry());
1213 }
1214 __ allocate_object(op->obj()->as_register(),
1215 op->tmp1()->as_register(),
1216 op->tmp2()->as_register(),
1217 op->header_size(),
1218 op->object_size(),
1219 op->klass()->as_register(),
1220 *op->stub()->entry());
1221 __ bind(*op->stub()->continuation());
1222 }
1223
1224 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1225 Register len = op->len()->as_register();
1226 __ movslq(len, len);
1227
1228 if (UseSlowPath ||
1229 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1230 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1231 __ jmp(*op->stub()->entry());
1232 } else {
1233 Register tmp1 = op->tmp1()->as_register();
1234 Register tmp2 = op->tmp2()->as_register();
1235 Register tmp3 = op->tmp3()->as_register();
1236 if (len == tmp1) {
1237 tmp1 = tmp3;
1238 } else if (len == tmp2) {
1239 tmp2 = tmp3;
1240 } else if (len == tmp3) {
1241 // everything is ok
1242 } else {
1243 __ mov(tmp3, len);
1244 }
1245 __ allocate_array(op->obj()->as_register(),
1246 len,
1247 tmp1,
1248 tmp2,
1249 arrayOopDesc::base_offset_in_bytes(op->type()),
1250 array_element_size(op->type()),
1251 op->klass()->as_register(),
1252 *op->stub()->entry(),
1253 op->zero_array());
1254 }
1255 __ bind(*op->stub()->continuation());
1256 }
1257
1258 void LIR_Assembler::type_profile_helper(Register mdo,
1259 ciMethodData *md, ciProfileData *data,
1260 Register recv, Label* update_done) {
1261 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1262 Label next_test;
1263 // See if the receiver is receiver[n].
1264 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1265 __ jccb(Assembler::notEqual, next_test);
1266 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1267 __ addptr(data_addr, DataLayout::counter_increment);
1268 __ jmp(*update_done);
1269 __ bind(next_test);
1270 }
1271
1272 // Didn't find receiver; find next empty slot and fill it in
1273 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1274 Label next_test;
1275 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1276 __ cmpptr(recv_addr, NULL_WORD);
1277 __ jccb(Assembler::notEqual, next_test);
1278 __ movptr(recv_addr, recv);
1279 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1280 __ jmp(*update_done);
1281 __ bind(next_test);
1282 }
1283 }
1284
1285 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1286 // we always need a stub for the failure case.
1287 CodeStub* stub = op->stub();
1288 Register obj = op->object()->as_register();
1289 Register k_RInfo = op->tmp1()->as_register();
1290 Register klass_RInfo = op->tmp2()->as_register();
1291 Register dst = op->result_opr()->as_register();
1292 ciKlass* k = op->klass();
1293 Register Rtmp1 = noreg;
1294 Register tmp_load_klass = rscratch1;
1295
1296 // check if it needs to be profiled
1297 ciMethodData* md = nullptr;
1298 ciProfileData* data = nullptr;
1299
1300 if (op->should_profile()) {
1301 ciMethod* method = op->profiled_method();
1302 assert(method != nullptr, "Should have method");
1303 int bci = op->profiled_bci();
1304 md = method->method_data_or_null();
1305 assert(md != nullptr, "Sanity");
1306 data = md->bci_to_data(bci);
1307 assert(data != nullptr, "need data for type check");
1308 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1309 }
1310 Label* success_target = success;
1311 Label* failure_target = failure;
1312
1313 if (obj == k_RInfo) {
1314 k_RInfo = dst;
1315 } else if (obj == klass_RInfo) {
1316 klass_RInfo = dst;
1317 }
1318 if (k->is_loaded() && !UseCompressedClassPointers) {
1319 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1320 } else {
1321 Rtmp1 = op->tmp3()->as_register();
1322 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1323 }
1324
1325 assert_different_registers(obj, k_RInfo, klass_RInfo);
1326
1327 __ testptr(obj, obj);
1328 if (op->should_profile()) {
1329 Label not_null;
1330 Register mdo = klass_RInfo;
1331 __ mov_metadata(mdo, md->constant_encoding());
1332 __ jccb(Assembler::notEqual, not_null);
1333 // Object is null; update MDO and exit
1334 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1335 int header_bits = BitData::null_seen_byte_constant();
1336 __ orb(data_addr, header_bits);
1337 __ jmp(*obj_is_null);
1338 __ bind(not_null);
1339
1340 Label update_done;
1341 Register recv = k_RInfo;
1342 __ load_klass(recv, obj, tmp_load_klass);
1343 type_profile_helper(mdo, md, data, recv, &update_done);
1344
1345 Address nonprofiled_receiver_count_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1346 __ addptr(nonprofiled_receiver_count_addr, DataLayout::counter_increment);
1347
1348 __ bind(update_done);
1349 } else {
1350 __ jcc(Assembler::equal, *obj_is_null);
1351 }
1352
1353 if (!k->is_loaded()) {
1354 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1355 } else {
1356 __ mov_metadata(k_RInfo, k->constant_encoding());
1357 }
1358 __ verify_oop(obj);
1359
1360 if (op->fast_check()) {
1361 // get object class
1362 // not a safepoint as obj null check happens earlier
1363 if (UseCompressedClassPointers) {
1364 __ load_klass(Rtmp1, obj, tmp_load_klass);
1365 __ cmpptr(k_RInfo, Rtmp1);
1366 } else {
1367 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1368 }
1369 __ jcc(Assembler::notEqual, *failure_target);
1370 // successful cast, fall through to profile or jump
1371 } else {
1372 // get object class
1373 // not a safepoint as obj null check happens earlier
1374 __ load_klass(klass_RInfo, obj, tmp_load_klass);
1375 if (k->is_loaded()) {
1376 // See if we get an immediate positive hit
1377 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1378 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1379 __ jcc(Assembler::notEqual, *failure_target);
1380 // successful cast, fall through to profile or jump
1381 } else {
1382 // See if we get an immediate positive hit
1383 __ jcc(Assembler::equal, *success_target);
1384 // check for self
1385 __ cmpptr(klass_RInfo, k_RInfo);
1386 __ jcc(Assembler::equal, *success_target);
1387
1388 __ push(klass_RInfo);
1389 __ push(k_RInfo);
1390 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1391 __ pop(klass_RInfo);
1392 __ pop(klass_RInfo);
1393 // result is a boolean
1394 __ testl(klass_RInfo, klass_RInfo);
1395 __ jcc(Assembler::equal, *failure_target);
1396 // successful cast, fall through to profile or jump
1397 }
1398 } else {
1399 // perform the fast part of the checking logic
1400 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1401 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1402 __ push(klass_RInfo);
1403 __ push(k_RInfo);
1404 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1405 __ pop(klass_RInfo);
1406 __ pop(k_RInfo);
1407 // result is a boolean
1408 __ testl(k_RInfo, k_RInfo);
1409 __ jcc(Assembler::equal, *failure_target);
1410 // successful cast, fall through to profile or jump
1411 }
1412 }
1413 __ jmp(*success);
1414 }
1415
1416
1417 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1418 Register tmp_load_klass = rscratch1;
1419 LIR_Code code = op->code();
1420 if (code == lir_store_check) {
1421 Register value = op->object()->as_register();
1422 Register array = op->array()->as_register();
1423 Register k_RInfo = op->tmp1()->as_register();
1424 Register klass_RInfo = op->tmp2()->as_register();
1425 Register Rtmp1 = op->tmp3()->as_register();
1426
1427 CodeStub* stub = op->stub();
1428
1429 // check if it needs to be profiled
1430 ciMethodData* md = nullptr;
1431 ciProfileData* data = nullptr;
1432
1433 if (op->should_profile()) {
1434 ciMethod* method = op->profiled_method();
1435 assert(method != nullptr, "Should have method");
1436 int bci = op->profiled_bci();
1437 md = method->method_data_or_null();
1438 assert(md != nullptr, "Sanity");
1439 data = md->bci_to_data(bci);
1440 assert(data != nullptr, "need data for type check");
1441 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1442 }
1443 Label done;
1444 Label* success_target = &done;
1445 Label* failure_target = stub->entry();
1446
1447 __ testptr(value, value);
1448 if (op->should_profile()) {
1449 Label not_null;
1450 Register mdo = klass_RInfo;
1451 __ mov_metadata(mdo, md->constant_encoding());
1452 __ jccb(Assembler::notEqual, not_null);
1453 // Object is null; update MDO and exit
1454 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1455 int header_bits = BitData::null_seen_byte_constant();
1456 __ orb(data_addr, header_bits);
1457 __ jmp(done);
1458 __ bind(not_null);
1459
1460 Label update_done;
1461 Register recv = k_RInfo;
1462 __ load_klass(recv, value, tmp_load_klass);
1463 type_profile_helper(mdo, md, data, recv, &update_done);
1464
1465 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1466 __ addptr(counter_addr, DataLayout::counter_increment);
1467 __ bind(update_done);
1468 } else {
1469 __ jcc(Assembler::equal, done);
1470 }
1471
1472 add_debug_info_for_null_check_here(op->info_for_exception());
1473 __ load_klass(k_RInfo, array, tmp_load_klass);
1474 __ load_klass(klass_RInfo, value, tmp_load_klass);
1475
1476 // get instance klass (it's already uncompressed)
1477 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1478 // perform the fast part of the checking logic
1479 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1480 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1481 __ push(klass_RInfo);
1482 __ push(k_RInfo);
1483 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1484 __ pop(klass_RInfo);
1485 __ pop(k_RInfo);
1486 // result is a boolean
1487 __ testl(k_RInfo, k_RInfo);
1488 __ jcc(Assembler::equal, *failure_target);
1489 // fall through to the success case
1490
1491 __ bind(done);
1492 } else
1493 if (code == lir_checkcast) {
1494 Register obj = op->object()->as_register();
1495 Register dst = op->result_opr()->as_register();
1496 Label success;
1497 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1498 __ bind(success);
1499 if (dst != obj) {
1500 __ mov(dst, obj);
1501 }
1502 } else
1503 if (code == lir_instanceof) {
1504 Register obj = op->object()->as_register();
1505 Register dst = op->result_opr()->as_register();
1506 Label success, failure, done;
1507 emit_typecheck_helper(op, &success, &failure, &failure);
1508 __ bind(failure);
1509 __ xorptr(dst, dst);
1510 __ jmpb(done);
1511 __ bind(success);
1512 __ movptr(dst, 1);
1513 __ bind(done);
1514 } else {
1515 ShouldNotReachHere();
1516 }
1517
1518 }
1519
1520
1521 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1522 if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
1523 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1524 Register newval = op->new_value()->as_register();
1525 Register cmpval = op->cmp_value()->as_register();
1526 assert(cmpval == rax, "wrong register");
1527 assert(newval != noreg, "new val must be register");
1528 assert(cmpval != newval, "cmp and new values must be in different registers");
1529 assert(cmpval != addr, "cmp and addr must be in different registers");
1530 assert(newval != addr, "new value and addr must be in different registers");
1531
1532 if (op->code() == lir_cas_obj) {
1533 if (UseCompressedOops) {
1534 __ encode_heap_oop(cmpval);
1535 __ mov(rscratch1, newval);
1536 __ encode_heap_oop(rscratch1);
1537 __ lock();
1538 // cmpval (rax) is implicitly used by this instruction
1539 __ cmpxchgl(rscratch1, Address(addr, 0));
1540 } else {
1541 __ lock();
1542 __ cmpxchgptr(newval, Address(addr, 0));
1543 }
1544 } else {
1545 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1546 __ lock();
1547 __ cmpxchgl(newval, Address(addr, 0));
1548 }
1549 } else if (op->code() == lir_cas_long) {
1550 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1551 Register newval = op->new_value()->as_register_lo();
1552 Register cmpval = op->cmp_value()->as_register_lo();
1553 assert(cmpval == rax, "wrong register");
1554 assert(newval != noreg, "new val must be register");
1555 assert(cmpval != newval, "cmp and new values must be in different registers");
1556 assert(cmpval != addr, "cmp and addr must be in different registers");
1557 assert(newval != addr, "new value and addr must be in different registers");
1558 __ lock();
1559 __ cmpxchgq(newval, Address(addr, 0));
1560 } else {
1561 Unimplemented();
1562 }
1563 }
1564
1565 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1566 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1567 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
1568
1569 Assembler::Condition acond, ncond;
1570 switch (condition) {
1571 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1572 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1573 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1574 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1575 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1576 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1577 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1578 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1579 default: acond = Assembler::equal; ncond = Assembler::notEqual;
1580 ShouldNotReachHere();
1581 }
1582
1583 if (opr1->is_cpu_register()) {
1584 reg2reg(opr1, result);
1585 } else if (opr1->is_stack()) {
1586 stack2reg(opr1, result, result->type());
1587 } else if (opr1->is_constant()) {
1588 const2reg(opr1, result, lir_patch_none, nullptr);
1589 } else {
1590 ShouldNotReachHere();
1591 }
1592
1593 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
1594 // optimized version that does not require a branch
1595 if (opr2->is_single_cpu()) {
1596 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1597 __ cmov(ncond, result->as_register(), opr2->as_register());
1598 } else if (opr2->is_double_cpu()) {
1599 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1600 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1601 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
1602 } else if (opr2->is_single_stack()) {
1603 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
1604 } else if (opr2->is_double_stack()) {
1605 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
1606 } else {
1607 ShouldNotReachHere();
1608 }
1609
1610 } else {
1611 Label skip;
1612 __ jccb(acond, skip);
1613 if (opr2->is_cpu_register()) {
1614 reg2reg(opr2, result);
1615 } else if (opr2->is_stack()) {
1616 stack2reg(opr2, result, result->type());
1617 } else if (opr2->is_constant()) {
1618 const2reg(opr2, result, lir_patch_none, nullptr);
1619 } else {
1620 ShouldNotReachHere();
1621 }
1622 __ bind(skip);
1623 }
1624 }
1625
1626
1627 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1628 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1629
1630 if (left->is_single_cpu()) {
1631 assert(left == dest, "left and dest must be equal");
1632 Register lreg = left->as_register();
1633
1634 if (right->is_single_cpu()) {
1635 // cpu register - cpu register
1636 Register rreg = right->as_register();
1637 switch (code) {
1638 case lir_add: __ addl (lreg, rreg); break;
1639 case lir_sub: __ subl (lreg, rreg); break;
1640 case lir_mul: __ imull(lreg, rreg); break;
1641 default: ShouldNotReachHere();
1642 }
1643
1644 } else if (right->is_stack()) {
1645 // cpu register - stack
1646 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1647 switch (code) {
1648 case lir_add: __ addl(lreg, raddr); break;
1649 case lir_sub: __ subl(lreg, raddr); break;
1650 default: ShouldNotReachHere();
1651 }
1652
1653 } else if (right->is_constant()) {
1654 // cpu register - constant
1655 jint c = right->as_constant_ptr()->as_jint();
1656 switch (code) {
1657 case lir_add: {
1658 __ incrementl(lreg, c);
1659 break;
1660 }
1661 case lir_sub: {
1662 __ decrementl(lreg, c);
1663 break;
1664 }
1665 default: ShouldNotReachHere();
1666 }
1667
1668 } else {
1669 ShouldNotReachHere();
1670 }
1671
1672 } else if (left->is_double_cpu()) {
1673 assert(left == dest, "left and dest must be equal");
1674 Register lreg_lo = left->as_register_lo();
1675 Register lreg_hi = left->as_register_hi();
1676
1677 if (right->is_double_cpu()) {
1678 // cpu register - cpu register
1679 Register rreg_lo = right->as_register_lo();
1680 Register rreg_hi = right->as_register_hi();
1681 assert_different_registers(lreg_lo, rreg_lo);
1682 switch (code) {
1683 case lir_add:
1684 __ addptr(lreg_lo, rreg_lo);
1685 break;
1686 case lir_sub:
1687 __ subptr(lreg_lo, rreg_lo);
1688 break;
1689 case lir_mul:
1690 __ imulq(lreg_lo, rreg_lo);
1691 break;
1692 default:
1693 ShouldNotReachHere();
1694 }
1695
1696 } else if (right->is_constant()) {
1697 // cpu register - constant
1698 jlong c = right->as_constant_ptr()->as_jlong_bits();
1699 __ movptr(r10, (intptr_t) c);
1700 switch (code) {
1701 case lir_add:
1702 __ addptr(lreg_lo, r10);
1703 break;
1704 case lir_sub:
1705 __ subptr(lreg_lo, r10);
1706 break;
1707 default:
1708 ShouldNotReachHere();
1709 }
1710
1711 } else {
1712 ShouldNotReachHere();
1713 }
1714
1715 } else if (left->is_single_xmm()) {
1716 assert(left == dest, "left and dest must be equal");
1717 XMMRegister lreg = left->as_xmm_float_reg();
1718
1719 if (right->is_single_xmm()) {
1720 XMMRegister rreg = right->as_xmm_float_reg();
1721 switch (code) {
1722 case lir_add: __ addss(lreg, rreg); break;
1723 case lir_sub: __ subss(lreg, rreg); break;
1724 case lir_mul: __ mulss(lreg, rreg); break;
1725 case lir_div: __ divss(lreg, rreg); break;
1726 default: ShouldNotReachHere();
1727 }
1728 } else {
1729 Address raddr;
1730 if (right->is_single_stack()) {
1731 raddr = frame_map()->address_for_slot(right->single_stack_ix());
1732 } else if (right->is_constant()) {
1733 // hack for now
1734 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
1735 } else {
1736 ShouldNotReachHere();
1737 }
1738 switch (code) {
1739 case lir_add: __ addss(lreg, raddr); break;
1740 case lir_sub: __ subss(lreg, raddr); break;
1741 case lir_mul: __ mulss(lreg, raddr); break;
1742 case lir_div: __ divss(lreg, raddr); break;
1743 default: ShouldNotReachHere();
1744 }
1745 }
1746
1747 } else if (left->is_double_xmm()) {
1748 assert(left == dest, "left and dest must be equal");
1749
1750 XMMRegister lreg = left->as_xmm_double_reg();
1751 if (right->is_double_xmm()) {
1752 XMMRegister rreg = right->as_xmm_double_reg();
1753 switch (code) {
1754 case lir_add: __ addsd(lreg, rreg); break;
1755 case lir_sub: __ subsd(lreg, rreg); break;
1756 case lir_mul: __ mulsd(lreg, rreg); break;
1757 case lir_div: __ divsd(lreg, rreg); break;
1758 default: ShouldNotReachHere();
1759 }
1760 } else {
1761 Address raddr;
1762 if (right->is_double_stack()) {
1763 raddr = frame_map()->address_for_slot(right->double_stack_ix());
1764 } else if (right->is_constant()) {
1765 // hack for now
1766 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
1767 } else {
1768 ShouldNotReachHere();
1769 }
1770 switch (code) {
1771 case lir_add: __ addsd(lreg, raddr); break;
1772 case lir_sub: __ subsd(lreg, raddr); break;
1773 case lir_mul: __ mulsd(lreg, raddr); break;
1774 case lir_div: __ divsd(lreg, raddr); break;
1775 default: ShouldNotReachHere();
1776 }
1777 }
1778
1779 } else if (left->is_single_stack() || left->is_address()) {
1780 assert(left == dest, "left and dest must be equal");
1781
1782 Address laddr;
1783 if (left->is_single_stack()) {
1784 laddr = frame_map()->address_for_slot(left->single_stack_ix());
1785 } else if (left->is_address()) {
1786 laddr = as_Address(left->as_address_ptr());
1787 } else {
1788 ShouldNotReachHere();
1789 }
1790
1791 if (right->is_single_cpu()) {
1792 Register rreg = right->as_register();
1793 switch (code) {
1794 case lir_add: __ addl(laddr, rreg); break;
1795 case lir_sub: __ subl(laddr, rreg); break;
1796 default: ShouldNotReachHere();
1797 }
1798 } else if (right->is_constant()) {
1799 jint c = right->as_constant_ptr()->as_jint();
1800 switch (code) {
1801 case lir_add: {
1802 __ incrementl(laddr, c);
1803 break;
1804 }
1805 case lir_sub: {
1806 __ decrementl(laddr, c);
1807 break;
1808 }
1809 default: ShouldNotReachHere();
1810 }
1811 } else {
1812 ShouldNotReachHere();
1813 }
1814
1815 } else {
1816 ShouldNotReachHere();
1817 }
1818 }
1819
1820
1821 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1822 if (value->is_double_xmm()) {
1823 switch(code) {
1824 case lir_abs :
1825 {
1826 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
1827 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
1828 }
1829 assert(!tmp->is_valid(), "do not need temporary");
1830 __ andpd(dest->as_xmm_double_reg(),
1831 ExternalAddress((address)double_signmask_pool),
1832 rscratch1);
1833 }
1834 break;
1835
1836 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
1837 // all other intrinsics are not available in the SSE instruction set, so FPU is used
1838 default : ShouldNotReachHere();
1839 }
1840
1841 } else if (code == lir_f2hf) {
1842 __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg());
1843 } else if (code == lir_hf2f) {
1844 __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register());
1845 } else {
1846 Unimplemented();
1847 }
1848 }
1849
1850 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1851 // assert(left->destroys_register(), "check");
1852 if (left->is_single_cpu()) {
1853 Register reg = left->as_register();
1854 if (right->is_constant()) {
1855 int val = right->as_constant_ptr()->as_jint();
1856 switch (code) {
1857 case lir_logic_and: __ andl (reg, val); break;
1858 case lir_logic_or: __ orl (reg, val); break;
1859 case lir_logic_xor: __ xorl (reg, val); break;
1860 default: ShouldNotReachHere();
1861 }
1862 } else if (right->is_stack()) {
1863 // added support for stack operands
1864 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1865 switch (code) {
1866 case lir_logic_and: __ andl (reg, raddr); break;
1867 case lir_logic_or: __ orl (reg, raddr); break;
1868 case lir_logic_xor: __ xorl (reg, raddr); break;
1869 default: ShouldNotReachHere();
1870 }
1871 } else {
1872 Register rright = right->as_register();
1873 switch (code) {
1874 case lir_logic_and: __ andptr (reg, rright); break;
1875 case lir_logic_or : __ orptr (reg, rright); break;
1876 case lir_logic_xor: __ xorptr (reg, rright); break;
1877 default: ShouldNotReachHere();
1878 }
1879 }
1880 move_regs(reg, dst->as_register());
1881 } else {
1882 Register l_lo = left->as_register_lo();
1883 Register l_hi = left->as_register_hi();
1884 if (right->is_constant()) {
1885 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
1886 switch (code) {
1887 case lir_logic_and:
1888 __ andq(l_lo, rscratch1);
1889 break;
1890 case lir_logic_or:
1891 __ orq(l_lo, rscratch1);
1892 break;
1893 case lir_logic_xor:
1894 __ xorq(l_lo, rscratch1);
1895 break;
1896 default: ShouldNotReachHere();
1897 }
1898 } else {
1899 Register r_lo;
1900 if (is_reference_type(right->type())) {
1901 r_lo = right->as_register();
1902 } else {
1903 r_lo = right->as_register_lo();
1904 }
1905 switch (code) {
1906 case lir_logic_and:
1907 __ andptr(l_lo, r_lo);
1908 break;
1909 case lir_logic_or:
1910 __ orptr(l_lo, r_lo);
1911 break;
1912 case lir_logic_xor:
1913 __ xorptr(l_lo, r_lo);
1914 break;
1915 default: ShouldNotReachHere();
1916 }
1917 }
1918
1919 Register dst_lo = dst->as_register_lo();
1920 Register dst_hi = dst->as_register_hi();
1921
1922 move_regs(l_lo, dst_lo);
1923 }
1924 }
1925
1926
1927 // we assume that rax, and rdx can be overwritten
1928 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
1929
1930 assert(left->is_single_cpu(), "left must be register");
1931 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1932 assert(result->is_single_cpu(), "result must be register");
1933
1934 // assert(left->destroys_register(), "check");
1935 // assert(right->destroys_register(), "check");
1936
1937 Register lreg = left->as_register();
1938 Register dreg = result->as_register();
1939
1940 if (right->is_constant()) {
1941 jint divisor = right->as_constant_ptr()->as_jint();
1942 assert(divisor > 0 && is_power_of_2(divisor), "must be");
1943 if (code == lir_idiv) {
1944 assert(lreg == rax, "must be rax,");
1945 assert(temp->as_register() == rdx, "tmp register must be rdx");
1946 __ cdql(); // sign extend into rdx:rax
1947 if (divisor == 2) {
1948 __ subl(lreg, rdx);
1949 } else {
1950 __ andl(rdx, divisor - 1);
1951 __ addl(lreg, rdx);
1952 }
1953 __ sarl(lreg, log2i_exact(divisor));
1954 move_regs(lreg, dreg);
1955 } else if (code == lir_irem) {
1956 Label done;
1957 __ mov(dreg, lreg);
1958 __ andl(dreg, 0x80000000 | (divisor - 1));
1959 __ jcc(Assembler::positive, done);
1960 __ decrement(dreg);
1961 __ orl(dreg, ~(divisor - 1));
1962 __ increment(dreg);
1963 __ bind(done);
1964 } else {
1965 ShouldNotReachHere();
1966 }
1967 } else {
1968 Register rreg = right->as_register();
1969 assert(lreg == rax, "left register must be rax,");
1970 assert(rreg != rdx, "right register must not be rdx");
1971 assert(temp->as_register() == rdx, "tmp register must be rdx");
1972
1973 move_regs(lreg, rax);
1974
1975 int idivl_offset = __ corrected_idivl(rreg);
1976 if (ImplicitDiv0Checks) {
1977 add_debug_info_for_div0(idivl_offset, info);
1978 }
1979 if (code == lir_irem) {
1980 move_regs(rdx, dreg); // result is in rdx
1981 } else {
1982 move_regs(rax, dreg);
1983 }
1984 }
1985 }
1986
1987
1988 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1989 if (opr1->is_single_cpu()) {
1990 Register reg1 = opr1->as_register();
1991 if (opr2->is_single_cpu()) {
1992 // cpu register - cpu register
1993 if (is_reference_type(opr1->type())) {
1994 __ cmpoop(reg1, opr2->as_register());
1995 } else {
1996 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1997 __ cmpl(reg1, opr2->as_register());
1998 }
1999 } else if (opr2->is_stack()) {
2000 // cpu register - stack
2001 if (is_reference_type(opr1->type())) {
2002 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2003 } else {
2004 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2005 }
2006 } else if (opr2->is_constant()) {
2007 // cpu register - constant
2008 LIR_Const* c = opr2->as_constant_ptr();
2009 if (c->type() == T_INT) {
2010 jint i = c->as_jint();
2011 if (i == 0) {
2012 __ testl(reg1, reg1);
2013 } else {
2014 __ cmpl(reg1, i);
2015 }
2016 } else if (c->type() == T_METADATA) {
2017 // All we need for now is a comparison with null for equality.
2018 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2019 Metadata* m = c->as_metadata();
2020 if (m == nullptr) {
2021 __ testptr(reg1, reg1);
2022 } else {
2023 ShouldNotReachHere();
2024 }
2025 } else if (is_reference_type(c->type())) {
2026 // In 64bit oops are single register
2027 jobject o = c->as_jobject();
2028 if (o == nullptr) {
2029 __ testptr(reg1, reg1);
2030 } else {
2031 __ cmpoop(reg1, o, rscratch1);
2032 }
2033 } else {
2034 fatal("unexpected type: %s", basictype_to_str(c->type()));
2035 }
2036 // cpu register - address
2037 } else if (opr2->is_address()) {
2038 if (op->info() != nullptr) {
2039 add_debug_info_for_null_check_here(op->info());
2040 }
2041 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2042 } else {
2043 ShouldNotReachHere();
2044 }
2045
2046 } else if(opr1->is_double_cpu()) {
2047 Register xlo = opr1->as_register_lo();
2048 Register xhi = opr1->as_register_hi();
2049 if (opr2->is_double_cpu()) {
2050 __ cmpptr(xlo, opr2->as_register_lo());
2051 } else if (opr2->is_constant()) {
2052 // cpu register - constant 0
2053 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2054 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2055 } else {
2056 ShouldNotReachHere();
2057 }
2058
2059 } else if (opr1->is_single_xmm()) {
2060 XMMRegister reg1 = opr1->as_xmm_float_reg();
2061 if (opr2->is_single_xmm()) {
2062 // xmm register - xmm register
2063 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2064 } else if (opr2->is_stack()) {
2065 // xmm register - stack
2066 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2067 } else if (opr2->is_constant()) {
2068 // xmm register - constant
2069 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2070 } else if (opr2->is_address()) {
2071 // xmm register - address
2072 if (op->info() != nullptr) {
2073 add_debug_info_for_null_check_here(op->info());
2074 }
2075 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2076 } else {
2077 ShouldNotReachHere();
2078 }
2079
2080 } else if (opr1->is_double_xmm()) {
2081 XMMRegister reg1 = opr1->as_xmm_double_reg();
2082 if (opr2->is_double_xmm()) {
2083 // xmm register - xmm register
2084 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2085 } else if (opr2->is_stack()) {
2086 // xmm register - stack
2087 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2088 } else if (opr2->is_constant()) {
2089 // xmm register - constant
2090 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2091 } else if (opr2->is_address()) {
2092 // xmm register - address
2093 if (op->info() != nullptr) {
2094 add_debug_info_for_null_check_here(op->info());
2095 }
2096 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2097 } else {
2098 ShouldNotReachHere();
2099 }
2100
2101 } else if (opr1->is_address() && opr2->is_constant()) {
2102 LIR_Const* c = opr2->as_constant_ptr();
2103 if (is_reference_type(c->type())) {
2104 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2105 __ movoop(rscratch1, c->as_jobject());
2106 }
2107 if (op->info() != nullptr) {
2108 add_debug_info_for_null_check_here(op->info());
2109 }
2110 // special case: address - constant
2111 LIR_Address* addr = opr1->as_address_ptr();
2112 if (c->type() == T_INT) {
2113 __ cmpl(as_Address(addr), c->as_jint());
2114 } else if (is_reference_type(c->type())) {
2115 // %%% Make this explode if addr isn't reachable until we figure out a
2116 // better strategy by giving noreg as the temp for as_Address
2117 __ cmpoop(rscratch1, as_Address(addr, noreg));
2118 } else {
2119 ShouldNotReachHere();
2120 }
2121
2122 } else {
2123 ShouldNotReachHere();
2124 }
2125 }
2126
2127 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2128 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2129 if (left->is_single_xmm()) {
2130 assert(right->is_single_xmm(), "must match");
2131 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2132 } else if (left->is_double_xmm()) {
2133 assert(right->is_double_xmm(), "must match");
2134 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2135
2136 } else {
2137 ShouldNotReachHere();
2138 }
2139 } else {
2140 assert(code == lir_cmp_l2i, "check");
2141 Label done;
2142 Register dest = dst->as_register();
2143 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2144 __ movl(dest, -1);
2145 __ jccb(Assembler::less, done);
2146 __ setb(Assembler::notZero, dest);
2147 __ movzbl(dest, dest);
2148 __ bind(done);
2149 }
2150 }
2151
2152
2153 void LIR_Assembler::align_call(LIR_Code code) {
2154 // make sure that the displacement word of the call ends up word aligned
2155 int offset = __ offset();
2156 switch (code) {
2157 case lir_static_call:
2158 case lir_optvirtual_call:
2159 case lir_dynamic_call:
2160 offset += NativeCall::displacement_offset;
2161 break;
2162 case lir_icvirtual_call:
2163 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size_rex;
2164 break;
2165 default: ShouldNotReachHere();
2166 }
2167 __ align(BytesPerWord, offset);
2168 }
2169
2170
2171 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2172 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2173 "must be aligned");
2174 __ call(AddressLiteral(op->addr(), rtype));
2175 add_call_info(code_offset(), op->info());
2176 __ post_call_nop();
2177 }
2178
2179
2180 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2181 __ ic_call(op->addr());
2182 add_call_info(code_offset(), op->info());
2183 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2184 "must be aligned");
2185 __ post_call_nop();
2186 }
2187
2188
2189 void LIR_Assembler::emit_static_call_stub() {
2190 address call_pc = __ pc();
2191 address stub = __ start_a_stub(call_stub_size());
2192 if (stub == nullptr) {
2193 bailout("static call stub overflow");
2194 return;
2195 }
2196
2197 int start = __ offset();
2198
2199 // make sure that the displacement word of the call ends up word aligned
2200 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size_rex + NativeCall::displacement_offset);
2201 __ relocate(static_stub_Relocation::spec(call_pc));
2202 __ mov_metadata(rbx, (Metadata*)nullptr);
2203 // must be set to -1 at code generation time
2204 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2205 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2206 __ jump(RuntimeAddress(__ pc()));
2207
2208 assert(__ offset() - start <= call_stub_size(), "stub too big");
2209 __ end_a_stub();
2210 }
2211
2212
2213 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2214 assert(exceptionOop->as_register() == rax, "must match");
2215 assert(exceptionPC->as_register() == rdx, "must match");
2216
2217 // exception object is not added to oop map by LinearScan
2218 // (LinearScan assumes that no oops are in fixed registers)
2219 info->add_register_oop(exceptionOop);
2220 C1StubId unwind_id;
2221
2222 // get current pc information
2223 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2224 int pc_for_athrow_offset = __ offset();
2225 InternalAddress pc_for_athrow(__ pc());
2226 __ lea(exceptionPC->as_register(), pc_for_athrow);
2227 add_call_info(pc_for_athrow_offset, info); // for exception handler
2228
2229 __ verify_not_null_oop(rax);
2230 // search an exception handler (rax: exception oop, rdx: throwing pc)
2231 if (compilation()->has_fpu_code()) {
2232 unwind_id = C1StubId::handle_exception_id;
2233 } else {
2234 unwind_id = C1StubId::handle_exception_nofpu_id;
2235 }
2236 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2237
2238 // enough room for two byte trap
2239 __ nop();
2240 }
2241
2242
2243 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2244 assert(exceptionOop->as_register() == rax, "must match");
2245
2246 __ jmp(_unwind_handler_entry);
2247 }
2248
2249
2250 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2251
2252 // optimized version for linear scan:
2253 // * count must be already in ECX (guaranteed by LinearScan)
2254 // * left and dest must be equal
2255 // * tmp must be unused
2256 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2257 assert(left == dest, "left and dest must be equal");
2258 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2259
2260 if (left->is_single_cpu()) {
2261 Register value = left->as_register();
2262 assert(value != SHIFT_count, "left cannot be ECX");
2263
2264 switch (code) {
2265 case lir_shl: __ shll(value); break;
2266 case lir_shr: __ sarl(value); break;
2267 case lir_ushr: __ shrl(value); break;
2268 default: ShouldNotReachHere();
2269 }
2270 } else if (left->is_double_cpu()) {
2271 Register lo = left->as_register_lo();
2272 Register hi = left->as_register_hi();
2273 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2274 switch (code) {
2275 case lir_shl: __ shlptr(lo); break;
2276 case lir_shr: __ sarptr(lo); break;
2277 case lir_ushr: __ shrptr(lo); break;
2278 default: ShouldNotReachHere();
2279 }
2280 } else {
2281 ShouldNotReachHere();
2282 }
2283 }
2284
2285
2286 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2287 if (dest->is_single_cpu()) {
2288 // first move left into dest so that left is not destroyed by the shift
2289 Register value = dest->as_register();
2290 count = count & 0x1F; // Java spec
2291
2292 move_regs(left->as_register(), value);
2293 switch (code) {
2294 case lir_shl: __ shll(value, count); break;
2295 case lir_shr: __ sarl(value, count); break;
2296 case lir_ushr: __ shrl(value, count); break;
2297 default: ShouldNotReachHere();
2298 }
2299 } else if (dest->is_double_cpu()) {
2300 // first move left into dest so that left is not destroyed by the shift
2301 Register value = dest->as_register_lo();
2302 count = count & 0x1F; // Java spec
2303
2304 move_regs(left->as_register_lo(), value);
2305 switch (code) {
2306 case lir_shl: __ shlptr(value, count); break;
2307 case lir_shr: __ sarptr(value, count); break;
2308 case lir_ushr: __ shrptr(value, count); break;
2309 default: ShouldNotReachHere();
2310 }
2311 } else {
2312 ShouldNotReachHere();
2313 }
2314 }
2315
2316
2317 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2318 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2319 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2320 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2321 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
2322 }
2323
2324
2325 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2326 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2327 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2328 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2329 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
2330 }
2331
2332
2333 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2334 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2335 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2336 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2337 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1);
2338 }
2339
2340
2341 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
2342 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2343 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2344 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2345 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1);
2346 }
2347
2348
2349 // This code replaces a call to arraycopy; no exception may
2350 // be thrown in this code, they must be thrown in the System.arraycopy
2351 // activation frame; we could save some checks if this would not be the case
2352 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2353 ciArrayKlass* default_type = op->expected_type();
2354 Register src = op->src()->as_register();
2355 Register dst = op->dst()->as_register();
2356 Register src_pos = op->src_pos()->as_register();
2357 Register dst_pos = op->dst_pos()->as_register();
2358 Register length = op->length()->as_register();
2359 Register tmp = op->tmp()->as_register();
2360 Register tmp_load_klass = rscratch1;
2361 Register tmp2 = UseCompactObjectHeaders ? rscratch2 : noreg;
2362
2363 CodeStub* stub = op->stub();
2364 int flags = op->flags();
2365 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2366 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2367
2368 // if we don't know anything, just go through the generic arraycopy
2369 if (default_type == nullptr) {
2370 // save outgoing arguments on stack in case call to System.arraycopy is needed
2371 // HACK ALERT. This code used to push the parameters in a hardwired fashion
2372 // for interpreter calling conventions. Now we have to do it in new style conventions.
2373 // For the moment until C1 gets the new register allocator I just force all the
2374 // args to the right place (except the register args) and then on the back side
2375 // reload the register args properly if we go slow path. Yuck
2376
2377 // These are proper for the calling convention
2378 store_parameter(length, 2);
2379 store_parameter(dst_pos, 1);
2380 store_parameter(dst, 0);
2381
2382 // these are just temporary placements until we need to reload
2383 store_parameter(src_pos, 3);
2384 store_parameter(src, 4);
2385
2386 address copyfunc_addr = StubRoutines::generic_arraycopy();
2387 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2388
2389 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
2390 // The arguments are in java calling convention so we can trivially shift them to C
2391 // convention
2392 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2393 __ mov(c_rarg0, j_rarg0);
2394 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2395 __ mov(c_rarg1, j_rarg1);
2396 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2397 __ mov(c_rarg2, j_rarg2);
2398 assert_different_registers(c_rarg3, j_rarg4);
2399 __ mov(c_rarg3, j_rarg3);
2400 #ifdef _WIN64
2401 // Allocate abi space for args but be sure to keep stack aligned
2402 __ subptr(rsp, 6*wordSize);
2403 store_parameter(j_rarg4, 4);
2404 #ifndef PRODUCT
2405 if (PrintC1Statistics) {
2406 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
2407 }
2408 #endif
2409 __ call(RuntimeAddress(copyfunc_addr));
2410 __ addptr(rsp, 6*wordSize);
2411 #else
2412 __ mov(c_rarg4, j_rarg4);
2413 #ifndef PRODUCT
2414 if (PrintC1Statistics) {
2415 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
2416 }
2417 #endif
2418 __ call(RuntimeAddress(copyfunc_addr));
2419 #endif // _WIN64
2420
2421 __ testl(rax, rax);
2422 __ jcc(Assembler::equal, *stub->continuation());
2423
2424 __ mov(tmp, rax);
2425 __ xorl(tmp, -1);
2426
2427 // Reload values from the stack so they are where the stub
2428 // expects them.
2429 __ movptr (dst, Address(rsp, 0*BytesPerWord));
2430 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
2431 __ movptr (length, Address(rsp, 2*BytesPerWord));
2432 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
2433 __ movptr (src, Address(rsp, 4*BytesPerWord));
2434
2435 __ subl(length, tmp);
2436 __ addl(src_pos, tmp);
2437 __ addl(dst_pos, tmp);
2438 __ jmp(*stub->entry());
2439
2440 __ bind(*stub->continuation());
2441 return;
2442 }
2443
2444 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2445
2446 int elem_size = type2aelembytes(basic_type);
2447 Address::ScaleFactor scale;
2448
2449 switch (elem_size) {
2450 case 1 :
2451 scale = Address::times_1;
2452 break;
2453 case 2 :
2454 scale = Address::times_2;
2455 break;
2456 case 4 :
2457 scale = Address::times_4;
2458 break;
2459 case 8 :
2460 scale = Address::times_8;
2461 break;
2462 default:
2463 scale = Address::no_scale;
2464 ShouldNotReachHere();
2465 }
2466
2467 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2468 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2469
2470 // length and pos's are all sign extended at this point on 64bit
2471
2472 // test for null
2473 if (flags & LIR_OpArrayCopy::src_null_check) {
2474 __ testptr(src, src);
2475 __ jcc(Assembler::zero, *stub->entry());
2476 }
2477 if (flags & LIR_OpArrayCopy::dst_null_check) {
2478 __ testptr(dst, dst);
2479 __ jcc(Assembler::zero, *stub->entry());
2480 }
2481
2482 // If the compiler was not able to prove that exact type of the source or the destination
2483 // of the arraycopy is an array type, check at runtime if the source or the destination is
2484 // an instance type.
2485 if (flags & LIR_OpArrayCopy::type_check) {
2486 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2487 __ load_klass(tmp, dst, tmp_load_klass);
2488 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
2489 __ jcc(Assembler::greaterEqual, *stub->entry());
2490 }
2491
2492 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2493 __ load_klass(tmp, src, tmp_load_klass);
2494 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
2495 __ jcc(Assembler::greaterEqual, *stub->entry());
2496 }
2497 }
2498
2499 // check if negative
2500 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2501 __ testl(src_pos, src_pos);
2502 __ jcc(Assembler::less, *stub->entry());
2503 }
2504 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2505 __ testl(dst_pos, dst_pos);
2506 __ jcc(Assembler::less, *stub->entry());
2507 }
2508
2509 if (flags & LIR_OpArrayCopy::src_range_check) {
2510 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
2511 __ cmpl(tmp, src_length_addr);
2512 __ jcc(Assembler::above, *stub->entry());
2513 }
2514 if (flags & LIR_OpArrayCopy::dst_range_check) {
2515 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
2516 __ cmpl(tmp, dst_length_addr);
2517 __ jcc(Assembler::above, *stub->entry());
2518 }
2519
2520 if (flags & LIR_OpArrayCopy::length_positive_check) {
2521 __ testl(length, length);
2522 __ jcc(Assembler::less, *stub->entry());
2523 }
2524
2525 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
2526 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
2527
2528 if (flags & LIR_OpArrayCopy::type_check) {
2529 // We don't know the array types are compatible
2530 if (basic_type != T_OBJECT) {
2531 // Simple test for basic type arrays
2532 __ cmp_klasses_from_objects(src, dst, tmp, tmp2);
2533 __ jcc(Assembler::notEqual, *stub->entry());
2534 } else {
2535 // For object arrays, if src is a sub class of dst then we can
2536 // safely do the copy.
2537 Label cont, slow;
2538
2539 __ push(src);
2540 __ push(dst);
2541
2542 __ load_klass(src, src, tmp_load_klass);
2543 __ load_klass(dst, dst, tmp_load_klass);
2544
2545 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2546
2547 __ push(src);
2548 __ push(dst);
2549 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
2550 __ pop(dst);
2551 __ pop(src);
2552
2553 __ testl(src, src);
2554 __ jcc(Assembler::notEqual, cont);
2555
2556 __ bind(slow);
2557 __ pop(dst);
2558 __ pop(src);
2559
2560 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2561 if (copyfunc_addr != nullptr) { // use stub if available
2562 // src is not a sub class of dst so we have to do a
2563 // per-element check.
2564
2565 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2566 if ((flags & mask) != mask) {
2567 // Check that at least both of them object arrays.
2568 assert(flags & mask, "one of the two should be known to be an object array");
2569
2570 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2571 __ load_klass(tmp, src, tmp_load_klass);
2572 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2573 __ load_klass(tmp, dst, tmp_load_klass);
2574 }
2575 int lh_offset = in_bytes(Klass::layout_helper_offset());
2576 Address klass_lh_addr(tmp, lh_offset);
2577 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2578 __ cmpl(klass_lh_addr, objArray_lh);
2579 __ jcc(Assembler::notEqual, *stub->entry());
2580 }
2581
2582 // Spill because stubs can use any register they like and it's
2583 // easier to restore just those that we care about.
2584 store_parameter(dst, 0);
2585 store_parameter(dst_pos, 1);
2586 store_parameter(length, 2);
2587 store_parameter(src_pos, 3);
2588 store_parameter(src, 4);
2589
2590 __ movl2ptr(length, length); //higher 32bits must be null
2591
2592 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
2593 assert_different_registers(c_rarg0, dst, dst_pos, length);
2594 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
2595 assert_different_registers(c_rarg1, dst, length);
2596
2597 __ mov(c_rarg2, length);
2598 assert_different_registers(c_rarg2, dst);
2599
2600 #ifdef _WIN64
2601 // Allocate abi space for args but be sure to keep stack aligned
2602 __ subptr(rsp, 6*wordSize);
2603 __ load_klass(c_rarg3, dst, tmp_load_klass);
2604 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
2605 store_parameter(c_rarg3, 4);
2606 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
2607 __ call(RuntimeAddress(copyfunc_addr));
2608 __ addptr(rsp, 6*wordSize);
2609 #else
2610 __ load_klass(c_rarg4, dst, tmp_load_klass);
2611 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2612 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2613 __ call(RuntimeAddress(copyfunc_addr));
2614 #endif
2615
2616 #ifndef PRODUCT
2617 if (PrintC1Statistics) {
2618 Label failed;
2619 __ testl(rax, rax);
2620 __ jcc(Assembler::notZero, failed);
2621 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1);
2622 __ bind(failed);
2623 }
2624 #endif
2625
2626 __ testl(rax, rax);
2627 __ jcc(Assembler::zero, *stub->continuation());
2628
2629 #ifndef PRODUCT
2630 if (PrintC1Statistics) {
2631 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1);
2632 }
2633 #endif
2634
2635 __ mov(tmp, rax);
2636
2637 __ xorl(tmp, -1);
2638
2639 // Restore previously spilled arguments
2640 __ movptr (dst, Address(rsp, 0*BytesPerWord));
2641 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
2642 __ movptr (length, Address(rsp, 2*BytesPerWord));
2643 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
2644 __ movptr (src, Address(rsp, 4*BytesPerWord));
2645
2646
2647 __ subl(length, tmp);
2648 __ addl(src_pos, tmp);
2649 __ addl(dst_pos, tmp);
2650 }
2651
2652 __ jmp(*stub->entry());
2653
2654 __ bind(cont);
2655 __ pop(dst);
2656 __ pop(src);
2657 }
2658 }
2659
2660 #ifdef ASSERT
2661 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2662 // Sanity check the known type with the incoming class. For the
2663 // primitive case the types must match exactly with src.klass and
2664 // dst.klass each exactly matching the default type. For the
2665 // object array case, if no type check is needed then either the
2666 // dst type is exactly the expected type and the src type is a
2667 // subtype which we can't check or src is the same array as dst
2668 // but not necessarily exactly of type default_type.
2669 Label known_ok, halt;
2670 __ mov_metadata(tmp, default_type->constant_encoding());
2671 if (UseCompressedClassPointers) {
2672 __ encode_klass_not_null(tmp, rscratch1);
2673 }
2674
2675 if (basic_type != T_OBJECT) {
2676 __ cmp_klass(tmp, dst, tmp2);
2677 __ jcc(Assembler::notEqual, halt);
2678 __ cmp_klass(tmp, src, tmp2);
2679 __ jcc(Assembler::equal, known_ok);
2680 } else {
2681 __ cmp_klass(tmp, dst, tmp2);
2682 __ jcc(Assembler::equal, known_ok);
2683 __ cmpptr(src, dst);
2684 __ jcc(Assembler::equal, known_ok);
2685 }
2686 __ bind(halt);
2687 __ stop("incorrect type information in arraycopy");
2688 __ bind(known_ok);
2689 }
2690 #endif
2691
2692 #ifndef PRODUCT
2693 if (PrintC1Statistics) {
2694 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1);
2695 }
2696 #endif
2697
2698 assert_different_registers(c_rarg0, dst, dst_pos, length);
2699 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
2700 assert_different_registers(c_rarg1, length);
2701 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
2702 __ mov(c_rarg2, length);
2703
2704 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2705 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2706 const char *name;
2707 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2708 __ call_VM_leaf(entry, 0);
2709
2710 if (stub != nullptr) {
2711 __ bind(*stub->continuation());
2712 }
2713 }
2714
2715 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2716 assert(op->crc()->is_single_cpu(), "crc must be register");
2717 assert(op->val()->is_single_cpu(), "byte value must be register");
2718 assert(op->result_opr()->is_single_cpu(), "result must be register");
2719 Register crc = op->crc()->as_register();
2720 Register val = op->val()->as_register();
2721 Register res = op->result_opr()->as_register();
2722
2723 assert_different_registers(val, crc, res);
2724
2725 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
2726 __ notl(crc); // ~crc
2727 __ update_byte_crc32(crc, val, res);
2728 __ notl(crc); // ~crc
2729 __ mov(res, crc);
2730 }
2731
2732 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2733 Register obj = op->obj_opr()->as_register(); // may not be an oop
2734 Register hdr = op->hdr_opr()->as_register();
2735 Register lock = op->lock_opr()->as_register();
2736 if (LockingMode == LM_MONITOR) {
2737 if (op->info() != nullptr) {
2738 add_debug_info_for_null_check_here(op->info());
2739 __ null_check(obj);
2740 }
2741 __ jmp(*op->stub()->entry());
2742 } else if (op->code() == lir_lock) {
2743 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2744 Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg;
2745 // add debug info for NullPointerException only if one is possible
2746 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
2747 if (op->info() != nullptr) {
2748 add_debug_info_for_null_check(null_check_offset, op->info());
2749 }
2750 // done
2751 } else if (op->code() == lir_unlock) {
2752 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2753 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2754 } else {
2755 Unimplemented();
2756 }
2757 __ bind(*op->stub()->continuation());
2758 }
2759
2760 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2761 Register obj = op->obj()->as_pointer_register();
2762 Register result = op->result_opr()->as_pointer_register();
2763
2764 CodeEmitInfo* info = op->info();
2765 if (info != nullptr) {
2766 add_debug_info_for_null_check_here(info);
2767 }
2768
2769 __ load_klass(result, obj, rscratch1);
2770 }
2771
2772 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2773 ciMethod* method = op->profiled_method();
2774 int bci = op->profiled_bci();
2775 ciMethod* callee = op->profiled_callee();
2776 Register tmp_load_klass = rscratch1;
2777
2778 // Update counter for all call types
2779 ciMethodData* md = method->method_data_or_null();
2780 assert(md != nullptr, "Sanity");
2781 ciProfileData* data = md->bci_to_data(bci);
2782 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2783 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2784 Register mdo = op->mdo()->as_register();
2785 __ mov_metadata(mdo, md->constant_encoding());
2786 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2787 // Perform additional virtual call profiling for invokevirtual and
2788 // invokeinterface bytecodes
2789 if (op->should_profile_receiver_type()) {
2790 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2791 Register recv = op->recv()->as_register();
2792 assert_different_registers(mdo, recv);
2793 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2794 ciKlass* known_klass = op->known_holder();
2795 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2796 // We know the type that will be seen at this call site; we can
2797 // statically update the MethodData* rather than needing to do
2798 // dynamic tests on the receiver type
2799
2800 // NOTE: we should probably put a lock around this search to
2801 // avoid collisions by concurrent compilations
2802 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2803 uint i;
2804 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2805 ciKlass* receiver = vc_data->receiver(i);
2806 if (known_klass->equals(receiver)) {
2807 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2808 __ addptr(data_addr, DataLayout::counter_increment);
2809 return;
2810 }
2811 }
2812
2813 // Receiver type not found in profile data; select an empty slot
2814
2815 // Note that this is less efficient than it should be because it
2816 // always does a write to the receiver part of the
2817 // VirtualCallData rather than just the first time
2818 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2819 ciKlass* receiver = vc_data->receiver(i);
2820 if (receiver == nullptr) {
2821 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2822 __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1);
2823 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2824 __ addptr(data_addr, DataLayout::counter_increment);
2825 return;
2826 }
2827 }
2828 } else {
2829 __ load_klass(recv, recv, tmp_load_klass);
2830 Label update_done;
2831 type_profile_helper(mdo, md, data, recv, &update_done);
2832 // Receiver did not match any saved receiver and there is no empty row for it.
2833 // Increment total counter to indicate polymorphic case.
2834 __ addptr(counter_addr, DataLayout::counter_increment);
2835
2836 __ bind(update_done);
2837 }
2838 } else {
2839 // Static call
2840 __ addptr(counter_addr, DataLayout::counter_increment);
2841 }
2842 }
2843
2844 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2845 Register obj = op->obj()->as_register();
2846 Register tmp = op->tmp()->as_pointer_register();
2847 Register tmp_load_klass = rscratch1;
2848 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2849 ciKlass* exact_klass = op->exact_klass();
2850 intptr_t current_klass = op->current_klass();
2851 bool not_null = op->not_null();
2852 bool no_conflict = op->no_conflict();
2853
2854 Label update, next, none;
2855
2856 bool do_null = !not_null;
2857 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2858 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2859
2860 assert(do_null || do_update, "why are we here?");
2861 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2862
2863 __ verify_oop(obj);
2864
2865 #ifdef ASSERT
2866 if (obj == tmp) {
2867 assert_different_registers(obj, rscratch1, mdo_addr.base(), mdo_addr.index());
2868 } else {
2869 assert_different_registers(obj, tmp, rscratch1, mdo_addr.base(), mdo_addr.index());
2870 }
2871 #endif
2872 if (do_null) {
2873 __ testptr(obj, obj);
2874 __ jccb(Assembler::notZero, update);
2875 if (!TypeEntries::was_null_seen(current_klass)) {
2876 __ testptr(mdo_addr, TypeEntries::null_seen);
2877 #ifndef ASSERT
2878 __ jccb(Assembler::notZero, next); // already set
2879 #else
2880 __ jcc(Assembler::notZero, next); // already set
2881 #endif
2882 // atomic update to prevent overwriting Klass* with 0
2883 __ lock();
2884 __ orptr(mdo_addr, TypeEntries::null_seen);
2885 }
2886 if (do_update) {
2887 #ifndef ASSERT
2888 __ jmpb(next);
2889 }
2890 #else
2891 __ jmp(next);
2892 }
2893 } else {
2894 __ testptr(obj, obj);
2895 __ jcc(Assembler::notZero, update);
2896 __ stop("unexpected null obj");
2897 #endif
2898 }
2899
2900 __ bind(update);
2901
2902 if (do_update) {
2903 #ifdef ASSERT
2904 if (exact_klass != nullptr) {
2905 Label ok;
2906 __ load_klass(tmp, obj, tmp_load_klass);
2907 __ push(tmp);
2908 __ mov_metadata(tmp, exact_klass->constant_encoding());
2909 __ cmpptr(tmp, Address(rsp, 0));
2910 __ jcc(Assembler::equal, ok);
2911 __ stop("exact klass and actual klass differ");
2912 __ bind(ok);
2913 __ pop(tmp);
2914 }
2915 #endif
2916 if (!no_conflict) {
2917 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2918 if (exact_klass != nullptr) {
2919 __ mov_metadata(tmp, exact_klass->constant_encoding());
2920 } else {
2921 __ load_klass(tmp, obj, tmp_load_klass);
2922 }
2923 __ mov(rscratch1, tmp); // save original value before XOR
2924 __ xorptr(tmp, mdo_addr);
2925 __ testptr(tmp, TypeEntries::type_klass_mask);
2926 // klass seen before, nothing to do. The unknown bit may have been
2927 // set already but no need to check.
2928 __ jccb(Assembler::zero, next);
2929
2930 __ testptr(tmp, TypeEntries::type_unknown);
2931 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
2932
2933 if (TypeEntries::is_type_none(current_klass)) {
2934 __ testptr(mdo_addr, TypeEntries::type_mask);
2935 __ jccb(Assembler::zero, none);
2936 // There is a chance that the checks above (re-reading profiling
2937 // data from memory) fail if another thread has just set the
2938 // profiling to this obj's klass
2939 __ mov(tmp, rscratch1); // get back original value before XOR
2940 __ xorptr(tmp, mdo_addr);
2941 __ testptr(tmp, TypeEntries::type_klass_mask);
2942 __ jccb(Assembler::zero, next);
2943 }
2944 } else {
2945 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2946 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2947
2948 __ testptr(mdo_addr, TypeEntries::type_unknown);
2949 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
2950 }
2951
2952 // different than before. Cannot keep accurate profile.
2953 __ orptr(mdo_addr, TypeEntries::type_unknown);
2954
2955 if (TypeEntries::is_type_none(current_klass)) {
2956 __ jmpb(next);
2957
2958 __ bind(none);
2959 // first time here. Set profile type.
2960 __ movptr(mdo_addr, tmp);
2961 #ifdef ASSERT
2962 __ andptr(tmp, TypeEntries::type_klass_mask);
2963 __ verify_klass_ptr(tmp);
2964 #endif
2965 }
2966 } else {
2967 // There's a single possible klass at this profile point
2968 assert(exact_klass != nullptr, "should be");
2969 if (TypeEntries::is_type_none(current_klass)) {
2970 __ mov_metadata(tmp, exact_klass->constant_encoding());
2971 __ xorptr(tmp, mdo_addr);
2972 __ testptr(tmp, TypeEntries::type_klass_mask);
2973 #ifdef ASSERT
2974 __ jcc(Assembler::zero, next);
2975
2976 {
2977 Label ok;
2978 __ push(tmp);
2979 __ testptr(mdo_addr, TypeEntries::type_mask);
2980 __ jcc(Assembler::zero, ok);
2981 // may have been set by another thread
2982 __ mov_metadata(tmp, exact_klass->constant_encoding());
2983 __ xorptr(tmp, mdo_addr);
2984 __ testptr(tmp, TypeEntries::type_mask);
2985 __ jcc(Assembler::zero, ok);
2986
2987 __ stop("unexpected profiling mismatch");
2988 __ bind(ok);
2989 __ pop(tmp);
2990 }
2991 #else
2992 __ jccb(Assembler::zero, next);
2993 #endif
2994 // first time here. Set profile type.
2995 __ movptr(mdo_addr, tmp);
2996 #ifdef ASSERT
2997 __ andptr(tmp, TypeEntries::type_klass_mask);
2998 __ verify_klass_ptr(tmp);
2999 #endif
3000 } else {
3001 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3002 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3003
3004 __ testptr(mdo_addr, TypeEntries::type_unknown);
3005 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3006
3007 __ orptr(mdo_addr, TypeEntries::type_unknown);
3008 }
3009 }
3010 }
3011 __ bind(next);
3012 }
3013
3014 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3015 Unimplemented();
3016 }
3017
3018
3019 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3020 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3021 }
3022
3023
3024 void LIR_Assembler::align_backward_branch_target() {
3025 __ align(BytesPerWord);
3026 }
3027
3028
3029 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3030 if (left->is_single_cpu()) {
3031 __ negl(left->as_register());
3032 move_regs(left->as_register(), dest->as_register());
3033
3034 } else if (left->is_double_cpu()) {
3035 Register lo = left->as_register_lo();
3036 Register dst = dest->as_register_lo();
3037 __ movptr(dst, lo);
3038 __ negptr(dst);
3039
3040 } else if (dest->is_single_xmm()) {
3041 assert(!tmp->is_valid(), "do not need temporary");
3042 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3043 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3044 }
3045 __ xorps(dest->as_xmm_float_reg(),
3046 ExternalAddress((address)float_signflip_pool),
3047 rscratch1);
3048 } else if (dest->is_double_xmm()) {
3049 assert(!tmp->is_valid(), "do not need temporary");
3050 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3051 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3052 }
3053 __ xorpd(dest->as_xmm_double_reg(),
3054 ExternalAddress((address)double_signflip_pool),
3055 rscratch1);
3056 } else {
3057 ShouldNotReachHere();
3058 }
3059 }
3060
3061
3062 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3063 assert(src->is_address(), "must be an address");
3064 assert(dest->is_register(), "must be a register");
3065
3066 PatchingStub* patch = nullptr;
3067 if (patch_code != lir_patch_none) {
3068 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3069 }
3070
3071 Register reg = dest->as_pointer_register();
3072 LIR_Address* addr = src->as_address_ptr();
3073 __ lea(reg, as_Address(addr));
3074
3075 if (patch != nullptr) {
3076 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3077 }
3078 }
3079
3080
3081
3082 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3083 assert(!tmp->is_valid(), "don't need temporary");
3084 __ call(RuntimeAddress(dest));
3085 if (info != nullptr) {
3086 add_call_info_here(info);
3087 }
3088 __ post_call_nop();
3089 }
3090
3091
3092 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3093 assert(type == T_LONG, "only for volatile long fields");
3094
3095 if (info != nullptr) {
3096 add_debug_info_for_null_check_here(info);
3097 }
3098
3099 if (src->is_double_xmm()) {
3100 if (dest->is_double_cpu()) {
3101 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3102 } else if (dest->is_double_stack()) {
3103 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3104 } else if (dest->is_address()) {
3105 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3106 } else {
3107 ShouldNotReachHere();
3108 }
3109
3110 } else if (dest->is_double_xmm()) {
3111 if (src->is_double_stack()) {
3112 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3113 } else if (src->is_address()) {
3114 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3115 } else {
3116 ShouldNotReachHere();
3117 }
3118
3119 } else {
3120 ShouldNotReachHere();
3121 }
3122 }
3123
3124 #ifdef ASSERT
3125 // emit run-time assertion
3126 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3127 assert(op->code() == lir_assert, "must be");
3128
3129 if (op->in_opr1()->is_valid()) {
3130 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3131 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3132 } else {
3133 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3134 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3135 }
3136
3137 Label ok;
3138 if (op->condition() != lir_cond_always) {
3139 Assembler::Condition acond = Assembler::zero;
3140 switch (op->condition()) {
3141 case lir_cond_equal: acond = Assembler::equal; break;
3142 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3143 case lir_cond_less: acond = Assembler::less; break;
3144 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3145 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3146 case lir_cond_greater: acond = Assembler::greater; break;
3147 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3148 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3149 default: ShouldNotReachHere();
3150 }
3151 __ jcc(acond, ok);
3152 }
3153 if (op->halt()) {
3154 const char* str = __ code_string(op->msg());
3155 __ stop(str);
3156 } else {
3157 breakpoint();
3158 }
3159 __ bind(ok);
3160 }
3161 #endif
3162
3163 void LIR_Assembler::membar() {
3164 // QQQ sparc TSO uses this,
3165 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3166 }
3167
3168 void LIR_Assembler::membar_acquire() {
3169 // No x86 machines currently require load fences
3170 }
3171
3172 void LIR_Assembler::membar_release() {
3173 // No x86 machines currently require store fences
3174 }
3175
3176 void LIR_Assembler::membar_loadload() {
3177 // no-op
3178 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3179 }
3180
3181 void LIR_Assembler::membar_storestore() {
3182 // no-op
3183 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3184 }
3185
3186 void LIR_Assembler::membar_loadstore() {
3187 // no-op
3188 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3189 }
3190
3191 void LIR_Assembler::membar_storeload() {
3192 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3193 }
3194
3195 void LIR_Assembler::on_spin_wait() {
3196 __ pause ();
3197 }
3198
3199 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3200 assert(result_reg->is_register(), "check");
3201 __ mov(result_reg->as_register(), r15_thread);
3202 }
3203
3204
3205 void LIR_Assembler::peephole(LIR_List*) {
3206 // do nothing for now
3207 }
3208
3209 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3210 assert(data == dest, "xchg/xadd uses only 2 operands");
3211
3212 if (data->type() == T_INT) {
3213 if (code == lir_xadd) {
3214 __ lock();
3215 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3216 } else {
3217 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
3218 }
3219 } else if (data->is_oop()) {
3220 assert (code == lir_xchg, "xadd for oops");
3221 Register obj = data->as_register();
3222 if (UseCompressedOops) {
3223 __ encode_heap_oop(obj);
3224 __ xchgl(obj, as_Address(src->as_address_ptr()));
3225 __ decode_heap_oop(obj);
3226 } else {
3227 __ xchgptr(obj, as_Address(src->as_address_ptr()));
3228 }
3229 } else if (data->type() == T_LONG) {
3230 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
3231 if (code == lir_xadd) {
3232 __ lock();
3233 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
3234 } else {
3235 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
3236 }
3237 } else {
3238 ShouldNotReachHere();
3239 }
3240 }
3241
3242 #undef __