1 /*
2 * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "ci/ciUtilities.hpp"
37 #include "code/SCCache.hpp"
38 #include "compiler/oopMap.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/gc_globals.hpp"
41 #include "nativeInst_x86.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/safepointMechanism.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/stubRoutines.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_x86.inline.hpp"
49
50
51 // These masks are used to provide 128-bit aligned bitmasks to the XMM
52 // instructions, to allow sign-masking or sign-bit flipping. They allow
53 // fast versions of NegF/NegD and AbsF/AbsD.
54
55 // Note: 'double' and 'long long' have 32-bits alignment on x86.
56 static address double_quadword(jlong *adr, jlong lo, jlong hi) {
57 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
58 // of 128-bits operands for SSE instructions.
59 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
60 // Store the value to a 128-bits operand.
61 operand[0] = lo;
62 operand[1] = hi;
63 return (address)operand;
64 }
65
66 // Buffer for 128-bits masks used by SSE instructions.
67 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
68
69 // Static initialization during VM startup.
70 address LIR_Assembler::float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
71 address LIR_Assembler::double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
72 address LIR_Assembler::float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
73 address LIR_Assembler::double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
74
75
76 NEEDS_CLEANUP // remove this definitions ?
77 const Register SYNC_header = rax; // synchronization header
78 const Register SHIFT_count = rcx; // where count for shift operations must be
79
80 #define __ _masm->
81
82
83 static void select_different_registers(Register preserve,
84 Register extra,
85 Register &tmp1,
86 Register &tmp2) {
87 if (tmp1 == preserve) {
88 assert_different_registers(tmp1, tmp2, extra);
89 tmp1 = extra;
90 } else if (tmp2 == preserve) {
91 assert_different_registers(tmp1, tmp2, extra);
92 tmp2 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2);
95 }
96
97
98
99 static void select_different_registers(Register preserve,
100 Register extra,
101 Register &tmp1,
102 Register &tmp2,
103 Register &tmp3) {
104 if (tmp1 == preserve) {
105 assert_different_registers(tmp1, tmp2, tmp3, extra);
106 tmp1 = extra;
107 } else if (tmp2 == preserve) {
108 assert_different_registers(tmp1, tmp2, tmp3, extra);
109 tmp2 = extra;
110 } else if (tmp3 == preserve) {
111 assert_different_registers(tmp1, tmp2, tmp3, extra);
112 tmp3 = extra;
113 }
114 assert_different_registers(preserve, tmp1, tmp2, tmp3);
115 }
116
117
118
119 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
120 if (opr->is_constant()) {
121 LIR_Const* constant = opr->as_constant_ptr();
122 switch (constant->type()) {
123 case T_INT: {
124 return true;
125 }
126
127 default:
128 return false;
129 }
130 }
131 return false;
132 }
133
134
135 LIR_Opr LIR_Assembler::receiverOpr() {
136 return FrameMap::receiver_opr;
137 }
138
139 LIR_Opr LIR_Assembler::osrBufferPointer() {
140 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
141 }
142
143 //--------------fpu register translations-----------------------
144
145
146 address LIR_Assembler::float_constant(float f) {
147 address const_addr = __ float_constant(f);
148 if (const_addr == nullptr) {
149 bailout("const section overflow");
150 return __ code()->consts()->start();
151 } else {
152 return const_addr;
153 }
154 }
155
156
157 address LIR_Assembler::double_constant(double d) {
158 address const_addr = __ double_constant(d);
159 if (const_addr == nullptr) {
160 bailout("const section overflow");
161 return __ code()->consts()->start();
162 } else {
163 return const_addr;
164 }
165 }
166
167 #ifndef _LP64
168 void LIR_Assembler::fpop() {
169 __ fpop();
170 }
171
172 void LIR_Assembler::fxch(int i) {
173 __ fxch(i);
174 }
175
176 void LIR_Assembler::fld(int i) {
177 __ fld_s(i);
178 }
179
180 void LIR_Assembler::ffree(int i) {
181 __ ffree(i);
182 }
183 #endif // !_LP64
184
185 void LIR_Assembler::breakpoint() {
186 __ int3();
187 }
188
189 void LIR_Assembler::push(LIR_Opr opr) {
190 if (opr->is_single_cpu()) {
191 __ push_reg(opr->as_register());
192 } else if (opr->is_double_cpu()) {
193 NOT_LP64(__ push_reg(opr->as_register_hi()));
194 __ push_reg(opr->as_register_lo());
195 } else if (opr->is_stack()) {
196 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
197 } else if (opr->is_constant()) {
198 LIR_Const* const_opr = opr->as_constant_ptr();
199 if (const_opr->type() == T_OBJECT) {
200 __ push_oop(const_opr->as_jobject(), rscratch1);
201 } else if (const_opr->type() == T_INT) {
202 __ push_jint(const_opr->as_jint());
203 } else {
204 ShouldNotReachHere();
205 }
206
207 } else {
208 ShouldNotReachHere();
209 }
210 }
211
212 void LIR_Assembler::pop(LIR_Opr opr) {
213 if (opr->is_single_cpu()) {
214 __ pop_reg(opr->as_register());
215 } else {
216 ShouldNotReachHere();
217 }
218 }
219
220 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
221 return addr->base()->is_illegal() && addr->index()->is_illegal();
222 }
223
224 //-------------------------------------------
225
226 Address LIR_Assembler::as_Address(LIR_Address* addr) {
227 return as_Address(addr, rscratch1);
228 }
229
230 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
231 if (addr->base()->is_illegal()) {
232 assert(addr->index()->is_illegal(), "must be illegal too");
233 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
234 if (! __ reachable(laddr)) {
235 __ movptr(tmp, laddr.addr());
236 Address res(tmp, 0);
237 return res;
238 } else {
239 return __ as_Address(laddr);
240 }
241 }
242
243 Register base = addr->base()->as_pointer_register();
244
245 if (addr->index()->is_illegal()) {
246 return Address( base, addr->disp());
247 } else if (addr->index()->is_cpu_register()) {
248 Register index = addr->index()->as_pointer_register();
249 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
250 } else if (addr->index()->is_constant()) {
251 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
252 assert(Assembler::is_simm32(addr_offset), "must be");
253
254 return Address(base, addr_offset);
255 } else {
256 Unimplemented();
257 return Address();
258 }
259 }
260
261
262 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
263 Address base = as_Address(addr);
264 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
265 }
266
267
268 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
269 return as_Address(addr);
270 }
271
272
273 void LIR_Assembler::osr_entry() {
274 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
275 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
276 ValueStack* entry_state = osr_entry->state();
277 int number_of_locks = entry_state->locks_size();
278
279 // we jump here if osr happens with the interpreter
280 // state set up to continue at the beginning of the
281 // loop that triggered osr - in particular, we have
282 // the following registers setup:
283 //
284 // rcx: osr buffer
285 //
286
287 // build frame
288 ciMethod* m = compilation()->method();
289 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
290
291 // OSR buffer is
292 //
293 // locals[nlocals-1..0]
294 // monitors[0..number_of_locks]
295 //
296 // locals is a direct copy of the interpreter frame so in the osr buffer
297 // so first slot in the local array is the last local from the interpreter
298 // and last slot is local[0] (receiver) from the interpreter
299 //
300 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
301 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
302 // in the interpreter frame (the method lock if a sync method)
303
304 // Initialize monitors in the compiled activation.
305 // rcx: pointer to osr buffer
306 //
307 // All other registers are dead at this point and the locals will be
308 // copied into place by code emitted in the IR.
309
310 Register OSR_buf = osrBufferPointer()->as_pointer_register();
311 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
312 int monitor_offset = BytesPerWord * method()->max_locals() +
313 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
314 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
315 // the OSR buffer using 2 word entries: first the lock and then
316 // the oop.
317 for (int i = 0; i < number_of_locks; i++) {
318 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
319 #ifdef ASSERT
320 // verify the interpreter's monitor has a non-null object
321 {
322 Label L;
323 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD);
324 __ jcc(Assembler::notZero, L);
325 __ stop("locked object is null");
326 __ bind(L);
327 }
328 #endif
329 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
330 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
331 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
332 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
333 }
334 }
335 }
336
337
338 // inline cache check; done before the frame is built.
339 int LIR_Assembler::check_icache() {
340 return __ ic_check(CodeEntryAlignment);
341 }
342
343 void LIR_Assembler::clinit_barrier(ciMethod* method) {
344 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
345 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
346
347 Label L_skip_barrier;
348 Register klass = rscratch1;
349 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
350 assert(thread != noreg, "x86_32 not implemented");
351
352 __ mov_metadata(klass, method->holder()->constant_encoding());
353 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
354
355 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
356
357 __ bind(L_skip_barrier);
358 }
359
360 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
361 jobject o = nullptr;
362 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
363 __ movoop(reg, o);
364 patching_epilog(patch, lir_patch_normal, reg, info);
365 }
366
367 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
368 Metadata* o = nullptr;
369 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
370 __ mov_metadata(reg, o);
371 patching_epilog(patch, lir_patch_normal, reg, info);
372 }
373
374 // This specifies the rsp decrement needed to build the frame
375 int LIR_Assembler::initial_frame_size_in_bytes() const {
376 // if rounding, must let FrameMap know!
377
378 // The frame_map records size in slots (32bit word)
379
380 // subtract two words to account for return address and link
381 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
382 }
383
384
385 int LIR_Assembler::emit_exception_handler() {
386 // generate code for exception handler
387 address handler_base = __ start_a_stub(exception_handler_size());
388 if (handler_base == nullptr) {
389 // not enough space left for the handler
390 bailout("exception handler overflow");
391 return -1;
392 }
393
394 int offset = code_offset();
395
396 // the exception oop and pc are in rax, and rdx
397 // no other registers need to be preserved, so invalidate them
398 __ invalidate_registers(false, true, true, false, true, true);
399
400 // check that there is really an exception
401 __ verify_not_null_oop(rax);
402
403 // search an exception handler (rax: exception oop, rdx: throwing pc)
404 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
405 __ should_not_reach_here();
406 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
407 __ end_a_stub();
408
409 return offset;
410 }
411
412
413 // Emit the code to remove the frame from the stack in the exception
414 // unwind path.
415 int LIR_Assembler::emit_unwind_handler() {
416 #ifndef PRODUCT
417 if (CommentedAssembly) {
418 _masm->block_comment("Unwind handler");
419 }
420 #endif
421
422 int offset = code_offset();
423
424 // Fetch the exception from TLS and clear out exception related thread state
425 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
426 NOT_LP64(__ get_thread(thread));
427 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
428 __ movptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
429 __ movptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
430
431 __ bind(_unwind_handler_entry);
432 __ verify_not_null_oop(rax);
433 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
434 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
435 }
436
437 // Perform needed unlocking
438 MonitorExitStub* stub = nullptr;
439 if (method()->is_synchronized()) {
440 monitor_address(0, FrameMap::rax_opr);
441 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
442 if (LockingMode == LM_MONITOR) {
443 __ jmp(*stub->entry());
444 } else {
445 __ unlock_object(rdi, rsi, rax, *stub->entry());
446 }
447 __ bind(*stub->continuation());
448 }
449
450 if (compilation()->env()->dtrace_method_probes()) {
451 #ifdef _LP64
452 __ mov(rdi, r15_thread);
453 __ mov_metadata(rsi, method()->constant_encoding());
454 #else
455 __ get_thread(rax);
456 __ movptr(Address(rsp, 0), rax);
457 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding(), noreg);
458 #endif
459 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
460 }
461
462 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
463 __ mov(rax, rbx); // Restore the exception
464 }
465
466 // remove the activation and dispatch to the unwind handler
467 __ remove_frame(initial_frame_size_in_bytes());
468 __ jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
469
470 // Emit the slow path assembly
471 if (stub != nullptr) {
472 stub->emit_code(this);
473 }
474
475 return offset;
476 }
477
478
479 int LIR_Assembler::emit_deopt_handler() {
480 // generate code for exception handler
481 address handler_base = __ start_a_stub(deopt_handler_size());
482 if (handler_base == nullptr) {
483 // not enough space left for the handler
484 bailout("deopt handler overflow");
485 return -1;
486 }
487
488 int offset = code_offset();
489 InternalAddress here(__ pc());
490
491 __ pushptr(here.addr(), rscratch1);
492 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
493 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
494 __ end_a_stub();
495
496 return offset;
497 }
498
499 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
500 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
501 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
502 assert(result->fpu() == 0, "result must already be on TOS");
503 }
504
505 // Pop the stack before the safepoint code
506 __ remove_frame(initial_frame_size_in_bytes());
507
508 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
509 __ reserved_stack_check();
510 }
511
512 // Note: we do not need to round double result; float result has the right precision
513 // the poll sets the condition code, but no data registers
514
515 #ifdef _LP64
516 const Register thread = r15_thread;
517 #else
518 const Register thread = rbx;
519 __ get_thread(thread);
520 #endif
521 code_stub->set_safepoint_offset(__ offset());
522 __ relocate(relocInfo::poll_return_type);
523 __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */);
524 __ ret(0);
525 }
526
527
528 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
529 guarantee(info != nullptr, "Shouldn't be null");
530 int offset = __ offset();
531 #ifdef _LP64
532 const Register poll_addr = rscratch1;
533 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
534 #else
535 assert(tmp->is_cpu_register(), "needed");
536 const Register poll_addr = tmp->as_register();
537 __ get_thread(poll_addr);
538 __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset())));
539 #endif
540 add_debug_info_for_branch(info);
541 __ relocate(relocInfo::poll_type);
542 address pre_pc = __ pc();
543 __ testl(rax, Address(poll_addr, 0));
544 address post_pc = __ pc();
545 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
546 return offset;
547 }
548
549
550 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
551 if (from_reg != to_reg) __ mov(to_reg, from_reg);
552 }
553
554 void LIR_Assembler::swap_reg(Register a, Register b) {
555 __ xchgptr(a, b);
556 }
557
558
559 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
560 assert(src->is_constant(), "should not call otherwise");
561 assert(dest->is_register(), "should not call otherwise");
562 LIR_Const* c = src->as_constant_ptr();
563
564 switch (c->type()) {
565 case T_INT: {
566 assert(patch_code == lir_patch_none, "no patching handled here");
567 __ movl(dest->as_register(), c->as_jint());
568 break;
569 }
570
571 case T_ADDRESS: {
572 assert(patch_code == lir_patch_none, "no patching handled here");
573 __ movptr(dest->as_register(), c->as_jint());
574 break;
575 }
576
577 case T_LONG: {
578 assert(patch_code == lir_patch_none, "no patching handled here");
579 #ifdef _LP64
580 if (SCCache::is_on_for_write()) {
581 // SCA needs relocation info for card table base
582 address b = c->as_pointer();
583 if (is_card_table_address(b)) {
584 __ lea(dest->as_register_lo(), ExternalAddress(b));
585 break;
586 }
587 if (AOTRuntimeConstants::contains(b)) {
588 __ load_aotrc_address(dest->as_register_lo(), b);
589 break;
590 }
591 }
592 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
593 #else
594 __ movptr(dest->as_register_lo(), c->as_jint_lo());
595 __ movptr(dest->as_register_hi(), c->as_jint_hi());
596 #endif // _LP64
597 break;
598 }
599
600 case T_OBJECT: {
601 if (patch_code != lir_patch_none) {
602 jobject2reg_with_patching(dest->as_register(), info);
603 } else {
604 __ movoop(dest->as_register(), c->as_jobject());
605 }
606 break;
607 }
608
609 case T_METADATA: {
610 if (patch_code != lir_patch_none) {
611 klass2reg_with_patching(dest->as_register(), info);
612 } else {
613 __ mov_metadata(dest->as_register(), c->as_metadata());
614 }
615 break;
616 }
617
618 case T_FLOAT: {
619 if (dest->is_single_xmm()) {
620 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
621 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
622 } else {
623 __ movflt(dest->as_xmm_float_reg(),
624 InternalAddress(float_constant(c->as_jfloat())));
625 }
626 } else {
627 #ifndef _LP64
628 assert(dest->is_single_fpu(), "must be");
629 assert(dest->fpu_regnr() == 0, "dest must be TOS");
630 if (c->is_zero_float()) {
631 __ fldz();
632 } else if (c->is_one_float()) {
633 __ fld1();
634 } else {
635 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
636 }
637 #else
638 ShouldNotReachHere();
639 #endif // !_LP64
640 }
641 break;
642 }
643
644 case T_DOUBLE: {
645 if (dest->is_double_xmm()) {
646 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
647 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
648 } else {
649 __ movdbl(dest->as_xmm_double_reg(),
650 InternalAddress(double_constant(c->as_jdouble())));
651 }
652 } else {
653 #ifndef _LP64
654 assert(dest->is_double_fpu(), "must be");
655 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
656 if (c->is_zero_double()) {
657 __ fldz();
658 } else if (c->is_one_double()) {
659 __ fld1();
660 } else {
661 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
662 }
663 #else
664 ShouldNotReachHere();
665 #endif // !_LP64
666 }
667 break;
668 }
669
670 default:
671 ShouldNotReachHere();
672 }
673 }
674
675 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
676 assert(src->is_constant(), "should not call otherwise");
677 assert(dest->is_stack(), "should not call otherwise");
678 LIR_Const* c = src->as_constant_ptr();
679
680 switch (c->type()) {
681 case T_INT: // fall through
682 case T_FLOAT:
683 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
684 break;
685
686 case T_ADDRESS:
687 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
688 break;
689
690 case T_OBJECT:
691 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1);
692 break;
693
694 case T_LONG: // fall through
695 case T_DOUBLE:
696 #ifdef _LP64
697 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
698 lo_word_offset_in_bytes),
699 (intptr_t)c->as_jlong_bits(),
700 rscratch1);
701 #else
702 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
703 lo_word_offset_in_bytes), c->as_jint_lo_bits());
704 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
705 hi_word_offset_in_bytes), c->as_jint_hi_bits());
706 #endif // _LP64
707 break;
708
709 default:
710 ShouldNotReachHere();
711 }
712 }
713
714 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
715 assert(src->is_constant(), "should not call otherwise");
716 assert(dest->is_address(), "should not call otherwise");
717 LIR_Const* c = src->as_constant_ptr();
718 LIR_Address* addr = dest->as_address_ptr();
719
720 int null_check_here = code_offset();
721 switch (type) {
722 case T_INT: // fall through
723 case T_FLOAT:
724 __ movl(as_Address(addr), c->as_jint_bits());
725 break;
726
727 case T_ADDRESS:
728 __ movptr(as_Address(addr), c->as_jint_bits());
729 break;
730
731 case T_OBJECT: // fall through
732 case T_ARRAY:
733 if (c->as_jobject() == nullptr) {
734 if (UseCompressedOops && !wide) {
735 __ movl(as_Address(addr), NULL_WORD);
736 } else {
737 #ifdef _LP64
738 __ xorptr(rscratch1, rscratch1);
739 null_check_here = code_offset();
740 __ movptr(as_Address(addr), rscratch1);
741 #else
742 __ movptr(as_Address(addr), NULL_WORD);
743 #endif
744 }
745 } else {
746 if (is_literal_address(addr)) {
747 ShouldNotReachHere();
748 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1);
749 } else {
750 #ifdef _LP64
751 __ movoop(rscratch1, c->as_jobject());
752 if (UseCompressedOops && !wide) {
753 __ encode_heap_oop(rscratch1);
754 null_check_here = code_offset();
755 __ movl(as_Address_lo(addr), rscratch1);
756 } else {
757 null_check_here = code_offset();
758 __ movptr(as_Address_lo(addr), rscratch1);
759 }
760 #else
761 __ movoop(as_Address(addr), c->as_jobject(), noreg);
762 #endif
763 }
764 }
765 break;
766
767 case T_LONG: // fall through
768 case T_DOUBLE:
769 #ifdef _LP64
770 if (is_literal_address(addr)) {
771 ShouldNotReachHere();
772 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
773 } else {
774 __ movptr(r10, (intptr_t)c->as_jlong_bits());
775 null_check_here = code_offset();
776 __ movptr(as_Address_lo(addr), r10);
777 }
778 #else
779 // Always reachable in 32bit so this doesn't produce useless move literal
780 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
781 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
782 #endif // _LP64
783 break;
784
785 case T_BOOLEAN: // fall through
786 case T_BYTE:
787 __ movb(as_Address(addr), c->as_jint() & 0xFF);
788 break;
789
790 case T_CHAR: // fall through
791 case T_SHORT:
792 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
793 break;
794
795 default:
796 ShouldNotReachHere();
797 };
798
799 if (info != nullptr) {
800 add_debug_info_for_null_check(null_check_here, info);
801 }
802 }
803
804
805 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
806 assert(src->is_register(), "should not call otherwise");
807 assert(dest->is_register(), "should not call otherwise");
808
809 // move between cpu-registers
810 if (dest->is_single_cpu()) {
811 #ifdef _LP64
812 if (src->type() == T_LONG) {
813 // Can do LONG -> OBJECT
814 move_regs(src->as_register_lo(), dest->as_register());
815 return;
816 }
817 #endif
818 assert(src->is_single_cpu(), "must match");
819 if (src->type() == T_OBJECT) {
820 __ verify_oop(src->as_register());
821 }
822 move_regs(src->as_register(), dest->as_register());
823
824 } else if (dest->is_double_cpu()) {
825 #ifdef _LP64
826 if (is_reference_type(src->type())) {
827 // Surprising to me but we can see move of a long to t_object
828 __ verify_oop(src->as_register());
829 move_regs(src->as_register(), dest->as_register_lo());
830 return;
831 }
832 #endif
833 assert(src->is_double_cpu(), "must match");
834 Register f_lo = src->as_register_lo();
835 Register f_hi = src->as_register_hi();
836 Register t_lo = dest->as_register_lo();
837 Register t_hi = dest->as_register_hi();
838 #ifdef _LP64
839 assert(f_hi == f_lo, "must be same");
840 assert(t_hi == t_lo, "must be same");
841 move_regs(f_lo, t_lo);
842 #else
843 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
844
845
846 if (f_lo == t_hi && f_hi == t_lo) {
847 swap_reg(f_lo, f_hi);
848 } else if (f_hi == t_lo) {
849 assert(f_lo != t_hi, "overwriting register");
850 move_regs(f_hi, t_hi);
851 move_regs(f_lo, t_lo);
852 } else {
853 assert(f_hi != t_lo, "overwriting register");
854 move_regs(f_lo, t_lo);
855 move_regs(f_hi, t_hi);
856 }
857 #endif // LP64
858
859 #ifndef _LP64
860 // special moves from fpu-register to xmm-register
861 // necessary for method results
862 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
863 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
864 __ fld_s(Address(rsp, 0));
865 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
866 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
867 __ fld_d(Address(rsp, 0));
868 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
869 __ fstp_s(Address(rsp, 0));
870 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
871 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
872 __ fstp_d(Address(rsp, 0));
873 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
874 #endif // !_LP64
875
876 // move between xmm-registers
877 } else if (dest->is_single_xmm()) {
878 assert(src->is_single_xmm(), "must match");
879 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
880 } else if (dest->is_double_xmm()) {
881 assert(src->is_double_xmm(), "must match");
882 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
883
884 #ifndef _LP64
885 // move between fpu-registers (no instruction necessary because of fpu-stack)
886 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
887 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
888 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
889 #endif // !_LP64
890
891 } else {
892 ShouldNotReachHere();
893 }
894 }
895
896 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
897 assert(src->is_register(), "should not call otherwise");
898 assert(dest->is_stack(), "should not call otherwise");
899
900 if (src->is_single_cpu()) {
901 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
902 if (is_reference_type(type)) {
903 __ verify_oop(src->as_register());
904 __ movptr (dst, src->as_register());
905 } else if (type == T_METADATA || type == T_ADDRESS) {
906 __ movptr (dst, src->as_register());
907 } else {
908 __ movl (dst, src->as_register());
909 }
910
911 } else if (src->is_double_cpu()) {
912 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
913 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
914 __ movptr (dstLO, src->as_register_lo());
915 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
916
917 } else if (src->is_single_xmm()) {
918 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
919 __ movflt(dst_addr, src->as_xmm_float_reg());
920
921 } else if (src->is_double_xmm()) {
922 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
923 __ movdbl(dst_addr, src->as_xmm_double_reg());
924
925 #ifndef _LP64
926 } else if (src->is_single_fpu()) {
927 assert(src->fpu_regnr() == 0, "argument must be on TOS");
928 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
929 if (pop_fpu_stack) __ fstp_s (dst_addr);
930 else __ fst_s (dst_addr);
931
932 } else if (src->is_double_fpu()) {
933 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
934 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
935 if (pop_fpu_stack) __ fstp_d (dst_addr);
936 else __ fst_d (dst_addr);
937 #endif // !_LP64
938
939 } else {
940 ShouldNotReachHere();
941 }
942 }
943
944
945 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
946 LIR_Address* to_addr = dest->as_address_ptr();
947 PatchingStub* patch = nullptr;
948 Register compressed_src = rscratch1;
949
950 if (is_reference_type(type)) {
951 __ verify_oop(src->as_register());
952 #ifdef _LP64
953 if (UseCompressedOops && !wide) {
954 __ movptr(compressed_src, src->as_register());
955 __ encode_heap_oop(compressed_src);
956 if (patch_code != lir_patch_none) {
957 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
958 }
959 }
960 #endif
961 }
962
963 if (patch_code != lir_patch_none) {
964 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
965 Address toa = as_Address(to_addr);
966 assert(toa.disp() != 0, "must have");
967 }
968
969 int null_check_here = code_offset();
970 switch (type) {
971 case T_FLOAT: {
972 #ifdef _LP64
973 assert(src->is_single_xmm(), "not a float");
974 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
975 #else
976 if (src->is_single_xmm()) {
977 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
978 } else {
979 assert(src->is_single_fpu(), "must be");
980 assert(src->fpu_regnr() == 0, "argument must be on TOS");
981 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
982 else __ fst_s (as_Address(to_addr));
983 }
984 #endif // _LP64
985 break;
986 }
987
988 case T_DOUBLE: {
989 #ifdef _LP64
990 assert(src->is_double_xmm(), "not a double");
991 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
992 #else
993 if (src->is_double_xmm()) {
994 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
995 } else {
996 assert(src->is_double_fpu(), "must be");
997 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
998 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
999 else __ fst_d (as_Address(to_addr));
1000 }
1001 #endif // _LP64
1002 break;
1003 }
1004
1005 case T_ARRAY: // fall through
1006 case T_OBJECT: // fall through
1007 if (UseCompressedOops && !wide) {
1008 __ movl(as_Address(to_addr), compressed_src);
1009 } else {
1010 __ movptr(as_Address(to_addr), src->as_register());
1011 }
1012 break;
1013 case T_METADATA:
1014 // We get here to store a method pointer to the stack to pass to
1015 // a dtrace runtime call. This can't work on 64 bit with
1016 // compressed klass ptrs: T_METADATA can be a compressed klass
1017 // ptr or a 64 bit method pointer.
1018 LP64_ONLY(ShouldNotReachHere());
1019 __ movptr(as_Address(to_addr), src->as_register());
1020 break;
1021 case T_ADDRESS:
1022 __ movptr(as_Address(to_addr), src->as_register());
1023 break;
1024 case T_INT:
1025 __ movl(as_Address(to_addr), src->as_register());
1026 break;
1027
1028 case T_LONG: {
1029 Register from_lo = src->as_register_lo();
1030 Register from_hi = src->as_register_hi();
1031 #ifdef _LP64
1032 __ movptr(as_Address_lo(to_addr), from_lo);
1033 #else
1034 Register base = to_addr->base()->as_register();
1035 Register index = noreg;
1036 if (to_addr->index()->is_register()) {
1037 index = to_addr->index()->as_register();
1038 }
1039 if (base == from_lo || index == from_lo) {
1040 assert(base != from_hi, "can't be");
1041 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1042 __ movl(as_Address_hi(to_addr), from_hi);
1043 if (patch != nullptr) {
1044 patching_epilog(patch, lir_patch_high, base, info);
1045 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1046 patch_code = lir_patch_low;
1047 }
1048 __ movl(as_Address_lo(to_addr), from_lo);
1049 } else {
1050 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1051 __ movl(as_Address_lo(to_addr), from_lo);
1052 if (patch != nullptr) {
1053 patching_epilog(patch, lir_patch_low, base, info);
1054 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1055 patch_code = lir_patch_high;
1056 }
1057 __ movl(as_Address_hi(to_addr), from_hi);
1058 }
1059 #endif // _LP64
1060 break;
1061 }
1062
1063 case T_BYTE: // fall through
1064 case T_BOOLEAN: {
1065 Register src_reg = src->as_register();
1066 Address dst_addr = as_Address(to_addr);
1067 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1068 __ movb(dst_addr, src_reg);
1069 break;
1070 }
1071
1072 case T_CHAR: // fall through
1073 case T_SHORT:
1074 __ movw(as_Address(to_addr), src->as_register());
1075 break;
1076
1077 default:
1078 ShouldNotReachHere();
1079 }
1080 if (info != nullptr) {
1081 add_debug_info_for_null_check(null_check_here, info);
1082 }
1083
1084 if (patch_code != lir_patch_none) {
1085 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1086 }
1087 }
1088
1089
1090 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1091 assert(src->is_stack(), "should not call otherwise");
1092 assert(dest->is_register(), "should not call otherwise");
1093
1094 if (dest->is_single_cpu()) {
1095 if (is_reference_type(type)) {
1096 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1097 __ verify_oop(dest->as_register());
1098 } else if (type == T_METADATA || type == T_ADDRESS) {
1099 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1100 } else {
1101 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1102 }
1103
1104 } else if (dest->is_double_cpu()) {
1105 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1106 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1107 __ movptr(dest->as_register_lo(), src_addr_LO);
1108 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1109
1110 } else if (dest->is_single_xmm()) {
1111 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1112 __ movflt(dest->as_xmm_float_reg(), src_addr);
1113
1114 } else if (dest->is_double_xmm()) {
1115 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1116 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1117
1118 #ifndef _LP64
1119 } else if (dest->is_single_fpu()) {
1120 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1121 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1122 __ fld_s(src_addr);
1123
1124 } else if (dest->is_double_fpu()) {
1125 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1126 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1127 __ fld_d(src_addr);
1128 #endif // _LP64
1129
1130 } else {
1131 ShouldNotReachHere();
1132 }
1133 }
1134
1135
1136 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1137 if (src->is_single_stack()) {
1138 if (is_reference_type(type)) {
1139 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1140 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1141 } else {
1142 #ifndef _LP64
1143 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1144 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1145 #else
1146 //no pushl on 64bits
1147 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1148 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1149 #endif
1150 }
1151
1152 } else if (src->is_double_stack()) {
1153 #ifdef _LP64
1154 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1155 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1156 #else
1157 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1158 // push and pop the part at src + wordSize, adding wordSize for the previous push
1159 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1160 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1161 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1162 #endif // _LP64
1163
1164 } else {
1165 ShouldNotReachHere();
1166 }
1167 }
1168
1169
1170 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1171 assert(src->is_address(), "should not call otherwise");
1172 assert(dest->is_register(), "should not call otherwise");
1173
1174 LIR_Address* addr = src->as_address_ptr();
1175 Address from_addr = as_Address(addr);
1176
1177 if (addr->base()->type() == T_OBJECT) {
1178 __ verify_oop(addr->base()->as_pointer_register());
1179 }
1180
1181 switch (type) {
1182 case T_BOOLEAN: // fall through
1183 case T_BYTE: // fall through
1184 case T_CHAR: // fall through
1185 case T_SHORT:
1186 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1187 // on pre P6 processors we may get partial register stalls
1188 // so blow away the value of to_rinfo before loading a
1189 // partial word into it. Do it here so that it precedes
1190 // the potential patch point below.
1191 __ xorptr(dest->as_register(), dest->as_register());
1192 }
1193 break;
1194 default:
1195 break;
1196 }
1197
1198 PatchingStub* patch = nullptr;
1199 if (patch_code != lir_patch_none) {
1200 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1201 assert(from_addr.disp() != 0, "must have");
1202 }
1203 if (info != nullptr) {
1204 add_debug_info_for_null_check_here(info);
1205 }
1206
1207 switch (type) {
1208 case T_FLOAT: {
1209 if (dest->is_single_xmm()) {
1210 __ movflt(dest->as_xmm_float_reg(), from_addr);
1211 } else {
1212 #ifndef _LP64
1213 assert(dest->is_single_fpu(), "must be");
1214 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1215 __ fld_s(from_addr);
1216 #else
1217 ShouldNotReachHere();
1218 #endif // !LP64
1219 }
1220 break;
1221 }
1222
1223 case T_DOUBLE: {
1224 if (dest->is_double_xmm()) {
1225 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1226 } else {
1227 #ifndef _LP64
1228 assert(dest->is_double_fpu(), "must be");
1229 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1230 __ fld_d(from_addr);
1231 #else
1232 ShouldNotReachHere();
1233 #endif // !LP64
1234 }
1235 break;
1236 }
1237
1238 case T_OBJECT: // fall through
1239 case T_ARRAY: // fall through
1240 if (UseCompressedOops && !wide) {
1241 __ movl(dest->as_register(), from_addr);
1242 } else {
1243 __ movptr(dest->as_register(), from_addr);
1244 }
1245 break;
1246
1247 case T_ADDRESS:
1248 __ movptr(dest->as_register(), from_addr);
1249 break;
1250 case T_INT:
1251 __ movl(dest->as_register(), from_addr);
1252 break;
1253
1254 case T_LONG: {
1255 Register to_lo = dest->as_register_lo();
1256 Register to_hi = dest->as_register_hi();
1257 #ifdef _LP64
1258 __ movptr(to_lo, as_Address_lo(addr));
1259 #else
1260 Register base = addr->base()->as_register();
1261 Register index = noreg;
1262 if (addr->index()->is_register()) {
1263 index = addr->index()->as_register();
1264 }
1265 if ((base == to_lo && index == to_hi) ||
1266 (base == to_hi && index == to_lo)) {
1267 // addresses with 2 registers are only formed as a result of
1268 // array access so this code will never have to deal with
1269 // patches or null checks.
1270 assert(info == nullptr && patch == nullptr, "must be");
1271 __ lea(to_hi, as_Address(addr));
1272 __ movl(to_lo, Address(to_hi, 0));
1273 __ movl(to_hi, Address(to_hi, BytesPerWord));
1274 } else if (base == to_lo || index == to_lo) {
1275 assert(base != to_hi, "can't be");
1276 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1277 __ movl(to_hi, as_Address_hi(addr));
1278 if (patch != nullptr) {
1279 patching_epilog(patch, lir_patch_high, base, info);
1280 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1281 patch_code = lir_patch_low;
1282 }
1283 __ movl(to_lo, as_Address_lo(addr));
1284 } else {
1285 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1286 __ movl(to_lo, as_Address_lo(addr));
1287 if (patch != nullptr) {
1288 patching_epilog(patch, lir_patch_low, base, info);
1289 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1290 patch_code = lir_patch_high;
1291 }
1292 __ movl(to_hi, as_Address_hi(addr));
1293 }
1294 #endif // _LP64
1295 break;
1296 }
1297
1298 case T_BOOLEAN: // fall through
1299 case T_BYTE: {
1300 Register dest_reg = dest->as_register();
1301 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1302 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1303 __ movsbl(dest_reg, from_addr);
1304 } else {
1305 __ movb(dest_reg, from_addr);
1306 __ shll(dest_reg, 24);
1307 __ sarl(dest_reg, 24);
1308 }
1309 break;
1310 }
1311
1312 case T_CHAR: {
1313 Register dest_reg = dest->as_register();
1314 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1315 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1316 __ movzwl(dest_reg, from_addr);
1317 } else {
1318 __ movw(dest_reg, from_addr);
1319 }
1320 break;
1321 }
1322
1323 case T_SHORT: {
1324 Register dest_reg = dest->as_register();
1325 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1326 __ movswl(dest_reg, from_addr);
1327 } else {
1328 __ movw(dest_reg, from_addr);
1329 __ shll(dest_reg, 16);
1330 __ sarl(dest_reg, 16);
1331 }
1332 break;
1333 }
1334
1335 default:
1336 ShouldNotReachHere();
1337 }
1338
1339 if (patch != nullptr) {
1340 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1341 }
1342
1343 if (is_reference_type(type)) {
1344 #ifdef _LP64
1345 if (UseCompressedOops && !wide) {
1346 __ decode_heap_oop(dest->as_register());
1347 }
1348 #endif
1349
1350 __ verify_oop(dest->as_register());
1351 }
1352 }
1353
1354
1355 NEEDS_CLEANUP; // This could be static?
1356 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1357 int elem_size = type2aelembytes(type);
1358 switch (elem_size) {
1359 case 1: return Address::times_1;
1360 case 2: return Address::times_2;
1361 case 4: return Address::times_4;
1362 case 8: return Address::times_8;
1363 }
1364 ShouldNotReachHere();
1365 return Address::no_scale;
1366 }
1367
1368
1369 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1370 switch (op->code()) {
1371 case lir_idiv:
1372 case lir_irem:
1373 arithmetic_idiv(op->code(),
1374 op->in_opr1(),
1375 op->in_opr2(),
1376 op->in_opr3(),
1377 op->result_opr(),
1378 op->info());
1379 break;
1380 case lir_fmad:
1381 __ fmad(op->result_opr()->as_xmm_double_reg(),
1382 op->in_opr1()->as_xmm_double_reg(),
1383 op->in_opr2()->as_xmm_double_reg(),
1384 op->in_opr3()->as_xmm_double_reg());
1385 break;
1386 case lir_fmaf:
1387 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1388 op->in_opr1()->as_xmm_float_reg(),
1389 op->in_opr2()->as_xmm_float_reg(),
1390 op->in_opr3()->as_xmm_float_reg());
1391 break;
1392 default: ShouldNotReachHere(); break;
1393 }
1394 }
1395
1396 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1397 #ifdef ASSERT
1398 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1399 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1400 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1401 #endif
1402
1403 if (op->cond() == lir_cond_always) {
1404 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1405 __ jmp (*(op->label()));
1406 } else {
1407 Assembler::Condition acond = Assembler::zero;
1408 if (op->code() == lir_cond_float_branch) {
1409 assert(op->ublock() != nullptr, "must have unordered successor");
1410 __ jcc(Assembler::parity, *(op->ublock()->label()));
1411 switch(op->cond()) {
1412 case lir_cond_equal: acond = Assembler::equal; break;
1413 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1414 case lir_cond_less: acond = Assembler::below; break;
1415 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1416 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1417 case lir_cond_greater: acond = Assembler::above; break;
1418 default: ShouldNotReachHere();
1419 }
1420 } else {
1421 switch (op->cond()) {
1422 case lir_cond_equal: acond = Assembler::equal; break;
1423 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1424 case lir_cond_less: acond = Assembler::less; break;
1425 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1426 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1427 case lir_cond_greater: acond = Assembler::greater; break;
1428 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1429 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1430 default: ShouldNotReachHere();
1431 }
1432 }
1433 __ jcc(acond,*(op->label()));
1434 }
1435 }
1436
1437 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1438 LIR_Opr src = op->in_opr();
1439 LIR_Opr dest = op->result_opr();
1440
1441 switch (op->bytecode()) {
1442 case Bytecodes::_i2l:
1443 #ifdef _LP64
1444 __ movl2ptr(dest->as_register_lo(), src->as_register());
1445 #else
1446 move_regs(src->as_register(), dest->as_register_lo());
1447 move_regs(src->as_register(), dest->as_register_hi());
1448 __ sarl(dest->as_register_hi(), 31);
1449 #endif // LP64
1450 break;
1451
1452 case Bytecodes::_l2i:
1453 #ifdef _LP64
1454 __ movl(dest->as_register(), src->as_register_lo());
1455 #else
1456 move_regs(src->as_register_lo(), dest->as_register());
1457 #endif
1458 break;
1459
1460 case Bytecodes::_i2b:
1461 move_regs(src->as_register(), dest->as_register());
1462 __ sign_extend_byte(dest->as_register());
1463 break;
1464
1465 case Bytecodes::_i2c:
1466 move_regs(src->as_register(), dest->as_register());
1467 __ andl(dest->as_register(), 0xFFFF);
1468 break;
1469
1470 case Bytecodes::_i2s:
1471 move_regs(src->as_register(), dest->as_register());
1472 __ sign_extend_short(dest->as_register());
1473 break;
1474
1475
1476 #ifdef _LP64
1477 case Bytecodes::_f2d:
1478 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1479 break;
1480
1481 case Bytecodes::_d2f:
1482 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1483 break;
1484
1485 case Bytecodes::_i2f:
1486 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1487 break;
1488
1489 case Bytecodes::_i2d:
1490 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1491 break;
1492
1493 case Bytecodes::_l2f:
1494 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1495 break;
1496
1497 case Bytecodes::_l2d:
1498 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1499 break;
1500
1501 case Bytecodes::_f2i:
1502 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1503 break;
1504
1505 case Bytecodes::_d2i:
1506 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1507 break;
1508
1509 case Bytecodes::_f2l:
1510 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1511 break;
1512
1513 case Bytecodes::_d2l:
1514 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1515 break;
1516 #else
1517 case Bytecodes::_f2d:
1518 case Bytecodes::_d2f:
1519 if (dest->is_single_xmm()) {
1520 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1521 } else if (dest->is_double_xmm()) {
1522 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1523 } else {
1524 assert(src->fpu() == dest->fpu(), "register must be equal");
1525 // do nothing (float result is rounded later through spilling)
1526 }
1527 break;
1528
1529 case Bytecodes::_i2f:
1530 case Bytecodes::_i2d:
1531 if (dest->is_single_xmm()) {
1532 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1533 } else if (dest->is_double_xmm()) {
1534 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1535 } else {
1536 assert(dest->fpu() == 0, "result must be on TOS");
1537 __ movl(Address(rsp, 0), src->as_register());
1538 __ fild_s(Address(rsp, 0));
1539 }
1540 break;
1541
1542 case Bytecodes::_l2f:
1543 case Bytecodes::_l2d:
1544 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1545 assert(dest->fpu() == 0, "result must be on TOS");
1546 __ movptr(Address(rsp, 0), src->as_register_lo());
1547 __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1548 __ fild_d(Address(rsp, 0));
1549 // float result is rounded later through spilling
1550 break;
1551
1552 case Bytecodes::_f2i:
1553 case Bytecodes::_d2i:
1554 if (src->is_single_xmm()) {
1555 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1556 } else if (src->is_double_xmm()) {
1557 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1558 } else {
1559 assert(src->fpu() == 0, "input must be on TOS");
1560 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc()));
1561 __ fist_s(Address(rsp, 0));
1562 __ movl(dest->as_register(), Address(rsp, 0));
1563 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
1564 }
1565 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1566 assert(op->stub() != nullptr, "stub required");
1567 __ cmpl(dest->as_register(), 0x80000000);
1568 __ jcc(Assembler::equal, *op->stub()->entry());
1569 __ bind(*op->stub()->continuation());
1570 break;
1571
1572 case Bytecodes::_f2l:
1573 case Bytecodes::_d2l:
1574 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1575 assert(src->fpu() == 0, "input must be on TOS");
1576 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1577
1578 // instruction sequence too long to inline it here
1579 {
1580 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::fpu2long_stub_id)));
1581 }
1582 break;
1583 #endif // _LP64
1584
1585 default: ShouldNotReachHere();
1586 }
1587 }
1588
1589 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1590 if (op->init_check()) {
1591 add_debug_info_for_null_check_here(op->stub()->info());
1592 // init_state needs acquire, but x86 is TSO, and so we are already good.
1593 __ cmpb(Address(op->klass()->as_register(),
1594 InstanceKlass::init_state_offset()),
1595 InstanceKlass::fully_initialized);
1596 __ jcc(Assembler::notEqual, *op->stub()->entry());
1597 }
1598 __ allocate_object(op->obj()->as_register(),
1599 op->tmp1()->as_register(),
1600 op->tmp2()->as_register(),
1601 op->header_size(),
1602 op->object_size(),
1603 op->klass()->as_register(),
1604 *op->stub()->entry());
1605 __ bind(*op->stub()->continuation());
1606 }
1607
1608 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1609 Register len = op->len()->as_register();
1610 LP64_ONLY( __ movslq(len, len); )
1611
1612 if (UseSlowPath ||
1613 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1614 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1615 __ jmp(*op->stub()->entry());
1616 } else {
1617 Register tmp1 = op->tmp1()->as_register();
1618 Register tmp2 = op->tmp2()->as_register();
1619 Register tmp3 = op->tmp3()->as_register();
1620 if (len == tmp1) {
1621 tmp1 = tmp3;
1622 } else if (len == tmp2) {
1623 tmp2 = tmp3;
1624 } else if (len == tmp3) {
1625 // everything is ok
1626 } else {
1627 __ mov(tmp3, len);
1628 }
1629 __ allocate_array(op->obj()->as_register(),
1630 len,
1631 tmp1,
1632 tmp2,
1633 arrayOopDesc::base_offset_in_bytes(op->type()),
1634 array_element_size(op->type()),
1635 op->klass()->as_register(),
1636 *op->stub()->entry(),
1637 op->zero_array());
1638 }
1639 __ bind(*op->stub()->continuation());
1640 }
1641
1642 void LIR_Assembler::type_profile_helper(Register mdo,
1643 ciMethodData *md, ciProfileData *data,
1644 Register recv, Label* update_done) {
1645 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1646 Label next_test;
1647 // See if the receiver is receiver[n].
1648 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1649 __ jccb(Assembler::notEqual, next_test);
1650 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1651 __ addptr(data_addr, DataLayout::counter_increment);
1652 __ jmp(*update_done);
1653 __ bind(next_test);
1654 }
1655
1656 // Didn't find receiver; find next empty slot and fill it in
1657 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1658 Label next_test;
1659 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1660 __ cmpptr(recv_addr, NULL_WORD);
1661 __ jccb(Assembler::notEqual, next_test);
1662 __ movptr(recv_addr, recv);
1663 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1664 __ jmp(*update_done);
1665 __ bind(next_test);
1666 }
1667 }
1668
1669 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1670 // we always need a stub for the failure case.
1671 CodeStub* stub = op->stub();
1672 Register obj = op->object()->as_register();
1673 Register k_RInfo = op->tmp1()->as_register();
1674 Register klass_RInfo = op->tmp2()->as_register();
1675 Register dst = op->result_opr()->as_register();
1676 ciKlass* k = op->klass();
1677 Register Rtmp1 = noreg;
1678 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1679
1680 // check if it needs to be profiled
1681 ciMethodData* md = nullptr;
1682 ciProfileData* data = nullptr;
1683
1684 if (op->should_profile()) {
1685 ciMethod* method = op->profiled_method();
1686 assert(method != nullptr, "Should have method");
1687 int bci = op->profiled_bci();
1688 md = method->method_data_or_null();
1689 assert(md != nullptr, "Sanity");
1690 data = md->bci_to_data(bci);
1691 assert(data != nullptr, "need data for type check");
1692 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1693 }
1694 Label* success_target = success;
1695 Label* failure_target = failure;
1696
1697 if (obj == k_RInfo) {
1698 k_RInfo = dst;
1699 } else if (obj == klass_RInfo) {
1700 klass_RInfo = dst;
1701 }
1702 if (k->is_loaded() && !UseCompressedClassPointers) {
1703 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1704 } else {
1705 Rtmp1 = op->tmp3()->as_register();
1706 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1707 }
1708
1709 assert_different_registers(obj, k_RInfo, klass_RInfo);
1710
1711 __ testptr(obj, obj);
1712 if (op->should_profile()) {
1713 Label not_null;
1714 Register mdo = klass_RInfo;
1715 __ mov_metadata(mdo, md->constant_encoding());
1716 __ jccb(Assembler::notEqual, not_null);
1717 // Object is null; update MDO and exit
1718 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1719 int header_bits = BitData::null_seen_byte_constant();
1720 __ orb(data_addr, header_bits);
1721 __ jmp(*obj_is_null);
1722 __ bind(not_null);
1723
1724 Label update_done;
1725 Register recv = k_RInfo;
1726 __ load_klass(recv, obj, tmp_load_klass);
1727 type_profile_helper(mdo, md, data, recv, &update_done);
1728
1729 Address nonprofiled_receiver_count_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1730 __ addptr(nonprofiled_receiver_count_addr, DataLayout::counter_increment);
1731
1732 __ bind(update_done);
1733 } else {
1734 __ jcc(Assembler::equal, *obj_is_null);
1735 }
1736
1737 if (!k->is_loaded()) {
1738 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1739 } else {
1740 #ifdef _LP64
1741 __ mov_metadata(k_RInfo, k->constant_encoding());
1742 #endif // _LP64
1743 }
1744 __ verify_oop(obj);
1745
1746 if (op->fast_check()) {
1747 // get object class
1748 // not a safepoint as obj null check happens earlier
1749 #ifdef _LP64
1750 if (UseCompressedClassPointers) {
1751 __ load_klass(Rtmp1, obj, tmp_load_klass);
1752 __ cmpptr(k_RInfo, Rtmp1);
1753 } else {
1754 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1755 }
1756 #else
1757 if (k->is_loaded()) {
1758 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1759 } else {
1760 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1761 }
1762 #endif
1763 __ jcc(Assembler::notEqual, *failure_target);
1764 // successful cast, fall through to profile or jump
1765 } else {
1766 // get object class
1767 // not a safepoint as obj null check happens earlier
1768 __ load_klass(klass_RInfo, obj, tmp_load_klass);
1769 if (k->is_loaded()) {
1770 // See if we get an immediate positive hit
1771 #ifdef _LP64
1772 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1773 #else
1774 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1775 #endif // _LP64
1776 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1777 __ jcc(Assembler::notEqual, *failure_target);
1778 // successful cast, fall through to profile or jump
1779 } else {
1780 // See if we get an immediate positive hit
1781 __ jcc(Assembler::equal, *success_target);
1782 // check for self
1783 #ifdef _LP64
1784 __ cmpptr(klass_RInfo, k_RInfo);
1785 #else
1786 __ cmpklass(klass_RInfo, k->constant_encoding());
1787 #endif // _LP64
1788 __ jcc(Assembler::equal, *success_target);
1789
1790 __ push(klass_RInfo);
1791 #ifdef _LP64
1792 __ push(k_RInfo);
1793 #else
1794 __ pushklass(k->constant_encoding(), noreg);
1795 #endif // _LP64
1796 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1797 __ pop(klass_RInfo);
1798 __ pop(klass_RInfo);
1799 // result is a boolean
1800 __ testl(klass_RInfo, klass_RInfo);
1801 __ jcc(Assembler::equal, *failure_target);
1802 // successful cast, fall through to profile or jump
1803 }
1804 } else {
1805 // perform the fast part of the checking logic
1806 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1807 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1808 __ push(klass_RInfo);
1809 __ push(k_RInfo);
1810 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1811 __ pop(klass_RInfo);
1812 __ pop(k_RInfo);
1813 // result is a boolean
1814 __ testl(k_RInfo, k_RInfo);
1815 __ jcc(Assembler::equal, *failure_target);
1816 // successful cast, fall through to profile or jump
1817 }
1818 }
1819 __ jmp(*success);
1820 }
1821
1822
1823 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1824 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1825 LIR_Code code = op->code();
1826 if (code == lir_store_check) {
1827 Register value = op->object()->as_register();
1828 Register array = op->array()->as_register();
1829 Register k_RInfo = op->tmp1()->as_register();
1830 Register klass_RInfo = op->tmp2()->as_register();
1831 Register Rtmp1 = op->tmp3()->as_register();
1832
1833 CodeStub* stub = op->stub();
1834
1835 // check if it needs to be profiled
1836 ciMethodData* md = nullptr;
1837 ciProfileData* data = nullptr;
1838
1839 if (op->should_profile()) {
1840 ciMethod* method = op->profiled_method();
1841 assert(method != nullptr, "Should have method");
1842 int bci = op->profiled_bci();
1843 md = method->method_data_or_null();
1844 assert(md != nullptr, "Sanity");
1845 data = md->bci_to_data(bci);
1846 assert(data != nullptr, "need data for type check");
1847 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1848 }
1849 Label done;
1850 Label* success_target = &done;
1851 Label* failure_target = stub->entry();
1852
1853 __ testptr(value, value);
1854 if (op->should_profile()) {
1855 Label not_null;
1856 Register mdo = klass_RInfo;
1857 __ mov_metadata(mdo, md->constant_encoding());
1858 __ jccb(Assembler::notEqual, not_null);
1859 // Object is null; update MDO and exit
1860 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1861 int header_bits = BitData::null_seen_byte_constant();
1862 __ orb(data_addr, header_bits);
1863 __ jmp(done);
1864 __ bind(not_null);
1865
1866 Label update_done;
1867 Register recv = k_RInfo;
1868 __ load_klass(recv, value, tmp_load_klass);
1869 type_profile_helper(mdo, md, data, recv, &update_done);
1870
1871 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1872 __ addptr(counter_addr, DataLayout::counter_increment);
1873 __ bind(update_done);
1874 } else {
1875 __ jcc(Assembler::equal, done);
1876 }
1877
1878 add_debug_info_for_null_check_here(op->info_for_exception());
1879 __ load_klass(k_RInfo, array, tmp_load_klass);
1880 __ load_klass(klass_RInfo, value, tmp_load_klass);
1881
1882 // get instance klass (it's already uncompressed)
1883 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1884 // perform the fast part of the checking logic
1885 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1886 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1887 __ push(klass_RInfo);
1888 __ push(k_RInfo);
1889 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1890 __ pop(klass_RInfo);
1891 __ pop(k_RInfo);
1892 // result is a boolean
1893 __ testl(k_RInfo, k_RInfo);
1894 __ jcc(Assembler::equal, *failure_target);
1895 // fall through to the success case
1896
1897 __ bind(done);
1898 } else
1899 if (code == lir_checkcast) {
1900 Register obj = op->object()->as_register();
1901 Register dst = op->result_opr()->as_register();
1902 Label success;
1903 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1904 __ bind(success);
1905 if (dst != obj) {
1906 __ mov(dst, obj);
1907 }
1908 } else
1909 if (code == lir_instanceof) {
1910 Register obj = op->object()->as_register();
1911 Register dst = op->result_opr()->as_register();
1912 Label success, failure, done;
1913 emit_typecheck_helper(op, &success, &failure, &failure);
1914 __ bind(failure);
1915 __ xorptr(dst, dst);
1916 __ jmpb(done);
1917 __ bind(success);
1918 __ movptr(dst, 1);
1919 __ bind(done);
1920 } else {
1921 ShouldNotReachHere();
1922 }
1923
1924 }
1925
1926
1927 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1928 if (LP64_ONLY(false &&) op->code() == lir_cas_long) {
1929 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1930 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1931 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1932 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1933 Register addr = op->addr()->as_register();
1934 __ lock();
1935 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1936
1937 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1938 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1939 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1940 Register newval = op->new_value()->as_register();
1941 Register cmpval = op->cmp_value()->as_register();
1942 assert(cmpval == rax, "wrong register");
1943 assert(newval != noreg, "new val must be register");
1944 assert(cmpval != newval, "cmp and new values must be in different registers");
1945 assert(cmpval != addr, "cmp and addr must be in different registers");
1946 assert(newval != addr, "new value and addr must be in different registers");
1947
1948 if ( op->code() == lir_cas_obj) {
1949 #ifdef _LP64
1950 if (UseCompressedOops) {
1951 __ encode_heap_oop(cmpval);
1952 __ mov(rscratch1, newval);
1953 __ encode_heap_oop(rscratch1);
1954 __ lock();
1955 // cmpval (rax) is implicitly used by this instruction
1956 __ cmpxchgl(rscratch1, Address(addr, 0));
1957 } else
1958 #endif
1959 {
1960 __ lock();
1961 __ cmpxchgptr(newval, Address(addr, 0));
1962 }
1963 } else {
1964 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1965 __ lock();
1966 __ cmpxchgl(newval, Address(addr, 0));
1967 }
1968 #ifdef _LP64
1969 } else if (op->code() == lir_cas_long) {
1970 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1971 Register newval = op->new_value()->as_register_lo();
1972 Register cmpval = op->cmp_value()->as_register_lo();
1973 assert(cmpval == rax, "wrong register");
1974 assert(newval != noreg, "new val must be register");
1975 assert(cmpval != newval, "cmp and new values must be in different registers");
1976 assert(cmpval != addr, "cmp and addr must be in different registers");
1977 assert(newval != addr, "new value and addr must be in different registers");
1978 __ lock();
1979 __ cmpxchgq(newval, Address(addr, 0));
1980 #endif // _LP64
1981 } else {
1982 Unimplemented();
1983 }
1984 }
1985
1986 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1987 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1988 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
1989
1990 Assembler::Condition acond, ncond;
1991 switch (condition) {
1992 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1993 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1994 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1995 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1996 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1997 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1998 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1999 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2000 default: acond = Assembler::equal; ncond = Assembler::notEqual;
2001 ShouldNotReachHere();
2002 }
2003
2004 if (opr1->is_cpu_register()) {
2005 reg2reg(opr1, result);
2006 } else if (opr1->is_stack()) {
2007 stack2reg(opr1, result, result->type());
2008 } else if (opr1->is_constant()) {
2009 const2reg(opr1, result, lir_patch_none, nullptr);
2010 } else {
2011 ShouldNotReachHere();
2012 }
2013
2014 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2015 // optimized version that does not require a branch
2016 if (opr2->is_single_cpu()) {
2017 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2018 __ cmov(ncond, result->as_register(), opr2->as_register());
2019 } else if (opr2->is_double_cpu()) {
2020 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2021 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2022 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2023 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2024 } else if (opr2->is_single_stack()) {
2025 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2026 } else if (opr2->is_double_stack()) {
2027 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2028 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2029 } else {
2030 ShouldNotReachHere();
2031 }
2032
2033 } else {
2034 Label skip;
2035 __ jccb(acond, skip);
2036 if (opr2->is_cpu_register()) {
2037 reg2reg(opr2, result);
2038 } else if (opr2->is_stack()) {
2039 stack2reg(opr2, result, result->type());
2040 } else if (opr2->is_constant()) {
2041 const2reg(opr2, result, lir_patch_none, nullptr);
2042 } else {
2043 ShouldNotReachHere();
2044 }
2045 __ bind(skip);
2046 }
2047 }
2048
2049
2050 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2051 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2052
2053 if (left->is_single_cpu()) {
2054 assert(left == dest, "left and dest must be equal");
2055 Register lreg = left->as_register();
2056
2057 if (right->is_single_cpu()) {
2058 // cpu register - cpu register
2059 Register rreg = right->as_register();
2060 switch (code) {
2061 case lir_add: __ addl (lreg, rreg); break;
2062 case lir_sub: __ subl (lreg, rreg); break;
2063 case lir_mul: __ imull(lreg, rreg); break;
2064 default: ShouldNotReachHere();
2065 }
2066
2067 } else if (right->is_stack()) {
2068 // cpu register - stack
2069 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2070 switch (code) {
2071 case lir_add: __ addl(lreg, raddr); break;
2072 case lir_sub: __ subl(lreg, raddr); break;
2073 default: ShouldNotReachHere();
2074 }
2075
2076 } else if (right->is_constant()) {
2077 // cpu register - constant
2078 jint c = right->as_constant_ptr()->as_jint();
2079 switch (code) {
2080 case lir_add: {
2081 __ incrementl(lreg, c);
2082 break;
2083 }
2084 case lir_sub: {
2085 __ decrementl(lreg, c);
2086 break;
2087 }
2088 default: ShouldNotReachHere();
2089 }
2090
2091 } else {
2092 ShouldNotReachHere();
2093 }
2094
2095 } else if (left->is_double_cpu()) {
2096 assert(left == dest, "left and dest must be equal");
2097 Register lreg_lo = left->as_register_lo();
2098 Register lreg_hi = left->as_register_hi();
2099
2100 if (right->is_double_cpu()) {
2101 // cpu register - cpu register
2102 Register rreg_lo = right->as_register_lo();
2103 Register rreg_hi = right->as_register_hi();
2104 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2105 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2106 switch (code) {
2107 case lir_add:
2108 __ addptr(lreg_lo, rreg_lo);
2109 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2110 break;
2111 case lir_sub:
2112 __ subptr(lreg_lo, rreg_lo);
2113 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2114 break;
2115 case lir_mul:
2116 #ifdef _LP64
2117 __ imulq(lreg_lo, rreg_lo);
2118 #else
2119 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2120 __ imull(lreg_hi, rreg_lo);
2121 __ imull(rreg_hi, lreg_lo);
2122 __ addl (rreg_hi, lreg_hi);
2123 __ mull (rreg_lo);
2124 __ addl (lreg_hi, rreg_hi);
2125 #endif // _LP64
2126 break;
2127 default:
2128 ShouldNotReachHere();
2129 }
2130
2131 } else if (right->is_constant()) {
2132 // cpu register - constant
2133 #ifdef _LP64
2134 jlong c = right->as_constant_ptr()->as_jlong_bits();
2135 __ movptr(r10, (intptr_t) c);
2136 switch (code) {
2137 case lir_add:
2138 __ addptr(lreg_lo, r10);
2139 break;
2140 case lir_sub:
2141 __ subptr(lreg_lo, r10);
2142 break;
2143 default:
2144 ShouldNotReachHere();
2145 }
2146 #else
2147 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2148 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2149 switch (code) {
2150 case lir_add:
2151 __ addptr(lreg_lo, c_lo);
2152 __ adcl(lreg_hi, c_hi);
2153 break;
2154 case lir_sub:
2155 __ subptr(lreg_lo, c_lo);
2156 __ sbbl(lreg_hi, c_hi);
2157 break;
2158 default:
2159 ShouldNotReachHere();
2160 }
2161 #endif // _LP64
2162
2163 } else {
2164 ShouldNotReachHere();
2165 }
2166
2167 } else if (left->is_single_xmm()) {
2168 assert(left == dest, "left and dest must be equal");
2169 XMMRegister lreg = left->as_xmm_float_reg();
2170
2171 if (right->is_single_xmm()) {
2172 XMMRegister rreg = right->as_xmm_float_reg();
2173 switch (code) {
2174 case lir_add: __ addss(lreg, rreg); break;
2175 case lir_sub: __ subss(lreg, rreg); break;
2176 case lir_mul: __ mulss(lreg, rreg); break;
2177 case lir_div: __ divss(lreg, rreg); break;
2178 default: ShouldNotReachHere();
2179 }
2180 } else {
2181 Address raddr;
2182 if (right->is_single_stack()) {
2183 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2184 } else if (right->is_constant()) {
2185 // hack for now
2186 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2187 } else {
2188 ShouldNotReachHere();
2189 }
2190 switch (code) {
2191 case lir_add: __ addss(lreg, raddr); break;
2192 case lir_sub: __ subss(lreg, raddr); break;
2193 case lir_mul: __ mulss(lreg, raddr); break;
2194 case lir_div: __ divss(lreg, raddr); break;
2195 default: ShouldNotReachHere();
2196 }
2197 }
2198
2199 } else if (left->is_double_xmm()) {
2200 assert(left == dest, "left and dest must be equal");
2201
2202 XMMRegister lreg = left->as_xmm_double_reg();
2203 if (right->is_double_xmm()) {
2204 XMMRegister rreg = right->as_xmm_double_reg();
2205 switch (code) {
2206 case lir_add: __ addsd(lreg, rreg); break;
2207 case lir_sub: __ subsd(lreg, rreg); break;
2208 case lir_mul: __ mulsd(lreg, rreg); break;
2209 case lir_div: __ divsd(lreg, rreg); break;
2210 default: ShouldNotReachHere();
2211 }
2212 } else {
2213 Address raddr;
2214 if (right->is_double_stack()) {
2215 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2216 } else if (right->is_constant()) {
2217 // hack for now
2218 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2219 } else {
2220 ShouldNotReachHere();
2221 }
2222 switch (code) {
2223 case lir_add: __ addsd(lreg, raddr); break;
2224 case lir_sub: __ subsd(lreg, raddr); break;
2225 case lir_mul: __ mulsd(lreg, raddr); break;
2226 case lir_div: __ divsd(lreg, raddr); break;
2227 default: ShouldNotReachHere();
2228 }
2229 }
2230
2231 #ifndef _LP64
2232 } else if (left->is_single_fpu()) {
2233 assert(dest->is_single_fpu(), "fpu stack allocation required");
2234
2235 if (right->is_single_fpu()) {
2236 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2237
2238 } else {
2239 assert(left->fpu_regnr() == 0, "left must be on TOS");
2240 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2241
2242 Address raddr;
2243 if (right->is_single_stack()) {
2244 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2245 } else if (right->is_constant()) {
2246 address const_addr = float_constant(right->as_jfloat());
2247 assert(const_addr != nullptr, "incorrect float/double constant maintenance");
2248 // hack for now
2249 raddr = __ as_Address(InternalAddress(const_addr));
2250 } else {
2251 ShouldNotReachHere();
2252 }
2253
2254 switch (code) {
2255 case lir_add: __ fadd_s(raddr); break;
2256 case lir_sub: __ fsub_s(raddr); break;
2257 case lir_mul: __ fmul_s(raddr); break;
2258 case lir_div: __ fdiv_s(raddr); break;
2259 default: ShouldNotReachHere();
2260 }
2261 }
2262
2263 } else if (left->is_double_fpu()) {
2264 assert(dest->is_double_fpu(), "fpu stack allocation required");
2265
2266 if (code == lir_mul || code == lir_div) {
2267 // Double values require special handling for strictfp mul/div on x86
2268 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1()));
2269 __ fmulp(left->fpu_regnrLo() + 1);
2270 }
2271
2272 if (right->is_double_fpu()) {
2273 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2274
2275 } else {
2276 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2277 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2278
2279 Address raddr;
2280 if (right->is_double_stack()) {
2281 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2282 } else if (right->is_constant()) {
2283 // hack for now
2284 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2285 } else {
2286 ShouldNotReachHere();
2287 }
2288
2289 switch (code) {
2290 case lir_add: __ fadd_d(raddr); break;
2291 case lir_sub: __ fsub_d(raddr); break;
2292 case lir_mul: __ fmul_d(raddr); break;
2293 case lir_div: __ fdiv_d(raddr); break;
2294 default: ShouldNotReachHere();
2295 }
2296 }
2297
2298 if (code == lir_mul || code == lir_div) {
2299 // Double values require special handling for strictfp mul/div on x86
2300 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2()));
2301 __ fmulp(dest->fpu_regnrLo() + 1);
2302 }
2303 #endif // !_LP64
2304
2305 } else if (left->is_single_stack() || left->is_address()) {
2306 assert(left == dest, "left and dest must be equal");
2307
2308 Address laddr;
2309 if (left->is_single_stack()) {
2310 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2311 } else if (left->is_address()) {
2312 laddr = as_Address(left->as_address_ptr());
2313 } else {
2314 ShouldNotReachHere();
2315 }
2316
2317 if (right->is_single_cpu()) {
2318 Register rreg = right->as_register();
2319 switch (code) {
2320 case lir_add: __ addl(laddr, rreg); break;
2321 case lir_sub: __ subl(laddr, rreg); break;
2322 default: ShouldNotReachHere();
2323 }
2324 } else if (right->is_constant()) {
2325 jint c = right->as_constant_ptr()->as_jint();
2326 switch (code) {
2327 case lir_add: {
2328 __ incrementl(laddr, c);
2329 break;
2330 }
2331 case lir_sub: {
2332 __ decrementl(laddr, c);
2333 break;
2334 }
2335 default: ShouldNotReachHere();
2336 }
2337 } else {
2338 ShouldNotReachHere();
2339 }
2340
2341 } else {
2342 ShouldNotReachHere();
2343 }
2344 }
2345
2346 #ifndef _LP64
2347 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2348 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2349 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2350 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2351
2352 bool left_is_tos = (left_index == 0);
2353 bool dest_is_tos = (dest_index == 0);
2354 int non_tos_index = (left_is_tos ? right_index : left_index);
2355
2356 switch (code) {
2357 case lir_add:
2358 if (pop_fpu_stack) __ faddp(non_tos_index);
2359 else if (dest_is_tos) __ fadd (non_tos_index);
2360 else __ fadda(non_tos_index);
2361 break;
2362
2363 case lir_sub:
2364 if (left_is_tos) {
2365 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2366 else if (dest_is_tos) __ fsub (non_tos_index);
2367 else __ fsubra(non_tos_index);
2368 } else {
2369 if (pop_fpu_stack) __ fsubp (non_tos_index);
2370 else if (dest_is_tos) __ fsubr (non_tos_index);
2371 else __ fsuba (non_tos_index);
2372 }
2373 break;
2374
2375 case lir_mul:
2376 if (pop_fpu_stack) __ fmulp(non_tos_index);
2377 else if (dest_is_tos) __ fmul (non_tos_index);
2378 else __ fmula(non_tos_index);
2379 break;
2380
2381 case lir_div:
2382 if (left_is_tos) {
2383 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2384 else if (dest_is_tos) __ fdiv (non_tos_index);
2385 else __ fdivra(non_tos_index);
2386 } else {
2387 if (pop_fpu_stack) __ fdivp (non_tos_index);
2388 else if (dest_is_tos) __ fdivr (non_tos_index);
2389 else __ fdiva (non_tos_index);
2390 }
2391 break;
2392
2393 case lir_rem:
2394 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2395 __ fremr(noreg);
2396 break;
2397
2398 default:
2399 ShouldNotReachHere();
2400 }
2401 }
2402 #endif // _LP64
2403
2404
2405 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2406 if (value->is_double_xmm()) {
2407 switch(code) {
2408 case lir_abs :
2409 {
2410 #ifdef _LP64
2411 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2412 assert(tmp->is_valid(), "need temporary");
2413 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2414 } else
2415 #endif
2416 {
2417 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2418 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2419 }
2420 assert(!tmp->is_valid(), "do not need temporary");
2421 __ andpd(dest->as_xmm_double_reg(),
2422 ExternalAddress(LIR_Assembler::double_signmask_pool),
2423 rscratch1);
2424 }
2425 }
2426 break;
2427
2428 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2429 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2430 default : ShouldNotReachHere();
2431 }
2432
2433 #ifndef _LP64
2434 } else if (value->is_double_fpu()) {
2435 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2436 switch(code) {
2437 case lir_abs : __ fabs() ; break;
2438 case lir_sqrt : __ fsqrt(); break;
2439 default : ShouldNotReachHere();
2440 }
2441 #endif // !_LP64
2442 } else if (code == lir_f2hf) {
2443 __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg());
2444 } else if (code == lir_hf2f) {
2445 __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register());
2446 } else {
2447 Unimplemented();
2448 }
2449 }
2450
2451 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2452 // assert(left->destroys_register(), "check");
2453 if (left->is_single_cpu()) {
2454 Register reg = left->as_register();
2455 if (right->is_constant()) {
2456 int val = right->as_constant_ptr()->as_jint();
2457 switch (code) {
2458 case lir_logic_and: __ andl (reg, val); break;
2459 case lir_logic_or: __ orl (reg, val); break;
2460 case lir_logic_xor: __ xorl (reg, val); break;
2461 default: ShouldNotReachHere();
2462 }
2463 } else if (right->is_stack()) {
2464 // added support for stack operands
2465 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2466 switch (code) {
2467 case lir_logic_and: __ andl (reg, raddr); break;
2468 case lir_logic_or: __ orl (reg, raddr); break;
2469 case lir_logic_xor: __ xorl (reg, raddr); break;
2470 default: ShouldNotReachHere();
2471 }
2472 } else {
2473 Register rright = right->as_register();
2474 switch (code) {
2475 case lir_logic_and: __ andptr (reg, rright); break;
2476 case lir_logic_or : __ orptr (reg, rright); break;
2477 case lir_logic_xor: __ xorptr (reg, rright); break;
2478 default: ShouldNotReachHere();
2479 }
2480 }
2481 move_regs(reg, dst->as_register());
2482 } else {
2483 Register l_lo = left->as_register_lo();
2484 Register l_hi = left->as_register_hi();
2485 if (right->is_constant()) {
2486 #ifdef _LP64
2487 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2488 switch (code) {
2489 case lir_logic_and:
2490 __ andq(l_lo, rscratch1);
2491 break;
2492 case lir_logic_or:
2493 __ orq(l_lo, rscratch1);
2494 break;
2495 case lir_logic_xor:
2496 __ xorq(l_lo, rscratch1);
2497 break;
2498 default: ShouldNotReachHere();
2499 }
2500 #else
2501 int r_lo = right->as_constant_ptr()->as_jint_lo();
2502 int r_hi = right->as_constant_ptr()->as_jint_hi();
2503 switch (code) {
2504 case lir_logic_and:
2505 __ andl(l_lo, r_lo);
2506 __ andl(l_hi, r_hi);
2507 break;
2508 case lir_logic_or:
2509 __ orl(l_lo, r_lo);
2510 __ orl(l_hi, r_hi);
2511 break;
2512 case lir_logic_xor:
2513 __ xorl(l_lo, r_lo);
2514 __ xorl(l_hi, r_hi);
2515 break;
2516 default: ShouldNotReachHere();
2517 }
2518 #endif // _LP64
2519 } else {
2520 #ifdef _LP64
2521 Register r_lo;
2522 if (is_reference_type(right->type())) {
2523 r_lo = right->as_register();
2524 } else {
2525 r_lo = right->as_register_lo();
2526 }
2527 #else
2528 Register r_lo = right->as_register_lo();
2529 Register r_hi = right->as_register_hi();
2530 assert(l_lo != r_hi, "overwriting registers");
2531 #endif
2532 switch (code) {
2533 case lir_logic_and:
2534 __ andptr(l_lo, r_lo);
2535 NOT_LP64(__ andptr(l_hi, r_hi);)
2536 break;
2537 case lir_logic_or:
2538 __ orptr(l_lo, r_lo);
2539 NOT_LP64(__ orptr(l_hi, r_hi);)
2540 break;
2541 case lir_logic_xor:
2542 __ xorptr(l_lo, r_lo);
2543 NOT_LP64(__ xorptr(l_hi, r_hi);)
2544 break;
2545 default: ShouldNotReachHere();
2546 }
2547 }
2548
2549 Register dst_lo = dst->as_register_lo();
2550 Register dst_hi = dst->as_register_hi();
2551
2552 #ifdef _LP64
2553 move_regs(l_lo, dst_lo);
2554 #else
2555 if (dst_lo == l_hi) {
2556 assert(dst_hi != l_lo, "overwriting registers");
2557 move_regs(l_hi, dst_hi);
2558 move_regs(l_lo, dst_lo);
2559 } else {
2560 assert(dst_lo != l_hi, "overwriting registers");
2561 move_regs(l_lo, dst_lo);
2562 move_regs(l_hi, dst_hi);
2563 }
2564 #endif // _LP64
2565 }
2566 }
2567
2568
2569 // we assume that rax, and rdx can be overwritten
2570 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2571
2572 assert(left->is_single_cpu(), "left must be register");
2573 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2574 assert(result->is_single_cpu(), "result must be register");
2575
2576 // assert(left->destroys_register(), "check");
2577 // assert(right->destroys_register(), "check");
2578
2579 Register lreg = left->as_register();
2580 Register dreg = result->as_register();
2581
2582 if (right->is_constant()) {
2583 jint divisor = right->as_constant_ptr()->as_jint();
2584 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2585 if (code == lir_idiv) {
2586 assert(lreg == rax, "must be rax,");
2587 assert(temp->as_register() == rdx, "tmp register must be rdx");
2588 __ cdql(); // sign extend into rdx:rax
2589 if (divisor == 2) {
2590 __ subl(lreg, rdx);
2591 } else {
2592 __ andl(rdx, divisor - 1);
2593 __ addl(lreg, rdx);
2594 }
2595 __ sarl(lreg, log2i_exact(divisor));
2596 move_regs(lreg, dreg);
2597 } else if (code == lir_irem) {
2598 Label done;
2599 __ mov(dreg, lreg);
2600 __ andl(dreg, 0x80000000 | (divisor - 1));
2601 __ jcc(Assembler::positive, done);
2602 __ decrement(dreg);
2603 __ orl(dreg, ~(divisor - 1));
2604 __ increment(dreg);
2605 __ bind(done);
2606 } else {
2607 ShouldNotReachHere();
2608 }
2609 } else {
2610 Register rreg = right->as_register();
2611 assert(lreg == rax, "left register must be rax,");
2612 assert(rreg != rdx, "right register must not be rdx");
2613 assert(temp->as_register() == rdx, "tmp register must be rdx");
2614
2615 move_regs(lreg, rax);
2616
2617 int idivl_offset = __ corrected_idivl(rreg);
2618 if (ImplicitDiv0Checks) {
2619 add_debug_info_for_div0(idivl_offset, info);
2620 }
2621 if (code == lir_irem) {
2622 move_regs(rdx, dreg); // result is in rdx
2623 } else {
2624 move_regs(rax, dreg);
2625 }
2626 }
2627 }
2628
2629
2630 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2631 if (opr1->is_single_cpu()) {
2632 Register reg1 = opr1->as_register();
2633 if (opr2->is_single_cpu()) {
2634 // cpu register - cpu register
2635 if (is_reference_type(opr1->type())) {
2636 __ cmpoop(reg1, opr2->as_register());
2637 } else {
2638 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2639 __ cmpl(reg1, opr2->as_register());
2640 }
2641 } else if (opr2->is_stack()) {
2642 // cpu register - stack
2643 if (is_reference_type(opr1->type())) {
2644 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2645 } else {
2646 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2647 }
2648 } else if (opr2->is_constant()) {
2649 // cpu register - constant
2650 LIR_Const* c = opr2->as_constant_ptr();
2651 if (c->type() == T_INT) {
2652 jint i = c->as_jint();
2653 if (i == 0) {
2654 __ testl(reg1, reg1);
2655 } else {
2656 __ cmpl(reg1, i);
2657 }
2658 } else if (c->type() == T_METADATA) {
2659 // All we need for now is a comparison with null for equality.
2660 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2661 Metadata* m = c->as_metadata();
2662 if (m == nullptr) {
2663 __ testptr(reg1, reg1);
2664 } else {
2665 ShouldNotReachHere();
2666 }
2667 } else if (is_reference_type(c->type())) {
2668 // In 64bit oops are single register
2669 jobject o = c->as_jobject();
2670 if (o == nullptr) {
2671 __ testptr(reg1, reg1);
2672 } else {
2673 __ cmpoop(reg1, o, rscratch1);
2674 }
2675 } else {
2676 fatal("unexpected type: %s", basictype_to_str(c->type()));
2677 }
2678 // cpu register - address
2679 } else if (opr2->is_address()) {
2680 if (op->info() != nullptr) {
2681 add_debug_info_for_null_check_here(op->info());
2682 }
2683 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2684 } else {
2685 ShouldNotReachHere();
2686 }
2687
2688 } else if(opr1->is_double_cpu()) {
2689 Register xlo = opr1->as_register_lo();
2690 Register xhi = opr1->as_register_hi();
2691 if (opr2->is_double_cpu()) {
2692 #ifdef _LP64
2693 __ cmpptr(xlo, opr2->as_register_lo());
2694 #else
2695 // cpu register - cpu register
2696 Register ylo = opr2->as_register_lo();
2697 Register yhi = opr2->as_register_hi();
2698 __ subl(xlo, ylo);
2699 __ sbbl(xhi, yhi);
2700 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2701 __ orl(xhi, xlo);
2702 }
2703 #endif // _LP64
2704 } else if (opr2->is_constant()) {
2705 // cpu register - constant 0
2706 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2707 #ifdef _LP64
2708 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2709 #else
2710 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2711 __ orl(xhi, xlo);
2712 #endif // _LP64
2713 } else {
2714 ShouldNotReachHere();
2715 }
2716
2717 } else if (opr1->is_single_xmm()) {
2718 XMMRegister reg1 = opr1->as_xmm_float_reg();
2719 if (opr2->is_single_xmm()) {
2720 // xmm register - xmm register
2721 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2722 } else if (opr2->is_stack()) {
2723 // xmm register - stack
2724 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2725 } else if (opr2->is_constant()) {
2726 // xmm register - constant
2727 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2728 } else if (opr2->is_address()) {
2729 // xmm register - address
2730 if (op->info() != nullptr) {
2731 add_debug_info_for_null_check_here(op->info());
2732 }
2733 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2734 } else {
2735 ShouldNotReachHere();
2736 }
2737
2738 } else if (opr1->is_double_xmm()) {
2739 XMMRegister reg1 = opr1->as_xmm_double_reg();
2740 if (opr2->is_double_xmm()) {
2741 // xmm register - xmm register
2742 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2743 } else if (opr2->is_stack()) {
2744 // xmm register - stack
2745 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2746 } else if (opr2->is_constant()) {
2747 // xmm register - constant
2748 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2749 } else if (opr2->is_address()) {
2750 // xmm register - address
2751 if (op->info() != nullptr) {
2752 add_debug_info_for_null_check_here(op->info());
2753 }
2754 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2755 } else {
2756 ShouldNotReachHere();
2757 }
2758
2759 #ifndef _LP64
2760 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2761 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2762 assert(opr2->is_fpu_register(), "both must be registers");
2763 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2764 #endif // LP64
2765
2766 } else if (opr1->is_address() && opr2->is_constant()) {
2767 LIR_Const* c = opr2->as_constant_ptr();
2768 #ifdef _LP64
2769 if (is_reference_type(c->type())) {
2770 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2771 __ movoop(rscratch1, c->as_jobject());
2772 }
2773 #endif // LP64
2774 if (op->info() != nullptr) {
2775 add_debug_info_for_null_check_here(op->info());
2776 }
2777 // special case: address - constant
2778 LIR_Address* addr = opr1->as_address_ptr();
2779 if (c->type() == T_INT) {
2780 __ cmpl(as_Address(addr), c->as_jint());
2781 } else if (is_reference_type(c->type())) {
2782 #ifdef _LP64
2783 // %%% Make this explode if addr isn't reachable until we figure out a
2784 // better strategy by giving noreg as the temp for as_Address
2785 __ cmpoop(rscratch1, as_Address(addr, noreg));
2786 #else
2787 __ cmpoop(as_Address(addr), c->as_jobject());
2788 #endif // _LP64
2789 } else {
2790 ShouldNotReachHere();
2791 }
2792
2793 } else {
2794 ShouldNotReachHere();
2795 }
2796 }
2797
2798 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2799 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2800 if (left->is_single_xmm()) {
2801 assert(right->is_single_xmm(), "must match");
2802 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2803 } else if (left->is_double_xmm()) {
2804 assert(right->is_double_xmm(), "must match");
2805 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2806
2807 } else {
2808 #ifdef _LP64
2809 ShouldNotReachHere();
2810 #else
2811 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2812 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2813
2814 assert(left->fpu() == 0, "left must be on TOS");
2815 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2816 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2817 #endif // LP64
2818 }
2819 } else {
2820 assert(code == lir_cmp_l2i, "check");
2821 #ifdef _LP64
2822 Label done;
2823 Register dest = dst->as_register();
2824 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2825 __ movl(dest, -1);
2826 __ jccb(Assembler::less, done);
2827 __ setb(Assembler::notZero, dest);
2828 __ movzbl(dest, dest);
2829 __ bind(done);
2830 #else
2831 __ lcmp2int(left->as_register_hi(),
2832 left->as_register_lo(),
2833 right->as_register_hi(),
2834 right->as_register_lo());
2835 move_regs(left->as_register_hi(), dst->as_register());
2836 #endif // _LP64
2837 }
2838 }
2839
2840
2841 void LIR_Assembler::align_call(LIR_Code code) {
2842 // make sure that the displacement word of the call ends up word aligned
2843 int offset = __ offset();
2844 switch (code) {
2845 case lir_static_call:
2846 case lir_optvirtual_call:
2847 case lir_dynamic_call:
2848 offset += NativeCall::displacement_offset;
2849 break;
2850 case lir_icvirtual_call:
2851 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size_rex;
2852 break;
2853 default: ShouldNotReachHere();
2854 }
2855 __ align(BytesPerWord, offset);
2856 }
2857
2858
2859 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2860 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2861 "must be aligned");
2862 __ call(AddressLiteral(op->addr(), rtype));
2863 add_call_info(code_offset(), op->info());
2864 __ post_call_nop();
2865 }
2866
2867
2868 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2869 __ ic_call(op->addr());
2870 add_call_info(code_offset(), op->info());
2871 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2872 "must be aligned");
2873 __ post_call_nop();
2874 }
2875
2876
2877 void LIR_Assembler::emit_static_call_stub() {
2878 address call_pc = __ pc();
2879 address stub = __ start_a_stub(call_stub_size());
2880 if (stub == nullptr) {
2881 bailout("static call stub overflow");
2882 return;
2883 }
2884
2885 int start = __ offset();
2886
2887 // make sure that the displacement word of the call ends up word aligned
2888 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size_rex + NativeCall::displacement_offset);
2889 __ relocate(static_stub_Relocation::spec(call_pc));
2890 __ mov_metadata(rbx, (Metadata*)nullptr);
2891 // must be set to -1 at code generation time
2892 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2893 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2894 __ jump(RuntimeAddress(__ pc()));
2895
2896 assert(__ offset() - start <= call_stub_size(), "stub too big");
2897 __ end_a_stub();
2898 }
2899
2900
2901 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2902 assert(exceptionOop->as_register() == rax, "must match");
2903 assert(exceptionPC->as_register() == rdx, "must match");
2904
2905 // exception object is not added to oop map by LinearScan
2906 // (LinearScan assumes that no oops are in fixed registers)
2907 info->add_register_oop(exceptionOop);
2908 C1StubId unwind_id;
2909
2910 // get current pc information
2911 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2912 int pc_for_athrow_offset = __ offset();
2913 InternalAddress pc_for_athrow(__ pc());
2914 __ lea(exceptionPC->as_register(), pc_for_athrow);
2915 add_call_info(pc_for_athrow_offset, info); // for exception handler
2916
2917 __ verify_not_null_oop(rax);
2918 // search an exception handler (rax: exception oop, rdx: throwing pc)
2919 if (compilation()->has_fpu_code()) {
2920 unwind_id = C1StubId::handle_exception_id;
2921 } else {
2922 unwind_id = C1StubId::handle_exception_nofpu_id;
2923 }
2924 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2925
2926 // enough room for two byte trap
2927 __ nop();
2928 }
2929
2930
2931 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2932 assert(exceptionOop->as_register() == rax, "must match");
2933
2934 __ jmp(_unwind_handler_entry);
2935 }
2936
2937
2938 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2939
2940 // optimized version for linear scan:
2941 // * count must be already in ECX (guaranteed by LinearScan)
2942 // * left and dest must be equal
2943 // * tmp must be unused
2944 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2945 assert(left == dest, "left and dest must be equal");
2946 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2947
2948 if (left->is_single_cpu()) {
2949 Register value = left->as_register();
2950 assert(value != SHIFT_count, "left cannot be ECX");
2951
2952 switch (code) {
2953 case lir_shl: __ shll(value); break;
2954 case lir_shr: __ sarl(value); break;
2955 case lir_ushr: __ shrl(value); break;
2956 default: ShouldNotReachHere();
2957 }
2958 } else if (left->is_double_cpu()) {
2959 Register lo = left->as_register_lo();
2960 Register hi = left->as_register_hi();
2961 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2962 #ifdef _LP64
2963 switch (code) {
2964 case lir_shl: __ shlptr(lo); break;
2965 case lir_shr: __ sarptr(lo); break;
2966 case lir_ushr: __ shrptr(lo); break;
2967 default: ShouldNotReachHere();
2968 }
2969 #else
2970
2971 switch (code) {
2972 case lir_shl: __ lshl(hi, lo); break;
2973 case lir_shr: __ lshr(hi, lo, true); break;
2974 case lir_ushr: __ lshr(hi, lo, false); break;
2975 default: ShouldNotReachHere();
2976 }
2977 #endif // LP64
2978 } else {
2979 ShouldNotReachHere();
2980 }
2981 }
2982
2983
2984 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2985 if (dest->is_single_cpu()) {
2986 // first move left into dest so that left is not destroyed by the shift
2987 Register value = dest->as_register();
2988 count = count & 0x1F; // Java spec
2989
2990 move_regs(left->as_register(), value);
2991 switch (code) {
2992 case lir_shl: __ shll(value, count); break;
2993 case lir_shr: __ sarl(value, count); break;
2994 case lir_ushr: __ shrl(value, count); break;
2995 default: ShouldNotReachHere();
2996 }
2997 } else if (dest->is_double_cpu()) {
2998 #ifndef _LP64
2999 Unimplemented();
3000 #else
3001 // first move left into dest so that left is not destroyed by the shift
3002 Register value = dest->as_register_lo();
3003 count = count & 0x1F; // Java spec
3004
3005 move_regs(left->as_register_lo(), value);
3006 switch (code) {
3007 case lir_shl: __ shlptr(value, count); break;
3008 case lir_shr: __ sarptr(value, count); break;
3009 case lir_ushr: __ shrptr(value, count); break;
3010 default: ShouldNotReachHere();
3011 }
3012 #endif // _LP64
3013 } else {
3014 ShouldNotReachHere();
3015 }
3016 }
3017
3018
3019 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3020 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3021 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3022 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3023 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3024 }
3025
3026
3027 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3028 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3029 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3030 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3031 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3032 }
3033
3034
3035 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3036 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3037 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3038 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3039 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1);
3040 }
3041
3042
3043 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3044 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3045 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3046 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3047 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1);
3048 }
3049
3050
3051 // This code replaces a call to arraycopy; no exception may
3052 // be thrown in this code, they must be thrown in the System.arraycopy
3053 // activation frame; we could save some checks if this would not be the case
3054 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3055 ciArrayKlass* default_type = op->expected_type();
3056 Register src = op->src()->as_register();
3057 Register dst = op->dst()->as_register();
3058 Register src_pos = op->src_pos()->as_register();
3059 Register dst_pos = op->dst_pos()->as_register();
3060 Register length = op->length()->as_register();
3061 Register tmp = op->tmp()->as_register();
3062 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3063 Register tmp2 = UseCompactObjectHeaders ? rscratch2 : noreg;
3064
3065 CodeStub* stub = op->stub();
3066 int flags = op->flags();
3067 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
3068 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3069
3070 // if we don't know anything, just go through the generic arraycopy
3071 if (default_type == nullptr) {
3072 // save outgoing arguments on stack in case call to System.arraycopy is needed
3073 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3074 // for interpreter calling conventions. Now we have to do it in new style conventions.
3075 // For the moment until C1 gets the new register allocator I just force all the
3076 // args to the right place (except the register args) and then on the back side
3077 // reload the register args properly if we go slow path. Yuck
3078
3079 // These are proper for the calling convention
3080 store_parameter(length, 2);
3081 store_parameter(dst_pos, 1);
3082 store_parameter(dst, 0);
3083
3084 // these are just temporary placements until we need to reload
3085 store_parameter(src_pos, 3);
3086 store_parameter(src, 4);
3087 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3088
3089 address copyfunc_addr = StubRoutines::generic_arraycopy();
3090 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
3091
3092 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3093 #ifdef _LP64
3094 // The arguments are in java calling convention so we can trivially shift them to C
3095 // convention
3096 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3097 __ mov(c_rarg0, j_rarg0);
3098 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3099 __ mov(c_rarg1, j_rarg1);
3100 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3101 __ mov(c_rarg2, j_rarg2);
3102 assert_different_registers(c_rarg3, j_rarg4);
3103 __ mov(c_rarg3, j_rarg3);
3104 #ifdef _WIN64
3105 // Allocate abi space for args but be sure to keep stack aligned
3106 __ subptr(rsp, 6*wordSize);
3107 store_parameter(j_rarg4, 4);
3108 #ifndef PRODUCT
3109 if (PrintC1Statistics) {
3110 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3111 }
3112 #endif
3113 __ call(RuntimeAddress(copyfunc_addr));
3114 __ addptr(rsp, 6*wordSize);
3115 #else
3116 __ mov(c_rarg4, j_rarg4);
3117 #ifndef PRODUCT
3118 if (PrintC1Statistics) {
3119 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3120 }
3121 #endif
3122 __ call(RuntimeAddress(copyfunc_addr));
3123 #endif // _WIN64
3124 #else
3125 __ push(length);
3126 __ push(dst_pos);
3127 __ push(dst);
3128 __ push(src_pos);
3129 __ push(src);
3130
3131 #ifndef PRODUCT
3132 if (PrintC1Statistics) {
3133 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3134 }
3135 #endif
3136 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3137
3138 #endif // _LP64
3139
3140 __ testl(rax, rax);
3141 __ jcc(Assembler::equal, *stub->continuation());
3142
3143 __ mov(tmp, rax);
3144 __ xorl(tmp, -1);
3145
3146 // Reload values from the stack so they are where the stub
3147 // expects them.
3148 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3149 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3150 __ movptr (length, Address(rsp, 2*BytesPerWord));
3151 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3152 __ movptr (src, Address(rsp, 4*BytesPerWord));
3153
3154 __ subl(length, tmp);
3155 __ addl(src_pos, tmp);
3156 __ addl(dst_pos, tmp);
3157 __ jmp(*stub->entry());
3158
3159 __ bind(*stub->continuation());
3160 return;
3161 }
3162
3163 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3164
3165 int elem_size = type2aelembytes(basic_type);
3166 Address::ScaleFactor scale;
3167
3168 switch (elem_size) {
3169 case 1 :
3170 scale = Address::times_1;
3171 break;
3172 case 2 :
3173 scale = Address::times_2;
3174 break;
3175 case 4 :
3176 scale = Address::times_4;
3177 break;
3178 case 8 :
3179 scale = Address::times_8;
3180 break;
3181 default:
3182 scale = Address::no_scale;
3183 ShouldNotReachHere();
3184 }
3185
3186 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3187 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3188
3189 // length and pos's are all sign extended at this point on 64bit
3190
3191 // test for null
3192 if (flags & LIR_OpArrayCopy::src_null_check) {
3193 __ testptr(src, src);
3194 __ jcc(Assembler::zero, *stub->entry());
3195 }
3196 if (flags & LIR_OpArrayCopy::dst_null_check) {
3197 __ testptr(dst, dst);
3198 __ jcc(Assembler::zero, *stub->entry());
3199 }
3200
3201 // If the compiler was not able to prove that exact type of the source or the destination
3202 // of the arraycopy is an array type, check at runtime if the source or the destination is
3203 // an instance type.
3204 if (flags & LIR_OpArrayCopy::type_check) {
3205 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3206 __ load_klass(tmp, dst, tmp_load_klass);
3207 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3208 __ jcc(Assembler::greaterEqual, *stub->entry());
3209 }
3210
3211 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3212 __ load_klass(tmp, src, tmp_load_klass);
3213 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3214 __ jcc(Assembler::greaterEqual, *stub->entry());
3215 }
3216 }
3217
3218 // check if negative
3219 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3220 __ testl(src_pos, src_pos);
3221 __ jcc(Assembler::less, *stub->entry());
3222 }
3223 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3224 __ testl(dst_pos, dst_pos);
3225 __ jcc(Assembler::less, *stub->entry());
3226 }
3227
3228 if (flags & LIR_OpArrayCopy::src_range_check) {
3229 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3230 __ cmpl(tmp, src_length_addr);
3231 __ jcc(Assembler::above, *stub->entry());
3232 }
3233 if (flags & LIR_OpArrayCopy::dst_range_check) {
3234 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3235 __ cmpl(tmp, dst_length_addr);
3236 __ jcc(Assembler::above, *stub->entry());
3237 }
3238
3239 if (flags & LIR_OpArrayCopy::length_positive_check) {
3240 __ testl(length, length);
3241 __ jcc(Assembler::less, *stub->entry());
3242 }
3243
3244 #ifdef _LP64
3245 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3246 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3247 #endif
3248
3249 if (flags & LIR_OpArrayCopy::type_check) {
3250 // We don't know the array types are compatible
3251 if (basic_type != T_OBJECT) {
3252 // Simple test for basic type arrays
3253 __ cmp_klasses_from_objects(src, dst, tmp, tmp2);
3254 __ jcc(Assembler::notEqual, *stub->entry());
3255 } else {
3256 // For object arrays, if src is a sub class of dst then we can
3257 // safely do the copy.
3258 Label cont, slow;
3259
3260 __ push(src);
3261 __ push(dst);
3262
3263 __ load_klass(src, src, tmp_load_klass);
3264 __ load_klass(dst, dst, tmp_load_klass);
3265
3266 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
3267
3268 __ push(src);
3269 __ push(dst);
3270 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
3271 __ pop(dst);
3272 __ pop(src);
3273
3274 __ testl(src, src);
3275 __ jcc(Assembler::notEqual, cont);
3276
3277 __ bind(slow);
3278 __ pop(dst);
3279 __ pop(src);
3280
3281 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3282 if (copyfunc_addr != nullptr) { // use stub if available
3283 // src is not a sub class of dst so we have to do a
3284 // per-element check.
3285
3286 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3287 if ((flags & mask) != mask) {
3288 // Check that at least both of them object arrays.
3289 assert(flags & mask, "one of the two should be known to be an object array");
3290
3291 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3292 __ load_klass(tmp, src, tmp_load_klass);
3293 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3294 __ load_klass(tmp, dst, tmp_load_klass);
3295 }
3296 int lh_offset = in_bytes(Klass::layout_helper_offset());
3297 Address klass_lh_addr(tmp, lh_offset);
3298 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3299 __ cmpl(klass_lh_addr, objArray_lh);
3300 __ jcc(Assembler::notEqual, *stub->entry());
3301 }
3302
3303 // Spill because stubs can use any register they like and it's
3304 // easier to restore just those that we care about.
3305 store_parameter(dst, 0);
3306 store_parameter(dst_pos, 1);
3307 store_parameter(length, 2);
3308 store_parameter(src_pos, 3);
3309 store_parameter(src, 4);
3310
3311 #ifndef _LP64
3312 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3313 __ movptr(tmp, dst_klass_addr);
3314 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3315 __ push(tmp);
3316 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3317 __ push(tmp);
3318 __ push(length);
3319 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3320 __ push(tmp);
3321 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3322 __ push(tmp);
3323
3324 __ call_VM_leaf(copyfunc_addr, 5);
3325 #else
3326 __ movl2ptr(length, length); //higher 32bits must be null
3327
3328 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3329 assert_different_registers(c_rarg0, dst, dst_pos, length);
3330 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3331 assert_different_registers(c_rarg1, dst, length);
3332
3333 __ mov(c_rarg2, length);
3334 assert_different_registers(c_rarg2, dst);
3335
3336 #ifdef _WIN64
3337 // Allocate abi space for args but be sure to keep stack aligned
3338 __ subptr(rsp, 6*wordSize);
3339 __ load_klass(c_rarg3, dst, tmp_load_klass);
3340 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3341 store_parameter(c_rarg3, 4);
3342 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3343 __ call(RuntimeAddress(copyfunc_addr));
3344 __ addptr(rsp, 6*wordSize);
3345 #else
3346 __ load_klass(c_rarg4, dst, tmp_load_klass);
3347 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3348 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3349 __ call(RuntimeAddress(copyfunc_addr));
3350 #endif
3351
3352 #endif
3353
3354 #ifndef PRODUCT
3355 if (PrintC1Statistics) {
3356 Label failed;
3357 __ testl(rax, rax);
3358 __ jcc(Assembler::notZero, failed);
3359 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1);
3360 __ bind(failed);
3361 }
3362 #endif
3363
3364 __ testl(rax, rax);
3365 __ jcc(Assembler::zero, *stub->continuation());
3366
3367 #ifndef PRODUCT
3368 if (PrintC1Statistics) {
3369 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1);
3370 }
3371 #endif
3372
3373 __ mov(tmp, rax);
3374
3375 __ xorl(tmp, -1);
3376
3377 // Restore previously spilled arguments
3378 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3379 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3380 __ movptr (length, Address(rsp, 2*BytesPerWord));
3381 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3382 __ movptr (src, Address(rsp, 4*BytesPerWord));
3383
3384
3385 __ subl(length, tmp);
3386 __ addl(src_pos, tmp);
3387 __ addl(dst_pos, tmp);
3388 }
3389
3390 __ jmp(*stub->entry());
3391
3392 __ bind(cont);
3393 __ pop(dst);
3394 __ pop(src);
3395 }
3396 }
3397
3398 #ifdef ASSERT
3399 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3400 // Sanity check the known type with the incoming class. For the
3401 // primitive case the types must match exactly with src.klass and
3402 // dst.klass each exactly matching the default type. For the
3403 // object array case, if no type check is needed then either the
3404 // dst type is exactly the expected type and the src type is a
3405 // subtype which we can't check or src is the same array as dst
3406 // but not necessarily exactly of type default_type.
3407 Label known_ok, halt;
3408 __ mov_metadata(tmp, default_type->constant_encoding());
3409 #ifdef _LP64
3410 if (UseCompressedClassPointers) {
3411 __ encode_klass_not_null(tmp, rscratch1);
3412 }
3413 #endif
3414
3415 if (basic_type != T_OBJECT) {
3416 __ cmp_klass(tmp, dst, tmp2);
3417 __ jcc(Assembler::notEqual, halt);
3418 __ cmp_klass(tmp, src, tmp2);
3419 __ jcc(Assembler::equal, known_ok);
3420 } else {
3421 __ cmp_klass(tmp, dst, tmp2);
3422 __ jcc(Assembler::equal, known_ok);
3423 __ cmpptr(src, dst);
3424 __ jcc(Assembler::equal, known_ok);
3425 }
3426 __ bind(halt);
3427 __ stop("incorrect type information in arraycopy");
3428 __ bind(known_ok);
3429 }
3430 #endif
3431
3432 #ifndef PRODUCT
3433 if (PrintC1Statistics) {
3434 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1);
3435 }
3436 #endif
3437
3438 #ifdef _LP64
3439 assert_different_registers(c_rarg0, dst, dst_pos, length);
3440 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3441 assert_different_registers(c_rarg1, length);
3442 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3443 __ mov(c_rarg2, length);
3444
3445 #else
3446 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3447 store_parameter(tmp, 0);
3448 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3449 store_parameter(tmp, 1);
3450 store_parameter(length, 2);
3451 #endif // _LP64
3452
3453 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3454 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3455 const char *name;
3456 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3457 __ call_VM_leaf(entry, 0);
3458
3459 if (stub != nullptr) {
3460 __ bind(*stub->continuation());
3461 }
3462 }
3463
3464 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3465 assert(op->crc()->is_single_cpu(), "crc must be register");
3466 assert(op->val()->is_single_cpu(), "byte value must be register");
3467 assert(op->result_opr()->is_single_cpu(), "result must be register");
3468 Register crc = op->crc()->as_register();
3469 Register val = op->val()->as_register();
3470 Register res = op->result_opr()->as_register();
3471
3472 assert_different_registers(val, crc, res);
3473
3474 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3475 __ notl(crc); // ~crc
3476 __ update_byte_crc32(crc, val, res);
3477 __ notl(crc); // ~crc
3478 __ mov(res, crc);
3479 }
3480
3481 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3482 Register obj = op->obj_opr()->as_register(); // may not be an oop
3483 Register hdr = op->hdr_opr()->as_register();
3484 Register lock = op->lock_opr()->as_register();
3485 if (LockingMode == LM_MONITOR) {
3486 if (op->info() != nullptr) {
3487 add_debug_info_for_null_check_here(op->info());
3488 __ null_check(obj);
3489 }
3490 __ jmp(*op->stub()->entry());
3491 } else if (op->code() == lir_lock) {
3492 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3493 Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg;
3494 // add debug info for NullPointerException only if one is possible
3495 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
3496 if (op->info() != nullptr) {
3497 add_debug_info_for_null_check(null_check_offset, op->info());
3498 }
3499 // done
3500 } else if (op->code() == lir_unlock) {
3501 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3502 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3503 } else {
3504 Unimplemented();
3505 }
3506 __ bind(*op->stub()->continuation());
3507 }
3508
3509 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
3510 Register obj = op->obj()->as_pointer_register();
3511 Register result = op->result_opr()->as_pointer_register();
3512
3513 CodeEmitInfo* info = op->info();
3514 if (info != nullptr) {
3515 add_debug_info_for_null_check_here(info);
3516 }
3517
3518 __ load_klass(result, obj, rscratch1);
3519 }
3520
3521 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3522 ciMethod* method = op->profiled_method();
3523 int bci = op->profiled_bci();
3524 ciMethod* callee = op->profiled_callee();
3525 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3526
3527 // Update counter for all call types
3528 ciMethodData* md = method->method_data_or_null();
3529 assert(md != nullptr, "Sanity");
3530 ciProfileData* data = md->bci_to_data(bci);
3531 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
3532 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3533 Register mdo = op->mdo()->as_register();
3534 __ mov_metadata(mdo, md->constant_encoding());
3535 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3536 // Perform additional virtual call profiling for invokevirtual and
3537 // invokeinterface bytecodes
3538 if (op->should_profile_receiver_type()) {
3539 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3540 Register recv = op->recv()->as_register();
3541 assert_different_registers(mdo, recv);
3542 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3543 ciKlass* known_klass = op->known_holder();
3544 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
3545 // We know the type that will be seen at this call site; we can
3546 // statically update the MethodData* rather than needing to do
3547 // dynamic tests on the receiver type
3548
3549 // NOTE: we should probably put a lock around this search to
3550 // avoid collisions by concurrent compilations
3551 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3552 uint i;
3553 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3554 ciKlass* receiver = vc_data->receiver(i);
3555 if (known_klass->equals(receiver)) {
3556 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3557 __ addptr(data_addr, DataLayout::counter_increment);
3558 return;
3559 }
3560 }
3561
3562 // Receiver type not found in profile data; select an empty slot
3563
3564 // Note that this is less efficient than it should be because it
3565 // always does a write to the receiver part of the
3566 // VirtualCallData rather than just the first time
3567 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3568 ciKlass* receiver = vc_data->receiver(i);
3569 if (receiver == nullptr) {
3570 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3571 __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1);
3572 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3573 __ addptr(data_addr, DataLayout::counter_increment);
3574 return;
3575 }
3576 }
3577 } else {
3578 __ load_klass(recv, recv, tmp_load_klass);
3579 Label update_done;
3580 type_profile_helper(mdo, md, data, recv, &update_done);
3581 // Receiver did not match any saved receiver and there is no empty row for it.
3582 // Increment total counter to indicate polymorphic case.
3583 __ addptr(counter_addr, DataLayout::counter_increment);
3584
3585 __ bind(update_done);
3586 }
3587 } else {
3588 // Static call
3589 __ addptr(counter_addr, DataLayout::counter_increment);
3590 }
3591 }
3592
3593 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3594 Register obj = op->obj()->as_register();
3595 Register tmp = op->tmp()->as_pointer_register();
3596 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3597 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3598 ciKlass* exact_klass = op->exact_klass();
3599 intptr_t current_klass = op->current_klass();
3600 bool not_null = op->not_null();
3601 bool no_conflict = op->no_conflict();
3602
3603 Label update, next, none;
3604
3605 bool do_null = !not_null;
3606 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3607 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3608
3609 assert(do_null || do_update, "why are we here?");
3610 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3611
3612 __ verify_oop(obj);
3613
3614 #ifdef ASSERT
3615 if (obj == tmp) {
3616 #ifdef _LP64
3617 assert_different_registers(obj, rscratch1, mdo_addr.base(), mdo_addr.index());
3618 #else
3619 assert_different_registers(obj, mdo_addr.base(), mdo_addr.index());
3620 #endif
3621 } else {
3622 #ifdef _LP64
3623 assert_different_registers(obj, tmp, rscratch1, mdo_addr.base(), mdo_addr.index());
3624 #else
3625 assert_different_registers(obj, tmp, mdo_addr.base(), mdo_addr.index());
3626 #endif
3627 }
3628 #endif
3629 if (do_null) {
3630 __ testptr(obj, obj);
3631 __ jccb(Assembler::notZero, update);
3632 if (!TypeEntries::was_null_seen(current_klass)) {
3633 __ testptr(mdo_addr, TypeEntries::null_seen);
3634 #ifndef ASSERT
3635 __ jccb(Assembler::notZero, next); // already set
3636 #else
3637 __ jcc(Assembler::notZero, next); // already set
3638 #endif
3639 // atomic update to prevent overwriting Klass* with 0
3640 __ lock();
3641 __ orptr(mdo_addr, TypeEntries::null_seen);
3642 }
3643 if (do_update) {
3644 #ifndef ASSERT
3645 __ jmpb(next);
3646 }
3647 #else
3648 __ jmp(next);
3649 }
3650 } else {
3651 __ testptr(obj, obj);
3652 __ jcc(Assembler::notZero, update);
3653 __ stop("unexpected null obj");
3654 #endif
3655 }
3656
3657 __ bind(update);
3658
3659 if (do_update) {
3660 #ifdef ASSERT
3661 if (exact_klass != nullptr) {
3662 Label ok;
3663 __ load_klass(tmp, obj, tmp_load_klass);
3664 __ push(tmp);
3665 __ mov_metadata(tmp, exact_klass->constant_encoding());
3666 __ cmpptr(tmp, Address(rsp, 0));
3667 __ jcc(Assembler::equal, ok);
3668 __ stop("exact klass and actual klass differ");
3669 __ bind(ok);
3670 __ pop(tmp);
3671 }
3672 #endif
3673 if (!no_conflict) {
3674 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3675 if (exact_klass != nullptr) {
3676 __ mov_metadata(tmp, exact_klass->constant_encoding());
3677 } else {
3678 __ load_klass(tmp, obj, tmp_load_klass);
3679 }
3680 #ifdef _LP64
3681 __ mov(rscratch1, tmp); // save original value before XOR
3682 #endif
3683 __ xorptr(tmp, mdo_addr);
3684 __ testptr(tmp, TypeEntries::type_klass_mask);
3685 // klass seen before, nothing to do. The unknown bit may have been
3686 // set already but no need to check.
3687 __ jccb(Assembler::zero, next);
3688
3689 __ testptr(tmp, TypeEntries::type_unknown);
3690 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3691
3692 if (TypeEntries::is_type_none(current_klass)) {
3693 __ testptr(mdo_addr, TypeEntries::type_mask);
3694 __ jccb(Assembler::zero, none);
3695 #ifdef _LP64
3696 // There is a chance that the checks above (re-reading profiling
3697 // data from memory) fail if another thread has just set the
3698 // profiling to this obj's klass
3699 __ mov(tmp, rscratch1); // get back original value before XOR
3700 __ xorptr(tmp, mdo_addr);
3701 __ testptr(tmp, TypeEntries::type_klass_mask);
3702 __ jccb(Assembler::zero, next);
3703 #endif
3704 }
3705 } else {
3706 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3707 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3708
3709 __ testptr(mdo_addr, TypeEntries::type_unknown);
3710 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3711 }
3712
3713 // different than before. Cannot keep accurate profile.
3714 __ orptr(mdo_addr, TypeEntries::type_unknown);
3715
3716 if (TypeEntries::is_type_none(current_klass)) {
3717 __ jmpb(next);
3718
3719 __ bind(none);
3720 // first time here. Set profile type.
3721 __ movptr(mdo_addr, tmp);
3722 #ifdef ASSERT
3723 __ andptr(tmp, TypeEntries::type_klass_mask);
3724 __ verify_klass_ptr(tmp);
3725 #endif
3726 }
3727 } else {
3728 // There's a single possible klass at this profile point
3729 assert(exact_klass != nullptr, "should be");
3730 if (TypeEntries::is_type_none(current_klass)) {
3731 __ mov_metadata(tmp, exact_klass->constant_encoding());
3732 __ xorptr(tmp, mdo_addr);
3733 __ testptr(tmp, TypeEntries::type_klass_mask);
3734 #ifdef ASSERT
3735 __ jcc(Assembler::zero, next);
3736
3737 {
3738 Label ok;
3739 __ push(tmp);
3740 __ testptr(mdo_addr, TypeEntries::type_mask);
3741 __ jcc(Assembler::zero, ok);
3742 // may have been set by another thread
3743 __ mov_metadata(tmp, exact_klass->constant_encoding());
3744 __ xorptr(tmp, mdo_addr);
3745 __ testptr(tmp, TypeEntries::type_mask);
3746 __ jcc(Assembler::zero, ok);
3747
3748 __ stop("unexpected profiling mismatch");
3749 __ bind(ok);
3750 __ pop(tmp);
3751 }
3752 #else
3753 __ jccb(Assembler::zero, next);
3754 #endif
3755 // first time here. Set profile type.
3756 __ movptr(mdo_addr, tmp);
3757 #ifdef ASSERT
3758 __ andptr(tmp, TypeEntries::type_klass_mask);
3759 __ verify_klass_ptr(tmp);
3760 #endif
3761 } else {
3762 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3763 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3764
3765 __ testptr(mdo_addr, TypeEntries::type_unknown);
3766 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3767
3768 __ orptr(mdo_addr, TypeEntries::type_unknown);
3769 }
3770 }
3771 }
3772 __ bind(next);
3773 }
3774
3775 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3776 Unimplemented();
3777 }
3778
3779
3780 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3781 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3782 }
3783
3784
3785 void LIR_Assembler::align_backward_branch_target() {
3786 __ align(BytesPerWord);
3787 }
3788
3789
3790 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3791 if (left->is_single_cpu()) {
3792 __ negl(left->as_register());
3793 move_regs(left->as_register(), dest->as_register());
3794
3795 } else if (left->is_double_cpu()) {
3796 Register lo = left->as_register_lo();
3797 #ifdef _LP64
3798 Register dst = dest->as_register_lo();
3799 __ movptr(dst, lo);
3800 __ negptr(dst);
3801 #else
3802 Register hi = left->as_register_hi();
3803 __ lneg(hi, lo);
3804 if (dest->as_register_lo() == hi) {
3805 assert(dest->as_register_hi() != lo, "destroying register");
3806 move_regs(hi, dest->as_register_hi());
3807 move_regs(lo, dest->as_register_lo());
3808 } else {
3809 move_regs(lo, dest->as_register_lo());
3810 move_regs(hi, dest->as_register_hi());
3811 }
3812 #endif // _LP64
3813
3814 } else if (dest->is_single_xmm()) {
3815 #ifdef _LP64
3816 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3817 assert(tmp->is_valid(), "need temporary");
3818 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
3819 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
3820 }
3821 else
3822 #endif
3823 {
3824 assert(!tmp->is_valid(), "do not need temporary");
3825 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3826 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3827 }
3828 __ xorps(dest->as_xmm_float_reg(),
3829 ExternalAddress(LIR_Assembler::float_signflip_pool),
3830 rscratch1);
3831 }
3832 } else if (dest->is_double_xmm()) {
3833 #ifdef _LP64
3834 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3835 assert(tmp->is_valid(), "need temporary");
3836 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
3837 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
3838 }
3839 else
3840 #endif
3841 {
3842 assert(!tmp->is_valid(), "do not need temporary");
3843 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3844 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3845 }
3846 __ xorpd(dest->as_xmm_double_reg(),
3847 ExternalAddress(LIR_Assembler::double_signflip_pool),
3848 rscratch1);
3849 }
3850 #ifndef _LP64
3851 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3852 assert(left->fpu() == 0, "arg must be on TOS");
3853 assert(dest->fpu() == 0, "dest must be TOS");
3854 __ fchs();
3855 #endif // !_LP64
3856
3857 } else {
3858 ShouldNotReachHere();
3859 }
3860 }
3861
3862
3863 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3864 assert(src->is_address(), "must be an address");
3865 assert(dest->is_register(), "must be a register");
3866
3867 PatchingStub* patch = nullptr;
3868 if (patch_code != lir_patch_none) {
3869 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3870 }
3871
3872 Register reg = dest->as_pointer_register();
3873 LIR_Address* addr = src->as_address_ptr();
3874 __ lea(reg, as_Address(addr));
3875
3876 if (patch != nullptr) {
3877 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3878 }
3879 }
3880
3881
3882
3883 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3884 assert(!tmp->is_valid(), "don't need temporary");
3885 __ call(RuntimeAddress(dest));
3886 if (info != nullptr) {
3887 add_call_info_here(info);
3888 }
3889 __ post_call_nop();
3890 }
3891
3892
3893 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3894 assert(type == T_LONG, "only for volatile long fields");
3895
3896 if (info != nullptr) {
3897 add_debug_info_for_null_check_here(info);
3898 }
3899
3900 if (src->is_double_xmm()) {
3901 if (dest->is_double_cpu()) {
3902 #ifdef _LP64
3903 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3904 #else
3905 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3906 __ psrlq(src->as_xmm_double_reg(), 32);
3907 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3908 #endif // _LP64
3909 } else if (dest->is_double_stack()) {
3910 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3911 } else if (dest->is_address()) {
3912 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3913 } else {
3914 ShouldNotReachHere();
3915 }
3916
3917 } else if (dest->is_double_xmm()) {
3918 if (src->is_double_stack()) {
3919 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3920 } else if (src->is_address()) {
3921 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3922 } else {
3923 ShouldNotReachHere();
3924 }
3925
3926 #ifndef _LP64
3927 } else if (src->is_double_fpu()) {
3928 assert(src->fpu_regnrLo() == 0, "must be TOS");
3929 if (dest->is_double_stack()) {
3930 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3931 } else if (dest->is_address()) {
3932 __ fistp_d(as_Address(dest->as_address_ptr()));
3933 } else {
3934 ShouldNotReachHere();
3935 }
3936
3937 } else if (dest->is_double_fpu()) {
3938 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3939 if (src->is_double_stack()) {
3940 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3941 } else if (src->is_address()) {
3942 __ fild_d(as_Address(src->as_address_ptr()));
3943 } else {
3944 ShouldNotReachHere();
3945 }
3946 #endif // !_LP64
3947
3948 } else {
3949 ShouldNotReachHere();
3950 }
3951 }
3952
3953 #ifdef ASSERT
3954 // emit run-time assertion
3955 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3956 assert(op->code() == lir_assert, "must be");
3957
3958 if (op->in_opr1()->is_valid()) {
3959 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3960 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3961 } else {
3962 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3963 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3964 }
3965
3966 Label ok;
3967 if (op->condition() != lir_cond_always) {
3968 Assembler::Condition acond = Assembler::zero;
3969 switch (op->condition()) {
3970 case lir_cond_equal: acond = Assembler::equal; break;
3971 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3972 case lir_cond_less: acond = Assembler::less; break;
3973 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3974 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3975 case lir_cond_greater: acond = Assembler::greater; break;
3976 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3977 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3978 default: ShouldNotReachHere();
3979 }
3980 __ jcc(acond, ok);
3981 }
3982 if (op->halt()) {
3983 const char* str = __ code_string(op->msg());
3984 __ stop(str);
3985 } else {
3986 breakpoint();
3987 }
3988 __ bind(ok);
3989 }
3990 #endif
3991
3992 void LIR_Assembler::membar() {
3993 // QQQ sparc TSO uses this,
3994 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3995 }
3996
3997 void LIR_Assembler::membar_acquire() {
3998 // No x86 machines currently require load fences
3999 }
4000
4001 void LIR_Assembler::membar_release() {
4002 // No x86 machines currently require store fences
4003 }
4004
4005 void LIR_Assembler::membar_loadload() {
4006 // no-op
4007 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
4008 }
4009
4010 void LIR_Assembler::membar_storestore() {
4011 // no-op
4012 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4013 }
4014
4015 void LIR_Assembler::membar_loadstore() {
4016 // no-op
4017 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4018 }
4019
4020 void LIR_Assembler::membar_storeload() {
4021 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4022 }
4023
4024 void LIR_Assembler::on_spin_wait() {
4025 __ pause ();
4026 }
4027
4028 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4029 assert(result_reg->is_register(), "check");
4030 #ifdef _LP64
4031 // __ get_thread(result_reg->as_register_lo());
4032 __ mov(result_reg->as_register(), r15_thread);
4033 #else
4034 __ get_thread(result_reg->as_register());
4035 #endif // _LP64
4036 }
4037
4038
4039 void LIR_Assembler::peephole(LIR_List*) {
4040 // do nothing for now
4041 }
4042
4043 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4044 assert(data == dest, "xchg/xadd uses only 2 operands");
4045
4046 if (data->type() == T_INT) {
4047 if (code == lir_xadd) {
4048 __ lock();
4049 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4050 } else {
4051 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4052 }
4053 } else if (data->is_oop()) {
4054 assert (code == lir_xchg, "xadd for oops");
4055 Register obj = data->as_register();
4056 #ifdef _LP64
4057 if (UseCompressedOops) {
4058 __ encode_heap_oop(obj);
4059 __ xchgl(obj, as_Address(src->as_address_ptr()));
4060 __ decode_heap_oop(obj);
4061 } else {
4062 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4063 }
4064 #else
4065 __ xchgl(obj, as_Address(src->as_address_ptr()));
4066 #endif
4067 } else if (data->type() == T_LONG) {
4068 #ifdef _LP64
4069 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4070 if (code == lir_xadd) {
4071 __ lock();
4072 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4073 } else {
4074 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4075 }
4076 #else
4077 ShouldNotReachHere();
4078 #endif
4079 } else {
4080 ShouldNotReachHere();
4081 }
4082 }
4083
4084 #undef __