1 /*
2 * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "ci/ciUtilities.hpp"
37 #include "code/SCCache.hpp"
38 #include "compiler/oopMap.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/gc_globals.hpp"
41 #include "nativeInst_x86.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/safepointMechanism.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/stubRoutines.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_x86.inline.hpp"
49
50
51 // These masks are used to provide 128-bit aligned bitmasks to the XMM
52 // instructions, to allow sign-masking or sign-bit flipping. They allow
53 // fast versions of NegF/NegD and AbsF/AbsD.
54
55 // Note: 'double' and 'long long' have 32-bits alignment on x86.
56 static address double_quadword(jlong *adr, jlong lo, jlong hi) {
57 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
58 // of 128-bits operands for SSE instructions.
59 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
60 // Store the value to a 128-bits operand.
61 operand[0] = lo;
62 operand[1] = hi;
63 return (address)operand;
64 }
65
66 // Buffer for 128-bits masks used by SSE instructions.
67 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
68
69 // Static initialization during VM startup.
70 address LIR_Assembler::float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
71 address LIR_Assembler::double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
72 address LIR_Assembler::float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
73 address LIR_Assembler::double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
74
75
76 NEEDS_CLEANUP // remove this definitions ?
77 const Register SYNC_header = rax; // synchronization header
78 const Register SHIFT_count = rcx; // where count for shift operations must be
79
80 #define __ _masm->
81
82
83 static void select_different_registers(Register preserve,
84 Register extra,
85 Register &tmp1,
86 Register &tmp2) {
87 if (tmp1 == preserve) {
88 assert_different_registers(tmp1, tmp2, extra);
89 tmp1 = extra;
90 } else if (tmp2 == preserve) {
91 assert_different_registers(tmp1, tmp2, extra);
92 tmp2 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2);
95 }
96
97
98
99 static void select_different_registers(Register preserve,
100 Register extra,
101 Register &tmp1,
102 Register &tmp2,
103 Register &tmp3) {
104 if (tmp1 == preserve) {
105 assert_different_registers(tmp1, tmp2, tmp3, extra);
106 tmp1 = extra;
107 } else if (tmp2 == preserve) {
108 assert_different_registers(tmp1, tmp2, tmp3, extra);
109 tmp2 = extra;
110 } else if (tmp3 == preserve) {
111 assert_different_registers(tmp1, tmp2, tmp3, extra);
112 tmp3 = extra;
113 }
114 assert_different_registers(preserve, tmp1, tmp2, tmp3);
115 }
116
117
118
119 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
120 if (opr->is_constant()) {
121 LIR_Const* constant = opr->as_constant_ptr();
122 switch (constant->type()) {
123 case T_INT: {
124 return true;
125 }
126
127 default:
128 return false;
129 }
130 }
131 return false;
132 }
133
134
135 LIR_Opr LIR_Assembler::receiverOpr() {
136 return FrameMap::receiver_opr;
137 }
138
139 LIR_Opr LIR_Assembler::osrBufferPointer() {
140 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
141 }
142
143 //--------------fpu register translations-----------------------
144
145
146 address LIR_Assembler::float_constant(float f) {
147 address const_addr = __ float_constant(f);
148 if (const_addr == nullptr) {
149 bailout("const section overflow");
150 return __ code()->consts()->start();
151 } else {
152 return const_addr;
153 }
154 }
155
156
157 address LIR_Assembler::double_constant(double d) {
158 address const_addr = __ double_constant(d);
159 if (const_addr == nullptr) {
160 bailout("const section overflow");
161 return __ code()->consts()->start();
162 } else {
163 return const_addr;
164 }
165 }
166
167 #ifndef _LP64
168 void LIR_Assembler::fpop() {
169 __ fpop();
170 }
171
172 void LIR_Assembler::fxch(int i) {
173 __ fxch(i);
174 }
175
176 void LIR_Assembler::fld(int i) {
177 __ fld_s(i);
178 }
179
180 void LIR_Assembler::ffree(int i) {
181 __ ffree(i);
182 }
183 #endif // !_LP64
184
185 void LIR_Assembler::breakpoint() {
186 __ int3();
187 }
188
189 void LIR_Assembler::push(LIR_Opr opr) {
190 if (opr->is_single_cpu()) {
191 __ push_reg(opr->as_register());
192 } else if (opr->is_double_cpu()) {
193 NOT_LP64(__ push_reg(opr->as_register_hi()));
194 __ push_reg(opr->as_register_lo());
195 } else if (opr->is_stack()) {
196 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
197 } else if (opr->is_constant()) {
198 LIR_Const* const_opr = opr->as_constant_ptr();
199 if (const_opr->type() == T_OBJECT) {
200 __ push_oop(const_opr->as_jobject(), rscratch1);
201 } else if (const_opr->type() == T_INT) {
202 __ push_jint(const_opr->as_jint());
203 } else {
204 ShouldNotReachHere();
205 }
206
207 } else {
208 ShouldNotReachHere();
209 }
210 }
211
212 void LIR_Assembler::pop(LIR_Opr opr) {
213 if (opr->is_single_cpu()) {
214 __ pop_reg(opr->as_register());
215 } else {
216 ShouldNotReachHere();
217 }
218 }
219
220 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
221 return addr->base()->is_illegal() && addr->index()->is_illegal();
222 }
223
224 //-------------------------------------------
225
226 Address LIR_Assembler::as_Address(LIR_Address* addr) {
227 return as_Address(addr, rscratch1);
228 }
229
230 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
231 if (addr->base()->is_illegal()) {
232 assert(addr->index()->is_illegal(), "must be illegal too");
233 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
234 if (! __ reachable(laddr)) {
235 __ movptr(tmp, laddr.addr());
236 Address res(tmp, 0);
237 return res;
238 } else {
239 return __ as_Address(laddr);
240 }
241 }
242
243 Register base = addr->base()->as_pointer_register();
244
245 if (addr->index()->is_illegal()) {
246 return Address( base, addr->disp());
247 } else if (addr->index()->is_cpu_register()) {
248 Register index = addr->index()->as_pointer_register();
249 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
250 } else if (addr->index()->is_constant()) {
251 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
252 assert(Assembler::is_simm32(addr_offset), "must be");
253
254 return Address(base, addr_offset);
255 } else {
256 Unimplemented();
257 return Address();
258 }
259 }
260
261
262 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
263 Address base = as_Address(addr);
264 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
265 }
266
267
268 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
269 return as_Address(addr);
270 }
271
272
273 void LIR_Assembler::osr_entry() {
274 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
275 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
276 ValueStack* entry_state = osr_entry->state();
277 int number_of_locks = entry_state->locks_size();
278
279 // we jump here if osr happens with the interpreter
280 // state set up to continue at the beginning of the
281 // loop that triggered osr - in particular, we have
282 // the following registers setup:
283 //
284 // rcx: osr buffer
285 //
286
287 // build frame
288 ciMethod* m = compilation()->method();
289 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
290
291 // OSR buffer is
292 //
293 // locals[nlocals-1..0]
294 // monitors[0..number_of_locks]
295 //
296 // locals is a direct copy of the interpreter frame so in the osr buffer
297 // so first slot in the local array is the last local from the interpreter
298 // and last slot is local[0] (receiver) from the interpreter
299 //
300 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
301 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
302 // in the interpreter frame (the method lock if a sync method)
303
304 // Initialize monitors in the compiled activation.
305 // rcx: pointer to osr buffer
306 //
307 // All other registers are dead at this point and the locals will be
308 // copied into place by code emitted in the IR.
309
310 Register OSR_buf = osrBufferPointer()->as_pointer_register();
311 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
312 int monitor_offset = BytesPerWord * method()->max_locals() +
313 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
314 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
315 // the OSR buffer using 2 word entries: first the lock and then
316 // the oop.
317 for (int i = 0; i < number_of_locks; i++) {
318 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
319 #ifdef ASSERT
320 // verify the interpreter's monitor has a non-null object
321 {
322 Label L;
323 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD);
324 __ jcc(Assembler::notZero, L);
325 __ stop("locked object is null");
326 __ bind(L);
327 }
328 #endif
329 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
330 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
331 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
332 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
333 }
334 }
335 }
336
337
338 // inline cache check; done before the frame is built.
339 int LIR_Assembler::check_icache() {
340 return __ ic_check(CodeEntryAlignment);
341 }
342
343 void LIR_Assembler::clinit_barrier(ciMethod* method) {
344 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
345 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
346
347 Label L_skip_barrier;
348 Register klass = rscratch1;
349 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
350 assert(thread != noreg, "x86_32 not implemented");
351
352 __ mov_metadata(klass, method->holder()->constant_encoding());
353 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
354
355 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
356
357 __ bind(L_skip_barrier);
358 }
359
360 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
361 jobject o = nullptr;
362 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
363 __ movoop(reg, o);
364 patching_epilog(patch, lir_patch_normal, reg, info);
365 }
366
367 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
368 Metadata* o = nullptr;
369 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
370 __ mov_metadata(reg, o);
371 patching_epilog(patch, lir_patch_normal, reg, info);
372 }
373
374 // This specifies the rsp decrement needed to build the frame
375 int LIR_Assembler::initial_frame_size_in_bytes() const {
376 // if rounding, must let FrameMap know!
377
378 // The frame_map records size in slots (32bit word)
379
380 // subtract two words to account for return address and link
381 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
382 }
383
384
385 int LIR_Assembler::emit_exception_handler() {
386 // generate code for exception handler
387 address handler_base = __ start_a_stub(exception_handler_size());
388 if (handler_base == nullptr) {
389 // not enough space left for the handler
390 bailout("exception handler overflow");
391 return -1;
392 }
393
394 int offset = code_offset();
395
396 // the exception oop and pc are in rax, and rdx
397 // no other registers need to be preserved, so invalidate them
398 __ invalidate_registers(false, true, true, false, true, true);
399
400 // check that there is really an exception
401 __ verify_not_null_oop(rax);
402
403 // search an exception handler (rax: exception oop, rdx: throwing pc)
404 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
405 __ should_not_reach_here();
406 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
407 __ end_a_stub();
408
409 return offset;
410 }
411
412
413 // Emit the code to remove the frame from the stack in the exception
414 // unwind path.
415 int LIR_Assembler::emit_unwind_handler() {
416 #ifndef PRODUCT
417 if (CommentedAssembly) {
418 _masm->block_comment("Unwind handler");
419 }
420 #endif
421
422 int offset = code_offset();
423
424 // Fetch the exception from TLS and clear out exception related thread state
425 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
426 NOT_LP64(__ get_thread(thread));
427 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
428 __ movptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
429 __ movptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
430
431 __ bind(_unwind_handler_entry);
432 __ verify_not_null_oop(rax);
433 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
434 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
435 }
436
437 // Perform needed unlocking
438 MonitorExitStub* stub = nullptr;
439 if (method()->is_synchronized()) {
440 monitor_address(0, FrameMap::rax_opr);
441 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
442 if (LockingMode == LM_MONITOR) {
443 __ jmp(*stub->entry());
444 } else {
445 __ unlock_object(rdi, rsi, rax, *stub->entry());
446 }
447 __ bind(*stub->continuation());
448 }
449
450 if (compilation()->env()->dtrace_method_probes()) {
451 #ifdef _LP64
452 __ mov(rdi, r15_thread);
453 __ mov_metadata(rsi, method()->constant_encoding());
454 #else
455 __ get_thread(rax);
456 __ movptr(Address(rsp, 0), rax);
457 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding(), noreg);
458 #endif
459 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
460 }
461
462 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
463 __ mov(rax, rbx); // Restore the exception
464 }
465
466 // remove the activation and dispatch to the unwind handler
467 __ remove_frame(initial_frame_size_in_bytes());
468 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
469
470 // Emit the slow path assembly
471 if (stub != nullptr) {
472 stub->emit_code(this);
473 }
474
475 return offset;
476 }
477
478
479 int LIR_Assembler::emit_deopt_handler() {
480 // generate code for exception handler
481 address handler_base = __ start_a_stub(deopt_handler_size());
482 if (handler_base == nullptr) {
483 // not enough space left for the handler
484 bailout("deopt handler overflow");
485 return -1;
486 }
487
488 int offset = code_offset();
489 InternalAddress here(__ pc());
490
491 __ pushptr(here.addr(), rscratch1);
492 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
493 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
494 __ end_a_stub();
495
496 return offset;
497 }
498
499 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
500 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
501 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
502 assert(result->fpu() == 0, "result must already be on TOS");
503 }
504
505 // Pop the stack before the safepoint code
506 __ remove_frame(initial_frame_size_in_bytes());
507
508 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
509 __ reserved_stack_check();
510 }
511
512 // Note: we do not need to round double result; float result has the right precision
513 // the poll sets the condition code, but no data registers
514
515 #ifdef _LP64
516 const Register thread = r15_thread;
517 #else
518 const Register thread = rbx;
519 __ get_thread(thread);
520 #endif
521 code_stub->set_safepoint_offset(__ offset());
522 __ relocate(relocInfo::poll_return_type);
523 __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */);
524 __ ret(0);
525 }
526
527
528 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
529 guarantee(info != nullptr, "Shouldn't be null");
530 int offset = __ offset();
531 #ifdef _LP64
532 const Register poll_addr = rscratch1;
533 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
534 #else
535 assert(tmp->is_cpu_register(), "needed");
536 const Register poll_addr = tmp->as_register();
537 __ get_thread(poll_addr);
538 __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset())));
539 #endif
540 add_debug_info_for_branch(info);
541 __ relocate(relocInfo::poll_type);
542 address pre_pc = __ pc();
543 __ testl(rax, Address(poll_addr, 0));
544 address post_pc = __ pc();
545 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
546 return offset;
547 }
548
549
550 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
551 if (from_reg != to_reg) __ mov(to_reg, from_reg);
552 }
553
554 void LIR_Assembler::swap_reg(Register a, Register b) {
555 __ xchgptr(a, b);
556 }
557
558
559 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
560 assert(src->is_constant(), "should not call otherwise");
561 assert(dest->is_register(), "should not call otherwise");
562 LIR_Const* c = src->as_constant_ptr();
563
564 switch (c->type()) {
565 case T_INT: {
566 assert(patch_code == lir_patch_none, "no patching handled here");
567 __ movl(dest->as_register(), c->as_jint());
568 break;
569 }
570
571 case T_ADDRESS: {
572 assert(patch_code == lir_patch_none, "no patching handled here");
573 __ movptr(dest->as_register(), c->as_jint());
574 break;
575 }
576
577 case T_LONG: {
578 assert(patch_code == lir_patch_none, "no patching handled here");
579 #ifdef _LP64
580 if (SCCache::is_on_for_write()) {
581 // SCA needs relocation info for card table base
582 address b = c->as_pointer();
583 if (is_card_table_address(b)) {
584 __ lea(dest->as_register_lo(), ExternalAddress(b));
585 break;
586 }
587 }
588 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
589 #else
590 __ movptr(dest->as_register_lo(), c->as_jint_lo());
591 __ movptr(dest->as_register_hi(), c->as_jint_hi());
592 #endif // _LP64
593 break;
594 }
595
596 case T_OBJECT: {
597 if (patch_code != lir_patch_none) {
598 jobject2reg_with_patching(dest->as_register(), info);
599 } else {
600 __ movoop(dest->as_register(), c->as_jobject());
601 }
602 break;
603 }
604
605 case T_METADATA: {
606 if (patch_code != lir_patch_none) {
607 klass2reg_with_patching(dest->as_register(), info);
608 } else {
609 __ mov_metadata(dest->as_register(), c->as_metadata());
610 }
611 break;
612 }
613
614 case T_FLOAT: {
615 if (dest->is_single_xmm()) {
616 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
617 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
618 } else {
619 __ movflt(dest->as_xmm_float_reg(),
620 InternalAddress(float_constant(c->as_jfloat())));
621 }
622 } else {
623 #ifndef _LP64
624 assert(dest->is_single_fpu(), "must be");
625 assert(dest->fpu_regnr() == 0, "dest must be TOS");
626 if (c->is_zero_float()) {
627 __ fldz();
628 } else if (c->is_one_float()) {
629 __ fld1();
630 } else {
631 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
632 }
633 #else
634 ShouldNotReachHere();
635 #endif // !_LP64
636 }
637 break;
638 }
639
640 case T_DOUBLE: {
641 if (dest->is_double_xmm()) {
642 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
643 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
644 } else {
645 __ movdbl(dest->as_xmm_double_reg(),
646 InternalAddress(double_constant(c->as_jdouble())));
647 }
648 } else {
649 #ifndef _LP64
650 assert(dest->is_double_fpu(), "must be");
651 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
652 if (c->is_zero_double()) {
653 __ fldz();
654 } else if (c->is_one_double()) {
655 __ fld1();
656 } else {
657 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
658 }
659 #else
660 ShouldNotReachHere();
661 #endif // !_LP64
662 }
663 break;
664 }
665
666 default:
667 ShouldNotReachHere();
668 }
669 }
670
671 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
672 assert(src->is_constant(), "should not call otherwise");
673 assert(dest->is_stack(), "should not call otherwise");
674 LIR_Const* c = src->as_constant_ptr();
675
676 switch (c->type()) {
677 case T_INT: // fall through
678 case T_FLOAT:
679 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
680 break;
681
682 case T_ADDRESS:
683 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
684 break;
685
686 case T_OBJECT:
687 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1);
688 break;
689
690 case T_LONG: // fall through
691 case T_DOUBLE:
692 #ifdef _LP64
693 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
694 lo_word_offset_in_bytes),
695 (intptr_t)c->as_jlong_bits(),
696 rscratch1);
697 #else
698 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
699 lo_word_offset_in_bytes), c->as_jint_lo_bits());
700 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
701 hi_word_offset_in_bytes), c->as_jint_hi_bits());
702 #endif // _LP64
703 break;
704
705 default:
706 ShouldNotReachHere();
707 }
708 }
709
710 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
711 assert(src->is_constant(), "should not call otherwise");
712 assert(dest->is_address(), "should not call otherwise");
713 LIR_Const* c = src->as_constant_ptr();
714 LIR_Address* addr = dest->as_address_ptr();
715
716 int null_check_here = code_offset();
717 switch (type) {
718 case T_INT: // fall through
719 case T_FLOAT:
720 __ movl(as_Address(addr), c->as_jint_bits());
721 break;
722
723 case T_ADDRESS:
724 __ movptr(as_Address(addr), c->as_jint_bits());
725 break;
726
727 case T_OBJECT: // fall through
728 case T_ARRAY:
729 if (c->as_jobject() == nullptr) {
730 if (UseCompressedOops && !wide) {
731 __ movl(as_Address(addr), NULL_WORD);
732 } else {
733 #ifdef _LP64
734 __ xorptr(rscratch1, rscratch1);
735 null_check_here = code_offset();
736 __ movptr(as_Address(addr), rscratch1);
737 #else
738 __ movptr(as_Address(addr), NULL_WORD);
739 #endif
740 }
741 } else {
742 if (is_literal_address(addr)) {
743 ShouldNotReachHere();
744 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1);
745 } else {
746 #ifdef _LP64
747 __ movoop(rscratch1, c->as_jobject());
748 if (UseCompressedOops && !wide) {
749 __ encode_heap_oop(rscratch1);
750 null_check_here = code_offset();
751 __ movl(as_Address_lo(addr), rscratch1);
752 } else {
753 null_check_here = code_offset();
754 __ movptr(as_Address_lo(addr), rscratch1);
755 }
756 #else
757 __ movoop(as_Address(addr), c->as_jobject(), noreg);
758 #endif
759 }
760 }
761 break;
762
763 case T_LONG: // fall through
764 case T_DOUBLE:
765 #ifdef _LP64
766 if (is_literal_address(addr)) {
767 ShouldNotReachHere();
768 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
769 } else {
770 __ movptr(r10, (intptr_t)c->as_jlong_bits());
771 null_check_here = code_offset();
772 __ movptr(as_Address_lo(addr), r10);
773 }
774 #else
775 // Always reachable in 32bit so this doesn't produce useless move literal
776 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
777 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
778 #endif // _LP64
779 break;
780
781 case T_BOOLEAN: // fall through
782 case T_BYTE:
783 __ movb(as_Address(addr), c->as_jint() & 0xFF);
784 break;
785
786 case T_CHAR: // fall through
787 case T_SHORT:
788 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
789 break;
790
791 default:
792 ShouldNotReachHere();
793 };
794
795 if (info != nullptr) {
796 add_debug_info_for_null_check(null_check_here, info);
797 }
798 }
799
800
801 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
802 assert(src->is_register(), "should not call otherwise");
803 assert(dest->is_register(), "should not call otherwise");
804
805 // move between cpu-registers
806 if (dest->is_single_cpu()) {
807 #ifdef _LP64
808 if (src->type() == T_LONG) {
809 // Can do LONG -> OBJECT
810 move_regs(src->as_register_lo(), dest->as_register());
811 return;
812 }
813 #endif
814 assert(src->is_single_cpu(), "must match");
815 if (src->type() == T_OBJECT) {
816 __ verify_oop(src->as_register());
817 }
818 move_regs(src->as_register(), dest->as_register());
819
820 } else if (dest->is_double_cpu()) {
821 #ifdef _LP64
822 if (is_reference_type(src->type())) {
823 // Surprising to me but we can see move of a long to t_object
824 __ verify_oop(src->as_register());
825 move_regs(src->as_register(), dest->as_register_lo());
826 return;
827 }
828 #endif
829 assert(src->is_double_cpu(), "must match");
830 Register f_lo = src->as_register_lo();
831 Register f_hi = src->as_register_hi();
832 Register t_lo = dest->as_register_lo();
833 Register t_hi = dest->as_register_hi();
834 #ifdef _LP64
835 assert(f_hi == f_lo, "must be same");
836 assert(t_hi == t_lo, "must be same");
837 move_regs(f_lo, t_lo);
838 #else
839 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
840
841
842 if (f_lo == t_hi && f_hi == t_lo) {
843 swap_reg(f_lo, f_hi);
844 } else if (f_hi == t_lo) {
845 assert(f_lo != t_hi, "overwriting register");
846 move_regs(f_hi, t_hi);
847 move_regs(f_lo, t_lo);
848 } else {
849 assert(f_hi != t_lo, "overwriting register");
850 move_regs(f_lo, t_lo);
851 move_regs(f_hi, t_hi);
852 }
853 #endif // LP64
854
855 #ifndef _LP64
856 // special moves from fpu-register to xmm-register
857 // necessary for method results
858 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
859 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
860 __ fld_s(Address(rsp, 0));
861 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
862 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
863 __ fld_d(Address(rsp, 0));
864 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
865 __ fstp_s(Address(rsp, 0));
866 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
867 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
868 __ fstp_d(Address(rsp, 0));
869 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
870 #endif // !_LP64
871
872 // move between xmm-registers
873 } else if (dest->is_single_xmm()) {
874 assert(src->is_single_xmm(), "must match");
875 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
876 } else if (dest->is_double_xmm()) {
877 assert(src->is_double_xmm(), "must match");
878 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
879
880 #ifndef _LP64
881 // move between fpu-registers (no instruction necessary because of fpu-stack)
882 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
883 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
884 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
885 #endif // !_LP64
886
887 } else {
888 ShouldNotReachHere();
889 }
890 }
891
892 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
893 assert(src->is_register(), "should not call otherwise");
894 assert(dest->is_stack(), "should not call otherwise");
895
896 if (src->is_single_cpu()) {
897 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
898 if (is_reference_type(type)) {
899 __ verify_oop(src->as_register());
900 __ movptr (dst, src->as_register());
901 } else if (type == T_METADATA || type == T_ADDRESS) {
902 __ movptr (dst, src->as_register());
903 } else {
904 __ movl (dst, src->as_register());
905 }
906
907 } else if (src->is_double_cpu()) {
908 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
909 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
910 __ movptr (dstLO, src->as_register_lo());
911 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
912
913 } else if (src->is_single_xmm()) {
914 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
915 __ movflt(dst_addr, src->as_xmm_float_reg());
916
917 } else if (src->is_double_xmm()) {
918 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
919 __ movdbl(dst_addr, src->as_xmm_double_reg());
920
921 #ifndef _LP64
922 } else if (src->is_single_fpu()) {
923 assert(src->fpu_regnr() == 0, "argument must be on TOS");
924 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
925 if (pop_fpu_stack) __ fstp_s (dst_addr);
926 else __ fst_s (dst_addr);
927
928 } else if (src->is_double_fpu()) {
929 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
930 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
931 if (pop_fpu_stack) __ fstp_d (dst_addr);
932 else __ fst_d (dst_addr);
933 #endif // !_LP64
934
935 } else {
936 ShouldNotReachHere();
937 }
938 }
939
940
941 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
942 LIR_Address* to_addr = dest->as_address_ptr();
943 PatchingStub* patch = nullptr;
944 Register compressed_src = rscratch1;
945
946 if (is_reference_type(type)) {
947 __ verify_oop(src->as_register());
948 #ifdef _LP64
949 if (UseCompressedOops && !wide) {
950 __ movptr(compressed_src, src->as_register());
951 __ encode_heap_oop(compressed_src);
952 if (patch_code != lir_patch_none) {
953 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
954 }
955 }
956 #endif
957 }
958
959 if (patch_code != lir_patch_none) {
960 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
961 Address toa = as_Address(to_addr);
962 assert(toa.disp() != 0, "must have");
963 }
964
965 int null_check_here = code_offset();
966 switch (type) {
967 case T_FLOAT: {
968 #ifdef _LP64
969 assert(src->is_single_xmm(), "not a float");
970 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
971 #else
972 if (src->is_single_xmm()) {
973 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
974 } else {
975 assert(src->is_single_fpu(), "must be");
976 assert(src->fpu_regnr() == 0, "argument must be on TOS");
977 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
978 else __ fst_s (as_Address(to_addr));
979 }
980 #endif // _LP64
981 break;
982 }
983
984 case T_DOUBLE: {
985 #ifdef _LP64
986 assert(src->is_double_xmm(), "not a double");
987 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
988 #else
989 if (src->is_double_xmm()) {
990 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
991 } else {
992 assert(src->is_double_fpu(), "must be");
993 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
994 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
995 else __ fst_d (as_Address(to_addr));
996 }
997 #endif // _LP64
998 break;
999 }
1000
1001 case T_ARRAY: // fall through
1002 case T_OBJECT: // fall through
1003 if (UseCompressedOops && !wide) {
1004 __ movl(as_Address(to_addr), compressed_src);
1005 } else {
1006 __ movptr(as_Address(to_addr), src->as_register());
1007 }
1008 break;
1009 case T_METADATA:
1010 // We get here to store a method pointer to the stack to pass to
1011 // a dtrace runtime call. This can't work on 64 bit with
1012 // compressed klass ptrs: T_METADATA can be a compressed klass
1013 // ptr or a 64 bit method pointer.
1014 LP64_ONLY(ShouldNotReachHere());
1015 __ movptr(as_Address(to_addr), src->as_register());
1016 break;
1017 case T_ADDRESS:
1018 __ movptr(as_Address(to_addr), src->as_register());
1019 break;
1020 case T_INT:
1021 __ movl(as_Address(to_addr), src->as_register());
1022 break;
1023
1024 case T_LONG: {
1025 Register from_lo = src->as_register_lo();
1026 Register from_hi = src->as_register_hi();
1027 #ifdef _LP64
1028 __ movptr(as_Address_lo(to_addr), from_lo);
1029 #else
1030 Register base = to_addr->base()->as_register();
1031 Register index = noreg;
1032 if (to_addr->index()->is_register()) {
1033 index = to_addr->index()->as_register();
1034 }
1035 if (base == from_lo || index == from_lo) {
1036 assert(base != from_hi, "can't be");
1037 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1038 __ movl(as_Address_hi(to_addr), from_hi);
1039 if (patch != nullptr) {
1040 patching_epilog(patch, lir_patch_high, base, info);
1041 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1042 patch_code = lir_patch_low;
1043 }
1044 __ movl(as_Address_lo(to_addr), from_lo);
1045 } else {
1046 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1047 __ movl(as_Address_lo(to_addr), from_lo);
1048 if (patch != nullptr) {
1049 patching_epilog(patch, lir_patch_low, base, info);
1050 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1051 patch_code = lir_patch_high;
1052 }
1053 __ movl(as_Address_hi(to_addr), from_hi);
1054 }
1055 #endif // _LP64
1056 break;
1057 }
1058
1059 case T_BYTE: // fall through
1060 case T_BOOLEAN: {
1061 Register src_reg = src->as_register();
1062 Address dst_addr = as_Address(to_addr);
1063 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1064 __ movb(dst_addr, src_reg);
1065 break;
1066 }
1067
1068 case T_CHAR: // fall through
1069 case T_SHORT:
1070 __ movw(as_Address(to_addr), src->as_register());
1071 break;
1072
1073 default:
1074 ShouldNotReachHere();
1075 }
1076 if (info != nullptr) {
1077 add_debug_info_for_null_check(null_check_here, info);
1078 }
1079
1080 if (patch_code != lir_patch_none) {
1081 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1082 }
1083 }
1084
1085
1086 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1087 assert(src->is_stack(), "should not call otherwise");
1088 assert(dest->is_register(), "should not call otherwise");
1089
1090 if (dest->is_single_cpu()) {
1091 if (is_reference_type(type)) {
1092 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1093 __ verify_oop(dest->as_register());
1094 } else if (type == T_METADATA || type == T_ADDRESS) {
1095 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1096 } else {
1097 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1098 }
1099
1100 } else if (dest->is_double_cpu()) {
1101 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1102 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1103 __ movptr(dest->as_register_lo(), src_addr_LO);
1104 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1105
1106 } else if (dest->is_single_xmm()) {
1107 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1108 __ movflt(dest->as_xmm_float_reg(), src_addr);
1109
1110 } else if (dest->is_double_xmm()) {
1111 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1112 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1113
1114 #ifndef _LP64
1115 } else if (dest->is_single_fpu()) {
1116 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1117 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1118 __ fld_s(src_addr);
1119
1120 } else if (dest->is_double_fpu()) {
1121 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1122 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1123 __ fld_d(src_addr);
1124 #endif // _LP64
1125
1126 } else {
1127 ShouldNotReachHere();
1128 }
1129 }
1130
1131
1132 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1133 if (src->is_single_stack()) {
1134 if (is_reference_type(type)) {
1135 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1136 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1137 } else {
1138 #ifndef _LP64
1139 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1140 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1141 #else
1142 //no pushl on 64bits
1143 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1144 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1145 #endif
1146 }
1147
1148 } else if (src->is_double_stack()) {
1149 #ifdef _LP64
1150 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1151 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1152 #else
1153 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1154 // push and pop the part at src + wordSize, adding wordSize for the previous push
1155 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1156 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1157 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1158 #endif // _LP64
1159
1160 } else {
1161 ShouldNotReachHere();
1162 }
1163 }
1164
1165
1166 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1167 assert(src->is_address(), "should not call otherwise");
1168 assert(dest->is_register(), "should not call otherwise");
1169
1170 LIR_Address* addr = src->as_address_ptr();
1171 Address from_addr = as_Address(addr);
1172
1173 if (addr->base()->type() == T_OBJECT) {
1174 __ verify_oop(addr->base()->as_pointer_register());
1175 }
1176
1177 switch (type) {
1178 case T_BOOLEAN: // fall through
1179 case T_BYTE: // fall through
1180 case T_CHAR: // fall through
1181 case T_SHORT:
1182 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1183 // on pre P6 processors we may get partial register stalls
1184 // so blow away the value of to_rinfo before loading a
1185 // partial word into it. Do it here so that it precedes
1186 // the potential patch point below.
1187 __ xorptr(dest->as_register(), dest->as_register());
1188 }
1189 break;
1190 default:
1191 break;
1192 }
1193
1194 PatchingStub* patch = nullptr;
1195 if (patch_code != lir_patch_none) {
1196 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1197 assert(from_addr.disp() != 0, "must have");
1198 }
1199 if (info != nullptr) {
1200 add_debug_info_for_null_check_here(info);
1201 }
1202
1203 switch (type) {
1204 case T_FLOAT: {
1205 if (dest->is_single_xmm()) {
1206 __ movflt(dest->as_xmm_float_reg(), from_addr);
1207 } else {
1208 #ifndef _LP64
1209 assert(dest->is_single_fpu(), "must be");
1210 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1211 __ fld_s(from_addr);
1212 #else
1213 ShouldNotReachHere();
1214 #endif // !LP64
1215 }
1216 break;
1217 }
1218
1219 case T_DOUBLE: {
1220 if (dest->is_double_xmm()) {
1221 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1222 } else {
1223 #ifndef _LP64
1224 assert(dest->is_double_fpu(), "must be");
1225 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1226 __ fld_d(from_addr);
1227 #else
1228 ShouldNotReachHere();
1229 #endif // !LP64
1230 }
1231 break;
1232 }
1233
1234 case T_OBJECT: // fall through
1235 case T_ARRAY: // fall through
1236 if (UseCompressedOops && !wide) {
1237 __ movl(dest->as_register(), from_addr);
1238 } else {
1239 __ movptr(dest->as_register(), from_addr);
1240 }
1241 break;
1242
1243 case T_ADDRESS:
1244 __ movptr(dest->as_register(), from_addr);
1245 break;
1246 case T_INT:
1247 __ movl(dest->as_register(), from_addr);
1248 break;
1249
1250 case T_LONG: {
1251 Register to_lo = dest->as_register_lo();
1252 Register to_hi = dest->as_register_hi();
1253 #ifdef _LP64
1254 __ movptr(to_lo, as_Address_lo(addr));
1255 #else
1256 Register base = addr->base()->as_register();
1257 Register index = noreg;
1258 if (addr->index()->is_register()) {
1259 index = addr->index()->as_register();
1260 }
1261 if ((base == to_lo && index == to_hi) ||
1262 (base == to_hi && index == to_lo)) {
1263 // addresses with 2 registers are only formed as a result of
1264 // array access so this code will never have to deal with
1265 // patches or null checks.
1266 assert(info == nullptr && patch == nullptr, "must be");
1267 __ lea(to_hi, as_Address(addr));
1268 __ movl(to_lo, Address(to_hi, 0));
1269 __ movl(to_hi, Address(to_hi, BytesPerWord));
1270 } else if (base == to_lo || index == to_lo) {
1271 assert(base != to_hi, "can't be");
1272 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1273 __ movl(to_hi, as_Address_hi(addr));
1274 if (patch != nullptr) {
1275 patching_epilog(patch, lir_patch_high, base, info);
1276 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1277 patch_code = lir_patch_low;
1278 }
1279 __ movl(to_lo, as_Address_lo(addr));
1280 } else {
1281 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1282 __ movl(to_lo, as_Address_lo(addr));
1283 if (patch != nullptr) {
1284 patching_epilog(patch, lir_patch_low, base, info);
1285 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1286 patch_code = lir_patch_high;
1287 }
1288 __ movl(to_hi, as_Address_hi(addr));
1289 }
1290 #endif // _LP64
1291 break;
1292 }
1293
1294 case T_BOOLEAN: // fall through
1295 case T_BYTE: {
1296 Register dest_reg = dest->as_register();
1297 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1298 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1299 __ movsbl(dest_reg, from_addr);
1300 } else {
1301 __ movb(dest_reg, from_addr);
1302 __ shll(dest_reg, 24);
1303 __ sarl(dest_reg, 24);
1304 }
1305 break;
1306 }
1307
1308 case T_CHAR: {
1309 Register dest_reg = dest->as_register();
1310 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1311 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1312 __ movzwl(dest_reg, from_addr);
1313 } else {
1314 __ movw(dest_reg, from_addr);
1315 }
1316 break;
1317 }
1318
1319 case T_SHORT: {
1320 Register dest_reg = dest->as_register();
1321 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1322 __ movswl(dest_reg, from_addr);
1323 } else {
1324 __ movw(dest_reg, from_addr);
1325 __ shll(dest_reg, 16);
1326 __ sarl(dest_reg, 16);
1327 }
1328 break;
1329 }
1330
1331 default:
1332 ShouldNotReachHere();
1333 }
1334
1335 if (patch != nullptr) {
1336 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1337 }
1338
1339 if (is_reference_type(type)) {
1340 #ifdef _LP64
1341 if (UseCompressedOops && !wide) {
1342 __ decode_heap_oop(dest->as_register());
1343 }
1344 #endif
1345
1346 if (!(UseZGC && !ZGenerational)) {
1347 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1348 __ verify_oop(dest->as_register());
1349 }
1350 }
1351 }
1352
1353
1354 NEEDS_CLEANUP; // This could be static?
1355 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1356 int elem_size = type2aelembytes(type);
1357 switch (elem_size) {
1358 case 1: return Address::times_1;
1359 case 2: return Address::times_2;
1360 case 4: return Address::times_4;
1361 case 8: return Address::times_8;
1362 }
1363 ShouldNotReachHere();
1364 return Address::no_scale;
1365 }
1366
1367
1368 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1369 switch (op->code()) {
1370 case lir_idiv:
1371 case lir_irem:
1372 arithmetic_idiv(op->code(),
1373 op->in_opr1(),
1374 op->in_opr2(),
1375 op->in_opr3(),
1376 op->result_opr(),
1377 op->info());
1378 break;
1379 case lir_fmad:
1380 __ fmad(op->result_opr()->as_xmm_double_reg(),
1381 op->in_opr1()->as_xmm_double_reg(),
1382 op->in_opr2()->as_xmm_double_reg(),
1383 op->in_opr3()->as_xmm_double_reg());
1384 break;
1385 case lir_fmaf:
1386 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1387 op->in_opr1()->as_xmm_float_reg(),
1388 op->in_opr2()->as_xmm_float_reg(),
1389 op->in_opr3()->as_xmm_float_reg());
1390 break;
1391 default: ShouldNotReachHere(); break;
1392 }
1393 }
1394
1395 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1396 #ifdef ASSERT
1397 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1398 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1399 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1400 #endif
1401
1402 if (op->cond() == lir_cond_always) {
1403 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1404 __ jmp (*(op->label()));
1405 } else {
1406 Assembler::Condition acond = Assembler::zero;
1407 if (op->code() == lir_cond_float_branch) {
1408 assert(op->ublock() != nullptr, "must have unordered successor");
1409 __ jcc(Assembler::parity, *(op->ublock()->label()));
1410 switch(op->cond()) {
1411 case lir_cond_equal: acond = Assembler::equal; break;
1412 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1413 case lir_cond_less: acond = Assembler::below; break;
1414 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1415 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1416 case lir_cond_greater: acond = Assembler::above; break;
1417 default: ShouldNotReachHere();
1418 }
1419 } else {
1420 switch (op->cond()) {
1421 case lir_cond_equal: acond = Assembler::equal; break;
1422 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1423 case lir_cond_less: acond = Assembler::less; break;
1424 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1425 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1426 case lir_cond_greater: acond = Assembler::greater; break;
1427 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1428 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1429 default: ShouldNotReachHere();
1430 }
1431 }
1432 __ jcc(acond,*(op->label()));
1433 }
1434 }
1435
1436 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1437 LIR_Opr src = op->in_opr();
1438 LIR_Opr dest = op->result_opr();
1439
1440 switch (op->bytecode()) {
1441 case Bytecodes::_i2l:
1442 #ifdef _LP64
1443 __ movl2ptr(dest->as_register_lo(), src->as_register());
1444 #else
1445 move_regs(src->as_register(), dest->as_register_lo());
1446 move_regs(src->as_register(), dest->as_register_hi());
1447 __ sarl(dest->as_register_hi(), 31);
1448 #endif // LP64
1449 break;
1450
1451 case Bytecodes::_l2i:
1452 #ifdef _LP64
1453 __ movl(dest->as_register(), src->as_register_lo());
1454 #else
1455 move_regs(src->as_register_lo(), dest->as_register());
1456 #endif
1457 break;
1458
1459 case Bytecodes::_i2b:
1460 move_regs(src->as_register(), dest->as_register());
1461 __ sign_extend_byte(dest->as_register());
1462 break;
1463
1464 case Bytecodes::_i2c:
1465 move_regs(src->as_register(), dest->as_register());
1466 __ andl(dest->as_register(), 0xFFFF);
1467 break;
1468
1469 case Bytecodes::_i2s:
1470 move_regs(src->as_register(), dest->as_register());
1471 __ sign_extend_short(dest->as_register());
1472 break;
1473
1474
1475 #ifdef _LP64
1476 case Bytecodes::_f2d:
1477 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1478 break;
1479
1480 case Bytecodes::_d2f:
1481 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1482 break;
1483
1484 case Bytecodes::_i2f:
1485 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1486 break;
1487
1488 case Bytecodes::_i2d:
1489 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1490 break;
1491
1492 case Bytecodes::_l2f:
1493 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1494 break;
1495
1496 case Bytecodes::_l2d:
1497 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1498 break;
1499
1500 case Bytecodes::_f2i:
1501 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1502 break;
1503
1504 case Bytecodes::_d2i:
1505 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1506 break;
1507
1508 case Bytecodes::_f2l:
1509 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1510 break;
1511
1512 case Bytecodes::_d2l:
1513 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1514 break;
1515 #else
1516 case Bytecodes::_f2d:
1517 case Bytecodes::_d2f:
1518 if (dest->is_single_xmm()) {
1519 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1520 } else if (dest->is_double_xmm()) {
1521 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1522 } else {
1523 assert(src->fpu() == dest->fpu(), "register must be equal");
1524 // do nothing (float result is rounded later through spilling)
1525 }
1526 break;
1527
1528 case Bytecodes::_i2f:
1529 case Bytecodes::_i2d:
1530 if (dest->is_single_xmm()) {
1531 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1532 } else if (dest->is_double_xmm()) {
1533 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1534 } else {
1535 assert(dest->fpu() == 0, "result must be on TOS");
1536 __ movl(Address(rsp, 0), src->as_register());
1537 __ fild_s(Address(rsp, 0));
1538 }
1539 break;
1540
1541 case Bytecodes::_l2f:
1542 case Bytecodes::_l2d:
1543 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1544 assert(dest->fpu() == 0, "result must be on TOS");
1545 __ movptr(Address(rsp, 0), src->as_register_lo());
1546 __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1547 __ fild_d(Address(rsp, 0));
1548 // float result is rounded later through spilling
1549 break;
1550
1551 case Bytecodes::_f2i:
1552 case Bytecodes::_d2i:
1553 if (src->is_single_xmm()) {
1554 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1555 } else if (src->is_double_xmm()) {
1556 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1557 } else {
1558 assert(src->fpu() == 0, "input must be on TOS");
1559 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc()));
1560 __ fist_s(Address(rsp, 0));
1561 __ movl(dest->as_register(), Address(rsp, 0));
1562 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
1563 }
1564 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1565 assert(op->stub() != nullptr, "stub required");
1566 __ cmpl(dest->as_register(), 0x80000000);
1567 __ jcc(Assembler::equal, *op->stub()->entry());
1568 __ bind(*op->stub()->continuation());
1569 break;
1570
1571 case Bytecodes::_f2l:
1572 case Bytecodes::_d2l:
1573 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1574 assert(src->fpu() == 0, "input must be on TOS");
1575 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1576
1577 // instruction sequence too long to inline it here
1578 {
1579 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1580 }
1581 break;
1582 #endif // _LP64
1583
1584 default: ShouldNotReachHere();
1585 }
1586 }
1587
1588 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1589 if (op->init_check()) {
1590 add_debug_info_for_null_check_here(op->stub()->info());
1591 __ cmpb(Address(op->klass()->as_register(),
1592 InstanceKlass::init_state_offset()),
1593 InstanceKlass::fully_initialized);
1594 __ jcc(Assembler::notEqual, *op->stub()->entry());
1595 }
1596 __ allocate_object(op->obj()->as_register(),
1597 op->tmp1()->as_register(),
1598 op->tmp2()->as_register(),
1599 op->header_size(),
1600 op->object_size(),
1601 op->klass()->as_register(),
1602 *op->stub()->entry());
1603 __ bind(*op->stub()->continuation());
1604 }
1605
1606 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1607 Register len = op->len()->as_register();
1608 LP64_ONLY( __ movslq(len, len); )
1609
1610 if (UseSlowPath ||
1611 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1612 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1613 __ jmp(*op->stub()->entry());
1614 } else {
1615 Register tmp1 = op->tmp1()->as_register();
1616 Register tmp2 = op->tmp2()->as_register();
1617 Register tmp3 = op->tmp3()->as_register();
1618 if (len == tmp1) {
1619 tmp1 = tmp3;
1620 } else if (len == tmp2) {
1621 tmp2 = tmp3;
1622 } else if (len == tmp3) {
1623 // everything is ok
1624 } else {
1625 __ mov(tmp3, len);
1626 }
1627 __ allocate_array(op->obj()->as_register(),
1628 len,
1629 tmp1,
1630 tmp2,
1631 arrayOopDesc::base_offset_in_bytes(op->type()),
1632 array_element_size(op->type()),
1633 op->klass()->as_register(),
1634 *op->stub()->entry(),
1635 op->zero_array());
1636 }
1637 __ bind(*op->stub()->continuation());
1638 }
1639
1640 void LIR_Assembler::type_profile_helper(Register mdo,
1641 ciMethodData *md, ciProfileData *data,
1642 Register recv, Label* update_done) {
1643 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1644 Label next_test;
1645 // See if the receiver is receiver[n].
1646 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1647 __ jccb(Assembler::notEqual, next_test);
1648 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1649 __ addptr(data_addr, DataLayout::counter_increment);
1650 __ jmp(*update_done);
1651 __ bind(next_test);
1652 }
1653
1654 // Didn't find receiver; find next empty slot and fill it in
1655 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1656 Label next_test;
1657 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1658 __ cmpptr(recv_addr, NULL_WORD);
1659 __ jccb(Assembler::notEqual, next_test);
1660 __ movptr(recv_addr, recv);
1661 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1662 __ jmp(*update_done);
1663 __ bind(next_test);
1664 }
1665 }
1666
1667 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1668 // we always need a stub for the failure case.
1669 CodeStub* stub = op->stub();
1670 Register obj = op->object()->as_register();
1671 Register k_RInfo = op->tmp1()->as_register();
1672 Register klass_RInfo = op->tmp2()->as_register();
1673 Register dst = op->result_opr()->as_register();
1674 ciKlass* k = op->klass();
1675 Register Rtmp1 = noreg;
1676 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1677
1678 // check if it needs to be profiled
1679 ciMethodData* md = nullptr;
1680 ciProfileData* data = nullptr;
1681
1682 if (op->should_profile()) {
1683 ciMethod* method = op->profiled_method();
1684 assert(method != nullptr, "Should have method");
1685 int bci = op->profiled_bci();
1686 md = method->method_data_or_null();
1687 assert(md != nullptr, "Sanity");
1688 data = md->bci_to_data(bci);
1689 assert(data != nullptr, "need data for type check");
1690 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1691 }
1692 Label* success_target = success;
1693 Label* failure_target = failure;
1694
1695 if (obj == k_RInfo) {
1696 k_RInfo = dst;
1697 } else if (obj == klass_RInfo) {
1698 klass_RInfo = dst;
1699 }
1700 if (k->is_loaded() && !UseCompressedClassPointers) {
1701 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1702 } else {
1703 Rtmp1 = op->tmp3()->as_register();
1704 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1705 }
1706
1707 assert_different_registers(obj, k_RInfo, klass_RInfo);
1708
1709 __ testptr(obj, obj);
1710 if (op->should_profile()) {
1711 Label not_null;
1712 Register mdo = klass_RInfo;
1713 __ mov_metadata(mdo, md->constant_encoding());
1714 __ jccb(Assembler::notEqual, not_null);
1715 // Object is null; update MDO and exit
1716 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1717 int header_bits = BitData::null_seen_byte_constant();
1718 __ orb(data_addr, header_bits);
1719 __ jmp(*obj_is_null);
1720 __ bind(not_null);
1721
1722 Label update_done;
1723 Register recv = k_RInfo;
1724 __ load_klass(recv, obj, tmp_load_klass);
1725 type_profile_helper(mdo, md, data, recv, &update_done);
1726
1727 Address nonprofiled_receiver_count_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1728 __ addptr(nonprofiled_receiver_count_addr, DataLayout::counter_increment);
1729
1730 __ bind(update_done);
1731 } else {
1732 __ jcc(Assembler::equal, *obj_is_null);
1733 }
1734
1735 if (!k->is_loaded()) {
1736 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1737 } else {
1738 #ifdef _LP64
1739 __ mov_metadata(k_RInfo, k->constant_encoding());
1740 #endif // _LP64
1741 }
1742 __ verify_oop(obj);
1743
1744 if (op->fast_check()) {
1745 // get object class
1746 // not a safepoint as obj null check happens earlier
1747 #ifdef _LP64
1748 if (UseCompressedClassPointers) {
1749 __ load_klass(Rtmp1, obj, tmp_load_klass);
1750 __ cmpptr(k_RInfo, Rtmp1);
1751 } else {
1752 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1753 }
1754 #else
1755 if (k->is_loaded()) {
1756 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1757 } else {
1758 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1759 }
1760 #endif
1761 __ jcc(Assembler::notEqual, *failure_target);
1762 // successful cast, fall through to profile or jump
1763 } else {
1764 // get object class
1765 // not a safepoint as obj null check happens earlier
1766 __ load_klass(klass_RInfo, obj, tmp_load_klass);
1767 if (k->is_loaded()) {
1768 // See if we get an immediate positive hit
1769 #ifdef _LP64
1770 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1771 #else
1772 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1773 #endif // _LP64
1774 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1775 __ jcc(Assembler::notEqual, *failure_target);
1776 // successful cast, fall through to profile or jump
1777 } else {
1778 // See if we get an immediate positive hit
1779 __ jcc(Assembler::equal, *success_target);
1780 // check for self
1781 #ifdef _LP64
1782 __ cmpptr(klass_RInfo, k_RInfo);
1783 #else
1784 __ cmpklass(klass_RInfo, k->constant_encoding());
1785 #endif // _LP64
1786 __ jcc(Assembler::equal, *success_target);
1787
1788 __ push(klass_RInfo);
1789 #ifdef _LP64
1790 __ push(k_RInfo);
1791 #else
1792 __ pushklass(k->constant_encoding(), noreg);
1793 #endif // _LP64
1794 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1795 __ pop(klass_RInfo);
1796 __ pop(klass_RInfo);
1797 // result is a boolean
1798 __ testl(klass_RInfo, klass_RInfo);
1799 __ jcc(Assembler::equal, *failure_target);
1800 // successful cast, fall through to profile or jump
1801 }
1802 } else {
1803 // perform the fast part of the checking logic
1804 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1805 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1806 __ push(klass_RInfo);
1807 __ push(k_RInfo);
1808 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1809 __ pop(klass_RInfo);
1810 __ pop(k_RInfo);
1811 // result is a boolean
1812 __ testl(k_RInfo, k_RInfo);
1813 __ jcc(Assembler::equal, *failure_target);
1814 // successful cast, fall through to profile or jump
1815 }
1816 }
1817 __ jmp(*success);
1818 }
1819
1820
1821 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1822 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1823 LIR_Code code = op->code();
1824 if (code == lir_store_check) {
1825 Register value = op->object()->as_register();
1826 Register array = op->array()->as_register();
1827 Register k_RInfo = op->tmp1()->as_register();
1828 Register klass_RInfo = op->tmp2()->as_register();
1829 Register Rtmp1 = op->tmp3()->as_register();
1830
1831 CodeStub* stub = op->stub();
1832
1833 // check if it needs to be profiled
1834 ciMethodData* md = nullptr;
1835 ciProfileData* data = nullptr;
1836
1837 if (op->should_profile()) {
1838 ciMethod* method = op->profiled_method();
1839 assert(method != nullptr, "Should have method");
1840 int bci = op->profiled_bci();
1841 md = method->method_data_or_null();
1842 assert(md != nullptr, "Sanity");
1843 data = md->bci_to_data(bci);
1844 assert(data != nullptr, "need data for type check");
1845 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1846 }
1847 Label done;
1848 Label* success_target = &done;
1849 Label* failure_target = stub->entry();
1850
1851 __ testptr(value, value);
1852 if (op->should_profile()) {
1853 Label not_null;
1854 Register mdo = klass_RInfo;
1855 __ mov_metadata(mdo, md->constant_encoding());
1856 __ jccb(Assembler::notEqual, not_null);
1857 // Object is null; update MDO and exit
1858 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1859 int header_bits = BitData::null_seen_byte_constant();
1860 __ orb(data_addr, header_bits);
1861 __ jmp(done);
1862 __ bind(not_null);
1863
1864 Label update_done;
1865 Register recv = k_RInfo;
1866 __ load_klass(recv, value, tmp_load_klass);
1867 type_profile_helper(mdo, md, data, recv, &update_done);
1868
1869 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1870 __ addptr(counter_addr, DataLayout::counter_increment);
1871 __ bind(update_done);
1872 } else {
1873 __ jcc(Assembler::equal, done);
1874 }
1875
1876 add_debug_info_for_null_check_here(op->info_for_exception());
1877 __ load_klass(k_RInfo, array, tmp_load_klass);
1878 __ load_klass(klass_RInfo, value, tmp_load_klass);
1879
1880 // get instance klass (it's already uncompressed)
1881 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1882 // perform the fast part of the checking logic
1883 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1884 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1885 __ push(klass_RInfo);
1886 __ push(k_RInfo);
1887 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1888 __ pop(klass_RInfo);
1889 __ pop(k_RInfo);
1890 // result is a boolean
1891 __ testl(k_RInfo, k_RInfo);
1892 __ jcc(Assembler::equal, *failure_target);
1893 // fall through to the success case
1894
1895 __ bind(done);
1896 } else
1897 if (code == lir_checkcast) {
1898 Register obj = op->object()->as_register();
1899 Register dst = op->result_opr()->as_register();
1900 Label success;
1901 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1902 __ bind(success);
1903 if (dst != obj) {
1904 __ mov(dst, obj);
1905 }
1906 } else
1907 if (code == lir_instanceof) {
1908 Register obj = op->object()->as_register();
1909 Register dst = op->result_opr()->as_register();
1910 Label success, failure, done;
1911 emit_typecheck_helper(op, &success, &failure, &failure);
1912 __ bind(failure);
1913 __ xorptr(dst, dst);
1914 __ jmpb(done);
1915 __ bind(success);
1916 __ movptr(dst, 1);
1917 __ bind(done);
1918 } else {
1919 ShouldNotReachHere();
1920 }
1921
1922 }
1923
1924
1925 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1926 if (LP64_ONLY(false &&) op->code() == lir_cas_long) {
1927 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1928 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1929 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1930 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1931 Register addr = op->addr()->as_register();
1932 __ lock();
1933 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1934
1935 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1936 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1937 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1938 Register newval = op->new_value()->as_register();
1939 Register cmpval = op->cmp_value()->as_register();
1940 assert(cmpval == rax, "wrong register");
1941 assert(newval != noreg, "new val must be register");
1942 assert(cmpval != newval, "cmp and new values must be in different registers");
1943 assert(cmpval != addr, "cmp and addr must be in different registers");
1944 assert(newval != addr, "new value and addr must be in different registers");
1945
1946 if ( op->code() == lir_cas_obj) {
1947 #ifdef _LP64
1948 if (UseCompressedOops) {
1949 __ encode_heap_oop(cmpval);
1950 __ mov(rscratch1, newval);
1951 __ encode_heap_oop(rscratch1);
1952 __ lock();
1953 // cmpval (rax) is implicitly used by this instruction
1954 __ cmpxchgl(rscratch1, Address(addr, 0));
1955 } else
1956 #endif
1957 {
1958 __ lock();
1959 __ cmpxchgptr(newval, Address(addr, 0));
1960 }
1961 } else {
1962 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1963 __ lock();
1964 __ cmpxchgl(newval, Address(addr, 0));
1965 }
1966 #ifdef _LP64
1967 } else if (op->code() == lir_cas_long) {
1968 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1969 Register newval = op->new_value()->as_register_lo();
1970 Register cmpval = op->cmp_value()->as_register_lo();
1971 assert(cmpval == rax, "wrong register");
1972 assert(newval != noreg, "new val must be register");
1973 assert(cmpval != newval, "cmp and new values must be in different registers");
1974 assert(cmpval != addr, "cmp and addr must be in different registers");
1975 assert(newval != addr, "new value and addr must be in different registers");
1976 __ lock();
1977 __ cmpxchgq(newval, Address(addr, 0));
1978 #endif // _LP64
1979 } else {
1980 Unimplemented();
1981 }
1982 }
1983
1984 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1985 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1986 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
1987
1988 Assembler::Condition acond, ncond;
1989 switch (condition) {
1990 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1991 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1992 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1993 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1994 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1995 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1996 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1997 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1998 default: acond = Assembler::equal; ncond = Assembler::notEqual;
1999 ShouldNotReachHere();
2000 }
2001
2002 if (opr1->is_cpu_register()) {
2003 reg2reg(opr1, result);
2004 } else if (opr1->is_stack()) {
2005 stack2reg(opr1, result, result->type());
2006 } else if (opr1->is_constant()) {
2007 const2reg(opr1, result, lir_patch_none, nullptr);
2008 } else {
2009 ShouldNotReachHere();
2010 }
2011
2012 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2013 // optimized version that does not require a branch
2014 if (opr2->is_single_cpu()) {
2015 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2016 __ cmov(ncond, result->as_register(), opr2->as_register());
2017 } else if (opr2->is_double_cpu()) {
2018 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2019 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2020 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2021 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2022 } else if (opr2->is_single_stack()) {
2023 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2024 } else if (opr2->is_double_stack()) {
2025 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2026 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2027 } else {
2028 ShouldNotReachHere();
2029 }
2030
2031 } else {
2032 Label skip;
2033 __ jccb(acond, skip);
2034 if (opr2->is_cpu_register()) {
2035 reg2reg(opr2, result);
2036 } else if (opr2->is_stack()) {
2037 stack2reg(opr2, result, result->type());
2038 } else if (opr2->is_constant()) {
2039 const2reg(opr2, result, lir_patch_none, nullptr);
2040 } else {
2041 ShouldNotReachHere();
2042 }
2043 __ bind(skip);
2044 }
2045 }
2046
2047
2048 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2049 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2050
2051 if (left->is_single_cpu()) {
2052 assert(left == dest, "left and dest must be equal");
2053 Register lreg = left->as_register();
2054
2055 if (right->is_single_cpu()) {
2056 // cpu register - cpu register
2057 Register rreg = right->as_register();
2058 switch (code) {
2059 case lir_add: __ addl (lreg, rreg); break;
2060 case lir_sub: __ subl (lreg, rreg); break;
2061 case lir_mul: __ imull(lreg, rreg); break;
2062 default: ShouldNotReachHere();
2063 }
2064
2065 } else if (right->is_stack()) {
2066 // cpu register - stack
2067 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2068 switch (code) {
2069 case lir_add: __ addl(lreg, raddr); break;
2070 case lir_sub: __ subl(lreg, raddr); break;
2071 default: ShouldNotReachHere();
2072 }
2073
2074 } else if (right->is_constant()) {
2075 // cpu register - constant
2076 jint c = right->as_constant_ptr()->as_jint();
2077 switch (code) {
2078 case lir_add: {
2079 __ incrementl(lreg, c);
2080 break;
2081 }
2082 case lir_sub: {
2083 __ decrementl(lreg, c);
2084 break;
2085 }
2086 default: ShouldNotReachHere();
2087 }
2088
2089 } else {
2090 ShouldNotReachHere();
2091 }
2092
2093 } else if (left->is_double_cpu()) {
2094 assert(left == dest, "left and dest must be equal");
2095 Register lreg_lo = left->as_register_lo();
2096 Register lreg_hi = left->as_register_hi();
2097
2098 if (right->is_double_cpu()) {
2099 // cpu register - cpu register
2100 Register rreg_lo = right->as_register_lo();
2101 Register rreg_hi = right->as_register_hi();
2102 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2103 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2104 switch (code) {
2105 case lir_add:
2106 __ addptr(lreg_lo, rreg_lo);
2107 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2108 break;
2109 case lir_sub:
2110 __ subptr(lreg_lo, rreg_lo);
2111 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2112 break;
2113 case lir_mul:
2114 #ifdef _LP64
2115 __ imulq(lreg_lo, rreg_lo);
2116 #else
2117 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2118 __ imull(lreg_hi, rreg_lo);
2119 __ imull(rreg_hi, lreg_lo);
2120 __ addl (rreg_hi, lreg_hi);
2121 __ mull (rreg_lo);
2122 __ addl (lreg_hi, rreg_hi);
2123 #endif // _LP64
2124 break;
2125 default:
2126 ShouldNotReachHere();
2127 }
2128
2129 } else if (right->is_constant()) {
2130 // cpu register - constant
2131 #ifdef _LP64
2132 jlong c = right->as_constant_ptr()->as_jlong_bits();
2133 __ movptr(r10, (intptr_t) c);
2134 switch (code) {
2135 case lir_add:
2136 __ addptr(lreg_lo, r10);
2137 break;
2138 case lir_sub:
2139 __ subptr(lreg_lo, r10);
2140 break;
2141 default:
2142 ShouldNotReachHere();
2143 }
2144 #else
2145 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2146 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2147 switch (code) {
2148 case lir_add:
2149 __ addptr(lreg_lo, c_lo);
2150 __ adcl(lreg_hi, c_hi);
2151 break;
2152 case lir_sub:
2153 __ subptr(lreg_lo, c_lo);
2154 __ sbbl(lreg_hi, c_hi);
2155 break;
2156 default:
2157 ShouldNotReachHere();
2158 }
2159 #endif // _LP64
2160
2161 } else {
2162 ShouldNotReachHere();
2163 }
2164
2165 } else if (left->is_single_xmm()) {
2166 assert(left == dest, "left and dest must be equal");
2167 XMMRegister lreg = left->as_xmm_float_reg();
2168
2169 if (right->is_single_xmm()) {
2170 XMMRegister rreg = right->as_xmm_float_reg();
2171 switch (code) {
2172 case lir_add: __ addss(lreg, rreg); break;
2173 case lir_sub: __ subss(lreg, rreg); break;
2174 case lir_mul: __ mulss(lreg, rreg); break;
2175 case lir_div: __ divss(lreg, rreg); break;
2176 default: ShouldNotReachHere();
2177 }
2178 } else {
2179 Address raddr;
2180 if (right->is_single_stack()) {
2181 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2182 } else if (right->is_constant()) {
2183 // hack for now
2184 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2185 } else {
2186 ShouldNotReachHere();
2187 }
2188 switch (code) {
2189 case lir_add: __ addss(lreg, raddr); break;
2190 case lir_sub: __ subss(lreg, raddr); break;
2191 case lir_mul: __ mulss(lreg, raddr); break;
2192 case lir_div: __ divss(lreg, raddr); break;
2193 default: ShouldNotReachHere();
2194 }
2195 }
2196
2197 } else if (left->is_double_xmm()) {
2198 assert(left == dest, "left and dest must be equal");
2199
2200 XMMRegister lreg = left->as_xmm_double_reg();
2201 if (right->is_double_xmm()) {
2202 XMMRegister rreg = right->as_xmm_double_reg();
2203 switch (code) {
2204 case lir_add: __ addsd(lreg, rreg); break;
2205 case lir_sub: __ subsd(lreg, rreg); break;
2206 case lir_mul: __ mulsd(lreg, rreg); break;
2207 case lir_div: __ divsd(lreg, rreg); break;
2208 default: ShouldNotReachHere();
2209 }
2210 } else {
2211 Address raddr;
2212 if (right->is_double_stack()) {
2213 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2214 } else if (right->is_constant()) {
2215 // hack for now
2216 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2217 } else {
2218 ShouldNotReachHere();
2219 }
2220 switch (code) {
2221 case lir_add: __ addsd(lreg, raddr); break;
2222 case lir_sub: __ subsd(lreg, raddr); break;
2223 case lir_mul: __ mulsd(lreg, raddr); break;
2224 case lir_div: __ divsd(lreg, raddr); break;
2225 default: ShouldNotReachHere();
2226 }
2227 }
2228
2229 #ifndef _LP64
2230 } else if (left->is_single_fpu()) {
2231 assert(dest->is_single_fpu(), "fpu stack allocation required");
2232
2233 if (right->is_single_fpu()) {
2234 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2235
2236 } else {
2237 assert(left->fpu_regnr() == 0, "left must be on TOS");
2238 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2239
2240 Address raddr;
2241 if (right->is_single_stack()) {
2242 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2243 } else if (right->is_constant()) {
2244 address const_addr = float_constant(right->as_jfloat());
2245 assert(const_addr != nullptr, "incorrect float/double constant maintenance");
2246 // hack for now
2247 raddr = __ as_Address(InternalAddress(const_addr));
2248 } else {
2249 ShouldNotReachHere();
2250 }
2251
2252 switch (code) {
2253 case lir_add: __ fadd_s(raddr); break;
2254 case lir_sub: __ fsub_s(raddr); break;
2255 case lir_mul: __ fmul_s(raddr); break;
2256 case lir_div: __ fdiv_s(raddr); break;
2257 default: ShouldNotReachHere();
2258 }
2259 }
2260
2261 } else if (left->is_double_fpu()) {
2262 assert(dest->is_double_fpu(), "fpu stack allocation required");
2263
2264 if (code == lir_mul || code == lir_div) {
2265 // Double values require special handling for strictfp mul/div on x86
2266 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1()));
2267 __ fmulp(left->fpu_regnrLo() + 1);
2268 }
2269
2270 if (right->is_double_fpu()) {
2271 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2272
2273 } else {
2274 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2275 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2276
2277 Address raddr;
2278 if (right->is_double_stack()) {
2279 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2280 } else if (right->is_constant()) {
2281 // hack for now
2282 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2283 } else {
2284 ShouldNotReachHere();
2285 }
2286
2287 switch (code) {
2288 case lir_add: __ fadd_d(raddr); break;
2289 case lir_sub: __ fsub_d(raddr); break;
2290 case lir_mul: __ fmul_d(raddr); break;
2291 case lir_div: __ fdiv_d(raddr); break;
2292 default: ShouldNotReachHere();
2293 }
2294 }
2295
2296 if (code == lir_mul || code == lir_div) {
2297 // Double values require special handling for strictfp mul/div on x86
2298 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2()));
2299 __ fmulp(dest->fpu_regnrLo() + 1);
2300 }
2301 #endif // !_LP64
2302
2303 } else if (left->is_single_stack() || left->is_address()) {
2304 assert(left == dest, "left and dest must be equal");
2305
2306 Address laddr;
2307 if (left->is_single_stack()) {
2308 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2309 } else if (left->is_address()) {
2310 laddr = as_Address(left->as_address_ptr());
2311 } else {
2312 ShouldNotReachHere();
2313 }
2314
2315 if (right->is_single_cpu()) {
2316 Register rreg = right->as_register();
2317 switch (code) {
2318 case lir_add: __ addl(laddr, rreg); break;
2319 case lir_sub: __ subl(laddr, rreg); break;
2320 default: ShouldNotReachHere();
2321 }
2322 } else if (right->is_constant()) {
2323 jint c = right->as_constant_ptr()->as_jint();
2324 switch (code) {
2325 case lir_add: {
2326 __ incrementl(laddr, c);
2327 break;
2328 }
2329 case lir_sub: {
2330 __ decrementl(laddr, c);
2331 break;
2332 }
2333 default: ShouldNotReachHere();
2334 }
2335 } else {
2336 ShouldNotReachHere();
2337 }
2338
2339 } else {
2340 ShouldNotReachHere();
2341 }
2342 }
2343
2344 #ifndef _LP64
2345 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2346 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2347 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2348 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2349
2350 bool left_is_tos = (left_index == 0);
2351 bool dest_is_tos = (dest_index == 0);
2352 int non_tos_index = (left_is_tos ? right_index : left_index);
2353
2354 switch (code) {
2355 case lir_add:
2356 if (pop_fpu_stack) __ faddp(non_tos_index);
2357 else if (dest_is_tos) __ fadd (non_tos_index);
2358 else __ fadda(non_tos_index);
2359 break;
2360
2361 case lir_sub:
2362 if (left_is_tos) {
2363 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2364 else if (dest_is_tos) __ fsub (non_tos_index);
2365 else __ fsubra(non_tos_index);
2366 } else {
2367 if (pop_fpu_stack) __ fsubp (non_tos_index);
2368 else if (dest_is_tos) __ fsubr (non_tos_index);
2369 else __ fsuba (non_tos_index);
2370 }
2371 break;
2372
2373 case lir_mul:
2374 if (pop_fpu_stack) __ fmulp(non_tos_index);
2375 else if (dest_is_tos) __ fmul (non_tos_index);
2376 else __ fmula(non_tos_index);
2377 break;
2378
2379 case lir_div:
2380 if (left_is_tos) {
2381 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2382 else if (dest_is_tos) __ fdiv (non_tos_index);
2383 else __ fdivra(non_tos_index);
2384 } else {
2385 if (pop_fpu_stack) __ fdivp (non_tos_index);
2386 else if (dest_is_tos) __ fdivr (non_tos_index);
2387 else __ fdiva (non_tos_index);
2388 }
2389 break;
2390
2391 case lir_rem:
2392 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2393 __ fremr(noreg);
2394 break;
2395
2396 default:
2397 ShouldNotReachHere();
2398 }
2399 }
2400 #endif // _LP64
2401
2402
2403 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2404 if (value->is_double_xmm()) {
2405 switch(code) {
2406 case lir_abs :
2407 {
2408 #ifdef _LP64
2409 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2410 assert(tmp->is_valid(), "need temporary");
2411 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2412 } else
2413 #endif
2414 {
2415 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2416 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2417 }
2418 assert(!tmp->is_valid(), "do not need temporary");
2419 __ andpd(dest->as_xmm_double_reg(),
2420 ExternalAddress(LIR_Assembler::double_signmask_pool),
2421 rscratch1);
2422 }
2423 }
2424 break;
2425
2426 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2427 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2428 default : ShouldNotReachHere();
2429 }
2430
2431 #ifndef _LP64
2432 } else if (value->is_double_fpu()) {
2433 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2434 switch(code) {
2435 case lir_abs : __ fabs() ; break;
2436 case lir_sqrt : __ fsqrt(); break;
2437 default : ShouldNotReachHere();
2438 }
2439 #endif // !_LP64
2440 } else if (code == lir_f2hf) {
2441 __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg());
2442 } else if (code == lir_hf2f) {
2443 __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register());
2444 } else {
2445 Unimplemented();
2446 }
2447 }
2448
2449 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2450 // assert(left->destroys_register(), "check");
2451 if (left->is_single_cpu()) {
2452 Register reg = left->as_register();
2453 if (right->is_constant()) {
2454 int val = right->as_constant_ptr()->as_jint();
2455 switch (code) {
2456 case lir_logic_and: __ andl (reg, val); break;
2457 case lir_logic_or: __ orl (reg, val); break;
2458 case lir_logic_xor: __ xorl (reg, val); break;
2459 default: ShouldNotReachHere();
2460 }
2461 } else if (right->is_stack()) {
2462 // added support for stack operands
2463 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2464 switch (code) {
2465 case lir_logic_and: __ andl (reg, raddr); break;
2466 case lir_logic_or: __ orl (reg, raddr); break;
2467 case lir_logic_xor: __ xorl (reg, raddr); break;
2468 default: ShouldNotReachHere();
2469 }
2470 } else {
2471 Register rright = right->as_register();
2472 switch (code) {
2473 case lir_logic_and: __ andptr (reg, rright); break;
2474 case lir_logic_or : __ orptr (reg, rright); break;
2475 case lir_logic_xor: __ xorptr (reg, rright); break;
2476 default: ShouldNotReachHere();
2477 }
2478 }
2479 move_regs(reg, dst->as_register());
2480 } else {
2481 Register l_lo = left->as_register_lo();
2482 Register l_hi = left->as_register_hi();
2483 if (right->is_constant()) {
2484 #ifdef _LP64
2485 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2486 switch (code) {
2487 case lir_logic_and:
2488 __ andq(l_lo, rscratch1);
2489 break;
2490 case lir_logic_or:
2491 __ orq(l_lo, rscratch1);
2492 break;
2493 case lir_logic_xor:
2494 __ xorq(l_lo, rscratch1);
2495 break;
2496 default: ShouldNotReachHere();
2497 }
2498 #else
2499 int r_lo = right->as_constant_ptr()->as_jint_lo();
2500 int r_hi = right->as_constant_ptr()->as_jint_hi();
2501 switch (code) {
2502 case lir_logic_and:
2503 __ andl(l_lo, r_lo);
2504 __ andl(l_hi, r_hi);
2505 break;
2506 case lir_logic_or:
2507 __ orl(l_lo, r_lo);
2508 __ orl(l_hi, r_hi);
2509 break;
2510 case lir_logic_xor:
2511 __ xorl(l_lo, r_lo);
2512 __ xorl(l_hi, r_hi);
2513 break;
2514 default: ShouldNotReachHere();
2515 }
2516 #endif // _LP64
2517 } else {
2518 #ifdef _LP64
2519 Register r_lo;
2520 if (is_reference_type(right->type())) {
2521 r_lo = right->as_register();
2522 } else {
2523 r_lo = right->as_register_lo();
2524 }
2525 #else
2526 Register r_lo = right->as_register_lo();
2527 Register r_hi = right->as_register_hi();
2528 assert(l_lo != r_hi, "overwriting registers");
2529 #endif
2530 switch (code) {
2531 case lir_logic_and:
2532 __ andptr(l_lo, r_lo);
2533 NOT_LP64(__ andptr(l_hi, r_hi);)
2534 break;
2535 case lir_logic_or:
2536 __ orptr(l_lo, r_lo);
2537 NOT_LP64(__ orptr(l_hi, r_hi);)
2538 break;
2539 case lir_logic_xor:
2540 __ xorptr(l_lo, r_lo);
2541 NOT_LP64(__ xorptr(l_hi, r_hi);)
2542 break;
2543 default: ShouldNotReachHere();
2544 }
2545 }
2546
2547 Register dst_lo = dst->as_register_lo();
2548 Register dst_hi = dst->as_register_hi();
2549
2550 #ifdef _LP64
2551 move_regs(l_lo, dst_lo);
2552 #else
2553 if (dst_lo == l_hi) {
2554 assert(dst_hi != l_lo, "overwriting registers");
2555 move_regs(l_hi, dst_hi);
2556 move_regs(l_lo, dst_lo);
2557 } else {
2558 assert(dst_lo != l_hi, "overwriting registers");
2559 move_regs(l_lo, dst_lo);
2560 move_regs(l_hi, dst_hi);
2561 }
2562 #endif // _LP64
2563 }
2564 }
2565
2566
2567 // we assume that rax, and rdx can be overwritten
2568 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2569
2570 assert(left->is_single_cpu(), "left must be register");
2571 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2572 assert(result->is_single_cpu(), "result must be register");
2573
2574 // assert(left->destroys_register(), "check");
2575 // assert(right->destroys_register(), "check");
2576
2577 Register lreg = left->as_register();
2578 Register dreg = result->as_register();
2579
2580 if (right->is_constant()) {
2581 jint divisor = right->as_constant_ptr()->as_jint();
2582 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2583 if (code == lir_idiv) {
2584 assert(lreg == rax, "must be rax,");
2585 assert(temp->as_register() == rdx, "tmp register must be rdx");
2586 __ cdql(); // sign extend into rdx:rax
2587 if (divisor == 2) {
2588 __ subl(lreg, rdx);
2589 } else {
2590 __ andl(rdx, divisor - 1);
2591 __ addl(lreg, rdx);
2592 }
2593 __ sarl(lreg, log2i_exact(divisor));
2594 move_regs(lreg, dreg);
2595 } else if (code == lir_irem) {
2596 Label done;
2597 __ mov(dreg, lreg);
2598 __ andl(dreg, 0x80000000 | (divisor - 1));
2599 __ jcc(Assembler::positive, done);
2600 __ decrement(dreg);
2601 __ orl(dreg, ~(divisor - 1));
2602 __ increment(dreg);
2603 __ bind(done);
2604 } else {
2605 ShouldNotReachHere();
2606 }
2607 } else {
2608 Register rreg = right->as_register();
2609 assert(lreg == rax, "left register must be rax,");
2610 assert(rreg != rdx, "right register must not be rdx");
2611 assert(temp->as_register() == rdx, "tmp register must be rdx");
2612
2613 move_regs(lreg, rax);
2614
2615 int idivl_offset = __ corrected_idivl(rreg);
2616 if (ImplicitDiv0Checks) {
2617 add_debug_info_for_div0(idivl_offset, info);
2618 }
2619 if (code == lir_irem) {
2620 move_regs(rdx, dreg); // result is in rdx
2621 } else {
2622 move_regs(rax, dreg);
2623 }
2624 }
2625 }
2626
2627
2628 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2629 if (opr1->is_single_cpu()) {
2630 Register reg1 = opr1->as_register();
2631 if (opr2->is_single_cpu()) {
2632 // cpu register - cpu register
2633 if (is_reference_type(opr1->type())) {
2634 __ cmpoop(reg1, opr2->as_register());
2635 } else {
2636 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2637 __ cmpl(reg1, opr2->as_register());
2638 }
2639 } else if (opr2->is_stack()) {
2640 // cpu register - stack
2641 if (is_reference_type(opr1->type())) {
2642 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2643 } else {
2644 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2645 }
2646 } else if (opr2->is_constant()) {
2647 // cpu register - constant
2648 LIR_Const* c = opr2->as_constant_ptr();
2649 if (c->type() == T_INT) {
2650 jint i = c->as_jint();
2651 if (i == 0) {
2652 __ testl(reg1, reg1);
2653 } else {
2654 __ cmpl(reg1, i);
2655 }
2656 } else if (c->type() == T_METADATA) {
2657 // All we need for now is a comparison with null for equality.
2658 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2659 Metadata* m = c->as_metadata();
2660 if (m == nullptr) {
2661 __ testptr(reg1, reg1);
2662 } else {
2663 ShouldNotReachHere();
2664 }
2665 } else if (is_reference_type(c->type())) {
2666 // In 64bit oops are single register
2667 jobject o = c->as_jobject();
2668 if (o == nullptr) {
2669 __ testptr(reg1, reg1);
2670 } else {
2671 __ cmpoop(reg1, o, rscratch1);
2672 }
2673 } else {
2674 fatal("unexpected type: %s", basictype_to_str(c->type()));
2675 }
2676 // cpu register - address
2677 } else if (opr2->is_address()) {
2678 if (op->info() != nullptr) {
2679 add_debug_info_for_null_check_here(op->info());
2680 }
2681 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2682 } else {
2683 ShouldNotReachHere();
2684 }
2685
2686 } else if(opr1->is_double_cpu()) {
2687 Register xlo = opr1->as_register_lo();
2688 Register xhi = opr1->as_register_hi();
2689 if (opr2->is_double_cpu()) {
2690 #ifdef _LP64
2691 __ cmpptr(xlo, opr2->as_register_lo());
2692 #else
2693 // cpu register - cpu register
2694 Register ylo = opr2->as_register_lo();
2695 Register yhi = opr2->as_register_hi();
2696 __ subl(xlo, ylo);
2697 __ sbbl(xhi, yhi);
2698 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2699 __ orl(xhi, xlo);
2700 }
2701 #endif // _LP64
2702 } else if (opr2->is_constant()) {
2703 // cpu register - constant 0
2704 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2705 #ifdef _LP64
2706 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2707 #else
2708 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2709 __ orl(xhi, xlo);
2710 #endif // _LP64
2711 } else {
2712 ShouldNotReachHere();
2713 }
2714
2715 } else if (opr1->is_single_xmm()) {
2716 XMMRegister reg1 = opr1->as_xmm_float_reg();
2717 if (opr2->is_single_xmm()) {
2718 // xmm register - xmm register
2719 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2720 } else if (opr2->is_stack()) {
2721 // xmm register - stack
2722 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2723 } else if (opr2->is_constant()) {
2724 // xmm register - constant
2725 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2726 } else if (opr2->is_address()) {
2727 // xmm register - address
2728 if (op->info() != nullptr) {
2729 add_debug_info_for_null_check_here(op->info());
2730 }
2731 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2732 } else {
2733 ShouldNotReachHere();
2734 }
2735
2736 } else if (opr1->is_double_xmm()) {
2737 XMMRegister reg1 = opr1->as_xmm_double_reg();
2738 if (opr2->is_double_xmm()) {
2739 // xmm register - xmm register
2740 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2741 } else if (opr2->is_stack()) {
2742 // xmm register - stack
2743 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2744 } else if (opr2->is_constant()) {
2745 // xmm register - constant
2746 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2747 } else if (opr2->is_address()) {
2748 // xmm register - address
2749 if (op->info() != nullptr) {
2750 add_debug_info_for_null_check_here(op->info());
2751 }
2752 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2753 } else {
2754 ShouldNotReachHere();
2755 }
2756
2757 #ifndef _LP64
2758 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2759 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2760 assert(opr2->is_fpu_register(), "both must be registers");
2761 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2762 #endif // LP64
2763
2764 } else if (opr1->is_address() && opr2->is_constant()) {
2765 LIR_Const* c = opr2->as_constant_ptr();
2766 #ifdef _LP64
2767 if (is_reference_type(c->type())) {
2768 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2769 __ movoop(rscratch1, c->as_jobject());
2770 }
2771 #endif // LP64
2772 if (op->info() != nullptr) {
2773 add_debug_info_for_null_check_here(op->info());
2774 }
2775 // special case: address - constant
2776 LIR_Address* addr = opr1->as_address_ptr();
2777 if (c->type() == T_INT) {
2778 __ cmpl(as_Address(addr), c->as_jint());
2779 } else if (is_reference_type(c->type())) {
2780 #ifdef _LP64
2781 // %%% Make this explode if addr isn't reachable until we figure out a
2782 // better strategy by giving noreg as the temp for as_Address
2783 __ cmpoop(rscratch1, as_Address(addr, noreg));
2784 #else
2785 __ cmpoop(as_Address(addr), c->as_jobject());
2786 #endif // _LP64
2787 } else {
2788 ShouldNotReachHere();
2789 }
2790
2791 } else {
2792 ShouldNotReachHere();
2793 }
2794 }
2795
2796 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2797 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2798 if (left->is_single_xmm()) {
2799 assert(right->is_single_xmm(), "must match");
2800 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2801 } else if (left->is_double_xmm()) {
2802 assert(right->is_double_xmm(), "must match");
2803 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2804
2805 } else {
2806 #ifdef _LP64
2807 ShouldNotReachHere();
2808 #else
2809 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2810 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2811
2812 assert(left->fpu() == 0, "left must be on TOS");
2813 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2814 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2815 #endif // LP64
2816 }
2817 } else {
2818 assert(code == lir_cmp_l2i, "check");
2819 #ifdef _LP64
2820 Label done;
2821 Register dest = dst->as_register();
2822 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2823 __ movl(dest, -1);
2824 __ jccb(Assembler::less, done);
2825 __ setb(Assembler::notZero, dest);
2826 __ movzbl(dest, dest);
2827 __ bind(done);
2828 #else
2829 __ lcmp2int(left->as_register_hi(),
2830 left->as_register_lo(),
2831 right->as_register_hi(),
2832 right->as_register_lo());
2833 move_regs(left->as_register_hi(), dst->as_register());
2834 #endif // _LP64
2835 }
2836 }
2837
2838
2839 void LIR_Assembler::align_call(LIR_Code code) {
2840 // make sure that the displacement word of the call ends up word aligned
2841 int offset = __ offset();
2842 switch (code) {
2843 case lir_static_call:
2844 case lir_optvirtual_call:
2845 case lir_dynamic_call:
2846 offset += NativeCall::displacement_offset;
2847 break;
2848 case lir_icvirtual_call:
2849 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2850 break;
2851 default: ShouldNotReachHere();
2852 }
2853 __ align(BytesPerWord, offset);
2854 }
2855
2856
2857 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2858 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2859 "must be aligned");
2860 __ call(AddressLiteral(op->addr(), rtype));
2861 add_call_info(code_offset(), op->info());
2862 __ post_call_nop();
2863 }
2864
2865
2866 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2867 __ ic_call(op->addr());
2868 add_call_info(code_offset(), op->info());
2869 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2870 "must be aligned");
2871 __ post_call_nop();
2872 }
2873
2874
2875 void LIR_Assembler::emit_static_call_stub() {
2876 address call_pc = __ pc();
2877 address stub = __ start_a_stub(call_stub_size());
2878 if (stub == nullptr) {
2879 bailout("static call stub overflow");
2880 return;
2881 }
2882
2883 int start = __ offset();
2884
2885 // make sure that the displacement word of the call ends up word aligned
2886 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2887 __ relocate(static_stub_Relocation::spec(call_pc));
2888 __ mov_metadata(rbx, (Metadata*)nullptr);
2889 // must be set to -1 at code generation time
2890 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2891 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2892 __ jump(RuntimeAddress(__ pc()));
2893
2894 assert(__ offset() - start <= call_stub_size(), "stub too big");
2895 __ end_a_stub();
2896 }
2897
2898
2899 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2900 assert(exceptionOop->as_register() == rax, "must match");
2901 assert(exceptionPC->as_register() == rdx, "must match");
2902
2903 // exception object is not added to oop map by LinearScan
2904 // (LinearScan assumes that no oops are in fixed registers)
2905 info->add_register_oop(exceptionOop);
2906 Runtime1::StubID unwind_id;
2907
2908 // get current pc information
2909 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2910 int pc_for_athrow_offset = __ offset();
2911 InternalAddress pc_for_athrow(__ pc());
2912 __ lea(exceptionPC->as_register(), pc_for_athrow);
2913 add_call_info(pc_for_athrow_offset, info); // for exception handler
2914
2915 __ verify_not_null_oop(rax);
2916 // search an exception handler (rax: exception oop, rdx: throwing pc)
2917 if (compilation()->has_fpu_code()) {
2918 unwind_id = Runtime1::handle_exception_id;
2919 } else {
2920 unwind_id = Runtime1::handle_exception_nofpu_id;
2921 }
2922 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2923
2924 // enough room for two byte trap
2925 __ nop();
2926 }
2927
2928
2929 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2930 assert(exceptionOop->as_register() == rax, "must match");
2931
2932 __ jmp(_unwind_handler_entry);
2933 }
2934
2935
2936 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2937
2938 // optimized version for linear scan:
2939 // * count must be already in ECX (guaranteed by LinearScan)
2940 // * left and dest must be equal
2941 // * tmp must be unused
2942 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2943 assert(left == dest, "left and dest must be equal");
2944 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2945
2946 if (left->is_single_cpu()) {
2947 Register value = left->as_register();
2948 assert(value != SHIFT_count, "left cannot be ECX");
2949
2950 switch (code) {
2951 case lir_shl: __ shll(value); break;
2952 case lir_shr: __ sarl(value); break;
2953 case lir_ushr: __ shrl(value); break;
2954 default: ShouldNotReachHere();
2955 }
2956 } else if (left->is_double_cpu()) {
2957 Register lo = left->as_register_lo();
2958 Register hi = left->as_register_hi();
2959 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2960 #ifdef _LP64
2961 switch (code) {
2962 case lir_shl: __ shlptr(lo); break;
2963 case lir_shr: __ sarptr(lo); break;
2964 case lir_ushr: __ shrptr(lo); break;
2965 default: ShouldNotReachHere();
2966 }
2967 #else
2968
2969 switch (code) {
2970 case lir_shl: __ lshl(hi, lo); break;
2971 case lir_shr: __ lshr(hi, lo, true); break;
2972 case lir_ushr: __ lshr(hi, lo, false); break;
2973 default: ShouldNotReachHere();
2974 }
2975 #endif // LP64
2976 } else {
2977 ShouldNotReachHere();
2978 }
2979 }
2980
2981
2982 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2983 if (dest->is_single_cpu()) {
2984 // first move left into dest so that left is not destroyed by the shift
2985 Register value = dest->as_register();
2986 count = count & 0x1F; // Java spec
2987
2988 move_regs(left->as_register(), value);
2989 switch (code) {
2990 case lir_shl: __ shll(value, count); break;
2991 case lir_shr: __ sarl(value, count); break;
2992 case lir_ushr: __ shrl(value, count); break;
2993 default: ShouldNotReachHere();
2994 }
2995 } else if (dest->is_double_cpu()) {
2996 #ifndef _LP64
2997 Unimplemented();
2998 #else
2999 // first move left into dest so that left is not destroyed by the shift
3000 Register value = dest->as_register_lo();
3001 count = count & 0x1F; // Java spec
3002
3003 move_regs(left->as_register_lo(), value);
3004 switch (code) {
3005 case lir_shl: __ shlptr(value, count); break;
3006 case lir_shr: __ sarptr(value, count); break;
3007 case lir_ushr: __ shrptr(value, count); break;
3008 default: ShouldNotReachHere();
3009 }
3010 #endif // _LP64
3011 } else {
3012 ShouldNotReachHere();
3013 }
3014 }
3015
3016
3017 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3018 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3019 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3020 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3021 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3022 }
3023
3024
3025 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3026 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3027 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3028 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3029 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3030 }
3031
3032
3033 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3034 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3035 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3036 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3037 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1);
3038 }
3039
3040
3041 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3042 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3043 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3044 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3045 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1);
3046 }
3047
3048
3049 // This code replaces a call to arraycopy; no exception may
3050 // be thrown in this code, they must be thrown in the System.arraycopy
3051 // activation frame; we could save some checks if this would not be the case
3052 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3053 ciArrayKlass* default_type = op->expected_type();
3054 Register src = op->src()->as_register();
3055 Register dst = op->dst()->as_register();
3056 Register src_pos = op->src_pos()->as_register();
3057 Register dst_pos = op->dst_pos()->as_register();
3058 Register length = op->length()->as_register();
3059 Register tmp = op->tmp()->as_register();
3060 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3061
3062 CodeStub* stub = op->stub();
3063 int flags = op->flags();
3064 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
3065 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3066
3067 // if we don't know anything, just go through the generic arraycopy
3068 if (default_type == nullptr) {
3069 // save outgoing arguments on stack in case call to System.arraycopy is needed
3070 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3071 // for interpreter calling conventions. Now we have to do it in new style conventions.
3072 // For the moment until C1 gets the new register allocator I just force all the
3073 // args to the right place (except the register args) and then on the back side
3074 // reload the register args properly if we go slow path. Yuck
3075
3076 // These are proper for the calling convention
3077 store_parameter(length, 2);
3078 store_parameter(dst_pos, 1);
3079 store_parameter(dst, 0);
3080
3081 // these are just temporary placements until we need to reload
3082 store_parameter(src_pos, 3);
3083 store_parameter(src, 4);
3084 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3085
3086 address copyfunc_addr = StubRoutines::generic_arraycopy();
3087 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
3088
3089 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3090 #ifdef _LP64
3091 // The arguments are in java calling convention so we can trivially shift them to C
3092 // convention
3093 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3094 __ mov(c_rarg0, j_rarg0);
3095 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3096 __ mov(c_rarg1, j_rarg1);
3097 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3098 __ mov(c_rarg2, j_rarg2);
3099 assert_different_registers(c_rarg3, j_rarg4);
3100 __ mov(c_rarg3, j_rarg3);
3101 #ifdef _WIN64
3102 // Allocate abi space for args but be sure to keep stack aligned
3103 __ subptr(rsp, 6*wordSize);
3104 store_parameter(j_rarg4, 4);
3105 #ifndef PRODUCT
3106 if (PrintC1Statistics) {
3107 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3108 }
3109 #endif
3110 __ call(RuntimeAddress(copyfunc_addr));
3111 __ addptr(rsp, 6*wordSize);
3112 #else
3113 __ mov(c_rarg4, j_rarg4);
3114 #ifndef PRODUCT
3115 if (PrintC1Statistics) {
3116 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3117 }
3118 #endif
3119 __ call(RuntimeAddress(copyfunc_addr));
3120 #endif // _WIN64
3121 #else
3122 __ push(length);
3123 __ push(dst_pos);
3124 __ push(dst);
3125 __ push(src_pos);
3126 __ push(src);
3127
3128 #ifndef PRODUCT
3129 if (PrintC1Statistics) {
3130 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3131 }
3132 #endif
3133 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3134
3135 #endif // _LP64
3136
3137 __ testl(rax, rax);
3138 __ jcc(Assembler::equal, *stub->continuation());
3139
3140 __ mov(tmp, rax);
3141 __ xorl(tmp, -1);
3142
3143 // Reload values from the stack so they are where the stub
3144 // expects them.
3145 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3146 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3147 __ movptr (length, Address(rsp, 2*BytesPerWord));
3148 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3149 __ movptr (src, Address(rsp, 4*BytesPerWord));
3150
3151 __ subl(length, tmp);
3152 __ addl(src_pos, tmp);
3153 __ addl(dst_pos, tmp);
3154 __ jmp(*stub->entry());
3155
3156 __ bind(*stub->continuation());
3157 return;
3158 }
3159
3160 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3161
3162 int elem_size = type2aelembytes(basic_type);
3163 Address::ScaleFactor scale;
3164
3165 switch (elem_size) {
3166 case 1 :
3167 scale = Address::times_1;
3168 break;
3169 case 2 :
3170 scale = Address::times_2;
3171 break;
3172 case 4 :
3173 scale = Address::times_4;
3174 break;
3175 case 8 :
3176 scale = Address::times_8;
3177 break;
3178 default:
3179 scale = Address::no_scale;
3180 ShouldNotReachHere();
3181 }
3182
3183 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3184 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3185 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3186 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3187
3188 // length and pos's are all sign extended at this point on 64bit
3189
3190 // test for null
3191 if (flags & LIR_OpArrayCopy::src_null_check) {
3192 __ testptr(src, src);
3193 __ jcc(Assembler::zero, *stub->entry());
3194 }
3195 if (flags & LIR_OpArrayCopy::dst_null_check) {
3196 __ testptr(dst, dst);
3197 __ jcc(Assembler::zero, *stub->entry());
3198 }
3199
3200 // If the compiler was not able to prove that exact type of the source or the destination
3201 // of the arraycopy is an array type, check at runtime if the source or the destination is
3202 // an instance type.
3203 if (flags & LIR_OpArrayCopy::type_check) {
3204 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3205 __ load_klass(tmp, dst, tmp_load_klass);
3206 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3207 __ jcc(Assembler::greaterEqual, *stub->entry());
3208 }
3209
3210 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3211 __ load_klass(tmp, src, tmp_load_klass);
3212 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3213 __ jcc(Assembler::greaterEqual, *stub->entry());
3214 }
3215 }
3216
3217 // check if negative
3218 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3219 __ testl(src_pos, src_pos);
3220 __ jcc(Assembler::less, *stub->entry());
3221 }
3222 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3223 __ testl(dst_pos, dst_pos);
3224 __ jcc(Assembler::less, *stub->entry());
3225 }
3226
3227 if (flags & LIR_OpArrayCopy::src_range_check) {
3228 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3229 __ cmpl(tmp, src_length_addr);
3230 __ jcc(Assembler::above, *stub->entry());
3231 }
3232 if (flags & LIR_OpArrayCopy::dst_range_check) {
3233 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3234 __ cmpl(tmp, dst_length_addr);
3235 __ jcc(Assembler::above, *stub->entry());
3236 }
3237
3238 if (flags & LIR_OpArrayCopy::length_positive_check) {
3239 __ testl(length, length);
3240 __ jcc(Assembler::less, *stub->entry());
3241 }
3242
3243 #ifdef _LP64
3244 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3245 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3246 #endif
3247
3248 if (flags & LIR_OpArrayCopy::type_check) {
3249 // We don't know the array types are compatible
3250 if (basic_type != T_OBJECT) {
3251 // Simple test for basic type arrays
3252 if (UseCompressedClassPointers) {
3253 __ movl(tmp, src_klass_addr);
3254 __ cmpl(tmp, dst_klass_addr);
3255 } else {
3256 __ movptr(tmp, src_klass_addr);
3257 __ cmpptr(tmp, dst_klass_addr);
3258 }
3259 __ jcc(Assembler::notEqual, *stub->entry());
3260 } else {
3261 // For object arrays, if src is a sub class of dst then we can
3262 // safely do the copy.
3263 Label cont, slow;
3264
3265 __ push(src);
3266 __ push(dst);
3267
3268 __ load_klass(src, src, tmp_load_klass);
3269 __ load_klass(dst, dst, tmp_load_klass);
3270
3271 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
3272
3273 __ push(src);
3274 __ push(dst);
3275 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3276 __ pop(dst);
3277 __ pop(src);
3278
3279 __ testl(src, src);
3280 __ jcc(Assembler::notEqual, cont);
3281
3282 __ bind(slow);
3283 __ pop(dst);
3284 __ pop(src);
3285
3286 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3287 if (copyfunc_addr != nullptr) { // use stub if available
3288 // src is not a sub class of dst so we have to do a
3289 // per-element check.
3290
3291 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3292 if ((flags & mask) != mask) {
3293 // Check that at least both of them object arrays.
3294 assert(flags & mask, "one of the two should be known to be an object array");
3295
3296 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3297 __ load_klass(tmp, src, tmp_load_klass);
3298 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3299 __ load_klass(tmp, dst, tmp_load_klass);
3300 }
3301 int lh_offset = in_bytes(Klass::layout_helper_offset());
3302 Address klass_lh_addr(tmp, lh_offset);
3303 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3304 __ cmpl(klass_lh_addr, objArray_lh);
3305 __ jcc(Assembler::notEqual, *stub->entry());
3306 }
3307
3308 // Spill because stubs can use any register they like and it's
3309 // easier to restore just those that we care about.
3310 store_parameter(dst, 0);
3311 store_parameter(dst_pos, 1);
3312 store_parameter(length, 2);
3313 store_parameter(src_pos, 3);
3314 store_parameter(src, 4);
3315
3316 #ifndef _LP64
3317 __ movptr(tmp, dst_klass_addr);
3318 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3319 __ push(tmp);
3320 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3321 __ push(tmp);
3322 __ push(length);
3323 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3324 __ push(tmp);
3325 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3326 __ push(tmp);
3327
3328 __ call_VM_leaf(copyfunc_addr, 5);
3329 #else
3330 __ movl2ptr(length, length); //higher 32bits must be null
3331
3332 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3333 assert_different_registers(c_rarg0, dst, dst_pos, length);
3334 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3335 assert_different_registers(c_rarg1, dst, length);
3336
3337 __ mov(c_rarg2, length);
3338 assert_different_registers(c_rarg2, dst);
3339
3340 #ifdef _WIN64
3341 // Allocate abi space for args but be sure to keep stack aligned
3342 __ subptr(rsp, 6*wordSize);
3343 __ load_klass(c_rarg3, dst, tmp_load_klass);
3344 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3345 store_parameter(c_rarg3, 4);
3346 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3347 __ call(RuntimeAddress(copyfunc_addr));
3348 __ addptr(rsp, 6*wordSize);
3349 #else
3350 __ load_klass(c_rarg4, dst, tmp_load_klass);
3351 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3352 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3353 __ call(RuntimeAddress(copyfunc_addr));
3354 #endif
3355
3356 #endif
3357
3358 #ifndef PRODUCT
3359 if (PrintC1Statistics) {
3360 Label failed;
3361 __ testl(rax, rax);
3362 __ jcc(Assembler::notZero, failed);
3363 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1);
3364 __ bind(failed);
3365 }
3366 #endif
3367
3368 __ testl(rax, rax);
3369 __ jcc(Assembler::zero, *stub->continuation());
3370
3371 #ifndef PRODUCT
3372 if (PrintC1Statistics) {
3373 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1);
3374 }
3375 #endif
3376
3377 __ mov(tmp, rax);
3378
3379 __ xorl(tmp, -1);
3380
3381 // Restore previously spilled arguments
3382 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3383 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3384 __ movptr (length, Address(rsp, 2*BytesPerWord));
3385 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3386 __ movptr (src, Address(rsp, 4*BytesPerWord));
3387
3388
3389 __ subl(length, tmp);
3390 __ addl(src_pos, tmp);
3391 __ addl(dst_pos, tmp);
3392 }
3393
3394 __ jmp(*stub->entry());
3395
3396 __ bind(cont);
3397 __ pop(dst);
3398 __ pop(src);
3399 }
3400 }
3401
3402 #ifdef ASSERT
3403 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3404 // Sanity check the known type with the incoming class. For the
3405 // primitive case the types must match exactly with src.klass and
3406 // dst.klass each exactly matching the default type. For the
3407 // object array case, if no type check is needed then either the
3408 // dst type is exactly the expected type and the src type is a
3409 // subtype which we can't check or src is the same array as dst
3410 // but not necessarily exactly of type default_type.
3411 Label known_ok, halt;
3412 __ mov_metadata(tmp, default_type->constant_encoding());
3413 #ifdef _LP64
3414 if (UseCompressedClassPointers) {
3415 __ encode_klass_not_null(tmp, rscratch1);
3416 }
3417 #endif
3418
3419 if (basic_type != T_OBJECT) {
3420
3421 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3422 else __ cmpptr(tmp, dst_klass_addr);
3423 __ jcc(Assembler::notEqual, halt);
3424 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3425 else __ cmpptr(tmp, src_klass_addr);
3426 __ jcc(Assembler::equal, known_ok);
3427 } else {
3428 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3429 else __ cmpptr(tmp, dst_klass_addr);
3430 __ jcc(Assembler::equal, known_ok);
3431 __ cmpptr(src, dst);
3432 __ jcc(Assembler::equal, known_ok);
3433 }
3434 __ bind(halt);
3435 __ stop("incorrect type information in arraycopy");
3436 __ bind(known_ok);
3437 }
3438 #endif
3439
3440 #ifndef PRODUCT
3441 if (PrintC1Statistics) {
3442 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1);
3443 }
3444 #endif
3445
3446 #ifdef _LP64
3447 assert_different_registers(c_rarg0, dst, dst_pos, length);
3448 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3449 assert_different_registers(c_rarg1, length);
3450 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3451 __ mov(c_rarg2, length);
3452
3453 #else
3454 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3455 store_parameter(tmp, 0);
3456 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3457 store_parameter(tmp, 1);
3458 store_parameter(length, 2);
3459 #endif // _LP64
3460
3461 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3462 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3463 const char *name;
3464 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3465 __ call_VM_leaf(entry, 0);
3466
3467 if (stub != nullptr) {
3468 __ bind(*stub->continuation());
3469 }
3470 }
3471
3472 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3473 assert(op->crc()->is_single_cpu(), "crc must be register");
3474 assert(op->val()->is_single_cpu(), "byte value must be register");
3475 assert(op->result_opr()->is_single_cpu(), "result must be register");
3476 Register crc = op->crc()->as_register();
3477 Register val = op->val()->as_register();
3478 Register res = op->result_opr()->as_register();
3479
3480 assert_different_registers(val, crc, res);
3481
3482 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3483 __ notl(crc); // ~crc
3484 __ update_byte_crc32(crc, val, res);
3485 __ notl(crc); // ~crc
3486 __ mov(res, crc);
3487 }
3488
3489 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3490 Register obj = op->obj_opr()->as_register(); // may not be an oop
3491 Register hdr = op->hdr_opr()->as_register();
3492 Register lock = op->lock_opr()->as_register();
3493 if (LockingMode == LM_MONITOR) {
3494 if (op->info() != nullptr) {
3495 add_debug_info_for_null_check_here(op->info());
3496 __ null_check(obj);
3497 }
3498 __ jmp(*op->stub()->entry());
3499 } else if (op->code() == lir_lock) {
3500 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3501 Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg;
3502 // add debug info for NullPointerException only if one is possible
3503 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
3504 if (op->info() != nullptr) {
3505 add_debug_info_for_null_check(null_check_offset, op->info());
3506 }
3507 // done
3508 } else if (op->code() == lir_unlock) {
3509 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3510 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3511 } else {
3512 Unimplemented();
3513 }
3514 __ bind(*op->stub()->continuation());
3515 }
3516
3517 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
3518 Register obj = op->obj()->as_pointer_register();
3519 Register result = op->result_opr()->as_pointer_register();
3520
3521 CodeEmitInfo* info = op->info();
3522 if (info != nullptr) {
3523 add_debug_info_for_null_check_here(info);
3524 }
3525
3526 #ifdef _LP64
3527 if (UseCompressedClassPointers) {
3528 __ movl(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3529 __ decode_klass_not_null(result, rscratch1);
3530 } else
3531 #endif
3532 __ movptr(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3533 }
3534
3535 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3536 ciMethod* method = op->profiled_method();
3537 int bci = op->profiled_bci();
3538 ciMethod* callee = op->profiled_callee();
3539 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3540
3541 // Update counter for all call types
3542 ciMethodData* md = method->method_data_or_null();
3543 assert(md != nullptr, "Sanity");
3544 ciProfileData* data = md->bci_to_data(bci);
3545 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
3546 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3547 Register mdo = op->mdo()->as_register();
3548 __ mov_metadata(mdo, md->constant_encoding());
3549 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3550 // Perform additional virtual call profiling for invokevirtual and
3551 // invokeinterface bytecodes
3552 if (op->should_profile_receiver_type()) {
3553 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3554 Register recv = op->recv()->as_register();
3555 assert_different_registers(mdo, recv);
3556 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3557 ciKlass* known_klass = op->known_holder();
3558 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
3559 // We know the type that will be seen at this call site; we can
3560 // statically update the MethodData* rather than needing to do
3561 // dynamic tests on the receiver type
3562
3563 // NOTE: we should probably put a lock around this search to
3564 // avoid collisions by concurrent compilations
3565 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3566 uint i;
3567 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3568 ciKlass* receiver = vc_data->receiver(i);
3569 if (known_klass->equals(receiver)) {
3570 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3571 __ addptr(data_addr, DataLayout::counter_increment);
3572 return;
3573 }
3574 }
3575
3576 // Receiver type not found in profile data; select an empty slot
3577
3578 // Note that this is less efficient than it should be because it
3579 // always does a write to the receiver part of the
3580 // VirtualCallData rather than just the first time
3581 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3582 ciKlass* receiver = vc_data->receiver(i);
3583 if (receiver == nullptr) {
3584 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3585 __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1);
3586 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3587 __ addptr(data_addr, DataLayout::counter_increment);
3588 return;
3589 }
3590 }
3591 } else {
3592 __ load_klass(recv, recv, tmp_load_klass);
3593 Label update_done;
3594 type_profile_helper(mdo, md, data, recv, &update_done);
3595 // Receiver did not match any saved receiver and there is no empty row for it.
3596 // Increment total counter to indicate polymorphic case.
3597 __ addptr(counter_addr, DataLayout::counter_increment);
3598
3599 __ bind(update_done);
3600 }
3601 } else {
3602 // Static call
3603 __ addptr(counter_addr, DataLayout::counter_increment);
3604 }
3605 }
3606
3607 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3608 Register obj = op->obj()->as_register();
3609 Register tmp = op->tmp()->as_pointer_register();
3610 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3611 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3612 ciKlass* exact_klass = op->exact_klass();
3613 intptr_t current_klass = op->current_klass();
3614 bool not_null = op->not_null();
3615 bool no_conflict = op->no_conflict();
3616
3617 Label update, next, none;
3618
3619 bool do_null = !not_null;
3620 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3621 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3622
3623 assert(do_null || do_update, "why are we here?");
3624 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3625
3626 __ verify_oop(obj);
3627
3628 #ifdef ASSERT
3629 if (obj == tmp) {
3630 #ifdef _LP64
3631 assert_different_registers(obj, rscratch1, mdo_addr.base(), mdo_addr.index());
3632 #else
3633 assert_different_registers(obj, mdo_addr.base(), mdo_addr.index());
3634 #endif
3635 } else {
3636 #ifdef _LP64
3637 assert_different_registers(obj, tmp, rscratch1, mdo_addr.base(), mdo_addr.index());
3638 #else
3639 assert_different_registers(obj, tmp, mdo_addr.base(), mdo_addr.index());
3640 #endif
3641 }
3642 #endif
3643 if (do_null) {
3644 __ testptr(obj, obj);
3645 __ jccb(Assembler::notZero, update);
3646 if (!TypeEntries::was_null_seen(current_klass)) {
3647 __ testptr(mdo_addr, TypeEntries::null_seen);
3648 #ifndef ASSERT
3649 __ jccb(Assembler::notZero, next); // already set
3650 #else
3651 __ jcc(Assembler::notZero, next); // already set
3652 #endif
3653 // atomic update to prevent overwriting Klass* with 0
3654 __ lock();
3655 __ orptr(mdo_addr, TypeEntries::null_seen);
3656 }
3657 if (do_update) {
3658 #ifndef ASSERT
3659 __ jmpb(next);
3660 }
3661 #else
3662 __ jmp(next);
3663 }
3664 } else {
3665 __ testptr(obj, obj);
3666 __ jcc(Assembler::notZero, update);
3667 __ stop("unexpected null obj");
3668 #endif
3669 }
3670
3671 __ bind(update);
3672
3673 if (do_update) {
3674 #ifdef ASSERT
3675 if (exact_klass != nullptr) {
3676 Label ok;
3677 __ load_klass(tmp, obj, tmp_load_klass);
3678 __ push(tmp);
3679 __ mov_metadata(tmp, exact_klass->constant_encoding());
3680 __ cmpptr(tmp, Address(rsp, 0));
3681 __ jcc(Assembler::equal, ok);
3682 __ stop("exact klass and actual klass differ");
3683 __ bind(ok);
3684 __ pop(tmp);
3685 }
3686 #endif
3687 if (!no_conflict) {
3688 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3689 if (exact_klass != nullptr) {
3690 __ mov_metadata(tmp, exact_klass->constant_encoding());
3691 } else {
3692 __ load_klass(tmp, obj, tmp_load_klass);
3693 }
3694 #ifdef _LP64
3695 __ mov(rscratch1, tmp); // save original value before XOR
3696 #endif
3697 __ xorptr(tmp, mdo_addr);
3698 __ testptr(tmp, TypeEntries::type_klass_mask);
3699 // klass seen before, nothing to do. The unknown bit may have been
3700 // set already but no need to check.
3701 __ jccb(Assembler::zero, next);
3702
3703 __ testptr(tmp, TypeEntries::type_unknown);
3704 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3705
3706 if (TypeEntries::is_type_none(current_klass)) {
3707 __ testptr(mdo_addr, TypeEntries::type_mask);
3708 __ jccb(Assembler::zero, none);
3709 #ifdef _LP64
3710 // There is a chance that the checks above (re-reading profiling
3711 // data from memory) fail if another thread has just set the
3712 // profiling to this obj's klass
3713 __ mov(tmp, rscratch1); // get back original value before XOR
3714 __ xorptr(tmp, mdo_addr);
3715 __ testptr(tmp, TypeEntries::type_klass_mask);
3716 __ jccb(Assembler::zero, next);
3717 #endif
3718 }
3719 } else {
3720 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3721 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3722
3723 __ testptr(mdo_addr, TypeEntries::type_unknown);
3724 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3725 }
3726
3727 // different than before. Cannot keep accurate profile.
3728 __ orptr(mdo_addr, TypeEntries::type_unknown);
3729
3730 if (TypeEntries::is_type_none(current_klass)) {
3731 __ jmpb(next);
3732
3733 __ bind(none);
3734 // first time here. Set profile type.
3735 __ movptr(mdo_addr, tmp);
3736 #ifdef ASSERT
3737 __ andptr(tmp, TypeEntries::type_klass_mask);
3738 __ verify_klass_ptr(tmp);
3739 #endif
3740 }
3741 } else {
3742 // There's a single possible klass at this profile point
3743 assert(exact_klass != nullptr, "should be");
3744 if (TypeEntries::is_type_none(current_klass)) {
3745 __ mov_metadata(tmp, exact_klass->constant_encoding());
3746 __ xorptr(tmp, mdo_addr);
3747 __ testptr(tmp, TypeEntries::type_klass_mask);
3748 #ifdef ASSERT
3749 __ jcc(Assembler::zero, next);
3750
3751 {
3752 Label ok;
3753 __ push(tmp);
3754 __ testptr(mdo_addr, TypeEntries::type_mask);
3755 __ jcc(Assembler::zero, ok);
3756 // may have been set by another thread
3757 __ mov_metadata(tmp, exact_klass->constant_encoding());
3758 __ xorptr(tmp, mdo_addr);
3759 __ testptr(tmp, TypeEntries::type_mask);
3760 __ jcc(Assembler::zero, ok);
3761
3762 __ stop("unexpected profiling mismatch");
3763 __ bind(ok);
3764 __ pop(tmp);
3765 }
3766 #else
3767 __ jccb(Assembler::zero, next);
3768 #endif
3769 // first time here. Set profile type.
3770 __ movptr(mdo_addr, tmp);
3771 #ifdef ASSERT
3772 __ andptr(tmp, TypeEntries::type_klass_mask);
3773 __ verify_klass_ptr(tmp);
3774 #endif
3775 } else {
3776 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3777 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3778
3779 __ testptr(mdo_addr, TypeEntries::type_unknown);
3780 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3781
3782 __ orptr(mdo_addr, TypeEntries::type_unknown);
3783 }
3784 }
3785 }
3786 __ bind(next);
3787 }
3788
3789 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3790 Unimplemented();
3791 }
3792
3793
3794 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3795 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3796 }
3797
3798
3799 void LIR_Assembler::align_backward_branch_target() {
3800 __ align(BytesPerWord);
3801 }
3802
3803
3804 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3805 if (left->is_single_cpu()) {
3806 __ negl(left->as_register());
3807 move_regs(left->as_register(), dest->as_register());
3808
3809 } else if (left->is_double_cpu()) {
3810 Register lo = left->as_register_lo();
3811 #ifdef _LP64
3812 Register dst = dest->as_register_lo();
3813 __ movptr(dst, lo);
3814 __ negptr(dst);
3815 #else
3816 Register hi = left->as_register_hi();
3817 __ lneg(hi, lo);
3818 if (dest->as_register_lo() == hi) {
3819 assert(dest->as_register_hi() != lo, "destroying register");
3820 move_regs(hi, dest->as_register_hi());
3821 move_regs(lo, dest->as_register_lo());
3822 } else {
3823 move_regs(lo, dest->as_register_lo());
3824 move_regs(hi, dest->as_register_hi());
3825 }
3826 #endif // _LP64
3827
3828 } else if (dest->is_single_xmm()) {
3829 #ifdef _LP64
3830 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3831 assert(tmp->is_valid(), "need temporary");
3832 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
3833 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
3834 }
3835 else
3836 #endif
3837 {
3838 assert(!tmp->is_valid(), "do not need temporary");
3839 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3840 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3841 }
3842 __ xorps(dest->as_xmm_float_reg(),
3843 ExternalAddress(LIR_Assembler::float_signflip_pool),
3844 rscratch1);
3845 }
3846 } else if (dest->is_double_xmm()) {
3847 #ifdef _LP64
3848 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3849 assert(tmp->is_valid(), "need temporary");
3850 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
3851 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
3852 }
3853 else
3854 #endif
3855 {
3856 assert(!tmp->is_valid(), "do not need temporary");
3857 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3858 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3859 }
3860 __ xorpd(dest->as_xmm_double_reg(),
3861 ExternalAddress(LIR_Assembler::double_signflip_pool),
3862 rscratch1);
3863 }
3864 #ifndef _LP64
3865 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3866 assert(left->fpu() == 0, "arg must be on TOS");
3867 assert(dest->fpu() == 0, "dest must be TOS");
3868 __ fchs();
3869 #endif // !_LP64
3870
3871 } else {
3872 ShouldNotReachHere();
3873 }
3874 }
3875
3876
3877 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3878 assert(src->is_address(), "must be an address");
3879 assert(dest->is_register(), "must be a register");
3880
3881 PatchingStub* patch = nullptr;
3882 if (patch_code != lir_patch_none) {
3883 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3884 }
3885
3886 Register reg = dest->as_pointer_register();
3887 LIR_Address* addr = src->as_address_ptr();
3888 __ lea(reg, as_Address(addr));
3889
3890 if (patch != nullptr) {
3891 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3892 }
3893 }
3894
3895
3896
3897 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3898 assert(!tmp->is_valid(), "don't need temporary");
3899 __ call(RuntimeAddress(dest));
3900 if (info != nullptr) {
3901 add_call_info_here(info);
3902 }
3903 __ post_call_nop();
3904 }
3905
3906
3907 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3908 assert(type == T_LONG, "only for volatile long fields");
3909
3910 if (info != nullptr) {
3911 add_debug_info_for_null_check_here(info);
3912 }
3913
3914 if (src->is_double_xmm()) {
3915 if (dest->is_double_cpu()) {
3916 #ifdef _LP64
3917 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3918 #else
3919 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3920 __ psrlq(src->as_xmm_double_reg(), 32);
3921 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3922 #endif // _LP64
3923 } else if (dest->is_double_stack()) {
3924 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3925 } else if (dest->is_address()) {
3926 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3927 } else {
3928 ShouldNotReachHere();
3929 }
3930
3931 } else if (dest->is_double_xmm()) {
3932 if (src->is_double_stack()) {
3933 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3934 } else if (src->is_address()) {
3935 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3936 } else {
3937 ShouldNotReachHere();
3938 }
3939
3940 #ifndef _LP64
3941 } else if (src->is_double_fpu()) {
3942 assert(src->fpu_regnrLo() == 0, "must be TOS");
3943 if (dest->is_double_stack()) {
3944 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3945 } else if (dest->is_address()) {
3946 __ fistp_d(as_Address(dest->as_address_ptr()));
3947 } else {
3948 ShouldNotReachHere();
3949 }
3950
3951 } else if (dest->is_double_fpu()) {
3952 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3953 if (src->is_double_stack()) {
3954 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3955 } else if (src->is_address()) {
3956 __ fild_d(as_Address(src->as_address_ptr()));
3957 } else {
3958 ShouldNotReachHere();
3959 }
3960 #endif // !_LP64
3961
3962 } else {
3963 ShouldNotReachHere();
3964 }
3965 }
3966
3967 #ifdef ASSERT
3968 // emit run-time assertion
3969 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3970 assert(op->code() == lir_assert, "must be");
3971
3972 if (op->in_opr1()->is_valid()) {
3973 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3974 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3975 } else {
3976 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3977 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3978 }
3979
3980 Label ok;
3981 if (op->condition() != lir_cond_always) {
3982 Assembler::Condition acond = Assembler::zero;
3983 switch (op->condition()) {
3984 case lir_cond_equal: acond = Assembler::equal; break;
3985 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3986 case lir_cond_less: acond = Assembler::less; break;
3987 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3988 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3989 case lir_cond_greater: acond = Assembler::greater; break;
3990 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3991 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3992 default: ShouldNotReachHere();
3993 }
3994 __ jcc(acond, ok);
3995 }
3996 if (op->halt()) {
3997 const char* str = __ code_string(op->msg());
3998 __ stop(str);
3999 } else {
4000 breakpoint();
4001 }
4002 __ bind(ok);
4003 }
4004 #endif
4005
4006 void LIR_Assembler::membar() {
4007 // QQQ sparc TSO uses this,
4008 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
4009 }
4010
4011 void LIR_Assembler::membar_acquire() {
4012 // No x86 machines currently require load fences
4013 }
4014
4015 void LIR_Assembler::membar_release() {
4016 // No x86 machines currently require store fences
4017 }
4018
4019 void LIR_Assembler::membar_loadload() {
4020 // no-op
4021 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
4022 }
4023
4024 void LIR_Assembler::membar_storestore() {
4025 // no-op
4026 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4027 }
4028
4029 void LIR_Assembler::membar_loadstore() {
4030 // no-op
4031 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4032 }
4033
4034 void LIR_Assembler::membar_storeload() {
4035 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4036 }
4037
4038 void LIR_Assembler::on_spin_wait() {
4039 __ pause ();
4040 }
4041
4042 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4043 assert(result_reg->is_register(), "check");
4044 #ifdef _LP64
4045 // __ get_thread(result_reg->as_register_lo());
4046 __ mov(result_reg->as_register(), r15_thread);
4047 #else
4048 __ get_thread(result_reg->as_register());
4049 #endif // _LP64
4050 }
4051
4052
4053 void LIR_Assembler::peephole(LIR_List*) {
4054 // do nothing for now
4055 }
4056
4057 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4058 assert(data == dest, "xchg/xadd uses only 2 operands");
4059
4060 if (data->type() == T_INT) {
4061 if (code == lir_xadd) {
4062 __ lock();
4063 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4064 } else {
4065 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4066 }
4067 } else if (data->is_oop()) {
4068 assert (code == lir_xchg, "xadd for oops");
4069 Register obj = data->as_register();
4070 #ifdef _LP64
4071 if (UseCompressedOops) {
4072 __ encode_heap_oop(obj);
4073 __ xchgl(obj, as_Address(src->as_address_ptr()));
4074 __ decode_heap_oop(obj);
4075 } else {
4076 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4077 }
4078 #else
4079 __ xchgl(obj, as_Address(src->as_address_ptr()));
4080 #endif
4081 } else if (data->type() == T_LONG) {
4082 #ifdef _LP64
4083 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4084 if (code == lir_xadd) {
4085 __ lock();
4086 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4087 } else {
4088 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4089 }
4090 #else
4091 ShouldNotReachHere();
4092 #endif
4093 } else {
4094 ShouldNotReachHere();
4095 }
4096 }
4097
4098 #undef __