1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/macroAssembler.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "c1/c1_CodeStubs.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "ci/ciUtilities.hpp"
36 #include "code/SCCache.hpp"
37 #include "compiler/oopMap.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/gc_globals.hpp"
40 #include "nativeInst_x86.hpp"
41 #include "oops/objArrayKlass.hpp"
42 #include "runtime/frame.inline.hpp"
43 #include "runtime/safepointMechanism.hpp"
44 #include "runtime/sharedRuntime.hpp"
45 #include "runtime/stubRoutines.hpp"
46 #include "utilities/powerOfTwo.hpp"
47 #include "vmreg_x86.inline.hpp"
48
49
50 // These masks are used to provide 128-bit aligned bitmasks to the XMM
51 // instructions, to allow sign-masking or sign-bit flipping. They allow
52 // fast versions of NegF/NegD and AbsF/AbsD.
53
54 // Note: 'double' and 'long long' have 32-bits alignment on x86.
55 static address double_quadword(jlong *adr, jlong lo, jlong hi) {
56 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
57 // of 128-bits operands for SSE instructions.
58 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
59 // Store the value to a 128-bits operand.
60 operand[0] = lo;
61 operand[1] = hi;
62 return (address)operand;
63 }
64
65 // Buffer for 128-bits masks used by SSE instructions.
66 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
67
68 // Static initialization during VM startup.
69 address LIR_Assembler::float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
70 address LIR_Assembler::double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
71 address LIR_Assembler::float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
72 address LIR_Assembler::double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
73
74
75 NEEDS_CLEANUP // remove this definitions ?
76 const Register SYNC_header = rax; // synchronization header
77 const Register SHIFT_count = rcx; // where count for shift operations must be
78
79 #define __ _masm->
80
81
82 static void select_different_registers(Register preserve,
83 Register extra,
84 Register &tmp1,
85 Register &tmp2) {
86 if (tmp1 == preserve) {
87 assert_different_registers(tmp1, tmp2, extra);
88 tmp1 = extra;
89 } else if (tmp2 == preserve) {
90 assert_different_registers(tmp1, tmp2, extra);
91 tmp2 = extra;
92 }
93 assert_different_registers(preserve, tmp1, tmp2);
94 }
95
96
97
98 static void select_different_registers(Register preserve,
99 Register extra,
100 Register &tmp1,
101 Register &tmp2,
102 Register &tmp3) {
103 if (tmp1 == preserve) {
104 assert_different_registers(tmp1, tmp2, tmp3, extra);
105 tmp1 = extra;
106 } else if (tmp2 == preserve) {
107 assert_different_registers(tmp1, tmp2, tmp3, extra);
108 tmp2 = extra;
109 } else if (tmp3 == preserve) {
110 assert_different_registers(tmp1, tmp2, tmp3, extra);
111 tmp3 = extra;
112 }
113 assert_different_registers(preserve, tmp1, tmp2, tmp3);
114 }
115
116
117
118 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
119 if (opr->is_constant()) {
120 LIR_Const* constant = opr->as_constant_ptr();
121 switch (constant->type()) {
122 case T_INT: {
123 return true;
124 }
125
126 default:
127 return false;
128 }
129 }
130 return false;
131 }
132
133
134 LIR_Opr LIR_Assembler::receiverOpr() {
135 return FrameMap::receiver_opr;
136 }
137
138 LIR_Opr LIR_Assembler::osrBufferPointer() {
139 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
140 }
141
142 //--------------fpu register translations-----------------------
143
144
145 address LIR_Assembler::float_constant(float f) {
146 address const_addr = __ float_constant(f);
147 if (const_addr == nullptr) {
148 bailout("const section overflow");
149 return __ code()->consts()->start();
150 } else {
151 return const_addr;
152 }
153 }
154
155
156 address LIR_Assembler::double_constant(double d) {
157 address const_addr = __ double_constant(d);
158 if (const_addr == nullptr) {
159 bailout("const section overflow");
160 return __ code()->consts()->start();
161 } else {
162 return const_addr;
163 }
164 }
165
166 #ifndef _LP64
167 void LIR_Assembler::fpop() {
168 __ fpop();
169 }
170
171 void LIR_Assembler::fxch(int i) {
172 __ fxch(i);
173 }
174
175 void LIR_Assembler::fld(int i) {
176 __ fld_s(i);
177 }
178
179 void LIR_Assembler::ffree(int i) {
180 __ ffree(i);
181 }
182 #endif // !_LP64
183
184 void LIR_Assembler::breakpoint() {
185 __ int3();
186 }
187
188 void LIR_Assembler::push(LIR_Opr opr) {
189 if (opr->is_single_cpu()) {
190 __ push_reg(opr->as_register());
191 } else if (opr->is_double_cpu()) {
192 NOT_LP64(__ push_reg(opr->as_register_hi()));
193 __ push_reg(opr->as_register_lo());
194 } else if (opr->is_stack()) {
195 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
196 } else if (opr->is_constant()) {
197 LIR_Const* const_opr = opr->as_constant_ptr();
198 if (const_opr->type() == T_OBJECT) {
199 __ push_oop(const_opr->as_jobject(), rscratch1);
200 } else if (const_opr->type() == T_INT) {
201 __ push_jint(const_opr->as_jint());
202 } else {
203 ShouldNotReachHere();
204 }
205
206 } else {
207 ShouldNotReachHere();
208 }
209 }
210
211 void LIR_Assembler::pop(LIR_Opr opr) {
212 if (opr->is_single_cpu()) {
213 __ pop_reg(opr->as_register());
214 } else {
215 ShouldNotReachHere();
216 }
217 }
218
219 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
220 return addr->base()->is_illegal() && addr->index()->is_illegal();
221 }
222
223 //-------------------------------------------
224
225 Address LIR_Assembler::as_Address(LIR_Address* addr) {
226 return as_Address(addr, rscratch1);
227 }
228
229 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
230 if (addr->base()->is_illegal()) {
231 assert(addr->index()->is_illegal(), "must be illegal too");
232 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
233 if (! __ reachable(laddr)) {
234 __ movptr(tmp, laddr.addr());
235 Address res(tmp, 0);
236 return res;
237 } else {
238 return __ as_Address(laddr);
239 }
240 }
241
242 Register base = addr->base()->as_pointer_register();
243
244 if (addr->index()->is_illegal()) {
245 return Address( base, addr->disp());
246 } else if (addr->index()->is_cpu_register()) {
247 Register index = addr->index()->as_pointer_register();
248 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
249 } else if (addr->index()->is_constant()) {
250 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
251 assert(Assembler::is_simm32(addr_offset), "must be");
252
253 return Address(base, addr_offset);
254 } else {
255 Unimplemented();
256 return Address();
257 }
258 }
259
260
261 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
262 Address base = as_Address(addr);
263 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
264 }
265
266
267 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
268 return as_Address(addr);
269 }
270
271
272 void LIR_Assembler::osr_entry() {
273 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
274 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
275 ValueStack* entry_state = osr_entry->state();
276 int number_of_locks = entry_state->locks_size();
277
278 // we jump here if osr happens with the interpreter
279 // state set up to continue at the beginning of the
280 // loop that triggered osr - in particular, we have
281 // the following registers setup:
282 //
283 // rcx: osr buffer
284 //
285
286 // build frame
287 ciMethod* m = compilation()->method();
288 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
289
290 // OSR buffer is
291 //
292 // locals[nlocals-1..0]
293 // monitors[0..number_of_locks]
294 //
295 // locals is a direct copy of the interpreter frame so in the osr buffer
296 // so first slot in the local array is the last local from the interpreter
297 // and last slot is local[0] (receiver) from the interpreter
298 //
299 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
300 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
301 // in the interpreter frame (the method lock if a sync method)
302
303 // Initialize monitors in the compiled activation.
304 // rcx: pointer to osr buffer
305 //
306 // All other registers are dead at this point and the locals will be
307 // copied into place by code emitted in the IR.
308
309 Register OSR_buf = osrBufferPointer()->as_pointer_register();
310 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
311 int monitor_offset = BytesPerWord * method()->max_locals() +
312 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
313 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
314 // the OSR buffer using 2 word entries: first the lock and then
315 // the oop.
316 for (int i = 0; i < number_of_locks; i++) {
317 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
318 #ifdef ASSERT
319 // verify the interpreter's monitor has a non-null object
320 {
321 Label L;
322 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD);
323 __ jcc(Assembler::notZero, L);
324 __ stop("locked object is null");
325 __ bind(L);
326 }
327 #endif
328 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
329 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
330 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
331 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
332 }
333 }
334 }
335
336
337 // inline cache check; done before the frame is built.
338 int LIR_Assembler::check_icache() {
339 return __ ic_check(CodeEntryAlignment);
340 }
341
342 void LIR_Assembler::clinit_barrier(ciMethod* method) {
343 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
344 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
345
346 Label L_skip_barrier;
347 Register klass = rscratch1;
348 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
349 assert(thread != noreg, "x86_32 not implemented");
350
351 __ mov_metadata(klass, method->holder()->constant_encoding());
352 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
353
354 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
355
356 __ bind(L_skip_barrier);
357 }
358
359 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
360 jobject o = nullptr;
361 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
362 __ movoop(reg, o);
363 patching_epilog(patch, lir_patch_normal, reg, info);
364 }
365
366 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
367 Metadata* o = nullptr;
368 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
369 __ mov_metadata(reg, o);
370 patching_epilog(patch, lir_patch_normal, reg, info);
371 }
372
373 // This specifies the rsp decrement needed to build the frame
374 int LIR_Assembler::initial_frame_size_in_bytes() const {
375 // if rounding, must let FrameMap know!
376
377 // The frame_map records size in slots (32bit word)
378
379 // subtract two words to account for return address and link
380 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
381 }
382
383
384 int LIR_Assembler::emit_exception_handler() {
385 // generate code for exception handler
386 address handler_base = __ start_a_stub(exception_handler_size());
387 if (handler_base == nullptr) {
388 // not enough space left for the handler
389 bailout("exception handler overflow");
390 return -1;
391 }
392
393 int offset = code_offset();
394
395 // the exception oop and pc are in rax, and rdx
396 // no other registers need to be preserved, so invalidate them
397 __ invalidate_registers(false, true, true, false, true, true);
398
399 // check that there is really an exception
400 __ verify_not_null_oop(rax);
401
402 // search an exception handler (rax: exception oop, rdx: throwing pc)
403 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
404 __ should_not_reach_here();
405 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
406 __ end_a_stub();
407
408 return offset;
409 }
410
411
412 // Emit the code to remove the frame from the stack in the exception
413 // unwind path.
414 int LIR_Assembler::emit_unwind_handler() {
415 #ifndef PRODUCT
416 if (CommentedAssembly) {
417 _masm->block_comment("Unwind handler");
418 }
419 #endif
420
421 int offset = code_offset();
422
423 // Fetch the exception from TLS and clear out exception related thread state
424 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
425 NOT_LP64(__ get_thread(thread));
426 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
427 __ movptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
428 __ movptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
429
430 __ bind(_unwind_handler_entry);
431 __ verify_not_null_oop(rax);
432 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
433 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
434 }
435
436 // Perform needed unlocking
437 MonitorExitStub* stub = nullptr;
438 if (method()->is_synchronized()) {
439 monitor_address(0, FrameMap::rax_opr);
440 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
441 if (LockingMode == LM_MONITOR) {
442 __ jmp(*stub->entry());
443 } else {
444 __ unlock_object(rdi, rsi, rax, *stub->entry());
445 }
446 __ bind(*stub->continuation());
447 }
448
449 if (compilation()->env()->dtrace_method_probes()) {
450 #ifdef _LP64
451 __ mov(rdi, r15_thread);
452 __ mov_metadata(rsi, method()->constant_encoding());
453 #else
454 __ get_thread(rax);
455 __ movptr(Address(rsp, 0), rax);
456 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding(), noreg);
457 #endif
458 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
459 }
460
461 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
462 __ mov(rax, rbx); // Restore the exception
463 }
464
465 // remove the activation and dispatch to the unwind handler
466 __ remove_frame(initial_frame_size_in_bytes());
467 __ jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
468
469 // Emit the slow path assembly
470 if (stub != nullptr) {
471 stub->emit_code(this);
472 }
473
474 return offset;
475 }
476
477
478 int LIR_Assembler::emit_deopt_handler() {
479 // generate code for exception handler
480 address handler_base = __ start_a_stub(deopt_handler_size());
481 if (handler_base == nullptr) {
482 // not enough space left for the handler
483 bailout("deopt handler overflow");
484 return -1;
485 }
486
487 int offset = code_offset();
488 InternalAddress here(__ pc());
489
490 __ pushptr(here.addr(), rscratch1);
491 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
492 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
493 __ end_a_stub();
494
495 return offset;
496 }
497
498 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
499 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
500 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
501 assert(result->fpu() == 0, "result must already be on TOS");
502 }
503
504 // Pop the stack before the safepoint code
505 __ remove_frame(initial_frame_size_in_bytes());
506
507 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
508 __ reserved_stack_check();
509 }
510
511 // Note: we do not need to round double result; float result has the right precision
512 // the poll sets the condition code, but no data registers
513
514 #ifdef _LP64
515 const Register thread = r15_thread;
516 #else
517 const Register thread = rbx;
518 __ get_thread(thread);
519 #endif
520 code_stub->set_safepoint_offset(__ offset());
521 __ relocate(relocInfo::poll_return_type);
522 __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */);
523 __ ret(0);
524 }
525
526
527 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
528 guarantee(info != nullptr, "Shouldn't be null");
529 int offset = __ offset();
530 #ifdef _LP64
531 const Register poll_addr = rscratch1;
532 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
533 #else
534 assert(tmp->is_cpu_register(), "needed");
535 const Register poll_addr = tmp->as_register();
536 __ get_thread(poll_addr);
537 __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset())));
538 #endif
539 add_debug_info_for_branch(info);
540 __ relocate(relocInfo::poll_type);
541 address pre_pc = __ pc();
542 __ testl(rax, Address(poll_addr, 0));
543 address post_pc = __ pc();
544 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
545 return offset;
546 }
547
548
549 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
550 if (from_reg != to_reg) __ mov(to_reg, from_reg);
551 }
552
553 void LIR_Assembler::swap_reg(Register a, Register b) {
554 __ xchgptr(a, b);
555 }
556
557
558 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
559 assert(src->is_constant(), "should not call otherwise");
560 assert(dest->is_register(), "should not call otherwise");
561 LIR_Const* c = src->as_constant_ptr();
562
563 switch (c->type()) {
564 case T_INT: {
565 assert(patch_code == lir_patch_none, "no patching handled here");
566 __ movl(dest->as_register(), c->as_jint());
567 break;
568 }
569
570 case T_ADDRESS: {
571 assert(patch_code == lir_patch_none, "no patching handled here");
572 __ movptr(dest->as_register(), c->as_jint());
573 break;
574 }
575
576 case T_LONG: {
577 assert(patch_code == lir_patch_none, "no patching handled here");
578 #ifdef _LP64
579 if (SCCache::is_on_for_write()) {
580 // SCA needs relocation info for card table base
581 address b = c->as_pointer();
582 if (is_card_table_address(b)) {
583 __ lea(dest->as_register_lo(), ExternalAddress(b));
584 break;
585 }
586 if (AOTRuntimeConstants::contains(b)) {
587 __ load_aotrc_address(dest->as_register_lo(), b);
588 break;
589 }
590 }
591 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
592 #else
593 __ movptr(dest->as_register_lo(), c->as_jint_lo());
594 __ movptr(dest->as_register_hi(), c->as_jint_hi());
595 #endif // _LP64
596 break;
597 }
598
599 case T_OBJECT: {
600 if (patch_code != lir_patch_none) {
601 jobject2reg_with_patching(dest->as_register(), info);
602 } else {
603 __ movoop(dest->as_register(), c->as_jobject());
604 }
605 break;
606 }
607
608 case T_METADATA: {
609 if (patch_code != lir_patch_none) {
610 klass2reg_with_patching(dest->as_register(), info);
611 } else {
612 __ mov_metadata(dest->as_register(), c->as_metadata());
613 }
614 break;
615 }
616
617 case T_FLOAT: {
618 if (dest->is_single_xmm()) {
619 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
620 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
621 } else {
622 __ movflt(dest->as_xmm_float_reg(),
623 InternalAddress(float_constant(c->as_jfloat())));
624 }
625 } else {
626 #ifndef _LP64
627 assert(dest->is_single_fpu(), "must be");
628 assert(dest->fpu_regnr() == 0, "dest must be TOS");
629 if (c->is_zero_float()) {
630 __ fldz();
631 } else if (c->is_one_float()) {
632 __ fld1();
633 } else {
634 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
635 }
636 #else
637 ShouldNotReachHere();
638 #endif // !_LP64
639 }
640 break;
641 }
642
643 case T_DOUBLE: {
644 if (dest->is_double_xmm()) {
645 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
646 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
647 } else {
648 __ movdbl(dest->as_xmm_double_reg(),
649 InternalAddress(double_constant(c->as_jdouble())));
650 }
651 } else {
652 #ifndef _LP64
653 assert(dest->is_double_fpu(), "must be");
654 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
655 if (c->is_zero_double()) {
656 __ fldz();
657 } else if (c->is_one_double()) {
658 __ fld1();
659 } else {
660 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
661 }
662 #else
663 ShouldNotReachHere();
664 #endif // !_LP64
665 }
666 break;
667 }
668
669 default:
670 ShouldNotReachHere();
671 }
672 }
673
674 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
675 assert(src->is_constant(), "should not call otherwise");
676 assert(dest->is_stack(), "should not call otherwise");
677 LIR_Const* c = src->as_constant_ptr();
678
679 switch (c->type()) {
680 case T_INT: // fall through
681 case T_FLOAT:
682 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
683 break;
684
685 case T_ADDRESS:
686 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
687 break;
688
689 case T_OBJECT:
690 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1);
691 break;
692
693 case T_LONG: // fall through
694 case T_DOUBLE:
695 #ifdef _LP64
696 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
697 lo_word_offset_in_bytes),
698 (intptr_t)c->as_jlong_bits(),
699 rscratch1);
700 #else
701 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
702 lo_word_offset_in_bytes), c->as_jint_lo_bits());
703 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
704 hi_word_offset_in_bytes), c->as_jint_hi_bits());
705 #endif // _LP64
706 break;
707
708 default:
709 ShouldNotReachHere();
710 }
711 }
712
713 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
714 assert(src->is_constant(), "should not call otherwise");
715 assert(dest->is_address(), "should not call otherwise");
716 LIR_Const* c = src->as_constant_ptr();
717 LIR_Address* addr = dest->as_address_ptr();
718
719 int null_check_here = code_offset();
720 switch (type) {
721 case T_INT: // fall through
722 case T_FLOAT:
723 __ movl(as_Address(addr), c->as_jint_bits());
724 break;
725
726 case T_ADDRESS:
727 __ movptr(as_Address(addr), c->as_jint_bits());
728 break;
729
730 case T_OBJECT: // fall through
731 case T_ARRAY:
732 if (c->as_jobject() == nullptr) {
733 if (UseCompressedOops && !wide) {
734 __ movl(as_Address(addr), NULL_WORD);
735 } else {
736 #ifdef _LP64
737 __ xorptr(rscratch1, rscratch1);
738 null_check_here = code_offset();
739 __ movptr(as_Address(addr), rscratch1);
740 #else
741 __ movptr(as_Address(addr), NULL_WORD);
742 #endif
743 }
744 } else {
745 if (is_literal_address(addr)) {
746 ShouldNotReachHere();
747 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1);
748 } else {
749 #ifdef _LP64
750 __ movoop(rscratch1, c->as_jobject());
751 if (UseCompressedOops && !wide) {
752 __ encode_heap_oop(rscratch1);
753 null_check_here = code_offset();
754 __ movl(as_Address_lo(addr), rscratch1);
755 } else {
756 null_check_here = code_offset();
757 __ movptr(as_Address_lo(addr), rscratch1);
758 }
759 #else
760 __ movoop(as_Address(addr), c->as_jobject(), noreg);
761 #endif
762 }
763 }
764 break;
765
766 case T_LONG: // fall through
767 case T_DOUBLE:
768 #ifdef _LP64
769 if (is_literal_address(addr)) {
770 ShouldNotReachHere();
771 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
772 } else {
773 __ movptr(r10, (intptr_t)c->as_jlong_bits());
774 null_check_here = code_offset();
775 __ movptr(as_Address_lo(addr), r10);
776 }
777 #else
778 // Always reachable in 32bit so this doesn't produce useless move literal
779 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
780 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
781 #endif // _LP64
782 break;
783
784 case T_BOOLEAN: // fall through
785 case T_BYTE:
786 __ movb(as_Address(addr), c->as_jint() & 0xFF);
787 break;
788
789 case T_CHAR: // fall through
790 case T_SHORT:
791 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
792 break;
793
794 default:
795 ShouldNotReachHere();
796 };
797
798 if (info != nullptr) {
799 add_debug_info_for_null_check(null_check_here, info);
800 }
801 }
802
803
804 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
805 assert(src->is_register(), "should not call otherwise");
806 assert(dest->is_register(), "should not call otherwise");
807
808 // move between cpu-registers
809 if (dest->is_single_cpu()) {
810 #ifdef _LP64
811 if (src->type() == T_LONG) {
812 // Can do LONG -> OBJECT
813 move_regs(src->as_register_lo(), dest->as_register());
814 return;
815 }
816 #endif
817 assert(src->is_single_cpu(), "must match");
818 if (src->type() == T_OBJECT) {
819 __ verify_oop(src->as_register());
820 }
821 move_regs(src->as_register(), dest->as_register());
822
823 } else if (dest->is_double_cpu()) {
824 #ifdef _LP64
825 if (is_reference_type(src->type())) {
826 // Surprising to me but we can see move of a long to t_object
827 __ verify_oop(src->as_register());
828 move_regs(src->as_register(), dest->as_register_lo());
829 return;
830 }
831 #endif
832 assert(src->is_double_cpu(), "must match");
833 Register f_lo = src->as_register_lo();
834 Register f_hi = src->as_register_hi();
835 Register t_lo = dest->as_register_lo();
836 Register t_hi = dest->as_register_hi();
837 #ifdef _LP64
838 assert(f_hi == f_lo, "must be same");
839 assert(t_hi == t_lo, "must be same");
840 move_regs(f_lo, t_lo);
841 #else
842 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
843
844
845 if (f_lo == t_hi && f_hi == t_lo) {
846 swap_reg(f_lo, f_hi);
847 } else if (f_hi == t_lo) {
848 assert(f_lo != t_hi, "overwriting register");
849 move_regs(f_hi, t_hi);
850 move_regs(f_lo, t_lo);
851 } else {
852 assert(f_hi != t_lo, "overwriting register");
853 move_regs(f_lo, t_lo);
854 move_regs(f_hi, t_hi);
855 }
856 #endif // LP64
857
858 #ifndef _LP64
859 // special moves from fpu-register to xmm-register
860 // necessary for method results
861 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
862 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
863 __ fld_s(Address(rsp, 0));
864 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
865 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
866 __ fld_d(Address(rsp, 0));
867 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
868 __ fstp_s(Address(rsp, 0));
869 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
870 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
871 __ fstp_d(Address(rsp, 0));
872 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
873 #endif // !_LP64
874
875 // move between xmm-registers
876 } else if (dest->is_single_xmm()) {
877 assert(src->is_single_xmm(), "must match");
878 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
879 } else if (dest->is_double_xmm()) {
880 assert(src->is_double_xmm(), "must match");
881 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
882
883 #ifndef _LP64
884 // move between fpu-registers (no instruction necessary because of fpu-stack)
885 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
886 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
887 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
888 #endif // !_LP64
889
890 } else {
891 ShouldNotReachHere();
892 }
893 }
894
895 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
896 assert(src->is_register(), "should not call otherwise");
897 assert(dest->is_stack(), "should not call otherwise");
898
899 if (src->is_single_cpu()) {
900 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
901 if (is_reference_type(type)) {
902 __ verify_oop(src->as_register());
903 __ movptr (dst, src->as_register());
904 } else if (type == T_METADATA || type == T_ADDRESS) {
905 __ movptr (dst, src->as_register());
906 } else {
907 __ movl (dst, src->as_register());
908 }
909
910 } else if (src->is_double_cpu()) {
911 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
912 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
913 __ movptr (dstLO, src->as_register_lo());
914 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
915
916 } else if (src->is_single_xmm()) {
917 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
918 __ movflt(dst_addr, src->as_xmm_float_reg());
919
920 } else if (src->is_double_xmm()) {
921 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
922 __ movdbl(dst_addr, src->as_xmm_double_reg());
923
924 #ifndef _LP64
925 } else if (src->is_single_fpu()) {
926 assert(src->fpu_regnr() == 0, "argument must be on TOS");
927 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
928 if (pop_fpu_stack) __ fstp_s (dst_addr);
929 else __ fst_s (dst_addr);
930
931 } else if (src->is_double_fpu()) {
932 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
933 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
934 if (pop_fpu_stack) __ fstp_d (dst_addr);
935 else __ fst_d (dst_addr);
936 #endif // !_LP64
937
938 } else {
939 ShouldNotReachHere();
940 }
941 }
942
943
944 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
945 LIR_Address* to_addr = dest->as_address_ptr();
946 PatchingStub* patch = nullptr;
947 Register compressed_src = rscratch1;
948
949 if (is_reference_type(type)) {
950 __ verify_oop(src->as_register());
951 #ifdef _LP64
952 if (UseCompressedOops && !wide) {
953 __ movptr(compressed_src, src->as_register());
954 __ encode_heap_oop(compressed_src);
955 if (patch_code != lir_patch_none) {
956 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
957 }
958 }
959 #endif
960 }
961
962 if (patch_code != lir_patch_none) {
963 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
964 Address toa = as_Address(to_addr);
965 assert(toa.disp() != 0, "must have");
966 }
967
968 int null_check_here = code_offset();
969 switch (type) {
970 case T_FLOAT: {
971 #ifdef _LP64
972 assert(src->is_single_xmm(), "not a float");
973 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
974 #else
975 if (src->is_single_xmm()) {
976 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
977 } else {
978 assert(src->is_single_fpu(), "must be");
979 assert(src->fpu_regnr() == 0, "argument must be on TOS");
980 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
981 else __ fst_s (as_Address(to_addr));
982 }
983 #endif // _LP64
984 break;
985 }
986
987 case T_DOUBLE: {
988 #ifdef _LP64
989 assert(src->is_double_xmm(), "not a double");
990 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
991 #else
992 if (src->is_double_xmm()) {
993 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
994 } else {
995 assert(src->is_double_fpu(), "must be");
996 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
997 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
998 else __ fst_d (as_Address(to_addr));
999 }
1000 #endif // _LP64
1001 break;
1002 }
1003
1004 case T_ARRAY: // fall through
1005 case T_OBJECT: // fall through
1006 if (UseCompressedOops && !wide) {
1007 __ movl(as_Address(to_addr), compressed_src);
1008 } else {
1009 __ movptr(as_Address(to_addr), src->as_register());
1010 }
1011 break;
1012 case T_METADATA:
1013 // We get here to store a method pointer to the stack to pass to
1014 // a dtrace runtime call. This can't work on 64 bit with
1015 // compressed klass ptrs: T_METADATA can be a compressed klass
1016 // ptr or a 64 bit method pointer.
1017 LP64_ONLY(ShouldNotReachHere());
1018 __ movptr(as_Address(to_addr), src->as_register());
1019 break;
1020 case T_ADDRESS:
1021 __ movptr(as_Address(to_addr), src->as_register());
1022 break;
1023 case T_INT:
1024 __ movl(as_Address(to_addr), src->as_register());
1025 break;
1026
1027 case T_LONG: {
1028 Register from_lo = src->as_register_lo();
1029 Register from_hi = src->as_register_hi();
1030 #ifdef _LP64
1031 __ movptr(as_Address_lo(to_addr), from_lo);
1032 #else
1033 Register base = to_addr->base()->as_register();
1034 Register index = noreg;
1035 if (to_addr->index()->is_register()) {
1036 index = to_addr->index()->as_register();
1037 }
1038 if (base == from_lo || index == from_lo) {
1039 assert(base != from_hi, "can't be");
1040 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1041 __ movl(as_Address_hi(to_addr), from_hi);
1042 if (patch != nullptr) {
1043 patching_epilog(patch, lir_patch_high, base, info);
1044 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1045 patch_code = lir_patch_low;
1046 }
1047 __ movl(as_Address_lo(to_addr), from_lo);
1048 } else {
1049 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1050 __ movl(as_Address_lo(to_addr), from_lo);
1051 if (patch != nullptr) {
1052 patching_epilog(patch, lir_patch_low, base, info);
1053 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1054 patch_code = lir_patch_high;
1055 }
1056 __ movl(as_Address_hi(to_addr), from_hi);
1057 }
1058 #endif // _LP64
1059 break;
1060 }
1061
1062 case T_BYTE: // fall through
1063 case T_BOOLEAN: {
1064 Register src_reg = src->as_register();
1065 Address dst_addr = as_Address(to_addr);
1066 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1067 __ movb(dst_addr, src_reg);
1068 break;
1069 }
1070
1071 case T_CHAR: // fall through
1072 case T_SHORT:
1073 __ movw(as_Address(to_addr), src->as_register());
1074 break;
1075
1076 default:
1077 ShouldNotReachHere();
1078 }
1079 if (info != nullptr) {
1080 add_debug_info_for_null_check(null_check_here, info);
1081 }
1082
1083 if (patch_code != lir_patch_none) {
1084 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1085 }
1086 }
1087
1088
1089 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1090 assert(src->is_stack(), "should not call otherwise");
1091 assert(dest->is_register(), "should not call otherwise");
1092
1093 if (dest->is_single_cpu()) {
1094 if (is_reference_type(type)) {
1095 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1096 __ verify_oop(dest->as_register());
1097 } else if (type == T_METADATA || type == T_ADDRESS) {
1098 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1099 } else {
1100 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1101 }
1102
1103 } else if (dest->is_double_cpu()) {
1104 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1105 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1106 __ movptr(dest->as_register_lo(), src_addr_LO);
1107 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1108
1109 } else if (dest->is_single_xmm()) {
1110 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1111 __ movflt(dest->as_xmm_float_reg(), src_addr);
1112
1113 } else if (dest->is_double_xmm()) {
1114 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1115 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1116
1117 #ifndef _LP64
1118 } else if (dest->is_single_fpu()) {
1119 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1120 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1121 __ fld_s(src_addr);
1122
1123 } else if (dest->is_double_fpu()) {
1124 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1125 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1126 __ fld_d(src_addr);
1127 #endif // _LP64
1128
1129 } else {
1130 ShouldNotReachHere();
1131 }
1132 }
1133
1134
1135 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1136 if (src->is_single_stack()) {
1137 if (is_reference_type(type)) {
1138 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1139 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1140 } else {
1141 #ifndef _LP64
1142 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1143 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1144 #else
1145 //no pushl on 64bits
1146 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1147 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1148 #endif
1149 }
1150
1151 } else if (src->is_double_stack()) {
1152 #ifdef _LP64
1153 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1154 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1155 #else
1156 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1157 // push and pop the part at src + wordSize, adding wordSize for the previous push
1158 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1159 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1160 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1161 #endif // _LP64
1162
1163 } else {
1164 ShouldNotReachHere();
1165 }
1166 }
1167
1168
1169 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1170 assert(src->is_address(), "should not call otherwise");
1171 assert(dest->is_register(), "should not call otherwise");
1172
1173 LIR_Address* addr = src->as_address_ptr();
1174 Address from_addr = as_Address(addr);
1175
1176 if (addr->base()->type() == T_OBJECT) {
1177 __ verify_oop(addr->base()->as_pointer_register());
1178 }
1179
1180 switch (type) {
1181 case T_BOOLEAN: // fall through
1182 case T_BYTE: // fall through
1183 case T_CHAR: // fall through
1184 case T_SHORT:
1185 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1186 // on pre P6 processors we may get partial register stalls
1187 // so blow away the value of to_rinfo before loading a
1188 // partial word into it. Do it here so that it precedes
1189 // the potential patch point below.
1190 __ xorptr(dest->as_register(), dest->as_register());
1191 }
1192 break;
1193 default:
1194 break;
1195 }
1196
1197 PatchingStub* patch = nullptr;
1198 if (patch_code != lir_patch_none) {
1199 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1200 assert(from_addr.disp() != 0, "must have");
1201 }
1202 if (info != nullptr) {
1203 add_debug_info_for_null_check_here(info);
1204 }
1205
1206 switch (type) {
1207 case T_FLOAT: {
1208 if (dest->is_single_xmm()) {
1209 __ movflt(dest->as_xmm_float_reg(), from_addr);
1210 } else {
1211 #ifndef _LP64
1212 assert(dest->is_single_fpu(), "must be");
1213 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1214 __ fld_s(from_addr);
1215 #else
1216 ShouldNotReachHere();
1217 #endif // !LP64
1218 }
1219 break;
1220 }
1221
1222 case T_DOUBLE: {
1223 if (dest->is_double_xmm()) {
1224 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1225 } else {
1226 #ifndef _LP64
1227 assert(dest->is_double_fpu(), "must be");
1228 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1229 __ fld_d(from_addr);
1230 #else
1231 ShouldNotReachHere();
1232 #endif // !LP64
1233 }
1234 break;
1235 }
1236
1237 case T_OBJECT: // fall through
1238 case T_ARRAY: // fall through
1239 if (UseCompressedOops && !wide) {
1240 __ movl(dest->as_register(), from_addr);
1241 } else {
1242 __ movptr(dest->as_register(), from_addr);
1243 }
1244 break;
1245
1246 case T_ADDRESS:
1247 __ movptr(dest->as_register(), from_addr);
1248 break;
1249 case T_INT:
1250 __ movl(dest->as_register(), from_addr);
1251 break;
1252
1253 case T_LONG: {
1254 Register to_lo = dest->as_register_lo();
1255 Register to_hi = dest->as_register_hi();
1256 #ifdef _LP64
1257 __ movptr(to_lo, as_Address_lo(addr));
1258 #else
1259 Register base = addr->base()->as_register();
1260 Register index = noreg;
1261 if (addr->index()->is_register()) {
1262 index = addr->index()->as_register();
1263 }
1264 if ((base == to_lo && index == to_hi) ||
1265 (base == to_hi && index == to_lo)) {
1266 // addresses with 2 registers are only formed as a result of
1267 // array access so this code will never have to deal with
1268 // patches or null checks.
1269 assert(info == nullptr && patch == nullptr, "must be");
1270 __ lea(to_hi, as_Address(addr));
1271 __ movl(to_lo, Address(to_hi, 0));
1272 __ movl(to_hi, Address(to_hi, BytesPerWord));
1273 } else if (base == to_lo || index == to_lo) {
1274 assert(base != to_hi, "can't be");
1275 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1276 __ movl(to_hi, as_Address_hi(addr));
1277 if (patch != nullptr) {
1278 patching_epilog(patch, lir_patch_high, base, info);
1279 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1280 patch_code = lir_patch_low;
1281 }
1282 __ movl(to_lo, as_Address_lo(addr));
1283 } else {
1284 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1285 __ movl(to_lo, as_Address_lo(addr));
1286 if (patch != nullptr) {
1287 patching_epilog(patch, lir_patch_low, base, info);
1288 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1289 patch_code = lir_patch_high;
1290 }
1291 __ movl(to_hi, as_Address_hi(addr));
1292 }
1293 #endif // _LP64
1294 break;
1295 }
1296
1297 case T_BOOLEAN: // fall through
1298 case T_BYTE: {
1299 Register dest_reg = dest->as_register();
1300 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1301 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1302 __ movsbl(dest_reg, from_addr);
1303 } else {
1304 __ movb(dest_reg, from_addr);
1305 __ shll(dest_reg, 24);
1306 __ sarl(dest_reg, 24);
1307 }
1308 break;
1309 }
1310
1311 case T_CHAR: {
1312 Register dest_reg = dest->as_register();
1313 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1314 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1315 __ movzwl(dest_reg, from_addr);
1316 } else {
1317 __ movw(dest_reg, from_addr);
1318 }
1319 break;
1320 }
1321
1322 case T_SHORT: {
1323 Register dest_reg = dest->as_register();
1324 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1325 __ movswl(dest_reg, from_addr);
1326 } else {
1327 __ movw(dest_reg, from_addr);
1328 __ shll(dest_reg, 16);
1329 __ sarl(dest_reg, 16);
1330 }
1331 break;
1332 }
1333
1334 default:
1335 ShouldNotReachHere();
1336 }
1337
1338 if (patch != nullptr) {
1339 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1340 }
1341
1342 if (is_reference_type(type)) {
1343 #ifdef _LP64
1344 if (UseCompressedOops && !wide) {
1345 __ decode_heap_oop(dest->as_register());
1346 }
1347 #endif
1348
1349 __ verify_oop(dest->as_register());
1350 }
1351 }
1352
1353
1354 NEEDS_CLEANUP; // This could be static?
1355 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1356 int elem_size = type2aelembytes(type);
1357 switch (elem_size) {
1358 case 1: return Address::times_1;
1359 case 2: return Address::times_2;
1360 case 4: return Address::times_4;
1361 case 8: return Address::times_8;
1362 }
1363 ShouldNotReachHere();
1364 return Address::no_scale;
1365 }
1366
1367
1368 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1369 switch (op->code()) {
1370 case lir_idiv:
1371 case lir_irem:
1372 arithmetic_idiv(op->code(),
1373 op->in_opr1(),
1374 op->in_opr2(),
1375 op->in_opr3(),
1376 op->result_opr(),
1377 op->info());
1378 break;
1379 case lir_fmad:
1380 __ fmad(op->result_opr()->as_xmm_double_reg(),
1381 op->in_opr1()->as_xmm_double_reg(),
1382 op->in_opr2()->as_xmm_double_reg(),
1383 op->in_opr3()->as_xmm_double_reg());
1384 break;
1385 case lir_fmaf:
1386 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1387 op->in_opr1()->as_xmm_float_reg(),
1388 op->in_opr2()->as_xmm_float_reg(),
1389 op->in_opr3()->as_xmm_float_reg());
1390 break;
1391 default: ShouldNotReachHere(); break;
1392 }
1393 }
1394
1395 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1396 #ifdef ASSERT
1397 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1398 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1399 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1400 #endif
1401
1402 if (op->cond() == lir_cond_always) {
1403 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1404 __ jmp (*(op->label()));
1405 } else {
1406 Assembler::Condition acond = Assembler::zero;
1407 if (op->code() == lir_cond_float_branch) {
1408 assert(op->ublock() != nullptr, "must have unordered successor");
1409 __ jcc(Assembler::parity, *(op->ublock()->label()));
1410 switch(op->cond()) {
1411 case lir_cond_equal: acond = Assembler::equal; break;
1412 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1413 case lir_cond_less: acond = Assembler::below; break;
1414 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1415 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1416 case lir_cond_greater: acond = Assembler::above; break;
1417 default: ShouldNotReachHere();
1418 }
1419 } else {
1420 switch (op->cond()) {
1421 case lir_cond_equal: acond = Assembler::equal; break;
1422 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1423 case lir_cond_less: acond = Assembler::less; break;
1424 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1425 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1426 case lir_cond_greater: acond = Assembler::greater; break;
1427 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1428 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1429 default: ShouldNotReachHere();
1430 }
1431 }
1432 __ jcc(acond,*(op->label()));
1433 }
1434 }
1435
1436 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1437 LIR_Opr src = op->in_opr();
1438 LIR_Opr dest = op->result_opr();
1439
1440 switch (op->bytecode()) {
1441 case Bytecodes::_i2l:
1442 #ifdef _LP64
1443 __ movl2ptr(dest->as_register_lo(), src->as_register());
1444 #else
1445 move_regs(src->as_register(), dest->as_register_lo());
1446 move_regs(src->as_register(), dest->as_register_hi());
1447 __ sarl(dest->as_register_hi(), 31);
1448 #endif // LP64
1449 break;
1450
1451 case Bytecodes::_l2i:
1452 #ifdef _LP64
1453 __ movl(dest->as_register(), src->as_register_lo());
1454 #else
1455 move_regs(src->as_register_lo(), dest->as_register());
1456 #endif
1457 break;
1458
1459 case Bytecodes::_i2b:
1460 move_regs(src->as_register(), dest->as_register());
1461 __ sign_extend_byte(dest->as_register());
1462 break;
1463
1464 case Bytecodes::_i2c:
1465 move_regs(src->as_register(), dest->as_register());
1466 __ andl(dest->as_register(), 0xFFFF);
1467 break;
1468
1469 case Bytecodes::_i2s:
1470 move_regs(src->as_register(), dest->as_register());
1471 __ sign_extend_short(dest->as_register());
1472 break;
1473
1474
1475 #ifdef _LP64
1476 case Bytecodes::_f2d:
1477 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1478 break;
1479
1480 case Bytecodes::_d2f:
1481 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1482 break;
1483
1484 case Bytecodes::_i2f:
1485 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1486 break;
1487
1488 case Bytecodes::_i2d:
1489 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1490 break;
1491
1492 case Bytecodes::_l2f:
1493 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1494 break;
1495
1496 case Bytecodes::_l2d:
1497 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1498 break;
1499
1500 case Bytecodes::_f2i:
1501 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1502 break;
1503
1504 case Bytecodes::_d2i:
1505 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1506 break;
1507
1508 case Bytecodes::_f2l:
1509 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1510 break;
1511
1512 case Bytecodes::_d2l:
1513 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1514 break;
1515 #else
1516 case Bytecodes::_f2d:
1517 case Bytecodes::_d2f:
1518 if (dest->is_single_xmm()) {
1519 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1520 } else if (dest->is_double_xmm()) {
1521 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1522 } else {
1523 assert(src->fpu() == dest->fpu(), "register must be equal");
1524 // do nothing (float result is rounded later through spilling)
1525 }
1526 break;
1527
1528 case Bytecodes::_i2f:
1529 case Bytecodes::_i2d:
1530 if (dest->is_single_xmm()) {
1531 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1532 } else if (dest->is_double_xmm()) {
1533 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1534 } else {
1535 assert(dest->fpu() == 0, "result must be on TOS");
1536 __ movl(Address(rsp, 0), src->as_register());
1537 __ fild_s(Address(rsp, 0));
1538 }
1539 break;
1540
1541 case Bytecodes::_l2f:
1542 case Bytecodes::_l2d:
1543 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1544 assert(dest->fpu() == 0, "result must be on TOS");
1545 __ movptr(Address(rsp, 0), src->as_register_lo());
1546 __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1547 __ fild_d(Address(rsp, 0));
1548 // float result is rounded later through spilling
1549 break;
1550
1551 case Bytecodes::_f2i:
1552 case Bytecodes::_d2i:
1553 if (src->is_single_xmm()) {
1554 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1555 } else if (src->is_double_xmm()) {
1556 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1557 } else {
1558 assert(src->fpu() == 0, "input must be on TOS");
1559 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc()));
1560 __ fist_s(Address(rsp, 0));
1561 __ movl(dest->as_register(), Address(rsp, 0));
1562 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
1563 }
1564 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1565 assert(op->stub() != nullptr, "stub required");
1566 __ cmpl(dest->as_register(), 0x80000000);
1567 __ jcc(Assembler::equal, *op->stub()->entry());
1568 __ bind(*op->stub()->continuation());
1569 break;
1570
1571 case Bytecodes::_f2l:
1572 case Bytecodes::_d2l:
1573 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1574 assert(src->fpu() == 0, "input must be on TOS");
1575 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1576
1577 // instruction sequence too long to inline it here
1578 {
1579 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::fpu2long_stub_id)));
1580 }
1581 break;
1582 #endif // _LP64
1583
1584 default: ShouldNotReachHere();
1585 }
1586 }
1587
1588 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1589 if (op->init_check()) {
1590 add_debug_info_for_null_check_here(op->stub()->info());
1591 // init_state needs acquire, but x86 is TSO, and so we are already good.
1592 __ cmpb(Address(op->klass()->as_register(),
1593 InstanceKlass::init_state_offset()),
1594 InstanceKlass::fully_initialized);
1595 __ jcc(Assembler::notEqual, *op->stub()->entry());
1596 }
1597 __ allocate_object(op->obj()->as_register(),
1598 op->tmp1()->as_register(),
1599 op->tmp2()->as_register(),
1600 op->header_size(),
1601 op->object_size(),
1602 op->klass()->as_register(),
1603 *op->stub()->entry());
1604 __ bind(*op->stub()->continuation());
1605 }
1606
1607 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1608 Register len = op->len()->as_register();
1609 LP64_ONLY( __ movslq(len, len); )
1610
1611 if (UseSlowPath ||
1612 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1613 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1614 __ jmp(*op->stub()->entry());
1615 } else {
1616 Register tmp1 = op->tmp1()->as_register();
1617 Register tmp2 = op->tmp2()->as_register();
1618 Register tmp3 = op->tmp3()->as_register();
1619 if (len == tmp1) {
1620 tmp1 = tmp3;
1621 } else if (len == tmp2) {
1622 tmp2 = tmp3;
1623 } else if (len == tmp3) {
1624 // everything is ok
1625 } else {
1626 __ mov(tmp3, len);
1627 }
1628 __ allocate_array(op->obj()->as_register(),
1629 len,
1630 tmp1,
1631 tmp2,
1632 arrayOopDesc::base_offset_in_bytes(op->type()),
1633 array_element_size(op->type()),
1634 op->klass()->as_register(),
1635 *op->stub()->entry(),
1636 op->zero_array());
1637 }
1638 __ bind(*op->stub()->continuation());
1639 }
1640
1641 void LIR_Assembler::type_profile_helper(Register mdo,
1642 ciMethodData *md, ciProfileData *data,
1643 Register recv, Label* update_done) {
1644 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1645 Label next_test;
1646 // See if the receiver is receiver[n].
1647 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1648 __ jccb(Assembler::notEqual, next_test);
1649 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1650 __ addptr(data_addr, DataLayout::counter_increment);
1651 __ jmp(*update_done);
1652 __ bind(next_test);
1653 }
1654
1655 // Didn't find receiver; find next empty slot and fill it in
1656 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1657 Label next_test;
1658 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1659 __ cmpptr(recv_addr, NULL_WORD);
1660 __ jccb(Assembler::notEqual, next_test);
1661 __ movptr(recv_addr, recv);
1662 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1663 __ jmp(*update_done);
1664 __ bind(next_test);
1665 }
1666 }
1667
1668 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1669 // we always need a stub for the failure case.
1670 CodeStub* stub = op->stub();
1671 Register obj = op->object()->as_register();
1672 Register k_RInfo = op->tmp1()->as_register();
1673 Register klass_RInfo = op->tmp2()->as_register();
1674 Register dst = op->result_opr()->as_register();
1675 ciKlass* k = op->klass();
1676 Register Rtmp1 = noreg;
1677 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1678
1679 // check if it needs to be profiled
1680 ciMethodData* md = nullptr;
1681 ciProfileData* data = nullptr;
1682
1683 if (op->should_profile()) {
1684 ciMethod* method = op->profiled_method();
1685 assert(method != nullptr, "Should have method");
1686 int bci = op->profiled_bci();
1687 md = method->method_data_or_null();
1688 assert(md != nullptr, "Sanity");
1689 data = md->bci_to_data(bci);
1690 assert(data != nullptr, "need data for type check");
1691 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1692 }
1693 Label* success_target = success;
1694 Label* failure_target = failure;
1695
1696 if (obj == k_RInfo) {
1697 k_RInfo = dst;
1698 } else if (obj == klass_RInfo) {
1699 klass_RInfo = dst;
1700 }
1701 if (k->is_loaded() && !UseCompressedClassPointers) {
1702 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1703 } else {
1704 Rtmp1 = op->tmp3()->as_register();
1705 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1706 }
1707
1708 assert_different_registers(obj, k_RInfo, klass_RInfo);
1709
1710 __ testptr(obj, obj);
1711 if (op->should_profile()) {
1712 Label not_null;
1713 Register mdo = klass_RInfo;
1714 __ mov_metadata(mdo, md->constant_encoding());
1715 __ jccb(Assembler::notEqual, not_null);
1716 // Object is null; update MDO and exit
1717 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1718 int header_bits = BitData::null_seen_byte_constant();
1719 __ orb(data_addr, header_bits);
1720 __ jmp(*obj_is_null);
1721 __ bind(not_null);
1722
1723 Label update_done;
1724 Register recv = k_RInfo;
1725 __ load_klass(recv, obj, tmp_load_klass);
1726 type_profile_helper(mdo, md, data, recv, &update_done);
1727
1728 Address nonprofiled_receiver_count_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1729 __ addptr(nonprofiled_receiver_count_addr, DataLayout::counter_increment);
1730
1731 __ bind(update_done);
1732 } else {
1733 __ jcc(Assembler::equal, *obj_is_null);
1734 }
1735
1736 if (!k->is_loaded()) {
1737 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1738 } else {
1739 #ifdef _LP64
1740 __ mov_metadata(k_RInfo, k->constant_encoding());
1741 #endif // _LP64
1742 }
1743 __ verify_oop(obj);
1744
1745 if (op->fast_check()) {
1746 // get object class
1747 // not a safepoint as obj null check happens earlier
1748 #ifdef _LP64
1749 if (UseCompressedClassPointers) {
1750 __ load_klass(Rtmp1, obj, tmp_load_klass);
1751 __ cmpptr(k_RInfo, Rtmp1);
1752 } else {
1753 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1754 }
1755 #else
1756 if (k->is_loaded()) {
1757 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1758 } else {
1759 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1760 }
1761 #endif
1762 __ jcc(Assembler::notEqual, *failure_target);
1763 // successful cast, fall through to profile or jump
1764 } else {
1765 // get object class
1766 // not a safepoint as obj null check happens earlier
1767 __ load_klass(klass_RInfo, obj, tmp_load_klass);
1768 if (k->is_loaded()) {
1769 // See if we get an immediate positive hit
1770 #ifdef _LP64
1771 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1772 #else
1773 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1774 #endif // _LP64
1775 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1776 __ jcc(Assembler::notEqual, *failure_target);
1777 // successful cast, fall through to profile or jump
1778 } else {
1779 // See if we get an immediate positive hit
1780 __ jcc(Assembler::equal, *success_target);
1781 // check for self
1782 #ifdef _LP64
1783 __ cmpptr(klass_RInfo, k_RInfo);
1784 #else
1785 __ cmpklass(klass_RInfo, k->constant_encoding());
1786 #endif // _LP64
1787 __ jcc(Assembler::equal, *success_target);
1788
1789 __ push(klass_RInfo);
1790 #ifdef _LP64
1791 __ push(k_RInfo);
1792 #else
1793 __ pushklass(k->constant_encoding(), noreg);
1794 #endif // _LP64
1795 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1796 __ pop(klass_RInfo);
1797 __ pop(klass_RInfo);
1798 // result is a boolean
1799 __ testl(klass_RInfo, klass_RInfo);
1800 __ jcc(Assembler::equal, *failure_target);
1801 // successful cast, fall through to profile or jump
1802 }
1803 } else {
1804 // perform the fast part of the checking logic
1805 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1806 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1807 __ push(klass_RInfo);
1808 __ push(k_RInfo);
1809 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1810 __ pop(klass_RInfo);
1811 __ pop(k_RInfo);
1812 // result is a boolean
1813 __ testl(k_RInfo, k_RInfo);
1814 __ jcc(Assembler::equal, *failure_target);
1815 // successful cast, fall through to profile or jump
1816 }
1817 }
1818 __ jmp(*success);
1819 }
1820
1821
1822 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1823 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1824 LIR_Code code = op->code();
1825 if (code == lir_store_check) {
1826 Register value = op->object()->as_register();
1827 Register array = op->array()->as_register();
1828 Register k_RInfo = op->tmp1()->as_register();
1829 Register klass_RInfo = op->tmp2()->as_register();
1830 Register Rtmp1 = op->tmp3()->as_register();
1831
1832 CodeStub* stub = op->stub();
1833
1834 // check if it needs to be profiled
1835 ciMethodData* md = nullptr;
1836 ciProfileData* data = nullptr;
1837
1838 if (op->should_profile()) {
1839 ciMethod* method = op->profiled_method();
1840 assert(method != nullptr, "Should have method");
1841 int bci = op->profiled_bci();
1842 md = method->method_data_or_null();
1843 assert(md != nullptr, "Sanity");
1844 data = md->bci_to_data(bci);
1845 assert(data != nullptr, "need data for type check");
1846 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1847 }
1848 Label done;
1849 Label* success_target = &done;
1850 Label* failure_target = stub->entry();
1851
1852 __ testptr(value, value);
1853 if (op->should_profile()) {
1854 Label not_null;
1855 Register mdo = klass_RInfo;
1856 __ mov_metadata(mdo, md->constant_encoding());
1857 __ jccb(Assembler::notEqual, not_null);
1858 // Object is null; update MDO and exit
1859 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1860 int header_bits = BitData::null_seen_byte_constant();
1861 __ orb(data_addr, header_bits);
1862 __ jmp(done);
1863 __ bind(not_null);
1864
1865 Label update_done;
1866 Register recv = k_RInfo;
1867 __ load_klass(recv, value, tmp_load_klass);
1868 type_profile_helper(mdo, md, data, recv, &update_done);
1869
1870 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1871 __ addptr(counter_addr, DataLayout::counter_increment);
1872 __ bind(update_done);
1873 } else {
1874 __ jcc(Assembler::equal, done);
1875 }
1876
1877 add_debug_info_for_null_check_here(op->info_for_exception());
1878 __ load_klass(k_RInfo, array, tmp_load_klass);
1879 __ load_klass(klass_RInfo, value, tmp_load_klass);
1880
1881 // get instance klass (it's already uncompressed)
1882 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1883 // perform the fast part of the checking logic
1884 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1885 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1886 __ push(klass_RInfo);
1887 __ push(k_RInfo);
1888 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1889 __ pop(klass_RInfo);
1890 __ pop(k_RInfo);
1891 // result is a boolean
1892 __ testl(k_RInfo, k_RInfo);
1893 __ jcc(Assembler::equal, *failure_target);
1894 // fall through to the success case
1895
1896 __ bind(done);
1897 } else
1898 if (code == lir_checkcast) {
1899 Register obj = op->object()->as_register();
1900 Register dst = op->result_opr()->as_register();
1901 Label success;
1902 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1903 __ bind(success);
1904 if (dst != obj) {
1905 __ mov(dst, obj);
1906 }
1907 } else
1908 if (code == lir_instanceof) {
1909 Register obj = op->object()->as_register();
1910 Register dst = op->result_opr()->as_register();
1911 Label success, failure, done;
1912 emit_typecheck_helper(op, &success, &failure, &failure);
1913 __ bind(failure);
1914 __ xorptr(dst, dst);
1915 __ jmpb(done);
1916 __ bind(success);
1917 __ movptr(dst, 1);
1918 __ bind(done);
1919 } else {
1920 ShouldNotReachHere();
1921 }
1922
1923 }
1924
1925
1926 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1927 if (LP64_ONLY(false &&) op->code() == lir_cas_long) {
1928 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1929 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1930 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1931 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1932 Register addr = op->addr()->as_register();
1933 __ lock();
1934 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1935
1936 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1937 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1938 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1939 Register newval = op->new_value()->as_register();
1940 Register cmpval = op->cmp_value()->as_register();
1941 assert(cmpval == rax, "wrong register");
1942 assert(newval != noreg, "new val must be register");
1943 assert(cmpval != newval, "cmp and new values must be in different registers");
1944 assert(cmpval != addr, "cmp and addr must be in different registers");
1945 assert(newval != addr, "new value and addr must be in different registers");
1946
1947 if ( op->code() == lir_cas_obj) {
1948 #ifdef _LP64
1949 if (UseCompressedOops) {
1950 __ encode_heap_oop(cmpval);
1951 __ mov(rscratch1, newval);
1952 __ encode_heap_oop(rscratch1);
1953 __ lock();
1954 // cmpval (rax) is implicitly used by this instruction
1955 __ cmpxchgl(rscratch1, Address(addr, 0));
1956 } else
1957 #endif
1958 {
1959 __ lock();
1960 __ cmpxchgptr(newval, Address(addr, 0));
1961 }
1962 } else {
1963 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1964 __ lock();
1965 __ cmpxchgl(newval, Address(addr, 0));
1966 }
1967 #ifdef _LP64
1968 } else if (op->code() == lir_cas_long) {
1969 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1970 Register newval = op->new_value()->as_register_lo();
1971 Register cmpval = op->cmp_value()->as_register_lo();
1972 assert(cmpval == rax, "wrong register");
1973 assert(newval != noreg, "new val must be register");
1974 assert(cmpval != newval, "cmp and new values must be in different registers");
1975 assert(cmpval != addr, "cmp and addr must be in different registers");
1976 assert(newval != addr, "new value and addr must be in different registers");
1977 __ lock();
1978 __ cmpxchgq(newval, Address(addr, 0));
1979 #endif // _LP64
1980 } else {
1981 Unimplemented();
1982 }
1983 }
1984
1985 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1986 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1987 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
1988
1989 Assembler::Condition acond, ncond;
1990 switch (condition) {
1991 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1992 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1993 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1994 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1995 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1996 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1997 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1998 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1999 default: acond = Assembler::equal; ncond = Assembler::notEqual;
2000 ShouldNotReachHere();
2001 }
2002
2003 if (opr1->is_cpu_register()) {
2004 reg2reg(opr1, result);
2005 } else if (opr1->is_stack()) {
2006 stack2reg(opr1, result, result->type());
2007 } else if (opr1->is_constant()) {
2008 const2reg(opr1, result, lir_patch_none, nullptr);
2009 } else {
2010 ShouldNotReachHere();
2011 }
2012
2013 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2014 // optimized version that does not require a branch
2015 if (opr2->is_single_cpu()) {
2016 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2017 __ cmov(ncond, result->as_register(), opr2->as_register());
2018 } else if (opr2->is_double_cpu()) {
2019 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2020 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2021 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2022 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2023 } else if (opr2->is_single_stack()) {
2024 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2025 } else if (opr2->is_double_stack()) {
2026 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2027 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2028 } else {
2029 ShouldNotReachHere();
2030 }
2031
2032 } else {
2033 Label skip;
2034 __ jccb(acond, skip);
2035 if (opr2->is_cpu_register()) {
2036 reg2reg(opr2, result);
2037 } else if (opr2->is_stack()) {
2038 stack2reg(opr2, result, result->type());
2039 } else if (opr2->is_constant()) {
2040 const2reg(opr2, result, lir_patch_none, nullptr);
2041 } else {
2042 ShouldNotReachHere();
2043 }
2044 __ bind(skip);
2045 }
2046 }
2047
2048
2049 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2050 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2051
2052 if (left->is_single_cpu()) {
2053 assert(left == dest, "left and dest must be equal");
2054 Register lreg = left->as_register();
2055
2056 if (right->is_single_cpu()) {
2057 // cpu register - cpu register
2058 Register rreg = right->as_register();
2059 switch (code) {
2060 case lir_add: __ addl (lreg, rreg); break;
2061 case lir_sub: __ subl (lreg, rreg); break;
2062 case lir_mul: __ imull(lreg, rreg); break;
2063 default: ShouldNotReachHere();
2064 }
2065
2066 } else if (right->is_stack()) {
2067 // cpu register - stack
2068 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2069 switch (code) {
2070 case lir_add: __ addl(lreg, raddr); break;
2071 case lir_sub: __ subl(lreg, raddr); break;
2072 default: ShouldNotReachHere();
2073 }
2074
2075 } else if (right->is_constant()) {
2076 // cpu register - constant
2077 jint c = right->as_constant_ptr()->as_jint();
2078 switch (code) {
2079 case lir_add: {
2080 __ incrementl(lreg, c);
2081 break;
2082 }
2083 case lir_sub: {
2084 __ decrementl(lreg, c);
2085 break;
2086 }
2087 default: ShouldNotReachHere();
2088 }
2089
2090 } else {
2091 ShouldNotReachHere();
2092 }
2093
2094 } else if (left->is_double_cpu()) {
2095 assert(left == dest, "left and dest must be equal");
2096 Register lreg_lo = left->as_register_lo();
2097 Register lreg_hi = left->as_register_hi();
2098
2099 if (right->is_double_cpu()) {
2100 // cpu register - cpu register
2101 Register rreg_lo = right->as_register_lo();
2102 Register rreg_hi = right->as_register_hi();
2103 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2104 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2105 switch (code) {
2106 case lir_add:
2107 __ addptr(lreg_lo, rreg_lo);
2108 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2109 break;
2110 case lir_sub:
2111 __ subptr(lreg_lo, rreg_lo);
2112 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2113 break;
2114 case lir_mul:
2115 #ifdef _LP64
2116 __ imulq(lreg_lo, rreg_lo);
2117 #else
2118 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2119 __ imull(lreg_hi, rreg_lo);
2120 __ imull(rreg_hi, lreg_lo);
2121 __ addl (rreg_hi, lreg_hi);
2122 __ mull (rreg_lo);
2123 __ addl (lreg_hi, rreg_hi);
2124 #endif // _LP64
2125 break;
2126 default:
2127 ShouldNotReachHere();
2128 }
2129
2130 } else if (right->is_constant()) {
2131 // cpu register - constant
2132 #ifdef _LP64
2133 jlong c = right->as_constant_ptr()->as_jlong_bits();
2134 __ movptr(r10, (intptr_t) c);
2135 switch (code) {
2136 case lir_add:
2137 __ addptr(lreg_lo, r10);
2138 break;
2139 case lir_sub:
2140 __ subptr(lreg_lo, r10);
2141 break;
2142 default:
2143 ShouldNotReachHere();
2144 }
2145 #else
2146 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2147 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2148 switch (code) {
2149 case lir_add:
2150 __ addptr(lreg_lo, c_lo);
2151 __ adcl(lreg_hi, c_hi);
2152 break;
2153 case lir_sub:
2154 __ subptr(lreg_lo, c_lo);
2155 __ sbbl(lreg_hi, c_hi);
2156 break;
2157 default:
2158 ShouldNotReachHere();
2159 }
2160 #endif // _LP64
2161
2162 } else {
2163 ShouldNotReachHere();
2164 }
2165
2166 } else if (left->is_single_xmm()) {
2167 assert(left == dest, "left and dest must be equal");
2168 XMMRegister lreg = left->as_xmm_float_reg();
2169
2170 if (right->is_single_xmm()) {
2171 XMMRegister rreg = right->as_xmm_float_reg();
2172 switch (code) {
2173 case lir_add: __ addss(lreg, rreg); break;
2174 case lir_sub: __ subss(lreg, rreg); break;
2175 case lir_mul: __ mulss(lreg, rreg); break;
2176 case lir_div: __ divss(lreg, rreg); break;
2177 default: ShouldNotReachHere();
2178 }
2179 } else {
2180 Address raddr;
2181 if (right->is_single_stack()) {
2182 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2183 } else if (right->is_constant()) {
2184 // hack for now
2185 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2186 } else {
2187 ShouldNotReachHere();
2188 }
2189 switch (code) {
2190 case lir_add: __ addss(lreg, raddr); break;
2191 case lir_sub: __ subss(lreg, raddr); break;
2192 case lir_mul: __ mulss(lreg, raddr); break;
2193 case lir_div: __ divss(lreg, raddr); break;
2194 default: ShouldNotReachHere();
2195 }
2196 }
2197
2198 } else if (left->is_double_xmm()) {
2199 assert(left == dest, "left and dest must be equal");
2200
2201 XMMRegister lreg = left->as_xmm_double_reg();
2202 if (right->is_double_xmm()) {
2203 XMMRegister rreg = right->as_xmm_double_reg();
2204 switch (code) {
2205 case lir_add: __ addsd(lreg, rreg); break;
2206 case lir_sub: __ subsd(lreg, rreg); break;
2207 case lir_mul: __ mulsd(lreg, rreg); break;
2208 case lir_div: __ divsd(lreg, rreg); break;
2209 default: ShouldNotReachHere();
2210 }
2211 } else {
2212 Address raddr;
2213 if (right->is_double_stack()) {
2214 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2215 } else if (right->is_constant()) {
2216 // hack for now
2217 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2218 } else {
2219 ShouldNotReachHere();
2220 }
2221 switch (code) {
2222 case lir_add: __ addsd(lreg, raddr); break;
2223 case lir_sub: __ subsd(lreg, raddr); break;
2224 case lir_mul: __ mulsd(lreg, raddr); break;
2225 case lir_div: __ divsd(lreg, raddr); break;
2226 default: ShouldNotReachHere();
2227 }
2228 }
2229
2230 #ifndef _LP64
2231 } else if (left->is_single_fpu()) {
2232 assert(dest->is_single_fpu(), "fpu stack allocation required");
2233
2234 if (right->is_single_fpu()) {
2235 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2236
2237 } else {
2238 assert(left->fpu_regnr() == 0, "left must be on TOS");
2239 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2240
2241 Address raddr;
2242 if (right->is_single_stack()) {
2243 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2244 } else if (right->is_constant()) {
2245 address const_addr = float_constant(right->as_jfloat());
2246 assert(const_addr != nullptr, "incorrect float/double constant maintenance");
2247 // hack for now
2248 raddr = __ as_Address(InternalAddress(const_addr));
2249 } else {
2250 ShouldNotReachHere();
2251 }
2252
2253 switch (code) {
2254 case lir_add: __ fadd_s(raddr); break;
2255 case lir_sub: __ fsub_s(raddr); break;
2256 case lir_mul: __ fmul_s(raddr); break;
2257 case lir_div: __ fdiv_s(raddr); break;
2258 default: ShouldNotReachHere();
2259 }
2260 }
2261
2262 } else if (left->is_double_fpu()) {
2263 assert(dest->is_double_fpu(), "fpu stack allocation required");
2264
2265 if (code == lir_mul || code == lir_div) {
2266 // Double values require special handling for strictfp mul/div on x86
2267 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1()));
2268 __ fmulp(left->fpu_regnrLo() + 1);
2269 }
2270
2271 if (right->is_double_fpu()) {
2272 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2273
2274 } else {
2275 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2276 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2277
2278 Address raddr;
2279 if (right->is_double_stack()) {
2280 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2281 } else if (right->is_constant()) {
2282 // hack for now
2283 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2284 } else {
2285 ShouldNotReachHere();
2286 }
2287
2288 switch (code) {
2289 case lir_add: __ fadd_d(raddr); break;
2290 case lir_sub: __ fsub_d(raddr); break;
2291 case lir_mul: __ fmul_d(raddr); break;
2292 case lir_div: __ fdiv_d(raddr); break;
2293 default: ShouldNotReachHere();
2294 }
2295 }
2296
2297 if (code == lir_mul || code == lir_div) {
2298 // Double values require special handling for strictfp mul/div on x86
2299 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2()));
2300 __ fmulp(dest->fpu_regnrLo() + 1);
2301 }
2302 #endif // !_LP64
2303
2304 } else if (left->is_single_stack() || left->is_address()) {
2305 assert(left == dest, "left and dest must be equal");
2306
2307 Address laddr;
2308 if (left->is_single_stack()) {
2309 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2310 } else if (left->is_address()) {
2311 laddr = as_Address(left->as_address_ptr());
2312 } else {
2313 ShouldNotReachHere();
2314 }
2315
2316 if (right->is_single_cpu()) {
2317 Register rreg = right->as_register();
2318 switch (code) {
2319 case lir_add: __ addl(laddr, rreg); break;
2320 case lir_sub: __ subl(laddr, rreg); break;
2321 default: ShouldNotReachHere();
2322 }
2323 } else if (right->is_constant()) {
2324 jint c = right->as_constant_ptr()->as_jint();
2325 switch (code) {
2326 case lir_add: {
2327 __ incrementl(laddr, c);
2328 break;
2329 }
2330 case lir_sub: {
2331 __ decrementl(laddr, c);
2332 break;
2333 }
2334 default: ShouldNotReachHere();
2335 }
2336 } else {
2337 ShouldNotReachHere();
2338 }
2339
2340 } else {
2341 ShouldNotReachHere();
2342 }
2343 }
2344
2345 #ifndef _LP64
2346 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2347 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2348 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2349 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2350
2351 bool left_is_tos = (left_index == 0);
2352 bool dest_is_tos = (dest_index == 0);
2353 int non_tos_index = (left_is_tos ? right_index : left_index);
2354
2355 switch (code) {
2356 case lir_add:
2357 if (pop_fpu_stack) __ faddp(non_tos_index);
2358 else if (dest_is_tos) __ fadd (non_tos_index);
2359 else __ fadda(non_tos_index);
2360 break;
2361
2362 case lir_sub:
2363 if (left_is_tos) {
2364 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2365 else if (dest_is_tos) __ fsub (non_tos_index);
2366 else __ fsubra(non_tos_index);
2367 } else {
2368 if (pop_fpu_stack) __ fsubp (non_tos_index);
2369 else if (dest_is_tos) __ fsubr (non_tos_index);
2370 else __ fsuba (non_tos_index);
2371 }
2372 break;
2373
2374 case lir_mul:
2375 if (pop_fpu_stack) __ fmulp(non_tos_index);
2376 else if (dest_is_tos) __ fmul (non_tos_index);
2377 else __ fmula(non_tos_index);
2378 break;
2379
2380 case lir_div:
2381 if (left_is_tos) {
2382 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2383 else if (dest_is_tos) __ fdiv (non_tos_index);
2384 else __ fdivra(non_tos_index);
2385 } else {
2386 if (pop_fpu_stack) __ fdivp (non_tos_index);
2387 else if (dest_is_tos) __ fdivr (non_tos_index);
2388 else __ fdiva (non_tos_index);
2389 }
2390 break;
2391
2392 case lir_rem:
2393 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2394 __ fremr(noreg);
2395 break;
2396
2397 default:
2398 ShouldNotReachHere();
2399 }
2400 }
2401 #endif // _LP64
2402
2403
2404 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2405 if (value->is_double_xmm()) {
2406 switch(code) {
2407 case lir_abs :
2408 {
2409 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2410 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2411 }
2412 assert(!tmp->is_valid(), "do not need temporary");
2413 __ andpd(dest->as_xmm_double_reg(),
2414 ExternalAddress(LIR_Assembler::double_signmask_pool),
2415 rscratch1);
2416 }
2417 break;
2418
2419 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2420 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2421 default : ShouldNotReachHere();
2422 }
2423
2424 #ifndef _LP64
2425 } else if (value->is_double_fpu()) {
2426 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2427 switch(code) {
2428 case lir_abs : __ fabs() ; break;
2429 case lir_sqrt : __ fsqrt(); break;
2430 default : ShouldNotReachHere();
2431 }
2432 #endif // !_LP64
2433 } else if (code == lir_f2hf) {
2434 __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg());
2435 } else if (code == lir_hf2f) {
2436 __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register());
2437 } else {
2438 Unimplemented();
2439 }
2440 }
2441
2442 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2443 // assert(left->destroys_register(), "check");
2444 if (left->is_single_cpu()) {
2445 Register reg = left->as_register();
2446 if (right->is_constant()) {
2447 int val = right->as_constant_ptr()->as_jint();
2448 switch (code) {
2449 case lir_logic_and: __ andl (reg, val); break;
2450 case lir_logic_or: __ orl (reg, val); break;
2451 case lir_logic_xor: __ xorl (reg, val); break;
2452 default: ShouldNotReachHere();
2453 }
2454 } else if (right->is_stack()) {
2455 // added support for stack operands
2456 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2457 switch (code) {
2458 case lir_logic_and: __ andl (reg, raddr); break;
2459 case lir_logic_or: __ orl (reg, raddr); break;
2460 case lir_logic_xor: __ xorl (reg, raddr); break;
2461 default: ShouldNotReachHere();
2462 }
2463 } else {
2464 Register rright = right->as_register();
2465 switch (code) {
2466 case lir_logic_and: __ andptr (reg, rright); break;
2467 case lir_logic_or : __ orptr (reg, rright); break;
2468 case lir_logic_xor: __ xorptr (reg, rright); break;
2469 default: ShouldNotReachHere();
2470 }
2471 }
2472 move_regs(reg, dst->as_register());
2473 } else {
2474 Register l_lo = left->as_register_lo();
2475 Register l_hi = left->as_register_hi();
2476 if (right->is_constant()) {
2477 #ifdef _LP64
2478 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2479 switch (code) {
2480 case lir_logic_and:
2481 __ andq(l_lo, rscratch1);
2482 break;
2483 case lir_logic_or:
2484 __ orq(l_lo, rscratch1);
2485 break;
2486 case lir_logic_xor:
2487 __ xorq(l_lo, rscratch1);
2488 break;
2489 default: ShouldNotReachHere();
2490 }
2491 #else
2492 int r_lo = right->as_constant_ptr()->as_jint_lo();
2493 int r_hi = right->as_constant_ptr()->as_jint_hi();
2494 switch (code) {
2495 case lir_logic_and:
2496 __ andl(l_lo, r_lo);
2497 __ andl(l_hi, r_hi);
2498 break;
2499 case lir_logic_or:
2500 __ orl(l_lo, r_lo);
2501 __ orl(l_hi, r_hi);
2502 break;
2503 case lir_logic_xor:
2504 __ xorl(l_lo, r_lo);
2505 __ xorl(l_hi, r_hi);
2506 break;
2507 default: ShouldNotReachHere();
2508 }
2509 #endif // _LP64
2510 } else {
2511 #ifdef _LP64
2512 Register r_lo;
2513 if (is_reference_type(right->type())) {
2514 r_lo = right->as_register();
2515 } else {
2516 r_lo = right->as_register_lo();
2517 }
2518 #else
2519 Register r_lo = right->as_register_lo();
2520 Register r_hi = right->as_register_hi();
2521 assert(l_lo != r_hi, "overwriting registers");
2522 #endif
2523 switch (code) {
2524 case lir_logic_and:
2525 __ andptr(l_lo, r_lo);
2526 NOT_LP64(__ andptr(l_hi, r_hi);)
2527 break;
2528 case lir_logic_or:
2529 __ orptr(l_lo, r_lo);
2530 NOT_LP64(__ orptr(l_hi, r_hi);)
2531 break;
2532 case lir_logic_xor:
2533 __ xorptr(l_lo, r_lo);
2534 NOT_LP64(__ xorptr(l_hi, r_hi);)
2535 break;
2536 default: ShouldNotReachHere();
2537 }
2538 }
2539
2540 Register dst_lo = dst->as_register_lo();
2541 Register dst_hi = dst->as_register_hi();
2542
2543 #ifdef _LP64
2544 move_regs(l_lo, dst_lo);
2545 #else
2546 if (dst_lo == l_hi) {
2547 assert(dst_hi != l_lo, "overwriting registers");
2548 move_regs(l_hi, dst_hi);
2549 move_regs(l_lo, dst_lo);
2550 } else {
2551 assert(dst_lo != l_hi, "overwriting registers");
2552 move_regs(l_lo, dst_lo);
2553 move_regs(l_hi, dst_hi);
2554 }
2555 #endif // _LP64
2556 }
2557 }
2558
2559
2560 // we assume that rax, and rdx can be overwritten
2561 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2562
2563 assert(left->is_single_cpu(), "left must be register");
2564 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2565 assert(result->is_single_cpu(), "result must be register");
2566
2567 // assert(left->destroys_register(), "check");
2568 // assert(right->destroys_register(), "check");
2569
2570 Register lreg = left->as_register();
2571 Register dreg = result->as_register();
2572
2573 if (right->is_constant()) {
2574 jint divisor = right->as_constant_ptr()->as_jint();
2575 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2576 if (code == lir_idiv) {
2577 assert(lreg == rax, "must be rax,");
2578 assert(temp->as_register() == rdx, "tmp register must be rdx");
2579 __ cdql(); // sign extend into rdx:rax
2580 if (divisor == 2) {
2581 __ subl(lreg, rdx);
2582 } else {
2583 __ andl(rdx, divisor - 1);
2584 __ addl(lreg, rdx);
2585 }
2586 __ sarl(lreg, log2i_exact(divisor));
2587 move_regs(lreg, dreg);
2588 } else if (code == lir_irem) {
2589 Label done;
2590 __ mov(dreg, lreg);
2591 __ andl(dreg, 0x80000000 | (divisor - 1));
2592 __ jcc(Assembler::positive, done);
2593 __ decrement(dreg);
2594 __ orl(dreg, ~(divisor - 1));
2595 __ increment(dreg);
2596 __ bind(done);
2597 } else {
2598 ShouldNotReachHere();
2599 }
2600 } else {
2601 Register rreg = right->as_register();
2602 assert(lreg == rax, "left register must be rax,");
2603 assert(rreg != rdx, "right register must not be rdx");
2604 assert(temp->as_register() == rdx, "tmp register must be rdx");
2605
2606 move_regs(lreg, rax);
2607
2608 int idivl_offset = __ corrected_idivl(rreg);
2609 if (ImplicitDiv0Checks) {
2610 add_debug_info_for_div0(idivl_offset, info);
2611 }
2612 if (code == lir_irem) {
2613 move_regs(rdx, dreg); // result is in rdx
2614 } else {
2615 move_regs(rax, dreg);
2616 }
2617 }
2618 }
2619
2620
2621 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2622 if (opr1->is_single_cpu()) {
2623 Register reg1 = opr1->as_register();
2624 if (opr2->is_single_cpu()) {
2625 // cpu register - cpu register
2626 if (is_reference_type(opr1->type())) {
2627 __ cmpoop(reg1, opr2->as_register());
2628 } else {
2629 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2630 __ cmpl(reg1, opr2->as_register());
2631 }
2632 } else if (opr2->is_stack()) {
2633 // cpu register - stack
2634 if (is_reference_type(opr1->type())) {
2635 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2636 } else {
2637 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2638 }
2639 } else if (opr2->is_constant()) {
2640 // cpu register - constant
2641 LIR_Const* c = opr2->as_constant_ptr();
2642 if (c->type() == T_INT) {
2643 jint i = c->as_jint();
2644 if (i == 0) {
2645 __ testl(reg1, reg1);
2646 } else {
2647 __ cmpl(reg1, i);
2648 }
2649 } else if (c->type() == T_METADATA) {
2650 // All we need for now is a comparison with null for equality.
2651 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2652 Metadata* m = c->as_metadata();
2653 if (m == nullptr) {
2654 __ testptr(reg1, reg1);
2655 } else {
2656 ShouldNotReachHere();
2657 }
2658 } else if (is_reference_type(c->type())) {
2659 // In 64bit oops are single register
2660 jobject o = c->as_jobject();
2661 if (o == nullptr) {
2662 __ testptr(reg1, reg1);
2663 } else {
2664 __ cmpoop(reg1, o, rscratch1);
2665 }
2666 } else {
2667 fatal("unexpected type: %s", basictype_to_str(c->type()));
2668 }
2669 // cpu register - address
2670 } else if (opr2->is_address()) {
2671 if (op->info() != nullptr) {
2672 add_debug_info_for_null_check_here(op->info());
2673 }
2674 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2675 } else {
2676 ShouldNotReachHere();
2677 }
2678
2679 } else if(opr1->is_double_cpu()) {
2680 Register xlo = opr1->as_register_lo();
2681 Register xhi = opr1->as_register_hi();
2682 if (opr2->is_double_cpu()) {
2683 #ifdef _LP64
2684 __ cmpptr(xlo, opr2->as_register_lo());
2685 #else
2686 // cpu register - cpu register
2687 Register ylo = opr2->as_register_lo();
2688 Register yhi = opr2->as_register_hi();
2689 __ subl(xlo, ylo);
2690 __ sbbl(xhi, yhi);
2691 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2692 __ orl(xhi, xlo);
2693 }
2694 #endif // _LP64
2695 } else if (opr2->is_constant()) {
2696 // cpu register - constant 0
2697 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2698 #ifdef _LP64
2699 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2700 #else
2701 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2702 __ orl(xhi, xlo);
2703 #endif // _LP64
2704 } else {
2705 ShouldNotReachHere();
2706 }
2707
2708 } else if (opr1->is_single_xmm()) {
2709 XMMRegister reg1 = opr1->as_xmm_float_reg();
2710 if (opr2->is_single_xmm()) {
2711 // xmm register - xmm register
2712 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2713 } else if (opr2->is_stack()) {
2714 // xmm register - stack
2715 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2716 } else if (opr2->is_constant()) {
2717 // xmm register - constant
2718 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2719 } else if (opr2->is_address()) {
2720 // xmm register - address
2721 if (op->info() != nullptr) {
2722 add_debug_info_for_null_check_here(op->info());
2723 }
2724 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2725 } else {
2726 ShouldNotReachHere();
2727 }
2728
2729 } else if (opr1->is_double_xmm()) {
2730 XMMRegister reg1 = opr1->as_xmm_double_reg();
2731 if (opr2->is_double_xmm()) {
2732 // xmm register - xmm register
2733 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2734 } else if (opr2->is_stack()) {
2735 // xmm register - stack
2736 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2737 } else if (opr2->is_constant()) {
2738 // xmm register - constant
2739 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2740 } else if (opr2->is_address()) {
2741 // xmm register - address
2742 if (op->info() != nullptr) {
2743 add_debug_info_for_null_check_here(op->info());
2744 }
2745 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2746 } else {
2747 ShouldNotReachHere();
2748 }
2749
2750 #ifndef _LP64
2751 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2752 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2753 assert(opr2->is_fpu_register(), "both must be registers");
2754 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2755 #endif // LP64
2756
2757 } else if (opr1->is_address() && opr2->is_constant()) {
2758 LIR_Const* c = opr2->as_constant_ptr();
2759 #ifdef _LP64
2760 if (is_reference_type(c->type())) {
2761 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2762 __ movoop(rscratch1, c->as_jobject());
2763 }
2764 #endif // LP64
2765 if (op->info() != nullptr) {
2766 add_debug_info_for_null_check_here(op->info());
2767 }
2768 // special case: address - constant
2769 LIR_Address* addr = opr1->as_address_ptr();
2770 if (c->type() == T_INT) {
2771 __ cmpl(as_Address(addr), c->as_jint());
2772 } else if (is_reference_type(c->type())) {
2773 #ifdef _LP64
2774 // %%% Make this explode if addr isn't reachable until we figure out a
2775 // better strategy by giving noreg as the temp for as_Address
2776 __ cmpoop(rscratch1, as_Address(addr, noreg));
2777 #else
2778 __ cmpoop(as_Address(addr), c->as_jobject());
2779 #endif // _LP64
2780 } else {
2781 ShouldNotReachHere();
2782 }
2783
2784 } else {
2785 ShouldNotReachHere();
2786 }
2787 }
2788
2789 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2790 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2791 if (left->is_single_xmm()) {
2792 assert(right->is_single_xmm(), "must match");
2793 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2794 } else if (left->is_double_xmm()) {
2795 assert(right->is_double_xmm(), "must match");
2796 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2797
2798 } else {
2799 #ifdef _LP64
2800 ShouldNotReachHere();
2801 #else
2802 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2803 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2804
2805 assert(left->fpu() == 0, "left must be on TOS");
2806 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2807 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2808 #endif // LP64
2809 }
2810 } else {
2811 assert(code == lir_cmp_l2i, "check");
2812 #ifdef _LP64
2813 Label done;
2814 Register dest = dst->as_register();
2815 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2816 __ movl(dest, -1);
2817 __ jccb(Assembler::less, done);
2818 __ setb(Assembler::notZero, dest);
2819 __ movzbl(dest, dest);
2820 __ bind(done);
2821 #else
2822 __ lcmp2int(left->as_register_hi(),
2823 left->as_register_lo(),
2824 right->as_register_hi(),
2825 right->as_register_lo());
2826 move_regs(left->as_register_hi(), dst->as_register());
2827 #endif // _LP64
2828 }
2829 }
2830
2831
2832 void LIR_Assembler::align_call(LIR_Code code) {
2833 // make sure that the displacement word of the call ends up word aligned
2834 int offset = __ offset();
2835 switch (code) {
2836 case lir_static_call:
2837 case lir_optvirtual_call:
2838 case lir_dynamic_call:
2839 offset += NativeCall::displacement_offset;
2840 break;
2841 case lir_icvirtual_call:
2842 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size_rex;
2843 break;
2844 default: ShouldNotReachHere();
2845 }
2846 __ align(BytesPerWord, offset);
2847 }
2848
2849
2850 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2851 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2852 "must be aligned");
2853 __ call(AddressLiteral(op->addr(), rtype));
2854 add_call_info(code_offset(), op->info());
2855 __ post_call_nop();
2856 }
2857
2858
2859 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2860 __ ic_call(op->addr());
2861 add_call_info(code_offset(), op->info());
2862 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2863 "must be aligned");
2864 __ post_call_nop();
2865 }
2866
2867
2868 void LIR_Assembler::emit_static_call_stub() {
2869 address call_pc = __ pc();
2870 address stub = __ start_a_stub(call_stub_size());
2871 if (stub == nullptr) {
2872 bailout("static call stub overflow");
2873 return;
2874 }
2875
2876 int start = __ offset();
2877
2878 // make sure that the displacement word of the call ends up word aligned
2879 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size_rex + NativeCall::displacement_offset);
2880 __ relocate(static_stub_Relocation::spec(call_pc));
2881 __ mov_metadata(rbx, (Metadata*)nullptr);
2882 // must be set to -1 at code generation time
2883 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2884 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2885 __ jump(RuntimeAddress(__ pc()));
2886
2887 assert(__ offset() - start <= call_stub_size(), "stub too big");
2888 __ end_a_stub();
2889 }
2890
2891
2892 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2893 assert(exceptionOop->as_register() == rax, "must match");
2894 assert(exceptionPC->as_register() == rdx, "must match");
2895
2896 // exception object is not added to oop map by LinearScan
2897 // (LinearScan assumes that no oops are in fixed registers)
2898 info->add_register_oop(exceptionOop);
2899 C1StubId unwind_id;
2900
2901 // get current pc information
2902 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2903 int pc_for_athrow_offset = __ offset();
2904 InternalAddress pc_for_athrow(__ pc());
2905 __ lea(exceptionPC->as_register(), pc_for_athrow);
2906 add_call_info(pc_for_athrow_offset, info); // for exception handler
2907
2908 __ verify_not_null_oop(rax);
2909 // search an exception handler (rax: exception oop, rdx: throwing pc)
2910 if (compilation()->has_fpu_code()) {
2911 unwind_id = C1StubId::handle_exception_id;
2912 } else {
2913 unwind_id = C1StubId::handle_exception_nofpu_id;
2914 }
2915 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2916
2917 // enough room for two byte trap
2918 __ nop();
2919 }
2920
2921
2922 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2923 assert(exceptionOop->as_register() == rax, "must match");
2924
2925 __ jmp(_unwind_handler_entry);
2926 }
2927
2928
2929 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2930
2931 // optimized version for linear scan:
2932 // * count must be already in ECX (guaranteed by LinearScan)
2933 // * left and dest must be equal
2934 // * tmp must be unused
2935 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2936 assert(left == dest, "left and dest must be equal");
2937 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2938
2939 if (left->is_single_cpu()) {
2940 Register value = left->as_register();
2941 assert(value != SHIFT_count, "left cannot be ECX");
2942
2943 switch (code) {
2944 case lir_shl: __ shll(value); break;
2945 case lir_shr: __ sarl(value); break;
2946 case lir_ushr: __ shrl(value); break;
2947 default: ShouldNotReachHere();
2948 }
2949 } else if (left->is_double_cpu()) {
2950 Register lo = left->as_register_lo();
2951 Register hi = left->as_register_hi();
2952 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2953 #ifdef _LP64
2954 switch (code) {
2955 case lir_shl: __ shlptr(lo); break;
2956 case lir_shr: __ sarptr(lo); break;
2957 case lir_ushr: __ shrptr(lo); break;
2958 default: ShouldNotReachHere();
2959 }
2960 #else
2961
2962 switch (code) {
2963 case lir_shl: __ lshl(hi, lo); break;
2964 case lir_shr: __ lshr(hi, lo, true); break;
2965 case lir_ushr: __ lshr(hi, lo, false); break;
2966 default: ShouldNotReachHere();
2967 }
2968 #endif // LP64
2969 } else {
2970 ShouldNotReachHere();
2971 }
2972 }
2973
2974
2975 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2976 if (dest->is_single_cpu()) {
2977 // first move left into dest so that left is not destroyed by the shift
2978 Register value = dest->as_register();
2979 count = count & 0x1F; // Java spec
2980
2981 move_regs(left->as_register(), value);
2982 switch (code) {
2983 case lir_shl: __ shll(value, count); break;
2984 case lir_shr: __ sarl(value, count); break;
2985 case lir_ushr: __ shrl(value, count); break;
2986 default: ShouldNotReachHere();
2987 }
2988 } else if (dest->is_double_cpu()) {
2989 #ifndef _LP64
2990 Unimplemented();
2991 #else
2992 // first move left into dest so that left is not destroyed by the shift
2993 Register value = dest->as_register_lo();
2994 count = count & 0x1F; // Java spec
2995
2996 move_regs(left->as_register_lo(), value);
2997 switch (code) {
2998 case lir_shl: __ shlptr(value, count); break;
2999 case lir_shr: __ sarptr(value, count); break;
3000 case lir_ushr: __ shrptr(value, count); break;
3001 default: ShouldNotReachHere();
3002 }
3003 #endif // _LP64
3004 } else {
3005 ShouldNotReachHere();
3006 }
3007 }
3008
3009
3010 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3011 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3012 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3013 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3014 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3015 }
3016
3017
3018 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3019 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3020 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3021 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3022 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3023 }
3024
3025
3026 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3027 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3028 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3029 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3030 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1);
3031 }
3032
3033
3034 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3035 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3036 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3037 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3038 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1);
3039 }
3040
3041
3042 // This code replaces a call to arraycopy; no exception may
3043 // be thrown in this code, they must be thrown in the System.arraycopy
3044 // activation frame; we could save some checks if this would not be the case
3045 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3046 ciArrayKlass* default_type = op->expected_type();
3047 Register src = op->src()->as_register();
3048 Register dst = op->dst()->as_register();
3049 Register src_pos = op->src_pos()->as_register();
3050 Register dst_pos = op->dst_pos()->as_register();
3051 Register length = op->length()->as_register();
3052 Register tmp = op->tmp()->as_register();
3053 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3054 Register tmp2 = UseCompactObjectHeaders ? rscratch2 : noreg;
3055
3056 CodeStub* stub = op->stub();
3057 int flags = op->flags();
3058 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
3059 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3060
3061 // if we don't know anything, just go through the generic arraycopy
3062 if (default_type == nullptr) {
3063 // save outgoing arguments on stack in case call to System.arraycopy is needed
3064 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3065 // for interpreter calling conventions. Now we have to do it in new style conventions.
3066 // For the moment until C1 gets the new register allocator I just force all the
3067 // args to the right place (except the register args) and then on the back side
3068 // reload the register args properly if we go slow path. Yuck
3069
3070 // These are proper for the calling convention
3071 store_parameter(length, 2);
3072 store_parameter(dst_pos, 1);
3073 store_parameter(dst, 0);
3074
3075 // these are just temporary placements until we need to reload
3076 store_parameter(src_pos, 3);
3077 store_parameter(src, 4);
3078 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3079
3080 address copyfunc_addr = StubRoutines::generic_arraycopy();
3081 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
3082
3083 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3084 #ifdef _LP64
3085 // The arguments are in java calling convention so we can trivially shift them to C
3086 // convention
3087 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3088 __ mov(c_rarg0, j_rarg0);
3089 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3090 __ mov(c_rarg1, j_rarg1);
3091 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3092 __ mov(c_rarg2, j_rarg2);
3093 assert_different_registers(c_rarg3, j_rarg4);
3094 __ mov(c_rarg3, j_rarg3);
3095 #ifdef _WIN64
3096 // Allocate abi space for args but be sure to keep stack aligned
3097 __ subptr(rsp, 6*wordSize);
3098 store_parameter(j_rarg4, 4);
3099 #ifndef PRODUCT
3100 if (PrintC1Statistics) {
3101 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3102 }
3103 #endif
3104 __ call(RuntimeAddress(copyfunc_addr));
3105 __ addptr(rsp, 6*wordSize);
3106 #else
3107 __ mov(c_rarg4, j_rarg4);
3108 #ifndef PRODUCT
3109 if (PrintC1Statistics) {
3110 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3111 }
3112 #endif
3113 __ call(RuntimeAddress(copyfunc_addr));
3114 #endif // _WIN64
3115 #else
3116 __ push(length);
3117 __ push(dst_pos);
3118 __ push(dst);
3119 __ push(src_pos);
3120 __ push(src);
3121
3122 #ifndef PRODUCT
3123 if (PrintC1Statistics) {
3124 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3125 }
3126 #endif
3127 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3128
3129 #endif // _LP64
3130
3131 __ testl(rax, rax);
3132 __ jcc(Assembler::equal, *stub->continuation());
3133
3134 __ mov(tmp, rax);
3135 __ xorl(tmp, -1);
3136
3137 // Reload values from the stack so they are where the stub
3138 // expects them.
3139 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3140 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3141 __ movptr (length, Address(rsp, 2*BytesPerWord));
3142 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3143 __ movptr (src, Address(rsp, 4*BytesPerWord));
3144
3145 __ subl(length, tmp);
3146 __ addl(src_pos, tmp);
3147 __ addl(dst_pos, tmp);
3148 __ jmp(*stub->entry());
3149
3150 __ bind(*stub->continuation());
3151 return;
3152 }
3153
3154 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3155
3156 int elem_size = type2aelembytes(basic_type);
3157 Address::ScaleFactor scale;
3158
3159 switch (elem_size) {
3160 case 1 :
3161 scale = Address::times_1;
3162 break;
3163 case 2 :
3164 scale = Address::times_2;
3165 break;
3166 case 4 :
3167 scale = Address::times_4;
3168 break;
3169 case 8 :
3170 scale = Address::times_8;
3171 break;
3172 default:
3173 scale = Address::no_scale;
3174 ShouldNotReachHere();
3175 }
3176
3177 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3178 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3179
3180 // length and pos's are all sign extended at this point on 64bit
3181
3182 // test for null
3183 if (flags & LIR_OpArrayCopy::src_null_check) {
3184 __ testptr(src, src);
3185 __ jcc(Assembler::zero, *stub->entry());
3186 }
3187 if (flags & LIR_OpArrayCopy::dst_null_check) {
3188 __ testptr(dst, dst);
3189 __ jcc(Assembler::zero, *stub->entry());
3190 }
3191
3192 // If the compiler was not able to prove that exact type of the source or the destination
3193 // of the arraycopy is an array type, check at runtime if the source or the destination is
3194 // an instance type.
3195 if (flags & LIR_OpArrayCopy::type_check) {
3196 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3197 __ load_klass(tmp, dst, tmp_load_klass);
3198 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3199 __ jcc(Assembler::greaterEqual, *stub->entry());
3200 }
3201
3202 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3203 __ load_klass(tmp, src, tmp_load_klass);
3204 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3205 __ jcc(Assembler::greaterEqual, *stub->entry());
3206 }
3207 }
3208
3209 // check if negative
3210 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3211 __ testl(src_pos, src_pos);
3212 __ jcc(Assembler::less, *stub->entry());
3213 }
3214 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3215 __ testl(dst_pos, dst_pos);
3216 __ jcc(Assembler::less, *stub->entry());
3217 }
3218
3219 if (flags & LIR_OpArrayCopy::src_range_check) {
3220 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3221 __ cmpl(tmp, src_length_addr);
3222 __ jcc(Assembler::above, *stub->entry());
3223 }
3224 if (flags & LIR_OpArrayCopy::dst_range_check) {
3225 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3226 __ cmpl(tmp, dst_length_addr);
3227 __ jcc(Assembler::above, *stub->entry());
3228 }
3229
3230 if (flags & LIR_OpArrayCopy::length_positive_check) {
3231 __ testl(length, length);
3232 __ jcc(Assembler::less, *stub->entry());
3233 }
3234
3235 #ifdef _LP64
3236 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3237 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3238 #endif
3239
3240 if (flags & LIR_OpArrayCopy::type_check) {
3241 // We don't know the array types are compatible
3242 if (basic_type != T_OBJECT) {
3243 // Simple test for basic type arrays
3244 __ cmp_klasses_from_objects(src, dst, tmp, tmp2);
3245 __ jcc(Assembler::notEqual, *stub->entry());
3246 } else {
3247 // For object arrays, if src is a sub class of dst then we can
3248 // safely do the copy.
3249 Label cont, slow;
3250
3251 __ push(src);
3252 __ push(dst);
3253
3254 __ load_klass(src, src, tmp_load_klass);
3255 __ load_klass(dst, dst, tmp_load_klass);
3256
3257 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
3258
3259 __ push(src);
3260 __ push(dst);
3261 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
3262 __ pop(dst);
3263 __ pop(src);
3264
3265 __ testl(src, src);
3266 __ jcc(Assembler::notEqual, cont);
3267
3268 __ bind(slow);
3269 __ pop(dst);
3270 __ pop(src);
3271
3272 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3273 if (copyfunc_addr != nullptr) { // use stub if available
3274 // src is not a sub class of dst so we have to do a
3275 // per-element check.
3276
3277 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3278 if ((flags & mask) != mask) {
3279 // Check that at least both of them object arrays.
3280 assert(flags & mask, "one of the two should be known to be an object array");
3281
3282 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3283 __ load_klass(tmp, src, tmp_load_klass);
3284 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3285 __ load_klass(tmp, dst, tmp_load_klass);
3286 }
3287 int lh_offset = in_bytes(Klass::layout_helper_offset());
3288 Address klass_lh_addr(tmp, lh_offset);
3289 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3290 __ cmpl(klass_lh_addr, objArray_lh);
3291 __ jcc(Assembler::notEqual, *stub->entry());
3292 }
3293
3294 // Spill because stubs can use any register they like and it's
3295 // easier to restore just those that we care about.
3296 store_parameter(dst, 0);
3297 store_parameter(dst_pos, 1);
3298 store_parameter(length, 2);
3299 store_parameter(src_pos, 3);
3300 store_parameter(src, 4);
3301
3302 #ifndef _LP64
3303 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3304 __ movptr(tmp, dst_klass_addr);
3305 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3306 __ push(tmp);
3307 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3308 __ push(tmp);
3309 __ push(length);
3310 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3311 __ push(tmp);
3312 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3313 __ push(tmp);
3314
3315 __ call_VM_leaf(copyfunc_addr, 5);
3316 #else
3317 __ movl2ptr(length, length); //higher 32bits must be null
3318
3319 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3320 assert_different_registers(c_rarg0, dst, dst_pos, length);
3321 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3322 assert_different_registers(c_rarg1, dst, length);
3323
3324 __ mov(c_rarg2, length);
3325 assert_different_registers(c_rarg2, dst);
3326
3327 #ifdef _WIN64
3328 // Allocate abi space for args but be sure to keep stack aligned
3329 __ subptr(rsp, 6*wordSize);
3330 __ load_klass(c_rarg3, dst, tmp_load_klass);
3331 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3332 store_parameter(c_rarg3, 4);
3333 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3334 __ call(RuntimeAddress(copyfunc_addr));
3335 __ addptr(rsp, 6*wordSize);
3336 #else
3337 __ load_klass(c_rarg4, dst, tmp_load_klass);
3338 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3339 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3340 __ call(RuntimeAddress(copyfunc_addr));
3341 #endif
3342
3343 #endif
3344
3345 #ifndef PRODUCT
3346 if (PrintC1Statistics) {
3347 Label failed;
3348 __ testl(rax, rax);
3349 __ jcc(Assembler::notZero, failed);
3350 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1);
3351 __ bind(failed);
3352 }
3353 #endif
3354
3355 __ testl(rax, rax);
3356 __ jcc(Assembler::zero, *stub->continuation());
3357
3358 #ifndef PRODUCT
3359 if (PrintC1Statistics) {
3360 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1);
3361 }
3362 #endif
3363
3364 __ mov(tmp, rax);
3365
3366 __ xorl(tmp, -1);
3367
3368 // Restore previously spilled arguments
3369 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3370 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3371 __ movptr (length, Address(rsp, 2*BytesPerWord));
3372 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3373 __ movptr (src, Address(rsp, 4*BytesPerWord));
3374
3375
3376 __ subl(length, tmp);
3377 __ addl(src_pos, tmp);
3378 __ addl(dst_pos, tmp);
3379 }
3380
3381 __ jmp(*stub->entry());
3382
3383 __ bind(cont);
3384 __ pop(dst);
3385 __ pop(src);
3386 }
3387 }
3388
3389 #ifdef ASSERT
3390 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3391 // Sanity check the known type with the incoming class. For the
3392 // primitive case the types must match exactly with src.klass and
3393 // dst.klass each exactly matching the default type. For the
3394 // object array case, if no type check is needed then either the
3395 // dst type is exactly the expected type and the src type is a
3396 // subtype which we can't check or src is the same array as dst
3397 // but not necessarily exactly of type default_type.
3398 Label known_ok, halt;
3399 __ mov_metadata(tmp, default_type->constant_encoding());
3400 #ifdef _LP64
3401 if (UseCompressedClassPointers) {
3402 __ encode_klass_not_null(tmp, rscratch1);
3403 }
3404 #endif
3405
3406 if (basic_type != T_OBJECT) {
3407 __ cmp_klass(tmp, dst, tmp2);
3408 __ jcc(Assembler::notEqual, halt);
3409 __ cmp_klass(tmp, src, tmp2);
3410 __ jcc(Assembler::equal, known_ok);
3411 } else {
3412 __ cmp_klass(tmp, dst, tmp2);
3413 __ jcc(Assembler::equal, known_ok);
3414 __ cmpptr(src, dst);
3415 __ jcc(Assembler::equal, known_ok);
3416 }
3417 __ bind(halt);
3418 __ stop("incorrect type information in arraycopy");
3419 __ bind(known_ok);
3420 }
3421 #endif
3422
3423 #ifndef PRODUCT
3424 if (PrintC1Statistics) {
3425 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1);
3426 }
3427 #endif
3428
3429 #ifdef _LP64
3430 assert_different_registers(c_rarg0, dst, dst_pos, length);
3431 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3432 assert_different_registers(c_rarg1, length);
3433 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3434 __ mov(c_rarg2, length);
3435
3436 #else
3437 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3438 store_parameter(tmp, 0);
3439 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3440 store_parameter(tmp, 1);
3441 store_parameter(length, 2);
3442 #endif // _LP64
3443
3444 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3445 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3446 const char *name;
3447 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3448 __ call_VM_leaf(entry, 0);
3449
3450 if (stub != nullptr) {
3451 __ bind(*stub->continuation());
3452 }
3453 }
3454
3455 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3456 assert(op->crc()->is_single_cpu(), "crc must be register");
3457 assert(op->val()->is_single_cpu(), "byte value must be register");
3458 assert(op->result_opr()->is_single_cpu(), "result must be register");
3459 Register crc = op->crc()->as_register();
3460 Register val = op->val()->as_register();
3461 Register res = op->result_opr()->as_register();
3462
3463 assert_different_registers(val, crc, res);
3464
3465 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3466 __ notl(crc); // ~crc
3467 __ update_byte_crc32(crc, val, res);
3468 __ notl(crc); // ~crc
3469 __ mov(res, crc);
3470 }
3471
3472 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3473 Register obj = op->obj_opr()->as_register(); // may not be an oop
3474 Register hdr = op->hdr_opr()->as_register();
3475 Register lock = op->lock_opr()->as_register();
3476 if (LockingMode == LM_MONITOR) {
3477 if (op->info() != nullptr) {
3478 add_debug_info_for_null_check_here(op->info());
3479 __ null_check(obj);
3480 }
3481 __ jmp(*op->stub()->entry());
3482 } else if (op->code() == lir_lock) {
3483 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3484 Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg;
3485 // add debug info for NullPointerException only if one is possible
3486 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
3487 if (op->info() != nullptr) {
3488 add_debug_info_for_null_check(null_check_offset, op->info());
3489 }
3490 // done
3491 } else if (op->code() == lir_unlock) {
3492 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3493 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3494 } else {
3495 Unimplemented();
3496 }
3497 __ bind(*op->stub()->continuation());
3498 }
3499
3500 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
3501 Register obj = op->obj()->as_pointer_register();
3502 Register result = op->result_opr()->as_pointer_register();
3503
3504 CodeEmitInfo* info = op->info();
3505 if (info != nullptr) {
3506 add_debug_info_for_null_check_here(info);
3507 }
3508
3509 __ load_klass(result, obj, rscratch1);
3510 }
3511
3512 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3513 ciMethod* method = op->profiled_method();
3514 int bci = op->profiled_bci();
3515 ciMethod* callee = op->profiled_callee();
3516 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3517
3518 // Update counter for all call types
3519 ciMethodData* md = method->method_data_or_null();
3520 assert(md != nullptr, "Sanity");
3521 ciProfileData* data = md->bci_to_data(bci);
3522 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
3523 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3524 Register mdo = op->mdo()->as_register();
3525 __ mov_metadata(mdo, md->constant_encoding());
3526 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3527 // Perform additional virtual call profiling for invokevirtual and
3528 // invokeinterface bytecodes
3529 if (op->should_profile_receiver_type()) {
3530 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3531 Register recv = op->recv()->as_register();
3532 assert_different_registers(mdo, recv);
3533 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3534 ciKlass* known_klass = op->known_holder();
3535 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
3536 // We know the type that will be seen at this call site; we can
3537 // statically update the MethodData* rather than needing to do
3538 // dynamic tests on the receiver type
3539
3540 // NOTE: we should probably put a lock around this search to
3541 // avoid collisions by concurrent compilations
3542 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3543 uint i;
3544 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3545 ciKlass* receiver = vc_data->receiver(i);
3546 if (known_klass->equals(receiver)) {
3547 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3548 __ addptr(data_addr, DataLayout::counter_increment);
3549 return;
3550 }
3551 }
3552
3553 // Receiver type not found in profile data; select an empty slot
3554
3555 // Note that this is less efficient than it should be because it
3556 // always does a write to the receiver part of the
3557 // VirtualCallData rather than just the first time
3558 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3559 ciKlass* receiver = vc_data->receiver(i);
3560 if (receiver == nullptr) {
3561 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3562 __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1);
3563 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3564 __ addptr(data_addr, DataLayout::counter_increment);
3565 return;
3566 }
3567 }
3568 } else {
3569 __ load_klass(recv, recv, tmp_load_klass);
3570 Label update_done;
3571 type_profile_helper(mdo, md, data, recv, &update_done);
3572 // Receiver did not match any saved receiver and there is no empty row for it.
3573 // Increment total counter to indicate polymorphic case.
3574 __ addptr(counter_addr, DataLayout::counter_increment);
3575
3576 __ bind(update_done);
3577 }
3578 } else {
3579 // Static call
3580 __ addptr(counter_addr, DataLayout::counter_increment);
3581 }
3582 }
3583
3584 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3585 Register obj = op->obj()->as_register();
3586 Register tmp = op->tmp()->as_pointer_register();
3587 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3588 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3589 ciKlass* exact_klass = op->exact_klass();
3590 intptr_t current_klass = op->current_klass();
3591 bool not_null = op->not_null();
3592 bool no_conflict = op->no_conflict();
3593
3594 Label update, next, none;
3595
3596 bool do_null = !not_null;
3597 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3598 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3599
3600 assert(do_null || do_update, "why are we here?");
3601 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3602
3603 __ verify_oop(obj);
3604
3605 #ifdef ASSERT
3606 if (obj == tmp) {
3607 #ifdef _LP64
3608 assert_different_registers(obj, rscratch1, mdo_addr.base(), mdo_addr.index());
3609 #else
3610 assert_different_registers(obj, mdo_addr.base(), mdo_addr.index());
3611 #endif
3612 } else {
3613 #ifdef _LP64
3614 assert_different_registers(obj, tmp, rscratch1, mdo_addr.base(), mdo_addr.index());
3615 #else
3616 assert_different_registers(obj, tmp, mdo_addr.base(), mdo_addr.index());
3617 #endif
3618 }
3619 #endif
3620 if (do_null) {
3621 __ testptr(obj, obj);
3622 __ jccb(Assembler::notZero, update);
3623 if (!TypeEntries::was_null_seen(current_klass)) {
3624 __ testptr(mdo_addr, TypeEntries::null_seen);
3625 #ifndef ASSERT
3626 __ jccb(Assembler::notZero, next); // already set
3627 #else
3628 __ jcc(Assembler::notZero, next); // already set
3629 #endif
3630 // atomic update to prevent overwriting Klass* with 0
3631 __ lock();
3632 __ orptr(mdo_addr, TypeEntries::null_seen);
3633 }
3634 if (do_update) {
3635 #ifndef ASSERT
3636 __ jmpb(next);
3637 }
3638 #else
3639 __ jmp(next);
3640 }
3641 } else {
3642 __ testptr(obj, obj);
3643 __ jcc(Assembler::notZero, update);
3644 __ stop("unexpected null obj");
3645 #endif
3646 }
3647
3648 __ bind(update);
3649
3650 if (do_update) {
3651 #ifdef ASSERT
3652 if (exact_klass != nullptr) {
3653 Label ok;
3654 __ load_klass(tmp, obj, tmp_load_klass);
3655 __ push(tmp);
3656 __ mov_metadata(tmp, exact_klass->constant_encoding());
3657 __ cmpptr(tmp, Address(rsp, 0));
3658 __ jcc(Assembler::equal, ok);
3659 __ stop("exact klass and actual klass differ");
3660 __ bind(ok);
3661 __ pop(tmp);
3662 }
3663 #endif
3664 if (!no_conflict) {
3665 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3666 if (exact_klass != nullptr) {
3667 __ mov_metadata(tmp, exact_klass->constant_encoding());
3668 } else {
3669 __ load_klass(tmp, obj, tmp_load_klass);
3670 }
3671 #ifdef _LP64
3672 __ mov(rscratch1, tmp); // save original value before XOR
3673 #endif
3674 __ xorptr(tmp, mdo_addr);
3675 __ testptr(tmp, TypeEntries::type_klass_mask);
3676 // klass seen before, nothing to do. The unknown bit may have been
3677 // set already but no need to check.
3678 __ jccb(Assembler::zero, next);
3679
3680 __ testptr(tmp, TypeEntries::type_unknown);
3681 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3682
3683 if (TypeEntries::is_type_none(current_klass)) {
3684 __ testptr(mdo_addr, TypeEntries::type_mask);
3685 __ jccb(Assembler::zero, none);
3686 #ifdef _LP64
3687 // There is a chance that the checks above (re-reading profiling
3688 // data from memory) fail if another thread has just set the
3689 // profiling to this obj's klass
3690 __ mov(tmp, rscratch1); // get back original value before XOR
3691 __ xorptr(tmp, mdo_addr);
3692 __ testptr(tmp, TypeEntries::type_klass_mask);
3693 __ jccb(Assembler::zero, next);
3694 #endif
3695 }
3696 } else {
3697 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3698 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3699
3700 __ testptr(mdo_addr, TypeEntries::type_unknown);
3701 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3702 }
3703
3704 // different than before. Cannot keep accurate profile.
3705 __ orptr(mdo_addr, TypeEntries::type_unknown);
3706
3707 if (TypeEntries::is_type_none(current_klass)) {
3708 __ jmpb(next);
3709
3710 __ bind(none);
3711 // first time here. Set profile type.
3712 __ movptr(mdo_addr, tmp);
3713 #ifdef ASSERT
3714 __ andptr(tmp, TypeEntries::type_klass_mask);
3715 __ verify_klass_ptr(tmp);
3716 #endif
3717 }
3718 } else {
3719 // There's a single possible klass at this profile point
3720 assert(exact_klass != nullptr, "should be");
3721 if (TypeEntries::is_type_none(current_klass)) {
3722 __ mov_metadata(tmp, exact_klass->constant_encoding());
3723 __ xorptr(tmp, mdo_addr);
3724 __ testptr(tmp, TypeEntries::type_klass_mask);
3725 #ifdef ASSERT
3726 __ jcc(Assembler::zero, next);
3727
3728 {
3729 Label ok;
3730 __ push(tmp);
3731 __ testptr(mdo_addr, TypeEntries::type_mask);
3732 __ jcc(Assembler::zero, ok);
3733 // may have been set by another thread
3734 __ mov_metadata(tmp, exact_klass->constant_encoding());
3735 __ xorptr(tmp, mdo_addr);
3736 __ testptr(tmp, TypeEntries::type_mask);
3737 __ jcc(Assembler::zero, ok);
3738
3739 __ stop("unexpected profiling mismatch");
3740 __ bind(ok);
3741 __ pop(tmp);
3742 }
3743 #else
3744 __ jccb(Assembler::zero, next);
3745 #endif
3746 // first time here. Set profile type.
3747 __ movptr(mdo_addr, tmp);
3748 #ifdef ASSERT
3749 __ andptr(tmp, TypeEntries::type_klass_mask);
3750 __ verify_klass_ptr(tmp);
3751 #endif
3752 } else {
3753 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3754 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3755
3756 __ testptr(mdo_addr, TypeEntries::type_unknown);
3757 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3758
3759 __ orptr(mdo_addr, TypeEntries::type_unknown);
3760 }
3761 }
3762 }
3763 __ bind(next);
3764 }
3765
3766 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3767 Unimplemented();
3768 }
3769
3770
3771 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3772 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3773 }
3774
3775
3776 void LIR_Assembler::align_backward_branch_target() {
3777 __ align(BytesPerWord);
3778 }
3779
3780
3781 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3782 if (left->is_single_cpu()) {
3783 __ negl(left->as_register());
3784 move_regs(left->as_register(), dest->as_register());
3785
3786 } else if (left->is_double_cpu()) {
3787 Register lo = left->as_register_lo();
3788 #ifdef _LP64
3789 Register dst = dest->as_register_lo();
3790 __ movptr(dst, lo);
3791 __ negptr(dst);
3792 #else
3793 Register hi = left->as_register_hi();
3794 __ lneg(hi, lo);
3795 if (dest->as_register_lo() == hi) {
3796 assert(dest->as_register_hi() != lo, "destroying register");
3797 move_regs(hi, dest->as_register_hi());
3798 move_regs(lo, dest->as_register_lo());
3799 } else {
3800 move_regs(lo, dest->as_register_lo());
3801 move_regs(hi, dest->as_register_hi());
3802 }
3803 #endif // _LP64
3804
3805 } else if (dest->is_single_xmm()) {
3806 assert(!tmp->is_valid(), "do not need temporary");
3807 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3808 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3809 }
3810 __ xorps(dest->as_xmm_float_reg(),
3811 ExternalAddress((address)float_signflip_pool),
3812 rscratch1);
3813 } else if (dest->is_double_xmm()) {
3814 assert(!tmp->is_valid(), "do not need temporary");
3815 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3816 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3817 }
3818 __ xorpd(dest->as_xmm_double_reg(),
3819 ExternalAddress((address)double_signflip_pool),
3820 rscratch1);
3821 #ifndef _LP64
3822 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3823 assert(left->fpu() == 0, "arg must be on TOS");
3824 assert(dest->fpu() == 0, "dest must be TOS");
3825 __ fchs();
3826 #endif // !_LP64
3827
3828 } else {
3829 ShouldNotReachHere();
3830 }
3831 }
3832
3833
3834 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3835 assert(src->is_address(), "must be an address");
3836 assert(dest->is_register(), "must be a register");
3837
3838 PatchingStub* patch = nullptr;
3839 if (patch_code != lir_patch_none) {
3840 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3841 }
3842
3843 Register reg = dest->as_pointer_register();
3844 LIR_Address* addr = src->as_address_ptr();
3845 __ lea(reg, as_Address(addr));
3846
3847 if (patch != nullptr) {
3848 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3849 }
3850 }
3851
3852
3853
3854 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3855 assert(!tmp->is_valid(), "don't need temporary");
3856 __ call(RuntimeAddress(dest));
3857 if (info != nullptr) {
3858 add_call_info_here(info);
3859 }
3860 __ post_call_nop();
3861 }
3862
3863
3864 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3865 assert(type == T_LONG, "only for volatile long fields");
3866
3867 if (info != nullptr) {
3868 add_debug_info_for_null_check_here(info);
3869 }
3870
3871 if (src->is_double_xmm()) {
3872 if (dest->is_double_cpu()) {
3873 #ifdef _LP64
3874 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3875 #else
3876 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3877 __ psrlq(src->as_xmm_double_reg(), 32);
3878 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3879 #endif // _LP64
3880 } else if (dest->is_double_stack()) {
3881 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3882 } else if (dest->is_address()) {
3883 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3884 } else {
3885 ShouldNotReachHere();
3886 }
3887
3888 } else if (dest->is_double_xmm()) {
3889 if (src->is_double_stack()) {
3890 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3891 } else if (src->is_address()) {
3892 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3893 } else {
3894 ShouldNotReachHere();
3895 }
3896
3897 #ifndef _LP64
3898 } else if (src->is_double_fpu()) {
3899 assert(src->fpu_regnrLo() == 0, "must be TOS");
3900 if (dest->is_double_stack()) {
3901 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3902 } else if (dest->is_address()) {
3903 __ fistp_d(as_Address(dest->as_address_ptr()));
3904 } else {
3905 ShouldNotReachHere();
3906 }
3907
3908 } else if (dest->is_double_fpu()) {
3909 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3910 if (src->is_double_stack()) {
3911 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3912 } else if (src->is_address()) {
3913 __ fild_d(as_Address(src->as_address_ptr()));
3914 } else {
3915 ShouldNotReachHere();
3916 }
3917 #endif // !_LP64
3918
3919 } else {
3920 ShouldNotReachHere();
3921 }
3922 }
3923
3924 #ifdef ASSERT
3925 // emit run-time assertion
3926 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3927 assert(op->code() == lir_assert, "must be");
3928
3929 if (op->in_opr1()->is_valid()) {
3930 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3931 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3932 } else {
3933 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3934 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3935 }
3936
3937 Label ok;
3938 if (op->condition() != lir_cond_always) {
3939 Assembler::Condition acond = Assembler::zero;
3940 switch (op->condition()) {
3941 case lir_cond_equal: acond = Assembler::equal; break;
3942 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3943 case lir_cond_less: acond = Assembler::less; break;
3944 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3945 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3946 case lir_cond_greater: acond = Assembler::greater; break;
3947 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3948 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3949 default: ShouldNotReachHere();
3950 }
3951 __ jcc(acond, ok);
3952 }
3953 if (op->halt()) {
3954 const char* str = __ code_string(op->msg());
3955 __ stop(str);
3956 } else {
3957 breakpoint();
3958 }
3959 __ bind(ok);
3960 }
3961 #endif
3962
3963 void LIR_Assembler::membar() {
3964 // QQQ sparc TSO uses this,
3965 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3966 }
3967
3968 void LIR_Assembler::membar_acquire() {
3969 // No x86 machines currently require load fences
3970 }
3971
3972 void LIR_Assembler::membar_release() {
3973 // No x86 machines currently require store fences
3974 }
3975
3976 void LIR_Assembler::membar_loadload() {
3977 // no-op
3978 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3979 }
3980
3981 void LIR_Assembler::membar_storestore() {
3982 // no-op
3983 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3984 }
3985
3986 void LIR_Assembler::membar_loadstore() {
3987 // no-op
3988 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3989 }
3990
3991 void LIR_Assembler::membar_storeload() {
3992 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3993 }
3994
3995 void LIR_Assembler::on_spin_wait() {
3996 __ pause ();
3997 }
3998
3999 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4000 assert(result_reg->is_register(), "check");
4001 #ifdef _LP64
4002 // __ get_thread(result_reg->as_register_lo());
4003 __ mov(result_reg->as_register(), r15_thread);
4004 #else
4005 __ get_thread(result_reg->as_register());
4006 #endif // _LP64
4007 }
4008
4009
4010 void LIR_Assembler::peephole(LIR_List*) {
4011 // do nothing for now
4012 }
4013
4014 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4015 assert(data == dest, "xchg/xadd uses only 2 operands");
4016
4017 if (data->type() == T_INT) {
4018 if (code == lir_xadd) {
4019 __ lock();
4020 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4021 } else {
4022 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4023 }
4024 } else if (data->is_oop()) {
4025 assert (code == lir_xchg, "xadd for oops");
4026 Register obj = data->as_register();
4027 #ifdef _LP64
4028 if (UseCompressedOops) {
4029 __ encode_heap_oop(obj);
4030 __ xchgl(obj, as_Address(src->as_address_ptr()));
4031 __ decode_heap_oop(obj);
4032 } else {
4033 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4034 }
4035 #else
4036 __ xchgl(obj, as_Address(src->as_address_ptr()));
4037 #endif
4038 } else if (data->type() == T_LONG) {
4039 #ifdef _LP64
4040 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4041 if (code == lir_xadd) {
4042 __ lock();
4043 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4044 } else {
4045 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4046 }
4047 #else
4048 ShouldNotReachHere();
4049 #endif
4050 } else {
4051 ShouldNotReachHere();
4052 }
4053 }
4054
4055 #undef __