1 /*
   2  * Copyright (c) 2000, 2023, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "c1/c1_CodeStubs.hpp"
  29 #include "c1/c1_Compilation.hpp"
  30 #include "c1/c1_LIRAssembler.hpp"
  31 #include "c1/c1_MacroAssembler.hpp"
  32 #include "c1/c1_Runtime1.hpp"
  33 #include "c1/c1_ValueStack.hpp"
  34 #include "ci/ciArrayKlass.hpp"
  35 #include "ci/ciInstance.hpp"
  36 #include "ci/ciUtilities.hpp"
  37 #include "code/SCCache.hpp"
  38 #include "compiler/oopMap.hpp"
  39 #include "gc/shared/collectedHeap.hpp"
  40 #include "gc/shared/gc_globals.hpp"
  41 #include "nativeInst_x86.hpp"
  42 #include "oops/objArrayKlass.hpp"
  43 #include "runtime/frame.inline.hpp"
  44 #include "runtime/safepointMechanism.hpp"
  45 #include "runtime/sharedRuntime.hpp"
  46 #include "runtime/stubRoutines.hpp"
  47 #include "utilities/powerOfTwo.hpp"
  48 #include "vmreg_x86.inline.hpp"
  49 
  50 
  51 // These masks are used to provide 128-bit aligned bitmasks to the XMM
  52 // instructions, to allow sign-masking or sign-bit flipping.  They allow
  53 // fast versions of NegF/NegD and AbsF/AbsD.
  54 
  55 // Note: 'double' and 'long long' have 32-bits alignment on x86.
  56 static address double_quadword(jlong *adr, jlong lo, jlong hi) {
  57   // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
  58   // of 128-bits operands for SSE instructions.
  59   jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
  60   // Store the value to a 128-bits operand.
  61   operand[0] = lo;
  62   operand[1] = hi;
  63   return (address)operand;
  64 }
  65 
  66 // Buffer for 128-bits masks used by SSE instructions.
  67 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
  68 
  69 // Static initialization during VM startup.
  70 address LIR_Assembler::float_signmask_pool  = double_quadword(&fp_signmask_pool[1*2],         CONST64(0x7FFFFFFF7FFFFFFF),         CONST64(0x7FFFFFFF7FFFFFFF));
  71 address LIR_Assembler::double_signmask_pool = double_quadword(&fp_signmask_pool[2*2],         CONST64(0x7FFFFFFFFFFFFFFF),         CONST64(0x7FFFFFFFFFFFFFFF));
  72 address LIR_Assembler::float_signflip_pool  = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
  73 address LIR_Assembler::double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
  74 
  75 
  76 NEEDS_CLEANUP // remove this definitions ?
  77 const Register IC_Klass    = rax;   // where the IC klass is cached
  78 const Register SYNC_header = rax;   // synchronization header
  79 const Register SHIFT_count = rcx;   // where count for shift operations must be
  80 
  81 #define __ _masm->
  82 
  83 
  84 static void select_different_registers(Register preserve,
  85                                        Register extra,
  86                                        Register &tmp1,
  87                                        Register &tmp2) {
  88   if (tmp1 == preserve) {
  89     assert_different_registers(tmp1, tmp2, extra);
  90     tmp1 = extra;
  91   } else if (tmp2 == preserve) {
  92     assert_different_registers(tmp1, tmp2, extra);
  93     tmp2 = extra;
  94   }
  95   assert_different_registers(preserve, tmp1, tmp2);
  96 }
  97 
  98 
  99 
 100 static void select_different_registers(Register preserve,
 101                                        Register extra,
 102                                        Register &tmp1,
 103                                        Register &tmp2,
 104                                        Register &tmp3) {
 105   if (tmp1 == preserve) {
 106     assert_different_registers(tmp1, tmp2, tmp3, extra);
 107     tmp1 = extra;
 108   } else if (tmp2 == preserve) {
 109     assert_different_registers(tmp1, tmp2, tmp3, extra);
 110     tmp2 = extra;
 111   } else if (tmp3 == preserve) {
 112     assert_different_registers(tmp1, tmp2, tmp3, extra);
 113     tmp3 = extra;
 114   }
 115   assert_different_registers(preserve, tmp1, tmp2, tmp3);
 116 }
 117 
 118 
 119 
 120 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
 121   if (opr->is_constant()) {
 122     LIR_Const* constant = opr->as_constant_ptr();
 123     switch (constant->type()) {
 124       case T_INT: {
 125         return true;
 126       }
 127 
 128       default:
 129         return false;
 130     }
 131   }
 132   return false;
 133 }
 134 
 135 
 136 LIR_Opr LIR_Assembler::receiverOpr() {
 137   return FrameMap::receiver_opr;
 138 }
 139 
 140 LIR_Opr LIR_Assembler::osrBufferPointer() {
 141   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 142 }
 143 
 144 //--------------fpu register translations-----------------------
 145 
 146 
 147 address LIR_Assembler::float_constant(float f) {
 148   address const_addr = __ float_constant(f);
 149   if (const_addr == nullptr) {
 150     bailout("const section overflow");
 151     return __ code()->consts()->start();
 152   } else {
 153     return const_addr;
 154   }
 155 }
 156 
 157 
 158 address LIR_Assembler::double_constant(double d) {
 159   address const_addr = __ double_constant(d);
 160   if (const_addr == nullptr) {
 161     bailout("const section overflow");
 162     return __ code()->consts()->start();
 163   } else {
 164     return const_addr;
 165   }
 166 }
 167 
 168 #ifndef _LP64
 169 void LIR_Assembler::fpop() {
 170   __ fpop();
 171 }
 172 
 173 void LIR_Assembler::fxch(int i) {
 174   __ fxch(i);
 175 }
 176 
 177 void LIR_Assembler::fld(int i) {
 178   __ fld_s(i);
 179 }
 180 
 181 void LIR_Assembler::ffree(int i) {
 182   __ ffree(i);
 183 }
 184 #endif // !_LP64
 185 
 186 void LIR_Assembler::breakpoint() {
 187   __ int3();
 188 }
 189 
 190 void LIR_Assembler::push(LIR_Opr opr) {
 191   if (opr->is_single_cpu()) {
 192     __ push_reg(opr->as_register());
 193   } else if (opr->is_double_cpu()) {
 194     NOT_LP64(__ push_reg(opr->as_register_hi()));
 195     __ push_reg(opr->as_register_lo());
 196   } else if (opr->is_stack()) {
 197     __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
 198   } else if (opr->is_constant()) {
 199     LIR_Const* const_opr = opr->as_constant_ptr();
 200     if (const_opr->type() == T_OBJECT) {
 201       __ push_oop(const_opr->as_jobject(), rscratch1);
 202     } else if (const_opr->type() == T_INT) {
 203       __ push_jint(const_opr->as_jint());
 204     } else {
 205       ShouldNotReachHere();
 206     }
 207 
 208   } else {
 209     ShouldNotReachHere();
 210   }
 211 }
 212 
 213 void LIR_Assembler::pop(LIR_Opr opr) {
 214   if (opr->is_single_cpu()) {
 215     __ pop_reg(opr->as_register());
 216   } else {
 217     ShouldNotReachHere();
 218   }
 219 }
 220 
 221 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
 222   return addr->base()->is_illegal() && addr->index()->is_illegal();
 223 }
 224 
 225 //-------------------------------------------
 226 
 227 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 228   return as_Address(addr, rscratch1);
 229 }
 230 
 231 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 232   if (addr->base()->is_illegal()) {
 233     assert(addr->index()->is_illegal(), "must be illegal too");
 234     AddressLiteral laddr((address)addr->disp(), relocInfo::none);
 235     if (! __ reachable(laddr)) {
 236       __ movptr(tmp, laddr.addr());
 237       Address res(tmp, 0);
 238       return res;
 239     } else {
 240       return __ as_Address(laddr);
 241     }
 242   }
 243 
 244   Register base = addr->base()->as_pointer_register();
 245 
 246   if (addr->index()->is_illegal()) {
 247     return Address( base, addr->disp());
 248   } else if (addr->index()->is_cpu_register()) {
 249     Register index = addr->index()->as_pointer_register();
 250     return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
 251   } else if (addr->index()->is_constant()) {
 252     intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
 253     assert(Assembler::is_simm32(addr_offset), "must be");
 254 
 255     return Address(base, addr_offset);
 256   } else {
 257     Unimplemented();
 258     return Address();
 259   }
 260 }
 261 
 262 
 263 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 264   Address base = as_Address(addr);
 265   return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
 266 }
 267 
 268 
 269 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 270   return as_Address(addr);
 271 }
 272 
 273 
 274 void LIR_Assembler::osr_entry() {
 275   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 276   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 277   ValueStack* entry_state = osr_entry->state();
 278   int number_of_locks = entry_state->locks_size();
 279 
 280   // we jump here if osr happens with the interpreter
 281   // state set up to continue at the beginning of the
 282   // loop that triggered osr - in particular, we have
 283   // the following registers setup:
 284   //
 285   // rcx: osr buffer
 286   //
 287 
 288   // build frame
 289   ciMethod* m = compilation()->method();
 290   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 291 
 292   // OSR buffer is
 293   //
 294   // locals[nlocals-1..0]
 295   // monitors[0..number_of_locks]
 296   //
 297   // locals is a direct copy of the interpreter frame so in the osr buffer
 298   // so first slot in the local array is the last local from the interpreter
 299   // and last slot is local[0] (receiver) from the interpreter
 300   //
 301   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 302   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 303   // in the interpreter frame (the method lock if a sync method)
 304 
 305   // Initialize monitors in the compiled activation.
 306   //   rcx: pointer to osr buffer
 307   //
 308   // All other registers are dead at this point and the locals will be
 309   // copied into place by code emitted in the IR.
 310 
 311   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 312   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 313     int monitor_offset = BytesPerWord * method()->max_locals() +
 314       (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
 315     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 316     // the OSR buffer using 2 word entries: first the lock and then
 317     // the oop.
 318     for (int i = 0; i < number_of_locks; i++) {
 319       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 320 #ifdef ASSERT
 321       // verify the interpreter's monitor has a non-null object
 322       {
 323         Label L;
 324         __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD);
 325         __ jcc(Assembler::notZero, L);
 326         __ stop("locked object is null");
 327         __ bind(L);
 328       }
 329 #endif
 330       __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
 331       __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
 332       __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 333       __ movptr(frame_map()->address_for_monitor_object(i), rbx);
 334     }
 335   }
 336 }
 337 
 338 
 339 // inline cache check; done before the frame is built.
 340 int LIR_Assembler::check_icache() {
 341   Register receiver = FrameMap::receiver_opr->as_register();
 342   Register ic_klass = IC_Klass;
 343   const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
 344   const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
 345   if (!do_post_padding) {
 346     // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
 347     __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
 348   }
 349   int offset = __ offset();
 350   __ inline_cache_check(receiver, IC_Klass);
 351   assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
 352   if (do_post_padding) {
 353     // force alignment after the cache check.
 354     // It's been verified to be aligned if !VerifyOops
 355     __ align(CodeEntryAlignment);
 356   }
 357   return offset;
 358 }
 359 
 360 void LIR_Assembler::clinit_barrier(ciMethod* method) {
 361   assert(VM_Version::supports_fast_class_init_checks(), "sanity");
 362   assert(!method->holder()->is_not_initialized(), "initialization should have been started");
 363 
 364   Label L_skip_barrier;
 365   Register klass = rscratch1;
 366   Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
 367   assert(thread != noreg, "x86_32 not implemented");
 368 
 369   __ mov_metadata(klass, method->holder()->constant_encoding());
 370   __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
 371 
 372   __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
 373 
 374   __ bind(L_skip_barrier);
 375 }
 376 
 377 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
 378   jobject o = nullptr;
 379   PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
 380   __ movoop(reg, o);
 381   patching_epilog(patch, lir_patch_normal, reg, info);
 382 }
 383 
 384 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 385   Metadata* o = nullptr;
 386   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
 387   __ mov_metadata(reg, o);
 388   patching_epilog(patch, lir_patch_normal, reg, info);
 389 }
 390 
 391 // This specifies the rsp decrement needed to build the frame
 392 int LIR_Assembler::initial_frame_size_in_bytes() const {
 393   // if rounding, must let FrameMap know!
 394 
 395   // The frame_map records size in slots (32bit word)
 396 
 397   // subtract two words to account for return address and link
 398   return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word))  * VMRegImpl::stack_slot_size;
 399 }
 400 
 401 
 402 int LIR_Assembler::emit_exception_handler() {
 403   // generate code for exception handler
 404   address handler_base = __ start_a_stub(exception_handler_size());
 405   if (handler_base == nullptr) {
 406     // not enough space left for the handler
 407     bailout("exception handler overflow");
 408     return -1;
 409   }
 410 
 411   int offset = code_offset();
 412 
 413   // the exception oop and pc are in rax, and rdx
 414   // no other registers need to be preserved, so invalidate them
 415   __ invalidate_registers(false, true, true, false, true, true);
 416 
 417   // check that there is really an exception
 418   __ verify_not_null_oop(rax);
 419 
 420   // search an exception handler (rax: exception oop, rdx: throwing pc)
 421   __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
 422   __ should_not_reach_here();
 423   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 424   __ end_a_stub();
 425 
 426   return offset;
 427 }
 428 
 429 
 430 // Emit the code to remove the frame from the stack in the exception
 431 // unwind path.
 432 int LIR_Assembler::emit_unwind_handler() {
 433 #ifndef PRODUCT
 434   if (CommentedAssembly) {
 435     _masm->block_comment("Unwind handler");
 436   }
 437 #endif
 438 
 439   int offset = code_offset();
 440 
 441   // Fetch the exception from TLS and clear out exception related thread state
 442   Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
 443   NOT_LP64(__ get_thread(thread));
 444   __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
 445   __ movptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
 446   __ movptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
 447 
 448   __ bind(_unwind_handler_entry);
 449   __ verify_not_null_oop(rax);
 450   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 451     __ mov(rbx, rax);  // Preserve the exception (rbx is always callee-saved)
 452   }
 453 
 454   // Perform needed unlocking
 455   MonitorExitStub* stub = nullptr;
 456   if (method()->is_synchronized()) {
 457     monitor_address(0, FrameMap::rax_opr);
 458     stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
 459     if (LockingMode == LM_MONITOR) {
 460       __ jmp(*stub->entry());
 461     } else {
 462       __ unlock_object(rdi, rsi, rax, *stub->entry());
 463     }
 464     __ bind(*stub->continuation());
 465   }
 466 
 467   if (compilation()->env()->dtrace_method_probes()) {
 468 #ifdef _LP64
 469     __ mov(rdi, r15_thread);
 470     __ mov_metadata(rsi, method()->constant_encoding());
 471 #else
 472     __ get_thread(rax);
 473     __ movptr(Address(rsp, 0), rax);
 474     __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding(), noreg);
 475 #endif
 476     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
 477   }
 478 
 479   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 480     __ mov(rax, rbx);  // Restore the exception
 481   }
 482 
 483   // remove the activation and dispatch to the unwind handler
 484   __ remove_frame(initial_frame_size_in_bytes());
 485   __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 486 
 487   // Emit the slow path assembly
 488   if (stub != nullptr) {
 489     stub->emit_code(this);
 490   }
 491 
 492   return offset;
 493 }
 494 
 495 
 496 int LIR_Assembler::emit_deopt_handler() {
 497   // generate code for exception handler
 498   address handler_base = __ start_a_stub(deopt_handler_size());
 499   if (handler_base == nullptr) {
 500     // not enough space left for the handler
 501     bailout("deopt handler overflow");
 502     return -1;
 503   }
 504 
 505   int offset = code_offset();
 506   InternalAddress here(__ pc());
 507 
 508   __ pushptr(here.addr(), rscratch1);
 509   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 510   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 511   __ end_a_stub();
 512 
 513   return offset;
 514 }
 515 
 516 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
 517   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
 518   if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
 519     assert(result->fpu() == 0, "result must already be on TOS");
 520   }
 521 
 522   // Pop the stack before the safepoint code
 523   __ remove_frame(initial_frame_size_in_bytes());
 524 
 525   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 526     __ reserved_stack_check();
 527   }
 528 
 529   // Note: we do not need to round double result; float result has the right precision
 530   // the poll sets the condition code, but no data registers
 531 
 532 #ifdef _LP64
 533   const Register thread = r15_thread;
 534 #else
 535   const Register thread = rbx;
 536   __ get_thread(thread);
 537 #endif
 538   code_stub->set_safepoint_offset(__ offset());
 539   __ relocate(relocInfo::poll_return_type);
 540   __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */);
 541   __ ret(0);
 542 }
 543 
 544 
 545 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 546   guarantee(info != nullptr, "Shouldn't be null");
 547   int offset = __ offset();
 548 #ifdef _LP64
 549   const Register poll_addr = rscratch1;
 550   __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
 551 #else
 552   assert(tmp->is_cpu_register(), "needed");
 553   const Register poll_addr = tmp->as_register();
 554   __ get_thread(poll_addr);
 555   __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset())));
 556 #endif
 557   add_debug_info_for_branch(info);
 558   __ relocate(relocInfo::poll_type);
 559   address pre_pc = __ pc();
 560   __ testl(rax, Address(poll_addr, 0));
 561   address post_pc = __ pc();
 562   guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
 563   return offset;
 564 }
 565 
 566 
 567 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 568   if (from_reg != to_reg) __ mov(to_reg, from_reg);
 569 }
 570 
 571 void LIR_Assembler::swap_reg(Register a, Register b) {
 572   __ xchgptr(a, b);
 573 }
 574 
 575 
 576 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 577   assert(src->is_constant(), "should not call otherwise");
 578   assert(dest->is_register(), "should not call otherwise");
 579   LIR_Const* c = src->as_constant_ptr();
 580 
 581   switch (c->type()) {
 582     case T_INT: {
 583       assert(patch_code == lir_patch_none, "no patching handled here");
 584       __ movl(dest->as_register(), c->as_jint());
 585       break;
 586     }
 587 
 588     case T_ADDRESS: {
 589       assert(patch_code == lir_patch_none, "no patching handled here");
 590       __ movptr(dest->as_register(), c->as_jint());
 591       break;
 592     }
 593 
 594     case T_LONG: {
 595       assert(patch_code == lir_patch_none, "no patching handled here");
 596 #ifdef _LP64
 597       if (SCCache::is_on_for_write()) {
 598         // SCA needs relocation info for card table base
 599         address b = c->as_pointer();
 600         if (is_card_table_address(b)) {
 601           __ lea(dest->as_register_lo(), ExternalAddress(b));
 602           break;
 603         }
 604       }
 605       __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
 606 #else
 607       __ movptr(dest->as_register_lo(), c->as_jint_lo());
 608       __ movptr(dest->as_register_hi(), c->as_jint_hi());
 609 #endif // _LP64
 610       break;
 611     }
 612 
 613     case T_OBJECT: {
 614       if (patch_code != lir_patch_none) {
 615         jobject2reg_with_patching(dest->as_register(), info);
 616       } else {
 617         __ movoop(dest->as_register(), c->as_jobject());
 618       }
 619       break;
 620     }
 621 
 622     case T_METADATA: {
 623       if (patch_code != lir_patch_none) {
 624         klass2reg_with_patching(dest->as_register(), info);
 625       } else {
 626         __ mov_metadata(dest->as_register(), c->as_metadata());
 627       }
 628       break;
 629     }
 630 
 631     case T_FLOAT: {
 632       if (dest->is_single_xmm()) {
 633         if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
 634           __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
 635         } else {
 636           __ movflt(dest->as_xmm_float_reg(),
 637                    InternalAddress(float_constant(c->as_jfloat())));
 638         }
 639       } else {
 640 #ifndef _LP64
 641         assert(dest->is_single_fpu(), "must be");
 642         assert(dest->fpu_regnr() == 0, "dest must be TOS");
 643         if (c->is_zero_float()) {
 644           __ fldz();
 645         } else if (c->is_one_float()) {
 646           __ fld1();
 647         } else {
 648           __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
 649         }
 650 #else
 651         ShouldNotReachHere();
 652 #endif // !_LP64
 653       }
 654       break;
 655     }
 656 
 657     case T_DOUBLE: {
 658       if (dest->is_double_xmm()) {
 659         if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
 660           __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
 661         } else {
 662           __ movdbl(dest->as_xmm_double_reg(),
 663                     InternalAddress(double_constant(c->as_jdouble())));
 664         }
 665       } else {
 666 #ifndef _LP64
 667         assert(dest->is_double_fpu(), "must be");
 668         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
 669         if (c->is_zero_double()) {
 670           __ fldz();
 671         } else if (c->is_one_double()) {
 672           __ fld1();
 673         } else {
 674           __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
 675         }
 676 #else
 677         ShouldNotReachHere();
 678 #endif // !_LP64
 679       }
 680       break;
 681     }
 682 
 683     default:
 684       ShouldNotReachHere();
 685   }
 686 }
 687 
 688 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 689   assert(src->is_constant(), "should not call otherwise");
 690   assert(dest->is_stack(), "should not call otherwise");
 691   LIR_Const* c = src->as_constant_ptr();
 692 
 693   switch (c->type()) {
 694     case T_INT:  // fall through
 695     case T_FLOAT:
 696       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 697       break;
 698 
 699     case T_ADDRESS:
 700       __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 701       break;
 702 
 703     case T_OBJECT:
 704       __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1);
 705       break;
 706 
 707     case T_LONG:  // fall through
 708     case T_DOUBLE:
 709 #ifdef _LP64
 710       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 711                                               lo_word_offset_in_bytes),
 712                 (intptr_t)c->as_jlong_bits(),
 713                 rscratch1);
 714 #else
 715       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 716                                               lo_word_offset_in_bytes), c->as_jint_lo_bits());
 717       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 718                                               hi_word_offset_in_bytes), c->as_jint_hi_bits());
 719 #endif // _LP64
 720       break;
 721 
 722     default:
 723       ShouldNotReachHere();
 724   }
 725 }
 726 
 727 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 728   assert(src->is_constant(), "should not call otherwise");
 729   assert(dest->is_address(), "should not call otherwise");
 730   LIR_Const* c = src->as_constant_ptr();
 731   LIR_Address* addr = dest->as_address_ptr();
 732 
 733   int null_check_here = code_offset();
 734   switch (type) {
 735     case T_INT:    // fall through
 736     case T_FLOAT:
 737       __ movl(as_Address(addr), c->as_jint_bits());
 738       break;
 739 
 740     case T_ADDRESS:
 741       __ movptr(as_Address(addr), c->as_jint_bits());
 742       break;
 743 
 744     case T_OBJECT:  // fall through
 745     case T_ARRAY:
 746       if (c->as_jobject() == nullptr) {
 747         if (UseCompressedOops && !wide) {
 748           __ movl(as_Address(addr), NULL_WORD);
 749         } else {
 750 #ifdef _LP64
 751           __ xorptr(rscratch1, rscratch1);
 752           null_check_here = code_offset();
 753           __ movptr(as_Address(addr), rscratch1);
 754 #else
 755           __ movptr(as_Address(addr), NULL_WORD);
 756 #endif
 757         }
 758       } else {
 759         if (is_literal_address(addr)) {
 760           ShouldNotReachHere();
 761           __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1);
 762         } else {
 763 #ifdef _LP64
 764           __ movoop(rscratch1, c->as_jobject());
 765           if (UseCompressedOops && !wide) {
 766             __ encode_heap_oop(rscratch1);
 767             null_check_here = code_offset();
 768             __ movl(as_Address_lo(addr), rscratch1);
 769           } else {
 770             null_check_here = code_offset();
 771             __ movptr(as_Address_lo(addr), rscratch1);
 772           }
 773 #else
 774           __ movoop(as_Address(addr), c->as_jobject(), noreg);
 775 #endif
 776         }
 777       }
 778       break;
 779 
 780     case T_LONG:    // fall through
 781     case T_DOUBLE:
 782 #ifdef _LP64
 783       if (is_literal_address(addr)) {
 784         ShouldNotReachHere();
 785         __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
 786       } else {
 787         __ movptr(r10, (intptr_t)c->as_jlong_bits());
 788         null_check_here = code_offset();
 789         __ movptr(as_Address_lo(addr), r10);
 790       }
 791 #else
 792       // Always reachable in 32bit so this doesn't produce useless move literal
 793       __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
 794       __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
 795 #endif // _LP64
 796       break;
 797 
 798     case T_BOOLEAN: // fall through
 799     case T_BYTE:
 800       __ movb(as_Address(addr), c->as_jint() & 0xFF);
 801       break;
 802 
 803     case T_CHAR:    // fall through
 804     case T_SHORT:
 805       __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
 806       break;
 807 
 808     default:
 809       ShouldNotReachHere();
 810   };
 811 
 812   if (info != nullptr) {
 813     add_debug_info_for_null_check(null_check_here, info);
 814   }
 815 }
 816 
 817 
 818 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 819   assert(src->is_register(), "should not call otherwise");
 820   assert(dest->is_register(), "should not call otherwise");
 821 
 822   // move between cpu-registers
 823   if (dest->is_single_cpu()) {
 824 #ifdef _LP64
 825     if (src->type() == T_LONG) {
 826       // Can do LONG -> OBJECT
 827       move_regs(src->as_register_lo(), dest->as_register());
 828       return;
 829     }
 830 #endif
 831     assert(src->is_single_cpu(), "must match");
 832     if (src->type() == T_OBJECT) {
 833       __ verify_oop(src->as_register());
 834     }
 835     move_regs(src->as_register(), dest->as_register());
 836 
 837   } else if (dest->is_double_cpu()) {
 838 #ifdef _LP64
 839     if (is_reference_type(src->type())) {
 840       // Surprising to me but we can see move of a long to t_object
 841       __ verify_oop(src->as_register());
 842       move_regs(src->as_register(), dest->as_register_lo());
 843       return;
 844     }
 845 #endif
 846     assert(src->is_double_cpu(), "must match");
 847     Register f_lo = src->as_register_lo();
 848     Register f_hi = src->as_register_hi();
 849     Register t_lo = dest->as_register_lo();
 850     Register t_hi = dest->as_register_hi();
 851 #ifdef _LP64
 852     assert(f_hi == f_lo, "must be same");
 853     assert(t_hi == t_lo, "must be same");
 854     move_regs(f_lo, t_lo);
 855 #else
 856     assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
 857 
 858 
 859     if (f_lo == t_hi && f_hi == t_lo) {
 860       swap_reg(f_lo, f_hi);
 861     } else if (f_hi == t_lo) {
 862       assert(f_lo != t_hi, "overwriting register");
 863       move_regs(f_hi, t_hi);
 864       move_regs(f_lo, t_lo);
 865     } else {
 866       assert(f_hi != t_lo, "overwriting register");
 867       move_regs(f_lo, t_lo);
 868       move_regs(f_hi, t_hi);
 869     }
 870 #endif // LP64
 871 
 872 #ifndef _LP64
 873     // special moves from fpu-register to xmm-register
 874     // necessary for method results
 875   } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
 876     __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
 877     __ fld_s(Address(rsp, 0));
 878   } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
 879     __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
 880     __ fld_d(Address(rsp, 0));
 881   } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
 882     __ fstp_s(Address(rsp, 0));
 883     __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
 884   } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
 885     __ fstp_d(Address(rsp, 0));
 886     __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
 887 #endif // !_LP64
 888 
 889     // move between xmm-registers
 890   } else if (dest->is_single_xmm()) {
 891     assert(src->is_single_xmm(), "must match");
 892     __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
 893   } else if (dest->is_double_xmm()) {
 894     assert(src->is_double_xmm(), "must match");
 895     __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
 896 
 897 #ifndef _LP64
 898     // move between fpu-registers (no instruction necessary because of fpu-stack)
 899   } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
 900     assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
 901     assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
 902 #endif // !_LP64
 903 
 904   } else {
 905     ShouldNotReachHere();
 906   }
 907 }
 908 
 909 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 910   assert(src->is_register(), "should not call otherwise");
 911   assert(dest->is_stack(), "should not call otherwise");
 912 
 913   if (src->is_single_cpu()) {
 914     Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
 915     if (is_reference_type(type)) {
 916       __ verify_oop(src->as_register());
 917       __ movptr (dst, src->as_register());
 918     } else if (type == T_METADATA || type == T_ADDRESS) {
 919       __ movptr (dst, src->as_register());
 920     } else {
 921       __ movl (dst, src->as_register());
 922     }
 923 
 924   } else if (src->is_double_cpu()) {
 925     Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
 926     Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
 927     __ movptr (dstLO, src->as_register_lo());
 928     NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
 929 
 930   } else if (src->is_single_xmm()) {
 931     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 932     __ movflt(dst_addr, src->as_xmm_float_reg());
 933 
 934   } else if (src->is_double_xmm()) {
 935     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 936     __ movdbl(dst_addr, src->as_xmm_double_reg());
 937 
 938 #ifndef _LP64
 939   } else if (src->is_single_fpu()) {
 940     assert(src->fpu_regnr() == 0, "argument must be on TOS");
 941     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 942     if (pop_fpu_stack)     __ fstp_s (dst_addr);
 943     else                   __ fst_s  (dst_addr);
 944 
 945   } else if (src->is_double_fpu()) {
 946     assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
 947     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 948     if (pop_fpu_stack)     __ fstp_d (dst_addr);
 949     else                   __ fst_d  (dst_addr);
 950 #endif // !_LP64
 951 
 952   } else {
 953     ShouldNotReachHere();
 954   }
 955 }
 956 
 957 
 958 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
 959   LIR_Address* to_addr = dest->as_address_ptr();
 960   PatchingStub* patch = nullptr;
 961   Register compressed_src = rscratch1;
 962 
 963   if (is_reference_type(type)) {
 964     __ verify_oop(src->as_register());
 965 #ifdef _LP64
 966     if (UseCompressedOops && !wide) {
 967       __ movptr(compressed_src, src->as_register());
 968       __ encode_heap_oop(compressed_src);
 969       if (patch_code != lir_patch_none) {
 970         info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
 971       }
 972     }
 973 #endif
 974   }
 975 
 976   if (patch_code != lir_patch_none) {
 977     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 978     Address toa = as_Address(to_addr);
 979     assert(toa.disp() != 0, "must have");
 980   }
 981 
 982   int null_check_here = code_offset();
 983   switch (type) {
 984     case T_FLOAT: {
 985 #ifdef _LP64
 986       assert(src->is_single_xmm(), "not a float");
 987       __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
 988 #else
 989       if (src->is_single_xmm()) {
 990         __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
 991       } else {
 992         assert(src->is_single_fpu(), "must be");
 993         assert(src->fpu_regnr() == 0, "argument must be on TOS");
 994         if (pop_fpu_stack)      __ fstp_s(as_Address(to_addr));
 995         else                    __ fst_s (as_Address(to_addr));
 996       }
 997 #endif // _LP64
 998       break;
 999     }
1000 
1001     case T_DOUBLE: {
1002 #ifdef _LP64
1003       assert(src->is_double_xmm(), "not a double");
1004       __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1005 #else
1006       if (src->is_double_xmm()) {
1007         __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1008       } else {
1009         assert(src->is_double_fpu(), "must be");
1010         assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1011         if (pop_fpu_stack)      __ fstp_d(as_Address(to_addr));
1012         else                    __ fst_d (as_Address(to_addr));
1013       }
1014 #endif // _LP64
1015       break;
1016     }
1017 
1018     case T_ARRAY:   // fall through
1019     case T_OBJECT:  // fall through
1020       if (UseCompressedOops && !wide) {
1021         __ movl(as_Address(to_addr), compressed_src);
1022       } else {
1023         __ movptr(as_Address(to_addr), src->as_register());
1024       }
1025       break;
1026     case T_METADATA:
1027       // We get here to store a method pointer to the stack to pass to
1028       // a dtrace runtime call. This can't work on 64 bit with
1029       // compressed klass ptrs: T_METADATA can be a compressed klass
1030       // ptr or a 64 bit method pointer.
1031       LP64_ONLY(ShouldNotReachHere());
1032       __ movptr(as_Address(to_addr), src->as_register());
1033       break;
1034     case T_ADDRESS:
1035       __ movptr(as_Address(to_addr), src->as_register());
1036       break;
1037     case T_INT:
1038       __ movl(as_Address(to_addr), src->as_register());
1039       break;
1040 
1041     case T_LONG: {
1042       Register from_lo = src->as_register_lo();
1043       Register from_hi = src->as_register_hi();
1044 #ifdef _LP64
1045       __ movptr(as_Address_lo(to_addr), from_lo);
1046 #else
1047       Register base = to_addr->base()->as_register();
1048       Register index = noreg;
1049       if (to_addr->index()->is_register()) {
1050         index = to_addr->index()->as_register();
1051       }
1052       if (base == from_lo || index == from_lo) {
1053         assert(base != from_hi, "can't be");
1054         assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1055         __ movl(as_Address_hi(to_addr), from_hi);
1056         if (patch != nullptr) {
1057           patching_epilog(patch, lir_patch_high, base, info);
1058           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1059           patch_code = lir_patch_low;
1060         }
1061         __ movl(as_Address_lo(to_addr), from_lo);
1062       } else {
1063         assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1064         __ movl(as_Address_lo(to_addr), from_lo);
1065         if (patch != nullptr) {
1066           patching_epilog(patch, lir_patch_low, base, info);
1067           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1068           patch_code = lir_patch_high;
1069         }
1070         __ movl(as_Address_hi(to_addr), from_hi);
1071       }
1072 #endif // _LP64
1073       break;
1074     }
1075 
1076     case T_BYTE:    // fall through
1077     case T_BOOLEAN: {
1078       Register src_reg = src->as_register();
1079       Address dst_addr = as_Address(to_addr);
1080       assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1081       __ movb(dst_addr, src_reg);
1082       break;
1083     }
1084 
1085     case T_CHAR:    // fall through
1086     case T_SHORT:
1087       __ movw(as_Address(to_addr), src->as_register());
1088       break;
1089 
1090     default:
1091       ShouldNotReachHere();
1092   }
1093   if (info != nullptr) {
1094     add_debug_info_for_null_check(null_check_here, info);
1095   }
1096 
1097   if (patch_code != lir_patch_none) {
1098     patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1099   }
1100 }
1101 
1102 
1103 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1104   assert(src->is_stack(), "should not call otherwise");
1105   assert(dest->is_register(), "should not call otherwise");
1106 
1107   if (dest->is_single_cpu()) {
1108     if (is_reference_type(type)) {
1109       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1110       __ verify_oop(dest->as_register());
1111     } else if (type == T_METADATA || type == T_ADDRESS) {
1112       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1113     } else {
1114       __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1115     }
1116 
1117   } else if (dest->is_double_cpu()) {
1118     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1119     Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1120     __ movptr(dest->as_register_lo(), src_addr_LO);
1121     NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1122 
1123   } else if (dest->is_single_xmm()) {
1124     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1125     __ movflt(dest->as_xmm_float_reg(), src_addr);
1126 
1127   } else if (dest->is_double_xmm()) {
1128     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1129     __ movdbl(dest->as_xmm_double_reg(), src_addr);
1130 
1131 #ifndef _LP64
1132   } else if (dest->is_single_fpu()) {
1133     assert(dest->fpu_regnr() == 0, "dest must be TOS");
1134     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1135     __ fld_s(src_addr);
1136 
1137   } else if (dest->is_double_fpu()) {
1138     assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1139     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1140     __ fld_d(src_addr);
1141 #endif // _LP64
1142 
1143   } else {
1144     ShouldNotReachHere();
1145   }
1146 }
1147 
1148 
1149 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1150   if (src->is_single_stack()) {
1151     if (is_reference_type(type)) {
1152       __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1153       __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1154     } else {
1155 #ifndef _LP64
1156       __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1157       __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1158 #else
1159       //no pushl on 64bits
1160       __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1161       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1162 #endif
1163     }
1164 
1165   } else if (src->is_double_stack()) {
1166 #ifdef _LP64
1167     __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1168     __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1169 #else
1170     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1171     // push and pop the part at src + wordSize, adding wordSize for the previous push
1172     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1173     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1174     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1175 #endif // _LP64
1176 
1177   } else {
1178     ShouldNotReachHere();
1179   }
1180 }
1181 
1182 
1183 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1184   assert(src->is_address(), "should not call otherwise");
1185   assert(dest->is_register(), "should not call otherwise");
1186 
1187   LIR_Address* addr = src->as_address_ptr();
1188   Address from_addr = as_Address(addr);
1189 
1190   if (addr->base()->type() == T_OBJECT) {
1191     __ verify_oop(addr->base()->as_pointer_register());
1192   }
1193 
1194   switch (type) {
1195     case T_BOOLEAN: // fall through
1196     case T_BYTE:    // fall through
1197     case T_CHAR:    // fall through
1198     case T_SHORT:
1199       if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1200         // on pre P6 processors we may get partial register stalls
1201         // so blow away the value of to_rinfo before loading a
1202         // partial word into it.  Do it here so that it precedes
1203         // the potential patch point below.
1204         __ xorptr(dest->as_register(), dest->as_register());
1205       }
1206       break;
1207    default:
1208      break;
1209   }
1210 
1211   PatchingStub* patch = nullptr;
1212   if (patch_code != lir_patch_none) {
1213     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1214     assert(from_addr.disp() != 0, "must have");
1215   }
1216   if (info != nullptr) {
1217     add_debug_info_for_null_check_here(info);
1218   }
1219 
1220   switch (type) {
1221     case T_FLOAT: {
1222       if (dest->is_single_xmm()) {
1223         __ movflt(dest->as_xmm_float_reg(), from_addr);
1224       } else {
1225 #ifndef _LP64
1226         assert(dest->is_single_fpu(), "must be");
1227         assert(dest->fpu_regnr() == 0, "dest must be TOS");
1228         __ fld_s(from_addr);
1229 #else
1230         ShouldNotReachHere();
1231 #endif // !LP64
1232       }
1233       break;
1234     }
1235 
1236     case T_DOUBLE: {
1237       if (dest->is_double_xmm()) {
1238         __ movdbl(dest->as_xmm_double_reg(), from_addr);
1239       } else {
1240 #ifndef _LP64
1241         assert(dest->is_double_fpu(), "must be");
1242         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1243         __ fld_d(from_addr);
1244 #else
1245         ShouldNotReachHere();
1246 #endif // !LP64
1247       }
1248       break;
1249     }
1250 
1251     case T_OBJECT:  // fall through
1252     case T_ARRAY:   // fall through
1253       if (UseCompressedOops && !wide) {
1254         __ movl(dest->as_register(), from_addr);
1255       } else {
1256         __ movptr(dest->as_register(), from_addr);
1257       }
1258       break;
1259 
1260     case T_ADDRESS:
1261       __ movptr(dest->as_register(), from_addr);
1262       break;
1263     case T_INT:
1264       __ movl(dest->as_register(), from_addr);
1265       break;
1266 
1267     case T_LONG: {
1268       Register to_lo = dest->as_register_lo();
1269       Register to_hi = dest->as_register_hi();
1270 #ifdef _LP64
1271       __ movptr(to_lo, as_Address_lo(addr));
1272 #else
1273       Register base = addr->base()->as_register();
1274       Register index = noreg;
1275       if (addr->index()->is_register()) {
1276         index = addr->index()->as_register();
1277       }
1278       if ((base == to_lo && index == to_hi) ||
1279           (base == to_hi && index == to_lo)) {
1280         // addresses with 2 registers are only formed as a result of
1281         // array access so this code will never have to deal with
1282         // patches or null checks.
1283         assert(info == nullptr && patch == nullptr, "must be");
1284         __ lea(to_hi, as_Address(addr));
1285         __ movl(to_lo, Address(to_hi, 0));
1286         __ movl(to_hi, Address(to_hi, BytesPerWord));
1287       } else if (base == to_lo || index == to_lo) {
1288         assert(base != to_hi, "can't be");
1289         assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1290         __ movl(to_hi, as_Address_hi(addr));
1291         if (patch != nullptr) {
1292           patching_epilog(patch, lir_patch_high, base, info);
1293           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1294           patch_code = lir_patch_low;
1295         }
1296         __ movl(to_lo, as_Address_lo(addr));
1297       } else {
1298         assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1299         __ movl(to_lo, as_Address_lo(addr));
1300         if (patch != nullptr) {
1301           patching_epilog(patch, lir_patch_low, base, info);
1302           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1303           patch_code = lir_patch_high;
1304         }
1305         __ movl(to_hi, as_Address_hi(addr));
1306       }
1307 #endif // _LP64
1308       break;
1309     }
1310 
1311     case T_BOOLEAN: // fall through
1312     case T_BYTE: {
1313       Register dest_reg = dest->as_register();
1314       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1315       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1316         __ movsbl(dest_reg, from_addr);
1317       } else {
1318         __ movb(dest_reg, from_addr);
1319         __ shll(dest_reg, 24);
1320         __ sarl(dest_reg, 24);
1321       }
1322       break;
1323     }
1324 
1325     case T_CHAR: {
1326       Register dest_reg = dest->as_register();
1327       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1328       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1329         __ movzwl(dest_reg, from_addr);
1330       } else {
1331         __ movw(dest_reg, from_addr);
1332       }
1333       break;
1334     }
1335 
1336     case T_SHORT: {
1337       Register dest_reg = dest->as_register();
1338       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1339         __ movswl(dest_reg, from_addr);
1340       } else {
1341         __ movw(dest_reg, from_addr);
1342         __ shll(dest_reg, 16);
1343         __ sarl(dest_reg, 16);
1344       }
1345       break;
1346     }
1347 
1348     default:
1349       ShouldNotReachHere();
1350   }
1351 
1352   if (patch != nullptr) {
1353     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1354   }
1355 
1356   if (is_reference_type(type)) {
1357 #ifdef _LP64
1358     if (UseCompressedOops && !wide) {
1359       __ decode_heap_oop(dest->as_register());
1360     }
1361 #endif
1362 
1363     if (!(UseZGC && !ZGenerational)) {
1364       // Load barrier has not yet been applied, so ZGC can't verify the oop here
1365       __ verify_oop(dest->as_register());
1366     }
1367   }
1368 }
1369 
1370 
1371 NEEDS_CLEANUP; // This could be static?
1372 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1373   int elem_size = type2aelembytes(type);
1374   switch (elem_size) {
1375     case 1: return Address::times_1;
1376     case 2: return Address::times_2;
1377     case 4: return Address::times_4;
1378     case 8: return Address::times_8;
1379   }
1380   ShouldNotReachHere();
1381   return Address::no_scale;
1382 }
1383 
1384 
1385 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1386   switch (op->code()) {
1387     case lir_idiv:
1388     case lir_irem:
1389       arithmetic_idiv(op->code(),
1390                       op->in_opr1(),
1391                       op->in_opr2(),
1392                       op->in_opr3(),
1393                       op->result_opr(),
1394                       op->info());
1395       break;
1396     case lir_fmad:
1397       __ fmad(op->result_opr()->as_xmm_double_reg(),
1398               op->in_opr1()->as_xmm_double_reg(),
1399               op->in_opr2()->as_xmm_double_reg(),
1400               op->in_opr3()->as_xmm_double_reg());
1401       break;
1402     case lir_fmaf:
1403       __ fmaf(op->result_opr()->as_xmm_float_reg(),
1404               op->in_opr1()->as_xmm_float_reg(),
1405               op->in_opr2()->as_xmm_float_reg(),
1406               op->in_opr3()->as_xmm_float_reg());
1407       break;
1408     default:      ShouldNotReachHere(); break;
1409   }
1410 }
1411 
1412 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1413 #ifdef ASSERT
1414   assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1415   if (op->block() != nullptr)  _branch_target_blocks.append(op->block());
1416   if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1417 #endif
1418 
1419   if (op->cond() == lir_cond_always) {
1420     if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1421     __ jmp (*(op->label()));
1422   } else {
1423     Assembler::Condition acond = Assembler::zero;
1424     if (op->code() == lir_cond_float_branch) {
1425       assert(op->ublock() != nullptr, "must have unordered successor");
1426       __ jcc(Assembler::parity, *(op->ublock()->label()));
1427       switch(op->cond()) {
1428         case lir_cond_equal:        acond = Assembler::equal;      break;
1429         case lir_cond_notEqual:     acond = Assembler::notEqual;   break;
1430         case lir_cond_less:         acond = Assembler::below;      break;
1431         case lir_cond_lessEqual:    acond = Assembler::belowEqual; break;
1432         case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1433         case lir_cond_greater:      acond = Assembler::above;      break;
1434         default:                         ShouldNotReachHere();
1435       }
1436     } else {
1437       switch (op->cond()) {
1438         case lir_cond_equal:        acond = Assembler::equal;       break;
1439         case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
1440         case lir_cond_less:         acond = Assembler::less;        break;
1441         case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
1442         case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1443         case lir_cond_greater:      acond = Assembler::greater;     break;
1444         case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
1445         case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
1446         default:                         ShouldNotReachHere();
1447       }
1448     }
1449     __ jcc(acond,*(op->label()));
1450   }
1451 }
1452 
1453 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1454   LIR_Opr src  = op->in_opr();
1455   LIR_Opr dest = op->result_opr();
1456 
1457   switch (op->bytecode()) {
1458     case Bytecodes::_i2l:
1459 #ifdef _LP64
1460       __ movl2ptr(dest->as_register_lo(), src->as_register());
1461 #else
1462       move_regs(src->as_register(), dest->as_register_lo());
1463       move_regs(src->as_register(), dest->as_register_hi());
1464       __ sarl(dest->as_register_hi(), 31);
1465 #endif // LP64
1466       break;
1467 
1468     case Bytecodes::_l2i:
1469 #ifdef _LP64
1470       __ movl(dest->as_register(), src->as_register_lo());
1471 #else
1472       move_regs(src->as_register_lo(), dest->as_register());
1473 #endif
1474       break;
1475 
1476     case Bytecodes::_i2b:
1477       move_regs(src->as_register(), dest->as_register());
1478       __ sign_extend_byte(dest->as_register());
1479       break;
1480 
1481     case Bytecodes::_i2c:
1482       move_regs(src->as_register(), dest->as_register());
1483       __ andl(dest->as_register(), 0xFFFF);
1484       break;
1485 
1486     case Bytecodes::_i2s:
1487       move_regs(src->as_register(), dest->as_register());
1488       __ sign_extend_short(dest->as_register());
1489       break;
1490 
1491 
1492 #ifdef _LP64
1493     case Bytecodes::_f2d:
1494       __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1495       break;
1496 
1497     case Bytecodes::_d2f:
1498       __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1499       break;
1500 
1501     case Bytecodes::_i2f:
1502       __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1503       break;
1504 
1505     case Bytecodes::_i2d:
1506       __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1507       break;
1508 
1509     case Bytecodes::_l2f:
1510       __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1511       break;
1512 
1513     case Bytecodes::_l2d:
1514       __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1515       break;
1516 
1517     case Bytecodes::_f2i:
1518       __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1519       break;
1520 
1521     case Bytecodes::_d2i:
1522       __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1523       break;
1524 
1525     case Bytecodes::_f2l:
1526       __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1527       break;
1528 
1529     case Bytecodes::_d2l:
1530       __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1531       break;
1532 #else
1533     case Bytecodes::_f2d:
1534     case Bytecodes::_d2f:
1535       if (dest->is_single_xmm()) {
1536         __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1537       } else if (dest->is_double_xmm()) {
1538         __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1539       } else {
1540         assert(src->fpu() == dest->fpu(), "register must be equal");
1541         // do nothing (float result is rounded later through spilling)
1542       }
1543       break;
1544 
1545     case Bytecodes::_i2f:
1546     case Bytecodes::_i2d:
1547       if (dest->is_single_xmm()) {
1548         __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1549       } else if (dest->is_double_xmm()) {
1550         __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1551       } else {
1552         assert(dest->fpu() == 0, "result must be on TOS");
1553         __ movl(Address(rsp, 0), src->as_register());
1554         __ fild_s(Address(rsp, 0));
1555       }
1556       break;
1557 
1558     case Bytecodes::_l2f:
1559     case Bytecodes::_l2d:
1560       assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1561       assert(dest->fpu() == 0, "result must be on TOS");
1562       __ movptr(Address(rsp, 0),          src->as_register_lo());
1563       __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1564       __ fild_d(Address(rsp, 0));
1565       // float result is rounded later through spilling
1566       break;
1567 
1568     case Bytecodes::_f2i:
1569     case Bytecodes::_d2i:
1570       if (src->is_single_xmm()) {
1571         __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1572       } else if (src->is_double_xmm()) {
1573         __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1574       } else {
1575         assert(src->fpu() == 0, "input must be on TOS");
1576         __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc()));
1577         __ fist_s(Address(rsp, 0));
1578         __ movl(dest->as_register(), Address(rsp, 0));
1579         __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
1580       }
1581       // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1582       assert(op->stub() != nullptr, "stub required");
1583       __ cmpl(dest->as_register(), 0x80000000);
1584       __ jcc(Assembler::equal, *op->stub()->entry());
1585       __ bind(*op->stub()->continuation());
1586       break;
1587 
1588     case Bytecodes::_f2l:
1589     case Bytecodes::_d2l:
1590       assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1591       assert(src->fpu() == 0, "input must be on TOS");
1592       assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1593 
1594       // instruction sequence too long to inline it here
1595       {
1596         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1597       }
1598       break;
1599 #endif // _LP64
1600 
1601     default: ShouldNotReachHere();
1602   }
1603 }
1604 
1605 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1606   if (op->init_check()) {
1607     add_debug_info_for_null_check_here(op->stub()->info());
1608     __ cmpb(Address(op->klass()->as_register(),
1609                     InstanceKlass::init_state_offset()),
1610                     InstanceKlass::fully_initialized);
1611     __ jcc(Assembler::notEqual, *op->stub()->entry());
1612   }
1613   __ allocate_object(op->obj()->as_register(),
1614                      op->tmp1()->as_register(),
1615                      op->tmp2()->as_register(),
1616                      op->header_size(),
1617                      op->object_size(),
1618                      op->klass()->as_register(),
1619                      *op->stub()->entry());
1620   __ bind(*op->stub()->continuation());
1621 }
1622 
1623 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1624   Register len =  op->len()->as_register();
1625   LP64_ONLY( __ movslq(len, len); )
1626 
1627   if (UseSlowPath ||
1628       (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1629       (!UseFastNewTypeArray   && !is_reference_type(op->type()))) {
1630     __ jmp(*op->stub()->entry());
1631   } else {
1632     Register tmp1 = op->tmp1()->as_register();
1633     Register tmp2 = op->tmp2()->as_register();
1634     Register tmp3 = op->tmp3()->as_register();
1635     if (len == tmp1) {
1636       tmp1 = tmp3;
1637     } else if (len == tmp2) {
1638       tmp2 = tmp3;
1639     } else if (len == tmp3) {
1640       // everything is ok
1641     } else {
1642       __ mov(tmp3, len);
1643     }
1644     __ allocate_array(op->obj()->as_register(),
1645                       len,
1646                       tmp1,
1647                       tmp2,
1648                       arrayOopDesc::header_size(op->type()),
1649                       array_element_size(op->type()),
1650                       op->klass()->as_register(),
1651                       *op->stub()->entry());
1652   }
1653   __ bind(*op->stub()->continuation());
1654 }
1655 
1656 void LIR_Assembler::type_profile_helper(Register mdo,
1657                                         ciMethodData *md, ciProfileData *data,
1658                                         Register recv, Label* update_done) {
1659   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1660     Label next_test;
1661     // See if the receiver is receiver[n].
1662     __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1663     __ jccb(Assembler::notEqual, next_test);
1664     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1665     __ addptr(data_addr, DataLayout::counter_increment);
1666     __ jmp(*update_done);
1667     __ bind(next_test);
1668   }
1669 
1670   // Didn't find receiver; find next empty slot and fill it in
1671   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1672     Label next_test;
1673     Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1674     __ cmpptr(recv_addr, NULL_WORD);
1675     __ jccb(Assembler::notEqual, next_test);
1676     __ movptr(recv_addr, recv);
1677     __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1678     __ jmp(*update_done);
1679     __ bind(next_test);
1680   }
1681 }
1682 
1683 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1684   // we always need a stub for the failure case.
1685   CodeStub* stub = op->stub();
1686   Register obj = op->object()->as_register();
1687   Register k_RInfo = op->tmp1()->as_register();
1688   Register klass_RInfo = op->tmp2()->as_register();
1689   Register dst = op->result_opr()->as_register();
1690   ciKlass* k = op->klass();
1691   Register Rtmp1 = noreg;
1692   Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1693 
1694   // check if it needs to be profiled
1695   ciMethodData* md = nullptr;
1696   ciProfileData* data = nullptr;
1697 
1698   if (op->should_profile()) {
1699     ciMethod* method = op->profiled_method();
1700     assert(method != nullptr, "Should have method");
1701     int bci = op->profiled_bci();
1702     md = method->method_data_or_null();
1703     assert(md != nullptr, "Sanity");
1704     data = md->bci_to_data(bci);
1705     assert(data != nullptr,                "need data for type check");
1706     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1707   }
1708   Label* success_target = success;
1709   Label* failure_target = failure;
1710 
1711   if (obj == k_RInfo) {
1712     k_RInfo = dst;
1713   } else if (obj == klass_RInfo) {
1714     klass_RInfo = dst;
1715   }
1716   if (k->is_loaded() && !UseCompressedClassPointers) {
1717     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1718   } else {
1719     Rtmp1 = op->tmp3()->as_register();
1720     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1721   }
1722 
1723   assert_different_registers(obj, k_RInfo, klass_RInfo);
1724 
1725   __ testptr(obj, obj);
1726   if (op->should_profile()) {
1727     Label not_null;
1728     Register mdo  = klass_RInfo;
1729     __ mov_metadata(mdo, md->constant_encoding());
1730     __ jccb(Assembler::notEqual, not_null);
1731     // Object is null; update MDO and exit
1732     Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1733     int header_bits = BitData::null_seen_byte_constant();
1734     __ orb(data_addr, header_bits);
1735     __ jmp(*obj_is_null);
1736     __ bind(not_null);
1737 
1738     Label update_done;
1739     Register recv = k_RInfo;
1740     __ load_klass(recv, obj, tmp_load_klass);
1741     type_profile_helper(mdo, md, data, recv, &update_done);
1742 
1743     Address nonprofiled_receiver_count_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1744     __ addptr(nonprofiled_receiver_count_addr, DataLayout::counter_increment);
1745 
1746     __ bind(update_done);
1747   } else {
1748     __ jcc(Assembler::equal, *obj_is_null);
1749   }
1750 
1751   if (!k->is_loaded()) {
1752     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1753   } else {
1754 #ifdef _LP64
1755     __ mov_metadata(k_RInfo, k->constant_encoding());
1756 #endif // _LP64
1757   }
1758   __ verify_oop(obj);
1759 
1760   if (op->fast_check()) {
1761     // get object class
1762     // not a safepoint as obj null check happens earlier
1763 #ifdef _LP64
1764     if (UseCompressedClassPointers) {
1765       __ load_klass(Rtmp1, obj, tmp_load_klass);
1766       __ cmpptr(k_RInfo, Rtmp1);
1767     } else {
1768       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1769     }
1770 #else
1771     if (k->is_loaded()) {
1772       __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1773     } else {
1774       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1775     }
1776 #endif
1777     __ jcc(Assembler::notEqual, *failure_target);
1778     // successful cast, fall through to profile or jump
1779   } else {
1780     // get object class
1781     // not a safepoint as obj null check happens earlier
1782     __ load_klass(klass_RInfo, obj, tmp_load_klass);
1783     if (k->is_loaded()) {
1784       // See if we get an immediate positive hit
1785 #ifdef _LP64
1786       __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1787 #else
1788       __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1789 #endif // _LP64
1790       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1791         __ jcc(Assembler::notEqual, *failure_target);
1792         // successful cast, fall through to profile or jump
1793       } else {
1794         // See if we get an immediate positive hit
1795         __ jcc(Assembler::equal, *success_target);
1796         // check for self
1797 #ifdef _LP64
1798         __ cmpptr(klass_RInfo, k_RInfo);
1799 #else
1800         __ cmpklass(klass_RInfo, k->constant_encoding());
1801 #endif // _LP64
1802         __ jcc(Assembler::equal, *success_target);
1803 
1804         __ push(klass_RInfo);
1805 #ifdef _LP64
1806         __ push(k_RInfo);
1807 #else
1808         __ pushklass(k->constant_encoding(), noreg);
1809 #endif // _LP64
1810         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1811         __ pop(klass_RInfo);
1812         __ pop(klass_RInfo);
1813         // result is a boolean
1814         __ testl(klass_RInfo, klass_RInfo);
1815         __ jcc(Assembler::equal, *failure_target);
1816         // successful cast, fall through to profile or jump
1817       }
1818     } else {
1819       // perform the fast part of the checking logic
1820       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1821       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1822       __ push(klass_RInfo);
1823       __ push(k_RInfo);
1824       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1825       __ pop(klass_RInfo);
1826       __ pop(k_RInfo);
1827       // result is a boolean
1828       __ testl(k_RInfo, k_RInfo);
1829       __ jcc(Assembler::equal, *failure_target);
1830       // successful cast, fall through to profile or jump
1831     }
1832   }
1833   __ jmp(*success);
1834 }
1835 
1836 
1837 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1838   Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1839   LIR_Code code = op->code();
1840   if (code == lir_store_check) {
1841     Register value = op->object()->as_register();
1842     Register array = op->array()->as_register();
1843     Register k_RInfo = op->tmp1()->as_register();
1844     Register klass_RInfo = op->tmp2()->as_register();
1845     Register Rtmp1 = op->tmp3()->as_register();
1846 
1847     CodeStub* stub = op->stub();
1848 
1849     // check if it needs to be profiled
1850     ciMethodData* md = nullptr;
1851     ciProfileData* data = nullptr;
1852 
1853     if (op->should_profile()) {
1854       ciMethod* method = op->profiled_method();
1855       assert(method != nullptr, "Should have method");
1856       int bci = op->profiled_bci();
1857       md = method->method_data_or_null();
1858       assert(md != nullptr, "Sanity");
1859       data = md->bci_to_data(bci);
1860       assert(data != nullptr,                "need data for type check");
1861       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1862     }
1863     Label done;
1864     Label* success_target = &done;
1865     Label* failure_target = stub->entry();
1866 
1867     __ testptr(value, value);
1868     if (op->should_profile()) {
1869       Label not_null;
1870       Register mdo  = klass_RInfo;
1871       __ mov_metadata(mdo, md->constant_encoding());
1872       __ jccb(Assembler::notEqual, not_null);
1873       // Object is null; update MDO and exit
1874       Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1875       int header_bits = BitData::null_seen_byte_constant();
1876       __ orb(data_addr, header_bits);
1877       __ jmp(done);
1878       __ bind(not_null);
1879 
1880       Label update_done;
1881       Register recv = k_RInfo;
1882       __ load_klass(recv, value, tmp_load_klass);
1883       type_profile_helper(mdo, md, data, recv, &update_done);
1884 
1885       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1886       __ addptr(counter_addr, DataLayout::counter_increment);
1887       __ bind(update_done);
1888     } else {
1889       __ jcc(Assembler::equal, done);
1890     }
1891 
1892     add_debug_info_for_null_check_here(op->info_for_exception());
1893     __ load_klass(k_RInfo, array, tmp_load_klass);
1894     __ load_klass(klass_RInfo, value, tmp_load_klass);
1895 
1896     // get instance klass (it's already uncompressed)
1897     __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1898     // perform the fast part of the checking logic
1899     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1900     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1901     __ push(klass_RInfo);
1902     __ push(k_RInfo);
1903     __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1904     __ pop(klass_RInfo);
1905     __ pop(k_RInfo);
1906     // result is a boolean
1907     __ testl(k_RInfo, k_RInfo);
1908     __ jcc(Assembler::equal, *failure_target);
1909     // fall through to the success case
1910 
1911     __ bind(done);
1912   } else
1913     if (code == lir_checkcast) {
1914       Register obj = op->object()->as_register();
1915       Register dst = op->result_opr()->as_register();
1916       Label success;
1917       emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1918       __ bind(success);
1919       if (dst != obj) {
1920         __ mov(dst, obj);
1921       }
1922     } else
1923       if (code == lir_instanceof) {
1924         Register obj = op->object()->as_register();
1925         Register dst = op->result_opr()->as_register();
1926         Label success, failure, done;
1927         emit_typecheck_helper(op, &success, &failure, &failure);
1928         __ bind(failure);
1929         __ xorptr(dst, dst);
1930         __ jmpb(done);
1931         __ bind(success);
1932         __ movptr(dst, 1);
1933         __ bind(done);
1934       } else {
1935         ShouldNotReachHere();
1936       }
1937 
1938 }
1939 
1940 
1941 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1942   if (LP64_ONLY(false &&) op->code() == lir_cas_long) {
1943     assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1944     assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1945     assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1946     assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1947     Register addr = op->addr()->as_register();
1948     __ lock();
1949     NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1950 
1951   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1952     NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1953     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1954     Register newval = op->new_value()->as_register();
1955     Register cmpval = op->cmp_value()->as_register();
1956     assert(cmpval == rax, "wrong register");
1957     assert(newval != noreg, "new val must be register");
1958     assert(cmpval != newval, "cmp and new values must be in different registers");
1959     assert(cmpval != addr, "cmp and addr must be in different registers");
1960     assert(newval != addr, "new value and addr must be in different registers");
1961 
1962     if ( op->code() == lir_cas_obj) {
1963 #ifdef _LP64
1964       if (UseCompressedOops) {
1965         __ encode_heap_oop(cmpval);
1966         __ mov(rscratch1, newval);
1967         __ encode_heap_oop(rscratch1);
1968         __ lock();
1969         // cmpval (rax) is implicitly used by this instruction
1970         __ cmpxchgl(rscratch1, Address(addr, 0));
1971       } else
1972 #endif
1973       {
1974         __ lock();
1975         __ cmpxchgptr(newval, Address(addr, 0));
1976       }
1977     } else {
1978       assert(op->code() == lir_cas_int, "lir_cas_int expected");
1979       __ lock();
1980       __ cmpxchgl(newval, Address(addr, 0));
1981     }
1982 #ifdef _LP64
1983   } else if (op->code() == lir_cas_long) {
1984     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1985     Register newval = op->new_value()->as_register_lo();
1986     Register cmpval = op->cmp_value()->as_register_lo();
1987     assert(cmpval == rax, "wrong register");
1988     assert(newval != noreg, "new val must be register");
1989     assert(cmpval != newval, "cmp and new values must be in different registers");
1990     assert(cmpval != addr, "cmp and addr must be in different registers");
1991     assert(newval != addr, "new value and addr must be in different registers");
1992     __ lock();
1993     __ cmpxchgq(newval, Address(addr, 0));
1994 #endif // _LP64
1995   } else {
1996     Unimplemented();
1997   }
1998 }
1999 
2000 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
2001                           LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
2002   assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
2003 
2004   Assembler::Condition acond, ncond;
2005   switch (condition) {
2006     case lir_cond_equal:        acond = Assembler::equal;        ncond = Assembler::notEqual;     break;
2007     case lir_cond_notEqual:     acond = Assembler::notEqual;     ncond = Assembler::equal;        break;
2008     case lir_cond_less:         acond = Assembler::less;         ncond = Assembler::greaterEqual; break;
2009     case lir_cond_lessEqual:    acond = Assembler::lessEqual;    ncond = Assembler::greater;      break;
2010     case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less;         break;
2011     case lir_cond_greater:      acond = Assembler::greater;      ncond = Assembler::lessEqual;    break;
2012     case lir_cond_belowEqual:   acond = Assembler::belowEqual;   ncond = Assembler::above;        break;
2013     case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;   ncond = Assembler::below;        break;
2014     default:                    acond = Assembler::equal;        ncond = Assembler::notEqual;
2015                                 ShouldNotReachHere();
2016   }
2017 
2018   if (opr1->is_cpu_register()) {
2019     reg2reg(opr1, result);
2020   } else if (opr1->is_stack()) {
2021     stack2reg(opr1, result, result->type());
2022   } else if (opr1->is_constant()) {
2023     const2reg(opr1, result, lir_patch_none, nullptr);
2024   } else {
2025     ShouldNotReachHere();
2026   }
2027 
2028   if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2029     // optimized version that does not require a branch
2030     if (opr2->is_single_cpu()) {
2031       assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2032       __ cmov(ncond, result->as_register(), opr2->as_register());
2033     } else if (opr2->is_double_cpu()) {
2034       assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2035       assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2036       __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2037       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2038     } else if (opr2->is_single_stack()) {
2039       __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2040     } else if (opr2->is_double_stack()) {
2041       __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2042       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2043     } else {
2044       ShouldNotReachHere();
2045     }
2046 
2047   } else {
2048     Label skip;
2049     __ jccb(acond, skip);
2050     if (opr2->is_cpu_register()) {
2051       reg2reg(opr2, result);
2052     } else if (opr2->is_stack()) {
2053       stack2reg(opr2, result, result->type());
2054     } else if (opr2->is_constant()) {
2055       const2reg(opr2, result, lir_patch_none, nullptr);
2056     } else {
2057       ShouldNotReachHere();
2058     }
2059     __ bind(skip);
2060   }
2061 }
2062 
2063 
2064 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2065   assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2066 
2067   if (left->is_single_cpu()) {
2068     assert(left == dest, "left and dest must be equal");
2069     Register lreg = left->as_register();
2070 
2071     if (right->is_single_cpu()) {
2072       // cpu register - cpu register
2073       Register rreg = right->as_register();
2074       switch (code) {
2075         case lir_add: __ addl (lreg, rreg); break;
2076         case lir_sub: __ subl (lreg, rreg); break;
2077         case lir_mul: __ imull(lreg, rreg); break;
2078         default:      ShouldNotReachHere();
2079       }
2080 
2081     } else if (right->is_stack()) {
2082       // cpu register - stack
2083       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2084       switch (code) {
2085         case lir_add: __ addl(lreg, raddr); break;
2086         case lir_sub: __ subl(lreg, raddr); break;
2087         default:      ShouldNotReachHere();
2088       }
2089 
2090     } else if (right->is_constant()) {
2091       // cpu register - constant
2092       jint c = right->as_constant_ptr()->as_jint();
2093       switch (code) {
2094         case lir_add: {
2095           __ incrementl(lreg, c);
2096           break;
2097         }
2098         case lir_sub: {
2099           __ decrementl(lreg, c);
2100           break;
2101         }
2102         default: ShouldNotReachHere();
2103       }
2104 
2105     } else {
2106       ShouldNotReachHere();
2107     }
2108 
2109   } else if (left->is_double_cpu()) {
2110     assert(left == dest, "left and dest must be equal");
2111     Register lreg_lo = left->as_register_lo();
2112     Register lreg_hi = left->as_register_hi();
2113 
2114     if (right->is_double_cpu()) {
2115       // cpu register - cpu register
2116       Register rreg_lo = right->as_register_lo();
2117       Register rreg_hi = right->as_register_hi();
2118       NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2119       LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2120       switch (code) {
2121         case lir_add:
2122           __ addptr(lreg_lo, rreg_lo);
2123           NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2124           break;
2125         case lir_sub:
2126           __ subptr(lreg_lo, rreg_lo);
2127           NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2128           break;
2129         case lir_mul:
2130 #ifdef _LP64
2131           __ imulq(lreg_lo, rreg_lo);
2132 #else
2133           assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2134           __ imull(lreg_hi, rreg_lo);
2135           __ imull(rreg_hi, lreg_lo);
2136           __ addl (rreg_hi, lreg_hi);
2137           __ mull (rreg_lo);
2138           __ addl (lreg_hi, rreg_hi);
2139 #endif // _LP64
2140           break;
2141         default:
2142           ShouldNotReachHere();
2143       }
2144 
2145     } else if (right->is_constant()) {
2146       // cpu register - constant
2147 #ifdef _LP64
2148       jlong c = right->as_constant_ptr()->as_jlong_bits();
2149       __ movptr(r10, (intptr_t) c);
2150       switch (code) {
2151         case lir_add:
2152           __ addptr(lreg_lo, r10);
2153           break;
2154         case lir_sub:
2155           __ subptr(lreg_lo, r10);
2156           break;
2157         default:
2158           ShouldNotReachHere();
2159       }
2160 #else
2161       jint c_lo = right->as_constant_ptr()->as_jint_lo();
2162       jint c_hi = right->as_constant_ptr()->as_jint_hi();
2163       switch (code) {
2164         case lir_add:
2165           __ addptr(lreg_lo, c_lo);
2166           __ adcl(lreg_hi, c_hi);
2167           break;
2168         case lir_sub:
2169           __ subptr(lreg_lo, c_lo);
2170           __ sbbl(lreg_hi, c_hi);
2171           break;
2172         default:
2173           ShouldNotReachHere();
2174       }
2175 #endif // _LP64
2176 
2177     } else {
2178       ShouldNotReachHere();
2179     }
2180 
2181   } else if (left->is_single_xmm()) {
2182     assert(left == dest, "left and dest must be equal");
2183     XMMRegister lreg = left->as_xmm_float_reg();
2184 
2185     if (right->is_single_xmm()) {
2186       XMMRegister rreg = right->as_xmm_float_reg();
2187       switch (code) {
2188         case lir_add: __ addss(lreg, rreg);  break;
2189         case lir_sub: __ subss(lreg, rreg);  break;
2190         case lir_mul: __ mulss(lreg, rreg);  break;
2191         case lir_div: __ divss(lreg, rreg);  break;
2192         default: ShouldNotReachHere();
2193       }
2194     } else {
2195       Address raddr;
2196       if (right->is_single_stack()) {
2197         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2198       } else if (right->is_constant()) {
2199         // hack for now
2200         raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2201       } else {
2202         ShouldNotReachHere();
2203       }
2204       switch (code) {
2205         case lir_add: __ addss(lreg, raddr);  break;
2206         case lir_sub: __ subss(lreg, raddr);  break;
2207         case lir_mul: __ mulss(lreg, raddr);  break;
2208         case lir_div: __ divss(lreg, raddr);  break;
2209         default: ShouldNotReachHere();
2210       }
2211     }
2212 
2213   } else if (left->is_double_xmm()) {
2214     assert(left == dest, "left and dest must be equal");
2215 
2216     XMMRegister lreg = left->as_xmm_double_reg();
2217     if (right->is_double_xmm()) {
2218       XMMRegister rreg = right->as_xmm_double_reg();
2219       switch (code) {
2220         case lir_add: __ addsd(lreg, rreg);  break;
2221         case lir_sub: __ subsd(lreg, rreg);  break;
2222         case lir_mul: __ mulsd(lreg, rreg);  break;
2223         case lir_div: __ divsd(lreg, rreg);  break;
2224         default: ShouldNotReachHere();
2225       }
2226     } else {
2227       Address raddr;
2228       if (right->is_double_stack()) {
2229         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2230       } else if (right->is_constant()) {
2231         // hack for now
2232         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2233       } else {
2234         ShouldNotReachHere();
2235       }
2236       switch (code) {
2237         case lir_add: __ addsd(lreg, raddr);  break;
2238         case lir_sub: __ subsd(lreg, raddr);  break;
2239         case lir_mul: __ mulsd(lreg, raddr);  break;
2240         case lir_div: __ divsd(lreg, raddr);  break;
2241         default: ShouldNotReachHere();
2242       }
2243     }
2244 
2245 #ifndef _LP64
2246   } else if (left->is_single_fpu()) {
2247     assert(dest->is_single_fpu(),  "fpu stack allocation required");
2248 
2249     if (right->is_single_fpu()) {
2250       arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2251 
2252     } else {
2253       assert(left->fpu_regnr() == 0, "left must be on TOS");
2254       assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2255 
2256       Address raddr;
2257       if (right->is_single_stack()) {
2258         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2259       } else if (right->is_constant()) {
2260         address const_addr = float_constant(right->as_jfloat());
2261         assert(const_addr != nullptr, "incorrect float/double constant maintenance");
2262         // hack for now
2263         raddr = __ as_Address(InternalAddress(const_addr));
2264       } else {
2265         ShouldNotReachHere();
2266       }
2267 
2268       switch (code) {
2269         case lir_add: __ fadd_s(raddr); break;
2270         case lir_sub: __ fsub_s(raddr); break;
2271         case lir_mul: __ fmul_s(raddr); break;
2272         case lir_div: __ fdiv_s(raddr); break;
2273         default:      ShouldNotReachHere();
2274       }
2275     }
2276 
2277   } else if (left->is_double_fpu()) {
2278     assert(dest->is_double_fpu(),  "fpu stack allocation required");
2279 
2280     if (code == lir_mul || code == lir_div) {
2281       // Double values require special handling for strictfp mul/div on x86
2282       __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1()));
2283       __ fmulp(left->fpu_regnrLo() + 1);
2284     }
2285 
2286     if (right->is_double_fpu()) {
2287       arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2288 
2289     } else {
2290       assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2291       assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2292 
2293       Address raddr;
2294       if (right->is_double_stack()) {
2295         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2296       } else if (right->is_constant()) {
2297         // hack for now
2298         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2299       } else {
2300         ShouldNotReachHere();
2301       }
2302 
2303       switch (code) {
2304         case lir_add: __ fadd_d(raddr); break;
2305         case lir_sub: __ fsub_d(raddr); break;
2306         case lir_mul: __ fmul_d(raddr); break;
2307         case lir_div: __ fdiv_d(raddr); break;
2308         default: ShouldNotReachHere();
2309       }
2310     }
2311 
2312     if (code == lir_mul || code == lir_div) {
2313       // Double values require special handling for strictfp mul/div on x86
2314       __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2()));
2315       __ fmulp(dest->fpu_regnrLo() + 1);
2316     }
2317 #endif // !_LP64
2318 
2319   } else if (left->is_single_stack() || left->is_address()) {
2320     assert(left == dest, "left and dest must be equal");
2321 
2322     Address laddr;
2323     if (left->is_single_stack()) {
2324       laddr = frame_map()->address_for_slot(left->single_stack_ix());
2325     } else if (left->is_address()) {
2326       laddr = as_Address(left->as_address_ptr());
2327     } else {
2328       ShouldNotReachHere();
2329     }
2330 
2331     if (right->is_single_cpu()) {
2332       Register rreg = right->as_register();
2333       switch (code) {
2334         case lir_add: __ addl(laddr, rreg); break;
2335         case lir_sub: __ subl(laddr, rreg); break;
2336         default:      ShouldNotReachHere();
2337       }
2338     } else if (right->is_constant()) {
2339       jint c = right->as_constant_ptr()->as_jint();
2340       switch (code) {
2341         case lir_add: {
2342           __ incrementl(laddr, c);
2343           break;
2344         }
2345         case lir_sub: {
2346           __ decrementl(laddr, c);
2347           break;
2348         }
2349         default: ShouldNotReachHere();
2350       }
2351     } else {
2352       ShouldNotReachHere();
2353     }
2354 
2355   } else {
2356     ShouldNotReachHere();
2357   }
2358 }
2359 
2360 #ifndef _LP64
2361 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2362   assert(pop_fpu_stack  || (left_index     == dest_index || right_index     == dest_index), "invalid LIR");
2363   assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2364   assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2365 
2366   bool left_is_tos = (left_index == 0);
2367   bool dest_is_tos = (dest_index == 0);
2368   int non_tos_index = (left_is_tos ? right_index : left_index);
2369 
2370   switch (code) {
2371     case lir_add:
2372       if (pop_fpu_stack)       __ faddp(non_tos_index);
2373       else if (dest_is_tos)    __ fadd (non_tos_index);
2374       else                     __ fadda(non_tos_index);
2375       break;
2376 
2377     case lir_sub:
2378       if (left_is_tos) {
2379         if (pop_fpu_stack)     __ fsubrp(non_tos_index);
2380         else if (dest_is_tos)  __ fsub  (non_tos_index);
2381         else                   __ fsubra(non_tos_index);
2382       } else {
2383         if (pop_fpu_stack)     __ fsubp (non_tos_index);
2384         else if (dest_is_tos)  __ fsubr (non_tos_index);
2385         else                   __ fsuba (non_tos_index);
2386       }
2387       break;
2388 
2389     case lir_mul:
2390       if (pop_fpu_stack)       __ fmulp(non_tos_index);
2391       else if (dest_is_tos)    __ fmul (non_tos_index);
2392       else                     __ fmula(non_tos_index);
2393       break;
2394 
2395     case lir_div:
2396       if (left_is_tos) {
2397         if (pop_fpu_stack)     __ fdivrp(non_tos_index);
2398         else if (dest_is_tos)  __ fdiv  (non_tos_index);
2399         else                   __ fdivra(non_tos_index);
2400       } else {
2401         if (pop_fpu_stack)     __ fdivp (non_tos_index);
2402         else if (dest_is_tos)  __ fdivr (non_tos_index);
2403         else                   __ fdiva (non_tos_index);
2404       }
2405       break;
2406 
2407     case lir_rem:
2408       assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2409       __ fremr(noreg);
2410       break;
2411 
2412     default:
2413       ShouldNotReachHere();
2414   }
2415 }
2416 #endif // _LP64
2417 
2418 
2419 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2420   if (value->is_double_xmm()) {
2421     switch(code) {
2422       case lir_abs :
2423         {
2424 #ifdef _LP64
2425           if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2426             assert(tmp->is_valid(), "need temporary");
2427             __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2428           } else
2429 #endif
2430           {
2431             if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2432               __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2433             }
2434             assert(!tmp->is_valid(), "do not need temporary");
2435             __ andpd(dest->as_xmm_double_reg(),
2436                      ExternalAddress(LIR_Assembler::double_signmask_pool),
2437                      rscratch1);
2438           }
2439         }
2440         break;
2441 
2442       case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2443       // all other intrinsics are not available in the SSE instruction set, so FPU is used
2444       default      : ShouldNotReachHere();
2445     }
2446 
2447 #ifndef _LP64
2448   } else if (value->is_double_fpu()) {
2449     assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2450     switch(code) {
2451       case lir_abs   : __ fabs() ; break;
2452       case lir_sqrt  : __ fsqrt(); break;
2453       default      : ShouldNotReachHere();
2454     }
2455 #endif // !_LP64
2456   } else if (code == lir_f2hf) {
2457     __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg());
2458   } else if (code == lir_hf2f) {
2459     __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register());
2460   } else {
2461     Unimplemented();
2462   }
2463 }
2464 
2465 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2466   // assert(left->destroys_register(), "check");
2467   if (left->is_single_cpu()) {
2468     Register reg = left->as_register();
2469     if (right->is_constant()) {
2470       int val = right->as_constant_ptr()->as_jint();
2471       switch (code) {
2472         case lir_logic_and: __ andl (reg, val); break;
2473         case lir_logic_or:  __ orl  (reg, val); break;
2474         case lir_logic_xor: __ xorl (reg, val); break;
2475         default: ShouldNotReachHere();
2476       }
2477     } else if (right->is_stack()) {
2478       // added support for stack operands
2479       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2480       switch (code) {
2481         case lir_logic_and: __ andl (reg, raddr); break;
2482         case lir_logic_or:  __ orl  (reg, raddr); break;
2483         case lir_logic_xor: __ xorl (reg, raddr); break;
2484         default: ShouldNotReachHere();
2485       }
2486     } else {
2487       Register rright = right->as_register();
2488       switch (code) {
2489         case lir_logic_and: __ andptr (reg, rright); break;
2490         case lir_logic_or : __ orptr  (reg, rright); break;
2491         case lir_logic_xor: __ xorptr (reg, rright); break;
2492         default: ShouldNotReachHere();
2493       }
2494     }
2495     move_regs(reg, dst->as_register());
2496   } else {
2497     Register l_lo = left->as_register_lo();
2498     Register l_hi = left->as_register_hi();
2499     if (right->is_constant()) {
2500 #ifdef _LP64
2501       __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2502       switch (code) {
2503         case lir_logic_and:
2504           __ andq(l_lo, rscratch1);
2505           break;
2506         case lir_logic_or:
2507           __ orq(l_lo, rscratch1);
2508           break;
2509         case lir_logic_xor:
2510           __ xorq(l_lo, rscratch1);
2511           break;
2512         default: ShouldNotReachHere();
2513       }
2514 #else
2515       int r_lo = right->as_constant_ptr()->as_jint_lo();
2516       int r_hi = right->as_constant_ptr()->as_jint_hi();
2517       switch (code) {
2518         case lir_logic_and:
2519           __ andl(l_lo, r_lo);
2520           __ andl(l_hi, r_hi);
2521           break;
2522         case lir_logic_or:
2523           __ orl(l_lo, r_lo);
2524           __ orl(l_hi, r_hi);
2525           break;
2526         case lir_logic_xor:
2527           __ xorl(l_lo, r_lo);
2528           __ xorl(l_hi, r_hi);
2529           break;
2530         default: ShouldNotReachHere();
2531       }
2532 #endif // _LP64
2533     } else {
2534 #ifdef _LP64
2535       Register r_lo;
2536       if (is_reference_type(right->type())) {
2537         r_lo = right->as_register();
2538       } else {
2539         r_lo = right->as_register_lo();
2540       }
2541 #else
2542       Register r_lo = right->as_register_lo();
2543       Register r_hi = right->as_register_hi();
2544       assert(l_lo != r_hi, "overwriting registers");
2545 #endif
2546       switch (code) {
2547         case lir_logic_and:
2548           __ andptr(l_lo, r_lo);
2549           NOT_LP64(__ andptr(l_hi, r_hi);)
2550           break;
2551         case lir_logic_or:
2552           __ orptr(l_lo, r_lo);
2553           NOT_LP64(__ orptr(l_hi, r_hi);)
2554           break;
2555         case lir_logic_xor:
2556           __ xorptr(l_lo, r_lo);
2557           NOT_LP64(__ xorptr(l_hi, r_hi);)
2558           break;
2559         default: ShouldNotReachHere();
2560       }
2561     }
2562 
2563     Register dst_lo = dst->as_register_lo();
2564     Register dst_hi = dst->as_register_hi();
2565 
2566 #ifdef _LP64
2567     move_regs(l_lo, dst_lo);
2568 #else
2569     if (dst_lo == l_hi) {
2570       assert(dst_hi != l_lo, "overwriting registers");
2571       move_regs(l_hi, dst_hi);
2572       move_regs(l_lo, dst_lo);
2573     } else {
2574       assert(dst_lo != l_hi, "overwriting registers");
2575       move_regs(l_lo, dst_lo);
2576       move_regs(l_hi, dst_hi);
2577     }
2578 #endif // _LP64
2579   }
2580 }
2581 
2582 
2583 // we assume that rax, and rdx can be overwritten
2584 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2585 
2586   assert(left->is_single_cpu(),   "left must be register");
2587   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
2588   assert(result->is_single_cpu(), "result must be register");
2589 
2590   //  assert(left->destroys_register(), "check");
2591   //  assert(right->destroys_register(), "check");
2592 
2593   Register lreg = left->as_register();
2594   Register dreg = result->as_register();
2595 
2596   if (right->is_constant()) {
2597     jint divisor = right->as_constant_ptr()->as_jint();
2598     assert(divisor > 0 && is_power_of_2(divisor), "must be");
2599     if (code == lir_idiv) {
2600       assert(lreg == rax, "must be rax,");
2601       assert(temp->as_register() == rdx, "tmp register must be rdx");
2602       __ cdql(); // sign extend into rdx:rax
2603       if (divisor == 2) {
2604         __ subl(lreg, rdx);
2605       } else {
2606         __ andl(rdx, divisor - 1);
2607         __ addl(lreg, rdx);
2608       }
2609       __ sarl(lreg, log2i_exact(divisor));
2610       move_regs(lreg, dreg);
2611     } else if (code == lir_irem) {
2612       Label done;
2613       __ mov(dreg, lreg);
2614       __ andl(dreg, 0x80000000 | (divisor - 1));
2615       __ jcc(Assembler::positive, done);
2616       __ decrement(dreg);
2617       __ orl(dreg, ~(divisor - 1));
2618       __ increment(dreg);
2619       __ bind(done);
2620     } else {
2621       ShouldNotReachHere();
2622     }
2623   } else {
2624     Register rreg = right->as_register();
2625     assert(lreg == rax, "left register must be rax,");
2626     assert(rreg != rdx, "right register must not be rdx");
2627     assert(temp->as_register() == rdx, "tmp register must be rdx");
2628 
2629     move_regs(lreg, rax);
2630 
2631     int idivl_offset = __ corrected_idivl(rreg);
2632     if (ImplicitDiv0Checks) {
2633       add_debug_info_for_div0(idivl_offset, info);
2634     }
2635     if (code == lir_irem) {
2636       move_regs(rdx, dreg); // result is in rdx
2637     } else {
2638       move_regs(rax, dreg);
2639     }
2640   }
2641 }
2642 
2643 
2644 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2645   if (opr1->is_single_cpu()) {
2646     Register reg1 = opr1->as_register();
2647     if (opr2->is_single_cpu()) {
2648       // cpu register - cpu register
2649       if (is_reference_type(opr1->type())) {
2650         __ cmpoop(reg1, opr2->as_register());
2651       } else {
2652         assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2653         __ cmpl(reg1, opr2->as_register());
2654       }
2655     } else if (opr2->is_stack()) {
2656       // cpu register - stack
2657       if (is_reference_type(opr1->type())) {
2658         __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2659       } else {
2660         __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2661       }
2662     } else if (opr2->is_constant()) {
2663       // cpu register - constant
2664       LIR_Const* c = opr2->as_constant_ptr();
2665       if (c->type() == T_INT) {
2666         jint i = c->as_jint();
2667         if (i == 0) {
2668           __ testl(reg1, reg1);
2669         } else {
2670           __ cmpl(reg1, i);
2671         }
2672       } else if (c->type() == T_METADATA) {
2673         // All we need for now is a comparison with null for equality.
2674         assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2675         Metadata* m = c->as_metadata();
2676         if (m == nullptr) {
2677           __ testptr(reg1, reg1);
2678         } else {
2679           ShouldNotReachHere();
2680         }
2681       } else if (is_reference_type(c->type())) {
2682         // In 64bit oops are single register
2683         jobject o = c->as_jobject();
2684         if (o == nullptr) {
2685           __ testptr(reg1, reg1);
2686         } else {
2687           __ cmpoop(reg1, o, rscratch1);
2688         }
2689       } else {
2690         fatal("unexpected type: %s", basictype_to_str(c->type()));
2691       }
2692       // cpu register - address
2693     } else if (opr2->is_address()) {
2694       if (op->info() != nullptr) {
2695         add_debug_info_for_null_check_here(op->info());
2696       }
2697       __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2698     } else {
2699       ShouldNotReachHere();
2700     }
2701 
2702   } else if(opr1->is_double_cpu()) {
2703     Register xlo = opr1->as_register_lo();
2704     Register xhi = opr1->as_register_hi();
2705     if (opr2->is_double_cpu()) {
2706 #ifdef _LP64
2707       __ cmpptr(xlo, opr2->as_register_lo());
2708 #else
2709       // cpu register - cpu register
2710       Register ylo = opr2->as_register_lo();
2711       Register yhi = opr2->as_register_hi();
2712       __ subl(xlo, ylo);
2713       __ sbbl(xhi, yhi);
2714       if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2715         __ orl(xhi, xlo);
2716       }
2717 #endif // _LP64
2718     } else if (opr2->is_constant()) {
2719       // cpu register - constant 0
2720       assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2721 #ifdef _LP64
2722       __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2723 #else
2724       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2725       __ orl(xhi, xlo);
2726 #endif // _LP64
2727     } else {
2728       ShouldNotReachHere();
2729     }
2730 
2731   } else if (opr1->is_single_xmm()) {
2732     XMMRegister reg1 = opr1->as_xmm_float_reg();
2733     if (opr2->is_single_xmm()) {
2734       // xmm register - xmm register
2735       __ ucomiss(reg1, opr2->as_xmm_float_reg());
2736     } else if (opr2->is_stack()) {
2737       // xmm register - stack
2738       __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2739     } else if (opr2->is_constant()) {
2740       // xmm register - constant
2741       __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2742     } else if (opr2->is_address()) {
2743       // xmm register - address
2744       if (op->info() != nullptr) {
2745         add_debug_info_for_null_check_here(op->info());
2746       }
2747       __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2748     } else {
2749       ShouldNotReachHere();
2750     }
2751 
2752   } else if (opr1->is_double_xmm()) {
2753     XMMRegister reg1 = opr1->as_xmm_double_reg();
2754     if (opr2->is_double_xmm()) {
2755       // xmm register - xmm register
2756       __ ucomisd(reg1, opr2->as_xmm_double_reg());
2757     } else if (opr2->is_stack()) {
2758       // xmm register - stack
2759       __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2760     } else if (opr2->is_constant()) {
2761       // xmm register - constant
2762       __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2763     } else if (opr2->is_address()) {
2764       // xmm register - address
2765       if (op->info() != nullptr) {
2766         add_debug_info_for_null_check_here(op->info());
2767       }
2768       __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2769     } else {
2770       ShouldNotReachHere();
2771     }
2772 
2773 #ifndef _LP64
2774   } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2775     assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2776     assert(opr2->is_fpu_register(), "both must be registers");
2777     __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2778 #endif // LP64
2779 
2780   } else if (opr1->is_address() && opr2->is_constant()) {
2781     LIR_Const* c = opr2->as_constant_ptr();
2782 #ifdef _LP64
2783     if (is_reference_type(c->type())) {
2784       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2785       __ movoop(rscratch1, c->as_jobject());
2786     }
2787 #endif // LP64
2788     if (op->info() != nullptr) {
2789       add_debug_info_for_null_check_here(op->info());
2790     }
2791     // special case: address - constant
2792     LIR_Address* addr = opr1->as_address_ptr();
2793     if (c->type() == T_INT) {
2794       __ cmpl(as_Address(addr), c->as_jint());
2795     } else if (is_reference_type(c->type())) {
2796 #ifdef _LP64
2797       // %%% Make this explode if addr isn't reachable until we figure out a
2798       // better strategy by giving noreg as the temp for as_Address
2799       __ cmpoop(rscratch1, as_Address(addr, noreg));
2800 #else
2801       __ cmpoop(as_Address(addr), c->as_jobject());
2802 #endif // _LP64
2803     } else {
2804       ShouldNotReachHere();
2805     }
2806 
2807   } else {
2808     ShouldNotReachHere();
2809   }
2810 }
2811 
2812 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2813   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2814     if (left->is_single_xmm()) {
2815       assert(right->is_single_xmm(), "must match");
2816       __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2817     } else if (left->is_double_xmm()) {
2818       assert(right->is_double_xmm(), "must match");
2819       __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2820 
2821     } else {
2822 #ifdef _LP64
2823       ShouldNotReachHere();
2824 #else
2825       assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2826       assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2827 
2828       assert(left->fpu() == 0, "left must be on TOS");
2829       __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2830                   op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2831 #endif // LP64
2832     }
2833   } else {
2834     assert(code == lir_cmp_l2i, "check");
2835 #ifdef _LP64
2836     Label done;
2837     Register dest = dst->as_register();
2838     __ cmpptr(left->as_register_lo(), right->as_register_lo());
2839     __ movl(dest, -1);
2840     __ jccb(Assembler::less, done);
2841     __ setb(Assembler::notZero, dest);
2842     __ movzbl(dest, dest);
2843     __ bind(done);
2844 #else
2845     __ lcmp2int(left->as_register_hi(),
2846                 left->as_register_lo(),
2847                 right->as_register_hi(),
2848                 right->as_register_lo());
2849     move_regs(left->as_register_hi(), dst->as_register());
2850 #endif // _LP64
2851   }
2852 }
2853 
2854 
2855 void LIR_Assembler::align_call(LIR_Code code) {
2856   // make sure that the displacement word of the call ends up word aligned
2857   int offset = __ offset();
2858   switch (code) {
2859   case lir_static_call:
2860   case lir_optvirtual_call:
2861   case lir_dynamic_call:
2862     offset += NativeCall::displacement_offset;
2863     break;
2864   case lir_icvirtual_call:
2865     offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2866     break;
2867   default: ShouldNotReachHere();
2868   }
2869   __ align(BytesPerWord, offset);
2870 }
2871 
2872 
2873 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2874   assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2875          "must be aligned");
2876   __ call(AddressLiteral(op->addr(), rtype));
2877   add_call_info(code_offset(), op->info());
2878   __ post_call_nop();
2879 }
2880 
2881 
2882 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2883   __ ic_call(op->addr());
2884   add_call_info(code_offset(), op->info());
2885   assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2886          "must be aligned");
2887   __ post_call_nop();
2888 }
2889 
2890 
2891 void LIR_Assembler::emit_static_call_stub() {
2892   address call_pc = __ pc();
2893   address stub = __ start_a_stub(call_stub_size());
2894   if (stub == nullptr) {
2895     bailout("static call stub overflow");
2896     return;
2897   }
2898 
2899   int start = __ offset();
2900 
2901   // make sure that the displacement word of the call ends up word aligned
2902   __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2903   __ relocate(static_stub_Relocation::spec(call_pc));
2904   __ mov_metadata(rbx, (Metadata*)nullptr);
2905   // must be set to -1 at code generation time
2906   assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2907   // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2908   __ jump(RuntimeAddress(__ pc()));
2909 
2910   assert(__ offset() - start <= call_stub_size(), "stub too big");
2911   __ end_a_stub();
2912 }
2913 
2914 
2915 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2916   assert(exceptionOop->as_register() == rax, "must match");
2917   assert(exceptionPC->as_register() == rdx, "must match");
2918 
2919   // exception object is not added to oop map by LinearScan
2920   // (LinearScan assumes that no oops are in fixed registers)
2921   info->add_register_oop(exceptionOop);
2922   Runtime1::StubID unwind_id;
2923 
2924   // get current pc information
2925   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2926   int pc_for_athrow_offset = __ offset();
2927   InternalAddress pc_for_athrow(__ pc());
2928   __ lea(exceptionPC->as_register(), pc_for_athrow);
2929   add_call_info(pc_for_athrow_offset, info); // for exception handler
2930 
2931   __ verify_not_null_oop(rax);
2932   // search an exception handler (rax: exception oop, rdx: throwing pc)
2933   if (compilation()->has_fpu_code()) {
2934     unwind_id = Runtime1::handle_exception_id;
2935   } else {
2936     unwind_id = Runtime1::handle_exception_nofpu_id;
2937   }
2938   __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2939 
2940   // enough room for two byte trap
2941   __ nop();
2942 }
2943 
2944 
2945 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2946   assert(exceptionOop->as_register() == rax, "must match");
2947 
2948   __ jmp(_unwind_handler_entry);
2949 }
2950 
2951 
2952 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2953 
2954   // optimized version for linear scan:
2955   // * count must be already in ECX (guaranteed by LinearScan)
2956   // * left and dest must be equal
2957   // * tmp must be unused
2958   assert(count->as_register() == SHIFT_count, "count must be in ECX");
2959   assert(left == dest, "left and dest must be equal");
2960   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2961 
2962   if (left->is_single_cpu()) {
2963     Register value = left->as_register();
2964     assert(value != SHIFT_count, "left cannot be ECX");
2965 
2966     switch (code) {
2967       case lir_shl:  __ shll(value); break;
2968       case lir_shr:  __ sarl(value); break;
2969       case lir_ushr: __ shrl(value); break;
2970       default: ShouldNotReachHere();
2971     }
2972   } else if (left->is_double_cpu()) {
2973     Register lo = left->as_register_lo();
2974     Register hi = left->as_register_hi();
2975     assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2976 #ifdef _LP64
2977     switch (code) {
2978       case lir_shl:  __ shlptr(lo);        break;
2979       case lir_shr:  __ sarptr(lo);        break;
2980       case lir_ushr: __ shrptr(lo);        break;
2981       default: ShouldNotReachHere();
2982     }
2983 #else
2984 
2985     switch (code) {
2986       case lir_shl:  __ lshl(hi, lo);        break;
2987       case lir_shr:  __ lshr(hi, lo, true);  break;
2988       case lir_ushr: __ lshr(hi, lo, false); break;
2989       default: ShouldNotReachHere();
2990     }
2991 #endif // LP64
2992   } else {
2993     ShouldNotReachHere();
2994   }
2995 }
2996 
2997 
2998 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2999   if (dest->is_single_cpu()) {
3000     // first move left into dest so that left is not destroyed by the shift
3001     Register value = dest->as_register();
3002     count = count & 0x1F; // Java spec
3003 
3004     move_regs(left->as_register(), value);
3005     switch (code) {
3006       case lir_shl:  __ shll(value, count); break;
3007       case lir_shr:  __ sarl(value, count); break;
3008       case lir_ushr: __ shrl(value, count); break;
3009       default: ShouldNotReachHere();
3010     }
3011   } else if (dest->is_double_cpu()) {
3012 #ifndef _LP64
3013     Unimplemented();
3014 #else
3015     // first move left into dest so that left is not destroyed by the shift
3016     Register value = dest->as_register_lo();
3017     count = count & 0x1F; // Java spec
3018 
3019     move_regs(left->as_register_lo(), value);
3020     switch (code) {
3021       case lir_shl:  __ shlptr(value, count); break;
3022       case lir_shr:  __ sarptr(value, count); break;
3023       case lir_ushr: __ shrptr(value, count); break;
3024       default: ShouldNotReachHere();
3025     }
3026 #endif // _LP64
3027   } else {
3028     ShouldNotReachHere();
3029   }
3030 }
3031 
3032 
3033 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3034   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3035   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3036   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3037   __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3038 }
3039 
3040 
3041 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
3042   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3043   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3044   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3045   __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3046 }
3047 
3048 
3049 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3050   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3051   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3052   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3053   __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1);
3054 }
3055 
3056 
3057 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3058   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3059   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3060   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3061   __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1);
3062 }
3063 
3064 
3065 // This code replaces a call to arraycopy; no exception may
3066 // be thrown in this code, they must be thrown in the System.arraycopy
3067 // activation frame; we could save some checks if this would not be the case
3068 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3069   ciArrayKlass* default_type = op->expected_type();
3070   Register src = op->src()->as_register();
3071   Register dst = op->dst()->as_register();
3072   Register src_pos = op->src_pos()->as_register();
3073   Register dst_pos = op->dst_pos()->as_register();
3074   Register length  = op->length()->as_register();
3075   Register tmp = op->tmp()->as_register();
3076   Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3077 
3078   CodeStub* stub = op->stub();
3079   int flags = op->flags();
3080   BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
3081   if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3082 
3083   // if we don't know anything, just go through the generic arraycopy
3084   if (default_type == nullptr) {
3085     // save outgoing arguments on stack in case call to System.arraycopy is needed
3086     // HACK ALERT. This code used to push the parameters in a hardwired fashion
3087     // for interpreter calling conventions. Now we have to do it in new style conventions.
3088     // For the moment until C1 gets the new register allocator I just force all the
3089     // args to the right place (except the register args) and then on the back side
3090     // reload the register args properly if we go slow path. Yuck
3091 
3092     // These are proper for the calling convention
3093     store_parameter(length, 2);
3094     store_parameter(dst_pos, 1);
3095     store_parameter(dst, 0);
3096 
3097     // these are just temporary placements until we need to reload
3098     store_parameter(src_pos, 3);
3099     store_parameter(src, 4);
3100     NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3101 
3102     address copyfunc_addr = StubRoutines::generic_arraycopy();
3103     assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
3104 
3105     // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3106 #ifdef _LP64
3107     // The arguments are in java calling convention so we can trivially shift them to C
3108     // convention
3109     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3110     __ mov(c_rarg0, j_rarg0);
3111     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3112     __ mov(c_rarg1, j_rarg1);
3113     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3114     __ mov(c_rarg2, j_rarg2);
3115     assert_different_registers(c_rarg3, j_rarg4);
3116     __ mov(c_rarg3, j_rarg3);
3117 #ifdef _WIN64
3118     // Allocate abi space for args but be sure to keep stack aligned
3119     __ subptr(rsp, 6*wordSize);
3120     store_parameter(j_rarg4, 4);
3121 #ifndef PRODUCT
3122     if (PrintC1Statistics) {
3123       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3124     }
3125 #endif
3126     __ call(RuntimeAddress(copyfunc_addr));
3127     __ addptr(rsp, 6*wordSize);
3128 #else
3129     __ mov(c_rarg4, j_rarg4);
3130 #ifndef PRODUCT
3131     if (PrintC1Statistics) {
3132       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3133     }
3134 #endif
3135     __ call(RuntimeAddress(copyfunc_addr));
3136 #endif // _WIN64
3137 #else
3138     __ push(length);
3139     __ push(dst_pos);
3140     __ push(dst);
3141     __ push(src_pos);
3142     __ push(src);
3143 
3144 #ifndef PRODUCT
3145     if (PrintC1Statistics) {
3146       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3147     }
3148 #endif
3149     __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3150 
3151 #endif // _LP64
3152 
3153     __ testl(rax, rax);
3154     __ jcc(Assembler::equal, *stub->continuation());
3155 
3156     __ mov(tmp, rax);
3157     __ xorl(tmp, -1);
3158 
3159     // Reload values from the stack so they are where the stub
3160     // expects them.
3161     __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3162     __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3163     __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3164     __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3165     __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3166 
3167     __ subl(length, tmp);
3168     __ addl(src_pos, tmp);
3169     __ addl(dst_pos, tmp);
3170     __ jmp(*stub->entry());
3171 
3172     __ bind(*stub->continuation());
3173     return;
3174   }
3175 
3176   assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3177 
3178   int elem_size = type2aelembytes(basic_type);
3179   Address::ScaleFactor scale;
3180 
3181   switch (elem_size) {
3182     case 1 :
3183       scale = Address::times_1;
3184       break;
3185     case 2 :
3186       scale = Address::times_2;
3187       break;
3188     case 4 :
3189       scale = Address::times_4;
3190       break;
3191     case 8 :
3192       scale = Address::times_8;
3193       break;
3194     default:
3195       scale = Address::no_scale;
3196       ShouldNotReachHere();
3197   }
3198 
3199   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3200   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3201   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3202   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3203 
3204   // length and pos's are all sign extended at this point on 64bit
3205 
3206   // test for null
3207   if (flags & LIR_OpArrayCopy::src_null_check) {
3208     __ testptr(src, src);
3209     __ jcc(Assembler::zero, *stub->entry());
3210   }
3211   if (flags & LIR_OpArrayCopy::dst_null_check) {
3212     __ testptr(dst, dst);
3213     __ jcc(Assembler::zero, *stub->entry());
3214   }
3215 
3216   // If the compiler was not able to prove that exact type of the source or the destination
3217   // of the arraycopy is an array type, check at runtime if the source or the destination is
3218   // an instance type.
3219   if (flags & LIR_OpArrayCopy::type_check) {
3220     if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3221       __ load_klass(tmp, dst, tmp_load_klass);
3222       __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3223       __ jcc(Assembler::greaterEqual, *stub->entry());
3224     }
3225 
3226     if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3227       __ load_klass(tmp, src, tmp_load_klass);
3228       __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3229       __ jcc(Assembler::greaterEqual, *stub->entry());
3230     }
3231   }
3232 
3233   // check if negative
3234   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3235     __ testl(src_pos, src_pos);
3236     __ jcc(Assembler::less, *stub->entry());
3237   }
3238   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3239     __ testl(dst_pos, dst_pos);
3240     __ jcc(Assembler::less, *stub->entry());
3241   }
3242 
3243   if (flags & LIR_OpArrayCopy::src_range_check) {
3244     __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3245     __ cmpl(tmp, src_length_addr);
3246     __ jcc(Assembler::above, *stub->entry());
3247   }
3248   if (flags & LIR_OpArrayCopy::dst_range_check) {
3249     __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3250     __ cmpl(tmp, dst_length_addr);
3251     __ jcc(Assembler::above, *stub->entry());
3252   }
3253 
3254   if (flags & LIR_OpArrayCopy::length_positive_check) {
3255     __ testl(length, length);
3256     __ jcc(Assembler::less, *stub->entry());
3257   }
3258 
3259 #ifdef _LP64
3260   __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3261   __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3262 #endif
3263 
3264   if (flags & LIR_OpArrayCopy::type_check) {
3265     // We don't know the array types are compatible
3266     if (basic_type != T_OBJECT) {
3267       // Simple test for basic type arrays
3268       if (UseCompressedClassPointers) {
3269         __ movl(tmp, src_klass_addr);
3270         __ cmpl(tmp, dst_klass_addr);
3271       } else {
3272         __ movptr(tmp, src_klass_addr);
3273         __ cmpptr(tmp, dst_klass_addr);
3274       }
3275       __ jcc(Assembler::notEqual, *stub->entry());
3276     } else {
3277       // For object arrays, if src is a sub class of dst then we can
3278       // safely do the copy.
3279       Label cont, slow;
3280 
3281       __ push(src);
3282       __ push(dst);
3283 
3284       __ load_klass(src, src, tmp_load_klass);
3285       __ load_klass(dst, dst, tmp_load_klass);
3286 
3287       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
3288 
3289       __ push(src);
3290       __ push(dst);
3291       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3292       __ pop(dst);
3293       __ pop(src);
3294 
3295       __ testl(src, src);
3296       __ jcc(Assembler::notEqual, cont);
3297 
3298       __ bind(slow);
3299       __ pop(dst);
3300       __ pop(src);
3301 
3302       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3303       if (copyfunc_addr != nullptr) { // use stub if available
3304         // src is not a sub class of dst so we have to do a
3305         // per-element check.
3306 
3307         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3308         if ((flags & mask) != mask) {
3309           // Check that at least both of them object arrays.
3310           assert(flags & mask, "one of the two should be known to be an object array");
3311 
3312           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3313             __ load_klass(tmp, src, tmp_load_klass);
3314           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3315             __ load_klass(tmp, dst, tmp_load_klass);
3316           }
3317           int lh_offset = in_bytes(Klass::layout_helper_offset());
3318           Address klass_lh_addr(tmp, lh_offset);
3319           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3320           __ cmpl(klass_lh_addr, objArray_lh);
3321           __ jcc(Assembler::notEqual, *stub->entry());
3322         }
3323 
3324        // Spill because stubs can use any register they like and it's
3325        // easier to restore just those that we care about.
3326        store_parameter(dst, 0);
3327        store_parameter(dst_pos, 1);
3328        store_parameter(length, 2);
3329        store_parameter(src_pos, 3);
3330        store_parameter(src, 4);
3331 
3332 #ifndef _LP64
3333         __ movptr(tmp, dst_klass_addr);
3334         __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3335         __ push(tmp);
3336         __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3337         __ push(tmp);
3338         __ push(length);
3339         __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3340         __ push(tmp);
3341         __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3342         __ push(tmp);
3343 
3344         __ call_VM_leaf(copyfunc_addr, 5);
3345 #else
3346         __ movl2ptr(length, length); //higher 32bits must be null
3347 
3348         __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3349         assert_different_registers(c_rarg0, dst, dst_pos, length);
3350         __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3351         assert_different_registers(c_rarg1, dst, length);
3352 
3353         __ mov(c_rarg2, length);
3354         assert_different_registers(c_rarg2, dst);
3355 
3356 #ifdef _WIN64
3357         // Allocate abi space for args but be sure to keep stack aligned
3358         __ subptr(rsp, 6*wordSize);
3359         __ load_klass(c_rarg3, dst, tmp_load_klass);
3360         __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3361         store_parameter(c_rarg3, 4);
3362         __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3363         __ call(RuntimeAddress(copyfunc_addr));
3364         __ addptr(rsp, 6*wordSize);
3365 #else
3366         __ load_klass(c_rarg4, dst, tmp_load_klass);
3367         __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3368         __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3369         __ call(RuntimeAddress(copyfunc_addr));
3370 #endif
3371 
3372 #endif
3373 
3374 #ifndef PRODUCT
3375         if (PrintC1Statistics) {
3376           Label failed;
3377           __ testl(rax, rax);
3378           __ jcc(Assembler::notZero, failed);
3379           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1);
3380           __ bind(failed);
3381         }
3382 #endif
3383 
3384         __ testl(rax, rax);
3385         __ jcc(Assembler::zero, *stub->continuation());
3386 
3387 #ifndef PRODUCT
3388         if (PrintC1Statistics) {
3389           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1);
3390         }
3391 #endif
3392 
3393         __ mov(tmp, rax);
3394 
3395         __ xorl(tmp, -1);
3396 
3397         // Restore previously spilled arguments
3398         __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3399         __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3400         __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3401         __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3402         __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3403 
3404 
3405         __ subl(length, tmp);
3406         __ addl(src_pos, tmp);
3407         __ addl(dst_pos, tmp);
3408       }
3409 
3410       __ jmp(*stub->entry());
3411 
3412       __ bind(cont);
3413       __ pop(dst);
3414       __ pop(src);
3415     }
3416   }
3417 
3418 #ifdef ASSERT
3419   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3420     // Sanity check the known type with the incoming class.  For the
3421     // primitive case the types must match exactly with src.klass and
3422     // dst.klass each exactly matching the default type.  For the
3423     // object array case, if no type check is needed then either the
3424     // dst type is exactly the expected type and the src type is a
3425     // subtype which we can't check or src is the same array as dst
3426     // but not necessarily exactly of type default_type.
3427     Label known_ok, halt;
3428     __ mov_metadata(tmp, default_type->constant_encoding());
3429 #ifdef _LP64
3430     if (UseCompressedClassPointers) {
3431       __ encode_klass_not_null(tmp, rscratch1);
3432     }
3433 #endif
3434 
3435     if (basic_type != T_OBJECT) {
3436 
3437       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3438       else                   __ cmpptr(tmp, dst_klass_addr);
3439       __ jcc(Assembler::notEqual, halt);
3440       if (UseCompressedClassPointers)          __ cmpl(tmp, src_klass_addr);
3441       else                   __ cmpptr(tmp, src_klass_addr);
3442       __ jcc(Assembler::equal, known_ok);
3443     } else {
3444       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3445       else                   __ cmpptr(tmp, dst_klass_addr);
3446       __ jcc(Assembler::equal, known_ok);
3447       __ cmpptr(src, dst);
3448       __ jcc(Assembler::equal, known_ok);
3449     }
3450     __ bind(halt);
3451     __ stop("incorrect type information in arraycopy");
3452     __ bind(known_ok);
3453   }
3454 #endif
3455 
3456 #ifndef PRODUCT
3457   if (PrintC1Statistics) {
3458     __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1);
3459   }
3460 #endif
3461 
3462 #ifdef _LP64
3463   assert_different_registers(c_rarg0, dst, dst_pos, length);
3464   __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3465   assert_different_registers(c_rarg1, length);
3466   __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3467   __ mov(c_rarg2, length);
3468 
3469 #else
3470   __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3471   store_parameter(tmp, 0);
3472   __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3473   store_parameter(tmp, 1);
3474   store_parameter(length, 2);
3475 #endif // _LP64
3476 
3477   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3478   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3479   const char *name;
3480   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3481   __ call_VM_leaf(entry, 0);
3482 
3483   __ bind(*stub->continuation());
3484 }
3485 
3486 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3487   assert(op->crc()->is_single_cpu(),  "crc must be register");
3488   assert(op->val()->is_single_cpu(),  "byte value must be register");
3489   assert(op->result_opr()->is_single_cpu(), "result must be register");
3490   Register crc = op->crc()->as_register();
3491   Register val = op->val()->as_register();
3492   Register res = op->result_opr()->as_register();
3493 
3494   assert_different_registers(val, crc, res);
3495 
3496   __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3497   __ notl(crc); // ~crc
3498   __ update_byte_crc32(crc, val, res);
3499   __ notl(crc); // ~crc
3500   __ mov(res, crc);
3501 }
3502 
3503 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3504   Register obj = op->obj_opr()->as_register();  // may not be an oop
3505   Register hdr = op->hdr_opr()->as_register();
3506   Register lock = op->lock_opr()->as_register();
3507   if (LockingMode == LM_MONITOR) {
3508     if (op->info() != nullptr) {
3509       add_debug_info_for_null_check_here(op->info());
3510       __ null_check(obj);
3511     }
3512     __ jmp(*op->stub()->entry());
3513   } else if (op->code() == lir_lock) {
3514     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3515     Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg;
3516     // add debug info for NullPointerException only if one is possible
3517     int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
3518     if (op->info() != nullptr) {
3519       add_debug_info_for_null_check(null_check_offset, op->info());
3520     }
3521     // done
3522   } else if (op->code() == lir_unlock) {
3523     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3524     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3525   } else {
3526     Unimplemented();
3527   }
3528   __ bind(*op->stub()->continuation());
3529 }
3530 
3531 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
3532   Register obj = op->obj()->as_pointer_register();
3533   Register result = op->result_opr()->as_pointer_register();
3534 
3535   CodeEmitInfo* info = op->info();
3536   if (info != nullptr) {
3537     add_debug_info_for_null_check_here(info);
3538   }
3539 
3540 #ifdef _LP64
3541   if (UseCompressedClassPointers) {
3542     __ movl(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3543     __ decode_klass_not_null(result, rscratch1);
3544   } else
3545 #endif
3546     __ movptr(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3547 }
3548 
3549 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3550   ciMethod* method = op->profiled_method();
3551   int bci          = op->profiled_bci();
3552   ciMethod* callee = op->profiled_callee();
3553   Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3554 
3555   // Update counter for all call types
3556   ciMethodData* md = method->method_data_or_null();
3557   assert(md != nullptr, "Sanity");
3558   ciProfileData* data = md->bci_to_data(bci);
3559   assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
3560   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
3561   Register mdo  = op->mdo()->as_register();
3562   __ mov_metadata(mdo, md->constant_encoding());
3563   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3564   // Perform additional virtual call profiling for invokevirtual and
3565   // invokeinterface bytecodes
3566   if (op->should_profile_receiver_type()) {
3567     assert(op->recv()->is_single_cpu(), "recv must be allocated");
3568     Register recv = op->recv()->as_register();
3569     assert_different_registers(mdo, recv);
3570     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3571     ciKlass* known_klass = op->known_holder();
3572     if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
3573       // We know the type that will be seen at this call site; we can
3574       // statically update the MethodData* rather than needing to do
3575       // dynamic tests on the receiver type
3576 
3577       // NOTE: we should probably put a lock around this search to
3578       // avoid collisions by concurrent compilations
3579       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3580       uint i;
3581       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3582         ciKlass* receiver = vc_data->receiver(i);
3583         if (known_klass->equals(receiver)) {
3584           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3585           __ addptr(data_addr, DataLayout::counter_increment);
3586           return;
3587         }
3588       }
3589 
3590       // Receiver type not found in profile data; select an empty slot
3591 
3592       // Note that this is less efficient than it should be because it
3593       // always does a write to the receiver part of the
3594       // VirtualCallData rather than just the first time
3595       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3596         ciKlass* receiver = vc_data->receiver(i);
3597         if (receiver == nullptr) {
3598           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3599           __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1);
3600           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3601           __ addptr(data_addr, DataLayout::counter_increment);
3602           return;
3603         }
3604       }
3605     } else {
3606       __ load_klass(recv, recv, tmp_load_klass);
3607       Label update_done;
3608       type_profile_helper(mdo, md, data, recv, &update_done);
3609       // Receiver did not match any saved receiver and there is no empty row for it.
3610       // Increment total counter to indicate polymorphic case.
3611       __ addptr(counter_addr, DataLayout::counter_increment);
3612 
3613       __ bind(update_done);
3614     }
3615   } else {
3616     // Static call
3617     __ addptr(counter_addr, DataLayout::counter_increment);
3618   }
3619 }
3620 
3621 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3622   Register obj = op->obj()->as_register();
3623   Register tmp = op->tmp()->as_pointer_register();
3624   Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3625   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3626   ciKlass* exact_klass = op->exact_klass();
3627   intptr_t current_klass = op->current_klass();
3628   bool not_null = op->not_null();
3629   bool no_conflict = op->no_conflict();
3630 
3631   Label update, next, none;
3632 
3633   bool do_null = !not_null;
3634   bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3635   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3636 
3637   assert(do_null || do_update, "why are we here?");
3638   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3639 
3640   __ verify_oop(obj);
3641 
3642 #ifdef ASSERT
3643   if (obj == tmp) {
3644 #ifdef _LP64
3645     assert_different_registers(obj, rscratch1, mdo_addr.base(), mdo_addr.index());
3646 #else
3647     assert_different_registers(obj, mdo_addr.base(), mdo_addr.index());
3648 #endif
3649   } else {
3650 #ifdef _LP64
3651     assert_different_registers(obj, tmp, rscratch1, mdo_addr.base(), mdo_addr.index());
3652 #else
3653     assert_different_registers(obj, tmp, mdo_addr.base(), mdo_addr.index());
3654 #endif
3655   }
3656 #endif
3657   if (do_null) {
3658     __ testptr(obj, obj);
3659     __ jccb(Assembler::notZero, update);
3660     if (!TypeEntries::was_null_seen(current_klass)) {
3661       __ testptr(mdo_addr, TypeEntries::null_seen);
3662 #ifndef ASSERT
3663       __ jccb(Assembler::notZero, next); // already set
3664 #else
3665       __ jcc(Assembler::notZero, next); // already set
3666 #endif
3667       // atomic update to prevent overwriting Klass* with 0
3668       __ lock();
3669       __ orptr(mdo_addr, TypeEntries::null_seen);
3670     }
3671     if (do_update) {
3672 #ifndef ASSERT
3673       __ jmpb(next);
3674     }
3675 #else
3676       __ jmp(next);
3677     }
3678   } else {
3679     __ testptr(obj, obj);
3680     __ jcc(Assembler::notZero, update);
3681     __ stop("unexpected null obj");
3682 #endif
3683   }
3684 
3685   __ bind(update);
3686 
3687   if (do_update) {
3688 #ifdef ASSERT
3689     if (exact_klass != nullptr) {
3690       Label ok;
3691       __ load_klass(tmp, obj, tmp_load_klass);
3692       __ push(tmp);
3693       __ mov_metadata(tmp, exact_klass->constant_encoding());
3694       __ cmpptr(tmp, Address(rsp, 0));
3695       __ jcc(Assembler::equal, ok);
3696       __ stop("exact klass and actual klass differ");
3697       __ bind(ok);
3698       __ pop(tmp);
3699     }
3700 #endif
3701     if (!no_conflict) {
3702       if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3703         if (exact_klass != nullptr) {
3704           __ mov_metadata(tmp, exact_klass->constant_encoding());
3705         } else {
3706           __ load_klass(tmp, obj, tmp_load_klass);
3707         }
3708 #ifdef _LP64
3709         __ mov(rscratch1, tmp); // save original value before XOR
3710 #endif
3711         __ xorptr(tmp, mdo_addr);
3712         __ testptr(tmp, TypeEntries::type_klass_mask);
3713         // klass seen before, nothing to do. The unknown bit may have been
3714         // set already but no need to check.
3715         __ jccb(Assembler::zero, next);
3716 
3717         __ testptr(tmp, TypeEntries::type_unknown);
3718         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3719 
3720         if (TypeEntries::is_type_none(current_klass)) {
3721           __ testptr(mdo_addr, TypeEntries::type_mask);
3722           __ jccb(Assembler::zero, none);
3723 #ifdef _LP64
3724           // There is a chance that the checks above (re-reading profiling
3725           // data from memory) fail if another thread has just set the
3726           // profiling to this obj's klass
3727           __ mov(tmp, rscratch1); // get back original value before XOR
3728           __ xorptr(tmp, mdo_addr);
3729           __ testptr(tmp, TypeEntries::type_klass_mask);
3730           __ jccb(Assembler::zero, next);
3731 #endif
3732         }
3733       } else {
3734         assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3735                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3736 
3737         __ testptr(mdo_addr, TypeEntries::type_unknown);
3738         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3739       }
3740 
3741       // different than before. Cannot keep accurate profile.
3742       __ orptr(mdo_addr, TypeEntries::type_unknown);
3743 
3744       if (TypeEntries::is_type_none(current_klass)) {
3745         __ jmpb(next);
3746 
3747         __ bind(none);
3748         // first time here. Set profile type.
3749         __ movptr(mdo_addr, tmp);
3750 #ifdef ASSERT
3751         __ andptr(tmp, TypeEntries::type_klass_mask);
3752         __ verify_klass_ptr(tmp);
3753 #endif
3754       }
3755     } else {
3756       // There's a single possible klass at this profile point
3757       assert(exact_klass != nullptr, "should be");
3758       if (TypeEntries::is_type_none(current_klass)) {
3759         __ mov_metadata(tmp, exact_klass->constant_encoding());
3760         __ xorptr(tmp, mdo_addr);
3761         __ testptr(tmp, TypeEntries::type_klass_mask);
3762 #ifdef ASSERT
3763         __ jcc(Assembler::zero, next);
3764 
3765         {
3766           Label ok;
3767           __ push(tmp);
3768           __ testptr(mdo_addr, TypeEntries::type_mask);
3769           __ jcc(Assembler::zero, ok);
3770           // may have been set by another thread
3771           __ mov_metadata(tmp, exact_klass->constant_encoding());
3772           __ xorptr(tmp, mdo_addr);
3773           __ testptr(tmp, TypeEntries::type_mask);
3774           __ jcc(Assembler::zero, ok);
3775 
3776           __ stop("unexpected profiling mismatch");
3777           __ bind(ok);
3778           __ pop(tmp);
3779         }
3780 #else
3781         __ jccb(Assembler::zero, next);
3782 #endif
3783         // first time here. Set profile type.
3784         __ movptr(mdo_addr, tmp);
3785 #ifdef ASSERT
3786         __ andptr(tmp, TypeEntries::type_klass_mask);
3787         __ verify_klass_ptr(tmp);
3788 #endif
3789       } else {
3790         assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3791                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3792 
3793         __ testptr(mdo_addr, TypeEntries::type_unknown);
3794         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3795 
3796         __ orptr(mdo_addr, TypeEntries::type_unknown);
3797       }
3798     }
3799   }
3800   __ bind(next);
3801 }
3802 
3803 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3804   Unimplemented();
3805 }
3806 
3807 
3808 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3809   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3810 }
3811 
3812 
3813 void LIR_Assembler::align_backward_branch_target() {
3814   __ align(BytesPerWord);
3815 }
3816 
3817 
3818 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3819   if (left->is_single_cpu()) {
3820     __ negl(left->as_register());
3821     move_regs(left->as_register(), dest->as_register());
3822 
3823   } else if (left->is_double_cpu()) {
3824     Register lo = left->as_register_lo();
3825 #ifdef _LP64
3826     Register dst = dest->as_register_lo();
3827     __ movptr(dst, lo);
3828     __ negptr(dst);
3829 #else
3830     Register hi = left->as_register_hi();
3831     __ lneg(hi, lo);
3832     if (dest->as_register_lo() == hi) {
3833       assert(dest->as_register_hi() != lo, "destroying register");
3834       move_regs(hi, dest->as_register_hi());
3835       move_regs(lo, dest->as_register_lo());
3836     } else {
3837       move_regs(lo, dest->as_register_lo());
3838       move_regs(hi, dest->as_register_hi());
3839     }
3840 #endif // _LP64
3841 
3842   } else if (dest->is_single_xmm()) {
3843 #ifdef _LP64
3844     if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3845       assert(tmp->is_valid(), "need temporary");
3846       assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
3847       __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
3848     }
3849     else
3850 #endif
3851     {
3852       assert(!tmp->is_valid(), "do not need temporary");
3853       if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3854         __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3855       }
3856       __ xorps(dest->as_xmm_float_reg(),
3857                ExternalAddress(LIR_Assembler::float_signflip_pool),
3858                rscratch1);
3859     }
3860   } else if (dest->is_double_xmm()) {
3861 #ifdef _LP64
3862     if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3863       assert(tmp->is_valid(), "need temporary");
3864       assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
3865       __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
3866     }
3867     else
3868 #endif
3869     {
3870       assert(!tmp->is_valid(), "do not need temporary");
3871       if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3872         __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3873       }
3874       __ xorpd(dest->as_xmm_double_reg(),
3875                ExternalAddress(LIR_Assembler::double_signflip_pool),
3876                rscratch1);
3877     }
3878 #ifndef _LP64
3879   } else if (left->is_single_fpu() || left->is_double_fpu()) {
3880     assert(left->fpu() == 0, "arg must be on TOS");
3881     assert(dest->fpu() == 0, "dest must be TOS");
3882     __ fchs();
3883 #endif // !_LP64
3884 
3885   } else {
3886     ShouldNotReachHere();
3887   }
3888 }
3889 
3890 
3891 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3892   assert(src->is_address(), "must be an address");
3893   assert(dest->is_register(), "must be a register");
3894 
3895   PatchingStub* patch = nullptr;
3896   if (patch_code != lir_patch_none) {
3897     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3898   }
3899 
3900   Register reg = dest->as_pointer_register();
3901   LIR_Address* addr = src->as_address_ptr();
3902   __ lea(reg, as_Address(addr));
3903 
3904   if (patch != nullptr) {
3905     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3906   }
3907 }
3908 
3909 
3910 
3911 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3912   assert(!tmp->is_valid(), "don't need temporary");
3913   __ call(RuntimeAddress(dest));
3914   if (info != nullptr) {
3915     add_call_info_here(info);
3916   }
3917   __ post_call_nop();
3918 }
3919 
3920 
3921 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3922   assert(type == T_LONG, "only for volatile long fields");
3923 
3924   if (info != nullptr) {
3925     add_debug_info_for_null_check_here(info);
3926   }
3927 
3928   if (src->is_double_xmm()) {
3929     if (dest->is_double_cpu()) {
3930 #ifdef _LP64
3931       __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3932 #else
3933       __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3934       __ psrlq(src->as_xmm_double_reg(), 32);
3935       __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3936 #endif // _LP64
3937     } else if (dest->is_double_stack()) {
3938       __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3939     } else if (dest->is_address()) {
3940       __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3941     } else {
3942       ShouldNotReachHere();
3943     }
3944 
3945   } else if (dest->is_double_xmm()) {
3946     if (src->is_double_stack()) {
3947       __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3948     } else if (src->is_address()) {
3949       __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3950     } else {
3951       ShouldNotReachHere();
3952     }
3953 
3954 #ifndef _LP64
3955   } else if (src->is_double_fpu()) {
3956     assert(src->fpu_regnrLo() == 0, "must be TOS");
3957     if (dest->is_double_stack()) {
3958       __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3959     } else if (dest->is_address()) {
3960       __ fistp_d(as_Address(dest->as_address_ptr()));
3961     } else {
3962       ShouldNotReachHere();
3963     }
3964 
3965   } else if (dest->is_double_fpu()) {
3966     assert(dest->fpu_regnrLo() == 0, "must be TOS");
3967     if (src->is_double_stack()) {
3968       __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3969     } else if (src->is_address()) {
3970       __ fild_d(as_Address(src->as_address_ptr()));
3971     } else {
3972       ShouldNotReachHere();
3973     }
3974 #endif // !_LP64
3975 
3976   } else {
3977     ShouldNotReachHere();
3978   }
3979 }
3980 
3981 #ifdef ASSERT
3982 // emit run-time assertion
3983 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3984   assert(op->code() == lir_assert, "must be");
3985 
3986   if (op->in_opr1()->is_valid()) {
3987     assert(op->in_opr2()->is_valid(), "both operands must be valid");
3988     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3989   } else {
3990     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3991     assert(op->condition() == lir_cond_always, "no other conditions allowed");
3992   }
3993 
3994   Label ok;
3995   if (op->condition() != lir_cond_always) {
3996     Assembler::Condition acond = Assembler::zero;
3997     switch (op->condition()) {
3998       case lir_cond_equal:        acond = Assembler::equal;       break;
3999       case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
4000       case lir_cond_less:         acond = Assembler::less;        break;
4001       case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
4002       case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
4003       case lir_cond_greater:      acond = Assembler::greater;     break;
4004       case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
4005       case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
4006       default:                    ShouldNotReachHere();
4007     }
4008     __ jcc(acond, ok);
4009   }
4010   if (op->halt()) {
4011     const char* str = __ code_string(op->msg());
4012     __ stop(str);
4013   } else {
4014     breakpoint();
4015   }
4016   __ bind(ok);
4017 }
4018 #endif
4019 
4020 void LIR_Assembler::membar() {
4021   // QQQ sparc TSO uses this,
4022   __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
4023 }
4024 
4025 void LIR_Assembler::membar_acquire() {
4026   // No x86 machines currently require load fences
4027 }
4028 
4029 void LIR_Assembler::membar_release() {
4030   // No x86 machines currently require store fences
4031 }
4032 
4033 void LIR_Assembler::membar_loadload() {
4034   // no-op
4035   //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
4036 }
4037 
4038 void LIR_Assembler::membar_storestore() {
4039   // no-op
4040   //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4041 }
4042 
4043 void LIR_Assembler::membar_loadstore() {
4044   // no-op
4045   //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4046 }
4047 
4048 void LIR_Assembler::membar_storeload() {
4049   __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4050 }
4051 
4052 void LIR_Assembler::on_spin_wait() {
4053   __ pause ();
4054 }
4055 
4056 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4057   assert(result_reg->is_register(), "check");
4058 #ifdef _LP64
4059   // __ get_thread(result_reg->as_register_lo());
4060   __ mov(result_reg->as_register(), r15_thread);
4061 #else
4062   __ get_thread(result_reg->as_register());
4063 #endif // _LP64
4064 }
4065 
4066 
4067 void LIR_Assembler::peephole(LIR_List*) {
4068   // do nothing for now
4069 }
4070 
4071 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4072   assert(data == dest, "xchg/xadd uses only 2 operands");
4073 
4074   if (data->type() == T_INT) {
4075     if (code == lir_xadd) {
4076       __ lock();
4077       __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4078     } else {
4079       __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4080     }
4081   } else if (data->is_oop()) {
4082     assert (code == lir_xchg, "xadd for oops");
4083     Register obj = data->as_register();
4084 #ifdef _LP64
4085     if (UseCompressedOops) {
4086       __ encode_heap_oop(obj);
4087       __ xchgl(obj, as_Address(src->as_address_ptr()));
4088       __ decode_heap_oop(obj);
4089     } else {
4090       __ xchgptr(obj, as_Address(src->as_address_ptr()));
4091     }
4092 #else
4093     __ xchgl(obj, as_Address(src->as_address_ptr()));
4094 #endif
4095   } else if (data->type() == T_LONG) {
4096 #ifdef _LP64
4097     assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4098     if (code == lir_xadd) {
4099       __ lock();
4100       __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4101     } else {
4102       __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4103     }
4104 #else
4105     ShouldNotReachHere();
4106 #endif
4107   } else {
4108     ShouldNotReachHere();
4109   }
4110 }
4111 
4112 #undef __