1 /*
2 * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "ci/ciUtilities.hpp"
37 #include "code/SCCache.hpp"
38 #include "compiler/oopMap.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/gc_globals.hpp"
41 #include "nativeInst_x86.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/safepointMechanism.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/stubRoutines.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_x86.inline.hpp"
49
50
51 // These masks are used to provide 128-bit aligned bitmasks to the XMM
52 // instructions, to allow sign-masking or sign-bit flipping. They allow
53 // fast versions of NegF/NegD and AbsF/AbsD.
54
55 // Note: 'double' and 'long long' have 32-bits alignment on x86.
56 static address double_quadword(jlong *adr, jlong lo, jlong hi) {
57 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
58 // of 128-bits operands for SSE instructions.
59 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
60 // Store the value to a 128-bits operand.
61 operand[0] = lo;
62 operand[1] = hi;
63 return (address)operand;
64 }
65
66 // Buffer for 128-bits masks used by SSE instructions.
67 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
68
69 // Static initialization during VM startup.
70 address LIR_Assembler::float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
71 address LIR_Assembler::double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
72 address LIR_Assembler::float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
73 address LIR_Assembler::double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
74
75
76 NEEDS_CLEANUP // remove this definitions ?
77 const Register SYNC_header = rax; // synchronization header
78 const Register SHIFT_count = rcx; // where count for shift operations must be
79
80 #define __ _masm->
81
82
83 static void select_different_registers(Register preserve,
84 Register extra,
85 Register &tmp1,
86 Register &tmp2) {
87 if (tmp1 == preserve) {
88 assert_different_registers(tmp1, tmp2, extra);
89 tmp1 = extra;
90 } else if (tmp2 == preserve) {
91 assert_different_registers(tmp1, tmp2, extra);
92 tmp2 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2);
95 }
96
97
98
99 static void select_different_registers(Register preserve,
100 Register extra,
101 Register &tmp1,
102 Register &tmp2,
103 Register &tmp3) {
104 if (tmp1 == preserve) {
105 assert_different_registers(tmp1, tmp2, tmp3, extra);
106 tmp1 = extra;
107 } else if (tmp2 == preserve) {
108 assert_different_registers(tmp1, tmp2, tmp3, extra);
109 tmp2 = extra;
110 } else if (tmp3 == preserve) {
111 assert_different_registers(tmp1, tmp2, tmp3, extra);
112 tmp3 = extra;
113 }
114 assert_different_registers(preserve, tmp1, tmp2, tmp3);
115 }
116
117
118
119 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
120 if (opr->is_constant()) {
121 LIR_Const* constant = opr->as_constant_ptr();
122 switch (constant->type()) {
123 case T_INT: {
124 return true;
125 }
126
127 default:
128 return false;
129 }
130 }
131 return false;
132 }
133
134
135 LIR_Opr LIR_Assembler::receiverOpr() {
136 return FrameMap::receiver_opr;
137 }
138
139 LIR_Opr LIR_Assembler::osrBufferPointer() {
140 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
141 }
142
143 //--------------fpu register translations-----------------------
144
145
146 address LIR_Assembler::float_constant(float f) {
147 address const_addr = __ float_constant(f);
148 if (const_addr == nullptr) {
149 bailout("const section overflow");
150 return __ code()->consts()->start();
151 } else {
152 return const_addr;
153 }
154 }
155
156
157 address LIR_Assembler::double_constant(double d) {
158 address const_addr = __ double_constant(d);
159 if (const_addr == nullptr) {
160 bailout("const section overflow");
161 return __ code()->consts()->start();
162 } else {
163 return const_addr;
164 }
165 }
166
167 #ifndef _LP64
168 void LIR_Assembler::fpop() {
169 __ fpop();
170 }
171
172 void LIR_Assembler::fxch(int i) {
173 __ fxch(i);
174 }
175
176 void LIR_Assembler::fld(int i) {
177 __ fld_s(i);
178 }
179
180 void LIR_Assembler::ffree(int i) {
181 __ ffree(i);
182 }
183 #endif // !_LP64
184
185 void LIR_Assembler::breakpoint() {
186 __ int3();
187 }
188
189 void LIR_Assembler::push(LIR_Opr opr) {
190 if (opr->is_single_cpu()) {
191 __ push_reg(opr->as_register());
192 } else if (opr->is_double_cpu()) {
193 NOT_LP64(__ push_reg(opr->as_register_hi()));
194 __ push_reg(opr->as_register_lo());
195 } else if (opr->is_stack()) {
196 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
197 } else if (opr->is_constant()) {
198 LIR_Const* const_opr = opr->as_constant_ptr();
199 if (const_opr->type() == T_OBJECT) {
200 __ push_oop(const_opr->as_jobject(), rscratch1);
201 } else if (const_opr->type() == T_INT) {
202 __ push_jint(const_opr->as_jint());
203 } else {
204 ShouldNotReachHere();
205 }
206
207 } else {
208 ShouldNotReachHere();
209 }
210 }
211
212 void LIR_Assembler::pop(LIR_Opr opr) {
213 if (opr->is_single_cpu()) {
214 __ pop_reg(opr->as_register());
215 } else {
216 ShouldNotReachHere();
217 }
218 }
219
220 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
221 return addr->base()->is_illegal() && addr->index()->is_illegal();
222 }
223
224 //-------------------------------------------
225
226 Address LIR_Assembler::as_Address(LIR_Address* addr) {
227 return as_Address(addr, rscratch1);
228 }
229
230 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
231 if (addr->base()->is_illegal()) {
232 assert(addr->index()->is_illegal(), "must be illegal too");
233 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
234 if (! __ reachable(laddr)) {
235 __ movptr(tmp, laddr.addr());
236 Address res(tmp, 0);
237 return res;
238 } else {
239 return __ as_Address(laddr);
240 }
241 }
242
243 Register base = addr->base()->as_pointer_register();
244
245 if (addr->index()->is_illegal()) {
246 return Address( base, addr->disp());
247 } else if (addr->index()->is_cpu_register()) {
248 Register index = addr->index()->as_pointer_register();
249 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
250 } else if (addr->index()->is_constant()) {
251 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
252 assert(Assembler::is_simm32(addr_offset), "must be");
253
254 return Address(base, addr_offset);
255 } else {
256 Unimplemented();
257 return Address();
258 }
259 }
260
261
262 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
263 Address base = as_Address(addr);
264 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
265 }
266
267
268 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
269 return as_Address(addr);
270 }
271
272
273 void LIR_Assembler::osr_entry() {
274 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
275 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
276 ValueStack* entry_state = osr_entry->state();
277 int number_of_locks = entry_state->locks_size();
278
279 // we jump here if osr happens with the interpreter
280 // state set up to continue at the beginning of the
281 // loop that triggered osr - in particular, we have
282 // the following registers setup:
283 //
284 // rcx: osr buffer
285 //
286
287 // build frame
288 ciMethod* m = compilation()->method();
289 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
290
291 // OSR buffer is
292 //
293 // locals[nlocals-1..0]
294 // monitors[0..number_of_locks]
295 //
296 // locals is a direct copy of the interpreter frame so in the osr buffer
297 // so first slot in the local array is the last local from the interpreter
298 // and last slot is local[0] (receiver) from the interpreter
299 //
300 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
301 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
302 // in the interpreter frame (the method lock if a sync method)
303
304 // Initialize monitors in the compiled activation.
305 // rcx: pointer to osr buffer
306 //
307 // All other registers are dead at this point and the locals will be
308 // copied into place by code emitted in the IR.
309
310 Register OSR_buf = osrBufferPointer()->as_pointer_register();
311 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
312 int monitor_offset = BytesPerWord * method()->max_locals() +
313 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
314 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
315 // the OSR buffer using 2 word entries: first the lock and then
316 // the oop.
317 for (int i = 0; i < number_of_locks; i++) {
318 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
319 #ifdef ASSERT
320 // verify the interpreter's monitor has a non-null object
321 {
322 Label L;
323 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD);
324 __ jcc(Assembler::notZero, L);
325 __ stop("locked object is null");
326 __ bind(L);
327 }
328 #endif
329 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
330 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
331 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
332 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
333 }
334 }
335 }
336
337
338 // inline cache check; done before the frame is built.
339 int LIR_Assembler::check_icache() {
340 return __ ic_check(CodeEntryAlignment);
341 }
342
343 void LIR_Assembler::clinit_barrier(ciMethod* method) {
344 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
345 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
346
347 Label L_skip_barrier;
348 Register klass = rscratch1;
349 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
350 assert(thread != noreg, "x86_32 not implemented");
351
352 __ mov_metadata(klass, method->holder()->constant_encoding());
353 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
354
355 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
356
357 __ bind(L_skip_barrier);
358 }
359
360 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
361 jobject o = nullptr;
362 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
363 __ movoop(reg, o);
364 patching_epilog(patch, lir_patch_normal, reg, info);
365 }
366
367 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
368 Metadata* o = nullptr;
369 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
370 __ mov_metadata(reg, o);
371 patching_epilog(patch, lir_patch_normal, reg, info);
372 }
373
374 // This specifies the rsp decrement needed to build the frame
375 int LIR_Assembler::initial_frame_size_in_bytes() const {
376 // if rounding, must let FrameMap know!
377
378 // The frame_map records size in slots (32bit word)
379
380 // subtract two words to account for return address and link
381 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
382 }
383
384
385 int LIR_Assembler::emit_exception_handler() {
386 // generate code for exception handler
387 address handler_base = __ start_a_stub(exception_handler_size());
388 if (handler_base == nullptr) {
389 // not enough space left for the handler
390 bailout("exception handler overflow");
391 return -1;
392 }
393
394 int offset = code_offset();
395
396 // the exception oop and pc are in rax, and rdx
397 // no other registers need to be preserved, so invalidate them
398 __ invalidate_registers(false, true, true, false, true, true);
399
400 // check that there is really an exception
401 __ verify_not_null_oop(rax);
402
403 // search an exception handler (rax: exception oop, rdx: throwing pc)
404 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
405 __ should_not_reach_here();
406 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
407 __ end_a_stub();
408
409 return offset;
410 }
411
412
413 // Emit the code to remove the frame from the stack in the exception
414 // unwind path.
415 int LIR_Assembler::emit_unwind_handler() {
416 #ifndef PRODUCT
417 if (CommentedAssembly) {
418 _masm->block_comment("Unwind handler");
419 }
420 #endif
421
422 int offset = code_offset();
423
424 // Fetch the exception from TLS and clear out exception related thread state
425 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
426 NOT_LP64(__ get_thread(thread));
427 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
428 __ movptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
429 __ movptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
430
431 __ bind(_unwind_handler_entry);
432 __ verify_not_null_oop(rax);
433 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
434 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
435 }
436
437 // Perform needed unlocking
438 MonitorExitStub* stub = nullptr;
439 if (method()->is_synchronized()) {
440 monitor_address(0, FrameMap::rax_opr);
441 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
442 if (LockingMode == LM_MONITOR) {
443 __ jmp(*stub->entry());
444 } else {
445 __ unlock_object(rdi, rsi, rax, *stub->entry());
446 }
447 __ bind(*stub->continuation());
448 }
449
450 if (compilation()->env()->dtrace_method_probes()) {
451 #ifdef _LP64
452 __ mov(rdi, r15_thread);
453 __ mov_metadata(rsi, method()->constant_encoding());
454 #else
455 __ get_thread(rax);
456 __ movptr(Address(rsp, 0), rax);
457 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding(), noreg);
458 #endif
459 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
460 }
461
462 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
463 __ mov(rax, rbx); // Restore the exception
464 }
465
466 // remove the activation and dispatch to the unwind handler
467 __ remove_frame(initial_frame_size_in_bytes());
468 __ jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
469
470 // Emit the slow path assembly
471 if (stub != nullptr) {
472 stub->emit_code(this);
473 }
474
475 return offset;
476 }
477
478
479 int LIR_Assembler::emit_deopt_handler() {
480 // generate code for exception handler
481 address handler_base = __ start_a_stub(deopt_handler_size());
482 if (handler_base == nullptr) {
483 // not enough space left for the handler
484 bailout("deopt handler overflow");
485 return -1;
486 }
487
488 int offset = code_offset();
489 InternalAddress here(__ pc());
490
491 __ pushptr(here.addr(), rscratch1);
492 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
493 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
494 __ end_a_stub();
495
496 return offset;
497 }
498
499 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
500 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
501 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
502 assert(result->fpu() == 0, "result must already be on TOS");
503 }
504
505 // Pop the stack before the safepoint code
506 __ remove_frame(initial_frame_size_in_bytes());
507
508 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
509 __ reserved_stack_check();
510 }
511
512 // Note: we do not need to round double result; float result has the right precision
513 // the poll sets the condition code, but no data registers
514
515 #ifdef _LP64
516 const Register thread = r15_thread;
517 #else
518 const Register thread = rbx;
519 __ get_thread(thread);
520 #endif
521 code_stub->set_safepoint_offset(__ offset());
522 __ relocate(relocInfo::poll_return_type);
523 __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */);
524 __ ret(0);
525 }
526
527
528 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
529 guarantee(info != nullptr, "Shouldn't be null");
530 int offset = __ offset();
531 #ifdef _LP64
532 const Register poll_addr = rscratch1;
533 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
534 #else
535 assert(tmp->is_cpu_register(), "needed");
536 const Register poll_addr = tmp->as_register();
537 __ get_thread(poll_addr);
538 __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset())));
539 #endif
540 add_debug_info_for_branch(info);
541 __ relocate(relocInfo::poll_type);
542 address pre_pc = __ pc();
543 __ testl(rax, Address(poll_addr, 0));
544 address post_pc = __ pc();
545 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
546 return offset;
547 }
548
549
550 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
551 if (from_reg != to_reg) __ mov(to_reg, from_reg);
552 }
553
554 void LIR_Assembler::swap_reg(Register a, Register b) {
555 __ xchgptr(a, b);
556 }
557
558
559 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
560 assert(src->is_constant(), "should not call otherwise");
561 assert(dest->is_register(), "should not call otherwise");
562 LIR_Const* c = src->as_constant_ptr();
563
564 switch (c->type()) {
565 case T_INT: {
566 assert(patch_code == lir_patch_none, "no patching handled here");
567 __ movl(dest->as_register(), c->as_jint());
568 break;
569 }
570
571 case T_ADDRESS: {
572 assert(patch_code == lir_patch_none, "no patching handled here");
573 __ movptr(dest->as_register(), c->as_jint());
574 break;
575 }
576
577 case T_LONG: {
578 assert(patch_code == lir_patch_none, "no patching handled here");
579 #ifdef _LP64
580 if (SCCache::is_on_for_write()) {
581 // SCA needs relocation info for card table base
582 address b = c->as_pointer();
583 if (is_card_table_address(b)) {
584 __ lea(dest->as_register_lo(), ExternalAddress(b));
585 break;
586 }
587 if (AOTRuntimeConstants::contains(b)) {
588 __ load_aotrc_address(dest->as_register_lo(), b);
589 break;
590 }
591 }
592 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
593 #else
594 __ movptr(dest->as_register_lo(), c->as_jint_lo());
595 __ movptr(dest->as_register_hi(), c->as_jint_hi());
596 #endif // _LP64
597 break;
598 }
599
600 case T_OBJECT: {
601 if (patch_code != lir_patch_none) {
602 jobject2reg_with_patching(dest->as_register(), info);
603 } else {
604 __ movoop(dest->as_register(), c->as_jobject());
605 }
606 break;
607 }
608
609 case T_METADATA: {
610 if (patch_code != lir_patch_none) {
611 klass2reg_with_patching(dest->as_register(), info);
612 } else {
613 __ mov_metadata(dest->as_register(), c->as_metadata());
614 }
615 break;
616 }
617
618 case T_FLOAT: {
619 if (dest->is_single_xmm()) {
620 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
621 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
622 } else {
623 __ movflt(dest->as_xmm_float_reg(),
624 InternalAddress(float_constant(c->as_jfloat())));
625 }
626 } else {
627 #ifndef _LP64
628 assert(dest->is_single_fpu(), "must be");
629 assert(dest->fpu_regnr() == 0, "dest must be TOS");
630 if (c->is_zero_float()) {
631 __ fldz();
632 } else if (c->is_one_float()) {
633 __ fld1();
634 } else {
635 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
636 }
637 #else
638 ShouldNotReachHere();
639 #endif // !_LP64
640 }
641 break;
642 }
643
644 case T_DOUBLE: {
645 if (dest->is_double_xmm()) {
646 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
647 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
648 } else {
649 __ movdbl(dest->as_xmm_double_reg(),
650 InternalAddress(double_constant(c->as_jdouble())));
651 }
652 } else {
653 #ifndef _LP64
654 assert(dest->is_double_fpu(), "must be");
655 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
656 if (c->is_zero_double()) {
657 __ fldz();
658 } else if (c->is_one_double()) {
659 __ fld1();
660 } else {
661 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
662 }
663 #else
664 ShouldNotReachHere();
665 #endif // !_LP64
666 }
667 break;
668 }
669
670 default:
671 ShouldNotReachHere();
672 }
673 }
674
675 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
676 assert(src->is_constant(), "should not call otherwise");
677 assert(dest->is_stack(), "should not call otherwise");
678 LIR_Const* c = src->as_constant_ptr();
679
680 switch (c->type()) {
681 case T_INT: // fall through
682 case T_FLOAT:
683 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
684 break;
685
686 case T_ADDRESS:
687 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
688 break;
689
690 case T_OBJECT:
691 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1);
692 break;
693
694 case T_LONG: // fall through
695 case T_DOUBLE:
696 #ifdef _LP64
697 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
698 lo_word_offset_in_bytes),
699 (intptr_t)c->as_jlong_bits(),
700 rscratch1);
701 #else
702 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
703 lo_word_offset_in_bytes), c->as_jint_lo_bits());
704 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
705 hi_word_offset_in_bytes), c->as_jint_hi_bits());
706 #endif // _LP64
707 break;
708
709 default:
710 ShouldNotReachHere();
711 }
712 }
713
714 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
715 assert(src->is_constant(), "should not call otherwise");
716 assert(dest->is_address(), "should not call otherwise");
717 LIR_Const* c = src->as_constant_ptr();
718 LIR_Address* addr = dest->as_address_ptr();
719
720 int null_check_here = code_offset();
721 switch (type) {
722 case T_INT: // fall through
723 case T_FLOAT:
724 __ movl(as_Address(addr), c->as_jint_bits());
725 break;
726
727 case T_ADDRESS:
728 __ movptr(as_Address(addr), c->as_jint_bits());
729 break;
730
731 case T_OBJECT: // fall through
732 case T_ARRAY:
733 if (c->as_jobject() == nullptr) {
734 if (UseCompressedOops && !wide) {
735 __ movl(as_Address(addr), NULL_WORD);
736 } else {
737 #ifdef _LP64
738 __ xorptr(rscratch1, rscratch1);
739 null_check_here = code_offset();
740 __ movptr(as_Address(addr), rscratch1);
741 #else
742 __ movptr(as_Address(addr), NULL_WORD);
743 #endif
744 }
745 } else {
746 if (is_literal_address(addr)) {
747 ShouldNotReachHere();
748 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1);
749 } else {
750 #ifdef _LP64
751 __ movoop(rscratch1, c->as_jobject());
752 if (UseCompressedOops && !wide) {
753 __ encode_heap_oop(rscratch1);
754 null_check_here = code_offset();
755 __ movl(as_Address_lo(addr), rscratch1);
756 } else {
757 null_check_here = code_offset();
758 __ movptr(as_Address_lo(addr), rscratch1);
759 }
760 #else
761 __ movoop(as_Address(addr), c->as_jobject(), noreg);
762 #endif
763 }
764 }
765 break;
766
767 case T_LONG: // fall through
768 case T_DOUBLE:
769 #ifdef _LP64
770 if (is_literal_address(addr)) {
771 ShouldNotReachHere();
772 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
773 } else {
774 __ movptr(r10, (intptr_t)c->as_jlong_bits());
775 null_check_here = code_offset();
776 __ movptr(as_Address_lo(addr), r10);
777 }
778 #else
779 // Always reachable in 32bit so this doesn't produce useless move literal
780 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
781 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
782 #endif // _LP64
783 break;
784
785 case T_BOOLEAN: // fall through
786 case T_BYTE:
787 __ movb(as_Address(addr), c->as_jint() & 0xFF);
788 break;
789
790 case T_CHAR: // fall through
791 case T_SHORT:
792 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
793 break;
794
795 default:
796 ShouldNotReachHere();
797 };
798
799 if (info != nullptr) {
800 add_debug_info_for_null_check(null_check_here, info);
801 }
802 }
803
804
805 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
806 assert(src->is_register(), "should not call otherwise");
807 assert(dest->is_register(), "should not call otherwise");
808
809 // move between cpu-registers
810 if (dest->is_single_cpu()) {
811 #ifdef _LP64
812 if (src->type() == T_LONG) {
813 // Can do LONG -> OBJECT
814 move_regs(src->as_register_lo(), dest->as_register());
815 return;
816 }
817 #endif
818 assert(src->is_single_cpu(), "must match");
819 if (src->type() == T_OBJECT) {
820 __ verify_oop(src->as_register());
821 }
822 move_regs(src->as_register(), dest->as_register());
823
824 } else if (dest->is_double_cpu()) {
825 #ifdef _LP64
826 if (is_reference_type(src->type())) {
827 // Surprising to me but we can see move of a long to t_object
828 __ verify_oop(src->as_register());
829 move_regs(src->as_register(), dest->as_register_lo());
830 return;
831 }
832 #endif
833 assert(src->is_double_cpu(), "must match");
834 Register f_lo = src->as_register_lo();
835 Register f_hi = src->as_register_hi();
836 Register t_lo = dest->as_register_lo();
837 Register t_hi = dest->as_register_hi();
838 #ifdef _LP64
839 assert(f_hi == f_lo, "must be same");
840 assert(t_hi == t_lo, "must be same");
841 move_regs(f_lo, t_lo);
842 #else
843 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
844
845
846 if (f_lo == t_hi && f_hi == t_lo) {
847 swap_reg(f_lo, f_hi);
848 } else if (f_hi == t_lo) {
849 assert(f_lo != t_hi, "overwriting register");
850 move_regs(f_hi, t_hi);
851 move_regs(f_lo, t_lo);
852 } else {
853 assert(f_hi != t_lo, "overwriting register");
854 move_regs(f_lo, t_lo);
855 move_regs(f_hi, t_hi);
856 }
857 #endif // LP64
858
859 #ifndef _LP64
860 // special moves from fpu-register to xmm-register
861 // necessary for method results
862 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
863 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
864 __ fld_s(Address(rsp, 0));
865 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
866 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
867 __ fld_d(Address(rsp, 0));
868 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
869 __ fstp_s(Address(rsp, 0));
870 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
871 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
872 __ fstp_d(Address(rsp, 0));
873 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
874 #endif // !_LP64
875
876 // move between xmm-registers
877 } else if (dest->is_single_xmm()) {
878 assert(src->is_single_xmm(), "must match");
879 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
880 } else if (dest->is_double_xmm()) {
881 assert(src->is_double_xmm(), "must match");
882 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
883
884 #ifndef _LP64
885 // move between fpu-registers (no instruction necessary because of fpu-stack)
886 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
887 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
888 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
889 #endif // !_LP64
890
891 } else {
892 ShouldNotReachHere();
893 }
894 }
895
896 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
897 assert(src->is_register(), "should not call otherwise");
898 assert(dest->is_stack(), "should not call otherwise");
899
900 if (src->is_single_cpu()) {
901 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
902 if (is_reference_type(type)) {
903 __ verify_oop(src->as_register());
904 __ movptr (dst, src->as_register());
905 } else if (type == T_METADATA || type == T_ADDRESS) {
906 __ movptr (dst, src->as_register());
907 } else {
908 __ movl (dst, src->as_register());
909 }
910
911 } else if (src->is_double_cpu()) {
912 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
913 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
914 __ movptr (dstLO, src->as_register_lo());
915 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
916
917 } else if (src->is_single_xmm()) {
918 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
919 __ movflt(dst_addr, src->as_xmm_float_reg());
920
921 } else if (src->is_double_xmm()) {
922 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
923 __ movdbl(dst_addr, src->as_xmm_double_reg());
924
925 #ifndef _LP64
926 } else if (src->is_single_fpu()) {
927 assert(src->fpu_regnr() == 0, "argument must be on TOS");
928 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
929 if (pop_fpu_stack) __ fstp_s (dst_addr);
930 else __ fst_s (dst_addr);
931
932 } else if (src->is_double_fpu()) {
933 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
934 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
935 if (pop_fpu_stack) __ fstp_d (dst_addr);
936 else __ fst_d (dst_addr);
937 #endif // !_LP64
938
939 } else {
940 ShouldNotReachHere();
941 }
942 }
943
944
945 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
946 LIR_Address* to_addr = dest->as_address_ptr();
947 PatchingStub* patch = nullptr;
948 Register compressed_src = rscratch1;
949
950 if (is_reference_type(type)) {
951 __ verify_oop(src->as_register());
952 #ifdef _LP64
953 if (UseCompressedOops && !wide) {
954 __ movptr(compressed_src, src->as_register());
955 __ encode_heap_oop(compressed_src);
956 if (patch_code != lir_patch_none) {
957 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
958 }
959 }
960 #endif
961 }
962
963 if (patch_code != lir_patch_none) {
964 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
965 Address toa = as_Address(to_addr);
966 assert(toa.disp() != 0, "must have");
967 }
968
969 int null_check_here = code_offset();
970 switch (type) {
971 case T_FLOAT: {
972 #ifdef _LP64
973 assert(src->is_single_xmm(), "not a float");
974 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
975 #else
976 if (src->is_single_xmm()) {
977 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
978 } else {
979 assert(src->is_single_fpu(), "must be");
980 assert(src->fpu_regnr() == 0, "argument must be on TOS");
981 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
982 else __ fst_s (as_Address(to_addr));
983 }
984 #endif // _LP64
985 break;
986 }
987
988 case T_DOUBLE: {
989 #ifdef _LP64
990 assert(src->is_double_xmm(), "not a double");
991 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
992 #else
993 if (src->is_double_xmm()) {
994 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
995 } else {
996 assert(src->is_double_fpu(), "must be");
997 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
998 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
999 else __ fst_d (as_Address(to_addr));
1000 }
1001 #endif // _LP64
1002 break;
1003 }
1004
1005 case T_ARRAY: // fall through
1006 case T_OBJECT: // fall through
1007 if (UseCompressedOops && !wide) {
1008 __ movl(as_Address(to_addr), compressed_src);
1009 } else {
1010 __ movptr(as_Address(to_addr), src->as_register());
1011 }
1012 break;
1013 case T_METADATA:
1014 // We get here to store a method pointer to the stack to pass to
1015 // a dtrace runtime call. This can't work on 64 bit with
1016 // compressed klass ptrs: T_METADATA can be a compressed klass
1017 // ptr or a 64 bit method pointer.
1018 LP64_ONLY(ShouldNotReachHere());
1019 __ movptr(as_Address(to_addr), src->as_register());
1020 break;
1021 case T_ADDRESS:
1022 __ movptr(as_Address(to_addr), src->as_register());
1023 break;
1024 case T_INT:
1025 __ movl(as_Address(to_addr), src->as_register());
1026 break;
1027
1028 case T_LONG: {
1029 Register from_lo = src->as_register_lo();
1030 Register from_hi = src->as_register_hi();
1031 #ifdef _LP64
1032 __ movptr(as_Address_lo(to_addr), from_lo);
1033 #else
1034 Register base = to_addr->base()->as_register();
1035 Register index = noreg;
1036 if (to_addr->index()->is_register()) {
1037 index = to_addr->index()->as_register();
1038 }
1039 if (base == from_lo || index == from_lo) {
1040 assert(base != from_hi, "can't be");
1041 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1042 __ movl(as_Address_hi(to_addr), from_hi);
1043 if (patch != nullptr) {
1044 patching_epilog(patch, lir_patch_high, base, info);
1045 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1046 patch_code = lir_patch_low;
1047 }
1048 __ movl(as_Address_lo(to_addr), from_lo);
1049 } else {
1050 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1051 __ movl(as_Address_lo(to_addr), from_lo);
1052 if (patch != nullptr) {
1053 patching_epilog(patch, lir_patch_low, base, info);
1054 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1055 patch_code = lir_patch_high;
1056 }
1057 __ movl(as_Address_hi(to_addr), from_hi);
1058 }
1059 #endif // _LP64
1060 break;
1061 }
1062
1063 case T_BYTE: // fall through
1064 case T_BOOLEAN: {
1065 Register src_reg = src->as_register();
1066 Address dst_addr = as_Address(to_addr);
1067 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1068 __ movb(dst_addr, src_reg);
1069 break;
1070 }
1071
1072 case T_CHAR: // fall through
1073 case T_SHORT:
1074 __ movw(as_Address(to_addr), src->as_register());
1075 break;
1076
1077 default:
1078 ShouldNotReachHere();
1079 }
1080 if (info != nullptr) {
1081 add_debug_info_for_null_check(null_check_here, info);
1082 }
1083
1084 if (patch_code != lir_patch_none) {
1085 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1086 }
1087 }
1088
1089
1090 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1091 assert(src->is_stack(), "should not call otherwise");
1092 assert(dest->is_register(), "should not call otherwise");
1093
1094 if (dest->is_single_cpu()) {
1095 if (is_reference_type(type)) {
1096 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1097 __ verify_oop(dest->as_register());
1098 } else if (type == T_METADATA || type == T_ADDRESS) {
1099 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1100 } else {
1101 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1102 }
1103
1104 } else if (dest->is_double_cpu()) {
1105 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1106 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1107 __ movptr(dest->as_register_lo(), src_addr_LO);
1108 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1109
1110 } else if (dest->is_single_xmm()) {
1111 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1112 __ movflt(dest->as_xmm_float_reg(), src_addr);
1113
1114 } else if (dest->is_double_xmm()) {
1115 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1116 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1117
1118 #ifndef _LP64
1119 } else if (dest->is_single_fpu()) {
1120 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1121 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1122 __ fld_s(src_addr);
1123
1124 } else if (dest->is_double_fpu()) {
1125 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1126 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1127 __ fld_d(src_addr);
1128 #endif // _LP64
1129
1130 } else {
1131 ShouldNotReachHere();
1132 }
1133 }
1134
1135
1136 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1137 if (src->is_single_stack()) {
1138 if (is_reference_type(type)) {
1139 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1140 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1141 } else {
1142 #ifndef _LP64
1143 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1144 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1145 #else
1146 //no pushl on 64bits
1147 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1148 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1149 #endif
1150 }
1151
1152 } else if (src->is_double_stack()) {
1153 #ifdef _LP64
1154 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1155 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1156 #else
1157 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1158 // push and pop the part at src + wordSize, adding wordSize for the previous push
1159 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1160 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1161 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1162 #endif // _LP64
1163
1164 } else {
1165 ShouldNotReachHere();
1166 }
1167 }
1168
1169
1170 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1171 assert(src->is_address(), "should not call otherwise");
1172 assert(dest->is_register(), "should not call otherwise");
1173
1174 LIR_Address* addr = src->as_address_ptr();
1175 Address from_addr = as_Address(addr);
1176
1177 if (addr->base()->type() == T_OBJECT) {
1178 __ verify_oop(addr->base()->as_pointer_register());
1179 }
1180
1181 switch (type) {
1182 case T_BOOLEAN: // fall through
1183 case T_BYTE: // fall through
1184 case T_CHAR: // fall through
1185 case T_SHORT:
1186 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1187 // on pre P6 processors we may get partial register stalls
1188 // so blow away the value of to_rinfo before loading a
1189 // partial word into it. Do it here so that it precedes
1190 // the potential patch point below.
1191 __ xorptr(dest->as_register(), dest->as_register());
1192 }
1193 break;
1194 default:
1195 break;
1196 }
1197
1198 PatchingStub* patch = nullptr;
1199 if (patch_code != lir_patch_none) {
1200 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1201 assert(from_addr.disp() != 0, "must have");
1202 }
1203 if (info != nullptr) {
1204 add_debug_info_for_null_check_here(info);
1205 }
1206
1207 switch (type) {
1208 case T_FLOAT: {
1209 if (dest->is_single_xmm()) {
1210 __ movflt(dest->as_xmm_float_reg(), from_addr);
1211 } else {
1212 #ifndef _LP64
1213 assert(dest->is_single_fpu(), "must be");
1214 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1215 __ fld_s(from_addr);
1216 #else
1217 ShouldNotReachHere();
1218 #endif // !LP64
1219 }
1220 break;
1221 }
1222
1223 case T_DOUBLE: {
1224 if (dest->is_double_xmm()) {
1225 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1226 } else {
1227 #ifndef _LP64
1228 assert(dest->is_double_fpu(), "must be");
1229 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1230 __ fld_d(from_addr);
1231 #else
1232 ShouldNotReachHere();
1233 #endif // !LP64
1234 }
1235 break;
1236 }
1237
1238 case T_OBJECT: // fall through
1239 case T_ARRAY: // fall through
1240 if (UseCompressedOops && !wide) {
1241 __ movl(dest->as_register(), from_addr);
1242 } else {
1243 __ movptr(dest->as_register(), from_addr);
1244 }
1245 break;
1246
1247 case T_ADDRESS:
1248 __ movptr(dest->as_register(), from_addr);
1249 break;
1250 case T_INT:
1251 __ movl(dest->as_register(), from_addr);
1252 break;
1253
1254 case T_LONG: {
1255 Register to_lo = dest->as_register_lo();
1256 Register to_hi = dest->as_register_hi();
1257 #ifdef _LP64
1258 __ movptr(to_lo, as_Address_lo(addr));
1259 #else
1260 Register base = addr->base()->as_register();
1261 Register index = noreg;
1262 if (addr->index()->is_register()) {
1263 index = addr->index()->as_register();
1264 }
1265 if ((base == to_lo && index == to_hi) ||
1266 (base == to_hi && index == to_lo)) {
1267 // addresses with 2 registers are only formed as a result of
1268 // array access so this code will never have to deal with
1269 // patches or null checks.
1270 assert(info == nullptr && patch == nullptr, "must be");
1271 __ lea(to_hi, as_Address(addr));
1272 __ movl(to_lo, Address(to_hi, 0));
1273 __ movl(to_hi, Address(to_hi, BytesPerWord));
1274 } else if (base == to_lo || index == to_lo) {
1275 assert(base != to_hi, "can't be");
1276 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1277 __ movl(to_hi, as_Address_hi(addr));
1278 if (patch != nullptr) {
1279 patching_epilog(patch, lir_patch_high, base, info);
1280 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1281 patch_code = lir_patch_low;
1282 }
1283 __ movl(to_lo, as_Address_lo(addr));
1284 } else {
1285 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1286 __ movl(to_lo, as_Address_lo(addr));
1287 if (patch != nullptr) {
1288 patching_epilog(patch, lir_patch_low, base, info);
1289 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1290 patch_code = lir_patch_high;
1291 }
1292 __ movl(to_hi, as_Address_hi(addr));
1293 }
1294 #endif // _LP64
1295 break;
1296 }
1297
1298 case T_BOOLEAN: // fall through
1299 case T_BYTE: {
1300 Register dest_reg = dest->as_register();
1301 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1302 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1303 __ movsbl(dest_reg, from_addr);
1304 } else {
1305 __ movb(dest_reg, from_addr);
1306 __ shll(dest_reg, 24);
1307 __ sarl(dest_reg, 24);
1308 }
1309 break;
1310 }
1311
1312 case T_CHAR: {
1313 Register dest_reg = dest->as_register();
1314 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1315 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1316 __ movzwl(dest_reg, from_addr);
1317 } else {
1318 __ movw(dest_reg, from_addr);
1319 }
1320 break;
1321 }
1322
1323 case T_SHORT: {
1324 Register dest_reg = dest->as_register();
1325 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1326 __ movswl(dest_reg, from_addr);
1327 } else {
1328 __ movw(dest_reg, from_addr);
1329 __ shll(dest_reg, 16);
1330 __ sarl(dest_reg, 16);
1331 }
1332 break;
1333 }
1334
1335 default:
1336 ShouldNotReachHere();
1337 }
1338
1339 if (patch != nullptr) {
1340 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1341 }
1342
1343 if (is_reference_type(type)) {
1344 #ifdef _LP64
1345 if (UseCompressedOops && !wide) {
1346 __ decode_heap_oop(dest->as_register());
1347 }
1348 #endif
1349
1350 if (!(UseZGC && !ZGenerational)) {
1351 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1352 __ verify_oop(dest->as_register());
1353 }
1354 }
1355 }
1356
1357
1358 NEEDS_CLEANUP; // This could be static?
1359 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1360 int elem_size = type2aelembytes(type);
1361 switch (elem_size) {
1362 case 1: return Address::times_1;
1363 case 2: return Address::times_2;
1364 case 4: return Address::times_4;
1365 case 8: return Address::times_8;
1366 }
1367 ShouldNotReachHere();
1368 return Address::no_scale;
1369 }
1370
1371
1372 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1373 switch (op->code()) {
1374 case lir_idiv:
1375 case lir_irem:
1376 arithmetic_idiv(op->code(),
1377 op->in_opr1(),
1378 op->in_opr2(),
1379 op->in_opr3(),
1380 op->result_opr(),
1381 op->info());
1382 break;
1383 case lir_fmad:
1384 __ fmad(op->result_opr()->as_xmm_double_reg(),
1385 op->in_opr1()->as_xmm_double_reg(),
1386 op->in_opr2()->as_xmm_double_reg(),
1387 op->in_opr3()->as_xmm_double_reg());
1388 break;
1389 case lir_fmaf:
1390 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1391 op->in_opr1()->as_xmm_float_reg(),
1392 op->in_opr2()->as_xmm_float_reg(),
1393 op->in_opr3()->as_xmm_float_reg());
1394 break;
1395 default: ShouldNotReachHere(); break;
1396 }
1397 }
1398
1399 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1400 #ifdef ASSERT
1401 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1402 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1403 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1404 #endif
1405
1406 if (op->cond() == lir_cond_always) {
1407 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1408 __ jmp (*(op->label()));
1409 } else {
1410 Assembler::Condition acond = Assembler::zero;
1411 if (op->code() == lir_cond_float_branch) {
1412 assert(op->ublock() != nullptr, "must have unordered successor");
1413 __ jcc(Assembler::parity, *(op->ublock()->label()));
1414 switch(op->cond()) {
1415 case lir_cond_equal: acond = Assembler::equal; break;
1416 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1417 case lir_cond_less: acond = Assembler::below; break;
1418 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1419 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1420 case lir_cond_greater: acond = Assembler::above; break;
1421 default: ShouldNotReachHere();
1422 }
1423 } else {
1424 switch (op->cond()) {
1425 case lir_cond_equal: acond = Assembler::equal; break;
1426 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1427 case lir_cond_less: acond = Assembler::less; break;
1428 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1429 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1430 case lir_cond_greater: acond = Assembler::greater; break;
1431 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1432 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1433 default: ShouldNotReachHere();
1434 }
1435 }
1436 __ jcc(acond,*(op->label()));
1437 }
1438 }
1439
1440 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1441 LIR_Opr src = op->in_opr();
1442 LIR_Opr dest = op->result_opr();
1443
1444 switch (op->bytecode()) {
1445 case Bytecodes::_i2l:
1446 #ifdef _LP64
1447 __ movl2ptr(dest->as_register_lo(), src->as_register());
1448 #else
1449 move_regs(src->as_register(), dest->as_register_lo());
1450 move_regs(src->as_register(), dest->as_register_hi());
1451 __ sarl(dest->as_register_hi(), 31);
1452 #endif // LP64
1453 break;
1454
1455 case Bytecodes::_l2i:
1456 #ifdef _LP64
1457 __ movl(dest->as_register(), src->as_register_lo());
1458 #else
1459 move_regs(src->as_register_lo(), dest->as_register());
1460 #endif
1461 break;
1462
1463 case Bytecodes::_i2b:
1464 move_regs(src->as_register(), dest->as_register());
1465 __ sign_extend_byte(dest->as_register());
1466 break;
1467
1468 case Bytecodes::_i2c:
1469 move_regs(src->as_register(), dest->as_register());
1470 __ andl(dest->as_register(), 0xFFFF);
1471 break;
1472
1473 case Bytecodes::_i2s:
1474 move_regs(src->as_register(), dest->as_register());
1475 __ sign_extend_short(dest->as_register());
1476 break;
1477
1478
1479 #ifdef _LP64
1480 case Bytecodes::_f2d:
1481 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1482 break;
1483
1484 case Bytecodes::_d2f:
1485 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1486 break;
1487
1488 case Bytecodes::_i2f:
1489 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1490 break;
1491
1492 case Bytecodes::_i2d:
1493 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1494 break;
1495
1496 case Bytecodes::_l2f:
1497 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1498 break;
1499
1500 case Bytecodes::_l2d:
1501 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1502 break;
1503
1504 case Bytecodes::_f2i:
1505 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1506 break;
1507
1508 case Bytecodes::_d2i:
1509 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1510 break;
1511
1512 case Bytecodes::_f2l:
1513 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1514 break;
1515
1516 case Bytecodes::_d2l:
1517 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1518 break;
1519 #else
1520 case Bytecodes::_f2d:
1521 case Bytecodes::_d2f:
1522 if (dest->is_single_xmm()) {
1523 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1524 } else if (dest->is_double_xmm()) {
1525 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1526 } else {
1527 assert(src->fpu() == dest->fpu(), "register must be equal");
1528 // do nothing (float result is rounded later through spilling)
1529 }
1530 break;
1531
1532 case Bytecodes::_i2f:
1533 case Bytecodes::_i2d:
1534 if (dest->is_single_xmm()) {
1535 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1536 } else if (dest->is_double_xmm()) {
1537 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1538 } else {
1539 assert(dest->fpu() == 0, "result must be on TOS");
1540 __ movl(Address(rsp, 0), src->as_register());
1541 __ fild_s(Address(rsp, 0));
1542 }
1543 break;
1544
1545 case Bytecodes::_l2f:
1546 case Bytecodes::_l2d:
1547 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1548 assert(dest->fpu() == 0, "result must be on TOS");
1549 __ movptr(Address(rsp, 0), src->as_register_lo());
1550 __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1551 __ fild_d(Address(rsp, 0));
1552 // float result is rounded later through spilling
1553 break;
1554
1555 case Bytecodes::_f2i:
1556 case Bytecodes::_d2i:
1557 if (src->is_single_xmm()) {
1558 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1559 } else if (src->is_double_xmm()) {
1560 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1561 } else {
1562 assert(src->fpu() == 0, "input must be on TOS");
1563 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc()));
1564 __ fist_s(Address(rsp, 0));
1565 __ movl(dest->as_register(), Address(rsp, 0));
1566 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
1567 }
1568 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1569 assert(op->stub() != nullptr, "stub required");
1570 __ cmpl(dest->as_register(), 0x80000000);
1571 __ jcc(Assembler::equal, *op->stub()->entry());
1572 __ bind(*op->stub()->continuation());
1573 break;
1574
1575 case Bytecodes::_f2l:
1576 case Bytecodes::_d2l:
1577 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1578 assert(src->fpu() == 0, "input must be on TOS");
1579 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1580
1581 // instruction sequence too long to inline it here
1582 {
1583 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::fpu2long_stub_id)));
1584 }
1585 break;
1586 #endif // _LP64
1587
1588 default: ShouldNotReachHere();
1589 }
1590 }
1591
1592 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1593 if (op->init_check()) {
1594 add_debug_info_for_null_check_here(op->stub()->info());
1595 // init_state needs acquire, but x86 is TSO, and so we are already good.
1596 __ cmpb(Address(op->klass()->as_register(),
1597 InstanceKlass::init_state_offset()),
1598 InstanceKlass::fully_initialized);
1599 __ jcc(Assembler::notEqual, *op->stub()->entry());
1600 }
1601 __ allocate_object(op->obj()->as_register(),
1602 op->tmp1()->as_register(),
1603 op->tmp2()->as_register(),
1604 op->header_size(),
1605 op->object_size(),
1606 op->klass()->as_register(),
1607 *op->stub()->entry());
1608 __ bind(*op->stub()->continuation());
1609 }
1610
1611 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1612 Register len = op->len()->as_register();
1613 LP64_ONLY( __ movslq(len, len); )
1614
1615 if (UseSlowPath ||
1616 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1617 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1618 __ jmp(*op->stub()->entry());
1619 } else {
1620 Register tmp1 = op->tmp1()->as_register();
1621 Register tmp2 = op->tmp2()->as_register();
1622 Register tmp3 = op->tmp3()->as_register();
1623 if (len == tmp1) {
1624 tmp1 = tmp3;
1625 } else if (len == tmp2) {
1626 tmp2 = tmp3;
1627 } else if (len == tmp3) {
1628 // everything is ok
1629 } else {
1630 __ mov(tmp3, len);
1631 }
1632 __ allocate_array(op->obj()->as_register(),
1633 len,
1634 tmp1,
1635 tmp2,
1636 arrayOopDesc::base_offset_in_bytes(op->type()),
1637 array_element_size(op->type()),
1638 op->klass()->as_register(),
1639 *op->stub()->entry(),
1640 op->zero_array());
1641 }
1642 __ bind(*op->stub()->continuation());
1643 }
1644
1645 void LIR_Assembler::type_profile_helper(Register mdo,
1646 ciMethodData *md, ciProfileData *data,
1647 Register recv, Label* update_done) {
1648 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1649 Label next_test;
1650 // See if the receiver is receiver[n].
1651 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1652 __ jccb(Assembler::notEqual, next_test);
1653 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1654 __ addptr(data_addr, DataLayout::counter_increment);
1655 __ jmp(*update_done);
1656 __ bind(next_test);
1657 }
1658
1659 // Didn't find receiver; find next empty slot and fill it in
1660 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1661 Label next_test;
1662 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1663 __ cmpptr(recv_addr, NULL_WORD);
1664 __ jccb(Assembler::notEqual, next_test);
1665 __ movptr(recv_addr, recv);
1666 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1667 __ jmp(*update_done);
1668 __ bind(next_test);
1669 }
1670 }
1671
1672 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1673 // we always need a stub for the failure case.
1674 CodeStub* stub = op->stub();
1675 Register obj = op->object()->as_register();
1676 Register k_RInfo = op->tmp1()->as_register();
1677 Register klass_RInfo = op->tmp2()->as_register();
1678 Register dst = op->result_opr()->as_register();
1679 ciKlass* k = op->klass();
1680 Register Rtmp1 = noreg;
1681 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1682
1683 // check if it needs to be profiled
1684 ciMethodData* md = nullptr;
1685 ciProfileData* data = nullptr;
1686
1687 if (op->should_profile()) {
1688 ciMethod* method = op->profiled_method();
1689 assert(method != nullptr, "Should have method");
1690 int bci = op->profiled_bci();
1691 md = method->method_data_or_null();
1692 assert(md != nullptr, "Sanity");
1693 data = md->bci_to_data(bci);
1694 assert(data != nullptr, "need data for type check");
1695 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1696 }
1697 Label* success_target = success;
1698 Label* failure_target = failure;
1699
1700 if (obj == k_RInfo) {
1701 k_RInfo = dst;
1702 } else if (obj == klass_RInfo) {
1703 klass_RInfo = dst;
1704 }
1705 if (k->is_loaded() && !UseCompressedClassPointers) {
1706 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1707 } else {
1708 Rtmp1 = op->tmp3()->as_register();
1709 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1710 }
1711
1712 assert_different_registers(obj, k_RInfo, klass_RInfo);
1713
1714 __ testptr(obj, obj);
1715 if (op->should_profile()) {
1716 Label not_null;
1717 Register mdo = klass_RInfo;
1718 __ mov_metadata(mdo, md->constant_encoding());
1719 __ jccb(Assembler::notEqual, not_null);
1720 // Object is null; update MDO and exit
1721 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1722 int header_bits = BitData::null_seen_byte_constant();
1723 __ orb(data_addr, header_bits);
1724 __ jmp(*obj_is_null);
1725 __ bind(not_null);
1726
1727 Label update_done;
1728 Register recv = k_RInfo;
1729 __ load_klass(recv, obj, tmp_load_klass);
1730 type_profile_helper(mdo, md, data, recv, &update_done);
1731
1732 Address nonprofiled_receiver_count_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1733 __ addptr(nonprofiled_receiver_count_addr, DataLayout::counter_increment);
1734
1735 __ bind(update_done);
1736 } else {
1737 __ jcc(Assembler::equal, *obj_is_null);
1738 }
1739
1740 if (!k->is_loaded()) {
1741 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1742 } else {
1743 #ifdef _LP64
1744 __ mov_metadata(k_RInfo, k->constant_encoding());
1745 #endif // _LP64
1746 }
1747 __ verify_oop(obj);
1748
1749 if (op->fast_check()) {
1750 // get object class
1751 // not a safepoint as obj null check happens earlier
1752 #ifdef _LP64
1753 if (UseCompressedClassPointers) {
1754 __ load_klass(Rtmp1, obj, tmp_load_klass);
1755 __ cmpptr(k_RInfo, Rtmp1);
1756 } else {
1757 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1758 }
1759 #else
1760 if (k->is_loaded()) {
1761 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1762 } else {
1763 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1764 }
1765 #endif
1766 __ jcc(Assembler::notEqual, *failure_target);
1767 // successful cast, fall through to profile or jump
1768 } else {
1769 // get object class
1770 // not a safepoint as obj null check happens earlier
1771 __ load_klass(klass_RInfo, obj, tmp_load_klass);
1772 if (k->is_loaded()) {
1773 // See if we get an immediate positive hit
1774 #ifdef _LP64
1775 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1776 #else
1777 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1778 #endif // _LP64
1779 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1780 __ jcc(Assembler::notEqual, *failure_target);
1781 // successful cast, fall through to profile or jump
1782 } else {
1783 // See if we get an immediate positive hit
1784 __ jcc(Assembler::equal, *success_target);
1785 // check for self
1786 #ifdef _LP64
1787 __ cmpptr(klass_RInfo, k_RInfo);
1788 #else
1789 __ cmpklass(klass_RInfo, k->constant_encoding());
1790 #endif // _LP64
1791 __ jcc(Assembler::equal, *success_target);
1792
1793 __ push(klass_RInfo);
1794 #ifdef _LP64
1795 __ push(k_RInfo);
1796 #else
1797 __ pushklass(k->constant_encoding(), noreg);
1798 #endif // _LP64
1799 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1800 __ pop(klass_RInfo);
1801 __ pop(klass_RInfo);
1802 // result is a boolean
1803 __ testl(klass_RInfo, klass_RInfo);
1804 __ jcc(Assembler::equal, *failure_target);
1805 // successful cast, fall through to profile or jump
1806 }
1807 } else {
1808 // perform the fast part of the checking logic
1809 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1810 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1811 __ push(klass_RInfo);
1812 __ push(k_RInfo);
1813 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1814 __ pop(klass_RInfo);
1815 __ pop(k_RInfo);
1816 // result is a boolean
1817 __ testl(k_RInfo, k_RInfo);
1818 __ jcc(Assembler::equal, *failure_target);
1819 // successful cast, fall through to profile or jump
1820 }
1821 }
1822 __ jmp(*success);
1823 }
1824
1825
1826 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1827 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1828 LIR_Code code = op->code();
1829 if (code == lir_store_check) {
1830 Register value = op->object()->as_register();
1831 Register array = op->array()->as_register();
1832 Register k_RInfo = op->tmp1()->as_register();
1833 Register klass_RInfo = op->tmp2()->as_register();
1834 Register Rtmp1 = op->tmp3()->as_register();
1835
1836 CodeStub* stub = op->stub();
1837
1838 // check if it needs to be profiled
1839 ciMethodData* md = nullptr;
1840 ciProfileData* data = nullptr;
1841
1842 if (op->should_profile()) {
1843 ciMethod* method = op->profiled_method();
1844 assert(method != nullptr, "Should have method");
1845 int bci = op->profiled_bci();
1846 md = method->method_data_or_null();
1847 assert(md != nullptr, "Sanity");
1848 data = md->bci_to_data(bci);
1849 assert(data != nullptr, "need data for type check");
1850 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1851 }
1852 Label done;
1853 Label* success_target = &done;
1854 Label* failure_target = stub->entry();
1855
1856 __ testptr(value, value);
1857 if (op->should_profile()) {
1858 Label not_null;
1859 Register mdo = klass_RInfo;
1860 __ mov_metadata(mdo, md->constant_encoding());
1861 __ jccb(Assembler::notEqual, not_null);
1862 // Object is null; update MDO and exit
1863 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1864 int header_bits = BitData::null_seen_byte_constant();
1865 __ orb(data_addr, header_bits);
1866 __ jmp(done);
1867 __ bind(not_null);
1868
1869 Label update_done;
1870 Register recv = k_RInfo;
1871 __ load_klass(recv, value, tmp_load_klass);
1872 type_profile_helper(mdo, md, data, recv, &update_done);
1873
1874 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1875 __ addptr(counter_addr, DataLayout::counter_increment);
1876 __ bind(update_done);
1877 } else {
1878 __ jcc(Assembler::equal, done);
1879 }
1880
1881 add_debug_info_for_null_check_here(op->info_for_exception());
1882 __ load_klass(k_RInfo, array, tmp_load_klass);
1883 __ load_klass(klass_RInfo, value, tmp_load_klass);
1884
1885 // get instance klass (it's already uncompressed)
1886 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1887 // perform the fast part of the checking logic
1888 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1889 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1890 __ push(klass_RInfo);
1891 __ push(k_RInfo);
1892 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1893 __ pop(klass_RInfo);
1894 __ pop(k_RInfo);
1895 // result is a boolean
1896 __ testl(k_RInfo, k_RInfo);
1897 __ jcc(Assembler::equal, *failure_target);
1898 // fall through to the success case
1899
1900 __ bind(done);
1901 } else
1902 if (code == lir_checkcast) {
1903 Register obj = op->object()->as_register();
1904 Register dst = op->result_opr()->as_register();
1905 Label success;
1906 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1907 __ bind(success);
1908 if (dst != obj) {
1909 __ mov(dst, obj);
1910 }
1911 } else
1912 if (code == lir_instanceof) {
1913 Register obj = op->object()->as_register();
1914 Register dst = op->result_opr()->as_register();
1915 Label success, failure, done;
1916 emit_typecheck_helper(op, &success, &failure, &failure);
1917 __ bind(failure);
1918 __ xorptr(dst, dst);
1919 __ jmpb(done);
1920 __ bind(success);
1921 __ movptr(dst, 1);
1922 __ bind(done);
1923 } else {
1924 ShouldNotReachHere();
1925 }
1926
1927 }
1928
1929
1930 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1931 if (LP64_ONLY(false &&) op->code() == lir_cas_long) {
1932 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1933 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1934 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1935 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1936 Register addr = op->addr()->as_register();
1937 __ lock();
1938 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1939
1940 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1941 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1942 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1943 Register newval = op->new_value()->as_register();
1944 Register cmpval = op->cmp_value()->as_register();
1945 assert(cmpval == rax, "wrong register");
1946 assert(newval != noreg, "new val must be register");
1947 assert(cmpval != newval, "cmp and new values must be in different registers");
1948 assert(cmpval != addr, "cmp and addr must be in different registers");
1949 assert(newval != addr, "new value and addr must be in different registers");
1950
1951 if ( op->code() == lir_cas_obj) {
1952 #ifdef _LP64
1953 if (UseCompressedOops) {
1954 __ encode_heap_oop(cmpval);
1955 __ mov(rscratch1, newval);
1956 __ encode_heap_oop(rscratch1);
1957 __ lock();
1958 // cmpval (rax) is implicitly used by this instruction
1959 __ cmpxchgl(rscratch1, Address(addr, 0));
1960 } else
1961 #endif
1962 {
1963 __ lock();
1964 __ cmpxchgptr(newval, Address(addr, 0));
1965 }
1966 } else {
1967 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1968 __ lock();
1969 __ cmpxchgl(newval, Address(addr, 0));
1970 }
1971 #ifdef _LP64
1972 } else if (op->code() == lir_cas_long) {
1973 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1974 Register newval = op->new_value()->as_register_lo();
1975 Register cmpval = op->cmp_value()->as_register_lo();
1976 assert(cmpval == rax, "wrong register");
1977 assert(newval != noreg, "new val must be register");
1978 assert(cmpval != newval, "cmp and new values must be in different registers");
1979 assert(cmpval != addr, "cmp and addr must be in different registers");
1980 assert(newval != addr, "new value and addr must be in different registers");
1981 __ lock();
1982 __ cmpxchgq(newval, Address(addr, 0));
1983 #endif // _LP64
1984 } else {
1985 Unimplemented();
1986 }
1987 }
1988
1989 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1990 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1991 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
1992
1993 Assembler::Condition acond, ncond;
1994 switch (condition) {
1995 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1996 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1997 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1998 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1999 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2000 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2001 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2002 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2003 default: acond = Assembler::equal; ncond = Assembler::notEqual;
2004 ShouldNotReachHere();
2005 }
2006
2007 if (opr1->is_cpu_register()) {
2008 reg2reg(opr1, result);
2009 } else if (opr1->is_stack()) {
2010 stack2reg(opr1, result, result->type());
2011 } else if (opr1->is_constant()) {
2012 const2reg(opr1, result, lir_patch_none, nullptr);
2013 } else {
2014 ShouldNotReachHere();
2015 }
2016
2017 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2018 // optimized version that does not require a branch
2019 if (opr2->is_single_cpu()) {
2020 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2021 __ cmov(ncond, result->as_register(), opr2->as_register());
2022 } else if (opr2->is_double_cpu()) {
2023 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2024 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2025 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2026 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2027 } else if (opr2->is_single_stack()) {
2028 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2029 } else if (opr2->is_double_stack()) {
2030 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2031 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2032 } else {
2033 ShouldNotReachHere();
2034 }
2035
2036 } else {
2037 Label skip;
2038 __ jccb(acond, skip);
2039 if (opr2->is_cpu_register()) {
2040 reg2reg(opr2, result);
2041 } else if (opr2->is_stack()) {
2042 stack2reg(opr2, result, result->type());
2043 } else if (opr2->is_constant()) {
2044 const2reg(opr2, result, lir_patch_none, nullptr);
2045 } else {
2046 ShouldNotReachHere();
2047 }
2048 __ bind(skip);
2049 }
2050 }
2051
2052
2053 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2054 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2055
2056 if (left->is_single_cpu()) {
2057 assert(left == dest, "left and dest must be equal");
2058 Register lreg = left->as_register();
2059
2060 if (right->is_single_cpu()) {
2061 // cpu register - cpu register
2062 Register rreg = right->as_register();
2063 switch (code) {
2064 case lir_add: __ addl (lreg, rreg); break;
2065 case lir_sub: __ subl (lreg, rreg); break;
2066 case lir_mul: __ imull(lreg, rreg); break;
2067 default: ShouldNotReachHere();
2068 }
2069
2070 } else if (right->is_stack()) {
2071 // cpu register - stack
2072 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2073 switch (code) {
2074 case lir_add: __ addl(lreg, raddr); break;
2075 case lir_sub: __ subl(lreg, raddr); break;
2076 default: ShouldNotReachHere();
2077 }
2078
2079 } else if (right->is_constant()) {
2080 // cpu register - constant
2081 jint c = right->as_constant_ptr()->as_jint();
2082 switch (code) {
2083 case lir_add: {
2084 __ incrementl(lreg, c);
2085 break;
2086 }
2087 case lir_sub: {
2088 __ decrementl(lreg, c);
2089 break;
2090 }
2091 default: ShouldNotReachHere();
2092 }
2093
2094 } else {
2095 ShouldNotReachHere();
2096 }
2097
2098 } else if (left->is_double_cpu()) {
2099 assert(left == dest, "left and dest must be equal");
2100 Register lreg_lo = left->as_register_lo();
2101 Register lreg_hi = left->as_register_hi();
2102
2103 if (right->is_double_cpu()) {
2104 // cpu register - cpu register
2105 Register rreg_lo = right->as_register_lo();
2106 Register rreg_hi = right->as_register_hi();
2107 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2108 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2109 switch (code) {
2110 case lir_add:
2111 __ addptr(lreg_lo, rreg_lo);
2112 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2113 break;
2114 case lir_sub:
2115 __ subptr(lreg_lo, rreg_lo);
2116 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2117 break;
2118 case lir_mul:
2119 #ifdef _LP64
2120 __ imulq(lreg_lo, rreg_lo);
2121 #else
2122 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2123 __ imull(lreg_hi, rreg_lo);
2124 __ imull(rreg_hi, lreg_lo);
2125 __ addl (rreg_hi, lreg_hi);
2126 __ mull (rreg_lo);
2127 __ addl (lreg_hi, rreg_hi);
2128 #endif // _LP64
2129 break;
2130 default:
2131 ShouldNotReachHere();
2132 }
2133
2134 } else if (right->is_constant()) {
2135 // cpu register - constant
2136 #ifdef _LP64
2137 jlong c = right->as_constant_ptr()->as_jlong_bits();
2138 __ movptr(r10, (intptr_t) c);
2139 switch (code) {
2140 case lir_add:
2141 __ addptr(lreg_lo, r10);
2142 break;
2143 case lir_sub:
2144 __ subptr(lreg_lo, r10);
2145 break;
2146 default:
2147 ShouldNotReachHere();
2148 }
2149 #else
2150 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2151 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2152 switch (code) {
2153 case lir_add:
2154 __ addptr(lreg_lo, c_lo);
2155 __ adcl(lreg_hi, c_hi);
2156 break;
2157 case lir_sub:
2158 __ subptr(lreg_lo, c_lo);
2159 __ sbbl(lreg_hi, c_hi);
2160 break;
2161 default:
2162 ShouldNotReachHere();
2163 }
2164 #endif // _LP64
2165
2166 } else {
2167 ShouldNotReachHere();
2168 }
2169
2170 } else if (left->is_single_xmm()) {
2171 assert(left == dest, "left and dest must be equal");
2172 XMMRegister lreg = left->as_xmm_float_reg();
2173
2174 if (right->is_single_xmm()) {
2175 XMMRegister rreg = right->as_xmm_float_reg();
2176 switch (code) {
2177 case lir_add: __ addss(lreg, rreg); break;
2178 case lir_sub: __ subss(lreg, rreg); break;
2179 case lir_mul: __ mulss(lreg, rreg); break;
2180 case lir_div: __ divss(lreg, rreg); break;
2181 default: ShouldNotReachHere();
2182 }
2183 } else {
2184 Address raddr;
2185 if (right->is_single_stack()) {
2186 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2187 } else if (right->is_constant()) {
2188 // hack for now
2189 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2190 } else {
2191 ShouldNotReachHere();
2192 }
2193 switch (code) {
2194 case lir_add: __ addss(lreg, raddr); break;
2195 case lir_sub: __ subss(lreg, raddr); break;
2196 case lir_mul: __ mulss(lreg, raddr); break;
2197 case lir_div: __ divss(lreg, raddr); break;
2198 default: ShouldNotReachHere();
2199 }
2200 }
2201
2202 } else if (left->is_double_xmm()) {
2203 assert(left == dest, "left and dest must be equal");
2204
2205 XMMRegister lreg = left->as_xmm_double_reg();
2206 if (right->is_double_xmm()) {
2207 XMMRegister rreg = right->as_xmm_double_reg();
2208 switch (code) {
2209 case lir_add: __ addsd(lreg, rreg); break;
2210 case lir_sub: __ subsd(lreg, rreg); break;
2211 case lir_mul: __ mulsd(lreg, rreg); break;
2212 case lir_div: __ divsd(lreg, rreg); break;
2213 default: ShouldNotReachHere();
2214 }
2215 } else {
2216 Address raddr;
2217 if (right->is_double_stack()) {
2218 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2219 } else if (right->is_constant()) {
2220 // hack for now
2221 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2222 } else {
2223 ShouldNotReachHere();
2224 }
2225 switch (code) {
2226 case lir_add: __ addsd(lreg, raddr); break;
2227 case lir_sub: __ subsd(lreg, raddr); break;
2228 case lir_mul: __ mulsd(lreg, raddr); break;
2229 case lir_div: __ divsd(lreg, raddr); break;
2230 default: ShouldNotReachHere();
2231 }
2232 }
2233
2234 #ifndef _LP64
2235 } else if (left->is_single_fpu()) {
2236 assert(dest->is_single_fpu(), "fpu stack allocation required");
2237
2238 if (right->is_single_fpu()) {
2239 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2240
2241 } else {
2242 assert(left->fpu_regnr() == 0, "left must be on TOS");
2243 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2244
2245 Address raddr;
2246 if (right->is_single_stack()) {
2247 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2248 } else if (right->is_constant()) {
2249 address const_addr = float_constant(right->as_jfloat());
2250 assert(const_addr != nullptr, "incorrect float/double constant maintenance");
2251 // hack for now
2252 raddr = __ as_Address(InternalAddress(const_addr));
2253 } else {
2254 ShouldNotReachHere();
2255 }
2256
2257 switch (code) {
2258 case lir_add: __ fadd_s(raddr); break;
2259 case lir_sub: __ fsub_s(raddr); break;
2260 case lir_mul: __ fmul_s(raddr); break;
2261 case lir_div: __ fdiv_s(raddr); break;
2262 default: ShouldNotReachHere();
2263 }
2264 }
2265
2266 } else if (left->is_double_fpu()) {
2267 assert(dest->is_double_fpu(), "fpu stack allocation required");
2268
2269 if (code == lir_mul || code == lir_div) {
2270 // Double values require special handling for strictfp mul/div on x86
2271 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1()));
2272 __ fmulp(left->fpu_regnrLo() + 1);
2273 }
2274
2275 if (right->is_double_fpu()) {
2276 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2277
2278 } else {
2279 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2280 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2281
2282 Address raddr;
2283 if (right->is_double_stack()) {
2284 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2285 } else if (right->is_constant()) {
2286 // hack for now
2287 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2288 } else {
2289 ShouldNotReachHere();
2290 }
2291
2292 switch (code) {
2293 case lir_add: __ fadd_d(raddr); break;
2294 case lir_sub: __ fsub_d(raddr); break;
2295 case lir_mul: __ fmul_d(raddr); break;
2296 case lir_div: __ fdiv_d(raddr); break;
2297 default: ShouldNotReachHere();
2298 }
2299 }
2300
2301 if (code == lir_mul || code == lir_div) {
2302 // Double values require special handling for strictfp mul/div on x86
2303 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2()));
2304 __ fmulp(dest->fpu_regnrLo() + 1);
2305 }
2306 #endif // !_LP64
2307
2308 } else if (left->is_single_stack() || left->is_address()) {
2309 assert(left == dest, "left and dest must be equal");
2310
2311 Address laddr;
2312 if (left->is_single_stack()) {
2313 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2314 } else if (left->is_address()) {
2315 laddr = as_Address(left->as_address_ptr());
2316 } else {
2317 ShouldNotReachHere();
2318 }
2319
2320 if (right->is_single_cpu()) {
2321 Register rreg = right->as_register();
2322 switch (code) {
2323 case lir_add: __ addl(laddr, rreg); break;
2324 case lir_sub: __ subl(laddr, rreg); break;
2325 default: ShouldNotReachHere();
2326 }
2327 } else if (right->is_constant()) {
2328 jint c = right->as_constant_ptr()->as_jint();
2329 switch (code) {
2330 case lir_add: {
2331 __ incrementl(laddr, c);
2332 break;
2333 }
2334 case lir_sub: {
2335 __ decrementl(laddr, c);
2336 break;
2337 }
2338 default: ShouldNotReachHere();
2339 }
2340 } else {
2341 ShouldNotReachHere();
2342 }
2343
2344 } else {
2345 ShouldNotReachHere();
2346 }
2347 }
2348
2349 #ifndef _LP64
2350 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2351 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2352 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2353 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2354
2355 bool left_is_tos = (left_index == 0);
2356 bool dest_is_tos = (dest_index == 0);
2357 int non_tos_index = (left_is_tos ? right_index : left_index);
2358
2359 switch (code) {
2360 case lir_add:
2361 if (pop_fpu_stack) __ faddp(non_tos_index);
2362 else if (dest_is_tos) __ fadd (non_tos_index);
2363 else __ fadda(non_tos_index);
2364 break;
2365
2366 case lir_sub:
2367 if (left_is_tos) {
2368 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2369 else if (dest_is_tos) __ fsub (non_tos_index);
2370 else __ fsubra(non_tos_index);
2371 } else {
2372 if (pop_fpu_stack) __ fsubp (non_tos_index);
2373 else if (dest_is_tos) __ fsubr (non_tos_index);
2374 else __ fsuba (non_tos_index);
2375 }
2376 break;
2377
2378 case lir_mul:
2379 if (pop_fpu_stack) __ fmulp(non_tos_index);
2380 else if (dest_is_tos) __ fmul (non_tos_index);
2381 else __ fmula(non_tos_index);
2382 break;
2383
2384 case lir_div:
2385 if (left_is_tos) {
2386 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2387 else if (dest_is_tos) __ fdiv (non_tos_index);
2388 else __ fdivra(non_tos_index);
2389 } else {
2390 if (pop_fpu_stack) __ fdivp (non_tos_index);
2391 else if (dest_is_tos) __ fdivr (non_tos_index);
2392 else __ fdiva (non_tos_index);
2393 }
2394 break;
2395
2396 case lir_rem:
2397 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2398 __ fremr(noreg);
2399 break;
2400
2401 default:
2402 ShouldNotReachHere();
2403 }
2404 }
2405 #endif // _LP64
2406
2407
2408 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2409 if (value->is_double_xmm()) {
2410 switch(code) {
2411 case lir_abs :
2412 {
2413 #ifdef _LP64
2414 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2415 assert(tmp->is_valid(), "need temporary");
2416 __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2417 } else
2418 #endif
2419 {
2420 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2421 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2422 }
2423 assert(!tmp->is_valid(), "do not need temporary");
2424 __ andpd(dest->as_xmm_double_reg(),
2425 ExternalAddress(LIR_Assembler::double_signmask_pool),
2426 rscratch1);
2427 }
2428 }
2429 break;
2430
2431 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2432 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2433 default : ShouldNotReachHere();
2434 }
2435
2436 #ifndef _LP64
2437 } else if (value->is_double_fpu()) {
2438 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2439 switch(code) {
2440 case lir_abs : __ fabs() ; break;
2441 case lir_sqrt : __ fsqrt(); break;
2442 default : ShouldNotReachHere();
2443 }
2444 #endif // !_LP64
2445 } else if (code == lir_f2hf) {
2446 __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg());
2447 } else if (code == lir_hf2f) {
2448 __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register());
2449 } else {
2450 Unimplemented();
2451 }
2452 }
2453
2454 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2455 // assert(left->destroys_register(), "check");
2456 if (left->is_single_cpu()) {
2457 Register reg = left->as_register();
2458 if (right->is_constant()) {
2459 int val = right->as_constant_ptr()->as_jint();
2460 switch (code) {
2461 case lir_logic_and: __ andl (reg, val); break;
2462 case lir_logic_or: __ orl (reg, val); break;
2463 case lir_logic_xor: __ xorl (reg, val); break;
2464 default: ShouldNotReachHere();
2465 }
2466 } else if (right->is_stack()) {
2467 // added support for stack operands
2468 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2469 switch (code) {
2470 case lir_logic_and: __ andl (reg, raddr); break;
2471 case lir_logic_or: __ orl (reg, raddr); break;
2472 case lir_logic_xor: __ xorl (reg, raddr); break;
2473 default: ShouldNotReachHere();
2474 }
2475 } else {
2476 Register rright = right->as_register();
2477 switch (code) {
2478 case lir_logic_and: __ andptr (reg, rright); break;
2479 case lir_logic_or : __ orptr (reg, rright); break;
2480 case lir_logic_xor: __ xorptr (reg, rright); break;
2481 default: ShouldNotReachHere();
2482 }
2483 }
2484 move_regs(reg, dst->as_register());
2485 } else {
2486 Register l_lo = left->as_register_lo();
2487 Register l_hi = left->as_register_hi();
2488 if (right->is_constant()) {
2489 #ifdef _LP64
2490 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2491 switch (code) {
2492 case lir_logic_and:
2493 __ andq(l_lo, rscratch1);
2494 break;
2495 case lir_logic_or:
2496 __ orq(l_lo, rscratch1);
2497 break;
2498 case lir_logic_xor:
2499 __ xorq(l_lo, rscratch1);
2500 break;
2501 default: ShouldNotReachHere();
2502 }
2503 #else
2504 int r_lo = right->as_constant_ptr()->as_jint_lo();
2505 int r_hi = right->as_constant_ptr()->as_jint_hi();
2506 switch (code) {
2507 case lir_logic_and:
2508 __ andl(l_lo, r_lo);
2509 __ andl(l_hi, r_hi);
2510 break;
2511 case lir_logic_or:
2512 __ orl(l_lo, r_lo);
2513 __ orl(l_hi, r_hi);
2514 break;
2515 case lir_logic_xor:
2516 __ xorl(l_lo, r_lo);
2517 __ xorl(l_hi, r_hi);
2518 break;
2519 default: ShouldNotReachHere();
2520 }
2521 #endif // _LP64
2522 } else {
2523 #ifdef _LP64
2524 Register r_lo;
2525 if (is_reference_type(right->type())) {
2526 r_lo = right->as_register();
2527 } else {
2528 r_lo = right->as_register_lo();
2529 }
2530 #else
2531 Register r_lo = right->as_register_lo();
2532 Register r_hi = right->as_register_hi();
2533 assert(l_lo != r_hi, "overwriting registers");
2534 #endif
2535 switch (code) {
2536 case lir_logic_and:
2537 __ andptr(l_lo, r_lo);
2538 NOT_LP64(__ andptr(l_hi, r_hi);)
2539 break;
2540 case lir_logic_or:
2541 __ orptr(l_lo, r_lo);
2542 NOT_LP64(__ orptr(l_hi, r_hi);)
2543 break;
2544 case lir_logic_xor:
2545 __ xorptr(l_lo, r_lo);
2546 NOT_LP64(__ xorptr(l_hi, r_hi);)
2547 break;
2548 default: ShouldNotReachHere();
2549 }
2550 }
2551
2552 Register dst_lo = dst->as_register_lo();
2553 Register dst_hi = dst->as_register_hi();
2554
2555 #ifdef _LP64
2556 move_regs(l_lo, dst_lo);
2557 #else
2558 if (dst_lo == l_hi) {
2559 assert(dst_hi != l_lo, "overwriting registers");
2560 move_regs(l_hi, dst_hi);
2561 move_regs(l_lo, dst_lo);
2562 } else {
2563 assert(dst_lo != l_hi, "overwriting registers");
2564 move_regs(l_lo, dst_lo);
2565 move_regs(l_hi, dst_hi);
2566 }
2567 #endif // _LP64
2568 }
2569 }
2570
2571
2572 // we assume that rax, and rdx can be overwritten
2573 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2574
2575 assert(left->is_single_cpu(), "left must be register");
2576 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2577 assert(result->is_single_cpu(), "result must be register");
2578
2579 // assert(left->destroys_register(), "check");
2580 // assert(right->destroys_register(), "check");
2581
2582 Register lreg = left->as_register();
2583 Register dreg = result->as_register();
2584
2585 if (right->is_constant()) {
2586 jint divisor = right->as_constant_ptr()->as_jint();
2587 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2588 if (code == lir_idiv) {
2589 assert(lreg == rax, "must be rax,");
2590 assert(temp->as_register() == rdx, "tmp register must be rdx");
2591 __ cdql(); // sign extend into rdx:rax
2592 if (divisor == 2) {
2593 __ subl(lreg, rdx);
2594 } else {
2595 __ andl(rdx, divisor - 1);
2596 __ addl(lreg, rdx);
2597 }
2598 __ sarl(lreg, log2i_exact(divisor));
2599 move_regs(lreg, dreg);
2600 } else if (code == lir_irem) {
2601 Label done;
2602 __ mov(dreg, lreg);
2603 __ andl(dreg, 0x80000000 | (divisor - 1));
2604 __ jcc(Assembler::positive, done);
2605 __ decrement(dreg);
2606 __ orl(dreg, ~(divisor - 1));
2607 __ increment(dreg);
2608 __ bind(done);
2609 } else {
2610 ShouldNotReachHere();
2611 }
2612 } else {
2613 Register rreg = right->as_register();
2614 assert(lreg == rax, "left register must be rax,");
2615 assert(rreg != rdx, "right register must not be rdx");
2616 assert(temp->as_register() == rdx, "tmp register must be rdx");
2617
2618 move_regs(lreg, rax);
2619
2620 int idivl_offset = __ corrected_idivl(rreg);
2621 if (ImplicitDiv0Checks) {
2622 add_debug_info_for_div0(idivl_offset, info);
2623 }
2624 if (code == lir_irem) {
2625 move_regs(rdx, dreg); // result is in rdx
2626 } else {
2627 move_regs(rax, dreg);
2628 }
2629 }
2630 }
2631
2632
2633 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2634 if (opr1->is_single_cpu()) {
2635 Register reg1 = opr1->as_register();
2636 if (opr2->is_single_cpu()) {
2637 // cpu register - cpu register
2638 if (is_reference_type(opr1->type())) {
2639 __ cmpoop(reg1, opr2->as_register());
2640 } else {
2641 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2642 __ cmpl(reg1, opr2->as_register());
2643 }
2644 } else if (opr2->is_stack()) {
2645 // cpu register - stack
2646 if (is_reference_type(opr1->type())) {
2647 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2648 } else {
2649 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2650 }
2651 } else if (opr2->is_constant()) {
2652 // cpu register - constant
2653 LIR_Const* c = opr2->as_constant_ptr();
2654 if (c->type() == T_INT) {
2655 jint i = c->as_jint();
2656 if (i == 0) {
2657 __ testl(reg1, reg1);
2658 } else {
2659 __ cmpl(reg1, i);
2660 }
2661 } else if (c->type() == T_METADATA) {
2662 // All we need for now is a comparison with null for equality.
2663 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2664 Metadata* m = c->as_metadata();
2665 if (m == nullptr) {
2666 __ testptr(reg1, reg1);
2667 } else {
2668 ShouldNotReachHere();
2669 }
2670 } else if (is_reference_type(c->type())) {
2671 // In 64bit oops are single register
2672 jobject o = c->as_jobject();
2673 if (o == nullptr) {
2674 __ testptr(reg1, reg1);
2675 } else {
2676 __ cmpoop(reg1, o, rscratch1);
2677 }
2678 } else {
2679 fatal("unexpected type: %s", basictype_to_str(c->type()));
2680 }
2681 // cpu register - address
2682 } else if (opr2->is_address()) {
2683 if (op->info() != nullptr) {
2684 add_debug_info_for_null_check_here(op->info());
2685 }
2686 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2687 } else {
2688 ShouldNotReachHere();
2689 }
2690
2691 } else if(opr1->is_double_cpu()) {
2692 Register xlo = opr1->as_register_lo();
2693 Register xhi = opr1->as_register_hi();
2694 if (opr2->is_double_cpu()) {
2695 #ifdef _LP64
2696 __ cmpptr(xlo, opr2->as_register_lo());
2697 #else
2698 // cpu register - cpu register
2699 Register ylo = opr2->as_register_lo();
2700 Register yhi = opr2->as_register_hi();
2701 __ subl(xlo, ylo);
2702 __ sbbl(xhi, yhi);
2703 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2704 __ orl(xhi, xlo);
2705 }
2706 #endif // _LP64
2707 } else if (opr2->is_constant()) {
2708 // cpu register - constant 0
2709 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2710 #ifdef _LP64
2711 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2712 #else
2713 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2714 __ orl(xhi, xlo);
2715 #endif // _LP64
2716 } else {
2717 ShouldNotReachHere();
2718 }
2719
2720 } else if (opr1->is_single_xmm()) {
2721 XMMRegister reg1 = opr1->as_xmm_float_reg();
2722 if (opr2->is_single_xmm()) {
2723 // xmm register - xmm register
2724 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2725 } else if (opr2->is_stack()) {
2726 // xmm register - stack
2727 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2728 } else if (opr2->is_constant()) {
2729 // xmm register - constant
2730 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2731 } else if (opr2->is_address()) {
2732 // xmm register - address
2733 if (op->info() != nullptr) {
2734 add_debug_info_for_null_check_here(op->info());
2735 }
2736 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2737 } else {
2738 ShouldNotReachHere();
2739 }
2740
2741 } else if (opr1->is_double_xmm()) {
2742 XMMRegister reg1 = opr1->as_xmm_double_reg();
2743 if (opr2->is_double_xmm()) {
2744 // xmm register - xmm register
2745 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2746 } else if (opr2->is_stack()) {
2747 // xmm register - stack
2748 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2749 } else if (opr2->is_constant()) {
2750 // xmm register - constant
2751 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2752 } else if (opr2->is_address()) {
2753 // xmm register - address
2754 if (op->info() != nullptr) {
2755 add_debug_info_for_null_check_here(op->info());
2756 }
2757 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2758 } else {
2759 ShouldNotReachHere();
2760 }
2761
2762 #ifndef _LP64
2763 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2764 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2765 assert(opr2->is_fpu_register(), "both must be registers");
2766 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2767 #endif // LP64
2768
2769 } else if (opr1->is_address() && opr2->is_constant()) {
2770 LIR_Const* c = opr2->as_constant_ptr();
2771 #ifdef _LP64
2772 if (is_reference_type(c->type())) {
2773 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2774 __ movoop(rscratch1, c->as_jobject());
2775 }
2776 #endif // LP64
2777 if (op->info() != nullptr) {
2778 add_debug_info_for_null_check_here(op->info());
2779 }
2780 // special case: address - constant
2781 LIR_Address* addr = opr1->as_address_ptr();
2782 if (c->type() == T_INT) {
2783 __ cmpl(as_Address(addr), c->as_jint());
2784 } else if (is_reference_type(c->type())) {
2785 #ifdef _LP64
2786 // %%% Make this explode if addr isn't reachable until we figure out a
2787 // better strategy by giving noreg as the temp for as_Address
2788 __ cmpoop(rscratch1, as_Address(addr, noreg));
2789 #else
2790 __ cmpoop(as_Address(addr), c->as_jobject());
2791 #endif // _LP64
2792 } else {
2793 ShouldNotReachHere();
2794 }
2795
2796 } else {
2797 ShouldNotReachHere();
2798 }
2799 }
2800
2801 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2802 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2803 if (left->is_single_xmm()) {
2804 assert(right->is_single_xmm(), "must match");
2805 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2806 } else if (left->is_double_xmm()) {
2807 assert(right->is_double_xmm(), "must match");
2808 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2809
2810 } else {
2811 #ifdef _LP64
2812 ShouldNotReachHere();
2813 #else
2814 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2815 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2816
2817 assert(left->fpu() == 0, "left must be on TOS");
2818 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2819 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2820 #endif // LP64
2821 }
2822 } else {
2823 assert(code == lir_cmp_l2i, "check");
2824 #ifdef _LP64
2825 Label done;
2826 Register dest = dst->as_register();
2827 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2828 __ movl(dest, -1);
2829 __ jccb(Assembler::less, done);
2830 __ setb(Assembler::notZero, dest);
2831 __ movzbl(dest, dest);
2832 __ bind(done);
2833 #else
2834 __ lcmp2int(left->as_register_hi(),
2835 left->as_register_lo(),
2836 right->as_register_hi(),
2837 right->as_register_lo());
2838 move_regs(left->as_register_hi(), dst->as_register());
2839 #endif // _LP64
2840 }
2841 }
2842
2843
2844 void LIR_Assembler::align_call(LIR_Code code) {
2845 // make sure that the displacement word of the call ends up word aligned
2846 int offset = __ offset();
2847 switch (code) {
2848 case lir_static_call:
2849 case lir_optvirtual_call:
2850 case lir_dynamic_call:
2851 offset += NativeCall::displacement_offset;
2852 break;
2853 case lir_icvirtual_call:
2854 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size_rex;
2855 break;
2856 default: ShouldNotReachHere();
2857 }
2858 __ align(BytesPerWord, offset);
2859 }
2860
2861
2862 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2863 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2864 "must be aligned");
2865 __ call(AddressLiteral(op->addr(), rtype));
2866 add_call_info(code_offset(), op->info());
2867 __ post_call_nop();
2868 }
2869
2870
2871 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2872 __ ic_call(op->addr());
2873 add_call_info(code_offset(), op->info());
2874 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2875 "must be aligned");
2876 __ post_call_nop();
2877 }
2878
2879
2880 void LIR_Assembler::emit_static_call_stub() {
2881 address call_pc = __ pc();
2882 address stub = __ start_a_stub(call_stub_size());
2883 if (stub == nullptr) {
2884 bailout("static call stub overflow");
2885 return;
2886 }
2887
2888 int start = __ offset();
2889
2890 // make sure that the displacement word of the call ends up word aligned
2891 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size_rex + NativeCall::displacement_offset);
2892 __ relocate(static_stub_Relocation::spec(call_pc));
2893 __ mov_metadata(rbx, (Metadata*)nullptr);
2894 // must be set to -1 at code generation time
2895 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2896 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2897 __ jump(RuntimeAddress(__ pc()));
2898
2899 assert(__ offset() - start <= call_stub_size(), "stub too big");
2900 __ end_a_stub();
2901 }
2902
2903
2904 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2905 assert(exceptionOop->as_register() == rax, "must match");
2906 assert(exceptionPC->as_register() == rdx, "must match");
2907
2908 // exception object is not added to oop map by LinearScan
2909 // (LinearScan assumes that no oops are in fixed registers)
2910 info->add_register_oop(exceptionOop);
2911 C1StubId unwind_id;
2912
2913 // get current pc information
2914 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2915 int pc_for_athrow_offset = __ offset();
2916 InternalAddress pc_for_athrow(__ pc());
2917 __ lea(exceptionPC->as_register(), pc_for_athrow);
2918 add_call_info(pc_for_athrow_offset, info); // for exception handler
2919
2920 __ verify_not_null_oop(rax);
2921 // search an exception handler (rax: exception oop, rdx: throwing pc)
2922 if (compilation()->has_fpu_code()) {
2923 unwind_id = C1StubId::handle_exception_id;
2924 } else {
2925 unwind_id = C1StubId::handle_exception_nofpu_id;
2926 }
2927 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2928
2929 // enough room for two byte trap
2930 __ nop();
2931 }
2932
2933
2934 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2935 assert(exceptionOop->as_register() == rax, "must match");
2936
2937 __ jmp(_unwind_handler_entry);
2938 }
2939
2940
2941 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2942
2943 // optimized version for linear scan:
2944 // * count must be already in ECX (guaranteed by LinearScan)
2945 // * left and dest must be equal
2946 // * tmp must be unused
2947 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2948 assert(left == dest, "left and dest must be equal");
2949 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2950
2951 if (left->is_single_cpu()) {
2952 Register value = left->as_register();
2953 assert(value != SHIFT_count, "left cannot be ECX");
2954
2955 switch (code) {
2956 case lir_shl: __ shll(value); break;
2957 case lir_shr: __ sarl(value); break;
2958 case lir_ushr: __ shrl(value); break;
2959 default: ShouldNotReachHere();
2960 }
2961 } else if (left->is_double_cpu()) {
2962 Register lo = left->as_register_lo();
2963 Register hi = left->as_register_hi();
2964 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2965 #ifdef _LP64
2966 switch (code) {
2967 case lir_shl: __ shlptr(lo); break;
2968 case lir_shr: __ sarptr(lo); break;
2969 case lir_ushr: __ shrptr(lo); break;
2970 default: ShouldNotReachHere();
2971 }
2972 #else
2973
2974 switch (code) {
2975 case lir_shl: __ lshl(hi, lo); break;
2976 case lir_shr: __ lshr(hi, lo, true); break;
2977 case lir_ushr: __ lshr(hi, lo, false); break;
2978 default: ShouldNotReachHere();
2979 }
2980 #endif // LP64
2981 } else {
2982 ShouldNotReachHere();
2983 }
2984 }
2985
2986
2987 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2988 if (dest->is_single_cpu()) {
2989 // first move left into dest so that left is not destroyed by the shift
2990 Register value = dest->as_register();
2991 count = count & 0x1F; // Java spec
2992
2993 move_regs(left->as_register(), value);
2994 switch (code) {
2995 case lir_shl: __ shll(value, count); break;
2996 case lir_shr: __ sarl(value, count); break;
2997 case lir_ushr: __ shrl(value, count); break;
2998 default: ShouldNotReachHere();
2999 }
3000 } else if (dest->is_double_cpu()) {
3001 #ifndef _LP64
3002 Unimplemented();
3003 #else
3004 // first move left into dest so that left is not destroyed by the shift
3005 Register value = dest->as_register_lo();
3006 count = count & 0x1F; // Java spec
3007
3008 move_regs(left->as_register_lo(), value);
3009 switch (code) {
3010 case lir_shl: __ shlptr(value, count); break;
3011 case lir_shr: __ sarptr(value, count); break;
3012 case lir_ushr: __ shrptr(value, count); break;
3013 default: ShouldNotReachHere();
3014 }
3015 #endif // _LP64
3016 } else {
3017 ShouldNotReachHere();
3018 }
3019 }
3020
3021
3022 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3023 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3024 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3025 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3026 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3027 }
3028
3029
3030 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3031 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3032 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3033 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3034 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3035 }
3036
3037
3038 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3039 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3040 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3041 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3042 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1);
3043 }
3044
3045
3046 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3047 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3048 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3049 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3050 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1);
3051 }
3052
3053
3054 // This code replaces a call to arraycopy; no exception may
3055 // be thrown in this code, they must be thrown in the System.arraycopy
3056 // activation frame; we could save some checks if this would not be the case
3057 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3058 ciArrayKlass* default_type = op->expected_type();
3059 Register src = op->src()->as_register();
3060 Register dst = op->dst()->as_register();
3061 Register src_pos = op->src_pos()->as_register();
3062 Register dst_pos = op->dst_pos()->as_register();
3063 Register length = op->length()->as_register();
3064 Register tmp = op->tmp()->as_register();
3065 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3066
3067 CodeStub* stub = op->stub();
3068 int flags = op->flags();
3069 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
3070 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3071
3072 // if we don't know anything, just go through the generic arraycopy
3073 if (default_type == nullptr) {
3074 // save outgoing arguments on stack in case call to System.arraycopy is needed
3075 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3076 // for interpreter calling conventions. Now we have to do it in new style conventions.
3077 // For the moment until C1 gets the new register allocator I just force all the
3078 // args to the right place (except the register args) and then on the back side
3079 // reload the register args properly if we go slow path. Yuck
3080
3081 // These are proper for the calling convention
3082 store_parameter(length, 2);
3083 store_parameter(dst_pos, 1);
3084 store_parameter(dst, 0);
3085
3086 // these are just temporary placements until we need to reload
3087 store_parameter(src_pos, 3);
3088 store_parameter(src, 4);
3089 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3090
3091 address copyfunc_addr = StubRoutines::generic_arraycopy();
3092 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
3093
3094 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3095 #ifdef _LP64
3096 // The arguments are in java calling convention so we can trivially shift them to C
3097 // convention
3098 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3099 __ mov(c_rarg0, j_rarg0);
3100 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3101 __ mov(c_rarg1, j_rarg1);
3102 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3103 __ mov(c_rarg2, j_rarg2);
3104 assert_different_registers(c_rarg3, j_rarg4);
3105 __ mov(c_rarg3, j_rarg3);
3106 #ifdef _WIN64
3107 // Allocate abi space for args but be sure to keep stack aligned
3108 __ subptr(rsp, 6*wordSize);
3109 store_parameter(j_rarg4, 4);
3110 #ifndef PRODUCT
3111 if (PrintC1Statistics) {
3112 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3113 }
3114 #endif
3115 __ call(RuntimeAddress(copyfunc_addr));
3116 __ addptr(rsp, 6*wordSize);
3117 #else
3118 __ mov(c_rarg4, j_rarg4);
3119 #ifndef PRODUCT
3120 if (PrintC1Statistics) {
3121 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3122 }
3123 #endif
3124 __ call(RuntimeAddress(copyfunc_addr));
3125 #endif // _WIN64
3126 #else
3127 __ push(length);
3128 __ push(dst_pos);
3129 __ push(dst);
3130 __ push(src_pos);
3131 __ push(src);
3132
3133 #ifndef PRODUCT
3134 if (PrintC1Statistics) {
3135 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3136 }
3137 #endif
3138 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3139
3140 #endif // _LP64
3141
3142 __ testl(rax, rax);
3143 __ jcc(Assembler::equal, *stub->continuation());
3144
3145 __ mov(tmp, rax);
3146 __ xorl(tmp, -1);
3147
3148 // Reload values from the stack so they are where the stub
3149 // expects them.
3150 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3151 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3152 __ movptr (length, Address(rsp, 2*BytesPerWord));
3153 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3154 __ movptr (src, Address(rsp, 4*BytesPerWord));
3155
3156 __ subl(length, tmp);
3157 __ addl(src_pos, tmp);
3158 __ addl(dst_pos, tmp);
3159 __ jmp(*stub->entry());
3160
3161 __ bind(*stub->continuation());
3162 return;
3163 }
3164
3165 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3166
3167 int elem_size = type2aelembytes(basic_type);
3168 Address::ScaleFactor scale;
3169
3170 switch (elem_size) {
3171 case 1 :
3172 scale = Address::times_1;
3173 break;
3174 case 2 :
3175 scale = Address::times_2;
3176 break;
3177 case 4 :
3178 scale = Address::times_4;
3179 break;
3180 case 8 :
3181 scale = Address::times_8;
3182 break;
3183 default:
3184 scale = Address::no_scale;
3185 ShouldNotReachHere();
3186 }
3187
3188 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3189 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3190 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3191 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3192
3193 // length and pos's are all sign extended at this point on 64bit
3194
3195 // test for null
3196 if (flags & LIR_OpArrayCopy::src_null_check) {
3197 __ testptr(src, src);
3198 __ jcc(Assembler::zero, *stub->entry());
3199 }
3200 if (flags & LIR_OpArrayCopy::dst_null_check) {
3201 __ testptr(dst, dst);
3202 __ jcc(Assembler::zero, *stub->entry());
3203 }
3204
3205 // If the compiler was not able to prove that exact type of the source or the destination
3206 // of the arraycopy is an array type, check at runtime if the source or the destination is
3207 // an instance type.
3208 if (flags & LIR_OpArrayCopy::type_check) {
3209 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3210 __ load_klass(tmp, dst, tmp_load_klass);
3211 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3212 __ jcc(Assembler::greaterEqual, *stub->entry());
3213 }
3214
3215 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3216 __ load_klass(tmp, src, tmp_load_klass);
3217 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3218 __ jcc(Assembler::greaterEqual, *stub->entry());
3219 }
3220 }
3221
3222 // check if negative
3223 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3224 __ testl(src_pos, src_pos);
3225 __ jcc(Assembler::less, *stub->entry());
3226 }
3227 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3228 __ testl(dst_pos, dst_pos);
3229 __ jcc(Assembler::less, *stub->entry());
3230 }
3231
3232 if (flags & LIR_OpArrayCopy::src_range_check) {
3233 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3234 __ cmpl(tmp, src_length_addr);
3235 __ jcc(Assembler::above, *stub->entry());
3236 }
3237 if (flags & LIR_OpArrayCopy::dst_range_check) {
3238 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3239 __ cmpl(tmp, dst_length_addr);
3240 __ jcc(Assembler::above, *stub->entry());
3241 }
3242
3243 if (flags & LIR_OpArrayCopy::length_positive_check) {
3244 __ testl(length, length);
3245 __ jcc(Assembler::less, *stub->entry());
3246 }
3247
3248 #ifdef _LP64
3249 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3250 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3251 #endif
3252
3253 if (flags & LIR_OpArrayCopy::type_check) {
3254 // We don't know the array types are compatible
3255 if (basic_type != T_OBJECT) {
3256 // Simple test for basic type arrays
3257 if (UseCompressedClassPointers) {
3258 __ movl(tmp, src_klass_addr);
3259 __ cmpl(tmp, dst_klass_addr);
3260 } else {
3261 __ movptr(tmp, src_klass_addr);
3262 __ cmpptr(tmp, dst_klass_addr);
3263 }
3264 __ jcc(Assembler::notEqual, *stub->entry());
3265 } else {
3266 // For object arrays, if src is a sub class of dst then we can
3267 // safely do the copy.
3268 Label cont, slow;
3269
3270 __ push(src);
3271 __ push(dst);
3272
3273 __ load_klass(src, src, tmp_load_klass);
3274 __ load_klass(dst, dst, tmp_load_klass);
3275
3276 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
3277
3278 __ push(src);
3279 __ push(dst);
3280 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
3281 __ pop(dst);
3282 __ pop(src);
3283
3284 __ testl(src, src);
3285 __ jcc(Assembler::notEqual, cont);
3286
3287 __ bind(slow);
3288 __ pop(dst);
3289 __ pop(src);
3290
3291 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3292 if (copyfunc_addr != nullptr) { // use stub if available
3293 // src is not a sub class of dst so we have to do a
3294 // per-element check.
3295
3296 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3297 if ((flags & mask) != mask) {
3298 // Check that at least both of them object arrays.
3299 assert(flags & mask, "one of the two should be known to be an object array");
3300
3301 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3302 __ load_klass(tmp, src, tmp_load_klass);
3303 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3304 __ load_klass(tmp, dst, tmp_load_klass);
3305 }
3306 int lh_offset = in_bytes(Klass::layout_helper_offset());
3307 Address klass_lh_addr(tmp, lh_offset);
3308 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3309 __ cmpl(klass_lh_addr, objArray_lh);
3310 __ jcc(Assembler::notEqual, *stub->entry());
3311 }
3312
3313 // Spill because stubs can use any register they like and it's
3314 // easier to restore just those that we care about.
3315 store_parameter(dst, 0);
3316 store_parameter(dst_pos, 1);
3317 store_parameter(length, 2);
3318 store_parameter(src_pos, 3);
3319 store_parameter(src, 4);
3320
3321 #ifndef _LP64
3322 __ movptr(tmp, dst_klass_addr);
3323 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3324 __ push(tmp);
3325 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3326 __ push(tmp);
3327 __ push(length);
3328 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3329 __ push(tmp);
3330 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3331 __ push(tmp);
3332
3333 __ call_VM_leaf(copyfunc_addr, 5);
3334 #else
3335 __ movl2ptr(length, length); //higher 32bits must be null
3336
3337 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3338 assert_different_registers(c_rarg0, dst, dst_pos, length);
3339 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3340 assert_different_registers(c_rarg1, dst, length);
3341
3342 __ mov(c_rarg2, length);
3343 assert_different_registers(c_rarg2, dst);
3344
3345 #ifdef _WIN64
3346 // Allocate abi space for args but be sure to keep stack aligned
3347 __ subptr(rsp, 6*wordSize);
3348 __ load_klass(c_rarg3, dst, tmp_load_klass);
3349 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3350 store_parameter(c_rarg3, 4);
3351 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3352 __ call(RuntimeAddress(copyfunc_addr));
3353 __ addptr(rsp, 6*wordSize);
3354 #else
3355 __ load_klass(c_rarg4, dst, tmp_load_klass);
3356 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3357 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3358 __ call(RuntimeAddress(copyfunc_addr));
3359 #endif
3360
3361 #endif
3362
3363 #ifndef PRODUCT
3364 if (PrintC1Statistics) {
3365 Label failed;
3366 __ testl(rax, rax);
3367 __ jcc(Assembler::notZero, failed);
3368 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1);
3369 __ bind(failed);
3370 }
3371 #endif
3372
3373 __ testl(rax, rax);
3374 __ jcc(Assembler::zero, *stub->continuation());
3375
3376 #ifndef PRODUCT
3377 if (PrintC1Statistics) {
3378 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1);
3379 }
3380 #endif
3381
3382 __ mov(tmp, rax);
3383
3384 __ xorl(tmp, -1);
3385
3386 // Restore previously spilled arguments
3387 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3388 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3389 __ movptr (length, Address(rsp, 2*BytesPerWord));
3390 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3391 __ movptr (src, Address(rsp, 4*BytesPerWord));
3392
3393
3394 __ subl(length, tmp);
3395 __ addl(src_pos, tmp);
3396 __ addl(dst_pos, tmp);
3397 }
3398
3399 __ jmp(*stub->entry());
3400
3401 __ bind(cont);
3402 __ pop(dst);
3403 __ pop(src);
3404 }
3405 }
3406
3407 #ifdef ASSERT
3408 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3409 // Sanity check the known type with the incoming class. For the
3410 // primitive case the types must match exactly with src.klass and
3411 // dst.klass each exactly matching the default type. For the
3412 // object array case, if no type check is needed then either the
3413 // dst type is exactly the expected type and the src type is a
3414 // subtype which we can't check or src is the same array as dst
3415 // but not necessarily exactly of type default_type.
3416 Label known_ok, halt;
3417 __ mov_metadata(tmp, default_type->constant_encoding());
3418 #ifdef _LP64
3419 if (UseCompressedClassPointers) {
3420 __ encode_klass_not_null(tmp, rscratch1);
3421 }
3422 #endif
3423
3424 if (basic_type != T_OBJECT) {
3425
3426 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3427 else __ cmpptr(tmp, dst_klass_addr);
3428 __ jcc(Assembler::notEqual, halt);
3429 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3430 else __ cmpptr(tmp, src_klass_addr);
3431 __ jcc(Assembler::equal, known_ok);
3432 } else {
3433 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3434 else __ cmpptr(tmp, dst_klass_addr);
3435 __ jcc(Assembler::equal, known_ok);
3436 __ cmpptr(src, dst);
3437 __ jcc(Assembler::equal, known_ok);
3438 }
3439 __ bind(halt);
3440 __ stop("incorrect type information in arraycopy");
3441 __ bind(known_ok);
3442 }
3443 #endif
3444
3445 #ifndef PRODUCT
3446 if (PrintC1Statistics) {
3447 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1);
3448 }
3449 #endif
3450
3451 #ifdef _LP64
3452 assert_different_registers(c_rarg0, dst, dst_pos, length);
3453 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3454 assert_different_registers(c_rarg1, length);
3455 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3456 __ mov(c_rarg2, length);
3457
3458 #else
3459 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3460 store_parameter(tmp, 0);
3461 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3462 store_parameter(tmp, 1);
3463 store_parameter(length, 2);
3464 #endif // _LP64
3465
3466 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3467 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3468 const char *name;
3469 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3470 __ call_VM_leaf(entry, 0);
3471
3472 if (stub != nullptr) {
3473 __ bind(*stub->continuation());
3474 }
3475 }
3476
3477 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3478 assert(op->crc()->is_single_cpu(), "crc must be register");
3479 assert(op->val()->is_single_cpu(), "byte value must be register");
3480 assert(op->result_opr()->is_single_cpu(), "result must be register");
3481 Register crc = op->crc()->as_register();
3482 Register val = op->val()->as_register();
3483 Register res = op->result_opr()->as_register();
3484
3485 assert_different_registers(val, crc, res);
3486
3487 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3488 __ notl(crc); // ~crc
3489 __ update_byte_crc32(crc, val, res);
3490 __ notl(crc); // ~crc
3491 __ mov(res, crc);
3492 }
3493
3494 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3495 Register obj = op->obj_opr()->as_register(); // may not be an oop
3496 Register hdr = op->hdr_opr()->as_register();
3497 Register lock = op->lock_opr()->as_register();
3498 if (LockingMode == LM_MONITOR) {
3499 if (op->info() != nullptr) {
3500 add_debug_info_for_null_check_here(op->info());
3501 __ null_check(obj);
3502 }
3503 __ jmp(*op->stub()->entry());
3504 } else if (op->code() == lir_lock) {
3505 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3506 Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg;
3507 // add debug info for NullPointerException only if one is possible
3508 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
3509 if (op->info() != nullptr) {
3510 add_debug_info_for_null_check(null_check_offset, op->info());
3511 }
3512 // done
3513 } else if (op->code() == lir_unlock) {
3514 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3515 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3516 } else {
3517 Unimplemented();
3518 }
3519 __ bind(*op->stub()->continuation());
3520 }
3521
3522 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
3523 Register obj = op->obj()->as_pointer_register();
3524 Register result = op->result_opr()->as_pointer_register();
3525
3526 CodeEmitInfo* info = op->info();
3527 if (info != nullptr) {
3528 add_debug_info_for_null_check_here(info);
3529 }
3530
3531 #ifdef _LP64
3532 if (UseCompressedClassPointers) {
3533 __ movl(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3534 __ decode_klass_not_null(result, rscratch1);
3535 } else
3536 #endif
3537 __ movptr(result, Address(obj, oopDesc::klass_offset_in_bytes()));
3538 }
3539
3540 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3541 ciMethod* method = op->profiled_method();
3542 int bci = op->profiled_bci();
3543 ciMethod* callee = op->profiled_callee();
3544 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3545
3546 // Update counter for all call types
3547 ciMethodData* md = method->method_data_or_null();
3548 assert(md != nullptr, "Sanity");
3549 ciProfileData* data = md->bci_to_data(bci);
3550 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
3551 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3552 Register mdo = op->mdo()->as_register();
3553 __ mov_metadata(mdo, md->constant_encoding());
3554 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3555 // Perform additional virtual call profiling for invokevirtual and
3556 // invokeinterface bytecodes
3557 if (op->should_profile_receiver_type()) {
3558 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3559 Register recv = op->recv()->as_register();
3560 assert_different_registers(mdo, recv);
3561 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3562 ciKlass* known_klass = op->known_holder();
3563 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
3564 // We know the type that will be seen at this call site; we can
3565 // statically update the MethodData* rather than needing to do
3566 // dynamic tests on the receiver type
3567
3568 // NOTE: we should probably put a lock around this search to
3569 // avoid collisions by concurrent compilations
3570 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3571 uint i;
3572 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3573 ciKlass* receiver = vc_data->receiver(i);
3574 if (known_klass->equals(receiver)) {
3575 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3576 __ addptr(data_addr, DataLayout::counter_increment);
3577 return;
3578 }
3579 }
3580
3581 // Receiver type not found in profile data; select an empty slot
3582
3583 // Note that this is less efficient than it should be because it
3584 // always does a write to the receiver part of the
3585 // VirtualCallData rather than just the first time
3586 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3587 ciKlass* receiver = vc_data->receiver(i);
3588 if (receiver == nullptr) {
3589 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3590 __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1);
3591 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3592 __ addptr(data_addr, DataLayout::counter_increment);
3593 return;
3594 }
3595 }
3596 } else {
3597 __ load_klass(recv, recv, tmp_load_klass);
3598 Label update_done;
3599 type_profile_helper(mdo, md, data, recv, &update_done);
3600 // Receiver did not match any saved receiver and there is no empty row for it.
3601 // Increment total counter to indicate polymorphic case.
3602 __ addptr(counter_addr, DataLayout::counter_increment);
3603
3604 __ bind(update_done);
3605 }
3606 } else {
3607 // Static call
3608 __ addptr(counter_addr, DataLayout::counter_increment);
3609 }
3610 }
3611
3612 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3613 Register obj = op->obj()->as_register();
3614 Register tmp = op->tmp()->as_pointer_register();
3615 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3616 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3617 ciKlass* exact_klass = op->exact_klass();
3618 intptr_t current_klass = op->current_klass();
3619 bool not_null = op->not_null();
3620 bool no_conflict = op->no_conflict();
3621
3622 Label update, next, none;
3623
3624 bool do_null = !not_null;
3625 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3626 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3627
3628 assert(do_null || do_update, "why are we here?");
3629 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3630
3631 __ verify_oop(obj);
3632
3633 #ifdef ASSERT
3634 if (obj == tmp) {
3635 #ifdef _LP64
3636 assert_different_registers(obj, rscratch1, mdo_addr.base(), mdo_addr.index());
3637 #else
3638 assert_different_registers(obj, mdo_addr.base(), mdo_addr.index());
3639 #endif
3640 } else {
3641 #ifdef _LP64
3642 assert_different_registers(obj, tmp, rscratch1, mdo_addr.base(), mdo_addr.index());
3643 #else
3644 assert_different_registers(obj, tmp, mdo_addr.base(), mdo_addr.index());
3645 #endif
3646 }
3647 #endif
3648 if (do_null) {
3649 __ testptr(obj, obj);
3650 __ jccb(Assembler::notZero, update);
3651 if (!TypeEntries::was_null_seen(current_klass)) {
3652 __ testptr(mdo_addr, TypeEntries::null_seen);
3653 #ifndef ASSERT
3654 __ jccb(Assembler::notZero, next); // already set
3655 #else
3656 __ jcc(Assembler::notZero, next); // already set
3657 #endif
3658 // atomic update to prevent overwriting Klass* with 0
3659 __ lock();
3660 __ orptr(mdo_addr, TypeEntries::null_seen);
3661 }
3662 if (do_update) {
3663 #ifndef ASSERT
3664 __ jmpb(next);
3665 }
3666 #else
3667 __ jmp(next);
3668 }
3669 } else {
3670 __ testptr(obj, obj);
3671 __ jcc(Assembler::notZero, update);
3672 __ stop("unexpected null obj");
3673 #endif
3674 }
3675
3676 __ bind(update);
3677
3678 if (do_update) {
3679 #ifdef ASSERT
3680 if (exact_klass != nullptr) {
3681 Label ok;
3682 __ load_klass(tmp, obj, tmp_load_klass);
3683 __ push(tmp);
3684 __ mov_metadata(tmp, exact_klass->constant_encoding());
3685 __ cmpptr(tmp, Address(rsp, 0));
3686 __ jcc(Assembler::equal, ok);
3687 __ stop("exact klass and actual klass differ");
3688 __ bind(ok);
3689 __ pop(tmp);
3690 }
3691 #endif
3692 if (!no_conflict) {
3693 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3694 if (exact_klass != nullptr) {
3695 __ mov_metadata(tmp, exact_klass->constant_encoding());
3696 } else {
3697 __ load_klass(tmp, obj, tmp_load_klass);
3698 }
3699 #ifdef _LP64
3700 __ mov(rscratch1, tmp); // save original value before XOR
3701 #endif
3702 __ xorptr(tmp, mdo_addr);
3703 __ testptr(tmp, TypeEntries::type_klass_mask);
3704 // klass seen before, nothing to do. The unknown bit may have been
3705 // set already but no need to check.
3706 __ jccb(Assembler::zero, next);
3707
3708 __ testptr(tmp, TypeEntries::type_unknown);
3709 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3710
3711 if (TypeEntries::is_type_none(current_klass)) {
3712 __ testptr(mdo_addr, TypeEntries::type_mask);
3713 __ jccb(Assembler::zero, none);
3714 #ifdef _LP64
3715 // There is a chance that the checks above (re-reading profiling
3716 // data from memory) fail if another thread has just set the
3717 // profiling to this obj's klass
3718 __ mov(tmp, rscratch1); // get back original value before XOR
3719 __ xorptr(tmp, mdo_addr);
3720 __ testptr(tmp, TypeEntries::type_klass_mask);
3721 __ jccb(Assembler::zero, next);
3722 #endif
3723 }
3724 } else {
3725 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3726 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3727
3728 __ testptr(mdo_addr, TypeEntries::type_unknown);
3729 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3730 }
3731
3732 // different than before. Cannot keep accurate profile.
3733 __ orptr(mdo_addr, TypeEntries::type_unknown);
3734
3735 if (TypeEntries::is_type_none(current_klass)) {
3736 __ jmpb(next);
3737
3738 __ bind(none);
3739 // first time here. Set profile type.
3740 __ movptr(mdo_addr, tmp);
3741 #ifdef ASSERT
3742 __ andptr(tmp, TypeEntries::type_klass_mask);
3743 __ verify_klass_ptr(tmp);
3744 #endif
3745 }
3746 } else {
3747 // There's a single possible klass at this profile point
3748 assert(exact_klass != nullptr, "should be");
3749 if (TypeEntries::is_type_none(current_klass)) {
3750 __ mov_metadata(tmp, exact_klass->constant_encoding());
3751 __ xorptr(tmp, mdo_addr);
3752 __ testptr(tmp, TypeEntries::type_klass_mask);
3753 #ifdef ASSERT
3754 __ jcc(Assembler::zero, next);
3755
3756 {
3757 Label ok;
3758 __ push(tmp);
3759 __ testptr(mdo_addr, TypeEntries::type_mask);
3760 __ jcc(Assembler::zero, ok);
3761 // may have been set by another thread
3762 __ mov_metadata(tmp, exact_klass->constant_encoding());
3763 __ xorptr(tmp, mdo_addr);
3764 __ testptr(tmp, TypeEntries::type_mask);
3765 __ jcc(Assembler::zero, ok);
3766
3767 __ stop("unexpected profiling mismatch");
3768 __ bind(ok);
3769 __ pop(tmp);
3770 }
3771 #else
3772 __ jccb(Assembler::zero, next);
3773 #endif
3774 // first time here. Set profile type.
3775 __ movptr(mdo_addr, tmp);
3776 #ifdef ASSERT
3777 __ andptr(tmp, TypeEntries::type_klass_mask);
3778 __ verify_klass_ptr(tmp);
3779 #endif
3780 } else {
3781 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3782 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3783
3784 __ testptr(mdo_addr, TypeEntries::type_unknown);
3785 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3786
3787 __ orptr(mdo_addr, TypeEntries::type_unknown);
3788 }
3789 }
3790 }
3791 __ bind(next);
3792 }
3793
3794 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3795 Unimplemented();
3796 }
3797
3798
3799 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3800 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3801 }
3802
3803
3804 void LIR_Assembler::align_backward_branch_target() {
3805 __ align(BytesPerWord);
3806 }
3807
3808
3809 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3810 if (left->is_single_cpu()) {
3811 __ negl(left->as_register());
3812 move_regs(left->as_register(), dest->as_register());
3813
3814 } else if (left->is_double_cpu()) {
3815 Register lo = left->as_register_lo();
3816 #ifdef _LP64
3817 Register dst = dest->as_register_lo();
3818 __ movptr(dst, lo);
3819 __ negptr(dst);
3820 #else
3821 Register hi = left->as_register_hi();
3822 __ lneg(hi, lo);
3823 if (dest->as_register_lo() == hi) {
3824 assert(dest->as_register_hi() != lo, "destroying register");
3825 move_regs(hi, dest->as_register_hi());
3826 move_regs(lo, dest->as_register_lo());
3827 } else {
3828 move_regs(lo, dest->as_register_lo());
3829 move_regs(hi, dest->as_register_hi());
3830 }
3831 #endif // _LP64
3832
3833 } else if (dest->is_single_xmm()) {
3834 #ifdef _LP64
3835 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3836 assert(tmp->is_valid(), "need temporary");
3837 assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
3838 __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
3839 }
3840 else
3841 #endif
3842 {
3843 assert(!tmp->is_valid(), "do not need temporary");
3844 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3845 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3846 }
3847 __ xorps(dest->as_xmm_float_reg(),
3848 ExternalAddress(LIR_Assembler::float_signflip_pool),
3849 rscratch1);
3850 }
3851 } else if (dest->is_double_xmm()) {
3852 #ifdef _LP64
3853 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3854 assert(tmp->is_valid(), "need temporary");
3855 assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
3856 __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
3857 }
3858 else
3859 #endif
3860 {
3861 assert(!tmp->is_valid(), "do not need temporary");
3862 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3863 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3864 }
3865 __ xorpd(dest->as_xmm_double_reg(),
3866 ExternalAddress(LIR_Assembler::double_signflip_pool),
3867 rscratch1);
3868 }
3869 #ifndef _LP64
3870 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3871 assert(left->fpu() == 0, "arg must be on TOS");
3872 assert(dest->fpu() == 0, "dest must be TOS");
3873 __ fchs();
3874 #endif // !_LP64
3875
3876 } else {
3877 ShouldNotReachHere();
3878 }
3879 }
3880
3881
3882 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3883 assert(src->is_address(), "must be an address");
3884 assert(dest->is_register(), "must be a register");
3885
3886 PatchingStub* patch = nullptr;
3887 if (patch_code != lir_patch_none) {
3888 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3889 }
3890
3891 Register reg = dest->as_pointer_register();
3892 LIR_Address* addr = src->as_address_ptr();
3893 __ lea(reg, as_Address(addr));
3894
3895 if (patch != nullptr) {
3896 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3897 }
3898 }
3899
3900
3901
3902 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3903 assert(!tmp->is_valid(), "don't need temporary");
3904 __ call(RuntimeAddress(dest));
3905 if (info != nullptr) {
3906 add_call_info_here(info);
3907 }
3908 __ post_call_nop();
3909 }
3910
3911
3912 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3913 assert(type == T_LONG, "only for volatile long fields");
3914
3915 if (info != nullptr) {
3916 add_debug_info_for_null_check_here(info);
3917 }
3918
3919 if (src->is_double_xmm()) {
3920 if (dest->is_double_cpu()) {
3921 #ifdef _LP64
3922 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3923 #else
3924 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3925 __ psrlq(src->as_xmm_double_reg(), 32);
3926 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3927 #endif // _LP64
3928 } else if (dest->is_double_stack()) {
3929 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3930 } else if (dest->is_address()) {
3931 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3932 } else {
3933 ShouldNotReachHere();
3934 }
3935
3936 } else if (dest->is_double_xmm()) {
3937 if (src->is_double_stack()) {
3938 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3939 } else if (src->is_address()) {
3940 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3941 } else {
3942 ShouldNotReachHere();
3943 }
3944
3945 #ifndef _LP64
3946 } else if (src->is_double_fpu()) {
3947 assert(src->fpu_regnrLo() == 0, "must be TOS");
3948 if (dest->is_double_stack()) {
3949 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3950 } else if (dest->is_address()) {
3951 __ fistp_d(as_Address(dest->as_address_ptr()));
3952 } else {
3953 ShouldNotReachHere();
3954 }
3955
3956 } else if (dest->is_double_fpu()) {
3957 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3958 if (src->is_double_stack()) {
3959 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3960 } else if (src->is_address()) {
3961 __ fild_d(as_Address(src->as_address_ptr()));
3962 } else {
3963 ShouldNotReachHere();
3964 }
3965 #endif // !_LP64
3966
3967 } else {
3968 ShouldNotReachHere();
3969 }
3970 }
3971
3972 #ifdef ASSERT
3973 // emit run-time assertion
3974 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3975 assert(op->code() == lir_assert, "must be");
3976
3977 if (op->in_opr1()->is_valid()) {
3978 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3979 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3980 } else {
3981 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3982 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3983 }
3984
3985 Label ok;
3986 if (op->condition() != lir_cond_always) {
3987 Assembler::Condition acond = Assembler::zero;
3988 switch (op->condition()) {
3989 case lir_cond_equal: acond = Assembler::equal; break;
3990 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3991 case lir_cond_less: acond = Assembler::less; break;
3992 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3993 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3994 case lir_cond_greater: acond = Assembler::greater; break;
3995 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3996 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3997 default: ShouldNotReachHere();
3998 }
3999 __ jcc(acond, ok);
4000 }
4001 if (op->halt()) {
4002 const char* str = __ code_string(op->msg());
4003 __ stop(str);
4004 } else {
4005 breakpoint();
4006 }
4007 __ bind(ok);
4008 }
4009 #endif
4010
4011 void LIR_Assembler::membar() {
4012 // QQQ sparc TSO uses this,
4013 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
4014 }
4015
4016 void LIR_Assembler::membar_acquire() {
4017 // No x86 machines currently require load fences
4018 }
4019
4020 void LIR_Assembler::membar_release() {
4021 // No x86 machines currently require store fences
4022 }
4023
4024 void LIR_Assembler::membar_loadload() {
4025 // no-op
4026 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
4027 }
4028
4029 void LIR_Assembler::membar_storestore() {
4030 // no-op
4031 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4032 }
4033
4034 void LIR_Assembler::membar_loadstore() {
4035 // no-op
4036 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4037 }
4038
4039 void LIR_Assembler::membar_storeload() {
4040 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4041 }
4042
4043 void LIR_Assembler::on_spin_wait() {
4044 __ pause ();
4045 }
4046
4047 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4048 assert(result_reg->is_register(), "check");
4049 #ifdef _LP64
4050 // __ get_thread(result_reg->as_register_lo());
4051 __ mov(result_reg->as_register(), r15_thread);
4052 #else
4053 __ get_thread(result_reg->as_register());
4054 #endif // _LP64
4055 }
4056
4057
4058 void LIR_Assembler::peephole(LIR_List*) {
4059 // do nothing for now
4060 }
4061
4062 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4063 assert(data == dest, "xchg/xadd uses only 2 operands");
4064
4065 if (data->type() == T_INT) {
4066 if (code == lir_xadd) {
4067 __ lock();
4068 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4069 } else {
4070 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4071 }
4072 } else if (data->is_oop()) {
4073 assert (code == lir_xchg, "xadd for oops");
4074 Register obj = data->as_register();
4075 #ifdef _LP64
4076 if (UseCompressedOops) {
4077 __ encode_heap_oop(obj);
4078 __ xchgl(obj, as_Address(src->as_address_ptr()));
4079 __ decode_heap_oop(obj);
4080 } else {
4081 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4082 }
4083 #else
4084 __ xchgl(obj, as_Address(src->as_address_ptr()));
4085 #endif
4086 } else if (data->type() == T_LONG) {
4087 #ifdef _LP64
4088 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4089 if (code == lir_xadd) {
4090 __ lock();
4091 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4092 } else {
4093 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4094 }
4095 #else
4096 ShouldNotReachHere();
4097 #endif
4098 } else {
4099 ShouldNotReachHere();
4100 }
4101 }
4102
4103 #undef __