1 /*
2 * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "ci/ciUtilities.hpp"
37 #include "code/SCCache.hpp"
38 #include "compiler/oopMap.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/gc_globals.hpp"
41 #include "nativeInst_x86.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/safepointMechanism.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/stubRoutines.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_x86.inline.hpp"
49
50
51 // These masks are used to provide 128-bit aligned bitmasks to the XMM
52 // instructions, to allow sign-masking or sign-bit flipping. They allow
53 // fast versions of NegF/NegD and AbsF/AbsD.
54
55 // Note: 'double' and 'long long' have 32-bits alignment on x86.
56 static address double_quadword(jlong *adr, jlong lo, jlong hi) {
57 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
58 // of 128-bits operands for SSE instructions.
59 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
60 // Store the value to a 128-bits operand.
61 operand[0] = lo;
62 operand[1] = hi;
63 return (address)operand;
64 }
65
66 // Buffer for 128-bits masks used by SSE instructions.
67 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
68
69 // Static initialization during VM startup.
70 address LIR_Assembler::float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
71 address LIR_Assembler::double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
72 address LIR_Assembler::float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
73 address LIR_Assembler::double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
74
75
76 NEEDS_CLEANUP // remove this definitions ?
77 const Register SYNC_header = rax; // synchronization header
78 const Register SHIFT_count = rcx; // where count for shift operations must be
79
80 #define __ _masm->
81
82
83 static void select_different_registers(Register preserve,
84 Register extra,
85 Register &tmp1,
86 Register &tmp2) {
87 if (tmp1 == preserve) {
88 assert_different_registers(tmp1, tmp2, extra);
89 tmp1 = extra;
90 } else if (tmp2 == preserve) {
91 assert_different_registers(tmp1, tmp2, extra);
92 tmp2 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2);
95 }
96
97
98
99 static void select_different_registers(Register preserve,
100 Register extra,
101 Register &tmp1,
102 Register &tmp2,
103 Register &tmp3) {
104 if (tmp1 == preserve) {
105 assert_different_registers(tmp1, tmp2, tmp3, extra);
106 tmp1 = extra;
107 } else if (tmp2 == preserve) {
108 assert_different_registers(tmp1, tmp2, tmp3, extra);
109 tmp2 = extra;
110 } else if (tmp3 == preserve) {
111 assert_different_registers(tmp1, tmp2, tmp3, extra);
112 tmp3 = extra;
113 }
114 assert_different_registers(preserve, tmp1, tmp2, tmp3);
115 }
116
117
118
119 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
120 if (opr->is_constant()) {
121 LIR_Const* constant = opr->as_constant_ptr();
122 switch (constant->type()) {
123 case T_INT: {
124 return true;
125 }
126
127 default:
128 return false;
129 }
130 }
131 return false;
132 }
133
134
135 LIR_Opr LIR_Assembler::receiverOpr() {
136 return FrameMap::receiver_opr;
137 }
138
139 LIR_Opr LIR_Assembler::osrBufferPointer() {
140 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
141 }
142
143 //--------------fpu register translations-----------------------
144
145
146 address LIR_Assembler::float_constant(float f) {
147 address const_addr = __ float_constant(f);
148 if (const_addr == nullptr) {
149 bailout("const section overflow");
150 return __ code()->consts()->start();
151 } else {
152 return const_addr;
153 }
154 }
155
156
157 address LIR_Assembler::double_constant(double d) {
158 address const_addr = __ double_constant(d);
159 if (const_addr == nullptr) {
160 bailout("const section overflow");
161 return __ code()->consts()->start();
162 } else {
163 return const_addr;
164 }
165 }
166
167 #ifndef _LP64
168 void LIR_Assembler::fpop() {
169 __ fpop();
170 }
171
172 void LIR_Assembler::fxch(int i) {
173 __ fxch(i);
174 }
175
176 void LIR_Assembler::fld(int i) {
177 __ fld_s(i);
178 }
179
180 void LIR_Assembler::ffree(int i) {
181 __ ffree(i);
182 }
183 #endif // !_LP64
184
185 void LIR_Assembler::breakpoint() {
186 __ int3();
187 }
188
189 void LIR_Assembler::push(LIR_Opr opr) {
190 if (opr->is_single_cpu()) {
191 __ push_reg(opr->as_register());
192 } else if (opr->is_double_cpu()) {
193 NOT_LP64(__ push_reg(opr->as_register_hi()));
194 __ push_reg(opr->as_register_lo());
195 } else if (opr->is_stack()) {
196 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
197 } else if (opr->is_constant()) {
198 LIR_Const* const_opr = opr->as_constant_ptr();
199 if (const_opr->type() == T_OBJECT) {
200 __ push_oop(const_opr->as_jobject(), rscratch1);
201 } else if (const_opr->type() == T_INT) {
202 __ push_jint(const_opr->as_jint());
203 } else {
204 ShouldNotReachHere();
205 }
206
207 } else {
208 ShouldNotReachHere();
209 }
210 }
211
212 void LIR_Assembler::pop(LIR_Opr opr) {
213 if (opr->is_single_cpu()) {
214 __ pop_reg(opr->as_register());
215 } else {
216 ShouldNotReachHere();
217 }
218 }
219
220 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
221 return addr->base()->is_illegal() && addr->index()->is_illegal();
222 }
223
224 //-------------------------------------------
225
226 Address LIR_Assembler::as_Address(LIR_Address* addr) {
227 return as_Address(addr, rscratch1);
228 }
229
230 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
231 if (addr->base()->is_illegal()) {
232 assert(addr->index()->is_illegal(), "must be illegal too");
233 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
234 if (! __ reachable(laddr)) {
235 __ movptr(tmp, laddr.addr());
236 Address res(tmp, 0);
237 return res;
238 } else {
239 return __ as_Address(laddr);
240 }
241 }
242
243 Register base = addr->base()->as_pointer_register();
244
245 if (addr->index()->is_illegal()) {
246 return Address( base, addr->disp());
247 } else if (addr->index()->is_cpu_register()) {
248 Register index = addr->index()->as_pointer_register();
249 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
250 } else if (addr->index()->is_constant()) {
251 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
252 assert(Assembler::is_simm32(addr_offset), "must be");
253
254 return Address(base, addr_offset);
255 } else {
256 Unimplemented();
257 return Address();
258 }
259 }
260
261
262 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
263 Address base = as_Address(addr);
264 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
265 }
266
267
268 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
269 return as_Address(addr);
270 }
271
272
273 void LIR_Assembler::osr_entry() {
274 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
275 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
276 ValueStack* entry_state = osr_entry->state();
277 int number_of_locks = entry_state->locks_size();
278
279 // we jump here if osr happens with the interpreter
280 // state set up to continue at the beginning of the
281 // loop that triggered osr - in particular, we have
282 // the following registers setup:
283 //
284 // rcx: osr buffer
285 //
286
287 // build frame
288 ciMethod* m = compilation()->method();
289 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
290
291 // OSR buffer is
292 //
293 // locals[nlocals-1..0]
294 // monitors[0..number_of_locks]
295 //
296 // locals is a direct copy of the interpreter frame so in the osr buffer
297 // so first slot in the local array is the last local from the interpreter
298 // and last slot is local[0] (receiver) from the interpreter
299 //
300 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
301 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
302 // in the interpreter frame (the method lock if a sync method)
303
304 // Initialize monitors in the compiled activation.
305 // rcx: pointer to osr buffer
306 //
307 // All other registers are dead at this point and the locals will be
308 // copied into place by code emitted in the IR.
309
310 Register OSR_buf = osrBufferPointer()->as_pointer_register();
311 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
312 int monitor_offset = BytesPerWord * method()->max_locals() +
313 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
314 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
315 // the OSR buffer using 2 word entries: first the lock and then
316 // the oop.
317 for (int i = 0; i < number_of_locks; i++) {
318 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
319 #ifdef ASSERT
320 // verify the interpreter's monitor has a non-null object
321 {
322 Label L;
323 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD);
324 __ jcc(Assembler::notZero, L);
325 __ stop("locked object is null");
326 __ bind(L);
327 }
328 #endif
329 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
330 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
331 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
332 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
333 }
334 }
335 }
336
337
338 // inline cache check; done before the frame is built.
339 int LIR_Assembler::check_icache() {
340 return __ ic_check(CodeEntryAlignment);
341 }
342
343 void LIR_Assembler::clinit_barrier(ciMethod* method) {
344 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
345 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
346
347 Label L_skip_barrier;
348 Register klass = rscratch1;
349 Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
350 assert(thread != noreg, "x86_32 not implemented");
351
352 __ mov_metadata(klass, method->holder()->constant_encoding());
353 __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
354
355 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
356
357 __ bind(L_skip_barrier);
358 }
359
360 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
361 jobject o = nullptr;
362 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
363 __ movoop(reg, o);
364 patching_epilog(patch, lir_patch_normal, reg, info);
365 }
366
367 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
368 Metadata* o = nullptr;
369 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
370 __ mov_metadata(reg, o);
371 patching_epilog(patch, lir_patch_normal, reg, info);
372 }
373
374 // This specifies the rsp decrement needed to build the frame
375 int LIR_Assembler::initial_frame_size_in_bytes() const {
376 // if rounding, must let FrameMap know!
377
378 // The frame_map records size in slots (32bit word)
379
380 // subtract two words to account for return address and link
381 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
382 }
383
384
385 int LIR_Assembler::emit_exception_handler() {
386 // generate code for exception handler
387 address handler_base = __ start_a_stub(exception_handler_size());
388 if (handler_base == nullptr) {
389 // not enough space left for the handler
390 bailout("exception handler overflow");
391 return -1;
392 }
393
394 int offset = code_offset();
395
396 // the exception oop and pc are in rax, and rdx
397 // no other registers need to be preserved, so invalidate them
398 __ invalidate_registers(false, true, true, false, true, true);
399
400 // check that there is really an exception
401 __ verify_not_null_oop(rax);
402
403 // search an exception handler (rax: exception oop, rdx: throwing pc)
404 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
405 __ should_not_reach_here();
406 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
407 __ end_a_stub();
408
409 return offset;
410 }
411
412
413 // Emit the code to remove the frame from the stack in the exception
414 // unwind path.
415 int LIR_Assembler::emit_unwind_handler() {
416 #ifndef PRODUCT
417 if (CommentedAssembly) {
418 _masm->block_comment("Unwind handler");
419 }
420 #endif
421
422 int offset = code_offset();
423
424 // Fetch the exception from TLS and clear out exception related thread state
425 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
426 NOT_LP64(__ get_thread(thread));
427 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
428 __ movptr(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
429 __ movptr(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
430
431 __ bind(_unwind_handler_entry);
432 __ verify_not_null_oop(rax);
433 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
434 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
435 }
436
437 // Perform needed unlocking
438 MonitorExitStub* stub = nullptr;
439 if (method()->is_synchronized()) {
440 monitor_address(0, FrameMap::rax_opr);
441 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
442 if (LockingMode == LM_MONITOR) {
443 __ jmp(*stub->entry());
444 } else {
445 __ unlock_object(rdi, rsi, rax, *stub->entry());
446 }
447 __ bind(*stub->continuation());
448 }
449
450 if (compilation()->env()->dtrace_method_probes()) {
451 #ifdef _LP64
452 __ mov(rdi, r15_thread);
453 __ mov_metadata(rsi, method()->constant_encoding());
454 #else
455 __ get_thread(rax);
456 __ movptr(Address(rsp, 0), rax);
457 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding(), noreg);
458 #endif
459 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
460 }
461
462 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
463 __ mov(rax, rbx); // Restore the exception
464 }
465
466 // remove the activation and dispatch to the unwind handler
467 __ remove_frame(initial_frame_size_in_bytes());
468 __ jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
469
470 // Emit the slow path assembly
471 if (stub != nullptr) {
472 stub->emit_code(this);
473 }
474
475 return offset;
476 }
477
478
479 int LIR_Assembler::emit_deopt_handler() {
480 // generate code for exception handler
481 address handler_base = __ start_a_stub(deopt_handler_size());
482 if (handler_base == nullptr) {
483 // not enough space left for the handler
484 bailout("deopt handler overflow");
485 return -1;
486 }
487
488 int offset = code_offset();
489 InternalAddress here(__ pc());
490
491 __ pushptr(here.addr(), rscratch1);
492 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
493 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
494 __ end_a_stub();
495
496 return offset;
497 }
498
499 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
500 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
501 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
502 assert(result->fpu() == 0, "result must already be on TOS");
503 }
504
505 // Pop the stack before the safepoint code
506 __ remove_frame(initial_frame_size_in_bytes());
507
508 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
509 __ reserved_stack_check();
510 }
511
512 // Note: we do not need to round double result; float result has the right precision
513 // the poll sets the condition code, but no data registers
514
515 #ifdef _LP64
516 const Register thread = r15_thread;
517 #else
518 const Register thread = rbx;
519 __ get_thread(thread);
520 #endif
521 code_stub->set_safepoint_offset(__ offset());
522 __ relocate(relocInfo::poll_return_type);
523 __ safepoint_poll(*code_stub->entry(), thread, true /* at_return */, true /* in_nmethod */);
524 __ ret(0);
525 }
526
527
528 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
529 guarantee(info != nullptr, "Shouldn't be null");
530 int offset = __ offset();
531 #ifdef _LP64
532 const Register poll_addr = rscratch1;
533 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
534 #else
535 assert(tmp->is_cpu_register(), "needed");
536 const Register poll_addr = tmp->as_register();
537 __ get_thread(poll_addr);
538 __ movptr(poll_addr, Address(poll_addr, in_bytes(JavaThread::polling_page_offset())));
539 #endif
540 add_debug_info_for_branch(info);
541 __ relocate(relocInfo::poll_type);
542 address pre_pc = __ pc();
543 __ testl(rax, Address(poll_addr, 0));
544 address post_pc = __ pc();
545 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
546 return offset;
547 }
548
549
550 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
551 if (from_reg != to_reg) __ mov(to_reg, from_reg);
552 }
553
554 void LIR_Assembler::swap_reg(Register a, Register b) {
555 __ xchgptr(a, b);
556 }
557
558
559 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
560 assert(src->is_constant(), "should not call otherwise");
561 assert(dest->is_register(), "should not call otherwise");
562 LIR_Const* c = src->as_constant_ptr();
563
564 switch (c->type()) {
565 case T_INT: {
566 assert(patch_code == lir_patch_none, "no patching handled here");
567 __ movl(dest->as_register(), c->as_jint());
568 break;
569 }
570
571 case T_ADDRESS: {
572 assert(patch_code == lir_patch_none, "no patching handled here");
573 __ movptr(dest->as_register(), c->as_jint());
574 break;
575 }
576
577 case T_LONG: {
578 assert(patch_code == lir_patch_none, "no patching handled here");
579 #ifdef _LP64
580 if (SCCache::is_on_for_write()) {
581 // SCA needs relocation info for card table base
582 address b = c->as_pointer();
583 if (is_card_table_address(b)) {
584 __ lea(dest->as_register_lo(), ExternalAddress(b));
585 break;
586 }
587 if (AOTRuntimeConstants::contains(b)) {
588 __ load_aotrc_address(dest->as_register_lo(), b);
589 break;
590 }
591 }
592 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
593 #else
594 __ movptr(dest->as_register_lo(), c->as_jint_lo());
595 __ movptr(dest->as_register_hi(), c->as_jint_hi());
596 #endif // _LP64
597 break;
598 }
599
600 case T_OBJECT: {
601 if (patch_code != lir_patch_none) {
602 jobject2reg_with_patching(dest->as_register(), info);
603 } else {
604 __ movoop(dest->as_register(), c->as_jobject());
605 }
606 break;
607 }
608
609 case T_METADATA: {
610 if (patch_code != lir_patch_none) {
611 klass2reg_with_patching(dest->as_register(), info);
612 } else {
613 __ mov_metadata(dest->as_register(), c->as_metadata());
614 }
615 break;
616 }
617
618 case T_FLOAT: {
619 if (dest->is_single_xmm()) {
620 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
621 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
622 } else {
623 __ movflt(dest->as_xmm_float_reg(),
624 InternalAddress(float_constant(c->as_jfloat())));
625 }
626 } else {
627 #ifndef _LP64
628 assert(dest->is_single_fpu(), "must be");
629 assert(dest->fpu_regnr() == 0, "dest must be TOS");
630 if (c->is_zero_float()) {
631 __ fldz();
632 } else if (c->is_one_float()) {
633 __ fld1();
634 } else {
635 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
636 }
637 #else
638 ShouldNotReachHere();
639 #endif // !_LP64
640 }
641 break;
642 }
643
644 case T_DOUBLE: {
645 if (dest->is_double_xmm()) {
646 if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
647 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
648 } else {
649 __ movdbl(dest->as_xmm_double_reg(),
650 InternalAddress(double_constant(c->as_jdouble())));
651 }
652 } else {
653 #ifndef _LP64
654 assert(dest->is_double_fpu(), "must be");
655 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
656 if (c->is_zero_double()) {
657 __ fldz();
658 } else if (c->is_one_double()) {
659 __ fld1();
660 } else {
661 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
662 }
663 #else
664 ShouldNotReachHere();
665 #endif // !_LP64
666 }
667 break;
668 }
669
670 default:
671 ShouldNotReachHere();
672 }
673 }
674
675 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
676 assert(src->is_constant(), "should not call otherwise");
677 assert(dest->is_stack(), "should not call otherwise");
678 LIR_Const* c = src->as_constant_ptr();
679
680 switch (c->type()) {
681 case T_INT: // fall through
682 case T_FLOAT:
683 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
684 break;
685
686 case T_ADDRESS:
687 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
688 break;
689
690 case T_OBJECT:
691 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1);
692 break;
693
694 case T_LONG: // fall through
695 case T_DOUBLE:
696 #ifdef _LP64
697 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
698 lo_word_offset_in_bytes),
699 (intptr_t)c->as_jlong_bits(),
700 rscratch1);
701 #else
702 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
703 lo_word_offset_in_bytes), c->as_jint_lo_bits());
704 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
705 hi_word_offset_in_bytes), c->as_jint_hi_bits());
706 #endif // _LP64
707 break;
708
709 default:
710 ShouldNotReachHere();
711 }
712 }
713
714 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
715 assert(src->is_constant(), "should not call otherwise");
716 assert(dest->is_address(), "should not call otherwise");
717 LIR_Const* c = src->as_constant_ptr();
718 LIR_Address* addr = dest->as_address_ptr();
719
720 int null_check_here = code_offset();
721 switch (type) {
722 case T_INT: // fall through
723 case T_FLOAT:
724 __ movl(as_Address(addr), c->as_jint_bits());
725 break;
726
727 case T_ADDRESS:
728 __ movptr(as_Address(addr), c->as_jint_bits());
729 break;
730
731 case T_OBJECT: // fall through
732 case T_ARRAY:
733 if (c->as_jobject() == nullptr) {
734 if (UseCompressedOops && !wide) {
735 __ movl(as_Address(addr), NULL_WORD);
736 } else {
737 #ifdef _LP64
738 __ xorptr(rscratch1, rscratch1);
739 null_check_here = code_offset();
740 __ movptr(as_Address(addr), rscratch1);
741 #else
742 __ movptr(as_Address(addr), NULL_WORD);
743 #endif
744 }
745 } else {
746 if (is_literal_address(addr)) {
747 ShouldNotReachHere();
748 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1);
749 } else {
750 #ifdef _LP64
751 __ movoop(rscratch1, c->as_jobject());
752 if (UseCompressedOops && !wide) {
753 __ encode_heap_oop(rscratch1);
754 null_check_here = code_offset();
755 __ movl(as_Address_lo(addr), rscratch1);
756 } else {
757 null_check_here = code_offset();
758 __ movptr(as_Address_lo(addr), rscratch1);
759 }
760 #else
761 __ movoop(as_Address(addr), c->as_jobject(), noreg);
762 #endif
763 }
764 }
765 break;
766
767 case T_LONG: // fall through
768 case T_DOUBLE:
769 #ifdef _LP64
770 if (is_literal_address(addr)) {
771 ShouldNotReachHere();
772 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
773 } else {
774 __ movptr(r10, (intptr_t)c->as_jlong_bits());
775 null_check_here = code_offset();
776 __ movptr(as_Address_lo(addr), r10);
777 }
778 #else
779 // Always reachable in 32bit so this doesn't produce useless move literal
780 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
781 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
782 #endif // _LP64
783 break;
784
785 case T_BOOLEAN: // fall through
786 case T_BYTE:
787 __ movb(as_Address(addr), c->as_jint() & 0xFF);
788 break;
789
790 case T_CHAR: // fall through
791 case T_SHORT:
792 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
793 break;
794
795 default:
796 ShouldNotReachHere();
797 };
798
799 if (info != nullptr) {
800 add_debug_info_for_null_check(null_check_here, info);
801 }
802 }
803
804
805 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
806 assert(src->is_register(), "should not call otherwise");
807 assert(dest->is_register(), "should not call otherwise");
808
809 // move between cpu-registers
810 if (dest->is_single_cpu()) {
811 #ifdef _LP64
812 if (src->type() == T_LONG) {
813 // Can do LONG -> OBJECT
814 move_regs(src->as_register_lo(), dest->as_register());
815 return;
816 }
817 #endif
818 assert(src->is_single_cpu(), "must match");
819 if (src->type() == T_OBJECT) {
820 __ verify_oop(src->as_register());
821 }
822 move_regs(src->as_register(), dest->as_register());
823
824 } else if (dest->is_double_cpu()) {
825 #ifdef _LP64
826 if (is_reference_type(src->type())) {
827 // Surprising to me but we can see move of a long to t_object
828 __ verify_oop(src->as_register());
829 move_regs(src->as_register(), dest->as_register_lo());
830 return;
831 }
832 #endif
833 assert(src->is_double_cpu(), "must match");
834 Register f_lo = src->as_register_lo();
835 Register f_hi = src->as_register_hi();
836 Register t_lo = dest->as_register_lo();
837 Register t_hi = dest->as_register_hi();
838 #ifdef _LP64
839 assert(f_hi == f_lo, "must be same");
840 assert(t_hi == t_lo, "must be same");
841 move_regs(f_lo, t_lo);
842 #else
843 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
844
845
846 if (f_lo == t_hi && f_hi == t_lo) {
847 swap_reg(f_lo, f_hi);
848 } else if (f_hi == t_lo) {
849 assert(f_lo != t_hi, "overwriting register");
850 move_regs(f_hi, t_hi);
851 move_regs(f_lo, t_lo);
852 } else {
853 assert(f_hi != t_lo, "overwriting register");
854 move_regs(f_lo, t_lo);
855 move_regs(f_hi, t_hi);
856 }
857 #endif // LP64
858
859 #ifndef _LP64
860 // special moves from fpu-register to xmm-register
861 // necessary for method results
862 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
863 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
864 __ fld_s(Address(rsp, 0));
865 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
866 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
867 __ fld_d(Address(rsp, 0));
868 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
869 __ fstp_s(Address(rsp, 0));
870 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
871 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
872 __ fstp_d(Address(rsp, 0));
873 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
874 #endif // !_LP64
875
876 // move between xmm-registers
877 } else if (dest->is_single_xmm()) {
878 assert(src->is_single_xmm(), "must match");
879 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
880 } else if (dest->is_double_xmm()) {
881 assert(src->is_double_xmm(), "must match");
882 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
883
884 #ifndef _LP64
885 // move between fpu-registers (no instruction necessary because of fpu-stack)
886 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
887 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
888 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
889 #endif // !_LP64
890
891 } else {
892 ShouldNotReachHere();
893 }
894 }
895
896 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
897 assert(src->is_register(), "should not call otherwise");
898 assert(dest->is_stack(), "should not call otherwise");
899
900 if (src->is_single_cpu()) {
901 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
902 if (is_reference_type(type)) {
903 __ verify_oop(src->as_register());
904 __ movptr (dst, src->as_register());
905 } else if (type == T_METADATA || type == T_ADDRESS) {
906 __ movptr (dst, src->as_register());
907 } else {
908 __ movl (dst, src->as_register());
909 }
910
911 } else if (src->is_double_cpu()) {
912 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
913 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
914 __ movptr (dstLO, src->as_register_lo());
915 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
916
917 } else if (src->is_single_xmm()) {
918 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
919 __ movflt(dst_addr, src->as_xmm_float_reg());
920
921 } else if (src->is_double_xmm()) {
922 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
923 __ movdbl(dst_addr, src->as_xmm_double_reg());
924
925 #ifndef _LP64
926 } else if (src->is_single_fpu()) {
927 assert(src->fpu_regnr() == 0, "argument must be on TOS");
928 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
929 if (pop_fpu_stack) __ fstp_s (dst_addr);
930 else __ fst_s (dst_addr);
931
932 } else if (src->is_double_fpu()) {
933 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
934 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
935 if (pop_fpu_stack) __ fstp_d (dst_addr);
936 else __ fst_d (dst_addr);
937 #endif // !_LP64
938
939 } else {
940 ShouldNotReachHere();
941 }
942 }
943
944
945 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
946 LIR_Address* to_addr = dest->as_address_ptr();
947 PatchingStub* patch = nullptr;
948 Register compressed_src = rscratch1;
949
950 if (is_reference_type(type)) {
951 __ verify_oop(src->as_register());
952 #ifdef _LP64
953 if (UseCompressedOops && !wide) {
954 __ movptr(compressed_src, src->as_register());
955 __ encode_heap_oop(compressed_src);
956 if (patch_code != lir_patch_none) {
957 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
958 }
959 }
960 #endif
961 }
962
963 if (patch_code != lir_patch_none) {
964 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
965 Address toa = as_Address(to_addr);
966 assert(toa.disp() != 0, "must have");
967 }
968
969 int null_check_here = code_offset();
970 switch (type) {
971 case T_FLOAT: {
972 #ifdef _LP64
973 assert(src->is_single_xmm(), "not a float");
974 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
975 #else
976 if (src->is_single_xmm()) {
977 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
978 } else {
979 assert(src->is_single_fpu(), "must be");
980 assert(src->fpu_regnr() == 0, "argument must be on TOS");
981 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
982 else __ fst_s (as_Address(to_addr));
983 }
984 #endif // _LP64
985 break;
986 }
987
988 case T_DOUBLE: {
989 #ifdef _LP64
990 assert(src->is_double_xmm(), "not a double");
991 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
992 #else
993 if (src->is_double_xmm()) {
994 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
995 } else {
996 assert(src->is_double_fpu(), "must be");
997 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
998 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
999 else __ fst_d (as_Address(to_addr));
1000 }
1001 #endif // _LP64
1002 break;
1003 }
1004
1005 case T_ARRAY: // fall through
1006 case T_OBJECT: // fall through
1007 if (UseCompressedOops && !wide) {
1008 __ movl(as_Address(to_addr), compressed_src);
1009 } else {
1010 __ movptr(as_Address(to_addr), src->as_register());
1011 }
1012 break;
1013 case T_METADATA:
1014 // We get here to store a method pointer to the stack to pass to
1015 // a dtrace runtime call. This can't work on 64 bit with
1016 // compressed klass ptrs: T_METADATA can be a compressed klass
1017 // ptr or a 64 bit method pointer.
1018 LP64_ONLY(ShouldNotReachHere());
1019 __ movptr(as_Address(to_addr), src->as_register());
1020 break;
1021 case T_ADDRESS:
1022 __ movptr(as_Address(to_addr), src->as_register());
1023 break;
1024 case T_INT:
1025 __ movl(as_Address(to_addr), src->as_register());
1026 break;
1027
1028 case T_LONG: {
1029 Register from_lo = src->as_register_lo();
1030 Register from_hi = src->as_register_hi();
1031 #ifdef _LP64
1032 __ movptr(as_Address_lo(to_addr), from_lo);
1033 #else
1034 Register base = to_addr->base()->as_register();
1035 Register index = noreg;
1036 if (to_addr->index()->is_register()) {
1037 index = to_addr->index()->as_register();
1038 }
1039 if (base == from_lo || index == from_lo) {
1040 assert(base != from_hi, "can't be");
1041 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1042 __ movl(as_Address_hi(to_addr), from_hi);
1043 if (patch != nullptr) {
1044 patching_epilog(patch, lir_patch_high, base, info);
1045 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1046 patch_code = lir_patch_low;
1047 }
1048 __ movl(as_Address_lo(to_addr), from_lo);
1049 } else {
1050 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1051 __ movl(as_Address_lo(to_addr), from_lo);
1052 if (patch != nullptr) {
1053 patching_epilog(patch, lir_patch_low, base, info);
1054 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1055 patch_code = lir_patch_high;
1056 }
1057 __ movl(as_Address_hi(to_addr), from_hi);
1058 }
1059 #endif // _LP64
1060 break;
1061 }
1062
1063 case T_BYTE: // fall through
1064 case T_BOOLEAN: {
1065 Register src_reg = src->as_register();
1066 Address dst_addr = as_Address(to_addr);
1067 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1068 __ movb(dst_addr, src_reg);
1069 break;
1070 }
1071
1072 case T_CHAR: // fall through
1073 case T_SHORT:
1074 __ movw(as_Address(to_addr), src->as_register());
1075 break;
1076
1077 default:
1078 ShouldNotReachHere();
1079 }
1080 if (info != nullptr) {
1081 add_debug_info_for_null_check(null_check_here, info);
1082 }
1083
1084 if (patch_code != lir_patch_none) {
1085 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1086 }
1087 }
1088
1089
1090 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1091 assert(src->is_stack(), "should not call otherwise");
1092 assert(dest->is_register(), "should not call otherwise");
1093
1094 if (dest->is_single_cpu()) {
1095 if (is_reference_type(type)) {
1096 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1097 __ verify_oop(dest->as_register());
1098 } else if (type == T_METADATA || type == T_ADDRESS) {
1099 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1100 } else {
1101 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1102 }
1103
1104 } else if (dest->is_double_cpu()) {
1105 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1106 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1107 __ movptr(dest->as_register_lo(), src_addr_LO);
1108 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1109
1110 } else if (dest->is_single_xmm()) {
1111 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1112 __ movflt(dest->as_xmm_float_reg(), src_addr);
1113
1114 } else if (dest->is_double_xmm()) {
1115 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1116 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1117
1118 #ifndef _LP64
1119 } else if (dest->is_single_fpu()) {
1120 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1121 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1122 __ fld_s(src_addr);
1123
1124 } else if (dest->is_double_fpu()) {
1125 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1126 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1127 __ fld_d(src_addr);
1128 #endif // _LP64
1129
1130 } else {
1131 ShouldNotReachHere();
1132 }
1133 }
1134
1135
1136 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1137 if (src->is_single_stack()) {
1138 if (is_reference_type(type)) {
1139 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1140 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1141 } else {
1142 #ifndef _LP64
1143 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1144 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1145 #else
1146 //no pushl on 64bits
1147 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1148 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1149 #endif
1150 }
1151
1152 } else if (src->is_double_stack()) {
1153 #ifdef _LP64
1154 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1155 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1156 #else
1157 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1158 // push and pop the part at src + wordSize, adding wordSize for the previous push
1159 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1160 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1161 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1162 #endif // _LP64
1163
1164 } else {
1165 ShouldNotReachHere();
1166 }
1167 }
1168
1169
1170 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1171 assert(src->is_address(), "should not call otherwise");
1172 assert(dest->is_register(), "should not call otherwise");
1173
1174 LIR_Address* addr = src->as_address_ptr();
1175 Address from_addr = as_Address(addr);
1176
1177 if (addr->base()->type() == T_OBJECT) {
1178 __ verify_oop(addr->base()->as_pointer_register());
1179 }
1180
1181 switch (type) {
1182 case T_BOOLEAN: // fall through
1183 case T_BYTE: // fall through
1184 case T_CHAR: // fall through
1185 case T_SHORT:
1186 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1187 // on pre P6 processors we may get partial register stalls
1188 // so blow away the value of to_rinfo before loading a
1189 // partial word into it. Do it here so that it precedes
1190 // the potential patch point below.
1191 __ xorptr(dest->as_register(), dest->as_register());
1192 }
1193 break;
1194 default:
1195 break;
1196 }
1197
1198 PatchingStub* patch = nullptr;
1199 if (patch_code != lir_patch_none) {
1200 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1201 assert(from_addr.disp() != 0, "must have");
1202 }
1203 if (info != nullptr) {
1204 add_debug_info_for_null_check_here(info);
1205 }
1206
1207 switch (type) {
1208 case T_FLOAT: {
1209 if (dest->is_single_xmm()) {
1210 __ movflt(dest->as_xmm_float_reg(), from_addr);
1211 } else {
1212 #ifndef _LP64
1213 assert(dest->is_single_fpu(), "must be");
1214 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1215 __ fld_s(from_addr);
1216 #else
1217 ShouldNotReachHere();
1218 #endif // !LP64
1219 }
1220 break;
1221 }
1222
1223 case T_DOUBLE: {
1224 if (dest->is_double_xmm()) {
1225 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1226 } else {
1227 #ifndef _LP64
1228 assert(dest->is_double_fpu(), "must be");
1229 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1230 __ fld_d(from_addr);
1231 #else
1232 ShouldNotReachHere();
1233 #endif // !LP64
1234 }
1235 break;
1236 }
1237
1238 case T_OBJECT: // fall through
1239 case T_ARRAY: // fall through
1240 if (UseCompressedOops && !wide) {
1241 __ movl(dest->as_register(), from_addr);
1242 } else {
1243 __ movptr(dest->as_register(), from_addr);
1244 }
1245 break;
1246
1247 case T_ADDRESS:
1248 __ movptr(dest->as_register(), from_addr);
1249 break;
1250 case T_INT:
1251 __ movl(dest->as_register(), from_addr);
1252 break;
1253
1254 case T_LONG: {
1255 Register to_lo = dest->as_register_lo();
1256 Register to_hi = dest->as_register_hi();
1257 #ifdef _LP64
1258 __ movptr(to_lo, as_Address_lo(addr));
1259 #else
1260 Register base = addr->base()->as_register();
1261 Register index = noreg;
1262 if (addr->index()->is_register()) {
1263 index = addr->index()->as_register();
1264 }
1265 if ((base == to_lo && index == to_hi) ||
1266 (base == to_hi && index == to_lo)) {
1267 // addresses with 2 registers are only formed as a result of
1268 // array access so this code will never have to deal with
1269 // patches or null checks.
1270 assert(info == nullptr && patch == nullptr, "must be");
1271 __ lea(to_hi, as_Address(addr));
1272 __ movl(to_lo, Address(to_hi, 0));
1273 __ movl(to_hi, Address(to_hi, BytesPerWord));
1274 } else if (base == to_lo || index == to_lo) {
1275 assert(base != to_hi, "can't be");
1276 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1277 __ movl(to_hi, as_Address_hi(addr));
1278 if (patch != nullptr) {
1279 patching_epilog(patch, lir_patch_high, base, info);
1280 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1281 patch_code = lir_patch_low;
1282 }
1283 __ movl(to_lo, as_Address_lo(addr));
1284 } else {
1285 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1286 __ movl(to_lo, as_Address_lo(addr));
1287 if (patch != nullptr) {
1288 patching_epilog(patch, lir_patch_low, base, info);
1289 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1290 patch_code = lir_patch_high;
1291 }
1292 __ movl(to_hi, as_Address_hi(addr));
1293 }
1294 #endif // _LP64
1295 break;
1296 }
1297
1298 case T_BOOLEAN: // fall through
1299 case T_BYTE: {
1300 Register dest_reg = dest->as_register();
1301 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1302 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1303 __ movsbl(dest_reg, from_addr);
1304 } else {
1305 __ movb(dest_reg, from_addr);
1306 __ shll(dest_reg, 24);
1307 __ sarl(dest_reg, 24);
1308 }
1309 break;
1310 }
1311
1312 case T_CHAR: {
1313 Register dest_reg = dest->as_register();
1314 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1315 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1316 __ movzwl(dest_reg, from_addr);
1317 } else {
1318 __ movw(dest_reg, from_addr);
1319 }
1320 break;
1321 }
1322
1323 case T_SHORT: {
1324 Register dest_reg = dest->as_register();
1325 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1326 __ movswl(dest_reg, from_addr);
1327 } else {
1328 __ movw(dest_reg, from_addr);
1329 __ shll(dest_reg, 16);
1330 __ sarl(dest_reg, 16);
1331 }
1332 break;
1333 }
1334
1335 default:
1336 ShouldNotReachHere();
1337 }
1338
1339 if (patch != nullptr) {
1340 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1341 }
1342
1343 if (is_reference_type(type)) {
1344 #ifdef _LP64
1345 if (UseCompressedOops && !wide) {
1346 __ decode_heap_oop(dest->as_register());
1347 }
1348 #endif
1349
1350 __ verify_oop(dest->as_register());
1351 }
1352 }
1353
1354
1355 NEEDS_CLEANUP; // This could be static?
1356 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1357 int elem_size = type2aelembytes(type);
1358 switch (elem_size) {
1359 case 1: return Address::times_1;
1360 case 2: return Address::times_2;
1361 case 4: return Address::times_4;
1362 case 8: return Address::times_8;
1363 }
1364 ShouldNotReachHere();
1365 return Address::no_scale;
1366 }
1367
1368
1369 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1370 switch (op->code()) {
1371 case lir_idiv:
1372 case lir_irem:
1373 arithmetic_idiv(op->code(),
1374 op->in_opr1(),
1375 op->in_opr2(),
1376 op->in_opr3(),
1377 op->result_opr(),
1378 op->info());
1379 break;
1380 case lir_fmad:
1381 __ fmad(op->result_opr()->as_xmm_double_reg(),
1382 op->in_opr1()->as_xmm_double_reg(),
1383 op->in_opr2()->as_xmm_double_reg(),
1384 op->in_opr3()->as_xmm_double_reg());
1385 break;
1386 case lir_fmaf:
1387 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1388 op->in_opr1()->as_xmm_float_reg(),
1389 op->in_opr2()->as_xmm_float_reg(),
1390 op->in_opr3()->as_xmm_float_reg());
1391 break;
1392 default: ShouldNotReachHere(); break;
1393 }
1394 }
1395
1396 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1397 #ifdef ASSERT
1398 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1399 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1400 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1401 #endif
1402
1403 if (op->cond() == lir_cond_always) {
1404 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1405 __ jmp (*(op->label()));
1406 } else {
1407 Assembler::Condition acond = Assembler::zero;
1408 if (op->code() == lir_cond_float_branch) {
1409 assert(op->ublock() != nullptr, "must have unordered successor");
1410 __ jcc(Assembler::parity, *(op->ublock()->label()));
1411 switch(op->cond()) {
1412 case lir_cond_equal: acond = Assembler::equal; break;
1413 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1414 case lir_cond_less: acond = Assembler::below; break;
1415 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1416 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1417 case lir_cond_greater: acond = Assembler::above; break;
1418 default: ShouldNotReachHere();
1419 }
1420 } else {
1421 switch (op->cond()) {
1422 case lir_cond_equal: acond = Assembler::equal; break;
1423 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1424 case lir_cond_less: acond = Assembler::less; break;
1425 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1426 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1427 case lir_cond_greater: acond = Assembler::greater; break;
1428 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1429 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1430 default: ShouldNotReachHere();
1431 }
1432 }
1433 __ jcc(acond,*(op->label()));
1434 }
1435 }
1436
1437 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1438 LIR_Opr src = op->in_opr();
1439 LIR_Opr dest = op->result_opr();
1440
1441 switch (op->bytecode()) {
1442 case Bytecodes::_i2l:
1443 #ifdef _LP64
1444 __ movl2ptr(dest->as_register_lo(), src->as_register());
1445 #else
1446 move_regs(src->as_register(), dest->as_register_lo());
1447 move_regs(src->as_register(), dest->as_register_hi());
1448 __ sarl(dest->as_register_hi(), 31);
1449 #endif // LP64
1450 break;
1451
1452 case Bytecodes::_l2i:
1453 #ifdef _LP64
1454 __ movl(dest->as_register(), src->as_register_lo());
1455 #else
1456 move_regs(src->as_register_lo(), dest->as_register());
1457 #endif
1458 break;
1459
1460 case Bytecodes::_i2b:
1461 move_regs(src->as_register(), dest->as_register());
1462 __ sign_extend_byte(dest->as_register());
1463 break;
1464
1465 case Bytecodes::_i2c:
1466 move_regs(src->as_register(), dest->as_register());
1467 __ andl(dest->as_register(), 0xFFFF);
1468 break;
1469
1470 case Bytecodes::_i2s:
1471 move_regs(src->as_register(), dest->as_register());
1472 __ sign_extend_short(dest->as_register());
1473 break;
1474
1475
1476 #ifdef _LP64
1477 case Bytecodes::_f2d:
1478 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1479 break;
1480
1481 case Bytecodes::_d2f:
1482 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1483 break;
1484
1485 case Bytecodes::_i2f:
1486 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1487 break;
1488
1489 case Bytecodes::_i2d:
1490 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1491 break;
1492
1493 case Bytecodes::_l2f:
1494 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1495 break;
1496
1497 case Bytecodes::_l2d:
1498 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1499 break;
1500
1501 case Bytecodes::_f2i:
1502 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1503 break;
1504
1505 case Bytecodes::_d2i:
1506 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1507 break;
1508
1509 case Bytecodes::_f2l:
1510 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1511 break;
1512
1513 case Bytecodes::_d2l:
1514 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1515 break;
1516 #else
1517 case Bytecodes::_f2d:
1518 case Bytecodes::_d2f:
1519 if (dest->is_single_xmm()) {
1520 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1521 } else if (dest->is_double_xmm()) {
1522 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1523 } else {
1524 assert(src->fpu() == dest->fpu(), "register must be equal");
1525 // do nothing (float result is rounded later through spilling)
1526 }
1527 break;
1528
1529 case Bytecodes::_i2f:
1530 case Bytecodes::_i2d:
1531 if (dest->is_single_xmm()) {
1532 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1533 } else if (dest->is_double_xmm()) {
1534 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1535 } else {
1536 assert(dest->fpu() == 0, "result must be on TOS");
1537 __ movl(Address(rsp, 0), src->as_register());
1538 __ fild_s(Address(rsp, 0));
1539 }
1540 break;
1541
1542 case Bytecodes::_l2f:
1543 case Bytecodes::_l2d:
1544 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1545 assert(dest->fpu() == 0, "result must be on TOS");
1546 __ movptr(Address(rsp, 0), src->as_register_lo());
1547 __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
1548 __ fild_d(Address(rsp, 0));
1549 // float result is rounded later through spilling
1550 break;
1551
1552 case Bytecodes::_f2i:
1553 case Bytecodes::_d2i:
1554 if (src->is_single_xmm()) {
1555 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1556 } else if (src->is_double_xmm()) {
1557 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1558 } else {
1559 assert(src->fpu() == 0, "input must be on TOS");
1560 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc()));
1561 __ fist_s(Address(rsp, 0));
1562 __ movl(dest->as_register(), Address(rsp, 0));
1563 __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
1564 }
1565 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1566 assert(op->stub() != nullptr, "stub required");
1567 __ cmpl(dest->as_register(), 0x80000000);
1568 __ jcc(Assembler::equal, *op->stub()->entry());
1569 __ bind(*op->stub()->continuation());
1570 break;
1571
1572 case Bytecodes::_f2l:
1573 case Bytecodes::_d2l:
1574 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1575 assert(src->fpu() == 0, "input must be on TOS");
1576 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1577
1578 // instruction sequence too long to inline it here
1579 {
1580 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::fpu2long_stub_id)));
1581 }
1582 break;
1583 #endif // _LP64
1584
1585 default: ShouldNotReachHere();
1586 }
1587 }
1588
1589 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1590 if (op->init_check()) {
1591 add_debug_info_for_null_check_here(op->stub()->info());
1592 // init_state needs acquire, but x86 is TSO, and so we are already good.
1593 __ cmpb(Address(op->klass()->as_register(),
1594 InstanceKlass::init_state_offset()),
1595 InstanceKlass::fully_initialized);
1596 __ jcc(Assembler::notEqual, *op->stub()->entry());
1597 }
1598 __ allocate_object(op->obj()->as_register(),
1599 op->tmp1()->as_register(),
1600 op->tmp2()->as_register(),
1601 op->header_size(),
1602 op->object_size(),
1603 op->klass()->as_register(),
1604 *op->stub()->entry());
1605 __ bind(*op->stub()->continuation());
1606 }
1607
1608 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1609 Register len = op->len()->as_register();
1610 LP64_ONLY( __ movslq(len, len); )
1611
1612 if (UseSlowPath ||
1613 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1614 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1615 __ jmp(*op->stub()->entry());
1616 } else {
1617 Register tmp1 = op->tmp1()->as_register();
1618 Register tmp2 = op->tmp2()->as_register();
1619 Register tmp3 = op->tmp3()->as_register();
1620 if (len == tmp1) {
1621 tmp1 = tmp3;
1622 } else if (len == tmp2) {
1623 tmp2 = tmp3;
1624 } else if (len == tmp3) {
1625 // everything is ok
1626 } else {
1627 __ mov(tmp3, len);
1628 }
1629 __ allocate_array(op->obj()->as_register(),
1630 len,
1631 tmp1,
1632 tmp2,
1633 arrayOopDesc::base_offset_in_bytes(op->type()),
1634 array_element_size(op->type()),
1635 op->klass()->as_register(),
1636 *op->stub()->entry(),
1637 op->zero_array());
1638 }
1639 __ bind(*op->stub()->continuation());
1640 }
1641
1642 void LIR_Assembler::type_profile_helper(Register mdo,
1643 ciMethodData *md, ciProfileData *data,
1644 Register recv, Label* update_done) {
1645 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1646 Label next_test;
1647 // See if the receiver is receiver[n].
1648 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1649 __ jccb(Assembler::notEqual, next_test);
1650 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1651 __ addptr(data_addr, DataLayout::counter_increment);
1652 __ jmp(*update_done);
1653 __ bind(next_test);
1654 }
1655
1656 // Didn't find receiver; find next empty slot and fill it in
1657 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1658 Label next_test;
1659 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1660 __ cmpptr(recv_addr, NULL_WORD);
1661 __ jccb(Assembler::notEqual, next_test);
1662 __ movptr(recv_addr, recv);
1663 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1664 __ jmp(*update_done);
1665 __ bind(next_test);
1666 }
1667 }
1668
1669 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1670 // we always need a stub for the failure case.
1671 CodeStub* stub = op->stub();
1672 Register obj = op->object()->as_register();
1673 Register k_RInfo = op->tmp1()->as_register();
1674 Register klass_RInfo = op->tmp2()->as_register();
1675 Register dst = op->result_opr()->as_register();
1676 ciKlass* k = op->klass();
1677 Register Rtmp1 = noreg;
1678 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1679
1680 // check if it needs to be profiled
1681 ciMethodData* md = nullptr;
1682 ciProfileData* data = nullptr;
1683
1684 if (op->should_profile()) {
1685 ciMethod* method = op->profiled_method();
1686 assert(method != nullptr, "Should have method");
1687 int bci = op->profiled_bci();
1688 md = method->method_data_or_null();
1689 assert(md != nullptr, "Sanity");
1690 data = md->bci_to_data(bci);
1691 assert(data != nullptr, "need data for type check");
1692 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1693 }
1694 Label* success_target = success;
1695 Label* failure_target = failure;
1696
1697 if (obj == k_RInfo) {
1698 k_RInfo = dst;
1699 } else if (obj == klass_RInfo) {
1700 klass_RInfo = dst;
1701 }
1702 if (k->is_loaded() && !UseCompressedClassPointers) {
1703 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1704 } else {
1705 Rtmp1 = op->tmp3()->as_register();
1706 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1707 }
1708
1709 assert_different_registers(obj, k_RInfo, klass_RInfo);
1710
1711 __ testptr(obj, obj);
1712 if (op->should_profile()) {
1713 Label not_null;
1714 Register mdo = klass_RInfo;
1715 __ mov_metadata(mdo, md->constant_encoding());
1716 __ jccb(Assembler::notEqual, not_null);
1717 // Object is null; update MDO and exit
1718 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1719 int header_bits = BitData::null_seen_byte_constant();
1720 __ orb(data_addr, header_bits);
1721 __ jmp(*obj_is_null);
1722 __ bind(not_null);
1723
1724 Label update_done;
1725 Register recv = k_RInfo;
1726 __ load_klass(recv, obj, tmp_load_klass);
1727 type_profile_helper(mdo, md, data, recv, &update_done);
1728
1729 Address nonprofiled_receiver_count_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1730 __ addptr(nonprofiled_receiver_count_addr, DataLayout::counter_increment);
1731
1732 __ bind(update_done);
1733 } else {
1734 __ jcc(Assembler::equal, *obj_is_null);
1735 }
1736
1737 if (!k->is_loaded()) {
1738 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1739 } else {
1740 #ifdef _LP64
1741 __ mov_metadata(k_RInfo, k->constant_encoding());
1742 #endif // _LP64
1743 }
1744 __ verify_oop(obj);
1745
1746 if (op->fast_check()) {
1747 // get object class
1748 // not a safepoint as obj null check happens earlier
1749 #ifdef _LP64
1750 if (UseCompressedClassPointers) {
1751 __ load_klass(Rtmp1, obj, tmp_load_klass);
1752 __ cmpptr(k_RInfo, Rtmp1);
1753 } else {
1754 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1755 }
1756 #else
1757 if (k->is_loaded()) {
1758 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1759 } else {
1760 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1761 }
1762 #endif
1763 __ jcc(Assembler::notEqual, *failure_target);
1764 // successful cast, fall through to profile or jump
1765 } else {
1766 // get object class
1767 // not a safepoint as obj null check happens earlier
1768 __ load_klass(klass_RInfo, obj, tmp_load_klass);
1769 if (k->is_loaded()) {
1770 // See if we get an immediate positive hit
1771 #ifdef _LP64
1772 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1773 #else
1774 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1775 #endif // _LP64
1776 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1777 __ jcc(Assembler::notEqual, *failure_target);
1778 // successful cast, fall through to profile or jump
1779 } else {
1780 // See if we get an immediate positive hit
1781 __ jcc(Assembler::equal, *success_target);
1782 // check for self
1783 #ifdef _LP64
1784 __ cmpptr(klass_RInfo, k_RInfo);
1785 #else
1786 __ cmpklass(klass_RInfo, k->constant_encoding());
1787 #endif // _LP64
1788 __ jcc(Assembler::equal, *success_target);
1789
1790 __ push(klass_RInfo);
1791 #ifdef _LP64
1792 __ push(k_RInfo);
1793 #else
1794 __ pushklass(k->constant_encoding(), noreg);
1795 #endif // _LP64
1796 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1797 __ pop(klass_RInfo);
1798 __ pop(klass_RInfo);
1799 // result is a boolean
1800 __ testl(klass_RInfo, klass_RInfo);
1801 __ jcc(Assembler::equal, *failure_target);
1802 // successful cast, fall through to profile or jump
1803 }
1804 } else {
1805 // perform the fast part of the checking logic
1806 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1807 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1808 __ push(klass_RInfo);
1809 __ push(k_RInfo);
1810 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1811 __ pop(klass_RInfo);
1812 __ pop(k_RInfo);
1813 // result is a boolean
1814 __ testl(k_RInfo, k_RInfo);
1815 __ jcc(Assembler::equal, *failure_target);
1816 // successful cast, fall through to profile or jump
1817 }
1818 }
1819 __ jmp(*success);
1820 }
1821
1822
1823 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1824 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
1825 LIR_Code code = op->code();
1826 if (code == lir_store_check) {
1827 Register value = op->object()->as_register();
1828 Register array = op->array()->as_register();
1829 Register k_RInfo = op->tmp1()->as_register();
1830 Register klass_RInfo = op->tmp2()->as_register();
1831 Register Rtmp1 = op->tmp3()->as_register();
1832
1833 CodeStub* stub = op->stub();
1834
1835 // check if it needs to be profiled
1836 ciMethodData* md = nullptr;
1837 ciProfileData* data = nullptr;
1838
1839 if (op->should_profile()) {
1840 ciMethod* method = op->profiled_method();
1841 assert(method != nullptr, "Should have method");
1842 int bci = op->profiled_bci();
1843 md = method->method_data_or_null();
1844 assert(md != nullptr, "Sanity");
1845 data = md->bci_to_data(bci);
1846 assert(data != nullptr, "need data for type check");
1847 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1848 }
1849 Label done;
1850 Label* success_target = &done;
1851 Label* failure_target = stub->entry();
1852
1853 __ testptr(value, value);
1854 if (op->should_profile()) {
1855 Label not_null;
1856 Register mdo = klass_RInfo;
1857 __ mov_metadata(mdo, md->constant_encoding());
1858 __ jccb(Assembler::notEqual, not_null);
1859 // Object is null; update MDO and exit
1860 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1861 int header_bits = BitData::null_seen_byte_constant();
1862 __ orb(data_addr, header_bits);
1863 __ jmp(done);
1864 __ bind(not_null);
1865
1866 Label update_done;
1867 Register recv = k_RInfo;
1868 __ load_klass(recv, value, tmp_load_klass);
1869 type_profile_helper(mdo, md, data, recv, &update_done);
1870
1871 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1872 __ addptr(counter_addr, DataLayout::counter_increment);
1873 __ bind(update_done);
1874 } else {
1875 __ jcc(Assembler::equal, done);
1876 }
1877
1878 add_debug_info_for_null_check_here(op->info_for_exception());
1879 __ load_klass(k_RInfo, array, tmp_load_klass);
1880 __ load_klass(klass_RInfo, value, tmp_load_klass);
1881
1882 // get instance klass (it's already uncompressed)
1883 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1884 // perform the fast part of the checking logic
1885 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1886 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1887 __ push(klass_RInfo);
1888 __ push(k_RInfo);
1889 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1890 __ pop(klass_RInfo);
1891 __ pop(k_RInfo);
1892 // result is a boolean
1893 __ testl(k_RInfo, k_RInfo);
1894 __ jcc(Assembler::equal, *failure_target);
1895 // fall through to the success case
1896
1897 __ bind(done);
1898 } else
1899 if (code == lir_checkcast) {
1900 Register obj = op->object()->as_register();
1901 Register dst = op->result_opr()->as_register();
1902 Label success;
1903 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1904 __ bind(success);
1905 if (dst != obj) {
1906 __ mov(dst, obj);
1907 }
1908 } else
1909 if (code == lir_instanceof) {
1910 Register obj = op->object()->as_register();
1911 Register dst = op->result_opr()->as_register();
1912 Label success, failure, done;
1913 emit_typecheck_helper(op, &success, &failure, &failure);
1914 __ bind(failure);
1915 __ xorptr(dst, dst);
1916 __ jmpb(done);
1917 __ bind(success);
1918 __ movptr(dst, 1);
1919 __ bind(done);
1920 } else {
1921 ShouldNotReachHere();
1922 }
1923
1924 }
1925
1926
1927 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1928 if (LP64_ONLY(false &&) op->code() == lir_cas_long) {
1929 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1930 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1931 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1932 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1933 Register addr = op->addr()->as_register();
1934 __ lock();
1935 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1936
1937 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1938 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1939 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1940 Register newval = op->new_value()->as_register();
1941 Register cmpval = op->cmp_value()->as_register();
1942 assert(cmpval == rax, "wrong register");
1943 assert(newval != noreg, "new val must be register");
1944 assert(cmpval != newval, "cmp and new values must be in different registers");
1945 assert(cmpval != addr, "cmp and addr must be in different registers");
1946 assert(newval != addr, "new value and addr must be in different registers");
1947
1948 if ( op->code() == lir_cas_obj) {
1949 #ifdef _LP64
1950 if (UseCompressedOops) {
1951 __ encode_heap_oop(cmpval);
1952 __ mov(rscratch1, newval);
1953 __ encode_heap_oop(rscratch1);
1954 __ lock();
1955 // cmpval (rax) is implicitly used by this instruction
1956 __ cmpxchgl(rscratch1, Address(addr, 0));
1957 } else
1958 #endif
1959 {
1960 __ lock();
1961 __ cmpxchgptr(newval, Address(addr, 0));
1962 }
1963 } else {
1964 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1965 __ lock();
1966 __ cmpxchgl(newval, Address(addr, 0));
1967 }
1968 #ifdef _LP64
1969 } else if (op->code() == lir_cas_long) {
1970 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1971 Register newval = op->new_value()->as_register_lo();
1972 Register cmpval = op->cmp_value()->as_register_lo();
1973 assert(cmpval == rax, "wrong register");
1974 assert(newval != noreg, "new val must be register");
1975 assert(cmpval != newval, "cmp and new values must be in different registers");
1976 assert(cmpval != addr, "cmp and addr must be in different registers");
1977 assert(newval != addr, "new value and addr must be in different registers");
1978 __ lock();
1979 __ cmpxchgq(newval, Address(addr, 0));
1980 #endif // _LP64
1981 } else {
1982 Unimplemented();
1983 }
1984 }
1985
1986 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1987 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1988 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
1989
1990 Assembler::Condition acond, ncond;
1991 switch (condition) {
1992 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1993 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1994 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1995 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1996 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1997 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1998 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1999 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2000 default: acond = Assembler::equal; ncond = Assembler::notEqual;
2001 ShouldNotReachHere();
2002 }
2003
2004 if (opr1->is_cpu_register()) {
2005 reg2reg(opr1, result);
2006 } else if (opr1->is_stack()) {
2007 stack2reg(opr1, result, result->type());
2008 } else if (opr1->is_constant()) {
2009 const2reg(opr1, result, lir_patch_none, nullptr);
2010 } else {
2011 ShouldNotReachHere();
2012 }
2013
2014 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2015 // optimized version that does not require a branch
2016 if (opr2->is_single_cpu()) {
2017 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2018 __ cmov(ncond, result->as_register(), opr2->as_register());
2019 } else if (opr2->is_double_cpu()) {
2020 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2021 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2022 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2023 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2024 } else if (opr2->is_single_stack()) {
2025 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2026 } else if (opr2->is_double_stack()) {
2027 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2028 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2029 } else {
2030 ShouldNotReachHere();
2031 }
2032
2033 } else {
2034 Label skip;
2035 __ jccb(acond, skip);
2036 if (opr2->is_cpu_register()) {
2037 reg2reg(opr2, result);
2038 } else if (opr2->is_stack()) {
2039 stack2reg(opr2, result, result->type());
2040 } else if (opr2->is_constant()) {
2041 const2reg(opr2, result, lir_patch_none, nullptr);
2042 } else {
2043 ShouldNotReachHere();
2044 }
2045 __ bind(skip);
2046 }
2047 }
2048
2049
2050 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2051 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2052
2053 if (left->is_single_cpu()) {
2054 assert(left == dest, "left and dest must be equal");
2055 Register lreg = left->as_register();
2056
2057 if (right->is_single_cpu()) {
2058 // cpu register - cpu register
2059 Register rreg = right->as_register();
2060 switch (code) {
2061 case lir_add: __ addl (lreg, rreg); break;
2062 case lir_sub: __ subl (lreg, rreg); break;
2063 case lir_mul: __ imull(lreg, rreg); break;
2064 default: ShouldNotReachHere();
2065 }
2066
2067 } else if (right->is_stack()) {
2068 // cpu register - stack
2069 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2070 switch (code) {
2071 case lir_add: __ addl(lreg, raddr); break;
2072 case lir_sub: __ subl(lreg, raddr); break;
2073 default: ShouldNotReachHere();
2074 }
2075
2076 } else if (right->is_constant()) {
2077 // cpu register - constant
2078 jint c = right->as_constant_ptr()->as_jint();
2079 switch (code) {
2080 case lir_add: {
2081 __ incrementl(lreg, c);
2082 break;
2083 }
2084 case lir_sub: {
2085 __ decrementl(lreg, c);
2086 break;
2087 }
2088 default: ShouldNotReachHere();
2089 }
2090
2091 } else {
2092 ShouldNotReachHere();
2093 }
2094
2095 } else if (left->is_double_cpu()) {
2096 assert(left == dest, "left and dest must be equal");
2097 Register lreg_lo = left->as_register_lo();
2098 Register lreg_hi = left->as_register_hi();
2099
2100 if (right->is_double_cpu()) {
2101 // cpu register - cpu register
2102 Register rreg_lo = right->as_register_lo();
2103 Register rreg_hi = right->as_register_hi();
2104 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2105 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2106 switch (code) {
2107 case lir_add:
2108 __ addptr(lreg_lo, rreg_lo);
2109 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2110 break;
2111 case lir_sub:
2112 __ subptr(lreg_lo, rreg_lo);
2113 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2114 break;
2115 case lir_mul:
2116 #ifdef _LP64
2117 __ imulq(lreg_lo, rreg_lo);
2118 #else
2119 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2120 __ imull(lreg_hi, rreg_lo);
2121 __ imull(rreg_hi, lreg_lo);
2122 __ addl (rreg_hi, lreg_hi);
2123 __ mull (rreg_lo);
2124 __ addl (lreg_hi, rreg_hi);
2125 #endif // _LP64
2126 break;
2127 default:
2128 ShouldNotReachHere();
2129 }
2130
2131 } else if (right->is_constant()) {
2132 // cpu register - constant
2133 #ifdef _LP64
2134 jlong c = right->as_constant_ptr()->as_jlong_bits();
2135 __ movptr(r10, (intptr_t) c);
2136 switch (code) {
2137 case lir_add:
2138 __ addptr(lreg_lo, r10);
2139 break;
2140 case lir_sub:
2141 __ subptr(lreg_lo, r10);
2142 break;
2143 default:
2144 ShouldNotReachHere();
2145 }
2146 #else
2147 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2148 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2149 switch (code) {
2150 case lir_add:
2151 __ addptr(lreg_lo, c_lo);
2152 __ adcl(lreg_hi, c_hi);
2153 break;
2154 case lir_sub:
2155 __ subptr(lreg_lo, c_lo);
2156 __ sbbl(lreg_hi, c_hi);
2157 break;
2158 default:
2159 ShouldNotReachHere();
2160 }
2161 #endif // _LP64
2162
2163 } else {
2164 ShouldNotReachHere();
2165 }
2166
2167 } else if (left->is_single_xmm()) {
2168 assert(left == dest, "left and dest must be equal");
2169 XMMRegister lreg = left->as_xmm_float_reg();
2170
2171 if (right->is_single_xmm()) {
2172 XMMRegister rreg = right->as_xmm_float_reg();
2173 switch (code) {
2174 case lir_add: __ addss(lreg, rreg); break;
2175 case lir_sub: __ subss(lreg, rreg); break;
2176 case lir_mul: __ mulss(lreg, rreg); break;
2177 case lir_div: __ divss(lreg, rreg); break;
2178 default: ShouldNotReachHere();
2179 }
2180 } else {
2181 Address raddr;
2182 if (right->is_single_stack()) {
2183 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2184 } else if (right->is_constant()) {
2185 // hack for now
2186 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2187 } else {
2188 ShouldNotReachHere();
2189 }
2190 switch (code) {
2191 case lir_add: __ addss(lreg, raddr); break;
2192 case lir_sub: __ subss(lreg, raddr); break;
2193 case lir_mul: __ mulss(lreg, raddr); break;
2194 case lir_div: __ divss(lreg, raddr); break;
2195 default: ShouldNotReachHere();
2196 }
2197 }
2198
2199 } else if (left->is_double_xmm()) {
2200 assert(left == dest, "left and dest must be equal");
2201
2202 XMMRegister lreg = left->as_xmm_double_reg();
2203 if (right->is_double_xmm()) {
2204 XMMRegister rreg = right->as_xmm_double_reg();
2205 switch (code) {
2206 case lir_add: __ addsd(lreg, rreg); break;
2207 case lir_sub: __ subsd(lreg, rreg); break;
2208 case lir_mul: __ mulsd(lreg, rreg); break;
2209 case lir_div: __ divsd(lreg, rreg); break;
2210 default: ShouldNotReachHere();
2211 }
2212 } else {
2213 Address raddr;
2214 if (right->is_double_stack()) {
2215 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2216 } else if (right->is_constant()) {
2217 // hack for now
2218 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2219 } else {
2220 ShouldNotReachHere();
2221 }
2222 switch (code) {
2223 case lir_add: __ addsd(lreg, raddr); break;
2224 case lir_sub: __ subsd(lreg, raddr); break;
2225 case lir_mul: __ mulsd(lreg, raddr); break;
2226 case lir_div: __ divsd(lreg, raddr); break;
2227 default: ShouldNotReachHere();
2228 }
2229 }
2230
2231 #ifndef _LP64
2232 } else if (left->is_single_fpu()) {
2233 assert(dest->is_single_fpu(), "fpu stack allocation required");
2234
2235 if (right->is_single_fpu()) {
2236 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2237
2238 } else {
2239 assert(left->fpu_regnr() == 0, "left must be on TOS");
2240 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2241
2242 Address raddr;
2243 if (right->is_single_stack()) {
2244 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2245 } else if (right->is_constant()) {
2246 address const_addr = float_constant(right->as_jfloat());
2247 assert(const_addr != nullptr, "incorrect float/double constant maintenance");
2248 // hack for now
2249 raddr = __ as_Address(InternalAddress(const_addr));
2250 } else {
2251 ShouldNotReachHere();
2252 }
2253
2254 switch (code) {
2255 case lir_add: __ fadd_s(raddr); break;
2256 case lir_sub: __ fsub_s(raddr); break;
2257 case lir_mul: __ fmul_s(raddr); break;
2258 case lir_div: __ fdiv_s(raddr); break;
2259 default: ShouldNotReachHere();
2260 }
2261 }
2262
2263 } else if (left->is_double_fpu()) {
2264 assert(dest->is_double_fpu(), "fpu stack allocation required");
2265
2266 if (code == lir_mul || code == lir_div) {
2267 // Double values require special handling for strictfp mul/div on x86
2268 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1()));
2269 __ fmulp(left->fpu_regnrLo() + 1);
2270 }
2271
2272 if (right->is_double_fpu()) {
2273 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2274
2275 } else {
2276 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2277 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2278
2279 Address raddr;
2280 if (right->is_double_stack()) {
2281 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2282 } else if (right->is_constant()) {
2283 // hack for now
2284 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2285 } else {
2286 ShouldNotReachHere();
2287 }
2288
2289 switch (code) {
2290 case lir_add: __ fadd_d(raddr); break;
2291 case lir_sub: __ fsub_d(raddr); break;
2292 case lir_mul: __ fmul_d(raddr); break;
2293 case lir_div: __ fdiv_d(raddr); break;
2294 default: ShouldNotReachHere();
2295 }
2296 }
2297
2298 if (code == lir_mul || code == lir_div) {
2299 // Double values require special handling for strictfp mul/div on x86
2300 __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2()));
2301 __ fmulp(dest->fpu_regnrLo() + 1);
2302 }
2303 #endif // !_LP64
2304
2305 } else if (left->is_single_stack() || left->is_address()) {
2306 assert(left == dest, "left and dest must be equal");
2307
2308 Address laddr;
2309 if (left->is_single_stack()) {
2310 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2311 } else if (left->is_address()) {
2312 laddr = as_Address(left->as_address_ptr());
2313 } else {
2314 ShouldNotReachHere();
2315 }
2316
2317 if (right->is_single_cpu()) {
2318 Register rreg = right->as_register();
2319 switch (code) {
2320 case lir_add: __ addl(laddr, rreg); break;
2321 case lir_sub: __ subl(laddr, rreg); break;
2322 default: ShouldNotReachHere();
2323 }
2324 } else if (right->is_constant()) {
2325 jint c = right->as_constant_ptr()->as_jint();
2326 switch (code) {
2327 case lir_add: {
2328 __ incrementl(laddr, c);
2329 break;
2330 }
2331 case lir_sub: {
2332 __ decrementl(laddr, c);
2333 break;
2334 }
2335 default: ShouldNotReachHere();
2336 }
2337 } else {
2338 ShouldNotReachHere();
2339 }
2340
2341 } else {
2342 ShouldNotReachHere();
2343 }
2344 }
2345
2346 #ifndef _LP64
2347 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2348 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2349 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2350 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2351
2352 bool left_is_tos = (left_index == 0);
2353 bool dest_is_tos = (dest_index == 0);
2354 int non_tos_index = (left_is_tos ? right_index : left_index);
2355
2356 switch (code) {
2357 case lir_add:
2358 if (pop_fpu_stack) __ faddp(non_tos_index);
2359 else if (dest_is_tos) __ fadd (non_tos_index);
2360 else __ fadda(non_tos_index);
2361 break;
2362
2363 case lir_sub:
2364 if (left_is_tos) {
2365 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2366 else if (dest_is_tos) __ fsub (non_tos_index);
2367 else __ fsubra(non_tos_index);
2368 } else {
2369 if (pop_fpu_stack) __ fsubp (non_tos_index);
2370 else if (dest_is_tos) __ fsubr (non_tos_index);
2371 else __ fsuba (non_tos_index);
2372 }
2373 break;
2374
2375 case lir_mul:
2376 if (pop_fpu_stack) __ fmulp(non_tos_index);
2377 else if (dest_is_tos) __ fmul (non_tos_index);
2378 else __ fmula(non_tos_index);
2379 break;
2380
2381 case lir_div:
2382 if (left_is_tos) {
2383 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2384 else if (dest_is_tos) __ fdiv (non_tos_index);
2385 else __ fdivra(non_tos_index);
2386 } else {
2387 if (pop_fpu_stack) __ fdivp (non_tos_index);
2388 else if (dest_is_tos) __ fdivr (non_tos_index);
2389 else __ fdiva (non_tos_index);
2390 }
2391 break;
2392
2393 case lir_rem:
2394 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2395 __ fremr(noreg);
2396 break;
2397
2398 default:
2399 ShouldNotReachHere();
2400 }
2401 }
2402 #endif // _LP64
2403
2404
2405 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2406 if (value->is_double_xmm()) {
2407 switch(code) {
2408 case lir_abs :
2409 {
2410 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2411 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2412 }
2413 assert(!tmp->is_valid(), "do not need temporary");
2414 __ andpd(dest->as_xmm_double_reg(),
2415 ExternalAddress(LIR_Assembler::double_signmask_pool),
2416 rscratch1);
2417 }
2418 break;
2419
2420 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2421 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2422 default : ShouldNotReachHere();
2423 }
2424
2425 #ifndef _LP64
2426 } else if (value->is_double_fpu()) {
2427 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2428 switch(code) {
2429 case lir_abs : __ fabs() ; break;
2430 case lir_sqrt : __ fsqrt(); break;
2431 default : ShouldNotReachHere();
2432 }
2433 #endif // !_LP64
2434 } else if (code == lir_f2hf) {
2435 __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg());
2436 } else if (code == lir_hf2f) {
2437 __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register());
2438 } else {
2439 Unimplemented();
2440 }
2441 }
2442
2443 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2444 // assert(left->destroys_register(), "check");
2445 if (left->is_single_cpu()) {
2446 Register reg = left->as_register();
2447 if (right->is_constant()) {
2448 int val = right->as_constant_ptr()->as_jint();
2449 switch (code) {
2450 case lir_logic_and: __ andl (reg, val); break;
2451 case lir_logic_or: __ orl (reg, val); break;
2452 case lir_logic_xor: __ xorl (reg, val); break;
2453 default: ShouldNotReachHere();
2454 }
2455 } else if (right->is_stack()) {
2456 // added support for stack operands
2457 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2458 switch (code) {
2459 case lir_logic_and: __ andl (reg, raddr); break;
2460 case lir_logic_or: __ orl (reg, raddr); break;
2461 case lir_logic_xor: __ xorl (reg, raddr); break;
2462 default: ShouldNotReachHere();
2463 }
2464 } else {
2465 Register rright = right->as_register();
2466 switch (code) {
2467 case lir_logic_and: __ andptr (reg, rright); break;
2468 case lir_logic_or : __ orptr (reg, rright); break;
2469 case lir_logic_xor: __ xorptr (reg, rright); break;
2470 default: ShouldNotReachHere();
2471 }
2472 }
2473 move_regs(reg, dst->as_register());
2474 } else {
2475 Register l_lo = left->as_register_lo();
2476 Register l_hi = left->as_register_hi();
2477 if (right->is_constant()) {
2478 #ifdef _LP64
2479 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2480 switch (code) {
2481 case lir_logic_and:
2482 __ andq(l_lo, rscratch1);
2483 break;
2484 case lir_logic_or:
2485 __ orq(l_lo, rscratch1);
2486 break;
2487 case lir_logic_xor:
2488 __ xorq(l_lo, rscratch1);
2489 break;
2490 default: ShouldNotReachHere();
2491 }
2492 #else
2493 int r_lo = right->as_constant_ptr()->as_jint_lo();
2494 int r_hi = right->as_constant_ptr()->as_jint_hi();
2495 switch (code) {
2496 case lir_logic_and:
2497 __ andl(l_lo, r_lo);
2498 __ andl(l_hi, r_hi);
2499 break;
2500 case lir_logic_or:
2501 __ orl(l_lo, r_lo);
2502 __ orl(l_hi, r_hi);
2503 break;
2504 case lir_logic_xor:
2505 __ xorl(l_lo, r_lo);
2506 __ xorl(l_hi, r_hi);
2507 break;
2508 default: ShouldNotReachHere();
2509 }
2510 #endif // _LP64
2511 } else {
2512 #ifdef _LP64
2513 Register r_lo;
2514 if (is_reference_type(right->type())) {
2515 r_lo = right->as_register();
2516 } else {
2517 r_lo = right->as_register_lo();
2518 }
2519 #else
2520 Register r_lo = right->as_register_lo();
2521 Register r_hi = right->as_register_hi();
2522 assert(l_lo != r_hi, "overwriting registers");
2523 #endif
2524 switch (code) {
2525 case lir_logic_and:
2526 __ andptr(l_lo, r_lo);
2527 NOT_LP64(__ andptr(l_hi, r_hi);)
2528 break;
2529 case lir_logic_or:
2530 __ orptr(l_lo, r_lo);
2531 NOT_LP64(__ orptr(l_hi, r_hi);)
2532 break;
2533 case lir_logic_xor:
2534 __ xorptr(l_lo, r_lo);
2535 NOT_LP64(__ xorptr(l_hi, r_hi);)
2536 break;
2537 default: ShouldNotReachHere();
2538 }
2539 }
2540
2541 Register dst_lo = dst->as_register_lo();
2542 Register dst_hi = dst->as_register_hi();
2543
2544 #ifdef _LP64
2545 move_regs(l_lo, dst_lo);
2546 #else
2547 if (dst_lo == l_hi) {
2548 assert(dst_hi != l_lo, "overwriting registers");
2549 move_regs(l_hi, dst_hi);
2550 move_regs(l_lo, dst_lo);
2551 } else {
2552 assert(dst_lo != l_hi, "overwriting registers");
2553 move_regs(l_lo, dst_lo);
2554 move_regs(l_hi, dst_hi);
2555 }
2556 #endif // _LP64
2557 }
2558 }
2559
2560
2561 // we assume that rax, and rdx can be overwritten
2562 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2563
2564 assert(left->is_single_cpu(), "left must be register");
2565 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2566 assert(result->is_single_cpu(), "result must be register");
2567
2568 // assert(left->destroys_register(), "check");
2569 // assert(right->destroys_register(), "check");
2570
2571 Register lreg = left->as_register();
2572 Register dreg = result->as_register();
2573
2574 if (right->is_constant()) {
2575 jint divisor = right->as_constant_ptr()->as_jint();
2576 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2577 if (code == lir_idiv) {
2578 assert(lreg == rax, "must be rax,");
2579 assert(temp->as_register() == rdx, "tmp register must be rdx");
2580 __ cdql(); // sign extend into rdx:rax
2581 if (divisor == 2) {
2582 __ subl(lreg, rdx);
2583 } else {
2584 __ andl(rdx, divisor - 1);
2585 __ addl(lreg, rdx);
2586 }
2587 __ sarl(lreg, log2i_exact(divisor));
2588 move_regs(lreg, dreg);
2589 } else if (code == lir_irem) {
2590 Label done;
2591 __ mov(dreg, lreg);
2592 __ andl(dreg, 0x80000000 | (divisor - 1));
2593 __ jcc(Assembler::positive, done);
2594 __ decrement(dreg);
2595 __ orl(dreg, ~(divisor - 1));
2596 __ increment(dreg);
2597 __ bind(done);
2598 } else {
2599 ShouldNotReachHere();
2600 }
2601 } else {
2602 Register rreg = right->as_register();
2603 assert(lreg == rax, "left register must be rax,");
2604 assert(rreg != rdx, "right register must not be rdx");
2605 assert(temp->as_register() == rdx, "tmp register must be rdx");
2606
2607 move_regs(lreg, rax);
2608
2609 int idivl_offset = __ corrected_idivl(rreg);
2610 if (ImplicitDiv0Checks) {
2611 add_debug_info_for_div0(idivl_offset, info);
2612 }
2613 if (code == lir_irem) {
2614 move_regs(rdx, dreg); // result is in rdx
2615 } else {
2616 move_regs(rax, dreg);
2617 }
2618 }
2619 }
2620
2621
2622 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2623 if (opr1->is_single_cpu()) {
2624 Register reg1 = opr1->as_register();
2625 if (opr2->is_single_cpu()) {
2626 // cpu register - cpu register
2627 if (is_reference_type(opr1->type())) {
2628 __ cmpoop(reg1, opr2->as_register());
2629 } else {
2630 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2631 __ cmpl(reg1, opr2->as_register());
2632 }
2633 } else if (opr2->is_stack()) {
2634 // cpu register - stack
2635 if (is_reference_type(opr1->type())) {
2636 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2637 } else {
2638 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2639 }
2640 } else if (opr2->is_constant()) {
2641 // cpu register - constant
2642 LIR_Const* c = opr2->as_constant_ptr();
2643 if (c->type() == T_INT) {
2644 jint i = c->as_jint();
2645 if (i == 0) {
2646 __ testl(reg1, reg1);
2647 } else {
2648 __ cmpl(reg1, i);
2649 }
2650 } else if (c->type() == T_METADATA) {
2651 // All we need for now is a comparison with null for equality.
2652 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2653 Metadata* m = c->as_metadata();
2654 if (m == nullptr) {
2655 __ testptr(reg1, reg1);
2656 } else {
2657 ShouldNotReachHere();
2658 }
2659 } else if (is_reference_type(c->type())) {
2660 // In 64bit oops are single register
2661 jobject o = c->as_jobject();
2662 if (o == nullptr) {
2663 __ testptr(reg1, reg1);
2664 } else {
2665 __ cmpoop(reg1, o, rscratch1);
2666 }
2667 } else {
2668 fatal("unexpected type: %s", basictype_to_str(c->type()));
2669 }
2670 // cpu register - address
2671 } else if (opr2->is_address()) {
2672 if (op->info() != nullptr) {
2673 add_debug_info_for_null_check_here(op->info());
2674 }
2675 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2676 } else {
2677 ShouldNotReachHere();
2678 }
2679
2680 } else if(opr1->is_double_cpu()) {
2681 Register xlo = opr1->as_register_lo();
2682 Register xhi = opr1->as_register_hi();
2683 if (opr2->is_double_cpu()) {
2684 #ifdef _LP64
2685 __ cmpptr(xlo, opr2->as_register_lo());
2686 #else
2687 // cpu register - cpu register
2688 Register ylo = opr2->as_register_lo();
2689 Register yhi = opr2->as_register_hi();
2690 __ subl(xlo, ylo);
2691 __ sbbl(xhi, yhi);
2692 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2693 __ orl(xhi, xlo);
2694 }
2695 #endif // _LP64
2696 } else if (opr2->is_constant()) {
2697 // cpu register - constant 0
2698 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2699 #ifdef _LP64
2700 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2701 #else
2702 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2703 __ orl(xhi, xlo);
2704 #endif // _LP64
2705 } else {
2706 ShouldNotReachHere();
2707 }
2708
2709 } else if (opr1->is_single_xmm()) {
2710 XMMRegister reg1 = opr1->as_xmm_float_reg();
2711 if (opr2->is_single_xmm()) {
2712 // xmm register - xmm register
2713 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2714 } else if (opr2->is_stack()) {
2715 // xmm register - stack
2716 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2717 } else if (opr2->is_constant()) {
2718 // xmm register - constant
2719 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2720 } else if (opr2->is_address()) {
2721 // xmm register - address
2722 if (op->info() != nullptr) {
2723 add_debug_info_for_null_check_here(op->info());
2724 }
2725 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2726 } else {
2727 ShouldNotReachHere();
2728 }
2729
2730 } else if (opr1->is_double_xmm()) {
2731 XMMRegister reg1 = opr1->as_xmm_double_reg();
2732 if (opr2->is_double_xmm()) {
2733 // xmm register - xmm register
2734 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2735 } else if (opr2->is_stack()) {
2736 // xmm register - stack
2737 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2738 } else if (opr2->is_constant()) {
2739 // xmm register - constant
2740 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2741 } else if (opr2->is_address()) {
2742 // xmm register - address
2743 if (op->info() != nullptr) {
2744 add_debug_info_for_null_check_here(op->info());
2745 }
2746 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2747 } else {
2748 ShouldNotReachHere();
2749 }
2750
2751 #ifndef _LP64
2752 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2753 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2754 assert(opr2->is_fpu_register(), "both must be registers");
2755 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2756 #endif // LP64
2757
2758 } else if (opr1->is_address() && opr2->is_constant()) {
2759 LIR_Const* c = opr2->as_constant_ptr();
2760 #ifdef _LP64
2761 if (is_reference_type(c->type())) {
2762 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2763 __ movoop(rscratch1, c->as_jobject());
2764 }
2765 #endif // LP64
2766 if (op->info() != nullptr) {
2767 add_debug_info_for_null_check_here(op->info());
2768 }
2769 // special case: address - constant
2770 LIR_Address* addr = opr1->as_address_ptr();
2771 if (c->type() == T_INT) {
2772 __ cmpl(as_Address(addr), c->as_jint());
2773 } else if (is_reference_type(c->type())) {
2774 #ifdef _LP64
2775 // %%% Make this explode if addr isn't reachable until we figure out a
2776 // better strategy by giving noreg as the temp for as_Address
2777 __ cmpoop(rscratch1, as_Address(addr, noreg));
2778 #else
2779 __ cmpoop(as_Address(addr), c->as_jobject());
2780 #endif // _LP64
2781 } else {
2782 ShouldNotReachHere();
2783 }
2784
2785 } else {
2786 ShouldNotReachHere();
2787 }
2788 }
2789
2790 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2791 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2792 if (left->is_single_xmm()) {
2793 assert(right->is_single_xmm(), "must match");
2794 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2795 } else if (left->is_double_xmm()) {
2796 assert(right->is_double_xmm(), "must match");
2797 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2798
2799 } else {
2800 #ifdef _LP64
2801 ShouldNotReachHere();
2802 #else
2803 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2804 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2805
2806 assert(left->fpu() == 0, "left must be on TOS");
2807 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2808 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2809 #endif // LP64
2810 }
2811 } else {
2812 assert(code == lir_cmp_l2i, "check");
2813 #ifdef _LP64
2814 Label done;
2815 Register dest = dst->as_register();
2816 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2817 __ movl(dest, -1);
2818 __ jccb(Assembler::less, done);
2819 __ setb(Assembler::notZero, dest);
2820 __ movzbl(dest, dest);
2821 __ bind(done);
2822 #else
2823 __ lcmp2int(left->as_register_hi(),
2824 left->as_register_lo(),
2825 right->as_register_hi(),
2826 right->as_register_lo());
2827 move_regs(left->as_register_hi(), dst->as_register());
2828 #endif // _LP64
2829 }
2830 }
2831
2832
2833 void LIR_Assembler::align_call(LIR_Code code) {
2834 // make sure that the displacement word of the call ends up word aligned
2835 int offset = __ offset();
2836 switch (code) {
2837 case lir_static_call:
2838 case lir_optvirtual_call:
2839 case lir_dynamic_call:
2840 offset += NativeCall::displacement_offset;
2841 break;
2842 case lir_icvirtual_call:
2843 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size_rex;
2844 break;
2845 default: ShouldNotReachHere();
2846 }
2847 __ align(BytesPerWord, offset);
2848 }
2849
2850
2851 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2852 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2853 "must be aligned");
2854 __ call(AddressLiteral(op->addr(), rtype));
2855 add_call_info(code_offset(), op->info());
2856 __ post_call_nop();
2857 }
2858
2859
2860 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2861 __ ic_call(op->addr());
2862 add_call_info(code_offset(), op->info());
2863 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2864 "must be aligned");
2865 __ post_call_nop();
2866 }
2867
2868
2869 void LIR_Assembler::emit_static_call_stub() {
2870 address call_pc = __ pc();
2871 address stub = __ start_a_stub(call_stub_size());
2872 if (stub == nullptr) {
2873 bailout("static call stub overflow");
2874 return;
2875 }
2876
2877 int start = __ offset();
2878
2879 // make sure that the displacement word of the call ends up word aligned
2880 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size_rex + NativeCall::displacement_offset);
2881 __ relocate(static_stub_Relocation::spec(call_pc));
2882 __ mov_metadata(rbx, (Metadata*)nullptr);
2883 // must be set to -1 at code generation time
2884 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2885 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2886 __ jump(RuntimeAddress(__ pc()));
2887
2888 assert(__ offset() - start <= call_stub_size(), "stub too big");
2889 __ end_a_stub();
2890 }
2891
2892
2893 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2894 assert(exceptionOop->as_register() == rax, "must match");
2895 assert(exceptionPC->as_register() == rdx, "must match");
2896
2897 // exception object is not added to oop map by LinearScan
2898 // (LinearScan assumes that no oops are in fixed registers)
2899 info->add_register_oop(exceptionOop);
2900 C1StubId unwind_id;
2901
2902 // get current pc information
2903 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2904 int pc_for_athrow_offset = __ offset();
2905 InternalAddress pc_for_athrow(__ pc());
2906 __ lea(exceptionPC->as_register(), pc_for_athrow);
2907 add_call_info(pc_for_athrow_offset, info); // for exception handler
2908
2909 __ verify_not_null_oop(rax);
2910 // search an exception handler (rax: exception oop, rdx: throwing pc)
2911 if (compilation()->has_fpu_code()) {
2912 unwind_id = C1StubId::handle_exception_id;
2913 } else {
2914 unwind_id = C1StubId::handle_exception_nofpu_id;
2915 }
2916 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2917
2918 // enough room for two byte trap
2919 __ nop();
2920 }
2921
2922
2923 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2924 assert(exceptionOop->as_register() == rax, "must match");
2925
2926 __ jmp(_unwind_handler_entry);
2927 }
2928
2929
2930 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2931
2932 // optimized version for linear scan:
2933 // * count must be already in ECX (guaranteed by LinearScan)
2934 // * left and dest must be equal
2935 // * tmp must be unused
2936 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2937 assert(left == dest, "left and dest must be equal");
2938 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2939
2940 if (left->is_single_cpu()) {
2941 Register value = left->as_register();
2942 assert(value != SHIFT_count, "left cannot be ECX");
2943
2944 switch (code) {
2945 case lir_shl: __ shll(value); break;
2946 case lir_shr: __ sarl(value); break;
2947 case lir_ushr: __ shrl(value); break;
2948 default: ShouldNotReachHere();
2949 }
2950 } else if (left->is_double_cpu()) {
2951 Register lo = left->as_register_lo();
2952 Register hi = left->as_register_hi();
2953 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2954 #ifdef _LP64
2955 switch (code) {
2956 case lir_shl: __ shlptr(lo); break;
2957 case lir_shr: __ sarptr(lo); break;
2958 case lir_ushr: __ shrptr(lo); break;
2959 default: ShouldNotReachHere();
2960 }
2961 #else
2962
2963 switch (code) {
2964 case lir_shl: __ lshl(hi, lo); break;
2965 case lir_shr: __ lshr(hi, lo, true); break;
2966 case lir_ushr: __ lshr(hi, lo, false); break;
2967 default: ShouldNotReachHere();
2968 }
2969 #endif // LP64
2970 } else {
2971 ShouldNotReachHere();
2972 }
2973 }
2974
2975
2976 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2977 if (dest->is_single_cpu()) {
2978 // first move left into dest so that left is not destroyed by the shift
2979 Register value = dest->as_register();
2980 count = count & 0x1F; // Java spec
2981
2982 move_regs(left->as_register(), value);
2983 switch (code) {
2984 case lir_shl: __ shll(value, count); break;
2985 case lir_shr: __ sarl(value, count); break;
2986 case lir_ushr: __ shrl(value, count); break;
2987 default: ShouldNotReachHere();
2988 }
2989 } else if (dest->is_double_cpu()) {
2990 #ifndef _LP64
2991 Unimplemented();
2992 #else
2993 // first move left into dest so that left is not destroyed by the shift
2994 Register value = dest->as_register_lo();
2995 count = count & 0x1F; // Java spec
2996
2997 move_regs(left->as_register_lo(), value);
2998 switch (code) {
2999 case lir_shl: __ shlptr(value, count); break;
3000 case lir_shr: __ sarptr(value, count); break;
3001 case lir_ushr: __ shrptr(value, count); break;
3002 default: ShouldNotReachHere();
3003 }
3004 #endif // _LP64
3005 } else {
3006 ShouldNotReachHere();
3007 }
3008 }
3009
3010
3011 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3012 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3013 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3014 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3015 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3016 }
3017
3018
3019 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3020 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3021 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3022 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3023 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3024 }
3025
3026
3027 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3028 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3029 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3030 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3031 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1);
3032 }
3033
3034
3035 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3036 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3037 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3038 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3039 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1);
3040 }
3041
3042
3043 // This code replaces a call to arraycopy; no exception may
3044 // be thrown in this code, they must be thrown in the System.arraycopy
3045 // activation frame; we could save some checks if this would not be the case
3046 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3047 ciArrayKlass* default_type = op->expected_type();
3048 Register src = op->src()->as_register();
3049 Register dst = op->dst()->as_register();
3050 Register src_pos = op->src_pos()->as_register();
3051 Register dst_pos = op->dst_pos()->as_register();
3052 Register length = op->length()->as_register();
3053 Register tmp = op->tmp()->as_register();
3054 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3055 Register tmp2 = UseCompactObjectHeaders ? rscratch2 : noreg;
3056
3057 CodeStub* stub = op->stub();
3058 int flags = op->flags();
3059 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
3060 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
3061
3062 // if we don't know anything, just go through the generic arraycopy
3063 if (default_type == nullptr) {
3064 // save outgoing arguments on stack in case call to System.arraycopy is needed
3065 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3066 // for interpreter calling conventions. Now we have to do it in new style conventions.
3067 // For the moment until C1 gets the new register allocator I just force all the
3068 // args to the right place (except the register args) and then on the back side
3069 // reload the register args properly if we go slow path. Yuck
3070
3071 // These are proper for the calling convention
3072 store_parameter(length, 2);
3073 store_parameter(dst_pos, 1);
3074 store_parameter(dst, 0);
3075
3076 // these are just temporary placements until we need to reload
3077 store_parameter(src_pos, 3);
3078 store_parameter(src, 4);
3079 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3080
3081 address copyfunc_addr = StubRoutines::generic_arraycopy();
3082 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
3083
3084 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3085 #ifdef _LP64
3086 // The arguments are in java calling convention so we can trivially shift them to C
3087 // convention
3088 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3089 __ mov(c_rarg0, j_rarg0);
3090 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3091 __ mov(c_rarg1, j_rarg1);
3092 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3093 __ mov(c_rarg2, j_rarg2);
3094 assert_different_registers(c_rarg3, j_rarg4);
3095 __ mov(c_rarg3, j_rarg3);
3096 #ifdef _WIN64
3097 // Allocate abi space for args but be sure to keep stack aligned
3098 __ subptr(rsp, 6*wordSize);
3099 store_parameter(j_rarg4, 4);
3100 #ifndef PRODUCT
3101 if (PrintC1Statistics) {
3102 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3103 }
3104 #endif
3105 __ call(RuntimeAddress(copyfunc_addr));
3106 __ addptr(rsp, 6*wordSize);
3107 #else
3108 __ mov(c_rarg4, j_rarg4);
3109 #ifndef PRODUCT
3110 if (PrintC1Statistics) {
3111 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3112 }
3113 #endif
3114 __ call(RuntimeAddress(copyfunc_addr));
3115 #endif // _WIN64
3116 #else
3117 __ push(length);
3118 __ push(dst_pos);
3119 __ push(dst);
3120 __ push(src_pos);
3121 __ push(src);
3122
3123 #ifndef PRODUCT
3124 if (PrintC1Statistics) {
3125 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
3126 }
3127 #endif
3128 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3129
3130 #endif // _LP64
3131
3132 __ testl(rax, rax);
3133 __ jcc(Assembler::equal, *stub->continuation());
3134
3135 __ mov(tmp, rax);
3136 __ xorl(tmp, -1);
3137
3138 // Reload values from the stack so they are where the stub
3139 // expects them.
3140 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3141 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3142 __ movptr (length, Address(rsp, 2*BytesPerWord));
3143 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3144 __ movptr (src, Address(rsp, 4*BytesPerWord));
3145
3146 __ subl(length, tmp);
3147 __ addl(src_pos, tmp);
3148 __ addl(dst_pos, tmp);
3149 __ jmp(*stub->entry());
3150
3151 __ bind(*stub->continuation());
3152 return;
3153 }
3154
3155 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3156
3157 int elem_size = type2aelembytes(basic_type);
3158 Address::ScaleFactor scale;
3159
3160 switch (elem_size) {
3161 case 1 :
3162 scale = Address::times_1;
3163 break;
3164 case 2 :
3165 scale = Address::times_2;
3166 break;
3167 case 4 :
3168 scale = Address::times_4;
3169 break;
3170 case 8 :
3171 scale = Address::times_8;
3172 break;
3173 default:
3174 scale = Address::no_scale;
3175 ShouldNotReachHere();
3176 }
3177
3178 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3179 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3180
3181 // length and pos's are all sign extended at this point on 64bit
3182
3183 // test for null
3184 if (flags & LIR_OpArrayCopy::src_null_check) {
3185 __ testptr(src, src);
3186 __ jcc(Assembler::zero, *stub->entry());
3187 }
3188 if (flags & LIR_OpArrayCopy::dst_null_check) {
3189 __ testptr(dst, dst);
3190 __ jcc(Assembler::zero, *stub->entry());
3191 }
3192
3193 // If the compiler was not able to prove that exact type of the source or the destination
3194 // of the arraycopy is an array type, check at runtime if the source or the destination is
3195 // an instance type.
3196 if (flags & LIR_OpArrayCopy::type_check) {
3197 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3198 __ load_klass(tmp, dst, tmp_load_klass);
3199 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3200 __ jcc(Assembler::greaterEqual, *stub->entry());
3201 }
3202
3203 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3204 __ load_klass(tmp, src, tmp_load_klass);
3205 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3206 __ jcc(Assembler::greaterEqual, *stub->entry());
3207 }
3208 }
3209
3210 // check if negative
3211 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3212 __ testl(src_pos, src_pos);
3213 __ jcc(Assembler::less, *stub->entry());
3214 }
3215 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3216 __ testl(dst_pos, dst_pos);
3217 __ jcc(Assembler::less, *stub->entry());
3218 }
3219
3220 if (flags & LIR_OpArrayCopy::src_range_check) {
3221 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3222 __ cmpl(tmp, src_length_addr);
3223 __ jcc(Assembler::above, *stub->entry());
3224 }
3225 if (flags & LIR_OpArrayCopy::dst_range_check) {
3226 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3227 __ cmpl(tmp, dst_length_addr);
3228 __ jcc(Assembler::above, *stub->entry());
3229 }
3230
3231 if (flags & LIR_OpArrayCopy::length_positive_check) {
3232 __ testl(length, length);
3233 __ jcc(Assembler::less, *stub->entry());
3234 }
3235
3236 #ifdef _LP64
3237 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3238 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3239 #endif
3240
3241 if (flags & LIR_OpArrayCopy::type_check) {
3242 // We don't know the array types are compatible
3243 if (basic_type != T_OBJECT) {
3244 // Simple test for basic type arrays
3245 __ cmp_klasses_from_objects(src, dst, tmp, tmp2);
3246 __ jcc(Assembler::notEqual, *stub->entry());
3247 } else {
3248 // For object arrays, if src is a sub class of dst then we can
3249 // safely do the copy.
3250 Label cont, slow;
3251
3252 __ push(src);
3253 __ push(dst);
3254
3255 __ load_klass(src, src, tmp_load_klass);
3256 __ load_klass(dst, dst, tmp_load_klass);
3257
3258 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
3259
3260 __ push(src);
3261 __ push(dst);
3262 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
3263 __ pop(dst);
3264 __ pop(src);
3265
3266 __ testl(src, src);
3267 __ jcc(Assembler::notEqual, cont);
3268
3269 __ bind(slow);
3270 __ pop(dst);
3271 __ pop(src);
3272
3273 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3274 if (copyfunc_addr != nullptr) { // use stub if available
3275 // src is not a sub class of dst so we have to do a
3276 // per-element check.
3277
3278 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3279 if ((flags & mask) != mask) {
3280 // Check that at least both of them object arrays.
3281 assert(flags & mask, "one of the two should be known to be an object array");
3282
3283 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3284 __ load_klass(tmp, src, tmp_load_klass);
3285 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3286 __ load_klass(tmp, dst, tmp_load_klass);
3287 }
3288 int lh_offset = in_bytes(Klass::layout_helper_offset());
3289 Address klass_lh_addr(tmp, lh_offset);
3290 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3291 __ cmpl(klass_lh_addr, objArray_lh);
3292 __ jcc(Assembler::notEqual, *stub->entry());
3293 }
3294
3295 // Spill because stubs can use any register they like and it's
3296 // easier to restore just those that we care about.
3297 store_parameter(dst, 0);
3298 store_parameter(dst_pos, 1);
3299 store_parameter(length, 2);
3300 store_parameter(src_pos, 3);
3301 store_parameter(src, 4);
3302
3303 #ifndef _LP64
3304 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3305 __ movptr(tmp, dst_klass_addr);
3306 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3307 __ push(tmp);
3308 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3309 __ push(tmp);
3310 __ push(length);
3311 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3312 __ push(tmp);
3313 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3314 __ push(tmp);
3315
3316 __ call_VM_leaf(copyfunc_addr, 5);
3317 #else
3318 __ movl2ptr(length, length); //higher 32bits must be null
3319
3320 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3321 assert_different_registers(c_rarg0, dst, dst_pos, length);
3322 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3323 assert_different_registers(c_rarg1, dst, length);
3324
3325 __ mov(c_rarg2, length);
3326 assert_different_registers(c_rarg2, dst);
3327
3328 #ifdef _WIN64
3329 // Allocate abi space for args but be sure to keep stack aligned
3330 __ subptr(rsp, 6*wordSize);
3331 __ load_klass(c_rarg3, dst, tmp_load_klass);
3332 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3333 store_parameter(c_rarg3, 4);
3334 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3335 __ call(RuntimeAddress(copyfunc_addr));
3336 __ addptr(rsp, 6*wordSize);
3337 #else
3338 __ load_klass(c_rarg4, dst, tmp_load_klass);
3339 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3340 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3341 __ call(RuntimeAddress(copyfunc_addr));
3342 #endif
3343
3344 #endif
3345
3346 #ifndef PRODUCT
3347 if (PrintC1Statistics) {
3348 Label failed;
3349 __ testl(rax, rax);
3350 __ jcc(Assembler::notZero, failed);
3351 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1);
3352 __ bind(failed);
3353 }
3354 #endif
3355
3356 __ testl(rax, rax);
3357 __ jcc(Assembler::zero, *stub->continuation());
3358
3359 #ifndef PRODUCT
3360 if (PrintC1Statistics) {
3361 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1);
3362 }
3363 #endif
3364
3365 __ mov(tmp, rax);
3366
3367 __ xorl(tmp, -1);
3368
3369 // Restore previously spilled arguments
3370 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3371 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3372 __ movptr (length, Address(rsp, 2*BytesPerWord));
3373 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3374 __ movptr (src, Address(rsp, 4*BytesPerWord));
3375
3376
3377 __ subl(length, tmp);
3378 __ addl(src_pos, tmp);
3379 __ addl(dst_pos, tmp);
3380 }
3381
3382 __ jmp(*stub->entry());
3383
3384 __ bind(cont);
3385 __ pop(dst);
3386 __ pop(src);
3387 }
3388 }
3389
3390 #ifdef ASSERT
3391 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3392 // Sanity check the known type with the incoming class. For the
3393 // primitive case the types must match exactly with src.klass and
3394 // dst.klass each exactly matching the default type. For the
3395 // object array case, if no type check is needed then either the
3396 // dst type is exactly the expected type and the src type is a
3397 // subtype which we can't check or src is the same array as dst
3398 // but not necessarily exactly of type default_type.
3399 Label known_ok, halt;
3400 __ mov_metadata(tmp, default_type->constant_encoding());
3401 #ifdef _LP64
3402 if (UseCompressedClassPointers) {
3403 __ encode_klass_not_null(tmp, rscratch1);
3404 }
3405 #endif
3406
3407 if (basic_type != T_OBJECT) {
3408 __ cmp_klass(tmp, dst, tmp2);
3409 __ jcc(Assembler::notEqual, halt);
3410 __ cmp_klass(tmp, src, tmp2);
3411 __ jcc(Assembler::equal, known_ok);
3412 } else {
3413 __ cmp_klass(tmp, dst, tmp2);
3414 __ jcc(Assembler::equal, known_ok);
3415 __ cmpptr(src, dst);
3416 __ jcc(Assembler::equal, known_ok);
3417 }
3418 __ bind(halt);
3419 __ stop("incorrect type information in arraycopy");
3420 __ bind(known_ok);
3421 }
3422 #endif
3423
3424 #ifndef PRODUCT
3425 if (PrintC1Statistics) {
3426 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1);
3427 }
3428 #endif
3429
3430 #ifdef _LP64
3431 assert_different_registers(c_rarg0, dst, dst_pos, length);
3432 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3433 assert_different_registers(c_rarg1, length);
3434 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3435 __ mov(c_rarg2, length);
3436
3437 #else
3438 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3439 store_parameter(tmp, 0);
3440 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3441 store_parameter(tmp, 1);
3442 store_parameter(length, 2);
3443 #endif // _LP64
3444
3445 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3446 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3447 const char *name;
3448 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3449 __ call_VM_leaf(entry, 0);
3450
3451 if (stub != nullptr) {
3452 __ bind(*stub->continuation());
3453 }
3454 }
3455
3456 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3457 assert(op->crc()->is_single_cpu(), "crc must be register");
3458 assert(op->val()->is_single_cpu(), "byte value must be register");
3459 assert(op->result_opr()->is_single_cpu(), "result must be register");
3460 Register crc = op->crc()->as_register();
3461 Register val = op->val()->as_register();
3462 Register res = op->result_opr()->as_register();
3463
3464 assert_different_registers(val, crc, res);
3465
3466 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3467 __ notl(crc); // ~crc
3468 __ update_byte_crc32(crc, val, res);
3469 __ notl(crc); // ~crc
3470 __ mov(res, crc);
3471 }
3472
3473 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3474 Register obj = op->obj_opr()->as_register(); // may not be an oop
3475 Register hdr = op->hdr_opr()->as_register();
3476 Register lock = op->lock_opr()->as_register();
3477 if (LockingMode == LM_MONITOR) {
3478 if (op->info() != nullptr) {
3479 add_debug_info_for_null_check_here(op->info());
3480 __ null_check(obj);
3481 }
3482 __ jmp(*op->stub()->entry());
3483 } else if (op->code() == lir_lock) {
3484 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3485 Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg;
3486 // add debug info for NullPointerException only if one is possible
3487 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
3488 if (op->info() != nullptr) {
3489 add_debug_info_for_null_check(null_check_offset, op->info());
3490 }
3491 // done
3492 } else if (op->code() == lir_unlock) {
3493 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3494 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3495 } else {
3496 Unimplemented();
3497 }
3498 __ bind(*op->stub()->continuation());
3499 }
3500
3501 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
3502 Register obj = op->obj()->as_pointer_register();
3503 Register result = op->result_opr()->as_pointer_register();
3504
3505 CodeEmitInfo* info = op->info();
3506 if (info != nullptr) {
3507 add_debug_info_for_null_check_here(info);
3508 }
3509
3510 __ load_klass(result, obj, rscratch1);
3511 }
3512
3513 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3514 ciMethod* method = op->profiled_method();
3515 int bci = op->profiled_bci();
3516 ciMethod* callee = op->profiled_callee();
3517 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3518
3519 // Update counter for all call types
3520 ciMethodData* md = method->method_data_or_null();
3521 assert(md != nullptr, "Sanity");
3522 ciProfileData* data = md->bci_to_data(bci);
3523 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
3524 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3525 Register mdo = op->mdo()->as_register();
3526 __ mov_metadata(mdo, md->constant_encoding());
3527 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3528 // Perform additional virtual call profiling for invokevirtual and
3529 // invokeinterface bytecodes
3530 if (op->should_profile_receiver_type()) {
3531 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3532 Register recv = op->recv()->as_register();
3533 assert_different_registers(mdo, recv);
3534 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3535 ciKlass* known_klass = op->known_holder();
3536 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
3537 // We know the type that will be seen at this call site; we can
3538 // statically update the MethodData* rather than needing to do
3539 // dynamic tests on the receiver type
3540
3541 // NOTE: we should probably put a lock around this search to
3542 // avoid collisions by concurrent compilations
3543 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3544 uint i;
3545 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3546 ciKlass* receiver = vc_data->receiver(i);
3547 if (known_klass->equals(receiver)) {
3548 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3549 __ addptr(data_addr, DataLayout::counter_increment);
3550 return;
3551 }
3552 }
3553
3554 // Receiver type not found in profile data; select an empty slot
3555
3556 // Note that this is less efficient than it should be because it
3557 // always does a write to the receiver part of the
3558 // VirtualCallData rather than just the first time
3559 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3560 ciKlass* receiver = vc_data->receiver(i);
3561 if (receiver == nullptr) {
3562 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3563 __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1);
3564 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3565 __ addptr(data_addr, DataLayout::counter_increment);
3566 return;
3567 }
3568 }
3569 } else {
3570 __ load_klass(recv, recv, tmp_load_klass);
3571 Label update_done;
3572 type_profile_helper(mdo, md, data, recv, &update_done);
3573 // Receiver did not match any saved receiver and there is no empty row for it.
3574 // Increment total counter to indicate polymorphic case.
3575 __ addptr(counter_addr, DataLayout::counter_increment);
3576
3577 __ bind(update_done);
3578 }
3579 } else {
3580 // Static call
3581 __ addptr(counter_addr, DataLayout::counter_increment);
3582 }
3583 }
3584
3585 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3586 Register obj = op->obj()->as_register();
3587 Register tmp = op->tmp()->as_pointer_register();
3588 Register tmp_load_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3589 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3590 ciKlass* exact_klass = op->exact_klass();
3591 intptr_t current_klass = op->current_klass();
3592 bool not_null = op->not_null();
3593 bool no_conflict = op->no_conflict();
3594
3595 Label update, next, none;
3596
3597 bool do_null = !not_null;
3598 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3599 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3600
3601 assert(do_null || do_update, "why are we here?");
3602 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3603
3604 __ verify_oop(obj);
3605
3606 #ifdef ASSERT
3607 if (obj == tmp) {
3608 #ifdef _LP64
3609 assert_different_registers(obj, rscratch1, mdo_addr.base(), mdo_addr.index());
3610 #else
3611 assert_different_registers(obj, mdo_addr.base(), mdo_addr.index());
3612 #endif
3613 } else {
3614 #ifdef _LP64
3615 assert_different_registers(obj, tmp, rscratch1, mdo_addr.base(), mdo_addr.index());
3616 #else
3617 assert_different_registers(obj, tmp, mdo_addr.base(), mdo_addr.index());
3618 #endif
3619 }
3620 #endif
3621 if (do_null) {
3622 __ testptr(obj, obj);
3623 __ jccb(Assembler::notZero, update);
3624 if (!TypeEntries::was_null_seen(current_klass)) {
3625 __ testptr(mdo_addr, TypeEntries::null_seen);
3626 #ifndef ASSERT
3627 __ jccb(Assembler::notZero, next); // already set
3628 #else
3629 __ jcc(Assembler::notZero, next); // already set
3630 #endif
3631 // atomic update to prevent overwriting Klass* with 0
3632 __ lock();
3633 __ orptr(mdo_addr, TypeEntries::null_seen);
3634 }
3635 if (do_update) {
3636 #ifndef ASSERT
3637 __ jmpb(next);
3638 }
3639 #else
3640 __ jmp(next);
3641 }
3642 } else {
3643 __ testptr(obj, obj);
3644 __ jcc(Assembler::notZero, update);
3645 __ stop("unexpected null obj");
3646 #endif
3647 }
3648
3649 __ bind(update);
3650
3651 if (do_update) {
3652 #ifdef ASSERT
3653 if (exact_klass != nullptr) {
3654 Label ok;
3655 __ load_klass(tmp, obj, tmp_load_klass);
3656 __ push(tmp);
3657 __ mov_metadata(tmp, exact_klass->constant_encoding());
3658 __ cmpptr(tmp, Address(rsp, 0));
3659 __ jcc(Assembler::equal, ok);
3660 __ stop("exact klass and actual klass differ");
3661 __ bind(ok);
3662 __ pop(tmp);
3663 }
3664 #endif
3665 if (!no_conflict) {
3666 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
3667 if (exact_klass != nullptr) {
3668 __ mov_metadata(tmp, exact_klass->constant_encoding());
3669 } else {
3670 __ load_klass(tmp, obj, tmp_load_klass);
3671 }
3672 #ifdef _LP64
3673 __ mov(rscratch1, tmp); // save original value before XOR
3674 #endif
3675 __ xorptr(tmp, mdo_addr);
3676 __ testptr(tmp, TypeEntries::type_klass_mask);
3677 // klass seen before, nothing to do. The unknown bit may have been
3678 // set already but no need to check.
3679 __ jccb(Assembler::zero, next);
3680
3681 __ testptr(tmp, TypeEntries::type_unknown);
3682 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3683
3684 if (TypeEntries::is_type_none(current_klass)) {
3685 __ testptr(mdo_addr, TypeEntries::type_mask);
3686 __ jccb(Assembler::zero, none);
3687 #ifdef _LP64
3688 // There is a chance that the checks above (re-reading profiling
3689 // data from memory) fail if another thread has just set the
3690 // profiling to this obj's klass
3691 __ mov(tmp, rscratch1); // get back original value before XOR
3692 __ xorptr(tmp, mdo_addr);
3693 __ testptr(tmp, TypeEntries::type_klass_mask);
3694 __ jccb(Assembler::zero, next);
3695 #endif
3696 }
3697 } else {
3698 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3699 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3700
3701 __ testptr(mdo_addr, TypeEntries::type_unknown);
3702 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3703 }
3704
3705 // different than before. Cannot keep accurate profile.
3706 __ orptr(mdo_addr, TypeEntries::type_unknown);
3707
3708 if (TypeEntries::is_type_none(current_klass)) {
3709 __ jmpb(next);
3710
3711 __ bind(none);
3712 // first time here. Set profile type.
3713 __ movptr(mdo_addr, tmp);
3714 #ifdef ASSERT
3715 __ andptr(tmp, TypeEntries::type_klass_mask);
3716 __ verify_klass_ptr(tmp);
3717 #endif
3718 }
3719 } else {
3720 // There's a single possible klass at this profile point
3721 assert(exact_klass != nullptr, "should be");
3722 if (TypeEntries::is_type_none(current_klass)) {
3723 __ mov_metadata(tmp, exact_klass->constant_encoding());
3724 __ xorptr(tmp, mdo_addr);
3725 __ testptr(tmp, TypeEntries::type_klass_mask);
3726 #ifdef ASSERT
3727 __ jcc(Assembler::zero, next);
3728
3729 {
3730 Label ok;
3731 __ push(tmp);
3732 __ testptr(mdo_addr, TypeEntries::type_mask);
3733 __ jcc(Assembler::zero, ok);
3734 // may have been set by another thread
3735 __ mov_metadata(tmp, exact_klass->constant_encoding());
3736 __ xorptr(tmp, mdo_addr);
3737 __ testptr(tmp, TypeEntries::type_mask);
3738 __ jcc(Assembler::zero, ok);
3739
3740 __ stop("unexpected profiling mismatch");
3741 __ bind(ok);
3742 __ pop(tmp);
3743 }
3744 #else
3745 __ jccb(Assembler::zero, next);
3746 #endif
3747 // first time here. Set profile type.
3748 __ movptr(mdo_addr, tmp);
3749 #ifdef ASSERT
3750 __ andptr(tmp, TypeEntries::type_klass_mask);
3751 __ verify_klass_ptr(tmp);
3752 #endif
3753 } else {
3754 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3755 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3756
3757 __ testptr(mdo_addr, TypeEntries::type_unknown);
3758 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3759
3760 __ orptr(mdo_addr, TypeEntries::type_unknown);
3761 }
3762 }
3763 }
3764 __ bind(next);
3765 }
3766
3767 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3768 Unimplemented();
3769 }
3770
3771
3772 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3773 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3774 }
3775
3776
3777 void LIR_Assembler::align_backward_branch_target() {
3778 __ align(BytesPerWord);
3779 }
3780
3781
3782 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3783 if (left->is_single_cpu()) {
3784 __ negl(left->as_register());
3785 move_regs(left->as_register(), dest->as_register());
3786
3787 } else if (left->is_double_cpu()) {
3788 Register lo = left->as_register_lo();
3789 #ifdef _LP64
3790 Register dst = dest->as_register_lo();
3791 __ movptr(dst, lo);
3792 __ negptr(dst);
3793 #else
3794 Register hi = left->as_register_hi();
3795 __ lneg(hi, lo);
3796 if (dest->as_register_lo() == hi) {
3797 assert(dest->as_register_hi() != lo, "destroying register");
3798 move_regs(hi, dest->as_register_hi());
3799 move_regs(lo, dest->as_register_lo());
3800 } else {
3801 move_regs(lo, dest->as_register_lo());
3802 move_regs(hi, dest->as_register_hi());
3803 }
3804 #endif // _LP64
3805
3806 } else if (dest->is_single_xmm()) {
3807 assert(!tmp->is_valid(), "do not need temporary");
3808 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3809 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3810 }
3811 __ xorps(dest->as_xmm_float_reg(),
3812 ExternalAddress((address)float_signflip_pool),
3813 rscratch1);
3814 } else if (dest->is_double_xmm()) {
3815 assert(!tmp->is_valid(), "do not need temporary");
3816 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3817 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3818 }
3819 __ xorpd(dest->as_xmm_double_reg(),
3820 ExternalAddress((address)double_signflip_pool),
3821 rscratch1);
3822 #ifndef _LP64
3823 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3824 assert(left->fpu() == 0, "arg must be on TOS");
3825 assert(dest->fpu() == 0, "dest must be TOS");
3826 __ fchs();
3827 #endif // !_LP64
3828
3829 } else {
3830 ShouldNotReachHere();
3831 }
3832 }
3833
3834
3835 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3836 assert(src->is_address(), "must be an address");
3837 assert(dest->is_register(), "must be a register");
3838
3839 PatchingStub* patch = nullptr;
3840 if (patch_code != lir_patch_none) {
3841 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3842 }
3843
3844 Register reg = dest->as_pointer_register();
3845 LIR_Address* addr = src->as_address_ptr();
3846 __ lea(reg, as_Address(addr));
3847
3848 if (patch != nullptr) {
3849 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3850 }
3851 }
3852
3853
3854
3855 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3856 assert(!tmp->is_valid(), "don't need temporary");
3857 __ call(RuntimeAddress(dest));
3858 if (info != nullptr) {
3859 add_call_info_here(info);
3860 }
3861 __ post_call_nop();
3862 }
3863
3864
3865 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3866 assert(type == T_LONG, "only for volatile long fields");
3867
3868 if (info != nullptr) {
3869 add_debug_info_for_null_check_here(info);
3870 }
3871
3872 if (src->is_double_xmm()) {
3873 if (dest->is_double_cpu()) {
3874 #ifdef _LP64
3875 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3876 #else
3877 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3878 __ psrlq(src->as_xmm_double_reg(), 32);
3879 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3880 #endif // _LP64
3881 } else if (dest->is_double_stack()) {
3882 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3883 } else if (dest->is_address()) {
3884 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3885 } else {
3886 ShouldNotReachHere();
3887 }
3888
3889 } else if (dest->is_double_xmm()) {
3890 if (src->is_double_stack()) {
3891 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3892 } else if (src->is_address()) {
3893 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3894 } else {
3895 ShouldNotReachHere();
3896 }
3897
3898 #ifndef _LP64
3899 } else if (src->is_double_fpu()) {
3900 assert(src->fpu_regnrLo() == 0, "must be TOS");
3901 if (dest->is_double_stack()) {
3902 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3903 } else if (dest->is_address()) {
3904 __ fistp_d(as_Address(dest->as_address_ptr()));
3905 } else {
3906 ShouldNotReachHere();
3907 }
3908
3909 } else if (dest->is_double_fpu()) {
3910 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3911 if (src->is_double_stack()) {
3912 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3913 } else if (src->is_address()) {
3914 __ fild_d(as_Address(src->as_address_ptr()));
3915 } else {
3916 ShouldNotReachHere();
3917 }
3918 #endif // !_LP64
3919
3920 } else {
3921 ShouldNotReachHere();
3922 }
3923 }
3924
3925 #ifdef ASSERT
3926 // emit run-time assertion
3927 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3928 assert(op->code() == lir_assert, "must be");
3929
3930 if (op->in_opr1()->is_valid()) {
3931 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3932 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3933 } else {
3934 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3935 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3936 }
3937
3938 Label ok;
3939 if (op->condition() != lir_cond_always) {
3940 Assembler::Condition acond = Assembler::zero;
3941 switch (op->condition()) {
3942 case lir_cond_equal: acond = Assembler::equal; break;
3943 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3944 case lir_cond_less: acond = Assembler::less; break;
3945 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3946 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3947 case lir_cond_greater: acond = Assembler::greater; break;
3948 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3949 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3950 default: ShouldNotReachHere();
3951 }
3952 __ jcc(acond, ok);
3953 }
3954 if (op->halt()) {
3955 const char* str = __ code_string(op->msg());
3956 __ stop(str);
3957 } else {
3958 breakpoint();
3959 }
3960 __ bind(ok);
3961 }
3962 #endif
3963
3964 void LIR_Assembler::membar() {
3965 // QQQ sparc TSO uses this,
3966 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3967 }
3968
3969 void LIR_Assembler::membar_acquire() {
3970 // No x86 machines currently require load fences
3971 }
3972
3973 void LIR_Assembler::membar_release() {
3974 // No x86 machines currently require store fences
3975 }
3976
3977 void LIR_Assembler::membar_loadload() {
3978 // no-op
3979 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3980 }
3981
3982 void LIR_Assembler::membar_storestore() {
3983 // no-op
3984 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3985 }
3986
3987 void LIR_Assembler::membar_loadstore() {
3988 // no-op
3989 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3990 }
3991
3992 void LIR_Assembler::membar_storeload() {
3993 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3994 }
3995
3996 void LIR_Assembler::on_spin_wait() {
3997 __ pause ();
3998 }
3999
4000 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4001 assert(result_reg->is_register(), "check");
4002 #ifdef _LP64
4003 // __ get_thread(result_reg->as_register_lo());
4004 __ mov(result_reg->as_register(), r15_thread);
4005 #else
4006 __ get_thread(result_reg->as_register());
4007 #endif // _LP64
4008 }
4009
4010
4011 void LIR_Assembler::peephole(LIR_List*) {
4012 // do nothing for now
4013 }
4014
4015 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4016 assert(data == dest, "xchg/xadd uses only 2 operands");
4017
4018 if (data->type() == T_INT) {
4019 if (code == lir_xadd) {
4020 __ lock();
4021 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4022 } else {
4023 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4024 }
4025 } else if (data->is_oop()) {
4026 assert (code == lir_xchg, "xadd for oops");
4027 Register obj = data->as_register();
4028 #ifdef _LP64
4029 if (UseCompressedOops) {
4030 __ encode_heap_oop(obj);
4031 __ xchgl(obj, as_Address(src->as_address_ptr()));
4032 __ decode_heap_oop(obj);
4033 } else {
4034 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4035 }
4036 #else
4037 __ xchgl(obj, as_Address(src->as_address_ptr()));
4038 #endif
4039 } else if (data->type() == T_LONG) {
4040 #ifdef _LP64
4041 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4042 if (code == lir_xadd) {
4043 __ lock();
4044 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4045 } else {
4046 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4047 }
4048 #else
4049 ShouldNotReachHere();
4050 #endif
4051 } else {
4052 ShouldNotReachHere();
4053 }
4054 }
4055
4056 #undef __