1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.hpp"
26 #include "asm/assembler.inline.hpp"
27 #include "code/compiledIC.hpp"
28 #include "compiler/compiler_globals.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "crc32c.h"
31 #include "gc/shared/barrierSet.hpp"
32 #include "gc/shared/barrierSetAssembler.hpp"
33 #include "gc/shared/collectedHeap.inline.hpp"
34 #include "gc/shared/tlab_globals.hpp"
35 #include "interpreter/bytecodeHistogram.hpp"
36 #include "interpreter/interpreter.hpp"
37 #include "interpreter/interpreterRuntime.hpp"
38 #include "jvm.h"
39 #include "memory/resourceArea.hpp"
40 #include "memory/universe.hpp"
41 #include "oops/accessDecorators.hpp"
42 #include "oops/compressedKlass.inline.hpp"
43 #include "oops/compressedOops.inline.hpp"
44 #include "oops/klass.inline.hpp"
45 #include "prims/methodHandles.hpp"
46 #include "runtime/continuation.hpp"
47 #include "runtime/interfaceSupport.inline.hpp"
48 #include "runtime/javaThread.hpp"
49 #include "runtime/jniHandles.hpp"
50 #include "runtime/objectMonitor.hpp"
51 #include "runtime/os.hpp"
52 #include "runtime/safepoint.hpp"
53 #include "runtime/safepointMechanism.hpp"
54 #include "runtime/sharedRuntime.hpp"
55 #include "runtime/stubRoutines.hpp"
56 #include "utilities/checkedCast.hpp"
57 #include "utilities/macros.hpp"
58
59 #ifdef PRODUCT
60 #define BLOCK_COMMENT(str) /* nothing */
61 #define STOP(error) stop(error)
62 #else
63 #define BLOCK_COMMENT(str) block_comment(str)
64 #define STOP(error) block_comment(error); stop(error)
65 #endif
66
67 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
68
69 #ifdef ASSERT
70 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
71 #endif
72
73 static const Assembler::Condition reverse[] = {
74 Assembler::noOverflow /* overflow = 0x0 */ ,
75 Assembler::overflow /* noOverflow = 0x1 */ ,
76 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
77 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
78 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
79 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
80 Assembler::above /* belowEqual = 0x6 */ ,
81 Assembler::belowEqual /* above = 0x7 */ ,
82 Assembler::positive /* negative = 0x8 */ ,
83 Assembler::negative /* positive = 0x9 */ ,
84 Assembler::noParity /* parity = 0xa */ ,
85 Assembler::parity /* noParity = 0xb */ ,
86 Assembler::greaterEqual /* less = 0xc */ ,
87 Assembler::less /* greaterEqual = 0xd */ ,
88 Assembler::greater /* lessEqual = 0xe */ ,
89 Assembler::lessEqual /* greater = 0xf, */
90
91 };
92
93
94 // Implementation of MacroAssembler
95
96 // First all the versions that have distinct versions depending on 32/64 bit
97 // Unless the difference is trivial (1 line or so).
98
99 #ifndef _LP64
100
101 // 32bit versions
102
103 Address MacroAssembler::as_Address(AddressLiteral adr) {
104 return Address(adr.target(), adr.rspec());
105 }
106
107 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
108 assert(rscratch == noreg, "");
109 return Address::make_array(adr);
110 }
111
112 void MacroAssembler::call_VM_leaf_base(address entry_point,
113 int number_of_arguments) {
114 call(RuntimeAddress(entry_point));
115 increment(rsp, number_of_arguments * wordSize);
116 }
117
118 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
119 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
120 }
121
122
123 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
124 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
125 }
126
127 void MacroAssembler::cmpoop(Address src1, jobject obj) {
128 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
129 }
130
131 void MacroAssembler::cmpoop(Register src1, jobject obj, Register rscratch) {
132 assert(rscratch == noreg, "redundant");
133 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
134 }
135
136 void MacroAssembler::extend_sign(Register hi, Register lo) {
137 // According to Intel Doc. AP-526, "Integer Divide", p.18.
138 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
139 cdql();
140 } else {
141 movl(hi, lo);
142 sarl(hi, 31);
143 }
144 }
145
146 void MacroAssembler::jC2(Register tmp, Label& L) {
147 // set parity bit if FPU flag C2 is set (via rax)
148 save_rax(tmp);
149 fwait(); fnstsw_ax();
150 sahf();
151 restore_rax(tmp);
152 // branch
153 jcc(Assembler::parity, L);
154 }
155
156 void MacroAssembler::jnC2(Register tmp, Label& L) {
157 // set parity bit if FPU flag C2 is set (via rax)
158 save_rax(tmp);
159 fwait(); fnstsw_ax();
160 sahf();
161 restore_rax(tmp);
162 // branch
163 jcc(Assembler::noParity, L);
164 }
165
166 // 32bit can do a case table jump in one instruction but we no longer allow the base
167 // to be installed in the Address class
168 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
169 assert(rscratch == noreg, "not needed");
170 jmp(as_Address(entry, noreg));
171 }
172
173 // Note: y_lo will be destroyed
174 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
175 // Long compare for Java (semantics as described in JVM spec.)
176 Label high, low, done;
177
178 cmpl(x_hi, y_hi);
179 jcc(Assembler::less, low);
180 jcc(Assembler::greater, high);
181 // x_hi is the return register
182 xorl(x_hi, x_hi);
183 cmpl(x_lo, y_lo);
184 jcc(Assembler::below, low);
185 jcc(Assembler::equal, done);
186
187 bind(high);
188 xorl(x_hi, x_hi);
189 increment(x_hi);
190 jmp(done);
191
192 bind(low);
193 xorl(x_hi, x_hi);
194 decrementl(x_hi);
195
196 bind(done);
197 }
198
199 void MacroAssembler::lea(Register dst, AddressLiteral src) {
200 mov_literal32(dst, (int32_t)src.target(), src.rspec());
201 }
202
203 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
204 assert(rscratch == noreg, "not needed");
205
206 // leal(dst, as_Address(adr));
207 // see note in movl as to why we must use a move
208 mov_literal32(dst, (int32_t)adr.target(), adr.rspec());
209 }
210
211 void MacroAssembler::leave() {
212 mov(rsp, rbp);
213 pop(rbp);
214 }
215
216 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
217 // Multiplication of two Java long values stored on the stack
218 // as illustrated below. Result is in rdx:rax.
219 //
220 // rsp ---> [ ?? ] \ \
221 // .... | y_rsp_offset |
222 // [ y_lo ] / (in bytes) | x_rsp_offset
223 // [ y_hi ] | (in bytes)
224 // .... |
225 // [ x_lo ] /
226 // [ x_hi ]
227 // ....
228 //
229 // Basic idea: lo(result) = lo(x_lo * y_lo)
230 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
231 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
232 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
233 Label quick;
234 // load x_hi, y_hi and check if quick
235 // multiplication is possible
236 movl(rbx, x_hi);
237 movl(rcx, y_hi);
238 movl(rax, rbx);
239 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
240 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
241 // do full multiplication
242 // 1st step
243 mull(y_lo); // x_hi * y_lo
244 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
245 // 2nd step
246 movl(rax, x_lo);
247 mull(rcx); // x_lo * y_hi
248 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
249 // 3rd step
250 bind(quick); // note: rbx, = 0 if quick multiply!
251 movl(rax, x_lo);
252 mull(y_lo); // x_lo * y_lo
253 addl(rdx, rbx); // correct hi(x_lo * y_lo)
254 }
255
256 void MacroAssembler::lneg(Register hi, Register lo) {
257 negl(lo);
258 adcl(hi, 0);
259 negl(hi);
260 }
261
262 void MacroAssembler::lshl(Register hi, Register lo) {
263 // Java shift left long support (semantics as described in JVM spec., p.305)
264 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
265 // shift value is in rcx !
266 assert(hi != rcx, "must not use rcx");
267 assert(lo != rcx, "must not use rcx");
268 const Register s = rcx; // shift count
269 const int n = BitsPerWord;
270 Label L;
271 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
272 cmpl(s, n); // if (s < n)
273 jcc(Assembler::less, L); // else (s >= n)
274 movl(hi, lo); // x := x << n
275 xorl(lo, lo);
276 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
277 bind(L); // s (mod n) < n
278 shldl(hi, lo); // x := x << s
279 shll(lo);
280 }
281
282
283 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
284 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
285 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
286 assert(hi != rcx, "must not use rcx");
287 assert(lo != rcx, "must not use rcx");
288 const Register s = rcx; // shift count
289 const int n = BitsPerWord;
290 Label L;
291 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
292 cmpl(s, n); // if (s < n)
293 jcc(Assembler::less, L); // else (s >= n)
294 movl(lo, hi); // x := x >> n
295 if (sign_extension) sarl(hi, 31);
296 else xorl(hi, hi);
297 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
298 bind(L); // s (mod n) < n
299 shrdl(lo, hi); // x := x >> s
300 if (sign_extension) sarl(hi);
301 else shrl(hi);
302 }
303
304 void MacroAssembler::movoop(Register dst, jobject obj) {
305 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
306 }
307
308 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
309 assert(rscratch == noreg, "redundant");
310 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
311 }
312
313 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
314 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
315 }
316
317 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
318 assert(rscratch == noreg, "redundant");
319 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
320 }
321
322 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
323 if (src.is_lval()) {
324 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
325 } else {
326 movl(dst, as_Address(src));
327 }
328 }
329
330 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
331 assert(rscratch == noreg, "redundant");
332 movl(as_Address(dst, noreg), src);
333 }
334
335 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
336 movl(dst, as_Address(src, noreg));
337 }
338
339 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
340 assert(rscratch == noreg, "redundant");
341 movl(dst, src);
342 }
343
344 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
345 assert(rscratch == noreg, "redundant");
346 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
347 }
348
349 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
350 assert(rscratch == noreg, "redundant");
351 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
352 }
353
354 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
355 assert(rscratch == noreg, "redundant");
356 if (src.is_lval()) {
357 push_literal32((int32_t)src.target(), src.rspec());
358 } else {
359 pushl(as_Address(src));
360 }
361 }
362
363 static void pass_arg0(MacroAssembler* masm, Register arg) {
364 masm->push(arg);
365 }
366
367 static void pass_arg1(MacroAssembler* masm, Register arg) {
368 masm->push(arg);
369 }
370
371 static void pass_arg2(MacroAssembler* masm, Register arg) {
372 masm->push(arg);
373 }
374
375 static void pass_arg3(MacroAssembler* masm, Register arg) {
376 masm->push(arg);
377 }
378
379 #ifndef PRODUCT
380 extern "C" void findpc(intptr_t x);
381 #endif
382
383 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
384 // In order to get locks to work, we need to fake a in_VM state
385 JavaThread* thread = JavaThread::current();
386 JavaThreadState saved_state = thread->thread_state();
387 thread->set_thread_state(_thread_in_vm);
388 if (ShowMessageBoxOnError) {
389 JavaThread* thread = JavaThread::current();
390 JavaThreadState saved_state = thread->thread_state();
391 thread->set_thread_state(_thread_in_vm);
392 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
393 ttyLocker ttyl;
394 BytecodeCounter::print();
395 }
396 // To see where a verify_oop failed, get $ebx+40/X for this frame.
397 // This is the value of eip which points to where verify_oop will return.
398 if (os::message_box(msg, "Execution stopped, print registers?")) {
399 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
400 BREAKPOINT;
401 }
402 }
403 fatal("DEBUG MESSAGE: %s", msg);
404 }
405
406 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
407 ttyLocker ttyl;
408 DebuggingContext debugging{};
409 tty->print_cr("eip = 0x%08x", eip);
410 #ifndef PRODUCT
411 if ((WizardMode || Verbose) && PrintMiscellaneous) {
412 tty->cr();
413 findpc(eip);
414 tty->cr();
415 }
416 #endif
417 #define PRINT_REG(rax) \
418 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
419 PRINT_REG(rax);
420 PRINT_REG(rbx);
421 PRINT_REG(rcx);
422 PRINT_REG(rdx);
423 PRINT_REG(rdi);
424 PRINT_REG(rsi);
425 PRINT_REG(rbp);
426 PRINT_REG(rsp);
427 #undef PRINT_REG
428 // Print some words near top of staack.
429 int* dump_sp = (int*) rsp;
430 for (int col1 = 0; col1 < 8; col1++) {
431 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
432 os::print_location(tty, *dump_sp++);
433 }
434 for (int row = 0; row < 16; row++) {
435 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
436 for (int col = 0; col < 8; col++) {
437 tty->print(" 0x%08x", *dump_sp++);
438 }
439 tty->cr();
440 }
441 // Print some instructions around pc:
442 Disassembler::decode((address)eip-64, (address)eip);
443 tty->print_cr("--------");
444 Disassembler::decode((address)eip, (address)eip+32);
445 }
446
447 void MacroAssembler::stop(const char* msg) {
448 // push address of message
449 ExternalAddress message((address)msg);
450 pushptr(message.addr(), noreg);
451 { Label L; call(L, relocInfo::none); bind(L); } // push eip
452 pusha(); // push registers
453 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
454 hlt();
455 }
456
457 void MacroAssembler::warn(const char* msg) {
458 push_CPU_state();
459
460 // push address of message
461 ExternalAddress message((address)msg);
462 pushptr(message.addr(), noreg);
463
464 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
465 addl(rsp, wordSize); // discard argument
466 pop_CPU_state();
467 }
468
469 void MacroAssembler::print_state() {
470 { Label L; call(L, relocInfo::none); bind(L); } // push eip
471 pusha(); // push registers
472
473 push_CPU_state();
474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
475 pop_CPU_state();
476
477 popa();
478 addl(rsp, wordSize);
479 }
480
481 #else // _LP64
482
483 // 64 bit versions
484
485 Address MacroAssembler::as_Address(AddressLiteral adr) {
486 // amd64 always does this as a pc-rel
487 // we can be absolute or disp based on the instruction type
488 // jmp/call are displacements others are absolute
489 assert(!adr.is_lval(), "must be rval");
490 assert(reachable(adr), "must be");
491 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
492
493 }
494
495 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
496 AddressLiteral base = adr.base();
497 lea(rscratch, base);
498 Address index = adr.index();
499 assert(index._disp == 0, "must not have disp"); // maybe it can?
500 Address array(rscratch, index._index, index._scale, index._disp);
501 return array;
502 }
503
504 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
505 Label L, E;
506
507 #ifdef _WIN64
508 // Windows always allocates space for it's register args
509 assert(num_args <= 4, "only register arguments supported");
510 subq(rsp, frame::arg_reg_save_area_bytes);
511 #endif
512
513 // Align stack if necessary
514 testl(rsp, 15);
515 jcc(Assembler::zero, L);
516
517 subq(rsp, 8);
518 call(RuntimeAddress(entry_point));
519 addq(rsp, 8);
520 jmp(E);
521
522 bind(L);
523 call(RuntimeAddress(entry_point));
524
525 bind(E);
526
527 #ifdef _WIN64
528 // restore stack pointer
529 addq(rsp, frame::arg_reg_save_area_bytes);
530 #endif
531 }
532
533 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
534 assert(!src2.is_lval(), "should use cmpptr");
535 assert(rscratch != noreg || always_reachable(src2), "missing");
536
537 if (reachable(src2)) {
538 cmpq(src1, as_Address(src2));
539 } else {
540 lea(rscratch, src2);
541 Assembler::cmpq(src1, Address(rscratch, 0));
542 }
543 }
544
545 int MacroAssembler::corrected_idivq(Register reg) {
546 // Full implementation of Java ldiv and lrem; checks for special
547 // case as described in JVM spec., p.243 & p.271. The function
548 // returns the (pc) offset of the idivl instruction - may be needed
549 // for implicit exceptions.
550 //
551 // normal case special case
552 //
553 // input : rax: dividend min_long
554 // reg: divisor (may not be eax/edx) -1
555 //
556 // output: rax: quotient (= rax idiv reg) min_long
557 // rdx: remainder (= rax irem reg) 0
558 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
559 static const int64_t min_long = 0x8000000000000000;
560 Label normal_case, special_case;
561
562 // check for special case
563 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
564 jcc(Assembler::notEqual, normal_case);
565 xorl(rdx, rdx); // prepare rdx for possible special case (where
566 // remainder = 0)
567 cmpq(reg, -1);
568 jcc(Assembler::equal, special_case);
569
570 // handle normal case
571 bind(normal_case);
572 cdqq();
573 int idivq_offset = offset();
574 idivq(reg);
575
576 // normal and special case exit
577 bind(special_case);
578
579 return idivq_offset;
580 }
581
582 void MacroAssembler::decrementq(Register reg, int value) {
583 if (value == min_jint) { subq(reg, value); return; }
584 if (value < 0) { incrementq(reg, -value); return; }
585 if (value == 0) { ; return; }
586 if (value == 1 && UseIncDec) { decq(reg) ; return; }
587 /* else */ { subq(reg, value) ; return; }
588 }
589
590 void MacroAssembler::decrementq(Address dst, int value) {
591 if (value == min_jint) { subq(dst, value); return; }
592 if (value < 0) { incrementq(dst, -value); return; }
593 if (value == 0) { ; return; }
594 if (value == 1 && UseIncDec) { decq(dst) ; return; }
595 /* else */ { subq(dst, value) ; return; }
596 }
597
598 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
599 assert(rscratch != noreg || always_reachable(dst), "missing");
600
601 if (reachable(dst)) {
602 incrementq(as_Address(dst));
603 } else {
604 lea(rscratch, dst);
605 incrementq(Address(rscratch, 0));
606 }
607 }
608
609 void MacroAssembler::incrementq(Register reg, int value) {
610 if (value == min_jint) { addq(reg, value); return; }
611 if (value < 0) { decrementq(reg, -value); return; }
612 if (value == 0) { ; return; }
613 if (value == 1 && UseIncDec) { incq(reg) ; return; }
614 /* else */ { addq(reg, value) ; return; }
615 }
616
617 void MacroAssembler::incrementq(Address dst, int value) {
618 if (value == min_jint) { addq(dst, value); return; }
619 if (value < 0) { decrementq(dst, -value); return; }
620 if (value == 0) { ; return; }
621 if (value == 1 && UseIncDec) { incq(dst) ; return; }
622 /* else */ { addq(dst, value) ; return; }
623 }
624
625 // 32bit can do a case table jump in one instruction but we no longer allow the base
626 // to be installed in the Address class
627 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
628 lea(rscratch, entry.base());
629 Address dispatch = entry.index();
630 assert(dispatch._base == noreg, "must be");
631 dispatch._base = rscratch;
632 jmp(dispatch);
633 }
634
635 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
636 ShouldNotReachHere(); // 64bit doesn't use two regs
637 cmpq(x_lo, y_lo);
638 }
639
640 void MacroAssembler::lea(Register dst, AddressLiteral src) {
641 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
642 }
643
644 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
645 lea(rscratch, adr);
646 movptr(dst, rscratch);
647 }
648
649 void MacroAssembler::leave() {
650 // %%% is this really better? Why not on 32bit too?
651 emit_int8((unsigned char)0xC9); // LEAVE
652 }
653
654 void MacroAssembler::lneg(Register hi, Register lo) {
655 ShouldNotReachHere(); // 64bit doesn't use two regs
656 negq(lo);
657 }
658
659 void MacroAssembler::movoop(Register dst, jobject obj) {
660 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
661 }
662
663 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
664 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
665 movq(dst, rscratch);
666 }
667
668 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
669 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
670 }
671
672 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
673 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
674 movq(dst, rscratch);
675 }
676
677 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
678 if (src.is_lval()) {
679 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
680 } else {
681 if (reachable(src)) {
682 movq(dst, as_Address(src));
683 } else {
684 lea(dst, src);
685 movq(dst, Address(dst, 0));
686 }
687 }
688 }
689
690 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
691 movq(as_Address(dst, rscratch), src);
692 }
693
694 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
695 movq(dst, as_Address(src, dst /*rscratch*/));
696 }
697
698 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
699 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
700 if (is_simm32(src)) {
701 movptr(dst, checked_cast<int32_t>(src));
702 } else {
703 mov64(rscratch, src);
704 movq(dst, rscratch);
705 }
706 }
707
708 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
709 movoop(rscratch, obj);
710 push(rscratch);
711 }
712
713 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
714 mov_metadata(rscratch, obj);
715 push(rscratch);
716 }
717
718 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
719 lea(rscratch, src);
720 if (src.is_lval()) {
721 push(rscratch);
722 } else {
723 pushq(Address(rscratch, 0));
724 }
725 }
726
727 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
728 reset_last_Java_frame(r15_thread, clear_fp);
729 }
730
731 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
732 Register last_java_fp,
733 address last_java_pc,
734 Register rscratch) {
735 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, last_java_pc, rscratch);
736 }
737
738 static void pass_arg0(MacroAssembler* masm, Register arg) {
739 if (c_rarg0 != arg ) {
740 masm->mov(c_rarg0, arg);
741 }
742 }
743
744 static void pass_arg1(MacroAssembler* masm, Register arg) {
745 if (c_rarg1 != arg ) {
746 masm->mov(c_rarg1, arg);
747 }
748 }
749
750 static void pass_arg2(MacroAssembler* masm, Register arg) {
751 if (c_rarg2 != arg ) {
752 masm->mov(c_rarg2, arg);
753 }
754 }
755
756 static void pass_arg3(MacroAssembler* masm, Register arg) {
757 if (c_rarg3 != arg ) {
758 masm->mov(c_rarg3, arg);
759 }
760 }
761
762 void MacroAssembler::stop(const char* msg) {
763 if (ShowMessageBoxOnError) {
764 address rip = pc();
765 pusha(); // get regs on stack
766 lea(c_rarg1, InternalAddress(rip));
767 movq(c_rarg2, rsp); // pass pointer to regs array
768 }
769 lea(c_rarg0, ExternalAddress((address) msg));
770 andq(rsp, -16); // align stack as required by ABI
771 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
772 hlt();
773 }
774
775 void MacroAssembler::warn(const char* msg) {
776 push(rbp);
777 movq(rbp, rsp);
778 andq(rsp, -16); // align stack as required by push_CPU_state and call
779 push_CPU_state(); // keeps alignment at 16 bytes
780
781 #ifdef _WIN64
782 // Windows always allocates space for its register args
783 subq(rsp, frame::arg_reg_save_area_bytes);
784 #endif
785 lea(c_rarg0, ExternalAddress((address) msg));
786 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
787
788 #ifdef _WIN64
789 // restore stack pointer
790 addq(rsp, frame::arg_reg_save_area_bytes);
791 #endif
792 pop_CPU_state();
793 mov(rsp, rbp);
794 pop(rbp);
795 }
796
797 void MacroAssembler::print_state() {
798 address rip = pc();
799 pusha(); // get regs on stack
800 push(rbp);
801 movq(rbp, rsp);
802 andq(rsp, -16); // align stack as required by push_CPU_state and call
803 push_CPU_state(); // keeps alignment at 16 bytes
804
805 lea(c_rarg0, InternalAddress(rip));
806 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
807 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
808
809 pop_CPU_state();
810 mov(rsp, rbp);
811 pop(rbp);
812 popa();
813 }
814
815 #ifndef PRODUCT
816 extern "C" void findpc(intptr_t x);
817 #endif
818
819 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
820 // In order to get locks to work, we need to fake a in_VM state
821 if (ShowMessageBoxOnError) {
822 JavaThread* thread = JavaThread::current();
823 JavaThreadState saved_state = thread->thread_state();
824 thread->set_thread_state(_thread_in_vm);
825 #ifndef PRODUCT
826 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
827 ttyLocker ttyl;
828 BytecodeCounter::print();
829 }
830 #endif
831 // To see where a verify_oop failed, get $ebx+40/X for this frame.
832 // XXX correct this offset for amd64
833 // This is the value of eip which points to where verify_oop will return.
834 if (os::message_box(msg, "Execution stopped, print registers?")) {
835 print_state64(pc, regs);
836 BREAKPOINT;
837 }
838 }
839 fatal("DEBUG MESSAGE: %s", msg);
840 }
841
842 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
843 ttyLocker ttyl;
844 DebuggingContext debugging{};
845 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
846 #ifndef PRODUCT
847 tty->cr();
848 findpc(pc);
849 tty->cr();
850 #endif
851 #define PRINT_REG(rax, value) \
852 { tty->print("%s = ", #rax); os::print_location(tty, value); }
853 PRINT_REG(rax, regs[15]);
854 PRINT_REG(rbx, regs[12]);
855 PRINT_REG(rcx, regs[14]);
856 PRINT_REG(rdx, regs[13]);
857 PRINT_REG(rdi, regs[8]);
858 PRINT_REG(rsi, regs[9]);
859 PRINT_REG(rbp, regs[10]);
860 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
861 PRINT_REG(rsp, (intptr_t)(®s[16]));
862 PRINT_REG(r8 , regs[7]);
863 PRINT_REG(r9 , regs[6]);
864 PRINT_REG(r10, regs[5]);
865 PRINT_REG(r11, regs[4]);
866 PRINT_REG(r12, regs[3]);
867 PRINT_REG(r13, regs[2]);
868 PRINT_REG(r14, regs[1]);
869 PRINT_REG(r15, regs[0]);
870 #undef PRINT_REG
871 // Print some words near the top of the stack.
872 int64_t* rsp = ®s[16];
873 int64_t* dump_sp = rsp;
874 for (int col1 = 0; col1 < 8; col1++) {
875 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
876 os::print_location(tty, *dump_sp++);
877 }
878 for (int row = 0; row < 25; row++) {
879 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
880 for (int col = 0; col < 4; col++) {
881 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
882 }
883 tty->cr();
884 }
885 // Print some instructions around pc:
886 Disassembler::decode((address)pc-64, (address)pc);
887 tty->print_cr("--------");
888 Disassembler::decode((address)pc, (address)pc+32);
889 }
890
891 // The java_calling_convention describes stack locations as ideal slots on
892 // a frame with no abi restrictions. Since we must observe abi restrictions
893 // (like the placement of the register window) the slots must be biased by
894 // the following value.
895 static int reg2offset_in(VMReg r) {
896 // Account for saved rbp and return address
897 // This should really be in_preserve_stack_slots
898 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
899 }
900
901 static int reg2offset_out(VMReg r) {
902 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
903 }
904
905 // A long move
906 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
907
908 // The calling conventions assures us that each VMregpair is either
909 // all really one physical register or adjacent stack slots.
910
911 if (src.is_single_phys_reg() ) {
912 if (dst.is_single_phys_reg()) {
913 if (dst.first() != src.first()) {
914 mov(dst.first()->as_Register(), src.first()->as_Register());
915 }
916 } else {
917 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
918 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
919 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
920 }
921 } else if (dst.is_single_phys_reg()) {
922 assert(src.is_single_reg(), "not a stack pair");
923 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
924 } else {
925 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
926 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
927 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
928 }
929 }
930
931 // A double move
932 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
933
934 // The calling conventions assures us that each VMregpair is either
935 // all really one physical register or adjacent stack slots.
936
937 if (src.is_single_phys_reg() ) {
938 if (dst.is_single_phys_reg()) {
939 // In theory these overlap but the ordering is such that this is likely a nop
940 if ( src.first() != dst.first()) {
941 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
942 }
943 } else {
944 assert(dst.is_single_reg(), "not a stack pair");
945 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
946 }
947 } else if (dst.is_single_phys_reg()) {
948 assert(src.is_single_reg(), "not a stack pair");
949 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
950 } else {
951 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
952 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
953 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
954 }
955 }
956
957
958 // A float arg may have to do float reg int reg conversion
959 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
960 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
961
962 // The calling conventions assures us that each VMregpair is either
963 // all really one physical register or adjacent stack slots.
964
965 if (src.first()->is_stack()) {
966 if (dst.first()->is_stack()) {
967 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
968 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
969 } else {
970 // stack to reg
971 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
972 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
973 }
974 } else if (dst.first()->is_stack()) {
975 // reg to stack
976 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
977 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
978 } else {
979 // reg to reg
980 // In theory these overlap but the ordering is such that this is likely a nop
981 if ( src.first() != dst.first()) {
982 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
983 }
984 }
985 }
986
987 // On 64 bit we will store integer like items to the stack as
988 // 64 bits items (x86_32/64 abi) even though java would only store
989 // 32bits for a parameter. On 32bit it will simply be 32 bits
990 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
991 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
992 if (src.first()->is_stack()) {
993 if (dst.first()->is_stack()) {
994 // stack to stack
995 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
996 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
997 } else {
998 // stack to reg
999 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
1000 }
1001 } else if (dst.first()->is_stack()) {
1002 // reg to stack
1003 // Do we really have to sign extend???
1004 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1005 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
1006 } else {
1007 // Do we really have to sign extend???
1008 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1009 if (dst.first() != src.first()) {
1010 movq(dst.first()->as_Register(), src.first()->as_Register());
1011 }
1012 }
1013 }
1014
1015 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1016 if (src.first()->is_stack()) {
1017 if (dst.first()->is_stack()) {
1018 // stack to stack
1019 movq(rax, Address(rbp, reg2offset_in(src.first())));
1020 movq(Address(rsp, reg2offset_out(dst.first())), rax);
1021 } else {
1022 // stack to reg
1023 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1024 }
1025 } else if (dst.first()->is_stack()) {
1026 // reg to stack
1027 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1028 } else {
1029 if (dst.first() != src.first()) {
1030 movq(dst.first()->as_Register(), src.first()->as_Register());
1031 }
1032 }
1033 }
1034
1035 // An oop arg. Must pass a handle not the oop itself
1036 void MacroAssembler::object_move(OopMap* map,
1037 int oop_handle_offset,
1038 int framesize_in_slots,
1039 VMRegPair src,
1040 VMRegPair dst,
1041 bool is_receiver,
1042 int* receiver_offset) {
1043
1044 // must pass a handle. First figure out the location we use as a handle
1045
1046 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1047
1048 // See if oop is null if it is we need no handle
1049
1050 if (src.first()->is_stack()) {
1051
1052 // Oop is already on the stack as an argument
1053 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1054 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1055 if (is_receiver) {
1056 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1057 }
1058
1059 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
1060 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1061 // conditionally move a null
1062 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1063 } else {
1064
1065 // Oop is in a register we must store it to the space we reserve
1066 // on the stack for oop_handles and pass a handle if oop is non-null
1067
1068 const Register rOop = src.first()->as_Register();
1069 int oop_slot;
1070 if (rOop == j_rarg0)
1071 oop_slot = 0;
1072 else if (rOop == j_rarg1)
1073 oop_slot = 1;
1074 else if (rOop == j_rarg2)
1075 oop_slot = 2;
1076 else if (rOop == j_rarg3)
1077 oop_slot = 3;
1078 else if (rOop == j_rarg4)
1079 oop_slot = 4;
1080 else {
1081 assert(rOop == j_rarg5, "wrong register");
1082 oop_slot = 5;
1083 }
1084
1085 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1086 int offset = oop_slot*VMRegImpl::stack_slot_size;
1087
1088 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1089 // Store oop in handle area, may be null
1090 movptr(Address(rsp, offset), rOop);
1091 if (is_receiver) {
1092 *receiver_offset = offset;
1093 }
1094
1095 cmpptr(rOop, NULL_WORD);
1096 lea(rHandle, Address(rsp, offset));
1097 // conditionally move a null from the handle area where it was just stored
1098 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1099 }
1100
1101 // If arg is on the stack then place it otherwise it is already in correct reg.
1102 if (dst.first()->is_stack()) {
1103 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1104 }
1105 }
1106
1107 #endif // _LP64
1108
1109 // Now versions that are common to 32/64 bit
1110
1111 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1112 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1113 }
1114
1115 void MacroAssembler::addptr(Register dst, Register src) {
1116 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1117 }
1118
1119 void MacroAssembler::addptr(Address dst, Register src) {
1120 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1121 }
1122
1123 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1124 assert(rscratch != noreg || always_reachable(src), "missing");
1125
1126 if (reachable(src)) {
1127 Assembler::addsd(dst, as_Address(src));
1128 } else {
1129 lea(rscratch, src);
1130 Assembler::addsd(dst, Address(rscratch, 0));
1131 }
1132 }
1133
1134 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1135 assert(rscratch != noreg || always_reachable(src), "missing");
1136
1137 if (reachable(src)) {
1138 addss(dst, as_Address(src));
1139 } else {
1140 lea(rscratch, src);
1141 addss(dst, Address(rscratch, 0));
1142 }
1143 }
1144
1145 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1146 assert(rscratch != noreg || always_reachable(src), "missing");
1147
1148 if (reachable(src)) {
1149 Assembler::addpd(dst, as_Address(src));
1150 } else {
1151 lea(rscratch, src);
1152 Assembler::addpd(dst, Address(rscratch, 0));
1153 }
1154 }
1155
1156 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
1157 // Stub code is generated once and never copied.
1158 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1159 void MacroAssembler::align64() {
1160 align(64, (uint)(uintptr_t)pc());
1161 }
1162
1163 void MacroAssembler::align32() {
1164 align(32, (uint)(uintptr_t)pc());
1165 }
1166
1167 void MacroAssembler::align(uint modulus) {
1168 // 8273459: Ensure alignment is possible with current segment alignment
1169 assert(modulus <= (uintx)CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1170 align(modulus, offset());
1171 }
1172
1173 void MacroAssembler::align(uint modulus, uint target) {
1174 if (target % modulus != 0) {
1175 nop(modulus - (target % modulus));
1176 }
1177 }
1178
1179 void MacroAssembler::push_f(XMMRegister r) {
1180 subptr(rsp, wordSize);
1181 movflt(Address(rsp, 0), r);
1182 }
1183
1184 void MacroAssembler::pop_f(XMMRegister r) {
1185 movflt(r, Address(rsp, 0));
1186 addptr(rsp, wordSize);
1187 }
1188
1189 void MacroAssembler::push_d(XMMRegister r) {
1190 subptr(rsp, 2 * wordSize);
1191 movdbl(Address(rsp, 0), r);
1192 }
1193
1194 void MacroAssembler::pop_d(XMMRegister r) {
1195 movdbl(r, Address(rsp, 0));
1196 addptr(rsp, 2 * Interpreter::stackElementSize);
1197 }
1198
1199 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1200 // Used in sign-masking with aligned address.
1201 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1202 assert(rscratch != noreg || always_reachable(src), "missing");
1203
1204 if (UseAVX > 2 &&
1205 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
1206 (dst->encoding() >= 16)) {
1207 vpand(dst, dst, src, AVX_512bit, rscratch);
1208 } else if (reachable(src)) {
1209 Assembler::andpd(dst, as_Address(src));
1210 } else {
1211 lea(rscratch, src);
1212 Assembler::andpd(dst, Address(rscratch, 0));
1213 }
1214 }
1215
1216 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
1217 // Used in sign-masking with aligned address.
1218 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1219 assert(rscratch != noreg || always_reachable(src), "missing");
1220
1221 if (reachable(src)) {
1222 Assembler::andps(dst, as_Address(src));
1223 } else {
1224 lea(rscratch, src);
1225 Assembler::andps(dst, Address(rscratch, 0));
1226 }
1227 }
1228
1229 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1230 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1231 }
1232
1233 #ifdef _LP64
1234 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
1235 assert(rscratch != noreg || always_reachable(src), "missing");
1236
1237 if (reachable(src)) {
1238 andq(dst, as_Address(src));
1239 } else {
1240 lea(rscratch, src);
1241 andq(dst, Address(rscratch, 0));
1242 }
1243 }
1244 #endif
1245
1246 void MacroAssembler::atomic_incl(Address counter_addr) {
1247 lock();
1248 incrementl(counter_addr);
1249 }
1250
1251 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
1252 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1253
1254 if (reachable(counter_addr)) {
1255 atomic_incl(as_Address(counter_addr));
1256 } else {
1257 lea(rscratch, counter_addr);
1258 atomic_incl(Address(rscratch, 0));
1259 }
1260 }
1261
1262 #ifdef _LP64
1263 void MacroAssembler::atomic_incq(Address counter_addr) {
1264 lock();
1265 incrementq(counter_addr);
1266 }
1267
1268 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
1269 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1270
1271 if (reachable(counter_addr)) {
1272 atomic_incq(as_Address(counter_addr));
1273 } else {
1274 lea(rscratch, counter_addr);
1275 atomic_incq(Address(rscratch, 0));
1276 }
1277 }
1278 #endif
1279
1280 // Writes to stack successive pages until offset reached to check for
1281 // stack overflow + shadow pages. This clobbers tmp.
1282 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1283 movptr(tmp, rsp);
1284 // Bang stack for total size given plus shadow page size.
1285 // Bang one page at a time because large size can bang beyond yellow and
1286 // red zones.
1287 Label loop;
1288 bind(loop);
1289 movl(Address(tmp, (-(int)os::vm_page_size())), size );
1290 subptr(tmp, (int)os::vm_page_size());
1291 subl(size, (int)os::vm_page_size());
1292 jcc(Assembler::greater, loop);
1293
1294 // Bang down shadow pages too.
1295 // At this point, (tmp-0) is the last address touched, so don't
1296 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1297 // was post-decremented.) Skip this address by starting at i=1, and
1298 // touch a few more pages below. N.B. It is important to touch all
1299 // the way down including all pages in the shadow zone.
1300 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
1301 // this could be any sized move but this is can be a debugging crumb
1302 // so the bigger the better.
1303 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
1304 }
1305 }
1306
1307 void MacroAssembler::reserved_stack_check() {
1308 // testing if reserved zone needs to be enabled
1309 Label no_reserved_zone_enabling;
1310 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1311 NOT_LP64(get_thread(rsi);)
1312
1313 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1314 jcc(Assembler::below, no_reserved_zone_enabling);
1315
1316 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1317 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
1318 should_not_reach_here();
1319
1320 bind(no_reserved_zone_enabling);
1321 }
1322
1323 void MacroAssembler::c2bool(Register x) {
1324 // implements x == 0 ? 0 : 1
1325 // note: must only look at least-significant byte of x
1326 // since C-style booleans are stored in one byte
1327 // only! (was bug)
1328 andl(x, 0xFF);
1329 setb(Assembler::notZero, x);
1330 }
1331
1332 // Wouldn't need if AddressLiteral version had new name
1333 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1334 Assembler::call(L, rtype);
1335 }
1336
1337 void MacroAssembler::call(Register entry) {
1338 Assembler::call(entry);
1339 }
1340
1341 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
1342 assert(rscratch != noreg || always_reachable(entry), "missing");
1343
1344 if (reachable(entry)) {
1345 Assembler::call_literal(entry.target(), entry.rspec());
1346 } else {
1347 lea(rscratch, entry);
1348 Assembler::call(rscratch);
1349 }
1350 }
1351
1352 void MacroAssembler::ic_call(address entry, jint method_index) {
1353 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1354 #ifdef _LP64
1355 // Needs full 64-bit immediate for later patching.
1356 mov64(rax, (int64_t)Universe::non_oop_word());
1357 #else
1358 movptr(rax, (intptr_t)Universe::non_oop_word());
1359 #endif
1360 call(AddressLiteral(entry, rh));
1361 }
1362
1363 int MacroAssembler::ic_check_size() {
1364 return
1365 LP64_ONLY(UseCompactObjectHeaders ? 17 : 14) NOT_LP64(12);
1366 }
1367
1368 int MacroAssembler::ic_check(int end_alignment) {
1369 Register receiver = LP64_ONLY(j_rarg0) NOT_LP64(rcx);
1370 Register data = rax;
1371 Register temp = LP64_ONLY(rscratch1) NOT_LP64(rbx);
1372
1373 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1374 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1375 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1376 // before the inline cache check here, and not after
1377 align(end_alignment, offset() + ic_check_size());
1378
1379 int uep_offset = offset();
1380
1381 #ifdef _LP64
1382 if (UseCompactObjectHeaders) {
1383 load_narrow_klass_compact(temp, receiver);
1384 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1385 } else
1386 #endif
1387 if (UseCompressedClassPointers) {
1388 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1389 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1390 } else {
1391 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1392 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
1393 }
1394
1395 // if inline cache check fails, then jump to runtime routine
1396 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1397 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
1398
1399 return uep_offset;
1400 }
1401
1402 void MacroAssembler::emit_static_call_stub() {
1403 // Static stub relocation also tags the Method* in the code-stream.
1404 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1405 // This is recognized as unresolved by relocs/nativeinst/ic code.
1406 jump(RuntimeAddress(pc()));
1407 }
1408
1409 // Implementation of call_VM versions
1410
1411 void MacroAssembler::call_VM(Register oop_result,
1412 address entry_point,
1413 bool check_exceptions) {
1414 Label C, E;
1415 call(C, relocInfo::none);
1416 jmp(E);
1417
1418 bind(C);
1419 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1420 ret(0);
1421
1422 bind(E);
1423 }
1424
1425 void MacroAssembler::call_VM(Register oop_result,
1426 address entry_point,
1427 Register arg_1,
1428 bool check_exceptions) {
1429 Label C, E;
1430 call(C, relocInfo::none);
1431 jmp(E);
1432
1433 bind(C);
1434 pass_arg1(this, arg_1);
1435 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1436 ret(0);
1437
1438 bind(E);
1439 }
1440
1441 void MacroAssembler::call_VM(Register oop_result,
1442 address entry_point,
1443 Register arg_1,
1444 Register arg_2,
1445 bool check_exceptions) {
1446 Label C, E;
1447 call(C, relocInfo::none);
1448 jmp(E);
1449
1450 bind(C);
1451
1452 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1453
1454 pass_arg2(this, arg_2);
1455 pass_arg1(this, arg_1);
1456 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1457 ret(0);
1458
1459 bind(E);
1460 }
1461
1462 void MacroAssembler::call_VM(Register oop_result,
1463 address entry_point,
1464 Register arg_1,
1465 Register arg_2,
1466 Register arg_3,
1467 bool check_exceptions) {
1468 Label C, E;
1469 call(C, relocInfo::none);
1470 jmp(E);
1471
1472 bind(C);
1473
1474 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1475 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1476 pass_arg3(this, arg_3);
1477 pass_arg2(this, arg_2);
1478 pass_arg1(this, arg_1);
1479 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1480 ret(0);
1481
1482 bind(E);
1483 }
1484
1485 void MacroAssembler::call_VM(Register oop_result,
1486 Register last_java_sp,
1487 address entry_point,
1488 int number_of_arguments,
1489 bool check_exceptions) {
1490 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1491 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1492 }
1493
1494 void MacroAssembler::call_VM(Register oop_result,
1495 Register last_java_sp,
1496 address entry_point,
1497 Register arg_1,
1498 bool check_exceptions) {
1499 pass_arg1(this, arg_1);
1500 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1501 }
1502
1503 void MacroAssembler::call_VM(Register oop_result,
1504 Register last_java_sp,
1505 address entry_point,
1506 Register arg_1,
1507 Register arg_2,
1508 bool check_exceptions) {
1509
1510 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1511 pass_arg2(this, arg_2);
1512 pass_arg1(this, arg_1);
1513 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1514 }
1515
1516 void MacroAssembler::call_VM(Register oop_result,
1517 Register last_java_sp,
1518 address entry_point,
1519 Register arg_1,
1520 Register arg_2,
1521 Register arg_3,
1522 bool check_exceptions) {
1523 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1524 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1525 pass_arg3(this, arg_3);
1526 pass_arg2(this, arg_2);
1527 pass_arg1(this, arg_1);
1528 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1529 }
1530
1531 void MacroAssembler::super_call_VM(Register oop_result,
1532 Register last_java_sp,
1533 address entry_point,
1534 int number_of_arguments,
1535 bool check_exceptions) {
1536 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1537 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1538 }
1539
1540 void MacroAssembler::super_call_VM(Register oop_result,
1541 Register last_java_sp,
1542 address entry_point,
1543 Register arg_1,
1544 bool check_exceptions) {
1545 pass_arg1(this, arg_1);
1546 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1547 }
1548
1549 void MacroAssembler::super_call_VM(Register oop_result,
1550 Register last_java_sp,
1551 address entry_point,
1552 Register arg_1,
1553 Register arg_2,
1554 bool check_exceptions) {
1555
1556 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1557 pass_arg2(this, arg_2);
1558 pass_arg1(this, arg_1);
1559 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1560 }
1561
1562 void MacroAssembler::super_call_VM(Register oop_result,
1563 Register last_java_sp,
1564 address entry_point,
1565 Register arg_1,
1566 Register arg_2,
1567 Register arg_3,
1568 bool check_exceptions) {
1569 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1570 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1571 pass_arg3(this, arg_3);
1572 pass_arg2(this, arg_2);
1573 pass_arg1(this, arg_1);
1574 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1575 }
1576
1577 void MacroAssembler::call_VM_base(Register oop_result,
1578 Register java_thread,
1579 Register last_java_sp,
1580 address entry_point,
1581 int number_of_arguments,
1582 bool check_exceptions) {
1583 // determine java_thread register
1584 if (!java_thread->is_valid()) {
1585 #ifdef _LP64
1586 java_thread = r15_thread;
1587 #else
1588 java_thread = rdi;
1589 get_thread(java_thread);
1590 #endif // LP64
1591 }
1592 // determine last_java_sp register
1593 if (!last_java_sp->is_valid()) {
1594 last_java_sp = rsp;
1595 }
1596 // debugging support
1597 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1598 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1599 #ifdef ASSERT
1600 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1601 // r12 is the heapbase.
1602 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1603 #endif // ASSERT
1604
1605 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1606 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1607
1608 // push java thread (becomes first argument of C function)
1609
1610 NOT_LP64(push(java_thread); number_of_arguments++);
1611 LP64_ONLY(mov(c_rarg0, r15_thread));
1612
1613 // set last Java frame before call
1614 assert(last_java_sp != rbp, "can't use ebp/rbp");
1615
1616 // Only interpreter should have to set fp
1617 set_last_Java_frame(java_thread, last_java_sp, rbp, nullptr, rscratch1);
1618
1619 // do the call, remove parameters
1620 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1621
1622 // restore the thread (cannot use the pushed argument since arguments
1623 // may be overwritten by C code generated by an optimizing compiler);
1624 // however can use the register value directly if it is callee saved.
1625 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1626 // rdi & rsi (also r15) are callee saved -> nothing to do
1627 #ifdef ASSERT
1628 guarantee(java_thread != rax, "change this code");
1629 push(rax);
1630 { Label L;
1631 get_thread(rax);
1632 cmpptr(java_thread, rax);
1633 jcc(Assembler::equal, L);
1634 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1635 bind(L);
1636 }
1637 pop(rax);
1638 #endif
1639 } else {
1640 get_thread(java_thread);
1641 }
1642 // reset last Java frame
1643 // Only interpreter should have to clear fp
1644 reset_last_Java_frame(java_thread, true);
1645
1646 // C++ interp handles this in the interpreter
1647 check_and_handle_popframe(java_thread);
1648 check_and_handle_earlyret(java_thread);
1649
1650 if (check_exceptions) {
1651 // check for pending exceptions (java_thread is set upon return)
1652 cmpptr(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
1653 #ifndef _LP64
1654 jump_cc(Assembler::notEqual,
1655 RuntimeAddress(StubRoutines::forward_exception_entry()));
1656 #else
1657 // This used to conditionally jump to forward_exception however it is
1658 // possible if we relocate that the branch will not reach. So we must jump
1659 // around so we can always reach
1660
1661 Label ok;
1662 jcc(Assembler::equal, ok);
1663 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1664 bind(ok);
1665 #endif // LP64
1666 }
1667
1668 // get oop result if there is one and reset the value in the thread
1669 if (oop_result->is_valid()) {
1670 get_vm_result(oop_result, java_thread);
1671 }
1672 }
1673
1674 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1675
1676 // Calculate the value for last_Java_sp
1677 // somewhat subtle. call_VM does an intermediate call
1678 // which places a return address on the stack just under the
1679 // stack pointer as the user finished with it. This allows
1680 // use to retrieve last_Java_pc from last_Java_sp[-1].
1681 // On 32bit we then have to push additional args on the stack to accomplish
1682 // the actual requested call. On 64bit call_VM only can use register args
1683 // so the only extra space is the return address that call_VM created.
1684 // This hopefully explains the calculations here.
1685
1686 #ifdef _LP64
1687 // We've pushed one address, correct last_Java_sp
1688 lea(rax, Address(rsp, wordSize));
1689 #else
1690 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1691 #endif // LP64
1692
1693 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1694
1695 }
1696
1697 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1698 void MacroAssembler::call_VM_leaf0(address entry_point) {
1699 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1700 }
1701
1702 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1703 call_VM_leaf_base(entry_point, number_of_arguments);
1704 }
1705
1706 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1707 pass_arg0(this, arg_0);
1708 call_VM_leaf(entry_point, 1);
1709 }
1710
1711 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1712
1713 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1714 pass_arg1(this, arg_1);
1715 pass_arg0(this, arg_0);
1716 call_VM_leaf(entry_point, 2);
1717 }
1718
1719 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1720 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1721 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1722 pass_arg2(this, arg_2);
1723 pass_arg1(this, arg_1);
1724 pass_arg0(this, arg_0);
1725 call_VM_leaf(entry_point, 3);
1726 }
1727
1728 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1729 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1730 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1731 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1732 pass_arg3(this, arg_3);
1733 pass_arg2(this, arg_2);
1734 pass_arg1(this, arg_1);
1735 pass_arg0(this, arg_0);
1736 call_VM_leaf(entry_point, 3);
1737 }
1738
1739 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1740 pass_arg0(this, arg_0);
1741 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1742 }
1743
1744 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1745 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1746 pass_arg1(this, arg_1);
1747 pass_arg0(this, arg_0);
1748 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1749 }
1750
1751 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1752 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1753 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1754 pass_arg2(this, arg_2);
1755 pass_arg1(this, arg_1);
1756 pass_arg0(this, arg_0);
1757 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1758 }
1759
1760 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1761 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1762 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1763 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1764 pass_arg3(this, arg_3);
1765 pass_arg2(this, arg_2);
1766 pass_arg1(this, arg_1);
1767 pass_arg0(this, arg_0);
1768 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1769 }
1770
1771 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1772 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1773 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1774 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1775 }
1776
1777 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1778 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1779 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1780 }
1781
1782 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1783 }
1784
1785 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1786 }
1787
1788 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1789 assert(rscratch != noreg || always_reachable(src1), "missing");
1790
1791 if (reachable(src1)) {
1792 cmpl(as_Address(src1), imm);
1793 } else {
1794 lea(rscratch, src1);
1795 cmpl(Address(rscratch, 0), imm);
1796 }
1797 }
1798
1799 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1800 assert(!src2.is_lval(), "use cmpptr");
1801 assert(rscratch != noreg || always_reachable(src2), "missing");
1802
1803 if (reachable(src2)) {
1804 cmpl(src1, as_Address(src2));
1805 } else {
1806 lea(rscratch, src2);
1807 cmpl(src1, Address(rscratch, 0));
1808 }
1809 }
1810
1811 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1812 Assembler::cmpl(src1, imm);
1813 }
1814
1815 void MacroAssembler::cmp32(Register src1, Address src2) {
1816 Assembler::cmpl(src1, src2);
1817 }
1818
1819 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1820 ucomisd(opr1, opr2);
1821
1822 Label L;
1823 if (unordered_is_less) {
1824 movl(dst, -1);
1825 jcc(Assembler::parity, L);
1826 jcc(Assembler::below , L);
1827 movl(dst, 0);
1828 jcc(Assembler::equal , L);
1829 increment(dst);
1830 } else { // unordered is greater
1831 movl(dst, 1);
1832 jcc(Assembler::parity, L);
1833 jcc(Assembler::above , L);
1834 movl(dst, 0);
1835 jcc(Assembler::equal , L);
1836 decrementl(dst);
1837 }
1838 bind(L);
1839 }
1840
1841 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1842 ucomiss(opr1, opr2);
1843
1844 Label L;
1845 if (unordered_is_less) {
1846 movl(dst, -1);
1847 jcc(Assembler::parity, L);
1848 jcc(Assembler::below , L);
1849 movl(dst, 0);
1850 jcc(Assembler::equal , L);
1851 increment(dst);
1852 } else { // unordered is greater
1853 movl(dst, 1);
1854 jcc(Assembler::parity, L);
1855 jcc(Assembler::above , L);
1856 movl(dst, 0);
1857 jcc(Assembler::equal , L);
1858 decrementl(dst);
1859 }
1860 bind(L);
1861 }
1862
1863
1864 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1865 assert(rscratch != noreg || always_reachable(src1), "missing");
1866
1867 if (reachable(src1)) {
1868 cmpb(as_Address(src1), imm);
1869 } else {
1870 lea(rscratch, src1);
1871 cmpb(Address(rscratch, 0), imm);
1872 }
1873 }
1874
1875 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1876 #ifdef _LP64
1877 assert(rscratch != noreg || always_reachable(src2), "missing");
1878
1879 if (src2.is_lval()) {
1880 movptr(rscratch, src2);
1881 Assembler::cmpq(src1, rscratch);
1882 } else if (reachable(src2)) {
1883 cmpq(src1, as_Address(src2));
1884 } else {
1885 lea(rscratch, src2);
1886 Assembler::cmpq(src1, Address(rscratch, 0));
1887 }
1888 #else
1889 assert(rscratch == noreg, "not needed");
1890 if (src2.is_lval()) {
1891 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1892 } else {
1893 cmpl(src1, as_Address(src2));
1894 }
1895 #endif // _LP64
1896 }
1897
1898 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1899 assert(src2.is_lval(), "not a mem-mem compare");
1900 #ifdef _LP64
1901 // moves src2's literal address
1902 movptr(rscratch, src2);
1903 Assembler::cmpq(src1, rscratch);
1904 #else
1905 assert(rscratch == noreg, "not needed");
1906 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1907 #endif // _LP64
1908 }
1909
1910 void MacroAssembler::cmpoop(Register src1, Register src2) {
1911 cmpptr(src1, src2);
1912 }
1913
1914 void MacroAssembler::cmpoop(Register src1, Address src2) {
1915 cmpptr(src1, src2);
1916 }
1917
1918 #ifdef _LP64
1919 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1920 movoop(rscratch, src2);
1921 cmpptr(src1, rscratch);
1922 }
1923 #endif
1924
1925 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1926 assert(rscratch != noreg || always_reachable(adr), "missing");
1927
1928 if (reachable(adr)) {
1929 lock();
1930 cmpxchgptr(reg, as_Address(adr));
1931 } else {
1932 lea(rscratch, adr);
1933 lock();
1934 cmpxchgptr(reg, Address(rscratch, 0));
1935 }
1936 }
1937
1938 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1939 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1940 }
1941
1942 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1943 assert(rscratch != noreg || always_reachable(src), "missing");
1944
1945 if (reachable(src)) {
1946 Assembler::comisd(dst, as_Address(src));
1947 } else {
1948 lea(rscratch, src);
1949 Assembler::comisd(dst, Address(rscratch, 0));
1950 }
1951 }
1952
1953 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1954 assert(rscratch != noreg || always_reachable(src), "missing");
1955
1956 if (reachable(src)) {
1957 Assembler::comiss(dst, as_Address(src));
1958 } else {
1959 lea(rscratch, src);
1960 Assembler::comiss(dst, Address(rscratch, 0));
1961 }
1962 }
1963
1964
1965 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1966 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1967
1968 Condition negated_cond = negate_condition(cond);
1969 Label L;
1970 jcc(negated_cond, L);
1971 pushf(); // Preserve flags
1972 atomic_incl(counter_addr, rscratch);
1973 popf();
1974 bind(L);
1975 }
1976
1977 int MacroAssembler::corrected_idivl(Register reg) {
1978 // Full implementation of Java idiv and irem; checks for
1979 // special case as described in JVM spec., p.243 & p.271.
1980 // The function returns the (pc) offset of the idivl
1981 // instruction - may be needed for implicit exceptions.
1982 //
1983 // normal case special case
1984 //
1985 // input : rax,: dividend min_int
1986 // reg: divisor (may not be rax,/rdx) -1
1987 //
1988 // output: rax,: quotient (= rax, idiv reg) min_int
1989 // rdx: remainder (= rax, irem reg) 0
1990 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1991 const int min_int = 0x80000000;
1992 Label normal_case, special_case;
1993
1994 // check for special case
1995 cmpl(rax, min_int);
1996 jcc(Assembler::notEqual, normal_case);
1997 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1998 cmpl(reg, -1);
1999 jcc(Assembler::equal, special_case);
2000
2001 // handle normal case
2002 bind(normal_case);
2003 cdql();
2004 int idivl_offset = offset();
2005 idivl(reg);
2006
2007 // normal and special case exit
2008 bind(special_case);
2009
2010 return idivl_offset;
2011 }
2012
2013
2014
2015 void MacroAssembler::decrementl(Register reg, int value) {
2016 if (value == min_jint) {subl(reg, value) ; return; }
2017 if (value < 0) { incrementl(reg, -value); return; }
2018 if (value == 0) { ; return; }
2019 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2020 /* else */ { subl(reg, value) ; return; }
2021 }
2022
2023 void MacroAssembler::decrementl(Address dst, int value) {
2024 if (value == min_jint) {subl(dst, value) ; return; }
2025 if (value < 0) { incrementl(dst, -value); return; }
2026 if (value == 0) { ; return; }
2027 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2028 /* else */ { subl(dst, value) ; return; }
2029 }
2030
2031 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2032 assert(shift_value > 0, "illegal shift value");
2033 Label _is_positive;
2034 testl (reg, reg);
2035 jcc (Assembler::positive, _is_positive);
2036 int offset = (1 << shift_value) - 1 ;
2037
2038 if (offset == 1) {
2039 incrementl(reg);
2040 } else {
2041 addl(reg, offset);
2042 }
2043
2044 bind (_is_positive);
2045 sarl(reg, shift_value);
2046 }
2047
2048 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2049 assert(rscratch != noreg || always_reachable(src), "missing");
2050
2051 if (reachable(src)) {
2052 Assembler::divsd(dst, as_Address(src));
2053 } else {
2054 lea(rscratch, src);
2055 Assembler::divsd(dst, Address(rscratch, 0));
2056 }
2057 }
2058
2059 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2060 assert(rscratch != noreg || always_reachable(src), "missing");
2061
2062 if (reachable(src)) {
2063 Assembler::divss(dst, as_Address(src));
2064 } else {
2065 lea(rscratch, src);
2066 Assembler::divss(dst, Address(rscratch, 0));
2067 }
2068 }
2069
2070 void MacroAssembler::enter() {
2071 push(rbp);
2072 mov(rbp, rsp);
2073 }
2074
2075 void MacroAssembler::post_call_nop() {
2076 if (!Continuations::enabled()) {
2077 return;
2078 }
2079 InstructionMark im(this);
2080 relocate(post_call_nop_Relocation::spec());
2081 InlineSkippedInstructionsCounter skipCounter(this);
2082 emit_int8((uint8_t)0x0f);
2083 emit_int8((uint8_t)0x1f);
2084 emit_int8((uint8_t)0x84);
2085 emit_int8((uint8_t)0x00);
2086 emit_int32(0x00);
2087 }
2088
2089 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2090 void MacroAssembler::fat_nop() {
2091 if (UseAddressNop) {
2092 addr_nop_5();
2093 } else {
2094 emit_int8((uint8_t)0x26); // es:
2095 emit_int8((uint8_t)0x2e); // cs:
2096 emit_int8((uint8_t)0x64); // fs:
2097 emit_int8((uint8_t)0x65); // gs:
2098 emit_int8((uint8_t)0x90);
2099 }
2100 }
2101
2102 #ifndef _LP64
2103 void MacroAssembler::fcmp(Register tmp) {
2104 fcmp(tmp, 1, true, true);
2105 }
2106
2107 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2108 assert(!pop_right || pop_left, "usage error");
2109 if (VM_Version::supports_cmov()) {
2110 assert(tmp == noreg, "unneeded temp");
2111 if (pop_left) {
2112 fucomip(index);
2113 } else {
2114 fucomi(index);
2115 }
2116 if (pop_right) {
2117 fpop();
2118 }
2119 } else {
2120 assert(tmp != noreg, "need temp");
2121 if (pop_left) {
2122 if (pop_right) {
2123 fcompp();
2124 } else {
2125 fcomp(index);
2126 }
2127 } else {
2128 fcom(index);
2129 }
2130 // convert FPU condition into eflags condition via rax,
2131 save_rax(tmp);
2132 fwait(); fnstsw_ax();
2133 sahf();
2134 restore_rax(tmp);
2135 }
2136 // condition codes set as follows:
2137 //
2138 // CF (corresponds to C0) if x < y
2139 // PF (corresponds to C2) if unordered
2140 // ZF (corresponds to C3) if x = y
2141 }
2142
2143 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2144 fcmp2int(dst, unordered_is_less, 1, true, true);
2145 }
2146
2147 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2148 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2149 Label L;
2150 if (unordered_is_less) {
2151 movl(dst, -1);
2152 jcc(Assembler::parity, L);
2153 jcc(Assembler::below , L);
2154 movl(dst, 0);
2155 jcc(Assembler::equal , L);
2156 increment(dst);
2157 } else { // unordered is greater
2158 movl(dst, 1);
2159 jcc(Assembler::parity, L);
2160 jcc(Assembler::above , L);
2161 movl(dst, 0);
2162 jcc(Assembler::equal , L);
2163 decrementl(dst);
2164 }
2165 bind(L);
2166 }
2167
2168 void MacroAssembler::fld_d(AddressLiteral src) {
2169 fld_d(as_Address(src));
2170 }
2171
2172 void MacroAssembler::fld_s(AddressLiteral src) {
2173 fld_s(as_Address(src));
2174 }
2175
2176 void MacroAssembler::fldcw(AddressLiteral src) {
2177 fldcw(as_Address(src));
2178 }
2179
2180 void MacroAssembler::fpop() {
2181 ffree();
2182 fincstp();
2183 }
2184
2185 void MacroAssembler::fremr(Register tmp) {
2186 save_rax(tmp);
2187 { Label L;
2188 bind(L);
2189 fprem();
2190 fwait(); fnstsw_ax();
2191 sahf();
2192 jcc(Assembler::parity, L);
2193 }
2194 restore_rax(tmp);
2195 // Result is in ST0.
2196 // Note: fxch & fpop to get rid of ST1
2197 // (otherwise FPU stack could overflow eventually)
2198 fxch(1);
2199 fpop();
2200 }
2201
2202 void MacroAssembler::empty_FPU_stack() {
2203 if (VM_Version::supports_mmx()) {
2204 emms();
2205 } else {
2206 for (int i = 8; i-- > 0; ) ffree(i);
2207 }
2208 }
2209 #endif // !LP64
2210
2211 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2212 assert(rscratch != noreg || always_reachable(src), "missing");
2213 if (reachable(src)) {
2214 Assembler::mulpd(dst, as_Address(src));
2215 } else {
2216 lea(rscratch, src);
2217 Assembler::mulpd(dst, Address(rscratch, 0));
2218 }
2219 }
2220
2221 void MacroAssembler::load_float(Address src) {
2222 #ifdef _LP64
2223 movflt(xmm0, src);
2224 #else
2225 if (UseSSE >= 1) {
2226 movflt(xmm0, src);
2227 } else {
2228 fld_s(src);
2229 }
2230 #endif // LP64
2231 }
2232
2233 void MacroAssembler::store_float(Address dst) {
2234 #ifdef _LP64
2235 movflt(dst, xmm0);
2236 #else
2237 if (UseSSE >= 1) {
2238 movflt(dst, xmm0);
2239 } else {
2240 fstp_s(dst);
2241 }
2242 #endif // LP64
2243 }
2244
2245 void MacroAssembler::load_double(Address src) {
2246 #ifdef _LP64
2247 movdbl(xmm0, src);
2248 #else
2249 if (UseSSE >= 2) {
2250 movdbl(xmm0, src);
2251 } else {
2252 fld_d(src);
2253 }
2254 #endif // LP64
2255 }
2256
2257 void MacroAssembler::store_double(Address dst) {
2258 #ifdef _LP64
2259 movdbl(dst, xmm0);
2260 #else
2261 if (UseSSE >= 2) {
2262 movdbl(dst, xmm0);
2263 } else {
2264 fstp_d(dst);
2265 }
2266 #endif // LP64
2267 }
2268
2269 // dst = c = a * b + c
2270 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2271 Assembler::vfmadd231sd(c, a, b);
2272 if (dst != c) {
2273 movdbl(dst, c);
2274 }
2275 }
2276
2277 // dst = c = a * b + c
2278 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2279 Assembler::vfmadd231ss(c, a, b);
2280 if (dst != c) {
2281 movflt(dst, c);
2282 }
2283 }
2284
2285 // dst = c = a * b + c
2286 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2287 Assembler::vfmadd231pd(c, a, b, vector_len);
2288 if (dst != c) {
2289 vmovdqu(dst, c);
2290 }
2291 }
2292
2293 // dst = c = a * b + c
2294 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2295 Assembler::vfmadd231ps(c, a, b, vector_len);
2296 if (dst != c) {
2297 vmovdqu(dst, c);
2298 }
2299 }
2300
2301 // dst = c = a * b + c
2302 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2303 Assembler::vfmadd231pd(c, a, b, vector_len);
2304 if (dst != c) {
2305 vmovdqu(dst, c);
2306 }
2307 }
2308
2309 // dst = c = a * b + c
2310 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2311 Assembler::vfmadd231ps(c, a, b, vector_len);
2312 if (dst != c) {
2313 vmovdqu(dst, c);
2314 }
2315 }
2316
2317 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
2318 assert(rscratch != noreg || always_reachable(dst), "missing");
2319
2320 if (reachable(dst)) {
2321 incrementl(as_Address(dst));
2322 } else {
2323 lea(rscratch, dst);
2324 incrementl(Address(rscratch, 0));
2325 }
2326 }
2327
2328 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
2329 incrementl(as_Address(dst, rscratch));
2330 }
2331
2332 void MacroAssembler::incrementl(Register reg, int value) {
2333 if (value == min_jint) {addl(reg, value) ; return; }
2334 if (value < 0) { decrementl(reg, -value); return; }
2335 if (value == 0) { ; return; }
2336 if (value == 1 && UseIncDec) { incl(reg) ; return; }
2337 /* else */ { addl(reg, value) ; return; }
2338 }
2339
2340 void MacroAssembler::incrementl(Address dst, int value) {
2341 if (value == min_jint) {addl(dst, value) ; return; }
2342 if (value < 0) { decrementl(dst, -value); return; }
2343 if (value == 0) { ; return; }
2344 if (value == 1 && UseIncDec) { incl(dst) ; return; }
2345 /* else */ { addl(dst, value) ; return; }
2346 }
2347
2348 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
2349 assert(rscratch != noreg || always_reachable(dst), "missing");
2350 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
2351 if (reachable(dst)) {
2352 jmp_literal(dst.target(), dst.rspec());
2353 } else {
2354 lea(rscratch, dst);
2355 jmp(rscratch);
2356 }
2357 }
2358
2359 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
2360 assert(rscratch != noreg || always_reachable(dst), "missing");
2361 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
2362 if (reachable(dst)) {
2363 InstructionMark im(this);
2364 relocate(dst.reloc());
2365 const int short_size = 2;
2366 const int long_size = 6;
2367 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2368 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2369 // 0111 tttn #8-bit disp
2370 emit_int8(0x70 | cc);
2371 emit_int8((offs - short_size) & 0xFF);
2372 } else {
2373 // 0000 1111 1000 tttn #32-bit disp
2374 emit_int8(0x0F);
2375 emit_int8((unsigned char)(0x80 | cc));
2376 emit_int32(offs - long_size);
2377 }
2378 } else {
2379 #ifdef ASSERT
2380 warning("reversing conditional branch");
2381 #endif /* ASSERT */
2382 Label skip;
2383 jccb(reverse[cc], skip);
2384 lea(rscratch, dst);
2385 Assembler::jmp(rscratch);
2386 bind(skip);
2387 }
2388 }
2389
2390 void MacroAssembler::cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch) {
2391 ExternalAddress mxcsr_std(StubRoutines::x86::addr_mxcsr_std());
2392 assert(rscratch != noreg || always_reachable(mxcsr_std), "missing");
2393
2394 stmxcsr(mxcsr_save);
2395 movl(tmp, mxcsr_save);
2396 if (EnableX86ECoreOpts) {
2397 // The mxcsr_std has status bits set for performance on ECore
2398 orl(tmp, 0x003f);
2399 } else {
2400 // Mask out status bits (only check control and mask bits)
2401 andl(tmp, 0xFFC0);
2402 }
2403 cmp32(tmp, mxcsr_std, rscratch);
2404 }
2405
2406 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
2407 assert(rscratch != noreg || always_reachable(src), "missing");
2408
2409 if (reachable(src)) {
2410 Assembler::ldmxcsr(as_Address(src));
2411 } else {
2412 lea(rscratch, src);
2413 Assembler::ldmxcsr(Address(rscratch, 0));
2414 }
2415 }
2416
2417 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2418 int off;
2419 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2420 off = offset();
2421 movsbl(dst, src); // movsxb
2422 } else {
2423 off = load_unsigned_byte(dst, src);
2424 shll(dst, 24);
2425 sarl(dst, 24);
2426 }
2427 return off;
2428 }
2429
2430 // Note: load_signed_short used to be called load_signed_word.
2431 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2432 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2433 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2434 int MacroAssembler::load_signed_short(Register dst, Address src) {
2435 int off;
2436 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2437 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2438 // version but this is what 64bit has always done. This seems to imply
2439 // that users are only using 32bits worth.
2440 off = offset();
2441 movswl(dst, src); // movsxw
2442 } else {
2443 off = load_unsigned_short(dst, src);
2444 shll(dst, 16);
2445 sarl(dst, 16);
2446 }
2447 return off;
2448 }
2449
2450 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2451 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2452 // and "3.9 Partial Register Penalties", p. 22).
2453 int off;
2454 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2455 off = offset();
2456 movzbl(dst, src); // movzxb
2457 } else {
2458 xorl(dst, dst);
2459 off = offset();
2460 movb(dst, src);
2461 }
2462 return off;
2463 }
2464
2465 // Note: load_unsigned_short used to be called load_unsigned_word.
2466 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2467 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2468 // and "3.9 Partial Register Penalties", p. 22).
2469 int off;
2470 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2471 off = offset();
2472 movzwl(dst, src); // movzxw
2473 } else {
2474 xorl(dst, dst);
2475 off = offset();
2476 movw(dst, src);
2477 }
2478 return off;
2479 }
2480
2481 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2482 switch (size_in_bytes) {
2483 #ifndef _LP64
2484 case 8:
2485 assert(dst2 != noreg, "second dest register required");
2486 movl(dst, src);
2487 movl(dst2, src.plus_disp(BytesPerInt));
2488 break;
2489 #else
2490 case 8: movq(dst, src); break;
2491 #endif
2492 case 4: movl(dst, src); break;
2493 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2494 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2495 default: ShouldNotReachHere();
2496 }
2497 }
2498
2499 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2500 switch (size_in_bytes) {
2501 #ifndef _LP64
2502 case 8:
2503 assert(src2 != noreg, "second source register required");
2504 movl(dst, src);
2505 movl(dst.plus_disp(BytesPerInt), src2);
2506 break;
2507 #else
2508 case 8: movq(dst, src); break;
2509 #endif
2510 case 4: movl(dst, src); break;
2511 case 2: movw(dst, src); break;
2512 case 1: movb(dst, src); break;
2513 default: ShouldNotReachHere();
2514 }
2515 }
2516
2517 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
2518 assert(rscratch != noreg || always_reachable(dst), "missing");
2519
2520 if (reachable(dst)) {
2521 movl(as_Address(dst), src);
2522 } else {
2523 lea(rscratch, dst);
2524 movl(Address(rscratch, 0), src);
2525 }
2526 }
2527
2528 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2529 if (reachable(src)) {
2530 movl(dst, as_Address(src));
2531 } else {
2532 lea(dst, src);
2533 movl(dst, Address(dst, 0));
2534 }
2535 }
2536
2537 // C++ bool manipulation
2538
2539 void MacroAssembler::movbool(Register dst, Address src) {
2540 if(sizeof(bool) == 1)
2541 movb(dst, src);
2542 else if(sizeof(bool) == 2)
2543 movw(dst, src);
2544 else if(sizeof(bool) == 4)
2545 movl(dst, src);
2546 else
2547 // unsupported
2548 ShouldNotReachHere();
2549 }
2550
2551 void MacroAssembler::movbool(Address dst, bool boolconst) {
2552 if(sizeof(bool) == 1)
2553 movb(dst, (int) boolconst);
2554 else if(sizeof(bool) == 2)
2555 movw(dst, (int) boolconst);
2556 else if(sizeof(bool) == 4)
2557 movl(dst, (int) boolconst);
2558 else
2559 // unsupported
2560 ShouldNotReachHere();
2561 }
2562
2563 void MacroAssembler::movbool(Address dst, Register src) {
2564 if(sizeof(bool) == 1)
2565 movb(dst, src);
2566 else if(sizeof(bool) == 2)
2567 movw(dst, src);
2568 else if(sizeof(bool) == 4)
2569 movl(dst, src);
2570 else
2571 // unsupported
2572 ShouldNotReachHere();
2573 }
2574
2575 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2576 assert(rscratch != noreg || always_reachable(src), "missing");
2577
2578 if (reachable(src)) {
2579 movdl(dst, as_Address(src));
2580 } else {
2581 lea(rscratch, src);
2582 movdl(dst, Address(rscratch, 0));
2583 }
2584 }
2585
2586 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
2587 assert(rscratch != noreg || always_reachable(src), "missing");
2588
2589 if (reachable(src)) {
2590 movq(dst, as_Address(src));
2591 } else {
2592 lea(rscratch, src);
2593 movq(dst, Address(rscratch, 0));
2594 }
2595 }
2596
2597 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2598 assert(rscratch != noreg || always_reachable(src), "missing");
2599
2600 if (reachable(src)) {
2601 if (UseXmmLoadAndClearUpper) {
2602 movsd (dst, as_Address(src));
2603 } else {
2604 movlpd(dst, as_Address(src));
2605 }
2606 } else {
2607 lea(rscratch, src);
2608 if (UseXmmLoadAndClearUpper) {
2609 movsd (dst, Address(rscratch, 0));
2610 } else {
2611 movlpd(dst, Address(rscratch, 0));
2612 }
2613 }
2614 }
2615
2616 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
2617 assert(rscratch != noreg || always_reachable(src), "missing");
2618
2619 if (reachable(src)) {
2620 movss(dst, as_Address(src));
2621 } else {
2622 lea(rscratch, src);
2623 movss(dst, Address(rscratch, 0));
2624 }
2625 }
2626
2627 void MacroAssembler::movptr(Register dst, Register src) {
2628 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2629 }
2630
2631 void MacroAssembler::movptr(Register dst, Address src) {
2632 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2633 }
2634
2635 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2636 void MacroAssembler::movptr(Register dst, intptr_t src) {
2637 #ifdef _LP64
2638 if (is_uimm32(src)) {
2639 movl(dst, checked_cast<uint32_t>(src));
2640 } else if (is_simm32(src)) {
2641 movq(dst, checked_cast<int32_t>(src));
2642 } else {
2643 mov64(dst, src);
2644 }
2645 #else
2646 movl(dst, src);
2647 #endif
2648 }
2649
2650 void MacroAssembler::movptr(Address dst, Register src) {
2651 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2652 }
2653
2654 void MacroAssembler::movptr(Address dst, int32_t src) {
2655 LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src));
2656 }
2657
2658 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2659 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2660 Assembler::movdqu(dst, src);
2661 }
2662
2663 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2664 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2665 Assembler::movdqu(dst, src);
2666 }
2667
2668 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2669 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2670 Assembler::movdqu(dst, src);
2671 }
2672
2673 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2674 assert(rscratch != noreg || always_reachable(src), "missing");
2675
2676 if (reachable(src)) {
2677 movdqu(dst, as_Address(src));
2678 } else {
2679 lea(rscratch, src);
2680 movdqu(dst, Address(rscratch, 0));
2681 }
2682 }
2683
2684 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2685 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2686 Assembler::vmovdqu(dst, src);
2687 }
2688
2689 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2690 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2691 Assembler::vmovdqu(dst, src);
2692 }
2693
2694 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2695 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2696 Assembler::vmovdqu(dst, src);
2697 }
2698
2699 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2700 assert(rscratch != noreg || always_reachable(src), "missing");
2701
2702 if (reachable(src)) {
2703 vmovdqu(dst, as_Address(src));
2704 }
2705 else {
2706 lea(rscratch, src);
2707 vmovdqu(dst, Address(rscratch, 0));
2708 }
2709 }
2710
2711 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2712 assert(rscratch != noreg || always_reachable(src), "missing");
2713
2714 if (vector_len == AVX_512bit) {
2715 evmovdquq(dst, src, AVX_512bit, rscratch);
2716 } else if (vector_len == AVX_256bit) {
2717 vmovdqu(dst, src, rscratch);
2718 } else {
2719 movdqu(dst, src, rscratch);
2720 }
2721 }
2722
2723 void MacroAssembler::kmov(KRegister dst, Address src) {
2724 if (VM_Version::supports_avx512bw()) {
2725 kmovql(dst, src);
2726 } else {
2727 assert(VM_Version::supports_evex(), "");
2728 kmovwl(dst, src);
2729 }
2730 }
2731
2732 void MacroAssembler::kmov(Address dst, KRegister src) {
2733 if (VM_Version::supports_avx512bw()) {
2734 kmovql(dst, src);
2735 } else {
2736 assert(VM_Version::supports_evex(), "");
2737 kmovwl(dst, src);
2738 }
2739 }
2740
2741 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2742 if (VM_Version::supports_avx512bw()) {
2743 kmovql(dst, src);
2744 } else {
2745 assert(VM_Version::supports_evex(), "");
2746 kmovwl(dst, src);
2747 }
2748 }
2749
2750 void MacroAssembler::kmov(Register dst, KRegister src) {
2751 if (VM_Version::supports_avx512bw()) {
2752 kmovql(dst, src);
2753 } else {
2754 assert(VM_Version::supports_evex(), "");
2755 kmovwl(dst, src);
2756 }
2757 }
2758
2759 void MacroAssembler::kmov(KRegister dst, Register src) {
2760 if (VM_Version::supports_avx512bw()) {
2761 kmovql(dst, src);
2762 } else {
2763 assert(VM_Version::supports_evex(), "");
2764 kmovwl(dst, src);
2765 }
2766 }
2767
2768 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2769 assert(rscratch != noreg || always_reachable(src), "missing");
2770
2771 if (reachable(src)) {
2772 kmovql(dst, as_Address(src));
2773 } else {
2774 lea(rscratch, src);
2775 kmovql(dst, Address(rscratch, 0));
2776 }
2777 }
2778
2779 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2780 assert(rscratch != noreg || always_reachable(src), "missing");
2781
2782 if (reachable(src)) {
2783 kmovwl(dst, as_Address(src));
2784 } else {
2785 lea(rscratch, src);
2786 kmovwl(dst, Address(rscratch, 0));
2787 }
2788 }
2789
2790 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2791 int vector_len, Register rscratch) {
2792 assert(rscratch != noreg || always_reachable(src), "missing");
2793
2794 if (reachable(src)) {
2795 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2796 } else {
2797 lea(rscratch, src);
2798 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2799 }
2800 }
2801
2802 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2803 int vector_len, Register rscratch) {
2804 assert(rscratch != noreg || always_reachable(src), "missing");
2805
2806 if (reachable(src)) {
2807 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2808 } else {
2809 lea(rscratch, src);
2810 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2811 }
2812 }
2813
2814 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2815 assert(rscratch != noreg || always_reachable(src), "missing");
2816
2817 if (reachable(src)) {
2818 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2819 } else {
2820 lea(rscratch, src);
2821 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2822 }
2823 }
2824
2825 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2826 assert(rscratch != noreg || always_reachable(src), "missing");
2827
2828 if (reachable(src)) {
2829 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2830 } else {
2831 lea(rscratch, src);
2832 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2833 }
2834 }
2835
2836 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2837 assert(rscratch != noreg || always_reachable(src), "missing");
2838
2839 if (reachable(src)) {
2840 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2841 } else {
2842 lea(rscratch, src);
2843 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2844 }
2845 }
2846
2847 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2848 assert(rscratch != noreg || always_reachable(src), "missing");
2849
2850 if (reachable(src)) {
2851 Assembler::movdqa(dst, as_Address(src));
2852 } else {
2853 lea(rscratch, src);
2854 Assembler::movdqa(dst, Address(rscratch, 0));
2855 }
2856 }
2857
2858 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2859 assert(rscratch != noreg || always_reachable(src), "missing");
2860
2861 if (reachable(src)) {
2862 Assembler::movsd(dst, as_Address(src));
2863 } else {
2864 lea(rscratch, src);
2865 Assembler::movsd(dst, Address(rscratch, 0));
2866 }
2867 }
2868
2869 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2870 assert(rscratch != noreg || always_reachable(src), "missing");
2871
2872 if (reachable(src)) {
2873 Assembler::movss(dst, as_Address(src));
2874 } else {
2875 lea(rscratch, src);
2876 Assembler::movss(dst, Address(rscratch, 0));
2877 }
2878 }
2879
2880 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2881 assert(rscratch != noreg || always_reachable(src), "missing");
2882
2883 if (reachable(src)) {
2884 Assembler::movddup(dst, as_Address(src));
2885 } else {
2886 lea(rscratch, src);
2887 Assembler::movddup(dst, Address(rscratch, 0));
2888 }
2889 }
2890
2891 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2892 assert(rscratch != noreg || always_reachable(src), "missing");
2893
2894 if (reachable(src)) {
2895 Assembler::vmovddup(dst, as_Address(src), vector_len);
2896 } else {
2897 lea(rscratch, src);
2898 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2899 }
2900 }
2901
2902 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2903 assert(rscratch != noreg || always_reachable(src), "missing");
2904
2905 if (reachable(src)) {
2906 Assembler::mulsd(dst, as_Address(src));
2907 } else {
2908 lea(rscratch, src);
2909 Assembler::mulsd(dst, Address(rscratch, 0));
2910 }
2911 }
2912
2913 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2914 assert(rscratch != noreg || always_reachable(src), "missing");
2915
2916 if (reachable(src)) {
2917 Assembler::mulss(dst, as_Address(src));
2918 } else {
2919 lea(rscratch, src);
2920 Assembler::mulss(dst, Address(rscratch, 0));
2921 }
2922 }
2923
2924 void MacroAssembler::null_check(Register reg, int offset) {
2925 if (needs_explicit_null_check(offset)) {
2926 // provoke OS null exception if reg is null by
2927 // accessing M[reg] w/o changing any (non-CC) registers
2928 // NOTE: cmpl is plenty here to provoke a segv
2929 cmpptr(rax, Address(reg, 0));
2930 // Note: should probably use testl(rax, Address(reg, 0));
2931 // may be shorter code (however, this version of
2932 // testl needs to be implemented first)
2933 } else {
2934 // nothing to do, (later) access of M[reg + offset]
2935 // will provoke OS null exception if reg is null
2936 }
2937 }
2938
2939 void MacroAssembler::os_breakpoint() {
2940 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2941 // (e.g., MSVC can't call ps() otherwise)
2942 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2943 }
2944
2945 void MacroAssembler::unimplemented(const char* what) {
2946 const char* buf = nullptr;
2947 {
2948 ResourceMark rm;
2949 stringStream ss;
2950 ss.print("unimplemented: %s", what);
2951 buf = code_string(ss.as_string());
2952 }
2953 stop(buf);
2954 }
2955
2956 #ifdef _LP64
2957 #define XSTATE_BV 0x200
2958 #endif
2959
2960 void MacroAssembler::pop_CPU_state() {
2961 pop_FPU_state();
2962 pop_IU_state();
2963 }
2964
2965 void MacroAssembler::pop_FPU_state() {
2966 #ifndef _LP64
2967 frstor(Address(rsp, 0));
2968 #else
2969 fxrstor(Address(rsp, 0));
2970 #endif
2971 addptr(rsp, FPUStateSizeInWords * wordSize);
2972 }
2973
2974 void MacroAssembler::pop_IU_state() {
2975 popa();
2976 LP64_ONLY(addq(rsp, 8));
2977 popf();
2978 }
2979
2980 // Save Integer and Float state
2981 // Warning: Stack must be 16 byte aligned (64bit)
2982 void MacroAssembler::push_CPU_state() {
2983 push_IU_state();
2984 push_FPU_state();
2985 }
2986
2987 void MacroAssembler::push_FPU_state() {
2988 subptr(rsp, FPUStateSizeInWords * wordSize);
2989 #ifndef _LP64
2990 fnsave(Address(rsp, 0));
2991 fwait();
2992 #else
2993 fxsave(Address(rsp, 0));
2994 #endif // LP64
2995 }
2996
2997 void MacroAssembler::push_IU_state() {
2998 // Push flags first because pusha kills them
2999 pushf();
3000 // Make sure rsp stays 16-byte aligned
3001 LP64_ONLY(subq(rsp, 8));
3002 pusha();
3003 }
3004
3005 void MacroAssembler::push_cont_fastpath() {
3006 if (!Continuations::enabled()) return;
3007
3008 #ifndef _LP64
3009 Register rthread = rax;
3010 Register rrealsp = rbx;
3011 push(rthread);
3012 push(rrealsp);
3013
3014 get_thread(rthread);
3015
3016 // The code below wants the original RSP.
3017 // Move it back after the pushes above.
3018 movptr(rrealsp, rsp);
3019 addptr(rrealsp, 2*wordSize);
3020 #else
3021 Register rthread = r15_thread;
3022 Register rrealsp = rsp;
3023 #endif
3024
3025 Label done;
3026 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3027 jccb(Assembler::belowEqual, done);
3028 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), rrealsp);
3029 bind(done);
3030
3031 #ifndef _LP64
3032 pop(rrealsp);
3033 pop(rthread);
3034 #endif
3035 }
3036
3037 void MacroAssembler::pop_cont_fastpath() {
3038 if (!Continuations::enabled()) return;
3039
3040 #ifndef _LP64
3041 Register rthread = rax;
3042 Register rrealsp = rbx;
3043 push(rthread);
3044 push(rrealsp);
3045
3046 get_thread(rthread);
3047
3048 // The code below wants the original RSP.
3049 // Move it back after the pushes above.
3050 movptr(rrealsp, rsp);
3051 addptr(rrealsp, 2*wordSize);
3052 #else
3053 Register rthread = r15_thread;
3054 Register rrealsp = rsp;
3055 #endif
3056
3057 Label done;
3058 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3059 jccb(Assembler::below, done);
3060 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), 0);
3061 bind(done);
3062
3063 #ifndef _LP64
3064 pop(rrealsp);
3065 pop(rthread);
3066 #endif
3067 }
3068
3069 void MacroAssembler::inc_held_monitor_count() {
3070 #ifdef _LP64
3071 incrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3072 #endif
3073 }
3074
3075 void MacroAssembler::dec_held_monitor_count() {
3076 #ifdef _LP64
3077 decrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3078 #endif
3079 }
3080
3081 #ifdef ASSERT
3082 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
3083 #ifdef _LP64
3084 Label no_cont;
3085 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
3086 testl(cont, cont);
3087 jcc(Assembler::zero, no_cont);
3088 stop(name);
3089 bind(no_cont);
3090 #else
3091 Unimplemented();
3092 #endif
3093 }
3094 #endif
3095
3096 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3097 if (!java_thread->is_valid()) {
3098 java_thread = rdi;
3099 get_thread(java_thread);
3100 }
3101 // we must set sp to zero to clear frame
3102 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3103 // must clear fp, so that compiled frames are not confused; it is
3104 // possible that we need it only for debugging
3105 if (clear_fp) {
3106 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3107 }
3108 // Always clear the pc because it could have been set by make_walkable()
3109 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3110 vzeroupper();
3111 }
3112
3113 void MacroAssembler::restore_rax(Register tmp) {
3114 if (tmp == noreg) pop(rax);
3115 else if (tmp != rax) mov(rax, tmp);
3116 }
3117
3118 void MacroAssembler::round_to(Register reg, int modulus) {
3119 addptr(reg, modulus - 1);
3120 andptr(reg, -modulus);
3121 }
3122
3123 void MacroAssembler::save_rax(Register tmp) {
3124 if (tmp == noreg) push(rax);
3125 else if (tmp != rax) mov(tmp, rax);
3126 }
3127
3128 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
3129 if (at_return) {
3130 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
3131 // we may safely use rsp instead to perform the stack watermark check.
3132 cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
3133 jcc(Assembler::above, slow_path);
3134 return;
3135 }
3136 testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
3137 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3138 }
3139
3140 // Calls to C land
3141 //
3142 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3143 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3144 // has to be reset to 0. This is required to allow proper stack traversal.
3145 void MacroAssembler::set_last_Java_frame(Register java_thread,
3146 Register last_java_sp,
3147 Register last_java_fp,
3148 address last_java_pc,
3149 Register rscratch) {
3150 vzeroupper();
3151 // determine java_thread register
3152 if (!java_thread->is_valid()) {
3153 java_thread = rdi;
3154 get_thread(java_thread);
3155 }
3156 // determine last_java_sp register
3157 if (!last_java_sp->is_valid()) {
3158 last_java_sp = rsp;
3159 }
3160 // last_java_fp is optional
3161 if (last_java_fp->is_valid()) {
3162 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3163 }
3164 // last_java_pc is optional
3165 if (last_java_pc != nullptr) {
3166 Address java_pc(java_thread,
3167 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
3168 lea(java_pc, InternalAddress(last_java_pc), rscratch);
3169 }
3170 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3171 }
3172
3173 #ifdef _LP64
3174 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
3175 Register last_java_fp,
3176 Label &L,
3177 Register scratch) {
3178 lea(scratch, L);
3179 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
3180 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, nullptr, scratch);
3181 }
3182 #endif
3183
3184 void MacroAssembler::shlptr(Register dst, int imm8) {
3185 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3186 }
3187
3188 void MacroAssembler::shrptr(Register dst, int imm8) {
3189 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3190 }
3191
3192 void MacroAssembler::sign_extend_byte(Register reg) {
3193 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3194 movsbl(reg, reg); // movsxb
3195 } else {
3196 shll(reg, 24);
3197 sarl(reg, 24);
3198 }
3199 }
3200
3201 void MacroAssembler::sign_extend_short(Register reg) {
3202 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3203 movswl(reg, reg); // movsxw
3204 } else {
3205 shll(reg, 16);
3206 sarl(reg, 16);
3207 }
3208 }
3209
3210 void MacroAssembler::testl(Address dst, int32_t imm32) {
3211 if (imm32 >= 0 && is8bit(imm32)) {
3212 testb(dst, imm32);
3213 } else {
3214 Assembler::testl(dst, imm32);
3215 }
3216 }
3217
3218 void MacroAssembler::testl(Register dst, int32_t imm32) {
3219 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
3220 testb(dst, imm32);
3221 } else {
3222 Assembler::testl(dst, imm32);
3223 }
3224 }
3225
3226 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3227 assert(always_reachable(src), "Address should be reachable");
3228 testl(dst, as_Address(src));
3229 }
3230
3231 #ifdef _LP64
3232
3233 void MacroAssembler::testq(Address dst, int32_t imm32) {
3234 if (imm32 >= 0) {
3235 testl(dst, imm32);
3236 } else {
3237 Assembler::testq(dst, imm32);
3238 }
3239 }
3240
3241 void MacroAssembler::testq(Register dst, int32_t imm32) {
3242 if (imm32 >= 0) {
3243 testl(dst, imm32);
3244 } else {
3245 Assembler::testq(dst, imm32);
3246 }
3247 }
3248
3249 #endif
3250
3251 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3252 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3253 Assembler::pcmpeqb(dst, src);
3254 }
3255
3256 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3257 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3258 Assembler::pcmpeqw(dst, src);
3259 }
3260
3261 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3262 assert((dst->encoding() < 16),"XMM register should be 0-15");
3263 Assembler::pcmpestri(dst, src, imm8);
3264 }
3265
3266 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3267 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3268 Assembler::pcmpestri(dst, src, imm8);
3269 }
3270
3271 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3272 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3273 Assembler::pmovzxbw(dst, src);
3274 }
3275
3276 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3277 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3278 Assembler::pmovzxbw(dst, src);
3279 }
3280
3281 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3282 assert((src->encoding() < 16),"XMM register should be 0-15");
3283 Assembler::pmovmskb(dst, src);
3284 }
3285
3286 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3287 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3288 Assembler::ptest(dst, src);
3289 }
3290
3291 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3292 assert(rscratch != noreg || always_reachable(src), "missing");
3293
3294 if (reachable(src)) {
3295 Assembler::sqrtss(dst, as_Address(src));
3296 } else {
3297 lea(rscratch, src);
3298 Assembler::sqrtss(dst, Address(rscratch, 0));
3299 }
3300 }
3301
3302 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3303 assert(rscratch != noreg || always_reachable(src), "missing");
3304
3305 if (reachable(src)) {
3306 Assembler::subsd(dst, as_Address(src));
3307 } else {
3308 lea(rscratch, src);
3309 Assembler::subsd(dst, Address(rscratch, 0));
3310 }
3311 }
3312
3313 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
3314 assert(rscratch != noreg || always_reachable(src), "missing");
3315
3316 if (reachable(src)) {
3317 Assembler::roundsd(dst, as_Address(src), rmode);
3318 } else {
3319 lea(rscratch, src);
3320 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
3321 }
3322 }
3323
3324 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3325 assert(rscratch != noreg || always_reachable(src), "missing");
3326
3327 if (reachable(src)) {
3328 Assembler::subss(dst, as_Address(src));
3329 } else {
3330 lea(rscratch, src);
3331 Assembler::subss(dst, Address(rscratch, 0));
3332 }
3333 }
3334
3335 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3336 assert(rscratch != noreg || always_reachable(src), "missing");
3337
3338 if (reachable(src)) {
3339 Assembler::ucomisd(dst, as_Address(src));
3340 } else {
3341 lea(rscratch, src);
3342 Assembler::ucomisd(dst, Address(rscratch, 0));
3343 }
3344 }
3345
3346 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3347 assert(rscratch != noreg || always_reachable(src), "missing");
3348
3349 if (reachable(src)) {
3350 Assembler::ucomiss(dst, as_Address(src));
3351 } else {
3352 lea(rscratch, src);
3353 Assembler::ucomiss(dst, Address(rscratch, 0));
3354 }
3355 }
3356
3357 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3358 assert(rscratch != noreg || always_reachable(src), "missing");
3359
3360 // Used in sign-bit flipping with aligned address.
3361 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3362
3363 if (UseAVX > 2 &&
3364 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3365 (dst->encoding() >= 16)) {
3366 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
3367 } else if (reachable(src)) {
3368 Assembler::xorpd(dst, as_Address(src));
3369 } else {
3370 lea(rscratch, src);
3371 Assembler::xorpd(dst, Address(rscratch, 0));
3372 }
3373 }
3374
3375 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3376 if (UseAVX > 2 &&
3377 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3378 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
3379 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3380 } else {
3381 Assembler::xorpd(dst, src);
3382 }
3383 }
3384
3385 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3386 if (UseAVX > 2 &&
3387 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3388 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
3389 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3390 } else {
3391 Assembler::xorps(dst, src);
3392 }
3393 }
3394
3395 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
3396 assert(rscratch != noreg || always_reachable(src), "missing");
3397
3398 // Used in sign-bit flipping with aligned address.
3399 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3400
3401 if (UseAVX > 2 &&
3402 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3403 (dst->encoding() >= 16)) {
3404 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
3405 } else if (reachable(src)) {
3406 Assembler::xorps(dst, as_Address(src));
3407 } else {
3408 lea(rscratch, src);
3409 Assembler::xorps(dst, Address(rscratch, 0));
3410 }
3411 }
3412
3413 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
3414 assert(rscratch != noreg || always_reachable(src), "missing");
3415
3416 // Used in sign-bit flipping with aligned address.
3417 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3418 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3419 if (reachable(src)) {
3420 Assembler::pshufb(dst, as_Address(src));
3421 } else {
3422 lea(rscratch, src);
3423 Assembler::pshufb(dst, Address(rscratch, 0));
3424 }
3425 }
3426
3427 // AVX 3-operands instructions
3428
3429 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3430 assert(rscratch != noreg || always_reachable(src), "missing");
3431
3432 if (reachable(src)) {
3433 vaddsd(dst, nds, as_Address(src));
3434 } else {
3435 lea(rscratch, src);
3436 vaddsd(dst, nds, Address(rscratch, 0));
3437 }
3438 }
3439
3440 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3441 assert(rscratch != noreg || always_reachable(src), "missing");
3442
3443 if (reachable(src)) {
3444 vaddss(dst, nds, as_Address(src));
3445 } else {
3446 lea(rscratch, src);
3447 vaddss(dst, nds, Address(rscratch, 0));
3448 }
3449 }
3450
3451 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3452 assert(UseAVX > 0, "requires some form of AVX");
3453 assert(rscratch != noreg || always_reachable(src), "missing");
3454
3455 if (reachable(src)) {
3456 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3457 } else {
3458 lea(rscratch, src);
3459 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3460 }
3461 }
3462
3463 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3464 assert(UseAVX > 0, "requires some form of AVX");
3465 assert(rscratch != noreg || always_reachable(src), "missing");
3466
3467 if (reachable(src)) {
3468 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3469 } else {
3470 lea(rscratch, src);
3471 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3472 }
3473 }
3474
3475 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3476 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3477 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3478
3479 vandps(dst, nds, negate_field, vector_len, rscratch);
3480 }
3481
3482 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3483 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3484 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3485
3486 vandpd(dst, nds, negate_field, vector_len, rscratch);
3487 }
3488
3489 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3490 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3491 Assembler::vpaddb(dst, nds, src, vector_len);
3492 }
3493
3494 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3495 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3496 Assembler::vpaddb(dst, nds, src, vector_len);
3497 }
3498
3499 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3500 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3501 Assembler::vpaddw(dst, nds, src, vector_len);
3502 }
3503
3504 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3505 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3506 Assembler::vpaddw(dst, nds, src, vector_len);
3507 }
3508
3509 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3510 assert(rscratch != noreg || always_reachable(src), "missing");
3511
3512 if (reachable(src)) {
3513 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3514 } else {
3515 lea(rscratch, src);
3516 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
3517 }
3518 }
3519
3520 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3521 assert(rscratch != noreg || always_reachable(src), "missing");
3522
3523 if (reachable(src)) {
3524 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
3525 } else {
3526 lea(rscratch, src);
3527 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
3528 }
3529 }
3530
3531 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3532 assert(rscratch != noreg || always_reachable(src), "missing");
3533
3534 if (reachable(src)) {
3535 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
3536 } else {
3537 lea(rscratch, src);
3538 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
3539 }
3540 }
3541
3542 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3543 assert(rscratch != noreg || always_reachable(src), "missing");
3544
3545 if (reachable(src)) {
3546 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3547 } else {
3548 lea(rscratch, src);
3549 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3550 }
3551 }
3552
3553 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3554 assert(rscratch != noreg || always_reachable(src), "missing");
3555
3556 if (reachable(src)) {
3557 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3558 } else {
3559 lea(rscratch, src);
3560 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3561 }
3562 }
3563
3564 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3565 assert(rscratch != noreg || always_reachable(src), "missing");
3566
3567 if (reachable(src)) {
3568 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3569 } else {
3570 lea(rscratch, src);
3571 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3572 }
3573 }
3574
3575 // Vector float blend
3576 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3577 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3578 // WARN: Allow dst == (src1|src2), mask == scratch
3579 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3580 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3581 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3582 if (blend_emulation && scratch_available && dst_available) {
3583 if (compute_mask) {
3584 vpsrad(scratch, mask, 32, vector_len);
3585 mask = scratch;
3586 }
3587 if (dst == src1) {
3588 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3589 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3590 } else {
3591 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3592 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3593 }
3594 vpor(dst, dst, scratch, vector_len);
3595 } else {
3596 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3597 }
3598 }
3599
3600 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3601 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3602 // WARN: Allow dst == (src1|src2), mask == scratch
3603 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3604 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3605 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3606 if (blend_emulation && scratch_available && dst_available) {
3607 if (compute_mask) {
3608 vpxor(scratch, scratch, scratch, vector_len);
3609 vpcmpgtq(scratch, scratch, mask, vector_len);
3610 mask = scratch;
3611 }
3612 if (dst == src1) {
3613 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3614 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3615 } else {
3616 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3617 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3618 }
3619 vpor(dst, dst, scratch, vector_len);
3620 } else {
3621 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3622 }
3623 }
3624
3625 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3626 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3627 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3628 }
3629
3630 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3631 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3632 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3633 }
3634
3635 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3636 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3637 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3638 }
3639
3640 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3641 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3642 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3643 }
3644
3645 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3646 assert(rscratch != noreg || always_reachable(src), "missing");
3647
3648 if (reachable(src)) {
3649 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3650 } else {
3651 lea(rscratch, src);
3652 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3653 }
3654 }
3655
3656 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3657 int comparison, bool is_signed, int vector_len, Register rscratch) {
3658 assert(rscratch != noreg || always_reachable(src), "missing");
3659
3660 if (reachable(src)) {
3661 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3662 } else {
3663 lea(rscratch, src);
3664 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3665 }
3666 }
3667
3668 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3669 int comparison, bool is_signed, int vector_len, Register rscratch) {
3670 assert(rscratch != noreg || always_reachable(src), "missing");
3671
3672 if (reachable(src)) {
3673 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3674 } else {
3675 lea(rscratch, src);
3676 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3677 }
3678 }
3679
3680 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3681 int comparison, bool is_signed, int vector_len, Register rscratch) {
3682 assert(rscratch != noreg || always_reachable(src), "missing");
3683
3684 if (reachable(src)) {
3685 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3686 } else {
3687 lea(rscratch, src);
3688 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3689 }
3690 }
3691
3692 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3693 int comparison, bool is_signed, int vector_len, Register rscratch) {
3694 assert(rscratch != noreg || always_reachable(src), "missing");
3695
3696 if (reachable(src)) {
3697 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3698 } else {
3699 lea(rscratch, src);
3700 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3701 }
3702 }
3703
3704 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3705 if (width == Assembler::Q) {
3706 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3707 } else {
3708 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3709 }
3710 }
3711
3712 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3713 int eq_cond_enc = 0x29;
3714 int gt_cond_enc = 0x37;
3715 if (width != Assembler::Q) {
3716 eq_cond_enc = 0x74 + width;
3717 gt_cond_enc = 0x64 + width;
3718 }
3719 switch (cond) {
3720 case eq:
3721 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3722 break;
3723 case neq:
3724 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3725 vallones(xtmp, vector_len);
3726 vpxor(dst, xtmp, dst, vector_len);
3727 break;
3728 case le:
3729 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3730 vallones(xtmp, vector_len);
3731 vpxor(dst, xtmp, dst, vector_len);
3732 break;
3733 case nlt:
3734 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3735 vallones(xtmp, vector_len);
3736 vpxor(dst, xtmp, dst, vector_len);
3737 break;
3738 case lt:
3739 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3740 break;
3741 case nle:
3742 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3743 break;
3744 default:
3745 assert(false, "Should not reach here");
3746 }
3747 }
3748
3749 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3750 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3751 Assembler::vpmovzxbw(dst, src, vector_len);
3752 }
3753
3754 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3755 assert((src->encoding() < 16),"XMM register should be 0-15");
3756 Assembler::vpmovmskb(dst, src, vector_len);
3757 }
3758
3759 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3760 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3761 Assembler::vpmullw(dst, nds, src, vector_len);
3762 }
3763
3764 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3765 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3766 Assembler::vpmullw(dst, nds, src, vector_len);
3767 }
3768
3769 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3770 assert((UseAVX > 0), "AVX support is needed");
3771 assert(rscratch != noreg || always_reachable(src), "missing");
3772
3773 if (reachable(src)) {
3774 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3775 } else {
3776 lea(rscratch, src);
3777 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3778 }
3779 }
3780
3781 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3782 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3783 Assembler::vpsubb(dst, nds, src, vector_len);
3784 }
3785
3786 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3787 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3788 Assembler::vpsubb(dst, nds, src, vector_len);
3789 }
3790
3791 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3792 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3793 Assembler::vpsubw(dst, nds, src, vector_len);
3794 }
3795
3796 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3797 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3798 Assembler::vpsubw(dst, nds, src, vector_len);
3799 }
3800
3801 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3802 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3803 Assembler::vpsraw(dst, nds, shift, vector_len);
3804 }
3805
3806 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3807 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3808 Assembler::vpsraw(dst, nds, shift, vector_len);
3809 }
3810
3811 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3812 assert(UseAVX > 2,"");
3813 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3814 vector_len = 2;
3815 }
3816 Assembler::evpsraq(dst, nds, shift, vector_len);
3817 }
3818
3819 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3820 assert(UseAVX > 2,"");
3821 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3822 vector_len = 2;
3823 }
3824 Assembler::evpsraq(dst, nds, shift, vector_len);
3825 }
3826
3827 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3828 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3829 Assembler::vpsrlw(dst, nds, shift, vector_len);
3830 }
3831
3832 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3833 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3834 Assembler::vpsrlw(dst, nds, shift, vector_len);
3835 }
3836
3837 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3838 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3839 Assembler::vpsllw(dst, nds, shift, vector_len);
3840 }
3841
3842 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3843 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3844 Assembler::vpsllw(dst, nds, shift, vector_len);
3845 }
3846
3847 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3848 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3849 Assembler::vptest(dst, src);
3850 }
3851
3852 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3853 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3854 Assembler::punpcklbw(dst, src);
3855 }
3856
3857 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3858 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3859 Assembler::pshufd(dst, src, mode);
3860 }
3861
3862 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3863 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3864 Assembler::pshuflw(dst, src, mode);
3865 }
3866
3867 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3868 assert(rscratch != noreg || always_reachable(src), "missing");
3869
3870 if (reachable(src)) {
3871 vandpd(dst, nds, as_Address(src), vector_len);
3872 } else {
3873 lea(rscratch, src);
3874 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3875 }
3876 }
3877
3878 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3879 assert(rscratch != noreg || always_reachable(src), "missing");
3880
3881 if (reachable(src)) {
3882 vandps(dst, nds, as_Address(src), vector_len);
3883 } else {
3884 lea(rscratch, src);
3885 vandps(dst, nds, Address(rscratch, 0), vector_len);
3886 }
3887 }
3888
3889 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3890 bool merge, int vector_len, Register rscratch) {
3891 assert(rscratch != noreg || always_reachable(src), "missing");
3892
3893 if (reachable(src)) {
3894 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3895 } else {
3896 lea(rscratch, src);
3897 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3898 }
3899 }
3900
3901 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3902 assert(rscratch != noreg || always_reachable(src), "missing");
3903
3904 if (reachable(src)) {
3905 vdivsd(dst, nds, as_Address(src));
3906 } else {
3907 lea(rscratch, src);
3908 vdivsd(dst, nds, Address(rscratch, 0));
3909 }
3910 }
3911
3912 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3913 assert(rscratch != noreg || always_reachable(src), "missing");
3914
3915 if (reachable(src)) {
3916 vdivss(dst, nds, as_Address(src));
3917 } else {
3918 lea(rscratch, src);
3919 vdivss(dst, nds, Address(rscratch, 0));
3920 }
3921 }
3922
3923 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3924 assert(rscratch != noreg || always_reachable(src), "missing");
3925
3926 if (reachable(src)) {
3927 vmulsd(dst, nds, as_Address(src));
3928 } else {
3929 lea(rscratch, src);
3930 vmulsd(dst, nds, Address(rscratch, 0));
3931 }
3932 }
3933
3934 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3935 assert(rscratch != noreg || always_reachable(src), "missing");
3936
3937 if (reachable(src)) {
3938 vmulss(dst, nds, as_Address(src));
3939 } else {
3940 lea(rscratch, src);
3941 vmulss(dst, nds, Address(rscratch, 0));
3942 }
3943 }
3944
3945 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3946 assert(rscratch != noreg || always_reachable(src), "missing");
3947
3948 if (reachable(src)) {
3949 vsubsd(dst, nds, as_Address(src));
3950 } else {
3951 lea(rscratch, src);
3952 vsubsd(dst, nds, Address(rscratch, 0));
3953 }
3954 }
3955
3956 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3957 assert(rscratch != noreg || always_reachable(src), "missing");
3958
3959 if (reachable(src)) {
3960 vsubss(dst, nds, as_Address(src));
3961 } else {
3962 lea(rscratch, src);
3963 vsubss(dst, nds, Address(rscratch, 0));
3964 }
3965 }
3966
3967 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3968 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3969 assert(rscratch != noreg || always_reachable(src), "missing");
3970
3971 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3972 }
3973
3974 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3975 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3976 assert(rscratch != noreg || always_reachable(src), "missing");
3977
3978 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3979 }
3980
3981 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3982 assert(rscratch != noreg || always_reachable(src), "missing");
3983
3984 if (reachable(src)) {
3985 vxorpd(dst, nds, as_Address(src), vector_len);
3986 } else {
3987 lea(rscratch, src);
3988 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3989 }
3990 }
3991
3992 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3993 assert(rscratch != noreg || always_reachable(src), "missing");
3994
3995 if (reachable(src)) {
3996 vxorps(dst, nds, as_Address(src), vector_len);
3997 } else {
3998 lea(rscratch, src);
3999 vxorps(dst, nds, Address(rscratch, 0), vector_len);
4000 }
4001 }
4002
4003 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
4004 assert(rscratch != noreg || always_reachable(src), "missing");
4005
4006 if (UseAVX > 1 || (vector_len < 1)) {
4007 if (reachable(src)) {
4008 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
4009 } else {
4010 lea(rscratch, src);
4011 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
4012 }
4013 } else {
4014 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
4015 }
4016 }
4017
4018 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
4019 assert(rscratch != noreg || always_reachable(src), "missing");
4020
4021 if (reachable(src)) {
4022 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
4023 } else {
4024 lea(rscratch, src);
4025 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
4026 }
4027 }
4028
4029 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
4030 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
4031 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
4032 // The inverted mask is sign-extended
4033 andptr(possibly_non_local, inverted_mask);
4034 }
4035
4036 void MacroAssembler::resolve_jobject(Register value,
4037 Register thread,
4038 Register tmp) {
4039 assert_different_registers(value, thread, tmp);
4040 Label done, tagged, weak_tagged;
4041 testptr(value, value);
4042 jcc(Assembler::zero, done); // Use null as-is.
4043 testptr(value, JNIHandles::tag_mask); // Test for tag.
4044 jcc(Assembler::notZero, tagged);
4045
4046 // Resolve local handle
4047 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp, thread);
4048 verify_oop(value);
4049 jmp(done);
4050
4051 bind(tagged);
4052 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
4053 jcc(Assembler::notZero, weak_tagged);
4054
4055 // Resolve global handle
4056 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4057 verify_oop(value);
4058 jmp(done);
4059
4060 bind(weak_tagged);
4061 // Resolve jweak.
4062 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4063 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp, thread);
4064 verify_oop(value);
4065
4066 bind(done);
4067 }
4068
4069 void MacroAssembler::resolve_global_jobject(Register value,
4070 Register thread,
4071 Register tmp) {
4072 assert_different_registers(value, thread, tmp);
4073 Label done;
4074
4075 testptr(value, value);
4076 jcc(Assembler::zero, done); // Use null as-is.
4077
4078 #ifdef ASSERT
4079 {
4080 Label valid_global_tag;
4081 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
4082 jcc(Assembler::notZero, valid_global_tag);
4083 stop("non global jobject using resolve_global_jobject");
4084 bind(valid_global_tag);
4085 }
4086 #endif
4087
4088 // Resolve global handle
4089 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4090 verify_oop(value);
4091
4092 bind(done);
4093 }
4094
4095 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4096 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4097 }
4098
4099 // Force generation of a 4 byte immediate value even if it fits into 8bit
4100 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4101 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4102 }
4103
4104 void MacroAssembler::subptr(Register dst, Register src) {
4105 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4106 }
4107
4108 // C++ bool manipulation
4109 void MacroAssembler::testbool(Register dst) {
4110 if(sizeof(bool) == 1)
4111 testb(dst, 0xff);
4112 else if(sizeof(bool) == 2) {
4113 // testw implementation needed for two byte bools
4114 ShouldNotReachHere();
4115 } else if(sizeof(bool) == 4)
4116 testl(dst, dst);
4117 else
4118 // unsupported
4119 ShouldNotReachHere();
4120 }
4121
4122 void MacroAssembler::testptr(Register dst, Register src) {
4123 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4124 }
4125
4126 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4127 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4128 Register var_size_in_bytes,
4129 int con_size_in_bytes,
4130 Register t1,
4131 Register t2,
4132 Label& slow_case) {
4133 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4134 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4135 }
4136
4137 RegSet MacroAssembler::call_clobbered_gp_registers() {
4138 RegSet regs;
4139 #ifdef _LP64
4140 regs += RegSet::of(rax, rcx, rdx);
4141 #ifndef _WINDOWS
4142 regs += RegSet::of(rsi, rdi);
4143 #endif
4144 regs += RegSet::range(r8, r11);
4145 #else
4146 regs += RegSet::of(rax, rcx, rdx);
4147 #endif
4148 #ifdef _LP64
4149 if (UseAPX) {
4150 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
4151 }
4152 #endif
4153 return regs;
4154 }
4155
4156 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
4157 int num_xmm_registers = XMMRegister::available_xmm_registers();
4158 #if defined(_WINDOWS)
4159 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
4160 if (num_xmm_registers > 16) {
4161 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
4162 }
4163 return result;
4164 #else
4165 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
4166 #endif
4167 }
4168
4169 static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor
4170
4171 #ifndef _LP64
4172 static bool use_x87_registers() { return UseSSE < 2; }
4173 #endif
4174 static bool use_xmm_registers() { return UseSSE >= 1; }
4175
4176 // C1 only ever uses the first double/float of the XMM register.
4177 static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); }
4178
4179 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4180 if (UseSSE == 1) {
4181 masm->movflt(Address(rsp, offset), reg);
4182 } else {
4183 masm->movdbl(Address(rsp, offset), reg);
4184 }
4185 }
4186
4187 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4188 if (UseSSE == 1) {
4189 masm->movflt(reg, Address(rsp, offset));
4190 } else {
4191 masm->movdbl(reg, Address(rsp, offset));
4192 }
4193 }
4194
4195 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
4196 bool save_fpu, int& gp_area_size,
4197 int& fp_area_size, int& xmm_area_size) {
4198
4199 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
4200 StackAlignmentInBytes);
4201 #ifdef _LP64
4202 fp_area_size = 0;
4203 #else
4204 fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0;
4205 #endif
4206 xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0;
4207
4208 return gp_area_size + fp_area_size + xmm_area_size;
4209 }
4210
4211 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
4212 block_comment("push_call_clobbered_registers start");
4213 // Regular registers
4214 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
4215
4216 int gp_area_size;
4217 int fp_area_size;
4218 int xmm_area_size;
4219 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
4220 gp_area_size, fp_area_size, xmm_area_size);
4221 subptr(rsp, total_save_size);
4222
4223 push_set(gp_registers_to_push, 0);
4224
4225 #ifndef _LP64
4226 if (save_fpu && use_x87_registers()) {
4227 fnsave(Address(rsp, gp_area_size));
4228 fwait();
4229 }
4230 #endif
4231 if (save_fpu && use_xmm_registers()) {
4232 push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4233 }
4234
4235 block_comment("push_call_clobbered_registers end");
4236 }
4237
4238 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
4239 block_comment("pop_call_clobbered_registers start");
4240
4241 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
4242
4243 int gp_area_size;
4244 int fp_area_size;
4245 int xmm_area_size;
4246 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
4247 gp_area_size, fp_area_size, xmm_area_size);
4248
4249 if (restore_fpu && use_xmm_registers()) {
4250 pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4251 }
4252 #ifndef _LP64
4253 if (restore_fpu && use_x87_registers()) {
4254 frstor(Address(rsp, gp_area_size));
4255 }
4256 #endif
4257
4258 pop_set(gp_registers_to_pop, 0);
4259
4260 addptr(rsp, total_save_size);
4261
4262 vzeroupper();
4263
4264 block_comment("pop_call_clobbered_registers end");
4265 }
4266
4267 void MacroAssembler::push_set(XMMRegSet set, int offset) {
4268 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
4269 int spill_offset = offset;
4270
4271 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
4272 save_xmm_register(this, spill_offset, *it);
4273 spill_offset += xmm_save_size();
4274 }
4275 }
4276
4277 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
4278 int restore_size = set.size() * xmm_save_size();
4279 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
4280
4281 int restore_offset = offset + restore_size - xmm_save_size();
4282
4283 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
4284 restore_xmm_register(this, restore_offset, *it);
4285 restore_offset -= xmm_save_size();
4286 }
4287 }
4288
4289 void MacroAssembler::push_set(RegSet set, int offset) {
4290 int spill_offset;
4291 if (offset == -1) {
4292 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4293 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4294 subptr(rsp, aligned_size);
4295 spill_offset = 0;
4296 } else {
4297 spill_offset = offset;
4298 }
4299
4300 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
4301 movptr(Address(rsp, spill_offset), *it);
4302 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4303 }
4304 }
4305
4306 void MacroAssembler::pop_set(RegSet set, int offset) {
4307
4308 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4309 int restore_size = set.size() * gp_reg_size;
4310 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
4311
4312 int restore_offset;
4313 if (offset == -1) {
4314 restore_offset = restore_size - gp_reg_size;
4315 } else {
4316 restore_offset = offset + restore_size - gp_reg_size;
4317 }
4318 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
4319 movptr(*it, Address(rsp, restore_offset));
4320 restore_offset -= gp_reg_size;
4321 }
4322
4323 if (offset == -1) {
4324 addptr(rsp, aligned_size);
4325 }
4326 }
4327
4328 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4329 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4330 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4331 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4332 Label done;
4333
4334 testptr(length_in_bytes, length_in_bytes);
4335 jcc(Assembler::zero, done);
4336
4337 // initialize topmost word, divide index by 2, check if odd and test if zero
4338 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4339 #ifdef ASSERT
4340 {
4341 Label L;
4342 testptr(length_in_bytes, BytesPerWord - 1);
4343 jcc(Assembler::zero, L);
4344 stop("length must be a multiple of BytesPerWord");
4345 bind(L);
4346 }
4347 #endif
4348 Register index = length_in_bytes;
4349 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4350 if (UseIncDec) {
4351 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4352 } else {
4353 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4354 shrptr(index, 1);
4355 }
4356 #ifndef _LP64
4357 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4358 {
4359 Label even;
4360 // note: if index was a multiple of 8, then it cannot
4361 // be 0 now otherwise it must have been 0 before
4362 // => if it is even, we don't need to check for 0 again
4363 jcc(Assembler::carryClear, even);
4364 // clear topmost word (no jump would be needed if conditional assignment worked here)
4365 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4366 // index could be 0 now, must check again
4367 jcc(Assembler::zero, done);
4368 bind(even);
4369 }
4370 #endif // !_LP64
4371 // initialize remaining object fields: index is a multiple of 2 now
4372 {
4373 Label loop;
4374 bind(loop);
4375 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4376 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4377 decrement(index);
4378 jcc(Assembler::notZero, loop);
4379 }
4380
4381 bind(done);
4382 }
4383
4384 // Look up the method for a megamorphic invokeinterface call.
4385 // The target method is determined by <intf_klass, itable_index>.
4386 // The receiver klass is in recv_klass.
4387 // On success, the result will be in method_result, and execution falls through.
4388 // On failure, execution transfers to the given label.
4389 void MacroAssembler::lookup_interface_method(Register recv_klass,
4390 Register intf_klass,
4391 RegisterOrConstant itable_index,
4392 Register method_result,
4393 Register scan_temp,
4394 Label& L_no_such_interface,
4395 bool return_method) {
4396 assert_different_registers(recv_klass, intf_klass, scan_temp);
4397 assert_different_registers(method_result, intf_klass, scan_temp);
4398 assert(recv_klass != method_result || !return_method,
4399 "recv_klass can be destroyed when method isn't needed");
4400
4401 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4402 "caller must use same register for non-constant itable index as for method");
4403
4404 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4405 int vtable_base = in_bytes(Klass::vtable_start_offset());
4406 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4407 int scan_step = itableOffsetEntry::size() * wordSize;
4408 int vte_size = vtableEntry::size_in_bytes();
4409 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4410 assert(vte_size == wordSize, "else adjust times_vte_scale");
4411
4412 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4413
4414 // Could store the aligned, prescaled offset in the klass.
4415 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4416
4417 if (return_method) {
4418 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4419 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4420 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4421 }
4422
4423 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
4424 // if (scan->interface() == intf) {
4425 // result = (klass + scan->offset() + itable_index);
4426 // }
4427 // }
4428 Label search, found_method;
4429
4430 for (int peel = 1; peel >= 0; peel--) {
4431 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
4432 cmpptr(intf_klass, method_result);
4433
4434 if (peel) {
4435 jccb(Assembler::equal, found_method);
4436 } else {
4437 jccb(Assembler::notEqual, search);
4438 // (invert the test to fall through to found_method...)
4439 }
4440
4441 if (!peel) break;
4442
4443 bind(search);
4444
4445 // Check that the previous entry is non-null. A null entry means that
4446 // the receiver class doesn't implement the interface, and wasn't the
4447 // same as when the caller was compiled.
4448 testptr(method_result, method_result);
4449 jcc(Assembler::zero, L_no_such_interface);
4450 addptr(scan_temp, scan_step);
4451 }
4452
4453 bind(found_method);
4454
4455 if (return_method) {
4456 // Got a hit.
4457 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
4458 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4459 }
4460 }
4461
4462 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
4463 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
4464 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
4465 // The target method is determined by <holder_klass, itable_index>.
4466 // The receiver klass is in recv_klass.
4467 // On success, the result will be in method_result, and execution falls through.
4468 // On failure, execution transfers to the given label.
4469 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
4470 Register holder_klass,
4471 Register resolved_klass,
4472 Register method_result,
4473 Register scan_temp,
4474 Register temp_reg2,
4475 Register receiver,
4476 int itable_index,
4477 Label& L_no_such_interface) {
4478 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
4479 Register temp_itbl_klass = method_result;
4480 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
4481
4482 int vtable_base = in_bytes(Klass::vtable_start_offset());
4483 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4484 int scan_step = itableOffsetEntry::size() * wordSize;
4485 int vte_size = vtableEntry::size_in_bytes();
4486 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
4487 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
4488 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4489 assert(vte_size == wordSize, "adjust times_vte_scale");
4490
4491 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
4492
4493 // temp_itbl_klass = recv_klass.itable[0]
4494 // scan_temp = &recv_klass.itable[0] + step
4495 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4496 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
4497 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
4498 xorptr(temp_reg, temp_reg);
4499
4500 // Initial checks:
4501 // - if (holder_klass != resolved_klass), go to "scan for resolved"
4502 // - if (itable[0] == 0), no such interface
4503 // - if (itable[0] == holder_klass), shortcut to "holder found"
4504 cmpptr(holder_klass, resolved_klass);
4505 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
4506 testptr(temp_itbl_klass, temp_itbl_klass);
4507 jccb(Assembler::zero, L_no_such_interface);
4508 cmpptr(holder_klass, temp_itbl_klass);
4509 jccb(Assembler::equal, L_holder_found);
4510
4511 // Loop: Look for holder_klass record in itable
4512 // do {
4513 // tmp = itable[index];
4514 // index += step;
4515 // if (tmp == holder_klass) {
4516 // goto L_holder_found; // Found!
4517 // }
4518 // } while (tmp != 0);
4519 // goto L_no_such_interface // Not found.
4520 Label L_scan_holder;
4521 bind(L_scan_holder);
4522 movptr(temp_itbl_klass, Address(scan_temp, 0));
4523 addptr(scan_temp, scan_step);
4524 cmpptr(holder_klass, temp_itbl_klass);
4525 jccb(Assembler::equal, L_holder_found);
4526 testptr(temp_itbl_klass, temp_itbl_klass);
4527 jccb(Assembler::notZero, L_scan_holder);
4528
4529 jmpb(L_no_such_interface);
4530
4531 // Loop: Look for resolved_class record in itable
4532 // do {
4533 // tmp = itable[index];
4534 // index += step;
4535 // if (tmp == holder_klass) {
4536 // // Also check if we have met a holder klass
4537 // holder_tmp = itable[index-step-ioffset];
4538 // }
4539 // if (tmp == resolved_klass) {
4540 // goto L_resolved_found; // Found!
4541 // }
4542 // } while (tmp != 0);
4543 // goto L_no_such_interface // Not found.
4544 //
4545 Label L_loop_scan_resolved;
4546 bind(L_loop_scan_resolved);
4547 movptr(temp_itbl_klass, Address(scan_temp, 0));
4548 addptr(scan_temp, scan_step);
4549 bind(L_loop_scan_resolved_entry);
4550 cmpptr(holder_klass, temp_itbl_klass);
4551 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4552 cmpptr(resolved_klass, temp_itbl_klass);
4553 jccb(Assembler::equal, L_resolved_found);
4554 testptr(temp_itbl_klass, temp_itbl_klass);
4555 jccb(Assembler::notZero, L_loop_scan_resolved);
4556
4557 jmpb(L_no_such_interface);
4558
4559 Label L_ready;
4560
4561 // See if we already have a holder klass. If not, go and scan for it.
4562 bind(L_resolved_found);
4563 testptr(temp_reg, temp_reg);
4564 jccb(Assembler::zero, L_scan_holder);
4565 jmpb(L_ready);
4566
4567 bind(L_holder_found);
4568 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4569
4570 // Finally, temp_reg contains holder_klass vtable offset
4571 bind(L_ready);
4572 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4573 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4574 load_klass(scan_temp, receiver, noreg);
4575 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4576 } else {
4577 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4578 }
4579 }
4580
4581
4582 // virtual method calling
4583 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4584 RegisterOrConstant vtable_index,
4585 Register method_result) {
4586 const ByteSize base = Klass::vtable_start_offset();
4587 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4588 Address vtable_entry_addr(recv_klass,
4589 vtable_index, Address::times_ptr,
4590 base + vtableEntry::method_offset());
4591 movptr(method_result, vtable_entry_addr);
4592 }
4593
4594
4595 void MacroAssembler::check_klass_subtype(Register sub_klass,
4596 Register super_klass,
4597 Register temp_reg,
4598 Label& L_success) {
4599 Label L_failure;
4600 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4601 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4602 bind(L_failure);
4603 }
4604
4605
4606 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4607 Register super_klass,
4608 Register temp_reg,
4609 Label* L_success,
4610 Label* L_failure,
4611 Label* L_slow_path,
4612 RegisterOrConstant super_check_offset) {
4613 assert_different_registers(sub_klass, super_klass, temp_reg);
4614 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4615 if (super_check_offset.is_register()) {
4616 assert_different_registers(sub_klass, super_klass,
4617 super_check_offset.as_register());
4618 } else if (must_load_sco) {
4619 assert(temp_reg != noreg, "supply either a temp or a register offset");
4620 }
4621
4622 Label L_fallthrough;
4623 int label_nulls = 0;
4624 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4625 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4626 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4627 assert(label_nulls <= 1, "at most one null in the batch");
4628
4629 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4630 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4631 Address super_check_offset_addr(super_klass, sco_offset);
4632
4633 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4634 // range of a jccb. If this routine grows larger, reconsider at
4635 // least some of these.
4636 #define local_jcc(assembler_cond, label) \
4637 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4638 else jcc( assembler_cond, label) /*omit semi*/
4639
4640 // Hacked jmp, which may only be used just before L_fallthrough.
4641 #define final_jmp(label) \
4642 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4643 else jmp(label) /*omit semi*/
4644
4645 // If the pointers are equal, we are done (e.g., String[] elements).
4646 // This self-check enables sharing of secondary supertype arrays among
4647 // non-primary types such as array-of-interface. Otherwise, each such
4648 // type would need its own customized SSA.
4649 // We move this check to the front of the fast path because many
4650 // type checks are in fact trivially successful in this manner,
4651 // so we get a nicely predicted branch right at the start of the check.
4652 cmpptr(sub_klass, super_klass);
4653 local_jcc(Assembler::equal, *L_success);
4654
4655 // Check the supertype display:
4656 if (must_load_sco) {
4657 // Positive movl does right thing on LP64.
4658 movl(temp_reg, super_check_offset_addr);
4659 super_check_offset = RegisterOrConstant(temp_reg);
4660 }
4661 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4662 cmpptr(super_klass, super_check_addr); // load displayed supertype
4663
4664 // This check has worked decisively for primary supers.
4665 // Secondary supers are sought in the super_cache ('super_cache_addr').
4666 // (Secondary supers are interfaces and very deeply nested subtypes.)
4667 // This works in the same check above because of a tricky aliasing
4668 // between the super_cache and the primary super display elements.
4669 // (The 'super_check_addr' can address either, as the case requires.)
4670 // Note that the cache is updated below if it does not help us find
4671 // what we need immediately.
4672 // So if it was a primary super, we can just fail immediately.
4673 // Otherwise, it's the slow path for us (no success at this point).
4674
4675 if (super_check_offset.is_register()) {
4676 local_jcc(Assembler::equal, *L_success);
4677 cmpl(super_check_offset.as_register(), sc_offset);
4678 if (L_failure == &L_fallthrough) {
4679 local_jcc(Assembler::equal, *L_slow_path);
4680 } else {
4681 local_jcc(Assembler::notEqual, *L_failure);
4682 final_jmp(*L_slow_path);
4683 }
4684 } else if (super_check_offset.as_constant() == sc_offset) {
4685 // Need a slow path; fast failure is impossible.
4686 if (L_slow_path == &L_fallthrough) {
4687 local_jcc(Assembler::equal, *L_success);
4688 } else {
4689 local_jcc(Assembler::notEqual, *L_slow_path);
4690 final_jmp(*L_success);
4691 }
4692 } else {
4693 // No slow path; it's a fast decision.
4694 if (L_failure == &L_fallthrough) {
4695 local_jcc(Assembler::equal, *L_success);
4696 } else {
4697 local_jcc(Assembler::notEqual, *L_failure);
4698 final_jmp(*L_success);
4699 }
4700 }
4701
4702 bind(L_fallthrough);
4703
4704 #undef local_jcc
4705 #undef final_jmp
4706 }
4707
4708
4709 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4710 Register super_klass,
4711 Register temp_reg,
4712 Register temp2_reg,
4713 Label* L_success,
4714 Label* L_failure,
4715 bool set_cond_codes) {
4716 assert_different_registers(sub_klass, super_klass, temp_reg);
4717 if (temp2_reg != noreg)
4718 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4719 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4720
4721 Label L_fallthrough;
4722 int label_nulls = 0;
4723 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4724 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4725 assert(label_nulls <= 1, "at most one null in the batch");
4726
4727 // a couple of useful fields in sub_klass:
4728 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4729 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4730 Address secondary_supers_addr(sub_klass, ss_offset);
4731 Address super_cache_addr( sub_klass, sc_offset);
4732
4733 // Do a linear scan of the secondary super-klass chain.
4734 // This code is rarely used, so simplicity is a virtue here.
4735 // The repne_scan instruction uses fixed registers, which we must spill.
4736 // Don't worry too much about pre-existing connections with the input regs.
4737
4738 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4739 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4740
4741 // Get super_klass value into rax (even if it was in rdi or rcx).
4742 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4743 if (super_klass != rax) {
4744 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4745 mov(rax, super_klass);
4746 }
4747 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4748 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4749
4750 #ifndef PRODUCT
4751 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4752 ExternalAddress pst_counter_addr((address) pst_counter);
4753 NOT_LP64( incrementl(pst_counter_addr) );
4754 LP64_ONLY( lea(rcx, pst_counter_addr) );
4755 LP64_ONLY( incrementl(Address(rcx, 0)) );
4756 #endif //PRODUCT
4757
4758 // We will consult the secondary-super array.
4759 movptr(rdi, secondary_supers_addr);
4760 // Load the array length. (Positive movl does right thing on LP64.)
4761 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4762 // Skip to start of data.
4763 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4764
4765 // Scan RCX words at [RDI] for an occurrence of RAX.
4766 // Set NZ/Z based on last compare.
4767 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4768 // not change flags (only scas instruction which is repeated sets flags).
4769 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4770
4771 testptr(rax,rax); // Set Z = 0
4772 repne_scan();
4773
4774 // Unspill the temp. registers:
4775 if (pushed_rdi) pop(rdi);
4776 if (pushed_rcx) pop(rcx);
4777 if (pushed_rax) pop(rax);
4778
4779 if (set_cond_codes) {
4780 // Special hack for the AD files: rdi is guaranteed non-zero.
4781 assert(!pushed_rdi, "rdi must be left non-null");
4782 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4783 }
4784
4785 if (L_failure == &L_fallthrough)
4786 jccb(Assembler::notEqual, *L_failure);
4787 else jcc(Assembler::notEqual, *L_failure);
4788
4789 // Success. Cache the super we found and proceed in triumph.
4790 movptr(super_cache_addr, super_klass);
4791
4792 if (L_success != &L_fallthrough) {
4793 jmp(*L_success);
4794 }
4795
4796 #undef IS_A_TEMP
4797
4798 bind(L_fallthrough);
4799 }
4800
4801 #ifndef _LP64
4802
4803 // 32-bit x86 only: always use the linear search.
4804 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4805 Register super_klass,
4806 Register temp_reg,
4807 Register temp2_reg,
4808 Label* L_success,
4809 Label* L_failure,
4810 bool set_cond_codes) {
4811 check_klass_subtype_slow_path_linear
4812 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
4813 }
4814
4815 #else // _LP64
4816
4817 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4818 Register super_klass,
4819 Register temp_reg,
4820 Register temp2_reg,
4821 Label* L_success,
4822 Label* L_failure,
4823 bool set_cond_codes) {
4824 assert(set_cond_codes == false, "must be false on 64-bit x86");
4825 check_klass_subtype_slow_path
4826 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4827 L_success, L_failure);
4828 }
4829
4830 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4831 Register super_klass,
4832 Register temp_reg,
4833 Register temp2_reg,
4834 Register temp3_reg,
4835 Register temp4_reg,
4836 Label* L_success,
4837 Label* L_failure) {
4838 if (UseSecondarySupersTable) {
4839 check_klass_subtype_slow_path_table
4840 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4841 L_success, L_failure);
4842 } else {
4843 check_klass_subtype_slow_path_linear
4844 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4845 }
4846 }
4847
4848 Register MacroAssembler::allocate_if_noreg(Register r,
4849 RegSetIterator<Register> &available_regs,
4850 RegSet ®s_to_push) {
4851 if (!r->is_valid()) {
4852 r = *available_regs++;
4853 regs_to_push += r;
4854 }
4855 return r;
4856 }
4857
4858 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4859 Register super_klass,
4860 Register temp_reg,
4861 Register temp2_reg,
4862 Register temp3_reg,
4863 Register result_reg,
4864 Label* L_success,
4865 Label* L_failure) {
4866 // NB! Callers may assume that, when temp2_reg is a valid register,
4867 // this code sets it to a nonzero value.
4868 bool temp2_reg_was_valid = temp2_reg->is_valid();
4869
4870 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4871
4872 Label L_fallthrough;
4873 int label_nulls = 0;
4874 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4875 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4876 assert(label_nulls <= 1, "at most one null in the batch");
4877
4878 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4879
4880 RegSetIterator<Register> available_regs
4881 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4882
4883 RegSet pushed_regs;
4884
4885 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4886 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4887 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4888 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4889 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4890
4891 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4892
4893 {
4894
4895 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4896 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4897 subptr(rsp, aligned_size);
4898 push_set(pushed_regs, 0);
4899
4900 lookup_secondary_supers_table_var(sub_klass,
4901 super_klass,
4902 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4903 cmpq(result_reg, 0);
4904
4905 // Unspill the temp. registers:
4906 pop_set(pushed_regs, 0);
4907 // Increment SP but do not clobber flags.
4908 lea(rsp, Address(rsp, aligned_size));
4909 }
4910
4911 if (temp2_reg_was_valid) {
4912 movq(temp2_reg, 1);
4913 }
4914
4915 jcc(Assembler::notEqual, *L_failure);
4916
4917 if (L_success != &L_fallthrough) {
4918 jmp(*L_success);
4919 }
4920
4921 bind(L_fallthrough);
4922 }
4923
4924 // population_count variant for running without the POPCNT
4925 // instruction, which was introduced with SSE4.2 in 2008.
4926 void MacroAssembler::population_count(Register dst, Register src,
4927 Register scratch1, Register scratch2) {
4928 assert_different_registers(src, scratch1, scratch2);
4929 if (UsePopCountInstruction) {
4930 Assembler::popcntq(dst, src);
4931 } else {
4932 assert_different_registers(src, scratch1, scratch2);
4933 assert_different_registers(dst, scratch1, scratch2);
4934 Label loop, done;
4935
4936 mov(scratch1, src);
4937 // dst = 0;
4938 // while(scratch1 != 0) {
4939 // dst++;
4940 // scratch1 &= (scratch1 - 1);
4941 // }
4942 xorl(dst, dst);
4943 testq(scratch1, scratch1);
4944 jccb(Assembler::equal, done);
4945 {
4946 bind(loop);
4947 incq(dst);
4948 movq(scratch2, scratch1);
4949 decq(scratch2);
4950 andq(scratch1, scratch2);
4951 jccb(Assembler::notEqual, loop);
4952 }
4953 bind(done);
4954 }
4955 #ifdef ASSERT
4956 mov64(scratch1, 0xCafeBabeDeadBeef);
4957 movq(scratch2, scratch1);
4958 #endif
4959 }
4960
4961 // Ensure that the inline code and the stub are using the same registers.
4962 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4963 do { \
4964 assert(r_super_klass == rax, "mismatch"); \
4965 assert(r_array_base == rbx, "mismatch"); \
4966 assert(r_array_length == rcx, "mismatch"); \
4967 assert(r_array_index == rdx, "mismatch"); \
4968 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4969 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4970 assert(result == rdi || result == noreg, "mismatch"); \
4971 } while(0)
4972
4973 // Versions of salq and rorq that don't need count to be in rcx
4974
4975 void MacroAssembler::salq(Register dest, Register count) {
4976 if (count == rcx) {
4977 Assembler::salq(dest);
4978 } else {
4979 assert_different_registers(rcx, dest);
4980 xchgq(rcx, count);
4981 Assembler::salq(dest);
4982 xchgq(rcx, count);
4983 }
4984 }
4985
4986 void MacroAssembler::rorq(Register dest, Register count) {
4987 if (count == rcx) {
4988 Assembler::rorq(dest);
4989 } else {
4990 assert_different_registers(rcx, dest);
4991 xchgq(rcx, count);
4992 Assembler::rorq(dest);
4993 xchgq(rcx, count);
4994 }
4995 }
4996
4997 // Return true: we succeeded in generating this code
4998 //
4999 // At runtime, return 0 in result if r_super_klass is a superclass of
5000 // r_sub_klass, otherwise return nonzero. Use this if you know the
5001 // super_klass_slot of the class you're looking for. This is always
5002 // the case for instanceof and checkcast.
5003 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
5004 Register r_super_klass,
5005 Register temp1,
5006 Register temp2,
5007 Register temp3,
5008 Register temp4,
5009 Register result,
5010 u1 super_klass_slot) {
5011 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
5012
5013 Label L_fallthrough, L_success, L_failure;
5014
5015 BLOCK_COMMENT("lookup_secondary_supers_table {");
5016
5017 const Register
5018 r_array_index = temp1,
5019 r_array_length = temp2,
5020 r_array_base = temp3,
5021 r_bitmap = temp4;
5022
5023 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
5024
5025 xorq(result, result); // = 0
5026
5027 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
5028 movq(r_array_index, r_bitmap);
5029
5030 // First check the bitmap to see if super_klass might be present. If
5031 // the bit is zero, we are certain that super_klass is not one of
5032 // the secondary supers.
5033 u1 bit = super_klass_slot;
5034 {
5035 // NB: If the count in a x86 shift instruction is 0, the flags are
5036 // not affected, so we do a testq instead.
5037 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
5038 if (shift_count != 0) {
5039 salq(r_array_index, shift_count);
5040 } else {
5041 testq(r_array_index, r_array_index);
5042 }
5043 }
5044 // We test the MSB of r_array_index, i.e. its sign bit
5045 jcc(Assembler::positive, L_failure);
5046
5047 // Get the first array index that can contain super_klass into r_array_index.
5048 if (bit != 0) {
5049 population_count(r_array_index, r_array_index, temp2, temp3);
5050 } else {
5051 movl(r_array_index, 1);
5052 }
5053 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5054
5055 // We will consult the secondary-super array.
5056 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5057
5058 // We're asserting that the first word in an Array<Klass*> is the
5059 // length, and the second word is the first word of the data. If
5060 // that ever changes, r_array_base will have to be adjusted here.
5061 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5062 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5063
5064 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5065 jccb(Assembler::equal, L_success);
5066
5067 // Is there another entry to check? Consult the bitmap.
5068 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
5069 jccb(Assembler::carryClear, L_failure);
5070
5071 // Linear probe. Rotate the bitmap so that the next bit to test is
5072 // in Bit 1.
5073 if (bit != 0) {
5074 rorq(r_bitmap, bit);
5075 }
5076
5077 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5078 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5079 // Kills: r_array_length.
5080 // Returns: result.
5081 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
5082 // Result (0/1) is in rdi
5083 jmpb(L_fallthrough);
5084
5085 bind(L_failure);
5086 incq(result); // 0 => 1
5087
5088 bind(L_success);
5089 // result = 0;
5090
5091 bind(L_fallthrough);
5092 BLOCK_COMMENT("} lookup_secondary_supers_table");
5093
5094 if (VerifySecondarySupers) {
5095 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5096 temp1, temp2, temp3);
5097 }
5098 }
5099
5100 // At runtime, return 0 in result if r_super_klass is a superclass of
5101 // r_sub_klass, otherwise return nonzero. Use this version of
5102 // lookup_secondary_supers_table() if you don't know ahead of time
5103 // which superclass will be searched for. Used by interpreter and
5104 // runtime stubs. It is larger and has somewhat greater latency than
5105 // the version above, which takes a constant super_klass_slot.
5106 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
5107 Register r_super_klass,
5108 Register temp1,
5109 Register temp2,
5110 Register temp3,
5111 Register temp4,
5112 Register result) {
5113 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
5114 assert_different_registers(r_sub_klass, r_super_klass, rcx);
5115 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
5116
5117 Label L_fallthrough, L_success, L_failure;
5118
5119 BLOCK_COMMENT("lookup_secondary_supers_table {");
5120
5121 RegSetIterator<Register> available_regs = (temps - rcx).begin();
5122
5123 // FIXME. Once we are sure that all paths reaching this point really
5124 // do pass rcx as one of our temps we can get rid of the following
5125 // workaround.
5126 assert(temps.contains(rcx), "fix this code");
5127
5128 // We prefer to have our shift count in rcx. If rcx is one of our
5129 // temps, use it for slot. If not, pick any of our temps.
5130 Register slot;
5131 if (!temps.contains(rcx)) {
5132 slot = *available_regs++;
5133 } else {
5134 slot = rcx;
5135 }
5136
5137 const Register r_array_index = *available_regs++;
5138 const Register r_bitmap = *available_regs++;
5139
5140 // The logic above guarantees this property, but we state it here.
5141 assert_different_registers(r_array_index, r_bitmap, rcx);
5142
5143 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
5144 movq(r_array_index, r_bitmap);
5145
5146 // First check the bitmap to see if super_klass might be present. If
5147 // the bit is zero, we are certain that super_klass is not one of
5148 // the secondary supers.
5149 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
5150 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
5151 salq(r_array_index, slot);
5152
5153 testq(r_array_index, r_array_index);
5154 // We test the MSB of r_array_index, i.e. its sign bit
5155 jcc(Assembler::positive, L_failure);
5156
5157 const Register r_array_base = *available_regs++;
5158
5159 // Get the first array index that can contain super_klass into r_array_index.
5160 // Note: Clobbers r_array_base and slot.
5161 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
5162
5163 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5164
5165 // We will consult the secondary-super array.
5166 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5167
5168 // We're asserting that the first word in an Array<Klass*> is the
5169 // length, and the second word is the first word of the data. If
5170 // that ever changes, r_array_base will have to be adjusted here.
5171 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5172 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5173
5174 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5175 jccb(Assembler::equal, L_success);
5176
5177 // Restore slot to its true value
5178 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
5179
5180 // Linear probe. Rotate the bitmap so that the next bit to test is
5181 // in Bit 1.
5182 rorq(r_bitmap, slot);
5183
5184 // Is there another entry to check? Consult the bitmap.
5185 btq(r_bitmap, 1);
5186 jccb(Assembler::carryClear, L_failure);
5187
5188 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5189 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5190 // Kills: r_array_length.
5191 // Returns: result.
5192 lookup_secondary_supers_table_slow_path(r_super_klass,
5193 r_array_base,
5194 r_array_index,
5195 r_bitmap,
5196 /*temp1*/result,
5197 /*temp2*/slot,
5198 &L_success,
5199 nullptr);
5200
5201 bind(L_failure);
5202 movq(result, 1);
5203 jmpb(L_fallthrough);
5204
5205 bind(L_success);
5206 xorq(result, result); // = 0
5207
5208 bind(L_fallthrough);
5209 BLOCK_COMMENT("} lookup_secondary_supers_table");
5210
5211 if (VerifySecondarySupers) {
5212 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5213 temp1, temp2, temp3);
5214 }
5215 }
5216
5217 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
5218 Label* L_success, Label* L_failure) {
5219 Label L_loop, L_fallthrough;
5220 {
5221 int label_nulls = 0;
5222 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5223 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5224 assert(label_nulls <= 1, "at most one null in the batch");
5225 }
5226 bind(L_loop);
5227 cmpq(value, Address(addr, count, Address::times_8));
5228 jcc(Assembler::equal, *L_success);
5229 addl(count, 1);
5230 cmpl(count, limit);
5231 jcc(Assembler::less, L_loop);
5232
5233 if (&L_fallthrough != L_failure) {
5234 jmp(*L_failure);
5235 }
5236 bind(L_fallthrough);
5237 }
5238
5239 // Called by code generated by check_klass_subtype_slow_path
5240 // above. This is called when there is a collision in the hashed
5241 // lookup in the secondary supers array.
5242 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
5243 Register r_array_base,
5244 Register r_array_index,
5245 Register r_bitmap,
5246 Register temp1,
5247 Register temp2,
5248 Label* L_success,
5249 Label* L_failure) {
5250 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
5251
5252 const Register
5253 r_array_length = temp1,
5254 r_sub_klass = noreg,
5255 result = noreg;
5256
5257 Label L_fallthrough;
5258 int label_nulls = 0;
5259 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5260 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5261 assert(label_nulls <= 1, "at most one null in the batch");
5262
5263 // Load the array length.
5264 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5265 // And adjust the array base to point to the data.
5266 // NB! Effectively increments current slot index by 1.
5267 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
5268 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5269
5270 // Linear probe
5271 Label L_huge;
5272
5273 // The bitmap is full to bursting.
5274 // Implicit invariant: BITMAP_FULL implies (length > 0)
5275 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
5276 jcc(Assembler::greater, L_huge);
5277
5278 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
5279 // current slot (at secondary_supers[r_array_index]) has not yet
5280 // been inspected, and r_array_index may be out of bounds if we
5281 // wrapped around the end of the array.
5282
5283 { // This is conventional linear probing, but instead of terminating
5284 // when a null entry is found in the table, we maintain a bitmap
5285 // in which a 0 indicates missing entries.
5286 // The check above guarantees there are 0s in the bitmap, so the loop
5287 // eventually terminates.
5288
5289 xorl(temp2, temp2); // = 0;
5290
5291 Label L_again;
5292 bind(L_again);
5293
5294 // Check for array wraparound.
5295 cmpl(r_array_index, r_array_length);
5296 cmovl(Assembler::greaterEqual, r_array_index, temp2);
5297
5298 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5299 jcc(Assembler::equal, *L_success);
5300
5301 // If the next bit in bitmap is zero, we're done.
5302 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
5303 jcc(Assembler::carryClear, *L_failure);
5304
5305 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
5306 addl(r_array_index, 1);
5307
5308 jmp(L_again);
5309 }
5310
5311 { // Degenerate case: more than 64 secondary supers.
5312 // FIXME: We could do something smarter here, maybe a vectorized
5313 // comparison or a binary search, but is that worth any added
5314 // complexity?
5315 bind(L_huge);
5316 xorl(r_array_index, r_array_index); // = 0
5317 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
5318 L_success,
5319 (&L_fallthrough != L_failure ? L_failure : nullptr));
5320
5321 bind(L_fallthrough);
5322 }
5323 }
5324
5325 struct VerifyHelperArguments {
5326 Klass* _super;
5327 Klass* _sub;
5328 intptr_t _linear_result;
5329 intptr_t _table_result;
5330 };
5331
5332 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
5333 Klass::on_secondary_supers_verification_failure(args->_super,
5334 args->_sub,
5335 args->_linear_result,
5336 args->_table_result,
5337 msg);
5338 }
5339
5340 // Make sure that the hashed lookup and a linear scan agree.
5341 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
5342 Register r_super_klass,
5343 Register result,
5344 Register temp1,
5345 Register temp2,
5346 Register temp3) {
5347 const Register
5348 r_array_index = temp1,
5349 r_array_length = temp2,
5350 r_array_base = temp3,
5351 r_bitmap = noreg;
5352
5353 BLOCK_COMMENT("verify_secondary_supers_table {");
5354
5355 Label L_success, L_failure, L_check, L_done;
5356
5357 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5358 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5359 // And adjust the array base to point to the data.
5360 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5361
5362 testl(r_array_length, r_array_length); // array_length == 0?
5363 jcc(Assembler::zero, L_failure);
5364
5365 movl(r_array_index, 0);
5366 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
5367 // fall through to L_failure
5368
5369 const Register linear_result = r_array_index; // reuse temp1
5370
5371 bind(L_failure); // not present
5372 movl(linear_result, 1);
5373 jmp(L_check);
5374
5375 bind(L_success); // present
5376 movl(linear_result, 0);
5377
5378 bind(L_check);
5379 cmpl(linear_result, result);
5380 jcc(Assembler::equal, L_done);
5381
5382 { // To avoid calling convention issues, build a record on the stack
5383 // and pass the pointer to that instead.
5384 push(result);
5385 push(linear_result);
5386 push(r_sub_klass);
5387 push(r_super_klass);
5388 movptr(c_rarg1, rsp);
5389 movptr(c_rarg0, (uintptr_t) "mismatch");
5390 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
5391 should_not_reach_here();
5392 }
5393 bind(L_done);
5394
5395 BLOCK_COMMENT("} verify_secondary_supers_table");
5396 }
5397
5398 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
5399
5400 #endif // LP64
5401
5402 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
5403 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
5404
5405 Label L_fallthrough;
5406 if (L_fast_path == nullptr) {
5407 L_fast_path = &L_fallthrough;
5408 } else if (L_slow_path == nullptr) {
5409 L_slow_path = &L_fallthrough;
5410 }
5411
5412 // Fast path check: class is fully initialized.
5413 // init_state needs acquire, but x86 is TSO, and so we are already good.
5414 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
5415 jcc(Assembler::equal, *L_fast_path);
5416
5417 // Fast path check: current thread is initializer thread
5418 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
5419 if (L_slow_path == &L_fallthrough) {
5420 jcc(Assembler::equal, *L_fast_path);
5421 bind(*L_slow_path);
5422 } else if (L_fast_path == &L_fallthrough) {
5423 jcc(Assembler::notEqual, *L_slow_path);
5424 bind(*L_fast_path);
5425 } else {
5426 Unimplemented();
5427 }
5428 }
5429
5430 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5431 if (VM_Version::supports_cmov()) {
5432 cmovl(cc, dst, src);
5433 } else {
5434 Label L;
5435 jccb(negate_condition(cc), L);
5436 movl(dst, src);
5437 bind(L);
5438 }
5439 }
5440
5441 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5442 if (VM_Version::supports_cmov()) {
5443 cmovl(cc, dst, src);
5444 } else {
5445 Label L;
5446 jccb(negate_condition(cc), L);
5447 movl(dst, src);
5448 bind(L);
5449 }
5450 }
5451
5452 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
5453 if (!VerifyOops) return;
5454
5455 BLOCK_COMMENT("verify_oop {");
5456 #ifdef _LP64
5457 push(rscratch1);
5458 #endif
5459 push(rax); // save rax
5460 push(reg); // pass register argument
5461
5462 // Pass register number to verify_oop_subroutine
5463 const char* b = nullptr;
5464 {
5465 ResourceMark rm;
5466 stringStream ss;
5467 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5468 b = code_string(ss.as_string());
5469 }
5470 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5471 pushptr(buffer.addr(), rscratch1);
5472
5473 // call indirectly to solve generation ordering problem
5474 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5475 call(rax);
5476 // Caller pops the arguments (oop, message) and restores rax, r10
5477 BLOCK_COMMENT("} verify_oop");
5478 }
5479
5480 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
5481 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
5482 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
5483 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
5484 vpternlogd(dst, 0xFF, dst, dst, vector_len);
5485 } else if (VM_Version::supports_avx()) {
5486 vpcmpeqd(dst, dst, dst, vector_len);
5487 } else {
5488 pcmpeqd(dst, dst);
5489 }
5490 }
5491
5492 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5493 int extra_slot_offset) {
5494 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5495 int stackElementSize = Interpreter::stackElementSize;
5496 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5497 #ifdef ASSERT
5498 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5499 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5500 #endif
5501 Register scale_reg = noreg;
5502 Address::ScaleFactor scale_factor = Address::no_scale;
5503 if (arg_slot.is_constant()) {
5504 offset += arg_slot.as_constant() * stackElementSize;
5505 } else {
5506 scale_reg = arg_slot.as_register();
5507 scale_factor = Address::times(stackElementSize);
5508 }
5509 offset += wordSize; // return PC is on stack
5510 return Address(rsp, scale_reg, scale_factor, offset);
5511 }
5512
5513 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5514 if (!VerifyOops) return;
5515
5516 #ifdef _LP64
5517 push(rscratch1);
5518 #endif
5519 push(rax); // save rax,
5520 // addr may contain rsp so we will have to adjust it based on the push
5521 // we just did (and on 64 bit we do two pushes)
5522 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5523 // stores rax into addr which is backwards of what was intended.
5524 if (addr.uses(rsp)) {
5525 lea(rax, addr);
5526 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5527 } else {
5528 pushptr(addr);
5529 }
5530
5531 // Pass register number to verify_oop_subroutine
5532 const char* b = nullptr;
5533 {
5534 ResourceMark rm;
5535 stringStream ss;
5536 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5537 b = code_string(ss.as_string());
5538 }
5539 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5540 pushptr(buffer.addr(), rscratch1);
5541
5542 // call indirectly to solve generation ordering problem
5543 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5544 call(rax);
5545 // Caller pops the arguments (addr, message) and restores rax, r10.
5546 }
5547
5548 void MacroAssembler::verify_tlab() {
5549 #ifdef ASSERT
5550 if (UseTLAB && VerifyOops) {
5551 Label next, ok;
5552 Register t1 = rsi;
5553 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5554
5555 push(t1);
5556 NOT_LP64(push(thread_reg));
5557 NOT_LP64(get_thread(thread_reg));
5558
5559 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5560 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5561 jcc(Assembler::aboveEqual, next);
5562 STOP("assert(top >= start)");
5563 should_not_reach_here();
5564
5565 bind(next);
5566 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5567 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5568 jcc(Assembler::aboveEqual, ok);
5569 STOP("assert(top <= end)");
5570 should_not_reach_here();
5571
5572 bind(ok);
5573 NOT_LP64(pop(thread_reg));
5574 pop(t1);
5575 }
5576 #endif
5577 }
5578
5579 class ControlWord {
5580 public:
5581 int32_t _value;
5582
5583 int rounding_control() const { return (_value >> 10) & 3 ; }
5584 int precision_control() const { return (_value >> 8) & 3 ; }
5585 bool precision() const { return ((_value >> 5) & 1) != 0; }
5586 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5587 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5588 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5589 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5590 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5591
5592 void print() const {
5593 // rounding control
5594 const char* rc;
5595 switch (rounding_control()) {
5596 case 0: rc = "round near"; break;
5597 case 1: rc = "round down"; break;
5598 case 2: rc = "round up "; break;
5599 case 3: rc = "chop "; break;
5600 default:
5601 rc = nullptr; // silence compiler warnings
5602 fatal("Unknown rounding control: %d", rounding_control());
5603 };
5604 // precision control
5605 const char* pc;
5606 switch (precision_control()) {
5607 case 0: pc = "24 bits "; break;
5608 case 1: pc = "reserved"; break;
5609 case 2: pc = "53 bits "; break;
5610 case 3: pc = "64 bits "; break;
5611 default:
5612 pc = nullptr; // silence compiler warnings
5613 fatal("Unknown precision control: %d", precision_control());
5614 };
5615 // flags
5616 char f[9];
5617 f[0] = ' ';
5618 f[1] = ' ';
5619 f[2] = (precision ()) ? 'P' : 'p';
5620 f[3] = (underflow ()) ? 'U' : 'u';
5621 f[4] = (overflow ()) ? 'O' : 'o';
5622 f[5] = (zero_divide ()) ? 'Z' : 'z';
5623 f[6] = (denormalized()) ? 'D' : 'd';
5624 f[7] = (invalid ()) ? 'I' : 'i';
5625 f[8] = '\x0';
5626 // output
5627 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5628 }
5629
5630 };
5631
5632 class StatusWord {
5633 public:
5634 int32_t _value;
5635
5636 bool busy() const { return ((_value >> 15) & 1) != 0; }
5637 bool C3() const { return ((_value >> 14) & 1) != 0; }
5638 bool C2() const { return ((_value >> 10) & 1) != 0; }
5639 bool C1() const { return ((_value >> 9) & 1) != 0; }
5640 bool C0() const { return ((_value >> 8) & 1) != 0; }
5641 int top() const { return (_value >> 11) & 7 ; }
5642 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5643 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5644 bool precision() const { return ((_value >> 5) & 1) != 0; }
5645 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5646 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5647 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5648 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5649 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5650
5651 void print() const {
5652 // condition codes
5653 char c[5];
5654 c[0] = (C3()) ? '3' : '-';
5655 c[1] = (C2()) ? '2' : '-';
5656 c[2] = (C1()) ? '1' : '-';
5657 c[3] = (C0()) ? '0' : '-';
5658 c[4] = '\x0';
5659 // flags
5660 char f[9];
5661 f[0] = (error_status()) ? 'E' : '-';
5662 f[1] = (stack_fault ()) ? 'S' : '-';
5663 f[2] = (precision ()) ? 'P' : '-';
5664 f[3] = (underflow ()) ? 'U' : '-';
5665 f[4] = (overflow ()) ? 'O' : '-';
5666 f[5] = (zero_divide ()) ? 'Z' : '-';
5667 f[6] = (denormalized()) ? 'D' : '-';
5668 f[7] = (invalid ()) ? 'I' : '-';
5669 f[8] = '\x0';
5670 // output
5671 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5672 }
5673
5674 };
5675
5676 class TagWord {
5677 public:
5678 int32_t _value;
5679
5680 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5681
5682 void print() const {
5683 printf("%04x", _value & 0xFFFF);
5684 }
5685
5686 };
5687
5688 class FPU_Register {
5689 public:
5690 int32_t _m0;
5691 int32_t _m1;
5692 int16_t _ex;
5693
5694 bool is_indefinite() const {
5695 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5696 }
5697
5698 void print() const {
5699 char sign = (_ex < 0) ? '-' : '+';
5700 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5701 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5702 };
5703
5704 };
5705
5706 class FPU_State {
5707 public:
5708 enum {
5709 register_size = 10,
5710 number_of_registers = 8,
5711 register_mask = 7
5712 };
5713
5714 ControlWord _control_word;
5715 StatusWord _status_word;
5716 TagWord _tag_word;
5717 int32_t _error_offset;
5718 int32_t _error_selector;
5719 int32_t _data_offset;
5720 int32_t _data_selector;
5721 int8_t _register[register_size * number_of_registers];
5722
5723 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5724 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5725
5726 const char* tag_as_string(int tag) const {
5727 switch (tag) {
5728 case 0: return "valid";
5729 case 1: return "zero";
5730 case 2: return "special";
5731 case 3: return "empty";
5732 }
5733 ShouldNotReachHere();
5734 return nullptr;
5735 }
5736
5737 void print() const {
5738 // print computation registers
5739 { int t = _status_word.top();
5740 for (int i = 0; i < number_of_registers; i++) {
5741 int j = (i - t) & register_mask;
5742 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5743 st(j)->print();
5744 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5745 }
5746 }
5747 printf("\n");
5748 // print control registers
5749 printf("ctrl = "); _control_word.print(); printf("\n");
5750 printf("stat = "); _status_word .print(); printf("\n");
5751 printf("tags = "); _tag_word .print(); printf("\n");
5752 }
5753
5754 };
5755
5756 class Flag_Register {
5757 public:
5758 int32_t _value;
5759
5760 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5761 bool direction() const { return ((_value >> 10) & 1) != 0; }
5762 bool sign() const { return ((_value >> 7) & 1) != 0; }
5763 bool zero() const { return ((_value >> 6) & 1) != 0; }
5764 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5765 bool parity() const { return ((_value >> 2) & 1) != 0; }
5766 bool carry() const { return ((_value >> 0) & 1) != 0; }
5767
5768 void print() const {
5769 // flags
5770 char f[8];
5771 f[0] = (overflow ()) ? 'O' : '-';
5772 f[1] = (direction ()) ? 'D' : '-';
5773 f[2] = (sign ()) ? 'S' : '-';
5774 f[3] = (zero ()) ? 'Z' : '-';
5775 f[4] = (auxiliary_carry()) ? 'A' : '-';
5776 f[5] = (parity ()) ? 'P' : '-';
5777 f[6] = (carry ()) ? 'C' : '-';
5778 f[7] = '\x0';
5779 // output
5780 printf("%08x flags = %s", _value, f);
5781 }
5782
5783 };
5784
5785 class IU_Register {
5786 public:
5787 int32_t _value;
5788
5789 void print() const {
5790 printf("%08x %11d", _value, _value);
5791 }
5792
5793 };
5794
5795 class IU_State {
5796 public:
5797 Flag_Register _eflags;
5798 IU_Register _rdi;
5799 IU_Register _rsi;
5800 IU_Register _rbp;
5801 IU_Register _rsp;
5802 IU_Register _rbx;
5803 IU_Register _rdx;
5804 IU_Register _rcx;
5805 IU_Register _rax;
5806
5807 void print() const {
5808 // computation registers
5809 printf("rax, = "); _rax.print(); printf("\n");
5810 printf("rbx, = "); _rbx.print(); printf("\n");
5811 printf("rcx = "); _rcx.print(); printf("\n");
5812 printf("rdx = "); _rdx.print(); printf("\n");
5813 printf("rdi = "); _rdi.print(); printf("\n");
5814 printf("rsi = "); _rsi.print(); printf("\n");
5815 printf("rbp, = "); _rbp.print(); printf("\n");
5816 printf("rsp = "); _rsp.print(); printf("\n");
5817 printf("\n");
5818 // control registers
5819 printf("flgs = "); _eflags.print(); printf("\n");
5820 }
5821 };
5822
5823
5824 class CPU_State {
5825 public:
5826 FPU_State _fpu_state;
5827 IU_State _iu_state;
5828
5829 void print() const {
5830 printf("--------------------------------------------------\n");
5831 _iu_state .print();
5832 printf("\n");
5833 _fpu_state.print();
5834 printf("--------------------------------------------------\n");
5835 }
5836
5837 };
5838
5839
5840 static void _print_CPU_state(CPU_State* state) {
5841 state->print();
5842 };
5843
5844
5845 void MacroAssembler::print_CPU_state() {
5846 push_CPU_state();
5847 push(rsp); // pass CPU state
5848 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5849 addptr(rsp, wordSize); // discard argument
5850 pop_CPU_state();
5851 }
5852
5853
5854 #ifndef _LP64
5855 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5856 static int counter = 0;
5857 FPU_State* fs = &state->_fpu_state;
5858 counter++;
5859 // For leaf calls, only verify that the top few elements remain empty.
5860 // We only need 1 empty at the top for C2 code.
5861 if( stack_depth < 0 ) {
5862 if( fs->tag_for_st(7) != 3 ) {
5863 printf("FPR7 not empty\n");
5864 state->print();
5865 assert(false, "error");
5866 return false;
5867 }
5868 return true; // All other stack states do not matter
5869 }
5870
5871 assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
5872 "bad FPU control word");
5873
5874 // compute stack depth
5875 int i = 0;
5876 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5877 int d = i;
5878 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5879 // verify findings
5880 if (i != FPU_State::number_of_registers) {
5881 // stack not contiguous
5882 printf("%s: stack not contiguous at ST%d\n", s, i);
5883 state->print();
5884 assert(false, "error");
5885 return false;
5886 }
5887 // check if computed stack depth corresponds to expected stack depth
5888 if (stack_depth < 0) {
5889 // expected stack depth is -stack_depth or less
5890 if (d > -stack_depth) {
5891 // too many elements on the stack
5892 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5893 state->print();
5894 assert(false, "error");
5895 return false;
5896 }
5897 } else {
5898 // expected stack depth is stack_depth
5899 if (d != stack_depth) {
5900 // wrong stack depth
5901 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5902 state->print();
5903 assert(false, "error");
5904 return false;
5905 }
5906 }
5907 // everything is cool
5908 return true;
5909 }
5910
5911 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5912 if (!VerifyFPU) return;
5913 push_CPU_state();
5914 push(rsp); // pass CPU state
5915 ExternalAddress msg((address) s);
5916 // pass message string s
5917 pushptr(msg.addr(), noreg);
5918 push(stack_depth); // pass stack depth
5919 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5920 addptr(rsp, 3 * wordSize); // discard arguments
5921 // check for error
5922 { Label L;
5923 testl(rax, rax);
5924 jcc(Assembler::notZero, L);
5925 int3(); // break if error condition
5926 bind(L);
5927 }
5928 pop_CPU_state();
5929 }
5930 #endif // _LP64
5931
5932 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5933 // Either restore the MXCSR register after returning from the JNI Call
5934 // or verify that it wasn't changed (with -Xcheck:jni flag).
5935 if (VM_Version::supports_sse()) {
5936 if (RestoreMXCSROnJNICalls) {
5937 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5938 } else if (CheckJNICalls) {
5939 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5940 }
5941 }
5942 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5943 vzeroupper();
5944
5945 #ifndef _LP64
5946 // Either restore the x87 floating pointer control word after returning
5947 // from the JNI call or verify that it wasn't changed.
5948 if (CheckJNICalls) {
5949 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5950 }
5951 #endif // _LP64
5952 }
5953
5954 // ((OopHandle)result).resolve();
5955 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5956 assert_different_registers(result, tmp);
5957
5958 // Only 64 bit platforms support GCs that require a tmp register
5959 // Only IN_HEAP loads require a thread_tmp register
5960 // OopHandle::resolve is an indirection like jobject.
5961 access_load_at(T_OBJECT, IN_NATIVE,
5962 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5963 }
5964
5965 // ((WeakHandle)result).resolve();
5966 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5967 assert_different_registers(rresult, rtmp);
5968 Label resolved;
5969
5970 // A null weak handle resolves to null.
5971 cmpptr(rresult, 0);
5972 jcc(Assembler::equal, resolved);
5973
5974 // Only 64 bit platforms support GCs that require a tmp register
5975 // Only IN_HEAP loads require a thread_tmp register
5976 // WeakHandle::resolve is an indirection like jweak.
5977 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5978 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
5979 bind(resolved);
5980 }
5981
5982 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5983 // get mirror
5984 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5985 load_method_holder(mirror, method);
5986 movptr(mirror, Address(mirror, mirror_offset));
5987 resolve_oop_handle(mirror, tmp);
5988 }
5989
5990 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5991 load_method_holder(rresult, rmethod);
5992 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5993 }
5994
5995 void MacroAssembler::load_method_holder(Register holder, Register method) {
5996 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5997 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5998 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5999 }
6000
6001 #ifdef _LP64
6002 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
6003 assert(UseCompactObjectHeaders, "expect compact object headers");
6004 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
6005 shrq(dst, markWord::klass_shift);
6006 }
6007 #endif
6008
6009 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
6010 assert_different_registers(src, tmp);
6011 assert_different_registers(dst, tmp);
6012 #ifdef _LP64
6013 if (UseCompactObjectHeaders) {
6014 load_narrow_klass_compact(dst, src);
6015 decode_klass_not_null(dst, tmp);
6016 } else if (UseCompressedClassPointers) {
6017 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6018 decode_klass_not_null(dst, tmp);
6019 } else
6020 #endif
6021 {
6022 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6023 }
6024 }
6025
6026 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
6027 assert(!UseCompactObjectHeaders, "not with compact headers");
6028 assert_different_registers(src, tmp);
6029 assert_different_registers(dst, tmp);
6030 #ifdef _LP64
6031 if (UseCompressedClassPointers) {
6032 encode_klass_not_null(src, tmp);
6033 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6034 } else
6035 #endif
6036 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6037 }
6038
6039 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
6040 #ifdef _LP64
6041 if (UseCompactObjectHeaders) {
6042 assert(tmp != noreg, "need tmp");
6043 assert_different_registers(klass, obj, tmp);
6044 load_narrow_klass_compact(tmp, obj);
6045 cmpl(klass, tmp);
6046 } else if (UseCompressedClassPointers) {
6047 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
6048 } else
6049 #endif
6050 {
6051 cmpptr(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
6052 }
6053 }
6054
6055 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
6056 #ifdef _LP64
6057 if (UseCompactObjectHeaders) {
6058 assert(tmp2 != noreg, "need tmp2");
6059 assert_different_registers(obj1, obj2, tmp1, tmp2);
6060 load_narrow_klass_compact(tmp1, obj1);
6061 load_narrow_klass_compact(tmp2, obj2);
6062 cmpl(tmp1, tmp2);
6063 } else if (UseCompressedClassPointers) {
6064 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
6065 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
6066 } else
6067 #endif
6068 {
6069 movptr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
6070 cmpptr(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
6071 }
6072 }
6073
6074 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
6075 Register tmp1, Register thread_tmp) {
6076 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6077 decorators = AccessInternal::decorator_fixup(decorators, type);
6078 bool as_raw = (decorators & AS_RAW) != 0;
6079 if (as_raw) {
6080 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6081 } else {
6082 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6083 }
6084 }
6085
6086 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
6087 Register tmp1, Register tmp2, Register tmp3) {
6088 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6089 decorators = AccessInternal::decorator_fixup(decorators, type);
6090 bool as_raw = (decorators & AS_RAW) != 0;
6091 if (as_raw) {
6092 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6093 } else {
6094 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6095 }
6096 }
6097
6098 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
6099 Register thread_tmp, DecoratorSet decorators) {
6100 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
6101 }
6102
6103 // Doesn't do verification, generates fixed size code
6104 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
6105 Register thread_tmp, DecoratorSet decorators) {
6106 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
6107 }
6108
6109 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
6110 Register tmp2, Register tmp3, DecoratorSet decorators) {
6111 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
6112 }
6113
6114 // Used for storing nulls.
6115 void MacroAssembler::store_heap_oop_null(Address dst) {
6116 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
6117 }
6118
6119 #ifdef _LP64
6120 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6121 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
6122 if (UseCompressedClassPointers) {
6123 // Store to klass gap in destination
6124 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6125 }
6126 }
6127
6128 #ifdef ASSERT
6129 void MacroAssembler::verify_heapbase(const char* msg) {
6130 assert (UseCompressedOops, "should be compressed");
6131 assert (Universe::heap() != nullptr, "java heap should be initialized");
6132 if (CheckCompressedOops) {
6133 Label ok;
6134 ExternalAddress src2(CompressedOops::base_addr());
6135 const bool is_src2_reachable = reachable(src2);
6136 if (!is_src2_reachable) {
6137 push(rscratch1); // cmpptr trashes rscratch1
6138 }
6139 cmpptr(r12_heapbase, src2, rscratch1);
6140 jcc(Assembler::equal, ok);
6141 STOP(msg);
6142 bind(ok);
6143 if (!is_src2_reachable) {
6144 pop(rscratch1);
6145 }
6146 }
6147 }
6148 #endif
6149
6150 // Algorithm must match oop.inline.hpp encode_heap_oop.
6151 void MacroAssembler::encode_heap_oop(Register r) {
6152 #ifdef ASSERT
6153 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6154 #endif
6155 verify_oop_msg(r, "broken oop in encode_heap_oop");
6156 if (CompressedOops::base() == nullptr) {
6157 if (CompressedOops::shift() != 0) {
6158 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6159 shrq(r, LogMinObjAlignmentInBytes);
6160 }
6161 return;
6162 }
6163 testq(r, r);
6164 cmovq(Assembler::equal, r, r12_heapbase);
6165 subq(r, r12_heapbase);
6166 shrq(r, LogMinObjAlignmentInBytes);
6167 }
6168
6169 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6170 #ifdef ASSERT
6171 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6172 if (CheckCompressedOops) {
6173 Label ok;
6174 testq(r, r);
6175 jcc(Assembler::notEqual, ok);
6176 STOP("null oop passed to encode_heap_oop_not_null");
6177 bind(ok);
6178 }
6179 #endif
6180 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
6181 if (CompressedOops::base() != nullptr) {
6182 subq(r, r12_heapbase);
6183 }
6184 if (CompressedOops::shift() != 0) {
6185 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6186 shrq(r, LogMinObjAlignmentInBytes);
6187 }
6188 }
6189
6190 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6191 #ifdef ASSERT
6192 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6193 if (CheckCompressedOops) {
6194 Label ok;
6195 testq(src, src);
6196 jcc(Assembler::notEqual, ok);
6197 STOP("null oop passed to encode_heap_oop_not_null2");
6198 bind(ok);
6199 }
6200 #endif
6201 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
6202 if (dst != src) {
6203 movq(dst, src);
6204 }
6205 if (CompressedOops::base() != nullptr) {
6206 subq(dst, r12_heapbase);
6207 }
6208 if (CompressedOops::shift() != 0) {
6209 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6210 shrq(dst, LogMinObjAlignmentInBytes);
6211 }
6212 }
6213
6214 void MacroAssembler::decode_heap_oop(Register r) {
6215 #ifdef ASSERT
6216 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6217 #endif
6218 if (CompressedOops::base() == nullptr) {
6219 if (CompressedOops::shift() != 0) {
6220 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6221 shlq(r, LogMinObjAlignmentInBytes);
6222 }
6223 } else {
6224 Label done;
6225 shlq(r, LogMinObjAlignmentInBytes);
6226 jccb(Assembler::equal, done);
6227 addq(r, r12_heapbase);
6228 bind(done);
6229 }
6230 verify_oop_msg(r, "broken oop in decode_heap_oop");
6231 }
6232
6233 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6234 // Note: it will change flags
6235 assert (UseCompressedOops, "should only be used for compressed headers");
6236 assert (Universe::heap() != nullptr, "java heap should be initialized");
6237 // Cannot assert, unverified entry point counts instructions (see .ad file)
6238 // vtableStubs also counts instructions in pd_code_size_limit.
6239 // Also do not verify_oop as this is called by verify_oop.
6240 if (CompressedOops::shift() != 0) {
6241 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6242 shlq(r, LogMinObjAlignmentInBytes);
6243 if (CompressedOops::base() != nullptr) {
6244 addq(r, r12_heapbase);
6245 }
6246 } else {
6247 assert (CompressedOops::base() == nullptr, "sanity");
6248 }
6249 }
6250
6251 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6252 // Note: it will change flags
6253 assert (UseCompressedOops, "should only be used for compressed headers");
6254 assert (Universe::heap() != nullptr, "java heap should be initialized");
6255 // Cannot assert, unverified entry point counts instructions (see .ad file)
6256 // vtableStubs also counts instructions in pd_code_size_limit.
6257 // Also do not verify_oop as this is called by verify_oop.
6258 if (CompressedOops::shift() != 0) {
6259 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6260 if (LogMinObjAlignmentInBytes == Address::times_8) {
6261 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6262 } else {
6263 if (dst != src) {
6264 movq(dst, src);
6265 }
6266 shlq(dst, LogMinObjAlignmentInBytes);
6267 if (CompressedOops::base() != nullptr) {
6268 addq(dst, r12_heapbase);
6269 }
6270 }
6271 } else {
6272 assert (CompressedOops::base() == nullptr, "sanity");
6273 if (dst != src) {
6274 movq(dst, src);
6275 }
6276 }
6277 }
6278
6279 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
6280 assert_different_registers(r, tmp);
6281 if (CompressedKlassPointers::base() != nullptr) {
6282 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6283 subq(r, tmp);
6284 }
6285 if (CompressedKlassPointers::shift() != 0) {
6286 shrq(r, CompressedKlassPointers::shift());
6287 }
6288 }
6289
6290 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
6291 assert_different_registers(src, dst);
6292 if (CompressedKlassPointers::base() != nullptr) {
6293 mov64(dst, -(int64_t)CompressedKlassPointers::base());
6294 addq(dst, src);
6295 } else {
6296 movptr(dst, src);
6297 }
6298 if (CompressedKlassPointers::shift() != 0) {
6299 shrq(dst, CompressedKlassPointers::shift());
6300 }
6301 }
6302
6303 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
6304 assert_different_registers(r, tmp);
6305 // Note: it will change flags
6306 assert(UseCompressedClassPointers, "should only be used for compressed headers");
6307 // Cannot assert, unverified entry point counts instructions (see .ad file)
6308 // vtableStubs also counts instructions in pd_code_size_limit.
6309 // Also do not verify_oop as this is called by verify_oop.
6310 if (CompressedKlassPointers::shift() != 0) {
6311 shlq(r, CompressedKlassPointers::shift());
6312 }
6313 if (CompressedKlassPointers::base() != nullptr) {
6314 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6315 addq(r, tmp);
6316 }
6317 }
6318
6319 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
6320 assert_different_registers(src, dst);
6321 // Note: it will change flags
6322 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6323 // Cannot assert, unverified entry point counts instructions (see .ad file)
6324 // vtableStubs also counts instructions in pd_code_size_limit.
6325 // Also do not verify_oop as this is called by verify_oop.
6326
6327 if (CompressedKlassPointers::base() == nullptr &&
6328 CompressedKlassPointers::shift() == 0) {
6329 // The best case scenario is that there is no base or shift. Then it is already
6330 // a pointer that needs nothing but a register rename.
6331 movl(dst, src);
6332 } else {
6333 if (CompressedKlassPointers::shift() <= Address::times_8) {
6334 if (CompressedKlassPointers::base() != nullptr) {
6335 mov64(dst, (int64_t)CompressedKlassPointers::base());
6336 } else {
6337 xorq(dst, dst);
6338 }
6339 if (CompressedKlassPointers::shift() != 0) {
6340 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
6341 leaq(dst, Address(dst, src, Address::times_8, 0));
6342 } else {
6343 addq(dst, src);
6344 }
6345 } else {
6346 if (CompressedKlassPointers::base() != nullptr) {
6347 const uint64_t base_right_shifted =
6348 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
6349 mov64(dst, base_right_shifted);
6350 } else {
6351 xorq(dst, dst);
6352 }
6353 addq(dst, src);
6354 shlq(dst, CompressedKlassPointers::shift());
6355 }
6356 }
6357 }
6358
6359 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6360 assert (UseCompressedOops, "should only be used for compressed headers");
6361 assert (Universe::heap() != nullptr, "java heap should be initialized");
6362 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6363 int oop_index = oop_recorder()->find_index(obj);
6364 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6365 mov_narrow_oop(dst, oop_index, rspec);
6366 }
6367
6368 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6369 assert (UseCompressedOops, "should only be used for compressed headers");
6370 assert (Universe::heap() != nullptr, "java heap should be initialized");
6371 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6372 int oop_index = oop_recorder()->find_index(obj);
6373 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6374 mov_narrow_oop(dst, oop_index, rspec);
6375 }
6376
6377 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6378 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6379 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6380 int klass_index = oop_recorder()->find_index(k);
6381 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6382 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6383 }
6384
6385 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6386 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6387 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6388 int klass_index = oop_recorder()->find_index(k);
6389 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6390 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6391 }
6392
6393 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6394 assert (UseCompressedOops, "should only be used for compressed headers");
6395 assert (Universe::heap() != nullptr, "java heap should be initialized");
6396 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6397 int oop_index = oop_recorder()->find_index(obj);
6398 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6399 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6400 }
6401
6402 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6403 assert (UseCompressedOops, "should only be used for compressed headers");
6404 assert (Universe::heap() != nullptr, "java heap should be initialized");
6405 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6406 int oop_index = oop_recorder()->find_index(obj);
6407 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6408 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6409 }
6410
6411 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6412 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6413 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6414 int klass_index = oop_recorder()->find_index(k);
6415 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6416 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6417 }
6418
6419 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6420 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6421 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6422 int klass_index = oop_recorder()->find_index(k);
6423 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6424 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6425 }
6426
6427 void MacroAssembler::reinit_heapbase() {
6428 if (UseCompressedOops) {
6429 if (Universe::heap() != nullptr) {
6430 if (CompressedOops::base() == nullptr) {
6431 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6432 } else {
6433 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6434 }
6435 } else {
6436 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6437 }
6438 }
6439 }
6440
6441 #endif // _LP64
6442
6443 #if COMPILER2_OR_JVMCI
6444
6445 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6446 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6447 // cnt - number of qwords (8-byte words).
6448 // base - start address, qword aligned.
6449 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6450 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
6451 if (use64byteVector) {
6452 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
6453 } else if (MaxVectorSize >= 32) {
6454 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
6455 } else {
6456 pxor(xtmp, xtmp);
6457 }
6458 jmp(L_zero_64_bytes);
6459
6460 BIND(L_loop);
6461 if (MaxVectorSize >= 32) {
6462 fill64(base, 0, xtmp, use64byteVector);
6463 } else {
6464 movdqu(Address(base, 0), xtmp);
6465 movdqu(Address(base, 16), xtmp);
6466 movdqu(Address(base, 32), xtmp);
6467 movdqu(Address(base, 48), xtmp);
6468 }
6469 addptr(base, 64);
6470
6471 BIND(L_zero_64_bytes);
6472 subptr(cnt, 8);
6473 jccb(Assembler::greaterEqual, L_loop);
6474
6475 // Copy trailing 64 bytes
6476 if (use64byteVector) {
6477 addptr(cnt, 8);
6478 jccb(Assembler::equal, L_end);
6479 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
6480 jmp(L_end);
6481 } else {
6482 addptr(cnt, 4);
6483 jccb(Assembler::less, L_tail);
6484 if (MaxVectorSize >= 32) {
6485 vmovdqu(Address(base, 0), xtmp);
6486 } else {
6487 movdqu(Address(base, 0), xtmp);
6488 movdqu(Address(base, 16), xtmp);
6489 }
6490 }
6491 addptr(base, 32);
6492 subptr(cnt, 4);
6493
6494 BIND(L_tail);
6495 addptr(cnt, 4);
6496 jccb(Assembler::lessEqual, L_end);
6497 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6498 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
6499 } else {
6500 decrement(cnt);
6501
6502 BIND(L_sloop);
6503 movq(Address(base, 0), xtmp);
6504 addptr(base, 8);
6505 decrement(cnt);
6506 jccb(Assembler::greaterEqual, L_sloop);
6507 }
6508 BIND(L_end);
6509 }
6510
6511 // Clearing constant sized memory using YMM/ZMM registers.
6512 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6513 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6514 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
6515
6516 int vector64_count = (cnt & (~0x7)) >> 3;
6517 cnt = cnt & 0x7;
6518 const int fill64_per_loop = 4;
6519 const int max_unrolled_fill64 = 8;
6520
6521 // 64 byte initialization loop.
6522 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6523 int start64 = 0;
6524 if (vector64_count > max_unrolled_fill64) {
6525 Label LOOP;
6526 Register index = rtmp;
6527
6528 start64 = vector64_count - (vector64_count % fill64_per_loop);
6529
6530 movl(index, 0);
6531 BIND(LOOP);
6532 for (int i = 0; i < fill64_per_loop; i++) {
6533 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6534 }
6535 addl(index, fill64_per_loop * 64);
6536 cmpl(index, start64 * 64);
6537 jccb(Assembler::less, LOOP);
6538 }
6539 for (int i = start64; i < vector64_count; i++) {
6540 fill64(base, i * 64, xtmp, use64byteVector);
6541 }
6542
6543 // Clear remaining 64 byte tail.
6544 int disp = vector64_count * 64;
6545 if (cnt) {
6546 switch (cnt) {
6547 case 1:
6548 movq(Address(base, disp), xtmp);
6549 break;
6550 case 2:
6551 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6552 break;
6553 case 3:
6554 movl(rtmp, 0x7);
6555 kmovwl(mask, rtmp);
6556 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6557 break;
6558 case 4:
6559 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6560 break;
6561 case 5:
6562 if (use64byteVector) {
6563 movl(rtmp, 0x1F);
6564 kmovwl(mask, rtmp);
6565 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6566 } else {
6567 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6568 movq(Address(base, disp + 32), xtmp);
6569 }
6570 break;
6571 case 6:
6572 if (use64byteVector) {
6573 movl(rtmp, 0x3F);
6574 kmovwl(mask, rtmp);
6575 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6576 } else {
6577 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6578 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6579 }
6580 break;
6581 case 7:
6582 if (use64byteVector) {
6583 movl(rtmp, 0x7F);
6584 kmovwl(mask, rtmp);
6585 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6586 } else {
6587 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6588 movl(rtmp, 0x7);
6589 kmovwl(mask, rtmp);
6590 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6591 }
6592 break;
6593 default:
6594 fatal("Unexpected length : %d\n",cnt);
6595 break;
6596 }
6597 }
6598 }
6599
6600 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
6601 bool is_large, KRegister mask) {
6602 // cnt - number of qwords (8-byte words).
6603 // base - start address, qword aligned.
6604 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6605 assert(base==rdi, "base register must be edi for rep stos");
6606 assert(tmp==rax, "tmp register must be eax for rep stos");
6607 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6608 assert(InitArrayShortSize % BytesPerLong == 0,
6609 "InitArrayShortSize should be the multiple of BytesPerLong");
6610
6611 Label DONE;
6612 if (!is_large || !UseXMMForObjInit) {
6613 xorptr(tmp, tmp);
6614 }
6615
6616 if (!is_large) {
6617 Label LOOP, LONG;
6618 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6619 jccb(Assembler::greater, LONG);
6620
6621 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6622
6623 decrement(cnt);
6624 jccb(Assembler::negative, DONE); // Zero length
6625
6626 // Use individual pointer-sized stores for small counts:
6627 BIND(LOOP);
6628 movptr(Address(base, cnt, Address::times_ptr), tmp);
6629 decrement(cnt);
6630 jccb(Assembler::greaterEqual, LOOP);
6631 jmpb(DONE);
6632
6633 BIND(LONG);
6634 }
6635
6636 // Use longer rep-prefixed ops for non-small counts:
6637 if (UseFastStosb) {
6638 shlptr(cnt, 3); // convert to number of bytes
6639 rep_stosb();
6640 } else if (UseXMMForObjInit) {
6641 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
6642 } else {
6643 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6644 rep_stos();
6645 }
6646
6647 BIND(DONE);
6648 }
6649
6650 #endif //COMPILER2_OR_JVMCI
6651
6652
6653 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6654 Register to, Register value, Register count,
6655 Register rtmp, XMMRegister xtmp) {
6656 ShortBranchVerifier sbv(this);
6657 assert_different_registers(to, value, count, rtmp);
6658 Label L_exit;
6659 Label L_fill_2_bytes, L_fill_4_bytes;
6660
6661 #if defined(COMPILER2) && defined(_LP64)
6662 if(MaxVectorSize >=32 &&
6663 VM_Version::supports_avx512vlbw() &&
6664 VM_Version::supports_bmi2()) {
6665 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6666 return;
6667 }
6668 #endif
6669
6670 int shift = -1;
6671 switch (t) {
6672 case T_BYTE:
6673 shift = 2;
6674 break;
6675 case T_SHORT:
6676 shift = 1;
6677 break;
6678 case T_INT:
6679 shift = 0;
6680 break;
6681 default: ShouldNotReachHere();
6682 }
6683
6684 if (t == T_BYTE) {
6685 andl(value, 0xff);
6686 movl(rtmp, value);
6687 shll(rtmp, 8);
6688 orl(value, rtmp);
6689 }
6690 if (t == T_SHORT) {
6691 andl(value, 0xffff);
6692 }
6693 if (t == T_BYTE || t == T_SHORT) {
6694 movl(rtmp, value);
6695 shll(rtmp, 16);
6696 orl(value, rtmp);
6697 }
6698
6699 cmpptr(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
6700 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6701 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6702 Label L_skip_align2;
6703 // align source address at 4 bytes address boundary
6704 if (t == T_BYTE) {
6705 Label L_skip_align1;
6706 // One byte misalignment happens only for byte arrays
6707 testptr(to, 1);
6708 jccb(Assembler::zero, L_skip_align1);
6709 movb(Address(to, 0), value);
6710 increment(to);
6711 decrement(count);
6712 BIND(L_skip_align1);
6713 }
6714 // Two bytes misalignment happens only for byte and short (char) arrays
6715 testptr(to, 2);
6716 jccb(Assembler::zero, L_skip_align2);
6717 movw(Address(to, 0), value);
6718 addptr(to, 2);
6719 subptr(count, 1<<(shift-1));
6720 BIND(L_skip_align2);
6721 }
6722 if (UseSSE < 2) {
6723 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6724 // Fill 32-byte chunks
6725 subptr(count, 8 << shift);
6726 jcc(Assembler::less, L_check_fill_8_bytes);
6727 align(16);
6728
6729 BIND(L_fill_32_bytes_loop);
6730
6731 for (int i = 0; i < 32; i += 4) {
6732 movl(Address(to, i), value);
6733 }
6734
6735 addptr(to, 32);
6736 subptr(count, 8 << shift);
6737 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6738 BIND(L_check_fill_8_bytes);
6739 addptr(count, 8 << shift);
6740 jccb(Assembler::zero, L_exit);
6741 jmpb(L_fill_8_bytes);
6742
6743 //
6744 // length is too short, just fill qwords
6745 //
6746 BIND(L_fill_8_bytes_loop);
6747 movl(Address(to, 0), value);
6748 movl(Address(to, 4), value);
6749 addptr(to, 8);
6750 BIND(L_fill_8_bytes);
6751 subptr(count, 1 << (shift + 1));
6752 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6753 // fall through to fill 4 bytes
6754 } else {
6755 Label L_fill_32_bytes;
6756 if (!UseUnalignedLoadStores) {
6757 // align to 8 bytes, we know we are 4 byte aligned to start
6758 testptr(to, 4);
6759 jccb(Assembler::zero, L_fill_32_bytes);
6760 movl(Address(to, 0), value);
6761 addptr(to, 4);
6762 subptr(count, 1<<shift);
6763 }
6764 BIND(L_fill_32_bytes);
6765 {
6766 assert( UseSSE >= 2, "supported cpu only" );
6767 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6768 movdl(xtmp, value);
6769 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6770 Label L_check_fill_32_bytes;
6771 if (UseAVX > 2) {
6772 // Fill 64-byte chunks
6773 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6774
6775 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
6776 cmpptr(count, VM_Version::avx3_threshold());
6777 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6778
6779 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6780
6781 subptr(count, 16 << shift);
6782 jccb(Assembler::less, L_check_fill_32_bytes);
6783 align(16);
6784
6785 BIND(L_fill_64_bytes_loop_avx3);
6786 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6787 addptr(to, 64);
6788 subptr(count, 16 << shift);
6789 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6790 jmpb(L_check_fill_32_bytes);
6791
6792 BIND(L_check_fill_64_bytes_avx2);
6793 }
6794 // Fill 64-byte chunks
6795 Label L_fill_64_bytes_loop;
6796 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6797
6798 subptr(count, 16 << shift);
6799 jcc(Assembler::less, L_check_fill_32_bytes);
6800 align(16);
6801
6802 BIND(L_fill_64_bytes_loop);
6803 vmovdqu(Address(to, 0), xtmp);
6804 vmovdqu(Address(to, 32), xtmp);
6805 addptr(to, 64);
6806 subptr(count, 16 << shift);
6807 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6808
6809 BIND(L_check_fill_32_bytes);
6810 addptr(count, 8 << shift);
6811 jccb(Assembler::less, L_check_fill_8_bytes);
6812 vmovdqu(Address(to, 0), xtmp);
6813 addptr(to, 32);
6814 subptr(count, 8 << shift);
6815
6816 BIND(L_check_fill_8_bytes);
6817 // clean upper bits of YMM registers
6818 movdl(xtmp, value);
6819 pshufd(xtmp, xtmp, 0);
6820 } else {
6821 // Fill 32-byte chunks
6822 pshufd(xtmp, xtmp, 0);
6823
6824 subptr(count, 8 << shift);
6825 jcc(Assembler::less, L_check_fill_8_bytes);
6826 align(16);
6827
6828 BIND(L_fill_32_bytes_loop);
6829
6830 if (UseUnalignedLoadStores) {
6831 movdqu(Address(to, 0), xtmp);
6832 movdqu(Address(to, 16), xtmp);
6833 } else {
6834 movq(Address(to, 0), xtmp);
6835 movq(Address(to, 8), xtmp);
6836 movq(Address(to, 16), xtmp);
6837 movq(Address(to, 24), xtmp);
6838 }
6839
6840 addptr(to, 32);
6841 subptr(count, 8 << shift);
6842 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6843
6844 BIND(L_check_fill_8_bytes);
6845 }
6846 addptr(count, 8 << shift);
6847 jccb(Assembler::zero, L_exit);
6848 jmpb(L_fill_8_bytes);
6849
6850 //
6851 // length is too short, just fill qwords
6852 //
6853 BIND(L_fill_8_bytes_loop);
6854 movq(Address(to, 0), xtmp);
6855 addptr(to, 8);
6856 BIND(L_fill_8_bytes);
6857 subptr(count, 1 << (shift + 1));
6858 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6859 }
6860 }
6861 // fill trailing 4 bytes
6862 BIND(L_fill_4_bytes);
6863 testl(count, 1<<shift);
6864 jccb(Assembler::zero, L_fill_2_bytes);
6865 movl(Address(to, 0), value);
6866 if (t == T_BYTE || t == T_SHORT) {
6867 Label L_fill_byte;
6868 addptr(to, 4);
6869 BIND(L_fill_2_bytes);
6870 // fill trailing 2 bytes
6871 testl(count, 1<<(shift-1));
6872 jccb(Assembler::zero, L_fill_byte);
6873 movw(Address(to, 0), value);
6874 if (t == T_BYTE) {
6875 addptr(to, 2);
6876 BIND(L_fill_byte);
6877 // fill trailing byte
6878 testl(count, 1);
6879 jccb(Assembler::zero, L_exit);
6880 movb(Address(to, 0), value);
6881 } else {
6882 BIND(L_fill_byte);
6883 }
6884 } else {
6885 BIND(L_fill_2_bytes);
6886 }
6887 BIND(L_exit);
6888 }
6889
6890 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6891 switch(type) {
6892 case T_BYTE:
6893 case T_BOOLEAN:
6894 evpbroadcastb(dst, src, vector_len);
6895 break;
6896 case T_SHORT:
6897 case T_CHAR:
6898 evpbroadcastw(dst, src, vector_len);
6899 break;
6900 case T_INT:
6901 case T_FLOAT:
6902 evpbroadcastd(dst, src, vector_len);
6903 break;
6904 case T_LONG:
6905 case T_DOUBLE:
6906 evpbroadcastq(dst, src, vector_len);
6907 break;
6908 default:
6909 fatal("Unhandled type : %s", type2name(type));
6910 break;
6911 }
6912 }
6913
6914 // encode char[] to byte[] in ISO_8859_1 or ASCII
6915 //@IntrinsicCandidate
6916 //private static int implEncodeISOArray(byte[] sa, int sp,
6917 //byte[] da, int dp, int len) {
6918 // int i = 0;
6919 // for (; i < len; i++) {
6920 // char c = StringUTF16.getChar(sa, sp++);
6921 // if (c > '\u00FF')
6922 // break;
6923 // da[dp++] = (byte)c;
6924 // }
6925 // return i;
6926 //}
6927 //
6928 //@IntrinsicCandidate
6929 //private static int implEncodeAsciiArray(char[] sa, int sp,
6930 // byte[] da, int dp, int len) {
6931 // int i = 0;
6932 // for (; i < len; i++) {
6933 // char c = sa[sp++];
6934 // if (c >= '\u0080')
6935 // break;
6936 // da[dp++] = (byte)c;
6937 // }
6938 // return i;
6939 //}
6940 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6941 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6942 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6943 Register tmp5, Register result, bool ascii) {
6944
6945 // rsi: src
6946 // rdi: dst
6947 // rdx: len
6948 // rcx: tmp5
6949 // rax: result
6950 ShortBranchVerifier sbv(this);
6951 assert_different_registers(src, dst, len, tmp5, result);
6952 Label L_done, L_copy_1_char, L_copy_1_char_exit;
6953
6954 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
6955 int short_mask = ascii ? 0xff80 : 0xff00;
6956
6957 // set result
6958 xorl(result, result);
6959 // check for zero length
6960 testl(len, len);
6961 jcc(Assembler::zero, L_done);
6962
6963 movl(result, len);
6964
6965 // Setup pointers
6966 lea(src, Address(src, len, Address::times_2)); // char[]
6967 lea(dst, Address(dst, len, Address::times_1)); // byte[]
6968 negptr(len);
6969
6970 if (UseSSE42Intrinsics || UseAVX >= 2) {
6971 Label L_copy_8_chars, L_copy_8_chars_exit;
6972 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
6973
6974 if (UseAVX >= 2) {
6975 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
6976 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6977 movdl(tmp1Reg, tmp5);
6978 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
6979 jmp(L_chars_32_check);
6980
6981 bind(L_copy_32_chars);
6982 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
6983 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
6984 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6985 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6986 jccb(Assembler::notZero, L_copy_32_chars_exit);
6987 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6988 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
6989 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
6990
6991 bind(L_chars_32_check);
6992 addptr(len, 32);
6993 jcc(Assembler::lessEqual, L_copy_32_chars);
6994
6995 bind(L_copy_32_chars_exit);
6996 subptr(len, 16);
6997 jccb(Assembler::greater, L_copy_16_chars_exit);
6998
6999 } else if (UseSSE42Intrinsics) {
7000 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7001 movdl(tmp1Reg, tmp5);
7002 pshufd(tmp1Reg, tmp1Reg, 0);
7003 jmpb(L_chars_16_check);
7004 }
7005
7006 bind(L_copy_16_chars);
7007 if (UseAVX >= 2) {
7008 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7009 vptest(tmp2Reg, tmp1Reg);
7010 jcc(Assembler::notZero, L_copy_16_chars_exit);
7011 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7012 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7013 } else {
7014 if (UseAVX > 0) {
7015 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7016 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7017 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7018 } else {
7019 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7020 por(tmp2Reg, tmp3Reg);
7021 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7022 por(tmp2Reg, tmp4Reg);
7023 }
7024 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7025 jccb(Assembler::notZero, L_copy_16_chars_exit);
7026 packuswb(tmp3Reg, tmp4Reg);
7027 }
7028 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7029
7030 bind(L_chars_16_check);
7031 addptr(len, 16);
7032 jcc(Assembler::lessEqual, L_copy_16_chars);
7033
7034 bind(L_copy_16_chars_exit);
7035 if (UseAVX >= 2) {
7036 // clean upper bits of YMM registers
7037 vpxor(tmp2Reg, tmp2Reg);
7038 vpxor(tmp3Reg, tmp3Reg);
7039 vpxor(tmp4Reg, tmp4Reg);
7040 movdl(tmp1Reg, tmp5);
7041 pshufd(tmp1Reg, tmp1Reg, 0);
7042 }
7043 subptr(len, 8);
7044 jccb(Assembler::greater, L_copy_8_chars_exit);
7045
7046 bind(L_copy_8_chars);
7047 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7048 ptest(tmp3Reg, tmp1Reg);
7049 jccb(Assembler::notZero, L_copy_8_chars_exit);
7050 packuswb(tmp3Reg, tmp1Reg);
7051 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7052 addptr(len, 8);
7053 jccb(Assembler::lessEqual, L_copy_8_chars);
7054
7055 bind(L_copy_8_chars_exit);
7056 subptr(len, 8);
7057 jccb(Assembler::zero, L_done);
7058 }
7059
7060 bind(L_copy_1_char);
7061 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7062 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
7063 jccb(Assembler::notZero, L_copy_1_char_exit);
7064 movb(Address(dst, len, Address::times_1, 0), tmp5);
7065 addptr(len, 1);
7066 jccb(Assembler::less, L_copy_1_char);
7067
7068 bind(L_copy_1_char_exit);
7069 addptr(result, len); // len is negative count of not processed elements
7070
7071 bind(L_done);
7072 }
7073
7074 #ifdef _LP64
7075 /**
7076 * Helper for multiply_to_len().
7077 */
7078 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7079 addq(dest_lo, src1);
7080 adcq(dest_hi, 0);
7081 addq(dest_lo, src2);
7082 adcq(dest_hi, 0);
7083 }
7084
7085 /**
7086 * Multiply 64 bit by 64 bit first loop.
7087 */
7088 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7089 Register y, Register y_idx, Register z,
7090 Register carry, Register product,
7091 Register idx, Register kdx) {
7092 //
7093 // jlong carry, x[], y[], z[];
7094 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7095 // huge_128 product = y[idx] * x[xstart] + carry;
7096 // z[kdx] = (jlong)product;
7097 // carry = (jlong)(product >>> 64);
7098 // }
7099 // z[xstart] = carry;
7100 //
7101
7102 Label L_first_loop, L_first_loop_exit;
7103 Label L_one_x, L_one_y, L_multiply;
7104
7105 decrementl(xstart);
7106 jcc(Assembler::negative, L_one_x);
7107
7108 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7109 rorq(x_xstart, 32); // convert big-endian to little-endian
7110
7111 bind(L_first_loop);
7112 decrementl(idx);
7113 jcc(Assembler::negative, L_first_loop_exit);
7114 decrementl(idx);
7115 jcc(Assembler::negative, L_one_y);
7116 movq(y_idx, Address(y, idx, Address::times_4, 0));
7117 rorq(y_idx, 32); // convert big-endian to little-endian
7118 bind(L_multiply);
7119 movq(product, x_xstart);
7120 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7121 addq(product, carry);
7122 adcq(rdx, 0);
7123 subl(kdx, 2);
7124 movl(Address(z, kdx, Address::times_4, 4), product);
7125 shrq(product, 32);
7126 movl(Address(z, kdx, Address::times_4, 0), product);
7127 movq(carry, rdx);
7128 jmp(L_first_loop);
7129
7130 bind(L_one_y);
7131 movl(y_idx, Address(y, 0));
7132 jmp(L_multiply);
7133
7134 bind(L_one_x);
7135 movl(x_xstart, Address(x, 0));
7136 jmp(L_first_loop);
7137
7138 bind(L_first_loop_exit);
7139 }
7140
7141 /**
7142 * Multiply 64 bit by 64 bit and add 128 bit.
7143 */
7144 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7145 Register yz_idx, Register idx,
7146 Register carry, Register product, int offset) {
7147 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7148 // z[kdx] = (jlong)product;
7149
7150 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7151 rorq(yz_idx, 32); // convert big-endian to little-endian
7152 movq(product, x_xstart);
7153 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7154 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7155 rorq(yz_idx, 32); // convert big-endian to little-endian
7156
7157 add2_with_carry(rdx, product, carry, yz_idx);
7158
7159 movl(Address(z, idx, Address::times_4, offset+4), product);
7160 shrq(product, 32);
7161 movl(Address(z, idx, Address::times_4, offset), product);
7162
7163 }
7164
7165 /**
7166 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7167 */
7168 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7169 Register yz_idx, Register idx, Register jdx,
7170 Register carry, Register product,
7171 Register carry2) {
7172 // jlong carry, x[], y[], z[];
7173 // int kdx = ystart+1;
7174 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7175 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7176 // z[kdx+idx+1] = (jlong)product;
7177 // jlong carry2 = (jlong)(product >>> 64);
7178 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7179 // z[kdx+idx] = (jlong)product;
7180 // carry = (jlong)(product >>> 64);
7181 // }
7182 // idx += 2;
7183 // if (idx > 0) {
7184 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7185 // z[kdx+idx] = (jlong)product;
7186 // carry = (jlong)(product >>> 64);
7187 // }
7188 //
7189
7190 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7191
7192 movl(jdx, idx);
7193 andl(jdx, 0xFFFFFFFC);
7194 shrl(jdx, 2);
7195
7196 bind(L_third_loop);
7197 subl(jdx, 1);
7198 jcc(Assembler::negative, L_third_loop_exit);
7199 subl(idx, 4);
7200
7201 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7202 movq(carry2, rdx);
7203
7204 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7205 movq(carry, rdx);
7206 jmp(L_third_loop);
7207
7208 bind (L_third_loop_exit);
7209
7210 andl (idx, 0x3);
7211 jcc(Assembler::zero, L_post_third_loop_done);
7212
7213 Label L_check_1;
7214 subl(idx, 2);
7215 jcc(Assembler::negative, L_check_1);
7216
7217 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7218 movq(carry, rdx);
7219
7220 bind (L_check_1);
7221 addl (idx, 0x2);
7222 andl (idx, 0x1);
7223 subl(idx, 1);
7224 jcc(Assembler::negative, L_post_third_loop_done);
7225
7226 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7227 movq(product, x_xstart);
7228 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7229 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7230
7231 add2_with_carry(rdx, product, yz_idx, carry);
7232
7233 movl(Address(z, idx, Address::times_4, 0), product);
7234 shrq(product, 32);
7235
7236 shlq(rdx, 32);
7237 orq(product, rdx);
7238 movq(carry, product);
7239
7240 bind(L_post_third_loop_done);
7241 }
7242
7243 /**
7244 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7245 *
7246 */
7247 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7248 Register carry, Register carry2,
7249 Register idx, Register jdx,
7250 Register yz_idx1, Register yz_idx2,
7251 Register tmp, Register tmp3, Register tmp4) {
7252 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7253
7254 // jlong carry, x[], y[], z[];
7255 // int kdx = ystart+1;
7256 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7257 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7258 // jlong carry2 = (jlong)(tmp3 >>> 64);
7259 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7260 // carry = (jlong)(tmp4 >>> 64);
7261 // z[kdx+idx+1] = (jlong)tmp3;
7262 // z[kdx+idx] = (jlong)tmp4;
7263 // }
7264 // idx += 2;
7265 // if (idx > 0) {
7266 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7267 // z[kdx+idx] = (jlong)yz_idx1;
7268 // carry = (jlong)(yz_idx1 >>> 64);
7269 // }
7270 //
7271
7272 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7273
7274 movl(jdx, idx);
7275 andl(jdx, 0xFFFFFFFC);
7276 shrl(jdx, 2);
7277
7278 bind(L_third_loop);
7279 subl(jdx, 1);
7280 jcc(Assembler::negative, L_third_loop_exit);
7281 subl(idx, 4);
7282
7283 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7284 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7285 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7286 rorxq(yz_idx2, yz_idx2, 32);
7287
7288 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7289 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7290
7291 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7292 rorxq(yz_idx1, yz_idx1, 32);
7293 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7294 rorxq(yz_idx2, yz_idx2, 32);
7295
7296 if (VM_Version::supports_adx()) {
7297 adcxq(tmp3, carry);
7298 adoxq(tmp3, yz_idx1);
7299
7300 adcxq(tmp4, tmp);
7301 adoxq(tmp4, yz_idx2);
7302
7303 movl(carry, 0); // does not affect flags
7304 adcxq(carry2, carry);
7305 adoxq(carry2, carry);
7306 } else {
7307 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7308 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7309 }
7310 movq(carry, carry2);
7311
7312 movl(Address(z, idx, Address::times_4, 12), tmp3);
7313 shrq(tmp3, 32);
7314 movl(Address(z, idx, Address::times_4, 8), tmp3);
7315
7316 movl(Address(z, idx, Address::times_4, 4), tmp4);
7317 shrq(tmp4, 32);
7318 movl(Address(z, idx, Address::times_4, 0), tmp4);
7319
7320 jmp(L_third_loop);
7321
7322 bind (L_third_loop_exit);
7323
7324 andl (idx, 0x3);
7325 jcc(Assembler::zero, L_post_third_loop_done);
7326
7327 Label L_check_1;
7328 subl(idx, 2);
7329 jcc(Assembler::negative, L_check_1);
7330
7331 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7332 rorxq(yz_idx1, yz_idx1, 32);
7333 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7334 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7335 rorxq(yz_idx2, yz_idx2, 32);
7336
7337 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7338
7339 movl(Address(z, idx, Address::times_4, 4), tmp3);
7340 shrq(tmp3, 32);
7341 movl(Address(z, idx, Address::times_4, 0), tmp3);
7342 movq(carry, tmp4);
7343
7344 bind (L_check_1);
7345 addl (idx, 0x2);
7346 andl (idx, 0x1);
7347 subl(idx, 1);
7348 jcc(Assembler::negative, L_post_third_loop_done);
7349 movl(tmp4, Address(y, idx, Address::times_4, 0));
7350 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7351 movl(tmp4, Address(z, idx, Address::times_4, 0));
7352
7353 add2_with_carry(carry2, tmp3, tmp4, carry);
7354
7355 movl(Address(z, idx, Address::times_4, 0), tmp3);
7356 shrq(tmp3, 32);
7357
7358 shlq(carry2, 32);
7359 orq(tmp3, carry2);
7360 movq(carry, tmp3);
7361
7362 bind(L_post_third_loop_done);
7363 }
7364
7365 /**
7366 * Code for BigInteger::multiplyToLen() intrinsic.
7367 *
7368 * rdi: x
7369 * rax: xlen
7370 * rsi: y
7371 * rcx: ylen
7372 * r8: z
7373 * r11: tmp0
7374 * r12: tmp1
7375 * r13: tmp2
7376 * r14: tmp3
7377 * r15: tmp4
7378 * rbx: tmp5
7379 *
7380 */
7381 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7382 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7383 ShortBranchVerifier sbv(this);
7384 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7385
7386 push(tmp0);
7387 push(tmp1);
7388 push(tmp2);
7389 push(tmp3);
7390 push(tmp4);
7391 push(tmp5);
7392
7393 push(xlen);
7394
7395 const Register idx = tmp1;
7396 const Register kdx = tmp2;
7397 const Register xstart = tmp3;
7398
7399 const Register y_idx = tmp4;
7400 const Register carry = tmp5;
7401 const Register product = xlen;
7402 const Register x_xstart = tmp0;
7403
7404 // First Loop.
7405 //
7406 // final static long LONG_MASK = 0xffffffffL;
7407 // int xstart = xlen - 1;
7408 // int ystart = ylen - 1;
7409 // long carry = 0;
7410 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7411 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7412 // z[kdx] = (int)product;
7413 // carry = product >>> 32;
7414 // }
7415 // z[xstart] = (int)carry;
7416 //
7417
7418 movl(idx, ylen); // idx = ylen;
7419 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7420 xorq(carry, carry); // carry = 0;
7421
7422 Label L_done;
7423
7424 movl(xstart, xlen);
7425 decrementl(xstart);
7426 jcc(Assembler::negative, L_done);
7427
7428 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7429
7430 Label L_second_loop;
7431 testl(kdx, kdx);
7432 jcc(Assembler::zero, L_second_loop);
7433
7434 Label L_carry;
7435 subl(kdx, 1);
7436 jcc(Assembler::zero, L_carry);
7437
7438 movl(Address(z, kdx, Address::times_4, 0), carry);
7439 shrq(carry, 32);
7440 subl(kdx, 1);
7441
7442 bind(L_carry);
7443 movl(Address(z, kdx, Address::times_4, 0), carry);
7444
7445 // Second and third (nested) loops.
7446 //
7447 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7448 // carry = 0;
7449 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7450 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7451 // (z[k] & LONG_MASK) + carry;
7452 // z[k] = (int)product;
7453 // carry = product >>> 32;
7454 // }
7455 // z[i] = (int)carry;
7456 // }
7457 //
7458 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7459
7460 const Register jdx = tmp1;
7461
7462 bind(L_second_loop);
7463 xorl(carry, carry); // carry = 0;
7464 movl(jdx, ylen); // j = ystart+1
7465
7466 subl(xstart, 1); // i = xstart-1;
7467 jcc(Assembler::negative, L_done);
7468
7469 push (z);
7470
7471 Label L_last_x;
7472 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7473 subl(xstart, 1); // i = xstart-1;
7474 jcc(Assembler::negative, L_last_x);
7475
7476 if (UseBMI2Instructions) {
7477 movq(rdx, Address(x, xstart, Address::times_4, 0));
7478 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7479 } else {
7480 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7481 rorq(x_xstart, 32); // convert big-endian to little-endian
7482 }
7483
7484 Label L_third_loop_prologue;
7485 bind(L_third_loop_prologue);
7486
7487 push (x);
7488 push (xstart);
7489 push (ylen);
7490
7491
7492 if (UseBMI2Instructions) {
7493 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7494 } else { // !UseBMI2Instructions
7495 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7496 }
7497
7498 pop(ylen);
7499 pop(xlen);
7500 pop(x);
7501 pop(z);
7502
7503 movl(tmp3, xlen);
7504 addl(tmp3, 1);
7505 movl(Address(z, tmp3, Address::times_4, 0), carry);
7506 subl(tmp3, 1);
7507 jccb(Assembler::negative, L_done);
7508
7509 shrq(carry, 32);
7510 movl(Address(z, tmp3, Address::times_4, 0), carry);
7511 jmp(L_second_loop);
7512
7513 // Next infrequent code is moved outside loops.
7514 bind(L_last_x);
7515 if (UseBMI2Instructions) {
7516 movl(rdx, Address(x, 0));
7517 } else {
7518 movl(x_xstart, Address(x, 0));
7519 }
7520 jmp(L_third_loop_prologue);
7521
7522 bind(L_done);
7523
7524 pop(xlen);
7525
7526 pop(tmp5);
7527 pop(tmp4);
7528 pop(tmp3);
7529 pop(tmp2);
7530 pop(tmp1);
7531 pop(tmp0);
7532 }
7533
7534 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7535 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7536 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7537 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7538 Label VECTOR8_TAIL, VECTOR4_TAIL;
7539 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7540 Label SAME_TILL_END, DONE;
7541 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7542
7543 //scale is in rcx in both Win64 and Unix
7544 ShortBranchVerifier sbv(this);
7545
7546 shlq(length);
7547 xorq(result, result);
7548
7549 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7550 VM_Version::supports_avx512vlbw()) {
7551 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7552
7553 cmpq(length, 64);
7554 jcc(Assembler::less, VECTOR32_TAIL);
7555
7556 movq(tmp1, length);
7557 andq(tmp1, 0x3F); // tail count
7558 andq(length, ~(0x3F)); //vector count
7559
7560 bind(VECTOR64_LOOP);
7561 // AVX512 code to compare 64 byte vectors.
7562 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7563 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7564 kortestql(k7, k7);
7565 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7566 addq(result, 64);
7567 subq(length, 64);
7568 jccb(Assembler::notZero, VECTOR64_LOOP);
7569
7570 //bind(VECTOR64_TAIL);
7571 testq(tmp1, tmp1);
7572 jcc(Assembler::zero, SAME_TILL_END);
7573
7574 //bind(VECTOR64_TAIL);
7575 // AVX512 code to compare up to 63 byte vectors.
7576 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7577 shlxq(tmp2, tmp2, tmp1);
7578 notq(tmp2);
7579 kmovql(k3, tmp2);
7580
7581 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7582 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7583
7584 ktestql(k7, k3);
7585 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7586
7587 bind(VECTOR64_NOT_EQUAL);
7588 kmovql(tmp1, k7);
7589 notq(tmp1);
7590 tzcntq(tmp1, tmp1);
7591 addq(result, tmp1);
7592 shrq(result);
7593 jmp(DONE);
7594 bind(VECTOR32_TAIL);
7595 }
7596
7597 cmpq(length, 8);
7598 jcc(Assembler::equal, VECTOR8_LOOP);
7599 jcc(Assembler::less, VECTOR4_TAIL);
7600
7601 if (UseAVX >= 2) {
7602 Label VECTOR16_TAIL, VECTOR32_LOOP;
7603
7604 cmpq(length, 16);
7605 jcc(Assembler::equal, VECTOR16_LOOP);
7606 jcc(Assembler::less, VECTOR8_LOOP);
7607
7608 cmpq(length, 32);
7609 jccb(Assembler::less, VECTOR16_TAIL);
7610
7611 subq(length, 32);
7612 bind(VECTOR32_LOOP);
7613 vmovdqu(rymm0, Address(obja, result));
7614 vmovdqu(rymm1, Address(objb, result));
7615 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7616 vptest(rymm2, rymm2);
7617 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7618 addq(result, 32);
7619 subq(length, 32);
7620 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7621 addq(length, 32);
7622 jcc(Assembler::equal, SAME_TILL_END);
7623 //falling through if less than 32 bytes left //close the branch here.
7624
7625 bind(VECTOR16_TAIL);
7626 cmpq(length, 16);
7627 jccb(Assembler::less, VECTOR8_TAIL);
7628 bind(VECTOR16_LOOP);
7629 movdqu(rymm0, Address(obja, result));
7630 movdqu(rymm1, Address(objb, result));
7631 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7632 ptest(rymm2, rymm2);
7633 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7634 addq(result, 16);
7635 subq(length, 16);
7636 jcc(Assembler::equal, SAME_TILL_END);
7637 //falling through if less than 16 bytes left
7638 } else {//regular intrinsics
7639
7640 cmpq(length, 16);
7641 jccb(Assembler::less, VECTOR8_TAIL);
7642
7643 subq(length, 16);
7644 bind(VECTOR16_LOOP);
7645 movdqu(rymm0, Address(obja, result));
7646 movdqu(rymm1, Address(objb, result));
7647 pxor(rymm0, rymm1);
7648 ptest(rymm0, rymm0);
7649 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7650 addq(result, 16);
7651 subq(length, 16);
7652 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7653 addq(length, 16);
7654 jcc(Assembler::equal, SAME_TILL_END);
7655 //falling through if less than 16 bytes left
7656 }
7657
7658 bind(VECTOR8_TAIL);
7659 cmpq(length, 8);
7660 jccb(Assembler::less, VECTOR4_TAIL);
7661 bind(VECTOR8_LOOP);
7662 movq(tmp1, Address(obja, result));
7663 movq(tmp2, Address(objb, result));
7664 xorq(tmp1, tmp2);
7665 testq(tmp1, tmp1);
7666 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7667 addq(result, 8);
7668 subq(length, 8);
7669 jcc(Assembler::equal, SAME_TILL_END);
7670 //falling through if less than 8 bytes left
7671
7672 bind(VECTOR4_TAIL);
7673 cmpq(length, 4);
7674 jccb(Assembler::less, BYTES_TAIL);
7675 bind(VECTOR4_LOOP);
7676 movl(tmp1, Address(obja, result));
7677 xorl(tmp1, Address(objb, result));
7678 testl(tmp1, tmp1);
7679 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7680 addq(result, 4);
7681 subq(length, 4);
7682 jcc(Assembler::equal, SAME_TILL_END);
7683 //falling through if less than 4 bytes left
7684
7685 bind(BYTES_TAIL);
7686 bind(BYTES_LOOP);
7687 load_unsigned_byte(tmp1, Address(obja, result));
7688 load_unsigned_byte(tmp2, Address(objb, result));
7689 xorl(tmp1, tmp2);
7690 testl(tmp1, tmp1);
7691 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7692 decq(length);
7693 jcc(Assembler::zero, SAME_TILL_END);
7694 incq(result);
7695 load_unsigned_byte(tmp1, Address(obja, result));
7696 load_unsigned_byte(tmp2, Address(objb, result));
7697 xorl(tmp1, tmp2);
7698 testl(tmp1, tmp1);
7699 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7700 decq(length);
7701 jcc(Assembler::zero, SAME_TILL_END);
7702 incq(result);
7703 load_unsigned_byte(tmp1, Address(obja, result));
7704 load_unsigned_byte(tmp2, Address(objb, result));
7705 xorl(tmp1, tmp2);
7706 testl(tmp1, tmp1);
7707 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7708 jmp(SAME_TILL_END);
7709
7710 if (UseAVX >= 2) {
7711 bind(VECTOR32_NOT_EQUAL);
7712 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7713 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7714 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7715 vpmovmskb(tmp1, rymm0);
7716 bsfq(tmp1, tmp1);
7717 addq(result, tmp1);
7718 shrq(result);
7719 jmp(DONE);
7720 }
7721
7722 bind(VECTOR16_NOT_EQUAL);
7723 if (UseAVX >= 2) {
7724 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7725 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7726 pxor(rymm0, rymm2);
7727 } else {
7728 pcmpeqb(rymm2, rymm2);
7729 pxor(rymm0, rymm1);
7730 pcmpeqb(rymm0, rymm1);
7731 pxor(rymm0, rymm2);
7732 }
7733 pmovmskb(tmp1, rymm0);
7734 bsfq(tmp1, tmp1);
7735 addq(result, tmp1);
7736 shrq(result);
7737 jmpb(DONE);
7738
7739 bind(VECTOR8_NOT_EQUAL);
7740 bind(VECTOR4_NOT_EQUAL);
7741 bsfq(tmp1, tmp1);
7742 shrq(tmp1, 3);
7743 addq(result, tmp1);
7744 bind(BYTES_NOT_EQUAL);
7745 shrq(result);
7746 jmpb(DONE);
7747
7748 bind(SAME_TILL_END);
7749 mov64(result, -1);
7750
7751 bind(DONE);
7752 }
7753
7754 //Helper functions for square_to_len()
7755
7756 /**
7757 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7758 * Preserves x and z and modifies rest of the registers.
7759 */
7760 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7761 // Perform square and right shift by 1
7762 // Handle odd xlen case first, then for even xlen do the following
7763 // jlong carry = 0;
7764 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7765 // huge_128 product = x[j:j+1] * x[j:j+1];
7766 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7767 // z[i+2:i+3] = (jlong)(product >>> 1);
7768 // carry = (jlong)product;
7769 // }
7770
7771 xorq(tmp5, tmp5); // carry
7772 xorq(rdxReg, rdxReg);
7773 xorl(tmp1, tmp1); // index for x
7774 xorl(tmp4, tmp4); // index for z
7775
7776 Label L_first_loop, L_first_loop_exit;
7777
7778 testl(xlen, 1);
7779 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7780
7781 // Square and right shift by 1 the odd element using 32 bit multiply
7782 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7783 imulq(raxReg, raxReg);
7784 shrq(raxReg, 1);
7785 adcq(tmp5, 0);
7786 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7787 incrementl(tmp1);
7788 addl(tmp4, 2);
7789
7790 // Square and right shift by 1 the rest using 64 bit multiply
7791 bind(L_first_loop);
7792 cmpptr(tmp1, xlen);
7793 jccb(Assembler::equal, L_first_loop_exit);
7794
7795 // Square
7796 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7797 rorq(raxReg, 32); // convert big-endian to little-endian
7798 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7799
7800 // Right shift by 1 and save carry
7801 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7802 rcrq(rdxReg, 1);
7803 rcrq(raxReg, 1);
7804 adcq(tmp5, 0);
7805
7806 // Store result in z
7807 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7808 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7809
7810 // Update indices for x and z
7811 addl(tmp1, 2);
7812 addl(tmp4, 4);
7813 jmp(L_first_loop);
7814
7815 bind(L_first_loop_exit);
7816 }
7817
7818
7819 /**
7820 * Perform the following multiply add operation using BMI2 instructions
7821 * carry:sum = sum + op1*op2 + carry
7822 * op2 should be in rdx
7823 * op2 is preserved, all other registers are modified
7824 */
7825 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7826 // assert op2 is rdx
7827 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7828 addq(sum, carry);
7829 adcq(tmp2, 0);
7830 addq(sum, op1);
7831 adcq(tmp2, 0);
7832 movq(carry, tmp2);
7833 }
7834
7835 /**
7836 * Perform the following multiply add operation:
7837 * carry:sum = sum + op1*op2 + carry
7838 * Preserves op1, op2 and modifies rest of registers
7839 */
7840 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7841 // rdx:rax = op1 * op2
7842 movq(raxReg, op2);
7843 mulq(op1);
7844
7845 // rdx:rax = sum + carry + rdx:rax
7846 addq(sum, carry);
7847 adcq(rdxReg, 0);
7848 addq(sum, raxReg);
7849 adcq(rdxReg, 0);
7850
7851 // carry:sum = rdx:sum
7852 movq(carry, rdxReg);
7853 }
7854
7855 /**
7856 * Add 64 bit long carry into z[] with carry propagation.
7857 * Preserves z and carry register values and modifies rest of registers.
7858 *
7859 */
7860 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7861 Label L_fourth_loop, L_fourth_loop_exit;
7862
7863 movl(tmp1, 1);
7864 subl(zlen, 2);
7865 addq(Address(z, zlen, Address::times_4, 0), carry);
7866
7867 bind(L_fourth_loop);
7868 jccb(Assembler::carryClear, L_fourth_loop_exit);
7869 subl(zlen, 2);
7870 jccb(Assembler::negative, L_fourth_loop_exit);
7871 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7872 jmp(L_fourth_loop);
7873 bind(L_fourth_loop_exit);
7874 }
7875
7876 /**
7877 * Shift z[] left by 1 bit.
7878 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7879 *
7880 */
7881 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7882
7883 Label L_fifth_loop, L_fifth_loop_exit;
7884
7885 // Fifth loop
7886 // Perform primitiveLeftShift(z, zlen, 1)
7887
7888 const Register prev_carry = tmp1;
7889 const Register new_carry = tmp4;
7890 const Register value = tmp2;
7891 const Register zidx = tmp3;
7892
7893 // int zidx, carry;
7894 // long value;
7895 // carry = 0;
7896 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7897 // (carry:value) = (z[i] << 1) | carry ;
7898 // z[i] = value;
7899 // }
7900
7901 movl(zidx, zlen);
7902 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7903
7904 bind(L_fifth_loop);
7905 decl(zidx); // Use decl to preserve carry flag
7906 decl(zidx);
7907 jccb(Assembler::negative, L_fifth_loop_exit);
7908
7909 if (UseBMI2Instructions) {
7910 movq(value, Address(z, zidx, Address::times_4, 0));
7911 rclq(value, 1);
7912 rorxq(value, value, 32);
7913 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7914 }
7915 else {
7916 // clear new_carry
7917 xorl(new_carry, new_carry);
7918
7919 // Shift z[i] by 1, or in previous carry and save new carry
7920 movq(value, Address(z, zidx, Address::times_4, 0));
7921 shlq(value, 1);
7922 adcl(new_carry, 0);
7923
7924 orq(value, prev_carry);
7925 rorq(value, 0x20);
7926 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7927
7928 // Set previous carry = new carry
7929 movl(prev_carry, new_carry);
7930 }
7931 jmp(L_fifth_loop);
7932
7933 bind(L_fifth_loop_exit);
7934 }
7935
7936
7937 /**
7938 * Code for BigInteger::squareToLen() intrinsic
7939 *
7940 * rdi: x
7941 * rsi: len
7942 * r8: z
7943 * rcx: zlen
7944 * r12: tmp1
7945 * r13: tmp2
7946 * r14: tmp3
7947 * r15: tmp4
7948 * rbx: tmp5
7949 *
7950 */
7951 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7952
7953 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
7954 push(tmp1);
7955 push(tmp2);
7956 push(tmp3);
7957 push(tmp4);
7958 push(tmp5);
7959
7960 // First loop
7961 // Store the squares, right shifted one bit (i.e., divided by 2).
7962 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7963
7964 // Add in off-diagonal sums.
7965 //
7966 // Second, third (nested) and fourth loops.
7967 // zlen +=2;
7968 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7969 // carry = 0;
7970 // long op2 = x[xidx:xidx+1];
7971 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7972 // k -= 2;
7973 // long op1 = x[j:j+1];
7974 // long sum = z[k:k+1];
7975 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7976 // z[k:k+1] = sum;
7977 // }
7978 // add_one_64(z, k, carry, tmp_regs);
7979 // }
7980
7981 const Register carry = tmp5;
7982 const Register sum = tmp3;
7983 const Register op1 = tmp4;
7984 Register op2 = tmp2;
7985
7986 push(zlen);
7987 push(len);
7988 addl(zlen,2);
7989 bind(L_second_loop);
7990 xorq(carry, carry);
7991 subl(zlen, 4);
7992 subl(len, 2);
7993 push(zlen);
7994 push(len);
7995 cmpl(len, 0);
7996 jccb(Assembler::lessEqual, L_second_loop_exit);
7997
7998 // Multiply an array by one 64 bit long.
7999 if (UseBMI2Instructions) {
8000 op2 = rdxReg;
8001 movq(op2, Address(x, len, Address::times_4, 0));
8002 rorxq(op2, op2, 32);
8003 }
8004 else {
8005 movq(op2, Address(x, len, Address::times_4, 0));
8006 rorq(op2, 32);
8007 }
8008
8009 bind(L_third_loop);
8010 decrementl(len);
8011 jccb(Assembler::negative, L_third_loop_exit);
8012 decrementl(len);
8013 jccb(Assembler::negative, L_last_x);
8014
8015 movq(op1, Address(x, len, Address::times_4, 0));
8016 rorq(op1, 32);
8017
8018 bind(L_multiply);
8019 subl(zlen, 2);
8020 movq(sum, Address(z, zlen, Address::times_4, 0));
8021
8022 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8023 if (UseBMI2Instructions) {
8024 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8025 }
8026 else {
8027 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8028 }
8029
8030 movq(Address(z, zlen, Address::times_4, 0), sum);
8031
8032 jmp(L_third_loop);
8033 bind(L_third_loop_exit);
8034
8035 // Fourth loop
8036 // Add 64 bit long carry into z with carry propagation.
8037 // Uses offsetted zlen.
8038 add_one_64(z, zlen, carry, tmp1);
8039
8040 pop(len);
8041 pop(zlen);
8042 jmp(L_second_loop);
8043
8044 // Next infrequent code is moved outside loops.
8045 bind(L_last_x);
8046 movl(op1, Address(x, 0));
8047 jmp(L_multiply);
8048
8049 bind(L_second_loop_exit);
8050 pop(len);
8051 pop(zlen);
8052 pop(len);
8053 pop(zlen);
8054
8055 // Fifth loop
8056 // Shift z left 1 bit.
8057 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8058
8059 // z[zlen-1] |= x[len-1] & 1;
8060 movl(tmp3, Address(x, len, Address::times_4, -4));
8061 andl(tmp3, 1);
8062 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8063
8064 pop(tmp5);
8065 pop(tmp4);
8066 pop(tmp3);
8067 pop(tmp2);
8068 pop(tmp1);
8069 }
8070
8071 /**
8072 * Helper function for mul_add()
8073 * Multiply the in[] by int k and add to out[] starting at offset offs using
8074 * 128 bit by 32 bit multiply and return the carry in tmp5.
8075 * Only quad int aligned length of in[] is operated on in this function.
8076 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8077 * This function preserves out, in and k registers.
8078 * len and offset point to the appropriate index in "in" & "out" correspondingly
8079 * tmp5 has the carry.
8080 * other registers are temporary and are modified.
8081 *
8082 */
8083 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8084 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8085 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8086
8087 Label L_first_loop, L_first_loop_exit;
8088
8089 movl(tmp1, len);
8090 shrl(tmp1, 2);
8091
8092 bind(L_first_loop);
8093 subl(tmp1, 1);
8094 jccb(Assembler::negative, L_first_loop_exit);
8095
8096 subl(len, 4);
8097 subl(offset, 4);
8098
8099 Register op2 = tmp2;
8100 const Register sum = tmp3;
8101 const Register op1 = tmp4;
8102 const Register carry = tmp5;
8103
8104 if (UseBMI2Instructions) {
8105 op2 = rdxReg;
8106 }
8107
8108 movq(op1, Address(in, len, Address::times_4, 8));
8109 rorq(op1, 32);
8110 movq(sum, Address(out, offset, Address::times_4, 8));
8111 rorq(sum, 32);
8112 if (UseBMI2Instructions) {
8113 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8114 }
8115 else {
8116 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8117 }
8118 // Store back in big endian from little endian
8119 rorq(sum, 0x20);
8120 movq(Address(out, offset, Address::times_4, 8), sum);
8121
8122 movq(op1, Address(in, len, Address::times_4, 0));
8123 rorq(op1, 32);
8124 movq(sum, Address(out, offset, Address::times_4, 0));
8125 rorq(sum, 32);
8126 if (UseBMI2Instructions) {
8127 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8128 }
8129 else {
8130 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8131 }
8132 // Store back in big endian from little endian
8133 rorq(sum, 0x20);
8134 movq(Address(out, offset, Address::times_4, 0), sum);
8135
8136 jmp(L_first_loop);
8137 bind(L_first_loop_exit);
8138 }
8139
8140 /**
8141 * Code for BigInteger::mulAdd() intrinsic
8142 *
8143 * rdi: out
8144 * rsi: in
8145 * r11: offs (out.length - offset)
8146 * rcx: len
8147 * r8: k
8148 * r12: tmp1
8149 * r13: tmp2
8150 * r14: tmp3
8151 * r15: tmp4
8152 * rbx: tmp5
8153 * Multiply the in[] by word k and add to out[], return the carry in rax
8154 */
8155 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8156 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8157 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8158
8159 Label L_carry, L_last_in, L_done;
8160
8161 // carry = 0;
8162 // for (int j=len-1; j >= 0; j--) {
8163 // long product = (in[j] & LONG_MASK) * kLong +
8164 // (out[offs] & LONG_MASK) + carry;
8165 // out[offs--] = (int)product;
8166 // carry = product >>> 32;
8167 // }
8168 //
8169 push(tmp1);
8170 push(tmp2);
8171 push(tmp3);
8172 push(tmp4);
8173 push(tmp5);
8174
8175 Register op2 = tmp2;
8176 const Register sum = tmp3;
8177 const Register op1 = tmp4;
8178 const Register carry = tmp5;
8179
8180 if (UseBMI2Instructions) {
8181 op2 = rdxReg;
8182 movl(op2, k);
8183 }
8184 else {
8185 movl(op2, k);
8186 }
8187
8188 xorq(carry, carry);
8189
8190 //First loop
8191
8192 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8193 //The carry is in tmp5
8194 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8195
8196 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8197 decrementl(len);
8198 jccb(Assembler::negative, L_carry);
8199 decrementl(len);
8200 jccb(Assembler::negative, L_last_in);
8201
8202 movq(op1, Address(in, len, Address::times_4, 0));
8203 rorq(op1, 32);
8204
8205 subl(offs, 2);
8206 movq(sum, Address(out, offs, Address::times_4, 0));
8207 rorq(sum, 32);
8208
8209 if (UseBMI2Instructions) {
8210 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8211 }
8212 else {
8213 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8214 }
8215
8216 // Store back in big endian from little endian
8217 rorq(sum, 0x20);
8218 movq(Address(out, offs, Address::times_4, 0), sum);
8219
8220 testl(len, len);
8221 jccb(Assembler::zero, L_carry);
8222
8223 //Multiply the last in[] entry, if any
8224 bind(L_last_in);
8225 movl(op1, Address(in, 0));
8226 movl(sum, Address(out, offs, Address::times_4, -4));
8227
8228 movl(raxReg, k);
8229 mull(op1); //tmp4 * eax -> edx:eax
8230 addl(sum, carry);
8231 adcl(rdxReg, 0);
8232 addl(sum, raxReg);
8233 adcl(rdxReg, 0);
8234 movl(carry, rdxReg);
8235
8236 movl(Address(out, offs, Address::times_4, -4), sum);
8237
8238 bind(L_carry);
8239 //return tmp5/carry as carry in rax
8240 movl(rax, carry);
8241
8242 bind(L_done);
8243 pop(tmp5);
8244 pop(tmp4);
8245 pop(tmp3);
8246 pop(tmp2);
8247 pop(tmp1);
8248 }
8249 #endif
8250
8251 /**
8252 * Emits code to update CRC-32 with a byte value according to constants in table
8253 *
8254 * @param [in,out]crc Register containing the crc.
8255 * @param [in]val Register containing the byte to fold into the CRC.
8256 * @param [in]table Register containing the table of crc constants.
8257 *
8258 * uint32_t crc;
8259 * val = crc_table[(val ^ crc) & 0xFF];
8260 * crc = val ^ (crc >> 8);
8261 *
8262 */
8263 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8264 xorl(val, crc);
8265 andl(val, 0xFF);
8266 shrl(crc, 8); // unsigned shift
8267 xorl(crc, Address(table, val, Address::times_4, 0));
8268 }
8269
8270 /**
8271 * Fold 128-bit data chunk
8272 */
8273 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8274 if (UseAVX > 0) {
8275 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8276 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8277 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8278 pxor(xcrc, xtmp);
8279 } else {
8280 movdqa(xtmp, xcrc);
8281 pclmulhdq(xtmp, xK); // [123:64]
8282 pclmulldq(xcrc, xK); // [63:0]
8283 pxor(xcrc, xtmp);
8284 movdqu(xtmp, Address(buf, offset));
8285 pxor(xcrc, xtmp);
8286 }
8287 }
8288
8289 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8290 if (UseAVX > 0) {
8291 vpclmulhdq(xtmp, xK, xcrc);
8292 vpclmulldq(xcrc, xK, xcrc);
8293 pxor(xcrc, xbuf);
8294 pxor(xcrc, xtmp);
8295 } else {
8296 movdqa(xtmp, xcrc);
8297 pclmulhdq(xtmp, xK);
8298 pclmulldq(xcrc, xK);
8299 pxor(xcrc, xbuf);
8300 pxor(xcrc, xtmp);
8301 }
8302 }
8303
8304 /**
8305 * 8-bit folds to compute 32-bit CRC
8306 *
8307 * uint64_t xcrc;
8308 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8309 */
8310 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8311 movdl(tmp, xcrc);
8312 andl(tmp, 0xFF);
8313 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8314 psrldq(xcrc, 1); // unsigned shift one byte
8315 pxor(xcrc, xtmp);
8316 }
8317
8318 /**
8319 * uint32_t crc;
8320 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8321 */
8322 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8323 movl(tmp, crc);
8324 andl(tmp, 0xFF);
8325 shrl(crc, 8);
8326 xorl(crc, Address(table, tmp, Address::times_4, 0));
8327 }
8328
8329 /**
8330 * @param crc register containing existing CRC (32-bit)
8331 * @param buf register pointing to input byte buffer (byte*)
8332 * @param len register containing number of bytes
8333 * @param table register that will contain address of CRC table
8334 * @param tmp scratch register
8335 */
8336 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8337 assert_different_registers(crc, buf, len, table, tmp, rax);
8338
8339 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8340 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8341
8342 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8343 // context for the registers used, where all instructions below are using 128-bit mode
8344 // On EVEX without VL and BW, these instructions will all be AVX.
8345 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8346 notl(crc); // ~crc
8347 cmpl(len, 16);
8348 jcc(Assembler::less, L_tail);
8349
8350 // Align buffer to 16 bytes
8351 movl(tmp, buf);
8352 andl(tmp, 0xF);
8353 jccb(Assembler::zero, L_aligned);
8354 subl(tmp, 16);
8355 addl(len, tmp);
8356
8357 align(4);
8358 BIND(L_align_loop);
8359 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8360 update_byte_crc32(crc, rax, table);
8361 increment(buf);
8362 incrementl(tmp);
8363 jccb(Assembler::less, L_align_loop);
8364
8365 BIND(L_aligned);
8366 movl(tmp, len); // save
8367 shrl(len, 4);
8368 jcc(Assembler::zero, L_tail_restore);
8369
8370 // Fold crc into first bytes of vector
8371 movdqa(xmm1, Address(buf, 0));
8372 movdl(rax, xmm1);
8373 xorl(crc, rax);
8374 if (VM_Version::supports_sse4_1()) {
8375 pinsrd(xmm1, crc, 0);
8376 } else {
8377 pinsrw(xmm1, crc, 0);
8378 shrl(crc, 16);
8379 pinsrw(xmm1, crc, 1);
8380 }
8381 addptr(buf, 16);
8382 subl(len, 4); // len > 0
8383 jcc(Assembler::less, L_fold_tail);
8384
8385 movdqa(xmm2, Address(buf, 0));
8386 movdqa(xmm3, Address(buf, 16));
8387 movdqa(xmm4, Address(buf, 32));
8388 addptr(buf, 48);
8389 subl(len, 3);
8390 jcc(Assembler::lessEqual, L_fold_512b);
8391
8392 // Fold total 512 bits of polynomial on each iteration,
8393 // 128 bits per each of 4 parallel streams.
8394 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8395
8396 align32();
8397 BIND(L_fold_512b_loop);
8398 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8399 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8400 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8401 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8402 addptr(buf, 64);
8403 subl(len, 4);
8404 jcc(Assembler::greater, L_fold_512b_loop);
8405
8406 // Fold 512 bits to 128 bits.
8407 BIND(L_fold_512b);
8408 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8409 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8410 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8411 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8412
8413 // Fold the rest of 128 bits data chunks
8414 BIND(L_fold_tail);
8415 addl(len, 3);
8416 jccb(Assembler::lessEqual, L_fold_128b);
8417 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8418
8419 BIND(L_fold_tail_loop);
8420 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8421 addptr(buf, 16);
8422 decrementl(len);
8423 jccb(Assembler::greater, L_fold_tail_loop);
8424
8425 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8426 BIND(L_fold_128b);
8427 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8428 if (UseAVX > 0) {
8429 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8430 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8431 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8432 } else {
8433 movdqa(xmm2, xmm0);
8434 pclmulqdq(xmm2, xmm1, 0x1);
8435 movdqa(xmm3, xmm0);
8436 pand(xmm3, xmm2);
8437 pclmulqdq(xmm0, xmm3, 0x1);
8438 }
8439 psrldq(xmm1, 8);
8440 psrldq(xmm2, 4);
8441 pxor(xmm0, xmm1);
8442 pxor(xmm0, xmm2);
8443
8444 // 8 8-bit folds to compute 32-bit CRC.
8445 for (int j = 0; j < 4; j++) {
8446 fold_8bit_crc32(xmm0, table, xmm1, rax);
8447 }
8448 movdl(crc, xmm0); // mov 32 bits to general register
8449 for (int j = 0; j < 4; j++) {
8450 fold_8bit_crc32(crc, table, rax);
8451 }
8452
8453 BIND(L_tail_restore);
8454 movl(len, tmp); // restore
8455 BIND(L_tail);
8456 andl(len, 0xf);
8457 jccb(Assembler::zero, L_exit);
8458
8459 // Fold the rest of bytes
8460 align(4);
8461 BIND(L_tail_loop);
8462 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8463 update_byte_crc32(crc, rax, table);
8464 increment(buf);
8465 decrementl(len);
8466 jccb(Assembler::greater, L_tail_loop);
8467
8468 BIND(L_exit);
8469 notl(crc); // ~c
8470 }
8471
8472 #ifdef _LP64
8473 // Helper function for AVX 512 CRC32
8474 // Fold 512-bit data chunks
8475 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8476 Register pos, int offset) {
8477 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8478 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8479 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8480 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8481 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8482 }
8483
8484 // Helper function for AVX 512 CRC32
8485 // Compute CRC32 for < 256B buffers
8486 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8487 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8488 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8489
8490 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8491 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8492 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8493
8494 // check if there is enough buffer to be able to fold 16B at a time
8495 cmpl(len, 32);
8496 jcc(Assembler::less, L_less_than_32);
8497
8498 // if there is, load the constants
8499 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8500 movdl(xmm0, crc); // get the initial crc value
8501 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8502 pxor(xmm7, xmm0);
8503
8504 // update the buffer pointer
8505 addl(pos, 16);
8506 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8507 subl(len, 32);
8508 jmp(L_16B_reduction_loop);
8509
8510 bind(L_less_than_32);
8511 //mov initial crc to the return value. this is necessary for zero - length buffers.
8512 movl(rax, crc);
8513 testl(len, len);
8514 jcc(Assembler::equal, L_cleanup);
8515
8516 movdl(xmm0, crc); //get the initial crc value
8517
8518 cmpl(len, 16);
8519 jcc(Assembler::equal, L_exact_16_left);
8520 jcc(Assembler::less, L_less_than_16_left);
8521
8522 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8523 pxor(xmm7, xmm0); //xor the initial crc value
8524 addl(pos, 16);
8525 subl(len, 16);
8526 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8527 jmp(L_get_last_two_xmms);
8528
8529 bind(L_less_than_16_left);
8530 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8531 pxor(xmm1, xmm1);
8532 movptr(tmp1, rsp);
8533 movdqu(Address(tmp1, 0 * 16), xmm1);
8534
8535 cmpl(len, 4);
8536 jcc(Assembler::less, L_only_less_than_4);
8537
8538 //backup the counter value
8539 movl(tmp2, len);
8540 cmpl(len, 8);
8541 jcc(Assembler::less, L_less_than_8_left);
8542
8543 //load 8 Bytes
8544 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8545 movq(Address(tmp1, 0 * 16), rax);
8546 addptr(tmp1, 8);
8547 subl(len, 8);
8548 addl(pos, 8);
8549
8550 bind(L_less_than_8_left);
8551 cmpl(len, 4);
8552 jcc(Assembler::less, L_less_than_4_left);
8553
8554 //load 4 Bytes
8555 movl(rax, Address(buf, pos, Address::times_1, 0));
8556 movl(Address(tmp1, 0 * 16), rax);
8557 addptr(tmp1, 4);
8558 subl(len, 4);
8559 addl(pos, 4);
8560
8561 bind(L_less_than_4_left);
8562 cmpl(len, 2);
8563 jcc(Assembler::less, L_less_than_2_left);
8564
8565 // load 2 Bytes
8566 movw(rax, Address(buf, pos, Address::times_1, 0));
8567 movl(Address(tmp1, 0 * 16), rax);
8568 addptr(tmp1, 2);
8569 subl(len, 2);
8570 addl(pos, 2);
8571
8572 bind(L_less_than_2_left);
8573 cmpl(len, 1);
8574 jcc(Assembler::less, L_zero_left);
8575
8576 // load 1 Byte
8577 movb(rax, Address(buf, pos, Address::times_1, 0));
8578 movb(Address(tmp1, 0 * 16), rax);
8579
8580 bind(L_zero_left);
8581 movdqu(xmm7, Address(rsp, 0));
8582 pxor(xmm7, xmm0); //xor the initial crc value
8583
8584 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8585 movdqu(xmm0, Address(rax, tmp2));
8586 pshufb(xmm7, xmm0);
8587 jmp(L_128_done);
8588
8589 bind(L_exact_16_left);
8590 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8591 pxor(xmm7, xmm0); //xor the initial crc value
8592 jmp(L_128_done);
8593
8594 bind(L_only_less_than_4);
8595 cmpl(len, 3);
8596 jcc(Assembler::less, L_only_less_than_3);
8597
8598 // load 3 Bytes
8599 movb(rax, Address(buf, pos, Address::times_1, 0));
8600 movb(Address(tmp1, 0), rax);
8601
8602 movb(rax, Address(buf, pos, Address::times_1, 1));
8603 movb(Address(tmp1, 1), rax);
8604
8605 movb(rax, Address(buf, pos, Address::times_1, 2));
8606 movb(Address(tmp1, 2), rax);
8607
8608 movdqu(xmm7, Address(rsp, 0));
8609 pxor(xmm7, xmm0); //xor the initial crc value
8610
8611 pslldq(xmm7, 0x5);
8612 jmp(L_barrett);
8613 bind(L_only_less_than_3);
8614 cmpl(len, 2);
8615 jcc(Assembler::less, L_only_less_than_2);
8616
8617 // load 2 Bytes
8618 movb(rax, Address(buf, pos, Address::times_1, 0));
8619 movb(Address(tmp1, 0), rax);
8620
8621 movb(rax, Address(buf, pos, Address::times_1, 1));
8622 movb(Address(tmp1, 1), rax);
8623
8624 movdqu(xmm7, Address(rsp, 0));
8625 pxor(xmm7, xmm0); //xor the initial crc value
8626
8627 pslldq(xmm7, 0x6);
8628 jmp(L_barrett);
8629
8630 bind(L_only_less_than_2);
8631 //load 1 Byte
8632 movb(rax, Address(buf, pos, Address::times_1, 0));
8633 movb(Address(tmp1, 0), rax);
8634
8635 movdqu(xmm7, Address(rsp, 0));
8636 pxor(xmm7, xmm0); //xor the initial crc value
8637
8638 pslldq(xmm7, 0x7);
8639 }
8640
8641 /**
8642 * Compute CRC32 using AVX512 instructions
8643 * param crc register containing existing CRC (32-bit)
8644 * param buf register pointing to input byte buffer (byte*)
8645 * param len register containing number of bytes
8646 * param table address of crc or crc32c table
8647 * param tmp1 scratch register
8648 * param tmp2 scratch register
8649 * return rax result register
8650 *
8651 * This routine is identical for crc32c with the exception of the precomputed constant
8652 * table which will be passed as the table argument. The calculation steps are
8653 * the same for both variants.
8654 */
8655 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8656 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8657
8658 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8659 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8660 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8661 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8662 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8663
8664 const Register pos = r12;
8665 push(r12);
8666 subptr(rsp, 16 * 2 + 8);
8667
8668 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8669 // context for the registers used, where all instructions below are using 128-bit mode
8670 // On EVEX without VL and BW, these instructions will all be AVX.
8671 movl(pos, 0);
8672
8673 // check if smaller than 256B
8674 cmpl(len, 256);
8675 jcc(Assembler::less, L_less_than_256);
8676
8677 // load the initial crc value
8678 movdl(xmm10, crc);
8679
8680 // receive the initial 64B data, xor the initial crc value
8681 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8682 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8683 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8684 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8685
8686 subl(len, 256);
8687 cmpl(len, 256);
8688 jcc(Assembler::less, L_fold_128_B_loop);
8689
8690 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8691 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8692 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8693 subl(len, 256);
8694
8695 bind(L_fold_256_B_loop);
8696 addl(pos, 256);
8697 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8698 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8699 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8700 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8701
8702 subl(len, 256);
8703 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8704
8705 // Fold 256 into 128
8706 addl(pos, 256);
8707 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8708 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8709 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8710
8711 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8712 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8713 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8714
8715 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8716 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8717
8718 addl(len, 128);
8719 jmp(L_fold_128_B_register);
8720
8721 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8722 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8723
8724 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8725 bind(L_fold_128_B_loop);
8726 addl(pos, 128);
8727 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8728 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8729
8730 subl(len, 128);
8731 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8732
8733 addl(pos, 128);
8734
8735 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8736 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8737 bind(L_fold_128_B_register);
8738 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8739 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8740 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8741 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8742 // save last that has no multiplicand
8743 vextracti64x2(xmm7, xmm4, 3);
8744
8745 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8746 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8747 // Needed later in reduction loop
8748 movdqu(xmm10, Address(table, 1 * 16));
8749 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8750 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8751
8752 // Swap 1,0,3,2 - 01 00 11 10
8753 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8754 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8755 vextracti128(xmm5, xmm8, 1);
8756 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8757
8758 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8759 // instead of a cmp instruction, we use the negative flag with the jl instruction
8760 addl(len, 128 - 16);
8761 jcc(Assembler::less, L_final_reduction_for_128);
8762
8763 bind(L_16B_reduction_loop);
8764 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8765 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8766 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8767 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8768 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8769 addl(pos, 16);
8770 subl(len, 16);
8771 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8772
8773 bind(L_final_reduction_for_128);
8774 addl(len, 16);
8775 jcc(Assembler::equal, L_128_done);
8776
8777 bind(L_get_last_two_xmms);
8778 movdqu(xmm2, xmm7);
8779 addl(pos, len);
8780 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8781 subl(pos, len);
8782
8783 // get rid of the extra data that was loaded before
8784 // load the shift constant
8785 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8786 movdqu(xmm0, Address(rax, len));
8787 addl(rax, len);
8788
8789 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8790 //Change mask to 512
8791 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8792 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8793
8794 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8795 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8796 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8797 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8798 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8799
8800 bind(L_128_done);
8801 // compute crc of a 128-bit value
8802 movdqu(xmm10, Address(table, 3 * 16));
8803 movdqu(xmm0, xmm7);
8804
8805 // 64b fold
8806 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8807 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8808 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8809
8810 // 32b fold
8811 movdqu(xmm0, xmm7);
8812 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8813 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8814 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8815 jmp(L_barrett);
8816
8817 bind(L_less_than_256);
8818 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8819
8820 //barrett reduction
8821 bind(L_barrett);
8822 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8823 movdqu(xmm1, xmm7);
8824 movdqu(xmm2, xmm7);
8825 movdqu(xmm10, Address(table, 4 * 16));
8826
8827 pclmulqdq(xmm7, xmm10, 0x0);
8828 pxor(xmm7, xmm2);
8829 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8830 movdqu(xmm2, xmm7);
8831 pclmulqdq(xmm7, xmm10, 0x10);
8832 pxor(xmm7, xmm2);
8833 pxor(xmm7, xmm1);
8834 pextrd(crc, xmm7, 2);
8835
8836 bind(L_cleanup);
8837 addptr(rsp, 16 * 2 + 8);
8838 pop(r12);
8839 }
8840
8841 // S. Gueron / Information Processing Letters 112 (2012) 184
8842 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8843 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8844 // Output: the 64-bit carry-less product of B * CONST
8845 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8846 Register tmp1, Register tmp2, Register tmp3) {
8847 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8848 if (n > 0) {
8849 addq(tmp3, n * 256 * 8);
8850 }
8851 // Q1 = TABLEExt[n][B & 0xFF];
8852 movl(tmp1, in);
8853 andl(tmp1, 0x000000FF);
8854 shll(tmp1, 3);
8855 addq(tmp1, tmp3);
8856 movq(tmp1, Address(tmp1, 0));
8857
8858 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8859 movl(tmp2, in);
8860 shrl(tmp2, 8);
8861 andl(tmp2, 0x000000FF);
8862 shll(tmp2, 3);
8863 addq(tmp2, tmp3);
8864 movq(tmp2, Address(tmp2, 0));
8865
8866 shlq(tmp2, 8);
8867 xorq(tmp1, tmp2);
8868
8869 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8870 movl(tmp2, in);
8871 shrl(tmp2, 16);
8872 andl(tmp2, 0x000000FF);
8873 shll(tmp2, 3);
8874 addq(tmp2, tmp3);
8875 movq(tmp2, Address(tmp2, 0));
8876
8877 shlq(tmp2, 16);
8878 xorq(tmp1, tmp2);
8879
8880 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8881 shrl(in, 24);
8882 andl(in, 0x000000FF);
8883 shll(in, 3);
8884 addq(in, tmp3);
8885 movq(in, Address(in, 0));
8886
8887 shlq(in, 24);
8888 xorq(in, tmp1);
8889 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8890 }
8891
8892 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8893 Register in_out,
8894 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8895 XMMRegister w_xtmp2,
8896 Register tmp1,
8897 Register n_tmp2, Register n_tmp3) {
8898 if (is_pclmulqdq_supported) {
8899 movdl(w_xtmp1, in_out); // modified blindly
8900
8901 movl(tmp1, const_or_pre_comp_const_index);
8902 movdl(w_xtmp2, tmp1);
8903 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8904
8905 movdq(in_out, w_xtmp1);
8906 } else {
8907 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8908 }
8909 }
8910
8911 // Recombination Alternative 2: No bit-reflections
8912 // T1 = (CRC_A * U1) << 1
8913 // T2 = (CRC_B * U2) << 1
8914 // C1 = T1 >> 32
8915 // C2 = T2 >> 32
8916 // T1 = T1 & 0xFFFFFFFF
8917 // T2 = T2 & 0xFFFFFFFF
8918 // T1 = CRC32(0, T1)
8919 // T2 = CRC32(0, T2)
8920 // C1 = C1 ^ T1
8921 // C2 = C2 ^ T2
8922 // CRC = C1 ^ C2 ^ CRC_C
8923 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8924 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8925 Register tmp1, Register tmp2,
8926 Register n_tmp3) {
8927 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8928 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8929 shlq(in_out, 1);
8930 movl(tmp1, in_out);
8931 shrq(in_out, 32);
8932 xorl(tmp2, tmp2);
8933 crc32(tmp2, tmp1, 4);
8934 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8935 shlq(in1, 1);
8936 movl(tmp1, in1);
8937 shrq(in1, 32);
8938 xorl(tmp2, tmp2);
8939 crc32(tmp2, tmp1, 4);
8940 xorl(in1, tmp2);
8941 xorl(in_out, in1);
8942 xorl(in_out, in2);
8943 }
8944
8945 // Set N to predefined value
8946 // Subtract from a length of a buffer
8947 // execute in a loop:
8948 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8949 // for i = 1 to N do
8950 // CRC_A = CRC32(CRC_A, A[i])
8951 // CRC_B = CRC32(CRC_B, B[i])
8952 // CRC_C = CRC32(CRC_C, C[i])
8953 // end for
8954 // Recombine
8955 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8956 Register in_out1, Register in_out2, Register in_out3,
8957 Register tmp1, Register tmp2, Register tmp3,
8958 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8959 Register tmp4, Register tmp5,
8960 Register n_tmp6) {
8961 Label L_processPartitions;
8962 Label L_processPartition;
8963 Label L_exit;
8964
8965 bind(L_processPartitions);
8966 cmpl(in_out1, 3 * size);
8967 jcc(Assembler::less, L_exit);
8968 xorl(tmp1, tmp1);
8969 xorl(tmp2, tmp2);
8970 movq(tmp3, in_out2);
8971 addq(tmp3, size);
8972
8973 bind(L_processPartition);
8974 crc32(in_out3, Address(in_out2, 0), 8);
8975 crc32(tmp1, Address(in_out2, size), 8);
8976 crc32(tmp2, Address(in_out2, size * 2), 8);
8977 addq(in_out2, 8);
8978 cmpq(in_out2, tmp3);
8979 jcc(Assembler::less, L_processPartition);
8980 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8981 w_xtmp1, w_xtmp2, w_xtmp3,
8982 tmp4, tmp5,
8983 n_tmp6);
8984 addq(in_out2, 2 * size);
8985 subl(in_out1, 3 * size);
8986 jmp(L_processPartitions);
8987
8988 bind(L_exit);
8989 }
8990 #else
8991 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
8992 Register tmp1, Register tmp2, Register tmp3,
8993 XMMRegister xtmp1, XMMRegister xtmp2) {
8994 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8995 if (n > 0) {
8996 addl(tmp3, n * 256 * 8);
8997 }
8998 // Q1 = TABLEExt[n][B & 0xFF];
8999 movl(tmp1, in_out);
9000 andl(tmp1, 0x000000FF);
9001 shll(tmp1, 3);
9002 addl(tmp1, tmp3);
9003 movq(xtmp1, Address(tmp1, 0));
9004
9005 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9006 movl(tmp2, in_out);
9007 shrl(tmp2, 8);
9008 andl(tmp2, 0x000000FF);
9009 shll(tmp2, 3);
9010 addl(tmp2, tmp3);
9011 movq(xtmp2, Address(tmp2, 0));
9012
9013 psllq(xtmp2, 8);
9014 pxor(xtmp1, xtmp2);
9015
9016 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9017 movl(tmp2, in_out);
9018 shrl(tmp2, 16);
9019 andl(tmp2, 0x000000FF);
9020 shll(tmp2, 3);
9021 addl(tmp2, tmp3);
9022 movq(xtmp2, Address(tmp2, 0));
9023
9024 psllq(xtmp2, 16);
9025 pxor(xtmp1, xtmp2);
9026
9027 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9028 shrl(in_out, 24);
9029 andl(in_out, 0x000000FF);
9030 shll(in_out, 3);
9031 addl(in_out, tmp3);
9032 movq(xtmp2, Address(in_out, 0));
9033
9034 psllq(xtmp2, 24);
9035 pxor(xtmp1, xtmp2); // Result in CXMM
9036 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9037 }
9038
9039 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9040 Register in_out,
9041 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9042 XMMRegister w_xtmp2,
9043 Register tmp1,
9044 Register n_tmp2, Register n_tmp3) {
9045 if (is_pclmulqdq_supported) {
9046 movdl(w_xtmp1, in_out);
9047
9048 movl(tmp1, const_or_pre_comp_const_index);
9049 movdl(w_xtmp2, tmp1);
9050 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9051 // Keep result in XMM since GPR is 32 bit in length
9052 } else {
9053 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
9054 }
9055 }
9056
9057 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9058 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9059 Register tmp1, Register tmp2,
9060 Register n_tmp3) {
9061 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9062 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9063
9064 psllq(w_xtmp1, 1);
9065 movdl(tmp1, w_xtmp1);
9066 psrlq(w_xtmp1, 32);
9067 movdl(in_out, w_xtmp1);
9068
9069 xorl(tmp2, tmp2);
9070 crc32(tmp2, tmp1, 4);
9071 xorl(in_out, tmp2);
9072
9073 psllq(w_xtmp2, 1);
9074 movdl(tmp1, w_xtmp2);
9075 psrlq(w_xtmp2, 32);
9076 movdl(in1, w_xtmp2);
9077
9078 xorl(tmp2, tmp2);
9079 crc32(tmp2, tmp1, 4);
9080 xorl(in1, tmp2);
9081 xorl(in_out, in1);
9082 xorl(in_out, in2);
9083 }
9084
9085 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9086 Register in_out1, Register in_out2, Register in_out3,
9087 Register tmp1, Register tmp2, Register tmp3,
9088 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9089 Register tmp4, Register tmp5,
9090 Register n_tmp6) {
9091 Label L_processPartitions;
9092 Label L_processPartition;
9093 Label L_exit;
9094
9095 bind(L_processPartitions);
9096 cmpl(in_out1, 3 * size);
9097 jcc(Assembler::less, L_exit);
9098 xorl(tmp1, tmp1);
9099 xorl(tmp2, tmp2);
9100 movl(tmp3, in_out2);
9101 addl(tmp3, size);
9102
9103 bind(L_processPartition);
9104 crc32(in_out3, Address(in_out2, 0), 4);
9105 crc32(tmp1, Address(in_out2, size), 4);
9106 crc32(tmp2, Address(in_out2, size*2), 4);
9107 crc32(in_out3, Address(in_out2, 0+4), 4);
9108 crc32(tmp1, Address(in_out2, size+4), 4);
9109 crc32(tmp2, Address(in_out2, size*2+4), 4);
9110 addl(in_out2, 8);
9111 cmpl(in_out2, tmp3);
9112 jcc(Assembler::less, L_processPartition);
9113
9114 push(tmp3);
9115 push(in_out1);
9116 push(in_out2);
9117 tmp4 = tmp3;
9118 tmp5 = in_out1;
9119 n_tmp6 = in_out2;
9120
9121 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9122 w_xtmp1, w_xtmp2, w_xtmp3,
9123 tmp4, tmp5,
9124 n_tmp6);
9125
9126 pop(in_out2);
9127 pop(in_out1);
9128 pop(tmp3);
9129
9130 addl(in_out2, 2 * size);
9131 subl(in_out1, 3 * size);
9132 jmp(L_processPartitions);
9133
9134 bind(L_exit);
9135 }
9136 #endif //LP64
9137
9138 #ifdef _LP64
9139 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9140 // Input: A buffer I of L bytes.
9141 // Output: the CRC32C value of the buffer.
9142 // Notations:
9143 // Write L = 24N + r, with N = floor (L/24).
9144 // r = L mod 24 (0 <= r < 24).
9145 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9146 // N quadwords, and R consists of r bytes.
9147 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9148 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9149 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9150 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9151 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9152 Register tmp1, Register tmp2, Register tmp3,
9153 Register tmp4, Register tmp5, Register tmp6,
9154 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9155 bool is_pclmulqdq_supported) {
9156 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9157 Label L_wordByWord;
9158 Label L_byteByByteProlog;
9159 Label L_byteByByte;
9160 Label L_exit;
9161
9162 if (is_pclmulqdq_supported ) {
9163 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
9164 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
9165
9166 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
9167 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
9168
9169 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
9170 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
9171 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9172 } else {
9173 const_or_pre_comp_const_index[0] = 1;
9174 const_or_pre_comp_const_index[1] = 0;
9175
9176 const_or_pre_comp_const_index[2] = 3;
9177 const_or_pre_comp_const_index[3] = 2;
9178
9179 const_or_pre_comp_const_index[4] = 5;
9180 const_or_pre_comp_const_index[5] = 4;
9181 }
9182 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9183 in2, in1, in_out,
9184 tmp1, tmp2, tmp3,
9185 w_xtmp1, w_xtmp2, w_xtmp3,
9186 tmp4, tmp5,
9187 tmp6);
9188 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9189 in2, in1, in_out,
9190 tmp1, tmp2, tmp3,
9191 w_xtmp1, w_xtmp2, w_xtmp3,
9192 tmp4, tmp5,
9193 tmp6);
9194 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9195 in2, in1, in_out,
9196 tmp1, tmp2, tmp3,
9197 w_xtmp1, w_xtmp2, w_xtmp3,
9198 tmp4, tmp5,
9199 tmp6);
9200 movl(tmp1, in2);
9201 andl(tmp1, 0x00000007);
9202 negl(tmp1);
9203 addl(tmp1, in2);
9204 addq(tmp1, in1);
9205
9206 cmpq(in1, tmp1);
9207 jccb(Assembler::greaterEqual, L_byteByByteProlog);
9208 align(16);
9209 BIND(L_wordByWord);
9210 crc32(in_out, Address(in1, 0), 8);
9211 addq(in1, 8);
9212 cmpq(in1, tmp1);
9213 jcc(Assembler::less, L_wordByWord);
9214
9215 BIND(L_byteByByteProlog);
9216 andl(in2, 0x00000007);
9217 movl(tmp2, 1);
9218
9219 cmpl(tmp2, in2);
9220 jccb(Assembler::greater, L_exit);
9221 BIND(L_byteByByte);
9222 crc32(in_out, Address(in1, 0), 1);
9223 incq(in1);
9224 incl(tmp2);
9225 cmpl(tmp2, in2);
9226 jcc(Assembler::lessEqual, L_byteByByte);
9227
9228 BIND(L_exit);
9229 }
9230 #else
9231 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9232 Register tmp1, Register tmp2, Register tmp3,
9233 Register tmp4, Register tmp5, Register tmp6,
9234 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9235 bool is_pclmulqdq_supported) {
9236 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9237 Label L_wordByWord;
9238 Label L_byteByByteProlog;
9239 Label L_byteByByte;
9240 Label L_exit;
9241
9242 if (is_pclmulqdq_supported) {
9243 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
9244 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
9245
9246 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
9247 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
9248
9249 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
9250 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
9251 } else {
9252 const_or_pre_comp_const_index[0] = 1;
9253 const_or_pre_comp_const_index[1] = 0;
9254
9255 const_or_pre_comp_const_index[2] = 3;
9256 const_or_pre_comp_const_index[3] = 2;
9257
9258 const_or_pre_comp_const_index[4] = 5;
9259 const_or_pre_comp_const_index[5] = 4;
9260 }
9261 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9262 in2, in1, in_out,
9263 tmp1, tmp2, tmp3,
9264 w_xtmp1, w_xtmp2, w_xtmp3,
9265 tmp4, tmp5,
9266 tmp6);
9267 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9268 in2, in1, in_out,
9269 tmp1, tmp2, tmp3,
9270 w_xtmp1, w_xtmp2, w_xtmp3,
9271 tmp4, tmp5,
9272 tmp6);
9273 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9274 in2, in1, in_out,
9275 tmp1, tmp2, tmp3,
9276 w_xtmp1, w_xtmp2, w_xtmp3,
9277 tmp4, tmp5,
9278 tmp6);
9279 movl(tmp1, in2);
9280 andl(tmp1, 0x00000007);
9281 negl(tmp1);
9282 addl(tmp1, in2);
9283 addl(tmp1, in1);
9284
9285 BIND(L_wordByWord);
9286 cmpl(in1, tmp1);
9287 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9288 crc32(in_out, Address(in1,0), 4);
9289 addl(in1, 4);
9290 jmp(L_wordByWord);
9291
9292 BIND(L_byteByByteProlog);
9293 andl(in2, 0x00000007);
9294 movl(tmp2, 1);
9295
9296 BIND(L_byteByByte);
9297 cmpl(tmp2, in2);
9298 jccb(Assembler::greater, L_exit);
9299 movb(tmp1, Address(in1, 0));
9300 crc32(in_out, tmp1, 1);
9301 incl(in1);
9302 incl(tmp2);
9303 jmp(L_byteByByte);
9304
9305 BIND(L_exit);
9306 }
9307 #endif // LP64
9308 #undef BIND
9309 #undef BLOCK_COMMENT
9310
9311 // Compress char[] array to byte[].
9312 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
9313 // Return the array length if every element in array can be encoded,
9314 // otherwise, the index of first non-latin1 (> 0xff) character.
9315 // @IntrinsicCandidate
9316 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9317 // for (int i = 0; i < len; i++) {
9318 // char c = src[srcOff];
9319 // if (c > 0xff) {
9320 // return i; // return index of non-latin1 char
9321 // }
9322 // dst[dstOff] = (byte)c;
9323 // srcOff++;
9324 // dstOff++;
9325 // }
9326 // return len;
9327 // }
9328 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9329 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9330 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9331 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9332 Label copy_chars_loop, done, reset_sp, copy_tail;
9333
9334 // rsi: src
9335 // rdi: dst
9336 // rdx: len
9337 // rcx: tmp5
9338 // rax: result
9339
9340 // rsi holds start addr of source char[] to be compressed
9341 // rdi holds start addr of destination byte[]
9342 // rdx holds length
9343
9344 assert(len != result, "");
9345
9346 // save length for return
9347 movl(result, len);
9348
9349 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9350 VM_Version::supports_avx512vlbw() &&
9351 VM_Version::supports_bmi2()) {
9352
9353 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9354
9355 // alignment
9356 Label post_alignment;
9357
9358 // if length of the string is less than 32, handle it the old fashioned way
9359 testl(len, -32);
9360 jcc(Assembler::zero, below_threshold);
9361
9362 // First check whether a character is compressible ( <= 0xFF).
9363 // Create mask to test for Unicode chars inside zmm vector
9364 movl(tmp5, 0x00FF);
9365 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9366
9367 testl(len, -64);
9368 jccb(Assembler::zero, post_alignment);
9369
9370 movl(tmp5, dst);
9371 andl(tmp5, (32 - 1));
9372 negl(tmp5);
9373 andl(tmp5, (32 - 1));
9374
9375 // bail out when there is nothing to be done
9376 testl(tmp5, 0xFFFFFFFF);
9377 jccb(Assembler::zero, post_alignment);
9378
9379 // ~(~0 << len), where len is the # of remaining elements to process
9380 movl(len, 0xFFFFFFFF);
9381 shlxl(len, len, tmp5);
9382 notl(len);
9383 kmovdl(mask2, len);
9384 movl(len, result);
9385
9386 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9387 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9388 ktestd(mask1, mask2);
9389 jcc(Assembler::carryClear, copy_tail);
9390
9391 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9392
9393 addptr(src, tmp5);
9394 addptr(src, tmp5);
9395 addptr(dst, tmp5);
9396 subl(len, tmp5);
9397
9398 bind(post_alignment);
9399 // end of alignment
9400
9401 movl(tmp5, len);
9402 andl(tmp5, (32 - 1)); // tail count (in chars)
9403 andl(len, ~(32 - 1)); // vector count (in chars)
9404 jccb(Assembler::zero, copy_loop_tail);
9405
9406 lea(src, Address(src, len, Address::times_2));
9407 lea(dst, Address(dst, len, Address::times_1));
9408 negptr(len);
9409
9410 bind(copy_32_loop);
9411 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9412 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9413 kortestdl(mask1, mask1);
9414 jccb(Assembler::carryClear, reset_for_copy_tail);
9415
9416 // All elements in current processed chunk are valid candidates for
9417 // compression. Write a truncated byte elements to the memory.
9418 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9419 addptr(len, 32);
9420 jccb(Assembler::notZero, copy_32_loop);
9421
9422 bind(copy_loop_tail);
9423 // bail out when there is nothing to be done
9424 testl(tmp5, 0xFFFFFFFF);
9425 jcc(Assembler::zero, done);
9426
9427 movl(len, tmp5);
9428
9429 // ~(~0 << len), where len is the # of remaining elements to process
9430 movl(tmp5, 0xFFFFFFFF);
9431 shlxl(tmp5, tmp5, len);
9432 notl(tmp5);
9433
9434 kmovdl(mask2, tmp5);
9435
9436 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9437 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9438 ktestd(mask1, mask2);
9439 jcc(Assembler::carryClear, copy_tail);
9440
9441 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9442 jmp(done);
9443
9444 bind(reset_for_copy_tail);
9445 lea(src, Address(src, tmp5, Address::times_2));
9446 lea(dst, Address(dst, tmp5, Address::times_1));
9447 subptr(len, tmp5);
9448 jmp(copy_chars_loop);
9449
9450 bind(below_threshold);
9451 }
9452
9453 if (UseSSE42Intrinsics) {
9454 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9455
9456 // vectored compression
9457 testl(len, 0xfffffff8);
9458 jcc(Assembler::zero, copy_tail);
9459
9460 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9461 movdl(tmp1Reg, tmp5);
9462 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9463
9464 andl(len, 0xfffffff0);
9465 jccb(Assembler::zero, copy_16);
9466
9467 // compress 16 chars per iter
9468 pxor(tmp4Reg, tmp4Reg);
9469
9470 lea(src, Address(src, len, Address::times_2));
9471 lea(dst, Address(dst, len, Address::times_1));
9472 negptr(len);
9473
9474 bind(copy_32_loop);
9475 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9476 por(tmp4Reg, tmp2Reg);
9477 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9478 por(tmp4Reg, tmp3Reg);
9479 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9480 jccb(Assembler::notZero, reset_for_copy_tail);
9481 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9482 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9483 addptr(len, 16);
9484 jccb(Assembler::notZero, copy_32_loop);
9485
9486 // compress next vector of 8 chars (if any)
9487 bind(copy_16);
9488 // len = 0
9489 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9490 jccb(Assembler::zero, copy_tail_sse);
9491
9492 pxor(tmp3Reg, tmp3Reg);
9493
9494 movdqu(tmp2Reg, Address(src, 0));
9495 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9496 jccb(Assembler::notZero, reset_for_copy_tail);
9497 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9498 movq(Address(dst, 0), tmp2Reg);
9499 addptr(src, 16);
9500 addptr(dst, 8);
9501 jmpb(copy_tail_sse);
9502
9503 bind(reset_for_copy_tail);
9504 movl(tmp5, result);
9505 andl(tmp5, 0x0000000f);
9506 lea(src, Address(src, tmp5, Address::times_2));
9507 lea(dst, Address(dst, tmp5, Address::times_1));
9508 subptr(len, tmp5);
9509 jmpb(copy_chars_loop);
9510
9511 bind(copy_tail_sse);
9512 movl(len, result);
9513 andl(len, 0x00000007); // tail count (in chars)
9514 }
9515 // compress 1 char per iter
9516 bind(copy_tail);
9517 testl(len, len);
9518 jccb(Assembler::zero, done);
9519 lea(src, Address(src, len, Address::times_2));
9520 lea(dst, Address(dst, len, Address::times_1));
9521 negptr(len);
9522
9523 bind(copy_chars_loop);
9524 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9525 testl(tmp5, 0xff00); // check if Unicode char
9526 jccb(Assembler::notZero, reset_sp);
9527 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9528 increment(len);
9529 jccb(Assembler::notZero, copy_chars_loop);
9530
9531 // add len then return (len will be zero if compress succeeded, otherwise negative)
9532 bind(reset_sp);
9533 addl(result, len);
9534
9535 bind(done);
9536 }
9537
9538 // Inflate byte[] array to char[].
9539 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9540 // @IntrinsicCandidate
9541 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9542 // for (int i = 0; i < len; i++) {
9543 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9544 // }
9545 // }
9546 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9547 XMMRegister tmp1, Register tmp2, KRegister mask) {
9548 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9549 // rsi: src
9550 // rdi: dst
9551 // rdx: len
9552 // rcx: tmp2
9553
9554 // rsi holds start addr of source byte[] to be inflated
9555 // rdi holds start addr of destination char[]
9556 // rdx holds length
9557 assert_different_registers(src, dst, len, tmp2);
9558 movl(tmp2, len);
9559 if ((UseAVX > 2) && // AVX512
9560 VM_Version::supports_avx512vlbw() &&
9561 VM_Version::supports_bmi2()) {
9562
9563 Label copy_32_loop, copy_tail;
9564 Register tmp3_aliased = len;
9565
9566 // if length of the string is less than 16, handle it in an old fashioned way
9567 testl(len, -16);
9568 jcc(Assembler::zero, below_threshold);
9569
9570 testl(len, -1 * AVX3Threshold);
9571 jcc(Assembler::zero, avx3_threshold);
9572
9573 // In order to use only one arithmetic operation for the main loop we use
9574 // this pre-calculation
9575 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9576 andl(len, -32); // vector count
9577 jccb(Assembler::zero, copy_tail);
9578
9579 lea(src, Address(src, len, Address::times_1));
9580 lea(dst, Address(dst, len, Address::times_2));
9581 negptr(len);
9582
9583
9584 // inflate 32 chars per iter
9585 bind(copy_32_loop);
9586 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9587 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9588 addptr(len, 32);
9589 jcc(Assembler::notZero, copy_32_loop);
9590
9591 bind(copy_tail);
9592 // bail out when there is nothing to be done
9593 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9594 jcc(Assembler::zero, done);
9595
9596 // ~(~0 << length), where length is the # of remaining elements to process
9597 movl(tmp3_aliased, -1);
9598 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9599 notl(tmp3_aliased);
9600 kmovdl(mask, tmp3_aliased);
9601 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9602 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9603
9604 jmp(done);
9605 bind(avx3_threshold);
9606 }
9607 if (UseSSE42Intrinsics) {
9608 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9609
9610 if (UseAVX > 1) {
9611 andl(tmp2, (16 - 1));
9612 andl(len, -16);
9613 jccb(Assembler::zero, copy_new_tail);
9614 } else {
9615 andl(tmp2, 0x00000007); // tail count (in chars)
9616 andl(len, 0xfffffff8); // vector count (in chars)
9617 jccb(Assembler::zero, copy_tail);
9618 }
9619
9620 // vectored inflation
9621 lea(src, Address(src, len, Address::times_1));
9622 lea(dst, Address(dst, len, Address::times_2));
9623 negptr(len);
9624
9625 if (UseAVX > 1) {
9626 bind(copy_16_loop);
9627 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9628 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9629 addptr(len, 16);
9630 jcc(Assembler::notZero, copy_16_loop);
9631
9632 bind(below_threshold);
9633 bind(copy_new_tail);
9634 movl(len, tmp2);
9635 andl(tmp2, 0x00000007);
9636 andl(len, 0xFFFFFFF8);
9637 jccb(Assembler::zero, copy_tail);
9638
9639 pmovzxbw(tmp1, Address(src, 0));
9640 movdqu(Address(dst, 0), tmp1);
9641 addptr(src, 8);
9642 addptr(dst, 2 * 8);
9643
9644 jmp(copy_tail, true);
9645 }
9646
9647 // inflate 8 chars per iter
9648 bind(copy_8_loop);
9649 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9650 movdqu(Address(dst, len, Address::times_2), tmp1);
9651 addptr(len, 8);
9652 jcc(Assembler::notZero, copy_8_loop);
9653
9654 bind(copy_tail);
9655 movl(len, tmp2);
9656
9657 cmpl(len, 4);
9658 jccb(Assembler::less, copy_bytes);
9659
9660 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9661 pmovzxbw(tmp1, tmp1);
9662 movq(Address(dst, 0), tmp1);
9663 subptr(len, 4);
9664 addptr(src, 4);
9665 addptr(dst, 8);
9666
9667 bind(copy_bytes);
9668 } else {
9669 bind(below_threshold);
9670 }
9671
9672 testl(len, len);
9673 jccb(Assembler::zero, done);
9674 lea(src, Address(src, len, Address::times_1));
9675 lea(dst, Address(dst, len, Address::times_2));
9676 negptr(len);
9677
9678 // inflate 1 char per iter
9679 bind(copy_chars_loop);
9680 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9681 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9682 increment(len);
9683 jcc(Assembler::notZero, copy_chars_loop);
9684
9685 bind(done);
9686 }
9687
9688 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
9689 switch(type) {
9690 case T_BYTE:
9691 case T_BOOLEAN:
9692 evmovdqub(dst, kmask, src, merge, vector_len);
9693 break;
9694 case T_CHAR:
9695 case T_SHORT:
9696 evmovdquw(dst, kmask, src, merge, vector_len);
9697 break;
9698 case T_INT:
9699 case T_FLOAT:
9700 evmovdqul(dst, kmask, src, merge, vector_len);
9701 break;
9702 case T_LONG:
9703 case T_DOUBLE:
9704 evmovdquq(dst, kmask, src, merge, vector_len);
9705 break;
9706 default:
9707 fatal("Unexpected type argument %s", type2name(type));
9708 break;
9709 }
9710 }
9711
9712
9713 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9714 switch(type) {
9715 case T_BYTE:
9716 case T_BOOLEAN:
9717 evmovdqub(dst, kmask, src, merge, vector_len);
9718 break;
9719 case T_CHAR:
9720 case T_SHORT:
9721 evmovdquw(dst, kmask, src, merge, vector_len);
9722 break;
9723 case T_INT:
9724 case T_FLOAT:
9725 evmovdqul(dst, kmask, src, merge, vector_len);
9726 break;
9727 case T_LONG:
9728 case T_DOUBLE:
9729 evmovdquq(dst, kmask, src, merge, vector_len);
9730 break;
9731 default:
9732 fatal("Unexpected type argument %s", type2name(type));
9733 break;
9734 }
9735 }
9736
9737 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9738 switch(type) {
9739 case T_BYTE:
9740 case T_BOOLEAN:
9741 evmovdqub(dst, kmask, src, merge, vector_len);
9742 break;
9743 case T_CHAR:
9744 case T_SHORT:
9745 evmovdquw(dst, kmask, src, merge, vector_len);
9746 break;
9747 case T_INT:
9748 case T_FLOAT:
9749 evmovdqul(dst, kmask, src, merge, vector_len);
9750 break;
9751 case T_LONG:
9752 case T_DOUBLE:
9753 evmovdquq(dst, kmask, src, merge, vector_len);
9754 break;
9755 default:
9756 fatal("Unexpected type argument %s", type2name(type));
9757 break;
9758 }
9759 }
9760
9761 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9762 switch(masklen) {
9763 case 2:
9764 knotbl(dst, src);
9765 movl(rtmp, 3);
9766 kmovbl(ktmp, rtmp);
9767 kandbl(dst, ktmp, dst);
9768 break;
9769 case 4:
9770 knotbl(dst, src);
9771 movl(rtmp, 15);
9772 kmovbl(ktmp, rtmp);
9773 kandbl(dst, ktmp, dst);
9774 break;
9775 case 8:
9776 knotbl(dst, src);
9777 break;
9778 case 16:
9779 knotwl(dst, src);
9780 break;
9781 case 32:
9782 knotdl(dst, src);
9783 break;
9784 case 64:
9785 knotql(dst, src);
9786 break;
9787 default:
9788 fatal("Unexpected vector length %d", masklen);
9789 break;
9790 }
9791 }
9792
9793 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9794 switch(type) {
9795 case T_BOOLEAN:
9796 case T_BYTE:
9797 kandbl(dst, src1, src2);
9798 break;
9799 case T_CHAR:
9800 case T_SHORT:
9801 kandwl(dst, src1, src2);
9802 break;
9803 case T_INT:
9804 case T_FLOAT:
9805 kanddl(dst, src1, src2);
9806 break;
9807 case T_LONG:
9808 case T_DOUBLE:
9809 kandql(dst, src1, src2);
9810 break;
9811 default:
9812 fatal("Unexpected type argument %s", type2name(type));
9813 break;
9814 }
9815 }
9816
9817 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9818 switch(type) {
9819 case T_BOOLEAN:
9820 case T_BYTE:
9821 korbl(dst, src1, src2);
9822 break;
9823 case T_CHAR:
9824 case T_SHORT:
9825 korwl(dst, src1, src2);
9826 break;
9827 case T_INT:
9828 case T_FLOAT:
9829 kordl(dst, src1, src2);
9830 break;
9831 case T_LONG:
9832 case T_DOUBLE:
9833 korql(dst, src1, src2);
9834 break;
9835 default:
9836 fatal("Unexpected type argument %s", type2name(type));
9837 break;
9838 }
9839 }
9840
9841 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9842 switch(type) {
9843 case T_BOOLEAN:
9844 case T_BYTE:
9845 kxorbl(dst, src1, src2);
9846 break;
9847 case T_CHAR:
9848 case T_SHORT:
9849 kxorwl(dst, src1, src2);
9850 break;
9851 case T_INT:
9852 case T_FLOAT:
9853 kxordl(dst, src1, src2);
9854 break;
9855 case T_LONG:
9856 case T_DOUBLE:
9857 kxorql(dst, src1, src2);
9858 break;
9859 default:
9860 fatal("Unexpected type argument %s", type2name(type));
9861 break;
9862 }
9863 }
9864
9865 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9866 switch(type) {
9867 case T_BOOLEAN:
9868 case T_BYTE:
9869 evpermb(dst, mask, nds, src, merge, vector_len); break;
9870 case T_CHAR:
9871 case T_SHORT:
9872 evpermw(dst, mask, nds, src, merge, vector_len); break;
9873 case T_INT:
9874 case T_FLOAT:
9875 evpermd(dst, mask, nds, src, merge, vector_len); break;
9876 case T_LONG:
9877 case T_DOUBLE:
9878 evpermq(dst, mask, nds, src, merge, vector_len); break;
9879 default:
9880 fatal("Unexpected type argument %s", type2name(type)); break;
9881 }
9882 }
9883
9884 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9885 switch(type) {
9886 case T_BOOLEAN:
9887 case T_BYTE:
9888 evpermb(dst, mask, nds, src, merge, vector_len); break;
9889 case T_CHAR:
9890 case T_SHORT:
9891 evpermw(dst, mask, nds, src, merge, vector_len); break;
9892 case T_INT:
9893 case T_FLOAT:
9894 evpermd(dst, mask, nds, src, merge, vector_len); break;
9895 case T_LONG:
9896 case T_DOUBLE:
9897 evpermq(dst, mask, nds, src, merge, vector_len); break;
9898 default:
9899 fatal("Unexpected type argument %s", type2name(type)); break;
9900 }
9901 }
9902
9903 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9904 switch(type) {
9905 case T_BYTE:
9906 evpminub(dst, mask, nds, src, merge, vector_len); break;
9907 case T_SHORT:
9908 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9909 case T_INT:
9910 evpminud(dst, mask, nds, src, merge, vector_len); break;
9911 case T_LONG:
9912 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9913 default:
9914 fatal("Unexpected type argument %s", type2name(type)); break;
9915 }
9916 }
9917
9918 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9919 switch(type) {
9920 case T_BYTE:
9921 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9922 case T_SHORT:
9923 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9924 case T_INT:
9925 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9926 case T_LONG:
9927 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9928 default:
9929 fatal("Unexpected type argument %s", type2name(type)); break;
9930 }
9931 }
9932
9933 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9934 switch(type) {
9935 case T_BYTE:
9936 evpminub(dst, mask, nds, src, merge, vector_len); break;
9937 case T_SHORT:
9938 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9939 case T_INT:
9940 evpminud(dst, mask, nds, src, merge, vector_len); break;
9941 case T_LONG:
9942 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9943 default:
9944 fatal("Unexpected type argument %s", type2name(type)); break;
9945 }
9946 }
9947
9948 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9949 switch(type) {
9950 case T_BYTE:
9951 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9952 case T_SHORT:
9953 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9954 case T_INT:
9955 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9956 case T_LONG:
9957 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9958 default:
9959 fatal("Unexpected type argument %s", type2name(type)); break;
9960 }
9961 }
9962
9963 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9964 switch(type) {
9965 case T_BYTE:
9966 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9967 case T_SHORT:
9968 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9969 case T_INT:
9970 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9971 case T_LONG:
9972 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9973 default:
9974 fatal("Unexpected type argument %s", type2name(type)); break;
9975 }
9976 }
9977
9978 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9979 switch(type) {
9980 case T_BYTE:
9981 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9982 case T_SHORT:
9983 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9984 case T_INT:
9985 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9986 case T_LONG:
9987 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9988 default:
9989 fatal("Unexpected type argument %s", type2name(type)); break;
9990 }
9991 }
9992
9993 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9994 switch(type) {
9995 case T_BYTE:
9996 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9997 case T_SHORT:
9998 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9999 case T_INT:
10000 evpminsd(dst, mask, nds, src, merge, vector_len); break;
10001 case T_LONG:
10002 evpminsq(dst, mask, nds, src, merge, vector_len); break;
10003 default:
10004 fatal("Unexpected type argument %s", type2name(type)); break;
10005 }
10006 }
10007
10008 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10009 switch(type) {
10010 case T_BYTE:
10011 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
10012 case T_SHORT:
10013 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
10014 case T_INT:
10015 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
10016 case T_LONG:
10017 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
10018 default:
10019 fatal("Unexpected type argument %s", type2name(type)); break;
10020 }
10021 }
10022
10023 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10024 switch(type) {
10025 case T_INT:
10026 evpxord(dst, mask, nds, src, merge, vector_len); break;
10027 case T_LONG:
10028 evpxorq(dst, mask, nds, src, merge, vector_len); break;
10029 default:
10030 fatal("Unexpected type argument %s", type2name(type)); break;
10031 }
10032 }
10033
10034 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10035 switch(type) {
10036 case T_INT:
10037 evpxord(dst, mask, nds, src, merge, vector_len); break;
10038 case T_LONG:
10039 evpxorq(dst, mask, nds, src, merge, vector_len); break;
10040 default:
10041 fatal("Unexpected type argument %s", type2name(type)); break;
10042 }
10043 }
10044
10045 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10046 switch(type) {
10047 case T_INT:
10048 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10049 case T_LONG:
10050 evporq(dst, mask, nds, src, merge, vector_len); break;
10051 default:
10052 fatal("Unexpected type argument %s", type2name(type)); break;
10053 }
10054 }
10055
10056 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10057 switch(type) {
10058 case T_INT:
10059 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10060 case T_LONG:
10061 evporq(dst, mask, nds, src, merge, vector_len); break;
10062 default:
10063 fatal("Unexpected type argument %s", type2name(type)); break;
10064 }
10065 }
10066
10067 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10068 switch(type) {
10069 case T_INT:
10070 evpandd(dst, mask, nds, src, merge, vector_len); break;
10071 case T_LONG:
10072 evpandq(dst, mask, nds, src, merge, vector_len); break;
10073 default:
10074 fatal("Unexpected type argument %s", type2name(type)); break;
10075 }
10076 }
10077
10078 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10079 switch(type) {
10080 case T_INT:
10081 evpandd(dst, mask, nds, src, merge, vector_len); break;
10082 case T_LONG:
10083 evpandq(dst, mask, nds, src, merge, vector_len); break;
10084 default:
10085 fatal("Unexpected type argument %s", type2name(type)); break;
10086 }
10087 }
10088
10089 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
10090 switch(masklen) {
10091 case 8:
10092 kortestbl(src1, src2);
10093 break;
10094 case 16:
10095 kortestwl(src1, src2);
10096 break;
10097 case 32:
10098 kortestdl(src1, src2);
10099 break;
10100 case 64:
10101 kortestql(src1, src2);
10102 break;
10103 default:
10104 fatal("Unexpected mask length %d", masklen);
10105 break;
10106 }
10107 }
10108
10109
10110 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
10111 switch(masklen) {
10112 case 8:
10113 ktestbl(src1, src2);
10114 break;
10115 case 16:
10116 ktestwl(src1, src2);
10117 break;
10118 case 32:
10119 ktestdl(src1, src2);
10120 break;
10121 case 64:
10122 ktestql(src1, src2);
10123 break;
10124 default:
10125 fatal("Unexpected mask length %d", masklen);
10126 break;
10127 }
10128 }
10129
10130 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10131 switch(type) {
10132 case T_INT:
10133 evprold(dst, mask, src, shift, merge, vlen_enc); break;
10134 case T_LONG:
10135 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
10136 default:
10137 fatal("Unexpected type argument %s", type2name(type)); break;
10138 break;
10139 }
10140 }
10141
10142 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10143 switch(type) {
10144 case T_INT:
10145 evprord(dst, mask, src, shift, merge, vlen_enc); break;
10146 case T_LONG:
10147 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
10148 default:
10149 fatal("Unexpected type argument %s", type2name(type)); break;
10150 }
10151 }
10152
10153 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10154 switch(type) {
10155 case T_INT:
10156 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
10157 case T_LONG:
10158 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
10159 default:
10160 fatal("Unexpected type argument %s", type2name(type)); break;
10161 }
10162 }
10163
10164 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10165 switch(type) {
10166 case T_INT:
10167 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
10168 case T_LONG:
10169 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
10170 default:
10171 fatal("Unexpected type argument %s", type2name(type)); break;
10172 }
10173 }
10174
10175 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10176 assert(rscratch != noreg || always_reachable(src), "missing");
10177
10178 if (reachable(src)) {
10179 evpandq(dst, nds, as_Address(src), vector_len);
10180 } else {
10181 lea(rscratch, src);
10182 evpandq(dst, nds, Address(rscratch, 0), vector_len);
10183 }
10184 }
10185
10186 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
10187 assert(rscratch != noreg || always_reachable(src), "missing");
10188
10189 if (reachable(src)) {
10190 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
10191 } else {
10192 lea(rscratch, src);
10193 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
10194 }
10195 }
10196
10197 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10198 assert(rscratch != noreg || always_reachable(src), "missing");
10199
10200 if (reachable(src)) {
10201 evporq(dst, nds, as_Address(src), vector_len);
10202 } else {
10203 lea(rscratch, src);
10204 evporq(dst, nds, Address(rscratch, 0), vector_len);
10205 }
10206 }
10207
10208 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10209 assert(rscratch != noreg || always_reachable(src), "missing");
10210
10211 if (reachable(src)) {
10212 vpshufb(dst, nds, as_Address(src), vector_len);
10213 } else {
10214 lea(rscratch, src);
10215 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
10216 }
10217 }
10218
10219 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10220 assert(rscratch != noreg || always_reachable(src), "missing");
10221
10222 if (reachable(src)) {
10223 Assembler::vpor(dst, nds, as_Address(src), vector_len);
10224 } else {
10225 lea(rscratch, src);
10226 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
10227 }
10228 }
10229
10230 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
10231 assert(rscratch != noreg || always_reachable(src3), "missing");
10232
10233 if (reachable(src3)) {
10234 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
10235 } else {
10236 lea(rscratch, src3);
10237 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
10238 }
10239 }
10240
10241 #if COMPILER2_OR_JVMCI
10242
10243 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
10244 Register length, Register temp, int vec_enc) {
10245 // Computing mask for predicated vector store.
10246 movptr(temp, -1);
10247 bzhiq(temp, temp, length);
10248 kmov(mask, temp);
10249 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
10250 }
10251
10252 // Set memory operation for length "less than" 64 bytes.
10253 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
10254 XMMRegister xmm, KRegister mask, Register length,
10255 Register temp, bool use64byteVector) {
10256 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10257 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10258 if (!use64byteVector) {
10259 fill32(dst, disp, xmm);
10260 subptr(length, 32 >> shift);
10261 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
10262 } else {
10263 assert(MaxVectorSize == 64, "vector length != 64");
10264 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
10265 }
10266 }
10267
10268
10269 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
10270 XMMRegister xmm, KRegister mask, Register length,
10271 Register temp) {
10272 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10273 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10274 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
10275 }
10276
10277
10278 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
10279 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10280 vmovdqu(dst, xmm);
10281 }
10282
10283 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
10284 fill32(Address(dst, disp), xmm);
10285 }
10286
10287 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
10288 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10289 if (!use64byteVector) {
10290 fill32(dst, xmm);
10291 fill32(dst.plus_disp(32), xmm);
10292 } else {
10293 evmovdquq(dst, xmm, Assembler::AVX_512bit);
10294 }
10295 }
10296
10297 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
10298 fill64(Address(dst, disp), xmm, use64byteVector);
10299 }
10300
10301 #ifdef _LP64
10302 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
10303 Register count, Register rtmp, XMMRegister xtmp) {
10304 Label L_exit;
10305 Label L_fill_start;
10306 Label L_fill_64_bytes;
10307 Label L_fill_96_bytes;
10308 Label L_fill_128_bytes;
10309 Label L_fill_128_bytes_loop;
10310 Label L_fill_128_loop_header;
10311 Label L_fill_128_bytes_loop_header;
10312 Label L_fill_128_bytes_loop_pre_header;
10313 Label L_fill_zmm_sequence;
10314
10315 int shift = -1;
10316 int avx3threshold = VM_Version::avx3_threshold();
10317 switch(type) {
10318 case T_BYTE: shift = 0;
10319 break;
10320 case T_SHORT: shift = 1;
10321 break;
10322 case T_INT: shift = 2;
10323 break;
10324 /* Uncomment when LONG fill stubs are supported.
10325 case T_LONG: shift = 3;
10326 break;
10327 */
10328 default:
10329 fatal("Unhandled type: %s\n", type2name(type));
10330 }
10331
10332 if ((avx3threshold != 0) || (MaxVectorSize == 32)) {
10333
10334 if (MaxVectorSize == 64) {
10335 cmpq(count, avx3threshold >> shift);
10336 jcc(Assembler::greater, L_fill_zmm_sequence);
10337 }
10338
10339 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
10340
10341 bind(L_fill_start);
10342
10343 cmpq(count, 32 >> shift);
10344 jccb(Assembler::greater, L_fill_64_bytes);
10345 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
10346 jmp(L_exit);
10347
10348 bind(L_fill_64_bytes);
10349 cmpq(count, 64 >> shift);
10350 jccb(Assembler::greater, L_fill_96_bytes);
10351 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10352 jmp(L_exit);
10353
10354 bind(L_fill_96_bytes);
10355 cmpq(count, 96 >> shift);
10356 jccb(Assembler::greater, L_fill_128_bytes);
10357 fill64(to, 0, xtmp);
10358 subq(count, 64 >> shift);
10359 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10360 jmp(L_exit);
10361
10362 bind(L_fill_128_bytes);
10363 cmpq(count, 128 >> shift);
10364 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10365 fill64(to, 0, xtmp);
10366 fill32(to, 64, xtmp);
10367 subq(count, 96 >> shift);
10368 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10369 jmp(L_exit);
10370
10371 bind(L_fill_128_bytes_loop_pre_header);
10372 {
10373 mov(rtmp, to);
10374 andq(rtmp, 31);
10375 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10376 negq(rtmp);
10377 addq(rtmp, 32);
10378 mov64(r8, -1L);
10379 bzhiq(r8, r8, rtmp);
10380 kmovql(k2, r8);
10381 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10382 addq(to, rtmp);
10383 shrq(rtmp, shift);
10384 subq(count, rtmp);
10385 }
10386
10387 cmpq(count, 128 >> shift);
10388 jcc(Assembler::less, L_fill_start);
10389
10390 bind(L_fill_128_bytes_loop_header);
10391 subq(count, 128 >> shift);
10392
10393 align32();
10394 bind(L_fill_128_bytes_loop);
10395 fill64(to, 0, xtmp);
10396 fill64(to, 64, xtmp);
10397 addq(to, 128);
10398 subq(count, 128 >> shift);
10399 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10400
10401 addq(count, 128 >> shift);
10402 jcc(Assembler::zero, L_exit);
10403 jmp(L_fill_start);
10404 }
10405
10406 if (MaxVectorSize == 64) {
10407 // Sequence using 64 byte ZMM register.
10408 Label L_fill_128_bytes_zmm;
10409 Label L_fill_192_bytes_zmm;
10410 Label L_fill_192_bytes_loop_zmm;
10411 Label L_fill_192_bytes_loop_header_zmm;
10412 Label L_fill_192_bytes_loop_pre_header_zmm;
10413 Label L_fill_start_zmm_sequence;
10414
10415 bind(L_fill_zmm_sequence);
10416 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10417
10418 bind(L_fill_start_zmm_sequence);
10419 cmpq(count, 64 >> shift);
10420 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10421 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10422 jmp(L_exit);
10423
10424 bind(L_fill_128_bytes_zmm);
10425 cmpq(count, 128 >> shift);
10426 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10427 fill64(to, 0, xtmp, true);
10428 subq(count, 64 >> shift);
10429 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10430 jmp(L_exit);
10431
10432 bind(L_fill_192_bytes_zmm);
10433 cmpq(count, 192 >> shift);
10434 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10435 fill64(to, 0, xtmp, true);
10436 fill64(to, 64, xtmp, true);
10437 subq(count, 128 >> shift);
10438 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10439 jmp(L_exit);
10440
10441 bind(L_fill_192_bytes_loop_pre_header_zmm);
10442 {
10443 movq(rtmp, to);
10444 andq(rtmp, 63);
10445 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10446 negq(rtmp);
10447 addq(rtmp, 64);
10448 mov64(r8, -1L);
10449 bzhiq(r8, r8, rtmp);
10450 kmovql(k2, r8);
10451 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10452 addq(to, rtmp);
10453 shrq(rtmp, shift);
10454 subq(count, rtmp);
10455 }
10456
10457 cmpq(count, 192 >> shift);
10458 jcc(Assembler::less, L_fill_start_zmm_sequence);
10459
10460 bind(L_fill_192_bytes_loop_header_zmm);
10461 subq(count, 192 >> shift);
10462
10463 align32();
10464 bind(L_fill_192_bytes_loop_zmm);
10465 fill64(to, 0, xtmp, true);
10466 fill64(to, 64, xtmp, true);
10467 fill64(to, 128, xtmp, true);
10468 addq(to, 192);
10469 subq(count, 192 >> shift);
10470 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10471
10472 addq(count, 192 >> shift);
10473 jcc(Assembler::zero, L_exit);
10474 jmp(L_fill_start_zmm_sequence);
10475 }
10476 bind(L_exit);
10477 }
10478 #endif
10479 #endif //COMPILER2_OR_JVMCI
10480
10481
10482 #ifdef _LP64
10483 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10484 Label done;
10485 cvttss2sil(dst, src);
10486 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10487 cmpl(dst, 0x80000000); // float_sign_flip
10488 jccb(Assembler::notEqual, done);
10489 subptr(rsp, 8);
10490 movflt(Address(rsp, 0), src);
10491 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10492 pop(dst);
10493 bind(done);
10494 }
10495
10496 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10497 Label done;
10498 cvttsd2sil(dst, src);
10499 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10500 cmpl(dst, 0x80000000); // float_sign_flip
10501 jccb(Assembler::notEqual, done);
10502 subptr(rsp, 8);
10503 movdbl(Address(rsp, 0), src);
10504 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10505 pop(dst);
10506 bind(done);
10507 }
10508
10509 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10510 Label done;
10511 cvttss2siq(dst, src);
10512 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10513 jccb(Assembler::notEqual, done);
10514 subptr(rsp, 8);
10515 movflt(Address(rsp, 0), src);
10516 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10517 pop(dst);
10518 bind(done);
10519 }
10520
10521 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10522 // Following code is line by line assembly translation rounding algorithm.
10523 // Please refer to java.lang.Math.round(float) algorithm for details.
10524 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10525 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10526 const int32_t FloatConsts_EXP_BIAS = 127;
10527 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10528 const int32_t MINUS_32 = 0xFFFFFFE0;
10529 Label L_special_case, L_block1, L_exit;
10530 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10531 movdl(dst, src);
10532 andl(dst, rtmp);
10533 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10534 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10535 subl(rtmp, dst);
10536 movl(rcx, rtmp);
10537 movl(dst, MINUS_32);
10538 testl(rtmp, dst);
10539 jccb(Assembler::notEqual, L_special_case);
10540 movdl(dst, src);
10541 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10542 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10543 movdl(rtmp, src);
10544 testl(rtmp, rtmp);
10545 jccb(Assembler::greaterEqual, L_block1);
10546 negl(dst);
10547 bind(L_block1);
10548 sarl(dst);
10549 addl(dst, 0x1);
10550 sarl(dst, 0x1);
10551 jmp(L_exit);
10552 bind(L_special_case);
10553 convert_f2i(dst, src);
10554 bind(L_exit);
10555 }
10556
10557 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10558 // Following code is line by line assembly translation rounding algorithm.
10559 // Please refer to java.lang.Math.round(double) algorithm for details.
10560 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10561 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10562 const int64_t DoubleConsts_EXP_BIAS = 1023;
10563 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10564 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10565 Label L_special_case, L_block1, L_exit;
10566 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10567 movq(dst, src);
10568 andq(dst, rtmp);
10569 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10570 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10571 subq(rtmp, dst);
10572 movq(rcx, rtmp);
10573 mov64(dst, MINUS_64);
10574 testq(rtmp, dst);
10575 jccb(Assembler::notEqual, L_special_case);
10576 movq(dst, src);
10577 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10578 andq(dst, rtmp);
10579 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10580 orq(dst, rtmp);
10581 movq(rtmp, src);
10582 testq(rtmp, rtmp);
10583 jccb(Assembler::greaterEqual, L_block1);
10584 negq(dst);
10585 bind(L_block1);
10586 sarq(dst);
10587 addq(dst, 0x1);
10588 sarq(dst, 0x1);
10589 jmp(L_exit);
10590 bind(L_special_case);
10591 convert_d2l(dst, src);
10592 bind(L_exit);
10593 }
10594
10595 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10596 Label done;
10597 cvttsd2siq(dst, src);
10598 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10599 jccb(Assembler::notEqual, done);
10600 subptr(rsp, 8);
10601 movdbl(Address(rsp, 0), src);
10602 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10603 pop(dst);
10604 bind(done);
10605 }
10606
10607 void MacroAssembler::cache_wb(Address line)
10608 {
10609 // 64 bit cpus always support clflush
10610 assert(VM_Version::supports_clflush(), "clflush should be available");
10611 bool optimized = VM_Version::supports_clflushopt();
10612 bool no_evict = VM_Version::supports_clwb();
10613
10614 // prefer clwb (writeback without evict) otherwise
10615 // prefer clflushopt (potentially parallel writeback with evict)
10616 // otherwise fallback on clflush (serial writeback with evict)
10617
10618 if (optimized) {
10619 if (no_evict) {
10620 clwb(line);
10621 } else {
10622 clflushopt(line);
10623 }
10624 } else {
10625 // no need for fence when using CLFLUSH
10626 clflush(line);
10627 }
10628 }
10629
10630 void MacroAssembler::cache_wbsync(bool is_pre)
10631 {
10632 assert(VM_Version::supports_clflush(), "clflush should be available");
10633 bool optimized = VM_Version::supports_clflushopt();
10634 bool no_evict = VM_Version::supports_clwb();
10635
10636 // pick the correct implementation
10637
10638 if (!is_pre && (optimized || no_evict)) {
10639 // need an sfence for post flush when using clflushopt or clwb
10640 // otherwise no no need for any synchroniaztion
10641
10642 sfence();
10643 }
10644 }
10645
10646 #endif // _LP64
10647
10648 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10649 switch (cond) {
10650 // Note some conditions are synonyms for others
10651 case Assembler::zero: return Assembler::notZero;
10652 case Assembler::notZero: return Assembler::zero;
10653 case Assembler::less: return Assembler::greaterEqual;
10654 case Assembler::lessEqual: return Assembler::greater;
10655 case Assembler::greater: return Assembler::lessEqual;
10656 case Assembler::greaterEqual: return Assembler::less;
10657 case Assembler::below: return Assembler::aboveEqual;
10658 case Assembler::belowEqual: return Assembler::above;
10659 case Assembler::above: return Assembler::belowEqual;
10660 case Assembler::aboveEqual: return Assembler::below;
10661 case Assembler::overflow: return Assembler::noOverflow;
10662 case Assembler::noOverflow: return Assembler::overflow;
10663 case Assembler::negative: return Assembler::positive;
10664 case Assembler::positive: return Assembler::negative;
10665 case Assembler::parity: return Assembler::noParity;
10666 case Assembler::noParity: return Assembler::parity;
10667 }
10668 ShouldNotReachHere(); return Assembler::overflow;
10669 }
10670
10671 // This is simply a call to Thread::current()
10672 void MacroAssembler::get_thread(Register thread) {
10673 if (thread != rax) {
10674 push(rax);
10675 }
10676 LP64_ONLY(push(rdi);)
10677 LP64_ONLY(push(rsi);)
10678 push(rdx);
10679 push(rcx);
10680 #ifdef _LP64
10681 push(r8);
10682 push(r9);
10683 push(r10);
10684 push(r11);
10685 #endif
10686
10687 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10688
10689 #ifdef _LP64
10690 pop(r11);
10691 pop(r10);
10692 pop(r9);
10693 pop(r8);
10694 #endif
10695 pop(rcx);
10696 pop(rdx);
10697 LP64_ONLY(pop(rsi);)
10698 LP64_ONLY(pop(rdi);)
10699 if (thread != rax) {
10700 mov(thread, rax);
10701 pop(rax);
10702 }
10703 }
10704
10705 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10706 Label L_stack_ok;
10707 if (bias == 0) {
10708 testptr(sp, 2 * wordSize - 1);
10709 } else {
10710 // lea(tmp, Address(rsp, bias);
10711 mov(tmp, sp);
10712 addptr(tmp, bias);
10713 testptr(tmp, 2 * wordSize - 1);
10714 }
10715 jcc(Assembler::equal, L_stack_ok);
10716 block_comment(msg);
10717 stop(msg);
10718 bind(L_stack_ok);
10719 }
10720
10721 // Implements lightweight-locking.
10722 //
10723 // obj: the object to be locked
10724 // reg_rax: rax
10725 // thread: the thread which attempts to lock obj
10726 // tmp: a temporary register
10727 void MacroAssembler::lightweight_lock(Register basic_lock, Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10728 assert(reg_rax == rax, "");
10729 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10730
10731 Label push;
10732 const Register top = tmp;
10733
10734 // Preload the markWord. It is important that this is the first
10735 // instruction emitted as it is part of C1's null check semantics.
10736 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10737
10738 if (UseObjectMonitorTable) {
10739 // Clear cache in case fast locking succeeds.
10740 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10741 }
10742
10743 // Load top.
10744 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10745
10746 // Check if the lock-stack is full.
10747 cmpl(top, LockStack::end_offset());
10748 jcc(Assembler::greaterEqual, slow);
10749
10750 // Check for recursion.
10751 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10752 jcc(Assembler::equal, push);
10753
10754 // Check header for monitor (0b10).
10755 testptr(reg_rax, markWord::monitor_value);
10756 jcc(Assembler::notZero, slow);
10757
10758 // Try to lock. Transition lock bits 0b01 => 0b00
10759 movptr(tmp, reg_rax);
10760 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10761 orptr(reg_rax, markWord::unlocked_value);
10762 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10763 jcc(Assembler::notEqual, slow);
10764
10765 // Restore top, CAS clobbers register.
10766 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10767
10768 bind(push);
10769 // After successful lock, push object on lock-stack.
10770 movptr(Address(thread, top), obj);
10771 incrementl(top, oopSize);
10772 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10773 }
10774
10775 // Implements lightweight-unlocking.
10776 //
10777 // obj: the object to be unlocked
10778 // reg_rax: rax
10779 // thread: the thread
10780 // tmp: a temporary register
10781 void MacroAssembler::lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10782 assert(reg_rax == rax, "");
10783 assert_different_registers(obj, reg_rax, thread, tmp);
10784
10785 Label unlocked, push_and_slow;
10786 const Register top = tmp;
10787
10788 // Check if obj is top of lock-stack.
10789 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10790 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10791 jcc(Assembler::notEqual, slow);
10792
10793 // Pop lock-stack.
10794 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10795 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10796
10797 // Check if recursive.
10798 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10799 jcc(Assembler::equal, unlocked);
10800
10801 // Not recursive. Check header for monitor (0b10).
10802 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10803 testptr(reg_rax, markWord::monitor_value);
10804 jcc(Assembler::notZero, push_and_slow);
10805
10806 #ifdef ASSERT
10807 // Check header not unlocked (0b01).
10808 Label not_unlocked;
10809 testptr(reg_rax, markWord::unlocked_value);
10810 jcc(Assembler::zero, not_unlocked);
10811 stop("lightweight_unlock already unlocked");
10812 bind(not_unlocked);
10813 #endif
10814
10815 // Try to unlock. Transition lock bits 0b00 => 0b01
10816 movptr(tmp, reg_rax);
10817 orptr(tmp, markWord::unlocked_value);
10818 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10819 jcc(Assembler::equal, unlocked);
10820
10821 bind(push_and_slow);
10822 // Restore lock-stack and handle the unlock in runtime.
10823 #ifdef ASSERT
10824 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10825 movptr(Address(thread, top), obj);
10826 #endif
10827 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10828 jmp(slow);
10829
10830 bind(unlocked);
10831 }
10832
10833 #ifdef _LP64
10834 // Saves legacy GPRs state on stack.
10835 void MacroAssembler::save_legacy_gprs() {
10836 subq(rsp, 16 * wordSize);
10837 movq(Address(rsp, 15 * wordSize), rax);
10838 movq(Address(rsp, 14 * wordSize), rcx);
10839 movq(Address(rsp, 13 * wordSize), rdx);
10840 movq(Address(rsp, 12 * wordSize), rbx);
10841 movq(Address(rsp, 10 * wordSize), rbp);
10842 movq(Address(rsp, 9 * wordSize), rsi);
10843 movq(Address(rsp, 8 * wordSize), rdi);
10844 movq(Address(rsp, 7 * wordSize), r8);
10845 movq(Address(rsp, 6 * wordSize), r9);
10846 movq(Address(rsp, 5 * wordSize), r10);
10847 movq(Address(rsp, 4 * wordSize), r11);
10848 movq(Address(rsp, 3 * wordSize), r12);
10849 movq(Address(rsp, 2 * wordSize), r13);
10850 movq(Address(rsp, wordSize), r14);
10851 movq(Address(rsp, 0), r15);
10852 }
10853
10854 // Resotres back legacy GPRs state from stack.
10855 void MacroAssembler::restore_legacy_gprs() {
10856 movq(r15, Address(rsp, 0));
10857 movq(r14, Address(rsp, wordSize));
10858 movq(r13, Address(rsp, 2 * wordSize));
10859 movq(r12, Address(rsp, 3 * wordSize));
10860 movq(r11, Address(rsp, 4 * wordSize));
10861 movq(r10, Address(rsp, 5 * wordSize));
10862 movq(r9, Address(rsp, 6 * wordSize));
10863 movq(r8, Address(rsp, 7 * wordSize));
10864 movq(rdi, Address(rsp, 8 * wordSize));
10865 movq(rsi, Address(rsp, 9 * wordSize));
10866 movq(rbp, Address(rsp, 10 * wordSize));
10867 movq(rbx, Address(rsp, 12 * wordSize));
10868 movq(rdx, Address(rsp, 13 * wordSize));
10869 movq(rcx, Address(rsp, 14 * wordSize));
10870 movq(rax, Address(rsp, 15 * wordSize));
10871 addq(rsp, 16 * wordSize);
10872 }
10873
10874 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10875 if (VM_Version::supports_apx_f()) {
10876 esetzucc(comparison, dst);
10877 } else {
10878 setb(comparison, dst);
10879 movzbl(dst, dst);
10880 }
10881 }
10882 #endif