1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "crc32c.h"
32 #include "gc/shared/barrierSet.hpp"
33 #include "gc/shared/barrierSetAssembler.hpp"
34 #include "gc/shared/collectedHeap.inline.hpp"
35 #include "gc/shared/tlab_globals.hpp"
36 #include "interpreter/bytecodeHistogram.hpp"
37 #include "interpreter/interpreter.hpp"
38 #include "interpreter/interpreterRuntime.hpp"
39 #include "jvm.h"
40 #include "memory/resourceArea.hpp"
41 #include "memory/universe.hpp"
42 #include "oops/accessDecorators.hpp"
43 #include "oops/compressedKlass.inline.hpp"
44 #include "oops/compressedOops.inline.hpp"
45 #include "oops/klass.inline.hpp"
46 #include "prims/methodHandles.hpp"
47 #include "runtime/continuation.hpp"
48 #include "runtime/interfaceSupport.inline.hpp"
49 #include "runtime/javaThread.hpp"
50 #include "runtime/jniHandles.hpp"
51 #include "runtime/objectMonitor.hpp"
52 #include "runtime/os.hpp"
53 #include "runtime/safepoint.hpp"
54 #include "runtime/safepointMechanism.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/checkedCast.hpp"
58 #include "utilities/macros.hpp"
59
60 #ifdef PRODUCT
61 #define BLOCK_COMMENT(str) /* nothing */
62 #define STOP(error) stop(error)
63 #else
64 #define BLOCK_COMMENT(str) block_comment(str)
65 #define STOP(error) block_comment(error); stop(error)
66 #endif
67
68 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
69
70 #ifdef ASSERT
71 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
72 #endif
73
74 static const Assembler::Condition reverse[] = {
75 Assembler::noOverflow /* overflow = 0x0 */ ,
76 Assembler::overflow /* noOverflow = 0x1 */ ,
77 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
78 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
79 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
80 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
81 Assembler::above /* belowEqual = 0x6 */ ,
82 Assembler::belowEqual /* above = 0x7 */ ,
83 Assembler::positive /* negative = 0x8 */ ,
84 Assembler::negative /* positive = 0x9 */ ,
85 Assembler::noParity /* parity = 0xa */ ,
86 Assembler::parity /* noParity = 0xb */ ,
87 Assembler::greaterEqual /* less = 0xc */ ,
88 Assembler::less /* greaterEqual = 0xd */ ,
89 Assembler::greater /* lessEqual = 0xe */ ,
90 Assembler::lessEqual /* greater = 0xf, */
91
92 };
93
94
95 // Implementation of MacroAssembler
96
97 // First all the versions that have distinct versions depending on 32/64 bit
98 // Unless the difference is trivial (1 line or so).
99
100 #ifndef _LP64
101
102 // 32bit versions
103
104 Address MacroAssembler::as_Address(AddressLiteral adr) {
105 return Address(adr.target(), adr.rspec());
106 }
107
108 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
109 assert(rscratch == noreg, "");
110 return Address::make_array(adr);
111 }
112
113 void MacroAssembler::call_VM_leaf_base(address entry_point,
114 int number_of_arguments) {
115 call(RuntimeAddress(entry_point));
116 increment(rsp, number_of_arguments * wordSize);
117 }
118
119 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
120 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
121 }
122
123
124 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
125 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
126 }
127
128 void MacroAssembler::cmpoop(Address src1, jobject obj) {
129 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
130 }
131
132 void MacroAssembler::cmpoop(Register src1, jobject obj, Register rscratch) {
133 assert(rscratch == noreg, "redundant");
134 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
135 }
136
137 void MacroAssembler::extend_sign(Register hi, Register lo) {
138 // According to Intel Doc. AP-526, "Integer Divide", p.18.
139 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
140 cdql();
141 } else {
142 movl(hi, lo);
143 sarl(hi, 31);
144 }
145 }
146
147 void MacroAssembler::jC2(Register tmp, Label& L) {
148 // set parity bit if FPU flag C2 is set (via rax)
149 save_rax(tmp);
150 fwait(); fnstsw_ax();
151 sahf();
152 restore_rax(tmp);
153 // branch
154 jcc(Assembler::parity, L);
155 }
156
157 void MacroAssembler::jnC2(Register tmp, Label& L) {
158 // set parity bit if FPU flag C2 is set (via rax)
159 save_rax(tmp);
160 fwait(); fnstsw_ax();
161 sahf();
162 restore_rax(tmp);
163 // branch
164 jcc(Assembler::noParity, L);
165 }
166
167 // 32bit can do a case table jump in one instruction but we no longer allow the base
168 // to be installed in the Address class
169 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
170 assert(rscratch == noreg, "not needed");
171 jmp(as_Address(entry, noreg));
172 }
173
174 // Note: y_lo will be destroyed
175 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
176 // Long compare for Java (semantics as described in JVM spec.)
177 Label high, low, done;
178
179 cmpl(x_hi, y_hi);
180 jcc(Assembler::less, low);
181 jcc(Assembler::greater, high);
182 // x_hi is the return register
183 xorl(x_hi, x_hi);
184 cmpl(x_lo, y_lo);
185 jcc(Assembler::below, low);
186 jcc(Assembler::equal, done);
187
188 bind(high);
189 xorl(x_hi, x_hi);
190 increment(x_hi);
191 jmp(done);
192
193 bind(low);
194 xorl(x_hi, x_hi);
195 decrementl(x_hi);
196
197 bind(done);
198 }
199
200 void MacroAssembler::lea(Register dst, AddressLiteral src) {
201 mov_literal32(dst, (int32_t)src.target(), src.rspec());
202 }
203
204 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
205 assert(rscratch == noreg, "not needed");
206
207 // leal(dst, as_Address(adr));
208 // see note in movl as to why we must use a move
209 mov_literal32(dst, (int32_t)adr.target(), adr.rspec());
210 }
211
212 void MacroAssembler::leave() {
213 mov(rsp, rbp);
214 pop(rbp);
215 }
216
217 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
218 // Multiplication of two Java long values stored on the stack
219 // as illustrated below. Result is in rdx:rax.
220 //
221 // rsp ---> [ ?? ] \ \
222 // .... | y_rsp_offset |
223 // [ y_lo ] / (in bytes) | x_rsp_offset
224 // [ y_hi ] | (in bytes)
225 // .... |
226 // [ x_lo ] /
227 // [ x_hi ]
228 // ....
229 //
230 // Basic idea: lo(result) = lo(x_lo * y_lo)
231 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
232 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
233 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
234 Label quick;
235 // load x_hi, y_hi and check if quick
236 // multiplication is possible
237 movl(rbx, x_hi);
238 movl(rcx, y_hi);
239 movl(rax, rbx);
240 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
241 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
242 // do full multiplication
243 // 1st step
244 mull(y_lo); // x_hi * y_lo
245 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
246 // 2nd step
247 movl(rax, x_lo);
248 mull(rcx); // x_lo * y_hi
249 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
250 // 3rd step
251 bind(quick); // note: rbx, = 0 if quick multiply!
252 movl(rax, x_lo);
253 mull(y_lo); // x_lo * y_lo
254 addl(rdx, rbx); // correct hi(x_lo * y_lo)
255 }
256
257 void MacroAssembler::lneg(Register hi, Register lo) {
258 negl(lo);
259 adcl(hi, 0);
260 negl(hi);
261 }
262
263 void MacroAssembler::lshl(Register hi, Register lo) {
264 // Java shift left long support (semantics as described in JVM spec., p.305)
265 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
266 // shift value is in rcx !
267 assert(hi != rcx, "must not use rcx");
268 assert(lo != rcx, "must not use rcx");
269 const Register s = rcx; // shift count
270 const int n = BitsPerWord;
271 Label L;
272 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
273 cmpl(s, n); // if (s < n)
274 jcc(Assembler::less, L); // else (s >= n)
275 movl(hi, lo); // x := x << n
276 xorl(lo, lo);
277 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
278 bind(L); // s (mod n) < n
279 shldl(hi, lo); // x := x << s
280 shll(lo);
281 }
282
283
284 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
285 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
286 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
287 assert(hi != rcx, "must not use rcx");
288 assert(lo != rcx, "must not use rcx");
289 const Register s = rcx; // shift count
290 const int n = BitsPerWord;
291 Label L;
292 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
293 cmpl(s, n); // if (s < n)
294 jcc(Assembler::less, L); // else (s >= n)
295 movl(lo, hi); // x := x >> n
296 if (sign_extension) sarl(hi, 31);
297 else xorl(hi, hi);
298 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
299 bind(L); // s (mod n) < n
300 shrdl(lo, hi); // x := x >> s
301 if (sign_extension) sarl(hi);
302 else shrl(hi);
303 }
304
305 void MacroAssembler::movoop(Register dst, jobject obj) {
306 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
307 }
308
309 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
310 assert(rscratch == noreg, "redundant");
311 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
312 }
313
314 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
315 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
316 }
317
318 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
319 assert(rscratch == noreg, "redundant");
320 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
321 }
322
323 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
324 if (src.is_lval()) {
325 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
326 } else {
327 movl(dst, as_Address(src));
328 }
329 }
330
331 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
332 assert(rscratch == noreg, "redundant");
333 movl(as_Address(dst, noreg), src);
334 }
335
336 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
337 movl(dst, as_Address(src, noreg));
338 }
339
340 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
341 assert(rscratch == noreg, "redundant");
342 movl(dst, src);
343 }
344
345 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
346 assert(rscratch == noreg, "redundant");
347 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
348 }
349
350 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
351 assert(rscratch == noreg, "redundant");
352 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
353 }
354
355 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
356 assert(rscratch == noreg, "redundant");
357 if (src.is_lval()) {
358 push_literal32((int32_t)src.target(), src.rspec());
359 } else {
360 pushl(as_Address(src));
361 }
362 }
363
364 static void pass_arg0(MacroAssembler* masm, Register arg) {
365 masm->push(arg);
366 }
367
368 static void pass_arg1(MacroAssembler* masm, Register arg) {
369 masm->push(arg);
370 }
371
372 static void pass_arg2(MacroAssembler* masm, Register arg) {
373 masm->push(arg);
374 }
375
376 static void pass_arg3(MacroAssembler* masm, Register arg) {
377 masm->push(arg);
378 }
379
380 #ifndef PRODUCT
381 extern "C" void findpc(intptr_t x);
382 #endif
383
384 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
385 // In order to get locks to work, we need to fake a in_VM state
386 JavaThread* thread = JavaThread::current();
387 JavaThreadState saved_state = thread->thread_state();
388 thread->set_thread_state(_thread_in_vm);
389 if (ShowMessageBoxOnError) {
390 JavaThread* thread = JavaThread::current();
391 JavaThreadState saved_state = thread->thread_state();
392 thread->set_thread_state(_thread_in_vm);
393 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
394 ttyLocker ttyl;
395 BytecodeCounter::print();
396 }
397 // To see where a verify_oop failed, get $ebx+40/X for this frame.
398 // This is the value of eip which points to where verify_oop will return.
399 if (os::message_box(msg, "Execution stopped, print registers?")) {
400 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
401 BREAKPOINT;
402 }
403 }
404 fatal("DEBUG MESSAGE: %s", msg);
405 }
406
407 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
408 ttyLocker ttyl;
409 DebuggingContext debugging{};
410 tty->print_cr("eip = 0x%08x", eip);
411 #ifndef PRODUCT
412 if ((WizardMode || Verbose) && PrintMiscellaneous) {
413 tty->cr();
414 findpc(eip);
415 tty->cr();
416 }
417 #endif
418 #define PRINT_REG(rax) \
419 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
420 PRINT_REG(rax);
421 PRINT_REG(rbx);
422 PRINT_REG(rcx);
423 PRINT_REG(rdx);
424 PRINT_REG(rdi);
425 PRINT_REG(rsi);
426 PRINT_REG(rbp);
427 PRINT_REG(rsp);
428 #undef PRINT_REG
429 // Print some words near top of staack.
430 int* dump_sp = (int*) rsp;
431 for (int col1 = 0; col1 < 8; col1++) {
432 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
433 os::print_location(tty, *dump_sp++);
434 }
435 for (int row = 0; row < 16; row++) {
436 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
437 for (int col = 0; col < 8; col++) {
438 tty->print(" 0x%08x", *dump_sp++);
439 }
440 tty->cr();
441 }
442 // Print some instructions around pc:
443 Disassembler::decode((address)eip-64, (address)eip);
444 tty->print_cr("--------");
445 Disassembler::decode((address)eip, (address)eip+32);
446 }
447
448 void MacroAssembler::stop(const char* msg) {
449 // push address of message
450 ExternalAddress message((address)msg);
451 pushptr(message.addr(), noreg);
452 { Label L; call(L, relocInfo::none); bind(L); } // push eip
453 pusha(); // push registers
454 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
455 hlt();
456 }
457
458 void MacroAssembler::warn(const char* msg) {
459 push_CPU_state();
460
461 // push address of message
462 ExternalAddress message((address)msg);
463 pushptr(message.addr(), noreg);
464
465 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
466 addl(rsp, wordSize); // discard argument
467 pop_CPU_state();
468 }
469
470 void MacroAssembler::print_state() {
471 { Label L; call(L, relocInfo::none); bind(L); } // push eip
472 pusha(); // push registers
473
474 push_CPU_state();
475 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
476 pop_CPU_state();
477
478 popa();
479 addl(rsp, wordSize);
480 }
481
482 #else // _LP64
483
484 // 64 bit versions
485
486 Address MacroAssembler::as_Address(AddressLiteral adr) {
487 // amd64 always does this as a pc-rel
488 // we can be absolute or disp based on the instruction type
489 // jmp/call are displacements others are absolute
490 assert(!adr.is_lval(), "must be rval");
491 assert(reachable(adr), "must be");
492 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
493
494 }
495
496 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
497 AddressLiteral base = adr.base();
498 lea(rscratch, base);
499 Address index = adr.index();
500 assert(index._disp == 0, "must not have disp"); // maybe it can?
501 Address array(rscratch, index._index, index._scale, index._disp);
502 return array;
503 }
504
505 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
506 Label L, E;
507
508 #ifdef _WIN64
509 // Windows always allocates space for it's register args
510 assert(num_args <= 4, "only register arguments supported");
511 subq(rsp, frame::arg_reg_save_area_bytes);
512 #endif
513
514 // Align stack if necessary
515 testl(rsp, 15);
516 jcc(Assembler::zero, L);
517
518 subq(rsp, 8);
519 call(RuntimeAddress(entry_point));
520 addq(rsp, 8);
521 jmp(E);
522
523 bind(L);
524 call(RuntimeAddress(entry_point));
525
526 bind(E);
527
528 #ifdef _WIN64
529 // restore stack pointer
530 addq(rsp, frame::arg_reg_save_area_bytes);
531 #endif
532 }
533
534 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
535 assert(!src2.is_lval(), "should use cmpptr");
536 assert(rscratch != noreg || always_reachable(src2), "missing");
537
538 if (reachable(src2)) {
539 cmpq(src1, as_Address(src2));
540 } else {
541 lea(rscratch, src2);
542 Assembler::cmpq(src1, Address(rscratch, 0));
543 }
544 }
545
546 int MacroAssembler::corrected_idivq(Register reg) {
547 // Full implementation of Java ldiv and lrem; checks for special
548 // case as described in JVM spec., p.243 & p.271. The function
549 // returns the (pc) offset of the idivl instruction - may be needed
550 // for implicit exceptions.
551 //
552 // normal case special case
553 //
554 // input : rax: dividend min_long
555 // reg: divisor (may not be eax/edx) -1
556 //
557 // output: rax: quotient (= rax idiv reg) min_long
558 // rdx: remainder (= rax irem reg) 0
559 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
560 static const int64_t min_long = 0x8000000000000000;
561 Label normal_case, special_case;
562
563 // check for special case
564 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
565 jcc(Assembler::notEqual, normal_case);
566 xorl(rdx, rdx); // prepare rdx for possible special case (where
567 // remainder = 0)
568 cmpq(reg, -1);
569 jcc(Assembler::equal, special_case);
570
571 // handle normal case
572 bind(normal_case);
573 cdqq();
574 int idivq_offset = offset();
575 idivq(reg);
576
577 // normal and special case exit
578 bind(special_case);
579
580 return idivq_offset;
581 }
582
583 void MacroAssembler::decrementq(Register reg, int value) {
584 if (value == min_jint) { subq(reg, value); return; }
585 if (value < 0) { incrementq(reg, -value); return; }
586 if (value == 0) { ; return; }
587 if (value == 1 && UseIncDec) { decq(reg) ; return; }
588 /* else */ { subq(reg, value) ; return; }
589 }
590
591 void MacroAssembler::decrementq(Address dst, int value) {
592 if (value == min_jint) { subq(dst, value); return; }
593 if (value < 0) { incrementq(dst, -value); return; }
594 if (value == 0) { ; return; }
595 if (value == 1 && UseIncDec) { decq(dst) ; return; }
596 /* else */ { subq(dst, value) ; return; }
597 }
598
599 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
600 assert(rscratch != noreg || always_reachable(dst), "missing");
601
602 if (reachable(dst)) {
603 incrementq(as_Address(dst));
604 } else {
605 lea(rscratch, dst);
606 incrementq(Address(rscratch, 0));
607 }
608 }
609
610 void MacroAssembler::incrementq(Register reg, int value) {
611 if (value == min_jint) { addq(reg, value); return; }
612 if (value < 0) { decrementq(reg, -value); return; }
613 if (value == 0) { ; return; }
614 if (value == 1 && UseIncDec) { incq(reg) ; return; }
615 /* else */ { addq(reg, value) ; return; }
616 }
617
618 void MacroAssembler::incrementq(Address dst, int value) {
619 if (value == min_jint) { addq(dst, value); return; }
620 if (value < 0) { decrementq(dst, -value); return; }
621 if (value == 0) { ; return; }
622 if (value == 1 && UseIncDec) { incq(dst) ; return; }
623 /* else */ { addq(dst, value) ; return; }
624 }
625
626 // 32bit can do a case table jump in one instruction but we no longer allow the base
627 // to be installed in the Address class
628 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
629 lea(rscratch, entry.base());
630 Address dispatch = entry.index();
631 assert(dispatch._base == noreg, "must be");
632 dispatch._base = rscratch;
633 jmp(dispatch);
634 }
635
636 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
637 ShouldNotReachHere(); // 64bit doesn't use two regs
638 cmpq(x_lo, y_lo);
639 }
640
641 void MacroAssembler::lea(Register dst, AddressLiteral src) {
642 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
643 }
644
645 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
646 lea(rscratch, adr);
647 movptr(dst, rscratch);
648 }
649
650 void MacroAssembler::leave() {
651 // %%% is this really better? Why not on 32bit too?
652 emit_int8((unsigned char)0xC9); // LEAVE
653 }
654
655 void MacroAssembler::lneg(Register hi, Register lo) {
656 ShouldNotReachHere(); // 64bit doesn't use two regs
657 negq(lo);
658 }
659
660 void MacroAssembler::movoop(Register dst, jobject obj) {
661 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
662 }
663
664 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
665 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
666 movq(dst, rscratch);
667 }
668
669 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
670 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
671 }
672
673 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
674 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
675 movq(dst, rscratch);
676 }
677
678 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
679 if (src.is_lval()) {
680 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
681 } else {
682 if (reachable(src)) {
683 movq(dst, as_Address(src));
684 } else {
685 lea(dst, src);
686 movq(dst, Address(dst, 0));
687 }
688 }
689 }
690
691 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
692 movq(as_Address(dst, rscratch), src);
693 }
694
695 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
696 movq(dst, as_Address(src, dst /*rscratch*/));
697 }
698
699 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
700 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
701 if (is_simm32(src)) {
702 movptr(dst, checked_cast<int32_t>(src));
703 } else {
704 mov64(rscratch, src);
705 movq(dst, rscratch);
706 }
707 }
708
709 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
710 movoop(rscratch, obj);
711 push(rscratch);
712 }
713
714 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
715 mov_metadata(rscratch, obj);
716 push(rscratch);
717 }
718
719 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
720 lea(rscratch, src);
721 if (src.is_lval()) {
722 push(rscratch);
723 } else {
724 pushq(Address(rscratch, 0));
725 }
726 }
727
728 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
729 reset_last_Java_frame(r15_thread, clear_fp);
730 }
731
732 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
733 Register last_java_fp,
734 address last_java_pc,
735 Register rscratch) {
736 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, last_java_pc, rscratch);
737 }
738
739 static void pass_arg0(MacroAssembler* masm, Register arg) {
740 if (c_rarg0 != arg ) {
741 masm->mov(c_rarg0, arg);
742 }
743 }
744
745 static void pass_arg1(MacroAssembler* masm, Register arg) {
746 if (c_rarg1 != arg ) {
747 masm->mov(c_rarg1, arg);
748 }
749 }
750
751 static void pass_arg2(MacroAssembler* masm, Register arg) {
752 if (c_rarg2 != arg ) {
753 masm->mov(c_rarg2, arg);
754 }
755 }
756
757 static void pass_arg3(MacroAssembler* masm, Register arg) {
758 if (c_rarg3 != arg ) {
759 masm->mov(c_rarg3, arg);
760 }
761 }
762
763 void MacroAssembler::stop(const char* msg) {
764 if (ShowMessageBoxOnError) {
765 address rip = pc();
766 pusha(); // get regs on stack
767 lea(c_rarg1, InternalAddress(rip));
768 movq(c_rarg2, rsp); // pass pointer to regs array
769 }
770 lea(c_rarg0, ExternalAddress((address) msg));
771 andq(rsp, -16); // align stack as required by ABI
772 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
773 hlt();
774 }
775
776 void MacroAssembler::warn(const char* msg) {
777 push(rbp);
778 movq(rbp, rsp);
779 andq(rsp, -16); // align stack as required by push_CPU_state and call
780 push_CPU_state(); // keeps alignment at 16 bytes
781
782 lea(c_rarg0, ExternalAddress((address) msg));
783 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
784
785 pop_CPU_state();
786 mov(rsp, rbp);
787 pop(rbp);
788 }
789
790 void MacroAssembler::print_state() {
791 address rip = pc();
792 pusha(); // get regs on stack
793 push(rbp);
794 movq(rbp, rsp);
795 andq(rsp, -16); // align stack as required by push_CPU_state and call
796 push_CPU_state(); // keeps alignment at 16 bytes
797
798 lea(c_rarg0, InternalAddress(rip));
799 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
800 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
801
802 pop_CPU_state();
803 mov(rsp, rbp);
804 pop(rbp);
805 popa();
806 }
807
808 #ifndef PRODUCT
809 extern "C" void findpc(intptr_t x);
810 #endif
811
812 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
813 // In order to get locks to work, we need to fake a in_VM state
814 if (ShowMessageBoxOnError) {
815 JavaThread* thread = JavaThread::current();
816 JavaThreadState saved_state = thread->thread_state();
817 thread->set_thread_state(_thread_in_vm);
818 #ifndef PRODUCT
819 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
820 ttyLocker ttyl;
821 BytecodeCounter::print();
822 }
823 #endif
824 // To see where a verify_oop failed, get $ebx+40/X for this frame.
825 // XXX correct this offset for amd64
826 // This is the value of eip which points to where verify_oop will return.
827 if (os::message_box(msg, "Execution stopped, print registers?")) {
828 print_state64(pc, regs);
829 BREAKPOINT;
830 }
831 }
832 fatal("DEBUG MESSAGE: %s", msg);
833 }
834
835 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
836 ttyLocker ttyl;
837 DebuggingContext debugging{};
838 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
839 #ifndef PRODUCT
840 tty->cr();
841 findpc(pc);
842 tty->cr();
843 #endif
844 #define PRINT_REG(rax, value) \
845 { tty->print("%s = ", #rax); os::print_location(tty, value); }
846 PRINT_REG(rax, regs[15]);
847 PRINT_REG(rbx, regs[12]);
848 PRINT_REG(rcx, regs[14]);
849 PRINT_REG(rdx, regs[13]);
850 PRINT_REG(rdi, regs[8]);
851 PRINT_REG(rsi, regs[9]);
852 PRINT_REG(rbp, regs[10]);
853 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
854 PRINT_REG(rsp, (intptr_t)(®s[16]));
855 PRINT_REG(r8 , regs[7]);
856 PRINT_REG(r9 , regs[6]);
857 PRINT_REG(r10, regs[5]);
858 PRINT_REG(r11, regs[4]);
859 PRINT_REG(r12, regs[3]);
860 PRINT_REG(r13, regs[2]);
861 PRINT_REG(r14, regs[1]);
862 PRINT_REG(r15, regs[0]);
863 #undef PRINT_REG
864 // Print some words near the top of the stack.
865 int64_t* rsp = ®s[16];
866 int64_t* dump_sp = rsp;
867 for (int col1 = 0; col1 < 8; col1++) {
868 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
869 os::print_location(tty, *dump_sp++);
870 }
871 for (int row = 0; row < 25; row++) {
872 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
873 for (int col = 0; col < 4; col++) {
874 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
875 }
876 tty->cr();
877 }
878 // Print some instructions around pc:
879 Disassembler::decode((address)pc-64, (address)pc);
880 tty->print_cr("--------");
881 Disassembler::decode((address)pc, (address)pc+32);
882 }
883
884 // The java_calling_convention describes stack locations as ideal slots on
885 // a frame with no abi restrictions. Since we must observe abi restrictions
886 // (like the placement of the register window) the slots must be biased by
887 // the following value.
888 static int reg2offset_in(VMReg r) {
889 // Account for saved rbp and return address
890 // This should really be in_preserve_stack_slots
891 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
892 }
893
894 static int reg2offset_out(VMReg r) {
895 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
896 }
897
898 // A long move
899 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
900
901 // The calling conventions assures us that each VMregpair is either
902 // all really one physical register or adjacent stack slots.
903
904 if (src.is_single_phys_reg() ) {
905 if (dst.is_single_phys_reg()) {
906 if (dst.first() != src.first()) {
907 mov(dst.first()->as_Register(), src.first()->as_Register());
908 }
909 } else {
910 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
911 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
912 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
913 }
914 } else if (dst.is_single_phys_reg()) {
915 assert(src.is_single_reg(), "not a stack pair");
916 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
917 } else {
918 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
919 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
920 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
921 }
922 }
923
924 // A double move
925 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
926
927 // The calling conventions assures us that each VMregpair is either
928 // all really one physical register or adjacent stack slots.
929
930 if (src.is_single_phys_reg() ) {
931 if (dst.is_single_phys_reg()) {
932 // In theory these overlap but the ordering is such that this is likely a nop
933 if ( src.first() != dst.first()) {
934 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
935 }
936 } else {
937 assert(dst.is_single_reg(), "not a stack pair");
938 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
939 }
940 } else if (dst.is_single_phys_reg()) {
941 assert(src.is_single_reg(), "not a stack pair");
942 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
943 } else {
944 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
945 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
946 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
947 }
948 }
949
950
951 // A float arg may have to do float reg int reg conversion
952 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
953 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
954
955 // The calling conventions assures us that each VMregpair is either
956 // all really one physical register or adjacent stack slots.
957
958 if (src.first()->is_stack()) {
959 if (dst.first()->is_stack()) {
960 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
961 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
962 } else {
963 // stack to reg
964 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
965 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
966 }
967 } else if (dst.first()->is_stack()) {
968 // reg to stack
969 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
970 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
971 } else {
972 // reg to reg
973 // In theory these overlap but the ordering is such that this is likely a nop
974 if ( src.first() != dst.first()) {
975 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
976 }
977 }
978 }
979
980 // On 64 bit we will store integer like items to the stack as
981 // 64 bits items (x86_32/64 abi) even though java would only store
982 // 32bits for a parameter. On 32bit it will simply be 32 bits
983 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
984 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
985 if (src.first()->is_stack()) {
986 if (dst.first()->is_stack()) {
987 // stack to stack
988 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
989 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
990 } else {
991 // stack to reg
992 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
993 }
994 } else if (dst.first()->is_stack()) {
995 // reg to stack
996 // Do we really have to sign extend???
997 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
998 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
999 } else {
1000 // Do we really have to sign extend???
1001 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1002 if (dst.first() != src.first()) {
1003 movq(dst.first()->as_Register(), src.first()->as_Register());
1004 }
1005 }
1006 }
1007
1008 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1009 if (src.first()->is_stack()) {
1010 if (dst.first()->is_stack()) {
1011 // stack to stack
1012 movq(rax, Address(rbp, reg2offset_in(src.first())));
1013 movq(Address(rsp, reg2offset_out(dst.first())), rax);
1014 } else {
1015 // stack to reg
1016 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1017 }
1018 } else if (dst.first()->is_stack()) {
1019 // reg to stack
1020 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1021 } else {
1022 if (dst.first() != src.first()) {
1023 movq(dst.first()->as_Register(), src.first()->as_Register());
1024 }
1025 }
1026 }
1027
1028 // An oop arg. Must pass a handle not the oop itself
1029 void MacroAssembler::object_move(OopMap* map,
1030 int oop_handle_offset,
1031 int framesize_in_slots,
1032 VMRegPair src,
1033 VMRegPair dst,
1034 bool is_receiver,
1035 int* receiver_offset) {
1036
1037 // must pass a handle. First figure out the location we use as a handle
1038
1039 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1040
1041 // See if oop is null if it is we need no handle
1042
1043 if (src.first()->is_stack()) {
1044
1045 // Oop is already on the stack as an argument
1046 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1047 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1048 if (is_receiver) {
1049 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1050 }
1051
1052 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
1053 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1054 // conditionally move a null
1055 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1056 } else {
1057
1058 // Oop is in a register we must store it to the space we reserve
1059 // on the stack for oop_handles and pass a handle if oop is non-null
1060
1061 const Register rOop = src.first()->as_Register();
1062 int oop_slot;
1063 if (rOop == j_rarg0)
1064 oop_slot = 0;
1065 else if (rOop == j_rarg1)
1066 oop_slot = 1;
1067 else if (rOop == j_rarg2)
1068 oop_slot = 2;
1069 else if (rOop == j_rarg3)
1070 oop_slot = 3;
1071 else if (rOop == j_rarg4)
1072 oop_slot = 4;
1073 else {
1074 assert(rOop == j_rarg5, "wrong register");
1075 oop_slot = 5;
1076 }
1077
1078 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1079 int offset = oop_slot*VMRegImpl::stack_slot_size;
1080
1081 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1082 // Store oop in handle area, may be null
1083 movptr(Address(rsp, offset), rOop);
1084 if (is_receiver) {
1085 *receiver_offset = offset;
1086 }
1087
1088 cmpptr(rOop, NULL_WORD);
1089 lea(rHandle, Address(rsp, offset));
1090 // conditionally move a null from the handle area where it was just stored
1091 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1092 }
1093
1094 // If arg is on the stack then place it otherwise it is already in correct reg.
1095 if (dst.first()->is_stack()) {
1096 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1097 }
1098 }
1099
1100 #endif // _LP64
1101
1102 // Now versions that are common to 32/64 bit
1103
1104 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1105 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1106 }
1107
1108 void MacroAssembler::addptr(Register dst, Register src) {
1109 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1110 }
1111
1112 void MacroAssembler::addptr(Address dst, Register src) {
1113 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1114 }
1115
1116 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1117 assert(rscratch != noreg || always_reachable(src), "missing");
1118
1119 if (reachable(src)) {
1120 Assembler::addsd(dst, as_Address(src));
1121 } else {
1122 lea(rscratch, src);
1123 Assembler::addsd(dst, Address(rscratch, 0));
1124 }
1125 }
1126
1127 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1128 assert(rscratch != noreg || always_reachable(src), "missing");
1129
1130 if (reachable(src)) {
1131 addss(dst, as_Address(src));
1132 } else {
1133 lea(rscratch, src);
1134 addss(dst, Address(rscratch, 0));
1135 }
1136 }
1137
1138 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1139 assert(rscratch != noreg || always_reachable(src), "missing");
1140
1141 if (reachable(src)) {
1142 Assembler::addpd(dst, as_Address(src));
1143 } else {
1144 lea(rscratch, src);
1145 Assembler::addpd(dst, Address(rscratch, 0));
1146 }
1147 }
1148
1149 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
1150 // Stub code is generated once and never copied.
1151 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1152 void MacroAssembler::align64() {
1153 align(64, (uint)(uintptr_t)pc());
1154 }
1155
1156 void MacroAssembler::align32() {
1157 align(32, (uint)(uintptr_t)pc());
1158 }
1159
1160 void MacroAssembler::align(uint modulus) {
1161 // 8273459: Ensure alignment is possible with current segment alignment
1162 assert(modulus <= (uintx)CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1163 align(modulus, offset());
1164 }
1165
1166 void MacroAssembler::align(uint modulus, uint target) {
1167 if (target % modulus != 0) {
1168 nop(modulus - (target % modulus));
1169 }
1170 }
1171
1172 void MacroAssembler::push_f(XMMRegister r) {
1173 subptr(rsp, wordSize);
1174 movflt(Address(rsp, 0), r);
1175 }
1176
1177 void MacroAssembler::pop_f(XMMRegister r) {
1178 movflt(r, Address(rsp, 0));
1179 addptr(rsp, wordSize);
1180 }
1181
1182 void MacroAssembler::push_d(XMMRegister r) {
1183 subptr(rsp, 2 * wordSize);
1184 movdbl(Address(rsp, 0), r);
1185 }
1186
1187 void MacroAssembler::pop_d(XMMRegister r) {
1188 movdbl(r, Address(rsp, 0));
1189 addptr(rsp, 2 * Interpreter::stackElementSize);
1190 }
1191
1192 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1193 // Used in sign-masking with aligned address.
1194 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1195 assert(rscratch != noreg || always_reachable(src), "missing");
1196
1197 if (reachable(src)) {
1198 Assembler::andpd(dst, as_Address(src));
1199 } else {
1200 lea(rscratch, src);
1201 Assembler::andpd(dst, Address(rscratch, 0));
1202 }
1203 }
1204
1205 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
1206 // Used in sign-masking with aligned address.
1207 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1208 assert(rscratch != noreg || always_reachable(src), "missing");
1209
1210 if (reachable(src)) {
1211 Assembler::andps(dst, as_Address(src));
1212 } else {
1213 lea(rscratch, src);
1214 Assembler::andps(dst, Address(rscratch, 0));
1215 }
1216 }
1217
1218 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1219 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1220 }
1221
1222 #ifdef _LP64
1223 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
1224 assert(rscratch != noreg || always_reachable(src), "missing");
1225
1226 if (reachable(src)) {
1227 andq(dst, as_Address(src));
1228 } else {
1229 lea(rscratch, src);
1230 andq(dst, Address(rscratch, 0));
1231 }
1232 }
1233 #endif
1234
1235 void MacroAssembler::atomic_incl(Address counter_addr) {
1236 lock();
1237 incrementl(counter_addr);
1238 }
1239
1240 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
1241 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1242
1243 if (reachable(counter_addr)) {
1244 atomic_incl(as_Address(counter_addr));
1245 } else {
1246 lea(rscratch, counter_addr);
1247 atomic_incl(Address(rscratch, 0));
1248 }
1249 }
1250
1251 #ifdef _LP64
1252 void MacroAssembler::atomic_incq(Address counter_addr) {
1253 lock();
1254 incrementq(counter_addr);
1255 }
1256
1257 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
1258 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1259
1260 if (reachable(counter_addr)) {
1261 atomic_incq(as_Address(counter_addr));
1262 } else {
1263 lea(rscratch, counter_addr);
1264 atomic_incq(Address(rscratch, 0));
1265 }
1266 }
1267 #endif
1268
1269 // Writes to stack successive pages until offset reached to check for
1270 // stack overflow + shadow pages. This clobbers tmp.
1271 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1272 movptr(tmp, rsp);
1273 // Bang stack for total size given plus shadow page size.
1274 // Bang one page at a time because large size can bang beyond yellow and
1275 // red zones.
1276 Label loop;
1277 bind(loop);
1278 movl(Address(tmp, (-(int)os::vm_page_size())), size );
1279 subptr(tmp, (int)os::vm_page_size());
1280 subl(size, (int)os::vm_page_size());
1281 jcc(Assembler::greater, loop);
1282
1283 // Bang down shadow pages too.
1284 // At this point, (tmp-0) is the last address touched, so don't
1285 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1286 // was post-decremented.) Skip this address by starting at i=1, and
1287 // touch a few more pages below. N.B. It is important to touch all
1288 // the way down including all pages in the shadow zone.
1289 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
1290 // this could be any sized move but this is can be a debugging crumb
1291 // so the bigger the better.
1292 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
1293 }
1294 }
1295
1296 void MacroAssembler::reserved_stack_check() {
1297 // testing if reserved zone needs to be enabled
1298 Label no_reserved_zone_enabling;
1299 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1300 NOT_LP64(get_thread(rsi);)
1301
1302 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1303 jcc(Assembler::below, no_reserved_zone_enabling);
1304
1305 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1306 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
1307 should_not_reach_here();
1308
1309 bind(no_reserved_zone_enabling);
1310 }
1311
1312 void MacroAssembler::c2bool(Register x) {
1313 // implements x == 0 ? 0 : 1
1314 // note: must only look at least-significant byte of x
1315 // since C-style booleans are stored in one byte
1316 // only! (was bug)
1317 andl(x, 0xFF);
1318 setb(Assembler::notZero, x);
1319 }
1320
1321 // Wouldn't need if AddressLiteral version had new name
1322 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1323 Assembler::call(L, rtype);
1324 }
1325
1326 void MacroAssembler::call(Register entry) {
1327 Assembler::call(entry);
1328 }
1329
1330 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
1331 assert(rscratch != noreg || always_reachable(entry), "missing");
1332
1333 if (reachable(entry)) {
1334 Assembler::call_literal(entry.target(), entry.rspec());
1335 } else {
1336 lea(rscratch, entry);
1337 Assembler::call(rscratch);
1338 }
1339 }
1340
1341 void MacroAssembler::ic_call(address entry, jint method_index) {
1342 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1343 #ifdef _LP64
1344 // Needs full 64-bit immediate for later patching.
1345 mov64(rax, (int64_t)Universe::non_oop_word());
1346 #else
1347 movptr(rax, (intptr_t)Universe::non_oop_word());
1348 #endif
1349 call(AddressLiteral(entry, rh));
1350 }
1351
1352 int MacroAssembler::ic_check_size() {
1353 return
1354 LP64_ONLY(UseCompactObjectHeaders ? 17 : 14) NOT_LP64(12);
1355 }
1356
1357 int MacroAssembler::ic_check(int end_alignment) {
1358 Register receiver = LP64_ONLY(j_rarg0) NOT_LP64(rcx);
1359 Register data = rax;
1360 Register temp = LP64_ONLY(rscratch1) NOT_LP64(rbx);
1361
1362 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1363 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1364 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1365 // before the inline cache check here, and not after
1366 align(end_alignment, offset() + ic_check_size());
1367
1368 int uep_offset = offset();
1369
1370 #ifdef _LP64
1371 if (UseCompactObjectHeaders) {
1372 load_narrow_klass_compact(temp, receiver);
1373 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1374 } else
1375 #endif
1376 if (UseCompressedClassPointers) {
1377 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1378 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1379 } else {
1380 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1381 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
1382 }
1383
1384 // if inline cache check fails, then jump to runtime routine
1385 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1386 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
1387
1388 return uep_offset;
1389 }
1390
1391 void MacroAssembler::emit_static_call_stub() {
1392 // Static stub relocation also tags the Method* in the code-stream.
1393 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1394 // This is recognized as unresolved by relocs/nativeinst/ic code.
1395 jump(RuntimeAddress(pc()));
1396 }
1397
1398 // Implementation of call_VM versions
1399
1400 void MacroAssembler::call_VM(Register oop_result,
1401 address entry_point,
1402 bool check_exceptions) {
1403 Label C, E;
1404 call(C, relocInfo::none);
1405 jmp(E);
1406
1407 bind(C);
1408 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1409 ret(0);
1410
1411 bind(E);
1412 }
1413
1414 void MacroAssembler::call_VM(Register oop_result,
1415 address entry_point,
1416 Register arg_1,
1417 bool check_exceptions) {
1418 Label C, E;
1419 call(C, relocInfo::none);
1420 jmp(E);
1421
1422 bind(C);
1423 pass_arg1(this, arg_1);
1424 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1425 ret(0);
1426
1427 bind(E);
1428 }
1429
1430 void MacroAssembler::call_VM(Register oop_result,
1431 address entry_point,
1432 Register arg_1,
1433 Register arg_2,
1434 bool check_exceptions) {
1435 Label C, E;
1436 call(C, relocInfo::none);
1437 jmp(E);
1438
1439 bind(C);
1440
1441 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1442
1443 pass_arg2(this, arg_2);
1444 pass_arg1(this, arg_1);
1445 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1446 ret(0);
1447
1448 bind(E);
1449 }
1450
1451 void MacroAssembler::call_VM(Register oop_result,
1452 address entry_point,
1453 Register arg_1,
1454 Register arg_2,
1455 Register arg_3,
1456 bool check_exceptions) {
1457 Label C, E;
1458 call(C, relocInfo::none);
1459 jmp(E);
1460
1461 bind(C);
1462
1463 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1464 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1465 pass_arg3(this, arg_3);
1466 pass_arg2(this, arg_2);
1467 pass_arg1(this, arg_1);
1468 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1469 ret(0);
1470
1471 bind(E);
1472 }
1473
1474 void MacroAssembler::call_VM(Register oop_result,
1475 Register last_java_sp,
1476 address entry_point,
1477 int number_of_arguments,
1478 bool check_exceptions) {
1479 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1480 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1481 }
1482
1483 void MacroAssembler::call_VM(Register oop_result,
1484 Register last_java_sp,
1485 address entry_point,
1486 Register arg_1,
1487 bool check_exceptions) {
1488 pass_arg1(this, arg_1);
1489 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1490 }
1491
1492 void MacroAssembler::call_VM(Register oop_result,
1493 Register last_java_sp,
1494 address entry_point,
1495 Register arg_1,
1496 Register arg_2,
1497 bool check_exceptions) {
1498
1499 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1500 pass_arg2(this, arg_2);
1501 pass_arg1(this, arg_1);
1502 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1503 }
1504
1505 void MacroAssembler::call_VM(Register oop_result,
1506 Register last_java_sp,
1507 address entry_point,
1508 Register arg_1,
1509 Register arg_2,
1510 Register arg_3,
1511 bool check_exceptions) {
1512 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1513 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1514 pass_arg3(this, arg_3);
1515 pass_arg2(this, arg_2);
1516 pass_arg1(this, arg_1);
1517 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1518 }
1519
1520 void MacroAssembler::super_call_VM(Register oop_result,
1521 Register last_java_sp,
1522 address entry_point,
1523 int number_of_arguments,
1524 bool check_exceptions) {
1525 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1526 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1527 }
1528
1529 void MacroAssembler::super_call_VM(Register oop_result,
1530 Register last_java_sp,
1531 address entry_point,
1532 Register arg_1,
1533 bool check_exceptions) {
1534 pass_arg1(this, arg_1);
1535 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1536 }
1537
1538 void MacroAssembler::super_call_VM(Register oop_result,
1539 Register last_java_sp,
1540 address entry_point,
1541 Register arg_1,
1542 Register arg_2,
1543 bool check_exceptions) {
1544
1545 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1546 pass_arg2(this, arg_2);
1547 pass_arg1(this, arg_1);
1548 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1549 }
1550
1551 void MacroAssembler::super_call_VM(Register oop_result,
1552 Register last_java_sp,
1553 address entry_point,
1554 Register arg_1,
1555 Register arg_2,
1556 Register arg_3,
1557 bool check_exceptions) {
1558 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1559 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1560 pass_arg3(this, arg_3);
1561 pass_arg2(this, arg_2);
1562 pass_arg1(this, arg_1);
1563 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1564 }
1565
1566 void MacroAssembler::call_VM_base(Register oop_result,
1567 Register java_thread,
1568 Register last_java_sp,
1569 address entry_point,
1570 int number_of_arguments,
1571 bool check_exceptions) {
1572 // determine java_thread register
1573 if (!java_thread->is_valid()) {
1574 #ifdef _LP64
1575 java_thread = r15_thread;
1576 #else
1577 java_thread = rdi;
1578 get_thread(java_thread);
1579 #endif // LP64
1580 }
1581 // determine last_java_sp register
1582 if (!last_java_sp->is_valid()) {
1583 last_java_sp = rsp;
1584 }
1585 // debugging support
1586 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1587 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1588 #ifdef ASSERT
1589 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1590 // r12 is the heapbase.
1591 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1592 #endif // ASSERT
1593
1594 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1595 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1596
1597 // push java thread (becomes first argument of C function)
1598
1599 NOT_LP64(push(java_thread); number_of_arguments++);
1600 LP64_ONLY(mov(c_rarg0, r15_thread));
1601
1602 // set last Java frame before call
1603 assert(last_java_sp != rbp, "can't use ebp/rbp");
1604
1605 // Only interpreter should have to set fp
1606 set_last_Java_frame(java_thread, last_java_sp, rbp, nullptr, rscratch1);
1607
1608 // do the call, remove parameters
1609 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1610
1611 // restore the thread (cannot use the pushed argument since arguments
1612 // may be overwritten by C code generated by an optimizing compiler);
1613 // however can use the register value directly if it is callee saved.
1614 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1615 // rdi & rsi (also r15) are callee saved -> nothing to do
1616 #ifdef ASSERT
1617 guarantee(java_thread != rax, "change this code");
1618 push(rax);
1619 { Label L;
1620 get_thread(rax);
1621 cmpptr(java_thread, rax);
1622 jcc(Assembler::equal, L);
1623 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1624 bind(L);
1625 }
1626 pop(rax);
1627 #endif
1628 } else {
1629 get_thread(java_thread);
1630 }
1631 // reset last Java frame
1632 // Only interpreter should have to clear fp
1633 reset_last_Java_frame(java_thread, true);
1634
1635 // C++ interp handles this in the interpreter
1636 check_and_handle_popframe(java_thread);
1637 check_and_handle_earlyret(java_thread);
1638
1639 if (check_exceptions) {
1640 // check for pending exceptions (java_thread is set upon return)
1641 cmpptr(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
1642 #ifndef _LP64
1643 jump_cc(Assembler::notEqual,
1644 RuntimeAddress(StubRoutines::forward_exception_entry()));
1645 #else
1646 // This used to conditionally jump to forward_exception however it is
1647 // possible if we relocate that the branch will not reach. So we must jump
1648 // around so we can always reach
1649
1650 Label ok;
1651 jcc(Assembler::equal, ok);
1652 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1653 bind(ok);
1654 #endif // LP64
1655 }
1656
1657 // get oop result if there is one and reset the value in the thread
1658 if (oop_result->is_valid()) {
1659 get_vm_result(oop_result, java_thread);
1660 }
1661 }
1662
1663 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1664
1665 // Calculate the value for last_Java_sp
1666 // somewhat subtle. call_VM does an intermediate call
1667 // which places a return address on the stack just under the
1668 // stack pointer as the user finished with it. This allows
1669 // use to retrieve last_Java_pc from last_Java_sp[-1].
1670 // On 32bit we then have to push additional args on the stack to accomplish
1671 // the actual requested call. On 64bit call_VM only can use register args
1672 // so the only extra space is the return address that call_VM created.
1673 // This hopefully explains the calculations here.
1674
1675 #ifdef _LP64
1676 // We've pushed one address, correct last_Java_sp
1677 lea(rax, Address(rsp, wordSize));
1678 #else
1679 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1680 #endif // LP64
1681
1682 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1683
1684 }
1685
1686 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1687 void MacroAssembler::call_VM_leaf0(address entry_point) {
1688 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1689 }
1690
1691 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1692 call_VM_leaf_base(entry_point, number_of_arguments);
1693 }
1694
1695 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1696 pass_arg0(this, arg_0);
1697 call_VM_leaf(entry_point, 1);
1698 }
1699
1700 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1701
1702 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1703 pass_arg1(this, arg_1);
1704 pass_arg0(this, arg_0);
1705 call_VM_leaf(entry_point, 2);
1706 }
1707
1708 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1709 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1710 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1711 pass_arg2(this, arg_2);
1712 pass_arg1(this, arg_1);
1713 pass_arg0(this, arg_0);
1714 call_VM_leaf(entry_point, 3);
1715 }
1716
1717 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1718 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1719 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1720 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1721 pass_arg3(this, arg_3);
1722 pass_arg2(this, arg_2);
1723 pass_arg1(this, arg_1);
1724 pass_arg0(this, arg_0);
1725 call_VM_leaf(entry_point, 3);
1726 }
1727
1728 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1729 pass_arg0(this, arg_0);
1730 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1731 }
1732
1733 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1734 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1735 pass_arg1(this, arg_1);
1736 pass_arg0(this, arg_0);
1737 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1738 }
1739
1740 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1741 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1742 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1743 pass_arg2(this, arg_2);
1744 pass_arg1(this, arg_1);
1745 pass_arg0(this, arg_0);
1746 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1747 }
1748
1749 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1750 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1751 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1752 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1753 pass_arg3(this, arg_3);
1754 pass_arg2(this, arg_2);
1755 pass_arg1(this, arg_1);
1756 pass_arg0(this, arg_0);
1757 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1758 }
1759
1760 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1761 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1762 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1763 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1764 }
1765
1766 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1767 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1768 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1769 }
1770
1771 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1772 }
1773
1774 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1775 }
1776
1777 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1778 assert(rscratch != noreg || always_reachable(src1), "missing");
1779
1780 if (reachable(src1)) {
1781 cmpl(as_Address(src1), imm);
1782 } else {
1783 lea(rscratch, src1);
1784 cmpl(Address(rscratch, 0), imm);
1785 }
1786 }
1787
1788 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1789 assert(!src2.is_lval(), "use cmpptr");
1790 assert(rscratch != noreg || always_reachable(src2), "missing");
1791
1792 if (reachable(src2)) {
1793 cmpl(src1, as_Address(src2));
1794 } else {
1795 lea(rscratch, src2);
1796 cmpl(src1, Address(rscratch, 0));
1797 }
1798 }
1799
1800 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1801 Assembler::cmpl(src1, imm);
1802 }
1803
1804 void MacroAssembler::cmp32(Register src1, Address src2) {
1805 Assembler::cmpl(src1, src2);
1806 }
1807
1808 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1809 ucomisd(opr1, opr2);
1810
1811 Label L;
1812 if (unordered_is_less) {
1813 movl(dst, -1);
1814 jcc(Assembler::parity, L);
1815 jcc(Assembler::below , L);
1816 movl(dst, 0);
1817 jcc(Assembler::equal , L);
1818 increment(dst);
1819 } else { // unordered is greater
1820 movl(dst, 1);
1821 jcc(Assembler::parity, L);
1822 jcc(Assembler::above , L);
1823 movl(dst, 0);
1824 jcc(Assembler::equal , L);
1825 decrementl(dst);
1826 }
1827 bind(L);
1828 }
1829
1830 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1831 ucomiss(opr1, opr2);
1832
1833 Label L;
1834 if (unordered_is_less) {
1835 movl(dst, -1);
1836 jcc(Assembler::parity, L);
1837 jcc(Assembler::below , L);
1838 movl(dst, 0);
1839 jcc(Assembler::equal , L);
1840 increment(dst);
1841 } else { // unordered is greater
1842 movl(dst, 1);
1843 jcc(Assembler::parity, L);
1844 jcc(Assembler::above , L);
1845 movl(dst, 0);
1846 jcc(Assembler::equal , L);
1847 decrementl(dst);
1848 }
1849 bind(L);
1850 }
1851
1852
1853 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1854 assert(rscratch != noreg || always_reachable(src1), "missing");
1855
1856 if (reachable(src1)) {
1857 cmpb(as_Address(src1), imm);
1858 } else {
1859 lea(rscratch, src1);
1860 cmpb(Address(rscratch, 0), imm);
1861 }
1862 }
1863
1864 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1865 #ifdef _LP64
1866 assert(rscratch != noreg || always_reachable(src2), "missing");
1867
1868 if (src2.is_lval()) {
1869 movptr(rscratch, src2);
1870 Assembler::cmpq(src1, rscratch);
1871 } else if (reachable(src2)) {
1872 cmpq(src1, as_Address(src2));
1873 } else {
1874 lea(rscratch, src2);
1875 Assembler::cmpq(src1, Address(rscratch, 0));
1876 }
1877 #else
1878 assert(rscratch == noreg, "not needed");
1879 if (src2.is_lval()) {
1880 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1881 } else {
1882 cmpl(src1, as_Address(src2));
1883 }
1884 #endif // _LP64
1885 }
1886
1887 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1888 assert(src2.is_lval(), "not a mem-mem compare");
1889 #ifdef _LP64
1890 // moves src2's literal address
1891 movptr(rscratch, src2);
1892 Assembler::cmpq(src1, rscratch);
1893 #else
1894 assert(rscratch == noreg, "not needed");
1895 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1896 #endif // _LP64
1897 }
1898
1899 void MacroAssembler::cmpoop(Register src1, Register src2) {
1900 cmpptr(src1, src2);
1901 }
1902
1903 void MacroAssembler::cmpoop(Register src1, Address src2) {
1904 cmpptr(src1, src2);
1905 }
1906
1907 #ifdef _LP64
1908 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1909 movoop(rscratch, src2);
1910 cmpptr(src1, rscratch);
1911 }
1912 #endif
1913
1914 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1915 assert(rscratch != noreg || always_reachable(adr), "missing");
1916
1917 if (reachable(adr)) {
1918 lock();
1919 cmpxchgptr(reg, as_Address(adr));
1920 } else {
1921 lea(rscratch, adr);
1922 lock();
1923 cmpxchgptr(reg, Address(rscratch, 0));
1924 }
1925 }
1926
1927 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1928 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1929 }
1930
1931 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1932 assert(rscratch != noreg || always_reachable(src), "missing");
1933
1934 if (reachable(src)) {
1935 Assembler::comisd(dst, as_Address(src));
1936 } else {
1937 lea(rscratch, src);
1938 Assembler::comisd(dst, Address(rscratch, 0));
1939 }
1940 }
1941
1942 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1943 assert(rscratch != noreg || always_reachable(src), "missing");
1944
1945 if (reachable(src)) {
1946 Assembler::comiss(dst, as_Address(src));
1947 } else {
1948 lea(rscratch, src);
1949 Assembler::comiss(dst, Address(rscratch, 0));
1950 }
1951 }
1952
1953
1954 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1955 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1956
1957 Condition negated_cond = negate_condition(cond);
1958 Label L;
1959 jcc(negated_cond, L);
1960 pushf(); // Preserve flags
1961 atomic_incl(counter_addr, rscratch);
1962 popf();
1963 bind(L);
1964 }
1965
1966 int MacroAssembler::corrected_idivl(Register reg) {
1967 // Full implementation of Java idiv and irem; checks for
1968 // special case as described in JVM spec., p.243 & p.271.
1969 // The function returns the (pc) offset of the idivl
1970 // instruction - may be needed for implicit exceptions.
1971 //
1972 // normal case special case
1973 //
1974 // input : rax,: dividend min_int
1975 // reg: divisor (may not be rax,/rdx) -1
1976 //
1977 // output: rax,: quotient (= rax, idiv reg) min_int
1978 // rdx: remainder (= rax, irem reg) 0
1979 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1980 const int min_int = 0x80000000;
1981 Label normal_case, special_case;
1982
1983 // check for special case
1984 cmpl(rax, min_int);
1985 jcc(Assembler::notEqual, normal_case);
1986 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1987 cmpl(reg, -1);
1988 jcc(Assembler::equal, special_case);
1989
1990 // handle normal case
1991 bind(normal_case);
1992 cdql();
1993 int idivl_offset = offset();
1994 idivl(reg);
1995
1996 // normal and special case exit
1997 bind(special_case);
1998
1999 return idivl_offset;
2000 }
2001
2002
2003
2004 void MacroAssembler::decrementl(Register reg, int value) {
2005 if (value == min_jint) {subl(reg, value) ; return; }
2006 if (value < 0) { incrementl(reg, -value); return; }
2007 if (value == 0) { ; return; }
2008 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2009 /* else */ { subl(reg, value) ; return; }
2010 }
2011
2012 void MacroAssembler::decrementl(Address dst, int value) {
2013 if (value == min_jint) {subl(dst, value) ; return; }
2014 if (value < 0) { incrementl(dst, -value); return; }
2015 if (value == 0) { ; return; }
2016 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2017 /* else */ { subl(dst, value) ; return; }
2018 }
2019
2020 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2021 assert(shift_value > 0, "illegal shift value");
2022 Label _is_positive;
2023 testl (reg, reg);
2024 jcc (Assembler::positive, _is_positive);
2025 int offset = (1 << shift_value) - 1 ;
2026
2027 if (offset == 1) {
2028 incrementl(reg);
2029 } else {
2030 addl(reg, offset);
2031 }
2032
2033 bind (_is_positive);
2034 sarl(reg, shift_value);
2035 }
2036
2037 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2038 assert(rscratch != noreg || always_reachable(src), "missing");
2039
2040 if (reachable(src)) {
2041 Assembler::divsd(dst, as_Address(src));
2042 } else {
2043 lea(rscratch, src);
2044 Assembler::divsd(dst, Address(rscratch, 0));
2045 }
2046 }
2047
2048 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2049 assert(rscratch != noreg || always_reachable(src), "missing");
2050
2051 if (reachable(src)) {
2052 Assembler::divss(dst, as_Address(src));
2053 } else {
2054 lea(rscratch, src);
2055 Assembler::divss(dst, Address(rscratch, 0));
2056 }
2057 }
2058
2059 void MacroAssembler::enter() {
2060 push(rbp);
2061 mov(rbp, rsp);
2062 }
2063
2064 void MacroAssembler::post_call_nop() {
2065 if (!Continuations::enabled()) {
2066 return;
2067 }
2068 InstructionMark im(this);
2069 relocate(post_call_nop_Relocation::spec());
2070 InlineSkippedInstructionsCounter skipCounter(this);
2071 emit_int8((uint8_t)0x0f);
2072 emit_int8((uint8_t)0x1f);
2073 emit_int8((uint8_t)0x84);
2074 emit_int8((uint8_t)0x00);
2075 emit_int32(0x00);
2076 }
2077
2078 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2079 void MacroAssembler::fat_nop() {
2080 if (UseAddressNop) {
2081 addr_nop_5();
2082 } else {
2083 emit_int8((uint8_t)0x26); // es:
2084 emit_int8((uint8_t)0x2e); // cs:
2085 emit_int8((uint8_t)0x64); // fs:
2086 emit_int8((uint8_t)0x65); // gs:
2087 emit_int8((uint8_t)0x90);
2088 }
2089 }
2090
2091 #ifndef _LP64
2092 void MacroAssembler::fcmp(Register tmp) {
2093 fcmp(tmp, 1, true, true);
2094 }
2095
2096 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2097 assert(!pop_right || pop_left, "usage error");
2098 if (VM_Version::supports_cmov()) {
2099 assert(tmp == noreg, "unneeded temp");
2100 if (pop_left) {
2101 fucomip(index);
2102 } else {
2103 fucomi(index);
2104 }
2105 if (pop_right) {
2106 fpop();
2107 }
2108 } else {
2109 assert(tmp != noreg, "need temp");
2110 if (pop_left) {
2111 if (pop_right) {
2112 fcompp();
2113 } else {
2114 fcomp(index);
2115 }
2116 } else {
2117 fcom(index);
2118 }
2119 // convert FPU condition into eflags condition via rax,
2120 save_rax(tmp);
2121 fwait(); fnstsw_ax();
2122 sahf();
2123 restore_rax(tmp);
2124 }
2125 // condition codes set as follows:
2126 //
2127 // CF (corresponds to C0) if x < y
2128 // PF (corresponds to C2) if unordered
2129 // ZF (corresponds to C3) if x = y
2130 }
2131
2132 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2133 fcmp2int(dst, unordered_is_less, 1, true, true);
2134 }
2135
2136 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2137 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2138 Label L;
2139 if (unordered_is_less) {
2140 movl(dst, -1);
2141 jcc(Assembler::parity, L);
2142 jcc(Assembler::below , L);
2143 movl(dst, 0);
2144 jcc(Assembler::equal , L);
2145 increment(dst);
2146 } else { // unordered is greater
2147 movl(dst, 1);
2148 jcc(Assembler::parity, L);
2149 jcc(Assembler::above , L);
2150 movl(dst, 0);
2151 jcc(Assembler::equal , L);
2152 decrementl(dst);
2153 }
2154 bind(L);
2155 }
2156
2157 void MacroAssembler::fld_d(AddressLiteral src) {
2158 fld_d(as_Address(src));
2159 }
2160
2161 void MacroAssembler::fld_s(AddressLiteral src) {
2162 fld_s(as_Address(src));
2163 }
2164
2165 void MacroAssembler::fldcw(AddressLiteral src) {
2166 fldcw(as_Address(src));
2167 }
2168
2169 void MacroAssembler::fpop() {
2170 ffree();
2171 fincstp();
2172 }
2173
2174 void MacroAssembler::fremr(Register tmp) {
2175 save_rax(tmp);
2176 { Label L;
2177 bind(L);
2178 fprem();
2179 fwait(); fnstsw_ax();
2180 sahf();
2181 jcc(Assembler::parity, L);
2182 }
2183 restore_rax(tmp);
2184 // Result is in ST0.
2185 // Note: fxch & fpop to get rid of ST1
2186 // (otherwise FPU stack could overflow eventually)
2187 fxch(1);
2188 fpop();
2189 }
2190
2191 void MacroAssembler::empty_FPU_stack() {
2192 if (VM_Version::supports_mmx()) {
2193 emms();
2194 } else {
2195 for (int i = 8; i-- > 0; ) ffree(i);
2196 }
2197 }
2198 #endif // !LP64
2199
2200 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2201 assert(rscratch != noreg || always_reachable(src), "missing");
2202 if (reachable(src)) {
2203 Assembler::mulpd(dst, as_Address(src));
2204 } else {
2205 lea(rscratch, src);
2206 Assembler::mulpd(dst, Address(rscratch, 0));
2207 }
2208 }
2209
2210 void MacroAssembler::load_float(Address src) {
2211 #ifdef _LP64
2212 movflt(xmm0, src);
2213 #else
2214 if (UseSSE >= 1) {
2215 movflt(xmm0, src);
2216 } else {
2217 fld_s(src);
2218 }
2219 #endif // LP64
2220 }
2221
2222 void MacroAssembler::store_float(Address dst) {
2223 #ifdef _LP64
2224 movflt(dst, xmm0);
2225 #else
2226 if (UseSSE >= 1) {
2227 movflt(dst, xmm0);
2228 } else {
2229 fstp_s(dst);
2230 }
2231 #endif // LP64
2232 }
2233
2234 void MacroAssembler::load_double(Address src) {
2235 #ifdef _LP64
2236 movdbl(xmm0, src);
2237 #else
2238 if (UseSSE >= 2) {
2239 movdbl(xmm0, src);
2240 } else {
2241 fld_d(src);
2242 }
2243 #endif // LP64
2244 }
2245
2246 void MacroAssembler::store_double(Address dst) {
2247 #ifdef _LP64
2248 movdbl(dst, xmm0);
2249 #else
2250 if (UseSSE >= 2) {
2251 movdbl(dst, xmm0);
2252 } else {
2253 fstp_d(dst);
2254 }
2255 #endif // LP64
2256 }
2257
2258 // dst = c = a * b + c
2259 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2260 Assembler::vfmadd231sd(c, a, b);
2261 if (dst != c) {
2262 movdbl(dst, c);
2263 }
2264 }
2265
2266 // dst = c = a * b + c
2267 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2268 Assembler::vfmadd231ss(c, a, b);
2269 if (dst != c) {
2270 movflt(dst, c);
2271 }
2272 }
2273
2274 // dst = c = a * b + c
2275 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2276 Assembler::vfmadd231pd(c, a, b, vector_len);
2277 if (dst != c) {
2278 vmovdqu(dst, c);
2279 }
2280 }
2281
2282 // dst = c = a * b + c
2283 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2284 Assembler::vfmadd231ps(c, a, b, vector_len);
2285 if (dst != c) {
2286 vmovdqu(dst, c);
2287 }
2288 }
2289
2290 // dst = c = a * b + c
2291 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2292 Assembler::vfmadd231pd(c, a, b, vector_len);
2293 if (dst != c) {
2294 vmovdqu(dst, c);
2295 }
2296 }
2297
2298 // dst = c = a * b + c
2299 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2300 Assembler::vfmadd231ps(c, a, b, vector_len);
2301 if (dst != c) {
2302 vmovdqu(dst, c);
2303 }
2304 }
2305
2306 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
2307 assert(rscratch != noreg || always_reachable(dst), "missing");
2308
2309 if (reachable(dst)) {
2310 incrementl(as_Address(dst));
2311 } else {
2312 lea(rscratch, dst);
2313 incrementl(Address(rscratch, 0));
2314 }
2315 }
2316
2317 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
2318 incrementl(as_Address(dst, rscratch));
2319 }
2320
2321 void MacroAssembler::incrementl(Register reg, int value) {
2322 if (value == min_jint) {addl(reg, value) ; return; }
2323 if (value < 0) { decrementl(reg, -value); return; }
2324 if (value == 0) { ; return; }
2325 if (value == 1 && UseIncDec) { incl(reg) ; return; }
2326 /* else */ { addl(reg, value) ; return; }
2327 }
2328
2329 void MacroAssembler::incrementl(Address dst, int value) {
2330 if (value == min_jint) {addl(dst, value) ; return; }
2331 if (value < 0) { decrementl(dst, -value); return; }
2332 if (value == 0) { ; return; }
2333 if (value == 1 && UseIncDec) { incl(dst) ; return; }
2334 /* else */ { addl(dst, value) ; return; }
2335 }
2336
2337 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
2338 assert(rscratch != noreg || always_reachable(dst), "missing");
2339 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
2340 if (reachable(dst)) {
2341 jmp_literal(dst.target(), dst.rspec());
2342 } else {
2343 lea(rscratch, dst);
2344 jmp(rscratch);
2345 }
2346 }
2347
2348 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
2349 assert(rscratch != noreg || always_reachable(dst), "missing");
2350 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
2351 if (reachable(dst)) {
2352 InstructionMark im(this);
2353 relocate(dst.reloc());
2354 const int short_size = 2;
2355 const int long_size = 6;
2356 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2357 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2358 // 0111 tttn #8-bit disp
2359 emit_int8(0x70 | cc);
2360 emit_int8((offs - short_size) & 0xFF);
2361 } else {
2362 // 0000 1111 1000 tttn #32-bit disp
2363 emit_int8(0x0F);
2364 emit_int8((unsigned char)(0x80 | cc));
2365 emit_int32(offs - long_size);
2366 }
2367 } else {
2368 #ifdef ASSERT
2369 warning("reversing conditional branch");
2370 #endif /* ASSERT */
2371 Label skip;
2372 jccb(reverse[cc], skip);
2373 lea(rscratch, dst);
2374 Assembler::jmp(rscratch);
2375 bind(skip);
2376 }
2377 }
2378
2379 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
2380 assert(rscratch != noreg || always_reachable(src), "missing");
2381
2382 if (reachable(src)) {
2383 Assembler::ldmxcsr(as_Address(src));
2384 } else {
2385 lea(rscratch, src);
2386 Assembler::ldmxcsr(Address(rscratch, 0));
2387 }
2388 }
2389
2390 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2391 int off;
2392 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2393 off = offset();
2394 movsbl(dst, src); // movsxb
2395 } else {
2396 off = load_unsigned_byte(dst, src);
2397 shll(dst, 24);
2398 sarl(dst, 24);
2399 }
2400 return off;
2401 }
2402
2403 // Note: load_signed_short used to be called load_signed_word.
2404 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2405 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2406 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2407 int MacroAssembler::load_signed_short(Register dst, Address src) {
2408 int off;
2409 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2410 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2411 // version but this is what 64bit has always done. This seems to imply
2412 // that users are only using 32bits worth.
2413 off = offset();
2414 movswl(dst, src); // movsxw
2415 } else {
2416 off = load_unsigned_short(dst, src);
2417 shll(dst, 16);
2418 sarl(dst, 16);
2419 }
2420 return off;
2421 }
2422
2423 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2424 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2425 // and "3.9 Partial Register Penalties", p. 22).
2426 int off;
2427 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2428 off = offset();
2429 movzbl(dst, src); // movzxb
2430 } else {
2431 xorl(dst, dst);
2432 off = offset();
2433 movb(dst, src);
2434 }
2435 return off;
2436 }
2437
2438 // Note: load_unsigned_short used to be called load_unsigned_word.
2439 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2440 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2441 // and "3.9 Partial Register Penalties", p. 22).
2442 int off;
2443 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2444 off = offset();
2445 movzwl(dst, src); // movzxw
2446 } else {
2447 xorl(dst, dst);
2448 off = offset();
2449 movw(dst, src);
2450 }
2451 return off;
2452 }
2453
2454 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2455 switch (size_in_bytes) {
2456 #ifndef _LP64
2457 case 8:
2458 assert(dst2 != noreg, "second dest register required");
2459 movl(dst, src);
2460 movl(dst2, src.plus_disp(BytesPerInt));
2461 break;
2462 #else
2463 case 8: movq(dst, src); break;
2464 #endif
2465 case 4: movl(dst, src); break;
2466 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2467 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2468 default: ShouldNotReachHere();
2469 }
2470 }
2471
2472 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2473 switch (size_in_bytes) {
2474 #ifndef _LP64
2475 case 8:
2476 assert(src2 != noreg, "second source register required");
2477 movl(dst, src);
2478 movl(dst.plus_disp(BytesPerInt), src2);
2479 break;
2480 #else
2481 case 8: movq(dst, src); break;
2482 #endif
2483 case 4: movl(dst, src); break;
2484 case 2: movw(dst, src); break;
2485 case 1: movb(dst, src); break;
2486 default: ShouldNotReachHere();
2487 }
2488 }
2489
2490 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
2491 assert(rscratch != noreg || always_reachable(dst), "missing");
2492
2493 if (reachable(dst)) {
2494 movl(as_Address(dst), src);
2495 } else {
2496 lea(rscratch, dst);
2497 movl(Address(rscratch, 0), src);
2498 }
2499 }
2500
2501 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2502 if (reachable(src)) {
2503 movl(dst, as_Address(src));
2504 } else {
2505 lea(dst, src);
2506 movl(dst, Address(dst, 0));
2507 }
2508 }
2509
2510 // C++ bool manipulation
2511
2512 void MacroAssembler::movbool(Register dst, Address src) {
2513 if(sizeof(bool) == 1)
2514 movb(dst, src);
2515 else if(sizeof(bool) == 2)
2516 movw(dst, src);
2517 else if(sizeof(bool) == 4)
2518 movl(dst, src);
2519 else
2520 // unsupported
2521 ShouldNotReachHere();
2522 }
2523
2524 void MacroAssembler::movbool(Address dst, bool boolconst) {
2525 if(sizeof(bool) == 1)
2526 movb(dst, (int) boolconst);
2527 else if(sizeof(bool) == 2)
2528 movw(dst, (int) boolconst);
2529 else if(sizeof(bool) == 4)
2530 movl(dst, (int) boolconst);
2531 else
2532 // unsupported
2533 ShouldNotReachHere();
2534 }
2535
2536 void MacroAssembler::movbool(Address dst, Register src) {
2537 if(sizeof(bool) == 1)
2538 movb(dst, src);
2539 else if(sizeof(bool) == 2)
2540 movw(dst, src);
2541 else if(sizeof(bool) == 4)
2542 movl(dst, src);
2543 else
2544 // unsupported
2545 ShouldNotReachHere();
2546 }
2547
2548 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2549 assert(rscratch != noreg || always_reachable(src), "missing");
2550
2551 if (reachable(src)) {
2552 movdl(dst, as_Address(src));
2553 } else {
2554 lea(rscratch, src);
2555 movdl(dst, Address(rscratch, 0));
2556 }
2557 }
2558
2559 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
2560 assert(rscratch != noreg || always_reachable(src), "missing");
2561
2562 if (reachable(src)) {
2563 movq(dst, as_Address(src));
2564 } else {
2565 lea(rscratch, src);
2566 movq(dst, Address(rscratch, 0));
2567 }
2568 }
2569
2570 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2571 assert(rscratch != noreg || always_reachable(src), "missing");
2572
2573 if (reachable(src)) {
2574 if (UseXmmLoadAndClearUpper) {
2575 movsd (dst, as_Address(src));
2576 } else {
2577 movlpd(dst, as_Address(src));
2578 }
2579 } else {
2580 lea(rscratch, src);
2581 if (UseXmmLoadAndClearUpper) {
2582 movsd (dst, Address(rscratch, 0));
2583 } else {
2584 movlpd(dst, Address(rscratch, 0));
2585 }
2586 }
2587 }
2588
2589 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
2590 assert(rscratch != noreg || always_reachable(src), "missing");
2591
2592 if (reachable(src)) {
2593 movss(dst, as_Address(src));
2594 } else {
2595 lea(rscratch, src);
2596 movss(dst, Address(rscratch, 0));
2597 }
2598 }
2599
2600 void MacroAssembler::movptr(Register dst, Register src) {
2601 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2602 }
2603
2604 void MacroAssembler::movptr(Register dst, Address src) {
2605 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2606 }
2607
2608 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2609 void MacroAssembler::movptr(Register dst, intptr_t src) {
2610 #ifdef _LP64
2611 if (is_uimm32(src)) {
2612 movl(dst, checked_cast<uint32_t>(src));
2613 } else if (is_simm32(src)) {
2614 movq(dst, checked_cast<int32_t>(src));
2615 } else {
2616 mov64(dst, src);
2617 }
2618 #else
2619 movl(dst, src);
2620 #endif
2621 }
2622
2623 void MacroAssembler::movptr(Address dst, Register src) {
2624 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2625 }
2626
2627 void MacroAssembler::movptr(Address dst, int32_t src) {
2628 LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src));
2629 }
2630
2631 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2632 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2633 Assembler::movdqu(dst, src);
2634 }
2635
2636 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2637 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2638 Assembler::movdqu(dst, src);
2639 }
2640
2641 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2642 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2643 Assembler::movdqu(dst, src);
2644 }
2645
2646 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2647 assert(rscratch != noreg || always_reachable(src), "missing");
2648
2649 if (reachable(src)) {
2650 movdqu(dst, as_Address(src));
2651 } else {
2652 lea(rscratch, src);
2653 movdqu(dst, Address(rscratch, 0));
2654 }
2655 }
2656
2657 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2658 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2659 Assembler::vmovdqu(dst, src);
2660 }
2661
2662 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2663 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2664 Assembler::vmovdqu(dst, src);
2665 }
2666
2667 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2668 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2669 Assembler::vmovdqu(dst, src);
2670 }
2671
2672 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2673 assert(rscratch != noreg || always_reachable(src), "missing");
2674
2675 if (reachable(src)) {
2676 vmovdqu(dst, as_Address(src));
2677 }
2678 else {
2679 lea(rscratch, src);
2680 vmovdqu(dst, Address(rscratch, 0));
2681 }
2682 }
2683
2684 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2685 assert(rscratch != noreg || always_reachable(src), "missing");
2686
2687 if (vector_len == AVX_512bit) {
2688 evmovdquq(dst, src, AVX_512bit, rscratch);
2689 } else if (vector_len == AVX_256bit) {
2690 vmovdqu(dst, src, rscratch);
2691 } else {
2692 movdqu(dst, src, rscratch);
2693 }
2694 }
2695
2696 void MacroAssembler::kmov(KRegister dst, Address src) {
2697 if (VM_Version::supports_avx512bw()) {
2698 kmovql(dst, src);
2699 } else {
2700 assert(VM_Version::supports_evex(), "");
2701 kmovwl(dst, src);
2702 }
2703 }
2704
2705 void MacroAssembler::kmov(Address dst, KRegister src) {
2706 if (VM_Version::supports_avx512bw()) {
2707 kmovql(dst, src);
2708 } else {
2709 assert(VM_Version::supports_evex(), "");
2710 kmovwl(dst, src);
2711 }
2712 }
2713
2714 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2715 if (VM_Version::supports_avx512bw()) {
2716 kmovql(dst, src);
2717 } else {
2718 assert(VM_Version::supports_evex(), "");
2719 kmovwl(dst, src);
2720 }
2721 }
2722
2723 void MacroAssembler::kmov(Register dst, KRegister src) {
2724 if (VM_Version::supports_avx512bw()) {
2725 kmovql(dst, src);
2726 } else {
2727 assert(VM_Version::supports_evex(), "");
2728 kmovwl(dst, src);
2729 }
2730 }
2731
2732 void MacroAssembler::kmov(KRegister dst, Register src) {
2733 if (VM_Version::supports_avx512bw()) {
2734 kmovql(dst, src);
2735 } else {
2736 assert(VM_Version::supports_evex(), "");
2737 kmovwl(dst, src);
2738 }
2739 }
2740
2741 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2742 assert(rscratch != noreg || always_reachable(src), "missing");
2743
2744 if (reachable(src)) {
2745 kmovql(dst, as_Address(src));
2746 } else {
2747 lea(rscratch, src);
2748 kmovql(dst, Address(rscratch, 0));
2749 }
2750 }
2751
2752 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2753 assert(rscratch != noreg || always_reachable(src), "missing");
2754
2755 if (reachable(src)) {
2756 kmovwl(dst, as_Address(src));
2757 } else {
2758 lea(rscratch, src);
2759 kmovwl(dst, Address(rscratch, 0));
2760 }
2761 }
2762
2763 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2764 int vector_len, Register rscratch) {
2765 assert(rscratch != noreg || always_reachable(src), "missing");
2766
2767 if (reachable(src)) {
2768 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2769 } else {
2770 lea(rscratch, src);
2771 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2772 }
2773 }
2774
2775 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2776 int vector_len, Register rscratch) {
2777 assert(rscratch != noreg || always_reachable(src), "missing");
2778
2779 if (reachable(src)) {
2780 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2781 } else {
2782 lea(rscratch, src);
2783 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2784 }
2785 }
2786
2787 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2788 assert(rscratch != noreg || always_reachable(src), "missing");
2789
2790 if (reachable(src)) {
2791 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2792 } else {
2793 lea(rscratch, src);
2794 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2795 }
2796 }
2797
2798 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2799 assert(rscratch != noreg || always_reachable(src), "missing");
2800
2801 if (reachable(src)) {
2802 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2803 } else {
2804 lea(rscratch, src);
2805 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2806 }
2807 }
2808
2809 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2810 assert(rscratch != noreg || always_reachable(src), "missing");
2811
2812 if (reachable(src)) {
2813 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2814 } else {
2815 lea(rscratch, src);
2816 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2817 }
2818 }
2819
2820 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2821 assert(rscratch != noreg || always_reachable(src), "missing");
2822
2823 if (reachable(src)) {
2824 Assembler::movdqa(dst, as_Address(src));
2825 } else {
2826 lea(rscratch, src);
2827 Assembler::movdqa(dst, Address(rscratch, 0));
2828 }
2829 }
2830
2831 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2832 assert(rscratch != noreg || always_reachable(src), "missing");
2833
2834 if (reachable(src)) {
2835 Assembler::movsd(dst, as_Address(src));
2836 } else {
2837 lea(rscratch, src);
2838 Assembler::movsd(dst, Address(rscratch, 0));
2839 }
2840 }
2841
2842 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2843 assert(rscratch != noreg || always_reachable(src), "missing");
2844
2845 if (reachable(src)) {
2846 Assembler::movss(dst, as_Address(src));
2847 } else {
2848 lea(rscratch, src);
2849 Assembler::movss(dst, Address(rscratch, 0));
2850 }
2851 }
2852
2853 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2854 assert(rscratch != noreg || always_reachable(src), "missing");
2855
2856 if (reachable(src)) {
2857 Assembler::movddup(dst, as_Address(src));
2858 } else {
2859 lea(rscratch, src);
2860 Assembler::movddup(dst, Address(rscratch, 0));
2861 }
2862 }
2863
2864 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2865 assert(rscratch != noreg || always_reachable(src), "missing");
2866
2867 if (reachable(src)) {
2868 Assembler::vmovddup(dst, as_Address(src), vector_len);
2869 } else {
2870 lea(rscratch, src);
2871 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2872 }
2873 }
2874
2875 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2876 assert(rscratch != noreg || always_reachable(src), "missing");
2877
2878 if (reachable(src)) {
2879 Assembler::mulsd(dst, as_Address(src));
2880 } else {
2881 lea(rscratch, src);
2882 Assembler::mulsd(dst, Address(rscratch, 0));
2883 }
2884 }
2885
2886 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2887 assert(rscratch != noreg || always_reachable(src), "missing");
2888
2889 if (reachable(src)) {
2890 Assembler::mulss(dst, as_Address(src));
2891 } else {
2892 lea(rscratch, src);
2893 Assembler::mulss(dst, Address(rscratch, 0));
2894 }
2895 }
2896
2897 void MacroAssembler::null_check(Register reg, int offset) {
2898 if (needs_explicit_null_check(offset)) {
2899 // provoke OS null exception if reg is null by
2900 // accessing M[reg] w/o changing any (non-CC) registers
2901 // NOTE: cmpl is plenty here to provoke a segv
2902 cmpptr(rax, Address(reg, 0));
2903 // Note: should probably use testl(rax, Address(reg, 0));
2904 // may be shorter code (however, this version of
2905 // testl needs to be implemented first)
2906 } else {
2907 // nothing to do, (later) access of M[reg + offset]
2908 // will provoke OS null exception if reg is null
2909 }
2910 }
2911
2912 void MacroAssembler::os_breakpoint() {
2913 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2914 // (e.g., MSVC can't call ps() otherwise)
2915 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2916 }
2917
2918 void MacroAssembler::unimplemented(const char* what) {
2919 const char* buf = nullptr;
2920 {
2921 ResourceMark rm;
2922 stringStream ss;
2923 ss.print("unimplemented: %s", what);
2924 buf = code_string(ss.as_string());
2925 }
2926 stop(buf);
2927 }
2928
2929 #ifdef _LP64
2930 #define XSTATE_BV 0x200
2931 #endif
2932
2933 void MacroAssembler::pop_CPU_state() {
2934 pop_FPU_state();
2935 pop_IU_state();
2936 }
2937
2938 void MacroAssembler::pop_FPU_state() {
2939 #ifndef _LP64
2940 frstor(Address(rsp, 0));
2941 #else
2942 fxrstor(Address(rsp, 0));
2943 #endif
2944 addptr(rsp, FPUStateSizeInWords * wordSize);
2945 }
2946
2947 void MacroAssembler::pop_IU_state() {
2948 popa();
2949 LP64_ONLY(addq(rsp, 8));
2950 popf();
2951 }
2952
2953 // Save Integer and Float state
2954 // Warning: Stack must be 16 byte aligned (64bit)
2955 void MacroAssembler::push_CPU_state() {
2956 push_IU_state();
2957 push_FPU_state();
2958 }
2959
2960 void MacroAssembler::push_FPU_state() {
2961 subptr(rsp, FPUStateSizeInWords * wordSize);
2962 #ifndef _LP64
2963 fnsave(Address(rsp, 0));
2964 fwait();
2965 #else
2966 fxsave(Address(rsp, 0));
2967 #endif // LP64
2968 }
2969
2970 void MacroAssembler::push_IU_state() {
2971 // Push flags first because pusha kills them
2972 pushf();
2973 // Make sure rsp stays 16-byte aligned
2974 LP64_ONLY(subq(rsp, 8));
2975 pusha();
2976 }
2977
2978 void MacroAssembler::push_cont_fastpath() {
2979 if (!Continuations::enabled()) return;
2980
2981 #ifndef _LP64
2982 Register rthread = rax;
2983 Register rrealsp = rbx;
2984 push(rthread);
2985 push(rrealsp);
2986
2987 get_thread(rthread);
2988
2989 // The code below wants the original RSP.
2990 // Move it back after the pushes above.
2991 movptr(rrealsp, rsp);
2992 addptr(rrealsp, 2*wordSize);
2993 #else
2994 Register rthread = r15_thread;
2995 Register rrealsp = rsp;
2996 #endif
2997
2998 Label done;
2999 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3000 jccb(Assembler::belowEqual, done);
3001 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), rrealsp);
3002 bind(done);
3003
3004 #ifndef _LP64
3005 pop(rrealsp);
3006 pop(rthread);
3007 #endif
3008 }
3009
3010 void MacroAssembler::pop_cont_fastpath() {
3011 if (!Continuations::enabled()) return;
3012
3013 #ifndef _LP64
3014 Register rthread = rax;
3015 Register rrealsp = rbx;
3016 push(rthread);
3017 push(rrealsp);
3018
3019 get_thread(rthread);
3020
3021 // The code below wants the original RSP.
3022 // Move it back after the pushes above.
3023 movptr(rrealsp, rsp);
3024 addptr(rrealsp, 2*wordSize);
3025 #else
3026 Register rthread = r15_thread;
3027 Register rrealsp = rsp;
3028 #endif
3029
3030 Label done;
3031 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3032 jccb(Assembler::below, done);
3033 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), 0);
3034 bind(done);
3035
3036 #ifndef _LP64
3037 pop(rrealsp);
3038 pop(rthread);
3039 #endif
3040 }
3041
3042 void MacroAssembler::inc_held_monitor_count() {
3043 #ifdef _LP64
3044 incrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3045 #endif
3046 }
3047
3048 void MacroAssembler::dec_held_monitor_count() {
3049 #ifdef _LP64
3050 decrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3051 #endif
3052 }
3053
3054 #ifdef ASSERT
3055 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
3056 #ifdef _LP64
3057 Label no_cont;
3058 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
3059 testl(cont, cont);
3060 jcc(Assembler::zero, no_cont);
3061 stop(name);
3062 bind(no_cont);
3063 #else
3064 Unimplemented();
3065 #endif
3066 }
3067 #endif
3068
3069 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3070 if (!java_thread->is_valid()) {
3071 java_thread = rdi;
3072 get_thread(java_thread);
3073 }
3074 // we must set sp to zero to clear frame
3075 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3076 // must clear fp, so that compiled frames are not confused; it is
3077 // possible that we need it only for debugging
3078 if (clear_fp) {
3079 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3080 }
3081 // Always clear the pc because it could have been set by make_walkable()
3082 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3083 vzeroupper();
3084 }
3085
3086 void MacroAssembler::restore_rax(Register tmp) {
3087 if (tmp == noreg) pop(rax);
3088 else if (tmp != rax) mov(rax, tmp);
3089 }
3090
3091 void MacroAssembler::round_to(Register reg, int modulus) {
3092 addptr(reg, modulus - 1);
3093 andptr(reg, -modulus);
3094 }
3095
3096 void MacroAssembler::save_rax(Register tmp) {
3097 if (tmp == noreg) push(rax);
3098 else if (tmp != rax) mov(tmp, rax);
3099 }
3100
3101 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
3102 if (at_return) {
3103 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
3104 // we may safely use rsp instead to perform the stack watermark check.
3105 cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
3106 jcc(Assembler::above, slow_path);
3107 return;
3108 }
3109 testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
3110 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3111 }
3112
3113 // Calls to C land
3114 //
3115 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3116 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3117 // has to be reset to 0. This is required to allow proper stack traversal.
3118 void MacroAssembler::set_last_Java_frame(Register java_thread,
3119 Register last_java_sp,
3120 Register last_java_fp,
3121 address last_java_pc,
3122 Register rscratch) {
3123 vzeroupper();
3124 // determine java_thread register
3125 if (!java_thread->is_valid()) {
3126 java_thread = rdi;
3127 get_thread(java_thread);
3128 }
3129 // determine last_java_sp register
3130 if (!last_java_sp->is_valid()) {
3131 last_java_sp = rsp;
3132 }
3133 // last_java_fp is optional
3134 if (last_java_fp->is_valid()) {
3135 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3136 }
3137 // last_java_pc is optional
3138 if (last_java_pc != nullptr) {
3139 Address java_pc(java_thread,
3140 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
3141 lea(java_pc, InternalAddress(last_java_pc), rscratch);
3142 }
3143 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3144 }
3145
3146 #ifdef _LP64
3147 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
3148 Register last_java_fp,
3149 Label &L,
3150 Register scratch) {
3151 lea(scratch, L);
3152 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
3153 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, nullptr, scratch);
3154 }
3155 #endif
3156
3157 void MacroAssembler::shlptr(Register dst, int imm8) {
3158 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3159 }
3160
3161 void MacroAssembler::shrptr(Register dst, int imm8) {
3162 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3163 }
3164
3165 void MacroAssembler::sign_extend_byte(Register reg) {
3166 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3167 movsbl(reg, reg); // movsxb
3168 } else {
3169 shll(reg, 24);
3170 sarl(reg, 24);
3171 }
3172 }
3173
3174 void MacroAssembler::sign_extend_short(Register reg) {
3175 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3176 movswl(reg, reg); // movsxw
3177 } else {
3178 shll(reg, 16);
3179 sarl(reg, 16);
3180 }
3181 }
3182
3183 void MacroAssembler::testl(Address dst, int32_t imm32) {
3184 if (imm32 >= 0 && is8bit(imm32)) {
3185 testb(dst, imm32);
3186 } else {
3187 Assembler::testl(dst, imm32);
3188 }
3189 }
3190
3191 void MacroAssembler::testl(Register dst, int32_t imm32) {
3192 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
3193 testb(dst, imm32);
3194 } else {
3195 Assembler::testl(dst, imm32);
3196 }
3197 }
3198
3199 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3200 assert(always_reachable(src), "Address should be reachable");
3201 testl(dst, as_Address(src));
3202 }
3203
3204 #ifdef _LP64
3205
3206 void MacroAssembler::testq(Address dst, int32_t imm32) {
3207 if (imm32 >= 0) {
3208 testl(dst, imm32);
3209 } else {
3210 Assembler::testq(dst, imm32);
3211 }
3212 }
3213
3214 void MacroAssembler::testq(Register dst, int32_t imm32) {
3215 if (imm32 >= 0) {
3216 testl(dst, imm32);
3217 } else {
3218 Assembler::testq(dst, imm32);
3219 }
3220 }
3221
3222 #endif
3223
3224 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3225 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3226 Assembler::pcmpeqb(dst, src);
3227 }
3228
3229 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3230 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3231 Assembler::pcmpeqw(dst, src);
3232 }
3233
3234 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3235 assert((dst->encoding() < 16),"XMM register should be 0-15");
3236 Assembler::pcmpestri(dst, src, imm8);
3237 }
3238
3239 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3240 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3241 Assembler::pcmpestri(dst, src, imm8);
3242 }
3243
3244 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3245 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3246 Assembler::pmovzxbw(dst, src);
3247 }
3248
3249 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3250 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3251 Assembler::pmovzxbw(dst, src);
3252 }
3253
3254 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3255 assert((src->encoding() < 16),"XMM register should be 0-15");
3256 Assembler::pmovmskb(dst, src);
3257 }
3258
3259 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3260 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3261 Assembler::ptest(dst, src);
3262 }
3263
3264 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3265 assert(rscratch != noreg || always_reachable(src), "missing");
3266
3267 if (reachable(src)) {
3268 Assembler::sqrtss(dst, as_Address(src));
3269 } else {
3270 lea(rscratch, src);
3271 Assembler::sqrtss(dst, Address(rscratch, 0));
3272 }
3273 }
3274
3275 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3276 assert(rscratch != noreg || always_reachable(src), "missing");
3277
3278 if (reachable(src)) {
3279 Assembler::subsd(dst, as_Address(src));
3280 } else {
3281 lea(rscratch, src);
3282 Assembler::subsd(dst, Address(rscratch, 0));
3283 }
3284 }
3285
3286 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
3287 assert(rscratch != noreg || always_reachable(src), "missing");
3288
3289 if (reachable(src)) {
3290 Assembler::roundsd(dst, as_Address(src), rmode);
3291 } else {
3292 lea(rscratch, src);
3293 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
3294 }
3295 }
3296
3297 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3298 assert(rscratch != noreg || always_reachable(src), "missing");
3299
3300 if (reachable(src)) {
3301 Assembler::subss(dst, as_Address(src));
3302 } else {
3303 lea(rscratch, src);
3304 Assembler::subss(dst, Address(rscratch, 0));
3305 }
3306 }
3307
3308 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3309 assert(rscratch != noreg || always_reachable(src), "missing");
3310
3311 if (reachable(src)) {
3312 Assembler::ucomisd(dst, as_Address(src));
3313 } else {
3314 lea(rscratch, src);
3315 Assembler::ucomisd(dst, Address(rscratch, 0));
3316 }
3317 }
3318
3319 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3320 assert(rscratch != noreg || always_reachable(src), "missing");
3321
3322 if (reachable(src)) {
3323 Assembler::ucomiss(dst, as_Address(src));
3324 } else {
3325 lea(rscratch, src);
3326 Assembler::ucomiss(dst, Address(rscratch, 0));
3327 }
3328 }
3329
3330 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3331 assert(rscratch != noreg || always_reachable(src), "missing");
3332
3333 // Used in sign-bit flipping with aligned address.
3334 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3335 if (reachable(src)) {
3336 Assembler::xorpd(dst, as_Address(src));
3337 } else {
3338 lea(rscratch, src);
3339 Assembler::xorpd(dst, Address(rscratch, 0));
3340 }
3341 }
3342
3343 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3344 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3345 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3346 }
3347 else {
3348 Assembler::xorpd(dst, src);
3349 }
3350 }
3351
3352 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3353 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3354 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3355 } else {
3356 Assembler::xorps(dst, src);
3357 }
3358 }
3359
3360 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
3361 assert(rscratch != noreg || always_reachable(src), "missing");
3362
3363 // Used in sign-bit flipping with aligned address.
3364 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3365 if (reachable(src)) {
3366 Assembler::xorps(dst, as_Address(src));
3367 } else {
3368 lea(rscratch, src);
3369 Assembler::xorps(dst, Address(rscratch, 0));
3370 }
3371 }
3372
3373 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
3374 assert(rscratch != noreg || always_reachable(src), "missing");
3375
3376 // Used in sign-bit flipping with aligned address.
3377 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3378 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3379 if (reachable(src)) {
3380 Assembler::pshufb(dst, as_Address(src));
3381 } else {
3382 lea(rscratch, src);
3383 Assembler::pshufb(dst, Address(rscratch, 0));
3384 }
3385 }
3386
3387 // AVX 3-operands instructions
3388
3389 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3390 assert(rscratch != noreg || always_reachable(src), "missing");
3391
3392 if (reachable(src)) {
3393 vaddsd(dst, nds, as_Address(src));
3394 } else {
3395 lea(rscratch, src);
3396 vaddsd(dst, nds, Address(rscratch, 0));
3397 }
3398 }
3399
3400 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3401 assert(rscratch != noreg || always_reachable(src), "missing");
3402
3403 if (reachable(src)) {
3404 vaddss(dst, nds, as_Address(src));
3405 } else {
3406 lea(rscratch, src);
3407 vaddss(dst, nds, Address(rscratch, 0));
3408 }
3409 }
3410
3411 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3412 assert(UseAVX > 0, "requires some form of AVX");
3413 assert(rscratch != noreg || always_reachable(src), "missing");
3414
3415 if (reachable(src)) {
3416 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3417 } else {
3418 lea(rscratch, src);
3419 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3420 }
3421 }
3422
3423 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3424 assert(UseAVX > 0, "requires some form of AVX");
3425 assert(rscratch != noreg || always_reachable(src), "missing");
3426
3427 if (reachable(src)) {
3428 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3429 } else {
3430 lea(rscratch, src);
3431 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3432 }
3433 }
3434
3435 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3436 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3437 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3438
3439 vandps(dst, nds, negate_field, vector_len, rscratch);
3440 }
3441
3442 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3443 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3444 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3445
3446 vandpd(dst, nds, negate_field, vector_len, rscratch);
3447 }
3448
3449 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3450 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3451 Assembler::vpaddb(dst, nds, src, vector_len);
3452 }
3453
3454 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3455 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3456 Assembler::vpaddb(dst, nds, src, vector_len);
3457 }
3458
3459 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3460 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3461 Assembler::vpaddw(dst, nds, src, vector_len);
3462 }
3463
3464 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3465 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3466 Assembler::vpaddw(dst, nds, src, vector_len);
3467 }
3468
3469 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3470 assert(rscratch != noreg || always_reachable(src), "missing");
3471
3472 if (reachable(src)) {
3473 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3474 } else {
3475 lea(rscratch, src);
3476 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
3477 }
3478 }
3479
3480 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3481 assert(rscratch != noreg || always_reachable(src), "missing");
3482
3483 if (reachable(src)) {
3484 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
3485 } else {
3486 lea(rscratch, src);
3487 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
3488 }
3489 }
3490
3491 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3492 assert(rscratch != noreg || always_reachable(src), "missing");
3493
3494 if (reachable(src)) {
3495 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
3496 } else {
3497 lea(rscratch, src);
3498 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
3499 }
3500 }
3501
3502 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3503 assert(rscratch != noreg || always_reachable(src), "missing");
3504
3505 if (reachable(src)) {
3506 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3507 } else {
3508 lea(rscratch, src);
3509 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3510 }
3511 }
3512
3513 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3514 assert(rscratch != noreg || always_reachable(src), "missing");
3515
3516 if (reachable(src)) {
3517 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3518 } else {
3519 lea(rscratch, src);
3520 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3521 }
3522 }
3523
3524 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3525 assert(rscratch != noreg || always_reachable(src), "missing");
3526
3527 if (reachable(src)) {
3528 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3529 } else {
3530 lea(rscratch, src);
3531 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3532 }
3533 }
3534
3535 // Vector float blend
3536 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3537 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3538 // WARN: Allow dst == (src1|src2), mask == scratch
3539 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3540 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3541 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3542 if (blend_emulation && scratch_available && dst_available) {
3543 if (compute_mask) {
3544 vpsrad(scratch, mask, 32, vector_len);
3545 mask = scratch;
3546 }
3547 if (dst == src1) {
3548 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3549 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3550 } else {
3551 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3552 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3553 }
3554 vpor(dst, dst, scratch, vector_len);
3555 } else {
3556 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3557 }
3558 }
3559
3560 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3561 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3562 // WARN: Allow dst == (src1|src2), mask == scratch
3563 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3564 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3565 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3566 if (blend_emulation && scratch_available && dst_available) {
3567 if (compute_mask) {
3568 vpxor(scratch, scratch, scratch, vector_len);
3569 vpcmpgtq(scratch, scratch, mask, vector_len);
3570 mask = scratch;
3571 }
3572 if (dst == src1) {
3573 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3574 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3575 } else {
3576 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3577 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3578 }
3579 vpor(dst, dst, scratch, vector_len);
3580 } else {
3581 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3582 }
3583 }
3584
3585 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3586 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3587 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3588 }
3589
3590 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3591 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3592 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3593 }
3594
3595 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3596 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3597 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3598 }
3599
3600 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3601 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3602 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3603 }
3604
3605 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3606 assert(rscratch != noreg || always_reachable(src), "missing");
3607
3608 if (reachable(src)) {
3609 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3610 } else {
3611 lea(rscratch, src);
3612 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3613 }
3614 }
3615
3616 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3617 int comparison, bool is_signed, int vector_len, Register rscratch) {
3618 assert(rscratch != noreg || always_reachable(src), "missing");
3619
3620 if (reachable(src)) {
3621 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3622 } else {
3623 lea(rscratch, src);
3624 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3625 }
3626 }
3627
3628 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3629 int comparison, bool is_signed, int vector_len, Register rscratch) {
3630 assert(rscratch != noreg || always_reachable(src), "missing");
3631
3632 if (reachable(src)) {
3633 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3634 } else {
3635 lea(rscratch, src);
3636 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3637 }
3638 }
3639
3640 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3641 int comparison, bool is_signed, int vector_len, Register rscratch) {
3642 assert(rscratch != noreg || always_reachable(src), "missing");
3643
3644 if (reachable(src)) {
3645 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3646 } else {
3647 lea(rscratch, src);
3648 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3649 }
3650 }
3651
3652 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3653 int comparison, bool is_signed, int vector_len, Register rscratch) {
3654 assert(rscratch != noreg || always_reachable(src), "missing");
3655
3656 if (reachable(src)) {
3657 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3658 } else {
3659 lea(rscratch, src);
3660 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3661 }
3662 }
3663
3664 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3665 if (width == Assembler::Q) {
3666 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3667 } else {
3668 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3669 }
3670 }
3671
3672 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3673 int eq_cond_enc = 0x29;
3674 int gt_cond_enc = 0x37;
3675 if (width != Assembler::Q) {
3676 eq_cond_enc = 0x74 + width;
3677 gt_cond_enc = 0x64 + width;
3678 }
3679 switch (cond) {
3680 case eq:
3681 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3682 break;
3683 case neq:
3684 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3685 vallones(xtmp, vector_len);
3686 vpxor(dst, xtmp, dst, vector_len);
3687 break;
3688 case le:
3689 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3690 vallones(xtmp, vector_len);
3691 vpxor(dst, xtmp, dst, vector_len);
3692 break;
3693 case nlt:
3694 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3695 vallones(xtmp, vector_len);
3696 vpxor(dst, xtmp, dst, vector_len);
3697 break;
3698 case lt:
3699 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3700 break;
3701 case nle:
3702 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3703 break;
3704 default:
3705 assert(false, "Should not reach here");
3706 }
3707 }
3708
3709 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3710 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3711 Assembler::vpmovzxbw(dst, src, vector_len);
3712 }
3713
3714 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3715 assert((src->encoding() < 16),"XMM register should be 0-15");
3716 Assembler::vpmovmskb(dst, src, vector_len);
3717 }
3718
3719 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3720 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3721 Assembler::vpmullw(dst, nds, src, vector_len);
3722 }
3723
3724 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3725 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3726 Assembler::vpmullw(dst, nds, src, vector_len);
3727 }
3728
3729 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3730 assert((UseAVX > 0), "AVX support is needed");
3731 assert(rscratch != noreg || always_reachable(src), "missing");
3732
3733 if (reachable(src)) {
3734 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3735 } else {
3736 lea(rscratch, src);
3737 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3738 }
3739 }
3740
3741 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3742 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3743 Assembler::vpsubb(dst, nds, src, vector_len);
3744 }
3745
3746 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3747 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3748 Assembler::vpsubb(dst, nds, src, vector_len);
3749 }
3750
3751 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3752 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3753 Assembler::vpsubw(dst, nds, src, vector_len);
3754 }
3755
3756 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3757 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3758 Assembler::vpsubw(dst, nds, src, vector_len);
3759 }
3760
3761 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3762 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3763 Assembler::vpsraw(dst, nds, shift, vector_len);
3764 }
3765
3766 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3767 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3768 Assembler::vpsraw(dst, nds, shift, vector_len);
3769 }
3770
3771 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3772 assert(UseAVX > 2,"");
3773 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3774 vector_len = 2;
3775 }
3776 Assembler::evpsraq(dst, nds, shift, vector_len);
3777 }
3778
3779 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3780 assert(UseAVX > 2,"");
3781 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3782 vector_len = 2;
3783 }
3784 Assembler::evpsraq(dst, nds, shift, vector_len);
3785 }
3786
3787 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3788 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3789 Assembler::vpsrlw(dst, nds, shift, vector_len);
3790 }
3791
3792 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3793 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3794 Assembler::vpsrlw(dst, nds, shift, vector_len);
3795 }
3796
3797 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3798 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3799 Assembler::vpsllw(dst, nds, shift, vector_len);
3800 }
3801
3802 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3803 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3804 Assembler::vpsllw(dst, nds, shift, vector_len);
3805 }
3806
3807 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3808 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3809 Assembler::vptest(dst, src);
3810 }
3811
3812 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3813 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3814 Assembler::punpcklbw(dst, src);
3815 }
3816
3817 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3818 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3819 Assembler::pshufd(dst, src, mode);
3820 }
3821
3822 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3823 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3824 Assembler::pshuflw(dst, src, mode);
3825 }
3826
3827 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3828 assert(rscratch != noreg || always_reachable(src), "missing");
3829
3830 if (reachable(src)) {
3831 vandpd(dst, nds, as_Address(src), vector_len);
3832 } else {
3833 lea(rscratch, src);
3834 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3835 }
3836 }
3837
3838 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3839 assert(rscratch != noreg || always_reachable(src), "missing");
3840
3841 if (reachable(src)) {
3842 vandps(dst, nds, as_Address(src), vector_len);
3843 } else {
3844 lea(rscratch, src);
3845 vandps(dst, nds, Address(rscratch, 0), vector_len);
3846 }
3847 }
3848
3849 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3850 bool merge, int vector_len, Register rscratch) {
3851 assert(rscratch != noreg || always_reachable(src), "missing");
3852
3853 if (reachable(src)) {
3854 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3855 } else {
3856 lea(rscratch, src);
3857 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3858 }
3859 }
3860
3861 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3862 assert(rscratch != noreg || always_reachable(src), "missing");
3863
3864 if (reachable(src)) {
3865 vdivsd(dst, nds, as_Address(src));
3866 } else {
3867 lea(rscratch, src);
3868 vdivsd(dst, nds, Address(rscratch, 0));
3869 }
3870 }
3871
3872 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3873 assert(rscratch != noreg || always_reachable(src), "missing");
3874
3875 if (reachable(src)) {
3876 vdivss(dst, nds, as_Address(src));
3877 } else {
3878 lea(rscratch, src);
3879 vdivss(dst, nds, Address(rscratch, 0));
3880 }
3881 }
3882
3883 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3884 assert(rscratch != noreg || always_reachable(src), "missing");
3885
3886 if (reachable(src)) {
3887 vmulsd(dst, nds, as_Address(src));
3888 } else {
3889 lea(rscratch, src);
3890 vmulsd(dst, nds, Address(rscratch, 0));
3891 }
3892 }
3893
3894 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3895 assert(rscratch != noreg || always_reachable(src), "missing");
3896
3897 if (reachable(src)) {
3898 vmulss(dst, nds, as_Address(src));
3899 } else {
3900 lea(rscratch, src);
3901 vmulss(dst, nds, Address(rscratch, 0));
3902 }
3903 }
3904
3905 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3906 assert(rscratch != noreg || always_reachable(src), "missing");
3907
3908 if (reachable(src)) {
3909 vsubsd(dst, nds, as_Address(src));
3910 } else {
3911 lea(rscratch, src);
3912 vsubsd(dst, nds, Address(rscratch, 0));
3913 }
3914 }
3915
3916 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3917 assert(rscratch != noreg || always_reachable(src), "missing");
3918
3919 if (reachable(src)) {
3920 vsubss(dst, nds, as_Address(src));
3921 } else {
3922 lea(rscratch, src);
3923 vsubss(dst, nds, Address(rscratch, 0));
3924 }
3925 }
3926
3927 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3928 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3929 assert(rscratch != noreg || always_reachable(src), "missing");
3930
3931 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3932 }
3933
3934 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3935 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3936 assert(rscratch != noreg || always_reachable(src), "missing");
3937
3938 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3939 }
3940
3941 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3942 assert(rscratch != noreg || always_reachable(src), "missing");
3943
3944 if (reachable(src)) {
3945 vxorpd(dst, nds, as_Address(src), vector_len);
3946 } else {
3947 lea(rscratch, src);
3948 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3949 }
3950 }
3951
3952 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3953 assert(rscratch != noreg || always_reachable(src), "missing");
3954
3955 if (reachable(src)) {
3956 vxorps(dst, nds, as_Address(src), vector_len);
3957 } else {
3958 lea(rscratch, src);
3959 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3960 }
3961 }
3962
3963 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3964 assert(rscratch != noreg || always_reachable(src), "missing");
3965
3966 if (UseAVX > 1 || (vector_len < 1)) {
3967 if (reachable(src)) {
3968 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3969 } else {
3970 lea(rscratch, src);
3971 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3972 }
3973 } else {
3974 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3975 }
3976 }
3977
3978 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3979 assert(rscratch != noreg || always_reachable(src), "missing");
3980
3981 if (reachable(src)) {
3982 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3983 } else {
3984 lea(rscratch, src);
3985 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3986 }
3987 }
3988
3989 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3990 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3991 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3992 // The inverted mask is sign-extended
3993 andptr(possibly_non_local, inverted_mask);
3994 }
3995
3996 void MacroAssembler::resolve_jobject(Register value,
3997 Register thread,
3998 Register tmp) {
3999 assert_different_registers(value, thread, tmp);
4000 Label done, tagged, weak_tagged;
4001 testptr(value, value);
4002 jcc(Assembler::zero, done); // Use null as-is.
4003 testptr(value, JNIHandles::tag_mask); // Test for tag.
4004 jcc(Assembler::notZero, tagged);
4005
4006 // Resolve local handle
4007 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp, thread);
4008 verify_oop(value);
4009 jmp(done);
4010
4011 bind(tagged);
4012 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
4013 jcc(Assembler::notZero, weak_tagged);
4014
4015 // Resolve global handle
4016 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4017 verify_oop(value);
4018 jmp(done);
4019
4020 bind(weak_tagged);
4021 // Resolve jweak.
4022 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4023 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp, thread);
4024 verify_oop(value);
4025
4026 bind(done);
4027 }
4028
4029 void MacroAssembler::resolve_global_jobject(Register value,
4030 Register thread,
4031 Register tmp) {
4032 assert_different_registers(value, thread, tmp);
4033 Label done;
4034
4035 testptr(value, value);
4036 jcc(Assembler::zero, done); // Use null as-is.
4037
4038 #ifdef ASSERT
4039 {
4040 Label valid_global_tag;
4041 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
4042 jcc(Assembler::notZero, valid_global_tag);
4043 stop("non global jobject using resolve_global_jobject");
4044 bind(valid_global_tag);
4045 }
4046 #endif
4047
4048 // Resolve global handle
4049 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4050 verify_oop(value);
4051
4052 bind(done);
4053 }
4054
4055 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4056 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4057 }
4058
4059 // Force generation of a 4 byte immediate value even if it fits into 8bit
4060 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4061 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4062 }
4063
4064 void MacroAssembler::subptr(Register dst, Register src) {
4065 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4066 }
4067
4068 // C++ bool manipulation
4069 void MacroAssembler::testbool(Register dst) {
4070 if(sizeof(bool) == 1)
4071 testb(dst, 0xff);
4072 else if(sizeof(bool) == 2) {
4073 // testw implementation needed for two byte bools
4074 ShouldNotReachHere();
4075 } else if(sizeof(bool) == 4)
4076 testl(dst, dst);
4077 else
4078 // unsupported
4079 ShouldNotReachHere();
4080 }
4081
4082 void MacroAssembler::testptr(Register dst, Register src) {
4083 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4084 }
4085
4086 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4087 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4088 Register var_size_in_bytes,
4089 int con_size_in_bytes,
4090 Register t1,
4091 Register t2,
4092 Label& slow_case) {
4093 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4094 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4095 }
4096
4097 RegSet MacroAssembler::call_clobbered_gp_registers() {
4098 RegSet regs;
4099 #ifdef _LP64
4100 regs += RegSet::of(rax, rcx, rdx);
4101 #ifndef _WINDOWS
4102 regs += RegSet::of(rsi, rdi);
4103 #endif
4104 regs += RegSet::range(r8, r11);
4105 #else
4106 regs += RegSet::of(rax, rcx, rdx);
4107 #endif
4108 #ifdef _LP64
4109 if (UseAPX) {
4110 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
4111 }
4112 #endif
4113 return regs;
4114 }
4115
4116 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
4117 int num_xmm_registers = XMMRegister::available_xmm_registers();
4118 #if defined(_WINDOWS)
4119 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
4120 if (num_xmm_registers > 16) {
4121 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
4122 }
4123 return result;
4124 #else
4125 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
4126 #endif
4127 }
4128
4129 static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor
4130
4131 #ifndef _LP64
4132 static bool use_x87_registers() { return UseSSE < 2; }
4133 #endif
4134 static bool use_xmm_registers() { return UseSSE >= 1; }
4135
4136 // C1 only ever uses the first double/float of the XMM register.
4137 static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); }
4138
4139 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4140 if (UseSSE == 1) {
4141 masm->movflt(Address(rsp, offset), reg);
4142 } else {
4143 masm->movdbl(Address(rsp, offset), reg);
4144 }
4145 }
4146
4147 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4148 if (UseSSE == 1) {
4149 masm->movflt(reg, Address(rsp, offset));
4150 } else {
4151 masm->movdbl(reg, Address(rsp, offset));
4152 }
4153 }
4154
4155 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
4156 bool save_fpu, int& gp_area_size,
4157 int& fp_area_size, int& xmm_area_size) {
4158
4159 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
4160 StackAlignmentInBytes);
4161 #ifdef _LP64
4162 fp_area_size = 0;
4163 #else
4164 fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0;
4165 #endif
4166 xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0;
4167
4168 return gp_area_size + fp_area_size + xmm_area_size;
4169 }
4170
4171 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
4172 block_comment("push_call_clobbered_registers start");
4173 // Regular registers
4174 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
4175
4176 int gp_area_size;
4177 int fp_area_size;
4178 int xmm_area_size;
4179 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
4180 gp_area_size, fp_area_size, xmm_area_size);
4181 subptr(rsp, total_save_size);
4182
4183 push_set(gp_registers_to_push, 0);
4184
4185 #ifndef _LP64
4186 if (save_fpu && use_x87_registers()) {
4187 fnsave(Address(rsp, gp_area_size));
4188 fwait();
4189 }
4190 #endif
4191 if (save_fpu && use_xmm_registers()) {
4192 push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4193 }
4194
4195 block_comment("push_call_clobbered_registers end");
4196 }
4197
4198 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
4199 block_comment("pop_call_clobbered_registers start");
4200
4201 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
4202
4203 int gp_area_size;
4204 int fp_area_size;
4205 int xmm_area_size;
4206 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
4207 gp_area_size, fp_area_size, xmm_area_size);
4208
4209 if (restore_fpu && use_xmm_registers()) {
4210 pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4211 }
4212 #ifndef _LP64
4213 if (restore_fpu && use_x87_registers()) {
4214 frstor(Address(rsp, gp_area_size));
4215 }
4216 #endif
4217
4218 pop_set(gp_registers_to_pop, 0);
4219
4220 addptr(rsp, total_save_size);
4221
4222 vzeroupper();
4223
4224 block_comment("pop_call_clobbered_registers end");
4225 }
4226
4227 void MacroAssembler::push_set(XMMRegSet set, int offset) {
4228 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
4229 int spill_offset = offset;
4230
4231 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
4232 save_xmm_register(this, spill_offset, *it);
4233 spill_offset += xmm_save_size();
4234 }
4235 }
4236
4237 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
4238 int restore_size = set.size() * xmm_save_size();
4239 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
4240
4241 int restore_offset = offset + restore_size - xmm_save_size();
4242
4243 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
4244 restore_xmm_register(this, restore_offset, *it);
4245 restore_offset -= xmm_save_size();
4246 }
4247 }
4248
4249 void MacroAssembler::push_set(RegSet set, int offset) {
4250 int spill_offset;
4251 if (offset == -1) {
4252 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4253 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4254 subptr(rsp, aligned_size);
4255 spill_offset = 0;
4256 } else {
4257 spill_offset = offset;
4258 }
4259
4260 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
4261 movptr(Address(rsp, spill_offset), *it);
4262 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4263 }
4264 }
4265
4266 void MacroAssembler::pop_set(RegSet set, int offset) {
4267
4268 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4269 int restore_size = set.size() * gp_reg_size;
4270 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
4271
4272 int restore_offset;
4273 if (offset == -1) {
4274 restore_offset = restore_size - gp_reg_size;
4275 } else {
4276 restore_offset = offset + restore_size - gp_reg_size;
4277 }
4278 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
4279 movptr(*it, Address(rsp, restore_offset));
4280 restore_offset -= gp_reg_size;
4281 }
4282
4283 if (offset == -1) {
4284 addptr(rsp, aligned_size);
4285 }
4286 }
4287
4288 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4289 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4290 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4291 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4292 Label done;
4293
4294 testptr(length_in_bytes, length_in_bytes);
4295 jcc(Assembler::zero, done);
4296
4297 // initialize topmost word, divide index by 2, check if odd and test if zero
4298 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4299 #ifdef ASSERT
4300 {
4301 Label L;
4302 testptr(length_in_bytes, BytesPerWord - 1);
4303 jcc(Assembler::zero, L);
4304 stop("length must be a multiple of BytesPerWord");
4305 bind(L);
4306 }
4307 #endif
4308 Register index = length_in_bytes;
4309 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4310 if (UseIncDec) {
4311 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4312 } else {
4313 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4314 shrptr(index, 1);
4315 }
4316 #ifndef _LP64
4317 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4318 {
4319 Label even;
4320 // note: if index was a multiple of 8, then it cannot
4321 // be 0 now otherwise it must have been 0 before
4322 // => if it is even, we don't need to check for 0 again
4323 jcc(Assembler::carryClear, even);
4324 // clear topmost word (no jump would be needed if conditional assignment worked here)
4325 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4326 // index could be 0 now, must check again
4327 jcc(Assembler::zero, done);
4328 bind(even);
4329 }
4330 #endif // !_LP64
4331 // initialize remaining object fields: index is a multiple of 2 now
4332 {
4333 Label loop;
4334 bind(loop);
4335 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4336 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4337 decrement(index);
4338 jcc(Assembler::notZero, loop);
4339 }
4340
4341 bind(done);
4342 }
4343
4344 // Look up the method for a megamorphic invokeinterface call.
4345 // The target method is determined by <intf_klass, itable_index>.
4346 // The receiver klass is in recv_klass.
4347 // On success, the result will be in method_result, and execution falls through.
4348 // On failure, execution transfers to the given label.
4349 void MacroAssembler::lookup_interface_method(Register recv_klass,
4350 Register intf_klass,
4351 RegisterOrConstant itable_index,
4352 Register method_result,
4353 Register scan_temp,
4354 Label& L_no_such_interface,
4355 bool return_method) {
4356 assert_different_registers(recv_klass, intf_klass, scan_temp);
4357 assert_different_registers(method_result, intf_klass, scan_temp);
4358 assert(recv_klass != method_result || !return_method,
4359 "recv_klass can be destroyed when method isn't needed");
4360
4361 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4362 "caller must use same register for non-constant itable index as for method");
4363
4364 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4365 int vtable_base = in_bytes(Klass::vtable_start_offset());
4366 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4367 int scan_step = itableOffsetEntry::size() * wordSize;
4368 int vte_size = vtableEntry::size_in_bytes();
4369 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4370 assert(vte_size == wordSize, "else adjust times_vte_scale");
4371
4372 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4373
4374 // Could store the aligned, prescaled offset in the klass.
4375 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4376
4377 if (return_method) {
4378 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4379 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4380 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4381 }
4382
4383 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
4384 // if (scan->interface() == intf) {
4385 // result = (klass + scan->offset() + itable_index);
4386 // }
4387 // }
4388 Label search, found_method;
4389
4390 for (int peel = 1; peel >= 0; peel--) {
4391 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
4392 cmpptr(intf_klass, method_result);
4393
4394 if (peel) {
4395 jccb(Assembler::equal, found_method);
4396 } else {
4397 jccb(Assembler::notEqual, search);
4398 // (invert the test to fall through to found_method...)
4399 }
4400
4401 if (!peel) break;
4402
4403 bind(search);
4404
4405 // Check that the previous entry is non-null. A null entry means that
4406 // the receiver class doesn't implement the interface, and wasn't the
4407 // same as when the caller was compiled.
4408 testptr(method_result, method_result);
4409 jcc(Assembler::zero, L_no_such_interface);
4410 addptr(scan_temp, scan_step);
4411 }
4412
4413 bind(found_method);
4414
4415 if (return_method) {
4416 // Got a hit.
4417 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
4418 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4419 }
4420 }
4421
4422 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
4423 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
4424 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
4425 // The target method is determined by <holder_klass, itable_index>.
4426 // The receiver klass is in recv_klass.
4427 // On success, the result will be in method_result, and execution falls through.
4428 // On failure, execution transfers to the given label.
4429 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
4430 Register holder_klass,
4431 Register resolved_klass,
4432 Register method_result,
4433 Register scan_temp,
4434 Register temp_reg2,
4435 Register receiver,
4436 int itable_index,
4437 Label& L_no_such_interface) {
4438 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
4439 Register temp_itbl_klass = method_result;
4440 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
4441
4442 int vtable_base = in_bytes(Klass::vtable_start_offset());
4443 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4444 int scan_step = itableOffsetEntry::size() * wordSize;
4445 int vte_size = vtableEntry::size_in_bytes();
4446 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
4447 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
4448 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4449 assert(vte_size == wordSize, "adjust times_vte_scale");
4450
4451 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
4452
4453 // temp_itbl_klass = recv_klass.itable[0]
4454 // scan_temp = &recv_klass.itable[0] + step
4455 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4456 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
4457 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
4458 xorptr(temp_reg, temp_reg);
4459
4460 // Initial checks:
4461 // - if (holder_klass != resolved_klass), go to "scan for resolved"
4462 // - if (itable[0] == 0), no such interface
4463 // - if (itable[0] == holder_klass), shortcut to "holder found"
4464 cmpptr(holder_klass, resolved_klass);
4465 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
4466 testptr(temp_itbl_klass, temp_itbl_klass);
4467 jccb(Assembler::zero, L_no_such_interface);
4468 cmpptr(holder_klass, temp_itbl_klass);
4469 jccb(Assembler::equal, L_holder_found);
4470
4471 // Loop: Look for holder_klass record in itable
4472 // do {
4473 // tmp = itable[index];
4474 // index += step;
4475 // if (tmp == holder_klass) {
4476 // goto L_holder_found; // Found!
4477 // }
4478 // } while (tmp != 0);
4479 // goto L_no_such_interface // Not found.
4480 Label L_scan_holder;
4481 bind(L_scan_holder);
4482 movptr(temp_itbl_klass, Address(scan_temp, 0));
4483 addptr(scan_temp, scan_step);
4484 cmpptr(holder_klass, temp_itbl_klass);
4485 jccb(Assembler::equal, L_holder_found);
4486 testptr(temp_itbl_klass, temp_itbl_klass);
4487 jccb(Assembler::notZero, L_scan_holder);
4488
4489 jmpb(L_no_such_interface);
4490
4491 // Loop: Look for resolved_class record in itable
4492 // do {
4493 // tmp = itable[index];
4494 // index += step;
4495 // if (tmp == holder_klass) {
4496 // // Also check if we have met a holder klass
4497 // holder_tmp = itable[index-step-ioffset];
4498 // }
4499 // if (tmp == resolved_klass) {
4500 // goto L_resolved_found; // Found!
4501 // }
4502 // } while (tmp != 0);
4503 // goto L_no_such_interface // Not found.
4504 //
4505 Label L_loop_scan_resolved;
4506 bind(L_loop_scan_resolved);
4507 movptr(temp_itbl_klass, Address(scan_temp, 0));
4508 addptr(scan_temp, scan_step);
4509 bind(L_loop_scan_resolved_entry);
4510 cmpptr(holder_klass, temp_itbl_klass);
4511 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4512 cmpptr(resolved_klass, temp_itbl_klass);
4513 jccb(Assembler::equal, L_resolved_found);
4514 testptr(temp_itbl_klass, temp_itbl_klass);
4515 jccb(Assembler::notZero, L_loop_scan_resolved);
4516
4517 jmpb(L_no_such_interface);
4518
4519 Label L_ready;
4520
4521 // See if we already have a holder klass. If not, go and scan for it.
4522 bind(L_resolved_found);
4523 testptr(temp_reg, temp_reg);
4524 jccb(Assembler::zero, L_scan_holder);
4525 jmpb(L_ready);
4526
4527 bind(L_holder_found);
4528 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4529
4530 // Finally, temp_reg contains holder_klass vtable offset
4531 bind(L_ready);
4532 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4533 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4534 load_klass(scan_temp, receiver, noreg);
4535 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4536 } else {
4537 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4538 }
4539 }
4540
4541
4542 // virtual method calling
4543 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4544 RegisterOrConstant vtable_index,
4545 Register method_result) {
4546 const ByteSize base = Klass::vtable_start_offset();
4547 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4548 Address vtable_entry_addr(recv_klass,
4549 vtable_index, Address::times_ptr,
4550 base + vtableEntry::method_offset());
4551 movptr(method_result, vtable_entry_addr);
4552 }
4553
4554
4555 void MacroAssembler::check_klass_subtype(Register sub_klass,
4556 Register super_klass,
4557 Register temp_reg,
4558 Label& L_success) {
4559 Label L_failure;
4560 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4561 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4562 bind(L_failure);
4563 }
4564
4565
4566 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4567 Register super_klass,
4568 Register temp_reg,
4569 Label* L_success,
4570 Label* L_failure,
4571 Label* L_slow_path,
4572 RegisterOrConstant super_check_offset) {
4573 assert_different_registers(sub_klass, super_klass, temp_reg);
4574 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4575 if (super_check_offset.is_register()) {
4576 assert_different_registers(sub_klass, super_klass,
4577 super_check_offset.as_register());
4578 } else if (must_load_sco) {
4579 assert(temp_reg != noreg, "supply either a temp or a register offset");
4580 }
4581
4582 Label L_fallthrough;
4583 int label_nulls = 0;
4584 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4585 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4586 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4587 assert(label_nulls <= 1, "at most one null in the batch");
4588
4589 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4590 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4591 Address super_check_offset_addr(super_klass, sco_offset);
4592
4593 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4594 // range of a jccb. If this routine grows larger, reconsider at
4595 // least some of these.
4596 #define local_jcc(assembler_cond, label) \
4597 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4598 else jcc( assembler_cond, label) /*omit semi*/
4599
4600 // Hacked jmp, which may only be used just before L_fallthrough.
4601 #define final_jmp(label) \
4602 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4603 else jmp(label) /*omit semi*/
4604
4605 // If the pointers are equal, we are done (e.g., String[] elements).
4606 // This self-check enables sharing of secondary supertype arrays among
4607 // non-primary types such as array-of-interface. Otherwise, each such
4608 // type would need its own customized SSA.
4609 // We move this check to the front of the fast path because many
4610 // type checks are in fact trivially successful in this manner,
4611 // so we get a nicely predicted branch right at the start of the check.
4612 cmpptr(sub_klass, super_klass);
4613 local_jcc(Assembler::equal, *L_success);
4614
4615 // Check the supertype display:
4616 if (must_load_sco) {
4617 // Positive movl does right thing on LP64.
4618 movl(temp_reg, super_check_offset_addr);
4619 super_check_offset = RegisterOrConstant(temp_reg);
4620 }
4621 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4622 cmpptr(super_klass, super_check_addr); // load displayed supertype
4623
4624 // This check has worked decisively for primary supers.
4625 // Secondary supers are sought in the super_cache ('super_cache_addr').
4626 // (Secondary supers are interfaces and very deeply nested subtypes.)
4627 // This works in the same check above because of a tricky aliasing
4628 // between the super_cache and the primary super display elements.
4629 // (The 'super_check_addr' can address either, as the case requires.)
4630 // Note that the cache is updated below if it does not help us find
4631 // what we need immediately.
4632 // So if it was a primary super, we can just fail immediately.
4633 // Otherwise, it's the slow path for us (no success at this point).
4634
4635 if (super_check_offset.is_register()) {
4636 local_jcc(Assembler::equal, *L_success);
4637 cmpl(super_check_offset.as_register(), sc_offset);
4638 if (L_failure == &L_fallthrough) {
4639 local_jcc(Assembler::equal, *L_slow_path);
4640 } else {
4641 local_jcc(Assembler::notEqual, *L_failure);
4642 final_jmp(*L_slow_path);
4643 }
4644 } else if (super_check_offset.as_constant() == sc_offset) {
4645 // Need a slow path; fast failure is impossible.
4646 if (L_slow_path == &L_fallthrough) {
4647 local_jcc(Assembler::equal, *L_success);
4648 } else {
4649 local_jcc(Assembler::notEqual, *L_slow_path);
4650 final_jmp(*L_success);
4651 }
4652 } else {
4653 // No slow path; it's a fast decision.
4654 if (L_failure == &L_fallthrough) {
4655 local_jcc(Assembler::equal, *L_success);
4656 } else {
4657 local_jcc(Assembler::notEqual, *L_failure);
4658 final_jmp(*L_success);
4659 }
4660 }
4661
4662 bind(L_fallthrough);
4663
4664 #undef local_jcc
4665 #undef final_jmp
4666 }
4667
4668
4669 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4670 Register super_klass,
4671 Register temp_reg,
4672 Register temp2_reg,
4673 Label* L_success,
4674 Label* L_failure,
4675 bool set_cond_codes) {
4676 assert_different_registers(sub_klass, super_klass, temp_reg);
4677 if (temp2_reg != noreg)
4678 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4679 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4680
4681 Label L_fallthrough;
4682 int label_nulls = 0;
4683 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4684 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4685 assert(label_nulls <= 1, "at most one null in the batch");
4686
4687 // a couple of useful fields in sub_klass:
4688 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4689 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4690 Address secondary_supers_addr(sub_klass, ss_offset);
4691 Address super_cache_addr( sub_klass, sc_offset);
4692
4693 // Do a linear scan of the secondary super-klass chain.
4694 // This code is rarely used, so simplicity is a virtue here.
4695 // The repne_scan instruction uses fixed registers, which we must spill.
4696 // Don't worry too much about pre-existing connections with the input regs.
4697
4698 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4699 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4700
4701 // Get super_klass value into rax (even if it was in rdi or rcx).
4702 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4703 if (super_klass != rax) {
4704 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4705 mov(rax, super_klass);
4706 }
4707 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4708 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4709
4710 #ifndef PRODUCT
4711 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4712 ExternalAddress pst_counter_addr((address) pst_counter);
4713 NOT_LP64( incrementl(pst_counter_addr) );
4714 LP64_ONLY( lea(rcx, pst_counter_addr) );
4715 LP64_ONLY( incrementl(Address(rcx, 0)) );
4716 #endif //PRODUCT
4717
4718 // We will consult the secondary-super array.
4719 movptr(rdi, secondary_supers_addr);
4720 // Load the array length. (Positive movl does right thing on LP64.)
4721 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4722 // Skip to start of data.
4723 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4724
4725 // Scan RCX words at [RDI] for an occurrence of RAX.
4726 // Set NZ/Z based on last compare.
4727 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4728 // not change flags (only scas instruction which is repeated sets flags).
4729 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4730
4731 testptr(rax,rax); // Set Z = 0
4732 repne_scan();
4733
4734 // Unspill the temp. registers:
4735 if (pushed_rdi) pop(rdi);
4736 if (pushed_rcx) pop(rcx);
4737 if (pushed_rax) pop(rax);
4738
4739 if (set_cond_codes) {
4740 // Special hack for the AD files: rdi is guaranteed non-zero.
4741 assert(!pushed_rdi, "rdi must be left non-null");
4742 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4743 }
4744
4745 if (L_failure == &L_fallthrough)
4746 jccb(Assembler::notEqual, *L_failure);
4747 else jcc(Assembler::notEqual, *L_failure);
4748
4749 // Success. Cache the super we found and proceed in triumph.
4750 movptr(super_cache_addr, super_klass);
4751
4752 if (L_success != &L_fallthrough) {
4753 jmp(*L_success);
4754 }
4755
4756 #undef IS_A_TEMP
4757
4758 bind(L_fallthrough);
4759 }
4760
4761 #ifndef _LP64
4762
4763 // 32-bit x86 only: always use the linear search.
4764 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4765 Register super_klass,
4766 Register temp_reg,
4767 Register temp2_reg,
4768 Label* L_success,
4769 Label* L_failure,
4770 bool set_cond_codes) {
4771 check_klass_subtype_slow_path_linear
4772 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
4773 }
4774
4775 #else // _LP64
4776
4777 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4778 Register super_klass,
4779 Register temp_reg,
4780 Register temp2_reg,
4781 Label* L_success,
4782 Label* L_failure,
4783 bool set_cond_codes) {
4784 assert(set_cond_codes == false, "must be false on 64-bit x86");
4785 check_klass_subtype_slow_path
4786 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4787 L_success, L_failure);
4788 }
4789
4790 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4791 Register super_klass,
4792 Register temp_reg,
4793 Register temp2_reg,
4794 Register temp3_reg,
4795 Register temp4_reg,
4796 Label* L_success,
4797 Label* L_failure) {
4798 if (UseSecondarySupersTable) {
4799 check_klass_subtype_slow_path_table
4800 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4801 L_success, L_failure);
4802 } else {
4803 check_klass_subtype_slow_path_linear
4804 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4805 }
4806 }
4807
4808 Register MacroAssembler::allocate_if_noreg(Register r,
4809 RegSetIterator<Register> &available_regs,
4810 RegSet ®s_to_push) {
4811 if (!r->is_valid()) {
4812 r = *available_regs++;
4813 regs_to_push += r;
4814 }
4815 return r;
4816 }
4817
4818 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4819 Register super_klass,
4820 Register temp_reg,
4821 Register temp2_reg,
4822 Register temp3_reg,
4823 Register result_reg,
4824 Label* L_success,
4825 Label* L_failure) {
4826 // NB! Callers may assume that, when temp2_reg is a valid register,
4827 // this code sets it to a nonzero value.
4828 bool temp2_reg_was_valid = temp2_reg->is_valid();
4829
4830 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4831
4832 Label L_fallthrough;
4833 int label_nulls = 0;
4834 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4835 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4836 assert(label_nulls <= 1, "at most one null in the batch");
4837
4838 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4839
4840 RegSetIterator<Register> available_regs
4841 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4842
4843 RegSet pushed_regs;
4844
4845 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4846 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4847 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4848 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4849 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4850
4851 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4852
4853 {
4854
4855 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4856 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4857 subptr(rsp, aligned_size);
4858 push_set(pushed_regs, 0);
4859
4860 lookup_secondary_supers_table_var(sub_klass,
4861 super_klass,
4862 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4863 cmpq(result_reg, 0);
4864
4865 // Unspill the temp. registers:
4866 pop_set(pushed_regs, 0);
4867 // Increment SP but do not clobber flags.
4868 lea(rsp, Address(rsp, aligned_size));
4869 }
4870
4871 if (temp2_reg_was_valid) {
4872 movq(temp2_reg, 1);
4873 }
4874
4875 jcc(Assembler::notEqual, *L_failure);
4876
4877 if (L_success != &L_fallthrough) {
4878 jmp(*L_success);
4879 }
4880
4881 bind(L_fallthrough);
4882 }
4883
4884 // population_count variant for running without the POPCNT
4885 // instruction, which was introduced with SSE4.2 in 2008.
4886 void MacroAssembler::population_count(Register dst, Register src,
4887 Register scratch1, Register scratch2) {
4888 assert_different_registers(src, scratch1, scratch2);
4889 if (UsePopCountInstruction) {
4890 Assembler::popcntq(dst, src);
4891 } else {
4892 assert_different_registers(src, scratch1, scratch2);
4893 assert_different_registers(dst, scratch1, scratch2);
4894 Label loop, done;
4895
4896 mov(scratch1, src);
4897 // dst = 0;
4898 // while(scratch1 != 0) {
4899 // dst++;
4900 // scratch1 &= (scratch1 - 1);
4901 // }
4902 xorl(dst, dst);
4903 testq(scratch1, scratch1);
4904 jccb(Assembler::equal, done);
4905 {
4906 bind(loop);
4907 incq(dst);
4908 movq(scratch2, scratch1);
4909 decq(scratch2);
4910 andq(scratch1, scratch2);
4911 jccb(Assembler::notEqual, loop);
4912 }
4913 bind(done);
4914 }
4915 }
4916
4917 // Ensure that the inline code and the stub are using the same registers.
4918 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4919 do { \
4920 assert(r_super_klass == rax, "mismatch"); \
4921 assert(r_array_base == rbx, "mismatch"); \
4922 assert(r_array_length == rcx, "mismatch"); \
4923 assert(r_array_index == rdx, "mismatch"); \
4924 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4925 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4926 assert(result == rdi || result == noreg, "mismatch"); \
4927 } while(0)
4928
4929 // Versions of salq and rorq that don't need count to be in rcx
4930
4931 void MacroAssembler::salq(Register dest, Register count) {
4932 if (count == rcx) {
4933 Assembler::salq(dest);
4934 } else {
4935 assert_different_registers(rcx, dest);
4936 xchgq(rcx, count);
4937 Assembler::salq(dest);
4938 xchgq(rcx, count);
4939 }
4940 }
4941
4942 void MacroAssembler::rorq(Register dest, Register count) {
4943 if (count == rcx) {
4944 Assembler::rorq(dest);
4945 } else {
4946 assert_different_registers(rcx, dest);
4947 xchgq(rcx, count);
4948 Assembler::rorq(dest);
4949 xchgq(rcx, count);
4950 }
4951 }
4952
4953 // Return true: we succeeded in generating this code
4954 //
4955 // At runtime, return 0 in result if r_super_klass is a superclass of
4956 // r_sub_klass, otherwise return nonzero. Use this if you know the
4957 // super_klass_slot of the class you're looking for. This is always
4958 // the case for instanceof and checkcast.
4959 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4960 Register r_super_klass,
4961 Register temp1,
4962 Register temp2,
4963 Register temp3,
4964 Register temp4,
4965 Register result,
4966 u1 super_klass_slot) {
4967 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4968
4969 Label L_fallthrough, L_success, L_failure;
4970
4971 BLOCK_COMMENT("lookup_secondary_supers_table {");
4972
4973 const Register
4974 r_array_index = temp1,
4975 r_array_length = temp2,
4976 r_array_base = temp3,
4977 r_bitmap = temp4;
4978
4979 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4980
4981 xorq(result, result); // = 0
4982
4983 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4984 movq(r_array_index, r_bitmap);
4985
4986 // First check the bitmap to see if super_klass might be present. If
4987 // the bit is zero, we are certain that super_klass is not one of
4988 // the secondary supers.
4989 u1 bit = super_klass_slot;
4990 {
4991 // NB: If the count in a x86 shift instruction is 0, the flags are
4992 // not affected, so we do a testq instead.
4993 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4994 if (shift_count != 0) {
4995 salq(r_array_index, shift_count);
4996 } else {
4997 testq(r_array_index, r_array_index);
4998 }
4999 }
5000 // We test the MSB of r_array_index, i.e. its sign bit
5001 jcc(Assembler::positive, L_failure);
5002
5003 // Get the first array index that can contain super_klass into r_array_index.
5004 if (bit != 0) {
5005 population_count(r_array_index, r_array_index, temp2, temp3);
5006 } else {
5007 movl(r_array_index, 1);
5008 }
5009 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5010
5011 // We will consult the secondary-super array.
5012 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5013
5014 // We're asserting that the first word in an Array<Klass*> is the
5015 // length, and the second word is the first word of the data. If
5016 // that ever changes, r_array_base will have to be adjusted here.
5017 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5018 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5019
5020 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5021 jccb(Assembler::equal, L_success);
5022
5023 // Is there another entry to check? Consult the bitmap.
5024 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
5025 jccb(Assembler::carryClear, L_failure);
5026
5027 // Linear probe. Rotate the bitmap so that the next bit to test is
5028 // in Bit 1.
5029 if (bit != 0) {
5030 rorq(r_bitmap, bit);
5031 }
5032
5033 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5034 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5035 // Kills: r_array_length.
5036 // Returns: result.
5037 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
5038 // Result (0/1) is in rdi
5039 jmpb(L_fallthrough);
5040
5041 bind(L_failure);
5042 incq(result); // 0 => 1
5043
5044 bind(L_success);
5045 // result = 0;
5046
5047 bind(L_fallthrough);
5048 BLOCK_COMMENT("} lookup_secondary_supers_table");
5049
5050 if (VerifySecondarySupers) {
5051 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5052 temp1, temp2, temp3);
5053 }
5054 }
5055
5056 // At runtime, return 0 in result if r_super_klass is a superclass of
5057 // r_sub_klass, otherwise return nonzero. Use this version of
5058 // lookup_secondary_supers_table() if you don't know ahead of time
5059 // which superclass will be searched for. Used by interpreter and
5060 // runtime stubs. It is larger and has somewhat greater latency than
5061 // the version above, which takes a constant super_klass_slot.
5062 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
5063 Register r_super_klass,
5064 Register temp1,
5065 Register temp2,
5066 Register temp3,
5067 Register temp4,
5068 Register result) {
5069 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
5070 assert_different_registers(r_sub_klass, r_super_klass, rcx);
5071 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
5072
5073 Label L_fallthrough, L_success, L_failure;
5074
5075 BLOCK_COMMENT("lookup_secondary_supers_table {");
5076
5077 RegSetIterator<Register> available_regs = (temps - rcx).begin();
5078
5079 // FIXME. Once we are sure that all paths reaching this point really
5080 // do pass rcx as one of our temps we can get rid of the following
5081 // workaround.
5082 assert(temps.contains(rcx), "fix this code");
5083
5084 // We prefer to have our shift count in rcx. If rcx is one of our
5085 // temps, use it for slot. If not, pick any of our temps.
5086 Register slot;
5087 if (!temps.contains(rcx)) {
5088 slot = *available_regs++;
5089 } else {
5090 slot = rcx;
5091 }
5092
5093 const Register r_array_index = *available_regs++;
5094 const Register r_bitmap = *available_regs++;
5095
5096 // The logic above guarantees this property, but we state it here.
5097 assert_different_registers(r_array_index, r_bitmap, rcx);
5098
5099 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
5100 movq(r_array_index, r_bitmap);
5101
5102 // First check the bitmap to see if super_klass might be present. If
5103 // the bit is zero, we are certain that super_klass is not one of
5104 // the secondary supers.
5105 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
5106 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
5107 salq(r_array_index, slot);
5108
5109 testq(r_array_index, r_array_index);
5110 // We test the MSB of r_array_index, i.e. its sign bit
5111 jcc(Assembler::positive, L_failure);
5112
5113 const Register r_array_base = *available_regs++;
5114
5115 // Get the first array index that can contain super_klass into r_array_index.
5116 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
5117
5118 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5119
5120 // We will consult the secondary-super array.
5121 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5122
5123 // We're asserting that the first word in an Array<Klass*> is the
5124 // length, and the second word is the first word of the data. If
5125 // that ever changes, r_array_base will have to be adjusted here.
5126 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5127 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5128
5129 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5130 jccb(Assembler::equal, L_success);
5131
5132 // Restore slot to its true value
5133 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
5134
5135 // Linear probe. Rotate the bitmap so that the next bit to test is
5136 // in Bit 1.
5137 rorq(r_bitmap, slot);
5138
5139 // Is there another entry to check? Consult the bitmap.
5140 btq(r_bitmap, 1);
5141 jccb(Assembler::carryClear, L_failure);
5142
5143 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5144 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5145 // Kills: r_array_length.
5146 // Returns: result.
5147 lookup_secondary_supers_table_slow_path(r_super_klass,
5148 r_array_base,
5149 r_array_index,
5150 r_bitmap,
5151 /*temp1*/result,
5152 /*temp2*/slot,
5153 &L_success,
5154 nullptr);
5155
5156 bind(L_failure);
5157 movq(result, 1);
5158 jmpb(L_fallthrough);
5159
5160 bind(L_success);
5161 xorq(result, result); // = 0
5162
5163 bind(L_fallthrough);
5164 BLOCK_COMMENT("} lookup_secondary_supers_table");
5165
5166 if (VerifySecondarySupers) {
5167 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5168 temp1, temp2, temp3);
5169 }
5170 }
5171
5172 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
5173 Label* L_success, Label* L_failure) {
5174 Label L_loop, L_fallthrough;
5175 {
5176 int label_nulls = 0;
5177 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5178 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5179 assert(label_nulls <= 1, "at most one null in the batch");
5180 }
5181 bind(L_loop);
5182 cmpq(value, Address(addr, count, Address::times_8));
5183 jcc(Assembler::equal, *L_success);
5184 addl(count, 1);
5185 cmpl(count, limit);
5186 jcc(Assembler::less, L_loop);
5187
5188 if (&L_fallthrough != L_failure) {
5189 jmp(*L_failure);
5190 }
5191 bind(L_fallthrough);
5192 }
5193
5194 // Called by code generated by check_klass_subtype_slow_path
5195 // above. This is called when there is a collision in the hashed
5196 // lookup in the secondary supers array.
5197 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
5198 Register r_array_base,
5199 Register r_array_index,
5200 Register r_bitmap,
5201 Register temp1,
5202 Register temp2,
5203 Label* L_success,
5204 Label* L_failure) {
5205 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
5206
5207 const Register
5208 r_array_length = temp1,
5209 r_sub_klass = noreg,
5210 result = noreg;
5211
5212 Label L_fallthrough;
5213 int label_nulls = 0;
5214 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5215 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5216 assert(label_nulls <= 1, "at most one null in the batch");
5217
5218 // Load the array length.
5219 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5220 // And adjust the array base to point to the data.
5221 // NB! Effectively increments current slot index by 1.
5222 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
5223 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5224
5225 // Linear probe
5226 Label L_huge;
5227
5228 // The bitmap is full to bursting.
5229 // Implicit invariant: BITMAP_FULL implies (length > 0)
5230 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
5231 jcc(Assembler::greater, L_huge);
5232
5233 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
5234 // current slot (at secondary_supers[r_array_index]) has not yet
5235 // been inspected, and r_array_index may be out of bounds if we
5236 // wrapped around the end of the array.
5237
5238 { // This is conventional linear probing, but instead of terminating
5239 // when a null entry is found in the table, we maintain a bitmap
5240 // in which a 0 indicates missing entries.
5241 // The check above guarantees there are 0s in the bitmap, so the loop
5242 // eventually terminates.
5243
5244 xorl(temp2, temp2); // = 0;
5245
5246 Label L_again;
5247 bind(L_again);
5248
5249 // Check for array wraparound.
5250 cmpl(r_array_index, r_array_length);
5251 cmovl(Assembler::greaterEqual, r_array_index, temp2);
5252
5253 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5254 jcc(Assembler::equal, *L_success);
5255
5256 // If the next bit in bitmap is zero, we're done.
5257 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
5258 jcc(Assembler::carryClear, *L_failure);
5259
5260 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
5261 addl(r_array_index, 1);
5262
5263 jmp(L_again);
5264 }
5265
5266 { // Degenerate case: more than 64 secondary supers.
5267 // FIXME: We could do something smarter here, maybe a vectorized
5268 // comparison or a binary search, but is that worth any added
5269 // complexity?
5270 bind(L_huge);
5271 xorl(r_array_index, r_array_index); // = 0
5272 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
5273 L_success,
5274 (&L_fallthrough != L_failure ? L_failure : nullptr));
5275
5276 bind(L_fallthrough);
5277 }
5278 }
5279
5280 struct VerifyHelperArguments {
5281 Klass* _super;
5282 Klass* _sub;
5283 intptr_t _linear_result;
5284 intptr_t _table_result;
5285 };
5286
5287 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
5288 Klass::on_secondary_supers_verification_failure(args->_super,
5289 args->_sub,
5290 args->_linear_result,
5291 args->_table_result,
5292 msg);
5293 }
5294
5295 // Make sure that the hashed lookup and a linear scan agree.
5296 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
5297 Register r_super_klass,
5298 Register result,
5299 Register temp1,
5300 Register temp2,
5301 Register temp3) {
5302 const Register
5303 r_array_index = temp1,
5304 r_array_length = temp2,
5305 r_array_base = temp3,
5306 r_bitmap = noreg;
5307
5308 BLOCK_COMMENT("verify_secondary_supers_table {");
5309
5310 Label L_success, L_failure, L_check, L_done;
5311
5312 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5313 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5314 // And adjust the array base to point to the data.
5315 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5316
5317 testl(r_array_length, r_array_length); // array_length == 0?
5318 jcc(Assembler::zero, L_failure);
5319
5320 movl(r_array_index, 0);
5321 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
5322 // fall through to L_failure
5323
5324 const Register linear_result = r_array_index; // reuse temp1
5325
5326 bind(L_failure); // not present
5327 movl(linear_result, 1);
5328 jmp(L_check);
5329
5330 bind(L_success); // present
5331 movl(linear_result, 0);
5332
5333 bind(L_check);
5334 cmpl(linear_result, result);
5335 jcc(Assembler::equal, L_done);
5336
5337 { // To avoid calling convention issues, build a record on the stack
5338 // and pass the pointer to that instead.
5339 push(result);
5340 push(linear_result);
5341 push(r_sub_klass);
5342 push(r_super_klass);
5343 movptr(c_rarg1, rsp);
5344 movptr(c_rarg0, (uintptr_t) "mismatch");
5345 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
5346 should_not_reach_here();
5347 }
5348 bind(L_done);
5349
5350 BLOCK_COMMENT("} verify_secondary_supers_table");
5351 }
5352
5353 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
5354
5355 #endif // LP64
5356
5357 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
5358 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
5359
5360 Label L_fallthrough;
5361 if (L_fast_path == nullptr) {
5362 L_fast_path = &L_fallthrough;
5363 } else if (L_slow_path == nullptr) {
5364 L_slow_path = &L_fallthrough;
5365 }
5366
5367 // Fast path check: class is fully initialized.
5368 // init_state needs acquire, but x86 is TSO, and so we are already good.
5369 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
5370 jcc(Assembler::equal, *L_fast_path);
5371
5372 // Fast path check: current thread is initializer thread
5373 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
5374 if (L_slow_path == &L_fallthrough) {
5375 jcc(Assembler::equal, *L_fast_path);
5376 bind(*L_slow_path);
5377 } else if (L_fast_path == &L_fallthrough) {
5378 jcc(Assembler::notEqual, *L_slow_path);
5379 bind(*L_fast_path);
5380 } else {
5381 Unimplemented();
5382 }
5383 }
5384
5385 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5386 if (VM_Version::supports_cmov()) {
5387 cmovl(cc, dst, src);
5388 } else {
5389 Label L;
5390 jccb(negate_condition(cc), L);
5391 movl(dst, src);
5392 bind(L);
5393 }
5394 }
5395
5396 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5397 if (VM_Version::supports_cmov()) {
5398 cmovl(cc, dst, src);
5399 } else {
5400 Label L;
5401 jccb(negate_condition(cc), L);
5402 movl(dst, src);
5403 bind(L);
5404 }
5405 }
5406
5407 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
5408 if (!VerifyOops) return;
5409
5410 BLOCK_COMMENT("verify_oop {");
5411 #ifdef _LP64
5412 push(rscratch1);
5413 #endif
5414 push(rax); // save rax
5415 push(reg); // pass register argument
5416
5417 // Pass register number to verify_oop_subroutine
5418 const char* b = nullptr;
5419 {
5420 ResourceMark rm;
5421 stringStream ss;
5422 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5423 b = code_string(ss.as_string());
5424 }
5425 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5426 pushptr(buffer.addr(), rscratch1);
5427
5428 // call indirectly to solve generation ordering problem
5429 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5430 call(rax);
5431 // Caller pops the arguments (oop, message) and restores rax, r10
5432 BLOCK_COMMENT("} verify_oop");
5433 }
5434
5435 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
5436 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
5437 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
5438 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
5439 vpternlogd(dst, 0xFF, dst, dst, vector_len);
5440 } else if (VM_Version::supports_avx()) {
5441 vpcmpeqd(dst, dst, dst, vector_len);
5442 } else {
5443 assert(VM_Version::supports_sse2(), "");
5444 pcmpeqd(dst, dst);
5445 }
5446 }
5447
5448 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5449 int extra_slot_offset) {
5450 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5451 int stackElementSize = Interpreter::stackElementSize;
5452 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5453 #ifdef ASSERT
5454 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5455 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5456 #endif
5457 Register scale_reg = noreg;
5458 Address::ScaleFactor scale_factor = Address::no_scale;
5459 if (arg_slot.is_constant()) {
5460 offset += arg_slot.as_constant() * stackElementSize;
5461 } else {
5462 scale_reg = arg_slot.as_register();
5463 scale_factor = Address::times(stackElementSize);
5464 }
5465 offset += wordSize; // return PC is on stack
5466 return Address(rsp, scale_reg, scale_factor, offset);
5467 }
5468
5469 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5470 if (!VerifyOops) return;
5471
5472 #ifdef _LP64
5473 push(rscratch1);
5474 #endif
5475 push(rax); // save rax,
5476 // addr may contain rsp so we will have to adjust it based on the push
5477 // we just did (and on 64 bit we do two pushes)
5478 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5479 // stores rax into addr which is backwards of what was intended.
5480 if (addr.uses(rsp)) {
5481 lea(rax, addr);
5482 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5483 } else {
5484 pushptr(addr);
5485 }
5486
5487 // Pass register number to verify_oop_subroutine
5488 const char* b = nullptr;
5489 {
5490 ResourceMark rm;
5491 stringStream ss;
5492 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5493 b = code_string(ss.as_string());
5494 }
5495 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5496 pushptr(buffer.addr(), rscratch1);
5497
5498 // call indirectly to solve generation ordering problem
5499 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5500 call(rax);
5501 // Caller pops the arguments (addr, message) and restores rax, r10.
5502 }
5503
5504 void MacroAssembler::verify_tlab() {
5505 #ifdef ASSERT
5506 if (UseTLAB && VerifyOops) {
5507 Label next, ok;
5508 Register t1 = rsi;
5509 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5510
5511 push(t1);
5512 NOT_LP64(push(thread_reg));
5513 NOT_LP64(get_thread(thread_reg));
5514
5515 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5516 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5517 jcc(Assembler::aboveEqual, next);
5518 STOP("assert(top >= start)");
5519 should_not_reach_here();
5520
5521 bind(next);
5522 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5523 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5524 jcc(Assembler::aboveEqual, ok);
5525 STOP("assert(top <= end)");
5526 should_not_reach_here();
5527
5528 bind(ok);
5529 NOT_LP64(pop(thread_reg));
5530 pop(t1);
5531 }
5532 #endif
5533 }
5534
5535 class ControlWord {
5536 public:
5537 int32_t _value;
5538
5539 int rounding_control() const { return (_value >> 10) & 3 ; }
5540 int precision_control() const { return (_value >> 8) & 3 ; }
5541 bool precision() const { return ((_value >> 5) & 1) != 0; }
5542 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5543 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5544 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5545 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5546 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5547
5548 void print() const {
5549 // rounding control
5550 const char* rc;
5551 switch (rounding_control()) {
5552 case 0: rc = "round near"; break;
5553 case 1: rc = "round down"; break;
5554 case 2: rc = "round up "; break;
5555 case 3: rc = "chop "; break;
5556 default:
5557 rc = nullptr; // silence compiler warnings
5558 fatal("Unknown rounding control: %d", rounding_control());
5559 };
5560 // precision control
5561 const char* pc;
5562 switch (precision_control()) {
5563 case 0: pc = "24 bits "; break;
5564 case 1: pc = "reserved"; break;
5565 case 2: pc = "53 bits "; break;
5566 case 3: pc = "64 bits "; break;
5567 default:
5568 pc = nullptr; // silence compiler warnings
5569 fatal("Unknown precision control: %d", precision_control());
5570 };
5571 // flags
5572 char f[9];
5573 f[0] = ' ';
5574 f[1] = ' ';
5575 f[2] = (precision ()) ? 'P' : 'p';
5576 f[3] = (underflow ()) ? 'U' : 'u';
5577 f[4] = (overflow ()) ? 'O' : 'o';
5578 f[5] = (zero_divide ()) ? 'Z' : 'z';
5579 f[6] = (denormalized()) ? 'D' : 'd';
5580 f[7] = (invalid ()) ? 'I' : 'i';
5581 f[8] = '\x0';
5582 // output
5583 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5584 }
5585
5586 };
5587
5588 class StatusWord {
5589 public:
5590 int32_t _value;
5591
5592 bool busy() const { return ((_value >> 15) & 1) != 0; }
5593 bool C3() const { return ((_value >> 14) & 1) != 0; }
5594 bool C2() const { return ((_value >> 10) & 1) != 0; }
5595 bool C1() const { return ((_value >> 9) & 1) != 0; }
5596 bool C0() const { return ((_value >> 8) & 1) != 0; }
5597 int top() const { return (_value >> 11) & 7 ; }
5598 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5599 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5600 bool precision() const { return ((_value >> 5) & 1) != 0; }
5601 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5602 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5603 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5604 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5605 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5606
5607 void print() const {
5608 // condition codes
5609 char c[5];
5610 c[0] = (C3()) ? '3' : '-';
5611 c[1] = (C2()) ? '2' : '-';
5612 c[2] = (C1()) ? '1' : '-';
5613 c[3] = (C0()) ? '0' : '-';
5614 c[4] = '\x0';
5615 // flags
5616 char f[9];
5617 f[0] = (error_status()) ? 'E' : '-';
5618 f[1] = (stack_fault ()) ? 'S' : '-';
5619 f[2] = (precision ()) ? 'P' : '-';
5620 f[3] = (underflow ()) ? 'U' : '-';
5621 f[4] = (overflow ()) ? 'O' : '-';
5622 f[5] = (zero_divide ()) ? 'Z' : '-';
5623 f[6] = (denormalized()) ? 'D' : '-';
5624 f[7] = (invalid ()) ? 'I' : '-';
5625 f[8] = '\x0';
5626 // output
5627 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5628 }
5629
5630 };
5631
5632 class TagWord {
5633 public:
5634 int32_t _value;
5635
5636 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5637
5638 void print() const {
5639 printf("%04x", _value & 0xFFFF);
5640 }
5641
5642 };
5643
5644 class FPU_Register {
5645 public:
5646 int32_t _m0;
5647 int32_t _m1;
5648 int16_t _ex;
5649
5650 bool is_indefinite() const {
5651 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5652 }
5653
5654 void print() const {
5655 char sign = (_ex < 0) ? '-' : '+';
5656 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5657 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5658 };
5659
5660 };
5661
5662 class FPU_State {
5663 public:
5664 enum {
5665 register_size = 10,
5666 number_of_registers = 8,
5667 register_mask = 7
5668 };
5669
5670 ControlWord _control_word;
5671 StatusWord _status_word;
5672 TagWord _tag_word;
5673 int32_t _error_offset;
5674 int32_t _error_selector;
5675 int32_t _data_offset;
5676 int32_t _data_selector;
5677 int8_t _register[register_size * number_of_registers];
5678
5679 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5680 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5681
5682 const char* tag_as_string(int tag) const {
5683 switch (tag) {
5684 case 0: return "valid";
5685 case 1: return "zero";
5686 case 2: return "special";
5687 case 3: return "empty";
5688 }
5689 ShouldNotReachHere();
5690 return nullptr;
5691 }
5692
5693 void print() const {
5694 // print computation registers
5695 { int t = _status_word.top();
5696 for (int i = 0; i < number_of_registers; i++) {
5697 int j = (i - t) & register_mask;
5698 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5699 st(j)->print();
5700 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5701 }
5702 }
5703 printf("\n");
5704 // print control registers
5705 printf("ctrl = "); _control_word.print(); printf("\n");
5706 printf("stat = "); _status_word .print(); printf("\n");
5707 printf("tags = "); _tag_word .print(); printf("\n");
5708 }
5709
5710 };
5711
5712 class Flag_Register {
5713 public:
5714 int32_t _value;
5715
5716 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5717 bool direction() const { return ((_value >> 10) & 1) != 0; }
5718 bool sign() const { return ((_value >> 7) & 1) != 0; }
5719 bool zero() const { return ((_value >> 6) & 1) != 0; }
5720 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5721 bool parity() const { return ((_value >> 2) & 1) != 0; }
5722 bool carry() const { return ((_value >> 0) & 1) != 0; }
5723
5724 void print() const {
5725 // flags
5726 char f[8];
5727 f[0] = (overflow ()) ? 'O' : '-';
5728 f[1] = (direction ()) ? 'D' : '-';
5729 f[2] = (sign ()) ? 'S' : '-';
5730 f[3] = (zero ()) ? 'Z' : '-';
5731 f[4] = (auxiliary_carry()) ? 'A' : '-';
5732 f[5] = (parity ()) ? 'P' : '-';
5733 f[6] = (carry ()) ? 'C' : '-';
5734 f[7] = '\x0';
5735 // output
5736 printf("%08x flags = %s", _value, f);
5737 }
5738
5739 };
5740
5741 class IU_Register {
5742 public:
5743 int32_t _value;
5744
5745 void print() const {
5746 printf("%08x %11d", _value, _value);
5747 }
5748
5749 };
5750
5751 class IU_State {
5752 public:
5753 Flag_Register _eflags;
5754 IU_Register _rdi;
5755 IU_Register _rsi;
5756 IU_Register _rbp;
5757 IU_Register _rsp;
5758 IU_Register _rbx;
5759 IU_Register _rdx;
5760 IU_Register _rcx;
5761 IU_Register _rax;
5762
5763 void print() const {
5764 // computation registers
5765 printf("rax, = "); _rax.print(); printf("\n");
5766 printf("rbx, = "); _rbx.print(); printf("\n");
5767 printf("rcx = "); _rcx.print(); printf("\n");
5768 printf("rdx = "); _rdx.print(); printf("\n");
5769 printf("rdi = "); _rdi.print(); printf("\n");
5770 printf("rsi = "); _rsi.print(); printf("\n");
5771 printf("rbp, = "); _rbp.print(); printf("\n");
5772 printf("rsp = "); _rsp.print(); printf("\n");
5773 printf("\n");
5774 // control registers
5775 printf("flgs = "); _eflags.print(); printf("\n");
5776 }
5777 };
5778
5779
5780 class CPU_State {
5781 public:
5782 FPU_State _fpu_state;
5783 IU_State _iu_state;
5784
5785 void print() const {
5786 printf("--------------------------------------------------\n");
5787 _iu_state .print();
5788 printf("\n");
5789 _fpu_state.print();
5790 printf("--------------------------------------------------\n");
5791 }
5792
5793 };
5794
5795
5796 static void _print_CPU_state(CPU_State* state) {
5797 state->print();
5798 };
5799
5800
5801 void MacroAssembler::print_CPU_state() {
5802 push_CPU_state();
5803 push(rsp); // pass CPU state
5804 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5805 addptr(rsp, wordSize); // discard argument
5806 pop_CPU_state();
5807 }
5808
5809
5810 #ifndef _LP64
5811 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5812 static int counter = 0;
5813 FPU_State* fs = &state->_fpu_state;
5814 counter++;
5815 // For leaf calls, only verify that the top few elements remain empty.
5816 // We only need 1 empty at the top for C2 code.
5817 if( stack_depth < 0 ) {
5818 if( fs->tag_for_st(7) != 3 ) {
5819 printf("FPR7 not empty\n");
5820 state->print();
5821 assert(false, "error");
5822 return false;
5823 }
5824 return true; // All other stack states do not matter
5825 }
5826
5827 assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
5828 "bad FPU control word");
5829
5830 // compute stack depth
5831 int i = 0;
5832 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5833 int d = i;
5834 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5835 // verify findings
5836 if (i != FPU_State::number_of_registers) {
5837 // stack not contiguous
5838 printf("%s: stack not contiguous at ST%d\n", s, i);
5839 state->print();
5840 assert(false, "error");
5841 return false;
5842 }
5843 // check if computed stack depth corresponds to expected stack depth
5844 if (stack_depth < 0) {
5845 // expected stack depth is -stack_depth or less
5846 if (d > -stack_depth) {
5847 // too many elements on the stack
5848 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5849 state->print();
5850 assert(false, "error");
5851 return false;
5852 }
5853 } else {
5854 // expected stack depth is stack_depth
5855 if (d != stack_depth) {
5856 // wrong stack depth
5857 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5858 state->print();
5859 assert(false, "error");
5860 return false;
5861 }
5862 }
5863 // everything is cool
5864 return true;
5865 }
5866
5867 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5868 if (!VerifyFPU) return;
5869 push_CPU_state();
5870 push(rsp); // pass CPU state
5871 ExternalAddress msg((address) s);
5872 // pass message string s
5873 pushptr(msg.addr(), noreg);
5874 push(stack_depth); // pass stack depth
5875 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5876 addptr(rsp, 3 * wordSize); // discard arguments
5877 // check for error
5878 { Label L;
5879 testl(rax, rax);
5880 jcc(Assembler::notZero, L);
5881 int3(); // break if error condition
5882 bind(L);
5883 }
5884 pop_CPU_state();
5885 }
5886 #endif // _LP64
5887
5888 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5889 // Either restore the MXCSR register after returning from the JNI Call
5890 // or verify that it wasn't changed (with -Xcheck:jni flag).
5891 if (VM_Version::supports_sse()) {
5892 if (RestoreMXCSROnJNICalls) {
5893 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5894 } else if (CheckJNICalls) {
5895 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5896 }
5897 }
5898 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5899 vzeroupper();
5900
5901 #ifndef _LP64
5902 // Either restore the x87 floating pointer control word after returning
5903 // from the JNI call or verify that it wasn't changed.
5904 if (CheckJNICalls) {
5905 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5906 }
5907 #endif // _LP64
5908 }
5909
5910 // ((OopHandle)result).resolve();
5911 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5912 assert_different_registers(result, tmp);
5913
5914 // Only 64 bit platforms support GCs that require a tmp register
5915 // Only IN_HEAP loads require a thread_tmp register
5916 // OopHandle::resolve is an indirection like jobject.
5917 access_load_at(T_OBJECT, IN_NATIVE,
5918 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5919 }
5920
5921 // ((WeakHandle)result).resolve();
5922 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5923 assert_different_registers(rresult, rtmp);
5924 Label resolved;
5925
5926 // A null weak handle resolves to null.
5927 cmpptr(rresult, 0);
5928 jcc(Assembler::equal, resolved);
5929
5930 // Only 64 bit platforms support GCs that require a tmp register
5931 // Only IN_HEAP loads require a thread_tmp register
5932 // WeakHandle::resolve is an indirection like jweak.
5933 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5934 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
5935 bind(resolved);
5936 }
5937
5938 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5939 // get mirror
5940 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5941 load_method_holder(mirror, method);
5942 movptr(mirror, Address(mirror, mirror_offset));
5943 resolve_oop_handle(mirror, tmp);
5944 }
5945
5946 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5947 load_method_holder(rresult, rmethod);
5948 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5949 }
5950
5951 void MacroAssembler::load_method_holder(Register holder, Register method) {
5952 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5953 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5954 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5955 }
5956
5957 #ifdef _LP64
5958 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5959 assert(UseCompactObjectHeaders, "expect compact object headers");
5960 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5961 shrq(dst, markWord::klass_shift);
5962 }
5963 #endif
5964
5965 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5966 assert_different_registers(src, tmp);
5967 assert_different_registers(dst, tmp);
5968 #ifdef _LP64
5969 if (UseCompactObjectHeaders) {
5970 load_narrow_klass_compact(dst, src);
5971 decode_klass_not_null(dst, tmp);
5972 } else if (UseCompressedClassPointers) {
5973 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5974 decode_klass_not_null(dst, tmp);
5975 } else
5976 #endif
5977 {
5978 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5979 }
5980 }
5981
5982 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5983 assert(!UseCompactObjectHeaders, "not with compact headers");
5984 assert_different_registers(src, tmp);
5985 assert_different_registers(dst, tmp);
5986 #ifdef _LP64
5987 if (UseCompressedClassPointers) {
5988 encode_klass_not_null(src, tmp);
5989 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5990 } else
5991 #endif
5992 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5993 }
5994
5995 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
5996 #ifdef _LP64
5997 if (UseCompactObjectHeaders) {
5998 assert(tmp != noreg, "need tmp");
5999 assert_different_registers(klass, obj, tmp);
6000 load_narrow_klass_compact(tmp, obj);
6001 cmpl(klass, tmp);
6002 } else if (UseCompressedClassPointers) {
6003 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
6004 } else
6005 #endif
6006 {
6007 cmpptr(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
6008 }
6009 }
6010
6011 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
6012 #ifdef _LP64
6013 if (UseCompactObjectHeaders) {
6014 assert(tmp2 != noreg, "need tmp2");
6015 assert_different_registers(obj1, obj2, tmp1, tmp2);
6016 load_narrow_klass_compact(tmp1, obj1);
6017 load_narrow_klass_compact(tmp2, obj2);
6018 cmpl(tmp1, tmp2);
6019 } else if (UseCompressedClassPointers) {
6020 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
6021 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
6022 } else
6023 #endif
6024 {
6025 movptr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
6026 cmpptr(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
6027 }
6028 }
6029
6030 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
6031 Register tmp1, Register thread_tmp) {
6032 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6033 decorators = AccessInternal::decorator_fixup(decorators, type);
6034 bool as_raw = (decorators & AS_RAW) != 0;
6035 if (as_raw) {
6036 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6037 } else {
6038 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6039 }
6040 }
6041
6042 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
6043 Register tmp1, Register tmp2, Register tmp3) {
6044 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6045 decorators = AccessInternal::decorator_fixup(decorators, type);
6046 bool as_raw = (decorators & AS_RAW) != 0;
6047 if (as_raw) {
6048 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6049 } else {
6050 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6051 }
6052 }
6053
6054 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
6055 Register thread_tmp, DecoratorSet decorators) {
6056 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
6057 }
6058
6059 // Doesn't do verification, generates fixed size code
6060 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
6061 Register thread_tmp, DecoratorSet decorators) {
6062 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
6063 }
6064
6065 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
6066 Register tmp2, Register tmp3, DecoratorSet decorators) {
6067 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
6068 }
6069
6070 // Used for storing nulls.
6071 void MacroAssembler::store_heap_oop_null(Address dst) {
6072 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
6073 }
6074
6075 #ifdef _LP64
6076 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6077 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
6078 if (UseCompressedClassPointers) {
6079 // Store to klass gap in destination
6080 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6081 }
6082 }
6083
6084 #ifdef ASSERT
6085 void MacroAssembler::verify_heapbase(const char* msg) {
6086 assert (UseCompressedOops, "should be compressed");
6087 assert (Universe::heap() != nullptr, "java heap should be initialized");
6088 if (CheckCompressedOops) {
6089 Label ok;
6090 ExternalAddress src2(CompressedOops::base_addr());
6091 const bool is_src2_reachable = reachable(src2);
6092 if (!is_src2_reachable) {
6093 push(rscratch1); // cmpptr trashes rscratch1
6094 }
6095 cmpptr(r12_heapbase, src2, rscratch1);
6096 jcc(Assembler::equal, ok);
6097 STOP(msg);
6098 bind(ok);
6099 if (!is_src2_reachable) {
6100 pop(rscratch1);
6101 }
6102 }
6103 }
6104 #endif
6105
6106 // Algorithm must match oop.inline.hpp encode_heap_oop.
6107 void MacroAssembler::encode_heap_oop(Register r) {
6108 #ifdef ASSERT
6109 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6110 #endif
6111 verify_oop_msg(r, "broken oop in encode_heap_oop");
6112 if (CompressedOops::base() == nullptr) {
6113 if (CompressedOops::shift() != 0) {
6114 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6115 shrq(r, LogMinObjAlignmentInBytes);
6116 }
6117 return;
6118 }
6119 testq(r, r);
6120 cmovq(Assembler::equal, r, r12_heapbase);
6121 subq(r, r12_heapbase);
6122 shrq(r, LogMinObjAlignmentInBytes);
6123 }
6124
6125 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6126 #ifdef ASSERT
6127 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6128 if (CheckCompressedOops) {
6129 Label ok;
6130 testq(r, r);
6131 jcc(Assembler::notEqual, ok);
6132 STOP("null oop passed to encode_heap_oop_not_null");
6133 bind(ok);
6134 }
6135 #endif
6136 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
6137 if (CompressedOops::base() != nullptr) {
6138 subq(r, r12_heapbase);
6139 }
6140 if (CompressedOops::shift() != 0) {
6141 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6142 shrq(r, LogMinObjAlignmentInBytes);
6143 }
6144 }
6145
6146 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6147 #ifdef ASSERT
6148 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6149 if (CheckCompressedOops) {
6150 Label ok;
6151 testq(src, src);
6152 jcc(Assembler::notEqual, ok);
6153 STOP("null oop passed to encode_heap_oop_not_null2");
6154 bind(ok);
6155 }
6156 #endif
6157 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
6158 if (dst != src) {
6159 movq(dst, src);
6160 }
6161 if (CompressedOops::base() != nullptr) {
6162 subq(dst, r12_heapbase);
6163 }
6164 if (CompressedOops::shift() != 0) {
6165 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6166 shrq(dst, LogMinObjAlignmentInBytes);
6167 }
6168 }
6169
6170 void MacroAssembler::decode_heap_oop(Register r) {
6171 #ifdef ASSERT
6172 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6173 #endif
6174 if (CompressedOops::base() == nullptr) {
6175 if (CompressedOops::shift() != 0) {
6176 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6177 shlq(r, LogMinObjAlignmentInBytes);
6178 }
6179 } else {
6180 Label done;
6181 shlq(r, LogMinObjAlignmentInBytes);
6182 jccb(Assembler::equal, done);
6183 addq(r, r12_heapbase);
6184 bind(done);
6185 }
6186 verify_oop_msg(r, "broken oop in decode_heap_oop");
6187 }
6188
6189 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6190 // Note: it will change flags
6191 assert (UseCompressedOops, "should only be used for compressed headers");
6192 assert (Universe::heap() != nullptr, "java heap should be initialized");
6193 // Cannot assert, unverified entry point counts instructions (see .ad file)
6194 // vtableStubs also counts instructions in pd_code_size_limit.
6195 // Also do not verify_oop as this is called by verify_oop.
6196 if (CompressedOops::shift() != 0) {
6197 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6198 shlq(r, LogMinObjAlignmentInBytes);
6199 if (CompressedOops::base() != nullptr) {
6200 addq(r, r12_heapbase);
6201 }
6202 } else {
6203 assert (CompressedOops::base() == nullptr, "sanity");
6204 }
6205 }
6206
6207 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6208 // Note: it will change flags
6209 assert (UseCompressedOops, "should only be used for compressed headers");
6210 assert (Universe::heap() != nullptr, "java heap should be initialized");
6211 // Cannot assert, unverified entry point counts instructions (see .ad file)
6212 // vtableStubs also counts instructions in pd_code_size_limit.
6213 // Also do not verify_oop as this is called by verify_oop.
6214 if (CompressedOops::shift() != 0) {
6215 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6216 if (LogMinObjAlignmentInBytes == Address::times_8) {
6217 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6218 } else {
6219 if (dst != src) {
6220 movq(dst, src);
6221 }
6222 shlq(dst, LogMinObjAlignmentInBytes);
6223 if (CompressedOops::base() != nullptr) {
6224 addq(dst, r12_heapbase);
6225 }
6226 }
6227 } else {
6228 assert (CompressedOops::base() == nullptr, "sanity");
6229 if (dst != src) {
6230 movq(dst, src);
6231 }
6232 }
6233 }
6234
6235 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
6236 assert_different_registers(r, tmp);
6237 if (CompressedKlassPointers::base() != nullptr) {
6238 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6239 subq(r, tmp);
6240 }
6241 if (CompressedKlassPointers::shift() != 0) {
6242 shrq(r, CompressedKlassPointers::shift());
6243 }
6244 }
6245
6246 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
6247 assert_different_registers(src, dst);
6248 if (CompressedKlassPointers::base() != nullptr) {
6249 mov64(dst, -(int64_t)CompressedKlassPointers::base());
6250 addq(dst, src);
6251 } else {
6252 movptr(dst, src);
6253 }
6254 if (CompressedKlassPointers::shift() != 0) {
6255 shrq(dst, CompressedKlassPointers::shift());
6256 }
6257 }
6258
6259 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
6260 assert_different_registers(r, tmp);
6261 // Note: it will change flags
6262 assert(UseCompressedClassPointers, "should only be used for compressed headers");
6263 // Cannot assert, unverified entry point counts instructions (see .ad file)
6264 // vtableStubs also counts instructions in pd_code_size_limit.
6265 // Also do not verify_oop as this is called by verify_oop.
6266 if (CompressedKlassPointers::shift() != 0) {
6267 shlq(r, CompressedKlassPointers::shift());
6268 }
6269 if (CompressedKlassPointers::base() != nullptr) {
6270 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6271 addq(r, tmp);
6272 }
6273 }
6274
6275 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
6276 assert_different_registers(src, dst);
6277 // Note: it will change flags
6278 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6279 // Cannot assert, unverified entry point counts instructions (see .ad file)
6280 // vtableStubs also counts instructions in pd_code_size_limit.
6281 // Also do not verify_oop as this is called by verify_oop.
6282
6283 if (CompressedKlassPointers::base() == nullptr &&
6284 CompressedKlassPointers::shift() == 0) {
6285 // The best case scenario is that there is no base or shift. Then it is already
6286 // a pointer that needs nothing but a register rename.
6287 movl(dst, src);
6288 } else {
6289 if (CompressedKlassPointers::shift() <= Address::times_8) {
6290 if (CompressedKlassPointers::base() != nullptr) {
6291 mov64(dst, (int64_t)CompressedKlassPointers::base());
6292 } else {
6293 xorq(dst, dst);
6294 }
6295 if (CompressedKlassPointers::shift() != 0) {
6296 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
6297 leaq(dst, Address(dst, src, Address::times_8, 0));
6298 } else {
6299 addq(dst, src);
6300 }
6301 } else {
6302 if (CompressedKlassPointers::base() != nullptr) {
6303 const uint64_t base_right_shifted =
6304 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
6305 mov64(dst, base_right_shifted);
6306 } else {
6307 xorq(dst, dst);
6308 }
6309 addq(dst, src);
6310 shlq(dst, CompressedKlassPointers::shift());
6311 }
6312 }
6313 }
6314
6315 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6316 assert (UseCompressedOops, "should only be used for compressed headers");
6317 assert (Universe::heap() != nullptr, "java heap should be initialized");
6318 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6319 int oop_index = oop_recorder()->find_index(obj);
6320 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6321 mov_narrow_oop(dst, oop_index, rspec);
6322 }
6323
6324 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6325 assert (UseCompressedOops, "should only be used for compressed headers");
6326 assert (Universe::heap() != nullptr, "java heap should be initialized");
6327 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6328 int oop_index = oop_recorder()->find_index(obj);
6329 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6330 mov_narrow_oop(dst, oop_index, rspec);
6331 }
6332
6333 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6334 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6335 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6336 int klass_index = oop_recorder()->find_index(k);
6337 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6338 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6339 }
6340
6341 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6342 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6343 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6344 int klass_index = oop_recorder()->find_index(k);
6345 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6346 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6347 }
6348
6349 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6350 assert (UseCompressedOops, "should only be used for compressed headers");
6351 assert (Universe::heap() != nullptr, "java heap should be initialized");
6352 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6353 int oop_index = oop_recorder()->find_index(obj);
6354 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6355 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6356 }
6357
6358 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6359 assert (UseCompressedOops, "should only be used for compressed headers");
6360 assert (Universe::heap() != nullptr, "java heap should be initialized");
6361 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6362 int oop_index = oop_recorder()->find_index(obj);
6363 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6364 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6365 }
6366
6367 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6368 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6369 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6370 int klass_index = oop_recorder()->find_index(k);
6371 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6372 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6373 }
6374
6375 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6376 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6377 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6378 int klass_index = oop_recorder()->find_index(k);
6379 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6380 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6381 }
6382
6383 void MacroAssembler::reinit_heapbase() {
6384 if (UseCompressedOops) {
6385 if (Universe::heap() != nullptr) {
6386 if (CompressedOops::base() == nullptr) {
6387 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6388 } else {
6389 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6390 }
6391 } else {
6392 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6393 }
6394 }
6395 }
6396
6397 #endif // _LP64
6398
6399 #if COMPILER2_OR_JVMCI
6400
6401 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6402 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6403 // cnt - number of qwords (8-byte words).
6404 // base - start address, qword aligned.
6405 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6406 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
6407 if (use64byteVector) {
6408 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
6409 } else if (MaxVectorSize >= 32) {
6410 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
6411 } else {
6412 pxor(xtmp, xtmp);
6413 }
6414 jmp(L_zero_64_bytes);
6415
6416 BIND(L_loop);
6417 if (MaxVectorSize >= 32) {
6418 fill64(base, 0, xtmp, use64byteVector);
6419 } else {
6420 movdqu(Address(base, 0), xtmp);
6421 movdqu(Address(base, 16), xtmp);
6422 movdqu(Address(base, 32), xtmp);
6423 movdqu(Address(base, 48), xtmp);
6424 }
6425 addptr(base, 64);
6426
6427 BIND(L_zero_64_bytes);
6428 subptr(cnt, 8);
6429 jccb(Assembler::greaterEqual, L_loop);
6430
6431 // Copy trailing 64 bytes
6432 if (use64byteVector) {
6433 addptr(cnt, 8);
6434 jccb(Assembler::equal, L_end);
6435 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
6436 jmp(L_end);
6437 } else {
6438 addptr(cnt, 4);
6439 jccb(Assembler::less, L_tail);
6440 if (MaxVectorSize >= 32) {
6441 vmovdqu(Address(base, 0), xtmp);
6442 } else {
6443 movdqu(Address(base, 0), xtmp);
6444 movdqu(Address(base, 16), xtmp);
6445 }
6446 }
6447 addptr(base, 32);
6448 subptr(cnt, 4);
6449
6450 BIND(L_tail);
6451 addptr(cnt, 4);
6452 jccb(Assembler::lessEqual, L_end);
6453 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6454 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
6455 } else {
6456 decrement(cnt);
6457
6458 BIND(L_sloop);
6459 movq(Address(base, 0), xtmp);
6460 addptr(base, 8);
6461 decrement(cnt);
6462 jccb(Assembler::greaterEqual, L_sloop);
6463 }
6464 BIND(L_end);
6465 }
6466
6467 // Clearing constant sized memory using YMM/ZMM registers.
6468 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6469 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6470 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
6471
6472 int vector64_count = (cnt & (~0x7)) >> 3;
6473 cnt = cnt & 0x7;
6474 const int fill64_per_loop = 4;
6475 const int max_unrolled_fill64 = 8;
6476
6477 // 64 byte initialization loop.
6478 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6479 int start64 = 0;
6480 if (vector64_count > max_unrolled_fill64) {
6481 Label LOOP;
6482 Register index = rtmp;
6483
6484 start64 = vector64_count - (vector64_count % fill64_per_loop);
6485
6486 movl(index, 0);
6487 BIND(LOOP);
6488 for (int i = 0; i < fill64_per_loop; i++) {
6489 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6490 }
6491 addl(index, fill64_per_loop * 64);
6492 cmpl(index, start64 * 64);
6493 jccb(Assembler::less, LOOP);
6494 }
6495 for (int i = start64; i < vector64_count; i++) {
6496 fill64(base, i * 64, xtmp, use64byteVector);
6497 }
6498
6499 // Clear remaining 64 byte tail.
6500 int disp = vector64_count * 64;
6501 if (cnt) {
6502 switch (cnt) {
6503 case 1:
6504 movq(Address(base, disp), xtmp);
6505 break;
6506 case 2:
6507 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6508 break;
6509 case 3:
6510 movl(rtmp, 0x7);
6511 kmovwl(mask, rtmp);
6512 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6513 break;
6514 case 4:
6515 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6516 break;
6517 case 5:
6518 if (use64byteVector) {
6519 movl(rtmp, 0x1F);
6520 kmovwl(mask, rtmp);
6521 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6522 } else {
6523 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6524 movq(Address(base, disp + 32), xtmp);
6525 }
6526 break;
6527 case 6:
6528 if (use64byteVector) {
6529 movl(rtmp, 0x3F);
6530 kmovwl(mask, rtmp);
6531 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6532 } else {
6533 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6534 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6535 }
6536 break;
6537 case 7:
6538 if (use64byteVector) {
6539 movl(rtmp, 0x7F);
6540 kmovwl(mask, rtmp);
6541 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6542 } else {
6543 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6544 movl(rtmp, 0x7);
6545 kmovwl(mask, rtmp);
6546 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6547 }
6548 break;
6549 default:
6550 fatal("Unexpected length : %d\n",cnt);
6551 break;
6552 }
6553 }
6554 }
6555
6556 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
6557 bool is_large, KRegister mask) {
6558 // cnt - number of qwords (8-byte words).
6559 // base - start address, qword aligned.
6560 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6561 assert(base==rdi, "base register must be edi for rep stos");
6562 assert(tmp==rax, "tmp register must be eax for rep stos");
6563 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6564 assert(InitArrayShortSize % BytesPerLong == 0,
6565 "InitArrayShortSize should be the multiple of BytesPerLong");
6566
6567 Label DONE;
6568 if (!is_large || !UseXMMForObjInit) {
6569 xorptr(tmp, tmp);
6570 }
6571
6572 if (!is_large) {
6573 Label LOOP, LONG;
6574 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6575 jccb(Assembler::greater, LONG);
6576
6577 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6578
6579 decrement(cnt);
6580 jccb(Assembler::negative, DONE); // Zero length
6581
6582 // Use individual pointer-sized stores for small counts:
6583 BIND(LOOP);
6584 movptr(Address(base, cnt, Address::times_ptr), tmp);
6585 decrement(cnt);
6586 jccb(Assembler::greaterEqual, LOOP);
6587 jmpb(DONE);
6588
6589 BIND(LONG);
6590 }
6591
6592 // Use longer rep-prefixed ops for non-small counts:
6593 if (UseFastStosb) {
6594 shlptr(cnt, 3); // convert to number of bytes
6595 rep_stosb();
6596 } else if (UseXMMForObjInit) {
6597 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
6598 } else {
6599 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6600 rep_stos();
6601 }
6602
6603 BIND(DONE);
6604 }
6605
6606 #endif //COMPILER2_OR_JVMCI
6607
6608
6609 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6610 Register to, Register value, Register count,
6611 Register rtmp, XMMRegister xtmp) {
6612 ShortBranchVerifier sbv(this);
6613 assert_different_registers(to, value, count, rtmp);
6614 Label L_exit;
6615 Label L_fill_2_bytes, L_fill_4_bytes;
6616
6617 #if defined(COMPILER2) && defined(_LP64)
6618 if(MaxVectorSize >=32 &&
6619 VM_Version::supports_avx512vlbw() &&
6620 VM_Version::supports_bmi2()) {
6621 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6622 return;
6623 }
6624 #endif
6625
6626 int shift = -1;
6627 switch (t) {
6628 case T_BYTE:
6629 shift = 2;
6630 break;
6631 case T_SHORT:
6632 shift = 1;
6633 break;
6634 case T_INT:
6635 shift = 0;
6636 break;
6637 default: ShouldNotReachHere();
6638 }
6639
6640 if (t == T_BYTE) {
6641 andl(value, 0xff);
6642 movl(rtmp, value);
6643 shll(rtmp, 8);
6644 orl(value, rtmp);
6645 }
6646 if (t == T_SHORT) {
6647 andl(value, 0xffff);
6648 }
6649 if (t == T_BYTE || t == T_SHORT) {
6650 movl(rtmp, value);
6651 shll(rtmp, 16);
6652 orl(value, rtmp);
6653 }
6654
6655 cmpptr(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
6656 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6657 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6658 Label L_skip_align2;
6659 // align source address at 4 bytes address boundary
6660 if (t == T_BYTE) {
6661 Label L_skip_align1;
6662 // One byte misalignment happens only for byte arrays
6663 testptr(to, 1);
6664 jccb(Assembler::zero, L_skip_align1);
6665 movb(Address(to, 0), value);
6666 increment(to);
6667 decrement(count);
6668 BIND(L_skip_align1);
6669 }
6670 // Two bytes misalignment happens only for byte and short (char) arrays
6671 testptr(to, 2);
6672 jccb(Assembler::zero, L_skip_align2);
6673 movw(Address(to, 0), value);
6674 addptr(to, 2);
6675 subptr(count, 1<<(shift-1));
6676 BIND(L_skip_align2);
6677 }
6678 if (UseSSE < 2) {
6679 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6680 // Fill 32-byte chunks
6681 subptr(count, 8 << shift);
6682 jcc(Assembler::less, L_check_fill_8_bytes);
6683 align(16);
6684
6685 BIND(L_fill_32_bytes_loop);
6686
6687 for (int i = 0; i < 32; i += 4) {
6688 movl(Address(to, i), value);
6689 }
6690
6691 addptr(to, 32);
6692 subptr(count, 8 << shift);
6693 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6694 BIND(L_check_fill_8_bytes);
6695 addptr(count, 8 << shift);
6696 jccb(Assembler::zero, L_exit);
6697 jmpb(L_fill_8_bytes);
6698
6699 //
6700 // length is too short, just fill qwords
6701 //
6702 BIND(L_fill_8_bytes_loop);
6703 movl(Address(to, 0), value);
6704 movl(Address(to, 4), value);
6705 addptr(to, 8);
6706 BIND(L_fill_8_bytes);
6707 subptr(count, 1 << (shift + 1));
6708 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6709 // fall through to fill 4 bytes
6710 } else {
6711 Label L_fill_32_bytes;
6712 if (!UseUnalignedLoadStores) {
6713 // align to 8 bytes, we know we are 4 byte aligned to start
6714 testptr(to, 4);
6715 jccb(Assembler::zero, L_fill_32_bytes);
6716 movl(Address(to, 0), value);
6717 addptr(to, 4);
6718 subptr(count, 1<<shift);
6719 }
6720 BIND(L_fill_32_bytes);
6721 {
6722 assert( UseSSE >= 2, "supported cpu only" );
6723 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6724 movdl(xtmp, value);
6725 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6726 Label L_check_fill_32_bytes;
6727 if (UseAVX > 2) {
6728 // Fill 64-byte chunks
6729 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6730
6731 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
6732 cmpptr(count, VM_Version::avx3_threshold());
6733 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6734
6735 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6736
6737 subptr(count, 16 << shift);
6738 jccb(Assembler::less, L_check_fill_32_bytes);
6739 align(16);
6740
6741 BIND(L_fill_64_bytes_loop_avx3);
6742 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6743 addptr(to, 64);
6744 subptr(count, 16 << shift);
6745 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6746 jmpb(L_check_fill_32_bytes);
6747
6748 BIND(L_check_fill_64_bytes_avx2);
6749 }
6750 // Fill 64-byte chunks
6751 Label L_fill_64_bytes_loop;
6752 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6753
6754 subptr(count, 16 << shift);
6755 jcc(Assembler::less, L_check_fill_32_bytes);
6756 align(16);
6757
6758 BIND(L_fill_64_bytes_loop);
6759 vmovdqu(Address(to, 0), xtmp);
6760 vmovdqu(Address(to, 32), xtmp);
6761 addptr(to, 64);
6762 subptr(count, 16 << shift);
6763 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6764
6765 BIND(L_check_fill_32_bytes);
6766 addptr(count, 8 << shift);
6767 jccb(Assembler::less, L_check_fill_8_bytes);
6768 vmovdqu(Address(to, 0), xtmp);
6769 addptr(to, 32);
6770 subptr(count, 8 << shift);
6771
6772 BIND(L_check_fill_8_bytes);
6773 // clean upper bits of YMM registers
6774 movdl(xtmp, value);
6775 pshufd(xtmp, xtmp, 0);
6776 } else {
6777 // Fill 32-byte chunks
6778 pshufd(xtmp, xtmp, 0);
6779
6780 subptr(count, 8 << shift);
6781 jcc(Assembler::less, L_check_fill_8_bytes);
6782 align(16);
6783
6784 BIND(L_fill_32_bytes_loop);
6785
6786 if (UseUnalignedLoadStores) {
6787 movdqu(Address(to, 0), xtmp);
6788 movdqu(Address(to, 16), xtmp);
6789 } else {
6790 movq(Address(to, 0), xtmp);
6791 movq(Address(to, 8), xtmp);
6792 movq(Address(to, 16), xtmp);
6793 movq(Address(to, 24), xtmp);
6794 }
6795
6796 addptr(to, 32);
6797 subptr(count, 8 << shift);
6798 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6799
6800 BIND(L_check_fill_8_bytes);
6801 }
6802 addptr(count, 8 << shift);
6803 jccb(Assembler::zero, L_exit);
6804 jmpb(L_fill_8_bytes);
6805
6806 //
6807 // length is too short, just fill qwords
6808 //
6809 BIND(L_fill_8_bytes_loop);
6810 movq(Address(to, 0), xtmp);
6811 addptr(to, 8);
6812 BIND(L_fill_8_bytes);
6813 subptr(count, 1 << (shift + 1));
6814 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6815 }
6816 }
6817 // fill trailing 4 bytes
6818 BIND(L_fill_4_bytes);
6819 testl(count, 1<<shift);
6820 jccb(Assembler::zero, L_fill_2_bytes);
6821 movl(Address(to, 0), value);
6822 if (t == T_BYTE || t == T_SHORT) {
6823 Label L_fill_byte;
6824 addptr(to, 4);
6825 BIND(L_fill_2_bytes);
6826 // fill trailing 2 bytes
6827 testl(count, 1<<(shift-1));
6828 jccb(Assembler::zero, L_fill_byte);
6829 movw(Address(to, 0), value);
6830 if (t == T_BYTE) {
6831 addptr(to, 2);
6832 BIND(L_fill_byte);
6833 // fill trailing byte
6834 testl(count, 1);
6835 jccb(Assembler::zero, L_exit);
6836 movb(Address(to, 0), value);
6837 } else {
6838 BIND(L_fill_byte);
6839 }
6840 } else {
6841 BIND(L_fill_2_bytes);
6842 }
6843 BIND(L_exit);
6844 }
6845
6846 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6847 switch(type) {
6848 case T_BYTE:
6849 case T_BOOLEAN:
6850 evpbroadcastb(dst, src, vector_len);
6851 break;
6852 case T_SHORT:
6853 case T_CHAR:
6854 evpbroadcastw(dst, src, vector_len);
6855 break;
6856 case T_INT:
6857 case T_FLOAT:
6858 evpbroadcastd(dst, src, vector_len);
6859 break;
6860 case T_LONG:
6861 case T_DOUBLE:
6862 evpbroadcastq(dst, src, vector_len);
6863 break;
6864 default:
6865 fatal("Unhandled type : %s", type2name(type));
6866 break;
6867 }
6868 }
6869
6870 // encode char[] to byte[] in ISO_8859_1 or ASCII
6871 //@IntrinsicCandidate
6872 //private static int implEncodeISOArray(byte[] sa, int sp,
6873 //byte[] da, int dp, int len) {
6874 // int i = 0;
6875 // for (; i < len; i++) {
6876 // char c = StringUTF16.getChar(sa, sp++);
6877 // if (c > '\u00FF')
6878 // break;
6879 // da[dp++] = (byte)c;
6880 // }
6881 // return i;
6882 //}
6883 //
6884 //@IntrinsicCandidate
6885 //private static int implEncodeAsciiArray(char[] sa, int sp,
6886 // byte[] da, int dp, int len) {
6887 // int i = 0;
6888 // for (; i < len; i++) {
6889 // char c = sa[sp++];
6890 // if (c >= '\u0080')
6891 // break;
6892 // da[dp++] = (byte)c;
6893 // }
6894 // return i;
6895 //}
6896 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6897 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6898 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6899 Register tmp5, Register result, bool ascii) {
6900
6901 // rsi: src
6902 // rdi: dst
6903 // rdx: len
6904 // rcx: tmp5
6905 // rax: result
6906 ShortBranchVerifier sbv(this);
6907 assert_different_registers(src, dst, len, tmp5, result);
6908 Label L_done, L_copy_1_char, L_copy_1_char_exit;
6909
6910 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
6911 int short_mask = ascii ? 0xff80 : 0xff00;
6912
6913 // set result
6914 xorl(result, result);
6915 // check for zero length
6916 testl(len, len);
6917 jcc(Assembler::zero, L_done);
6918
6919 movl(result, len);
6920
6921 // Setup pointers
6922 lea(src, Address(src, len, Address::times_2)); // char[]
6923 lea(dst, Address(dst, len, Address::times_1)); // byte[]
6924 negptr(len);
6925
6926 if (UseSSE42Intrinsics || UseAVX >= 2) {
6927 Label L_copy_8_chars, L_copy_8_chars_exit;
6928 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
6929
6930 if (UseAVX >= 2) {
6931 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
6932 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6933 movdl(tmp1Reg, tmp5);
6934 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
6935 jmp(L_chars_32_check);
6936
6937 bind(L_copy_32_chars);
6938 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
6939 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
6940 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6941 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6942 jccb(Assembler::notZero, L_copy_32_chars_exit);
6943 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6944 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
6945 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
6946
6947 bind(L_chars_32_check);
6948 addptr(len, 32);
6949 jcc(Assembler::lessEqual, L_copy_32_chars);
6950
6951 bind(L_copy_32_chars_exit);
6952 subptr(len, 16);
6953 jccb(Assembler::greater, L_copy_16_chars_exit);
6954
6955 } else if (UseSSE42Intrinsics) {
6956 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6957 movdl(tmp1Reg, tmp5);
6958 pshufd(tmp1Reg, tmp1Reg, 0);
6959 jmpb(L_chars_16_check);
6960 }
6961
6962 bind(L_copy_16_chars);
6963 if (UseAVX >= 2) {
6964 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
6965 vptest(tmp2Reg, tmp1Reg);
6966 jcc(Assembler::notZero, L_copy_16_chars_exit);
6967 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
6968 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
6969 } else {
6970 if (UseAVX > 0) {
6971 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6972 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6973 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
6974 } else {
6975 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6976 por(tmp2Reg, tmp3Reg);
6977 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6978 por(tmp2Reg, tmp4Reg);
6979 }
6980 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6981 jccb(Assembler::notZero, L_copy_16_chars_exit);
6982 packuswb(tmp3Reg, tmp4Reg);
6983 }
6984 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
6985
6986 bind(L_chars_16_check);
6987 addptr(len, 16);
6988 jcc(Assembler::lessEqual, L_copy_16_chars);
6989
6990 bind(L_copy_16_chars_exit);
6991 if (UseAVX >= 2) {
6992 // clean upper bits of YMM registers
6993 vpxor(tmp2Reg, tmp2Reg);
6994 vpxor(tmp3Reg, tmp3Reg);
6995 vpxor(tmp4Reg, tmp4Reg);
6996 movdl(tmp1Reg, tmp5);
6997 pshufd(tmp1Reg, tmp1Reg, 0);
6998 }
6999 subptr(len, 8);
7000 jccb(Assembler::greater, L_copy_8_chars_exit);
7001
7002 bind(L_copy_8_chars);
7003 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7004 ptest(tmp3Reg, tmp1Reg);
7005 jccb(Assembler::notZero, L_copy_8_chars_exit);
7006 packuswb(tmp3Reg, tmp1Reg);
7007 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7008 addptr(len, 8);
7009 jccb(Assembler::lessEqual, L_copy_8_chars);
7010
7011 bind(L_copy_8_chars_exit);
7012 subptr(len, 8);
7013 jccb(Assembler::zero, L_done);
7014 }
7015
7016 bind(L_copy_1_char);
7017 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7018 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
7019 jccb(Assembler::notZero, L_copy_1_char_exit);
7020 movb(Address(dst, len, Address::times_1, 0), tmp5);
7021 addptr(len, 1);
7022 jccb(Assembler::less, L_copy_1_char);
7023
7024 bind(L_copy_1_char_exit);
7025 addptr(result, len); // len is negative count of not processed elements
7026
7027 bind(L_done);
7028 }
7029
7030 #ifdef _LP64
7031 /**
7032 * Helper for multiply_to_len().
7033 */
7034 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7035 addq(dest_lo, src1);
7036 adcq(dest_hi, 0);
7037 addq(dest_lo, src2);
7038 adcq(dest_hi, 0);
7039 }
7040
7041 /**
7042 * Multiply 64 bit by 64 bit first loop.
7043 */
7044 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7045 Register y, Register y_idx, Register z,
7046 Register carry, Register product,
7047 Register idx, Register kdx) {
7048 //
7049 // jlong carry, x[], y[], z[];
7050 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7051 // huge_128 product = y[idx] * x[xstart] + carry;
7052 // z[kdx] = (jlong)product;
7053 // carry = (jlong)(product >>> 64);
7054 // }
7055 // z[xstart] = carry;
7056 //
7057
7058 Label L_first_loop, L_first_loop_exit;
7059 Label L_one_x, L_one_y, L_multiply;
7060
7061 decrementl(xstart);
7062 jcc(Assembler::negative, L_one_x);
7063
7064 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7065 rorq(x_xstart, 32); // convert big-endian to little-endian
7066
7067 bind(L_first_loop);
7068 decrementl(idx);
7069 jcc(Assembler::negative, L_first_loop_exit);
7070 decrementl(idx);
7071 jcc(Assembler::negative, L_one_y);
7072 movq(y_idx, Address(y, idx, Address::times_4, 0));
7073 rorq(y_idx, 32); // convert big-endian to little-endian
7074 bind(L_multiply);
7075 movq(product, x_xstart);
7076 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7077 addq(product, carry);
7078 adcq(rdx, 0);
7079 subl(kdx, 2);
7080 movl(Address(z, kdx, Address::times_4, 4), product);
7081 shrq(product, 32);
7082 movl(Address(z, kdx, Address::times_4, 0), product);
7083 movq(carry, rdx);
7084 jmp(L_first_loop);
7085
7086 bind(L_one_y);
7087 movl(y_idx, Address(y, 0));
7088 jmp(L_multiply);
7089
7090 bind(L_one_x);
7091 movl(x_xstart, Address(x, 0));
7092 jmp(L_first_loop);
7093
7094 bind(L_first_loop_exit);
7095 }
7096
7097 /**
7098 * Multiply 64 bit by 64 bit and add 128 bit.
7099 */
7100 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7101 Register yz_idx, Register idx,
7102 Register carry, Register product, int offset) {
7103 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7104 // z[kdx] = (jlong)product;
7105
7106 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7107 rorq(yz_idx, 32); // convert big-endian to little-endian
7108 movq(product, x_xstart);
7109 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7110 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7111 rorq(yz_idx, 32); // convert big-endian to little-endian
7112
7113 add2_with_carry(rdx, product, carry, yz_idx);
7114
7115 movl(Address(z, idx, Address::times_4, offset+4), product);
7116 shrq(product, 32);
7117 movl(Address(z, idx, Address::times_4, offset), product);
7118
7119 }
7120
7121 /**
7122 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7123 */
7124 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7125 Register yz_idx, Register idx, Register jdx,
7126 Register carry, Register product,
7127 Register carry2) {
7128 // jlong carry, x[], y[], z[];
7129 // int kdx = ystart+1;
7130 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7131 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7132 // z[kdx+idx+1] = (jlong)product;
7133 // jlong carry2 = (jlong)(product >>> 64);
7134 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7135 // z[kdx+idx] = (jlong)product;
7136 // carry = (jlong)(product >>> 64);
7137 // }
7138 // idx += 2;
7139 // if (idx > 0) {
7140 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7141 // z[kdx+idx] = (jlong)product;
7142 // carry = (jlong)(product >>> 64);
7143 // }
7144 //
7145
7146 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7147
7148 movl(jdx, idx);
7149 andl(jdx, 0xFFFFFFFC);
7150 shrl(jdx, 2);
7151
7152 bind(L_third_loop);
7153 subl(jdx, 1);
7154 jcc(Assembler::negative, L_third_loop_exit);
7155 subl(idx, 4);
7156
7157 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7158 movq(carry2, rdx);
7159
7160 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7161 movq(carry, rdx);
7162 jmp(L_third_loop);
7163
7164 bind (L_third_loop_exit);
7165
7166 andl (idx, 0x3);
7167 jcc(Assembler::zero, L_post_third_loop_done);
7168
7169 Label L_check_1;
7170 subl(idx, 2);
7171 jcc(Assembler::negative, L_check_1);
7172
7173 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7174 movq(carry, rdx);
7175
7176 bind (L_check_1);
7177 addl (idx, 0x2);
7178 andl (idx, 0x1);
7179 subl(idx, 1);
7180 jcc(Assembler::negative, L_post_third_loop_done);
7181
7182 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7183 movq(product, x_xstart);
7184 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7185 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7186
7187 add2_with_carry(rdx, product, yz_idx, carry);
7188
7189 movl(Address(z, idx, Address::times_4, 0), product);
7190 shrq(product, 32);
7191
7192 shlq(rdx, 32);
7193 orq(product, rdx);
7194 movq(carry, product);
7195
7196 bind(L_post_third_loop_done);
7197 }
7198
7199 /**
7200 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7201 *
7202 */
7203 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7204 Register carry, Register carry2,
7205 Register idx, Register jdx,
7206 Register yz_idx1, Register yz_idx2,
7207 Register tmp, Register tmp3, Register tmp4) {
7208 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7209
7210 // jlong carry, x[], y[], z[];
7211 // int kdx = ystart+1;
7212 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7213 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7214 // jlong carry2 = (jlong)(tmp3 >>> 64);
7215 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7216 // carry = (jlong)(tmp4 >>> 64);
7217 // z[kdx+idx+1] = (jlong)tmp3;
7218 // z[kdx+idx] = (jlong)tmp4;
7219 // }
7220 // idx += 2;
7221 // if (idx > 0) {
7222 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7223 // z[kdx+idx] = (jlong)yz_idx1;
7224 // carry = (jlong)(yz_idx1 >>> 64);
7225 // }
7226 //
7227
7228 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7229
7230 movl(jdx, idx);
7231 andl(jdx, 0xFFFFFFFC);
7232 shrl(jdx, 2);
7233
7234 bind(L_third_loop);
7235 subl(jdx, 1);
7236 jcc(Assembler::negative, L_third_loop_exit);
7237 subl(idx, 4);
7238
7239 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7240 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7241 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7242 rorxq(yz_idx2, yz_idx2, 32);
7243
7244 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7245 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7246
7247 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7248 rorxq(yz_idx1, yz_idx1, 32);
7249 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7250 rorxq(yz_idx2, yz_idx2, 32);
7251
7252 if (VM_Version::supports_adx()) {
7253 adcxq(tmp3, carry);
7254 adoxq(tmp3, yz_idx1);
7255
7256 adcxq(tmp4, tmp);
7257 adoxq(tmp4, yz_idx2);
7258
7259 movl(carry, 0); // does not affect flags
7260 adcxq(carry2, carry);
7261 adoxq(carry2, carry);
7262 } else {
7263 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7264 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7265 }
7266 movq(carry, carry2);
7267
7268 movl(Address(z, idx, Address::times_4, 12), tmp3);
7269 shrq(tmp3, 32);
7270 movl(Address(z, idx, Address::times_4, 8), tmp3);
7271
7272 movl(Address(z, idx, Address::times_4, 4), tmp4);
7273 shrq(tmp4, 32);
7274 movl(Address(z, idx, Address::times_4, 0), tmp4);
7275
7276 jmp(L_third_loop);
7277
7278 bind (L_third_loop_exit);
7279
7280 andl (idx, 0x3);
7281 jcc(Assembler::zero, L_post_third_loop_done);
7282
7283 Label L_check_1;
7284 subl(idx, 2);
7285 jcc(Assembler::negative, L_check_1);
7286
7287 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7288 rorxq(yz_idx1, yz_idx1, 32);
7289 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7290 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7291 rorxq(yz_idx2, yz_idx2, 32);
7292
7293 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7294
7295 movl(Address(z, idx, Address::times_4, 4), tmp3);
7296 shrq(tmp3, 32);
7297 movl(Address(z, idx, Address::times_4, 0), tmp3);
7298 movq(carry, tmp4);
7299
7300 bind (L_check_1);
7301 addl (idx, 0x2);
7302 andl (idx, 0x1);
7303 subl(idx, 1);
7304 jcc(Assembler::negative, L_post_third_loop_done);
7305 movl(tmp4, Address(y, idx, Address::times_4, 0));
7306 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7307 movl(tmp4, Address(z, idx, Address::times_4, 0));
7308
7309 add2_with_carry(carry2, tmp3, tmp4, carry);
7310
7311 movl(Address(z, idx, Address::times_4, 0), tmp3);
7312 shrq(tmp3, 32);
7313
7314 shlq(carry2, 32);
7315 orq(tmp3, carry2);
7316 movq(carry, tmp3);
7317
7318 bind(L_post_third_loop_done);
7319 }
7320
7321 /**
7322 * Code for BigInteger::multiplyToLen() intrinsic.
7323 *
7324 * rdi: x
7325 * rax: xlen
7326 * rsi: y
7327 * rcx: ylen
7328 * r8: z
7329 * r11: tmp0
7330 * r12: tmp1
7331 * r13: tmp2
7332 * r14: tmp3
7333 * r15: tmp4
7334 * rbx: tmp5
7335 *
7336 */
7337 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7338 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7339 ShortBranchVerifier sbv(this);
7340 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7341
7342 push(tmp0);
7343 push(tmp1);
7344 push(tmp2);
7345 push(tmp3);
7346 push(tmp4);
7347 push(tmp5);
7348
7349 push(xlen);
7350
7351 const Register idx = tmp1;
7352 const Register kdx = tmp2;
7353 const Register xstart = tmp3;
7354
7355 const Register y_idx = tmp4;
7356 const Register carry = tmp5;
7357 const Register product = xlen;
7358 const Register x_xstart = tmp0;
7359
7360 // First Loop.
7361 //
7362 // final static long LONG_MASK = 0xffffffffL;
7363 // int xstart = xlen - 1;
7364 // int ystart = ylen - 1;
7365 // long carry = 0;
7366 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7367 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7368 // z[kdx] = (int)product;
7369 // carry = product >>> 32;
7370 // }
7371 // z[xstart] = (int)carry;
7372 //
7373
7374 movl(idx, ylen); // idx = ylen;
7375 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7376 xorq(carry, carry); // carry = 0;
7377
7378 Label L_done;
7379
7380 movl(xstart, xlen);
7381 decrementl(xstart);
7382 jcc(Assembler::negative, L_done);
7383
7384 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7385
7386 Label L_second_loop;
7387 testl(kdx, kdx);
7388 jcc(Assembler::zero, L_second_loop);
7389
7390 Label L_carry;
7391 subl(kdx, 1);
7392 jcc(Assembler::zero, L_carry);
7393
7394 movl(Address(z, kdx, Address::times_4, 0), carry);
7395 shrq(carry, 32);
7396 subl(kdx, 1);
7397
7398 bind(L_carry);
7399 movl(Address(z, kdx, Address::times_4, 0), carry);
7400
7401 // Second and third (nested) loops.
7402 //
7403 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7404 // carry = 0;
7405 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7406 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7407 // (z[k] & LONG_MASK) + carry;
7408 // z[k] = (int)product;
7409 // carry = product >>> 32;
7410 // }
7411 // z[i] = (int)carry;
7412 // }
7413 //
7414 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7415
7416 const Register jdx = tmp1;
7417
7418 bind(L_second_loop);
7419 xorl(carry, carry); // carry = 0;
7420 movl(jdx, ylen); // j = ystart+1
7421
7422 subl(xstart, 1); // i = xstart-1;
7423 jcc(Assembler::negative, L_done);
7424
7425 push (z);
7426
7427 Label L_last_x;
7428 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7429 subl(xstart, 1); // i = xstart-1;
7430 jcc(Assembler::negative, L_last_x);
7431
7432 if (UseBMI2Instructions) {
7433 movq(rdx, Address(x, xstart, Address::times_4, 0));
7434 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7435 } else {
7436 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7437 rorq(x_xstart, 32); // convert big-endian to little-endian
7438 }
7439
7440 Label L_third_loop_prologue;
7441 bind(L_third_loop_prologue);
7442
7443 push (x);
7444 push (xstart);
7445 push (ylen);
7446
7447
7448 if (UseBMI2Instructions) {
7449 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7450 } else { // !UseBMI2Instructions
7451 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7452 }
7453
7454 pop(ylen);
7455 pop(xlen);
7456 pop(x);
7457 pop(z);
7458
7459 movl(tmp3, xlen);
7460 addl(tmp3, 1);
7461 movl(Address(z, tmp3, Address::times_4, 0), carry);
7462 subl(tmp3, 1);
7463 jccb(Assembler::negative, L_done);
7464
7465 shrq(carry, 32);
7466 movl(Address(z, tmp3, Address::times_4, 0), carry);
7467 jmp(L_second_loop);
7468
7469 // Next infrequent code is moved outside loops.
7470 bind(L_last_x);
7471 if (UseBMI2Instructions) {
7472 movl(rdx, Address(x, 0));
7473 } else {
7474 movl(x_xstart, Address(x, 0));
7475 }
7476 jmp(L_third_loop_prologue);
7477
7478 bind(L_done);
7479
7480 pop(xlen);
7481
7482 pop(tmp5);
7483 pop(tmp4);
7484 pop(tmp3);
7485 pop(tmp2);
7486 pop(tmp1);
7487 pop(tmp0);
7488 }
7489
7490 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7491 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7492 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7493 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7494 Label VECTOR8_TAIL, VECTOR4_TAIL;
7495 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7496 Label SAME_TILL_END, DONE;
7497 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7498
7499 //scale is in rcx in both Win64 and Unix
7500 ShortBranchVerifier sbv(this);
7501
7502 shlq(length);
7503 xorq(result, result);
7504
7505 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7506 VM_Version::supports_avx512vlbw()) {
7507 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7508
7509 cmpq(length, 64);
7510 jcc(Assembler::less, VECTOR32_TAIL);
7511
7512 movq(tmp1, length);
7513 andq(tmp1, 0x3F); // tail count
7514 andq(length, ~(0x3F)); //vector count
7515
7516 bind(VECTOR64_LOOP);
7517 // AVX512 code to compare 64 byte vectors.
7518 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7519 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7520 kortestql(k7, k7);
7521 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7522 addq(result, 64);
7523 subq(length, 64);
7524 jccb(Assembler::notZero, VECTOR64_LOOP);
7525
7526 //bind(VECTOR64_TAIL);
7527 testq(tmp1, tmp1);
7528 jcc(Assembler::zero, SAME_TILL_END);
7529
7530 //bind(VECTOR64_TAIL);
7531 // AVX512 code to compare up to 63 byte vectors.
7532 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7533 shlxq(tmp2, tmp2, tmp1);
7534 notq(tmp2);
7535 kmovql(k3, tmp2);
7536
7537 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7538 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7539
7540 ktestql(k7, k3);
7541 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7542
7543 bind(VECTOR64_NOT_EQUAL);
7544 kmovql(tmp1, k7);
7545 notq(tmp1);
7546 tzcntq(tmp1, tmp1);
7547 addq(result, tmp1);
7548 shrq(result);
7549 jmp(DONE);
7550 bind(VECTOR32_TAIL);
7551 }
7552
7553 cmpq(length, 8);
7554 jcc(Assembler::equal, VECTOR8_LOOP);
7555 jcc(Assembler::less, VECTOR4_TAIL);
7556
7557 if (UseAVX >= 2) {
7558 Label VECTOR16_TAIL, VECTOR32_LOOP;
7559
7560 cmpq(length, 16);
7561 jcc(Assembler::equal, VECTOR16_LOOP);
7562 jcc(Assembler::less, VECTOR8_LOOP);
7563
7564 cmpq(length, 32);
7565 jccb(Assembler::less, VECTOR16_TAIL);
7566
7567 subq(length, 32);
7568 bind(VECTOR32_LOOP);
7569 vmovdqu(rymm0, Address(obja, result));
7570 vmovdqu(rymm1, Address(objb, result));
7571 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7572 vptest(rymm2, rymm2);
7573 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7574 addq(result, 32);
7575 subq(length, 32);
7576 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7577 addq(length, 32);
7578 jcc(Assembler::equal, SAME_TILL_END);
7579 //falling through if less than 32 bytes left //close the branch here.
7580
7581 bind(VECTOR16_TAIL);
7582 cmpq(length, 16);
7583 jccb(Assembler::less, VECTOR8_TAIL);
7584 bind(VECTOR16_LOOP);
7585 movdqu(rymm0, Address(obja, result));
7586 movdqu(rymm1, Address(objb, result));
7587 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7588 ptest(rymm2, rymm2);
7589 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7590 addq(result, 16);
7591 subq(length, 16);
7592 jcc(Assembler::equal, SAME_TILL_END);
7593 //falling through if less than 16 bytes left
7594 } else {//regular intrinsics
7595
7596 cmpq(length, 16);
7597 jccb(Assembler::less, VECTOR8_TAIL);
7598
7599 subq(length, 16);
7600 bind(VECTOR16_LOOP);
7601 movdqu(rymm0, Address(obja, result));
7602 movdqu(rymm1, Address(objb, result));
7603 pxor(rymm0, rymm1);
7604 ptest(rymm0, rymm0);
7605 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7606 addq(result, 16);
7607 subq(length, 16);
7608 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7609 addq(length, 16);
7610 jcc(Assembler::equal, SAME_TILL_END);
7611 //falling through if less than 16 bytes left
7612 }
7613
7614 bind(VECTOR8_TAIL);
7615 cmpq(length, 8);
7616 jccb(Assembler::less, VECTOR4_TAIL);
7617 bind(VECTOR8_LOOP);
7618 movq(tmp1, Address(obja, result));
7619 movq(tmp2, Address(objb, result));
7620 xorq(tmp1, tmp2);
7621 testq(tmp1, tmp1);
7622 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7623 addq(result, 8);
7624 subq(length, 8);
7625 jcc(Assembler::equal, SAME_TILL_END);
7626 //falling through if less than 8 bytes left
7627
7628 bind(VECTOR4_TAIL);
7629 cmpq(length, 4);
7630 jccb(Assembler::less, BYTES_TAIL);
7631 bind(VECTOR4_LOOP);
7632 movl(tmp1, Address(obja, result));
7633 xorl(tmp1, Address(objb, result));
7634 testl(tmp1, tmp1);
7635 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7636 addq(result, 4);
7637 subq(length, 4);
7638 jcc(Assembler::equal, SAME_TILL_END);
7639 //falling through if less than 4 bytes left
7640
7641 bind(BYTES_TAIL);
7642 bind(BYTES_LOOP);
7643 load_unsigned_byte(tmp1, Address(obja, result));
7644 load_unsigned_byte(tmp2, Address(objb, result));
7645 xorl(tmp1, tmp2);
7646 testl(tmp1, tmp1);
7647 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7648 decq(length);
7649 jcc(Assembler::zero, SAME_TILL_END);
7650 incq(result);
7651 load_unsigned_byte(tmp1, Address(obja, result));
7652 load_unsigned_byte(tmp2, Address(objb, result));
7653 xorl(tmp1, tmp2);
7654 testl(tmp1, tmp1);
7655 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7656 decq(length);
7657 jcc(Assembler::zero, SAME_TILL_END);
7658 incq(result);
7659 load_unsigned_byte(tmp1, Address(obja, result));
7660 load_unsigned_byte(tmp2, Address(objb, result));
7661 xorl(tmp1, tmp2);
7662 testl(tmp1, tmp1);
7663 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7664 jmp(SAME_TILL_END);
7665
7666 if (UseAVX >= 2) {
7667 bind(VECTOR32_NOT_EQUAL);
7668 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7669 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7670 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7671 vpmovmskb(tmp1, rymm0);
7672 bsfq(tmp1, tmp1);
7673 addq(result, tmp1);
7674 shrq(result);
7675 jmp(DONE);
7676 }
7677
7678 bind(VECTOR16_NOT_EQUAL);
7679 if (UseAVX >= 2) {
7680 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7681 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7682 pxor(rymm0, rymm2);
7683 } else {
7684 pcmpeqb(rymm2, rymm2);
7685 pxor(rymm0, rymm1);
7686 pcmpeqb(rymm0, rymm1);
7687 pxor(rymm0, rymm2);
7688 }
7689 pmovmskb(tmp1, rymm0);
7690 bsfq(tmp1, tmp1);
7691 addq(result, tmp1);
7692 shrq(result);
7693 jmpb(DONE);
7694
7695 bind(VECTOR8_NOT_EQUAL);
7696 bind(VECTOR4_NOT_EQUAL);
7697 bsfq(tmp1, tmp1);
7698 shrq(tmp1, 3);
7699 addq(result, tmp1);
7700 bind(BYTES_NOT_EQUAL);
7701 shrq(result);
7702 jmpb(DONE);
7703
7704 bind(SAME_TILL_END);
7705 mov64(result, -1);
7706
7707 bind(DONE);
7708 }
7709
7710 //Helper functions for square_to_len()
7711
7712 /**
7713 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7714 * Preserves x and z and modifies rest of the registers.
7715 */
7716 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7717 // Perform square and right shift by 1
7718 // Handle odd xlen case first, then for even xlen do the following
7719 // jlong carry = 0;
7720 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7721 // huge_128 product = x[j:j+1] * x[j:j+1];
7722 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7723 // z[i+2:i+3] = (jlong)(product >>> 1);
7724 // carry = (jlong)product;
7725 // }
7726
7727 xorq(tmp5, tmp5); // carry
7728 xorq(rdxReg, rdxReg);
7729 xorl(tmp1, tmp1); // index for x
7730 xorl(tmp4, tmp4); // index for z
7731
7732 Label L_first_loop, L_first_loop_exit;
7733
7734 testl(xlen, 1);
7735 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7736
7737 // Square and right shift by 1 the odd element using 32 bit multiply
7738 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7739 imulq(raxReg, raxReg);
7740 shrq(raxReg, 1);
7741 adcq(tmp5, 0);
7742 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7743 incrementl(tmp1);
7744 addl(tmp4, 2);
7745
7746 // Square and right shift by 1 the rest using 64 bit multiply
7747 bind(L_first_loop);
7748 cmpptr(tmp1, xlen);
7749 jccb(Assembler::equal, L_first_loop_exit);
7750
7751 // Square
7752 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7753 rorq(raxReg, 32); // convert big-endian to little-endian
7754 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7755
7756 // Right shift by 1 and save carry
7757 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7758 rcrq(rdxReg, 1);
7759 rcrq(raxReg, 1);
7760 adcq(tmp5, 0);
7761
7762 // Store result in z
7763 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7764 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7765
7766 // Update indices for x and z
7767 addl(tmp1, 2);
7768 addl(tmp4, 4);
7769 jmp(L_first_loop);
7770
7771 bind(L_first_loop_exit);
7772 }
7773
7774
7775 /**
7776 * Perform the following multiply add operation using BMI2 instructions
7777 * carry:sum = sum + op1*op2 + carry
7778 * op2 should be in rdx
7779 * op2 is preserved, all other registers are modified
7780 */
7781 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7782 // assert op2 is rdx
7783 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7784 addq(sum, carry);
7785 adcq(tmp2, 0);
7786 addq(sum, op1);
7787 adcq(tmp2, 0);
7788 movq(carry, tmp2);
7789 }
7790
7791 /**
7792 * Perform the following multiply add operation:
7793 * carry:sum = sum + op1*op2 + carry
7794 * Preserves op1, op2 and modifies rest of registers
7795 */
7796 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7797 // rdx:rax = op1 * op2
7798 movq(raxReg, op2);
7799 mulq(op1);
7800
7801 // rdx:rax = sum + carry + rdx:rax
7802 addq(sum, carry);
7803 adcq(rdxReg, 0);
7804 addq(sum, raxReg);
7805 adcq(rdxReg, 0);
7806
7807 // carry:sum = rdx:sum
7808 movq(carry, rdxReg);
7809 }
7810
7811 /**
7812 * Add 64 bit long carry into z[] with carry propagation.
7813 * Preserves z and carry register values and modifies rest of registers.
7814 *
7815 */
7816 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7817 Label L_fourth_loop, L_fourth_loop_exit;
7818
7819 movl(tmp1, 1);
7820 subl(zlen, 2);
7821 addq(Address(z, zlen, Address::times_4, 0), carry);
7822
7823 bind(L_fourth_loop);
7824 jccb(Assembler::carryClear, L_fourth_loop_exit);
7825 subl(zlen, 2);
7826 jccb(Assembler::negative, L_fourth_loop_exit);
7827 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7828 jmp(L_fourth_loop);
7829 bind(L_fourth_loop_exit);
7830 }
7831
7832 /**
7833 * Shift z[] left by 1 bit.
7834 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7835 *
7836 */
7837 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7838
7839 Label L_fifth_loop, L_fifth_loop_exit;
7840
7841 // Fifth loop
7842 // Perform primitiveLeftShift(z, zlen, 1)
7843
7844 const Register prev_carry = tmp1;
7845 const Register new_carry = tmp4;
7846 const Register value = tmp2;
7847 const Register zidx = tmp3;
7848
7849 // int zidx, carry;
7850 // long value;
7851 // carry = 0;
7852 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7853 // (carry:value) = (z[i] << 1) | carry ;
7854 // z[i] = value;
7855 // }
7856
7857 movl(zidx, zlen);
7858 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7859
7860 bind(L_fifth_loop);
7861 decl(zidx); // Use decl to preserve carry flag
7862 decl(zidx);
7863 jccb(Assembler::negative, L_fifth_loop_exit);
7864
7865 if (UseBMI2Instructions) {
7866 movq(value, Address(z, zidx, Address::times_4, 0));
7867 rclq(value, 1);
7868 rorxq(value, value, 32);
7869 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7870 }
7871 else {
7872 // clear new_carry
7873 xorl(new_carry, new_carry);
7874
7875 // Shift z[i] by 1, or in previous carry and save new carry
7876 movq(value, Address(z, zidx, Address::times_4, 0));
7877 shlq(value, 1);
7878 adcl(new_carry, 0);
7879
7880 orq(value, prev_carry);
7881 rorq(value, 0x20);
7882 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7883
7884 // Set previous carry = new carry
7885 movl(prev_carry, new_carry);
7886 }
7887 jmp(L_fifth_loop);
7888
7889 bind(L_fifth_loop_exit);
7890 }
7891
7892
7893 /**
7894 * Code for BigInteger::squareToLen() intrinsic
7895 *
7896 * rdi: x
7897 * rsi: len
7898 * r8: z
7899 * rcx: zlen
7900 * r12: tmp1
7901 * r13: tmp2
7902 * r14: tmp3
7903 * r15: tmp4
7904 * rbx: tmp5
7905 *
7906 */
7907 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7908
7909 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
7910 push(tmp1);
7911 push(tmp2);
7912 push(tmp3);
7913 push(tmp4);
7914 push(tmp5);
7915
7916 // First loop
7917 // Store the squares, right shifted one bit (i.e., divided by 2).
7918 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7919
7920 // Add in off-diagonal sums.
7921 //
7922 // Second, third (nested) and fourth loops.
7923 // zlen +=2;
7924 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7925 // carry = 0;
7926 // long op2 = x[xidx:xidx+1];
7927 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7928 // k -= 2;
7929 // long op1 = x[j:j+1];
7930 // long sum = z[k:k+1];
7931 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7932 // z[k:k+1] = sum;
7933 // }
7934 // add_one_64(z, k, carry, tmp_regs);
7935 // }
7936
7937 const Register carry = tmp5;
7938 const Register sum = tmp3;
7939 const Register op1 = tmp4;
7940 Register op2 = tmp2;
7941
7942 push(zlen);
7943 push(len);
7944 addl(zlen,2);
7945 bind(L_second_loop);
7946 xorq(carry, carry);
7947 subl(zlen, 4);
7948 subl(len, 2);
7949 push(zlen);
7950 push(len);
7951 cmpl(len, 0);
7952 jccb(Assembler::lessEqual, L_second_loop_exit);
7953
7954 // Multiply an array by one 64 bit long.
7955 if (UseBMI2Instructions) {
7956 op2 = rdxReg;
7957 movq(op2, Address(x, len, Address::times_4, 0));
7958 rorxq(op2, op2, 32);
7959 }
7960 else {
7961 movq(op2, Address(x, len, Address::times_4, 0));
7962 rorq(op2, 32);
7963 }
7964
7965 bind(L_third_loop);
7966 decrementl(len);
7967 jccb(Assembler::negative, L_third_loop_exit);
7968 decrementl(len);
7969 jccb(Assembler::negative, L_last_x);
7970
7971 movq(op1, Address(x, len, Address::times_4, 0));
7972 rorq(op1, 32);
7973
7974 bind(L_multiply);
7975 subl(zlen, 2);
7976 movq(sum, Address(z, zlen, Address::times_4, 0));
7977
7978 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
7979 if (UseBMI2Instructions) {
7980 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
7981 }
7982 else {
7983 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7984 }
7985
7986 movq(Address(z, zlen, Address::times_4, 0), sum);
7987
7988 jmp(L_third_loop);
7989 bind(L_third_loop_exit);
7990
7991 // Fourth loop
7992 // Add 64 bit long carry into z with carry propagation.
7993 // Uses offsetted zlen.
7994 add_one_64(z, zlen, carry, tmp1);
7995
7996 pop(len);
7997 pop(zlen);
7998 jmp(L_second_loop);
7999
8000 // Next infrequent code is moved outside loops.
8001 bind(L_last_x);
8002 movl(op1, Address(x, 0));
8003 jmp(L_multiply);
8004
8005 bind(L_second_loop_exit);
8006 pop(len);
8007 pop(zlen);
8008 pop(len);
8009 pop(zlen);
8010
8011 // Fifth loop
8012 // Shift z left 1 bit.
8013 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8014
8015 // z[zlen-1] |= x[len-1] & 1;
8016 movl(tmp3, Address(x, len, Address::times_4, -4));
8017 andl(tmp3, 1);
8018 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8019
8020 pop(tmp5);
8021 pop(tmp4);
8022 pop(tmp3);
8023 pop(tmp2);
8024 pop(tmp1);
8025 }
8026
8027 /**
8028 * Helper function for mul_add()
8029 * Multiply the in[] by int k and add to out[] starting at offset offs using
8030 * 128 bit by 32 bit multiply and return the carry in tmp5.
8031 * Only quad int aligned length of in[] is operated on in this function.
8032 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8033 * This function preserves out, in and k registers.
8034 * len and offset point to the appropriate index in "in" & "out" correspondingly
8035 * tmp5 has the carry.
8036 * other registers are temporary and are modified.
8037 *
8038 */
8039 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8040 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8041 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8042
8043 Label L_first_loop, L_first_loop_exit;
8044
8045 movl(tmp1, len);
8046 shrl(tmp1, 2);
8047
8048 bind(L_first_loop);
8049 subl(tmp1, 1);
8050 jccb(Assembler::negative, L_first_loop_exit);
8051
8052 subl(len, 4);
8053 subl(offset, 4);
8054
8055 Register op2 = tmp2;
8056 const Register sum = tmp3;
8057 const Register op1 = tmp4;
8058 const Register carry = tmp5;
8059
8060 if (UseBMI2Instructions) {
8061 op2 = rdxReg;
8062 }
8063
8064 movq(op1, Address(in, len, Address::times_4, 8));
8065 rorq(op1, 32);
8066 movq(sum, Address(out, offset, Address::times_4, 8));
8067 rorq(sum, 32);
8068 if (UseBMI2Instructions) {
8069 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8070 }
8071 else {
8072 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8073 }
8074 // Store back in big endian from little endian
8075 rorq(sum, 0x20);
8076 movq(Address(out, offset, Address::times_4, 8), sum);
8077
8078 movq(op1, Address(in, len, Address::times_4, 0));
8079 rorq(op1, 32);
8080 movq(sum, Address(out, offset, Address::times_4, 0));
8081 rorq(sum, 32);
8082 if (UseBMI2Instructions) {
8083 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8084 }
8085 else {
8086 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8087 }
8088 // Store back in big endian from little endian
8089 rorq(sum, 0x20);
8090 movq(Address(out, offset, Address::times_4, 0), sum);
8091
8092 jmp(L_first_loop);
8093 bind(L_first_loop_exit);
8094 }
8095
8096 /**
8097 * Code for BigInteger::mulAdd() intrinsic
8098 *
8099 * rdi: out
8100 * rsi: in
8101 * r11: offs (out.length - offset)
8102 * rcx: len
8103 * r8: k
8104 * r12: tmp1
8105 * r13: tmp2
8106 * r14: tmp3
8107 * r15: tmp4
8108 * rbx: tmp5
8109 * Multiply the in[] by word k and add to out[], return the carry in rax
8110 */
8111 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8112 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8113 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8114
8115 Label L_carry, L_last_in, L_done;
8116
8117 // carry = 0;
8118 // for (int j=len-1; j >= 0; j--) {
8119 // long product = (in[j] & LONG_MASK) * kLong +
8120 // (out[offs] & LONG_MASK) + carry;
8121 // out[offs--] = (int)product;
8122 // carry = product >>> 32;
8123 // }
8124 //
8125 push(tmp1);
8126 push(tmp2);
8127 push(tmp3);
8128 push(tmp4);
8129 push(tmp5);
8130
8131 Register op2 = tmp2;
8132 const Register sum = tmp3;
8133 const Register op1 = tmp4;
8134 const Register carry = tmp5;
8135
8136 if (UseBMI2Instructions) {
8137 op2 = rdxReg;
8138 movl(op2, k);
8139 }
8140 else {
8141 movl(op2, k);
8142 }
8143
8144 xorq(carry, carry);
8145
8146 //First loop
8147
8148 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8149 //The carry is in tmp5
8150 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8151
8152 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8153 decrementl(len);
8154 jccb(Assembler::negative, L_carry);
8155 decrementl(len);
8156 jccb(Assembler::negative, L_last_in);
8157
8158 movq(op1, Address(in, len, Address::times_4, 0));
8159 rorq(op1, 32);
8160
8161 subl(offs, 2);
8162 movq(sum, Address(out, offs, Address::times_4, 0));
8163 rorq(sum, 32);
8164
8165 if (UseBMI2Instructions) {
8166 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8167 }
8168 else {
8169 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8170 }
8171
8172 // Store back in big endian from little endian
8173 rorq(sum, 0x20);
8174 movq(Address(out, offs, Address::times_4, 0), sum);
8175
8176 testl(len, len);
8177 jccb(Assembler::zero, L_carry);
8178
8179 //Multiply the last in[] entry, if any
8180 bind(L_last_in);
8181 movl(op1, Address(in, 0));
8182 movl(sum, Address(out, offs, Address::times_4, -4));
8183
8184 movl(raxReg, k);
8185 mull(op1); //tmp4 * eax -> edx:eax
8186 addl(sum, carry);
8187 adcl(rdxReg, 0);
8188 addl(sum, raxReg);
8189 adcl(rdxReg, 0);
8190 movl(carry, rdxReg);
8191
8192 movl(Address(out, offs, Address::times_4, -4), sum);
8193
8194 bind(L_carry);
8195 //return tmp5/carry as carry in rax
8196 movl(rax, carry);
8197
8198 bind(L_done);
8199 pop(tmp5);
8200 pop(tmp4);
8201 pop(tmp3);
8202 pop(tmp2);
8203 pop(tmp1);
8204 }
8205 #endif
8206
8207 /**
8208 * Emits code to update CRC-32 with a byte value according to constants in table
8209 *
8210 * @param [in,out]crc Register containing the crc.
8211 * @param [in]val Register containing the byte to fold into the CRC.
8212 * @param [in]table Register containing the table of crc constants.
8213 *
8214 * uint32_t crc;
8215 * val = crc_table[(val ^ crc) & 0xFF];
8216 * crc = val ^ (crc >> 8);
8217 *
8218 */
8219 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8220 xorl(val, crc);
8221 andl(val, 0xFF);
8222 shrl(crc, 8); // unsigned shift
8223 xorl(crc, Address(table, val, Address::times_4, 0));
8224 }
8225
8226 /**
8227 * Fold 128-bit data chunk
8228 */
8229 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8230 if (UseAVX > 0) {
8231 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8232 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8233 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8234 pxor(xcrc, xtmp);
8235 } else {
8236 movdqa(xtmp, xcrc);
8237 pclmulhdq(xtmp, xK); // [123:64]
8238 pclmulldq(xcrc, xK); // [63:0]
8239 pxor(xcrc, xtmp);
8240 movdqu(xtmp, Address(buf, offset));
8241 pxor(xcrc, xtmp);
8242 }
8243 }
8244
8245 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8246 if (UseAVX > 0) {
8247 vpclmulhdq(xtmp, xK, xcrc);
8248 vpclmulldq(xcrc, xK, xcrc);
8249 pxor(xcrc, xbuf);
8250 pxor(xcrc, xtmp);
8251 } else {
8252 movdqa(xtmp, xcrc);
8253 pclmulhdq(xtmp, xK);
8254 pclmulldq(xcrc, xK);
8255 pxor(xcrc, xbuf);
8256 pxor(xcrc, xtmp);
8257 }
8258 }
8259
8260 /**
8261 * 8-bit folds to compute 32-bit CRC
8262 *
8263 * uint64_t xcrc;
8264 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8265 */
8266 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8267 movdl(tmp, xcrc);
8268 andl(tmp, 0xFF);
8269 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8270 psrldq(xcrc, 1); // unsigned shift one byte
8271 pxor(xcrc, xtmp);
8272 }
8273
8274 /**
8275 * uint32_t crc;
8276 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8277 */
8278 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8279 movl(tmp, crc);
8280 andl(tmp, 0xFF);
8281 shrl(crc, 8);
8282 xorl(crc, Address(table, tmp, Address::times_4, 0));
8283 }
8284
8285 /**
8286 * @param crc register containing existing CRC (32-bit)
8287 * @param buf register pointing to input byte buffer (byte*)
8288 * @param len register containing number of bytes
8289 * @param table register that will contain address of CRC table
8290 * @param tmp scratch register
8291 */
8292 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8293 assert_different_registers(crc, buf, len, table, tmp, rax);
8294
8295 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8296 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8297
8298 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8299 // context for the registers used, where all instructions below are using 128-bit mode
8300 // On EVEX without VL and BW, these instructions will all be AVX.
8301 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8302 notl(crc); // ~crc
8303 cmpl(len, 16);
8304 jcc(Assembler::less, L_tail);
8305
8306 // Align buffer to 16 bytes
8307 movl(tmp, buf);
8308 andl(tmp, 0xF);
8309 jccb(Assembler::zero, L_aligned);
8310 subl(tmp, 16);
8311 addl(len, tmp);
8312
8313 align(4);
8314 BIND(L_align_loop);
8315 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8316 update_byte_crc32(crc, rax, table);
8317 increment(buf);
8318 incrementl(tmp);
8319 jccb(Assembler::less, L_align_loop);
8320
8321 BIND(L_aligned);
8322 movl(tmp, len); // save
8323 shrl(len, 4);
8324 jcc(Assembler::zero, L_tail_restore);
8325
8326 // Fold crc into first bytes of vector
8327 movdqa(xmm1, Address(buf, 0));
8328 movdl(rax, xmm1);
8329 xorl(crc, rax);
8330 if (VM_Version::supports_sse4_1()) {
8331 pinsrd(xmm1, crc, 0);
8332 } else {
8333 pinsrw(xmm1, crc, 0);
8334 shrl(crc, 16);
8335 pinsrw(xmm1, crc, 1);
8336 }
8337 addptr(buf, 16);
8338 subl(len, 4); // len > 0
8339 jcc(Assembler::less, L_fold_tail);
8340
8341 movdqa(xmm2, Address(buf, 0));
8342 movdqa(xmm3, Address(buf, 16));
8343 movdqa(xmm4, Address(buf, 32));
8344 addptr(buf, 48);
8345 subl(len, 3);
8346 jcc(Assembler::lessEqual, L_fold_512b);
8347
8348 // Fold total 512 bits of polynomial on each iteration,
8349 // 128 bits per each of 4 parallel streams.
8350 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8351
8352 align32();
8353 BIND(L_fold_512b_loop);
8354 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8355 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8356 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8357 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8358 addptr(buf, 64);
8359 subl(len, 4);
8360 jcc(Assembler::greater, L_fold_512b_loop);
8361
8362 // Fold 512 bits to 128 bits.
8363 BIND(L_fold_512b);
8364 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8365 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8366 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8367 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8368
8369 // Fold the rest of 128 bits data chunks
8370 BIND(L_fold_tail);
8371 addl(len, 3);
8372 jccb(Assembler::lessEqual, L_fold_128b);
8373 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8374
8375 BIND(L_fold_tail_loop);
8376 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8377 addptr(buf, 16);
8378 decrementl(len);
8379 jccb(Assembler::greater, L_fold_tail_loop);
8380
8381 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8382 BIND(L_fold_128b);
8383 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8384 if (UseAVX > 0) {
8385 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8386 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8387 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8388 } else {
8389 movdqa(xmm2, xmm0);
8390 pclmulqdq(xmm2, xmm1, 0x1);
8391 movdqa(xmm3, xmm0);
8392 pand(xmm3, xmm2);
8393 pclmulqdq(xmm0, xmm3, 0x1);
8394 }
8395 psrldq(xmm1, 8);
8396 psrldq(xmm2, 4);
8397 pxor(xmm0, xmm1);
8398 pxor(xmm0, xmm2);
8399
8400 // 8 8-bit folds to compute 32-bit CRC.
8401 for (int j = 0; j < 4; j++) {
8402 fold_8bit_crc32(xmm0, table, xmm1, rax);
8403 }
8404 movdl(crc, xmm0); // mov 32 bits to general register
8405 for (int j = 0; j < 4; j++) {
8406 fold_8bit_crc32(crc, table, rax);
8407 }
8408
8409 BIND(L_tail_restore);
8410 movl(len, tmp); // restore
8411 BIND(L_tail);
8412 andl(len, 0xf);
8413 jccb(Assembler::zero, L_exit);
8414
8415 // Fold the rest of bytes
8416 align(4);
8417 BIND(L_tail_loop);
8418 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8419 update_byte_crc32(crc, rax, table);
8420 increment(buf);
8421 decrementl(len);
8422 jccb(Assembler::greater, L_tail_loop);
8423
8424 BIND(L_exit);
8425 notl(crc); // ~c
8426 }
8427
8428 #ifdef _LP64
8429 // Helper function for AVX 512 CRC32
8430 // Fold 512-bit data chunks
8431 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8432 Register pos, int offset) {
8433 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8434 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8435 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8436 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8437 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8438 }
8439
8440 // Helper function for AVX 512 CRC32
8441 // Compute CRC32 for < 256B buffers
8442 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8443 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8444 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8445
8446 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8447 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8448 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8449
8450 // check if there is enough buffer to be able to fold 16B at a time
8451 cmpl(len, 32);
8452 jcc(Assembler::less, L_less_than_32);
8453
8454 // if there is, load the constants
8455 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8456 movdl(xmm0, crc); // get the initial crc value
8457 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8458 pxor(xmm7, xmm0);
8459
8460 // update the buffer pointer
8461 addl(pos, 16);
8462 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8463 subl(len, 32);
8464 jmp(L_16B_reduction_loop);
8465
8466 bind(L_less_than_32);
8467 //mov initial crc to the return value. this is necessary for zero - length buffers.
8468 movl(rax, crc);
8469 testl(len, len);
8470 jcc(Assembler::equal, L_cleanup);
8471
8472 movdl(xmm0, crc); //get the initial crc value
8473
8474 cmpl(len, 16);
8475 jcc(Assembler::equal, L_exact_16_left);
8476 jcc(Assembler::less, L_less_than_16_left);
8477
8478 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8479 pxor(xmm7, xmm0); //xor the initial crc value
8480 addl(pos, 16);
8481 subl(len, 16);
8482 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8483 jmp(L_get_last_two_xmms);
8484
8485 bind(L_less_than_16_left);
8486 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8487 pxor(xmm1, xmm1);
8488 movptr(tmp1, rsp);
8489 movdqu(Address(tmp1, 0 * 16), xmm1);
8490
8491 cmpl(len, 4);
8492 jcc(Assembler::less, L_only_less_than_4);
8493
8494 //backup the counter value
8495 movl(tmp2, len);
8496 cmpl(len, 8);
8497 jcc(Assembler::less, L_less_than_8_left);
8498
8499 //load 8 Bytes
8500 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8501 movq(Address(tmp1, 0 * 16), rax);
8502 addptr(tmp1, 8);
8503 subl(len, 8);
8504 addl(pos, 8);
8505
8506 bind(L_less_than_8_left);
8507 cmpl(len, 4);
8508 jcc(Assembler::less, L_less_than_4_left);
8509
8510 //load 4 Bytes
8511 movl(rax, Address(buf, pos, Address::times_1, 0));
8512 movl(Address(tmp1, 0 * 16), rax);
8513 addptr(tmp1, 4);
8514 subl(len, 4);
8515 addl(pos, 4);
8516
8517 bind(L_less_than_4_left);
8518 cmpl(len, 2);
8519 jcc(Assembler::less, L_less_than_2_left);
8520
8521 // load 2 Bytes
8522 movw(rax, Address(buf, pos, Address::times_1, 0));
8523 movl(Address(tmp1, 0 * 16), rax);
8524 addptr(tmp1, 2);
8525 subl(len, 2);
8526 addl(pos, 2);
8527
8528 bind(L_less_than_2_left);
8529 cmpl(len, 1);
8530 jcc(Assembler::less, L_zero_left);
8531
8532 // load 1 Byte
8533 movb(rax, Address(buf, pos, Address::times_1, 0));
8534 movb(Address(tmp1, 0 * 16), rax);
8535
8536 bind(L_zero_left);
8537 movdqu(xmm7, Address(rsp, 0));
8538 pxor(xmm7, xmm0); //xor the initial crc value
8539
8540 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8541 movdqu(xmm0, Address(rax, tmp2));
8542 pshufb(xmm7, xmm0);
8543 jmp(L_128_done);
8544
8545 bind(L_exact_16_left);
8546 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8547 pxor(xmm7, xmm0); //xor the initial crc value
8548 jmp(L_128_done);
8549
8550 bind(L_only_less_than_4);
8551 cmpl(len, 3);
8552 jcc(Assembler::less, L_only_less_than_3);
8553
8554 // load 3 Bytes
8555 movb(rax, Address(buf, pos, Address::times_1, 0));
8556 movb(Address(tmp1, 0), rax);
8557
8558 movb(rax, Address(buf, pos, Address::times_1, 1));
8559 movb(Address(tmp1, 1), rax);
8560
8561 movb(rax, Address(buf, pos, Address::times_1, 2));
8562 movb(Address(tmp1, 2), rax);
8563
8564 movdqu(xmm7, Address(rsp, 0));
8565 pxor(xmm7, xmm0); //xor the initial crc value
8566
8567 pslldq(xmm7, 0x5);
8568 jmp(L_barrett);
8569 bind(L_only_less_than_3);
8570 cmpl(len, 2);
8571 jcc(Assembler::less, L_only_less_than_2);
8572
8573 // load 2 Bytes
8574 movb(rax, Address(buf, pos, Address::times_1, 0));
8575 movb(Address(tmp1, 0), rax);
8576
8577 movb(rax, Address(buf, pos, Address::times_1, 1));
8578 movb(Address(tmp1, 1), rax);
8579
8580 movdqu(xmm7, Address(rsp, 0));
8581 pxor(xmm7, xmm0); //xor the initial crc value
8582
8583 pslldq(xmm7, 0x6);
8584 jmp(L_barrett);
8585
8586 bind(L_only_less_than_2);
8587 //load 1 Byte
8588 movb(rax, Address(buf, pos, Address::times_1, 0));
8589 movb(Address(tmp1, 0), rax);
8590
8591 movdqu(xmm7, Address(rsp, 0));
8592 pxor(xmm7, xmm0); //xor the initial crc value
8593
8594 pslldq(xmm7, 0x7);
8595 }
8596
8597 /**
8598 * Compute CRC32 using AVX512 instructions
8599 * param crc register containing existing CRC (32-bit)
8600 * param buf register pointing to input byte buffer (byte*)
8601 * param len register containing number of bytes
8602 * param table address of crc or crc32c table
8603 * param tmp1 scratch register
8604 * param tmp2 scratch register
8605 * return rax result register
8606 *
8607 * This routine is identical for crc32c with the exception of the precomputed constant
8608 * table which will be passed as the table argument. The calculation steps are
8609 * the same for both variants.
8610 */
8611 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8612 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8613
8614 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8615 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8616 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8617 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8618 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8619
8620 const Register pos = r12;
8621 push(r12);
8622 subptr(rsp, 16 * 2 + 8);
8623
8624 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8625 // context for the registers used, where all instructions below are using 128-bit mode
8626 // On EVEX without VL and BW, these instructions will all be AVX.
8627 movl(pos, 0);
8628
8629 // check if smaller than 256B
8630 cmpl(len, 256);
8631 jcc(Assembler::less, L_less_than_256);
8632
8633 // load the initial crc value
8634 movdl(xmm10, crc);
8635
8636 // receive the initial 64B data, xor the initial crc value
8637 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8638 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8639 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8640 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8641
8642 subl(len, 256);
8643 cmpl(len, 256);
8644 jcc(Assembler::less, L_fold_128_B_loop);
8645
8646 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8647 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8648 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8649 subl(len, 256);
8650
8651 bind(L_fold_256_B_loop);
8652 addl(pos, 256);
8653 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8654 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8655 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8656 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8657
8658 subl(len, 256);
8659 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8660
8661 // Fold 256 into 128
8662 addl(pos, 256);
8663 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8664 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8665 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8666
8667 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8668 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8669 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8670
8671 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8672 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8673
8674 addl(len, 128);
8675 jmp(L_fold_128_B_register);
8676
8677 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8678 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8679
8680 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8681 bind(L_fold_128_B_loop);
8682 addl(pos, 128);
8683 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8684 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8685
8686 subl(len, 128);
8687 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8688
8689 addl(pos, 128);
8690
8691 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8692 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8693 bind(L_fold_128_B_register);
8694 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8695 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8696 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8697 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8698 // save last that has no multiplicand
8699 vextracti64x2(xmm7, xmm4, 3);
8700
8701 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8702 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8703 // Needed later in reduction loop
8704 movdqu(xmm10, Address(table, 1 * 16));
8705 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8706 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8707
8708 // Swap 1,0,3,2 - 01 00 11 10
8709 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8710 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8711 vextracti128(xmm5, xmm8, 1);
8712 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8713
8714 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8715 // instead of a cmp instruction, we use the negative flag with the jl instruction
8716 addl(len, 128 - 16);
8717 jcc(Assembler::less, L_final_reduction_for_128);
8718
8719 bind(L_16B_reduction_loop);
8720 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8721 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8722 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8723 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8724 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8725 addl(pos, 16);
8726 subl(len, 16);
8727 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8728
8729 bind(L_final_reduction_for_128);
8730 addl(len, 16);
8731 jcc(Assembler::equal, L_128_done);
8732
8733 bind(L_get_last_two_xmms);
8734 movdqu(xmm2, xmm7);
8735 addl(pos, len);
8736 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8737 subl(pos, len);
8738
8739 // get rid of the extra data that was loaded before
8740 // load the shift constant
8741 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8742 movdqu(xmm0, Address(rax, len));
8743 addl(rax, len);
8744
8745 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8746 //Change mask to 512
8747 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8748 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8749
8750 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8751 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8752 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8753 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8754 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8755
8756 bind(L_128_done);
8757 // compute crc of a 128-bit value
8758 movdqu(xmm10, Address(table, 3 * 16));
8759 movdqu(xmm0, xmm7);
8760
8761 // 64b fold
8762 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8763 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8764 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8765
8766 // 32b fold
8767 movdqu(xmm0, xmm7);
8768 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8769 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8770 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8771 jmp(L_barrett);
8772
8773 bind(L_less_than_256);
8774 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8775
8776 //barrett reduction
8777 bind(L_barrett);
8778 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8779 movdqu(xmm1, xmm7);
8780 movdqu(xmm2, xmm7);
8781 movdqu(xmm10, Address(table, 4 * 16));
8782
8783 pclmulqdq(xmm7, xmm10, 0x0);
8784 pxor(xmm7, xmm2);
8785 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8786 movdqu(xmm2, xmm7);
8787 pclmulqdq(xmm7, xmm10, 0x10);
8788 pxor(xmm7, xmm2);
8789 pxor(xmm7, xmm1);
8790 pextrd(crc, xmm7, 2);
8791
8792 bind(L_cleanup);
8793 addptr(rsp, 16 * 2 + 8);
8794 pop(r12);
8795 }
8796
8797 // S. Gueron / Information Processing Letters 112 (2012) 184
8798 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8799 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8800 // Output: the 64-bit carry-less product of B * CONST
8801 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8802 Register tmp1, Register tmp2, Register tmp3) {
8803 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8804 if (n > 0) {
8805 addq(tmp3, n * 256 * 8);
8806 }
8807 // Q1 = TABLEExt[n][B & 0xFF];
8808 movl(tmp1, in);
8809 andl(tmp1, 0x000000FF);
8810 shll(tmp1, 3);
8811 addq(tmp1, tmp3);
8812 movq(tmp1, Address(tmp1, 0));
8813
8814 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8815 movl(tmp2, in);
8816 shrl(tmp2, 8);
8817 andl(tmp2, 0x000000FF);
8818 shll(tmp2, 3);
8819 addq(tmp2, tmp3);
8820 movq(tmp2, Address(tmp2, 0));
8821
8822 shlq(tmp2, 8);
8823 xorq(tmp1, tmp2);
8824
8825 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8826 movl(tmp2, in);
8827 shrl(tmp2, 16);
8828 andl(tmp2, 0x000000FF);
8829 shll(tmp2, 3);
8830 addq(tmp2, tmp3);
8831 movq(tmp2, Address(tmp2, 0));
8832
8833 shlq(tmp2, 16);
8834 xorq(tmp1, tmp2);
8835
8836 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8837 shrl(in, 24);
8838 andl(in, 0x000000FF);
8839 shll(in, 3);
8840 addq(in, tmp3);
8841 movq(in, Address(in, 0));
8842
8843 shlq(in, 24);
8844 xorq(in, tmp1);
8845 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8846 }
8847
8848 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8849 Register in_out,
8850 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8851 XMMRegister w_xtmp2,
8852 Register tmp1,
8853 Register n_tmp2, Register n_tmp3) {
8854 if (is_pclmulqdq_supported) {
8855 movdl(w_xtmp1, in_out); // modified blindly
8856
8857 movl(tmp1, const_or_pre_comp_const_index);
8858 movdl(w_xtmp2, tmp1);
8859 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8860
8861 movdq(in_out, w_xtmp1);
8862 } else {
8863 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8864 }
8865 }
8866
8867 // Recombination Alternative 2: No bit-reflections
8868 // T1 = (CRC_A * U1) << 1
8869 // T2 = (CRC_B * U2) << 1
8870 // C1 = T1 >> 32
8871 // C2 = T2 >> 32
8872 // T1 = T1 & 0xFFFFFFFF
8873 // T2 = T2 & 0xFFFFFFFF
8874 // T1 = CRC32(0, T1)
8875 // T2 = CRC32(0, T2)
8876 // C1 = C1 ^ T1
8877 // C2 = C2 ^ T2
8878 // CRC = C1 ^ C2 ^ CRC_C
8879 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8880 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8881 Register tmp1, Register tmp2,
8882 Register n_tmp3) {
8883 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8884 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8885 shlq(in_out, 1);
8886 movl(tmp1, in_out);
8887 shrq(in_out, 32);
8888 xorl(tmp2, tmp2);
8889 crc32(tmp2, tmp1, 4);
8890 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8891 shlq(in1, 1);
8892 movl(tmp1, in1);
8893 shrq(in1, 32);
8894 xorl(tmp2, tmp2);
8895 crc32(tmp2, tmp1, 4);
8896 xorl(in1, tmp2);
8897 xorl(in_out, in1);
8898 xorl(in_out, in2);
8899 }
8900
8901 // Set N to predefined value
8902 // Subtract from a length of a buffer
8903 // execute in a loop:
8904 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8905 // for i = 1 to N do
8906 // CRC_A = CRC32(CRC_A, A[i])
8907 // CRC_B = CRC32(CRC_B, B[i])
8908 // CRC_C = CRC32(CRC_C, C[i])
8909 // end for
8910 // Recombine
8911 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8912 Register in_out1, Register in_out2, Register in_out3,
8913 Register tmp1, Register tmp2, Register tmp3,
8914 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8915 Register tmp4, Register tmp5,
8916 Register n_tmp6) {
8917 Label L_processPartitions;
8918 Label L_processPartition;
8919 Label L_exit;
8920
8921 bind(L_processPartitions);
8922 cmpl(in_out1, 3 * size);
8923 jcc(Assembler::less, L_exit);
8924 xorl(tmp1, tmp1);
8925 xorl(tmp2, tmp2);
8926 movq(tmp3, in_out2);
8927 addq(tmp3, size);
8928
8929 bind(L_processPartition);
8930 crc32(in_out3, Address(in_out2, 0), 8);
8931 crc32(tmp1, Address(in_out2, size), 8);
8932 crc32(tmp2, Address(in_out2, size * 2), 8);
8933 addq(in_out2, 8);
8934 cmpq(in_out2, tmp3);
8935 jcc(Assembler::less, L_processPartition);
8936 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8937 w_xtmp1, w_xtmp2, w_xtmp3,
8938 tmp4, tmp5,
8939 n_tmp6);
8940 addq(in_out2, 2 * size);
8941 subl(in_out1, 3 * size);
8942 jmp(L_processPartitions);
8943
8944 bind(L_exit);
8945 }
8946 #else
8947 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
8948 Register tmp1, Register tmp2, Register tmp3,
8949 XMMRegister xtmp1, XMMRegister xtmp2) {
8950 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8951 if (n > 0) {
8952 addl(tmp3, n * 256 * 8);
8953 }
8954 // Q1 = TABLEExt[n][B & 0xFF];
8955 movl(tmp1, in_out);
8956 andl(tmp1, 0x000000FF);
8957 shll(tmp1, 3);
8958 addl(tmp1, tmp3);
8959 movq(xtmp1, Address(tmp1, 0));
8960
8961 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8962 movl(tmp2, in_out);
8963 shrl(tmp2, 8);
8964 andl(tmp2, 0x000000FF);
8965 shll(tmp2, 3);
8966 addl(tmp2, tmp3);
8967 movq(xtmp2, Address(tmp2, 0));
8968
8969 psllq(xtmp2, 8);
8970 pxor(xtmp1, xtmp2);
8971
8972 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8973 movl(tmp2, in_out);
8974 shrl(tmp2, 16);
8975 andl(tmp2, 0x000000FF);
8976 shll(tmp2, 3);
8977 addl(tmp2, tmp3);
8978 movq(xtmp2, Address(tmp2, 0));
8979
8980 psllq(xtmp2, 16);
8981 pxor(xtmp1, xtmp2);
8982
8983 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8984 shrl(in_out, 24);
8985 andl(in_out, 0x000000FF);
8986 shll(in_out, 3);
8987 addl(in_out, tmp3);
8988 movq(xtmp2, Address(in_out, 0));
8989
8990 psllq(xtmp2, 24);
8991 pxor(xtmp1, xtmp2); // Result in CXMM
8992 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8993 }
8994
8995 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8996 Register in_out,
8997 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8998 XMMRegister w_xtmp2,
8999 Register tmp1,
9000 Register n_tmp2, Register n_tmp3) {
9001 if (is_pclmulqdq_supported) {
9002 movdl(w_xtmp1, in_out);
9003
9004 movl(tmp1, const_or_pre_comp_const_index);
9005 movdl(w_xtmp2, tmp1);
9006 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9007 // Keep result in XMM since GPR is 32 bit in length
9008 } else {
9009 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
9010 }
9011 }
9012
9013 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9014 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9015 Register tmp1, Register tmp2,
9016 Register n_tmp3) {
9017 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9018 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9019
9020 psllq(w_xtmp1, 1);
9021 movdl(tmp1, w_xtmp1);
9022 psrlq(w_xtmp1, 32);
9023 movdl(in_out, w_xtmp1);
9024
9025 xorl(tmp2, tmp2);
9026 crc32(tmp2, tmp1, 4);
9027 xorl(in_out, tmp2);
9028
9029 psllq(w_xtmp2, 1);
9030 movdl(tmp1, w_xtmp2);
9031 psrlq(w_xtmp2, 32);
9032 movdl(in1, w_xtmp2);
9033
9034 xorl(tmp2, tmp2);
9035 crc32(tmp2, tmp1, 4);
9036 xorl(in1, tmp2);
9037 xorl(in_out, in1);
9038 xorl(in_out, in2);
9039 }
9040
9041 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9042 Register in_out1, Register in_out2, Register in_out3,
9043 Register tmp1, Register tmp2, Register tmp3,
9044 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9045 Register tmp4, Register tmp5,
9046 Register n_tmp6) {
9047 Label L_processPartitions;
9048 Label L_processPartition;
9049 Label L_exit;
9050
9051 bind(L_processPartitions);
9052 cmpl(in_out1, 3 * size);
9053 jcc(Assembler::less, L_exit);
9054 xorl(tmp1, tmp1);
9055 xorl(tmp2, tmp2);
9056 movl(tmp3, in_out2);
9057 addl(tmp3, size);
9058
9059 bind(L_processPartition);
9060 crc32(in_out3, Address(in_out2, 0), 4);
9061 crc32(tmp1, Address(in_out2, size), 4);
9062 crc32(tmp2, Address(in_out2, size*2), 4);
9063 crc32(in_out3, Address(in_out2, 0+4), 4);
9064 crc32(tmp1, Address(in_out2, size+4), 4);
9065 crc32(tmp2, Address(in_out2, size*2+4), 4);
9066 addl(in_out2, 8);
9067 cmpl(in_out2, tmp3);
9068 jcc(Assembler::less, L_processPartition);
9069
9070 push(tmp3);
9071 push(in_out1);
9072 push(in_out2);
9073 tmp4 = tmp3;
9074 tmp5 = in_out1;
9075 n_tmp6 = in_out2;
9076
9077 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9078 w_xtmp1, w_xtmp2, w_xtmp3,
9079 tmp4, tmp5,
9080 n_tmp6);
9081
9082 pop(in_out2);
9083 pop(in_out1);
9084 pop(tmp3);
9085
9086 addl(in_out2, 2 * size);
9087 subl(in_out1, 3 * size);
9088 jmp(L_processPartitions);
9089
9090 bind(L_exit);
9091 }
9092 #endif //LP64
9093
9094 #ifdef _LP64
9095 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9096 // Input: A buffer I of L bytes.
9097 // Output: the CRC32C value of the buffer.
9098 // Notations:
9099 // Write L = 24N + r, with N = floor (L/24).
9100 // r = L mod 24 (0 <= r < 24).
9101 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9102 // N quadwords, and R consists of r bytes.
9103 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9104 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9105 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9106 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9107 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9108 Register tmp1, Register tmp2, Register tmp3,
9109 Register tmp4, Register tmp5, Register tmp6,
9110 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9111 bool is_pclmulqdq_supported) {
9112 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9113 Label L_wordByWord;
9114 Label L_byteByByteProlog;
9115 Label L_byteByByte;
9116 Label L_exit;
9117
9118 if (is_pclmulqdq_supported ) {
9119 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9120 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
9121
9122 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9123 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9124
9125 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9126 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9127 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9128 } else {
9129 const_or_pre_comp_const_index[0] = 1;
9130 const_or_pre_comp_const_index[1] = 0;
9131
9132 const_or_pre_comp_const_index[2] = 3;
9133 const_or_pre_comp_const_index[3] = 2;
9134
9135 const_or_pre_comp_const_index[4] = 5;
9136 const_or_pre_comp_const_index[5] = 4;
9137 }
9138 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9139 in2, in1, in_out,
9140 tmp1, tmp2, tmp3,
9141 w_xtmp1, w_xtmp2, w_xtmp3,
9142 tmp4, tmp5,
9143 tmp6);
9144 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9145 in2, in1, in_out,
9146 tmp1, tmp2, tmp3,
9147 w_xtmp1, w_xtmp2, w_xtmp3,
9148 tmp4, tmp5,
9149 tmp6);
9150 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9151 in2, in1, in_out,
9152 tmp1, tmp2, tmp3,
9153 w_xtmp1, w_xtmp2, w_xtmp3,
9154 tmp4, tmp5,
9155 tmp6);
9156 movl(tmp1, in2);
9157 andl(tmp1, 0x00000007);
9158 negl(tmp1);
9159 addl(tmp1, in2);
9160 addq(tmp1, in1);
9161
9162 cmpq(in1, tmp1);
9163 jccb(Assembler::greaterEqual, L_byteByByteProlog);
9164 align(16);
9165 BIND(L_wordByWord);
9166 crc32(in_out, Address(in1, 0), 8);
9167 addq(in1, 8);
9168 cmpq(in1, tmp1);
9169 jcc(Assembler::less, L_wordByWord);
9170
9171 BIND(L_byteByByteProlog);
9172 andl(in2, 0x00000007);
9173 movl(tmp2, 1);
9174
9175 cmpl(tmp2, in2);
9176 jccb(Assembler::greater, L_exit);
9177 BIND(L_byteByByte);
9178 crc32(in_out, Address(in1, 0), 1);
9179 incq(in1);
9180 incl(tmp2);
9181 cmpl(tmp2, in2);
9182 jcc(Assembler::lessEqual, L_byteByByte);
9183
9184 BIND(L_exit);
9185 }
9186 #else
9187 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9188 Register tmp1, Register tmp2, Register tmp3,
9189 Register tmp4, Register tmp5, Register tmp6,
9190 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9191 bool is_pclmulqdq_supported) {
9192 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9193 Label L_wordByWord;
9194 Label L_byteByByteProlog;
9195 Label L_byteByByte;
9196 Label L_exit;
9197
9198 if (is_pclmulqdq_supported) {
9199 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9200 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
9201
9202 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9203 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9204
9205 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9206 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9207 } else {
9208 const_or_pre_comp_const_index[0] = 1;
9209 const_or_pre_comp_const_index[1] = 0;
9210
9211 const_or_pre_comp_const_index[2] = 3;
9212 const_or_pre_comp_const_index[3] = 2;
9213
9214 const_or_pre_comp_const_index[4] = 5;
9215 const_or_pre_comp_const_index[5] = 4;
9216 }
9217 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9218 in2, in1, in_out,
9219 tmp1, tmp2, tmp3,
9220 w_xtmp1, w_xtmp2, w_xtmp3,
9221 tmp4, tmp5,
9222 tmp6);
9223 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9224 in2, in1, in_out,
9225 tmp1, tmp2, tmp3,
9226 w_xtmp1, w_xtmp2, w_xtmp3,
9227 tmp4, tmp5,
9228 tmp6);
9229 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9230 in2, in1, in_out,
9231 tmp1, tmp2, tmp3,
9232 w_xtmp1, w_xtmp2, w_xtmp3,
9233 tmp4, tmp5,
9234 tmp6);
9235 movl(tmp1, in2);
9236 andl(tmp1, 0x00000007);
9237 negl(tmp1);
9238 addl(tmp1, in2);
9239 addl(tmp1, in1);
9240
9241 BIND(L_wordByWord);
9242 cmpl(in1, tmp1);
9243 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9244 crc32(in_out, Address(in1,0), 4);
9245 addl(in1, 4);
9246 jmp(L_wordByWord);
9247
9248 BIND(L_byteByByteProlog);
9249 andl(in2, 0x00000007);
9250 movl(tmp2, 1);
9251
9252 BIND(L_byteByByte);
9253 cmpl(tmp2, in2);
9254 jccb(Assembler::greater, L_exit);
9255 movb(tmp1, Address(in1, 0));
9256 crc32(in_out, tmp1, 1);
9257 incl(in1);
9258 incl(tmp2);
9259 jmp(L_byteByByte);
9260
9261 BIND(L_exit);
9262 }
9263 #endif // LP64
9264 #undef BIND
9265 #undef BLOCK_COMMENT
9266
9267 // Compress char[] array to byte[].
9268 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
9269 // Return the array length if every element in array can be encoded,
9270 // otherwise, the index of first non-latin1 (> 0xff) character.
9271 // @IntrinsicCandidate
9272 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9273 // for (int i = 0; i < len; i++) {
9274 // char c = src[srcOff];
9275 // if (c > 0xff) {
9276 // return i; // return index of non-latin1 char
9277 // }
9278 // dst[dstOff] = (byte)c;
9279 // srcOff++;
9280 // dstOff++;
9281 // }
9282 // return len;
9283 // }
9284 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9285 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9286 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9287 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9288 Label copy_chars_loop, done, reset_sp, copy_tail;
9289
9290 // rsi: src
9291 // rdi: dst
9292 // rdx: len
9293 // rcx: tmp5
9294 // rax: result
9295
9296 // rsi holds start addr of source char[] to be compressed
9297 // rdi holds start addr of destination byte[]
9298 // rdx holds length
9299
9300 assert(len != result, "");
9301
9302 // save length for return
9303 movl(result, len);
9304
9305 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9306 VM_Version::supports_avx512vlbw() &&
9307 VM_Version::supports_bmi2()) {
9308
9309 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9310
9311 // alignment
9312 Label post_alignment;
9313
9314 // if length of the string is less than 32, handle it the old fashioned way
9315 testl(len, -32);
9316 jcc(Assembler::zero, below_threshold);
9317
9318 // First check whether a character is compressible ( <= 0xFF).
9319 // Create mask to test for Unicode chars inside zmm vector
9320 movl(tmp5, 0x00FF);
9321 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9322
9323 testl(len, -64);
9324 jccb(Assembler::zero, post_alignment);
9325
9326 movl(tmp5, dst);
9327 andl(tmp5, (32 - 1));
9328 negl(tmp5);
9329 andl(tmp5, (32 - 1));
9330
9331 // bail out when there is nothing to be done
9332 testl(tmp5, 0xFFFFFFFF);
9333 jccb(Assembler::zero, post_alignment);
9334
9335 // ~(~0 << len), where len is the # of remaining elements to process
9336 movl(len, 0xFFFFFFFF);
9337 shlxl(len, len, tmp5);
9338 notl(len);
9339 kmovdl(mask2, len);
9340 movl(len, result);
9341
9342 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9343 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9344 ktestd(mask1, mask2);
9345 jcc(Assembler::carryClear, copy_tail);
9346
9347 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9348
9349 addptr(src, tmp5);
9350 addptr(src, tmp5);
9351 addptr(dst, tmp5);
9352 subl(len, tmp5);
9353
9354 bind(post_alignment);
9355 // end of alignment
9356
9357 movl(tmp5, len);
9358 andl(tmp5, (32 - 1)); // tail count (in chars)
9359 andl(len, ~(32 - 1)); // vector count (in chars)
9360 jccb(Assembler::zero, copy_loop_tail);
9361
9362 lea(src, Address(src, len, Address::times_2));
9363 lea(dst, Address(dst, len, Address::times_1));
9364 negptr(len);
9365
9366 bind(copy_32_loop);
9367 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9368 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9369 kortestdl(mask1, mask1);
9370 jccb(Assembler::carryClear, reset_for_copy_tail);
9371
9372 // All elements in current processed chunk are valid candidates for
9373 // compression. Write a truncated byte elements to the memory.
9374 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9375 addptr(len, 32);
9376 jccb(Assembler::notZero, copy_32_loop);
9377
9378 bind(copy_loop_tail);
9379 // bail out when there is nothing to be done
9380 testl(tmp5, 0xFFFFFFFF);
9381 jcc(Assembler::zero, done);
9382
9383 movl(len, tmp5);
9384
9385 // ~(~0 << len), where len is the # of remaining elements to process
9386 movl(tmp5, 0xFFFFFFFF);
9387 shlxl(tmp5, tmp5, len);
9388 notl(tmp5);
9389
9390 kmovdl(mask2, tmp5);
9391
9392 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9393 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9394 ktestd(mask1, mask2);
9395 jcc(Assembler::carryClear, copy_tail);
9396
9397 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9398 jmp(done);
9399
9400 bind(reset_for_copy_tail);
9401 lea(src, Address(src, tmp5, Address::times_2));
9402 lea(dst, Address(dst, tmp5, Address::times_1));
9403 subptr(len, tmp5);
9404 jmp(copy_chars_loop);
9405
9406 bind(below_threshold);
9407 }
9408
9409 if (UseSSE42Intrinsics) {
9410 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9411
9412 // vectored compression
9413 testl(len, 0xfffffff8);
9414 jcc(Assembler::zero, copy_tail);
9415
9416 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9417 movdl(tmp1Reg, tmp5);
9418 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9419
9420 andl(len, 0xfffffff0);
9421 jccb(Assembler::zero, copy_16);
9422
9423 // compress 16 chars per iter
9424 pxor(tmp4Reg, tmp4Reg);
9425
9426 lea(src, Address(src, len, Address::times_2));
9427 lea(dst, Address(dst, len, Address::times_1));
9428 negptr(len);
9429
9430 bind(copy_32_loop);
9431 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9432 por(tmp4Reg, tmp2Reg);
9433 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9434 por(tmp4Reg, tmp3Reg);
9435 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9436 jccb(Assembler::notZero, reset_for_copy_tail);
9437 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9438 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9439 addptr(len, 16);
9440 jccb(Assembler::notZero, copy_32_loop);
9441
9442 // compress next vector of 8 chars (if any)
9443 bind(copy_16);
9444 // len = 0
9445 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9446 jccb(Assembler::zero, copy_tail_sse);
9447
9448 pxor(tmp3Reg, tmp3Reg);
9449
9450 movdqu(tmp2Reg, Address(src, 0));
9451 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9452 jccb(Assembler::notZero, reset_for_copy_tail);
9453 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9454 movq(Address(dst, 0), tmp2Reg);
9455 addptr(src, 16);
9456 addptr(dst, 8);
9457 jmpb(copy_tail_sse);
9458
9459 bind(reset_for_copy_tail);
9460 movl(tmp5, result);
9461 andl(tmp5, 0x0000000f);
9462 lea(src, Address(src, tmp5, Address::times_2));
9463 lea(dst, Address(dst, tmp5, Address::times_1));
9464 subptr(len, tmp5);
9465 jmpb(copy_chars_loop);
9466
9467 bind(copy_tail_sse);
9468 movl(len, result);
9469 andl(len, 0x00000007); // tail count (in chars)
9470 }
9471 // compress 1 char per iter
9472 bind(copy_tail);
9473 testl(len, len);
9474 jccb(Assembler::zero, done);
9475 lea(src, Address(src, len, Address::times_2));
9476 lea(dst, Address(dst, len, Address::times_1));
9477 negptr(len);
9478
9479 bind(copy_chars_loop);
9480 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9481 testl(tmp5, 0xff00); // check if Unicode char
9482 jccb(Assembler::notZero, reset_sp);
9483 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9484 increment(len);
9485 jccb(Assembler::notZero, copy_chars_loop);
9486
9487 // add len then return (len will be zero if compress succeeded, otherwise negative)
9488 bind(reset_sp);
9489 addl(result, len);
9490
9491 bind(done);
9492 }
9493
9494 // Inflate byte[] array to char[].
9495 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9496 // @IntrinsicCandidate
9497 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9498 // for (int i = 0; i < len; i++) {
9499 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9500 // }
9501 // }
9502 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9503 XMMRegister tmp1, Register tmp2, KRegister mask) {
9504 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9505 // rsi: src
9506 // rdi: dst
9507 // rdx: len
9508 // rcx: tmp2
9509
9510 // rsi holds start addr of source byte[] to be inflated
9511 // rdi holds start addr of destination char[]
9512 // rdx holds length
9513 assert_different_registers(src, dst, len, tmp2);
9514 movl(tmp2, len);
9515 if ((UseAVX > 2) && // AVX512
9516 VM_Version::supports_avx512vlbw() &&
9517 VM_Version::supports_bmi2()) {
9518
9519 Label copy_32_loop, copy_tail;
9520 Register tmp3_aliased = len;
9521
9522 // if length of the string is less than 16, handle it in an old fashioned way
9523 testl(len, -16);
9524 jcc(Assembler::zero, below_threshold);
9525
9526 testl(len, -1 * AVX3Threshold);
9527 jcc(Assembler::zero, avx3_threshold);
9528
9529 // In order to use only one arithmetic operation for the main loop we use
9530 // this pre-calculation
9531 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9532 andl(len, -32); // vector count
9533 jccb(Assembler::zero, copy_tail);
9534
9535 lea(src, Address(src, len, Address::times_1));
9536 lea(dst, Address(dst, len, Address::times_2));
9537 negptr(len);
9538
9539
9540 // inflate 32 chars per iter
9541 bind(copy_32_loop);
9542 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9543 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9544 addptr(len, 32);
9545 jcc(Assembler::notZero, copy_32_loop);
9546
9547 bind(copy_tail);
9548 // bail out when there is nothing to be done
9549 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9550 jcc(Assembler::zero, done);
9551
9552 // ~(~0 << length), where length is the # of remaining elements to process
9553 movl(tmp3_aliased, -1);
9554 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9555 notl(tmp3_aliased);
9556 kmovdl(mask, tmp3_aliased);
9557 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9558 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9559
9560 jmp(done);
9561 bind(avx3_threshold);
9562 }
9563 if (UseSSE42Intrinsics) {
9564 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9565
9566 if (UseAVX > 1) {
9567 andl(tmp2, (16 - 1));
9568 andl(len, -16);
9569 jccb(Assembler::zero, copy_new_tail);
9570 } else {
9571 andl(tmp2, 0x00000007); // tail count (in chars)
9572 andl(len, 0xfffffff8); // vector count (in chars)
9573 jccb(Assembler::zero, copy_tail);
9574 }
9575
9576 // vectored inflation
9577 lea(src, Address(src, len, Address::times_1));
9578 lea(dst, Address(dst, len, Address::times_2));
9579 negptr(len);
9580
9581 if (UseAVX > 1) {
9582 bind(copy_16_loop);
9583 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9584 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9585 addptr(len, 16);
9586 jcc(Assembler::notZero, copy_16_loop);
9587
9588 bind(below_threshold);
9589 bind(copy_new_tail);
9590 movl(len, tmp2);
9591 andl(tmp2, 0x00000007);
9592 andl(len, 0xFFFFFFF8);
9593 jccb(Assembler::zero, copy_tail);
9594
9595 pmovzxbw(tmp1, Address(src, 0));
9596 movdqu(Address(dst, 0), tmp1);
9597 addptr(src, 8);
9598 addptr(dst, 2 * 8);
9599
9600 jmp(copy_tail, true);
9601 }
9602
9603 // inflate 8 chars per iter
9604 bind(copy_8_loop);
9605 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9606 movdqu(Address(dst, len, Address::times_2), tmp1);
9607 addptr(len, 8);
9608 jcc(Assembler::notZero, copy_8_loop);
9609
9610 bind(copy_tail);
9611 movl(len, tmp2);
9612
9613 cmpl(len, 4);
9614 jccb(Assembler::less, copy_bytes);
9615
9616 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9617 pmovzxbw(tmp1, tmp1);
9618 movq(Address(dst, 0), tmp1);
9619 subptr(len, 4);
9620 addptr(src, 4);
9621 addptr(dst, 8);
9622
9623 bind(copy_bytes);
9624 } else {
9625 bind(below_threshold);
9626 }
9627
9628 testl(len, len);
9629 jccb(Assembler::zero, done);
9630 lea(src, Address(src, len, Address::times_1));
9631 lea(dst, Address(dst, len, Address::times_2));
9632 negptr(len);
9633
9634 // inflate 1 char per iter
9635 bind(copy_chars_loop);
9636 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9637 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9638 increment(len);
9639 jcc(Assembler::notZero, copy_chars_loop);
9640
9641 bind(done);
9642 }
9643
9644 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
9645 switch(type) {
9646 case T_BYTE:
9647 case T_BOOLEAN:
9648 evmovdqub(dst, kmask, src, merge, vector_len);
9649 break;
9650 case T_CHAR:
9651 case T_SHORT:
9652 evmovdquw(dst, kmask, src, merge, vector_len);
9653 break;
9654 case T_INT:
9655 case T_FLOAT:
9656 evmovdqul(dst, kmask, src, merge, vector_len);
9657 break;
9658 case T_LONG:
9659 case T_DOUBLE:
9660 evmovdquq(dst, kmask, src, merge, vector_len);
9661 break;
9662 default:
9663 fatal("Unexpected type argument %s", type2name(type));
9664 break;
9665 }
9666 }
9667
9668
9669 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9670 switch(type) {
9671 case T_BYTE:
9672 case T_BOOLEAN:
9673 evmovdqub(dst, kmask, src, merge, vector_len);
9674 break;
9675 case T_CHAR:
9676 case T_SHORT:
9677 evmovdquw(dst, kmask, src, merge, vector_len);
9678 break;
9679 case T_INT:
9680 case T_FLOAT:
9681 evmovdqul(dst, kmask, src, merge, vector_len);
9682 break;
9683 case T_LONG:
9684 case T_DOUBLE:
9685 evmovdquq(dst, kmask, src, merge, vector_len);
9686 break;
9687 default:
9688 fatal("Unexpected type argument %s", type2name(type));
9689 break;
9690 }
9691 }
9692
9693 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9694 switch(type) {
9695 case T_BYTE:
9696 case T_BOOLEAN:
9697 evmovdqub(dst, kmask, src, merge, vector_len);
9698 break;
9699 case T_CHAR:
9700 case T_SHORT:
9701 evmovdquw(dst, kmask, src, merge, vector_len);
9702 break;
9703 case T_INT:
9704 case T_FLOAT:
9705 evmovdqul(dst, kmask, src, merge, vector_len);
9706 break;
9707 case T_LONG:
9708 case T_DOUBLE:
9709 evmovdquq(dst, kmask, src, merge, vector_len);
9710 break;
9711 default:
9712 fatal("Unexpected type argument %s", type2name(type));
9713 break;
9714 }
9715 }
9716
9717 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9718 switch(masklen) {
9719 case 2:
9720 knotbl(dst, src);
9721 movl(rtmp, 3);
9722 kmovbl(ktmp, rtmp);
9723 kandbl(dst, ktmp, dst);
9724 break;
9725 case 4:
9726 knotbl(dst, src);
9727 movl(rtmp, 15);
9728 kmovbl(ktmp, rtmp);
9729 kandbl(dst, ktmp, dst);
9730 break;
9731 case 8:
9732 knotbl(dst, src);
9733 break;
9734 case 16:
9735 knotwl(dst, src);
9736 break;
9737 case 32:
9738 knotdl(dst, src);
9739 break;
9740 case 64:
9741 knotql(dst, src);
9742 break;
9743 default:
9744 fatal("Unexpected vector length %d", masklen);
9745 break;
9746 }
9747 }
9748
9749 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9750 switch(type) {
9751 case T_BOOLEAN:
9752 case T_BYTE:
9753 kandbl(dst, src1, src2);
9754 break;
9755 case T_CHAR:
9756 case T_SHORT:
9757 kandwl(dst, src1, src2);
9758 break;
9759 case T_INT:
9760 case T_FLOAT:
9761 kanddl(dst, src1, src2);
9762 break;
9763 case T_LONG:
9764 case T_DOUBLE:
9765 kandql(dst, src1, src2);
9766 break;
9767 default:
9768 fatal("Unexpected type argument %s", type2name(type));
9769 break;
9770 }
9771 }
9772
9773 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9774 switch(type) {
9775 case T_BOOLEAN:
9776 case T_BYTE:
9777 korbl(dst, src1, src2);
9778 break;
9779 case T_CHAR:
9780 case T_SHORT:
9781 korwl(dst, src1, src2);
9782 break;
9783 case T_INT:
9784 case T_FLOAT:
9785 kordl(dst, src1, src2);
9786 break;
9787 case T_LONG:
9788 case T_DOUBLE:
9789 korql(dst, src1, src2);
9790 break;
9791 default:
9792 fatal("Unexpected type argument %s", type2name(type));
9793 break;
9794 }
9795 }
9796
9797 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9798 switch(type) {
9799 case T_BOOLEAN:
9800 case T_BYTE:
9801 kxorbl(dst, src1, src2);
9802 break;
9803 case T_CHAR:
9804 case T_SHORT:
9805 kxorwl(dst, src1, src2);
9806 break;
9807 case T_INT:
9808 case T_FLOAT:
9809 kxordl(dst, src1, src2);
9810 break;
9811 case T_LONG:
9812 case T_DOUBLE:
9813 kxorql(dst, src1, src2);
9814 break;
9815 default:
9816 fatal("Unexpected type argument %s", type2name(type));
9817 break;
9818 }
9819 }
9820
9821 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9822 switch(type) {
9823 case T_BOOLEAN:
9824 case T_BYTE:
9825 evpermb(dst, mask, nds, src, merge, vector_len); break;
9826 case T_CHAR:
9827 case T_SHORT:
9828 evpermw(dst, mask, nds, src, merge, vector_len); break;
9829 case T_INT:
9830 case T_FLOAT:
9831 evpermd(dst, mask, nds, src, merge, vector_len); break;
9832 case T_LONG:
9833 case T_DOUBLE:
9834 evpermq(dst, mask, nds, src, merge, vector_len); break;
9835 default:
9836 fatal("Unexpected type argument %s", type2name(type)); break;
9837 }
9838 }
9839
9840 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9841 switch(type) {
9842 case T_BOOLEAN:
9843 case T_BYTE:
9844 evpermb(dst, mask, nds, src, merge, vector_len); break;
9845 case T_CHAR:
9846 case T_SHORT:
9847 evpermw(dst, mask, nds, src, merge, vector_len); break;
9848 case T_INT:
9849 case T_FLOAT:
9850 evpermd(dst, mask, nds, src, merge, vector_len); break;
9851 case T_LONG:
9852 case T_DOUBLE:
9853 evpermq(dst, mask, nds, src, merge, vector_len); break;
9854 default:
9855 fatal("Unexpected type argument %s", type2name(type)); break;
9856 }
9857 }
9858
9859 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9860 switch(type) {
9861 case T_BYTE:
9862 evpminub(dst, mask, nds, src, merge, vector_len); break;
9863 case T_SHORT:
9864 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9865 case T_INT:
9866 evpminud(dst, mask, nds, src, merge, vector_len); break;
9867 case T_LONG:
9868 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9869 default:
9870 fatal("Unexpected type argument %s", type2name(type)); break;
9871 }
9872 }
9873
9874 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9875 switch(type) {
9876 case T_BYTE:
9877 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9878 case T_SHORT:
9879 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9880 case T_INT:
9881 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9882 case T_LONG:
9883 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9884 default:
9885 fatal("Unexpected type argument %s", type2name(type)); break;
9886 }
9887 }
9888
9889 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9890 switch(type) {
9891 case T_BYTE:
9892 evpminub(dst, mask, nds, src, merge, vector_len); break;
9893 case T_SHORT:
9894 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9895 case T_INT:
9896 evpminud(dst, mask, nds, src, merge, vector_len); break;
9897 case T_LONG:
9898 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9899 default:
9900 fatal("Unexpected type argument %s", type2name(type)); break;
9901 }
9902 }
9903
9904 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9905 switch(type) {
9906 case T_BYTE:
9907 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9908 case T_SHORT:
9909 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9910 case T_INT:
9911 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9912 case T_LONG:
9913 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9914 default:
9915 fatal("Unexpected type argument %s", type2name(type)); break;
9916 }
9917 }
9918
9919 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9920 switch(type) {
9921 case T_BYTE:
9922 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9923 case T_SHORT:
9924 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9925 case T_INT:
9926 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9927 case T_LONG:
9928 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9929 default:
9930 fatal("Unexpected type argument %s", type2name(type)); break;
9931 }
9932 }
9933
9934 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9935 switch(type) {
9936 case T_BYTE:
9937 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9938 case T_SHORT:
9939 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9940 case T_INT:
9941 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9942 case T_LONG:
9943 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9944 default:
9945 fatal("Unexpected type argument %s", type2name(type)); break;
9946 }
9947 }
9948
9949 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9950 switch(type) {
9951 case T_BYTE:
9952 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9953 case T_SHORT:
9954 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9955 case T_INT:
9956 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9957 case T_LONG:
9958 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9959 default:
9960 fatal("Unexpected type argument %s", type2name(type)); break;
9961 }
9962 }
9963
9964 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9965 switch(type) {
9966 case T_BYTE:
9967 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9968 case T_SHORT:
9969 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9970 case T_INT:
9971 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9972 case T_LONG:
9973 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9974 default:
9975 fatal("Unexpected type argument %s", type2name(type)); break;
9976 }
9977 }
9978
9979 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9980 switch(type) {
9981 case T_INT:
9982 evpxord(dst, mask, nds, src, merge, vector_len); break;
9983 case T_LONG:
9984 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9985 default:
9986 fatal("Unexpected type argument %s", type2name(type)); break;
9987 }
9988 }
9989
9990 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9991 switch(type) {
9992 case T_INT:
9993 evpxord(dst, mask, nds, src, merge, vector_len); break;
9994 case T_LONG:
9995 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9996 default:
9997 fatal("Unexpected type argument %s", type2name(type)); break;
9998 }
9999 }
10000
10001 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10002 switch(type) {
10003 case T_INT:
10004 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10005 case T_LONG:
10006 evporq(dst, mask, nds, src, merge, vector_len); break;
10007 default:
10008 fatal("Unexpected type argument %s", type2name(type)); break;
10009 }
10010 }
10011
10012 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10013 switch(type) {
10014 case T_INT:
10015 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10016 case T_LONG:
10017 evporq(dst, mask, nds, src, merge, vector_len); break;
10018 default:
10019 fatal("Unexpected type argument %s", type2name(type)); break;
10020 }
10021 }
10022
10023 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10024 switch(type) {
10025 case T_INT:
10026 evpandd(dst, mask, nds, src, merge, vector_len); break;
10027 case T_LONG:
10028 evpandq(dst, mask, nds, src, merge, vector_len); break;
10029 default:
10030 fatal("Unexpected type argument %s", type2name(type)); break;
10031 }
10032 }
10033
10034 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10035 switch(type) {
10036 case T_INT:
10037 evpandd(dst, mask, nds, src, merge, vector_len); break;
10038 case T_LONG:
10039 evpandq(dst, mask, nds, src, merge, vector_len); break;
10040 default:
10041 fatal("Unexpected type argument %s", type2name(type)); break;
10042 }
10043 }
10044
10045 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
10046 switch(masklen) {
10047 case 8:
10048 kortestbl(src1, src2);
10049 break;
10050 case 16:
10051 kortestwl(src1, src2);
10052 break;
10053 case 32:
10054 kortestdl(src1, src2);
10055 break;
10056 case 64:
10057 kortestql(src1, src2);
10058 break;
10059 default:
10060 fatal("Unexpected mask length %d", masklen);
10061 break;
10062 }
10063 }
10064
10065
10066 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
10067 switch(masklen) {
10068 case 8:
10069 ktestbl(src1, src2);
10070 break;
10071 case 16:
10072 ktestwl(src1, src2);
10073 break;
10074 case 32:
10075 ktestdl(src1, src2);
10076 break;
10077 case 64:
10078 ktestql(src1, src2);
10079 break;
10080 default:
10081 fatal("Unexpected mask length %d", masklen);
10082 break;
10083 }
10084 }
10085
10086 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10087 switch(type) {
10088 case T_INT:
10089 evprold(dst, mask, src, shift, merge, vlen_enc); break;
10090 case T_LONG:
10091 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
10092 default:
10093 fatal("Unexpected type argument %s", type2name(type)); break;
10094 break;
10095 }
10096 }
10097
10098 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10099 switch(type) {
10100 case T_INT:
10101 evprord(dst, mask, src, shift, merge, vlen_enc); break;
10102 case T_LONG:
10103 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
10104 default:
10105 fatal("Unexpected type argument %s", type2name(type)); break;
10106 }
10107 }
10108
10109 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10110 switch(type) {
10111 case T_INT:
10112 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
10113 case T_LONG:
10114 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
10115 default:
10116 fatal("Unexpected type argument %s", type2name(type)); break;
10117 }
10118 }
10119
10120 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10121 switch(type) {
10122 case T_INT:
10123 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
10124 case T_LONG:
10125 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
10126 default:
10127 fatal("Unexpected type argument %s", type2name(type)); break;
10128 }
10129 }
10130
10131 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10132 assert(rscratch != noreg || always_reachable(src), "missing");
10133
10134 if (reachable(src)) {
10135 evpandq(dst, nds, as_Address(src), vector_len);
10136 } else {
10137 lea(rscratch, src);
10138 evpandq(dst, nds, Address(rscratch, 0), vector_len);
10139 }
10140 }
10141
10142 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
10143 assert(rscratch != noreg || always_reachable(src), "missing");
10144
10145 if (reachable(src)) {
10146 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
10147 } else {
10148 lea(rscratch, src);
10149 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
10150 }
10151 }
10152
10153 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10154 assert(rscratch != noreg || always_reachable(src), "missing");
10155
10156 if (reachable(src)) {
10157 evporq(dst, nds, as_Address(src), vector_len);
10158 } else {
10159 lea(rscratch, src);
10160 evporq(dst, nds, Address(rscratch, 0), vector_len);
10161 }
10162 }
10163
10164 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10165 assert(rscratch != noreg || always_reachable(src), "missing");
10166
10167 if (reachable(src)) {
10168 vpshufb(dst, nds, as_Address(src), vector_len);
10169 } else {
10170 lea(rscratch, src);
10171 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
10172 }
10173 }
10174
10175 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10176 assert(rscratch != noreg || always_reachable(src), "missing");
10177
10178 if (reachable(src)) {
10179 Assembler::vpor(dst, nds, as_Address(src), vector_len);
10180 } else {
10181 lea(rscratch, src);
10182 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
10183 }
10184 }
10185
10186 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
10187 assert(rscratch != noreg || always_reachable(src3), "missing");
10188
10189 if (reachable(src3)) {
10190 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
10191 } else {
10192 lea(rscratch, src3);
10193 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
10194 }
10195 }
10196
10197 #if COMPILER2_OR_JVMCI
10198
10199 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
10200 Register length, Register temp, int vec_enc) {
10201 // Computing mask for predicated vector store.
10202 movptr(temp, -1);
10203 bzhiq(temp, temp, length);
10204 kmov(mask, temp);
10205 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
10206 }
10207
10208 // Set memory operation for length "less than" 64 bytes.
10209 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
10210 XMMRegister xmm, KRegister mask, Register length,
10211 Register temp, bool use64byteVector) {
10212 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10213 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10214 if (!use64byteVector) {
10215 fill32(dst, disp, xmm);
10216 subptr(length, 32 >> shift);
10217 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
10218 } else {
10219 assert(MaxVectorSize == 64, "vector length != 64");
10220 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
10221 }
10222 }
10223
10224
10225 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
10226 XMMRegister xmm, KRegister mask, Register length,
10227 Register temp) {
10228 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10229 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10230 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
10231 }
10232
10233
10234 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
10235 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10236 vmovdqu(dst, xmm);
10237 }
10238
10239 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
10240 fill32(Address(dst, disp), xmm);
10241 }
10242
10243 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
10244 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10245 if (!use64byteVector) {
10246 fill32(dst, xmm);
10247 fill32(dst.plus_disp(32), xmm);
10248 } else {
10249 evmovdquq(dst, xmm, Assembler::AVX_512bit);
10250 }
10251 }
10252
10253 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
10254 fill64(Address(dst, disp), xmm, use64byteVector);
10255 }
10256
10257 #ifdef _LP64
10258 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
10259 Register count, Register rtmp, XMMRegister xtmp) {
10260 Label L_exit;
10261 Label L_fill_start;
10262 Label L_fill_64_bytes;
10263 Label L_fill_96_bytes;
10264 Label L_fill_128_bytes;
10265 Label L_fill_128_bytes_loop;
10266 Label L_fill_128_loop_header;
10267 Label L_fill_128_bytes_loop_header;
10268 Label L_fill_128_bytes_loop_pre_header;
10269 Label L_fill_zmm_sequence;
10270
10271 int shift = -1;
10272 int avx3threshold = VM_Version::avx3_threshold();
10273 switch(type) {
10274 case T_BYTE: shift = 0;
10275 break;
10276 case T_SHORT: shift = 1;
10277 break;
10278 case T_INT: shift = 2;
10279 break;
10280 /* Uncomment when LONG fill stubs are supported.
10281 case T_LONG: shift = 3;
10282 break;
10283 */
10284 default:
10285 fatal("Unhandled type: %s\n", type2name(type));
10286 }
10287
10288 if ((avx3threshold != 0) || (MaxVectorSize == 32)) {
10289
10290 if (MaxVectorSize == 64) {
10291 cmpq(count, avx3threshold >> shift);
10292 jcc(Assembler::greater, L_fill_zmm_sequence);
10293 }
10294
10295 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
10296
10297 bind(L_fill_start);
10298
10299 cmpq(count, 32 >> shift);
10300 jccb(Assembler::greater, L_fill_64_bytes);
10301 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
10302 jmp(L_exit);
10303
10304 bind(L_fill_64_bytes);
10305 cmpq(count, 64 >> shift);
10306 jccb(Assembler::greater, L_fill_96_bytes);
10307 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10308 jmp(L_exit);
10309
10310 bind(L_fill_96_bytes);
10311 cmpq(count, 96 >> shift);
10312 jccb(Assembler::greater, L_fill_128_bytes);
10313 fill64(to, 0, xtmp);
10314 subq(count, 64 >> shift);
10315 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10316 jmp(L_exit);
10317
10318 bind(L_fill_128_bytes);
10319 cmpq(count, 128 >> shift);
10320 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10321 fill64(to, 0, xtmp);
10322 fill32(to, 64, xtmp);
10323 subq(count, 96 >> shift);
10324 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10325 jmp(L_exit);
10326
10327 bind(L_fill_128_bytes_loop_pre_header);
10328 {
10329 mov(rtmp, to);
10330 andq(rtmp, 31);
10331 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10332 negq(rtmp);
10333 addq(rtmp, 32);
10334 mov64(r8, -1L);
10335 bzhiq(r8, r8, rtmp);
10336 kmovql(k2, r8);
10337 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10338 addq(to, rtmp);
10339 shrq(rtmp, shift);
10340 subq(count, rtmp);
10341 }
10342
10343 cmpq(count, 128 >> shift);
10344 jcc(Assembler::less, L_fill_start);
10345
10346 bind(L_fill_128_bytes_loop_header);
10347 subq(count, 128 >> shift);
10348
10349 align32();
10350 bind(L_fill_128_bytes_loop);
10351 fill64(to, 0, xtmp);
10352 fill64(to, 64, xtmp);
10353 addq(to, 128);
10354 subq(count, 128 >> shift);
10355 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10356
10357 addq(count, 128 >> shift);
10358 jcc(Assembler::zero, L_exit);
10359 jmp(L_fill_start);
10360 }
10361
10362 if (MaxVectorSize == 64) {
10363 // Sequence using 64 byte ZMM register.
10364 Label L_fill_128_bytes_zmm;
10365 Label L_fill_192_bytes_zmm;
10366 Label L_fill_192_bytes_loop_zmm;
10367 Label L_fill_192_bytes_loop_header_zmm;
10368 Label L_fill_192_bytes_loop_pre_header_zmm;
10369 Label L_fill_start_zmm_sequence;
10370
10371 bind(L_fill_zmm_sequence);
10372 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10373
10374 bind(L_fill_start_zmm_sequence);
10375 cmpq(count, 64 >> shift);
10376 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10377 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10378 jmp(L_exit);
10379
10380 bind(L_fill_128_bytes_zmm);
10381 cmpq(count, 128 >> shift);
10382 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10383 fill64(to, 0, xtmp, true);
10384 subq(count, 64 >> shift);
10385 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10386 jmp(L_exit);
10387
10388 bind(L_fill_192_bytes_zmm);
10389 cmpq(count, 192 >> shift);
10390 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10391 fill64(to, 0, xtmp, true);
10392 fill64(to, 64, xtmp, true);
10393 subq(count, 128 >> shift);
10394 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10395 jmp(L_exit);
10396
10397 bind(L_fill_192_bytes_loop_pre_header_zmm);
10398 {
10399 movq(rtmp, to);
10400 andq(rtmp, 63);
10401 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10402 negq(rtmp);
10403 addq(rtmp, 64);
10404 mov64(r8, -1L);
10405 bzhiq(r8, r8, rtmp);
10406 kmovql(k2, r8);
10407 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10408 addq(to, rtmp);
10409 shrq(rtmp, shift);
10410 subq(count, rtmp);
10411 }
10412
10413 cmpq(count, 192 >> shift);
10414 jcc(Assembler::less, L_fill_start_zmm_sequence);
10415
10416 bind(L_fill_192_bytes_loop_header_zmm);
10417 subq(count, 192 >> shift);
10418
10419 align32();
10420 bind(L_fill_192_bytes_loop_zmm);
10421 fill64(to, 0, xtmp, true);
10422 fill64(to, 64, xtmp, true);
10423 fill64(to, 128, xtmp, true);
10424 addq(to, 192);
10425 subq(count, 192 >> shift);
10426 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10427
10428 addq(count, 192 >> shift);
10429 jcc(Assembler::zero, L_exit);
10430 jmp(L_fill_start_zmm_sequence);
10431 }
10432 bind(L_exit);
10433 }
10434 #endif
10435 #endif //COMPILER2_OR_JVMCI
10436
10437
10438 #ifdef _LP64
10439 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10440 Label done;
10441 cvttss2sil(dst, src);
10442 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10443 cmpl(dst, 0x80000000); // float_sign_flip
10444 jccb(Assembler::notEqual, done);
10445 subptr(rsp, 8);
10446 movflt(Address(rsp, 0), src);
10447 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10448 pop(dst);
10449 bind(done);
10450 }
10451
10452 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10453 Label done;
10454 cvttsd2sil(dst, src);
10455 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10456 cmpl(dst, 0x80000000); // float_sign_flip
10457 jccb(Assembler::notEqual, done);
10458 subptr(rsp, 8);
10459 movdbl(Address(rsp, 0), src);
10460 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10461 pop(dst);
10462 bind(done);
10463 }
10464
10465 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10466 Label done;
10467 cvttss2siq(dst, src);
10468 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10469 jccb(Assembler::notEqual, done);
10470 subptr(rsp, 8);
10471 movflt(Address(rsp, 0), src);
10472 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10473 pop(dst);
10474 bind(done);
10475 }
10476
10477 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10478 // Following code is line by line assembly translation rounding algorithm.
10479 // Please refer to java.lang.Math.round(float) algorithm for details.
10480 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10481 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10482 const int32_t FloatConsts_EXP_BIAS = 127;
10483 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10484 const int32_t MINUS_32 = 0xFFFFFFE0;
10485 Label L_special_case, L_block1, L_exit;
10486 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10487 movdl(dst, src);
10488 andl(dst, rtmp);
10489 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10490 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10491 subl(rtmp, dst);
10492 movl(rcx, rtmp);
10493 movl(dst, MINUS_32);
10494 testl(rtmp, dst);
10495 jccb(Assembler::notEqual, L_special_case);
10496 movdl(dst, src);
10497 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10498 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10499 movdl(rtmp, src);
10500 testl(rtmp, rtmp);
10501 jccb(Assembler::greaterEqual, L_block1);
10502 negl(dst);
10503 bind(L_block1);
10504 sarl(dst);
10505 addl(dst, 0x1);
10506 sarl(dst, 0x1);
10507 jmp(L_exit);
10508 bind(L_special_case);
10509 convert_f2i(dst, src);
10510 bind(L_exit);
10511 }
10512
10513 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10514 // Following code is line by line assembly translation rounding algorithm.
10515 // Please refer to java.lang.Math.round(double) algorithm for details.
10516 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10517 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10518 const int64_t DoubleConsts_EXP_BIAS = 1023;
10519 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10520 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10521 Label L_special_case, L_block1, L_exit;
10522 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10523 movq(dst, src);
10524 andq(dst, rtmp);
10525 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10526 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10527 subq(rtmp, dst);
10528 movq(rcx, rtmp);
10529 mov64(dst, MINUS_64);
10530 testq(rtmp, dst);
10531 jccb(Assembler::notEqual, L_special_case);
10532 movq(dst, src);
10533 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10534 andq(dst, rtmp);
10535 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10536 orq(dst, rtmp);
10537 movq(rtmp, src);
10538 testq(rtmp, rtmp);
10539 jccb(Assembler::greaterEqual, L_block1);
10540 negq(dst);
10541 bind(L_block1);
10542 sarq(dst);
10543 addq(dst, 0x1);
10544 sarq(dst, 0x1);
10545 jmp(L_exit);
10546 bind(L_special_case);
10547 convert_d2l(dst, src);
10548 bind(L_exit);
10549 }
10550
10551 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10552 Label done;
10553 cvttsd2siq(dst, src);
10554 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10555 jccb(Assembler::notEqual, done);
10556 subptr(rsp, 8);
10557 movdbl(Address(rsp, 0), src);
10558 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10559 pop(dst);
10560 bind(done);
10561 }
10562
10563 void MacroAssembler::cache_wb(Address line)
10564 {
10565 // 64 bit cpus always support clflush
10566 assert(VM_Version::supports_clflush(), "clflush should be available");
10567 bool optimized = VM_Version::supports_clflushopt();
10568 bool no_evict = VM_Version::supports_clwb();
10569
10570 // prefer clwb (writeback without evict) otherwise
10571 // prefer clflushopt (potentially parallel writeback with evict)
10572 // otherwise fallback on clflush (serial writeback with evict)
10573
10574 if (optimized) {
10575 if (no_evict) {
10576 clwb(line);
10577 } else {
10578 clflushopt(line);
10579 }
10580 } else {
10581 // no need for fence when using CLFLUSH
10582 clflush(line);
10583 }
10584 }
10585
10586 void MacroAssembler::cache_wbsync(bool is_pre)
10587 {
10588 assert(VM_Version::supports_clflush(), "clflush should be available");
10589 bool optimized = VM_Version::supports_clflushopt();
10590 bool no_evict = VM_Version::supports_clwb();
10591
10592 // pick the correct implementation
10593
10594 if (!is_pre && (optimized || no_evict)) {
10595 // need an sfence for post flush when using clflushopt or clwb
10596 // otherwise no no need for any synchroniaztion
10597
10598 sfence();
10599 }
10600 }
10601
10602 #endif // _LP64
10603
10604 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10605 switch (cond) {
10606 // Note some conditions are synonyms for others
10607 case Assembler::zero: return Assembler::notZero;
10608 case Assembler::notZero: return Assembler::zero;
10609 case Assembler::less: return Assembler::greaterEqual;
10610 case Assembler::lessEqual: return Assembler::greater;
10611 case Assembler::greater: return Assembler::lessEqual;
10612 case Assembler::greaterEqual: return Assembler::less;
10613 case Assembler::below: return Assembler::aboveEqual;
10614 case Assembler::belowEqual: return Assembler::above;
10615 case Assembler::above: return Assembler::belowEqual;
10616 case Assembler::aboveEqual: return Assembler::below;
10617 case Assembler::overflow: return Assembler::noOverflow;
10618 case Assembler::noOverflow: return Assembler::overflow;
10619 case Assembler::negative: return Assembler::positive;
10620 case Assembler::positive: return Assembler::negative;
10621 case Assembler::parity: return Assembler::noParity;
10622 case Assembler::noParity: return Assembler::parity;
10623 }
10624 ShouldNotReachHere(); return Assembler::overflow;
10625 }
10626
10627 // This is simply a call to Thread::current()
10628 void MacroAssembler::get_thread(Register thread) {
10629 if (thread != rax) {
10630 push(rax);
10631 }
10632 LP64_ONLY(push(rdi);)
10633 LP64_ONLY(push(rsi);)
10634 push(rdx);
10635 push(rcx);
10636 #ifdef _LP64
10637 push(r8);
10638 push(r9);
10639 push(r10);
10640 push(r11);
10641 #endif
10642
10643 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10644
10645 #ifdef _LP64
10646 pop(r11);
10647 pop(r10);
10648 pop(r9);
10649 pop(r8);
10650 #endif
10651 pop(rcx);
10652 pop(rdx);
10653 LP64_ONLY(pop(rsi);)
10654 LP64_ONLY(pop(rdi);)
10655 if (thread != rax) {
10656 mov(thread, rax);
10657 pop(rax);
10658 }
10659 }
10660
10661 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10662 Label L_stack_ok;
10663 if (bias == 0) {
10664 testptr(sp, 2 * wordSize - 1);
10665 } else {
10666 // lea(tmp, Address(rsp, bias);
10667 mov(tmp, sp);
10668 addptr(tmp, bias);
10669 testptr(tmp, 2 * wordSize - 1);
10670 }
10671 jcc(Assembler::equal, L_stack_ok);
10672 block_comment(msg);
10673 stop(msg);
10674 bind(L_stack_ok);
10675 }
10676
10677 // Implements lightweight-locking.
10678 //
10679 // obj: the object to be locked
10680 // reg_rax: rax
10681 // thread: the thread which attempts to lock obj
10682 // tmp: a temporary register
10683 void MacroAssembler::lightweight_lock(Register basic_lock, Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10684 assert(reg_rax == rax, "");
10685 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10686
10687 Label push;
10688 const Register top = tmp;
10689
10690 // Preload the markWord. It is important that this is the first
10691 // instruction emitted as it is part of C1's null check semantics.
10692 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10693
10694 if (UseObjectMonitorTable) {
10695 // Clear cache in case fast locking succeeds.
10696 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10697 }
10698
10699 // Load top.
10700 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10701
10702 // Check if the lock-stack is full.
10703 cmpl(top, LockStack::end_offset());
10704 jcc(Assembler::greaterEqual, slow);
10705
10706 // Check for recursion.
10707 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10708 jcc(Assembler::equal, push);
10709
10710 // Check header for monitor (0b10).
10711 testptr(reg_rax, markWord::monitor_value);
10712 jcc(Assembler::notZero, slow);
10713
10714 // Try to lock. Transition lock bits 0b01 => 0b00
10715 movptr(tmp, reg_rax);
10716 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10717 orptr(reg_rax, markWord::unlocked_value);
10718 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10719 jcc(Assembler::notEqual, slow);
10720
10721 // Restore top, CAS clobbers register.
10722 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10723
10724 bind(push);
10725 // After successful lock, push object on lock-stack.
10726 movptr(Address(thread, top), obj);
10727 incrementl(top, oopSize);
10728 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10729 }
10730
10731 // Implements lightweight-unlocking.
10732 //
10733 // obj: the object to be unlocked
10734 // reg_rax: rax
10735 // thread: the thread
10736 // tmp: a temporary register
10737 void MacroAssembler::lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10738 assert(reg_rax == rax, "");
10739 assert_different_registers(obj, reg_rax, thread, tmp);
10740
10741 Label unlocked, push_and_slow;
10742 const Register top = tmp;
10743
10744 // Check if obj is top of lock-stack.
10745 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10746 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10747 jcc(Assembler::notEqual, slow);
10748
10749 // Pop lock-stack.
10750 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10751 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10752
10753 // Check if recursive.
10754 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10755 jcc(Assembler::equal, unlocked);
10756
10757 // Not recursive. Check header for monitor (0b10).
10758 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10759 testptr(reg_rax, markWord::monitor_value);
10760 jcc(Assembler::notZero, push_and_slow);
10761
10762 #ifdef ASSERT
10763 // Check header not unlocked (0b01).
10764 Label not_unlocked;
10765 testptr(reg_rax, markWord::unlocked_value);
10766 jcc(Assembler::zero, not_unlocked);
10767 stop("lightweight_unlock already unlocked");
10768 bind(not_unlocked);
10769 #endif
10770
10771 // Try to unlock. Transition lock bits 0b00 => 0b01
10772 movptr(tmp, reg_rax);
10773 orptr(tmp, markWord::unlocked_value);
10774 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10775 jcc(Assembler::equal, unlocked);
10776
10777 bind(push_and_slow);
10778 // Restore lock-stack and handle the unlock in runtime.
10779 #ifdef ASSERT
10780 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10781 movptr(Address(thread, top), obj);
10782 #endif
10783 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10784 jmp(slow);
10785
10786 bind(unlocked);
10787 }
10788
10789 #ifdef _LP64
10790 // Saves legacy GPRs state on stack.
10791 void MacroAssembler::save_legacy_gprs() {
10792 subq(rsp, 16 * wordSize);
10793 movq(Address(rsp, 15 * wordSize), rax);
10794 movq(Address(rsp, 14 * wordSize), rcx);
10795 movq(Address(rsp, 13 * wordSize), rdx);
10796 movq(Address(rsp, 12 * wordSize), rbx);
10797 movq(Address(rsp, 10 * wordSize), rbp);
10798 movq(Address(rsp, 9 * wordSize), rsi);
10799 movq(Address(rsp, 8 * wordSize), rdi);
10800 movq(Address(rsp, 7 * wordSize), r8);
10801 movq(Address(rsp, 6 * wordSize), r9);
10802 movq(Address(rsp, 5 * wordSize), r10);
10803 movq(Address(rsp, 4 * wordSize), r11);
10804 movq(Address(rsp, 3 * wordSize), r12);
10805 movq(Address(rsp, 2 * wordSize), r13);
10806 movq(Address(rsp, wordSize), r14);
10807 movq(Address(rsp, 0), r15);
10808 }
10809
10810 // Resotres back legacy GPRs state from stack.
10811 void MacroAssembler::restore_legacy_gprs() {
10812 movq(r15, Address(rsp, 0));
10813 movq(r14, Address(rsp, wordSize));
10814 movq(r13, Address(rsp, 2 * wordSize));
10815 movq(r12, Address(rsp, 3 * wordSize));
10816 movq(r11, Address(rsp, 4 * wordSize));
10817 movq(r10, Address(rsp, 5 * wordSize));
10818 movq(r9, Address(rsp, 6 * wordSize));
10819 movq(r8, Address(rsp, 7 * wordSize));
10820 movq(rdi, Address(rsp, 8 * wordSize));
10821 movq(rsi, Address(rsp, 9 * wordSize));
10822 movq(rbp, Address(rsp, 10 * wordSize));
10823 movq(rbx, Address(rsp, 12 * wordSize));
10824 movq(rdx, Address(rsp, 13 * wordSize));
10825 movq(rcx, Address(rsp, 14 * wordSize));
10826 movq(rax, Address(rsp, 15 * wordSize));
10827 addq(rsp, 16 * wordSize);
10828 }
10829
10830 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10831 if (VM_Version::supports_apx_f()) {
10832 esetzucc(comparison, dst);
10833 } else {
10834 setb(comparison, dst);
10835 movzbl(dst, dst);
10836 }
10837 }
10838 #endif