1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "crc32c.h"
32 #include "gc/shared/barrierSet.hpp"
33 #include "gc/shared/barrierSetAssembler.hpp"
34 #include "gc/shared/collectedHeap.inline.hpp"
35 #include "gc/shared/tlab_globals.hpp"
36 #include "interpreter/bytecodeHistogram.hpp"
37 #include "interpreter/interpreter.hpp"
38 #include "interpreter/interpreterRuntime.hpp"
39 #include "jvm.h"
40 #include "memory/resourceArea.hpp"
41 #include "memory/universe.hpp"
42 #include "oops/accessDecorators.hpp"
43 #include "oops/compressedKlass.inline.hpp"
44 #include "oops/compressedOops.inline.hpp"
45 #include "oops/klass.inline.hpp"
46 #include "prims/methodHandles.hpp"
47 #include "runtime/continuation.hpp"
48 #include "runtime/interfaceSupport.inline.hpp"
49 #include "runtime/javaThread.hpp"
50 #include "runtime/jniHandles.hpp"
51 #include "runtime/objectMonitor.hpp"
52 #include "runtime/os.hpp"
53 #include "runtime/safepoint.hpp"
54 #include "runtime/safepointMechanism.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/checkedCast.hpp"
58 #include "utilities/macros.hpp"
59
60 #ifdef PRODUCT
61 #define BLOCK_COMMENT(str) /* nothing */
62 #define STOP(error) stop(error)
63 #else
64 #define BLOCK_COMMENT(str) block_comment(str)
65 #define STOP(error) block_comment(error); stop(error)
66 #endif
67
68 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
69
70 #ifdef ASSERT
71 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
72 #endif
73
74 static const Assembler::Condition reverse[] = {
75 Assembler::noOverflow /* overflow = 0x0 */ ,
76 Assembler::overflow /* noOverflow = 0x1 */ ,
77 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
78 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
79 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
80 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
81 Assembler::above /* belowEqual = 0x6 */ ,
82 Assembler::belowEqual /* above = 0x7 */ ,
83 Assembler::positive /* negative = 0x8 */ ,
84 Assembler::negative /* positive = 0x9 */ ,
85 Assembler::noParity /* parity = 0xa */ ,
86 Assembler::parity /* noParity = 0xb */ ,
87 Assembler::greaterEqual /* less = 0xc */ ,
88 Assembler::less /* greaterEqual = 0xd */ ,
89 Assembler::greater /* lessEqual = 0xe */ ,
90 Assembler::lessEqual /* greater = 0xf, */
91
92 };
93
94
95 // Implementation of MacroAssembler
96
97 // First all the versions that have distinct versions depending on 32/64 bit
98 // Unless the difference is trivial (1 line or so).
99
100 #ifndef _LP64
101
102 // 32bit versions
103
104 Address MacroAssembler::as_Address(AddressLiteral adr) {
105 return Address(adr.target(), adr.rspec());
106 }
107
108 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
109 assert(rscratch == noreg, "");
110 return Address::make_array(adr);
111 }
112
113 void MacroAssembler::call_VM_leaf_base(address entry_point,
114 int number_of_arguments) {
115 call(RuntimeAddress(entry_point));
116 increment(rsp, number_of_arguments * wordSize);
117 }
118
119 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
120 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
121 }
122
123
124 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
125 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
126 }
127
128 void MacroAssembler::cmpoop(Address src1, jobject obj) {
129 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
130 }
131
132 void MacroAssembler::cmpoop(Register src1, jobject obj, Register rscratch) {
133 assert(rscratch == noreg, "redundant");
134 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
135 }
136
137 void MacroAssembler::extend_sign(Register hi, Register lo) {
138 // According to Intel Doc. AP-526, "Integer Divide", p.18.
139 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
140 cdql();
141 } else {
142 movl(hi, lo);
143 sarl(hi, 31);
144 }
145 }
146
147 void MacroAssembler::jC2(Register tmp, Label& L) {
148 // set parity bit if FPU flag C2 is set (via rax)
149 save_rax(tmp);
150 fwait(); fnstsw_ax();
151 sahf();
152 restore_rax(tmp);
153 // branch
154 jcc(Assembler::parity, L);
155 }
156
157 void MacroAssembler::jnC2(Register tmp, Label& L) {
158 // set parity bit if FPU flag C2 is set (via rax)
159 save_rax(tmp);
160 fwait(); fnstsw_ax();
161 sahf();
162 restore_rax(tmp);
163 // branch
164 jcc(Assembler::noParity, L);
165 }
166
167 // 32bit can do a case table jump in one instruction but we no longer allow the base
168 // to be installed in the Address class
169 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
170 assert(rscratch == noreg, "not needed");
171 jmp(as_Address(entry, noreg));
172 }
173
174 // Note: y_lo will be destroyed
175 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
176 // Long compare for Java (semantics as described in JVM spec.)
177 Label high, low, done;
178
179 cmpl(x_hi, y_hi);
180 jcc(Assembler::less, low);
181 jcc(Assembler::greater, high);
182 // x_hi is the return register
183 xorl(x_hi, x_hi);
184 cmpl(x_lo, y_lo);
185 jcc(Assembler::below, low);
186 jcc(Assembler::equal, done);
187
188 bind(high);
189 xorl(x_hi, x_hi);
190 increment(x_hi);
191 jmp(done);
192
193 bind(low);
194 xorl(x_hi, x_hi);
195 decrementl(x_hi);
196
197 bind(done);
198 }
199
200 void MacroAssembler::lea(Register dst, AddressLiteral src) {
201 mov_literal32(dst, (int32_t)src.target(), src.rspec());
202 }
203
204 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
205 assert(rscratch == noreg, "not needed");
206
207 // leal(dst, as_Address(adr));
208 // see note in movl as to why we must use a move
209 mov_literal32(dst, (int32_t)adr.target(), adr.rspec());
210 }
211
212 void MacroAssembler::leave() {
213 mov(rsp, rbp);
214 pop(rbp);
215 }
216
217 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
218 // Multiplication of two Java long values stored on the stack
219 // as illustrated below. Result is in rdx:rax.
220 //
221 // rsp ---> [ ?? ] \ \
222 // .... | y_rsp_offset |
223 // [ y_lo ] / (in bytes) | x_rsp_offset
224 // [ y_hi ] | (in bytes)
225 // .... |
226 // [ x_lo ] /
227 // [ x_hi ]
228 // ....
229 //
230 // Basic idea: lo(result) = lo(x_lo * y_lo)
231 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
232 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
233 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
234 Label quick;
235 // load x_hi, y_hi and check if quick
236 // multiplication is possible
237 movl(rbx, x_hi);
238 movl(rcx, y_hi);
239 movl(rax, rbx);
240 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
241 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
242 // do full multiplication
243 // 1st step
244 mull(y_lo); // x_hi * y_lo
245 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
246 // 2nd step
247 movl(rax, x_lo);
248 mull(rcx); // x_lo * y_hi
249 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
250 // 3rd step
251 bind(quick); // note: rbx, = 0 if quick multiply!
252 movl(rax, x_lo);
253 mull(y_lo); // x_lo * y_lo
254 addl(rdx, rbx); // correct hi(x_lo * y_lo)
255 }
256
257 void MacroAssembler::lneg(Register hi, Register lo) {
258 negl(lo);
259 adcl(hi, 0);
260 negl(hi);
261 }
262
263 void MacroAssembler::lshl(Register hi, Register lo) {
264 // Java shift left long support (semantics as described in JVM spec., p.305)
265 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
266 // shift value is in rcx !
267 assert(hi != rcx, "must not use rcx");
268 assert(lo != rcx, "must not use rcx");
269 const Register s = rcx; // shift count
270 const int n = BitsPerWord;
271 Label L;
272 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
273 cmpl(s, n); // if (s < n)
274 jcc(Assembler::less, L); // else (s >= n)
275 movl(hi, lo); // x := x << n
276 xorl(lo, lo);
277 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
278 bind(L); // s (mod n) < n
279 shldl(hi, lo); // x := x << s
280 shll(lo);
281 }
282
283
284 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
285 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
286 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
287 assert(hi != rcx, "must not use rcx");
288 assert(lo != rcx, "must not use rcx");
289 const Register s = rcx; // shift count
290 const int n = BitsPerWord;
291 Label L;
292 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
293 cmpl(s, n); // if (s < n)
294 jcc(Assembler::less, L); // else (s >= n)
295 movl(lo, hi); // x := x >> n
296 if (sign_extension) sarl(hi, 31);
297 else xorl(hi, hi);
298 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
299 bind(L); // s (mod n) < n
300 shrdl(lo, hi); // x := x >> s
301 if (sign_extension) sarl(hi);
302 else shrl(hi);
303 }
304
305 void MacroAssembler::movoop(Register dst, jobject obj) {
306 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
307 }
308
309 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
310 assert(rscratch == noreg, "redundant");
311 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
312 }
313
314 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
315 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
316 }
317
318 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
319 assert(rscratch == noreg, "redundant");
320 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
321 }
322
323 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
324 if (src.is_lval()) {
325 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
326 } else {
327 movl(dst, as_Address(src));
328 }
329 }
330
331 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
332 assert(rscratch == noreg, "redundant");
333 movl(as_Address(dst, noreg), src);
334 }
335
336 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
337 movl(dst, as_Address(src, noreg));
338 }
339
340 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
341 assert(rscratch == noreg, "redundant");
342 movl(dst, src);
343 }
344
345 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
346 assert(rscratch == noreg, "redundant");
347 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
348 }
349
350 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
351 assert(rscratch == noreg, "redundant");
352 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
353 }
354
355 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
356 assert(rscratch == noreg, "redundant");
357 if (src.is_lval()) {
358 push_literal32((int32_t)src.target(), src.rspec());
359 } else {
360 pushl(as_Address(src));
361 }
362 }
363
364 static void pass_arg0(MacroAssembler* masm, Register arg) {
365 masm->push(arg);
366 }
367
368 static void pass_arg1(MacroAssembler* masm, Register arg) {
369 masm->push(arg);
370 }
371
372 static void pass_arg2(MacroAssembler* masm, Register arg) {
373 masm->push(arg);
374 }
375
376 static void pass_arg3(MacroAssembler* masm, Register arg) {
377 masm->push(arg);
378 }
379
380 #ifndef PRODUCT
381 extern "C" void findpc(intptr_t x);
382 #endif
383
384 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
385 // In order to get locks to work, we need to fake a in_VM state
386 JavaThread* thread = JavaThread::current();
387 JavaThreadState saved_state = thread->thread_state();
388 thread->set_thread_state(_thread_in_vm);
389 if (ShowMessageBoxOnError) {
390 JavaThread* thread = JavaThread::current();
391 JavaThreadState saved_state = thread->thread_state();
392 thread->set_thread_state(_thread_in_vm);
393 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
394 ttyLocker ttyl;
395 BytecodeCounter::print();
396 }
397 // To see where a verify_oop failed, get $ebx+40/X for this frame.
398 // This is the value of eip which points to where verify_oop will return.
399 if (os::message_box(msg, "Execution stopped, print registers?")) {
400 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
401 BREAKPOINT;
402 }
403 }
404 fatal("DEBUG MESSAGE: %s", msg);
405 }
406
407 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
408 ttyLocker ttyl;
409 DebuggingContext debugging{};
410 tty->print_cr("eip = 0x%08x", eip);
411 #ifndef PRODUCT
412 if ((WizardMode || Verbose) && PrintMiscellaneous) {
413 tty->cr();
414 findpc(eip);
415 tty->cr();
416 }
417 #endif
418 #define PRINT_REG(rax) \
419 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
420 PRINT_REG(rax);
421 PRINT_REG(rbx);
422 PRINT_REG(rcx);
423 PRINT_REG(rdx);
424 PRINT_REG(rdi);
425 PRINT_REG(rsi);
426 PRINT_REG(rbp);
427 PRINT_REG(rsp);
428 #undef PRINT_REG
429 // Print some words near top of staack.
430 int* dump_sp = (int*) rsp;
431 for (int col1 = 0; col1 < 8; col1++) {
432 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
433 os::print_location(tty, *dump_sp++);
434 }
435 for (int row = 0; row < 16; row++) {
436 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
437 for (int col = 0; col < 8; col++) {
438 tty->print(" 0x%08x", *dump_sp++);
439 }
440 tty->cr();
441 }
442 // Print some instructions around pc:
443 Disassembler::decode((address)eip-64, (address)eip);
444 tty->print_cr("--------");
445 Disassembler::decode((address)eip, (address)eip+32);
446 }
447
448 void MacroAssembler::stop(const char* msg) {
449 // push address of message
450 ExternalAddress message((address)msg);
451 pushptr(message.addr(), noreg);
452 { Label L; call(L, relocInfo::none); bind(L); } // push eip
453 pusha(); // push registers
454 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
455 hlt();
456 }
457
458 void MacroAssembler::warn(const char* msg) {
459 push_CPU_state();
460
461 // push address of message
462 ExternalAddress message((address)msg);
463 pushptr(message.addr(), noreg);
464
465 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
466 addl(rsp, wordSize); // discard argument
467 pop_CPU_state();
468 }
469
470 void MacroAssembler::print_state() {
471 { Label L; call(L, relocInfo::none); bind(L); } // push eip
472 pusha(); // push registers
473
474 push_CPU_state();
475 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
476 pop_CPU_state();
477
478 popa();
479 addl(rsp, wordSize);
480 }
481
482 #else // _LP64
483
484 // 64 bit versions
485
486 Address MacroAssembler::as_Address(AddressLiteral adr) {
487 // amd64 always does this as a pc-rel
488 // we can be absolute or disp based on the instruction type
489 // jmp/call are displacements others are absolute
490 assert(!adr.is_lval(), "must be rval");
491 assert(reachable(adr), "must be");
492 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
493
494 }
495
496 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
497 AddressLiteral base = adr.base();
498 lea(rscratch, base);
499 Address index = adr.index();
500 assert(index._disp == 0, "must not have disp"); // maybe it can?
501 Address array(rscratch, index._index, index._scale, index._disp);
502 return array;
503 }
504
505 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
506 Label L, E;
507
508 #ifdef _WIN64
509 // Windows always allocates space for it's register args
510 assert(num_args <= 4, "only register arguments supported");
511 subq(rsp, frame::arg_reg_save_area_bytes);
512 #endif
513
514 // Align stack if necessary
515 testl(rsp, 15);
516 jcc(Assembler::zero, L);
517
518 subq(rsp, 8);
519 call(RuntimeAddress(entry_point));
520 addq(rsp, 8);
521 jmp(E);
522
523 bind(L);
524 call(RuntimeAddress(entry_point));
525
526 bind(E);
527
528 #ifdef _WIN64
529 // restore stack pointer
530 addq(rsp, frame::arg_reg_save_area_bytes);
531 #endif
532 }
533
534 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
535 assert(!src2.is_lval(), "should use cmpptr");
536 assert(rscratch != noreg || always_reachable(src2), "missing");
537
538 if (reachable(src2)) {
539 cmpq(src1, as_Address(src2));
540 } else {
541 lea(rscratch, src2);
542 Assembler::cmpq(src1, Address(rscratch, 0));
543 }
544 }
545
546 int MacroAssembler::corrected_idivq(Register reg) {
547 // Full implementation of Java ldiv and lrem; checks for special
548 // case as described in JVM spec., p.243 & p.271. The function
549 // returns the (pc) offset of the idivl instruction - may be needed
550 // for implicit exceptions.
551 //
552 // normal case special case
553 //
554 // input : rax: dividend min_long
555 // reg: divisor (may not be eax/edx) -1
556 //
557 // output: rax: quotient (= rax idiv reg) min_long
558 // rdx: remainder (= rax irem reg) 0
559 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
560 static const int64_t min_long = 0x8000000000000000;
561 Label normal_case, special_case;
562
563 // check for special case
564 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
565 jcc(Assembler::notEqual, normal_case);
566 xorl(rdx, rdx); // prepare rdx for possible special case (where
567 // remainder = 0)
568 cmpq(reg, -1);
569 jcc(Assembler::equal, special_case);
570
571 // handle normal case
572 bind(normal_case);
573 cdqq();
574 int idivq_offset = offset();
575 idivq(reg);
576
577 // normal and special case exit
578 bind(special_case);
579
580 return idivq_offset;
581 }
582
583 void MacroAssembler::decrementq(Register reg, int value) {
584 if (value == min_jint) { subq(reg, value); return; }
585 if (value < 0) { incrementq(reg, -value); return; }
586 if (value == 0) { ; return; }
587 if (value == 1 && UseIncDec) { decq(reg) ; return; }
588 /* else */ { subq(reg, value) ; return; }
589 }
590
591 void MacroAssembler::decrementq(Address dst, int value) {
592 if (value == min_jint) { subq(dst, value); return; }
593 if (value < 0) { incrementq(dst, -value); return; }
594 if (value == 0) { ; return; }
595 if (value == 1 && UseIncDec) { decq(dst) ; return; }
596 /* else */ { subq(dst, value) ; return; }
597 }
598
599 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
600 assert(rscratch != noreg || always_reachable(dst), "missing");
601
602 if (reachable(dst)) {
603 incrementq(as_Address(dst));
604 } else {
605 lea(rscratch, dst);
606 incrementq(Address(rscratch, 0));
607 }
608 }
609
610 void MacroAssembler::incrementq(Register reg, int value) {
611 if (value == min_jint) { addq(reg, value); return; }
612 if (value < 0) { decrementq(reg, -value); return; }
613 if (value == 0) { ; return; }
614 if (value == 1 && UseIncDec) { incq(reg) ; return; }
615 /* else */ { addq(reg, value) ; return; }
616 }
617
618 void MacroAssembler::incrementq(Address dst, int value) {
619 if (value == min_jint) { addq(dst, value); return; }
620 if (value < 0) { decrementq(dst, -value); return; }
621 if (value == 0) { ; return; }
622 if (value == 1 && UseIncDec) { incq(dst) ; return; }
623 /* else */ { addq(dst, value) ; return; }
624 }
625
626 // 32bit can do a case table jump in one instruction but we no longer allow the base
627 // to be installed in the Address class
628 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
629 lea(rscratch, entry.base());
630 Address dispatch = entry.index();
631 assert(dispatch._base == noreg, "must be");
632 dispatch._base = rscratch;
633 jmp(dispatch);
634 }
635
636 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
637 ShouldNotReachHere(); // 64bit doesn't use two regs
638 cmpq(x_lo, y_lo);
639 }
640
641 void MacroAssembler::lea(Register dst, AddressLiteral src) {
642 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
643 }
644
645 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
646 lea(rscratch, adr);
647 movptr(dst, rscratch);
648 }
649
650 void MacroAssembler::leave() {
651 // %%% is this really better? Why not on 32bit too?
652 emit_int8((unsigned char)0xC9); // LEAVE
653 }
654
655 void MacroAssembler::lneg(Register hi, Register lo) {
656 ShouldNotReachHere(); // 64bit doesn't use two regs
657 negq(lo);
658 }
659
660 void MacroAssembler::movoop(Register dst, jobject obj) {
661 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
662 }
663
664 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
665 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
666 movq(dst, rscratch);
667 }
668
669 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
670 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
671 }
672
673 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
674 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
675 movq(dst, rscratch);
676 }
677
678 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
679 if (src.is_lval()) {
680 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
681 } else {
682 if (reachable(src)) {
683 movq(dst, as_Address(src));
684 } else {
685 lea(dst, src);
686 movq(dst, Address(dst, 0));
687 }
688 }
689 }
690
691 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
692 movq(as_Address(dst, rscratch), src);
693 }
694
695 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
696 movq(dst, as_Address(src, dst /*rscratch*/));
697 }
698
699 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
700 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
701 if (is_simm32(src)) {
702 movptr(dst, checked_cast<int32_t>(src));
703 } else {
704 mov64(rscratch, src);
705 movq(dst, rscratch);
706 }
707 }
708
709 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
710 movoop(rscratch, obj);
711 push(rscratch);
712 }
713
714 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
715 mov_metadata(rscratch, obj);
716 push(rscratch);
717 }
718
719 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
720 lea(rscratch, src);
721 if (src.is_lval()) {
722 push(rscratch);
723 } else {
724 pushq(Address(rscratch, 0));
725 }
726 }
727
728 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
729 reset_last_Java_frame(r15_thread, clear_fp);
730 }
731
732 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
733 Register last_java_fp,
734 address last_java_pc,
735 Register rscratch) {
736 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, last_java_pc, rscratch);
737 }
738
739 static void pass_arg0(MacroAssembler* masm, Register arg) {
740 if (c_rarg0 != arg ) {
741 masm->mov(c_rarg0, arg);
742 }
743 }
744
745 static void pass_arg1(MacroAssembler* masm, Register arg) {
746 if (c_rarg1 != arg ) {
747 masm->mov(c_rarg1, arg);
748 }
749 }
750
751 static void pass_arg2(MacroAssembler* masm, Register arg) {
752 if (c_rarg2 != arg ) {
753 masm->mov(c_rarg2, arg);
754 }
755 }
756
757 static void pass_arg3(MacroAssembler* masm, Register arg) {
758 if (c_rarg3 != arg ) {
759 masm->mov(c_rarg3, arg);
760 }
761 }
762
763 void MacroAssembler::stop(const char* msg) {
764 if (ShowMessageBoxOnError) {
765 address rip = pc();
766 pusha(); // get regs on stack
767 lea(c_rarg1, InternalAddress(rip));
768 movq(c_rarg2, rsp); // pass pointer to regs array
769 }
770 lea(c_rarg0, ExternalAddress((address) msg));
771 andq(rsp, -16); // align stack as required by ABI
772 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
773 hlt();
774 }
775
776 void MacroAssembler::warn(const char* msg) {
777 push(rbp);
778 movq(rbp, rsp);
779 andq(rsp, -16); // align stack as required by push_CPU_state and call
780 push_CPU_state(); // keeps alignment at 16 bytes
781
782 lea(c_rarg0, ExternalAddress((address) msg));
783 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
784
785 pop_CPU_state();
786 mov(rsp, rbp);
787 pop(rbp);
788 }
789
790 void MacroAssembler::print_state() {
791 address rip = pc();
792 pusha(); // get regs on stack
793 push(rbp);
794 movq(rbp, rsp);
795 andq(rsp, -16); // align stack as required by push_CPU_state and call
796 push_CPU_state(); // keeps alignment at 16 bytes
797
798 lea(c_rarg0, InternalAddress(rip));
799 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
800 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
801
802 pop_CPU_state();
803 mov(rsp, rbp);
804 pop(rbp);
805 popa();
806 }
807
808 #ifndef PRODUCT
809 extern "C" void findpc(intptr_t x);
810 #endif
811
812 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
813 // In order to get locks to work, we need to fake a in_VM state
814 if (ShowMessageBoxOnError) {
815 JavaThread* thread = JavaThread::current();
816 JavaThreadState saved_state = thread->thread_state();
817 thread->set_thread_state(_thread_in_vm);
818 #ifndef PRODUCT
819 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
820 ttyLocker ttyl;
821 BytecodeCounter::print();
822 }
823 #endif
824 // To see where a verify_oop failed, get $ebx+40/X for this frame.
825 // XXX correct this offset for amd64
826 // This is the value of eip which points to where verify_oop will return.
827 if (os::message_box(msg, "Execution stopped, print registers?")) {
828 print_state64(pc, regs);
829 BREAKPOINT;
830 }
831 }
832 fatal("DEBUG MESSAGE: %s", msg);
833 }
834
835 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
836 ttyLocker ttyl;
837 DebuggingContext debugging{};
838 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
839 #ifndef PRODUCT
840 tty->cr();
841 findpc(pc);
842 tty->cr();
843 #endif
844 #define PRINT_REG(rax, value) \
845 { tty->print("%s = ", #rax); os::print_location(tty, value); }
846 PRINT_REG(rax, regs[15]);
847 PRINT_REG(rbx, regs[12]);
848 PRINT_REG(rcx, regs[14]);
849 PRINT_REG(rdx, regs[13]);
850 PRINT_REG(rdi, regs[8]);
851 PRINT_REG(rsi, regs[9]);
852 PRINT_REG(rbp, regs[10]);
853 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
854 PRINT_REG(rsp, (intptr_t)(®s[16]));
855 PRINT_REG(r8 , regs[7]);
856 PRINT_REG(r9 , regs[6]);
857 PRINT_REG(r10, regs[5]);
858 PRINT_REG(r11, regs[4]);
859 PRINT_REG(r12, regs[3]);
860 PRINT_REG(r13, regs[2]);
861 PRINT_REG(r14, regs[1]);
862 PRINT_REG(r15, regs[0]);
863 #undef PRINT_REG
864 // Print some words near the top of the stack.
865 int64_t* rsp = ®s[16];
866 int64_t* dump_sp = rsp;
867 for (int col1 = 0; col1 < 8; col1++) {
868 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
869 os::print_location(tty, *dump_sp++);
870 }
871 for (int row = 0; row < 25; row++) {
872 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
873 for (int col = 0; col < 4; col++) {
874 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
875 }
876 tty->cr();
877 }
878 // Print some instructions around pc:
879 Disassembler::decode((address)pc-64, (address)pc);
880 tty->print_cr("--------");
881 Disassembler::decode((address)pc, (address)pc+32);
882 }
883
884 // The java_calling_convention describes stack locations as ideal slots on
885 // a frame with no abi restrictions. Since we must observe abi restrictions
886 // (like the placement of the register window) the slots must be biased by
887 // the following value.
888 static int reg2offset_in(VMReg r) {
889 // Account for saved rbp and return address
890 // This should really be in_preserve_stack_slots
891 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
892 }
893
894 static int reg2offset_out(VMReg r) {
895 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
896 }
897
898 // A long move
899 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
900
901 // The calling conventions assures us that each VMregpair is either
902 // all really one physical register or adjacent stack slots.
903
904 if (src.is_single_phys_reg() ) {
905 if (dst.is_single_phys_reg()) {
906 if (dst.first() != src.first()) {
907 mov(dst.first()->as_Register(), src.first()->as_Register());
908 }
909 } else {
910 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
911 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
912 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
913 }
914 } else if (dst.is_single_phys_reg()) {
915 assert(src.is_single_reg(), "not a stack pair");
916 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
917 } else {
918 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
919 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
920 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
921 }
922 }
923
924 // A double move
925 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
926
927 // The calling conventions assures us that each VMregpair is either
928 // all really one physical register or adjacent stack slots.
929
930 if (src.is_single_phys_reg() ) {
931 if (dst.is_single_phys_reg()) {
932 // In theory these overlap but the ordering is such that this is likely a nop
933 if ( src.first() != dst.first()) {
934 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
935 }
936 } else {
937 assert(dst.is_single_reg(), "not a stack pair");
938 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
939 }
940 } else if (dst.is_single_phys_reg()) {
941 assert(src.is_single_reg(), "not a stack pair");
942 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
943 } else {
944 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
945 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
946 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
947 }
948 }
949
950
951 // A float arg may have to do float reg int reg conversion
952 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
953 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
954
955 // The calling conventions assures us that each VMregpair is either
956 // all really one physical register or adjacent stack slots.
957
958 if (src.first()->is_stack()) {
959 if (dst.first()->is_stack()) {
960 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
961 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
962 } else {
963 // stack to reg
964 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
965 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
966 }
967 } else if (dst.first()->is_stack()) {
968 // reg to stack
969 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
970 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
971 } else {
972 // reg to reg
973 // In theory these overlap but the ordering is such that this is likely a nop
974 if ( src.first() != dst.first()) {
975 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
976 }
977 }
978 }
979
980 // On 64 bit we will store integer like items to the stack as
981 // 64 bits items (x86_32/64 abi) even though java would only store
982 // 32bits for a parameter. On 32bit it will simply be 32 bits
983 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
984 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
985 if (src.first()->is_stack()) {
986 if (dst.first()->is_stack()) {
987 // stack to stack
988 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
989 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
990 } else {
991 // stack to reg
992 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
993 }
994 } else if (dst.first()->is_stack()) {
995 // reg to stack
996 // Do we really have to sign extend???
997 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
998 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
999 } else {
1000 // Do we really have to sign extend???
1001 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1002 if (dst.first() != src.first()) {
1003 movq(dst.first()->as_Register(), src.first()->as_Register());
1004 }
1005 }
1006 }
1007
1008 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1009 if (src.first()->is_stack()) {
1010 if (dst.first()->is_stack()) {
1011 // stack to stack
1012 movq(rax, Address(rbp, reg2offset_in(src.first())));
1013 movq(Address(rsp, reg2offset_out(dst.first())), rax);
1014 } else {
1015 // stack to reg
1016 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1017 }
1018 } else if (dst.first()->is_stack()) {
1019 // reg to stack
1020 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1021 } else {
1022 if (dst.first() != src.first()) {
1023 movq(dst.first()->as_Register(), src.first()->as_Register());
1024 }
1025 }
1026 }
1027
1028 // An oop arg. Must pass a handle not the oop itself
1029 void MacroAssembler::object_move(OopMap* map,
1030 int oop_handle_offset,
1031 int framesize_in_slots,
1032 VMRegPair src,
1033 VMRegPair dst,
1034 bool is_receiver,
1035 int* receiver_offset) {
1036
1037 // must pass a handle. First figure out the location we use as a handle
1038
1039 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1040
1041 // See if oop is null if it is we need no handle
1042
1043 if (src.first()->is_stack()) {
1044
1045 // Oop is already on the stack as an argument
1046 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1047 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1048 if (is_receiver) {
1049 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1050 }
1051
1052 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
1053 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1054 // conditionally move a null
1055 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1056 } else {
1057
1058 // Oop is in a register we must store it to the space we reserve
1059 // on the stack for oop_handles and pass a handle if oop is non-null
1060
1061 const Register rOop = src.first()->as_Register();
1062 int oop_slot;
1063 if (rOop == j_rarg0)
1064 oop_slot = 0;
1065 else if (rOop == j_rarg1)
1066 oop_slot = 1;
1067 else if (rOop == j_rarg2)
1068 oop_slot = 2;
1069 else if (rOop == j_rarg3)
1070 oop_slot = 3;
1071 else if (rOop == j_rarg4)
1072 oop_slot = 4;
1073 else {
1074 assert(rOop == j_rarg5, "wrong register");
1075 oop_slot = 5;
1076 }
1077
1078 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1079 int offset = oop_slot*VMRegImpl::stack_slot_size;
1080
1081 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1082 // Store oop in handle area, may be null
1083 movptr(Address(rsp, offset), rOop);
1084 if (is_receiver) {
1085 *receiver_offset = offset;
1086 }
1087
1088 cmpptr(rOop, NULL_WORD);
1089 lea(rHandle, Address(rsp, offset));
1090 // conditionally move a null from the handle area where it was just stored
1091 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1092 }
1093
1094 // If arg is on the stack then place it otherwise it is already in correct reg.
1095 if (dst.first()->is_stack()) {
1096 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1097 }
1098 }
1099
1100 #endif // _LP64
1101
1102 // Now versions that are common to 32/64 bit
1103
1104 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1105 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1106 }
1107
1108 void MacroAssembler::addptr(Register dst, Register src) {
1109 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1110 }
1111
1112 void MacroAssembler::addptr(Address dst, Register src) {
1113 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1114 }
1115
1116 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1117 assert(rscratch != noreg || always_reachable(src), "missing");
1118
1119 if (reachable(src)) {
1120 Assembler::addsd(dst, as_Address(src));
1121 } else {
1122 lea(rscratch, src);
1123 Assembler::addsd(dst, Address(rscratch, 0));
1124 }
1125 }
1126
1127 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1128 assert(rscratch != noreg || always_reachable(src), "missing");
1129
1130 if (reachable(src)) {
1131 addss(dst, as_Address(src));
1132 } else {
1133 lea(rscratch, src);
1134 addss(dst, Address(rscratch, 0));
1135 }
1136 }
1137
1138 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1139 assert(rscratch != noreg || always_reachable(src), "missing");
1140
1141 if (reachable(src)) {
1142 Assembler::addpd(dst, as_Address(src));
1143 } else {
1144 lea(rscratch, src);
1145 Assembler::addpd(dst, Address(rscratch, 0));
1146 }
1147 }
1148
1149 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
1150 // Stub code is generated once and never copied.
1151 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1152 void MacroAssembler::align64() {
1153 align(64, (uint)(uintptr_t)pc());
1154 }
1155
1156 void MacroAssembler::align32() {
1157 align(32, (uint)(uintptr_t)pc());
1158 }
1159
1160 void MacroAssembler::align(uint modulus) {
1161 // 8273459: Ensure alignment is possible with current segment alignment
1162 assert(modulus <= (uintx)CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1163 align(modulus, offset());
1164 }
1165
1166 void MacroAssembler::align(uint modulus, uint target) {
1167 if (target % modulus != 0) {
1168 nop(modulus - (target % modulus));
1169 }
1170 }
1171
1172 void MacroAssembler::push_f(XMMRegister r) {
1173 subptr(rsp, wordSize);
1174 movflt(Address(rsp, 0), r);
1175 }
1176
1177 void MacroAssembler::pop_f(XMMRegister r) {
1178 movflt(r, Address(rsp, 0));
1179 addptr(rsp, wordSize);
1180 }
1181
1182 void MacroAssembler::push_d(XMMRegister r) {
1183 subptr(rsp, 2 * wordSize);
1184 movdbl(Address(rsp, 0), r);
1185 }
1186
1187 void MacroAssembler::pop_d(XMMRegister r) {
1188 movdbl(r, Address(rsp, 0));
1189 addptr(rsp, 2 * Interpreter::stackElementSize);
1190 }
1191
1192 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1193 // Used in sign-masking with aligned address.
1194 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1195 assert(rscratch != noreg || always_reachable(src), "missing");
1196
1197 if (UseAVX > 2 &&
1198 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
1199 (dst->encoding() >= 16)) {
1200 vpand(dst, dst, src, AVX_512bit, rscratch);
1201 } else if (reachable(src)) {
1202 Assembler::andpd(dst, as_Address(src));
1203 } else {
1204 lea(rscratch, src);
1205 Assembler::andpd(dst, Address(rscratch, 0));
1206 }
1207 }
1208
1209 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
1210 // Used in sign-masking with aligned address.
1211 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1212 assert(rscratch != noreg || always_reachable(src), "missing");
1213
1214 if (reachable(src)) {
1215 Assembler::andps(dst, as_Address(src));
1216 } else {
1217 lea(rscratch, src);
1218 Assembler::andps(dst, Address(rscratch, 0));
1219 }
1220 }
1221
1222 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1223 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1224 }
1225
1226 #ifdef _LP64
1227 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
1228 assert(rscratch != noreg || always_reachable(src), "missing");
1229
1230 if (reachable(src)) {
1231 andq(dst, as_Address(src));
1232 } else {
1233 lea(rscratch, src);
1234 andq(dst, Address(rscratch, 0));
1235 }
1236 }
1237 #endif
1238
1239 void MacroAssembler::atomic_incl(Address counter_addr) {
1240 lock();
1241 incrementl(counter_addr);
1242 }
1243
1244 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
1245 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1246
1247 if (reachable(counter_addr)) {
1248 atomic_incl(as_Address(counter_addr));
1249 } else {
1250 lea(rscratch, counter_addr);
1251 atomic_incl(Address(rscratch, 0));
1252 }
1253 }
1254
1255 #ifdef _LP64
1256 void MacroAssembler::atomic_incq(Address counter_addr) {
1257 lock();
1258 incrementq(counter_addr);
1259 }
1260
1261 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
1262 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1263
1264 if (reachable(counter_addr)) {
1265 atomic_incq(as_Address(counter_addr));
1266 } else {
1267 lea(rscratch, counter_addr);
1268 atomic_incq(Address(rscratch, 0));
1269 }
1270 }
1271 #endif
1272
1273 // Writes to stack successive pages until offset reached to check for
1274 // stack overflow + shadow pages. This clobbers tmp.
1275 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1276 movptr(tmp, rsp);
1277 // Bang stack for total size given plus shadow page size.
1278 // Bang one page at a time because large size can bang beyond yellow and
1279 // red zones.
1280 Label loop;
1281 bind(loop);
1282 movl(Address(tmp, (-(int)os::vm_page_size())), size );
1283 subptr(tmp, (int)os::vm_page_size());
1284 subl(size, (int)os::vm_page_size());
1285 jcc(Assembler::greater, loop);
1286
1287 // Bang down shadow pages too.
1288 // At this point, (tmp-0) is the last address touched, so don't
1289 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1290 // was post-decremented.) Skip this address by starting at i=1, and
1291 // touch a few more pages below. N.B. It is important to touch all
1292 // the way down including all pages in the shadow zone.
1293 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
1294 // this could be any sized move but this is can be a debugging crumb
1295 // so the bigger the better.
1296 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
1297 }
1298 }
1299
1300 void MacroAssembler::reserved_stack_check() {
1301 // testing if reserved zone needs to be enabled
1302 Label no_reserved_zone_enabling;
1303 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1304 NOT_LP64(get_thread(rsi);)
1305
1306 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1307 jcc(Assembler::below, no_reserved_zone_enabling);
1308
1309 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1310 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
1311 should_not_reach_here();
1312
1313 bind(no_reserved_zone_enabling);
1314 }
1315
1316 void MacroAssembler::c2bool(Register x) {
1317 // implements x == 0 ? 0 : 1
1318 // note: must only look at least-significant byte of x
1319 // since C-style booleans are stored in one byte
1320 // only! (was bug)
1321 andl(x, 0xFF);
1322 setb(Assembler::notZero, x);
1323 }
1324
1325 // Wouldn't need if AddressLiteral version had new name
1326 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1327 Assembler::call(L, rtype);
1328 }
1329
1330 void MacroAssembler::call(Register entry) {
1331 Assembler::call(entry);
1332 }
1333
1334 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
1335 assert(rscratch != noreg || always_reachable(entry), "missing");
1336
1337 if (reachable(entry)) {
1338 Assembler::call_literal(entry.target(), entry.rspec());
1339 } else {
1340 lea(rscratch, entry);
1341 Assembler::call(rscratch);
1342 }
1343 }
1344
1345 void MacroAssembler::ic_call(address entry, jint method_index) {
1346 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1347 #ifdef _LP64
1348 // Needs full 64-bit immediate for later patching.
1349 mov64(rax, (int64_t)Universe::non_oop_word());
1350 #else
1351 movptr(rax, (intptr_t)Universe::non_oop_word());
1352 #endif
1353 call(AddressLiteral(entry, rh));
1354 }
1355
1356 int MacroAssembler::ic_check_size() {
1357 return
1358 LP64_ONLY(UseCompactObjectHeaders ? 17 : 14) NOT_LP64(12);
1359 }
1360
1361 int MacroAssembler::ic_check(int end_alignment) {
1362 Register receiver = LP64_ONLY(j_rarg0) NOT_LP64(rcx);
1363 Register data = rax;
1364 Register temp = LP64_ONLY(rscratch1) NOT_LP64(rbx);
1365
1366 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1367 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1368 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1369 // before the inline cache check here, and not after
1370 align(end_alignment, offset() + ic_check_size());
1371
1372 int uep_offset = offset();
1373
1374 #ifdef _LP64
1375 if (UseCompactObjectHeaders) {
1376 load_narrow_klass_compact(temp, receiver);
1377 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1378 } else
1379 #endif
1380 if (UseCompressedClassPointers) {
1381 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1382 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1383 } else {
1384 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1385 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
1386 }
1387
1388 // if inline cache check fails, then jump to runtime routine
1389 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1390 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
1391
1392 return uep_offset;
1393 }
1394
1395 void MacroAssembler::emit_static_call_stub() {
1396 // Static stub relocation also tags the Method* in the code-stream.
1397 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1398 // This is recognized as unresolved by relocs/nativeinst/ic code.
1399 jump(RuntimeAddress(pc()));
1400 }
1401
1402 // Implementation of call_VM versions
1403
1404 void MacroAssembler::call_VM(Register oop_result,
1405 address entry_point,
1406 bool check_exceptions) {
1407 Label C, E;
1408 call(C, relocInfo::none);
1409 jmp(E);
1410
1411 bind(C);
1412 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1413 ret(0);
1414
1415 bind(E);
1416 }
1417
1418 void MacroAssembler::call_VM(Register oop_result,
1419 address entry_point,
1420 Register arg_1,
1421 bool check_exceptions) {
1422 Label C, E;
1423 call(C, relocInfo::none);
1424 jmp(E);
1425
1426 bind(C);
1427 pass_arg1(this, arg_1);
1428 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1429 ret(0);
1430
1431 bind(E);
1432 }
1433
1434 void MacroAssembler::call_VM(Register oop_result,
1435 address entry_point,
1436 Register arg_1,
1437 Register arg_2,
1438 bool check_exceptions) {
1439 Label C, E;
1440 call(C, relocInfo::none);
1441 jmp(E);
1442
1443 bind(C);
1444
1445 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1446
1447 pass_arg2(this, arg_2);
1448 pass_arg1(this, arg_1);
1449 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1450 ret(0);
1451
1452 bind(E);
1453 }
1454
1455 void MacroAssembler::call_VM(Register oop_result,
1456 address entry_point,
1457 Register arg_1,
1458 Register arg_2,
1459 Register arg_3,
1460 bool check_exceptions) {
1461 Label C, E;
1462 call(C, relocInfo::none);
1463 jmp(E);
1464
1465 bind(C);
1466
1467 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1468 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1469 pass_arg3(this, arg_3);
1470 pass_arg2(this, arg_2);
1471 pass_arg1(this, arg_1);
1472 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1473 ret(0);
1474
1475 bind(E);
1476 }
1477
1478 void MacroAssembler::call_VM(Register oop_result,
1479 Register last_java_sp,
1480 address entry_point,
1481 int number_of_arguments,
1482 bool check_exceptions) {
1483 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1484 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1485 }
1486
1487 void MacroAssembler::call_VM(Register oop_result,
1488 Register last_java_sp,
1489 address entry_point,
1490 Register arg_1,
1491 bool check_exceptions) {
1492 pass_arg1(this, arg_1);
1493 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1494 }
1495
1496 void MacroAssembler::call_VM(Register oop_result,
1497 Register last_java_sp,
1498 address entry_point,
1499 Register arg_1,
1500 Register arg_2,
1501 bool check_exceptions) {
1502
1503 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1504 pass_arg2(this, arg_2);
1505 pass_arg1(this, arg_1);
1506 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1507 }
1508
1509 void MacroAssembler::call_VM(Register oop_result,
1510 Register last_java_sp,
1511 address entry_point,
1512 Register arg_1,
1513 Register arg_2,
1514 Register arg_3,
1515 bool check_exceptions) {
1516 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1517 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1518 pass_arg3(this, arg_3);
1519 pass_arg2(this, arg_2);
1520 pass_arg1(this, arg_1);
1521 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1522 }
1523
1524 void MacroAssembler::super_call_VM(Register oop_result,
1525 Register last_java_sp,
1526 address entry_point,
1527 int number_of_arguments,
1528 bool check_exceptions) {
1529 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1530 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1531 }
1532
1533 void MacroAssembler::super_call_VM(Register oop_result,
1534 Register last_java_sp,
1535 address entry_point,
1536 Register arg_1,
1537 bool check_exceptions) {
1538 pass_arg1(this, arg_1);
1539 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1540 }
1541
1542 void MacroAssembler::super_call_VM(Register oop_result,
1543 Register last_java_sp,
1544 address entry_point,
1545 Register arg_1,
1546 Register arg_2,
1547 bool check_exceptions) {
1548
1549 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1550 pass_arg2(this, arg_2);
1551 pass_arg1(this, arg_1);
1552 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1553 }
1554
1555 void MacroAssembler::super_call_VM(Register oop_result,
1556 Register last_java_sp,
1557 address entry_point,
1558 Register arg_1,
1559 Register arg_2,
1560 Register arg_3,
1561 bool check_exceptions) {
1562 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1563 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1564 pass_arg3(this, arg_3);
1565 pass_arg2(this, arg_2);
1566 pass_arg1(this, arg_1);
1567 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1568 }
1569
1570 void MacroAssembler::call_VM_base(Register oop_result,
1571 Register java_thread,
1572 Register last_java_sp,
1573 address entry_point,
1574 int number_of_arguments,
1575 bool check_exceptions) {
1576 // determine java_thread register
1577 if (!java_thread->is_valid()) {
1578 #ifdef _LP64
1579 java_thread = r15_thread;
1580 #else
1581 java_thread = rdi;
1582 get_thread(java_thread);
1583 #endif // LP64
1584 }
1585 // determine last_java_sp register
1586 if (!last_java_sp->is_valid()) {
1587 last_java_sp = rsp;
1588 }
1589 // debugging support
1590 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1591 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1592 #ifdef ASSERT
1593 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1594 // r12 is the heapbase.
1595 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1596 #endif // ASSERT
1597
1598 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1599 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1600
1601 // push java thread (becomes first argument of C function)
1602
1603 NOT_LP64(push(java_thread); number_of_arguments++);
1604 LP64_ONLY(mov(c_rarg0, r15_thread));
1605
1606 // set last Java frame before call
1607 assert(last_java_sp != rbp, "can't use ebp/rbp");
1608
1609 // Only interpreter should have to set fp
1610 set_last_Java_frame(java_thread, last_java_sp, rbp, nullptr, rscratch1);
1611
1612 // do the call, remove parameters
1613 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1614
1615 // restore the thread (cannot use the pushed argument since arguments
1616 // may be overwritten by C code generated by an optimizing compiler);
1617 // however can use the register value directly if it is callee saved.
1618 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1619 // rdi & rsi (also r15) are callee saved -> nothing to do
1620 #ifdef ASSERT
1621 guarantee(java_thread != rax, "change this code");
1622 push(rax);
1623 { Label L;
1624 get_thread(rax);
1625 cmpptr(java_thread, rax);
1626 jcc(Assembler::equal, L);
1627 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1628 bind(L);
1629 }
1630 pop(rax);
1631 #endif
1632 } else {
1633 get_thread(java_thread);
1634 }
1635 // reset last Java frame
1636 // Only interpreter should have to clear fp
1637 reset_last_Java_frame(java_thread, true);
1638
1639 // C++ interp handles this in the interpreter
1640 check_and_handle_popframe(java_thread);
1641 check_and_handle_earlyret(java_thread);
1642
1643 if (check_exceptions) {
1644 // check for pending exceptions (java_thread is set upon return)
1645 cmpptr(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
1646 #ifndef _LP64
1647 jump_cc(Assembler::notEqual,
1648 RuntimeAddress(StubRoutines::forward_exception_entry()));
1649 #else
1650 // This used to conditionally jump to forward_exception however it is
1651 // possible if we relocate that the branch will not reach. So we must jump
1652 // around so we can always reach
1653
1654 Label ok;
1655 jcc(Assembler::equal, ok);
1656 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1657 bind(ok);
1658 #endif // LP64
1659 }
1660
1661 // get oop result if there is one and reset the value in the thread
1662 if (oop_result->is_valid()) {
1663 get_vm_result(oop_result, java_thread);
1664 }
1665 }
1666
1667 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1668
1669 // Calculate the value for last_Java_sp
1670 // somewhat subtle. call_VM does an intermediate call
1671 // which places a return address on the stack just under the
1672 // stack pointer as the user finished with it. This allows
1673 // use to retrieve last_Java_pc from last_Java_sp[-1].
1674 // On 32bit we then have to push additional args on the stack to accomplish
1675 // the actual requested call. On 64bit call_VM only can use register args
1676 // so the only extra space is the return address that call_VM created.
1677 // This hopefully explains the calculations here.
1678
1679 #ifdef _LP64
1680 // We've pushed one address, correct last_Java_sp
1681 lea(rax, Address(rsp, wordSize));
1682 #else
1683 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1684 #endif // LP64
1685
1686 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1687
1688 }
1689
1690 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1691 void MacroAssembler::call_VM_leaf0(address entry_point) {
1692 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1693 }
1694
1695 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1696 call_VM_leaf_base(entry_point, number_of_arguments);
1697 }
1698
1699 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1700 pass_arg0(this, arg_0);
1701 call_VM_leaf(entry_point, 1);
1702 }
1703
1704 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1705
1706 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1707 pass_arg1(this, arg_1);
1708 pass_arg0(this, arg_0);
1709 call_VM_leaf(entry_point, 2);
1710 }
1711
1712 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1713 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1714 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1715 pass_arg2(this, arg_2);
1716 pass_arg1(this, arg_1);
1717 pass_arg0(this, arg_0);
1718 call_VM_leaf(entry_point, 3);
1719 }
1720
1721 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1722 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1723 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1724 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1725 pass_arg3(this, arg_3);
1726 pass_arg2(this, arg_2);
1727 pass_arg1(this, arg_1);
1728 pass_arg0(this, arg_0);
1729 call_VM_leaf(entry_point, 3);
1730 }
1731
1732 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1733 pass_arg0(this, arg_0);
1734 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1735 }
1736
1737 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1738 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1739 pass_arg1(this, arg_1);
1740 pass_arg0(this, arg_0);
1741 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1742 }
1743
1744 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1745 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1746 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1747 pass_arg2(this, arg_2);
1748 pass_arg1(this, arg_1);
1749 pass_arg0(this, arg_0);
1750 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1751 }
1752
1753 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1754 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1755 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1756 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1757 pass_arg3(this, arg_3);
1758 pass_arg2(this, arg_2);
1759 pass_arg1(this, arg_1);
1760 pass_arg0(this, arg_0);
1761 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1762 }
1763
1764 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1765 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1766 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1767 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1768 }
1769
1770 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1771 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1772 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1773 }
1774
1775 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1776 }
1777
1778 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1779 }
1780
1781 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1782 assert(rscratch != noreg || always_reachable(src1), "missing");
1783
1784 if (reachable(src1)) {
1785 cmpl(as_Address(src1), imm);
1786 } else {
1787 lea(rscratch, src1);
1788 cmpl(Address(rscratch, 0), imm);
1789 }
1790 }
1791
1792 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1793 assert(!src2.is_lval(), "use cmpptr");
1794 assert(rscratch != noreg || always_reachable(src2), "missing");
1795
1796 if (reachable(src2)) {
1797 cmpl(src1, as_Address(src2));
1798 } else {
1799 lea(rscratch, src2);
1800 cmpl(src1, Address(rscratch, 0));
1801 }
1802 }
1803
1804 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1805 Assembler::cmpl(src1, imm);
1806 }
1807
1808 void MacroAssembler::cmp32(Register src1, Address src2) {
1809 Assembler::cmpl(src1, src2);
1810 }
1811
1812 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1813 ucomisd(opr1, opr2);
1814
1815 Label L;
1816 if (unordered_is_less) {
1817 movl(dst, -1);
1818 jcc(Assembler::parity, L);
1819 jcc(Assembler::below , L);
1820 movl(dst, 0);
1821 jcc(Assembler::equal , L);
1822 increment(dst);
1823 } else { // unordered is greater
1824 movl(dst, 1);
1825 jcc(Assembler::parity, L);
1826 jcc(Assembler::above , L);
1827 movl(dst, 0);
1828 jcc(Assembler::equal , L);
1829 decrementl(dst);
1830 }
1831 bind(L);
1832 }
1833
1834 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1835 ucomiss(opr1, opr2);
1836
1837 Label L;
1838 if (unordered_is_less) {
1839 movl(dst, -1);
1840 jcc(Assembler::parity, L);
1841 jcc(Assembler::below , L);
1842 movl(dst, 0);
1843 jcc(Assembler::equal , L);
1844 increment(dst);
1845 } else { // unordered is greater
1846 movl(dst, 1);
1847 jcc(Assembler::parity, L);
1848 jcc(Assembler::above , L);
1849 movl(dst, 0);
1850 jcc(Assembler::equal , L);
1851 decrementl(dst);
1852 }
1853 bind(L);
1854 }
1855
1856
1857 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1858 assert(rscratch != noreg || always_reachable(src1), "missing");
1859
1860 if (reachable(src1)) {
1861 cmpb(as_Address(src1), imm);
1862 } else {
1863 lea(rscratch, src1);
1864 cmpb(Address(rscratch, 0), imm);
1865 }
1866 }
1867
1868 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1869 #ifdef _LP64
1870 assert(rscratch != noreg || always_reachable(src2), "missing");
1871
1872 if (src2.is_lval()) {
1873 movptr(rscratch, src2);
1874 Assembler::cmpq(src1, rscratch);
1875 } else if (reachable(src2)) {
1876 cmpq(src1, as_Address(src2));
1877 } else {
1878 lea(rscratch, src2);
1879 Assembler::cmpq(src1, Address(rscratch, 0));
1880 }
1881 #else
1882 assert(rscratch == noreg, "not needed");
1883 if (src2.is_lval()) {
1884 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1885 } else {
1886 cmpl(src1, as_Address(src2));
1887 }
1888 #endif // _LP64
1889 }
1890
1891 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1892 assert(src2.is_lval(), "not a mem-mem compare");
1893 #ifdef _LP64
1894 // moves src2's literal address
1895 movptr(rscratch, src2);
1896 Assembler::cmpq(src1, rscratch);
1897 #else
1898 assert(rscratch == noreg, "not needed");
1899 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1900 #endif // _LP64
1901 }
1902
1903 void MacroAssembler::cmpoop(Register src1, Register src2) {
1904 cmpptr(src1, src2);
1905 }
1906
1907 void MacroAssembler::cmpoop(Register src1, Address src2) {
1908 cmpptr(src1, src2);
1909 }
1910
1911 #ifdef _LP64
1912 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1913 movoop(rscratch, src2);
1914 cmpptr(src1, rscratch);
1915 }
1916 #endif
1917
1918 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1919 assert(rscratch != noreg || always_reachable(adr), "missing");
1920
1921 if (reachable(adr)) {
1922 lock();
1923 cmpxchgptr(reg, as_Address(adr));
1924 } else {
1925 lea(rscratch, adr);
1926 lock();
1927 cmpxchgptr(reg, Address(rscratch, 0));
1928 }
1929 }
1930
1931 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1932 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1933 }
1934
1935 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1936 assert(rscratch != noreg || always_reachable(src), "missing");
1937
1938 if (reachable(src)) {
1939 Assembler::comisd(dst, as_Address(src));
1940 } else {
1941 lea(rscratch, src);
1942 Assembler::comisd(dst, Address(rscratch, 0));
1943 }
1944 }
1945
1946 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1947 assert(rscratch != noreg || always_reachable(src), "missing");
1948
1949 if (reachable(src)) {
1950 Assembler::comiss(dst, as_Address(src));
1951 } else {
1952 lea(rscratch, src);
1953 Assembler::comiss(dst, Address(rscratch, 0));
1954 }
1955 }
1956
1957
1958 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1959 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1960
1961 Condition negated_cond = negate_condition(cond);
1962 Label L;
1963 jcc(negated_cond, L);
1964 pushf(); // Preserve flags
1965 atomic_incl(counter_addr, rscratch);
1966 popf();
1967 bind(L);
1968 }
1969
1970 int MacroAssembler::corrected_idivl(Register reg) {
1971 // Full implementation of Java idiv and irem; checks for
1972 // special case as described in JVM spec., p.243 & p.271.
1973 // The function returns the (pc) offset of the idivl
1974 // instruction - may be needed for implicit exceptions.
1975 //
1976 // normal case special case
1977 //
1978 // input : rax,: dividend min_int
1979 // reg: divisor (may not be rax,/rdx) -1
1980 //
1981 // output: rax,: quotient (= rax, idiv reg) min_int
1982 // rdx: remainder (= rax, irem reg) 0
1983 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1984 const int min_int = 0x80000000;
1985 Label normal_case, special_case;
1986
1987 // check for special case
1988 cmpl(rax, min_int);
1989 jcc(Assembler::notEqual, normal_case);
1990 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1991 cmpl(reg, -1);
1992 jcc(Assembler::equal, special_case);
1993
1994 // handle normal case
1995 bind(normal_case);
1996 cdql();
1997 int idivl_offset = offset();
1998 idivl(reg);
1999
2000 // normal and special case exit
2001 bind(special_case);
2002
2003 return idivl_offset;
2004 }
2005
2006
2007
2008 void MacroAssembler::decrementl(Register reg, int value) {
2009 if (value == min_jint) {subl(reg, value) ; return; }
2010 if (value < 0) { incrementl(reg, -value); return; }
2011 if (value == 0) { ; return; }
2012 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2013 /* else */ { subl(reg, value) ; return; }
2014 }
2015
2016 void MacroAssembler::decrementl(Address dst, int value) {
2017 if (value == min_jint) {subl(dst, value) ; return; }
2018 if (value < 0) { incrementl(dst, -value); return; }
2019 if (value == 0) { ; return; }
2020 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2021 /* else */ { subl(dst, value) ; return; }
2022 }
2023
2024 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2025 assert(shift_value > 0, "illegal shift value");
2026 Label _is_positive;
2027 testl (reg, reg);
2028 jcc (Assembler::positive, _is_positive);
2029 int offset = (1 << shift_value) - 1 ;
2030
2031 if (offset == 1) {
2032 incrementl(reg);
2033 } else {
2034 addl(reg, offset);
2035 }
2036
2037 bind (_is_positive);
2038 sarl(reg, shift_value);
2039 }
2040
2041 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2042 assert(rscratch != noreg || always_reachable(src), "missing");
2043
2044 if (reachable(src)) {
2045 Assembler::divsd(dst, as_Address(src));
2046 } else {
2047 lea(rscratch, src);
2048 Assembler::divsd(dst, Address(rscratch, 0));
2049 }
2050 }
2051
2052 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2053 assert(rscratch != noreg || always_reachable(src), "missing");
2054
2055 if (reachable(src)) {
2056 Assembler::divss(dst, as_Address(src));
2057 } else {
2058 lea(rscratch, src);
2059 Assembler::divss(dst, Address(rscratch, 0));
2060 }
2061 }
2062
2063 void MacroAssembler::enter() {
2064 push(rbp);
2065 mov(rbp, rsp);
2066 }
2067
2068 void MacroAssembler::post_call_nop() {
2069 if (!Continuations::enabled()) {
2070 return;
2071 }
2072 InstructionMark im(this);
2073 relocate(post_call_nop_Relocation::spec());
2074 InlineSkippedInstructionsCounter skipCounter(this);
2075 emit_int8((uint8_t)0x0f);
2076 emit_int8((uint8_t)0x1f);
2077 emit_int8((uint8_t)0x84);
2078 emit_int8((uint8_t)0x00);
2079 emit_int32(0x00);
2080 }
2081
2082 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2083 void MacroAssembler::fat_nop() {
2084 if (UseAddressNop) {
2085 addr_nop_5();
2086 } else {
2087 emit_int8((uint8_t)0x26); // es:
2088 emit_int8((uint8_t)0x2e); // cs:
2089 emit_int8((uint8_t)0x64); // fs:
2090 emit_int8((uint8_t)0x65); // gs:
2091 emit_int8((uint8_t)0x90);
2092 }
2093 }
2094
2095 #ifndef _LP64
2096 void MacroAssembler::fcmp(Register tmp) {
2097 fcmp(tmp, 1, true, true);
2098 }
2099
2100 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2101 assert(!pop_right || pop_left, "usage error");
2102 if (VM_Version::supports_cmov()) {
2103 assert(tmp == noreg, "unneeded temp");
2104 if (pop_left) {
2105 fucomip(index);
2106 } else {
2107 fucomi(index);
2108 }
2109 if (pop_right) {
2110 fpop();
2111 }
2112 } else {
2113 assert(tmp != noreg, "need temp");
2114 if (pop_left) {
2115 if (pop_right) {
2116 fcompp();
2117 } else {
2118 fcomp(index);
2119 }
2120 } else {
2121 fcom(index);
2122 }
2123 // convert FPU condition into eflags condition via rax,
2124 save_rax(tmp);
2125 fwait(); fnstsw_ax();
2126 sahf();
2127 restore_rax(tmp);
2128 }
2129 // condition codes set as follows:
2130 //
2131 // CF (corresponds to C0) if x < y
2132 // PF (corresponds to C2) if unordered
2133 // ZF (corresponds to C3) if x = y
2134 }
2135
2136 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2137 fcmp2int(dst, unordered_is_less, 1, true, true);
2138 }
2139
2140 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2141 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2142 Label L;
2143 if (unordered_is_less) {
2144 movl(dst, -1);
2145 jcc(Assembler::parity, L);
2146 jcc(Assembler::below , L);
2147 movl(dst, 0);
2148 jcc(Assembler::equal , L);
2149 increment(dst);
2150 } else { // unordered is greater
2151 movl(dst, 1);
2152 jcc(Assembler::parity, L);
2153 jcc(Assembler::above , L);
2154 movl(dst, 0);
2155 jcc(Assembler::equal , L);
2156 decrementl(dst);
2157 }
2158 bind(L);
2159 }
2160
2161 void MacroAssembler::fld_d(AddressLiteral src) {
2162 fld_d(as_Address(src));
2163 }
2164
2165 void MacroAssembler::fld_s(AddressLiteral src) {
2166 fld_s(as_Address(src));
2167 }
2168
2169 void MacroAssembler::fldcw(AddressLiteral src) {
2170 fldcw(as_Address(src));
2171 }
2172
2173 void MacroAssembler::fpop() {
2174 ffree();
2175 fincstp();
2176 }
2177
2178 void MacroAssembler::fremr(Register tmp) {
2179 save_rax(tmp);
2180 { Label L;
2181 bind(L);
2182 fprem();
2183 fwait(); fnstsw_ax();
2184 sahf();
2185 jcc(Assembler::parity, L);
2186 }
2187 restore_rax(tmp);
2188 // Result is in ST0.
2189 // Note: fxch & fpop to get rid of ST1
2190 // (otherwise FPU stack could overflow eventually)
2191 fxch(1);
2192 fpop();
2193 }
2194
2195 void MacroAssembler::empty_FPU_stack() {
2196 if (VM_Version::supports_mmx()) {
2197 emms();
2198 } else {
2199 for (int i = 8; i-- > 0; ) ffree(i);
2200 }
2201 }
2202 #endif // !LP64
2203
2204 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2205 assert(rscratch != noreg || always_reachable(src), "missing");
2206 if (reachable(src)) {
2207 Assembler::mulpd(dst, as_Address(src));
2208 } else {
2209 lea(rscratch, src);
2210 Assembler::mulpd(dst, Address(rscratch, 0));
2211 }
2212 }
2213
2214 void MacroAssembler::load_float(Address src) {
2215 #ifdef _LP64
2216 movflt(xmm0, src);
2217 #else
2218 if (UseSSE >= 1) {
2219 movflt(xmm0, src);
2220 } else {
2221 fld_s(src);
2222 }
2223 #endif // LP64
2224 }
2225
2226 void MacroAssembler::store_float(Address dst) {
2227 #ifdef _LP64
2228 movflt(dst, xmm0);
2229 #else
2230 if (UseSSE >= 1) {
2231 movflt(dst, xmm0);
2232 } else {
2233 fstp_s(dst);
2234 }
2235 #endif // LP64
2236 }
2237
2238 void MacroAssembler::load_double(Address src) {
2239 #ifdef _LP64
2240 movdbl(xmm0, src);
2241 #else
2242 if (UseSSE >= 2) {
2243 movdbl(xmm0, src);
2244 } else {
2245 fld_d(src);
2246 }
2247 #endif // LP64
2248 }
2249
2250 void MacroAssembler::store_double(Address dst) {
2251 #ifdef _LP64
2252 movdbl(dst, xmm0);
2253 #else
2254 if (UseSSE >= 2) {
2255 movdbl(dst, xmm0);
2256 } else {
2257 fstp_d(dst);
2258 }
2259 #endif // LP64
2260 }
2261
2262 // dst = c = a * b + c
2263 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2264 Assembler::vfmadd231sd(c, a, b);
2265 if (dst != c) {
2266 movdbl(dst, c);
2267 }
2268 }
2269
2270 // dst = c = a * b + c
2271 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2272 Assembler::vfmadd231ss(c, a, b);
2273 if (dst != c) {
2274 movflt(dst, c);
2275 }
2276 }
2277
2278 // dst = c = a * b + c
2279 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2280 Assembler::vfmadd231pd(c, a, b, vector_len);
2281 if (dst != c) {
2282 vmovdqu(dst, c);
2283 }
2284 }
2285
2286 // dst = c = a * b + c
2287 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2288 Assembler::vfmadd231ps(c, a, b, vector_len);
2289 if (dst != c) {
2290 vmovdqu(dst, c);
2291 }
2292 }
2293
2294 // dst = c = a * b + c
2295 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2296 Assembler::vfmadd231pd(c, a, b, vector_len);
2297 if (dst != c) {
2298 vmovdqu(dst, c);
2299 }
2300 }
2301
2302 // dst = c = a * b + c
2303 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2304 Assembler::vfmadd231ps(c, a, b, vector_len);
2305 if (dst != c) {
2306 vmovdqu(dst, c);
2307 }
2308 }
2309
2310 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
2311 assert(rscratch != noreg || always_reachable(dst), "missing");
2312
2313 if (reachable(dst)) {
2314 incrementl(as_Address(dst));
2315 } else {
2316 lea(rscratch, dst);
2317 incrementl(Address(rscratch, 0));
2318 }
2319 }
2320
2321 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
2322 incrementl(as_Address(dst, rscratch));
2323 }
2324
2325 void MacroAssembler::incrementl(Register reg, int value) {
2326 if (value == min_jint) {addl(reg, value) ; return; }
2327 if (value < 0) { decrementl(reg, -value); return; }
2328 if (value == 0) { ; return; }
2329 if (value == 1 && UseIncDec) { incl(reg) ; return; }
2330 /* else */ { addl(reg, value) ; return; }
2331 }
2332
2333 void MacroAssembler::incrementl(Address dst, int value) {
2334 if (value == min_jint) {addl(dst, value) ; return; }
2335 if (value < 0) { decrementl(dst, -value); return; }
2336 if (value == 0) { ; return; }
2337 if (value == 1 && UseIncDec) { incl(dst) ; return; }
2338 /* else */ { addl(dst, value) ; return; }
2339 }
2340
2341 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
2342 assert(rscratch != noreg || always_reachable(dst), "missing");
2343 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
2344 if (reachable(dst)) {
2345 jmp_literal(dst.target(), dst.rspec());
2346 } else {
2347 lea(rscratch, dst);
2348 jmp(rscratch);
2349 }
2350 }
2351
2352 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
2353 assert(rscratch != noreg || always_reachable(dst), "missing");
2354 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
2355 if (reachable(dst)) {
2356 InstructionMark im(this);
2357 relocate(dst.reloc());
2358 const int short_size = 2;
2359 const int long_size = 6;
2360 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2361 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2362 // 0111 tttn #8-bit disp
2363 emit_int8(0x70 | cc);
2364 emit_int8((offs - short_size) & 0xFF);
2365 } else {
2366 // 0000 1111 1000 tttn #32-bit disp
2367 emit_int8(0x0F);
2368 emit_int8((unsigned char)(0x80 | cc));
2369 emit_int32(offs - long_size);
2370 }
2371 } else {
2372 #ifdef ASSERT
2373 warning("reversing conditional branch");
2374 #endif /* ASSERT */
2375 Label skip;
2376 jccb(reverse[cc], skip);
2377 lea(rscratch, dst);
2378 Assembler::jmp(rscratch);
2379 bind(skip);
2380 }
2381 }
2382
2383 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
2384 assert(rscratch != noreg || always_reachable(src), "missing");
2385
2386 if (reachable(src)) {
2387 Assembler::ldmxcsr(as_Address(src));
2388 } else {
2389 lea(rscratch, src);
2390 Assembler::ldmxcsr(Address(rscratch, 0));
2391 }
2392 }
2393
2394 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2395 int off;
2396 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2397 off = offset();
2398 movsbl(dst, src); // movsxb
2399 } else {
2400 off = load_unsigned_byte(dst, src);
2401 shll(dst, 24);
2402 sarl(dst, 24);
2403 }
2404 return off;
2405 }
2406
2407 // Note: load_signed_short used to be called load_signed_word.
2408 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2409 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2410 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2411 int MacroAssembler::load_signed_short(Register dst, Address src) {
2412 int off;
2413 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2414 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2415 // version but this is what 64bit has always done. This seems to imply
2416 // that users are only using 32bits worth.
2417 off = offset();
2418 movswl(dst, src); // movsxw
2419 } else {
2420 off = load_unsigned_short(dst, src);
2421 shll(dst, 16);
2422 sarl(dst, 16);
2423 }
2424 return off;
2425 }
2426
2427 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2428 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2429 // and "3.9 Partial Register Penalties", p. 22).
2430 int off;
2431 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2432 off = offset();
2433 movzbl(dst, src); // movzxb
2434 } else {
2435 xorl(dst, dst);
2436 off = offset();
2437 movb(dst, src);
2438 }
2439 return off;
2440 }
2441
2442 // Note: load_unsigned_short used to be called load_unsigned_word.
2443 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2444 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2445 // and "3.9 Partial Register Penalties", p. 22).
2446 int off;
2447 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2448 off = offset();
2449 movzwl(dst, src); // movzxw
2450 } else {
2451 xorl(dst, dst);
2452 off = offset();
2453 movw(dst, src);
2454 }
2455 return off;
2456 }
2457
2458 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2459 switch (size_in_bytes) {
2460 #ifndef _LP64
2461 case 8:
2462 assert(dst2 != noreg, "second dest register required");
2463 movl(dst, src);
2464 movl(dst2, src.plus_disp(BytesPerInt));
2465 break;
2466 #else
2467 case 8: movq(dst, src); break;
2468 #endif
2469 case 4: movl(dst, src); break;
2470 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2471 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2472 default: ShouldNotReachHere();
2473 }
2474 }
2475
2476 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2477 switch (size_in_bytes) {
2478 #ifndef _LP64
2479 case 8:
2480 assert(src2 != noreg, "second source register required");
2481 movl(dst, src);
2482 movl(dst.plus_disp(BytesPerInt), src2);
2483 break;
2484 #else
2485 case 8: movq(dst, src); break;
2486 #endif
2487 case 4: movl(dst, src); break;
2488 case 2: movw(dst, src); break;
2489 case 1: movb(dst, src); break;
2490 default: ShouldNotReachHere();
2491 }
2492 }
2493
2494 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
2495 assert(rscratch != noreg || always_reachable(dst), "missing");
2496
2497 if (reachable(dst)) {
2498 movl(as_Address(dst), src);
2499 } else {
2500 lea(rscratch, dst);
2501 movl(Address(rscratch, 0), src);
2502 }
2503 }
2504
2505 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2506 if (reachable(src)) {
2507 movl(dst, as_Address(src));
2508 } else {
2509 lea(dst, src);
2510 movl(dst, Address(dst, 0));
2511 }
2512 }
2513
2514 // C++ bool manipulation
2515
2516 void MacroAssembler::movbool(Register dst, Address src) {
2517 if(sizeof(bool) == 1)
2518 movb(dst, src);
2519 else if(sizeof(bool) == 2)
2520 movw(dst, src);
2521 else if(sizeof(bool) == 4)
2522 movl(dst, src);
2523 else
2524 // unsupported
2525 ShouldNotReachHere();
2526 }
2527
2528 void MacroAssembler::movbool(Address dst, bool boolconst) {
2529 if(sizeof(bool) == 1)
2530 movb(dst, (int) boolconst);
2531 else if(sizeof(bool) == 2)
2532 movw(dst, (int) boolconst);
2533 else if(sizeof(bool) == 4)
2534 movl(dst, (int) boolconst);
2535 else
2536 // unsupported
2537 ShouldNotReachHere();
2538 }
2539
2540 void MacroAssembler::movbool(Address dst, Register src) {
2541 if(sizeof(bool) == 1)
2542 movb(dst, src);
2543 else if(sizeof(bool) == 2)
2544 movw(dst, src);
2545 else if(sizeof(bool) == 4)
2546 movl(dst, src);
2547 else
2548 // unsupported
2549 ShouldNotReachHere();
2550 }
2551
2552 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2553 assert(rscratch != noreg || always_reachable(src), "missing");
2554
2555 if (reachable(src)) {
2556 movdl(dst, as_Address(src));
2557 } else {
2558 lea(rscratch, src);
2559 movdl(dst, Address(rscratch, 0));
2560 }
2561 }
2562
2563 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
2564 assert(rscratch != noreg || always_reachable(src), "missing");
2565
2566 if (reachable(src)) {
2567 movq(dst, as_Address(src));
2568 } else {
2569 lea(rscratch, src);
2570 movq(dst, Address(rscratch, 0));
2571 }
2572 }
2573
2574 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2575 assert(rscratch != noreg || always_reachable(src), "missing");
2576
2577 if (reachable(src)) {
2578 if (UseXmmLoadAndClearUpper) {
2579 movsd (dst, as_Address(src));
2580 } else {
2581 movlpd(dst, as_Address(src));
2582 }
2583 } else {
2584 lea(rscratch, src);
2585 if (UseXmmLoadAndClearUpper) {
2586 movsd (dst, Address(rscratch, 0));
2587 } else {
2588 movlpd(dst, Address(rscratch, 0));
2589 }
2590 }
2591 }
2592
2593 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
2594 assert(rscratch != noreg || always_reachable(src), "missing");
2595
2596 if (reachable(src)) {
2597 movss(dst, as_Address(src));
2598 } else {
2599 lea(rscratch, src);
2600 movss(dst, Address(rscratch, 0));
2601 }
2602 }
2603
2604 void MacroAssembler::movptr(Register dst, Register src) {
2605 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2606 }
2607
2608 void MacroAssembler::movptr(Register dst, Address src) {
2609 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2610 }
2611
2612 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2613 void MacroAssembler::movptr(Register dst, intptr_t src) {
2614 #ifdef _LP64
2615 if (is_uimm32(src)) {
2616 movl(dst, checked_cast<uint32_t>(src));
2617 } else if (is_simm32(src)) {
2618 movq(dst, checked_cast<int32_t>(src));
2619 } else {
2620 mov64(dst, src);
2621 }
2622 #else
2623 movl(dst, src);
2624 #endif
2625 }
2626
2627 void MacroAssembler::movptr(Address dst, Register src) {
2628 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2629 }
2630
2631 void MacroAssembler::movptr(Address dst, int32_t src) {
2632 LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src));
2633 }
2634
2635 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2636 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2637 Assembler::movdqu(dst, src);
2638 }
2639
2640 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2641 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2642 Assembler::movdqu(dst, src);
2643 }
2644
2645 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2646 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2647 Assembler::movdqu(dst, src);
2648 }
2649
2650 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2651 assert(rscratch != noreg || always_reachable(src), "missing");
2652
2653 if (reachable(src)) {
2654 movdqu(dst, as_Address(src));
2655 } else {
2656 lea(rscratch, src);
2657 movdqu(dst, Address(rscratch, 0));
2658 }
2659 }
2660
2661 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2662 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2663 Assembler::vmovdqu(dst, src);
2664 }
2665
2666 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2667 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2668 Assembler::vmovdqu(dst, src);
2669 }
2670
2671 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2672 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2673 Assembler::vmovdqu(dst, src);
2674 }
2675
2676 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2677 assert(rscratch != noreg || always_reachable(src), "missing");
2678
2679 if (reachable(src)) {
2680 vmovdqu(dst, as_Address(src));
2681 }
2682 else {
2683 lea(rscratch, src);
2684 vmovdqu(dst, Address(rscratch, 0));
2685 }
2686 }
2687
2688 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2689 assert(rscratch != noreg || always_reachable(src), "missing");
2690
2691 if (vector_len == AVX_512bit) {
2692 evmovdquq(dst, src, AVX_512bit, rscratch);
2693 } else if (vector_len == AVX_256bit) {
2694 vmovdqu(dst, src, rscratch);
2695 } else {
2696 movdqu(dst, src, rscratch);
2697 }
2698 }
2699
2700 void MacroAssembler::kmov(KRegister dst, Address src) {
2701 if (VM_Version::supports_avx512bw()) {
2702 kmovql(dst, src);
2703 } else {
2704 assert(VM_Version::supports_evex(), "");
2705 kmovwl(dst, src);
2706 }
2707 }
2708
2709 void MacroAssembler::kmov(Address dst, KRegister src) {
2710 if (VM_Version::supports_avx512bw()) {
2711 kmovql(dst, src);
2712 } else {
2713 assert(VM_Version::supports_evex(), "");
2714 kmovwl(dst, src);
2715 }
2716 }
2717
2718 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2719 if (VM_Version::supports_avx512bw()) {
2720 kmovql(dst, src);
2721 } else {
2722 assert(VM_Version::supports_evex(), "");
2723 kmovwl(dst, src);
2724 }
2725 }
2726
2727 void MacroAssembler::kmov(Register dst, KRegister src) {
2728 if (VM_Version::supports_avx512bw()) {
2729 kmovql(dst, src);
2730 } else {
2731 assert(VM_Version::supports_evex(), "");
2732 kmovwl(dst, src);
2733 }
2734 }
2735
2736 void MacroAssembler::kmov(KRegister dst, Register src) {
2737 if (VM_Version::supports_avx512bw()) {
2738 kmovql(dst, src);
2739 } else {
2740 assert(VM_Version::supports_evex(), "");
2741 kmovwl(dst, src);
2742 }
2743 }
2744
2745 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2746 assert(rscratch != noreg || always_reachable(src), "missing");
2747
2748 if (reachable(src)) {
2749 kmovql(dst, as_Address(src));
2750 } else {
2751 lea(rscratch, src);
2752 kmovql(dst, Address(rscratch, 0));
2753 }
2754 }
2755
2756 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2757 assert(rscratch != noreg || always_reachable(src), "missing");
2758
2759 if (reachable(src)) {
2760 kmovwl(dst, as_Address(src));
2761 } else {
2762 lea(rscratch, src);
2763 kmovwl(dst, Address(rscratch, 0));
2764 }
2765 }
2766
2767 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2768 int vector_len, Register rscratch) {
2769 assert(rscratch != noreg || always_reachable(src), "missing");
2770
2771 if (reachable(src)) {
2772 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2773 } else {
2774 lea(rscratch, src);
2775 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2776 }
2777 }
2778
2779 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2780 int vector_len, Register rscratch) {
2781 assert(rscratch != noreg || always_reachable(src), "missing");
2782
2783 if (reachable(src)) {
2784 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2785 } else {
2786 lea(rscratch, src);
2787 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2788 }
2789 }
2790
2791 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2792 assert(rscratch != noreg || always_reachable(src), "missing");
2793
2794 if (reachable(src)) {
2795 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2796 } else {
2797 lea(rscratch, src);
2798 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2799 }
2800 }
2801
2802 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2803 assert(rscratch != noreg || always_reachable(src), "missing");
2804
2805 if (reachable(src)) {
2806 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2807 } else {
2808 lea(rscratch, src);
2809 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2810 }
2811 }
2812
2813 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2814 assert(rscratch != noreg || always_reachable(src), "missing");
2815
2816 if (reachable(src)) {
2817 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2818 } else {
2819 lea(rscratch, src);
2820 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2821 }
2822 }
2823
2824 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2825 assert(rscratch != noreg || always_reachable(src), "missing");
2826
2827 if (reachable(src)) {
2828 Assembler::movdqa(dst, as_Address(src));
2829 } else {
2830 lea(rscratch, src);
2831 Assembler::movdqa(dst, Address(rscratch, 0));
2832 }
2833 }
2834
2835 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2836 assert(rscratch != noreg || always_reachable(src), "missing");
2837
2838 if (reachable(src)) {
2839 Assembler::movsd(dst, as_Address(src));
2840 } else {
2841 lea(rscratch, src);
2842 Assembler::movsd(dst, Address(rscratch, 0));
2843 }
2844 }
2845
2846 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2847 assert(rscratch != noreg || always_reachable(src), "missing");
2848
2849 if (reachable(src)) {
2850 Assembler::movss(dst, as_Address(src));
2851 } else {
2852 lea(rscratch, src);
2853 Assembler::movss(dst, Address(rscratch, 0));
2854 }
2855 }
2856
2857 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2858 assert(rscratch != noreg || always_reachable(src), "missing");
2859
2860 if (reachable(src)) {
2861 Assembler::movddup(dst, as_Address(src));
2862 } else {
2863 lea(rscratch, src);
2864 Assembler::movddup(dst, Address(rscratch, 0));
2865 }
2866 }
2867
2868 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2869 assert(rscratch != noreg || always_reachable(src), "missing");
2870
2871 if (reachable(src)) {
2872 Assembler::vmovddup(dst, as_Address(src), vector_len);
2873 } else {
2874 lea(rscratch, src);
2875 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2876 }
2877 }
2878
2879 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2880 assert(rscratch != noreg || always_reachable(src), "missing");
2881
2882 if (reachable(src)) {
2883 Assembler::mulsd(dst, as_Address(src));
2884 } else {
2885 lea(rscratch, src);
2886 Assembler::mulsd(dst, Address(rscratch, 0));
2887 }
2888 }
2889
2890 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2891 assert(rscratch != noreg || always_reachable(src), "missing");
2892
2893 if (reachable(src)) {
2894 Assembler::mulss(dst, as_Address(src));
2895 } else {
2896 lea(rscratch, src);
2897 Assembler::mulss(dst, Address(rscratch, 0));
2898 }
2899 }
2900
2901 void MacroAssembler::null_check(Register reg, int offset) {
2902 if (needs_explicit_null_check(offset)) {
2903 // provoke OS null exception if reg is null by
2904 // accessing M[reg] w/o changing any (non-CC) registers
2905 // NOTE: cmpl is plenty here to provoke a segv
2906 cmpptr(rax, Address(reg, 0));
2907 // Note: should probably use testl(rax, Address(reg, 0));
2908 // may be shorter code (however, this version of
2909 // testl needs to be implemented first)
2910 } else {
2911 // nothing to do, (later) access of M[reg + offset]
2912 // will provoke OS null exception if reg is null
2913 }
2914 }
2915
2916 void MacroAssembler::os_breakpoint() {
2917 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2918 // (e.g., MSVC can't call ps() otherwise)
2919 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2920 }
2921
2922 void MacroAssembler::unimplemented(const char* what) {
2923 const char* buf = nullptr;
2924 {
2925 ResourceMark rm;
2926 stringStream ss;
2927 ss.print("unimplemented: %s", what);
2928 buf = code_string(ss.as_string());
2929 }
2930 stop(buf);
2931 }
2932
2933 #ifdef _LP64
2934 #define XSTATE_BV 0x200
2935 #endif
2936
2937 void MacroAssembler::pop_CPU_state() {
2938 pop_FPU_state();
2939 pop_IU_state();
2940 }
2941
2942 void MacroAssembler::pop_FPU_state() {
2943 #ifndef _LP64
2944 frstor(Address(rsp, 0));
2945 #else
2946 fxrstor(Address(rsp, 0));
2947 #endif
2948 addptr(rsp, FPUStateSizeInWords * wordSize);
2949 }
2950
2951 void MacroAssembler::pop_IU_state() {
2952 popa();
2953 LP64_ONLY(addq(rsp, 8));
2954 popf();
2955 }
2956
2957 // Save Integer and Float state
2958 // Warning: Stack must be 16 byte aligned (64bit)
2959 void MacroAssembler::push_CPU_state() {
2960 push_IU_state();
2961 push_FPU_state();
2962 }
2963
2964 void MacroAssembler::push_FPU_state() {
2965 subptr(rsp, FPUStateSizeInWords * wordSize);
2966 #ifndef _LP64
2967 fnsave(Address(rsp, 0));
2968 fwait();
2969 #else
2970 fxsave(Address(rsp, 0));
2971 #endif // LP64
2972 }
2973
2974 void MacroAssembler::push_IU_state() {
2975 // Push flags first because pusha kills them
2976 pushf();
2977 // Make sure rsp stays 16-byte aligned
2978 LP64_ONLY(subq(rsp, 8));
2979 pusha();
2980 }
2981
2982 void MacroAssembler::push_cont_fastpath() {
2983 if (!Continuations::enabled()) return;
2984
2985 #ifndef _LP64
2986 Register rthread = rax;
2987 Register rrealsp = rbx;
2988 push(rthread);
2989 push(rrealsp);
2990
2991 get_thread(rthread);
2992
2993 // The code below wants the original RSP.
2994 // Move it back after the pushes above.
2995 movptr(rrealsp, rsp);
2996 addptr(rrealsp, 2*wordSize);
2997 #else
2998 Register rthread = r15_thread;
2999 Register rrealsp = rsp;
3000 #endif
3001
3002 Label done;
3003 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3004 jccb(Assembler::belowEqual, done);
3005 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), rrealsp);
3006 bind(done);
3007
3008 #ifndef _LP64
3009 pop(rrealsp);
3010 pop(rthread);
3011 #endif
3012 }
3013
3014 void MacroAssembler::pop_cont_fastpath() {
3015 if (!Continuations::enabled()) return;
3016
3017 #ifndef _LP64
3018 Register rthread = rax;
3019 Register rrealsp = rbx;
3020 push(rthread);
3021 push(rrealsp);
3022
3023 get_thread(rthread);
3024
3025 // The code below wants the original RSP.
3026 // Move it back after the pushes above.
3027 movptr(rrealsp, rsp);
3028 addptr(rrealsp, 2*wordSize);
3029 #else
3030 Register rthread = r15_thread;
3031 Register rrealsp = rsp;
3032 #endif
3033
3034 Label done;
3035 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3036 jccb(Assembler::below, done);
3037 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), 0);
3038 bind(done);
3039
3040 #ifndef _LP64
3041 pop(rrealsp);
3042 pop(rthread);
3043 #endif
3044 }
3045
3046 void MacroAssembler::inc_held_monitor_count() {
3047 #ifdef _LP64
3048 incrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3049 #endif
3050 }
3051
3052 void MacroAssembler::dec_held_monitor_count() {
3053 #ifdef _LP64
3054 decrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3055 #endif
3056 }
3057
3058 #ifdef ASSERT
3059 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
3060 #ifdef _LP64
3061 Label no_cont;
3062 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
3063 testl(cont, cont);
3064 jcc(Assembler::zero, no_cont);
3065 stop(name);
3066 bind(no_cont);
3067 #else
3068 Unimplemented();
3069 #endif
3070 }
3071 #endif
3072
3073 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3074 if (!java_thread->is_valid()) {
3075 java_thread = rdi;
3076 get_thread(java_thread);
3077 }
3078 // we must set sp to zero to clear frame
3079 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3080 // must clear fp, so that compiled frames are not confused; it is
3081 // possible that we need it only for debugging
3082 if (clear_fp) {
3083 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3084 }
3085 // Always clear the pc because it could have been set by make_walkable()
3086 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3087 vzeroupper();
3088 }
3089
3090 void MacroAssembler::restore_rax(Register tmp) {
3091 if (tmp == noreg) pop(rax);
3092 else if (tmp != rax) mov(rax, tmp);
3093 }
3094
3095 void MacroAssembler::round_to(Register reg, int modulus) {
3096 addptr(reg, modulus - 1);
3097 andptr(reg, -modulus);
3098 }
3099
3100 void MacroAssembler::save_rax(Register tmp) {
3101 if (tmp == noreg) push(rax);
3102 else if (tmp != rax) mov(tmp, rax);
3103 }
3104
3105 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
3106 if (at_return) {
3107 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
3108 // we may safely use rsp instead to perform the stack watermark check.
3109 cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
3110 jcc(Assembler::above, slow_path);
3111 return;
3112 }
3113 testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
3114 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3115 }
3116
3117 // Calls to C land
3118 //
3119 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3120 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3121 // has to be reset to 0. This is required to allow proper stack traversal.
3122 void MacroAssembler::set_last_Java_frame(Register java_thread,
3123 Register last_java_sp,
3124 Register last_java_fp,
3125 address last_java_pc,
3126 Register rscratch) {
3127 vzeroupper();
3128 // determine java_thread register
3129 if (!java_thread->is_valid()) {
3130 java_thread = rdi;
3131 get_thread(java_thread);
3132 }
3133 // determine last_java_sp register
3134 if (!last_java_sp->is_valid()) {
3135 last_java_sp = rsp;
3136 }
3137 // last_java_fp is optional
3138 if (last_java_fp->is_valid()) {
3139 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3140 }
3141 // last_java_pc is optional
3142 if (last_java_pc != nullptr) {
3143 Address java_pc(java_thread,
3144 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
3145 lea(java_pc, InternalAddress(last_java_pc), rscratch);
3146 }
3147 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3148 }
3149
3150 #ifdef _LP64
3151 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
3152 Register last_java_fp,
3153 Label &L,
3154 Register scratch) {
3155 lea(scratch, L);
3156 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
3157 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, nullptr, scratch);
3158 }
3159 #endif
3160
3161 void MacroAssembler::shlptr(Register dst, int imm8) {
3162 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3163 }
3164
3165 void MacroAssembler::shrptr(Register dst, int imm8) {
3166 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3167 }
3168
3169 void MacroAssembler::sign_extend_byte(Register reg) {
3170 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3171 movsbl(reg, reg); // movsxb
3172 } else {
3173 shll(reg, 24);
3174 sarl(reg, 24);
3175 }
3176 }
3177
3178 void MacroAssembler::sign_extend_short(Register reg) {
3179 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3180 movswl(reg, reg); // movsxw
3181 } else {
3182 shll(reg, 16);
3183 sarl(reg, 16);
3184 }
3185 }
3186
3187 void MacroAssembler::testl(Address dst, int32_t imm32) {
3188 if (imm32 >= 0 && is8bit(imm32)) {
3189 testb(dst, imm32);
3190 } else {
3191 Assembler::testl(dst, imm32);
3192 }
3193 }
3194
3195 void MacroAssembler::testl(Register dst, int32_t imm32) {
3196 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
3197 testb(dst, imm32);
3198 } else {
3199 Assembler::testl(dst, imm32);
3200 }
3201 }
3202
3203 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3204 assert(always_reachable(src), "Address should be reachable");
3205 testl(dst, as_Address(src));
3206 }
3207
3208 #ifdef _LP64
3209
3210 void MacroAssembler::testq(Address dst, int32_t imm32) {
3211 if (imm32 >= 0) {
3212 testl(dst, imm32);
3213 } else {
3214 Assembler::testq(dst, imm32);
3215 }
3216 }
3217
3218 void MacroAssembler::testq(Register dst, int32_t imm32) {
3219 if (imm32 >= 0) {
3220 testl(dst, imm32);
3221 } else {
3222 Assembler::testq(dst, imm32);
3223 }
3224 }
3225
3226 #endif
3227
3228 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3229 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3230 Assembler::pcmpeqb(dst, src);
3231 }
3232
3233 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3234 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3235 Assembler::pcmpeqw(dst, src);
3236 }
3237
3238 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3239 assert((dst->encoding() < 16),"XMM register should be 0-15");
3240 Assembler::pcmpestri(dst, src, imm8);
3241 }
3242
3243 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3244 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3245 Assembler::pcmpestri(dst, src, imm8);
3246 }
3247
3248 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3249 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3250 Assembler::pmovzxbw(dst, src);
3251 }
3252
3253 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3254 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3255 Assembler::pmovzxbw(dst, src);
3256 }
3257
3258 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3259 assert((src->encoding() < 16),"XMM register should be 0-15");
3260 Assembler::pmovmskb(dst, src);
3261 }
3262
3263 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3264 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3265 Assembler::ptest(dst, src);
3266 }
3267
3268 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3269 assert(rscratch != noreg || always_reachable(src), "missing");
3270
3271 if (reachable(src)) {
3272 Assembler::sqrtss(dst, as_Address(src));
3273 } else {
3274 lea(rscratch, src);
3275 Assembler::sqrtss(dst, Address(rscratch, 0));
3276 }
3277 }
3278
3279 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3280 assert(rscratch != noreg || always_reachable(src), "missing");
3281
3282 if (reachable(src)) {
3283 Assembler::subsd(dst, as_Address(src));
3284 } else {
3285 lea(rscratch, src);
3286 Assembler::subsd(dst, Address(rscratch, 0));
3287 }
3288 }
3289
3290 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
3291 assert(rscratch != noreg || always_reachable(src), "missing");
3292
3293 if (reachable(src)) {
3294 Assembler::roundsd(dst, as_Address(src), rmode);
3295 } else {
3296 lea(rscratch, src);
3297 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
3298 }
3299 }
3300
3301 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3302 assert(rscratch != noreg || always_reachable(src), "missing");
3303
3304 if (reachable(src)) {
3305 Assembler::subss(dst, as_Address(src));
3306 } else {
3307 lea(rscratch, src);
3308 Assembler::subss(dst, Address(rscratch, 0));
3309 }
3310 }
3311
3312 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3313 assert(rscratch != noreg || always_reachable(src), "missing");
3314
3315 if (reachable(src)) {
3316 Assembler::ucomisd(dst, as_Address(src));
3317 } else {
3318 lea(rscratch, src);
3319 Assembler::ucomisd(dst, Address(rscratch, 0));
3320 }
3321 }
3322
3323 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3324 assert(rscratch != noreg || always_reachable(src), "missing");
3325
3326 if (reachable(src)) {
3327 Assembler::ucomiss(dst, as_Address(src));
3328 } else {
3329 lea(rscratch, src);
3330 Assembler::ucomiss(dst, Address(rscratch, 0));
3331 }
3332 }
3333
3334 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3335 assert(rscratch != noreg || always_reachable(src), "missing");
3336
3337 // Used in sign-bit flipping with aligned address.
3338 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3339
3340 if (UseAVX > 2 &&
3341 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3342 (dst->encoding() >= 16)) {
3343 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
3344 } else if (reachable(src)) {
3345 Assembler::xorpd(dst, as_Address(src));
3346 } else {
3347 lea(rscratch, src);
3348 Assembler::xorpd(dst, Address(rscratch, 0));
3349 }
3350 }
3351
3352 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3353 if (UseAVX > 2 &&
3354 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3355 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
3356 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3357 } else {
3358 Assembler::xorpd(dst, src);
3359 }
3360 }
3361
3362 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3363 if (UseAVX > 2 &&
3364 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3365 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
3366 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3367 } else {
3368 Assembler::xorps(dst, src);
3369 }
3370 }
3371
3372 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
3373 assert(rscratch != noreg || always_reachable(src), "missing");
3374
3375 // Used in sign-bit flipping with aligned address.
3376 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3377
3378 if (UseAVX > 2 &&
3379 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3380 (dst->encoding() >= 16)) {
3381 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
3382 } else if (reachable(src)) {
3383 Assembler::xorps(dst, as_Address(src));
3384 } else {
3385 lea(rscratch, src);
3386 Assembler::xorps(dst, Address(rscratch, 0));
3387 }
3388 }
3389
3390 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
3391 assert(rscratch != noreg || always_reachable(src), "missing");
3392
3393 // Used in sign-bit flipping with aligned address.
3394 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3395 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3396 if (reachable(src)) {
3397 Assembler::pshufb(dst, as_Address(src));
3398 } else {
3399 lea(rscratch, src);
3400 Assembler::pshufb(dst, Address(rscratch, 0));
3401 }
3402 }
3403
3404 // AVX 3-operands instructions
3405
3406 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3407 assert(rscratch != noreg || always_reachable(src), "missing");
3408
3409 if (reachable(src)) {
3410 vaddsd(dst, nds, as_Address(src));
3411 } else {
3412 lea(rscratch, src);
3413 vaddsd(dst, nds, Address(rscratch, 0));
3414 }
3415 }
3416
3417 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3418 assert(rscratch != noreg || always_reachable(src), "missing");
3419
3420 if (reachable(src)) {
3421 vaddss(dst, nds, as_Address(src));
3422 } else {
3423 lea(rscratch, src);
3424 vaddss(dst, nds, Address(rscratch, 0));
3425 }
3426 }
3427
3428 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3429 assert(UseAVX > 0, "requires some form of AVX");
3430 assert(rscratch != noreg || always_reachable(src), "missing");
3431
3432 if (reachable(src)) {
3433 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3434 } else {
3435 lea(rscratch, src);
3436 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3437 }
3438 }
3439
3440 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3441 assert(UseAVX > 0, "requires some form of AVX");
3442 assert(rscratch != noreg || always_reachable(src), "missing");
3443
3444 if (reachable(src)) {
3445 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3446 } else {
3447 lea(rscratch, src);
3448 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3449 }
3450 }
3451
3452 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3453 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3454 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3455
3456 vandps(dst, nds, negate_field, vector_len, rscratch);
3457 }
3458
3459 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3460 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3461 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3462
3463 vandpd(dst, nds, negate_field, vector_len, rscratch);
3464 }
3465
3466 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3467 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3468 Assembler::vpaddb(dst, nds, src, vector_len);
3469 }
3470
3471 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3472 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3473 Assembler::vpaddb(dst, nds, src, vector_len);
3474 }
3475
3476 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3477 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3478 Assembler::vpaddw(dst, nds, src, vector_len);
3479 }
3480
3481 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3482 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3483 Assembler::vpaddw(dst, nds, src, vector_len);
3484 }
3485
3486 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3487 assert(rscratch != noreg || always_reachable(src), "missing");
3488
3489 if (reachable(src)) {
3490 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3491 } else {
3492 lea(rscratch, src);
3493 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
3494 }
3495 }
3496
3497 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3498 assert(rscratch != noreg || always_reachable(src), "missing");
3499
3500 if (reachable(src)) {
3501 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
3502 } else {
3503 lea(rscratch, src);
3504 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
3505 }
3506 }
3507
3508 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3509 assert(rscratch != noreg || always_reachable(src), "missing");
3510
3511 if (reachable(src)) {
3512 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
3513 } else {
3514 lea(rscratch, src);
3515 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
3516 }
3517 }
3518
3519 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3520 assert(rscratch != noreg || always_reachable(src), "missing");
3521
3522 if (reachable(src)) {
3523 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3524 } else {
3525 lea(rscratch, src);
3526 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3527 }
3528 }
3529
3530 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3531 assert(rscratch != noreg || always_reachable(src), "missing");
3532
3533 if (reachable(src)) {
3534 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3535 } else {
3536 lea(rscratch, src);
3537 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3538 }
3539 }
3540
3541 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3542 assert(rscratch != noreg || always_reachable(src), "missing");
3543
3544 if (reachable(src)) {
3545 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3546 } else {
3547 lea(rscratch, src);
3548 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3549 }
3550 }
3551
3552 // Vector float blend
3553 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3554 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3555 // WARN: Allow dst == (src1|src2), mask == scratch
3556 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3557 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3558 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3559 if (blend_emulation && scratch_available && dst_available) {
3560 if (compute_mask) {
3561 vpsrad(scratch, mask, 32, vector_len);
3562 mask = scratch;
3563 }
3564 if (dst == src1) {
3565 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3566 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3567 } else {
3568 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3569 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3570 }
3571 vpor(dst, dst, scratch, vector_len);
3572 } else {
3573 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3574 }
3575 }
3576
3577 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3578 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3579 // WARN: Allow dst == (src1|src2), mask == scratch
3580 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3581 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3582 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3583 if (blend_emulation && scratch_available && dst_available) {
3584 if (compute_mask) {
3585 vpxor(scratch, scratch, scratch, vector_len);
3586 vpcmpgtq(scratch, scratch, mask, vector_len);
3587 mask = scratch;
3588 }
3589 if (dst == src1) {
3590 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3591 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3592 } else {
3593 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3594 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3595 }
3596 vpor(dst, dst, scratch, vector_len);
3597 } else {
3598 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3599 }
3600 }
3601
3602 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3603 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3604 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3605 }
3606
3607 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3608 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3609 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3610 }
3611
3612 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3613 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3614 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3615 }
3616
3617 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3618 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3619 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3620 }
3621
3622 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3623 assert(rscratch != noreg || always_reachable(src), "missing");
3624
3625 if (reachable(src)) {
3626 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3627 } else {
3628 lea(rscratch, src);
3629 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3630 }
3631 }
3632
3633 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3634 int comparison, bool is_signed, int vector_len, Register rscratch) {
3635 assert(rscratch != noreg || always_reachable(src), "missing");
3636
3637 if (reachable(src)) {
3638 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3639 } else {
3640 lea(rscratch, src);
3641 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3642 }
3643 }
3644
3645 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3646 int comparison, bool is_signed, int vector_len, Register rscratch) {
3647 assert(rscratch != noreg || always_reachable(src), "missing");
3648
3649 if (reachable(src)) {
3650 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3651 } else {
3652 lea(rscratch, src);
3653 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3654 }
3655 }
3656
3657 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3658 int comparison, bool is_signed, int vector_len, Register rscratch) {
3659 assert(rscratch != noreg || always_reachable(src), "missing");
3660
3661 if (reachable(src)) {
3662 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3663 } else {
3664 lea(rscratch, src);
3665 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3666 }
3667 }
3668
3669 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3670 int comparison, bool is_signed, int vector_len, Register rscratch) {
3671 assert(rscratch != noreg || always_reachable(src), "missing");
3672
3673 if (reachable(src)) {
3674 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3675 } else {
3676 lea(rscratch, src);
3677 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3678 }
3679 }
3680
3681 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3682 if (width == Assembler::Q) {
3683 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3684 } else {
3685 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3686 }
3687 }
3688
3689 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3690 int eq_cond_enc = 0x29;
3691 int gt_cond_enc = 0x37;
3692 if (width != Assembler::Q) {
3693 eq_cond_enc = 0x74 + width;
3694 gt_cond_enc = 0x64 + width;
3695 }
3696 switch (cond) {
3697 case eq:
3698 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3699 break;
3700 case neq:
3701 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3702 vallones(xtmp, vector_len);
3703 vpxor(dst, xtmp, dst, vector_len);
3704 break;
3705 case le:
3706 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3707 vallones(xtmp, vector_len);
3708 vpxor(dst, xtmp, dst, vector_len);
3709 break;
3710 case nlt:
3711 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3712 vallones(xtmp, vector_len);
3713 vpxor(dst, xtmp, dst, vector_len);
3714 break;
3715 case lt:
3716 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3717 break;
3718 case nle:
3719 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3720 break;
3721 default:
3722 assert(false, "Should not reach here");
3723 }
3724 }
3725
3726 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3727 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3728 Assembler::vpmovzxbw(dst, src, vector_len);
3729 }
3730
3731 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3732 assert((src->encoding() < 16),"XMM register should be 0-15");
3733 Assembler::vpmovmskb(dst, src, vector_len);
3734 }
3735
3736 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3737 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3738 Assembler::vpmullw(dst, nds, src, vector_len);
3739 }
3740
3741 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3742 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3743 Assembler::vpmullw(dst, nds, src, vector_len);
3744 }
3745
3746 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3747 assert((UseAVX > 0), "AVX support is needed");
3748 assert(rscratch != noreg || always_reachable(src), "missing");
3749
3750 if (reachable(src)) {
3751 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3752 } else {
3753 lea(rscratch, src);
3754 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3755 }
3756 }
3757
3758 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3759 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3760 Assembler::vpsubb(dst, nds, src, vector_len);
3761 }
3762
3763 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3764 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3765 Assembler::vpsubb(dst, nds, src, vector_len);
3766 }
3767
3768 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3769 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3770 Assembler::vpsubw(dst, nds, src, vector_len);
3771 }
3772
3773 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3774 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3775 Assembler::vpsubw(dst, nds, src, vector_len);
3776 }
3777
3778 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3779 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3780 Assembler::vpsraw(dst, nds, shift, vector_len);
3781 }
3782
3783 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3784 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3785 Assembler::vpsraw(dst, nds, shift, vector_len);
3786 }
3787
3788 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3789 assert(UseAVX > 2,"");
3790 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3791 vector_len = 2;
3792 }
3793 Assembler::evpsraq(dst, nds, shift, vector_len);
3794 }
3795
3796 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3797 assert(UseAVX > 2,"");
3798 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3799 vector_len = 2;
3800 }
3801 Assembler::evpsraq(dst, nds, shift, vector_len);
3802 }
3803
3804 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3805 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3806 Assembler::vpsrlw(dst, nds, shift, vector_len);
3807 }
3808
3809 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3810 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3811 Assembler::vpsrlw(dst, nds, shift, vector_len);
3812 }
3813
3814 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3815 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3816 Assembler::vpsllw(dst, nds, shift, vector_len);
3817 }
3818
3819 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3820 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3821 Assembler::vpsllw(dst, nds, shift, vector_len);
3822 }
3823
3824 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3825 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3826 Assembler::vptest(dst, src);
3827 }
3828
3829 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3830 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3831 Assembler::punpcklbw(dst, src);
3832 }
3833
3834 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3835 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3836 Assembler::pshufd(dst, src, mode);
3837 }
3838
3839 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3840 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3841 Assembler::pshuflw(dst, src, mode);
3842 }
3843
3844 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3845 assert(rscratch != noreg || always_reachable(src), "missing");
3846
3847 if (reachable(src)) {
3848 vandpd(dst, nds, as_Address(src), vector_len);
3849 } else {
3850 lea(rscratch, src);
3851 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3852 }
3853 }
3854
3855 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3856 assert(rscratch != noreg || always_reachable(src), "missing");
3857
3858 if (reachable(src)) {
3859 vandps(dst, nds, as_Address(src), vector_len);
3860 } else {
3861 lea(rscratch, src);
3862 vandps(dst, nds, Address(rscratch, 0), vector_len);
3863 }
3864 }
3865
3866 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3867 bool merge, int vector_len, Register rscratch) {
3868 assert(rscratch != noreg || always_reachable(src), "missing");
3869
3870 if (reachable(src)) {
3871 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3872 } else {
3873 lea(rscratch, src);
3874 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3875 }
3876 }
3877
3878 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3879 assert(rscratch != noreg || always_reachable(src), "missing");
3880
3881 if (reachable(src)) {
3882 vdivsd(dst, nds, as_Address(src));
3883 } else {
3884 lea(rscratch, src);
3885 vdivsd(dst, nds, Address(rscratch, 0));
3886 }
3887 }
3888
3889 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3890 assert(rscratch != noreg || always_reachable(src), "missing");
3891
3892 if (reachable(src)) {
3893 vdivss(dst, nds, as_Address(src));
3894 } else {
3895 lea(rscratch, src);
3896 vdivss(dst, nds, Address(rscratch, 0));
3897 }
3898 }
3899
3900 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3901 assert(rscratch != noreg || always_reachable(src), "missing");
3902
3903 if (reachable(src)) {
3904 vmulsd(dst, nds, as_Address(src));
3905 } else {
3906 lea(rscratch, src);
3907 vmulsd(dst, nds, Address(rscratch, 0));
3908 }
3909 }
3910
3911 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3912 assert(rscratch != noreg || always_reachable(src), "missing");
3913
3914 if (reachable(src)) {
3915 vmulss(dst, nds, as_Address(src));
3916 } else {
3917 lea(rscratch, src);
3918 vmulss(dst, nds, Address(rscratch, 0));
3919 }
3920 }
3921
3922 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3923 assert(rscratch != noreg || always_reachable(src), "missing");
3924
3925 if (reachable(src)) {
3926 vsubsd(dst, nds, as_Address(src));
3927 } else {
3928 lea(rscratch, src);
3929 vsubsd(dst, nds, Address(rscratch, 0));
3930 }
3931 }
3932
3933 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3934 assert(rscratch != noreg || always_reachable(src), "missing");
3935
3936 if (reachable(src)) {
3937 vsubss(dst, nds, as_Address(src));
3938 } else {
3939 lea(rscratch, src);
3940 vsubss(dst, nds, Address(rscratch, 0));
3941 }
3942 }
3943
3944 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3945 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3946 assert(rscratch != noreg || always_reachable(src), "missing");
3947
3948 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3949 }
3950
3951 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3952 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3953 assert(rscratch != noreg || always_reachable(src), "missing");
3954
3955 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3956 }
3957
3958 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3959 assert(rscratch != noreg || always_reachable(src), "missing");
3960
3961 if (reachable(src)) {
3962 vxorpd(dst, nds, as_Address(src), vector_len);
3963 } else {
3964 lea(rscratch, src);
3965 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3966 }
3967 }
3968
3969 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3970 assert(rscratch != noreg || always_reachable(src), "missing");
3971
3972 if (reachable(src)) {
3973 vxorps(dst, nds, as_Address(src), vector_len);
3974 } else {
3975 lea(rscratch, src);
3976 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3977 }
3978 }
3979
3980 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3981 assert(rscratch != noreg || always_reachable(src), "missing");
3982
3983 if (UseAVX > 1 || (vector_len < 1)) {
3984 if (reachable(src)) {
3985 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3986 } else {
3987 lea(rscratch, src);
3988 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3989 }
3990 } else {
3991 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3992 }
3993 }
3994
3995 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3996 assert(rscratch != noreg || always_reachable(src), "missing");
3997
3998 if (reachable(src)) {
3999 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
4000 } else {
4001 lea(rscratch, src);
4002 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
4003 }
4004 }
4005
4006 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
4007 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
4008 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
4009 // The inverted mask is sign-extended
4010 andptr(possibly_non_local, inverted_mask);
4011 }
4012
4013 void MacroAssembler::resolve_jobject(Register value,
4014 Register thread,
4015 Register tmp) {
4016 assert_different_registers(value, thread, tmp);
4017 Label done, tagged, weak_tagged;
4018 testptr(value, value);
4019 jcc(Assembler::zero, done); // Use null as-is.
4020 testptr(value, JNIHandles::tag_mask); // Test for tag.
4021 jcc(Assembler::notZero, tagged);
4022
4023 // Resolve local handle
4024 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp, thread);
4025 verify_oop(value);
4026 jmp(done);
4027
4028 bind(tagged);
4029 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
4030 jcc(Assembler::notZero, weak_tagged);
4031
4032 // Resolve global handle
4033 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4034 verify_oop(value);
4035 jmp(done);
4036
4037 bind(weak_tagged);
4038 // Resolve jweak.
4039 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4040 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp, thread);
4041 verify_oop(value);
4042
4043 bind(done);
4044 }
4045
4046 void MacroAssembler::resolve_global_jobject(Register value,
4047 Register thread,
4048 Register tmp) {
4049 assert_different_registers(value, thread, tmp);
4050 Label done;
4051
4052 testptr(value, value);
4053 jcc(Assembler::zero, done); // Use null as-is.
4054
4055 #ifdef ASSERT
4056 {
4057 Label valid_global_tag;
4058 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
4059 jcc(Assembler::notZero, valid_global_tag);
4060 stop("non global jobject using resolve_global_jobject");
4061 bind(valid_global_tag);
4062 }
4063 #endif
4064
4065 // Resolve global handle
4066 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4067 verify_oop(value);
4068
4069 bind(done);
4070 }
4071
4072 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4073 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4074 }
4075
4076 // Force generation of a 4 byte immediate value even if it fits into 8bit
4077 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4078 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4079 }
4080
4081 void MacroAssembler::subptr(Register dst, Register src) {
4082 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4083 }
4084
4085 // C++ bool manipulation
4086 void MacroAssembler::testbool(Register dst) {
4087 if(sizeof(bool) == 1)
4088 testb(dst, 0xff);
4089 else if(sizeof(bool) == 2) {
4090 // testw implementation needed for two byte bools
4091 ShouldNotReachHere();
4092 } else if(sizeof(bool) == 4)
4093 testl(dst, dst);
4094 else
4095 // unsupported
4096 ShouldNotReachHere();
4097 }
4098
4099 void MacroAssembler::testptr(Register dst, Register src) {
4100 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4101 }
4102
4103 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4104 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4105 Register var_size_in_bytes,
4106 int con_size_in_bytes,
4107 Register t1,
4108 Register t2,
4109 Label& slow_case) {
4110 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4111 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4112 }
4113
4114 RegSet MacroAssembler::call_clobbered_gp_registers() {
4115 RegSet regs;
4116 #ifdef _LP64
4117 regs += RegSet::of(rax, rcx, rdx);
4118 #ifndef _WINDOWS
4119 regs += RegSet::of(rsi, rdi);
4120 #endif
4121 regs += RegSet::range(r8, r11);
4122 #else
4123 regs += RegSet::of(rax, rcx, rdx);
4124 #endif
4125 #ifdef _LP64
4126 if (UseAPX) {
4127 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
4128 }
4129 #endif
4130 return regs;
4131 }
4132
4133 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
4134 int num_xmm_registers = XMMRegister::available_xmm_registers();
4135 #if defined(_WINDOWS)
4136 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
4137 if (num_xmm_registers > 16) {
4138 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
4139 }
4140 return result;
4141 #else
4142 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
4143 #endif
4144 }
4145
4146 static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor
4147
4148 #ifndef _LP64
4149 static bool use_x87_registers() { return UseSSE < 2; }
4150 #endif
4151 static bool use_xmm_registers() { return UseSSE >= 1; }
4152
4153 // C1 only ever uses the first double/float of the XMM register.
4154 static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); }
4155
4156 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4157 if (UseSSE == 1) {
4158 masm->movflt(Address(rsp, offset), reg);
4159 } else {
4160 masm->movdbl(Address(rsp, offset), reg);
4161 }
4162 }
4163
4164 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4165 if (UseSSE == 1) {
4166 masm->movflt(reg, Address(rsp, offset));
4167 } else {
4168 masm->movdbl(reg, Address(rsp, offset));
4169 }
4170 }
4171
4172 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
4173 bool save_fpu, int& gp_area_size,
4174 int& fp_area_size, int& xmm_area_size) {
4175
4176 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
4177 StackAlignmentInBytes);
4178 #ifdef _LP64
4179 fp_area_size = 0;
4180 #else
4181 fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0;
4182 #endif
4183 xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0;
4184
4185 return gp_area_size + fp_area_size + xmm_area_size;
4186 }
4187
4188 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
4189 block_comment("push_call_clobbered_registers start");
4190 // Regular registers
4191 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
4192
4193 int gp_area_size;
4194 int fp_area_size;
4195 int xmm_area_size;
4196 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
4197 gp_area_size, fp_area_size, xmm_area_size);
4198 subptr(rsp, total_save_size);
4199
4200 push_set(gp_registers_to_push, 0);
4201
4202 #ifndef _LP64
4203 if (save_fpu && use_x87_registers()) {
4204 fnsave(Address(rsp, gp_area_size));
4205 fwait();
4206 }
4207 #endif
4208 if (save_fpu && use_xmm_registers()) {
4209 push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4210 }
4211
4212 block_comment("push_call_clobbered_registers end");
4213 }
4214
4215 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
4216 block_comment("pop_call_clobbered_registers start");
4217
4218 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
4219
4220 int gp_area_size;
4221 int fp_area_size;
4222 int xmm_area_size;
4223 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
4224 gp_area_size, fp_area_size, xmm_area_size);
4225
4226 if (restore_fpu && use_xmm_registers()) {
4227 pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4228 }
4229 #ifndef _LP64
4230 if (restore_fpu && use_x87_registers()) {
4231 frstor(Address(rsp, gp_area_size));
4232 }
4233 #endif
4234
4235 pop_set(gp_registers_to_pop, 0);
4236
4237 addptr(rsp, total_save_size);
4238
4239 vzeroupper();
4240
4241 block_comment("pop_call_clobbered_registers end");
4242 }
4243
4244 void MacroAssembler::push_set(XMMRegSet set, int offset) {
4245 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
4246 int spill_offset = offset;
4247
4248 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
4249 save_xmm_register(this, spill_offset, *it);
4250 spill_offset += xmm_save_size();
4251 }
4252 }
4253
4254 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
4255 int restore_size = set.size() * xmm_save_size();
4256 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
4257
4258 int restore_offset = offset + restore_size - xmm_save_size();
4259
4260 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
4261 restore_xmm_register(this, restore_offset, *it);
4262 restore_offset -= xmm_save_size();
4263 }
4264 }
4265
4266 void MacroAssembler::push_set(RegSet set, int offset) {
4267 int spill_offset;
4268 if (offset == -1) {
4269 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4270 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4271 subptr(rsp, aligned_size);
4272 spill_offset = 0;
4273 } else {
4274 spill_offset = offset;
4275 }
4276
4277 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
4278 movptr(Address(rsp, spill_offset), *it);
4279 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4280 }
4281 }
4282
4283 void MacroAssembler::pop_set(RegSet set, int offset) {
4284
4285 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4286 int restore_size = set.size() * gp_reg_size;
4287 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
4288
4289 int restore_offset;
4290 if (offset == -1) {
4291 restore_offset = restore_size - gp_reg_size;
4292 } else {
4293 restore_offset = offset + restore_size - gp_reg_size;
4294 }
4295 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
4296 movptr(*it, Address(rsp, restore_offset));
4297 restore_offset -= gp_reg_size;
4298 }
4299
4300 if (offset == -1) {
4301 addptr(rsp, aligned_size);
4302 }
4303 }
4304
4305 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4306 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4307 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4308 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4309 Label done;
4310
4311 testptr(length_in_bytes, length_in_bytes);
4312 jcc(Assembler::zero, done);
4313
4314 // initialize topmost word, divide index by 2, check if odd and test if zero
4315 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4316 #ifdef ASSERT
4317 {
4318 Label L;
4319 testptr(length_in_bytes, BytesPerWord - 1);
4320 jcc(Assembler::zero, L);
4321 stop("length must be a multiple of BytesPerWord");
4322 bind(L);
4323 }
4324 #endif
4325 Register index = length_in_bytes;
4326 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4327 if (UseIncDec) {
4328 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4329 } else {
4330 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4331 shrptr(index, 1);
4332 }
4333 #ifndef _LP64
4334 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4335 {
4336 Label even;
4337 // note: if index was a multiple of 8, then it cannot
4338 // be 0 now otherwise it must have been 0 before
4339 // => if it is even, we don't need to check for 0 again
4340 jcc(Assembler::carryClear, even);
4341 // clear topmost word (no jump would be needed if conditional assignment worked here)
4342 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4343 // index could be 0 now, must check again
4344 jcc(Assembler::zero, done);
4345 bind(even);
4346 }
4347 #endif // !_LP64
4348 // initialize remaining object fields: index is a multiple of 2 now
4349 {
4350 Label loop;
4351 bind(loop);
4352 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4353 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4354 decrement(index);
4355 jcc(Assembler::notZero, loop);
4356 }
4357
4358 bind(done);
4359 }
4360
4361 // Look up the method for a megamorphic invokeinterface call.
4362 // The target method is determined by <intf_klass, itable_index>.
4363 // The receiver klass is in recv_klass.
4364 // On success, the result will be in method_result, and execution falls through.
4365 // On failure, execution transfers to the given label.
4366 void MacroAssembler::lookup_interface_method(Register recv_klass,
4367 Register intf_klass,
4368 RegisterOrConstant itable_index,
4369 Register method_result,
4370 Register scan_temp,
4371 Label& L_no_such_interface,
4372 bool return_method) {
4373 assert_different_registers(recv_klass, intf_klass, scan_temp);
4374 assert_different_registers(method_result, intf_klass, scan_temp);
4375 assert(recv_klass != method_result || !return_method,
4376 "recv_klass can be destroyed when method isn't needed");
4377
4378 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4379 "caller must use same register for non-constant itable index as for method");
4380
4381 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4382 int vtable_base = in_bytes(Klass::vtable_start_offset());
4383 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4384 int scan_step = itableOffsetEntry::size() * wordSize;
4385 int vte_size = vtableEntry::size_in_bytes();
4386 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4387 assert(vte_size == wordSize, "else adjust times_vte_scale");
4388
4389 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4390
4391 // Could store the aligned, prescaled offset in the klass.
4392 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4393
4394 if (return_method) {
4395 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4396 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4397 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4398 }
4399
4400 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
4401 // if (scan->interface() == intf) {
4402 // result = (klass + scan->offset() + itable_index);
4403 // }
4404 // }
4405 Label search, found_method;
4406
4407 for (int peel = 1; peel >= 0; peel--) {
4408 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
4409 cmpptr(intf_klass, method_result);
4410
4411 if (peel) {
4412 jccb(Assembler::equal, found_method);
4413 } else {
4414 jccb(Assembler::notEqual, search);
4415 // (invert the test to fall through to found_method...)
4416 }
4417
4418 if (!peel) break;
4419
4420 bind(search);
4421
4422 // Check that the previous entry is non-null. A null entry means that
4423 // the receiver class doesn't implement the interface, and wasn't the
4424 // same as when the caller was compiled.
4425 testptr(method_result, method_result);
4426 jcc(Assembler::zero, L_no_such_interface);
4427 addptr(scan_temp, scan_step);
4428 }
4429
4430 bind(found_method);
4431
4432 if (return_method) {
4433 // Got a hit.
4434 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
4435 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4436 }
4437 }
4438
4439 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
4440 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
4441 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
4442 // The target method is determined by <holder_klass, itable_index>.
4443 // The receiver klass is in recv_klass.
4444 // On success, the result will be in method_result, and execution falls through.
4445 // On failure, execution transfers to the given label.
4446 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
4447 Register holder_klass,
4448 Register resolved_klass,
4449 Register method_result,
4450 Register scan_temp,
4451 Register temp_reg2,
4452 Register receiver,
4453 int itable_index,
4454 Label& L_no_such_interface) {
4455 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
4456 Register temp_itbl_klass = method_result;
4457 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
4458
4459 int vtable_base = in_bytes(Klass::vtable_start_offset());
4460 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4461 int scan_step = itableOffsetEntry::size() * wordSize;
4462 int vte_size = vtableEntry::size_in_bytes();
4463 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
4464 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
4465 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4466 assert(vte_size == wordSize, "adjust times_vte_scale");
4467
4468 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
4469
4470 // temp_itbl_klass = recv_klass.itable[0]
4471 // scan_temp = &recv_klass.itable[0] + step
4472 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4473 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
4474 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
4475 xorptr(temp_reg, temp_reg);
4476
4477 // Initial checks:
4478 // - if (holder_klass != resolved_klass), go to "scan for resolved"
4479 // - if (itable[0] == 0), no such interface
4480 // - if (itable[0] == holder_klass), shortcut to "holder found"
4481 cmpptr(holder_klass, resolved_klass);
4482 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
4483 testptr(temp_itbl_klass, temp_itbl_klass);
4484 jccb(Assembler::zero, L_no_such_interface);
4485 cmpptr(holder_klass, temp_itbl_klass);
4486 jccb(Assembler::equal, L_holder_found);
4487
4488 // Loop: Look for holder_klass record in itable
4489 // do {
4490 // tmp = itable[index];
4491 // index += step;
4492 // if (tmp == holder_klass) {
4493 // goto L_holder_found; // Found!
4494 // }
4495 // } while (tmp != 0);
4496 // goto L_no_such_interface // Not found.
4497 Label L_scan_holder;
4498 bind(L_scan_holder);
4499 movptr(temp_itbl_klass, Address(scan_temp, 0));
4500 addptr(scan_temp, scan_step);
4501 cmpptr(holder_klass, temp_itbl_klass);
4502 jccb(Assembler::equal, L_holder_found);
4503 testptr(temp_itbl_klass, temp_itbl_klass);
4504 jccb(Assembler::notZero, L_scan_holder);
4505
4506 jmpb(L_no_such_interface);
4507
4508 // Loop: Look for resolved_class record in itable
4509 // do {
4510 // tmp = itable[index];
4511 // index += step;
4512 // if (tmp == holder_klass) {
4513 // // Also check if we have met a holder klass
4514 // holder_tmp = itable[index-step-ioffset];
4515 // }
4516 // if (tmp == resolved_klass) {
4517 // goto L_resolved_found; // Found!
4518 // }
4519 // } while (tmp != 0);
4520 // goto L_no_such_interface // Not found.
4521 //
4522 Label L_loop_scan_resolved;
4523 bind(L_loop_scan_resolved);
4524 movptr(temp_itbl_klass, Address(scan_temp, 0));
4525 addptr(scan_temp, scan_step);
4526 bind(L_loop_scan_resolved_entry);
4527 cmpptr(holder_klass, temp_itbl_klass);
4528 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4529 cmpptr(resolved_klass, temp_itbl_klass);
4530 jccb(Assembler::equal, L_resolved_found);
4531 testptr(temp_itbl_klass, temp_itbl_klass);
4532 jccb(Assembler::notZero, L_loop_scan_resolved);
4533
4534 jmpb(L_no_such_interface);
4535
4536 Label L_ready;
4537
4538 // See if we already have a holder klass. If not, go and scan for it.
4539 bind(L_resolved_found);
4540 testptr(temp_reg, temp_reg);
4541 jccb(Assembler::zero, L_scan_holder);
4542 jmpb(L_ready);
4543
4544 bind(L_holder_found);
4545 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4546
4547 // Finally, temp_reg contains holder_klass vtable offset
4548 bind(L_ready);
4549 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4550 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4551 load_klass(scan_temp, receiver, noreg);
4552 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4553 } else {
4554 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4555 }
4556 }
4557
4558
4559 // virtual method calling
4560 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4561 RegisterOrConstant vtable_index,
4562 Register method_result) {
4563 const ByteSize base = Klass::vtable_start_offset();
4564 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4565 Address vtable_entry_addr(recv_klass,
4566 vtable_index, Address::times_ptr,
4567 base + vtableEntry::method_offset());
4568 movptr(method_result, vtable_entry_addr);
4569 }
4570
4571
4572 void MacroAssembler::check_klass_subtype(Register sub_klass,
4573 Register super_klass,
4574 Register temp_reg,
4575 Label& L_success) {
4576 Label L_failure;
4577 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4578 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4579 bind(L_failure);
4580 }
4581
4582
4583 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4584 Register super_klass,
4585 Register temp_reg,
4586 Label* L_success,
4587 Label* L_failure,
4588 Label* L_slow_path,
4589 RegisterOrConstant super_check_offset) {
4590 assert_different_registers(sub_klass, super_klass, temp_reg);
4591 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4592 if (super_check_offset.is_register()) {
4593 assert_different_registers(sub_klass, super_klass,
4594 super_check_offset.as_register());
4595 } else if (must_load_sco) {
4596 assert(temp_reg != noreg, "supply either a temp or a register offset");
4597 }
4598
4599 Label L_fallthrough;
4600 int label_nulls = 0;
4601 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4602 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4603 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4604 assert(label_nulls <= 1, "at most one null in the batch");
4605
4606 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4607 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4608 Address super_check_offset_addr(super_klass, sco_offset);
4609
4610 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4611 // range of a jccb. If this routine grows larger, reconsider at
4612 // least some of these.
4613 #define local_jcc(assembler_cond, label) \
4614 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4615 else jcc( assembler_cond, label) /*omit semi*/
4616
4617 // Hacked jmp, which may only be used just before L_fallthrough.
4618 #define final_jmp(label) \
4619 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4620 else jmp(label) /*omit semi*/
4621
4622 // If the pointers are equal, we are done (e.g., String[] elements).
4623 // This self-check enables sharing of secondary supertype arrays among
4624 // non-primary types such as array-of-interface. Otherwise, each such
4625 // type would need its own customized SSA.
4626 // We move this check to the front of the fast path because many
4627 // type checks are in fact trivially successful in this manner,
4628 // so we get a nicely predicted branch right at the start of the check.
4629 cmpptr(sub_klass, super_klass);
4630 local_jcc(Assembler::equal, *L_success);
4631
4632 // Check the supertype display:
4633 if (must_load_sco) {
4634 // Positive movl does right thing on LP64.
4635 movl(temp_reg, super_check_offset_addr);
4636 super_check_offset = RegisterOrConstant(temp_reg);
4637 }
4638 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4639 cmpptr(super_klass, super_check_addr); // load displayed supertype
4640
4641 // This check has worked decisively for primary supers.
4642 // Secondary supers are sought in the super_cache ('super_cache_addr').
4643 // (Secondary supers are interfaces and very deeply nested subtypes.)
4644 // This works in the same check above because of a tricky aliasing
4645 // between the super_cache and the primary super display elements.
4646 // (The 'super_check_addr' can address either, as the case requires.)
4647 // Note that the cache is updated below if it does not help us find
4648 // what we need immediately.
4649 // So if it was a primary super, we can just fail immediately.
4650 // Otherwise, it's the slow path for us (no success at this point).
4651
4652 if (super_check_offset.is_register()) {
4653 local_jcc(Assembler::equal, *L_success);
4654 cmpl(super_check_offset.as_register(), sc_offset);
4655 if (L_failure == &L_fallthrough) {
4656 local_jcc(Assembler::equal, *L_slow_path);
4657 } else {
4658 local_jcc(Assembler::notEqual, *L_failure);
4659 final_jmp(*L_slow_path);
4660 }
4661 } else if (super_check_offset.as_constant() == sc_offset) {
4662 // Need a slow path; fast failure is impossible.
4663 if (L_slow_path == &L_fallthrough) {
4664 local_jcc(Assembler::equal, *L_success);
4665 } else {
4666 local_jcc(Assembler::notEqual, *L_slow_path);
4667 final_jmp(*L_success);
4668 }
4669 } else {
4670 // No slow path; it's a fast decision.
4671 if (L_failure == &L_fallthrough) {
4672 local_jcc(Assembler::equal, *L_success);
4673 } else {
4674 local_jcc(Assembler::notEqual, *L_failure);
4675 final_jmp(*L_success);
4676 }
4677 }
4678
4679 bind(L_fallthrough);
4680
4681 #undef local_jcc
4682 #undef final_jmp
4683 }
4684
4685
4686 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4687 Register super_klass,
4688 Register temp_reg,
4689 Register temp2_reg,
4690 Label* L_success,
4691 Label* L_failure,
4692 bool set_cond_codes) {
4693 assert_different_registers(sub_klass, super_klass, temp_reg);
4694 if (temp2_reg != noreg)
4695 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4696 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4697
4698 Label L_fallthrough;
4699 int label_nulls = 0;
4700 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4701 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4702 assert(label_nulls <= 1, "at most one null in the batch");
4703
4704 // a couple of useful fields in sub_klass:
4705 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4706 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4707 Address secondary_supers_addr(sub_klass, ss_offset);
4708 Address super_cache_addr( sub_klass, sc_offset);
4709
4710 // Do a linear scan of the secondary super-klass chain.
4711 // This code is rarely used, so simplicity is a virtue here.
4712 // The repne_scan instruction uses fixed registers, which we must spill.
4713 // Don't worry too much about pre-existing connections with the input regs.
4714
4715 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4716 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4717
4718 // Get super_klass value into rax (even if it was in rdi or rcx).
4719 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4720 if (super_klass != rax) {
4721 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4722 mov(rax, super_klass);
4723 }
4724 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4725 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4726
4727 #ifndef PRODUCT
4728 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4729 ExternalAddress pst_counter_addr((address) pst_counter);
4730 NOT_LP64( incrementl(pst_counter_addr) );
4731 LP64_ONLY( lea(rcx, pst_counter_addr) );
4732 LP64_ONLY( incrementl(Address(rcx, 0)) );
4733 #endif //PRODUCT
4734
4735 // We will consult the secondary-super array.
4736 movptr(rdi, secondary_supers_addr);
4737 // Load the array length. (Positive movl does right thing on LP64.)
4738 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4739 // Skip to start of data.
4740 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4741
4742 // Scan RCX words at [RDI] for an occurrence of RAX.
4743 // Set NZ/Z based on last compare.
4744 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4745 // not change flags (only scas instruction which is repeated sets flags).
4746 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4747
4748 testptr(rax,rax); // Set Z = 0
4749 repne_scan();
4750
4751 // Unspill the temp. registers:
4752 if (pushed_rdi) pop(rdi);
4753 if (pushed_rcx) pop(rcx);
4754 if (pushed_rax) pop(rax);
4755
4756 if (set_cond_codes) {
4757 // Special hack for the AD files: rdi is guaranteed non-zero.
4758 assert(!pushed_rdi, "rdi must be left non-null");
4759 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4760 }
4761
4762 if (L_failure == &L_fallthrough)
4763 jccb(Assembler::notEqual, *L_failure);
4764 else jcc(Assembler::notEqual, *L_failure);
4765
4766 // Success. Cache the super we found and proceed in triumph.
4767 movptr(super_cache_addr, super_klass);
4768
4769 if (L_success != &L_fallthrough) {
4770 jmp(*L_success);
4771 }
4772
4773 #undef IS_A_TEMP
4774
4775 bind(L_fallthrough);
4776 }
4777
4778 #ifndef _LP64
4779
4780 // 32-bit x86 only: always use the linear search.
4781 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4782 Register super_klass,
4783 Register temp_reg,
4784 Register temp2_reg,
4785 Label* L_success,
4786 Label* L_failure,
4787 bool set_cond_codes) {
4788 check_klass_subtype_slow_path_linear
4789 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
4790 }
4791
4792 #else // _LP64
4793
4794 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4795 Register super_klass,
4796 Register temp_reg,
4797 Register temp2_reg,
4798 Label* L_success,
4799 Label* L_failure,
4800 bool set_cond_codes) {
4801 assert(set_cond_codes == false, "must be false on 64-bit x86");
4802 check_klass_subtype_slow_path
4803 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4804 L_success, L_failure);
4805 }
4806
4807 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4808 Register super_klass,
4809 Register temp_reg,
4810 Register temp2_reg,
4811 Register temp3_reg,
4812 Register temp4_reg,
4813 Label* L_success,
4814 Label* L_failure) {
4815 if (UseSecondarySupersTable) {
4816 check_klass_subtype_slow_path_table
4817 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4818 L_success, L_failure);
4819 } else {
4820 check_klass_subtype_slow_path_linear
4821 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4822 }
4823 }
4824
4825 Register MacroAssembler::allocate_if_noreg(Register r,
4826 RegSetIterator<Register> &available_regs,
4827 RegSet ®s_to_push) {
4828 if (!r->is_valid()) {
4829 r = *available_regs++;
4830 regs_to_push += r;
4831 }
4832 return r;
4833 }
4834
4835 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4836 Register super_klass,
4837 Register temp_reg,
4838 Register temp2_reg,
4839 Register temp3_reg,
4840 Register result_reg,
4841 Label* L_success,
4842 Label* L_failure) {
4843 // NB! Callers may assume that, when temp2_reg is a valid register,
4844 // this code sets it to a nonzero value.
4845 bool temp2_reg_was_valid = temp2_reg->is_valid();
4846
4847 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4848
4849 Label L_fallthrough;
4850 int label_nulls = 0;
4851 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4852 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4853 assert(label_nulls <= 1, "at most one null in the batch");
4854
4855 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4856
4857 RegSetIterator<Register> available_regs
4858 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4859
4860 RegSet pushed_regs;
4861
4862 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4863 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4864 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4865 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4866 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4867
4868 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4869
4870 {
4871
4872 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4873 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4874 subptr(rsp, aligned_size);
4875 push_set(pushed_regs, 0);
4876
4877 lookup_secondary_supers_table_var(sub_klass,
4878 super_klass,
4879 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4880 cmpq(result_reg, 0);
4881
4882 // Unspill the temp. registers:
4883 pop_set(pushed_regs, 0);
4884 // Increment SP but do not clobber flags.
4885 lea(rsp, Address(rsp, aligned_size));
4886 }
4887
4888 if (temp2_reg_was_valid) {
4889 movq(temp2_reg, 1);
4890 }
4891
4892 jcc(Assembler::notEqual, *L_failure);
4893
4894 if (L_success != &L_fallthrough) {
4895 jmp(*L_success);
4896 }
4897
4898 bind(L_fallthrough);
4899 }
4900
4901 // population_count variant for running without the POPCNT
4902 // instruction, which was introduced with SSE4.2 in 2008.
4903 void MacroAssembler::population_count(Register dst, Register src,
4904 Register scratch1, Register scratch2) {
4905 assert_different_registers(src, scratch1, scratch2);
4906 if (UsePopCountInstruction) {
4907 Assembler::popcntq(dst, src);
4908 } else {
4909 assert_different_registers(src, scratch1, scratch2);
4910 assert_different_registers(dst, scratch1, scratch2);
4911 Label loop, done;
4912
4913 mov(scratch1, src);
4914 // dst = 0;
4915 // while(scratch1 != 0) {
4916 // dst++;
4917 // scratch1 &= (scratch1 - 1);
4918 // }
4919 xorl(dst, dst);
4920 testq(scratch1, scratch1);
4921 jccb(Assembler::equal, done);
4922 {
4923 bind(loop);
4924 incq(dst);
4925 movq(scratch2, scratch1);
4926 decq(scratch2);
4927 andq(scratch1, scratch2);
4928 jccb(Assembler::notEqual, loop);
4929 }
4930 bind(done);
4931 }
4932 #ifdef ASSERT
4933 mov64(scratch1, 0xCafeBabeDeadBeef);
4934 movq(scratch2, scratch1);
4935 #endif
4936 }
4937
4938 // Ensure that the inline code and the stub are using the same registers.
4939 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4940 do { \
4941 assert(r_super_klass == rax, "mismatch"); \
4942 assert(r_array_base == rbx, "mismatch"); \
4943 assert(r_array_length == rcx, "mismatch"); \
4944 assert(r_array_index == rdx, "mismatch"); \
4945 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4946 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4947 assert(result == rdi || result == noreg, "mismatch"); \
4948 } while(0)
4949
4950 // Versions of salq and rorq that don't need count to be in rcx
4951
4952 void MacroAssembler::salq(Register dest, Register count) {
4953 if (count == rcx) {
4954 Assembler::salq(dest);
4955 } else {
4956 assert_different_registers(rcx, dest);
4957 xchgq(rcx, count);
4958 Assembler::salq(dest);
4959 xchgq(rcx, count);
4960 }
4961 }
4962
4963 void MacroAssembler::rorq(Register dest, Register count) {
4964 if (count == rcx) {
4965 Assembler::rorq(dest);
4966 } else {
4967 assert_different_registers(rcx, dest);
4968 xchgq(rcx, count);
4969 Assembler::rorq(dest);
4970 xchgq(rcx, count);
4971 }
4972 }
4973
4974 // Return true: we succeeded in generating this code
4975 //
4976 // At runtime, return 0 in result if r_super_klass is a superclass of
4977 // r_sub_klass, otherwise return nonzero. Use this if you know the
4978 // super_klass_slot of the class you're looking for. This is always
4979 // the case for instanceof and checkcast.
4980 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4981 Register r_super_klass,
4982 Register temp1,
4983 Register temp2,
4984 Register temp3,
4985 Register temp4,
4986 Register result,
4987 u1 super_klass_slot) {
4988 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4989
4990 Label L_fallthrough, L_success, L_failure;
4991
4992 BLOCK_COMMENT("lookup_secondary_supers_table {");
4993
4994 const Register
4995 r_array_index = temp1,
4996 r_array_length = temp2,
4997 r_array_base = temp3,
4998 r_bitmap = temp4;
4999
5000 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
5001
5002 xorq(result, result); // = 0
5003
5004 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
5005 movq(r_array_index, r_bitmap);
5006
5007 // First check the bitmap to see if super_klass might be present. If
5008 // the bit is zero, we are certain that super_klass is not one of
5009 // the secondary supers.
5010 u1 bit = super_klass_slot;
5011 {
5012 // NB: If the count in a x86 shift instruction is 0, the flags are
5013 // not affected, so we do a testq instead.
5014 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
5015 if (shift_count != 0) {
5016 salq(r_array_index, shift_count);
5017 } else {
5018 testq(r_array_index, r_array_index);
5019 }
5020 }
5021 // We test the MSB of r_array_index, i.e. its sign bit
5022 jcc(Assembler::positive, L_failure);
5023
5024 // Get the first array index that can contain super_klass into r_array_index.
5025 if (bit != 0) {
5026 population_count(r_array_index, r_array_index, temp2, temp3);
5027 } else {
5028 movl(r_array_index, 1);
5029 }
5030 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5031
5032 // We will consult the secondary-super array.
5033 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5034
5035 // We're asserting that the first word in an Array<Klass*> is the
5036 // length, and the second word is the first word of the data. If
5037 // that ever changes, r_array_base will have to be adjusted here.
5038 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5039 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5040
5041 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5042 jccb(Assembler::equal, L_success);
5043
5044 // Is there another entry to check? Consult the bitmap.
5045 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
5046 jccb(Assembler::carryClear, L_failure);
5047
5048 // Linear probe. Rotate the bitmap so that the next bit to test is
5049 // in Bit 1.
5050 if (bit != 0) {
5051 rorq(r_bitmap, bit);
5052 }
5053
5054 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5055 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5056 // Kills: r_array_length.
5057 // Returns: result.
5058 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
5059 // Result (0/1) is in rdi
5060 jmpb(L_fallthrough);
5061
5062 bind(L_failure);
5063 incq(result); // 0 => 1
5064
5065 bind(L_success);
5066 // result = 0;
5067
5068 bind(L_fallthrough);
5069 BLOCK_COMMENT("} lookup_secondary_supers_table");
5070
5071 if (VerifySecondarySupers) {
5072 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5073 temp1, temp2, temp3);
5074 }
5075 }
5076
5077 // At runtime, return 0 in result if r_super_klass is a superclass of
5078 // r_sub_klass, otherwise return nonzero. Use this version of
5079 // lookup_secondary_supers_table() if you don't know ahead of time
5080 // which superclass will be searched for. Used by interpreter and
5081 // runtime stubs. It is larger and has somewhat greater latency than
5082 // the version above, which takes a constant super_klass_slot.
5083 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
5084 Register r_super_klass,
5085 Register temp1,
5086 Register temp2,
5087 Register temp3,
5088 Register temp4,
5089 Register result) {
5090 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
5091 assert_different_registers(r_sub_klass, r_super_klass, rcx);
5092 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
5093
5094 Label L_fallthrough, L_success, L_failure;
5095
5096 BLOCK_COMMENT("lookup_secondary_supers_table {");
5097
5098 RegSetIterator<Register> available_regs = (temps - rcx).begin();
5099
5100 // FIXME. Once we are sure that all paths reaching this point really
5101 // do pass rcx as one of our temps we can get rid of the following
5102 // workaround.
5103 assert(temps.contains(rcx), "fix this code");
5104
5105 // We prefer to have our shift count in rcx. If rcx is one of our
5106 // temps, use it for slot. If not, pick any of our temps.
5107 Register slot;
5108 if (!temps.contains(rcx)) {
5109 slot = *available_regs++;
5110 } else {
5111 slot = rcx;
5112 }
5113
5114 const Register r_array_index = *available_regs++;
5115 const Register r_bitmap = *available_regs++;
5116
5117 // The logic above guarantees this property, but we state it here.
5118 assert_different_registers(r_array_index, r_bitmap, rcx);
5119
5120 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
5121 movq(r_array_index, r_bitmap);
5122
5123 // First check the bitmap to see if super_klass might be present. If
5124 // the bit is zero, we are certain that super_klass is not one of
5125 // the secondary supers.
5126 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
5127 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
5128 salq(r_array_index, slot);
5129
5130 testq(r_array_index, r_array_index);
5131 // We test the MSB of r_array_index, i.e. its sign bit
5132 jcc(Assembler::positive, L_failure);
5133
5134 const Register r_array_base = *available_regs++;
5135
5136 // Get the first array index that can contain super_klass into r_array_index.
5137 // Note: Clobbers r_array_base and slot.
5138 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
5139
5140 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5141
5142 // We will consult the secondary-super array.
5143 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5144
5145 // We're asserting that the first word in an Array<Klass*> is the
5146 // length, and the second word is the first word of the data. If
5147 // that ever changes, r_array_base will have to be adjusted here.
5148 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5149 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5150
5151 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5152 jccb(Assembler::equal, L_success);
5153
5154 // Restore slot to its true value
5155 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
5156
5157 // Linear probe. Rotate the bitmap so that the next bit to test is
5158 // in Bit 1.
5159 rorq(r_bitmap, slot);
5160
5161 // Is there another entry to check? Consult the bitmap.
5162 btq(r_bitmap, 1);
5163 jccb(Assembler::carryClear, L_failure);
5164
5165 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5166 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5167 // Kills: r_array_length.
5168 // Returns: result.
5169 lookup_secondary_supers_table_slow_path(r_super_klass,
5170 r_array_base,
5171 r_array_index,
5172 r_bitmap,
5173 /*temp1*/result,
5174 /*temp2*/slot,
5175 &L_success,
5176 nullptr);
5177
5178 bind(L_failure);
5179 movq(result, 1);
5180 jmpb(L_fallthrough);
5181
5182 bind(L_success);
5183 xorq(result, result); // = 0
5184
5185 bind(L_fallthrough);
5186 BLOCK_COMMENT("} lookup_secondary_supers_table");
5187
5188 if (VerifySecondarySupers) {
5189 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5190 temp1, temp2, temp3);
5191 }
5192 }
5193
5194 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
5195 Label* L_success, Label* L_failure) {
5196 Label L_loop, L_fallthrough;
5197 {
5198 int label_nulls = 0;
5199 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5200 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5201 assert(label_nulls <= 1, "at most one null in the batch");
5202 }
5203 bind(L_loop);
5204 cmpq(value, Address(addr, count, Address::times_8));
5205 jcc(Assembler::equal, *L_success);
5206 addl(count, 1);
5207 cmpl(count, limit);
5208 jcc(Assembler::less, L_loop);
5209
5210 if (&L_fallthrough != L_failure) {
5211 jmp(*L_failure);
5212 }
5213 bind(L_fallthrough);
5214 }
5215
5216 // Called by code generated by check_klass_subtype_slow_path
5217 // above. This is called when there is a collision in the hashed
5218 // lookup in the secondary supers array.
5219 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
5220 Register r_array_base,
5221 Register r_array_index,
5222 Register r_bitmap,
5223 Register temp1,
5224 Register temp2,
5225 Label* L_success,
5226 Label* L_failure) {
5227 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
5228
5229 const Register
5230 r_array_length = temp1,
5231 r_sub_klass = noreg,
5232 result = noreg;
5233
5234 Label L_fallthrough;
5235 int label_nulls = 0;
5236 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5237 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5238 assert(label_nulls <= 1, "at most one null in the batch");
5239
5240 // Load the array length.
5241 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5242 // And adjust the array base to point to the data.
5243 // NB! Effectively increments current slot index by 1.
5244 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
5245 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5246
5247 // Linear probe
5248 Label L_huge;
5249
5250 // The bitmap is full to bursting.
5251 // Implicit invariant: BITMAP_FULL implies (length > 0)
5252 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
5253 jcc(Assembler::greater, L_huge);
5254
5255 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
5256 // current slot (at secondary_supers[r_array_index]) has not yet
5257 // been inspected, and r_array_index may be out of bounds if we
5258 // wrapped around the end of the array.
5259
5260 { // This is conventional linear probing, but instead of terminating
5261 // when a null entry is found in the table, we maintain a bitmap
5262 // in which a 0 indicates missing entries.
5263 // The check above guarantees there are 0s in the bitmap, so the loop
5264 // eventually terminates.
5265
5266 xorl(temp2, temp2); // = 0;
5267
5268 Label L_again;
5269 bind(L_again);
5270
5271 // Check for array wraparound.
5272 cmpl(r_array_index, r_array_length);
5273 cmovl(Assembler::greaterEqual, r_array_index, temp2);
5274
5275 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5276 jcc(Assembler::equal, *L_success);
5277
5278 // If the next bit in bitmap is zero, we're done.
5279 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
5280 jcc(Assembler::carryClear, *L_failure);
5281
5282 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
5283 addl(r_array_index, 1);
5284
5285 jmp(L_again);
5286 }
5287
5288 { // Degenerate case: more than 64 secondary supers.
5289 // FIXME: We could do something smarter here, maybe a vectorized
5290 // comparison or a binary search, but is that worth any added
5291 // complexity?
5292 bind(L_huge);
5293 xorl(r_array_index, r_array_index); // = 0
5294 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
5295 L_success,
5296 (&L_fallthrough != L_failure ? L_failure : nullptr));
5297
5298 bind(L_fallthrough);
5299 }
5300 }
5301
5302 struct VerifyHelperArguments {
5303 Klass* _super;
5304 Klass* _sub;
5305 intptr_t _linear_result;
5306 intptr_t _table_result;
5307 };
5308
5309 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
5310 Klass::on_secondary_supers_verification_failure(args->_super,
5311 args->_sub,
5312 args->_linear_result,
5313 args->_table_result,
5314 msg);
5315 }
5316
5317 // Make sure that the hashed lookup and a linear scan agree.
5318 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
5319 Register r_super_klass,
5320 Register result,
5321 Register temp1,
5322 Register temp2,
5323 Register temp3) {
5324 const Register
5325 r_array_index = temp1,
5326 r_array_length = temp2,
5327 r_array_base = temp3,
5328 r_bitmap = noreg;
5329
5330 BLOCK_COMMENT("verify_secondary_supers_table {");
5331
5332 Label L_success, L_failure, L_check, L_done;
5333
5334 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5335 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5336 // And adjust the array base to point to the data.
5337 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5338
5339 testl(r_array_length, r_array_length); // array_length == 0?
5340 jcc(Assembler::zero, L_failure);
5341
5342 movl(r_array_index, 0);
5343 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
5344 // fall through to L_failure
5345
5346 const Register linear_result = r_array_index; // reuse temp1
5347
5348 bind(L_failure); // not present
5349 movl(linear_result, 1);
5350 jmp(L_check);
5351
5352 bind(L_success); // present
5353 movl(linear_result, 0);
5354
5355 bind(L_check);
5356 cmpl(linear_result, result);
5357 jcc(Assembler::equal, L_done);
5358
5359 { // To avoid calling convention issues, build a record on the stack
5360 // and pass the pointer to that instead.
5361 push(result);
5362 push(linear_result);
5363 push(r_sub_klass);
5364 push(r_super_klass);
5365 movptr(c_rarg1, rsp);
5366 movptr(c_rarg0, (uintptr_t) "mismatch");
5367 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
5368 should_not_reach_here();
5369 }
5370 bind(L_done);
5371
5372 BLOCK_COMMENT("} verify_secondary_supers_table");
5373 }
5374
5375 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
5376
5377 #endif // LP64
5378
5379 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
5380 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
5381
5382 Label L_fallthrough;
5383 if (L_fast_path == nullptr) {
5384 L_fast_path = &L_fallthrough;
5385 } else if (L_slow_path == nullptr) {
5386 L_slow_path = &L_fallthrough;
5387 }
5388
5389 // Fast path check: class is fully initialized.
5390 // init_state needs acquire, but x86 is TSO, and so we are already good.
5391 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
5392 jcc(Assembler::equal, *L_fast_path);
5393
5394 // Fast path check: current thread is initializer thread
5395 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
5396 if (L_slow_path == &L_fallthrough) {
5397 jcc(Assembler::equal, *L_fast_path);
5398 bind(*L_slow_path);
5399 } else if (L_fast_path == &L_fallthrough) {
5400 jcc(Assembler::notEqual, *L_slow_path);
5401 bind(*L_fast_path);
5402 } else {
5403 Unimplemented();
5404 }
5405 }
5406
5407 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5408 if (VM_Version::supports_cmov()) {
5409 cmovl(cc, dst, src);
5410 } else {
5411 Label L;
5412 jccb(negate_condition(cc), L);
5413 movl(dst, src);
5414 bind(L);
5415 }
5416 }
5417
5418 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5419 if (VM_Version::supports_cmov()) {
5420 cmovl(cc, dst, src);
5421 } else {
5422 Label L;
5423 jccb(negate_condition(cc), L);
5424 movl(dst, src);
5425 bind(L);
5426 }
5427 }
5428
5429 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
5430 if (!VerifyOops) return;
5431
5432 BLOCK_COMMENT("verify_oop {");
5433 #ifdef _LP64
5434 push(rscratch1);
5435 #endif
5436 push(rax); // save rax
5437 push(reg); // pass register argument
5438
5439 // Pass register number to verify_oop_subroutine
5440 const char* b = nullptr;
5441 {
5442 ResourceMark rm;
5443 stringStream ss;
5444 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5445 b = code_string(ss.as_string());
5446 }
5447 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5448 pushptr(buffer.addr(), rscratch1);
5449
5450 // call indirectly to solve generation ordering problem
5451 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5452 call(rax);
5453 // Caller pops the arguments (oop, message) and restores rax, r10
5454 BLOCK_COMMENT("} verify_oop");
5455 }
5456
5457 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
5458 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
5459 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
5460 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
5461 vpternlogd(dst, 0xFF, dst, dst, vector_len);
5462 } else if (VM_Version::supports_avx()) {
5463 vpcmpeqd(dst, dst, dst, vector_len);
5464 } else {
5465 pcmpeqd(dst, dst);
5466 }
5467 }
5468
5469 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5470 int extra_slot_offset) {
5471 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5472 int stackElementSize = Interpreter::stackElementSize;
5473 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5474 #ifdef ASSERT
5475 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5476 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5477 #endif
5478 Register scale_reg = noreg;
5479 Address::ScaleFactor scale_factor = Address::no_scale;
5480 if (arg_slot.is_constant()) {
5481 offset += arg_slot.as_constant() * stackElementSize;
5482 } else {
5483 scale_reg = arg_slot.as_register();
5484 scale_factor = Address::times(stackElementSize);
5485 }
5486 offset += wordSize; // return PC is on stack
5487 return Address(rsp, scale_reg, scale_factor, offset);
5488 }
5489
5490 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5491 if (!VerifyOops) return;
5492
5493 #ifdef _LP64
5494 push(rscratch1);
5495 #endif
5496 push(rax); // save rax,
5497 // addr may contain rsp so we will have to adjust it based on the push
5498 // we just did (and on 64 bit we do two pushes)
5499 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5500 // stores rax into addr which is backwards of what was intended.
5501 if (addr.uses(rsp)) {
5502 lea(rax, addr);
5503 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5504 } else {
5505 pushptr(addr);
5506 }
5507
5508 // Pass register number to verify_oop_subroutine
5509 const char* b = nullptr;
5510 {
5511 ResourceMark rm;
5512 stringStream ss;
5513 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5514 b = code_string(ss.as_string());
5515 }
5516 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5517 pushptr(buffer.addr(), rscratch1);
5518
5519 // call indirectly to solve generation ordering problem
5520 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5521 call(rax);
5522 // Caller pops the arguments (addr, message) and restores rax, r10.
5523 }
5524
5525 void MacroAssembler::verify_tlab() {
5526 #ifdef ASSERT
5527 if (UseTLAB && VerifyOops) {
5528 Label next, ok;
5529 Register t1 = rsi;
5530 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5531
5532 push(t1);
5533 NOT_LP64(push(thread_reg));
5534 NOT_LP64(get_thread(thread_reg));
5535
5536 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5537 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5538 jcc(Assembler::aboveEqual, next);
5539 STOP("assert(top >= start)");
5540 should_not_reach_here();
5541
5542 bind(next);
5543 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5544 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5545 jcc(Assembler::aboveEqual, ok);
5546 STOP("assert(top <= end)");
5547 should_not_reach_here();
5548
5549 bind(ok);
5550 NOT_LP64(pop(thread_reg));
5551 pop(t1);
5552 }
5553 #endif
5554 }
5555
5556 class ControlWord {
5557 public:
5558 int32_t _value;
5559
5560 int rounding_control() const { return (_value >> 10) & 3 ; }
5561 int precision_control() const { return (_value >> 8) & 3 ; }
5562 bool precision() const { return ((_value >> 5) & 1) != 0; }
5563 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5564 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5565 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5566 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5567 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5568
5569 void print() const {
5570 // rounding control
5571 const char* rc;
5572 switch (rounding_control()) {
5573 case 0: rc = "round near"; break;
5574 case 1: rc = "round down"; break;
5575 case 2: rc = "round up "; break;
5576 case 3: rc = "chop "; break;
5577 default:
5578 rc = nullptr; // silence compiler warnings
5579 fatal("Unknown rounding control: %d", rounding_control());
5580 };
5581 // precision control
5582 const char* pc;
5583 switch (precision_control()) {
5584 case 0: pc = "24 bits "; break;
5585 case 1: pc = "reserved"; break;
5586 case 2: pc = "53 bits "; break;
5587 case 3: pc = "64 bits "; break;
5588 default:
5589 pc = nullptr; // silence compiler warnings
5590 fatal("Unknown precision control: %d", precision_control());
5591 };
5592 // flags
5593 char f[9];
5594 f[0] = ' ';
5595 f[1] = ' ';
5596 f[2] = (precision ()) ? 'P' : 'p';
5597 f[3] = (underflow ()) ? 'U' : 'u';
5598 f[4] = (overflow ()) ? 'O' : 'o';
5599 f[5] = (zero_divide ()) ? 'Z' : 'z';
5600 f[6] = (denormalized()) ? 'D' : 'd';
5601 f[7] = (invalid ()) ? 'I' : 'i';
5602 f[8] = '\x0';
5603 // output
5604 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5605 }
5606
5607 };
5608
5609 class StatusWord {
5610 public:
5611 int32_t _value;
5612
5613 bool busy() const { return ((_value >> 15) & 1) != 0; }
5614 bool C3() const { return ((_value >> 14) & 1) != 0; }
5615 bool C2() const { return ((_value >> 10) & 1) != 0; }
5616 bool C1() const { return ((_value >> 9) & 1) != 0; }
5617 bool C0() const { return ((_value >> 8) & 1) != 0; }
5618 int top() const { return (_value >> 11) & 7 ; }
5619 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5620 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5621 bool precision() const { return ((_value >> 5) & 1) != 0; }
5622 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5623 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5624 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5625 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5626 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5627
5628 void print() const {
5629 // condition codes
5630 char c[5];
5631 c[0] = (C3()) ? '3' : '-';
5632 c[1] = (C2()) ? '2' : '-';
5633 c[2] = (C1()) ? '1' : '-';
5634 c[3] = (C0()) ? '0' : '-';
5635 c[4] = '\x0';
5636 // flags
5637 char f[9];
5638 f[0] = (error_status()) ? 'E' : '-';
5639 f[1] = (stack_fault ()) ? 'S' : '-';
5640 f[2] = (precision ()) ? 'P' : '-';
5641 f[3] = (underflow ()) ? 'U' : '-';
5642 f[4] = (overflow ()) ? 'O' : '-';
5643 f[5] = (zero_divide ()) ? 'Z' : '-';
5644 f[6] = (denormalized()) ? 'D' : '-';
5645 f[7] = (invalid ()) ? 'I' : '-';
5646 f[8] = '\x0';
5647 // output
5648 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5649 }
5650
5651 };
5652
5653 class TagWord {
5654 public:
5655 int32_t _value;
5656
5657 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5658
5659 void print() const {
5660 printf("%04x", _value & 0xFFFF);
5661 }
5662
5663 };
5664
5665 class FPU_Register {
5666 public:
5667 int32_t _m0;
5668 int32_t _m1;
5669 int16_t _ex;
5670
5671 bool is_indefinite() const {
5672 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5673 }
5674
5675 void print() const {
5676 char sign = (_ex < 0) ? '-' : '+';
5677 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5678 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5679 };
5680
5681 };
5682
5683 class FPU_State {
5684 public:
5685 enum {
5686 register_size = 10,
5687 number_of_registers = 8,
5688 register_mask = 7
5689 };
5690
5691 ControlWord _control_word;
5692 StatusWord _status_word;
5693 TagWord _tag_word;
5694 int32_t _error_offset;
5695 int32_t _error_selector;
5696 int32_t _data_offset;
5697 int32_t _data_selector;
5698 int8_t _register[register_size * number_of_registers];
5699
5700 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5701 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5702
5703 const char* tag_as_string(int tag) const {
5704 switch (tag) {
5705 case 0: return "valid";
5706 case 1: return "zero";
5707 case 2: return "special";
5708 case 3: return "empty";
5709 }
5710 ShouldNotReachHere();
5711 return nullptr;
5712 }
5713
5714 void print() const {
5715 // print computation registers
5716 { int t = _status_word.top();
5717 for (int i = 0; i < number_of_registers; i++) {
5718 int j = (i - t) & register_mask;
5719 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5720 st(j)->print();
5721 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5722 }
5723 }
5724 printf("\n");
5725 // print control registers
5726 printf("ctrl = "); _control_word.print(); printf("\n");
5727 printf("stat = "); _status_word .print(); printf("\n");
5728 printf("tags = "); _tag_word .print(); printf("\n");
5729 }
5730
5731 };
5732
5733 class Flag_Register {
5734 public:
5735 int32_t _value;
5736
5737 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5738 bool direction() const { return ((_value >> 10) & 1) != 0; }
5739 bool sign() const { return ((_value >> 7) & 1) != 0; }
5740 bool zero() const { return ((_value >> 6) & 1) != 0; }
5741 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5742 bool parity() const { return ((_value >> 2) & 1) != 0; }
5743 bool carry() const { return ((_value >> 0) & 1) != 0; }
5744
5745 void print() const {
5746 // flags
5747 char f[8];
5748 f[0] = (overflow ()) ? 'O' : '-';
5749 f[1] = (direction ()) ? 'D' : '-';
5750 f[2] = (sign ()) ? 'S' : '-';
5751 f[3] = (zero ()) ? 'Z' : '-';
5752 f[4] = (auxiliary_carry()) ? 'A' : '-';
5753 f[5] = (parity ()) ? 'P' : '-';
5754 f[6] = (carry ()) ? 'C' : '-';
5755 f[7] = '\x0';
5756 // output
5757 printf("%08x flags = %s", _value, f);
5758 }
5759
5760 };
5761
5762 class IU_Register {
5763 public:
5764 int32_t _value;
5765
5766 void print() const {
5767 printf("%08x %11d", _value, _value);
5768 }
5769
5770 };
5771
5772 class IU_State {
5773 public:
5774 Flag_Register _eflags;
5775 IU_Register _rdi;
5776 IU_Register _rsi;
5777 IU_Register _rbp;
5778 IU_Register _rsp;
5779 IU_Register _rbx;
5780 IU_Register _rdx;
5781 IU_Register _rcx;
5782 IU_Register _rax;
5783
5784 void print() const {
5785 // computation registers
5786 printf("rax, = "); _rax.print(); printf("\n");
5787 printf("rbx, = "); _rbx.print(); printf("\n");
5788 printf("rcx = "); _rcx.print(); printf("\n");
5789 printf("rdx = "); _rdx.print(); printf("\n");
5790 printf("rdi = "); _rdi.print(); printf("\n");
5791 printf("rsi = "); _rsi.print(); printf("\n");
5792 printf("rbp, = "); _rbp.print(); printf("\n");
5793 printf("rsp = "); _rsp.print(); printf("\n");
5794 printf("\n");
5795 // control registers
5796 printf("flgs = "); _eflags.print(); printf("\n");
5797 }
5798 };
5799
5800
5801 class CPU_State {
5802 public:
5803 FPU_State _fpu_state;
5804 IU_State _iu_state;
5805
5806 void print() const {
5807 printf("--------------------------------------------------\n");
5808 _iu_state .print();
5809 printf("\n");
5810 _fpu_state.print();
5811 printf("--------------------------------------------------\n");
5812 }
5813
5814 };
5815
5816
5817 static void _print_CPU_state(CPU_State* state) {
5818 state->print();
5819 };
5820
5821
5822 void MacroAssembler::print_CPU_state() {
5823 push_CPU_state();
5824 push(rsp); // pass CPU state
5825 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5826 addptr(rsp, wordSize); // discard argument
5827 pop_CPU_state();
5828 }
5829
5830
5831 #ifndef _LP64
5832 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5833 static int counter = 0;
5834 FPU_State* fs = &state->_fpu_state;
5835 counter++;
5836 // For leaf calls, only verify that the top few elements remain empty.
5837 // We only need 1 empty at the top for C2 code.
5838 if( stack_depth < 0 ) {
5839 if( fs->tag_for_st(7) != 3 ) {
5840 printf("FPR7 not empty\n");
5841 state->print();
5842 assert(false, "error");
5843 return false;
5844 }
5845 return true; // All other stack states do not matter
5846 }
5847
5848 assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
5849 "bad FPU control word");
5850
5851 // compute stack depth
5852 int i = 0;
5853 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5854 int d = i;
5855 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5856 // verify findings
5857 if (i != FPU_State::number_of_registers) {
5858 // stack not contiguous
5859 printf("%s: stack not contiguous at ST%d\n", s, i);
5860 state->print();
5861 assert(false, "error");
5862 return false;
5863 }
5864 // check if computed stack depth corresponds to expected stack depth
5865 if (stack_depth < 0) {
5866 // expected stack depth is -stack_depth or less
5867 if (d > -stack_depth) {
5868 // too many elements on the stack
5869 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5870 state->print();
5871 assert(false, "error");
5872 return false;
5873 }
5874 } else {
5875 // expected stack depth is stack_depth
5876 if (d != stack_depth) {
5877 // wrong stack depth
5878 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5879 state->print();
5880 assert(false, "error");
5881 return false;
5882 }
5883 }
5884 // everything is cool
5885 return true;
5886 }
5887
5888 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5889 if (!VerifyFPU) return;
5890 push_CPU_state();
5891 push(rsp); // pass CPU state
5892 ExternalAddress msg((address) s);
5893 // pass message string s
5894 pushptr(msg.addr(), noreg);
5895 push(stack_depth); // pass stack depth
5896 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5897 addptr(rsp, 3 * wordSize); // discard arguments
5898 // check for error
5899 { Label L;
5900 testl(rax, rax);
5901 jcc(Assembler::notZero, L);
5902 int3(); // break if error condition
5903 bind(L);
5904 }
5905 pop_CPU_state();
5906 }
5907 #endif // _LP64
5908
5909 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5910 // Either restore the MXCSR register after returning from the JNI Call
5911 // or verify that it wasn't changed (with -Xcheck:jni flag).
5912 if (VM_Version::supports_sse()) {
5913 if (RestoreMXCSROnJNICalls) {
5914 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5915 } else if (CheckJNICalls) {
5916 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5917 }
5918 }
5919 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5920 vzeroupper();
5921
5922 #ifndef _LP64
5923 // Either restore the x87 floating pointer control word after returning
5924 // from the JNI call or verify that it wasn't changed.
5925 if (CheckJNICalls) {
5926 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5927 }
5928 #endif // _LP64
5929 }
5930
5931 // ((OopHandle)result).resolve();
5932 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5933 assert_different_registers(result, tmp);
5934
5935 // Only 64 bit platforms support GCs that require a tmp register
5936 // Only IN_HEAP loads require a thread_tmp register
5937 // OopHandle::resolve is an indirection like jobject.
5938 access_load_at(T_OBJECT, IN_NATIVE,
5939 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5940 }
5941
5942 // ((WeakHandle)result).resolve();
5943 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5944 assert_different_registers(rresult, rtmp);
5945 Label resolved;
5946
5947 // A null weak handle resolves to null.
5948 cmpptr(rresult, 0);
5949 jcc(Assembler::equal, resolved);
5950
5951 // Only 64 bit platforms support GCs that require a tmp register
5952 // Only IN_HEAP loads require a thread_tmp register
5953 // WeakHandle::resolve is an indirection like jweak.
5954 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5955 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
5956 bind(resolved);
5957 }
5958
5959 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5960 // get mirror
5961 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5962 load_method_holder(mirror, method);
5963 movptr(mirror, Address(mirror, mirror_offset));
5964 resolve_oop_handle(mirror, tmp);
5965 }
5966
5967 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5968 load_method_holder(rresult, rmethod);
5969 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5970 }
5971
5972 void MacroAssembler::load_method_holder(Register holder, Register method) {
5973 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5974 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5975 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5976 }
5977
5978 #ifdef _LP64
5979 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5980 assert(UseCompactObjectHeaders, "expect compact object headers");
5981 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5982 shrq(dst, markWord::klass_shift);
5983 }
5984 #endif
5985
5986 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5987 assert_different_registers(src, tmp);
5988 assert_different_registers(dst, tmp);
5989 #ifdef _LP64
5990 if (UseCompactObjectHeaders) {
5991 load_narrow_klass_compact(dst, src);
5992 decode_klass_not_null(dst, tmp);
5993 } else if (UseCompressedClassPointers) {
5994 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5995 decode_klass_not_null(dst, tmp);
5996 } else
5997 #endif
5998 {
5999 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6000 }
6001 }
6002
6003 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
6004 assert(!UseCompactObjectHeaders, "not with compact headers");
6005 assert_different_registers(src, tmp);
6006 assert_different_registers(dst, tmp);
6007 #ifdef _LP64
6008 if (UseCompressedClassPointers) {
6009 encode_klass_not_null(src, tmp);
6010 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6011 } else
6012 #endif
6013 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6014 }
6015
6016 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
6017 #ifdef _LP64
6018 if (UseCompactObjectHeaders) {
6019 assert(tmp != noreg, "need tmp");
6020 assert_different_registers(klass, obj, tmp);
6021 load_narrow_klass_compact(tmp, obj);
6022 cmpl(klass, tmp);
6023 } else if (UseCompressedClassPointers) {
6024 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
6025 } else
6026 #endif
6027 {
6028 cmpptr(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
6029 }
6030 }
6031
6032 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
6033 #ifdef _LP64
6034 if (UseCompactObjectHeaders) {
6035 assert(tmp2 != noreg, "need tmp2");
6036 assert_different_registers(obj1, obj2, tmp1, tmp2);
6037 load_narrow_klass_compact(tmp1, obj1);
6038 load_narrow_klass_compact(tmp2, obj2);
6039 cmpl(tmp1, tmp2);
6040 } else if (UseCompressedClassPointers) {
6041 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
6042 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
6043 } else
6044 #endif
6045 {
6046 movptr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
6047 cmpptr(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
6048 }
6049 }
6050
6051 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
6052 Register tmp1, Register thread_tmp) {
6053 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6054 decorators = AccessInternal::decorator_fixup(decorators, type);
6055 bool as_raw = (decorators & AS_RAW) != 0;
6056 if (as_raw) {
6057 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6058 } else {
6059 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6060 }
6061 }
6062
6063 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
6064 Register tmp1, Register tmp2, Register tmp3) {
6065 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6066 decorators = AccessInternal::decorator_fixup(decorators, type);
6067 bool as_raw = (decorators & AS_RAW) != 0;
6068 if (as_raw) {
6069 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6070 } else {
6071 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6072 }
6073 }
6074
6075 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
6076 Register thread_tmp, DecoratorSet decorators) {
6077 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
6078 }
6079
6080 // Doesn't do verification, generates fixed size code
6081 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
6082 Register thread_tmp, DecoratorSet decorators) {
6083 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
6084 }
6085
6086 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
6087 Register tmp2, Register tmp3, DecoratorSet decorators) {
6088 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
6089 }
6090
6091 // Used for storing nulls.
6092 void MacroAssembler::store_heap_oop_null(Address dst) {
6093 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
6094 }
6095
6096 #ifdef _LP64
6097 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6098 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
6099 if (UseCompressedClassPointers) {
6100 // Store to klass gap in destination
6101 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6102 }
6103 }
6104
6105 #ifdef ASSERT
6106 void MacroAssembler::verify_heapbase(const char* msg) {
6107 assert (UseCompressedOops, "should be compressed");
6108 assert (Universe::heap() != nullptr, "java heap should be initialized");
6109 if (CheckCompressedOops) {
6110 Label ok;
6111 ExternalAddress src2(CompressedOops::base_addr());
6112 const bool is_src2_reachable = reachable(src2);
6113 if (!is_src2_reachable) {
6114 push(rscratch1); // cmpptr trashes rscratch1
6115 }
6116 cmpptr(r12_heapbase, src2, rscratch1);
6117 jcc(Assembler::equal, ok);
6118 STOP(msg);
6119 bind(ok);
6120 if (!is_src2_reachable) {
6121 pop(rscratch1);
6122 }
6123 }
6124 }
6125 #endif
6126
6127 // Algorithm must match oop.inline.hpp encode_heap_oop.
6128 void MacroAssembler::encode_heap_oop(Register r) {
6129 #ifdef ASSERT
6130 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6131 #endif
6132 verify_oop_msg(r, "broken oop in encode_heap_oop");
6133 if (CompressedOops::base() == nullptr) {
6134 if (CompressedOops::shift() != 0) {
6135 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6136 shrq(r, LogMinObjAlignmentInBytes);
6137 }
6138 return;
6139 }
6140 testq(r, r);
6141 cmovq(Assembler::equal, r, r12_heapbase);
6142 subq(r, r12_heapbase);
6143 shrq(r, LogMinObjAlignmentInBytes);
6144 }
6145
6146 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6147 #ifdef ASSERT
6148 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6149 if (CheckCompressedOops) {
6150 Label ok;
6151 testq(r, r);
6152 jcc(Assembler::notEqual, ok);
6153 STOP("null oop passed to encode_heap_oop_not_null");
6154 bind(ok);
6155 }
6156 #endif
6157 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
6158 if (CompressedOops::base() != nullptr) {
6159 subq(r, r12_heapbase);
6160 }
6161 if (CompressedOops::shift() != 0) {
6162 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6163 shrq(r, LogMinObjAlignmentInBytes);
6164 }
6165 }
6166
6167 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6168 #ifdef ASSERT
6169 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6170 if (CheckCompressedOops) {
6171 Label ok;
6172 testq(src, src);
6173 jcc(Assembler::notEqual, ok);
6174 STOP("null oop passed to encode_heap_oop_not_null2");
6175 bind(ok);
6176 }
6177 #endif
6178 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
6179 if (dst != src) {
6180 movq(dst, src);
6181 }
6182 if (CompressedOops::base() != nullptr) {
6183 subq(dst, r12_heapbase);
6184 }
6185 if (CompressedOops::shift() != 0) {
6186 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6187 shrq(dst, LogMinObjAlignmentInBytes);
6188 }
6189 }
6190
6191 void MacroAssembler::decode_heap_oop(Register r) {
6192 #ifdef ASSERT
6193 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6194 #endif
6195 if (CompressedOops::base() == nullptr) {
6196 if (CompressedOops::shift() != 0) {
6197 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6198 shlq(r, LogMinObjAlignmentInBytes);
6199 }
6200 } else {
6201 Label done;
6202 shlq(r, LogMinObjAlignmentInBytes);
6203 jccb(Assembler::equal, done);
6204 addq(r, r12_heapbase);
6205 bind(done);
6206 }
6207 verify_oop_msg(r, "broken oop in decode_heap_oop");
6208 }
6209
6210 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6211 // Note: it will change flags
6212 assert (UseCompressedOops, "should only be used for compressed headers");
6213 assert (Universe::heap() != nullptr, "java heap should be initialized");
6214 // Cannot assert, unverified entry point counts instructions (see .ad file)
6215 // vtableStubs also counts instructions in pd_code_size_limit.
6216 // Also do not verify_oop as this is called by verify_oop.
6217 if (CompressedOops::shift() != 0) {
6218 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6219 shlq(r, LogMinObjAlignmentInBytes);
6220 if (CompressedOops::base() != nullptr) {
6221 addq(r, r12_heapbase);
6222 }
6223 } else {
6224 assert (CompressedOops::base() == nullptr, "sanity");
6225 }
6226 }
6227
6228 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6229 // Note: it will change flags
6230 assert (UseCompressedOops, "should only be used for compressed headers");
6231 assert (Universe::heap() != nullptr, "java heap should be initialized");
6232 // Cannot assert, unverified entry point counts instructions (see .ad file)
6233 // vtableStubs also counts instructions in pd_code_size_limit.
6234 // Also do not verify_oop as this is called by verify_oop.
6235 if (CompressedOops::shift() != 0) {
6236 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6237 if (LogMinObjAlignmentInBytes == Address::times_8) {
6238 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6239 } else {
6240 if (dst != src) {
6241 movq(dst, src);
6242 }
6243 shlq(dst, LogMinObjAlignmentInBytes);
6244 if (CompressedOops::base() != nullptr) {
6245 addq(dst, r12_heapbase);
6246 }
6247 }
6248 } else {
6249 assert (CompressedOops::base() == nullptr, "sanity");
6250 if (dst != src) {
6251 movq(dst, src);
6252 }
6253 }
6254 }
6255
6256 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
6257 assert_different_registers(r, tmp);
6258 if (CompressedKlassPointers::base() != nullptr) {
6259 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6260 subq(r, tmp);
6261 }
6262 if (CompressedKlassPointers::shift() != 0) {
6263 shrq(r, CompressedKlassPointers::shift());
6264 }
6265 }
6266
6267 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
6268 assert_different_registers(src, dst);
6269 if (CompressedKlassPointers::base() != nullptr) {
6270 mov64(dst, -(int64_t)CompressedKlassPointers::base());
6271 addq(dst, src);
6272 } else {
6273 movptr(dst, src);
6274 }
6275 if (CompressedKlassPointers::shift() != 0) {
6276 shrq(dst, CompressedKlassPointers::shift());
6277 }
6278 }
6279
6280 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
6281 assert_different_registers(r, tmp);
6282 // Note: it will change flags
6283 assert(UseCompressedClassPointers, "should only be used for compressed headers");
6284 // Cannot assert, unverified entry point counts instructions (see .ad file)
6285 // vtableStubs also counts instructions in pd_code_size_limit.
6286 // Also do not verify_oop as this is called by verify_oop.
6287 if (CompressedKlassPointers::shift() != 0) {
6288 shlq(r, CompressedKlassPointers::shift());
6289 }
6290 if (CompressedKlassPointers::base() != nullptr) {
6291 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6292 addq(r, tmp);
6293 }
6294 }
6295
6296 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
6297 assert_different_registers(src, dst);
6298 // Note: it will change flags
6299 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6300 // Cannot assert, unverified entry point counts instructions (see .ad file)
6301 // vtableStubs also counts instructions in pd_code_size_limit.
6302 // Also do not verify_oop as this is called by verify_oop.
6303
6304 if (CompressedKlassPointers::base() == nullptr &&
6305 CompressedKlassPointers::shift() == 0) {
6306 // The best case scenario is that there is no base or shift. Then it is already
6307 // a pointer that needs nothing but a register rename.
6308 movl(dst, src);
6309 } else {
6310 if (CompressedKlassPointers::shift() <= Address::times_8) {
6311 if (CompressedKlassPointers::base() != nullptr) {
6312 mov64(dst, (int64_t)CompressedKlassPointers::base());
6313 } else {
6314 xorq(dst, dst);
6315 }
6316 if (CompressedKlassPointers::shift() != 0) {
6317 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
6318 leaq(dst, Address(dst, src, Address::times_8, 0));
6319 } else {
6320 addq(dst, src);
6321 }
6322 } else {
6323 if (CompressedKlassPointers::base() != nullptr) {
6324 const uint64_t base_right_shifted =
6325 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
6326 mov64(dst, base_right_shifted);
6327 } else {
6328 xorq(dst, dst);
6329 }
6330 addq(dst, src);
6331 shlq(dst, CompressedKlassPointers::shift());
6332 }
6333 }
6334 }
6335
6336 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6337 assert (UseCompressedOops, "should only be used for compressed headers");
6338 assert (Universe::heap() != nullptr, "java heap should be initialized");
6339 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6340 int oop_index = oop_recorder()->find_index(obj);
6341 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6342 mov_narrow_oop(dst, oop_index, rspec);
6343 }
6344
6345 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6346 assert (UseCompressedOops, "should only be used for compressed headers");
6347 assert (Universe::heap() != nullptr, "java heap should be initialized");
6348 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6349 int oop_index = oop_recorder()->find_index(obj);
6350 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6351 mov_narrow_oop(dst, oop_index, rspec);
6352 }
6353
6354 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6355 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6356 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6357 int klass_index = oop_recorder()->find_index(k);
6358 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6359 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6360 }
6361
6362 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6363 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6364 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6365 int klass_index = oop_recorder()->find_index(k);
6366 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6367 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6368 }
6369
6370 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6371 assert (UseCompressedOops, "should only be used for compressed headers");
6372 assert (Universe::heap() != nullptr, "java heap should be initialized");
6373 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6374 int oop_index = oop_recorder()->find_index(obj);
6375 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6376 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6377 }
6378
6379 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6380 assert (UseCompressedOops, "should only be used for compressed headers");
6381 assert (Universe::heap() != nullptr, "java heap should be initialized");
6382 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6383 int oop_index = oop_recorder()->find_index(obj);
6384 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6385 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6386 }
6387
6388 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6389 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6390 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6391 int klass_index = oop_recorder()->find_index(k);
6392 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6393 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6394 }
6395
6396 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6397 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6398 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6399 int klass_index = oop_recorder()->find_index(k);
6400 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6401 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6402 }
6403
6404 void MacroAssembler::reinit_heapbase() {
6405 if (UseCompressedOops) {
6406 if (Universe::heap() != nullptr) {
6407 if (CompressedOops::base() == nullptr) {
6408 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6409 } else {
6410 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6411 }
6412 } else {
6413 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6414 }
6415 }
6416 }
6417
6418 #endif // _LP64
6419
6420 #if COMPILER2_OR_JVMCI
6421
6422 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6423 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6424 // cnt - number of qwords (8-byte words).
6425 // base - start address, qword aligned.
6426 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6427 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
6428 if (use64byteVector) {
6429 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
6430 } else if (MaxVectorSize >= 32) {
6431 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
6432 } else {
6433 pxor(xtmp, xtmp);
6434 }
6435 jmp(L_zero_64_bytes);
6436
6437 BIND(L_loop);
6438 if (MaxVectorSize >= 32) {
6439 fill64(base, 0, xtmp, use64byteVector);
6440 } else {
6441 movdqu(Address(base, 0), xtmp);
6442 movdqu(Address(base, 16), xtmp);
6443 movdqu(Address(base, 32), xtmp);
6444 movdqu(Address(base, 48), xtmp);
6445 }
6446 addptr(base, 64);
6447
6448 BIND(L_zero_64_bytes);
6449 subptr(cnt, 8);
6450 jccb(Assembler::greaterEqual, L_loop);
6451
6452 // Copy trailing 64 bytes
6453 if (use64byteVector) {
6454 addptr(cnt, 8);
6455 jccb(Assembler::equal, L_end);
6456 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
6457 jmp(L_end);
6458 } else {
6459 addptr(cnt, 4);
6460 jccb(Assembler::less, L_tail);
6461 if (MaxVectorSize >= 32) {
6462 vmovdqu(Address(base, 0), xtmp);
6463 } else {
6464 movdqu(Address(base, 0), xtmp);
6465 movdqu(Address(base, 16), xtmp);
6466 }
6467 }
6468 addptr(base, 32);
6469 subptr(cnt, 4);
6470
6471 BIND(L_tail);
6472 addptr(cnt, 4);
6473 jccb(Assembler::lessEqual, L_end);
6474 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6475 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
6476 } else {
6477 decrement(cnt);
6478
6479 BIND(L_sloop);
6480 movq(Address(base, 0), xtmp);
6481 addptr(base, 8);
6482 decrement(cnt);
6483 jccb(Assembler::greaterEqual, L_sloop);
6484 }
6485 BIND(L_end);
6486 }
6487
6488 // Clearing constant sized memory using YMM/ZMM registers.
6489 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6490 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6491 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
6492
6493 int vector64_count = (cnt & (~0x7)) >> 3;
6494 cnt = cnt & 0x7;
6495 const int fill64_per_loop = 4;
6496 const int max_unrolled_fill64 = 8;
6497
6498 // 64 byte initialization loop.
6499 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6500 int start64 = 0;
6501 if (vector64_count > max_unrolled_fill64) {
6502 Label LOOP;
6503 Register index = rtmp;
6504
6505 start64 = vector64_count - (vector64_count % fill64_per_loop);
6506
6507 movl(index, 0);
6508 BIND(LOOP);
6509 for (int i = 0; i < fill64_per_loop; i++) {
6510 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6511 }
6512 addl(index, fill64_per_loop * 64);
6513 cmpl(index, start64 * 64);
6514 jccb(Assembler::less, LOOP);
6515 }
6516 for (int i = start64; i < vector64_count; i++) {
6517 fill64(base, i * 64, xtmp, use64byteVector);
6518 }
6519
6520 // Clear remaining 64 byte tail.
6521 int disp = vector64_count * 64;
6522 if (cnt) {
6523 switch (cnt) {
6524 case 1:
6525 movq(Address(base, disp), xtmp);
6526 break;
6527 case 2:
6528 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6529 break;
6530 case 3:
6531 movl(rtmp, 0x7);
6532 kmovwl(mask, rtmp);
6533 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6534 break;
6535 case 4:
6536 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6537 break;
6538 case 5:
6539 if (use64byteVector) {
6540 movl(rtmp, 0x1F);
6541 kmovwl(mask, rtmp);
6542 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6543 } else {
6544 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6545 movq(Address(base, disp + 32), xtmp);
6546 }
6547 break;
6548 case 6:
6549 if (use64byteVector) {
6550 movl(rtmp, 0x3F);
6551 kmovwl(mask, rtmp);
6552 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6553 } else {
6554 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6555 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6556 }
6557 break;
6558 case 7:
6559 if (use64byteVector) {
6560 movl(rtmp, 0x7F);
6561 kmovwl(mask, rtmp);
6562 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6563 } else {
6564 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6565 movl(rtmp, 0x7);
6566 kmovwl(mask, rtmp);
6567 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6568 }
6569 break;
6570 default:
6571 fatal("Unexpected length : %d\n",cnt);
6572 break;
6573 }
6574 }
6575 }
6576
6577 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
6578 bool is_large, KRegister mask) {
6579 // cnt - number of qwords (8-byte words).
6580 // base - start address, qword aligned.
6581 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6582 assert(base==rdi, "base register must be edi for rep stos");
6583 assert(tmp==rax, "tmp register must be eax for rep stos");
6584 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6585 assert(InitArrayShortSize % BytesPerLong == 0,
6586 "InitArrayShortSize should be the multiple of BytesPerLong");
6587
6588 Label DONE;
6589 if (!is_large || !UseXMMForObjInit) {
6590 xorptr(tmp, tmp);
6591 }
6592
6593 if (!is_large) {
6594 Label LOOP, LONG;
6595 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6596 jccb(Assembler::greater, LONG);
6597
6598 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6599
6600 decrement(cnt);
6601 jccb(Assembler::negative, DONE); // Zero length
6602
6603 // Use individual pointer-sized stores for small counts:
6604 BIND(LOOP);
6605 movptr(Address(base, cnt, Address::times_ptr), tmp);
6606 decrement(cnt);
6607 jccb(Assembler::greaterEqual, LOOP);
6608 jmpb(DONE);
6609
6610 BIND(LONG);
6611 }
6612
6613 // Use longer rep-prefixed ops for non-small counts:
6614 if (UseFastStosb) {
6615 shlptr(cnt, 3); // convert to number of bytes
6616 rep_stosb();
6617 } else if (UseXMMForObjInit) {
6618 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
6619 } else {
6620 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6621 rep_stos();
6622 }
6623
6624 BIND(DONE);
6625 }
6626
6627 #endif //COMPILER2_OR_JVMCI
6628
6629
6630 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6631 Register to, Register value, Register count,
6632 Register rtmp, XMMRegister xtmp) {
6633 ShortBranchVerifier sbv(this);
6634 assert_different_registers(to, value, count, rtmp);
6635 Label L_exit;
6636 Label L_fill_2_bytes, L_fill_4_bytes;
6637
6638 #if defined(COMPILER2) && defined(_LP64)
6639 if(MaxVectorSize >=32 &&
6640 VM_Version::supports_avx512vlbw() &&
6641 VM_Version::supports_bmi2()) {
6642 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6643 return;
6644 }
6645 #endif
6646
6647 int shift = -1;
6648 switch (t) {
6649 case T_BYTE:
6650 shift = 2;
6651 break;
6652 case T_SHORT:
6653 shift = 1;
6654 break;
6655 case T_INT:
6656 shift = 0;
6657 break;
6658 default: ShouldNotReachHere();
6659 }
6660
6661 if (t == T_BYTE) {
6662 andl(value, 0xff);
6663 movl(rtmp, value);
6664 shll(rtmp, 8);
6665 orl(value, rtmp);
6666 }
6667 if (t == T_SHORT) {
6668 andl(value, 0xffff);
6669 }
6670 if (t == T_BYTE || t == T_SHORT) {
6671 movl(rtmp, value);
6672 shll(rtmp, 16);
6673 orl(value, rtmp);
6674 }
6675
6676 cmpptr(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
6677 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6678 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6679 Label L_skip_align2;
6680 // align source address at 4 bytes address boundary
6681 if (t == T_BYTE) {
6682 Label L_skip_align1;
6683 // One byte misalignment happens only for byte arrays
6684 testptr(to, 1);
6685 jccb(Assembler::zero, L_skip_align1);
6686 movb(Address(to, 0), value);
6687 increment(to);
6688 decrement(count);
6689 BIND(L_skip_align1);
6690 }
6691 // Two bytes misalignment happens only for byte and short (char) arrays
6692 testptr(to, 2);
6693 jccb(Assembler::zero, L_skip_align2);
6694 movw(Address(to, 0), value);
6695 addptr(to, 2);
6696 subptr(count, 1<<(shift-1));
6697 BIND(L_skip_align2);
6698 }
6699 if (UseSSE < 2) {
6700 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6701 // Fill 32-byte chunks
6702 subptr(count, 8 << shift);
6703 jcc(Assembler::less, L_check_fill_8_bytes);
6704 align(16);
6705
6706 BIND(L_fill_32_bytes_loop);
6707
6708 for (int i = 0; i < 32; i += 4) {
6709 movl(Address(to, i), value);
6710 }
6711
6712 addptr(to, 32);
6713 subptr(count, 8 << shift);
6714 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6715 BIND(L_check_fill_8_bytes);
6716 addptr(count, 8 << shift);
6717 jccb(Assembler::zero, L_exit);
6718 jmpb(L_fill_8_bytes);
6719
6720 //
6721 // length is too short, just fill qwords
6722 //
6723 BIND(L_fill_8_bytes_loop);
6724 movl(Address(to, 0), value);
6725 movl(Address(to, 4), value);
6726 addptr(to, 8);
6727 BIND(L_fill_8_bytes);
6728 subptr(count, 1 << (shift + 1));
6729 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6730 // fall through to fill 4 bytes
6731 } else {
6732 Label L_fill_32_bytes;
6733 if (!UseUnalignedLoadStores) {
6734 // align to 8 bytes, we know we are 4 byte aligned to start
6735 testptr(to, 4);
6736 jccb(Assembler::zero, L_fill_32_bytes);
6737 movl(Address(to, 0), value);
6738 addptr(to, 4);
6739 subptr(count, 1<<shift);
6740 }
6741 BIND(L_fill_32_bytes);
6742 {
6743 assert( UseSSE >= 2, "supported cpu only" );
6744 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6745 movdl(xtmp, value);
6746 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6747 Label L_check_fill_32_bytes;
6748 if (UseAVX > 2) {
6749 // Fill 64-byte chunks
6750 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6751
6752 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
6753 cmpptr(count, VM_Version::avx3_threshold());
6754 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6755
6756 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6757
6758 subptr(count, 16 << shift);
6759 jccb(Assembler::less, L_check_fill_32_bytes);
6760 align(16);
6761
6762 BIND(L_fill_64_bytes_loop_avx3);
6763 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6764 addptr(to, 64);
6765 subptr(count, 16 << shift);
6766 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6767 jmpb(L_check_fill_32_bytes);
6768
6769 BIND(L_check_fill_64_bytes_avx2);
6770 }
6771 // Fill 64-byte chunks
6772 Label L_fill_64_bytes_loop;
6773 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6774
6775 subptr(count, 16 << shift);
6776 jcc(Assembler::less, L_check_fill_32_bytes);
6777 align(16);
6778
6779 BIND(L_fill_64_bytes_loop);
6780 vmovdqu(Address(to, 0), xtmp);
6781 vmovdqu(Address(to, 32), xtmp);
6782 addptr(to, 64);
6783 subptr(count, 16 << shift);
6784 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6785
6786 BIND(L_check_fill_32_bytes);
6787 addptr(count, 8 << shift);
6788 jccb(Assembler::less, L_check_fill_8_bytes);
6789 vmovdqu(Address(to, 0), xtmp);
6790 addptr(to, 32);
6791 subptr(count, 8 << shift);
6792
6793 BIND(L_check_fill_8_bytes);
6794 // clean upper bits of YMM registers
6795 movdl(xtmp, value);
6796 pshufd(xtmp, xtmp, 0);
6797 } else {
6798 // Fill 32-byte chunks
6799 pshufd(xtmp, xtmp, 0);
6800
6801 subptr(count, 8 << shift);
6802 jcc(Assembler::less, L_check_fill_8_bytes);
6803 align(16);
6804
6805 BIND(L_fill_32_bytes_loop);
6806
6807 if (UseUnalignedLoadStores) {
6808 movdqu(Address(to, 0), xtmp);
6809 movdqu(Address(to, 16), xtmp);
6810 } else {
6811 movq(Address(to, 0), xtmp);
6812 movq(Address(to, 8), xtmp);
6813 movq(Address(to, 16), xtmp);
6814 movq(Address(to, 24), xtmp);
6815 }
6816
6817 addptr(to, 32);
6818 subptr(count, 8 << shift);
6819 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6820
6821 BIND(L_check_fill_8_bytes);
6822 }
6823 addptr(count, 8 << shift);
6824 jccb(Assembler::zero, L_exit);
6825 jmpb(L_fill_8_bytes);
6826
6827 //
6828 // length is too short, just fill qwords
6829 //
6830 BIND(L_fill_8_bytes_loop);
6831 movq(Address(to, 0), xtmp);
6832 addptr(to, 8);
6833 BIND(L_fill_8_bytes);
6834 subptr(count, 1 << (shift + 1));
6835 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6836 }
6837 }
6838 // fill trailing 4 bytes
6839 BIND(L_fill_4_bytes);
6840 testl(count, 1<<shift);
6841 jccb(Assembler::zero, L_fill_2_bytes);
6842 movl(Address(to, 0), value);
6843 if (t == T_BYTE || t == T_SHORT) {
6844 Label L_fill_byte;
6845 addptr(to, 4);
6846 BIND(L_fill_2_bytes);
6847 // fill trailing 2 bytes
6848 testl(count, 1<<(shift-1));
6849 jccb(Assembler::zero, L_fill_byte);
6850 movw(Address(to, 0), value);
6851 if (t == T_BYTE) {
6852 addptr(to, 2);
6853 BIND(L_fill_byte);
6854 // fill trailing byte
6855 testl(count, 1);
6856 jccb(Assembler::zero, L_exit);
6857 movb(Address(to, 0), value);
6858 } else {
6859 BIND(L_fill_byte);
6860 }
6861 } else {
6862 BIND(L_fill_2_bytes);
6863 }
6864 BIND(L_exit);
6865 }
6866
6867 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6868 switch(type) {
6869 case T_BYTE:
6870 case T_BOOLEAN:
6871 evpbroadcastb(dst, src, vector_len);
6872 break;
6873 case T_SHORT:
6874 case T_CHAR:
6875 evpbroadcastw(dst, src, vector_len);
6876 break;
6877 case T_INT:
6878 case T_FLOAT:
6879 evpbroadcastd(dst, src, vector_len);
6880 break;
6881 case T_LONG:
6882 case T_DOUBLE:
6883 evpbroadcastq(dst, src, vector_len);
6884 break;
6885 default:
6886 fatal("Unhandled type : %s", type2name(type));
6887 break;
6888 }
6889 }
6890
6891 // encode char[] to byte[] in ISO_8859_1 or ASCII
6892 //@IntrinsicCandidate
6893 //private static int implEncodeISOArray(byte[] sa, int sp,
6894 //byte[] da, int dp, int len) {
6895 // int i = 0;
6896 // for (; i < len; i++) {
6897 // char c = StringUTF16.getChar(sa, sp++);
6898 // if (c > '\u00FF')
6899 // break;
6900 // da[dp++] = (byte)c;
6901 // }
6902 // return i;
6903 //}
6904 //
6905 //@IntrinsicCandidate
6906 //private static int implEncodeAsciiArray(char[] sa, int sp,
6907 // byte[] da, int dp, int len) {
6908 // int i = 0;
6909 // for (; i < len; i++) {
6910 // char c = sa[sp++];
6911 // if (c >= '\u0080')
6912 // break;
6913 // da[dp++] = (byte)c;
6914 // }
6915 // return i;
6916 //}
6917 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6918 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6919 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6920 Register tmp5, Register result, bool ascii) {
6921
6922 // rsi: src
6923 // rdi: dst
6924 // rdx: len
6925 // rcx: tmp5
6926 // rax: result
6927 ShortBranchVerifier sbv(this);
6928 assert_different_registers(src, dst, len, tmp5, result);
6929 Label L_done, L_copy_1_char, L_copy_1_char_exit;
6930
6931 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
6932 int short_mask = ascii ? 0xff80 : 0xff00;
6933
6934 // set result
6935 xorl(result, result);
6936 // check for zero length
6937 testl(len, len);
6938 jcc(Assembler::zero, L_done);
6939
6940 movl(result, len);
6941
6942 // Setup pointers
6943 lea(src, Address(src, len, Address::times_2)); // char[]
6944 lea(dst, Address(dst, len, Address::times_1)); // byte[]
6945 negptr(len);
6946
6947 if (UseSSE42Intrinsics || UseAVX >= 2) {
6948 Label L_copy_8_chars, L_copy_8_chars_exit;
6949 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
6950
6951 if (UseAVX >= 2) {
6952 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
6953 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6954 movdl(tmp1Reg, tmp5);
6955 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
6956 jmp(L_chars_32_check);
6957
6958 bind(L_copy_32_chars);
6959 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
6960 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
6961 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6962 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6963 jccb(Assembler::notZero, L_copy_32_chars_exit);
6964 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6965 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
6966 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
6967
6968 bind(L_chars_32_check);
6969 addptr(len, 32);
6970 jcc(Assembler::lessEqual, L_copy_32_chars);
6971
6972 bind(L_copy_32_chars_exit);
6973 subptr(len, 16);
6974 jccb(Assembler::greater, L_copy_16_chars_exit);
6975
6976 } else if (UseSSE42Intrinsics) {
6977 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6978 movdl(tmp1Reg, tmp5);
6979 pshufd(tmp1Reg, tmp1Reg, 0);
6980 jmpb(L_chars_16_check);
6981 }
6982
6983 bind(L_copy_16_chars);
6984 if (UseAVX >= 2) {
6985 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
6986 vptest(tmp2Reg, tmp1Reg);
6987 jcc(Assembler::notZero, L_copy_16_chars_exit);
6988 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
6989 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
6990 } else {
6991 if (UseAVX > 0) {
6992 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6993 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6994 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
6995 } else {
6996 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6997 por(tmp2Reg, tmp3Reg);
6998 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6999 por(tmp2Reg, tmp4Reg);
7000 }
7001 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7002 jccb(Assembler::notZero, L_copy_16_chars_exit);
7003 packuswb(tmp3Reg, tmp4Reg);
7004 }
7005 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7006
7007 bind(L_chars_16_check);
7008 addptr(len, 16);
7009 jcc(Assembler::lessEqual, L_copy_16_chars);
7010
7011 bind(L_copy_16_chars_exit);
7012 if (UseAVX >= 2) {
7013 // clean upper bits of YMM registers
7014 vpxor(tmp2Reg, tmp2Reg);
7015 vpxor(tmp3Reg, tmp3Reg);
7016 vpxor(tmp4Reg, tmp4Reg);
7017 movdl(tmp1Reg, tmp5);
7018 pshufd(tmp1Reg, tmp1Reg, 0);
7019 }
7020 subptr(len, 8);
7021 jccb(Assembler::greater, L_copy_8_chars_exit);
7022
7023 bind(L_copy_8_chars);
7024 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7025 ptest(tmp3Reg, tmp1Reg);
7026 jccb(Assembler::notZero, L_copy_8_chars_exit);
7027 packuswb(tmp3Reg, tmp1Reg);
7028 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7029 addptr(len, 8);
7030 jccb(Assembler::lessEqual, L_copy_8_chars);
7031
7032 bind(L_copy_8_chars_exit);
7033 subptr(len, 8);
7034 jccb(Assembler::zero, L_done);
7035 }
7036
7037 bind(L_copy_1_char);
7038 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7039 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
7040 jccb(Assembler::notZero, L_copy_1_char_exit);
7041 movb(Address(dst, len, Address::times_1, 0), tmp5);
7042 addptr(len, 1);
7043 jccb(Assembler::less, L_copy_1_char);
7044
7045 bind(L_copy_1_char_exit);
7046 addptr(result, len); // len is negative count of not processed elements
7047
7048 bind(L_done);
7049 }
7050
7051 #ifdef _LP64
7052 /**
7053 * Helper for multiply_to_len().
7054 */
7055 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7056 addq(dest_lo, src1);
7057 adcq(dest_hi, 0);
7058 addq(dest_lo, src2);
7059 adcq(dest_hi, 0);
7060 }
7061
7062 /**
7063 * Multiply 64 bit by 64 bit first loop.
7064 */
7065 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7066 Register y, Register y_idx, Register z,
7067 Register carry, Register product,
7068 Register idx, Register kdx) {
7069 //
7070 // jlong carry, x[], y[], z[];
7071 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7072 // huge_128 product = y[idx] * x[xstart] + carry;
7073 // z[kdx] = (jlong)product;
7074 // carry = (jlong)(product >>> 64);
7075 // }
7076 // z[xstart] = carry;
7077 //
7078
7079 Label L_first_loop, L_first_loop_exit;
7080 Label L_one_x, L_one_y, L_multiply;
7081
7082 decrementl(xstart);
7083 jcc(Assembler::negative, L_one_x);
7084
7085 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7086 rorq(x_xstart, 32); // convert big-endian to little-endian
7087
7088 bind(L_first_loop);
7089 decrementl(idx);
7090 jcc(Assembler::negative, L_first_loop_exit);
7091 decrementl(idx);
7092 jcc(Assembler::negative, L_one_y);
7093 movq(y_idx, Address(y, idx, Address::times_4, 0));
7094 rorq(y_idx, 32); // convert big-endian to little-endian
7095 bind(L_multiply);
7096 movq(product, x_xstart);
7097 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7098 addq(product, carry);
7099 adcq(rdx, 0);
7100 subl(kdx, 2);
7101 movl(Address(z, kdx, Address::times_4, 4), product);
7102 shrq(product, 32);
7103 movl(Address(z, kdx, Address::times_4, 0), product);
7104 movq(carry, rdx);
7105 jmp(L_first_loop);
7106
7107 bind(L_one_y);
7108 movl(y_idx, Address(y, 0));
7109 jmp(L_multiply);
7110
7111 bind(L_one_x);
7112 movl(x_xstart, Address(x, 0));
7113 jmp(L_first_loop);
7114
7115 bind(L_first_loop_exit);
7116 }
7117
7118 /**
7119 * Multiply 64 bit by 64 bit and add 128 bit.
7120 */
7121 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7122 Register yz_idx, Register idx,
7123 Register carry, Register product, int offset) {
7124 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7125 // z[kdx] = (jlong)product;
7126
7127 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7128 rorq(yz_idx, 32); // convert big-endian to little-endian
7129 movq(product, x_xstart);
7130 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7131 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7132 rorq(yz_idx, 32); // convert big-endian to little-endian
7133
7134 add2_with_carry(rdx, product, carry, yz_idx);
7135
7136 movl(Address(z, idx, Address::times_4, offset+4), product);
7137 shrq(product, 32);
7138 movl(Address(z, idx, Address::times_4, offset), product);
7139
7140 }
7141
7142 /**
7143 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7144 */
7145 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7146 Register yz_idx, Register idx, Register jdx,
7147 Register carry, Register product,
7148 Register carry2) {
7149 // jlong carry, x[], y[], z[];
7150 // int kdx = ystart+1;
7151 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7152 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7153 // z[kdx+idx+1] = (jlong)product;
7154 // jlong carry2 = (jlong)(product >>> 64);
7155 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7156 // z[kdx+idx] = (jlong)product;
7157 // carry = (jlong)(product >>> 64);
7158 // }
7159 // idx += 2;
7160 // if (idx > 0) {
7161 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7162 // z[kdx+idx] = (jlong)product;
7163 // carry = (jlong)(product >>> 64);
7164 // }
7165 //
7166
7167 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7168
7169 movl(jdx, idx);
7170 andl(jdx, 0xFFFFFFFC);
7171 shrl(jdx, 2);
7172
7173 bind(L_third_loop);
7174 subl(jdx, 1);
7175 jcc(Assembler::negative, L_third_loop_exit);
7176 subl(idx, 4);
7177
7178 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7179 movq(carry2, rdx);
7180
7181 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7182 movq(carry, rdx);
7183 jmp(L_third_loop);
7184
7185 bind (L_third_loop_exit);
7186
7187 andl (idx, 0x3);
7188 jcc(Assembler::zero, L_post_third_loop_done);
7189
7190 Label L_check_1;
7191 subl(idx, 2);
7192 jcc(Assembler::negative, L_check_1);
7193
7194 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7195 movq(carry, rdx);
7196
7197 bind (L_check_1);
7198 addl (idx, 0x2);
7199 andl (idx, 0x1);
7200 subl(idx, 1);
7201 jcc(Assembler::negative, L_post_third_loop_done);
7202
7203 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7204 movq(product, x_xstart);
7205 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7206 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7207
7208 add2_with_carry(rdx, product, yz_idx, carry);
7209
7210 movl(Address(z, idx, Address::times_4, 0), product);
7211 shrq(product, 32);
7212
7213 shlq(rdx, 32);
7214 orq(product, rdx);
7215 movq(carry, product);
7216
7217 bind(L_post_third_loop_done);
7218 }
7219
7220 /**
7221 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7222 *
7223 */
7224 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7225 Register carry, Register carry2,
7226 Register idx, Register jdx,
7227 Register yz_idx1, Register yz_idx2,
7228 Register tmp, Register tmp3, Register tmp4) {
7229 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7230
7231 // jlong carry, x[], y[], z[];
7232 // int kdx = ystart+1;
7233 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7234 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7235 // jlong carry2 = (jlong)(tmp3 >>> 64);
7236 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7237 // carry = (jlong)(tmp4 >>> 64);
7238 // z[kdx+idx+1] = (jlong)tmp3;
7239 // z[kdx+idx] = (jlong)tmp4;
7240 // }
7241 // idx += 2;
7242 // if (idx > 0) {
7243 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7244 // z[kdx+idx] = (jlong)yz_idx1;
7245 // carry = (jlong)(yz_idx1 >>> 64);
7246 // }
7247 //
7248
7249 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7250
7251 movl(jdx, idx);
7252 andl(jdx, 0xFFFFFFFC);
7253 shrl(jdx, 2);
7254
7255 bind(L_third_loop);
7256 subl(jdx, 1);
7257 jcc(Assembler::negative, L_third_loop_exit);
7258 subl(idx, 4);
7259
7260 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7261 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7262 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7263 rorxq(yz_idx2, yz_idx2, 32);
7264
7265 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7266 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7267
7268 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7269 rorxq(yz_idx1, yz_idx1, 32);
7270 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7271 rorxq(yz_idx2, yz_idx2, 32);
7272
7273 if (VM_Version::supports_adx()) {
7274 adcxq(tmp3, carry);
7275 adoxq(tmp3, yz_idx1);
7276
7277 adcxq(tmp4, tmp);
7278 adoxq(tmp4, yz_idx2);
7279
7280 movl(carry, 0); // does not affect flags
7281 adcxq(carry2, carry);
7282 adoxq(carry2, carry);
7283 } else {
7284 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7285 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7286 }
7287 movq(carry, carry2);
7288
7289 movl(Address(z, idx, Address::times_4, 12), tmp3);
7290 shrq(tmp3, 32);
7291 movl(Address(z, idx, Address::times_4, 8), tmp3);
7292
7293 movl(Address(z, idx, Address::times_4, 4), tmp4);
7294 shrq(tmp4, 32);
7295 movl(Address(z, idx, Address::times_4, 0), tmp4);
7296
7297 jmp(L_third_loop);
7298
7299 bind (L_third_loop_exit);
7300
7301 andl (idx, 0x3);
7302 jcc(Assembler::zero, L_post_third_loop_done);
7303
7304 Label L_check_1;
7305 subl(idx, 2);
7306 jcc(Assembler::negative, L_check_1);
7307
7308 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7309 rorxq(yz_idx1, yz_idx1, 32);
7310 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7311 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7312 rorxq(yz_idx2, yz_idx2, 32);
7313
7314 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7315
7316 movl(Address(z, idx, Address::times_4, 4), tmp3);
7317 shrq(tmp3, 32);
7318 movl(Address(z, idx, Address::times_4, 0), tmp3);
7319 movq(carry, tmp4);
7320
7321 bind (L_check_1);
7322 addl (idx, 0x2);
7323 andl (idx, 0x1);
7324 subl(idx, 1);
7325 jcc(Assembler::negative, L_post_third_loop_done);
7326 movl(tmp4, Address(y, idx, Address::times_4, 0));
7327 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7328 movl(tmp4, Address(z, idx, Address::times_4, 0));
7329
7330 add2_with_carry(carry2, tmp3, tmp4, carry);
7331
7332 movl(Address(z, idx, Address::times_4, 0), tmp3);
7333 shrq(tmp3, 32);
7334
7335 shlq(carry2, 32);
7336 orq(tmp3, carry2);
7337 movq(carry, tmp3);
7338
7339 bind(L_post_third_loop_done);
7340 }
7341
7342 /**
7343 * Code for BigInteger::multiplyToLen() intrinsic.
7344 *
7345 * rdi: x
7346 * rax: xlen
7347 * rsi: y
7348 * rcx: ylen
7349 * r8: z
7350 * r11: tmp0
7351 * r12: tmp1
7352 * r13: tmp2
7353 * r14: tmp3
7354 * r15: tmp4
7355 * rbx: tmp5
7356 *
7357 */
7358 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7359 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7360 ShortBranchVerifier sbv(this);
7361 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7362
7363 push(tmp0);
7364 push(tmp1);
7365 push(tmp2);
7366 push(tmp3);
7367 push(tmp4);
7368 push(tmp5);
7369
7370 push(xlen);
7371
7372 const Register idx = tmp1;
7373 const Register kdx = tmp2;
7374 const Register xstart = tmp3;
7375
7376 const Register y_idx = tmp4;
7377 const Register carry = tmp5;
7378 const Register product = xlen;
7379 const Register x_xstart = tmp0;
7380
7381 // First Loop.
7382 //
7383 // final static long LONG_MASK = 0xffffffffL;
7384 // int xstart = xlen - 1;
7385 // int ystart = ylen - 1;
7386 // long carry = 0;
7387 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7388 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7389 // z[kdx] = (int)product;
7390 // carry = product >>> 32;
7391 // }
7392 // z[xstart] = (int)carry;
7393 //
7394
7395 movl(idx, ylen); // idx = ylen;
7396 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7397 xorq(carry, carry); // carry = 0;
7398
7399 Label L_done;
7400
7401 movl(xstart, xlen);
7402 decrementl(xstart);
7403 jcc(Assembler::negative, L_done);
7404
7405 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7406
7407 Label L_second_loop;
7408 testl(kdx, kdx);
7409 jcc(Assembler::zero, L_second_loop);
7410
7411 Label L_carry;
7412 subl(kdx, 1);
7413 jcc(Assembler::zero, L_carry);
7414
7415 movl(Address(z, kdx, Address::times_4, 0), carry);
7416 shrq(carry, 32);
7417 subl(kdx, 1);
7418
7419 bind(L_carry);
7420 movl(Address(z, kdx, Address::times_4, 0), carry);
7421
7422 // Second and third (nested) loops.
7423 //
7424 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7425 // carry = 0;
7426 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7427 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7428 // (z[k] & LONG_MASK) + carry;
7429 // z[k] = (int)product;
7430 // carry = product >>> 32;
7431 // }
7432 // z[i] = (int)carry;
7433 // }
7434 //
7435 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7436
7437 const Register jdx = tmp1;
7438
7439 bind(L_second_loop);
7440 xorl(carry, carry); // carry = 0;
7441 movl(jdx, ylen); // j = ystart+1
7442
7443 subl(xstart, 1); // i = xstart-1;
7444 jcc(Assembler::negative, L_done);
7445
7446 push (z);
7447
7448 Label L_last_x;
7449 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7450 subl(xstart, 1); // i = xstart-1;
7451 jcc(Assembler::negative, L_last_x);
7452
7453 if (UseBMI2Instructions) {
7454 movq(rdx, Address(x, xstart, Address::times_4, 0));
7455 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7456 } else {
7457 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7458 rorq(x_xstart, 32); // convert big-endian to little-endian
7459 }
7460
7461 Label L_third_loop_prologue;
7462 bind(L_third_loop_prologue);
7463
7464 push (x);
7465 push (xstart);
7466 push (ylen);
7467
7468
7469 if (UseBMI2Instructions) {
7470 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7471 } else { // !UseBMI2Instructions
7472 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7473 }
7474
7475 pop(ylen);
7476 pop(xlen);
7477 pop(x);
7478 pop(z);
7479
7480 movl(tmp3, xlen);
7481 addl(tmp3, 1);
7482 movl(Address(z, tmp3, Address::times_4, 0), carry);
7483 subl(tmp3, 1);
7484 jccb(Assembler::negative, L_done);
7485
7486 shrq(carry, 32);
7487 movl(Address(z, tmp3, Address::times_4, 0), carry);
7488 jmp(L_second_loop);
7489
7490 // Next infrequent code is moved outside loops.
7491 bind(L_last_x);
7492 if (UseBMI2Instructions) {
7493 movl(rdx, Address(x, 0));
7494 } else {
7495 movl(x_xstart, Address(x, 0));
7496 }
7497 jmp(L_third_loop_prologue);
7498
7499 bind(L_done);
7500
7501 pop(xlen);
7502
7503 pop(tmp5);
7504 pop(tmp4);
7505 pop(tmp3);
7506 pop(tmp2);
7507 pop(tmp1);
7508 pop(tmp0);
7509 }
7510
7511 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7512 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7513 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7514 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7515 Label VECTOR8_TAIL, VECTOR4_TAIL;
7516 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7517 Label SAME_TILL_END, DONE;
7518 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7519
7520 //scale is in rcx in both Win64 and Unix
7521 ShortBranchVerifier sbv(this);
7522
7523 shlq(length);
7524 xorq(result, result);
7525
7526 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7527 VM_Version::supports_avx512vlbw()) {
7528 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7529
7530 cmpq(length, 64);
7531 jcc(Assembler::less, VECTOR32_TAIL);
7532
7533 movq(tmp1, length);
7534 andq(tmp1, 0x3F); // tail count
7535 andq(length, ~(0x3F)); //vector count
7536
7537 bind(VECTOR64_LOOP);
7538 // AVX512 code to compare 64 byte vectors.
7539 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7540 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7541 kortestql(k7, k7);
7542 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7543 addq(result, 64);
7544 subq(length, 64);
7545 jccb(Assembler::notZero, VECTOR64_LOOP);
7546
7547 //bind(VECTOR64_TAIL);
7548 testq(tmp1, tmp1);
7549 jcc(Assembler::zero, SAME_TILL_END);
7550
7551 //bind(VECTOR64_TAIL);
7552 // AVX512 code to compare up to 63 byte vectors.
7553 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7554 shlxq(tmp2, tmp2, tmp1);
7555 notq(tmp2);
7556 kmovql(k3, tmp2);
7557
7558 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7559 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7560
7561 ktestql(k7, k3);
7562 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7563
7564 bind(VECTOR64_NOT_EQUAL);
7565 kmovql(tmp1, k7);
7566 notq(tmp1);
7567 tzcntq(tmp1, tmp1);
7568 addq(result, tmp1);
7569 shrq(result);
7570 jmp(DONE);
7571 bind(VECTOR32_TAIL);
7572 }
7573
7574 cmpq(length, 8);
7575 jcc(Assembler::equal, VECTOR8_LOOP);
7576 jcc(Assembler::less, VECTOR4_TAIL);
7577
7578 if (UseAVX >= 2) {
7579 Label VECTOR16_TAIL, VECTOR32_LOOP;
7580
7581 cmpq(length, 16);
7582 jcc(Assembler::equal, VECTOR16_LOOP);
7583 jcc(Assembler::less, VECTOR8_LOOP);
7584
7585 cmpq(length, 32);
7586 jccb(Assembler::less, VECTOR16_TAIL);
7587
7588 subq(length, 32);
7589 bind(VECTOR32_LOOP);
7590 vmovdqu(rymm0, Address(obja, result));
7591 vmovdqu(rymm1, Address(objb, result));
7592 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7593 vptest(rymm2, rymm2);
7594 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7595 addq(result, 32);
7596 subq(length, 32);
7597 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7598 addq(length, 32);
7599 jcc(Assembler::equal, SAME_TILL_END);
7600 //falling through if less than 32 bytes left //close the branch here.
7601
7602 bind(VECTOR16_TAIL);
7603 cmpq(length, 16);
7604 jccb(Assembler::less, VECTOR8_TAIL);
7605 bind(VECTOR16_LOOP);
7606 movdqu(rymm0, Address(obja, result));
7607 movdqu(rymm1, Address(objb, result));
7608 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7609 ptest(rymm2, rymm2);
7610 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7611 addq(result, 16);
7612 subq(length, 16);
7613 jcc(Assembler::equal, SAME_TILL_END);
7614 //falling through if less than 16 bytes left
7615 } else {//regular intrinsics
7616
7617 cmpq(length, 16);
7618 jccb(Assembler::less, VECTOR8_TAIL);
7619
7620 subq(length, 16);
7621 bind(VECTOR16_LOOP);
7622 movdqu(rymm0, Address(obja, result));
7623 movdqu(rymm1, Address(objb, result));
7624 pxor(rymm0, rymm1);
7625 ptest(rymm0, rymm0);
7626 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7627 addq(result, 16);
7628 subq(length, 16);
7629 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7630 addq(length, 16);
7631 jcc(Assembler::equal, SAME_TILL_END);
7632 //falling through if less than 16 bytes left
7633 }
7634
7635 bind(VECTOR8_TAIL);
7636 cmpq(length, 8);
7637 jccb(Assembler::less, VECTOR4_TAIL);
7638 bind(VECTOR8_LOOP);
7639 movq(tmp1, Address(obja, result));
7640 movq(tmp2, Address(objb, result));
7641 xorq(tmp1, tmp2);
7642 testq(tmp1, tmp1);
7643 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7644 addq(result, 8);
7645 subq(length, 8);
7646 jcc(Assembler::equal, SAME_TILL_END);
7647 //falling through if less than 8 bytes left
7648
7649 bind(VECTOR4_TAIL);
7650 cmpq(length, 4);
7651 jccb(Assembler::less, BYTES_TAIL);
7652 bind(VECTOR4_LOOP);
7653 movl(tmp1, Address(obja, result));
7654 xorl(tmp1, Address(objb, result));
7655 testl(tmp1, tmp1);
7656 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7657 addq(result, 4);
7658 subq(length, 4);
7659 jcc(Assembler::equal, SAME_TILL_END);
7660 //falling through if less than 4 bytes left
7661
7662 bind(BYTES_TAIL);
7663 bind(BYTES_LOOP);
7664 load_unsigned_byte(tmp1, Address(obja, result));
7665 load_unsigned_byte(tmp2, Address(objb, result));
7666 xorl(tmp1, tmp2);
7667 testl(tmp1, tmp1);
7668 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7669 decq(length);
7670 jcc(Assembler::zero, SAME_TILL_END);
7671 incq(result);
7672 load_unsigned_byte(tmp1, Address(obja, result));
7673 load_unsigned_byte(tmp2, Address(objb, result));
7674 xorl(tmp1, tmp2);
7675 testl(tmp1, tmp1);
7676 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7677 decq(length);
7678 jcc(Assembler::zero, SAME_TILL_END);
7679 incq(result);
7680 load_unsigned_byte(tmp1, Address(obja, result));
7681 load_unsigned_byte(tmp2, Address(objb, result));
7682 xorl(tmp1, tmp2);
7683 testl(tmp1, tmp1);
7684 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7685 jmp(SAME_TILL_END);
7686
7687 if (UseAVX >= 2) {
7688 bind(VECTOR32_NOT_EQUAL);
7689 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7690 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7691 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7692 vpmovmskb(tmp1, rymm0);
7693 bsfq(tmp1, tmp1);
7694 addq(result, tmp1);
7695 shrq(result);
7696 jmp(DONE);
7697 }
7698
7699 bind(VECTOR16_NOT_EQUAL);
7700 if (UseAVX >= 2) {
7701 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7702 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7703 pxor(rymm0, rymm2);
7704 } else {
7705 pcmpeqb(rymm2, rymm2);
7706 pxor(rymm0, rymm1);
7707 pcmpeqb(rymm0, rymm1);
7708 pxor(rymm0, rymm2);
7709 }
7710 pmovmskb(tmp1, rymm0);
7711 bsfq(tmp1, tmp1);
7712 addq(result, tmp1);
7713 shrq(result);
7714 jmpb(DONE);
7715
7716 bind(VECTOR8_NOT_EQUAL);
7717 bind(VECTOR4_NOT_EQUAL);
7718 bsfq(tmp1, tmp1);
7719 shrq(tmp1, 3);
7720 addq(result, tmp1);
7721 bind(BYTES_NOT_EQUAL);
7722 shrq(result);
7723 jmpb(DONE);
7724
7725 bind(SAME_TILL_END);
7726 mov64(result, -1);
7727
7728 bind(DONE);
7729 }
7730
7731 //Helper functions for square_to_len()
7732
7733 /**
7734 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7735 * Preserves x and z and modifies rest of the registers.
7736 */
7737 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7738 // Perform square and right shift by 1
7739 // Handle odd xlen case first, then for even xlen do the following
7740 // jlong carry = 0;
7741 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7742 // huge_128 product = x[j:j+1] * x[j:j+1];
7743 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7744 // z[i+2:i+3] = (jlong)(product >>> 1);
7745 // carry = (jlong)product;
7746 // }
7747
7748 xorq(tmp5, tmp5); // carry
7749 xorq(rdxReg, rdxReg);
7750 xorl(tmp1, tmp1); // index for x
7751 xorl(tmp4, tmp4); // index for z
7752
7753 Label L_first_loop, L_first_loop_exit;
7754
7755 testl(xlen, 1);
7756 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7757
7758 // Square and right shift by 1 the odd element using 32 bit multiply
7759 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7760 imulq(raxReg, raxReg);
7761 shrq(raxReg, 1);
7762 adcq(tmp5, 0);
7763 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7764 incrementl(tmp1);
7765 addl(tmp4, 2);
7766
7767 // Square and right shift by 1 the rest using 64 bit multiply
7768 bind(L_first_loop);
7769 cmpptr(tmp1, xlen);
7770 jccb(Assembler::equal, L_first_loop_exit);
7771
7772 // Square
7773 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7774 rorq(raxReg, 32); // convert big-endian to little-endian
7775 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7776
7777 // Right shift by 1 and save carry
7778 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7779 rcrq(rdxReg, 1);
7780 rcrq(raxReg, 1);
7781 adcq(tmp5, 0);
7782
7783 // Store result in z
7784 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7785 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7786
7787 // Update indices for x and z
7788 addl(tmp1, 2);
7789 addl(tmp4, 4);
7790 jmp(L_first_loop);
7791
7792 bind(L_first_loop_exit);
7793 }
7794
7795
7796 /**
7797 * Perform the following multiply add operation using BMI2 instructions
7798 * carry:sum = sum + op1*op2 + carry
7799 * op2 should be in rdx
7800 * op2 is preserved, all other registers are modified
7801 */
7802 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7803 // assert op2 is rdx
7804 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7805 addq(sum, carry);
7806 adcq(tmp2, 0);
7807 addq(sum, op1);
7808 adcq(tmp2, 0);
7809 movq(carry, tmp2);
7810 }
7811
7812 /**
7813 * Perform the following multiply add operation:
7814 * carry:sum = sum + op1*op2 + carry
7815 * Preserves op1, op2 and modifies rest of registers
7816 */
7817 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7818 // rdx:rax = op1 * op2
7819 movq(raxReg, op2);
7820 mulq(op1);
7821
7822 // rdx:rax = sum + carry + rdx:rax
7823 addq(sum, carry);
7824 adcq(rdxReg, 0);
7825 addq(sum, raxReg);
7826 adcq(rdxReg, 0);
7827
7828 // carry:sum = rdx:sum
7829 movq(carry, rdxReg);
7830 }
7831
7832 /**
7833 * Add 64 bit long carry into z[] with carry propagation.
7834 * Preserves z and carry register values and modifies rest of registers.
7835 *
7836 */
7837 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7838 Label L_fourth_loop, L_fourth_loop_exit;
7839
7840 movl(tmp1, 1);
7841 subl(zlen, 2);
7842 addq(Address(z, zlen, Address::times_4, 0), carry);
7843
7844 bind(L_fourth_loop);
7845 jccb(Assembler::carryClear, L_fourth_loop_exit);
7846 subl(zlen, 2);
7847 jccb(Assembler::negative, L_fourth_loop_exit);
7848 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7849 jmp(L_fourth_loop);
7850 bind(L_fourth_loop_exit);
7851 }
7852
7853 /**
7854 * Shift z[] left by 1 bit.
7855 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7856 *
7857 */
7858 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7859
7860 Label L_fifth_loop, L_fifth_loop_exit;
7861
7862 // Fifth loop
7863 // Perform primitiveLeftShift(z, zlen, 1)
7864
7865 const Register prev_carry = tmp1;
7866 const Register new_carry = tmp4;
7867 const Register value = tmp2;
7868 const Register zidx = tmp3;
7869
7870 // int zidx, carry;
7871 // long value;
7872 // carry = 0;
7873 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7874 // (carry:value) = (z[i] << 1) | carry ;
7875 // z[i] = value;
7876 // }
7877
7878 movl(zidx, zlen);
7879 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7880
7881 bind(L_fifth_loop);
7882 decl(zidx); // Use decl to preserve carry flag
7883 decl(zidx);
7884 jccb(Assembler::negative, L_fifth_loop_exit);
7885
7886 if (UseBMI2Instructions) {
7887 movq(value, Address(z, zidx, Address::times_4, 0));
7888 rclq(value, 1);
7889 rorxq(value, value, 32);
7890 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7891 }
7892 else {
7893 // clear new_carry
7894 xorl(new_carry, new_carry);
7895
7896 // Shift z[i] by 1, or in previous carry and save new carry
7897 movq(value, Address(z, zidx, Address::times_4, 0));
7898 shlq(value, 1);
7899 adcl(new_carry, 0);
7900
7901 orq(value, prev_carry);
7902 rorq(value, 0x20);
7903 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7904
7905 // Set previous carry = new carry
7906 movl(prev_carry, new_carry);
7907 }
7908 jmp(L_fifth_loop);
7909
7910 bind(L_fifth_loop_exit);
7911 }
7912
7913
7914 /**
7915 * Code for BigInteger::squareToLen() intrinsic
7916 *
7917 * rdi: x
7918 * rsi: len
7919 * r8: z
7920 * rcx: zlen
7921 * r12: tmp1
7922 * r13: tmp2
7923 * r14: tmp3
7924 * r15: tmp4
7925 * rbx: tmp5
7926 *
7927 */
7928 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7929
7930 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
7931 push(tmp1);
7932 push(tmp2);
7933 push(tmp3);
7934 push(tmp4);
7935 push(tmp5);
7936
7937 // First loop
7938 // Store the squares, right shifted one bit (i.e., divided by 2).
7939 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7940
7941 // Add in off-diagonal sums.
7942 //
7943 // Second, third (nested) and fourth loops.
7944 // zlen +=2;
7945 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7946 // carry = 0;
7947 // long op2 = x[xidx:xidx+1];
7948 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7949 // k -= 2;
7950 // long op1 = x[j:j+1];
7951 // long sum = z[k:k+1];
7952 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7953 // z[k:k+1] = sum;
7954 // }
7955 // add_one_64(z, k, carry, tmp_regs);
7956 // }
7957
7958 const Register carry = tmp5;
7959 const Register sum = tmp3;
7960 const Register op1 = tmp4;
7961 Register op2 = tmp2;
7962
7963 push(zlen);
7964 push(len);
7965 addl(zlen,2);
7966 bind(L_second_loop);
7967 xorq(carry, carry);
7968 subl(zlen, 4);
7969 subl(len, 2);
7970 push(zlen);
7971 push(len);
7972 cmpl(len, 0);
7973 jccb(Assembler::lessEqual, L_second_loop_exit);
7974
7975 // Multiply an array by one 64 bit long.
7976 if (UseBMI2Instructions) {
7977 op2 = rdxReg;
7978 movq(op2, Address(x, len, Address::times_4, 0));
7979 rorxq(op2, op2, 32);
7980 }
7981 else {
7982 movq(op2, Address(x, len, Address::times_4, 0));
7983 rorq(op2, 32);
7984 }
7985
7986 bind(L_third_loop);
7987 decrementl(len);
7988 jccb(Assembler::negative, L_third_loop_exit);
7989 decrementl(len);
7990 jccb(Assembler::negative, L_last_x);
7991
7992 movq(op1, Address(x, len, Address::times_4, 0));
7993 rorq(op1, 32);
7994
7995 bind(L_multiply);
7996 subl(zlen, 2);
7997 movq(sum, Address(z, zlen, Address::times_4, 0));
7998
7999 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8000 if (UseBMI2Instructions) {
8001 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8002 }
8003 else {
8004 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8005 }
8006
8007 movq(Address(z, zlen, Address::times_4, 0), sum);
8008
8009 jmp(L_third_loop);
8010 bind(L_third_loop_exit);
8011
8012 // Fourth loop
8013 // Add 64 bit long carry into z with carry propagation.
8014 // Uses offsetted zlen.
8015 add_one_64(z, zlen, carry, tmp1);
8016
8017 pop(len);
8018 pop(zlen);
8019 jmp(L_second_loop);
8020
8021 // Next infrequent code is moved outside loops.
8022 bind(L_last_x);
8023 movl(op1, Address(x, 0));
8024 jmp(L_multiply);
8025
8026 bind(L_second_loop_exit);
8027 pop(len);
8028 pop(zlen);
8029 pop(len);
8030 pop(zlen);
8031
8032 // Fifth loop
8033 // Shift z left 1 bit.
8034 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8035
8036 // z[zlen-1] |= x[len-1] & 1;
8037 movl(tmp3, Address(x, len, Address::times_4, -4));
8038 andl(tmp3, 1);
8039 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8040
8041 pop(tmp5);
8042 pop(tmp4);
8043 pop(tmp3);
8044 pop(tmp2);
8045 pop(tmp1);
8046 }
8047
8048 /**
8049 * Helper function for mul_add()
8050 * Multiply the in[] by int k and add to out[] starting at offset offs using
8051 * 128 bit by 32 bit multiply and return the carry in tmp5.
8052 * Only quad int aligned length of in[] is operated on in this function.
8053 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8054 * This function preserves out, in and k registers.
8055 * len and offset point to the appropriate index in "in" & "out" correspondingly
8056 * tmp5 has the carry.
8057 * other registers are temporary and are modified.
8058 *
8059 */
8060 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8061 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8062 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8063
8064 Label L_first_loop, L_first_loop_exit;
8065
8066 movl(tmp1, len);
8067 shrl(tmp1, 2);
8068
8069 bind(L_first_loop);
8070 subl(tmp1, 1);
8071 jccb(Assembler::negative, L_first_loop_exit);
8072
8073 subl(len, 4);
8074 subl(offset, 4);
8075
8076 Register op2 = tmp2;
8077 const Register sum = tmp3;
8078 const Register op1 = tmp4;
8079 const Register carry = tmp5;
8080
8081 if (UseBMI2Instructions) {
8082 op2 = rdxReg;
8083 }
8084
8085 movq(op1, Address(in, len, Address::times_4, 8));
8086 rorq(op1, 32);
8087 movq(sum, Address(out, offset, Address::times_4, 8));
8088 rorq(sum, 32);
8089 if (UseBMI2Instructions) {
8090 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8091 }
8092 else {
8093 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8094 }
8095 // Store back in big endian from little endian
8096 rorq(sum, 0x20);
8097 movq(Address(out, offset, Address::times_4, 8), sum);
8098
8099 movq(op1, Address(in, len, Address::times_4, 0));
8100 rorq(op1, 32);
8101 movq(sum, Address(out, offset, Address::times_4, 0));
8102 rorq(sum, 32);
8103 if (UseBMI2Instructions) {
8104 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8105 }
8106 else {
8107 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8108 }
8109 // Store back in big endian from little endian
8110 rorq(sum, 0x20);
8111 movq(Address(out, offset, Address::times_4, 0), sum);
8112
8113 jmp(L_first_loop);
8114 bind(L_first_loop_exit);
8115 }
8116
8117 /**
8118 * Code for BigInteger::mulAdd() intrinsic
8119 *
8120 * rdi: out
8121 * rsi: in
8122 * r11: offs (out.length - offset)
8123 * rcx: len
8124 * r8: k
8125 * r12: tmp1
8126 * r13: tmp2
8127 * r14: tmp3
8128 * r15: tmp4
8129 * rbx: tmp5
8130 * Multiply the in[] by word k and add to out[], return the carry in rax
8131 */
8132 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8133 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8134 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8135
8136 Label L_carry, L_last_in, L_done;
8137
8138 // carry = 0;
8139 // for (int j=len-1; j >= 0; j--) {
8140 // long product = (in[j] & LONG_MASK) * kLong +
8141 // (out[offs] & LONG_MASK) + carry;
8142 // out[offs--] = (int)product;
8143 // carry = product >>> 32;
8144 // }
8145 //
8146 push(tmp1);
8147 push(tmp2);
8148 push(tmp3);
8149 push(tmp4);
8150 push(tmp5);
8151
8152 Register op2 = tmp2;
8153 const Register sum = tmp3;
8154 const Register op1 = tmp4;
8155 const Register carry = tmp5;
8156
8157 if (UseBMI2Instructions) {
8158 op2 = rdxReg;
8159 movl(op2, k);
8160 }
8161 else {
8162 movl(op2, k);
8163 }
8164
8165 xorq(carry, carry);
8166
8167 //First loop
8168
8169 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8170 //The carry is in tmp5
8171 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8172
8173 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8174 decrementl(len);
8175 jccb(Assembler::negative, L_carry);
8176 decrementl(len);
8177 jccb(Assembler::negative, L_last_in);
8178
8179 movq(op1, Address(in, len, Address::times_4, 0));
8180 rorq(op1, 32);
8181
8182 subl(offs, 2);
8183 movq(sum, Address(out, offs, Address::times_4, 0));
8184 rorq(sum, 32);
8185
8186 if (UseBMI2Instructions) {
8187 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8188 }
8189 else {
8190 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8191 }
8192
8193 // Store back in big endian from little endian
8194 rorq(sum, 0x20);
8195 movq(Address(out, offs, Address::times_4, 0), sum);
8196
8197 testl(len, len);
8198 jccb(Assembler::zero, L_carry);
8199
8200 //Multiply the last in[] entry, if any
8201 bind(L_last_in);
8202 movl(op1, Address(in, 0));
8203 movl(sum, Address(out, offs, Address::times_4, -4));
8204
8205 movl(raxReg, k);
8206 mull(op1); //tmp4 * eax -> edx:eax
8207 addl(sum, carry);
8208 adcl(rdxReg, 0);
8209 addl(sum, raxReg);
8210 adcl(rdxReg, 0);
8211 movl(carry, rdxReg);
8212
8213 movl(Address(out, offs, Address::times_4, -4), sum);
8214
8215 bind(L_carry);
8216 //return tmp5/carry as carry in rax
8217 movl(rax, carry);
8218
8219 bind(L_done);
8220 pop(tmp5);
8221 pop(tmp4);
8222 pop(tmp3);
8223 pop(tmp2);
8224 pop(tmp1);
8225 }
8226 #endif
8227
8228 /**
8229 * Emits code to update CRC-32 with a byte value according to constants in table
8230 *
8231 * @param [in,out]crc Register containing the crc.
8232 * @param [in]val Register containing the byte to fold into the CRC.
8233 * @param [in]table Register containing the table of crc constants.
8234 *
8235 * uint32_t crc;
8236 * val = crc_table[(val ^ crc) & 0xFF];
8237 * crc = val ^ (crc >> 8);
8238 *
8239 */
8240 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8241 xorl(val, crc);
8242 andl(val, 0xFF);
8243 shrl(crc, 8); // unsigned shift
8244 xorl(crc, Address(table, val, Address::times_4, 0));
8245 }
8246
8247 /**
8248 * Fold 128-bit data chunk
8249 */
8250 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8251 if (UseAVX > 0) {
8252 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8253 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8254 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8255 pxor(xcrc, xtmp);
8256 } else {
8257 movdqa(xtmp, xcrc);
8258 pclmulhdq(xtmp, xK); // [123:64]
8259 pclmulldq(xcrc, xK); // [63:0]
8260 pxor(xcrc, xtmp);
8261 movdqu(xtmp, Address(buf, offset));
8262 pxor(xcrc, xtmp);
8263 }
8264 }
8265
8266 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8267 if (UseAVX > 0) {
8268 vpclmulhdq(xtmp, xK, xcrc);
8269 vpclmulldq(xcrc, xK, xcrc);
8270 pxor(xcrc, xbuf);
8271 pxor(xcrc, xtmp);
8272 } else {
8273 movdqa(xtmp, xcrc);
8274 pclmulhdq(xtmp, xK);
8275 pclmulldq(xcrc, xK);
8276 pxor(xcrc, xbuf);
8277 pxor(xcrc, xtmp);
8278 }
8279 }
8280
8281 /**
8282 * 8-bit folds to compute 32-bit CRC
8283 *
8284 * uint64_t xcrc;
8285 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8286 */
8287 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8288 movdl(tmp, xcrc);
8289 andl(tmp, 0xFF);
8290 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8291 psrldq(xcrc, 1); // unsigned shift one byte
8292 pxor(xcrc, xtmp);
8293 }
8294
8295 /**
8296 * uint32_t crc;
8297 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8298 */
8299 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8300 movl(tmp, crc);
8301 andl(tmp, 0xFF);
8302 shrl(crc, 8);
8303 xorl(crc, Address(table, tmp, Address::times_4, 0));
8304 }
8305
8306 /**
8307 * @param crc register containing existing CRC (32-bit)
8308 * @param buf register pointing to input byte buffer (byte*)
8309 * @param len register containing number of bytes
8310 * @param table register that will contain address of CRC table
8311 * @param tmp scratch register
8312 */
8313 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8314 assert_different_registers(crc, buf, len, table, tmp, rax);
8315
8316 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8317 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8318
8319 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8320 // context for the registers used, where all instructions below are using 128-bit mode
8321 // On EVEX without VL and BW, these instructions will all be AVX.
8322 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8323 notl(crc); // ~crc
8324 cmpl(len, 16);
8325 jcc(Assembler::less, L_tail);
8326
8327 // Align buffer to 16 bytes
8328 movl(tmp, buf);
8329 andl(tmp, 0xF);
8330 jccb(Assembler::zero, L_aligned);
8331 subl(tmp, 16);
8332 addl(len, tmp);
8333
8334 align(4);
8335 BIND(L_align_loop);
8336 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8337 update_byte_crc32(crc, rax, table);
8338 increment(buf);
8339 incrementl(tmp);
8340 jccb(Assembler::less, L_align_loop);
8341
8342 BIND(L_aligned);
8343 movl(tmp, len); // save
8344 shrl(len, 4);
8345 jcc(Assembler::zero, L_tail_restore);
8346
8347 // Fold crc into first bytes of vector
8348 movdqa(xmm1, Address(buf, 0));
8349 movdl(rax, xmm1);
8350 xorl(crc, rax);
8351 if (VM_Version::supports_sse4_1()) {
8352 pinsrd(xmm1, crc, 0);
8353 } else {
8354 pinsrw(xmm1, crc, 0);
8355 shrl(crc, 16);
8356 pinsrw(xmm1, crc, 1);
8357 }
8358 addptr(buf, 16);
8359 subl(len, 4); // len > 0
8360 jcc(Assembler::less, L_fold_tail);
8361
8362 movdqa(xmm2, Address(buf, 0));
8363 movdqa(xmm3, Address(buf, 16));
8364 movdqa(xmm4, Address(buf, 32));
8365 addptr(buf, 48);
8366 subl(len, 3);
8367 jcc(Assembler::lessEqual, L_fold_512b);
8368
8369 // Fold total 512 bits of polynomial on each iteration,
8370 // 128 bits per each of 4 parallel streams.
8371 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8372
8373 align32();
8374 BIND(L_fold_512b_loop);
8375 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8376 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8377 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8378 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8379 addptr(buf, 64);
8380 subl(len, 4);
8381 jcc(Assembler::greater, L_fold_512b_loop);
8382
8383 // Fold 512 bits to 128 bits.
8384 BIND(L_fold_512b);
8385 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8386 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8387 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8388 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8389
8390 // Fold the rest of 128 bits data chunks
8391 BIND(L_fold_tail);
8392 addl(len, 3);
8393 jccb(Assembler::lessEqual, L_fold_128b);
8394 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8395
8396 BIND(L_fold_tail_loop);
8397 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8398 addptr(buf, 16);
8399 decrementl(len);
8400 jccb(Assembler::greater, L_fold_tail_loop);
8401
8402 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8403 BIND(L_fold_128b);
8404 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8405 if (UseAVX > 0) {
8406 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8407 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8408 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8409 } else {
8410 movdqa(xmm2, xmm0);
8411 pclmulqdq(xmm2, xmm1, 0x1);
8412 movdqa(xmm3, xmm0);
8413 pand(xmm3, xmm2);
8414 pclmulqdq(xmm0, xmm3, 0x1);
8415 }
8416 psrldq(xmm1, 8);
8417 psrldq(xmm2, 4);
8418 pxor(xmm0, xmm1);
8419 pxor(xmm0, xmm2);
8420
8421 // 8 8-bit folds to compute 32-bit CRC.
8422 for (int j = 0; j < 4; j++) {
8423 fold_8bit_crc32(xmm0, table, xmm1, rax);
8424 }
8425 movdl(crc, xmm0); // mov 32 bits to general register
8426 for (int j = 0; j < 4; j++) {
8427 fold_8bit_crc32(crc, table, rax);
8428 }
8429
8430 BIND(L_tail_restore);
8431 movl(len, tmp); // restore
8432 BIND(L_tail);
8433 andl(len, 0xf);
8434 jccb(Assembler::zero, L_exit);
8435
8436 // Fold the rest of bytes
8437 align(4);
8438 BIND(L_tail_loop);
8439 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8440 update_byte_crc32(crc, rax, table);
8441 increment(buf);
8442 decrementl(len);
8443 jccb(Assembler::greater, L_tail_loop);
8444
8445 BIND(L_exit);
8446 notl(crc); // ~c
8447 }
8448
8449 #ifdef _LP64
8450 // Helper function for AVX 512 CRC32
8451 // Fold 512-bit data chunks
8452 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8453 Register pos, int offset) {
8454 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8455 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8456 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8457 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8458 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8459 }
8460
8461 // Helper function for AVX 512 CRC32
8462 // Compute CRC32 for < 256B buffers
8463 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8464 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8465 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8466
8467 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8468 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8469 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8470
8471 // check if there is enough buffer to be able to fold 16B at a time
8472 cmpl(len, 32);
8473 jcc(Assembler::less, L_less_than_32);
8474
8475 // if there is, load the constants
8476 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8477 movdl(xmm0, crc); // get the initial crc value
8478 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8479 pxor(xmm7, xmm0);
8480
8481 // update the buffer pointer
8482 addl(pos, 16);
8483 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8484 subl(len, 32);
8485 jmp(L_16B_reduction_loop);
8486
8487 bind(L_less_than_32);
8488 //mov initial crc to the return value. this is necessary for zero - length buffers.
8489 movl(rax, crc);
8490 testl(len, len);
8491 jcc(Assembler::equal, L_cleanup);
8492
8493 movdl(xmm0, crc); //get the initial crc value
8494
8495 cmpl(len, 16);
8496 jcc(Assembler::equal, L_exact_16_left);
8497 jcc(Assembler::less, L_less_than_16_left);
8498
8499 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8500 pxor(xmm7, xmm0); //xor the initial crc value
8501 addl(pos, 16);
8502 subl(len, 16);
8503 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8504 jmp(L_get_last_two_xmms);
8505
8506 bind(L_less_than_16_left);
8507 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8508 pxor(xmm1, xmm1);
8509 movptr(tmp1, rsp);
8510 movdqu(Address(tmp1, 0 * 16), xmm1);
8511
8512 cmpl(len, 4);
8513 jcc(Assembler::less, L_only_less_than_4);
8514
8515 //backup the counter value
8516 movl(tmp2, len);
8517 cmpl(len, 8);
8518 jcc(Assembler::less, L_less_than_8_left);
8519
8520 //load 8 Bytes
8521 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8522 movq(Address(tmp1, 0 * 16), rax);
8523 addptr(tmp1, 8);
8524 subl(len, 8);
8525 addl(pos, 8);
8526
8527 bind(L_less_than_8_left);
8528 cmpl(len, 4);
8529 jcc(Assembler::less, L_less_than_4_left);
8530
8531 //load 4 Bytes
8532 movl(rax, Address(buf, pos, Address::times_1, 0));
8533 movl(Address(tmp1, 0 * 16), rax);
8534 addptr(tmp1, 4);
8535 subl(len, 4);
8536 addl(pos, 4);
8537
8538 bind(L_less_than_4_left);
8539 cmpl(len, 2);
8540 jcc(Assembler::less, L_less_than_2_left);
8541
8542 // load 2 Bytes
8543 movw(rax, Address(buf, pos, Address::times_1, 0));
8544 movl(Address(tmp1, 0 * 16), rax);
8545 addptr(tmp1, 2);
8546 subl(len, 2);
8547 addl(pos, 2);
8548
8549 bind(L_less_than_2_left);
8550 cmpl(len, 1);
8551 jcc(Assembler::less, L_zero_left);
8552
8553 // load 1 Byte
8554 movb(rax, Address(buf, pos, Address::times_1, 0));
8555 movb(Address(tmp1, 0 * 16), rax);
8556
8557 bind(L_zero_left);
8558 movdqu(xmm7, Address(rsp, 0));
8559 pxor(xmm7, xmm0); //xor the initial crc value
8560
8561 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8562 movdqu(xmm0, Address(rax, tmp2));
8563 pshufb(xmm7, xmm0);
8564 jmp(L_128_done);
8565
8566 bind(L_exact_16_left);
8567 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8568 pxor(xmm7, xmm0); //xor the initial crc value
8569 jmp(L_128_done);
8570
8571 bind(L_only_less_than_4);
8572 cmpl(len, 3);
8573 jcc(Assembler::less, L_only_less_than_3);
8574
8575 // load 3 Bytes
8576 movb(rax, Address(buf, pos, Address::times_1, 0));
8577 movb(Address(tmp1, 0), rax);
8578
8579 movb(rax, Address(buf, pos, Address::times_1, 1));
8580 movb(Address(tmp1, 1), rax);
8581
8582 movb(rax, Address(buf, pos, Address::times_1, 2));
8583 movb(Address(tmp1, 2), rax);
8584
8585 movdqu(xmm7, Address(rsp, 0));
8586 pxor(xmm7, xmm0); //xor the initial crc value
8587
8588 pslldq(xmm7, 0x5);
8589 jmp(L_barrett);
8590 bind(L_only_less_than_3);
8591 cmpl(len, 2);
8592 jcc(Assembler::less, L_only_less_than_2);
8593
8594 // load 2 Bytes
8595 movb(rax, Address(buf, pos, Address::times_1, 0));
8596 movb(Address(tmp1, 0), rax);
8597
8598 movb(rax, Address(buf, pos, Address::times_1, 1));
8599 movb(Address(tmp1, 1), rax);
8600
8601 movdqu(xmm7, Address(rsp, 0));
8602 pxor(xmm7, xmm0); //xor the initial crc value
8603
8604 pslldq(xmm7, 0x6);
8605 jmp(L_barrett);
8606
8607 bind(L_only_less_than_2);
8608 //load 1 Byte
8609 movb(rax, Address(buf, pos, Address::times_1, 0));
8610 movb(Address(tmp1, 0), rax);
8611
8612 movdqu(xmm7, Address(rsp, 0));
8613 pxor(xmm7, xmm0); //xor the initial crc value
8614
8615 pslldq(xmm7, 0x7);
8616 }
8617
8618 /**
8619 * Compute CRC32 using AVX512 instructions
8620 * param crc register containing existing CRC (32-bit)
8621 * param buf register pointing to input byte buffer (byte*)
8622 * param len register containing number of bytes
8623 * param table address of crc or crc32c table
8624 * param tmp1 scratch register
8625 * param tmp2 scratch register
8626 * return rax result register
8627 *
8628 * This routine is identical for crc32c with the exception of the precomputed constant
8629 * table which will be passed as the table argument. The calculation steps are
8630 * the same for both variants.
8631 */
8632 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8633 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8634
8635 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8636 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8637 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8638 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8639 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8640
8641 const Register pos = r12;
8642 push(r12);
8643 subptr(rsp, 16 * 2 + 8);
8644
8645 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8646 // context for the registers used, where all instructions below are using 128-bit mode
8647 // On EVEX without VL and BW, these instructions will all be AVX.
8648 movl(pos, 0);
8649
8650 // check if smaller than 256B
8651 cmpl(len, 256);
8652 jcc(Assembler::less, L_less_than_256);
8653
8654 // load the initial crc value
8655 movdl(xmm10, crc);
8656
8657 // receive the initial 64B data, xor the initial crc value
8658 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8659 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8660 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8661 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8662
8663 subl(len, 256);
8664 cmpl(len, 256);
8665 jcc(Assembler::less, L_fold_128_B_loop);
8666
8667 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8668 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8669 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8670 subl(len, 256);
8671
8672 bind(L_fold_256_B_loop);
8673 addl(pos, 256);
8674 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8675 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8676 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8677 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8678
8679 subl(len, 256);
8680 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8681
8682 // Fold 256 into 128
8683 addl(pos, 256);
8684 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8685 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8686 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8687
8688 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8689 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8690 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8691
8692 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8693 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8694
8695 addl(len, 128);
8696 jmp(L_fold_128_B_register);
8697
8698 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8699 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8700
8701 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8702 bind(L_fold_128_B_loop);
8703 addl(pos, 128);
8704 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8705 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8706
8707 subl(len, 128);
8708 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8709
8710 addl(pos, 128);
8711
8712 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8713 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8714 bind(L_fold_128_B_register);
8715 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8716 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8717 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8718 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8719 // save last that has no multiplicand
8720 vextracti64x2(xmm7, xmm4, 3);
8721
8722 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8723 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8724 // Needed later in reduction loop
8725 movdqu(xmm10, Address(table, 1 * 16));
8726 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8727 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8728
8729 // Swap 1,0,3,2 - 01 00 11 10
8730 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8731 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8732 vextracti128(xmm5, xmm8, 1);
8733 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8734
8735 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8736 // instead of a cmp instruction, we use the negative flag with the jl instruction
8737 addl(len, 128 - 16);
8738 jcc(Assembler::less, L_final_reduction_for_128);
8739
8740 bind(L_16B_reduction_loop);
8741 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8742 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8743 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8744 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8745 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8746 addl(pos, 16);
8747 subl(len, 16);
8748 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8749
8750 bind(L_final_reduction_for_128);
8751 addl(len, 16);
8752 jcc(Assembler::equal, L_128_done);
8753
8754 bind(L_get_last_two_xmms);
8755 movdqu(xmm2, xmm7);
8756 addl(pos, len);
8757 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8758 subl(pos, len);
8759
8760 // get rid of the extra data that was loaded before
8761 // load the shift constant
8762 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8763 movdqu(xmm0, Address(rax, len));
8764 addl(rax, len);
8765
8766 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8767 //Change mask to 512
8768 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8769 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8770
8771 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8772 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8773 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8774 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8775 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8776
8777 bind(L_128_done);
8778 // compute crc of a 128-bit value
8779 movdqu(xmm10, Address(table, 3 * 16));
8780 movdqu(xmm0, xmm7);
8781
8782 // 64b fold
8783 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8784 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8785 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8786
8787 // 32b fold
8788 movdqu(xmm0, xmm7);
8789 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8790 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8791 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8792 jmp(L_barrett);
8793
8794 bind(L_less_than_256);
8795 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8796
8797 //barrett reduction
8798 bind(L_barrett);
8799 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8800 movdqu(xmm1, xmm7);
8801 movdqu(xmm2, xmm7);
8802 movdqu(xmm10, Address(table, 4 * 16));
8803
8804 pclmulqdq(xmm7, xmm10, 0x0);
8805 pxor(xmm7, xmm2);
8806 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8807 movdqu(xmm2, xmm7);
8808 pclmulqdq(xmm7, xmm10, 0x10);
8809 pxor(xmm7, xmm2);
8810 pxor(xmm7, xmm1);
8811 pextrd(crc, xmm7, 2);
8812
8813 bind(L_cleanup);
8814 addptr(rsp, 16 * 2 + 8);
8815 pop(r12);
8816 }
8817
8818 // S. Gueron / Information Processing Letters 112 (2012) 184
8819 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8820 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8821 // Output: the 64-bit carry-less product of B * CONST
8822 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8823 Register tmp1, Register tmp2, Register tmp3) {
8824 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8825 if (n > 0) {
8826 addq(tmp3, n * 256 * 8);
8827 }
8828 // Q1 = TABLEExt[n][B & 0xFF];
8829 movl(tmp1, in);
8830 andl(tmp1, 0x000000FF);
8831 shll(tmp1, 3);
8832 addq(tmp1, tmp3);
8833 movq(tmp1, Address(tmp1, 0));
8834
8835 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8836 movl(tmp2, in);
8837 shrl(tmp2, 8);
8838 andl(tmp2, 0x000000FF);
8839 shll(tmp2, 3);
8840 addq(tmp2, tmp3);
8841 movq(tmp2, Address(tmp2, 0));
8842
8843 shlq(tmp2, 8);
8844 xorq(tmp1, tmp2);
8845
8846 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8847 movl(tmp2, in);
8848 shrl(tmp2, 16);
8849 andl(tmp2, 0x000000FF);
8850 shll(tmp2, 3);
8851 addq(tmp2, tmp3);
8852 movq(tmp2, Address(tmp2, 0));
8853
8854 shlq(tmp2, 16);
8855 xorq(tmp1, tmp2);
8856
8857 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8858 shrl(in, 24);
8859 andl(in, 0x000000FF);
8860 shll(in, 3);
8861 addq(in, tmp3);
8862 movq(in, Address(in, 0));
8863
8864 shlq(in, 24);
8865 xorq(in, tmp1);
8866 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8867 }
8868
8869 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8870 Register in_out,
8871 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8872 XMMRegister w_xtmp2,
8873 Register tmp1,
8874 Register n_tmp2, Register n_tmp3) {
8875 if (is_pclmulqdq_supported) {
8876 movdl(w_xtmp1, in_out); // modified blindly
8877
8878 movl(tmp1, const_or_pre_comp_const_index);
8879 movdl(w_xtmp2, tmp1);
8880 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8881
8882 movdq(in_out, w_xtmp1);
8883 } else {
8884 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8885 }
8886 }
8887
8888 // Recombination Alternative 2: No bit-reflections
8889 // T1 = (CRC_A * U1) << 1
8890 // T2 = (CRC_B * U2) << 1
8891 // C1 = T1 >> 32
8892 // C2 = T2 >> 32
8893 // T1 = T1 & 0xFFFFFFFF
8894 // T2 = T2 & 0xFFFFFFFF
8895 // T1 = CRC32(0, T1)
8896 // T2 = CRC32(0, T2)
8897 // C1 = C1 ^ T1
8898 // C2 = C2 ^ T2
8899 // CRC = C1 ^ C2 ^ CRC_C
8900 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8901 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8902 Register tmp1, Register tmp2,
8903 Register n_tmp3) {
8904 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8905 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8906 shlq(in_out, 1);
8907 movl(tmp1, in_out);
8908 shrq(in_out, 32);
8909 xorl(tmp2, tmp2);
8910 crc32(tmp2, tmp1, 4);
8911 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8912 shlq(in1, 1);
8913 movl(tmp1, in1);
8914 shrq(in1, 32);
8915 xorl(tmp2, tmp2);
8916 crc32(tmp2, tmp1, 4);
8917 xorl(in1, tmp2);
8918 xorl(in_out, in1);
8919 xorl(in_out, in2);
8920 }
8921
8922 // Set N to predefined value
8923 // Subtract from a length of a buffer
8924 // execute in a loop:
8925 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8926 // for i = 1 to N do
8927 // CRC_A = CRC32(CRC_A, A[i])
8928 // CRC_B = CRC32(CRC_B, B[i])
8929 // CRC_C = CRC32(CRC_C, C[i])
8930 // end for
8931 // Recombine
8932 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8933 Register in_out1, Register in_out2, Register in_out3,
8934 Register tmp1, Register tmp2, Register tmp3,
8935 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8936 Register tmp4, Register tmp5,
8937 Register n_tmp6) {
8938 Label L_processPartitions;
8939 Label L_processPartition;
8940 Label L_exit;
8941
8942 bind(L_processPartitions);
8943 cmpl(in_out1, 3 * size);
8944 jcc(Assembler::less, L_exit);
8945 xorl(tmp1, tmp1);
8946 xorl(tmp2, tmp2);
8947 movq(tmp3, in_out2);
8948 addq(tmp3, size);
8949
8950 bind(L_processPartition);
8951 crc32(in_out3, Address(in_out2, 0), 8);
8952 crc32(tmp1, Address(in_out2, size), 8);
8953 crc32(tmp2, Address(in_out2, size * 2), 8);
8954 addq(in_out2, 8);
8955 cmpq(in_out2, tmp3);
8956 jcc(Assembler::less, L_processPartition);
8957 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8958 w_xtmp1, w_xtmp2, w_xtmp3,
8959 tmp4, tmp5,
8960 n_tmp6);
8961 addq(in_out2, 2 * size);
8962 subl(in_out1, 3 * size);
8963 jmp(L_processPartitions);
8964
8965 bind(L_exit);
8966 }
8967 #else
8968 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
8969 Register tmp1, Register tmp2, Register tmp3,
8970 XMMRegister xtmp1, XMMRegister xtmp2) {
8971 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8972 if (n > 0) {
8973 addl(tmp3, n * 256 * 8);
8974 }
8975 // Q1 = TABLEExt[n][B & 0xFF];
8976 movl(tmp1, in_out);
8977 andl(tmp1, 0x000000FF);
8978 shll(tmp1, 3);
8979 addl(tmp1, tmp3);
8980 movq(xtmp1, Address(tmp1, 0));
8981
8982 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8983 movl(tmp2, in_out);
8984 shrl(tmp2, 8);
8985 andl(tmp2, 0x000000FF);
8986 shll(tmp2, 3);
8987 addl(tmp2, tmp3);
8988 movq(xtmp2, Address(tmp2, 0));
8989
8990 psllq(xtmp2, 8);
8991 pxor(xtmp1, xtmp2);
8992
8993 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8994 movl(tmp2, in_out);
8995 shrl(tmp2, 16);
8996 andl(tmp2, 0x000000FF);
8997 shll(tmp2, 3);
8998 addl(tmp2, tmp3);
8999 movq(xtmp2, Address(tmp2, 0));
9000
9001 psllq(xtmp2, 16);
9002 pxor(xtmp1, xtmp2);
9003
9004 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9005 shrl(in_out, 24);
9006 andl(in_out, 0x000000FF);
9007 shll(in_out, 3);
9008 addl(in_out, tmp3);
9009 movq(xtmp2, Address(in_out, 0));
9010
9011 psllq(xtmp2, 24);
9012 pxor(xtmp1, xtmp2); // Result in CXMM
9013 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9014 }
9015
9016 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9017 Register in_out,
9018 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9019 XMMRegister w_xtmp2,
9020 Register tmp1,
9021 Register n_tmp2, Register n_tmp3) {
9022 if (is_pclmulqdq_supported) {
9023 movdl(w_xtmp1, in_out);
9024
9025 movl(tmp1, const_or_pre_comp_const_index);
9026 movdl(w_xtmp2, tmp1);
9027 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9028 // Keep result in XMM since GPR is 32 bit in length
9029 } else {
9030 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
9031 }
9032 }
9033
9034 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9035 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9036 Register tmp1, Register tmp2,
9037 Register n_tmp3) {
9038 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9039 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9040
9041 psllq(w_xtmp1, 1);
9042 movdl(tmp1, w_xtmp1);
9043 psrlq(w_xtmp1, 32);
9044 movdl(in_out, w_xtmp1);
9045
9046 xorl(tmp2, tmp2);
9047 crc32(tmp2, tmp1, 4);
9048 xorl(in_out, tmp2);
9049
9050 psllq(w_xtmp2, 1);
9051 movdl(tmp1, w_xtmp2);
9052 psrlq(w_xtmp2, 32);
9053 movdl(in1, w_xtmp2);
9054
9055 xorl(tmp2, tmp2);
9056 crc32(tmp2, tmp1, 4);
9057 xorl(in1, tmp2);
9058 xorl(in_out, in1);
9059 xorl(in_out, in2);
9060 }
9061
9062 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9063 Register in_out1, Register in_out2, Register in_out3,
9064 Register tmp1, Register tmp2, Register tmp3,
9065 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9066 Register tmp4, Register tmp5,
9067 Register n_tmp6) {
9068 Label L_processPartitions;
9069 Label L_processPartition;
9070 Label L_exit;
9071
9072 bind(L_processPartitions);
9073 cmpl(in_out1, 3 * size);
9074 jcc(Assembler::less, L_exit);
9075 xorl(tmp1, tmp1);
9076 xorl(tmp2, tmp2);
9077 movl(tmp3, in_out2);
9078 addl(tmp3, size);
9079
9080 bind(L_processPartition);
9081 crc32(in_out3, Address(in_out2, 0), 4);
9082 crc32(tmp1, Address(in_out2, size), 4);
9083 crc32(tmp2, Address(in_out2, size*2), 4);
9084 crc32(in_out3, Address(in_out2, 0+4), 4);
9085 crc32(tmp1, Address(in_out2, size+4), 4);
9086 crc32(tmp2, Address(in_out2, size*2+4), 4);
9087 addl(in_out2, 8);
9088 cmpl(in_out2, tmp3);
9089 jcc(Assembler::less, L_processPartition);
9090
9091 push(tmp3);
9092 push(in_out1);
9093 push(in_out2);
9094 tmp4 = tmp3;
9095 tmp5 = in_out1;
9096 n_tmp6 = in_out2;
9097
9098 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9099 w_xtmp1, w_xtmp2, w_xtmp3,
9100 tmp4, tmp5,
9101 n_tmp6);
9102
9103 pop(in_out2);
9104 pop(in_out1);
9105 pop(tmp3);
9106
9107 addl(in_out2, 2 * size);
9108 subl(in_out1, 3 * size);
9109 jmp(L_processPartitions);
9110
9111 bind(L_exit);
9112 }
9113 #endif //LP64
9114
9115 #ifdef _LP64
9116 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9117 // Input: A buffer I of L bytes.
9118 // Output: the CRC32C value of the buffer.
9119 // Notations:
9120 // Write L = 24N + r, with N = floor (L/24).
9121 // r = L mod 24 (0 <= r < 24).
9122 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9123 // N quadwords, and R consists of r bytes.
9124 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9125 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9126 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9127 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9128 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9129 Register tmp1, Register tmp2, Register tmp3,
9130 Register tmp4, Register tmp5, Register tmp6,
9131 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9132 bool is_pclmulqdq_supported) {
9133 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9134 Label L_wordByWord;
9135 Label L_byteByByteProlog;
9136 Label L_byteByByte;
9137 Label L_exit;
9138
9139 if (is_pclmulqdq_supported ) {
9140 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9141 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
9142
9143 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9144 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9145
9146 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9147 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9148 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9149 } else {
9150 const_or_pre_comp_const_index[0] = 1;
9151 const_or_pre_comp_const_index[1] = 0;
9152
9153 const_or_pre_comp_const_index[2] = 3;
9154 const_or_pre_comp_const_index[3] = 2;
9155
9156 const_or_pre_comp_const_index[4] = 5;
9157 const_or_pre_comp_const_index[5] = 4;
9158 }
9159 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9160 in2, in1, in_out,
9161 tmp1, tmp2, tmp3,
9162 w_xtmp1, w_xtmp2, w_xtmp3,
9163 tmp4, tmp5,
9164 tmp6);
9165 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9166 in2, in1, in_out,
9167 tmp1, tmp2, tmp3,
9168 w_xtmp1, w_xtmp2, w_xtmp3,
9169 tmp4, tmp5,
9170 tmp6);
9171 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9172 in2, in1, in_out,
9173 tmp1, tmp2, tmp3,
9174 w_xtmp1, w_xtmp2, w_xtmp3,
9175 tmp4, tmp5,
9176 tmp6);
9177 movl(tmp1, in2);
9178 andl(tmp1, 0x00000007);
9179 negl(tmp1);
9180 addl(tmp1, in2);
9181 addq(tmp1, in1);
9182
9183 cmpq(in1, tmp1);
9184 jccb(Assembler::greaterEqual, L_byteByByteProlog);
9185 align(16);
9186 BIND(L_wordByWord);
9187 crc32(in_out, Address(in1, 0), 8);
9188 addq(in1, 8);
9189 cmpq(in1, tmp1);
9190 jcc(Assembler::less, L_wordByWord);
9191
9192 BIND(L_byteByByteProlog);
9193 andl(in2, 0x00000007);
9194 movl(tmp2, 1);
9195
9196 cmpl(tmp2, in2);
9197 jccb(Assembler::greater, L_exit);
9198 BIND(L_byteByByte);
9199 crc32(in_out, Address(in1, 0), 1);
9200 incq(in1);
9201 incl(tmp2);
9202 cmpl(tmp2, in2);
9203 jcc(Assembler::lessEqual, L_byteByByte);
9204
9205 BIND(L_exit);
9206 }
9207 #else
9208 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9209 Register tmp1, Register tmp2, Register tmp3,
9210 Register tmp4, Register tmp5, Register tmp6,
9211 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9212 bool is_pclmulqdq_supported) {
9213 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9214 Label L_wordByWord;
9215 Label L_byteByByteProlog;
9216 Label L_byteByByte;
9217 Label L_exit;
9218
9219 if (is_pclmulqdq_supported) {
9220 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9221 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
9222
9223 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9224 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9225
9226 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9227 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9228 } else {
9229 const_or_pre_comp_const_index[0] = 1;
9230 const_or_pre_comp_const_index[1] = 0;
9231
9232 const_or_pre_comp_const_index[2] = 3;
9233 const_or_pre_comp_const_index[3] = 2;
9234
9235 const_or_pre_comp_const_index[4] = 5;
9236 const_or_pre_comp_const_index[5] = 4;
9237 }
9238 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9239 in2, in1, in_out,
9240 tmp1, tmp2, tmp3,
9241 w_xtmp1, w_xtmp2, w_xtmp3,
9242 tmp4, tmp5,
9243 tmp6);
9244 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9245 in2, in1, in_out,
9246 tmp1, tmp2, tmp3,
9247 w_xtmp1, w_xtmp2, w_xtmp3,
9248 tmp4, tmp5,
9249 tmp6);
9250 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9251 in2, in1, in_out,
9252 tmp1, tmp2, tmp3,
9253 w_xtmp1, w_xtmp2, w_xtmp3,
9254 tmp4, tmp5,
9255 tmp6);
9256 movl(tmp1, in2);
9257 andl(tmp1, 0x00000007);
9258 negl(tmp1);
9259 addl(tmp1, in2);
9260 addl(tmp1, in1);
9261
9262 BIND(L_wordByWord);
9263 cmpl(in1, tmp1);
9264 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9265 crc32(in_out, Address(in1,0), 4);
9266 addl(in1, 4);
9267 jmp(L_wordByWord);
9268
9269 BIND(L_byteByByteProlog);
9270 andl(in2, 0x00000007);
9271 movl(tmp2, 1);
9272
9273 BIND(L_byteByByte);
9274 cmpl(tmp2, in2);
9275 jccb(Assembler::greater, L_exit);
9276 movb(tmp1, Address(in1, 0));
9277 crc32(in_out, tmp1, 1);
9278 incl(in1);
9279 incl(tmp2);
9280 jmp(L_byteByByte);
9281
9282 BIND(L_exit);
9283 }
9284 #endif // LP64
9285 #undef BIND
9286 #undef BLOCK_COMMENT
9287
9288 // Compress char[] array to byte[].
9289 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
9290 // Return the array length if every element in array can be encoded,
9291 // otherwise, the index of first non-latin1 (> 0xff) character.
9292 // @IntrinsicCandidate
9293 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9294 // for (int i = 0; i < len; i++) {
9295 // char c = src[srcOff];
9296 // if (c > 0xff) {
9297 // return i; // return index of non-latin1 char
9298 // }
9299 // dst[dstOff] = (byte)c;
9300 // srcOff++;
9301 // dstOff++;
9302 // }
9303 // return len;
9304 // }
9305 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9306 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9307 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9308 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9309 Label copy_chars_loop, done, reset_sp, copy_tail;
9310
9311 // rsi: src
9312 // rdi: dst
9313 // rdx: len
9314 // rcx: tmp5
9315 // rax: result
9316
9317 // rsi holds start addr of source char[] to be compressed
9318 // rdi holds start addr of destination byte[]
9319 // rdx holds length
9320
9321 assert(len != result, "");
9322
9323 // save length for return
9324 movl(result, len);
9325
9326 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9327 VM_Version::supports_avx512vlbw() &&
9328 VM_Version::supports_bmi2()) {
9329
9330 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9331
9332 // alignment
9333 Label post_alignment;
9334
9335 // if length of the string is less than 32, handle it the old fashioned way
9336 testl(len, -32);
9337 jcc(Assembler::zero, below_threshold);
9338
9339 // First check whether a character is compressible ( <= 0xFF).
9340 // Create mask to test for Unicode chars inside zmm vector
9341 movl(tmp5, 0x00FF);
9342 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9343
9344 testl(len, -64);
9345 jccb(Assembler::zero, post_alignment);
9346
9347 movl(tmp5, dst);
9348 andl(tmp5, (32 - 1));
9349 negl(tmp5);
9350 andl(tmp5, (32 - 1));
9351
9352 // bail out when there is nothing to be done
9353 testl(tmp5, 0xFFFFFFFF);
9354 jccb(Assembler::zero, post_alignment);
9355
9356 // ~(~0 << len), where len is the # of remaining elements to process
9357 movl(len, 0xFFFFFFFF);
9358 shlxl(len, len, tmp5);
9359 notl(len);
9360 kmovdl(mask2, len);
9361 movl(len, result);
9362
9363 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9364 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9365 ktestd(mask1, mask2);
9366 jcc(Assembler::carryClear, copy_tail);
9367
9368 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9369
9370 addptr(src, tmp5);
9371 addptr(src, tmp5);
9372 addptr(dst, tmp5);
9373 subl(len, tmp5);
9374
9375 bind(post_alignment);
9376 // end of alignment
9377
9378 movl(tmp5, len);
9379 andl(tmp5, (32 - 1)); // tail count (in chars)
9380 andl(len, ~(32 - 1)); // vector count (in chars)
9381 jccb(Assembler::zero, copy_loop_tail);
9382
9383 lea(src, Address(src, len, Address::times_2));
9384 lea(dst, Address(dst, len, Address::times_1));
9385 negptr(len);
9386
9387 bind(copy_32_loop);
9388 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9389 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9390 kortestdl(mask1, mask1);
9391 jccb(Assembler::carryClear, reset_for_copy_tail);
9392
9393 // All elements in current processed chunk are valid candidates for
9394 // compression. Write a truncated byte elements to the memory.
9395 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9396 addptr(len, 32);
9397 jccb(Assembler::notZero, copy_32_loop);
9398
9399 bind(copy_loop_tail);
9400 // bail out when there is nothing to be done
9401 testl(tmp5, 0xFFFFFFFF);
9402 jcc(Assembler::zero, done);
9403
9404 movl(len, tmp5);
9405
9406 // ~(~0 << len), where len is the # of remaining elements to process
9407 movl(tmp5, 0xFFFFFFFF);
9408 shlxl(tmp5, tmp5, len);
9409 notl(tmp5);
9410
9411 kmovdl(mask2, tmp5);
9412
9413 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9414 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9415 ktestd(mask1, mask2);
9416 jcc(Assembler::carryClear, copy_tail);
9417
9418 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9419 jmp(done);
9420
9421 bind(reset_for_copy_tail);
9422 lea(src, Address(src, tmp5, Address::times_2));
9423 lea(dst, Address(dst, tmp5, Address::times_1));
9424 subptr(len, tmp5);
9425 jmp(copy_chars_loop);
9426
9427 bind(below_threshold);
9428 }
9429
9430 if (UseSSE42Intrinsics) {
9431 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9432
9433 // vectored compression
9434 testl(len, 0xfffffff8);
9435 jcc(Assembler::zero, copy_tail);
9436
9437 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9438 movdl(tmp1Reg, tmp5);
9439 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9440
9441 andl(len, 0xfffffff0);
9442 jccb(Assembler::zero, copy_16);
9443
9444 // compress 16 chars per iter
9445 pxor(tmp4Reg, tmp4Reg);
9446
9447 lea(src, Address(src, len, Address::times_2));
9448 lea(dst, Address(dst, len, Address::times_1));
9449 negptr(len);
9450
9451 bind(copy_32_loop);
9452 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9453 por(tmp4Reg, tmp2Reg);
9454 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9455 por(tmp4Reg, tmp3Reg);
9456 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9457 jccb(Assembler::notZero, reset_for_copy_tail);
9458 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9459 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9460 addptr(len, 16);
9461 jccb(Assembler::notZero, copy_32_loop);
9462
9463 // compress next vector of 8 chars (if any)
9464 bind(copy_16);
9465 // len = 0
9466 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9467 jccb(Assembler::zero, copy_tail_sse);
9468
9469 pxor(tmp3Reg, tmp3Reg);
9470
9471 movdqu(tmp2Reg, Address(src, 0));
9472 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9473 jccb(Assembler::notZero, reset_for_copy_tail);
9474 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9475 movq(Address(dst, 0), tmp2Reg);
9476 addptr(src, 16);
9477 addptr(dst, 8);
9478 jmpb(copy_tail_sse);
9479
9480 bind(reset_for_copy_tail);
9481 movl(tmp5, result);
9482 andl(tmp5, 0x0000000f);
9483 lea(src, Address(src, tmp5, Address::times_2));
9484 lea(dst, Address(dst, tmp5, Address::times_1));
9485 subptr(len, tmp5);
9486 jmpb(copy_chars_loop);
9487
9488 bind(copy_tail_sse);
9489 movl(len, result);
9490 andl(len, 0x00000007); // tail count (in chars)
9491 }
9492 // compress 1 char per iter
9493 bind(copy_tail);
9494 testl(len, len);
9495 jccb(Assembler::zero, done);
9496 lea(src, Address(src, len, Address::times_2));
9497 lea(dst, Address(dst, len, Address::times_1));
9498 negptr(len);
9499
9500 bind(copy_chars_loop);
9501 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9502 testl(tmp5, 0xff00); // check if Unicode char
9503 jccb(Assembler::notZero, reset_sp);
9504 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9505 increment(len);
9506 jccb(Assembler::notZero, copy_chars_loop);
9507
9508 // add len then return (len will be zero if compress succeeded, otherwise negative)
9509 bind(reset_sp);
9510 addl(result, len);
9511
9512 bind(done);
9513 }
9514
9515 // Inflate byte[] array to char[].
9516 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9517 // @IntrinsicCandidate
9518 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9519 // for (int i = 0; i < len; i++) {
9520 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9521 // }
9522 // }
9523 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9524 XMMRegister tmp1, Register tmp2, KRegister mask) {
9525 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9526 // rsi: src
9527 // rdi: dst
9528 // rdx: len
9529 // rcx: tmp2
9530
9531 // rsi holds start addr of source byte[] to be inflated
9532 // rdi holds start addr of destination char[]
9533 // rdx holds length
9534 assert_different_registers(src, dst, len, tmp2);
9535 movl(tmp2, len);
9536 if ((UseAVX > 2) && // AVX512
9537 VM_Version::supports_avx512vlbw() &&
9538 VM_Version::supports_bmi2()) {
9539
9540 Label copy_32_loop, copy_tail;
9541 Register tmp3_aliased = len;
9542
9543 // if length of the string is less than 16, handle it in an old fashioned way
9544 testl(len, -16);
9545 jcc(Assembler::zero, below_threshold);
9546
9547 testl(len, -1 * AVX3Threshold);
9548 jcc(Assembler::zero, avx3_threshold);
9549
9550 // In order to use only one arithmetic operation for the main loop we use
9551 // this pre-calculation
9552 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9553 andl(len, -32); // vector count
9554 jccb(Assembler::zero, copy_tail);
9555
9556 lea(src, Address(src, len, Address::times_1));
9557 lea(dst, Address(dst, len, Address::times_2));
9558 negptr(len);
9559
9560
9561 // inflate 32 chars per iter
9562 bind(copy_32_loop);
9563 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9564 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9565 addptr(len, 32);
9566 jcc(Assembler::notZero, copy_32_loop);
9567
9568 bind(copy_tail);
9569 // bail out when there is nothing to be done
9570 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9571 jcc(Assembler::zero, done);
9572
9573 // ~(~0 << length), where length is the # of remaining elements to process
9574 movl(tmp3_aliased, -1);
9575 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9576 notl(tmp3_aliased);
9577 kmovdl(mask, tmp3_aliased);
9578 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9579 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9580
9581 jmp(done);
9582 bind(avx3_threshold);
9583 }
9584 if (UseSSE42Intrinsics) {
9585 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9586
9587 if (UseAVX > 1) {
9588 andl(tmp2, (16 - 1));
9589 andl(len, -16);
9590 jccb(Assembler::zero, copy_new_tail);
9591 } else {
9592 andl(tmp2, 0x00000007); // tail count (in chars)
9593 andl(len, 0xfffffff8); // vector count (in chars)
9594 jccb(Assembler::zero, copy_tail);
9595 }
9596
9597 // vectored inflation
9598 lea(src, Address(src, len, Address::times_1));
9599 lea(dst, Address(dst, len, Address::times_2));
9600 negptr(len);
9601
9602 if (UseAVX > 1) {
9603 bind(copy_16_loop);
9604 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9605 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9606 addptr(len, 16);
9607 jcc(Assembler::notZero, copy_16_loop);
9608
9609 bind(below_threshold);
9610 bind(copy_new_tail);
9611 movl(len, tmp2);
9612 andl(tmp2, 0x00000007);
9613 andl(len, 0xFFFFFFF8);
9614 jccb(Assembler::zero, copy_tail);
9615
9616 pmovzxbw(tmp1, Address(src, 0));
9617 movdqu(Address(dst, 0), tmp1);
9618 addptr(src, 8);
9619 addptr(dst, 2 * 8);
9620
9621 jmp(copy_tail, true);
9622 }
9623
9624 // inflate 8 chars per iter
9625 bind(copy_8_loop);
9626 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9627 movdqu(Address(dst, len, Address::times_2), tmp1);
9628 addptr(len, 8);
9629 jcc(Assembler::notZero, copy_8_loop);
9630
9631 bind(copy_tail);
9632 movl(len, tmp2);
9633
9634 cmpl(len, 4);
9635 jccb(Assembler::less, copy_bytes);
9636
9637 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9638 pmovzxbw(tmp1, tmp1);
9639 movq(Address(dst, 0), tmp1);
9640 subptr(len, 4);
9641 addptr(src, 4);
9642 addptr(dst, 8);
9643
9644 bind(copy_bytes);
9645 } else {
9646 bind(below_threshold);
9647 }
9648
9649 testl(len, len);
9650 jccb(Assembler::zero, done);
9651 lea(src, Address(src, len, Address::times_1));
9652 lea(dst, Address(dst, len, Address::times_2));
9653 negptr(len);
9654
9655 // inflate 1 char per iter
9656 bind(copy_chars_loop);
9657 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9658 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9659 increment(len);
9660 jcc(Assembler::notZero, copy_chars_loop);
9661
9662 bind(done);
9663 }
9664
9665 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
9666 switch(type) {
9667 case T_BYTE:
9668 case T_BOOLEAN:
9669 evmovdqub(dst, kmask, src, merge, vector_len);
9670 break;
9671 case T_CHAR:
9672 case T_SHORT:
9673 evmovdquw(dst, kmask, src, merge, vector_len);
9674 break;
9675 case T_INT:
9676 case T_FLOAT:
9677 evmovdqul(dst, kmask, src, merge, vector_len);
9678 break;
9679 case T_LONG:
9680 case T_DOUBLE:
9681 evmovdquq(dst, kmask, src, merge, vector_len);
9682 break;
9683 default:
9684 fatal("Unexpected type argument %s", type2name(type));
9685 break;
9686 }
9687 }
9688
9689
9690 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9691 switch(type) {
9692 case T_BYTE:
9693 case T_BOOLEAN:
9694 evmovdqub(dst, kmask, src, merge, vector_len);
9695 break;
9696 case T_CHAR:
9697 case T_SHORT:
9698 evmovdquw(dst, kmask, src, merge, vector_len);
9699 break;
9700 case T_INT:
9701 case T_FLOAT:
9702 evmovdqul(dst, kmask, src, merge, vector_len);
9703 break;
9704 case T_LONG:
9705 case T_DOUBLE:
9706 evmovdquq(dst, kmask, src, merge, vector_len);
9707 break;
9708 default:
9709 fatal("Unexpected type argument %s", type2name(type));
9710 break;
9711 }
9712 }
9713
9714 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9715 switch(type) {
9716 case T_BYTE:
9717 case T_BOOLEAN:
9718 evmovdqub(dst, kmask, src, merge, vector_len);
9719 break;
9720 case T_CHAR:
9721 case T_SHORT:
9722 evmovdquw(dst, kmask, src, merge, vector_len);
9723 break;
9724 case T_INT:
9725 case T_FLOAT:
9726 evmovdqul(dst, kmask, src, merge, vector_len);
9727 break;
9728 case T_LONG:
9729 case T_DOUBLE:
9730 evmovdquq(dst, kmask, src, merge, vector_len);
9731 break;
9732 default:
9733 fatal("Unexpected type argument %s", type2name(type));
9734 break;
9735 }
9736 }
9737
9738 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9739 switch(masklen) {
9740 case 2:
9741 knotbl(dst, src);
9742 movl(rtmp, 3);
9743 kmovbl(ktmp, rtmp);
9744 kandbl(dst, ktmp, dst);
9745 break;
9746 case 4:
9747 knotbl(dst, src);
9748 movl(rtmp, 15);
9749 kmovbl(ktmp, rtmp);
9750 kandbl(dst, ktmp, dst);
9751 break;
9752 case 8:
9753 knotbl(dst, src);
9754 break;
9755 case 16:
9756 knotwl(dst, src);
9757 break;
9758 case 32:
9759 knotdl(dst, src);
9760 break;
9761 case 64:
9762 knotql(dst, src);
9763 break;
9764 default:
9765 fatal("Unexpected vector length %d", masklen);
9766 break;
9767 }
9768 }
9769
9770 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9771 switch(type) {
9772 case T_BOOLEAN:
9773 case T_BYTE:
9774 kandbl(dst, src1, src2);
9775 break;
9776 case T_CHAR:
9777 case T_SHORT:
9778 kandwl(dst, src1, src2);
9779 break;
9780 case T_INT:
9781 case T_FLOAT:
9782 kanddl(dst, src1, src2);
9783 break;
9784 case T_LONG:
9785 case T_DOUBLE:
9786 kandql(dst, src1, src2);
9787 break;
9788 default:
9789 fatal("Unexpected type argument %s", type2name(type));
9790 break;
9791 }
9792 }
9793
9794 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9795 switch(type) {
9796 case T_BOOLEAN:
9797 case T_BYTE:
9798 korbl(dst, src1, src2);
9799 break;
9800 case T_CHAR:
9801 case T_SHORT:
9802 korwl(dst, src1, src2);
9803 break;
9804 case T_INT:
9805 case T_FLOAT:
9806 kordl(dst, src1, src2);
9807 break;
9808 case T_LONG:
9809 case T_DOUBLE:
9810 korql(dst, src1, src2);
9811 break;
9812 default:
9813 fatal("Unexpected type argument %s", type2name(type));
9814 break;
9815 }
9816 }
9817
9818 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9819 switch(type) {
9820 case T_BOOLEAN:
9821 case T_BYTE:
9822 kxorbl(dst, src1, src2);
9823 break;
9824 case T_CHAR:
9825 case T_SHORT:
9826 kxorwl(dst, src1, src2);
9827 break;
9828 case T_INT:
9829 case T_FLOAT:
9830 kxordl(dst, src1, src2);
9831 break;
9832 case T_LONG:
9833 case T_DOUBLE:
9834 kxorql(dst, src1, src2);
9835 break;
9836 default:
9837 fatal("Unexpected type argument %s", type2name(type));
9838 break;
9839 }
9840 }
9841
9842 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9843 switch(type) {
9844 case T_BOOLEAN:
9845 case T_BYTE:
9846 evpermb(dst, mask, nds, src, merge, vector_len); break;
9847 case T_CHAR:
9848 case T_SHORT:
9849 evpermw(dst, mask, nds, src, merge, vector_len); break;
9850 case T_INT:
9851 case T_FLOAT:
9852 evpermd(dst, mask, nds, src, merge, vector_len); break;
9853 case T_LONG:
9854 case T_DOUBLE:
9855 evpermq(dst, mask, nds, src, merge, vector_len); break;
9856 default:
9857 fatal("Unexpected type argument %s", type2name(type)); break;
9858 }
9859 }
9860
9861 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9862 switch(type) {
9863 case T_BOOLEAN:
9864 case T_BYTE:
9865 evpermb(dst, mask, nds, src, merge, vector_len); break;
9866 case T_CHAR:
9867 case T_SHORT:
9868 evpermw(dst, mask, nds, src, merge, vector_len); break;
9869 case T_INT:
9870 case T_FLOAT:
9871 evpermd(dst, mask, nds, src, merge, vector_len); break;
9872 case T_LONG:
9873 case T_DOUBLE:
9874 evpermq(dst, mask, nds, src, merge, vector_len); break;
9875 default:
9876 fatal("Unexpected type argument %s", type2name(type)); break;
9877 }
9878 }
9879
9880 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9881 switch(type) {
9882 case T_BYTE:
9883 evpminub(dst, mask, nds, src, merge, vector_len); break;
9884 case T_SHORT:
9885 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9886 case T_INT:
9887 evpminud(dst, mask, nds, src, merge, vector_len); break;
9888 case T_LONG:
9889 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9890 default:
9891 fatal("Unexpected type argument %s", type2name(type)); break;
9892 }
9893 }
9894
9895 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9896 switch(type) {
9897 case T_BYTE:
9898 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9899 case T_SHORT:
9900 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9901 case T_INT:
9902 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9903 case T_LONG:
9904 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9905 default:
9906 fatal("Unexpected type argument %s", type2name(type)); break;
9907 }
9908 }
9909
9910 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9911 switch(type) {
9912 case T_BYTE:
9913 evpminub(dst, mask, nds, src, merge, vector_len); break;
9914 case T_SHORT:
9915 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9916 case T_INT:
9917 evpminud(dst, mask, nds, src, merge, vector_len); break;
9918 case T_LONG:
9919 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9920 default:
9921 fatal("Unexpected type argument %s", type2name(type)); break;
9922 }
9923 }
9924
9925 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9926 switch(type) {
9927 case T_BYTE:
9928 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9929 case T_SHORT:
9930 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9931 case T_INT:
9932 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9933 case T_LONG:
9934 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9935 default:
9936 fatal("Unexpected type argument %s", type2name(type)); break;
9937 }
9938 }
9939
9940 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9941 switch(type) {
9942 case T_BYTE:
9943 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9944 case T_SHORT:
9945 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9946 case T_INT:
9947 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9948 case T_LONG:
9949 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9950 default:
9951 fatal("Unexpected type argument %s", type2name(type)); break;
9952 }
9953 }
9954
9955 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9956 switch(type) {
9957 case T_BYTE:
9958 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9959 case T_SHORT:
9960 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9961 case T_INT:
9962 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9963 case T_LONG:
9964 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9965 default:
9966 fatal("Unexpected type argument %s", type2name(type)); break;
9967 }
9968 }
9969
9970 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9971 switch(type) {
9972 case T_BYTE:
9973 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9974 case T_SHORT:
9975 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9976 case T_INT:
9977 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9978 case T_LONG:
9979 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9980 default:
9981 fatal("Unexpected type argument %s", type2name(type)); break;
9982 }
9983 }
9984
9985 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9986 switch(type) {
9987 case T_BYTE:
9988 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9989 case T_SHORT:
9990 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9991 case T_INT:
9992 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9993 case T_LONG:
9994 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9995 default:
9996 fatal("Unexpected type argument %s", type2name(type)); break;
9997 }
9998 }
9999
10000 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10001 switch(type) {
10002 case T_INT:
10003 evpxord(dst, mask, nds, src, merge, vector_len); break;
10004 case T_LONG:
10005 evpxorq(dst, mask, nds, src, merge, vector_len); break;
10006 default:
10007 fatal("Unexpected type argument %s", type2name(type)); break;
10008 }
10009 }
10010
10011 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10012 switch(type) {
10013 case T_INT:
10014 evpxord(dst, mask, nds, src, merge, vector_len); break;
10015 case T_LONG:
10016 evpxorq(dst, mask, nds, src, merge, vector_len); break;
10017 default:
10018 fatal("Unexpected type argument %s", type2name(type)); break;
10019 }
10020 }
10021
10022 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10023 switch(type) {
10024 case T_INT:
10025 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10026 case T_LONG:
10027 evporq(dst, mask, nds, src, merge, vector_len); break;
10028 default:
10029 fatal("Unexpected type argument %s", type2name(type)); break;
10030 }
10031 }
10032
10033 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10034 switch(type) {
10035 case T_INT:
10036 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10037 case T_LONG:
10038 evporq(dst, mask, nds, src, merge, vector_len); break;
10039 default:
10040 fatal("Unexpected type argument %s", type2name(type)); break;
10041 }
10042 }
10043
10044 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10045 switch(type) {
10046 case T_INT:
10047 evpandd(dst, mask, nds, src, merge, vector_len); break;
10048 case T_LONG:
10049 evpandq(dst, mask, nds, src, merge, vector_len); break;
10050 default:
10051 fatal("Unexpected type argument %s", type2name(type)); break;
10052 }
10053 }
10054
10055 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10056 switch(type) {
10057 case T_INT:
10058 evpandd(dst, mask, nds, src, merge, vector_len); break;
10059 case T_LONG:
10060 evpandq(dst, mask, nds, src, merge, vector_len); break;
10061 default:
10062 fatal("Unexpected type argument %s", type2name(type)); break;
10063 }
10064 }
10065
10066 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
10067 switch(masklen) {
10068 case 8:
10069 kortestbl(src1, src2);
10070 break;
10071 case 16:
10072 kortestwl(src1, src2);
10073 break;
10074 case 32:
10075 kortestdl(src1, src2);
10076 break;
10077 case 64:
10078 kortestql(src1, src2);
10079 break;
10080 default:
10081 fatal("Unexpected mask length %d", masklen);
10082 break;
10083 }
10084 }
10085
10086
10087 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
10088 switch(masklen) {
10089 case 8:
10090 ktestbl(src1, src2);
10091 break;
10092 case 16:
10093 ktestwl(src1, src2);
10094 break;
10095 case 32:
10096 ktestdl(src1, src2);
10097 break;
10098 case 64:
10099 ktestql(src1, src2);
10100 break;
10101 default:
10102 fatal("Unexpected mask length %d", masklen);
10103 break;
10104 }
10105 }
10106
10107 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10108 switch(type) {
10109 case T_INT:
10110 evprold(dst, mask, src, shift, merge, vlen_enc); break;
10111 case T_LONG:
10112 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
10113 default:
10114 fatal("Unexpected type argument %s", type2name(type)); break;
10115 break;
10116 }
10117 }
10118
10119 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10120 switch(type) {
10121 case T_INT:
10122 evprord(dst, mask, src, shift, merge, vlen_enc); break;
10123 case T_LONG:
10124 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
10125 default:
10126 fatal("Unexpected type argument %s", type2name(type)); break;
10127 }
10128 }
10129
10130 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10131 switch(type) {
10132 case T_INT:
10133 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
10134 case T_LONG:
10135 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
10136 default:
10137 fatal("Unexpected type argument %s", type2name(type)); break;
10138 }
10139 }
10140
10141 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10142 switch(type) {
10143 case T_INT:
10144 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
10145 case T_LONG:
10146 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
10147 default:
10148 fatal("Unexpected type argument %s", type2name(type)); break;
10149 }
10150 }
10151
10152 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10153 assert(rscratch != noreg || always_reachable(src), "missing");
10154
10155 if (reachable(src)) {
10156 evpandq(dst, nds, as_Address(src), vector_len);
10157 } else {
10158 lea(rscratch, src);
10159 evpandq(dst, nds, Address(rscratch, 0), vector_len);
10160 }
10161 }
10162
10163 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
10164 assert(rscratch != noreg || always_reachable(src), "missing");
10165
10166 if (reachable(src)) {
10167 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
10168 } else {
10169 lea(rscratch, src);
10170 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
10171 }
10172 }
10173
10174 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10175 assert(rscratch != noreg || always_reachable(src), "missing");
10176
10177 if (reachable(src)) {
10178 evporq(dst, nds, as_Address(src), vector_len);
10179 } else {
10180 lea(rscratch, src);
10181 evporq(dst, nds, Address(rscratch, 0), vector_len);
10182 }
10183 }
10184
10185 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10186 assert(rscratch != noreg || always_reachable(src), "missing");
10187
10188 if (reachable(src)) {
10189 vpshufb(dst, nds, as_Address(src), vector_len);
10190 } else {
10191 lea(rscratch, src);
10192 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
10193 }
10194 }
10195
10196 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10197 assert(rscratch != noreg || always_reachable(src), "missing");
10198
10199 if (reachable(src)) {
10200 Assembler::vpor(dst, nds, as_Address(src), vector_len);
10201 } else {
10202 lea(rscratch, src);
10203 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
10204 }
10205 }
10206
10207 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
10208 assert(rscratch != noreg || always_reachable(src3), "missing");
10209
10210 if (reachable(src3)) {
10211 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
10212 } else {
10213 lea(rscratch, src3);
10214 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
10215 }
10216 }
10217
10218 #if COMPILER2_OR_JVMCI
10219
10220 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
10221 Register length, Register temp, int vec_enc) {
10222 // Computing mask for predicated vector store.
10223 movptr(temp, -1);
10224 bzhiq(temp, temp, length);
10225 kmov(mask, temp);
10226 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
10227 }
10228
10229 // Set memory operation for length "less than" 64 bytes.
10230 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
10231 XMMRegister xmm, KRegister mask, Register length,
10232 Register temp, bool use64byteVector) {
10233 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10234 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10235 if (!use64byteVector) {
10236 fill32(dst, disp, xmm);
10237 subptr(length, 32 >> shift);
10238 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
10239 } else {
10240 assert(MaxVectorSize == 64, "vector length != 64");
10241 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
10242 }
10243 }
10244
10245
10246 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
10247 XMMRegister xmm, KRegister mask, Register length,
10248 Register temp) {
10249 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10250 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10251 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
10252 }
10253
10254
10255 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
10256 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10257 vmovdqu(dst, xmm);
10258 }
10259
10260 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
10261 fill32(Address(dst, disp), xmm);
10262 }
10263
10264 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
10265 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10266 if (!use64byteVector) {
10267 fill32(dst, xmm);
10268 fill32(dst.plus_disp(32), xmm);
10269 } else {
10270 evmovdquq(dst, xmm, Assembler::AVX_512bit);
10271 }
10272 }
10273
10274 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
10275 fill64(Address(dst, disp), xmm, use64byteVector);
10276 }
10277
10278 #ifdef _LP64
10279 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
10280 Register count, Register rtmp, XMMRegister xtmp) {
10281 Label L_exit;
10282 Label L_fill_start;
10283 Label L_fill_64_bytes;
10284 Label L_fill_96_bytes;
10285 Label L_fill_128_bytes;
10286 Label L_fill_128_bytes_loop;
10287 Label L_fill_128_loop_header;
10288 Label L_fill_128_bytes_loop_header;
10289 Label L_fill_128_bytes_loop_pre_header;
10290 Label L_fill_zmm_sequence;
10291
10292 int shift = -1;
10293 int avx3threshold = VM_Version::avx3_threshold();
10294 switch(type) {
10295 case T_BYTE: shift = 0;
10296 break;
10297 case T_SHORT: shift = 1;
10298 break;
10299 case T_INT: shift = 2;
10300 break;
10301 /* Uncomment when LONG fill stubs are supported.
10302 case T_LONG: shift = 3;
10303 break;
10304 */
10305 default:
10306 fatal("Unhandled type: %s\n", type2name(type));
10307 }
10308
10309 if ((avx3threshold != 0) || (MaxVectorSize == 32)) {
10310
10311 if (MaxVectorSize == 64) {
10312 cmpq(count, avx3threshold >> shift);
10313 jcc(Assembler::greater, L_fill_zmm_sequence);
10314 }
10315
10316 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
10317
10318 bind(L_fill_start);
10319
10320 cmpq(count, 32 >> shift);
10321 jccb(Assembler::greater, L_fill_64_bytes);
10322 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
10323 jmp(L_exit);
10324
10325 bind(L_fill_64_bytes);
10326 cmpq(count, 64 >> shift);
10327 jccb(Assembler::greater, L_fill_96_bytes);
10328 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10329 jmp(L_exit);
10330
10331 bind(L_fill_96_bytes);
10332 cmpq(count, 96 >> shift);
10333 jccb(Assembler::greater, L_fill_128_bytes);
10334 fill64(to, 0, xtmp);
10335 subq(count, 64 >> shift);
10336 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10337 jmp(L_exit);
10338
10339 bind(L_fill_128_bytes);
10340 cmpq(count, 128 >> shift);
10341 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10342 fill64(to, 0, xtmp);
10343 fill32(to, 64, xtmp);
10344 subq(count, 96 >> shift);
10345 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10346 jmp(L_exit);
10347
10348 bind(L_fill_128_bytes_loop_pre_header);
10349 {
10350 mov(rtmp, to);
10351 andq(rtmp, 31);
10352 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10353 negq(rtmp);
10354 addq(rtmp, 32);
10355 mov64(r8, -1L);
10356 bzhiq(r8, r8, rtmp);
10357 kmovql(k2, r8);
10358 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10359 addq(to, rtmp);
10360 shrq(rtmp, shift);
10361 subq(count, rtmp);
10362 }
10363
10364 cmpq(count, 128 >> shift);
10365 jcc(Assembler::less, L_fill_start);
10366
10367 bind(L_fill_128_bytes_loop_header);
10368 subq(count, 128 >> shift);
10369
10370 align32();
10371 bind(L_fill_128_bytes_loop);
10372 fill64(to, 0, xtmp);
10373 fill64(to, 64, xtmp);
10374 addq(to, 128);
10375 subq(count, 128 >> shift);
10376 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10377
10378 addq(count, 128 >> shift);
10379 jcc(Assembler::zero, L_exit);
10380 jmp(L_fill_start);
10381 }
10382
10383 if (MaxVectorSize == 64) {
10384 // Sequence using 64 byte ZMM register.
10385 Label L_fill_128_bytes_zmm;
10386 Label L_fill_192_bytes_zmm;
10387 Label L_fill_192_bytes_loop_zmm;
10388 Label L_fill_192_bytes_loop_header_zmm;
10389 Label L_fill_192_bytes_loop_pre_header_zmm;
10390 Label L_fill_start_zmm_sequence;
10391
10392 bind(L_fill_zmm_sequence);
10393 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10394
10395 bind(L_fill_start_zmm_sequence);
10396 cmpq(count, 64 >> shift);
10397 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10398 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10399 jmp(L_exit);
10400
10401 bind(L_fill_128_bytes_zmm);
10402 cmpq(count, 128 >> shift);
10403 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10404 fill64(to, 0, xtmp, true);
10405 subq(count, 64 >> shift);
10406 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10407 jmp(L_exit);
10408
10409 bind(L_fill_192_bytes_zmm);
10410 cmpq(count, 192 >> shift);
10411 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10412 fill64(to, 0, xtmp, true);
10413 fill64(to, 64, xtmp, true);
10414 subq(count, 128 >> shift);
10415 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10416 jmp(L_exit);
10417
10418 bind(L_fill_192_bytes_loop_pre_header_zmm);
10419 {
10420 movq(rtmp, to);
10421 andq(rtmp, 63);
10422 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10423 negq(rtmp);
10424 addq(rtmp, 64);
10425 mov64(r8, -1L);
10426 bzhiq(r8, r8, rtmp);
10427 kmovql(k2, r8);
10428 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10429 addq(to, rtmp);
10430 shrq(rtmp, shift);
10431 subq(count, rtmp);
10432 }
10433
10434 cmpq(count, 192 >> shift);
10435 jcc(Assembler::less, L_fill_start_zmm_sequence);
10436
10437 bind(L_fill_192_bytes_loop_header_zmm);
10438 subq(count, 192 >> shift);
10439
10440 align32();
10441 bind(L_fill_192_bytes_loop_zmm);
10442 fill64(to, 0, xtmp, true);
10443 fill64(to, 64, xtmp, true);
10444 fill64(to, 128, xtmp, true);
10445 addq(to, 192);
10446 subq(count, 192 >> shift);
10447 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10448
10449 addq(count, 192 >> shift);
10450 jcc(Assembler::zero, L_exit);
10451 jmp(L_fill_start_zmm_sequence);
10452 }
10453 bind(L_exit);
10454 }
10455 #endif
10456 #endif //COMPILER2_OR_JVMCI
10457
10458
10459 #ifdef _LP64
10460 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10461 Label done;
10462 cvttss2sil(dst, src);
10463 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10464 cmpl(dst, 0x80000000); // float_sign_flip
10465 jccb(Assembler::notEqual, done);
10466 subptr(rsp, 8);
10467 movflt(Address(rsp, 0), src);
10468 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10469 pop(dst);
10470 bind(done);
10471 }
10472
10473 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10474 Label done;
10475 cvttsd2sil(dst, src);
10476 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10477 cmpl(dst, 0x80000000); // float_sign_flip
10478 jccb(Assembler::notEqual, done);
10479 subptr(rsp, 8);
10480 movdbl(Address(rsp, 0), src);
10481 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10482 pop(dst);
10483 bind(done);
10484 }
10485
10486 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10487 Label done;
10488 cvttss2siq(dst, src);
10489 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10490 jccb(Assembler::notEqual, done);
10491 subptr(rsp, 8);
10492 movflt(Address(rsp, 0), src);
10493 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10494 pop(dst);
10495 bind(done);
10496 }
10497
10498 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10499 // Following code is line by line assembly translation rounding algorithm.
10500 // Please refer to java.lang.Math.round(float) algorithm for details.
10501 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10502 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10503 const int32_t FloatConsts_EXP_BIAS = 127;
10504 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10505 const int32_t MINUS_32 = 0xFFFFFFE0;
10506 Label L_special_case, L_block1, L_exit;
10507 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10508 movdl(dst, src);
10509 andl(dst, rtmp);
10510 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10511 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10512 subl(rtmp, dst);
10513 movl(rcx, rtmp);
10514 movl(dst, MINUS_32);
10515 testl(rtmp, dst);
10516 jccb(Assembler::notEqual, L_special_case);
10517 movdl(dst, src);
10518 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10519 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10520 movdl(rtmp, src);
10521 testl(rtmp, rtmp);
10522 jccb(Assembler::greaterEqual, L_block1);
10523 negl(dst);
10524 bind(L_block1);
10525 sarl(dst);
10526 addl(dst, 0x1);
10527 sarl(dst, 0x1);
10528 jmp(L_exit);
10529 bind(L_special_case);
10530 convert_f2i(dst, src);
10531 bind(L_exit);
10532 }
10533
10534 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10535 // Following code is line by line assembly translation rounding algorithm.
10536 // Please refer to java.lang.Math.round(double) algorithm for details.
10537 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10538 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10539 const int64_t DoubleConsts_EXP_BIAS = 1023;
10540 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10541 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10542 Label L_special_case, L_block1, L_exit;
10543 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10544 movq(dst, src);
10545 andq(dst, rtmp);
10546 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10547 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10548 subq(rtmp, dst);
10549 movq(rcx, rtmp);
10550 mov64(dst, MINUS_64);
10551 testq(rtmp, dst);
10552 jccb(Assembler::notEqual, L_special_case);
10553 movq(dst, src);
10554 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10555 andq(dst, rtmp);
10556 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10557 orq(dst, rtmp);
10558 movq(rtmp, src);
10559 testq(rtmp, rtmp);
10560 jccb(Assembler::greaterEqual, L_block1);
10561 negq(dst);
10562 bind(L_block1);
10563 sarq(dst);
10564 addq(dst, 0x1);
10565 sarq(dst, 0x1);
10566 jmp(L_exit);
10567 bind(L_special_case);
10568 convert_d2l(dst, src);
10569 bind(L_exit);
10570 }
10571
10572 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10573 Label done;
10574 cvttsd2siq(dst, src);
10575 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10576 jccb(Assembler::notEqual, done);
10577 subptr(rsp, 8);
10578 movdbl(Address(rsp, 0), src);
10579 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10580 pop(dst);
10581 bind(done);
10582 }
10583
10584 void MacroAssembler::cache_wb(Address line)
10585 {
10586 // 64 bit cpus always support clflush
10587 assert(VM_Version::supports_clflush(), "clflush should be available");
10588 bool optimized = VM_Version::supports_clflushopt();
10589 bool no_evict = VM_Version::supports_clwb();
10590
10591 // prefer clwb (writeback without evict) otherwise
10592 // prefer clflushopt (potentially parallel writeback with evict)
10593 // otherwise fallback on clflush (serial writeback with evict)
10594
10595 if (optimized) {
10596 if (no_evict) {
10597 clwb(line);
10598 } else {
10599 clflushopt(line);
10600 }
10601 } else {
10602 // no need for fence when using CLFLUSH
10603 clflush(line);
10604 }
10605 }
10606
10607 void MacroAssembler::cache_wbsync(bool is_pre)
10608 {
10609 assert(VM_Version::supports_clflush(), "clflush should be available");
10610 bool optimized = VM_Version::supports_clflushopt();
10611 bool no_evict = VM_Version::supports_clwb();
10612
10613 // pick the correct implementation
10614
10615 if (!is_pre && (optimized || no_evict)) {
10616 // need an sfence for post flush when using clflushopt or clwb
10617 // otherwise no no need for any synchroniaztion
10618
10619 sfence();
10620 }
10621 }
10622
10623 #endif // _LP64
10624
10625 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10626 switch (cond) {
10627 // Note some conditions are synonyms for others
10628 case Assembler::zero: return Assembler::notZero;
10629 case Assembler::notZero: return Assembler::zero;
10630 case Assembler::less: return Assembler::greaterEqual;
10631 case Assembler::lessEqual: return Assembler::greater;
10632 case Assembler::greater: return Assembler::lessEqual;
10633 case Assembler::greaterEqual: return Assembler::less;
10634 case Assembler::below: return Assembler::aboveEqual;
10635 case Assembler::belowEqual: return Assembler::above;
10636 case Assembler::above: return Assembler::belowEqual;
10637 case Assembler::aboveEqual: return Assembler::below;
10638 case Assembler::overflow: return Assembler::noOverflow;
10639 case Assembler::noOverflow: return Assembler::overflow;
10640 case Assembler::negative: return Assembler::positive;
10641 case Assembler::positive: return Assembler::negative;
10642 case Assembler::parity: return Assembler::noParity;
10643 case Assembler::noParity: return Assembler::parity;
10644 }
10645 ShouldNotReachHere(); return Assembler::overflow;
10646 }
10647
10648 // This is simply a call to Thread::current()
10649 void MacroAssembler::get_thread(Register thread) {
10650 if (thread != rax) {
10651 push(rax);
10652 }
10653 LP64_ONLY(push(rdi);)
10654 LP64_ONLY(push(rsi);)
10655 push(rdx);
10656 push(rcx);
10657 #ifdef _LP64
10658 push(r8);
10659 push(r9);
10660 push(r10);
10661 push(r11);
10662 #endif
10663
10664 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10665
10666 #ifdef _LP64
10667 pop(r11);
10668 pop(r10);
10669 pop(r9);
10670 pop(r8);
10671 #endif
10672 pop(rcx);
10673 pop(rdx);
10674 LP64_ONLY(pop(rsi);)
10675 LP64_ONLY(pop(rdi);)
10676 if (thread != rax) {
10677 mov(thread, rax);
10678 pop(rax);
10679 }
10680 }
10681
10682 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10683 Label L_stack_ok;
10684 if (bias == 0) {
10685 testptr(sp, 2 * wordSize - 1);
10686 } else {
10687 // lea(tmp, Address(rsp, bias);
10688 mov(tmp, sp);
10689 addptr(tmp, bias);
10690 testptr(tmp, 2 * wordSize - 1);
10691 }
10692 jcc(Assembler::equal, L_stack_ok);
10693 block_comment(msg);
10694 stop(msg);
10695 bind(L_stack_ok);
10696 }
10697
10698 // Implements lightweight-locking.
10699 //
10700 // obj: the object to be locked
10701 // reg_rax: rax
10702 // thread: the thread which attempts to lock obj
10703 // tmp: a temporary register
10704 void MacroAssembler::lightweight_lock(Register basic_lock, Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10705 assert(reg_rax == rax, "");
10706 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10707
10708 Label push;
10709 const Register top = tmp;
10710
10711 // Preload the markWord. It is important that this is the first
10712 // instruction emitted as it is part of C1's null check semantics.
10713 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10714
10715 if (UseObjectMonitorTable) {
10716 // Clear cache in case fast locking succeeds.
10717 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10718 }
10719
10720 // Load top.
10721 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10722
10723 // Check if the lock-stack is full.
10724 cmpl(top, LockStack::end_offset());
10725 jcc(Assembler::greaterEqual, slow);
10726
10727 // Check for recursion.
10728 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10729 jcc(Assembler::equal, push);
10730
10731 // Check header for monitor (0b10).
10732 testptr(reg_rax, markWord::monitor_value);
10733 jcc(Assembler::notZero, slow);
10734
10735 // Try to lock. Transition lock bits 0b01 => 0b00
10736 movptr(tmp, reg_rax);
10737 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10738 orptr(reg_rax, markWord::unlocked_value);
10739 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10740 jcc(Assembler::notEqual, slow);
10741
10742 // Restore top, CAS clobbers register.
10743 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10744
10745 bind(push);
10746 // After successful lock, push object on lock-stack.
10747 movptr(Address(thread, top), obj);
10748 incrementl(top, oopSize);
10749 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10750 }
10751
10752 // Implements lightweight-unlocking.
10753 //
10754 // obj: the object to be unlocked
10755 // reg_rax: rax
10756 // thread: the thread
10757 // tmp: a temporary register
10758 void MacroAssembler::lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10759 assert(reg_rax == rax, "");
10760 assert_different_registers(obj, reg_rax, thread, tmp);
10761
10762 Label unlocked, push_and_slow;
10763 const Register top = tmp;
10764
10765 // Check if obj is top of lock-stack.
10766 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10767 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10768 jcc(Assembler::notEqual, slow);
10769
10770 // Pop lock-stack.
10771 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10772 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10773
10774 // Check if recursive.
10775 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10776 jcc(Assembler::equal, unlocked);
10777
10778 // Not recursive. Check header for monitor (0b10).
10779 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10780 testptr(reg_rax, markWord::monitor_value);
10781 jcc(Assembler::notZero, push_and_slow);
10782
10783 #ifdef ASSERT
10784 // Check header not unlocked (0b01).
10785 Label not_unlocked;
10786 testptr(reg_rax, markWord::unlocked_value);
10787 jcc(Assembler::zero, not_unlocked);
10788 stop("lightweight_unlock already unlocked");
10789 bind(not_unlocked);
10790 #endif
10791
10792 // Try to unlock. Transition lock bits 0b00 => 0b01
10793 movptr(tmp, reg_rax);
10794 orptr(tmp, markWord::unlocked_value);
10795 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10796 jcc(Assembler::equal, unlocked);
10797
10798 bind(push_and_slow);
10799 // Restore lock-stack and handle the unlock in runtime.
10800 #ifdef ASSERT
10801 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10802 movptr(Address(thread, top), obj);
10803 #endif
10804 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10805 jmp(slow);
10806
10807 bind(unlocked);
10808 }
10809
10810 #ifdef _LP64
10811 // Saves legacy GPRs state on stack.
10812 void MacroAssembler::save_legacy_gprs() {
10813 subq(rsp, 16 * wordSize);
10814 movq(Address(rsp, 15 * wordSize), rax);
10815 movq(Address(rsp, 14 * wordSize), rcx);
10816 movq(Address(rsp, 13 * wordSize), rdx);
10817 movq(Address(rsp, 12 * wordSize), rbx);
10818 movq(Address(rsp, 10 * wordSize), rbp);
10819 movq(Address(rsp, 9 * wordSize), rsi);
10820 movq(Address(rsp, 8 * wordSize), rdi);
10821 movq(Address(rsp, 7 * wordSize), r8);
10822 movq(Address(rsp, 6 * wordSize), r9);
10823 movq(Address(rsp, 5 * wordSize), r10);
10824 movq(Address(rsp, 4 * wordSize), r11);
10825 movq(Address(rsp, 3 * wordSize), r12);
10826 movq(Address(rsp, 2 * wordSize), r13);
10827 movq(Address(rsp, wordSize), r14);
10828 movq(Address(rsp, 0), r15);
10829 }
10830
10831 // Resotres back legacy GPRs state from stack.
10832 void MacroAssembler::restore_legacy_gprs() {
10833 movq(r15, Address(rsp, 0));
10834 movq(r14, Address(rsp, wordSize));
10835 movq(r13, Address(rsp, 2 * wordSize));
10836 movq(r12, Address(rsp, 3 * wordSize));
10837 movq(r11, Address(rsp, 4 * wordSize));
10838 movq(r10, Address(rsp, 5 * wordSize));
10839 movq(r9, Address(rsp, 6 * wordSize));
10840 movq(r8, Address(rsp, 7 * wordSize));
10841 movq(rdi, Address(rsp, 8 * wordSize));
10842 movq(rsi, Address(rsp, 9 * wordSize));
10843 movq(rbp, Address(rsp, 10 * wordSize));
10844 movq(rbx, Address(rsp, 12 * wordSize));
10845 movq(rdx, Address(rsp, 13 * wordSize));
10846 movq(rcx, Address(rsp, 14 * wordSize));
10847 movq(rax, Address(rsp, 15 * wordSize));
10848 addq(rsp, 16 * wordSize);
10849 }
10850
10851 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10852 if (VM_Version::supports_apx_f()) {
10853 esetzucc(comparison, dst);
10854 } else {
10855 setb(comparison, dst);
10856 movzbl(dst, dst);
10857 }
10858 }
10859 #endif