1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.hpp"
26 #include "asm/assembler.inline.hpp"
27 #include "code/aotCodeCache.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "crc32c.h"
32 #include "gc/shared/barrierSet.hpp"
33 #include "gc/shared/barrierSetAssembler.hpp"
34 #include "gc/shared/collectedHeap.inline.hpp"
35 #include "gc/shared/tlab_globals.hpp"
36 #include "interpreter/bytecodeHistogram.hpp"
37 #include "interpreter/interpreter.hpp"
38 #include "interpreter/interpreterRuntime.hpp"
39 #include "jvm.h"
40 #include "memory/resourceArea.hpp"
41 #include "memory/universe.hpp"
42 #include "oops/accessDecorators.hpp"
43 #include "oops/compressedKlass.inline.hpp"
44 #include "oops/compressedOops.inline.hpp"
45 #include "oops/klass.inline.hpp"
46 #include "prims/methodHandles.hpp"
47 #include "runtime/continuation.hpp"
48 #include "runtime/interfaceSupport.inline.hpp"
49 #include "runtime/javaThread.hpp"
50 #include "runtime/jniHandles.hpp"
51 #include "runtime/objectMonitor.hpp"
52 #include "runtime/os.hpp"
53 #include "runtime/safepoint.hpp"
54 #include "runtime/safepointMechanism.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/checkedCast.hpp"
58 #include "utilities/macros.hpp"
59
60 #ifdef PRODUCT
61 #define BLOCK_COMMENT(str) /* nothing */
62 #define STOP(error) stop(error)
63 #else
64 #define BLOCK_COMMENT(str) block_comment(str)
65 #define STOP(error) block_comment(error); stop(error)
66 #endif
67
68 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
69
70 #ifdef ASSERT
71 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
72 #endif
73
74 static const Assembler::Condition reverse[] = {
75 Assembler::noOverflow /* overflow = 0x0 */ ,
76 Assembler::overflow /* noOverflow = 0x1 */ ,
77 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
78 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
79 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
80 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
81 Assembler::above /* belowEqual = 0x6 */ ,
82 Assembler::belowEqual /* above = 0x7 */ ,
83 Assembler::positive /* negative = 0x8 */ ,
84 Assembler::negative /* positive = 0x9 */ ,
85 Assembler::noParity /* parity = 0xa */ ,
86 Assembler::parity /* noParity = 0xb */ ,
87 Assembler::greaterEqual /* less = 0xc */ ,
88 Assembler::less /* greaterEqual = 0xd */ ,
89 Assembler::greater /* lessEqual = 0xe */ ,
90 Assembler::lessEqual /* greater = 0xf, */
91
92 };
93
94
95 // Implementation of MacroAssembler
96
97 Address MacroAssembler::as_Address(AddressLiteral adr) {
98 // amd64 always does this as a pc-rel
99 // we can be absolute or disp based on the instruction type
100 // jmp/call are displacements others are absolute
101 assert(!adr.is_lval(), "must be rval");
102 assert(reachable(adr), "must be");
103 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
104
105 }
106
107 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
108 AddressLiteral base = adr.base();
109 lea(rscratch, base);
110 Address index = adr.index();
111 assert(index._disp == 0, "must not have disp"); // maybe it can?
112 Address array(rscratch, index._index, index._scale, index._disp);
113 return array;
114 }
115
116 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
117 Label L, E;
118
119 #ifdef _WIN64
120 // Windows always allocates space for it's register args
121 assert(num_args <= 4, "only register arguments supported");
122 subq(rsp, frame::arg_reg_save_area_bytes);
123 #endif
124
125 // Align stack if necessary
126 testl(rsp, 15);
127 jcc(Assembler::zero, L);
128
129 subq(rsp, 8);
130 call(RuntimeAddress(entry_point));
131 addq(rsp, 8);
132 jmp(E);
133
134 bind(L);
135 call(RuntimeAddress(entry_point));
136
137 bind(E);
138
139 #ifdef _WIN64
140 // restore stack pointer
141 addq(rsp, frame::arg_reg_save_area_bytes);
142 #endif
143 }
144
145 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
146 assert(!src2.is_lval(), "should use cmpptr");
147 assert(rscratch != noreg || always_reachable(src2), "missing");
148
149 if (reachable(src2)) {
150 cmpq(src1, as_Address(src2));
151 } else {
152 lea(rscratch, src2);
153 Assembler::cmpq(src1, Address(rscratch, 0));
154 }
155 }
156
157 int MacroAssembler::corrected_idivq(Register reg) {
158 // Full implementation of Java ldiv and lrem; checks for special
159 // case as described in JVM spec., p.243 & p.271. The function
160 // returns the (pc) offset of the idivl instruction - may be needed
161 // for implicit exceptions.
162 //
163 // normal case special case
164 //
165 // input : rax: dividend min_long
166 // reg: divisor (may not be eax/edx) -1
167 //
168 // output: rax: quotient (= rax idiv reg) min_long
169 // rdx: remainder (= rax irem reg) 0
170 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
171 static const int64_t min_long = 0x8000000000000000;
172 Label normal_case, special_case;
173
174 // check for special case
175 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
176 jcc(Assembler::notEqual, normal_case);
177 xorl(rdx, rdx); // prepare rdx for possible special case (where
178 // remainder = 0)
179 cmpq(reg, -1);
180 jcc(Assembler::equal, special_case);
181
182 // handle normal case
183 bind(normal_case);
184 cdqq();
185 int idivq_offset = offset();
186 idivq(reg);
187
188 // normal and special case exit
189 bind(special_case);
190
191 return idivq_offset;
192 }
193
194 void MacroAssembler::decrementq(Register reg, int value) {
195 if (value == min_jint) { subq(reg, value); return; }
196 if (value < 0) { incrementq(reg, -value); return; }
197 if (value == 0) { ; return; }
198 if (value == 1 && UseIncDec) { decq(reg) ; return; }
199 /* else */ { subq(reg, value) ; return; }
200 }
201
202 void MacroAssembler::decrementq(Address dst, int value) {
203 if (value == min_jint) { subq(dst, value); return; }
204 if (value < 0) { incrementq(dst, -value); return; }
205 if (value == 0) { ; return; }
206 if (value == 1 && UseIncDec) { decq(dst) ; return; }
207 /* else */ { subq(dst, value) ; return; }
208 }
209
210 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
211 assert(rscratch != noreg || always_reachable(dst), "missing");
212
213 if (reachable(dst)) {
214 incrementq(as_Address(dst));
215 } else {
216 lea(rscratch, dst);
217 incrementq(Address(rscratch, 0));
218 }
219 }
220
221 void MacroAssembler::incrementq(Register reg, int value) {
222 if (value == min_jint) { addq(reg, value); return; }
223 if (value < 0) { decrementq(reg, -value); return; }
224 if (value == 0) { ; return; }
225 if (value == 1 && UseIncDec) { incq(reg) ; return; }
226 /* else */ { addq(reg, value) ; return; }
227 }
228
229 void MacroAssembler::incrementq(Address dst, int value) {
230 if (value == min_jint) { addq(dst, value); return; }
231 if (value < 0) { decrementq(dst, -value); return; }
232 if (value == 0) { ; return; }
233 if (value == 1 && UseIncDec) { incq(dst) ; return; }
234 /* else */ { addq(dst, value) ; return; }
235 }
236
237 // 32bit can do a case table jump in one instruction but we no longer allow the base
238 // to be installed in the Address class
239 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
240 lea(rscratch, entry.base());
241 Address dispatch = entry.index();
242 assert(dispatch._base == noreg, "must be");
243 dispatch._base = rscratch;
244 jmp(dispatch);
245 }
246
247 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
248 ShouldNotReachHere(); // 64bit doesn't use two regs
249 cmpq(x_lo, y_lo);
250 }
251
252 void MacroAssembler::lea(Register dst, AddressLiteral src) {
253 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
254 }
255
256 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
257 lea(rscratch, adr);
258 movptr(dst, rscratch);
259 }
260
261 void MacroAssembler::leave() {
262 // %%% is this really better? Why not on 32bit too?
263 emit_int8((unsigned char)0xC9); // LEAVE
264 }
265
266 void MacroAssembler::lneg(Register hi, Register lo) {
267 ShouldNotReachHere(); // 64bit doesn't use two regs
268 negq(lo);
269 }
270
271 void MacroAssembler::movoop(Register dst, jobject obj) {
272 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
273 }
274
275 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
276 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
277 movq(dst, rscratch);
278 }
279
280 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
281 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
282 }
283
284 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
285 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
286 movq(dst, rscratch);
287 }
288
289 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
290 if (src.is_lval()) {
291 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
292 } else {
293 if (reachable(src)) {
294 movq(dst, as_Address(src));
295 } else {
296 lea(dst, src);
297 movq(dst, Address(dst, 0));
298 }
299 }
300 }
301
302 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
303 movq(as_Address(dst, rscratch), src);
304 }
305
306 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
307 movq(dst, as_Address(src, dst /*rscratch*/));
308 }
309
310 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
311 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
312 if (is_simm32(src)) {
313 movptr(dst, checked_cast<int32_t>(src));
314 } else {
315 mov64(rscratch, src);
316 movq(dst, rscratch);
317 }
318 }
319
320 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
321 movoop(rscratch, obj);
322 push(rscratch);
323 }
324
325 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
326 mov_metadata(rscratch, obj);
327 push(rscratch);
328 }
329
330 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
331 lea(rscratch, src);
332 if (src.is_lval()) {
333 push(rscratch);
334 } else {
335 pushq(Address(rscratch, 0));
336 }
337 }
338
339 static void pass_arg0(MacroAssembler* masm, Register arg) {
340 if (c_rarg0 != arg ) {
341 masm->mov(c_rarg0, arg);
342 }
343 }
344
345 static void pass_arg1(MacroAssembler* masm, Register arg) {
346 if (c_rarg1 != arg ) {
347 masm->mov(c_rarg1, arg);
348 }
349 }
350
351 static void pass_arg2(MacroAssembler* masm, Register arg) {
352 if (c_rarg2 != arg ) {
353 masm->mov(c_rarg2, arg);
354 }
355 }
356
357 static void pass_arg3(MacroAssembler* masm, Register arg) {
358 if (c_rarg3 != arg ) {
359 masm->mov(c_rarg3, arg);
360 }
361 }
362
363 void MacroAssembler::stop(const char* msg) {
364 if (ShowMessageBoxOnError) {
365 address rip = pc();
366 pusha(); // get regs on stack
367 lea(c_rarg1, InternalAddress(rip));
368 movq(c_rarg2, rsp); // pass pointer to regs array
369 }
370 // Skip AOT caching C strings in scratch buffer.
371 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
372 lea(c_rarg0, ExternalAddress((address) str));
373 andq(rsp, -16); // align stack as required by ABI
374 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
375 hlt();
376 }
377
378 void MacroAssembler::warn(const char* msg) {
379 push(rbp);
380 movq(rbp, rsp);
381 andq(rsp, -16); // align stack as required by push_CPU_state and call
382 push_CPU_state(); // keeps alignment at 16 bytes
383
384 #ifdef _WIN64
385 // Windows always allocates space for its register args
386 subq(rsp, frame::arg_reg_save_area_bytes);
387 #endif
388 lea(c_rarg0, ExternalAddress((address) msg));
389 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
390
391 #ifdef _WIN64
392 // restore stack pointer
393 addq(rsp, frame::arg_reg_save_area_bytes);
394 #endif
395 pop_CPU_state();
396 mov(rsp, rbp);
397 pop(rbp);
398 }
399
400 void MacroAssembler::print_state() {
401 address rip = pc();
402 pusha(); // get regs on stack
403 push(rbp);
404 movq(rbp, rsp);
405 andq(rsp, -16); // align stack as required by push_CPU_state and call
406 push_CPU_state(); // keeps alignment at 16 bytes
407
408 lea(c_rarg0, InternalAddress(rip));
409 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
410 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
411
412 pop_CPU_state();
413 mov(rsp, rbp);
414 pop(rbp);
415 popa();
416 }
417
418 #ifndef PRODUCT
419 extern "C" void findpc(intptr_t x);
420 #endif
421
422 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
423 // In order to get locks to work, we need to fake a in_VM state
424 if (ShowMessageBoxOnError) {
425 JavaThread* thread = JavaThread::current();
426 JavaThreadState saved_state = thread->thread_state();
427 thread->set_thread_state(_thread_in_vm);
428 #ifndef PRODUCT
429 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
430 ttyLocker ttyl;
431 BytecodeCounter::print();
432 }
433 #endif
434 // To see where a verify_oop failed, get $ebx+40/X for this frame.
435 // XXX correct this offset for amd64
436 // This is the value of eip which points to where verify_oop will return.
437 if (os::message_box(msg, "Execution stopped, print registers?")) {
438 print_state64(pc, regs);
439 BREAKPOINT;
440 }
441 }
442 fatal("DEBUG MESSAGE: %s", msg);
443 }
444
445 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
446 ttyLocker ttyl;
447 DebuggingContext debugging{};
448 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
449 #ifndef PRODUCT
450 tty->cr();
451 findpc(pc);
452 tty->cr();
453 #endif
454 #define PRINT_REG(rax, value) \
455 { tty->print("%s = ", #rax); os::print_location(tty, value); }
456 PRINT_REG(rax, regs[15]);
457 PRINT_REG(rbx, regs[12]);
458 PRINT_REG(rcx, regs[14]);
459 PRINT_REG(rdx, regs[13]);
460 PRINT_REG(rdi, regs[8]);
461 PRINT_REG(rsi, regs[9]);
462 PRINT_REG(rbp, regs[10]);
463 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
464 PRINT_REG(rsp, (intptr_t)(®s[16]));
465 PRINT_REG(r8 , regs[7]);
466 PRINT_REG(r9 , regs[6]);
467 PRINT_REG(r10, regs[5]);
468 PRINT_REG(r11, regs[4]);
469 PRINT_REG(r12, regs[3]);
470 PRINT_REG(r13, regs[2]);
471 PRINT_REG(r14, regs[1]);
472 PRINT_REG(r15, regs[0]);
473 #undef PRINT_REG
474 // Print some words near the top of the stack.
475 int64_t* rsp = ®s[16];
476 int64_t* dump_sp = rsp;
477 for (int col1 = 0; col1 < 8; col1++) {
478 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
479 os::print_location(tty, *dump_sp++);
480 }
481 for (int row = 0; row < 25; row++) {
482 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
483 for (int col = 0; col < 4; col++) {
484 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
485 }
486 tty->cr();
487 }
488 // Print some instructions around pc:
489 Disassembler::decode((address)pc-64, (address)pc);
490 tty->print_cr("--------");
491 Disassembler::decode((address)pc, (address)pc+32);
492 }
493
494 // The java_calling_convention describes stack locations as ideal slots on
495 // a frame with no abi restrictions. Since we must observe abi restrictions
496 // (like the placement of the register window) the slots must be biased by
497 // the following value.
498 static int reg2offset_in(VMReg r) {
499 // Account for saved rbp and return address
500 // This should really be in_preserve_stack_slots
501 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
502 }
503
504 static int reg2offset_out(VMReg r) {
505 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
506 }
507
508 // A long move
509 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
510
511 // The calling conventions assures us that each VMregpair is either
512 // all really one physical register or adjacent stack slots.
513
514 if (src.is_single_phys_reg() ) {
515 if (dst.is_single_phys_reg()) {
516 if (dst.first() != src.first()) {
517 mov(dst.first()->as_Register(), src.first()->as_Register());
518 }
519 } else {
520 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
521 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
522 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
523 }
524 } else if (dst.is_single_phys_reg()) {
525 assert(src.is_single_reg(), "not a stack pair");
526 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
527 } else {
528 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
529 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
530 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
531 }
532 }
533
534 // A double move
535 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
536
537 // The calling conventions assures us that each VMregpair is either
538 // all really one physical register or adjacent stack slots.
539
540 if (src.is_single_phys_reg() ) {
541 if (dst.is_single_phys_reg()) {
542 // In theory these overlap but the ordering is such that this is likely a nop
543 if ( src.first() != dst.first()) {
544 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
545 }
546 } else {
547 assert(dst.is_single_reg(), "not a stack pair");
548 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
549 }
550 } else if (dst.is_single_phys_reg()) {
551 assert(src.is_single_reg(), "not a stack pair");
552 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
553 } else {
554 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
555 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
556 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
557 }
558 }
559
560
561 // A float arg may have to do float reg int reg conversion
562 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
563 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
564
565 // The calling conventions assures us that each VMregpair is either
566 // all really one physical register or adjacent stack slots.
567
568 if (src.first()->is_stack()) {
569 if (dst.first()->is_stack()) {
570 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
571 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
572 } else {
573 // stack to reg
574 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
575 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
576 }
577 } else if (dst.first()->is_stack()) {
578 // reg to stack
579 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
580 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
581 } else {
582 // reg to reg
583 // In theory these overlap but the ordering is such that this is likely a nop
584 if ( src.first() != dst.first()) {
585 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
586 }
587 }
588 }
589
590 // On 64 bit we will store integer like items to the stack as
591 // 64 bits items (x86_32/64 abi) even though java would only store
592 // 32bits for a parameter. On 32bit it will simply be 32 bits
593 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
594 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
595 if (src.first()->is_stack()) {
596 if (dst.first()->is_stack()) {
597 // stack to stack
598 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
599 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
600 } else {
601 // stack to reg
602 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
603 }
604 } else if (dst.first()->is_stack()) {
605 // reg to stack
606 // Do we really have to sign extend???
607 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
608 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
609 } else {
610 // Do we really have to sign extend???
611 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
612 if (dst.first() != src.first()) {
613 movq(dst.first()->as_Register(), src.first()->as_Register());
614 }
615 }
616 }
617
618 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
619 if (src.first()->is_stack()) {
620 if (dst.first()->is_stack()) {
621 // stack to stack
622 movq(rax, Address(rbp, reg2offset_in(src.first())));
623 movq(Address(rsp, reg2offset_out(dst.first())), rax);
624 } else {
625 // stack to reg
626 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
627 }
628 } else if (dst.first()->is_stack()) {
629 // reg to stack
630 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
631 } else {
632 if (dst.first() != src.first()) {
633 movq(dst.first()->as_Register(), src.first()->as_Register());
634 }
635 }
636 }
637
638 // An oop arg. Must pass a handle not the oop itself
639 void MacroAssembler::object_move(OopMap* map,
640 int oop_handle_offset,
641 int framesize_in_slots,
642 VMRegPair src,
643 VMRegPair dst,
644 bool is_receiver,
645 int* receiver_offset) {
646
647 // must pass a handle. First figure out the location we use as a handle
648
649 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
650
651 // See if oop is null if it is we need no handle
652
653 if (src.first()->is_stack()) {
654
655 // Oop is already on the stack as an argument
656 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
657 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
658 if (is_receiver) {
659 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
660 }
661
662 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
663 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
664 // conditionally move a null
665 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
666 } else {
667
668 // Oop is in a register we must store it to the space we reserve
669 // on the stack for oop_handles and pass a handle if oop is non-null
670
671 const Register rOop = src.first()->as_Register();
672 int oop_slot;
673 if (rOop == j_rarg0)
674 oop_slot = 0;
675 else if (rOop == j_rarg1)
676 oop_slot = 1;
677 else if (rOop == j_rarg2)
678 oop_slot = 2;
679 else if (rOop == j_rarg3)
680 oop_slot = 3;
681 else if (rOop == j_rarg4)
682 oop_slot = 4;
683 else {
684 assert(rOop == j_rarg5, "wrong register");
685 oop_slot = 5;
686 }
687
688 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
689 int offset = oop_slot*VMRegImpl::stack_slot_size;
690
691 map->set_oop(VMRegImpl::stack2reg(oop_slot));
692 // Store oop in handle area, may be null
693 movptr(Address(rsp, offset), rOop);
694 if (is_receiver) {
695 *receiver_offset = offset;
696 }
697
698 cmpptr(rOop, NULL_WORD);
699 lea(rHandle, Address(rsp, offset));
700 // conditionally move a null from the handle area where it was just stored
701 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
702 }
703
704 // If arg is on the stack then place it otherwise it is already in correct reg.
705 if (dst.first()->is_stack()) {
706 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
707 }
708 }
709
710 void MacroAssembler::addptr(Register dst, int32_t imm32) {
711 addq(dst, imm32);
712 }
713
714 void MacroAssembler::addptr(Register dst, Register src) {
715 addq(dst, src);
716 }
717
718 void MacroAssembler::addptr(Address dst, Register src) {
719 addq(dst, src);
720 }
721
722 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
723 assert(rscratch != noreg || always_reachable(src), "missing");
724
725 if (reachable(src)) {
726 Assembler::addsd(dst, as_Address(src));
727 } else {
728 lea(rscratch, src);
729 Assembler::addsd(dst, Address(rscratch, 0));
730 }
731 }
732
733 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
734 assert(rscratch != noreg || always_reachable(src), "missing");
735
736 if (reachable(src)) {
737 addss(dst, as_Address(src));
738 } else {
739 lea(rscratch, src);
740 addss(dst, Address(rscratch, 0));
741 }
742 }
743
744 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
745 assert(rscratch != noreg || always_reachable(src), "missing");
746
747 if (reachable(src)) {
748 Assembler::addpd(dst, as_Address(src));
749 } else {
750 lea(rscratch, src);
751 Assembler::addpd(dst, Address(rscratch, 0));
752 }
753 }
754
755 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
756 // Stub code is generated once and never copied.
757 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
758 void MacroAssembler::align64() {
759 align(64, (uint)(uintptr_t)pc());
760 }
761
762 void MacroAssembler::align32() {
763 align(32, (uint)(uintptr_t)pc());
764 }
765
766 void MacroAssembler::align(uint modulus) {
767 // 8273459: Ensure alignment is possible with current segment alignment
768 assert(modulus <= (uintx)CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
769 align(modulus, offset());
770 }
771
772 void MacroAssembler::align(uint modulus, uint target) {
773 if (target % modulus != 0) {
774 nop(modulus - (target % modulus));
775 }
776 }
777
778 void MacroAssembler::push_f(XMMRegister r) {
779 subptr(rsp, wordSize);
780 movflt(Address(rsp, 0), r);
781 }
782
783 void MacroAssembler::pop_f(XMMRegister r) {
784 movflt(r, Address(rsp, 0));
785 addptr(rsp, wordSize);
786 }
787
788 void MacroAssembler::push_d(XMMRegister r) {
789 subptr(rsp, 2 * wordSize);
790 movdbl(Address(rsp, 0), r);
791 }
792
793 void MacroAssembler::pop_d(XMMRegister r) {
794 movdbl(r, Address(rsp, 0));
795 addptr(rsp, 2 * Interpreter::stackElementSize);
796 }
797
798 void MacroAssembler::push_ppx(Register src) {
799 if (VM_Version::supports_apx_f()) {
800 pushp(src);
801 } else {
802 Assembler::push(src);
803 }
804 }
805
806 void MacroAssembler::pop_ppx(Register dst) {
807 if (VM_Version::supports_apx_f()) {
808 popp(dst);
809 } else {
810 Assembler::pop(dst);
811 }
812 }
813
814 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
815 // Used in sign-masking with aligned address.
816 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
817 assert(rscratch != noreg || always_reachable(src), "missing");
818
819 if (UseAVX > 2 &&
820 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
821 (dst->encoding() >= 16)) {
822 vpand(dst, dst, src, AVX_512bit, rscratch);
823 } else if (reachable(src)) {
824 Assembler::andpd(dst, as_Address(src));
825 } else {
826 lea(rscratch, src);
827 Assembler::andpd(dst, Address(rscratch, 0));
828 }
829 }
830
831 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
832 // Used in sign-masking with aligned address.
833 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
834 assert(rscratch != noreg || always_reachable(src), "missing");
835
836 if (reachable(src)) {
837 Assembler::andps(dst, as_Address(src));
838 } else {
839 lea(rscratch, src);
840 Assembler::andps(dst, Address(rscratch, 0));
841 }
842 }
843
844 void MacroAssembler::andptr(Register dst, int32_t imm32) {
845 andq(dst, imm32);
846 }
847
848 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
849 assert(rscratch != noreg || always_reachable(src), "missing");
850
851 if (reachable(src)) {
852 andq(dst, as_Address(src));
853 } else {
854 lea(rscratch, src);
855 andq(dst, Address(rscratch, 0));
856 }
857 }
858
859 void MacroAssembler::atomic_incl(Address counter_addr) {
860 lock();
861 incrementl(counter_addr);
862 }
863
864 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
865 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
866
867 if (reachable(counter_addr)) {
868 atomic_incl(as_Address(counter_addr));
869 } else {
870 lea(rscratch, counter_addr);
871 atomic_incl(Address(rscratch, 0));
872 }
873 }
874
875 void MacroAssembler::atomic_incq(Address counter_addr) {
876 lock();
877 incrementq(counter_addr);
878 }
879
880 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
881 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
882
883 if (reachable(counter_addr)) {
884 atomic_incq(as_Address(counter_addr));
885 } else {
886 lea(rscratch, counter_addr);
887 atomic_incq(Address(rscratch, 0));
888 }
889 }
890
891 // Writes to stack successive pages until offset reached to check for
892 // stack overflow + shadow pages. This clobbers tmp.
893 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
894 movptr(tmp, rsp);
895 // Bang stack for total size given plus shadow page size.
896 // Bang one page at a time because large size can bang beyond yellow and
897 // red zones.
898 Label loop;
899 bind(loop);
900 movl(Address(tmp, (-(int)os::vm_page_size())), size );
901 subptr(tmp, (int)os::vm_page_size());
902 subl(size, (int)os::vm_page_size());
903 jcc(Assembler::greater, loop);
904
905 // Bang down shadow pages too.
906 // At this point, (tmp-0) is the last address touched, so don't
907 // touch it again. (It was touched as (tmp-pagesize) but then tmp
908 // was post-decremented.) Skip this address by starting at i=1, and
909 // touch a few more pages below. N.B. It is important to touch all
910 // the way down including all pages in the shadow zone.
911 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
912 // this could be any sized move but this is can be a debugging crumb
913 // so the bigger the better.
914 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
915 }
916 }
917
918 void MacroAssembler::reserved_stack_check() {
919 // testing if reserved zone needs to be enabled
920 Label no_reserved_zone_enabling;
921
922 cmpptr(rsp, Address(r15_thread, JavaThread::reserved_stack_activation_offset()));
923 jcc(Assembler::below, no_reserved_zone_enabling);
924
925 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), r15_thread);
926 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
927 should_not_reach_here();
928
929 bind(no_reserved_zone_enabling);
930 }
931
932 void MacroAssembler::c2bool(Register x) {
933 // implements x == 0 ? 0 : 1
934 // note: must only look at least-significant byte of x
935 // since C-style booleans are stored in one byte
936 // only! (was bug)
937 andl(x, 0xFF);
938 setb(Assembler::notZero, x);
939 }
940
941 // Wouldn't need if AddressLiteral version had new name
942 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
943 Assembler::call(L, rtype);
944 }
945
946 void MacroAssembler::call(Register entry) {
947 Assembler::call(entry);
948 }
949
950 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
951 assert(rscratch != noreg || always_reachable(entry), "missing");
952
953 if (reachable(entry)) {
954 Assembler::call_literal(entry.target(), entry.rspec());
955 } else {
956 lea(rscratch, entry);
957 Assembler::call(rscratch);
958 }
959 }
960
961 void MacroAssembler::ic_call(address entry, jint method_index) {
962 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
963 // Needs full 64-bit immediate for later patching.
964 mov64(rax, (int64_t)Universe::non_oop_word());
965 call(AddressLiteral(entry, rh));
966 }
967
968 int MacroAssembler::ic_check_size() {
969 return UseCompactObjectHeaders ? 17 : 14;
970 }
971
972 int MacroAssembler::ic_check(int end_alignment) {
973 Register receiver = j_rarg0;
974 Register data = rax;
975 Register temp = rscratch1;
976
977 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
978 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
979 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
980 // before the inline cache check here, and not after
981 align(end_alignment, offset() + ic_check_size());
982
983 int uep_offset = offset();
984
985 if (UseCompactObjectHeaders) {
986 load_narrow_klass_compact(temp, receiver);
987 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
988 } else if (UseCompressedClassPointers) {
989 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
990 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
991 } else {
992 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
993 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
994 }
995
996 // if inline cache check fails, then jump to runtime routine
997 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
998 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
999
1000 return uep_offset;
1001 }
1002
1003 void MacroAssembler::emit_static_call_stub() {
1004 // Static stub relocation also tags the Method* in the code-stream.
1005 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1006 // This is recognized as unresolved by relocs/nativeinst/ic code.
1007 jump(RuntimeAddress(pc()));
1008 }
1009
1010 // Implementation of call_VM versions
1011
1012 void MacroAssembler::call_VM(Register oop_result,
1013 address entry_point,
1014 bool check_exceptions) {
1015 Label C, E;
1016 call(C, relocInfo::none);
1017 jmp(E);
1018
1019 bind(C);
1020 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1021 ret(0);
1022
1023 bind(E);
1024 }
1025
1026 void MacroAssembler::call_VM(Register oop_result,
1027 address entry_point,
1028 Register arg_1,
1029 bool check_exceptions) {
1030 Label C, E;
1031 call(C, relocInfo::none);
1032 jmp(E);
1033
1034 bind(C);
1035 pass_arg1(this, arg_1);
1036 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1037 ret(0);
1038
1039 bind(E);
1040 }
1041
1042 void MacroAssembler::call_VM(Register oop_result,
1043 address entry_point,
1044 Register arg_1,
1045 Register arg_2,
1046 bool check_exceptions) {
1047 Label C, E;
1048 call(C, relocInfo::none);
1049 jmp(E);
1050
1051 bind(C);
1052
1053 assert_different_registers(arg_1, c_rarg2);
1054
1055 pass_arg2(this, arg_2);
1056 pass_arg1(this, arg_1);
1057 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1058 ret(0);
1059
1060 bind(E);
1061 }
1062
1063 void MacroAssembler::call_VM(Register oop_result,
1064 address entry_point,
1065 Register arg_1,
1066 Register arg_2,
1067 Register arg_3,
1068 bool check_exceptions) {
1069 Label C, E;
1070 call(C, relocInfo::none);
1071 jmp(E);
1072
1073 bind(C);
1074
1075 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1076 assert_different_registers(arg_2, c_rarg3);
1077 pass_arg3(this, arg_3);
1078 pass_arg2(this, arg_2);
1079 pass_arg1(this, arg_1);
1080 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1081 ret(0);
1082
1083 bind(E);
1084 }
1085
1086 void MacroAssembler::call_VM(Register oop_result,
1087 Register last_java_sp,
1088 address entry_point,
1089 int number_of_arguments,
1090 bool check_exceptions) {
1091 call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1092 }
1093
1094 void MacroAssembler::call_VM(Register oop_result,
1095 Register last_java_sp,
1096 address entry_point,
1097 Register arg_1,
1098 bool check_exceptions) {
1099 pass_arg1(this, arg_1);
1100 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1101 }
1102
1103 void MacroAssembler::call_VM(Register oop_result,
1104 Register last_java_sp,
1105 address entry_point,
1106 Register arg_1,
1107 Register arg_2,
1108 bool check_exceptions) {
1109
1110 assert_different_registers(arg_1, c_rarg2);
1111 pass_arg2(this, arg_2);
1112 pass_arg1(this, arg_1);
1113 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1114 }
1115
1116 void MacroAssembler::call_VM(Register oop_result,
1117 Register last_java_sp,
1118 address entry_point,
1119 Register arg_1,
1120 Register arg_2,
1121 Register arg_3,
1122 bool check_exceptions) {
1123 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1124 assert_different_registers(arg_2, c_rarg3);
1125 pass_arg3(this, arg_3);
1126 pass_arg2(this, arg_2);
1127 pass_arg1(this, arg_1);
1128 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1129 }
1130
1131 void MacroAssembler::super_call_VM(Register oop_result,
1132 Register last_java_sp,
1133 address entry_point,
1134 int number_of_arguments,
1135 bool check_exceptions) {
1136 MacroAssembler::call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1137 }
1138
1139 void MacroAssembler::super_call_VM(Register oop_result,
1140 Register last_java_sp,
1141 address entry_point,
1142 Register arg_1,
1143 bool check_exceptions) {
1144 pass_arg1(this, arg_1);
1145 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1146 }
1147
1148 void MacroAssembler::super_call_VM(Register oop_result,
1149 Register last_java_sp,
1150 address entry_point,
1151 Register arg_1,
1152 Register arg_2,
1153 bool check_exceptions) {
1154
1155 assert_different_registers(arg_1, c_rarg2);
1156 pass_arg2(this, arg_2);
1157 pass_arg1(this, arg_1);
1158 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1159 }
1160
1161 void MacroAssembler::super_call_VM(Register oop_result,
1162 Register last_java_sp,
1163 address entry_point,
1164 Register arg_1,
1165 Register arg_2,
1166 Register arg_3,
1167 bool check_exceptions) {
1168 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1169 assert_different_registers(arg_2, c_rarg3);
1170 pass_arg3(this, arg_3);
1171 pass_arg2(this, arg_2);
1172 pass_arg1(this, arg_1);
1173 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1174 }
1175
1176 void MacroAssembler::call_VM_base(Register oop_result,
1177 Register last_java_sp,
1178 address entry_point,
1179 int number_of_arguments,
1180 bool check_exceptions) {
1181 Register java_thread = r15_thread;
1182
1183 // determine last_java_sp register
1184 if (!last_java_sp->is_valid()) {
1185 last_java_sp = rsp;
1186 }
1187 // debugging support
1188 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1189 #ifdef ASSERT
1190 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1191 // r12 is the heapbase.
1192 if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
1193 #endif // ASSERT
1194
1195 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1196 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1197
1198 // push java thread (becomes first argument of C function)
1199
1200 mov(c_rarg0, r15_thread);
1201
1202 // set last Java frame before call
1203 assert(last_java_sp != rbp, "can't use ebp/rbp");
1204
1205 // Only interpreter should have to set fp
1206 set_last_Java_frame(last_java_sp, rbp, nullptr, rscratch1);
1207
1208 // do the call, remove parameters
1209 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1210
1211 #ifdef ASSERT
1212 // Check that thread register is not clobbered.
1213 guarantee(java_thread != rax, "change this code");
1214 push(rax);
1215 { Label L;
1216 get_thread_slow(rax);
1217 cmpptr(java_thread, rax);
1218 jcc(Assembler::equal, L);
1219 STOP("MacroAssembler::call_VM_base: java_thread not callee saved?");
1220 bind(L);
1221 }
1222 pop(rax);
1223 #endif
1224
1225 // reset last Java frame
1226 // Only interpreter should have to clear fp
1227 reset_last_Java_frame(true);
1228
1229 // C++ interp handles this in the interpreter
1230 check_and_handle_popframe();
1231 check_and_handle_earlyret();
1232
1233 if (check_exceptions) {
1234 // check for pending exceptions (java_thread is set upon return)
1235 cmpptr(Address(r15_thread, Thread::pending_exception_offset()), NULL_WORD);
1236 // This used to conditionally jump to forward_exception however it is
1237 // possible if we relocate that the branch will not reach. So we must jump
1238 // around so we can always reach
1239
1240 Label ok;
1241 jcc(Assembler::equal, ok);
1242 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1243 bind(ok);
1244 }
1245
1246 // get oop result if there is one and reset the value in the thread
1247 if (oop_result->is_valid()) {
1248 get_vm_result_oop(oop_result);
1249 }
1250 }
1251
1252 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1253 // Calculate the value for last_Java_sp somewhat subtle.
1254 // call_VM does an intermediate call which places a return address on
1255 // the stack just under the stack pointer as the user finished with it.
1256 // This allows use to retrieve last_Java_pc from last_Java_sp[-1].
1257
1258 // We've pushed one address, correct last_Java_sp
1259 lea(rax, Address(rsp, wordSize));
1260
1261 call_VM_base(oop_result, rax, entry_point, number_of_arguments, check_exceptions);
1262 }
1263
1264 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1265 void MacroAssembler::call_VM_leaf0(address entry_point) {
1266 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1267 }
1268
1269 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1270 call_VM_leaf_base(entry_point, number_of_arguments);
1271 }
1272
1273 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1274 pass_arg0(this, arg_0);
1275 call_VM_leaf(entry_point, 1);
1276 }
1277
1278 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1279
1280 assert_different_registers(arg_0, c_rarg1);
1281 pass_arg1(this, arg_1);
1282 pass_arg0(this, arg_0);
1283 call_VM_leaf(entry_point, 2);
1284 }
1285
1286 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1287 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1288 assert_different_registers(arg_1, c_rarg2);
1289 pass_arg2(this, arg_2);
1290 pass_arg1(this, arg_1);
1291 pass_arg0(this, arg_0);
1292 call_VM_leaf(entry_point, 3);
1293 }
1294
1295 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1296 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1297 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1298 assert_different_registers(arg_2, c_rarg3);
1299 pass_arg3(this, arg_3);
1300 pass_arg2(this, arg_2);
1301 pass_arg1(this, arg_1);
1302 pass_arg0(this, arg_0);
1303 call_VM_leaf(entry_point, 3);
1304 }
1305
1306 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1307 pass_arg0(this, arg_0);
1308 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1309 }
1310
1311 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1312 assert_different_registers(arg_0, c_rarg1);
1313 pass_arg1(this, arg_1);
1314 pass_arg0(this, arg_0);
1315 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1316 }
1317
1318 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1319 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1320 assert_different_registers(arg_1, c_rarg2);
1321 pass_arg2(this, arg_2);
1322 pass_arg1(this, arg_1);
1323 pass_arg0(this, arg_0);
1324 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1325 }
1326
1327 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1328 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1329 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1330 assert_different_registers(arg_2, c_rarg3);
1331 pass_arg3(this, arg_3);
1332 pass_arg2(this, arg_2);
1333 pass_arg1(this, arg_1);
1334 pass_arg0(this, arg_0);
1335 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1336 }
1337
1338 void MacroAssembler::get_vm_result_oop(Register oop_result) {
1339 movptr(oop_result, Address(r15_thread, JavaThread::vm_result_oop_offset()));
1340 movptr(Address(r15_thread, JavaThread::vm_result_oop_offset()), NULL_WORD);
1341 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1342 }
1343
1344 void MacroAssembler::get_vm_result_metadata(Register metadata_result) {
1345 movptr(metadata_result, Address(r15_thread, JavaThread::vm_result_metadata_offset()));
1346 movptr(Address(r15_thread, JavaThread::vm_result_metadata_offset()), NULL_WORD);
1347 }
1348
1349 void MacroAssembler::check_and_handle_earlyret() {
1350 }
1351
1352 void MacroAssembler::check_and_handle_popframe() {
1353 }
1354
1355 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1356 assert(rscratch != noreg || always_reachable(src1), "missing");
1357
1358 if (reachable(src1)) {
1359 cmpl(as_Address(src1), imm);
1360 } else {
1361 lea(rscratch, src1);
1362 cmpl(Address(rscratch, 0), imm);
1363 }
1364 }
1365
1366 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1367 assert(!src2.is_lval(), "use cmpptr");
1368 assert(rscratch != noreg || always_reachable(src2), "missing");
1369
1370 if (reachable(src2)) {
1371 cmpl(src1, as_Address(src2));
1372 } else {
1373 lea(rscratch, src2);
1374 cmpl(src1, Address(rscratch, 0));
1375 }
1376 }
1377
1378 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1379 Assembler::cmpl(src1, imm);
1380 }
1381
1382 void MacroAssembler::cmp32(Register src1, Address src2) {
1383 Assembler::cmpl(src1, src2);
1384 }
1385
1386 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1387 ucomisd(opr1, opr2);
1388
1389 Label L;
1390 if (unordered_is_less) {
1391 movl(dst, -1);
1392 jcc(Assembler::parity, L);
1393 jcc(Assembler::below , L);
1394 movl(dst, 0);
1395 jcc(Assembler::equal , L);
1396 increment(dst);
1397 } else { // unordered is greater
1398 movl(dst, 1);
1399 jcc(Assembler::parity, L);
1400 jcc(Assembler::above , L);
1401 movl(dst, 0);
1402 jcc(Assembler::equal , L);
1403 decrementl(dst);
1404 }
1405 bind(L);
1406 }
1407
1408 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1409 ucomiss(opr1, opr2);
1410
1411 Label L;
1412 if (unordered_is_less) {
1413 movl(dst, -1);
1414 jcc(Assembler::parity, L);
1415 jcc(Assembler::below , L);
1416 movl(dst, 0);
1417 jcc(Assembler::equal , L);
1418 increment(dst);
1419 } else { // unordered is greater
1420 movl(dst, 1);
1421 jcc(Assembler::parity, L);
1422 jcc(Assembler::above , L);
1423 movl(dst, 0);
1424 jcc(Assembler::equal , L);
1425 decrementl(dst);
1426 }
1427 bind(L);
1428 }
1429
1430
1431 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1432 assert(rscratch != noreg || always_reachable(src1), "missing");
1433
1434 if (reachable(src1)) {
1435 cmpb(as_Address(src1), imm);
1436 } else {
1437 lea(rscratch, src1);
1438 cmpb(Address(rscratch, 0), imm);
1439 }
1440 }
1441
1442 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1443 assert(rscratch != noreg || always_reachable(src2), "missing");
1444
1445 if (src2.is_lval()) {
1446 movptr(rscratch, src2);
1447 Assembler::cmpq(src1, rscratch);
1448 } else if (reachable(src2)) {
1449 cmpq(src1, as_Address(src2));
1450 } else {
1451 lea(rscratch, src2);
1452 Assembler::cmpq(src1, Address(rscratch, 0));
1453 }
1454 }
1455
1456 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1457 assert(src2.is_lval(), "not a mem-mem compare");
1458 // moves src2's literal address
1459 movptr(rscratch, src2);
1460 Assembler::cmpq(src1, rscratch);
1461 }
1462
1463 void MacroAssembler::cmpoop(Register src1, Register src2) {
1464 cmpptr(src1, src2);
1465 }
1466
1467 void MacroAssembler::cmpoop(Register src1, Address src2) {
1468 cmpptr(src1, src2);
1469 }
1470
1471 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1472 movoop(rscratch, src2);
1473 cmpptr(src1, rscratch);
1474 }
1475
1476 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1477 assert(rscratch != noreg || always_reachable(adr), "missing");
1478
1479 if (reachable(adr)) {
1480 lock();
1481 cmpxchgptr(reg, as_Address(adr));
1482 } else {
1483 lea(rscratch, adr);
1484 lock();
1485 cmpxchgptr(reg, Address(rscratch, 0));
1486 }
1487 }
1488
1489 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1490 cmpxchgq(reg, adr);
1491 }
1492
1493 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1494 assert(rscratch != noreg || always_reachable(src), "missing");
1495
1496 if (reachable(src)) {
1497 Assembler::comisd(dst, as_Address(src));
1498 } else {
1499 lea(rscratch, src);
1500 Assembler::comisd(dst, Address(rscratch, 0));
1501 }
1502 }
1503
1504 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1505 assert(rscratch != noreg || always_reachable(src), "missing");
1506
1507 if (reachable(src)) {
1508 Assembler::comiss(dst, as_Address(src));
1509 } else {
1510 lea(rscratch, src);
1511 Assembler::comiss(dst, Address(rscratch, 0));
1512 }
1513 }
1514
1515
1516 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1517 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1518
1519 Condition negated_cond = negate_condition(cond);
1520 Label L;
1521 jcc(negated_cond, L);
1522 pushf(); // Preserve flags
1523 atomic_incl(counter_addr, rscratch);
1524 popf();
1525 bind(L);
1526 }
1527
1528 int MacroAssembler::corrected_idivl(Register reg) {
1529 // Full implementation of Java idiv and irem; checks for
1530 // special case as described in JVM spec., p.243 & p.271.
1531 // The function returns the (pc) offset of the idivl
1532 // instruction - may be needed for implicit exceptions.
1533 //
1534 // normal case special case
1535 //
1536 // input : rax,: dividend min_int
1537 // reg: divisor (may not be rax,/rdx) -1
1538 //
1539 // output: rax,: quotient (= rax, idiv reg) min_int
1540 // rdx: remainder (= rax, irem reg) 0
1541 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1542 const int min_int = 0x80000000;
1543 Label normal_case, special_case;
1544
1545 // check for special case
1546 cmpl(rax, min_int);
1547 jcc(Assembler::notEqual, normal_case);
1548 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1549 cmpl(reg, -1);
1550 jcc(Assembler::equal, special_case);
1551
1552 // handle normal case
1553 bind(normal_case);
1554 cdql();
1555 int idivl_offset = offset();
1556 idivl(reg);
1557
1558 // normal and special case exit
1559 bind(special_case);
1560
1561 return idivl_offset;
1562 }
1563
1564
1565
1566 void MacroAssembler::decrementl(Register reg, int value) {
1567 if (value == min_jint) {subl(reg, value) ; return; }
1568 if (value < 0) { incrementl(reg, -value); return; }
1569 if (value == 0) { ; return; }
1570 if (value == 1 && UseIncDec) { decl(reg) ; return; }
1571 /* else */ { subl(reg, value) ; return; }
1572 }
1573
1574 void MacroAssembler::decrementl(Address dst, int value) {
1575 if (value == min_jint) {subl(dst, value) ; return; }
1576 if (value < 0) { incrementl(dst, -value); return; }
1577 if (value == 0) { ; return; }
1578 if (value == 1 && UseIncDec) { decl(dst) ; return; }
1579 /* else */ { subl(dst, value) ; return; }
1580 }
1581
1582 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1583 assert(shift_value > 0, "illegal shift value");
1584 Label _is_positive;
1585 testl (reg, reg);
1586 jcc (Assembler::positive, _is_positive);
1587 int offset = (1 << shift_value) - 1 ;
1588
1589 if (offset == 1) {
1590 incrementl(reg);
1591 } else {
1592 addl(reg, offset);
1593 }
1594
1595 bind (_is_positive);
1596 sarl(reg, shift_value);
1597 }
1598
1599 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1600 assert(rscratch != noreg || always_reachable(src), "missing");
1601
1602 if (reachable(src)) {
1603 Assembler::divsd(dst, as_Address(src));
1604 } else {
1605 lea(rscratch, src);
1606 Assembler::divsd(dst, Address(rscratch, 0));
1607 }
1608 }
1609
1610 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1611 assert(rscratch != noreg || always_reachable(src), "missing");
1612
1613 if (reachable(src)) {
1614 Assembler::divss(dst, as_Address(src));
1615 } else {
1616 lea(rscratch, src);
1617 Assembler::divss(dst, Address(rscratch, 0));
1618 }
1619 }
1620
1621 void MacroAssembler::enter() {
1622 push(rbp);
1623 mov(rbp, rsp);
1624 }
1625
1626 void MacroAssembler::post_call_nop() {
1627 if (!Continuations::enabled()) {
1628 return;
1629 }
1630 InstructionMark im(this);
1631 relocate(post_call_nop_Relocation::spec());
1632 InlineSkippedInstructionsCounter skipCounter(this);
1633 emit_int8((uint8_t)0x0f);
1634 emit_int8((uint8_t)0x1f);
1635 emit_int8((uint8_t)0x84);
1636 emit_int8((uint8_t)0x00);
1637 emit_int32(0x00);
1638 }
1639
1640 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1641 assert(rscratch != noreg || always_reachable(src), "missing");
1642 if (reachable(src)) {
1643 Assembler::mulpd(dst, as_Address(src));
1644 } else {
1645 lea(rscratch, src);
1646 Assembler::mulpd(dst, Address(rscratch, 0));
1647 }
1648 }
1649
1650 // dst = c = a * b + c
1651 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1652 Assembler::vfmadd231sd(c, a, b);
1653 if (dst != c) {
1654 movdbl(dst, c);
1655 }
1656 }
1657
1658 // dst = c = a * b + c
1659 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1660 Assembler::vfmadd231ss(c, a, b);
1661 if (dst != c) {
1662 movflt(dst, c);
1663 }
1664 }
1665
1666 // dst = c = a * b + c
1667 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1668 Assembler::vfmadd231pd(c, a, b, vector_len);
1669 if (dst != c) {
1670 vmovdqu(dst, c);
1671 }
1672 }
1673
1674 // dst = c = a * b + c
1675 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1676 Assembler::vfmadd231ps(c, a, b, vector_len);
1677 if (dst != c) {
1678 vmovdqu(dst, c);
1679 }
1680 }
1681
1682 // dst = c = a * b + c
1683 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1684 Assembler::vfmadd231pd(c, a, b, vector_len);
1685 if (dst != c) {
1686 vmovdqu(dst, c);
1687 }
1688 }
1689
1690 // dst = c = a * b + c
1691 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1692 Assembler::vfmadd231ps(c, a, b, vector_len);
1693 if (dst != c) {
1694 vmovdqu(dst, c);
1695 }
1696 }
1697
1698 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
1699 assert(rscratch != noreg || always_reachable(dst), "missing");
1700
1701 if (reachable(dst)) {
1702 incrementl(as_Address(dst));
1703 } else {
1704 lea(rscratch, dst);
1705 incrementl(Address(rscratch, 0));
1706 }
1707 }
1708
1709 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
1710 incrementl(as_Address(dst, rscratch));
1711 }
1712
1713 void MacroAssembler::incrementl(Register reg, int value) {
1714 if (value == min_jint) {addl(reg, value) ; return; }
1715 if (value < 0) { decrementl(reg, -value); return; }
1716 if (value == 0) { ; return; }
1717 if (value == 1 && UseIncDec) { incl(reg) ; return; }
1718 /* else */ { addl(reg, value) ; return; }
1719 }
1720
1721 void MacroAssembler::incrementl(Address dst, int value) {
1722 if (value == min_jint) {addl(dst, value) ; return; }
1723 if (value < 0) { decrementl(dst, -value); return; }
1724 if (value == 0) { ; return; }
1725 if (value == 1 && UseIncDec) { incl(dst) ; return; }
1726 /* else */ { addl(dst, value) ; return; }
1727 }
1728
1729 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
1730 assert(rscratch != noreg || always_reachable(dst), "missing");
1731 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
1732 if (reachable(dst)) {
1733 jmp_literal(dst.target(), dst.rspec());
1734 } else {
1735 lea(rscratch, dst);
1736 jmp(rscratch);
1737 }
1738 }
1739
1740 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
1741 assert(rscratch != noreg || always_reachable(dst), "missing");
1742 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
1743 if (reachable(dst)) {
1744 InstructionMark im(this);
1745 relocate(dst.reloc());
1746 const int short_size = 2;
1747 const int long_size = 6;
1748 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
1749 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
1750 // 0111 tttn #8-bit disp
1751 emit_int8(0x70 | cc);
1752 emit_int8((offs - short_size) & 0xFF);
1753 } else {
1754 // 0000 1111 1000 tttn #32-bit disp
1755 emit_int8(0x0F);
1756 emit_int8((unsigned char)(0x80 | cc));
1757 emit_int32(offs - long_size);
1758 }
1759 } else {
1760 #ifdef ASSERT
1761 warning("reversing conditional branch");
1762 #endif /* ASSERT */
1763 Label skip;
1764 jccb(reverse[cc], skip);
1765 lea(rscratch, dst);
1766 Assembler::jmp(rscratch);
1767 bind(skip);
1768 }
1769 }
1770
1771 void MacroAssembler::cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch) {
1772 ExternalAddress mxcsr_std(StubRoutines::x86::addr_mxcsr_std());
1773 assert(rscratch != noreg || always_reachable(mxcsr_std), "missing");
1774
1775 stmxcsr(mxcsr_save);
1776 movl(tmp, mxcsr_save);
1777 if (EnableX86ECoreOpts) {
1778 // The mxcsr_std has status bits set for performance on ECore
1779 orl(tmp, 0x003f);
1780 } else {
1781 // Mask out status bits (only check control and mask bits)
1782 andl(tmp, 0xFFC0);
1783 }
1784 cmp32(tmp, mxcsr_std, rscratch);
1785 }
1786
1787 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
1788 assert(rscratch != noreg || always_reachable(src), "missing");
1789
1790 if (reachable(src)) {
1791 Assembler::ldmxcsr(as_Address(src));
1792 } else {
1793 lea(rscratch, src);
1794 Assembler::ldmxcsr(Address(rscratch, 0));
1795 }
1796 }
1797
1798 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1799 int off = offset();
1800 movsbl(dst, src); // movsxb
1801 return off;
1802 }
1803
1804 // Note: load_signed_short used to be called load_signed_word.
1805 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
1806 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
1807 // The term "word" in HotSpot means a 32- or 64-bit machine word.
1808 int MacroAssembler::load_signed_short(Register dst, Address src) {
1809 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
1810 // version but this is what 64bit has always done. This seems to imply
1811 // that users are only using 32bits worth.
1812 int off = offset();
1813 movswl(dst, src); // movsxw
1814 return off;
1815 }
1816
1817 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1818 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1819 // and "3.9 Partial Register Penalties", p. 22).
1820 int off = offset();
1821 movzbl(dst, src); // movzxb
1822 return off;
1823 }
1824
1825 // Note: load_unsigned_short used to be called load_unsigned_word.
1826 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1827 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1828 // and "3.9 Partial Register Penalties", p. 22).
1829 int off = offset();
1830 movzwl(dst, src); // movzxw
1831 return off;
1832 }
1833
1834 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1835 switch (size_in_bytes) {
1836 case 8: movq(dst, src); break;
1837 case 4: movl(dst, src); break;
1838 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1839 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1840 default: ShouldNotReachHere();
1841 }
1842 }
1843
1844 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1845 switch (size_in_bytes) {
1846 case 8: movq(dst, src); break;
1847 case 4: movl(dst, src); break;
1848 case 2: movw(dst, src); break;
1849 case 1: movb(dst, src); break;
1850 default: ShouldNotReachHere();
1851 }
1852 }
1853
1854 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
1855 assert(rscratch != noreg || always_reachable(dst), "missing");
1856
1857 if (reachable(dst)) {
1858 movl(as_Address(dst), src);
1859 } else {
1860 lea(rscratch, dst);
1861 movl(Address(rscratch, 0), src);
1862 }
1863 }
1864
1865 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
1866 if (reachable(src)) {
1867 movl(dst, as_Address(src));
1868 } else {
1869 lea(dst, src);
1870 movl(dst, Address(dst, 0));
1871 }
1872 }
1873
1874 // C++ bool manipulation
1875
1876 void MacroAssembler::movbool(Register dst, Address src) {
1877 if(sizeof(bool) == 1)
1878 movb(dst, src);
1879 else if(sizeof(bool) == 2)
1880 movw(dst, src);
1881 else if(sizeof(bool) == 4)
1882 movl(dst, src);
1883 else
1884 // unsupported
1885 ShouldNotReachHere();
1886 }
1887
1888 void MacroAssembler::movbool(Address dst, bool boolconst) {
1889 if(sizeof(bool) == 1)
1890 movb(dst, (int) boolconst);
1891 else if(sizeof(bool) == 2)
1892 movw(dst, (int) boolconst);
1893 else if(sizeof(bool) == 4)
1894 movl(dst, (int) boolconst);
1895 else
1896 // unsupported
1897 ShouldNotReachHere();
1898 }
1899
1900 void MacroAssembler::movbool(Address dst, Register src) {
1901 if(sizeof(bool) == 1)
1902 movb(dst, src);
1903 else if(sizeof(bool) == 2)
1904 movw(dst, src);
1905 else if(sizeof(bool) == 4)
1906 movl(dst, src);
1907 else
1908 // unsupported
1909 ShouldNotReachHere();
1910 }
1911
1912 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1913 assert(rscratch != noreg || always_reachable(src), "missing");
1914
1915 if (reachable(src)) {
1916 movdl(dst, as_Address(src));
1917 } else {
1918 lea(rscratch, src);
1919 movdl(dst, Address(rscratch, 0));
1920 }
1921 }
1922
1923 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
1924 assert(rscratch != noreg || always_reachable(src), "missing");
1925
1926 if (reachable(src)) {
1927 movq(dst, as_Address(src));
1928 } else {
1929 lea(rscratch, src);
1930 movq(dst, Address(rscratch, 0));
1931 }
1932 }
1933
1934 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1935 assert(rscratch != noreg || always_reachable(src), "missing");
1936
1937 if (reachable(src)) {
1938 if (UseXmmLoadAndClearUpper) {
1939 movsd (dst, as_Address(src));
1940 } else {
1941 movlpd(dst, as_Address(src));
1942 }
1943 } else {
1944 lea(rscratch, src);
1945 if (UseXmmLoadAndClearUpper) {
1946 movsd (dst, Address(rscratch, 0));
1947 } else {
1948 movlpd(dst, Address(rscratch, 0));
1949 }
1950 }
1951 }
1952
1953 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
1954 assert(rscratch != noreg || always_reachable(src), "missing");
1955
1956 if (reachable(src)) {
1957 movss(dst, as_Address(src));
1958 } else {
1959 lea(rscratch, src);
1960 movss(dst, Address(rscratch, 0));
1961 }
1962 }
1963
1964 void MacroAssembler::movptr(Register dst, Register src) {
1965 movq(dst, src);
1966 }
1967
1968 void MacroAssembler::movptr(Register dst, Address src) {
1969 movq(dst, src);
1970 }
1971
1972 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
1973 void MacroAssembler::movptr(Register dst, intptr_t src) {
1974 if (is_uimm32(src)) {
1975 movl(dst, checked_cast<uint32_t>(src));
1976 } else if (is_simm32(src)) {
1977 movq(dst, checked_cast<int32_t>(src));
1978 } else {
1979 mov64(dst, src);
1980 }
1981 }
1982
1983 void MacroAssembler::movptr(Address dst, Register src) {
1984 movq(dst, src);
1985 }
1986
1987 void MacroAssembler::movptr(Address dst, int32_t src) {
1988 movslq(dst, src);
1989 }
1990
1991 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
1992 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
1993 Assembler::movdqu(dst, src);
1994 }
1995
1996 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
1997 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
1998 Assembler::movdqu(dst, src);
1999 }
2000
2001 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2002 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2003 Assembler::movdqu(dst, src);
2004 }
2005
2006 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2007 assert(rscratch != noreg || always_reachable(src), "missing");
2008
2009 if (reachable(src)) {
2010 movdqu(dst, as_Address(src));
2011 } else {
2012 lea(rscratch, src);
2013 movdqu(dst, Address(rscratch, 0));
2014 }
2015 }
2016
2017 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2018 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2019 Assembler::vmovdqu(dst, src);
2020 }
2021
2022 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2023 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2024 Assembler::vmovdqu(dst, src);
2025 }
2026
2027 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2028 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2029 Assembler::vmovdqu(dst, src);
2030 }
2031
2032 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2033 assert(rscratch != noreg || always_reachable(src), "missing");
2034
2035 if (reachable(src)) {
2036 vmovdqu(dst, as_Address(src));
2037 }
2038 else {
2039 lea(rscratch, src);
2040 vmovdqu(dst, Address(rscratch, 0));
2041 }
2042 }
2043
2044 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2045 assert(rscratch != noreg || always_reachable(src), "missing");
2046
2047 if (vector_len == AVX_512bit) {
2048 evmovdquq(dst, src, AVX_512bit, rscratch);
2049 } else if (vector_len == AVX_256bit) {
2050 vmovdqu(dst, src, rscratch);
2051 } else {
2052 movdqu(dst, src, rscratch);
2053 }
2054 }
2055
2056 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2057 if (vector_len == AVX_512bit) {
2058 evmovdquq(dst, src, AVX_512bit);
2059 } else if (vector_len == AVX_256bit) {
2060 vmovdqu(dst, src);
2061 } else {
2062 movdqu(dst, src);
2063 }
2064 }
2065
2066 void MacroAssembler::vmovdqu(Address dst, XMMRegister src, int vector_len) {
2067 if (vector_len == AVX_512bit) {
2068 evmovdquq(dst, src, AVX_512bit);
2069 } else if (vector_len == AVX_256bit) {
2070 vmovdqu(dst, src);
2071 } else {
2072 movdqu(dst, src);
2073 }
2074 }
2075
2076 void MacroAssembler::vmovdqu(XMMRegister dst, Address src, int vector_len) {
2077 if (vector_len == AVX_512bit) {
2078 evmovdquq(dst, src, AVX_512bit);
2079 } else if (vector_len == AVX_256bit) {
2080 vmovdqu(dst, src);
2081 } else {
2082 movdqu(dst, src);
2083 }
2084 }
2085
2086 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2087 assert(rscratch != noreg || always_reachable(src), "missing");
2088
2089 if (reachable(src)) {
2090 vmovdqa(dst, as_Address(src));
2091 }
2092 else {
2093 lea(rscratch, src);
2094 vmovdqa(dst, Address(rscratch, 0));
2095 }
2096 }
2097
2098 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2099 assert(rscratch != noreg || always_reachable(src), "missing");
2100
2101 if (vector_len == AVX_512bit) {
2102 evmovdqaq(dst, src, AVX_512bit, rscratch);
2103 } else if (vector_len == AVX_256bit) {
2104 vmovdqa(dst, src, rscratch);
2105 } else {
2106 movdqa(dst, src, rscratch);
2107 }
2108 }
2109
2110 void MacroAssembler::kmov(KRegister dst, Address src) {
2111 if (VM_Version::supports_avx512bw()) {
2112 kmovql(dst, src);
2113 } else {
2114 assert(VM_Version::supports_evex(), "");
2115 kmovwl(dst, src);
2116 }
2117 }
2118
2119 void MacroAssembler::kmov(Address dst, KRegister src) {
2120 if (VM_Version::supports_avx512bw()) {
2121 kmovql(dst, src);
2122 } else {
2123 assert(VM_Version::supports_evex(), "");
2124 kmovwl(dst, src);
2125 }
2126 }
2127
2128 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2129 if (VM_Version::supports_avx512bw()) {
2130 kmovql(dst, src);
2131 } else {
2132 assert(VM_Version::supports_evex(), "");
2133 kmovwl(dst, src);
2134 }
2135 }
2136
2137 void MacroAssembler::kmov(Register dst, KRegister src) {
2138 if (VM_Version::supports_avx512bw()) {
2139 kmovql(dst, src);
2140 } else {
2141 assert(VM_Version::supports_evex(), "");
2142 kmovwl(dst, src);
2143 }
2144 }
2145
2146 void MacroAssembler::kmov(KRegister dst, Register src) {
2147 if (VM_Version::supports_avx512bw()) {
2148 kmovql(dst, src);
2149 } else {
2150 assert(VM_Version::supports_evex(), "");
2151 kmovwl(dst, src);
2152 }
2153 }
2154
2155 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2156 assert(rscratch != noreg || always_reachable(src), "missing");
2157
2158 if (reachable(src)) {
2159 kmovql(dst, as_Address(src));
2160 } else {
2161 lea(rscratch, src);
2162 kmovql(dst, Address(rscratch, 0));
2163 }
2164 }
2165
2166 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2167 assert(rscratch != noreg || always_reachable(src), "missing");
2168
2169 if (reachable(src)) {
2170 kmovwl(dst, as_Address(src));
2171 } else {
2172 lea(rscratch, src);
2173 kmovwl(dst, Address(rscratch, 0));
2174 }
2175 }
2176
2177 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2178 int vector_len, Register rscratch) {
2179 assert(rscratch != noreg || always_reachable(src), "missing");
2180
2181 if (reachable(src)) {
2182 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2183 } else {
2184 lea(rscratch, src);
2185 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2186 }
2187 }
2188
2189 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2190 int vector_len, Register rscratch) {
2191 assert(rscratch != noreg || always_reachable(src), "missing");
2192
2193 if (reachable(src)) {
2194 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2195 } else {
2196 lea(rscratch, src);
2197 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2198 }
2199 }
2200
2201 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2202 assert(rscratch != noreg || always_reachable(src), "missing");
2203
2204 if (reachable(src)) {
2205 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2206 } else {
2207 lea(rscratch, src);
2208 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2209 }
2210 }
2211
2212 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2213 assert(rscratch != noreg || always_reachable(src), "missing");
2214
2215 if (reachable(src)) {
2216 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2217 } else {
2218 lea(rscratch, src);
2219 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2220 }
2221 }
2222
2223 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2224 assert(rscratch != noreg || always_reachable(src), "missing");
2225
2226 if (reachable(src)) {
2227 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2228 } else {
2229 lea(rscratch, src);
2230 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2231 }
2232 }
2233
2234 void MacroAssembler::evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2235 assert(rscratch != noreg || always_reachable(src), "missing");
2236
2237 if (reachable(src)) {
2238 Assembler::evmovdqaq(dst, mask, as_Address(src), merge, vector_len);
2239 } else {
2240 lea(rscratch, src);
2241 Assembler::evmovdqaq(dst, mask, Address(rscratch, 0), merge, vector_len);
2242 }
2243 }
2244
2245 void MacroAssembler::evmovdqaq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2246 assert(rscratch != noreg || always_reachable(src), "missing");
2247
2248 if (reachable(src)) {
2249 Assembler::evmovdqaq(dst, as_Address(src), vector_len);
2250 } else {
2251 lea(rscratch, src);
2252 Assembler::evmovdqaq(dst, Address(rscratch, 0), vector_len);
2253 }
2254 }
2255
2256 void MacroAssembler::movapd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2257 assert(rscratch != noreg || always_reachable(src), "missing");
2258
2259 if (reachable(src)) {
2260 Assembler::movapd(dst, as_Address(src));
2261 } else {
2262 lea(rscratch, src);
2263 Assembler::movapd(dst, Address(rscratch, 0));
2264 }
2265 }
2266
2267 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2268 assert(rscratch != noreg || always_reachable(src), "missing");
2269
2270 if (reachable(src)) {
2271 Assembler::movdqa(dst, as_Address(src));
2272 } else {
2273 lea(rscratch, src);
2274 Assembler::movdqa(dst, Address(rscratch, 0));
2275 }
2276 }
2277
2278 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2279 assert(rscratch != noreg || always_reachable(src), "missing");
2280
2281 if (reachable(src)) {
2282 Assembler::movsd(dst, as_Address(src));
2283 } else {
2284 lea(rscratch, src);
2285 Assembler::movsd(dst, Address(rscratch, 0));
2286 }
2287 }
2288
2289 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2290 assert(rscratch != noreg || always_reachable(src), "missing");
2291
2292 if (reachable(src)) {
2293 Assembler::movss(dst, as_Address(src));
2294 } else {
2295 lea(rscratch, src);
2296 Assembler::movss(dst, Address(rscratch, 0));
2297 }
2298 }
2299
2300 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2301 assert(rscratch != noreg || always_reachable(src), "missing");
2302
2303 if (reachable(src)) {
2304 Assembler::movddup(dst, as_Address(src));
2305 } else {
2306 lea(rscratch, src);
2307 Assembler::movddup(dst, Address(rscratch, 0));
2308 }
2309 }
2310
2311 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2312 assert(rscratch != noreg || always_reachable(src), "missing");
2313
2314 if (reachable(src)) {
2315 Assembler::vmovddup(dst, as_Address(src), vector_len);
2316 } else {
2317 lea(rscratch, src);
2318 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2319 }
2320 }
2321
2322 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2323 assert(rscratch != noreg || always_reachable(src), "missing");
2324
2325 if (reachable(src)) {
2326 Assembler::mulsd(dst, as_Address(src));
2327 } else {
2328 lea(rscratch, src);
2329 Assembler::mulsd(dst, Address(rscratch, 0));
2330 }
2331 }
2332
2333 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2334 assert(rscratch != noreg || always_reachable(src), "missing");
2335
2336 if (reachable(src)) {
2337 Assembler::mulss(dst, as_Address(src));
2338 } else {
2339 lea(rscratch, src);
2340 Assembler::mulss(dst, Address(rscratch, 0));
2341 }
2342 }
2343
2344 void MacroAssembler::null_check(Register reg, int offset) {
2345 if (needs_explicit_null_check(offset)) {
2346 // provoke OS null exception if reg is null by
2347 // accessing M[reg] w/o changing any (non-CC) registers
2348 // NOTE: cmpl is plenty here to provoke a segv
2349 cmpptr(rax, Address(reg, 0));
2350 // Note: should probably use testl(rax, Address(reg, 0));
2351 // may be shorter code (however, this version of
2352 // testl needs to be implemented first)
2353 } else {
2354 // nothing to do, (later) access of M[reg + offset]
2355 // will provoke OS null exception if reg is null
2356 }
2357 }
2358
2359 void MacroAssembler::os_breakpoint() {
2360 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2361 // (e.g., MSVC can't call ps() otherwise)
2362 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2363 }
2364
2365 void MacroAssembler::unimplemented(const char* what) {
2366 const char* buf = nullptr;
2367 {
2368 ResourceMark rm;
2369 stringStream ss;
2370 ss.print("unimplemented: %s", what);
2371 buf = code_string(ss.as_string());
2372 }
2373 stop(buf);
2374 }
2375
2376 #define XSTATE_BV 0x200
2377
2378 void MacroAssembler::pop_CPU_state() {
2379 pop_FPU_state();
2380 pop_IU_state();
2381 }
2382
2383 void MacroAssembler::pop_FPU_state() {
2384 fxrstor(Address(rsp, 0));
2385 addptr(rsp, FPUStateSizeInWords * wordSize);
2386 }
2387
2388 void MacroAssembler::pop_IU_state() {
2389 popa();
2390 addq(rsp, 8);
2391 popf();
2392 }
2393
2394 // Save Integer and Float state
2395 // Warning: Stack must be 16 byte aligned (64bit)
2396 void MacroAssembler::push_CPU_state() {
2397 push_IU_state();
2398 push_FPU_state();
2399 }
2400
2401 void MacroAssembler::push_FPU_state() {
2402 subptr(rsp, FPUStateSizeInWords * wordSize);
2403 fxsave(Address(rsp, 0));
2404 }
2405
2406 void MacroAssembler::push_IU_state() {
2407 // Push flags first because pusha kills them
2408 pushf();
2409 // Make sure rsp stays 16-byte aligned
2410 subq(rsp, 8);
2411 pusha();
2412 }
2413
2414 void MacroAssembler::push_cont_fastpath() {
2415 if (!Continuations::enabled()) return;
2416
2417 Label L_done;
2418 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2419 jccb(Assembler::belowEqual, L_done);
2420 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), rsp);
2421 bind(L_done);
2422 }
2423
2424 void MacroAssembler::pop_cont_fastpath() {
2425 if (!Continuations::enabled()) return;
2426
2427 Label L_done;
2428 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2429 jccb(Assembler::below, L_done);
2430 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), 0);
2431 bind(L_done);
2432 }
2433
2434 #ifdef ASSERT
2435 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
2436 Label no_cont;
2437 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
2438 testl(cont, cont);
2439 jcc(Assembler::zero, no_cont);
2440 stop(name);
2441 bind(no_cont);
2442 }
2443 #endif
2444
2445 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { // determine java_thread register
2446 // we must set sp to zero to clear frame
2447 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2448 // must clear fp, so that compiled frames are not confused; it is
2449 // possible that we need it only for debugging
2450 if (clear_fp) {
2451 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2452 }
2453 // Always clear the pc because it could have been set by make_walkable()
2454 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2455 vzeroupper();
2456 }
2457
2458 void MacroAssembler::round_to(Register reg, int modulus) {
2459 addptr(reg, modulus - 1);
2460 andptr(reg, -modulus);
2461 }
2462
2463 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod) {
2464 if (at_return) {
2465 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2466 // we may safely use rsp instead to perform the stack watermark check.
2467 cmpptr(in_nmethod ? rsp : rbp, Address(r15_thread, JavaThread::polling_word_offset()));
2468 jcc(Assembler::above, slow_path);
2469 return;
2470 }
2471 testb(Address(r15_thread, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2472 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2473 }
2474
2475 // Calls to C land
2476 //
2477 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2478 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2479 // has to be reset to 0. This is required to allow proper stack traversal.
2480 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2481 Register last_java_fp,
2482 address last_java_pc,
2483 Register rscratch) {
2484 vzeroupper();
2485 // determine last_java_sp register
2486 if (!last_java_sp->is_valid()) {
2487 last_java_sp = rsp;
2488 }
2489 // last_java_fp is optional
2490 if (last_java_fp->is_valid()) {
2491 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2492 }
2493 // last_java_pc is optional
2494 if (last_java_pc != nullptr) {
2495 Address java_pc(r15_thread,
2496 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
2497 lea(java_pc, InternalAddress(last_java_pc), rscratch);
2498 }
2499 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2500 }
2501
2502 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2503 Register last_java_fp,
2504 Label &L,
2505 Register scratch) {
2506 lea(scratch, L);
2507 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
2508 set_last_Java_frame(last_java_sp, last_java_fp, nullptr, scratch);
2509 }
2510
2511 void MacroAssembler::shlptr(Register dst, int imm8) {
2512 shlq(dst, imm8);
2513 }
2514
2515 void MacroAssembler::shrptr(Register dst, int imm8) {
2516 shrq(dst, imm8);
2517 }
2518
2519 void MacroAssembler::sign_extend_byte(Register reg) {
2520 movsbl(reg, reg); // movsxb
2521 }
2522
2523 void MacroAssembler::sign_extend_short(Register reg) {
2524 movswl(reg, reg); // movsxw
2525 }
2526
2527 void MacroAssembler::testl(Address dst, int32_t imm32) {
2528 if (imm32 >= 0 && is8bit(imm32)) {
2529 testb(dst, imm32);
2530 } else {
2531 Assembler::testl(dst, imm32);
2532 }
2533 }
2534
2535 void MacroAssembler::testl(Register dst, int32_t imm32) {
2536 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
2537 testb(dst, imm32);
2538 } else {
2539 Assembler::testl(dst, imm32);
2540 }
2541 }
2542
2543 void MacroAssembler::testl(Register dst, AddressLiteral src) {
2544 assert(always_reachable(src), "Address should be reachable");
2545 testl(dst, as_Address(src));
2546 }
2547
2548 void MacroAssembler::testq(Address dst, int32_t imm32) {
2549 if (imm32 >= 0) {
2550 testl(dst, imm32);
2551 } else {
2552 Assembler::testq(dst, imm32);
2553 }
2554 }
2555
2556 void MacroAssembler::testq(Register dst, int32_t imm32) {
2557 if (imm32 >= 0) {
2558 testl(dst, imm32);
2559 } else {
2560 Assembler::testq(dst, imm32);
2561 }
2562 }
2563
2564 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
2565 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2566 Assembler::pcmpeqb(dst, src);
2567 }
2568
2569 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
2570 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2571 Assembler::pcmpeqw(dst, src);
2572 }
2573
2574 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2575 assert((dst->encoding() < 16),"XMM register should be 0-15");
2576 Assembler::pcmpestri(dst, src, imm8);
2577 }
2578
2579 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2580 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2581 Assembler::pcmpestri(dst, src, imm8);
2582 }
2583
2584 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2585 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2586 Assembler::pmovzxbw(dst, src);
2587 }
2588
2589 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
2590 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2591 Assembler::pmovzxbw(dst, src);
2592 }
2593
2594 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
2595 assert((src->encoding() < 16),"XMM register should be 0-15");
2596 Assembler::pmovmskb(dst, src);
2597 }
2598
2599 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
2600 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2601 Assembler::ptest(dst, src);
2602 }
2603
2604 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2605 assert(rscratch != noreg || always_reachable(src), "missing");
2606
2607 if (reachable(src)) {
2608 Assembler::sqrtss(dst, as_Address(src));
2609 } else {
2610 lea(rscratch, src);
2611 Assembler::sqrtss(dst, Address(rscratch, 0));
2612 }
2613 }
2614
2615 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2616 assert(rscratch != noreg || always_reachable(src), "missing");
2617
2618 if (reachable(src)) {
2619 Assembler::subsd(dst, as_Address(src));
2620 } else {
2621 lea(rscratch, src);
2622 Assembler::subsd(dst, Address(rscratch, 0));
2623 }
2624 }
2625
2626 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
2627 assert(rscratch != noreg || always_reachable(src), "missing");
2628
2629 if (reachable(src)) {
2630 Assembler::roundsd(dst, as_Address(src), rmode);
2631 } else {
2632 lea(rscratch, src);
2633 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
2634 }
2635 }
2636
2637 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2638 assert(rscratch != noreg || always_reachable(src), "missing");
2639
2640 if (reachable(src)) {
2641 Assembler::subss(dst, as_Address(src));
2642 } else {
2643 lea(rscratch, src);
2644 Assembler::subss(dst, Address(rscratch, 0));
2645 }
2646 }
2647
2648 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2649 assert(rscratch != noreg || always_reachable(src), "missing");
2650
2651 if (reachable(src)) {
2652 Assembler::ucomisd(dst, as_Address(src));
2653 } else {
2654 lea(rscratch, src);
2655 Assembler::ucomisd(dst, Address(rscratch, 0));
2656 }
2657 }
2658
2659 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2660 assert(rscratch != noreg || always_reachable(src), "missing");
2661
2662 if (reachable(src)) {
2663 Assembler::ucomiss(dst, as_Address(src));
2664 } else {
2665 lea(rscratch, src);
2666 Assembler::ucomiss(dst, Address(rscratch, 0));
2667 }
2668 }
2669
2670 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2671 assert(rscratch != noreg || always_reachable(src), "missing");
2672
2673 // Used in sign-bit flipping with aligned address.
2674 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2675
2676 if (UseAVX > 2 &&
2677 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2678 (dst->encoding() >= 16)) {
2679 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2680 } else if (reachable(src)) {
2681 Assembler::xorpd(dst, as_Address(src));
2682 } else {
2683 lea(rscratch, src);
2684 Assembler::xorpd(dst, Address(rscratch, 0));
2685 }
2686 }
2687
2688 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
2689 if (UseAVX > 2 &&
2690 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2691 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2692 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2693 } else {
2694 Assembler::xorpd(dst, src);
2695 }
2696 }
2697
2698 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
2699 if (UseAVX > 2 &&
2700 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2701 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2702 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2703 } else {
2704 Assembler::xorps(dst, src);
2705 }
2706 }
2707
2708 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
2709 assert(rscratch != noreg || always_reachable(src), "missing");
2710
2711 // Used in sign-bit flipping with aligned address.
2712 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2713
2714 if (UseAVX > 2 &&
2715 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2716 (dst->encoding() >= 16)) {
2717 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2718 } else if (reachable(src)) {
2719 Assembler::xorps(dst, as_Address(src));
2720 } else {
2721 lea(rscratch, src);
2722 Assembler::xorps(dst, Address(rscratch, 0));
2723 }
2724 }
2725
2726 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
2727 assert(rscratch != noreg || always_reachable(src), "missing");
2728
2729 // Used in sign-bit flipping with aligned address.
2730 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
2731 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
2732 if (reachable(src)) {
2733 Assembler::pshufb(dst, as_Address(src));
2734 } else {
2735 lea(rscratch, src);
2736 Assembler::pshufb(dst, Address(rscratch, 0));
2737 }
2738 }
2739
2740 // AVX 3-operands instructions
2741
2742 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2743 assert(rscratch != noreg || always_reachable(src), "missing");
2744
2745 if (reachable(src)) {
2746 vaddsd(dst, nds, as_Address(src));
2747 } else {
2748 lea(rscratch, src);
2749 vaddsd(dst, nds, Address(rscratch, 0));
2750 }
2751 }
2752
2753 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2754 assert(rscratch != noreg || always_reachable(src), "missing");
2755
2756 if (reachable(src)) {
2757 vaddss(dst, nds, as_Address(src));
2758 } else {
2759 lea(rscratch, src);
2760 vaddss(dst, nds, Address(rscratch, 0));
2761 }
2762 }
2763
2764 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2765 assert(UseAVX > 0, "requires some form of AVX");
2766 assert(rscratch != noreg || always_reachable(src), "missing");
2767
2768 if (reachable(src)) {
2769 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
2770 } else {
2771 lea(rscratch, src);
2772 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
2773 }
2774 }
2775
2776 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2777 assert(UseAVX > 0, "requires some form of AVX");
2778 assert(rscratch != noreg || always_reachable(src), "missing");
2779
2780 if (reachable(src)) {
2781 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
2782 } else {
2783 lea(rscratch, src);
2784 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
2785 }
2786 }
2787
2788 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2789 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2790 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2791
2792 vandps(dst, nds, negate_field, vector_len, rscratch);
2793 }
2794
2795 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2796 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2797 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2798
2799 vandpd(dst, nds, negate_field, vector_len, rscratch);
2800 }
2801
2802 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2803 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2804 Assembler::vpaddb(dst, nds, src, vector_len);
2805 }
2806
2807 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2808 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2809 Assembler::vpaddb(dst, nds, src, vector_len);
2810 }
2811
2812 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2813 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2814 Assembler::vpaddw(dst, nds, src, vector_len);
2815 }
2816
2817 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2818 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2819 Assembler::vpaddw(dst, nds, src, vector_len);
2820 }
2821
2822 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2823 assert(rscratch != noreg || always_reachable(src), "missing");
2824
2825 if (reachable(src)) {
2826 Assembler::vpand(dst, nds, as_Address(src), vector_len);
2827 } else {
2828 lea(rscratch, src);
2829 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
2830 }
2831 }
2832
2833 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2834 assert(rscratch != noreg || always_reachable(src), "missing");
2835
2836 if (reachable(src)) {
2837 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
2838 } else {
2839 lea(rscratch, src);
2840 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
2841 }
2842 }
2843
2844 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2845 assert(rscratch != noreg || always_reachable(src), "missing");
2846
2847 if (reachable(src)) {
2848 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
2849 } else {
2850 lea(rscratch, src);
2851 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
2852 }
2853 }
2854
2855 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2856 assert(rscratch != noreg || always_reachable(src), "missing");
2857
2858 if (reachable(src)) {
2859 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
2860 } else {
2861 lea(rscratch, src);
2862 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
2863 }
2864 }
2865
2866 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2867 assert(rscratch != noreg || always_reachable(src), "missing");
2868
2869 if (reachable(src)) {
2870 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
2871 } else {
2872 lea(rscratch, src);
2873 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
2874 }
2875 }
2876
2877 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2878 assert(rscratch != noreg || always_reachable(src), "missing");
2879
2880 if (reachable(src)) {
2881 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
2882 } else {
2883 lea(rscratch, src);
2884 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
2885 }
2886 }
2887
2888 // Vector float blend
2889 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
2890 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
2891 // WARN: Allow dst == (src1|src2), mask == scratch
2892 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
2893 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
2894 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
2895 bool dst_available = dst != mask && (dst != src1 || dst != src2);
2896 if (blend_emulation && scratch_available && dst_available) {
2897 if (compute_mask) {
2898 vpsrad(scratch, mask, 32, vector_len);
2899 mask = scratch;
2900 }
2901 if (dst == src1) {
2902 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
2903 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
2904 } else {
2905 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
2906 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
2907 }
2908 vpor(dst, dst, scratch, vector_len);
2909 } else {
2910 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
2911 }
2912 }
2913
2914 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
2915 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
2916 // WARN: Allow dst == (src1|src2), mask == scratch
2917 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
2918 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
2919 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
2920 bool dst_available = dst != mask && (dst != src1 || dst != src2);
2921 if (blend_emulation && scratch_available && dst_available) {
2922 if (compute_mask) {
2923 vpxor(scratch, scratch, scratch, vector_len);
2924 vpcmpgtq(scratch, scratch, mask, vector_len);
2925 mask = scratch;
2926 }
2927 if (dst == src1) {
2928 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
2929 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
2930 } else {
2931 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
2932 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
2933 }
2934 vpor(dst, dst, scratch, vector_len);
2935 } else {
2936 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
2937 }
2938 }
2939
2940 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2941 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2942 Assembler::vpcmpeqb(dst, nds, src, vector_len);
2943 }
2944
2945 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
2946 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2947 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
2948 }
2949
2950 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2951 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2952 Assembler::vpcmpeqw(dst, nds, src, vector_len);
2953 }
2954
2955 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2956 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2957 Assembler::vpcmpeqw(dst, nds, src, vector_len);
2958 }
2959
2960 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2961 assert(rscratch != noreg || always_reachable(src), "missing");
2962
2963 if (reachable(src)) {
2964 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
2965 } else {
2966 lea(rscratch, src);
2967 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
2968 }
2969 }
2970
2971 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
2972 int comparison, bool is_signed, int vector_len, Register rscratch) {
2973 assert(rscratch != noreg || always_reachable(src), "missing");
2974
2975 if (reachable(src)) {
2976 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
2977 } else {
2978 lea(rscratch, src);
2979 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
2980 }
2981 }
2982
2983 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
2984 int comparison, bool is_signed, int vector_len, Register rscratch) {
2985 assert(rscratch != noreg || always_reachable(src), "missing");
2986
2987 if (reachable(src)) {
2988 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
2989 } else {
2990 lea(rscratch, src);
2991 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
2992 }
2993 }
2994
2995 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
2996 int comparison, bool is_signed, int vector_len, Register rscratch) {
2997 assert(rscratch != noreg || always_reachable(src), "missing");
2998
2999 if (reachable(src)) {
3000 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3001 } else {
3002 lea(rscratch, src);
3003 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3004 }
3005 }
3006
3007 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3008 int comparison, bool is_signed, int vector_len, Register rscratch) {
3009 assert(rscratch != noreg || always_reachable(src), "missing");
3010
3011 if (reachable(src)) {
3012 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3013 } else {
3014 lea(rscratch, src);
3015 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3016 }
3017 }
3018
3019 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3020 if (width == Assembler::Q) {
3021 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3022 } else {
3023 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3024 }
3025 }
3026
3027 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3028 int eq_cond_enc = 0x29;
3029 int gt_cond_enc = 0x37;
3030 if (width != Assembler::Q) {
3031 eq_cond_enc = 0x74 + width;
3032 gt_cond_enc = 0x64 + width;
3033 }
3034 switch (cond) {
3035 case eq:
3036 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3037 break;
3038 case neq:
3039 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3040 vallones(xtmp, vector_len);
3041 vpxor(dst, xtmp, dst, vector_len);
3042 break;
3043 case le:
3044 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3045 vallones(xtmp, vector_len);
3046 vpxor(dst, xtmp, dst, vector_len);
3047 break;
3048 case nlt:
3049 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3050 vallones(xtmp, vector_len);
3051 vpxor(dst, xtmp, dst, vector_len);
3052 break;
3053 case lt:
3054 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3055 break;
3056 case nle:
3057 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3058 break;
3059 default:
3060 assert(false, "Should not reach here");
3061 }
3062 }
3063
3064 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3065 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3066 Assembler::vpmovzxbw(dst, src, vector_len);
3067 }
3068
3069 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3070 assert((src->encoding() < 16),"XMM register should be 0-15");
3071 Assembler::vpmovmskb(dst, src, vector_len);
3072 }
3073
3074 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3075 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3076 Assembler::vpmullw(dst, nds, src, vector_len);
3077 }
3078
3079 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3080 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3081 Assembler::vpmullw(dst, nds, src, vector_len);
3082 }
3083
3084 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3085 assert((UseAVX > 0), "AVX support is needed");
3086 assert(rscratch != noreg || always_reachable(src), "missing");
3087
3088 if (reachable(src)) {
3089 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3090 } else {
3091 lea(rscratch, src);
3092 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3093 }
3094 }
3095
3096 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3097 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3098 Assembler::vpsubb(dst, nds, src, vector_len);
3099 }
3100
3101 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3102 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3103 Assembler::vpsubb(dst, nds, src, vector_len);
3104 }
3105
3106 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3107 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3108 Assembler::vpsubw(dst, nds, src, vector_len);
3109 }
3110
3111 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3112 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3113 Assembler::vpsubw(dst, nds, src, vector_len);
3114 }
3115
3116 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3117 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3118 Assembler::vpsraw(dst, nds, shift, vector_len);
3119 }
3120
3121 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3122 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3123 Assembler::vpsraw(dst, nds, shift, vector_len);
3124 }
3125
3126 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3127 assert(UseAVX > 2,"");
3128 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3129 vector_len = 2;
3130 }
3131 Assembler::evpsraq(dst, nds, shift, vector_len);
3132 }
3133
3134 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3135 assert(UseAVX > 2,"");
3136 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3137 vector_len = 2;
3138 }
3139 Assembler::evpsraq(dst, nds, shift, vector_len);
3140 }
3141
3142 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3143 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3144 Assembler::vpsrlw(dst, nds, shift, vector_len);
3145 }
3146
3147 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3148 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3149 Assembler::vpsrlw(dst, nds, shift, vector_len);
3150 }
3151
3152 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3153 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3154 Assembler::vpsllw(dst, nds, shift, vector_len);
3155 }
3156
3157 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3158 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3159 Assembler::vpsllw(dst, nds, shift, vector_len);
3160 }
3161
3162 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3163 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3164 Assembler::vptest(dst, src);
3165 }
3166
3167 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3168 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3169 Assembler::punpcklbw(dst, src);
3170 }
3171
3172 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3173 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3174 Assembler::pshufd(dst, src, mode);
3175 }
3176
3177 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3178 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3179 Assembler::pshuflw(dst, src, mode);
3180 }
3181
3182 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3183 assert(rscratch != noreg || always_reachable(src), "missing");
3184
3185 if (reachable(src)) {
3186 vandpd(dst, nds, as_Address(src), vector_len);
3187 } else {
3188 lea(rscratch, src);
3189 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3190 }
3191 }
3192
3193 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3194 assert(rscratch != noreg || always_reachable(src), "missing");
3195
3196 if (reachable(src)) {
3197 vandps(dst, nds, as_Address(src), vector_len);
3198 } else {
3199 lea(rscratch, src);
3200 vandps(dst, nds, Address(rscratch, 0), vector_len);
3201 }
3202 }
3203
3204 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3205 bool merge, int vector_len, Register rscratch) {
3206 assert(rscratch != noreg || always_reachable(src), "missing");
3207
3208 if (reachable(src)) {
3209 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3210 } else {
3211 lea(rscratch, src);
3212 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3213 }
3214 }
3215
3216 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3217 assert(rscratch != noreg || always_reachable(src), "missing");
3218
3219 if (reachable(src)) {
3220 vdivsd(dst, nds, as_Address(src));
3221 } else {
3222 lea(rscratch, src);
3223 vdivsd(dst, nds, Address(rscratch, 0));
3224 }
3225 }
3226
3227 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3228 assert(rscratch != noreg || always_reachable(src), "missing");
3229
3230 if (reachable(src)) {
3231 vdivss(dst, nds, as_Address(src));
3232 } else {
3233 lea(rscratch, src);
3234 vdivss(dst, nds, Address(rscratch, 0));
3235 }
3236 }
3237
3238 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3239 assert(rscratch != noreg || always_reachable(src), "missing");
3240
3241 if (reachable(src)) {
3242 vmulsd(dst, nds, as_Address(src));
3243 } else {
3244 lea(rscratch, src);
3245 vmulsd(dst, nds, Address(rscratch, 0));
3246 }
3247 }
3248
3249 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3250 assert(rscratch != noreg || always_reachable(src), "missing");
3251
3252 if (reachable(src)) {
3253 vmulss(dst, nds, as_Address(src));
3254 } else {
3255 lea(rscratch, src);
3256 vmulss(dst, nds, Address(rscratch, 0));
3257 }
3258 }
3259
3260 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3261 assert(rscratch != noreg || always_reachable(src), "missing");
3262
3263 if (reachable(src)) {
3264 vsubsd(dst, nds, as_Address(src));
3265 } else {
3266 lea(rscratch, src);
3267 vsubsd(dst, nds, Address(rscratch, 0));
3268 }
3269 }
3270
3271 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3272 assert(rscratch != noreg || always_reachable(src), "missing");
3273
3274 if (reachable(src)) {
3275 vsubss(dst, nds, as_Address(src));
3276 } else {
3277 lea(rscratch, src);
3278 vsubss(dst, nds, Address(rscratch, 0));
3279 }
3280 }
3281
3282 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3283 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3284 assert(rscratch != noreg || always_reachable(src), "missing");
3285
3286 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3287 }
3288
3289 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3290 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3291 assert(rscratch != noreg || always_reachable(src), "missing");
3292
3293 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3294 }
3295
3296 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3297 assert(rscratch != noreg || always_reachable(src), "missing");
3298
3299 if (reachable(src)) {
3300 vxorpd(dst, nds, as_Address(src), vector_len);
3301 } else {
3302 lea(rscratch, src);
3303 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3304 }
3305 }
3306
3307 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3308 assert(rscratch != noreg || always_reachable(src), "missing");
3309
3310 if (reachable(src)) {
3311 vxorps(dst, nds, as_Address(src), vector_len);
3312 } else {
3313 lea(rscratch, src);
3314 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3315 }
3316 }
3317
3318 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3319 assert(rscratch != noreg || always_reachable(src), "missing");
3320
3321 if (UseAVX > 1 || (vector_len < 1)) {
3322 if (reachable(src)) {
3323 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3324 } else {
3325 lea(rscratch, src);
3326 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3327 }
3328 } else {
3329 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3330 }
3331 }
3332
3333 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3334 assert(rscratch != noreg || always_reachable(src), "missing");
3335
3336 if (reachable(src)) {
3337 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3338 } else {
3339 lea(rscratch, src);
3340 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3341 }
3342 }
3343
3344 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3345 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3346 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3347 // The inverted mask is sign-extended
3348 andptr(possibly_non_local, inverted_mask);
3349 }
3350
3351 void MacroAssembler::resolve_jobject(Register value,
3352 Register tmp) {
3353 Register thread = r15_thread;
3354 assert_different_registers(value, thread, tmp);
3355 Label done, tagged, weak_tagged;
3356 testptr(value, value);
3357 jcc(Assembler::zero, done); // Use null as-is.
3358 testptr(value, JNIHandles::tag_mask); // Test for tag.
3359 jcc(Assembler::notZero, tagged);
3360
3361 // Resolve local handle
3362 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp);
3363 verify_oop(value);
3364 jmp(done);
3365
3366 bind(tagged);
3367 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
3368 jcc(Assembler::notZero, weak_tagged);
3369
3370 // Resolve global handle
3371 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3372 verify_oop(value);
3373 jmp(done);
3374
3375 bind(weak_tagged);
3376 // Resolve jweak.
3377 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3378 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp);
3379 verify_oop(value);
3380
3381 bind(done);
3382 }
3383
3384 void MacroAssembler::resolve_global_jobject(Register value,
3385 Register tmp) {
3386 Register thread = r15_thread;
3387 assert_different_registers(value, thread, tmp);
3388 Label done;
3389
3390 testptr(value, value);
3391 jcc(Assembler::zero, done); // Use null as-is.
3392
3393 #ifdef ASSERT
3394 {
3395 Label valid_global_tag;
3396 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
3397 jcc(Assembler::notZero, valid_global_tag);
3398 stop("non global jobject using resolve_global_jobject");
3399 bind(valid_global_tag);
3400 }
3401 #endif
3402
3403 // Resolve global handle
3404 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3405 verify_oop(value);
3406
3407 bind(done);
3408 }
3409
3410 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3411 subq(dst, imm32);
3412 }
3413
3414 // Force generation of a 4 byte immediate value even if it fits into 8bit
3415 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3416 subq_imm32(dst, imm32);
3417 }
3418
3419 void MacroAssembler::subptr(Register dst, Register src) {
3420 subq(dst, src);
3421 }
3422
3423 // C++ bool manipulation
3424 void MacroAssembler::testbool(Register dst) {
3425 if(sizeof(bool) == 1)
3426 testb(dst, 0xff);
3427 else if(sizeof(bool) == 2) {
3428 // testw implementation needed for two byte bools
3429 ShouldNotReachHere();
3430 } else if(sizeof(bool) == 4)
3431 testl(dst, dst);
3432 else
3433 // unsupported
3434 ShouldNotReachHere();
3435 }
3436
3437 void MacroAssembler::testptr(Register dst, Register src) {
3438 testq(dst, src);
3439 }
3440
3441 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3442 void MacroAssembler::tlab_allocate(Register obj,
3443 Register var_size_in_bytes,
3444 int con_size_in_bytes,
3445 Register t1,
3446 Register t2,
3447 Label& slow_case) {
3448 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3449 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3450 }
3451
3452 RegSet MacroAssembler::call_clobbered_gp_registers() {
3453 RegSet regs;
3454 regs += RegSet::of(rax, rcx, rdx);
3455 #ifndef _WINDOWS
3456 regs += RegSet::of(rsi, rdi);
3457 #endif
3458 regs += RegSet::range(r8, r11);
3459 if (UseAPX) {
3460 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
3461 }
3462 return regs;
3463 }
3464
3465 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
3466 int num_xmm_registers = XMMRegister::available_xmm_registers();
3467 #if defined(_WINDOWS)
3468 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
3469 if (num_xmm_registers > 16) {
3470 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
3471 }
3472 return result;
3473 #else
3474 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
3475 #endif
3476 }
3477
3478 // C1 only ever uses the first double/float of the XMM register.
3479 static int xmm_save_size() { return sizeof(double); }
3480
3481 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3482 masm->movdbl(Address(rsp, offset), reg);
3483 }
3484
3485 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3486 masm->movdbl(reg, Address(rsp, offset));
3487 }
3488
3489 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
3490 bool save_fpu, int& gp_area_size, int& xmm_area_size) {
3491
3492 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
3493 StackAlignmentInBytes);
3494 xmm_area_size = save_fpu ? xmm_registers.size() * xmm_save_size() : 0;
3495
3496 return gp_area_size + xmm_area_size;
3497 }
3498
3499 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
3500 block_comment("push_call_clobbered_registers start");
3501 // Regular registers
3502 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
3503
3504 int gp_area_size;
3505 int xmm_area_size;
3506 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
3507 gp_area_size, xmm_area_size);
3508 subptr(rsp, total_save_size);
3509
3510 push_set(gp_registers_to_push, 0);
3511
3512 if (save_fpu) {
3513 push_set(call_clobbered_xmm_registers(), gp_area_size);
3514 }
3515
3516 block_comment("push_call_clobbered_registers end");
3517 }
3518
3519 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
3520 block_comment("pop_call_clobbered_registers start");
3521
3522 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
3523
3524 int gp_area_size;
3525 int xmm_area_size;
3526 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
3527 gp_area_size, xmm_area_size);
3528
3529 if (restore_fpu) {
3530 pop_set(call_clobbered_xmm_registers(), gp_area_size);
3531 }
3532
3533 pop_set(gp_registers_to_pop, 0);
3534
3535 addptr(rsp, total_save_size);
3536
3537 vzeroupper();
3538
3539 block_comment("pop_call_clobbered_registers end");
3540 }
3541
3542 void MacroAssembler::push_set(XMMRegSet set, int offset) {
3543 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
3544 int spill_offset = offset;
3545
3546 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
3547 save_xmm_register(this, spill_offset, *it);
3548 spill_offset += xmm_save_size();
3549 }
3550 }
3551
3552 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
3553 int restore_size = set.size() * xmm_save_size();
3554 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
3555
3556 int restore_offset = offset + restore_size - xmm_save_size();
3557
3558 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
3559 restore_xmm_register(this, restore_offset, *it);
3560 restore_offset -= xmm_save_size();
3561 }
3562 }
3563
3564 void MacroAssembler::push_set(RegSet set, int offset) {
3565 int spill_offset;
3566 if (offset == -1) {
3567 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3568 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
3569 subptr(rsp, aligned_size);
3570 spill_offset = 0;
3571 } else {
3572 spill_offset = offset;
3573 }
3574
3575 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
3576 movptr(Address(rsp, spill_offset), *it);
3577 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3578 }
3579 }
3580
3581 void MacroAssembler::pop_set(RegSet set, int offset) {
3582
3583 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3584 int restore_size = set.size() * gp_reg_size;
3585 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
3586
3587 int restore_offset;
3588 if (offset == -1) {
3589 restore_offset = restore_size - gp_reg_size;
3590 } else {
3591 restore_offset = offset + restore_size - gp_reg_size;
3592 }
3593 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
3594 movptr(*it, Address(rsp, restore_offset));
3595 restore_offset -= gp_reg_size;
3596 }
3597
3598 if (offset == -1) {
3599 addptr(rsp, aligned_size);
3600 }
3601 }
3602
3603 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3604 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3605 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3606 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3607 Label done;
3608
3609 testptr(length_in_bytes, length_in_bytes);
3610 jcc(Assembler::zero, done);
3611
3612 // initialize topmost word, divide index by 2, check if odd and test if zero
3613 // note: for the remaining code to work, index must be a multiple of BytesPerWord
3614 #ifdef ASSERT
3615 {
3616 Label L;
3617 testptr(length_in_bytes, BytesPerWord - 1);
3618 jcc(Assembler::zero, L);
3619 stop("length must be a multiple of BytesPerWord");
3620 bind(L);
3621 }
3622 #endif
3623 Register index = length_in_bytes;
3624 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
3625 if (UseIncDec) {
3626 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
3627 } else {
3628 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
3629 shrptr(index, 1);
3630 }
3631
3632 // initialize remaining object fields: index is a multiple of 2 now
3633 {
3634 Label loop;
3635 bind(loop);
3636 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3637 decrement(index);
3638 jcc(Assembler::notZero, loop);
3639 }
3640
3641 bind(done);
3642 }
3643
3644 // Look up the method for a megamorphic invokeinterface call.
3645 // The target method is determined by <intf_klass, itable_index>.
3646 // The receiver klass is in recv_klass.
3647 // On success, the result will be in method_result, and execution falls through.
3648 // On failure, execution transfers to the given label.
3649 void MacroAssembler::lookup_interface_method(Register recv_klass,
3650 Register intf_klass,
3651 RegisterOrConstant itable_index,
3652 Register method_result,
3653 Register scan_temp,
3654 Label& L_no_such_interface,
3655 bool return_method) {
3656 assert_different_registers(recv_klass, intf_klass, scan_temp);
3657 assert_different_registers(method_result, intf_klass, scan_temp);
3658 assert(recv_klass != method_result || !return_method,
3659 "recv_klass can be destroyed when method isn't needed");
3660
3661 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3662 "caller must use same register for non-constant itable index as for method");
3663
3664 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3665 int vtable_base = in_bytes(Klass::vtable_start_offset());
3666 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3667 int scan_step = itableOffsetEntry::size() * wordSize;
3668 int vte_size = vtableEntry::size_in_bytes();
3669 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3670 assert(vte_size == wordSize, "else adjust times_vte_scale");
3671
3672 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3673
3674 // Could store the aligned, prescaled offset in the klass.
3675 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3676
3677 if (return_method) {
3678 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3679 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3680 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3681 }
3682
3683 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
3684 // if (scan->interface() == intf) {
3685 // result = (klass + scan->offset() + itable_index);
3686 // }
3687 // }
3688 Label search, found_method;
3689
3690 for (int peel = 1; peel >= 0; peel--) {
3691 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
3692 cmpptr(intf_klass, method_result);
3693
3694 if (peel) {
3695 jccb(Assembler::equal, found_method);
3696 } else {
3697 jccb(Assembler::notEqual, search);
3698 // (invert the test to fall through to found_method...)
3699 }
3700
3701 if (!peel) break;
3702
3703 bind(search);
3704
3705 // Check that the previous entry is non-null. A null entry means that
3706 // the receiver class doesn't implement the interface, and wasn't the
3707 // same as when the caller was compiled.
3708 testptr(method_result, method_result);
3709 jcc(Assembler::zero, L_no_such_interface);
3710 addptr(scan_temp, scan_step);
3711 }
3712
3713 bind(found_method);
3714
3715 if (return_method) {
3716 // Got a hit.
3717 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
3718 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
3719 }
3720 }
3721
3722 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
3723 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
3724 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
3725 // The target method is determined by <holder_klass, itable_index>.
3726 // The receiver klass is in recv_klass.
3727 // On success, the result will be in method_result, and execution falls through.
3728 // On failure, execution transfers to the given label.
3729 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
3730 Register holder_klass,
3731 Register resolved_klass,
3732 Register method_result,
3733 Register scan_temp,
3734 Register temp_reg2,
3735 Register receiver,
3736 int itable_index,
3737 Label& L_no_such_interface) {
3738 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
3739 Register temp_itbl_klass = method_result;
3740 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
3741
3742 int vtable_base = in_bytes(Klass::vtable_start_offset());
3743 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3744 int scan_step = itableOffsetEntry::size() * wordSize;
3745 int vte_size = vtableEntry::size_in_bytes();
3746 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
3747 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
3748 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3749 assert(vte_size == wordSize, "adjust times_vte_scale");
3750
3751 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
3752
3753 // temp_itbl_klass = recv_klass.itable[0]
3754 // scan_temp = &recv_klass.itable[0] + step
3755 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3756 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
3757 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
3758 xorptr(temp_reg, temp_reg);
3759
3760 // Initial checks:
3761 // - if (holder_klass != resolved_klass), go to "scan for resolved"
3762 // - if (itable[0] == 0), no such interface
3763 // - if (itable[0] == holder_klass), shortcut to "holder found"
3764 cmpptr(holder_klass, resolved_klass);
3765 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
3766 testptr(temp_itbl_klass, temp_itbl_klass);
3767 jccb(Assembler::zero, L_no_such_interface);
3768 cmpptr(holder_klass, temp_itbl_klass);
3769 jccb(Assembler::equal, L_holder_found);
3770
3771 // Loop: Look for holder_klass record in itable
3772 // do {
3773 // tmp = itable[index];
3774 // index += step;
3775 // if (tmp == holder_klass) {
3776 // goto L_holder_found; // Found!
3777 // }
3778 // } while (tmp != 0);
3779 // goto L_no_such_interface // Not found.
3780 Label L_scan_holder;
3781 bind(L_scan_holder);
3782 movptr(temp_itbl_klass, Address(scan_temp, 0));
3783 addptr(scan_temp, scan_step);
3784 cmpptr(holder_klass, temp_itbl_klass);
3785 jccb(Assembler::equal, L_holder_found);
3786 testptr(temp_itbl_klass, temp_itbl_klass);
3787 jccb(Assembler::notZero, L_scan_holder);
3788
3789 jmpb(L_no_such_interface);
3790
3791 // Loop: Look for resolved_class record in itable
3792 // do {
3793 // tmp = itable[index];
3794 // index += step;
3795 // if (tmp == holder_klass) {
3796 // // Also check if we have met a holder klass
3797 // holder_tmp = itable[index-step-ioffset];
3798 // }
3799 // if (tmp == resolved_klass) {
3800 // goto L_resolved_found; // Found!
3801 // }
3802 // } while (tmp != 0);
3803 // goto L_no_such_interface // Not found.
3804 //
3805 Label L_loop_scan_resolved;
3806 bind(L_loop_scan_resolved);
3807 movptr(temp_itbl_klass, Address(scan_temp, 0));
3808 addptr(scan_temp, scan_step);
3809 bind(L_loop_scan_resolved_entry);
3810 cmpptr(holder_klass, temp_itbl_klass);
3811 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
3812 cmpptr(resolved_klass, temp_itbl_klass);
3813 jccb(Assembler::equal, L_resolved_found);
3814 testptr(temp_itbl_klass, temp_itbl_klass);
3815 jccb(Assembler::notZero, L_loop_scan_resolved);
3816
3817 jmpb(L_no_such_interface);
3818
3819 Label L_ready;
3820
3821 // See if we already have a holder klass. If not, go and scan for it.
3822 bind(L_resolved_found);
3823 testptr(temp_reg, temp_reg);
3824 jccb(Assembler::zero, L_scan_holder);
3825 jmpb(L_ready);
3826
3827 bind(L_holder_found);
3828 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
3829
3830 // Finally, temp_reg contains holder_klass vtable offset
3831 bind(L_ready);
3832 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3833 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
3834 load_klass(scan_temp, receiver, noreg);
3835 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
3836 } else {
3837 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
3838 }
3839 }
3840
3841
3842 // virtual method calling
3843 void MacroAssembler::lookup_virtual_method(Register recv_klass,
3844 RegisterOrConstant vtable_index,
3845 Register method_result) {
3846 const ByteSize base = Klass::vtable_start_offset();
3847 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
3848 Address vtable_entry_addr(recv_klass,
3849 vtable_index, Address::times_ptr,
3850 base + vtableEntry::method_offset());
3851 movptr(method_result, vtable_entry_addr);
3852 }
3853
3854
3855 void MacroAssembler::check_klass_subtype(Register sub_klass,
3856 Register super_klass,
3857 Register temp_reg,
3858 Label& L_success) {
3859 Label L_failure;
3860 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
3861 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
3862 bind(L_failure);
3863 }
3864
3865
3866 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
3867 Register super_klass,
3868 Register temp_reg,
3869 Label* L_success,
3870 Label* L_failure,
3871 Label* L_slow_path,
3872 RegisterOrConstant super_check_offset) {
3873 assert_different_registers(sub_klass, super_klass, temp_reg);
3874 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
3875 if (super_check_offset.is_register()) {
3876 assert_different_registers(sub_klass, super_klass,
3877 super_check_offset.as_register());
3878 } else if (must_load_sco) {
3879 assert(temp_reg != noreg, "supply either a temp or a register offset");
3880 }
3881
3882 Label L_fallthrough;
3883 int label_nulls = 0;
3884 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
3885 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
3886 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
3887 assert(label_nulls <= 1, "at most one null in the batch");
3888
3889 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3890 int sco_offset = in_bytes(Klass::super_check_offset_offset());
3891 Address super_check_offset_addr(super_klass, sco_offset);
3892
3893 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
3894 // range of a jccb. If this routine grows larger, reconsider at
3895 // least some of these.
3896 #define local_jcc(assembler_cond, label) \
3897 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
3898 else jcc( assembler_cond, label) /*omit semi*/
3899
3900 // Hacked jmp, which may only be used just before L_fallthrough.
3901 #define final_jmp(label) \
3902 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
3903 else jmp(label) /*omit semi*/
3904
3905 // If the pointers are equal, we are done (e.g., String[] elements).
3906 // This self-check enables sharing of secondary supertype arrays among
3907 // non-primary types such as array-of-interface. Otherwise, each such
3908 // type would need its own customized SSA.
3909 // We move this check to the front of the fast path because many
3910 // type checks are in fact trivially successful in this manner,
3911 // so we get a nicely predicted branch right at the start of the check.
3912 cmpptr(sub_klass, super_klass);
3913 local_jcc(Assembler::equal, *L_success);
3914
3915 // Check the supertype display:
3916 if (must_load_sco) {
3917 // Positive movl does right thing on LP64.
3918 movl(temp_reg, super_check_offset_addr);
3919 super_check_offset = RegisterOrConstant(temp_reg);
3920 }
3921 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
3922 cmpptr(super_klass, super_check_addr); // load displayed supertype
3923
3924 // This check has worked decisively for primary supers.
3925 // Secondary supers are sought in the super_cache ('super_cache_addr').
3926 // (Secondary supers are interfaces and very deeply nested subtypes.)
3927 // This works in the same check above because of a tricky aliasing
3928 // between the super_cache and the primary super display elements.
3929 // (The 'super_check_addr' can address either, as the case requires.)
3930 // Note that the cache is updated below if it does not help us find
3931 // what we need immediately.
3932 // So if it was a primary super, we can just fail immediately.
3933 // Otherwise, it's the slow path for us (no success at this point).
3934
3935 if (super_check_offset.is_register()) {
3936 local_jcc(Assembler::equal, *L_success);
3937 cmpl(super_check_offset.as_register(), sc_offset);
3938 if (L_failure == &L_fallthrough) {
3939 local_jcc(Assembler::equal, *L_slow_path);
3940 } else {
3941 local_jcc(Assembler::notEqual, *L_failure);
3942 final_jmp(*L_slow_path);
3943 }
3944 } else if (super_check_offset.as_constant() == sc_offset) {
3945 // Need a slow path; fast failure is impossible.
3946 if (L_slow_path == &L_fallthrough) {
3947 local_jcc(Assembler::equal, *L_success);
3948 } else {
3949 local_jcc(Assembler::notEqual, *L_slow_path);
3950 final_jmp(*L_success);
3951 }
3952 } else {
3953 // No slow path; it's a fast decision.
3954 if (L_failure == &L_fallthrough) {
3955 local_jcc(Assembler::equal, *L_success);
3956 } else {
3957 local_jcc(Assembler::notEqual, *L_failure);
3958 final_jmp(*L_success);
3959 }
3960 }
3961
3962 bind(L_fallthrough);
3963
3964 #undef local_jcc
3965 #undef final_jmp
3966 }
3967
3968
3969 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
3970 Register super_klass,
3971 Register temp_reg,
3972 Register temp2_reg,
3973 Label* L_success,
3974 Label* L_failure,
3975 bool set_cond_codes) {
3976 assert_different_registers(sub_klass, super_klass, temp_reg);
3977 if (temp2_reg != noreg)
3978 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
3979 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
3980
3981 Label L_fallthrough;
3982 int label_nulls = 0;
3983 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
3984 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
3985 assert(label_nulls <= 1, "at most one null in the batch");
3986
3987 // a couple of useful fields in sub_klass:
3988 int ss_offset = in_bytes(Klass::secondary_supers_offset());
3989 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3990 Address secondary_supers_addr(sub_klass, ss_offset);
3991 Address super_cache_addr( sub_klass, sc_offset);
3992
3993 // Do a linear scan of the secondary super-klass chain.
3994 // This code is rarely used, so simplicity is a virtue here.
3995 // The repne_scan instruction uses fixed registers, which we must spill.
3996 // Don't worry too much about pre-existing connections with the input regs.
3997
3998 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
3999 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4000
4001 // Get super_klass value into rax (even if it was in rdi or rcx).
4002 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4003 if (super_klass != rax) {
4004 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4005 mov(rax, super_klass);
4006 }
4007 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4008 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4009
4010 #ifndef PRODUCT
4011 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4012 ExternalAddress pst_counter_addr((address) pst_counter);
4013 lea(rcx, pst_counter_addr);
4014 incrementl(Address(rcx, 0));
4015 #endif //PRODUCT
4016
4017 // We will consult the secondary-super array.
4018 movptr(rdi, secondary_supers_addr);
4019 // Load the array length. (Positive movl does right thing on LP64.)
4020 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4021 // Skip to start of data.
4022 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4023
4024 // Scan RCX words at [RDI] for an occurrence of RAX.
4025 // Set NZ/Z based on last compare.
4026 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4027 // not change flags (only scas instruction which is repeated sets flags).
4028 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4029
4030 testptr(rax,rax); // Set Z = 0
4031 repne_scan();
4032
4033 // Unspill the temp. registers:
4034 if (pushed_rdi) pop(rdi);
4035 if (pushed_rcx) pop(rcx);
4036 if (pushed_rax) pop(rax);
4037
4038 if (set_cond_codes) {
4039 // Special hack for the AD files: rdi is guaranteed non-zero.
4040 assert(!pushed_rdi, "rdi must be left non-null");
4041 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4042 }
4043
4044 if (L_failure == &L_fallthrough)
4045 jccb(Assembler::notEqual, *L_failure);
4046 else jcc(Assembler::notEqual, *L_failure);
4047
4048 // Success. Cache the super we found and proceed in triumph.
4049 movptr(super_cache_addr, super_klass);
4050
4051 if (L_success != &L_fallthrough) {
4052 jmp(*L_success);
4053 }
4054
4055 #undef IS_A_TEMP
4056
4057 bind(L_fallthrough);
4058 }
4059
4060 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4061 Register super_klass,
4062 Register temp_reg,
4063 Register temp2_reg,
4064 Label* L_success,
4065 Label* L_failure,
4066 bool set_cond_codes) {
4067 assert(set_cond_codes == false, "must be false on 64-bit x86");
4068 check_klass_subtype_slow_path
4069 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4070 L_success, L_failure);
4071 }
4072
4073 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4074 Register super_klass,
4075 Register temp_reg,
4076 Register temp2_reg,
4077 Register temp3_reg,
4078 Register temp4_reg,
4079 Label* L_success,
4080 Label* L_failure) {
4081 if (UseSecondarySupersTable) {
4082 check_klass_subtype_slow_path_table
4083 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4084 L_success, L_failure);
4085 } else {
4086 check_klass_subtype_slow_path_linear
4087 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4088 }
4089 }
4090
4091 Register MacroAssembler::allocate_if_noreg(Register r,
4092 RegSetIterator<Register> &available_regs,
4093 RegSet ®s_to_push) {
4094 if (!r->is_valid()) {
4095 r = *available_regs++;
4096 regs_to_push += r;
4097 }
4098 return r;
4099 }
4100
4101 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4102 Register super_klass,
4103 Register temp_reg,
4104 Register temp2_reg,
4105 Register temp3_reg,
4106 Register result_reg,
4107 Label* L_success,
4108 Label* L_failure) {
4109 // NB! Callers may assume that, when temp2_reg is a valid register,
4110 // this code sets it to a nonzero value.
4111 bool temp2_reg_was_valid = temp2_reg->is_valid();
4112
4113 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4114
4115 Label L_fallthrough;
4116 int label_nulls = 0;
4117 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4118 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4119 assert(label_nulls <= 1, "at most one null in the batch");
4120
4121 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4122
4123 RegSetIterator<Register> available_regs
4124 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4125
4126 RegSet pushed_regs;
4127
4128 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4129 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4130 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4131 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4132 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4133
4134 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4135
4136 {
4137
4138 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4139 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4140 subptr(rsp, aligned_size);
4141 push_set(pushed_regs, 0);
4142
4143 lookup_secondary_supers_table_var(sub_klass,
4144 super_klass,
4145 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4146 cmpq(result_reg, 0);
4147
4148 // Unspill the temp. registers:
4149 pop_set(pushed_regs, 0);
4150 // Increment SP but do not clobber flags.
4151 lea(rsp, Address(rsp, aligned_size));
4152 }
4153
4154 if (temp2_reg_was_valid) {
4155 movq(temp2_reg, 1);
4156 }
4157
4158 jcc(Assembler::notEqual, *L_failure);
4159
4160 if (L_success != &L_fallthrough) {
4161 jmp(*L_success);
4162 }
4163
4164 bind(L_fallthrough);
4165 }
4166
4167 // population_count variant for running without the POPCNT
4168 // instruction, which was introduced with SSE4.2 in 2008.
4169 void MacroAssembler::population_count(Register dst, Register src,
4170 Register scratch1, Register scratch2) {
4171 assert_different_registers(src, scratch1, scratch2);
4172 if (UsePopCountInstruction) {
4173 Assembler::popcntq(dst, src);
4174 } else {
4175 assert_different_registers(src, scratch1, scratch2);
4176 assert_different_registers(dst, scratch1, scratch2);
4177 Label loop, done;
4178
4179 mov(scratch1, src);
4180 // dst = 0;
4181 // while(scratch1 != 0) {
4182 // dst++;
4183 // scratch1 &= (scratch1 - 1);
4184 // }
4185 xorl(dst, dst);
4186 testq(scratch1, scratch1);
4187 jccb(Assembler::equal, done);
4188 {
4189 bind(loop);
4190 incq(dst);
4191 movq(scratch2, scratch1);
4192 decq(scratch2);
4193 andq(scratch1, scratch2);
4194 jccb(Assembler::notEqual, loop);
4195 }
4196 bind(done);
4197 }
4198 #ifdef ASSERT
4199 mov64(scratch1, 0xCafeBabeDeadBeef);
4200 movq(scratch2, scratch1);
4201 #endif
4202 }
4203
4204 // Ensure that the inline code and the stub are using the same registers.
4205 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4206 do { \
4207 assert(r_super_klass == rax, "mismatch"); \
4208 assert(r_array_base == rbx, "mismatch"); \
4209 assert(r_array_length == rcx, "mismatch"); \
4210 assert(r_array_index == rdx, "mismatch"); \
4211 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4212 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4213 assert(result == rdi || result == noreg, "mismatch"); \
4214 } while(0)
4215
4216 // Versions of salq and rorq that don't need count to be in rcx
4217
4218 void MacroAssembler::salq(Register dest, Register count) {
4219 if (count == rcx) {
4220 Assembler::salq(dest);
4221 } else {
4222 assert_different_registers(rcx, dest);
4223 xchgq(rcx, count);
4224 Assembler::salq(dest);
4225 xchgq(rcx, count);
4226 }
4227 }
4228
4229 void MacroAssembler::rorq(Register dest, Register count) {
4230 if (count == rcx) {
4231 Assembler::rorq(dest);
4232 } else {
4233 assert_different_registers(rcx, dest);
4234 xchgq(rcx, count);
4235 Assembler::rorq(dest);
4236 xchgq(rcx, count);
4237 }
4238 }
4239
4240 // Return true: we succeeded in generating this code
4241 //
4242 // At runtime, return 0 in result if r_super_klass is a superclass of
4243 // r_sub_klass, otherwise return nonzero. Use this if you know the
4244 // super_klass_slot of the class you're looking for. This is always
4245 // the case for instanceof and checkcast.
4246 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4247 Register r_super_klass,
4248 Register temp1,
4249 Register temp2,
4250 Register temp3,
4251 Register temp4,
4252 Register result,
4253 u1 super_klass_slot) {
4254 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4255
4256 Label L_fallthrough, L_success, L_failure;
4257
4258 BLOCK_COMMENT("lookup_secondary_supers_table {");
4259
4260 const Register
4261 r_array_index = temp1,
4262 r_array_length = temp2,
4263 r_array_base = temp3,
4264 r_bitmap = temp4;
4265
4266 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4267
4268 xorq(result, result); // = 0
4269
4270 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4271 movq(r_array_index, r_bitmap);
4272
4273 // First check the bitmap to see if super_klass might be present. If
4274 // the bit is zero, we are certain that super_klass is not one of
4275 // the secondary supers.
4276 u1 bit = super_klass_slot;
4277 {
4278 // NB: If the count in a x86 shift instruction is 0, the flags are
4279 // not affected, so we do a testq instead.
4280 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4281 if (shift_count != 0) {
4282 salq(r_array_index, shift_count);
4283 } else {
4284 testq(r_array_index, r_array_index);
4285 }
4286 }
4287 // We test the MSB of r_array_index, i.e. its sign bit
4288 jcc(Assembler::positive, L_failure);
4289
4290 // Get the first array index that can contain super_klass into r_array_index.
4291 if (bit != 0) {
4292 population_count(r_array_index, r_array_index, temp2, temp3);
4293 } else {
4294 movl(r_array_index, 1);
4295 }
4296 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4297
4298 // We will consult the secondary-super array.
4299 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4300
4301 // We're asserting that the first word in an Array<Klass*> is the
4302 // length, and the second word is the first word of the data. If
4303 // that ever changes, r_array_base will have to be adjusted here.
4304 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4305 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4306
4307 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4308 jccb(Assembler::equal, L_success);
4309
4310 // Is there another entry to check? Consult the bitmap.
4311 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
4312 jccb(Assembler::carryClear, L_failure);
4313
4314 // Linear probe. Rotate the bitmap so that the next bit to test is
4315 // in Bit 1.
4316 if (bit != 0) {
4317 rorq(r_bitmap, bit);
4318 }
4319
4320 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4321 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4322 // Kills: r_array_length.
4323 // Returns: result.
4324 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
4325 // Result (0/1) is in rdi
4326 jmpb(L_fallthrough);
4327
4328 bind(L_failure);
4329 incq(result); // 0 => 1
4330
4331 bind(L_success);
4332 // result = 0;
4333
4334 bind(L_fallthrough);
4335 BLOCK_COMMENT("} lookup_secondary_supers_table");
4336
4337 if (VerifySecondarySupers) {
4338 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4339 temp1, temp2, temp3);
4340 }
4341 }
4342
4343 // At runtime, return 0 in result if r_super_klass is a superclass of
4344 // r_sub_klass, otherwise return nonzero. Use this version of
4345 // lookup_secondary_supers_table() if you don't know ahead of time
4346 // which superclass will be searched for. Used by interpreter and
4347 // runtime stubs. It is larger and has somewhat greater latency than
4348 // the version above, which takes a constant super_klass_slot.
4349 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
4350 Register r_super_klass,
4351 Register temp1,
4352 Register temp2,
4353 Register temp3,
4354 Register temp4,
4355 Register result) {
4356 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4357 assert_different_registers(r_sub_klass, r_super_klass, rcx);
4358 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
4359
4360 Label L_fallthrough, L_success, L_failure;
4361
4362 BLOCK_COMMENT("lookup_secondary_supers_table {");
4363
4364 RegSetIterator<Register> available_regs = (temps - rcx).begin();
4365
4366 // FIXME. Once we are sure that all paths reaching this point really
4367 // do pass rcx as one of our temps we can get rid of the following
4368 // workaround.
4369 assert(temps.contains(rcx), "fix this code");
4370
4371 // We prefer to have our shift count in rcx. If rcx is one of our
4372 // temps, use it for slot. If not, pick any of our temps.
4373 Register slot;
4374 if (!temps.contains(rcx)) {
4375 slot = *available_regs++;
4376 } else {
4377 slot = rcx;
4378 }
4379
4380 const Register r_array_index = *available_regs++;
4381 const Register r_bitmap = *available_regs++;
4382
4383 // The logic above guarantees this property, but we state it here.
4384 assert_different_registers(r_array_index, r_bitmap, rcx);
4385
4386 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4387 movq(r_array_index, r_bitmap);
4388
4389 // First check the bitmap to see if super_klass might be present. If
4390 // the bit is zero, we are certain that super_klass is not one of
4391 // the secondary supers.
4392 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4393 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
4394 salq(r_array_index, slot);
4395
4396 testq(r_array_index, r_array_index);
4397 // We test the MSB of r_array_index, i.e. its sign bit
4398 jcc(Assembler::positive, L_failure);
4399
4400 const Register r_array_base = *available_regs++;
4401
4402 // Get the first array index that can contain super_klass into r_array_index.
4403 // Note: Clobbers r_array_base and slot.
4404 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
4405
4406 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4407
4408 // We will consult the secondary-super array.
4409 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4410
4411 // We're asserting that the first word in an Array<Klass*> is the
4412 // length, and the second word is the first word of the data. If
4413 // that ever changes, r_array_base will have to be adjusted here.
4414 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4415 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4416
4417 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4418 jccb(Assembler::equal, L_success);
4419
4420 // Restore slot to its true value
4421 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4422
4423 // Linear probe. Rotate the bitmap so that the next bit to test is
4424 // in Bit 1.
4425 rorq(r_bitmap, slot);
4426
4427 // Is there another entry to check? Consult the bitmap.
4428 btq(r_bitmap, 1);
4429 jccb(Assembler::carryClear, L_failure);
4430
4431 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4432 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4433 // Kills: r_array_length.
4434 // Returns: result.
4435 lookup_secondary_supers_table_slow_path(r_super_klass,
4436 r_array_base,
4437 r_array_index,
4438 r_bitmap,
4439 /*temp1*/result,
4440 /*temp2*/slot,
4441 &L_success,
4442 nullptr);
4443
4444 bind(L_failure);
4445 movq(result, 1);
4446 jmpb(L_fallthrough);
4447
4448 bind(L_success);
4449 xorq(result, result); // = 0
4450
4451 bind(L_fallthrough);
4452 BLOCK_COMMENT("} lookup_secondary_supers_table");
4453
4454 if (VerifySecondarySupers) {
4455 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4456 temp1, temp2, temp3);
4457 }
4458 }
4459
4460 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
4461 Label* L_success, Label* L_failure) {
4462 Label L_loop, L_fallthrough;
4463 {
4464 int label_nulls = 0;
4465 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4466 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4467 assert(label_nulls <= 1, "at most one null in the batch");
4468 }
4469 bind(L_loop);
4470 cmpq(value, Address(addr, count, Address::times_8));
4471 jcc(Assembler::equal, *L_success);
4472 addl(count, 1);
4473 cmpl(count, limit);
4474 jcc(Assembler::less, L_loop);
4475
4476 if (&L_fallthrough != L_failure) {
4477 jmp(*L_failure);
4478 }
4479 bind(L_fallthrough);
4480 }
4481
4482 // Called by code generated by check_klass_subtype_slow_path
4483 // above. This is called when there is a collision in the hashed
4484 // lookup in the secondary supers array.
4485 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
4486 Register r_array_base,
4487 Register r_array_index,
4488 Register r_bitmap,
4489 Register temp1,
4490 Register temp2,
4491 Label* L_success,
4492 Label* L_failure) {
4493 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
4494
4495 const Register
4496 r_array_length = temp1,
4497 r_sub_klass = noreg,
4498 result = noreg;
4499
4500 Label L_fallthrough;
4501 int label_nulls = 0;
4502 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4503 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4504 assert(label_nulls <= 1, "at most one null in the batch");
4505
4506 // Load the array length.
4507 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4508 // And adjust the array base to point to the data.
4509 // NB! Effectively increments current slot index by 1.
4510 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
4511 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4512
4513 // Linear probe
4514 Label L_huge;
4515
4516 // The bitmap is full to bursting.
4517 // Implicit invariant: BITMAP_FULL implies (length > 0)
4518 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
4519 jcc(Assembler::greater, L_huge);
4520
4521 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
4522 // current slot (at secondary_supers[r_array_index]) has not yet
4523 // been inspected, and r_array_index may be out of bounds if we
4524 // wrapped around the end of the array.
4525
4526 { // This is conventional linear probing, but instead of terminating
4527 // when a null entry is found in the table, we maintain a bitmap
4528 // in which a 0 indicates missing entries.
4529 // The check above guarantees there are 0s in the bitmap, so the loop
4530 // eventually terminates.
4531
4532 xorl(temp2, temp2); // = 0;
4533
4534 Label L_again;
4535 bind(L_again);
4536
4537 // Check for array wraparound.
4538 cmpl(r_array_index, r_array_length);
4539 cmovl(Assembler::greaterEqual, r_array_index, temp2);
4540
4541 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4542 jcc(Assembler::equal, *L_success);
4543
4544 // If the next bit in bitmap is zero, we're done.
4545 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
4546 jcc(Assembler::carryClear, *L_failure);
4547
4548 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
4549 addl(r_array_index, 1);
4550
4551 jmp(L_again);
4552 }
4553
4554 { // Degenerate case: more than 64 secondary supers.
4555 // FIXME: We could do something smarter here, maybe a vectorized
4556 // comparison or a binary search, but is that worth any added
4557 // complexity?
4558 bind(L_huge);
4559 xorl(r_array_index, r_array_index); // = 0
4560 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
4561 L_success,
4562 (&L_fallthrough != L_failure ? L_failure : nullptr));
4563
4564 bind(L_fallthrough);
4565 }
4566 }
4567
4568 struct VerifyHelperArguments {
4569 Klass* _super;
4570 Klass* _sub;
4571 intptr_t _linear_result;
4572 intptr_t _table_result;
4573 };
4574
4575 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
4576 Klass::on_secondary_supers_verification_failure(args->_super,
4577 args->_sub,
4578 args->_linear_result,
4579 args->_table_result,
4580 msg);
4581 }
4582
4583 // Make sure that the hashed lookup and a linear scan agree.
4584 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
4585 Register r_super_klass,
4586 Register result,
4587 Register temp1,
4588 Register temp2,
4589 Register temp3) {
4590 const Register
4591 r_array_index = temp1,
4592 r_array_length = temp2,
4593 r_array_base = temp3,
4594 r_bitmap = noreg;
4595
4596 BLOCK_COMMENT("verify_secondary_supers_table {");
4597
4598 Label L_success, L_failure, L_check, L_done;
4599
4600 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4601 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4602 // And adjust the array base to point to the data.
4603 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4604
4605 testl(r_array_length, r_array_length); // array_length == 0?
4606 jcc(Assembler::zero, L_failure);
4607
4608 movl(r_array_index, 0);
4609 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
4610 // fall through to L_failure
4611
4612 const Register linear_result = r_array_index; // reuse temp1
4613
4614 bind(L_failure); // not present
4615 movl(linear_result, 1);
4616 jmp(L_check);
4617
4618 bind(L_success); // present
4619 movl(linear_result, 0);
4620
4621 bind(L_check);
4622 cmpl(linear_result, result);
4623 jcc(Assembler::equal, L_done);
4624
4625 { // To avoid calling convention issues, build a record on the stack
4626 // and pass the pointer to that instead.
4627 push(result);
4628 push(linear_result);
4629 push(r_sub_klass);
4630 push(r_super_klass);
4631 movptr(c_rarg1, rsp);
4632 movptr(c_rarg0, (uintptr_t) "mismatch");
4633 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
4634 should_not_reach_here();
4635 }
4636 bind(L_done);
4637
4638 BLOCK_COMMENT("} verify_secondary_supers_table");
4639 }
4640
4641 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
4642
4643 void MacroAssembler::clinit_barrier(Register klass, Label* L_fast_path, Label* L_slow_path) {
4644 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
4645
4646 Label L_fallthrough;
4647 if (L_fast_path == nullptr) {
4648 L_fast_path = &L_fallthrough;
4649 } else if (L_slow_path == nullptr) {
4650 L_slow_path = &L_fallthrough;
4651 }
4652
4653 // Fast path check: class is fully initialized.
4654 // init_state needs acquire, but x86 is TSO, and so we are already good.
4655 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4656 jcc(Assembler::equal, *L_fast_path);
4657
4658 // Fast path check: current thread is initializer thread
4659 cmpptr(r15_thread, Address(klass, InstanceKlass::init_thread_offset()));
4660 if (L_slow_path == &L_fallthrough) {
4661 jcc(Assembler::equal, *L_fast_path);
4662 bind(*L_slow_path);
4663 } else if (L_fast_path == &L_fallthrough) {
4664 jcc(Assembler::notEqual, *L_slow_path);
4665 bind(*L_fast_path);
4666 } else {
4667 Unimplemented();
4668 }
4669 }
4670
4671 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4672 if (VM_Version::supports_cmov()) {
4673 cmovl(cc, dst, src);
4674 } else {
4675 Label L;
4676 jccb(negate_condition(cc), L);
4677 movl(dst, src);
4678 bind(L);
4679 }
4680 }
4681
4682 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4683 if (VM_Version::supports_cmov()) {
4684 cmovl(cc, dst, src);
4685 } else {
4686 Label L;
4687 jccb(negate_condition(cc), L);
4688 movl(dst, src);
4689 bind(L);
4690 }
4691 }
4692
4693 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
4694 if (!VerifyOops) return;
4695
4696 BLOCK_COMMENT("verify_oop {");
4697 push(rscratch1);
4698 push(rax); // save rax
4699 push(reg); // pass register argument
4700
4701 // Pass register number to verify_oop_subroutine
4702 const char* b = nullptr;
4703 {
4704 ResourceMark rm;
4705 stringStream ss;
4706 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
4707 b = code_string(ss.as_string());
4708 }
4709 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
4710 pushptr(buffer.addr(), rscratch1);
4711
4712 // call indirectly to solve generation ordering problem
4713 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4714 call(rax);
4715 // Caller pops the arguments (oop, message) and restores rax, r10
4716 BLOCK_COMMENT("} verify_oop");
4717 }
4718
4719 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
4720 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
4721 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
4722 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
4723 vpternlogd(dst, 0xFF, dst, dst, vector_len);
4724 } else if (VM_Version::supports_avx()) {
4725 vpcmpeqd(dst, dst, dst, vector_len);
4726 } else {
4727 pcmpeqd(dst, dst);
4728 }
4729 }
4730
4731 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4732 int extra_slot_offset) {
4733 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4734 int stackElementSize = Interpreter::stackElementSize;
4735 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4736 #ifdef ASSERT
4737 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4738 assert(offset1 - offset == stackElementSize, "correct arithmetic");
4739 #endif
4740 Register scale_reg = noreg;
4741 Address::ScaleFactor scale_factor = Address::no_scale;
4742 if (arg_slot.is_constant()) {
4743 offset += arg_slot.as_constant() * stackElementSize;
4744 } else {
4745 scale_reg = arg_slot.as_register();
4746 scale_factor = Address::times(stackElementSize);
4747 }
4748 offset += wordSize; // return PC is on stack
4749 return Address(rsp, scale_reg, scale_factor, offset);
4750 }
4751
4752 // Handle the receiver type profile update given the "recv" klass.
4753 //
4754 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
4755 // If there are no matching or claimable receiver entries in RD, updates
4756 // the polymorphic counter.
4757 //
4758 // This code expected to run by either the interpreter or JIT-ed code, without
4759 // extra synchronization. For safety, receiver cells are claimed atomically, which
4760 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
4761 // counter updates are not atomic.
4762 //
4763 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
4764 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
4765 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
4766 int poly_count_offset = in_bytes(CounterData::count_offset());
4767 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
4768 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
4769
4770 // Adjust for MDP offsets. Slots are pointer-sized, so is the global offset.
4771 assert(is_aligned(mdp_offset, BytesPerWord), "sanity");
4772 base_receiver_offset += mdp_offset;
4773 end_receiver_offset += mdp_offset;
4774 poly_count_offset += mdp_offset;
4775
4776 // Scale down to optimize encoding. Slots are pointer-sized.
4777 assert(is_aligned(base_receiver_offset, BytesPerWord), "sanity");
4778 assert(is_aligned(end_receiver_offset, BytesPerWord), "sanity");
4779 assert(is_aligned(poly_count_offset, BytesPerWord), "sanity");
4780 assert(is_aligned(receiver_step, BytesPerWord), "sanity");
4781 assert(is_aligned(receiver_to_count_step, BytesPerWord), "sanity");
4782 base_receiver_offset >>= LogBytesPerWord;
4783 end_receiver_offset >>= LogBytesPerWord;
4784 poly_count_offset >>= LogBytesPerWord;
4785 receiver_step >>= LogBytesPerWord;
4786 receiver_to_count_step >>= LogBytesPerWord;
4787
4788 #ifdef ASSERT
4789 // We are about to walk the MDO slots without asking for offsets.
4790 // Check that our math hits all the right spots.
4791 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
4792 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
4793 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
4794 int offset = base_receiver_offset + receiver_step*c;
4795 int count_offset = offset + receiver_to_count_step;
4796 assert((offset << LogBytesPerWord) == real_recv_offset, "receiver slot math");
4797 assert((count_offset << LogBytesPerWord) == real_count_offset, "receiver count math");
4798 }
4799 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
4800 assert(poly_count_offset << LogBytesPerWord == real_poly_count_offset, "poly counter math");
4801 #endif
4802
4803 // Corner case: no profile table. Increment poly counter and exit.
4804 if (ReceiverTypeData::row_limit() == 0) {
4805 addptr(Address(mdp, poly_count_offset, Address::times_ptr), DataLayout::counter_increment);
4806 return;
4807 }
4808
4809 Register offset = rscratch1;
4810
4811 Label L_loop_search_receiver, L_loop_search_empty;
4812 Label L_restart, L_found_recv, L_found_empty, L_polymorphic, L_count_update;
4813
4814 // The code here recognizes three major cases:
4815 // A. Fastest: receiver found in the table
4816 // B. Fast: no receiver in the table, and the table is full
4817 // C. Slow: no receiver in the table, free slots in the table
4818 //
4819 // The case A performance is most important, as perfectly-behaved code would end up
4820 // there, especially with larger TypeProfileWidth. The case B performance is
4821 // important as well, this is where bulk of code would land for normally megamorphic
4822 // cases. The case C performance is not essential, its job is to deal with installation
4823 // races, we optimize for code density instead. Case C needs to make sure that receiver
4824 // rows are only claimed once. This makes sure we never overwrite a row for another
4825 // receiver and never duplicate the receivers in the list, making profile type-accurate.
4826 //
4827 // It is very tempting to handle these cases in a single loop, and claim the first slot
4828 // without checking the rest of the table. But, profiling code should tolerate free slots
4829 // in the table, as class unloading can clear them. After such cleanup, the receiver
4830 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
4831 // to complete, before trying to install new slots. Splitting the code in several tight
4832 // loops also helpfully optimizes for cases A and B.
4833 //
4834 // This code is effectively:
4835 //
4836 // restart:
4837 // // Fastest: receiver is already installed
4838 // for (i = 0; i < receiver_count(); i++) {
4839 // if (receiver(i) == recv) goto found_recv(i);
4840 // }
4841 //
4842 // // Fast: no receiver, but profile is full
4843 // for (i = 0; i < receiver_count(); i++) {
4844 // if (receiver(i) == null) goto found_null(i);
4845 // }
4846 // goto polymorphic
4847 //
4848 // // Slow: try to install receiver
4849 // found_null(i):
4850 // CAS(&receiver(i), null, recv);
4851 // goto restart
4852 //
4853 // polymorphic:
4854 // count++;
4855 // return
4856 //
4857 // found_recv(i):
4858 // *receiver_count(i)++
4859 //
4860
4861 bind(L_restart);
4862
4863 // Fastest: receiver is already installed
4864 movptr(offset, base_receiver_offset);
4865 bind(L_loop_search_receiver);
4866 cmpptr(recv, Address(mdp, offset, Address::times_ptr));
4867 jccb(Assembler::equal, L_found_recv);
4868 addptr(offset, receiver_step);
4869 cmpptr(offset, end_receiver_offset);
4870 jccb(Assembler::notEqual, L_loop_search_receiver);
4871
4872 // Fast: no receiver, but profile is full
4873 movptr(offset, base_receiver_offset);
4874 bind(L_loop_search_empty);
4875 cmpptr(Address(mdp, offset, Address::times_ptr), NULL_WORD);
4876 jccb(Assembler::equal, L_found_empty);
4877 addptr(offset, receiver_step);
4878 cmpptr(offset, end_receiver_offset);
4879 jccb(Assembler::notEqual, L_loop_search_empty);
4880 jmpb(L_polymorphic);
4881
4882 // Slow: try to install receiver
4883 bind(L_found_empty);
4884
4885 // Atomically swing receiver slot: null -> recv.
4886 //
4887 // The update code uses CAS, which wants RAX register specifically, *and* it needs
4888 // other important registers untouched, as they form the address. Therefore, we need
4889 // to shift any important registers from RAX into some other spare register. If we
4890 // have a spare register, we are forced to save it on stack here.
4891
4892 Register spare_reg = noreg;
4893 Register shifted_mdp = mdp;
4894 Register shifted_recv = recv;
4895 if (recv == rax || mdp == rax) {
4896 spare_reg = (recv != rbx && mdp != rbx) ? rbx :
4897 (recv != rcx && mdp != rcx) ? rcx :
4898 rdx;
4899 assert_different_registers(mdp, recv, offset, spare_reg);
4900
4901 push(spare_reg);
4902 if (recv == rax) {
4903 movptr(spare_reg, recv);
4904 shifted_recv = spare_reg;
4905 } else {
4906 assert(mdp == rax, "Remaining case");
4907 movptr(spare_reg, mdp);
4908 shifted_mdp = spare_reg;
4909 }
4910 } else {
4911 push(rax);
4912 }
4913
4914 // None of the important registers are in RAX after this shuffle.
4915 assert_different_registers(rax, shifted_mdp, shifted_recv, offset);
4916
4917 xorptr(rax, rax);
4918 cmpxchgptr(shifted_recv, Address(shifted_mdp, offset, Address::times_ptr));
4919
4920 // Unshift registers.
4921 if (recv == rax || mdp == rax) {
4922 movptr(rax, spare_reg);
4923 pop(spare_reg);
4924 } else {
4925 pop(rax);
4926 }
4927
4928 // CAS success means the slot now has the receiver we want. CAS failure means
4929 // something had claimed the slot concurrently: it can be the same receiver we want,
4930 // or something else. Since this is a slow path, we can optimize for code density,
4931 // and just restart the search from the beginning.
4932 jmpb(L_restart);
4933
4934 // Counter updates:
4935
4936 // Increment polymorphic counter instead of receiver slot.
4937 bind(L_polymorphic);
4938 movptr(offset, poly_count_offset);
4939 jmpb(L_count_update);
4940
4941 // Found a receiver, convert its slot offset to corresponding count offset.
4942 bind(L_found_recv);
4943 addptr(offset, receiver_to_count_step);
4944
4945 bind(L_count_update);
4946 addptr(Address(mdp, offset, Address::times_ptr), DataLayout::counter_increment);
4947 }
4948
4949 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
4950 if (!VerifyOops) return;
4951
4952 push(rscratch1);
4953 push(rax); // save rax,
4954 // addr may contain rsp so we will have to adjust it based on the push
4955 // we just did (and on 64 bit we do two pushes)
4956 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4957 // stores rax into addr which is backwards of what was intended.
4958 if (addr.uses(rsp)) {
4959 lea(rax, addr);
4960 pushptr(Address(rax, 2 * BytesPerWord));
4961 } else {
4962 pushptr(addr);
4963 }
4964
4965 // Pass register number to verify_oop_subroutine
4966 const char* b = nullptr;
4967 {
4968 ResourceMark rm;
4969 stringStream ss;
4970 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
4971 b = code_string(ss.as_string());
4972 }
4973 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
4974 pushptr(buffer.addr(), rscratch1);
4975
4976 // call indirectly to solve generation ordering problem
4977 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4978 call(rax);
4979 // Caller pops the arguments (addr, message) and restores rax, r10.
4980 }
4981
4982 void MacroAssembler::verify_tlab() {
4983 #ifdef ASSERT
4984 if (UseTLAB && VerifyOops) {
4985 Label next, ok;
4986 Register t1 = rsi;
4987
4988 push(t1);
4989
4990 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
4991 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_start_offset())));
4992 jcc(Assembler::aboveEqual, next);
4993 STOP("assert(top >= start)");
4994 should_not_reach_here();
4995
4996 bind(next);
4997 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_end_offset())));
4998 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
4999 jcc(Assembler::aboveEqual, ok);
5000 STOP("assert(top <= end)");
5001 should_not_reach_here();
5002
5003 bind(ok);
5004 pop(t1);
5005 }
5006 #endif
5007 }
5008
5009 class ControlWord {
5010 public:
5011 int32_t _value;
5012
5013 int rounding_control() const { return (_value >> 10) & 3 ; }
5014 int precision_control() const { return (_value >> 8) & 3 ; }
5015 bool precision() const { return ((_value >> 5) & 1) != 0; }
5016 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5017 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5018 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5019 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5020 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5021
5022 void print() const {
5023 // rounding control
5024 const char* rc;
5025 switch (rounding_control()) {
5026 case 0: rc = "round near"; break;
5027 case 1: rc = "round down"; break;
5028 case 2: rc = "round up "; break;
5029 case 3: rc = "chop "; break;
5030 default:
5031 rc = nullptr; // silence compiler warnings
5032 fatal("Unknown rounding control: %d", rounding_control());
5033 };
5034 // precision control
5035 const char* pc;
5036 switch (precision_control()) {
5037 case 0: pc = "24 bits "; break;
5038 case 1: pc = "reserved"; break;
5039 case 2: pc = "53 bits "; break;
5040 case 3: pc = "64 bits "; break;
5041 default:
5042 pc = nullptr; // silence compiler warnings
5043 fatal("Unknown precision control: %d", precision_control());
5044 };
5045 // flags
5046 char f[9];
5047 f[0] = ' ';
5048 f[1] = ' ';
5049 f[2] = (precision ()) ? 'P' : 'p';
5050 f[3] = (underflow ()) ? 'U' : 'u';
5051 f[4] = (overflow ()) ? 'O' : 'o';
5052 f[5] = (zero_divide ()) ? 'Z' : 'z';
5053 f[6] = (denormalized()) ? 'D' : 'd';
5054 f[7] = (invalid ()) ? 'I' : 'i';
5055 f[8] = '\x0';
5056 // output
5057 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5058 }
5059
5060 };
5061
5062 class StatusWord {
5063 public:
5064 int32_t _value;
5065
5066 bool busy() const { return ((_value >> 15) & 1) != 0; }
5067 bool C3() const { return ((_value >> 14) & 1) != 0; }
5068 bool C2() const { return ((_value >> 10) & 1) != 0; }
5069 bool C1() const { return ((_value >> 9) & 1) != 0; }
5070 bool C0() const { return ((_value >> 8) & 1) != 0; }
5071 int top() const { return (_value >> 11) & 7 ; }
5072 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5073 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5074 bool precision() const { return ((_value >> 5) & 1) != 0; }
5075 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5076 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5077 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5078 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5079 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5080
5081 void print() const {
5082 // condition codes
5083 char c[5];
5084 c[0] = (C3()) ? '3' : '-';
5085 c[1] = (C2()) ? '2' : '-';
5086 c[2] = (C1()) ? '1' : '-';
5087 c[3] = (C0()) ? '0' : '-';
5088 c[4] = '\x0';
5089 // flags
5090 char f[9];
5091 f[0] = (error_status()) ? 'E' : '-';
5092 f[1] = (stack_fault ()) ? 'S' : '-';
5093 f[2] = (precision ()) ? 'P' : '-';
5094 f[3] = (underflow ()) ? 'U' : '-';
5095 f[4] = (overflow ()) ? 'O' : '-';
5096 f[5] = (zero_divide ()) ? 'Z' : '-';
5097 f[6] = (denormalized()) ? 'D' : '-';
5098 f[7] = (invalid ()) ? 'I' : '-';
5099 f[8] = '\x0';
5100 // output
5101 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5102 }
5103
5104 };
5105
5106 class TagWord {
5107 public:
5108 int32_t _value;
5109
5110 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5111
5112 void print() const {
5113 printf("%04x", _value & 0xFFFF);
5114 }
5115
5116 };
5117
5118 class FPU_Register {
5119 public:
5120 int32_t _m0;
5121 int32_t _m1;
5122 int16_t _ex;
5123
5124 bool is_indefinite() const {
5125 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5126 }
5127
5128 void print() const {
5129 char sign = (_ex < 0) ? '-' : '+';
5130 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5131 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5132 };
5133
5134 };
5135
5136 class FPU_State {
5137 public:
5138 enum {
5139 register_size = 10,
5140 number_of_registers = 8,
5141 register_mask = 7
5142 };
5143
5144 ControlWord _control_word;
5145 StatusWord _status_word;
5146 TagWord _tag_word;
5147 int32_t _error_offset;
5148 int32_t _error_selector;
5149 int32_t _data_offset;
5150 int32_t _data_selector;
5151 int8_t _register[register_size * number_of_registers];
5152
5153 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5154 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5155
5156 const char* tag_as_string(int tag) const {
5157 switch (tag) {
5158 case 0: return "valid";
5159 case 1: return "zero";
5160 case 2: return "special";
5161 case 3: return "empty";
5162 }
5163 ShouldNotReachHere();
5164 return nullptr;
5165 }
5166
5167 void print() const {
5168 // print computation registers
5169 { int t = _status_word.top();
5170 for (int i = 0; i < number_of_registers; i++) {
5171 int j = (i - t) & register_mask;
5172 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5173 st(j)->print();
5174 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5175 }
5176 }
5177 printf("\n");
5178 // print control registers
5179 printf("ctrl = "); _control_word.print(); printf("\n");
5180 printf("stat = "); _status_word .print(); printf("\n");
5181 printf("tags = "); _tag_word .print(); printf("\n");
5182 }
5183
5184 };
5185
5186 class Flag_Register {
5187 public:
5188 int32_t _value;
5189
5190 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5191 bool direction() const { return ((_value >> 10) & 1) != 0; }
5192 bool sign() const { return ((_value >> 7) & 1) != 0; }
5193 bool zero() const { return ((_value >> 6) & 1) != 0; }
5194 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5195 bool parity() const { return ((_value >> 2) & 1) != 0; }
5196 bool carry() const { return ((_value >> 0) & 1) != 0; }
5197
5198 void print() const {
5199 // flags
5200 char f[8];
5201 f[0] = (overflow ()) ? 'O' : '-';
5202 f[1] = (direction ()) ? 'D' : '-';
5203 f[2] = (sign ()) ? 'S' : '-';
5204 f[3] = (zero ()) ? 'Z' : '-';
5205 f[4] = (auxiliary_carry()) ? 'A' : '-';
5206 f[5] = (parity ()) ? 'P' : '-';
5207 f[6] = (carry ()) ? 'C' : '-';
5208 f[7] = '\x0';
5209 // output
5210 printf("%08x flags = %s", _value, f);
5211 }
5212
5213 };
5214
5215 class IU_Register {
5216 public:
5217 int32_t _value;
5218
5219 void print() const {
5220 printf("%08x %11d", _value, _value);
5221 }
5222
5223 };
5224
5225 class IU_State {
5226 public:
5227 Flag_Register _eflags;
5228 IU_Register _rdi;
5229 IU_Register _rsi;
5230 IU_Register _rbp;
5231 IU_Register _rsp;
5232 IU_Register _rbx;
5233 IU_Register _rdx;
5234 IU_Register _rcx;
5235 IU_Register _rax;
5236
5237 void print() const {
5238 // computation registers
5239 printf("rax, = "); _rax.print(); printf("\n");
5240 printf("rbx, = "); _rbx.print(); printf("\n");
5241 printf("rcx = "); _rcx.print(); printf("\n");
5242 printf("rdx = "); _rdx.print(); printf("\n");
5243 printf("rdi = "); _rdi.print(); printf("\n");
5244 printf("rsi = "); _rsi.print(); printf("\n");
5245 printf("rbp, = "); _rbp.print(); printf("\n");
5246 printf("rsp = "); _rsp.print(); printf("\n");
5247 printf("\n");
5248 // control registers
5249 printf("flgs = "); _eflags.print(); printf("\n");
5250 }
5251 };
5252
5253
5254 class CPU_State {
5255 public:
5256 FPU_State _fpu_state;
5257 IU_State _iu_state;
5258
5259 void print() const {
5260 printf("--------------------------------------------------\n");
5261 _iu_state .print();
5262 printf("\n");
5263 _fpu_state.print();
5264 printf("--------------------------------------------------\n");
5265 }
5266
5267 };
5268
5269
5270 static void _print_CPU_state(CPU_State* state) {
5271 state->print();
5272 };
5273
5274
5275 void MacroAssembler::print_CPU_state() {
5276 push_CPU_state();
5277 push(rsp); // pass CPU state
5278 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5279 addptr(rsp, wordSize); // discard argument
5280 pop_CPU_state();
5281 }
5282
5283 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5284 // Either restore the MXCSR register after returning from the JNI Call
5285 // or verify that it wasn't changed (with -Xcheck:jni flag).
5286 if (VM_Version::supports_sse()) {
5287 if (RestoreMXCSROnJNICalls) {
5288 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5289 } else if (CheckJNICalls) {
5290 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5291 }
5292 }
5293 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5294 vzeroupper();
5295 }
5296
5297 // ((OopHandle)result).resolve();
5298 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5299 assert_different_registers(result, tmp);
5300
5301 // Only 64 bit platforms support GCs that require a tmp register
5302 // Only IN_HEAP loads require a thread_tmp register
5303 // OopHandle::resolve is an indirection like jobject.
5304 access_load_at(T_OBJECT, IN_NATIVE,
5305 result, Address(result, 0), tmp);
5306 }
5307
5308 // ((WeakHandle)result).resolve();
5309 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5310 assert_different_registers(rresult, rtmp);
5311 Label resolved;
5312
5313 // A null weak handle resolves to null.
5314 cmpptr(rresult, 0);
5315 jcc(Assembler::equal, resolved);
5316
5317 // Only 64 bit platforms support GCs that require a tmp register
5318 // Only IN_HEAP loads require a thread_tmp register
5319 // WeakHandle::resolve is an indirection like jweak.
5320 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5321 rresult, Address(rresult, 0), rtmp);
5322 bind(resolved);
5323 }
5324
5325 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5326 // get mirror
5327 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5328 load_method_holder(mirror, method);
5329 movptr(mirror, Address(mirror, mirror_offset));
5330 resolve_oop_handle(mirror, tmp);
5331 }
5332
5333 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5334 load_method_holder(rresult, rmethod);
5335 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5336 }
5337
5338 void MacroAssembler::load_method_holder(Register holder, Register method) {
5339 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5340 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5341 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5342 }
5343
5344 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5345 assert(UseCompactObjectHeaders, "expect compact object headers");
5346 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5347 shrq(dst, markWord::klass_shift);
5348 }
5349
5350 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5351 assert_different_registers(src, tmp);
5352 assert_different_registers(dst, tmp);
5353
5354 if (UseCompactObjectHeaders) {
5355 load_narrow_klass_compact(dst, src);
5356 decode_klass_not_null(dst, tmp);
5357 } else if (UseCompressedClassPointers) {
5358 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5359 decode_klass_not_null(dst, tmp);
5360 } else {
5361 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5362 }
5363 }
5364
5365 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5366 assert(!UseCompactObjectHeaders, "not with compact headers");
5367 assert_different_registers(src, tmp);
5368 assert_different_registers(dst, tmp);
5369 if (UseCompressedClassPointers) {
5370 encode_klass_not_null(src, tmp);
5371 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5372 } else {
5373 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5374 }
5375 }
5376
5377 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
5378 if (UseCompactObjectHeaders) {
5379 assert(tmp != noreg, "need tmp");
5380 assert_different_registers(klass, obj, tmp);
5381 load_narrow_klass_compact(tmp, obj);
5382 cmpl(klass, tmp);
5383 } else if (UseCompressedClassPointers) {
5384 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5385 } else {
5386 cmpptr(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5387 }
5388 }
5389
5390 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5391 if (UseCompactObjectHeaders) {
5392 assert(tmp2 != noreg, "need tmp2");
5393 assert_different_registers(obj1, obj2, tmp1, tmp2);
5394 load_narrow_klass_compact(tmp1, obj1);
5395 load_narrow_klass_compact(tmp2, obj2);
5396 cmpl(tmp1, tmp2);
5397 } else if (UseCompressedClassPointers) {
5398 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5399 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5400 } else {
5401 movptr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5402 cmpptr(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5403 }
5404 }
5405
5406 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5407 Register tmp1) {
5408 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5409 decorators = AccessInternal::decorator_fixup(decorators, type);
5410 bool as_raw = (decorators & AS_RAW) != 0;
5411 if (as_raw) {
5412 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1);
5413 } else {
5414 bs->load_at(this, decorators, type, dst, src, tmp1);
5415 }
5416 }
5417
5418 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5419 Register tmp1, Register tmp2, Register tmp3) {
5420 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5421 decorators = AccessInternal::decorator_fixup(decorators, type);
5422 bool as_raw = (decorators & AS_RAW) != 0;
5423 if (as_raw) {
5424 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5425 } else {
5426 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5427 }
5428 }
5429
5430 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5431 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1);
5432 }
5433
5434 // Doesn't do verification, generates fixed size code
5435 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5436 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1);
5437 }
5438
5439 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5440 Register tmp2, Register tmp3, DecoratorSet decorators) {
5441 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5442 }
5443
5444 // Used for storing nulls.
5445 void MacroAssembler::store_heap_oop_null(Address dst) {
5446 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5447 }
5448
5449 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5450 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
5451 if (UseCompressedClassPointers) {
5452 // Store to klass gap in destination
5453 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5454 }
5455 }
5456
5457 #ifdef ASSERT
5458 void MacroAssembler::verify_heapbase(const char* msg) {
5459 assert (UseCompressedOops, "should be compressed");
5460 assert (Universe::heap() != nullptr, "java heap should be initialized");
5461 if (CheckCompressedOops) {
5462 Label ok;
5463 ExternalAddress src2(CompressedOops::base_addr());
5464 const bool is_src2_reachable = reachable(src2);
5465 if (!is_src2_reachable) {
5466 push(rscratch1); // cmpptr trashes rscratch1
5467 }
5468 cmpptr(r12_heapbase, src2, rscratch1);
5469 jcc(Assembler::equal, ok);
5470 STOP(msg);
5471 bind(ok);
5472 if (!is_src2_reachable) {
5473 pop(rscratch1);
5474 }
5475 }
5476 }
5477 #endif
5478
5479 // Algorithm must match oop.inline.hpp encode_heap_oop.
5480 void MacroAssembler::encode_heap_oop(Register r) {
5481 #ifdef ASSERT
5482 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5483 #endif
5484 verify_oop_msg(r, "broken oop in encode_heap_oop");
5485 if (CompressedOops::base() == nullptr) {
5486 if (CompressedOops::shift() != 0) {
5487 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5488 shrq(r, LogMinObjAlignmentInBytes);
5489 }
5490 return;
5491 }
5492 testq(r, r);
5493 cmovq(Assembler::equal, r, r12_heapbase);
5494 subq(r, r12_heapbase);
5495 shrq(r, LogMinObjAlignmentInBytes);
5496 }
5497
5498 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5499 #ifdef ASSERT
5500 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5501 if (CheckCompressedOops) {
5502 Label ok;
5503 testq(r, r);
5504 jcc(Assembler::notEqual, ok);
5505 STOP("null oop passed to encode_heap_oop_not_null");
5506 bind(ok);
5507 }
5508 #endif
5509 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5510 if (CompressedOops::base() != nullptr) {
5511 subq(r, r12_heapbase);
5512 }
5513 if (CompressedOops::shift() != 0) {
5514 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5515 shrq(r, LogMinObjAlignmentInBytes);
5516 }
5517 }
5518
5519 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5520 #ifdef ASSERT
5521 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5522 if (CheckCompressedOops) {
5523 Label ok;
5524 testq(src, src);
5525 jcc(Assembler::notEqual, ok);
5526 STOP("null oop passed to encode_heap_oop_not_null2");
5527 bind(ok);
5528 }
5529 #endif
5530 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5531 if (dst != src) {
5532 movq(dst, src);
5533 }
5534 if (CompressedOops::base() != nullptr) {
5535 subq(dst, r12_heapbase);
5536 }
5537 if (CompressedOops::shift() != 0) {
5538 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5539 shrq(dst, LogMinObjAlignmentInBytes);
5540 }
5541 }
5542
5543 void MacroAssembler::decode_heap_oop(Register r) {
5544 #ifdef ASSERT
5545 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5546 #endif
5547 if (CompressedOops::base() == nullptr) {
5548 if (CompressedOops::shift() != 0) {
5549 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5550 shlq(r, LogMinObjAlignmentInBytes);
5551 }
5552 } else {
5553 Label done;
5554 shlq(r, LogMinObjAlignmentInBytes);
5555 jccb(Assembler::equal, done);
5556 addq(r, r12_heapbase);
5557 bind(done);
5558 }
5559 verify_oop_msg(r, "broken oop in decode_heap_oop");
5560 }
5561
5562 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5563 // Note: it will change flags
5564 assert (UseCompressedOops, "should only be used for compressed headers");
5565 assert (Universe::heap() != nullptr, "java heap should be initialized");
5566 // Cannot assert, unverified entry point counts instructions (see .ad file)
5567 // vtableStubs also counts instructions in pd_code_size_limit.
5568 // Also do not verify_oop as this is called by verify_oop.
5569 if (CompressedOops::shift() != 0) {
5570 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5571 shlq(r, LogMinObjAlignmentInBytes);
5572 if (CompressedOops::base() != nullptr) {
5573 addq(r, r12_heapbase);
5574 }
5575 } else {
5576 assert (CompressedOops::base() == nullptr, "sanity");
5577 }
5578 }
5579
5580 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5581 // Note: it will change flags
5582 assert (UseCompressedOops, "should only be used for compressed headers");
5583 assert (Universe::heap() != nullptr, "java heap should be initialized");
5584 // Cannot assert, unverified entry point counts instructions (see .ad file)
5585 // vtableStubs also counts instructions in pd_code_size_limit.
5586 // Also do not verify_oop as this is called by verify_oop.
5587 if (CompressedOops::shift() != 0) {
5588 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5589 if (LogMinObjAlignmentInBytes == Address::times_8) {
5590 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5591 } else {
5592 if (dst != src) {
5593 movq(dst, src);
5594 }
5595 shlq(dst, LogMinObjAlignmentInBytes);
5596 if (CompressedOops::base() != nullptr) {
5597 addq(dst, r12_heapbase);
5598 }
5599 }
5600 } else {
5601 assert (CompressedOops::base() == nullptr, "sanity");
5602 if (dst != src) {
5603 movq(dst, src);
5604 }
5605 }
5606 }
5607
5608 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
5609 BLOCK_COMMENT("encode_klass_not_null {");
5610 assert_different_registers(r, tmp);
5611 if (CompressedKlassPointers::base() != nullptr) {
5612 if (AOTCodeCache::is_on_for_dump()) {
5613 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5614 } else {
5615 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5616 }
5617 subq(r, tmp);
5618 }
5619 if (CompressedKlassPointers::shift() != 0) {
5620 shrq(r, CompressedKlassPointers::shift());
5621 }
5622 BLOCK_COMMENT("} encode_klass_not_null");
5623 }
5624
5625 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
5626 BLOCK_COMMENT("encode_and_move_klass_not_null {");
5627 assert_different_registers(src, dst);
5628 if (CompressedKlassPointers::base() != nullptr) {
5629 movptr(dst, -(intptr_t)CompressedKlassPointers::base());
5630 addq(dst, src);
5631 } else {
5632 movptr(dst, src);
5633 }
5634 if (CompressedKlassPointers::shift() != 0) {
5635 shrq(dst, CompressedKlassPointers::shift());
5636 }
5637 BLOCK_COMMENT("} encode_and_move_klass_not_null");
5638 }
5639
5640 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
5641 BLOCK_COMMENT("decode_klass_not_null {");
5642 assert_different_registers(r, tmp);
5643 // Note: it will change flags
5644 assert(UseCompressedClassPointers, "should only be used for compressed headers");
5645 // Cannot assert, unverified entry point counts instructions (see .ad file)
5646 // vtableStubs also counts instructions in pd_code_size_limit.
5647 // Also do not verify_oop as this is called by verify_oop.
5648 if (CompressedKlassPointers::shift() != 0) {
5649 shlq(r, CompressedKlassPointers::shift());
5650 }
5651 if (CompressedKlassPointers::base() != nullptr) {
5652 if (AOTCodeCache::is_on_for_dump()) {
5653 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5654 } else {
5655 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5656 }
5657 addq(r, tmp);
5658 }
5659 BLOCK_COMMENT("} decode_klass_not_null");
5660 }
5661
5662 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
5663 BLOCK_COMMENT("decode_and_move_klass_not_null {");
5664 assert_different_registers(src, dst);
5665 // Note: it will change flags
5666 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5667 // Cannot assert, unverified entry point counts instructions (see .ad file)
5668 // vtableStubs also counts instructions in pd_code_size_limit.
5669 // Also do not verify_oop as this is called by verify_oop.
5670
5671 if (CompressedKlassPointers::base() == nullptr &&
5672 CompressedKlassPointers::shift() == 0) {
5673 // The best case scenario is that there is no base or shift. Then it is already
5674 // a pointer that needs nothing but a register rename.
5675 movl(dst, src);
5676 } else {
5677 if (CompressedKlassPointers::shift() <= Address::times_8) {
5678 if (CompressedKlassPointers::base() != nullptr) {
5679 movptr(dst, (intptr_t)CompressedKlassPointers::base());
5680 } else {
5681 xorq(dst, dst);
5682 }
5683 if (CompressedKlassPointers::shift() != 0) {
5684 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
5685 leaq(dst, Address(dst, src, Address::times_8, 0));
5686 } else {
5687 addq(dst, src);
5688 }
5689 } else {
5690 if (CompressedKlassPointers::base() != nullptr) {
5691 const intptr_t base_right_shifted =
5692 (intptr_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5693 movptr(dst, base_right_shifted);
5694 } else {
5695 xorq(dst, dst);
5696 }
5697 addq(dst, src);
5698 shlq(dst, CompressedKlassPointers::shift());
5699 }
5700 }
5701 BLOCK_COMMENT("} decode_and_move_klass_not_null");
5702 }
5703
5704 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5705 assert (UseCompressedOops, "should only be used for compressed headers");
5706 assert (Universe::heap() != nullptr, "java heap should be initialized");
5707 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5708 int oop_index = oop_recorder()->find_index(obj);
5709 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5710 mov_narrow_oop(dst, oop_index, rspec);
5711 }
5712
5713 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5714 assert (UseCompressedOops, "should only be used for compressed headers");
5715 assert (Universe::heap() != nullptr, "java heap should be initialized");
5716 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5717 int oop_index = oop_recorder()->find_index(obj);
5718 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5719 mov_narrow_oop(dst, oop_index, rspec);
5720 }
5721
5722 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5723 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5724 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5725 int klass_index = oop_recorder()->find_index(k);
5726 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5727 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5728 }
5729
5730 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5731 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5732 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5733 int klass_index = oop_recorder()->find_index(k);
5734 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5735 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5736 }
5737
5738 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5739 assert (UseCompressedOops, "should only be used for compressed headers");
5740 assert (Universe::heap() != nullptr, "java heap should be initialized");
5741 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5742 int oop_index = oop_recorder()->find_index(obj);
5743 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5744 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5745 }
5746
5747 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5748 assert (UseCompressedOops, "should only be used for compressed headers");
5749 assert (Universe::heap() != nullptr, "java heap should be initialized");
5750 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5751 int oop_index = oop_recorder()->find_index(obj);
5752 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5753 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5754 }
5755
5756 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5757 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5758 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5759 int klass_index = oop_recorder()->find_index(k);
5760 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5761 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5762 }
5763
5764 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5765 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5766 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5767 int klass_index = oop_recorder()->find_index(k);
5768 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5769 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5770 }
5771
5772 void MacroAssembler::reinit_heapbase() {
5773 if (UseCompressedOops) {
5774 if (Universe::heap() != nullptr) {
5775 if (CompressedOops::base() == nullptr) {
5776 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5777 } else {
5778 mov64(r12_heapbase, (int64_t)CompressedOops::base());
5779 }
5780 } else {
5781 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
5782 }
5783 }
5784 }
5785
5786 #if COMPILER2_OR_JVMCI
5787
5788 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
5789 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5790 // cnt - number of qwords (8-byte words).
5791 // base - start address, qword aligned.
5792 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5793 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
5794 if (use64byteVector) {
5795 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
5796 } else if (MaxVectorSize >= 32) {
5797 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5798 } else {
5799 pxor(xtmp, xtmp);
5800 }
5801 jmp(L_zero_64_bytes);
5802
5803 BIND(L_loop);
5804 if (MaxVectorSize >= 32) {
5805 fill64(base, 0, xtmp, use64byteVector);
5806 } else {
5807 movdqu(Address(base, 0), xtmp);
5808 movdqu(Address(base, 16), xtmp);
5809 movdqu(Address(base, 32), xtmp);
5810 movdqu(Address(base, 48), xtmp);
5811 }
5812 addptr(base, 64);
5813
5814 BIND(L_zero_64_bytes);
5815 subptr(cnt, 8);
5816 jccb(Assembler::greaterEqual, L_loop);
5817
5818 // Copy trailing 64 bytes
5819 if (use64byteVector) {
5820 addptr(cnt, 8);
5821 jccb(Assembler::equal, L_end);
5822 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
5823 jmp(L_end);
5824 } else {
5825 addptr(cnt, 4);
5826 jccb(Assembler::less, L_tail);
5827 if (MaxVectorSize >= 32) {
5828 vmovdqu(Address(base, 0), xtmp);
5829 } else {
5830 movdqu(Address(base, 0), xtmp);
5831 movdqu(Address(base, 16), xtmp);
5832 }
5833 }
5834 addptr(base, 32);
5835 subptr(cnt, 4);
5836
5837 BIND(L_tail);
5838 addptr(cnt, 4);
5839 jccb(Assembler::lessEqual, L_end);
5840 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
5841 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
5842 } else {
5843 decrement(cnt);
5844
5845 BIND(L_sloop);
5846 movq(Address(base, 0), xtmp);
5847 addptr(base, 8);
5848 decrement(cnt);
5849 jccb(Assembler::greaterEqual, L_sloop);
5850 }
5851 BIND(L_end);
5852 }
5853
5854 // Clearing constant sized memory using YMM/ZMM registers.
5855 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5856 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
5857 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
5858
5859 int vector64_count = (cnt & (~0x7)) >> 3;
5860 cnt = cnt & 0x7;
5861 const int fill64_per_loop = 4;
5862 const int max_unrolled_fill64 = 8;
5863
5864 // 64 byte initialization loop.
5865 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
5866 int start64 = 0;
5867 if (vector64_count > max_unrolled_fill64) {
5868 Label LOOP;
5869 Register index = rtmp;
5870
5871 start64 = vector64_count - (vector64_count % fill64_per_loop);
5872
5873 movl(index, 0);
5874 BIND(LOOP);
5875 for (int i = 0; i < fill64_per_loop; i++) {
5876 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
5877 }
5878 addl(index, fill64_per_loop * 64);
5879 cmpl(index, start64 * 64);
5880 jccb(Assembler::less, LOOP);
5881 }
5882 for (int i = start64; i < vector64_count; i++) {
5883 fill64(base, i * 64, xtmp, use64byteVector);
5884 }
5885
5886 // Clear remaining 64 byte tail.
5887 int disp = vector64_count * 64;
5888 if (cnt) {
5889 switch (cnt) {
5890 case 1:
5891 movq(Address(base, disp), xtmp);
5892 break;
5893 case 2:
5894 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
5895 break;
5896 case 3:
5897 movl(rtmp, 0x7);
5898 kmovwl(mask, rtmp);
5899 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
5900 break;
5901 case 4:
5902 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
5903 break;
5904 case 5:
5905 if (use64byteVector) {
5906 movl(rtmp, 0x1F);
5907 kmovwl(mask, rtmp);
5908 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
5909 } else {
5910 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
5911 movq(Address(base, disp + 32), xtmp);
5912 }
5913 break;
5914 case 6:
5915 if (use64byteVector) {
5916 movl(rtmp, 0x3F);
5917 kmovwl(mask, rtmp);
5918 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
5919 } else {
5920 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
5921 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
5922 }
5923 break;
5924 case 7:
5925 if (use64byteVector) {
5926 movl(rtmp, 0x7F);
5927 kmovwl(mask, rtmp);
5928 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
5929 } else {
5930 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
5931 movl(rtmp, 0x7);
5932 kmovwl(mask, rtmp);
5933 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
5934 }
5935 break;
5936 default:
5937 fatal("Unexpected length : %d\n",cnt);
5938 break;
5939 }
5940 }
5941 }
5942
5943 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
5944 bool is_large, KRegister mask) {
5945 // cnt - number of qwords (8-byte words).
5946 // base - start address, qword aligned.
5947 // is_large - if optimizers know cnt is larger than InitArrayShortSize
5948 assert(base==rdi, "base register must be edi for rep stos");
5949 assert(tmp==rax, "tmp register must be eax for rep stos");
5950 assert(cnt==rcx, "cnt register must be ecx for rep stos");
5951 assert(InitArrayShortSize % BytesPerLong == 0,
5952 "InitArrayShortSize should be the multiple of BytesPerLong");
5953
5954 Label DONE;
5955 if (!is_large || !UseXMMForObjInit) {
5956 xorptr(tmp, tmp);
5957 }
5958
5959 if (!is_large) {
5960 Label LOOP, LONG;
5961 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
5962 jccb(Assembler::greater, LONG);
5963
5964 decrement(cnt);
5965 jccb(Assembler::negative, DONE); // Zero length
5966
5967 // Use individual pointer-sized stores for small counts:
5968 BIND(LOOP);
5969 movptr(Address(base, cnt, Address::times_ptr), tmp);
5970 decrement(cnt);
5971 jccb(Assembler::greaterEqual, LOOP);
5972 jmpb(DONE);
5973
5974 BIND(LONG);
5975 }
5976
5977 // Use longer rep-prefixed ops for non-small counts:
5978 if (UseFastStosb) {
5979 shlptr(cnt, 3); // convert to number of bytes
5980 rep_stosb();
5981 } else if (UseXMMForObjInit) {
5982 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
5983 } else {
5984 rep_stos();
5985 }
5986
5987 BIND(DONE);
5988 }
5989
5990 #endif //COMPILER2_OR_JVMCI
5991
5992
5993 void MacroAssembler::generate_fill(BasicType t, bool aligned,
5994 Register to, Register value, Register count,
5995 Register rtmp, XMMRegister xtmp) {
5996 ShortBranchVerifier sbv(this);
5997 assert_different_registers(to, value, count, rtmp);
5998 Label L_exit;
5999 Label L_fill_2_bytes, L_fill_4_bytes;
6000
6001 #if defined(COMPILER2)
6002 if(MaxVectorSize >=32 &&
6003 VM_Version::supports_avx512vlbw() &&
6004 VM_Version::supports_bmi2()) {
6005 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6006 return;
6007 }
6008 #endif
6009
6010 int shift = -1;
6011 switch (t) {
6012 case T_BYTE:
6013 shift = 2;
6014 break;
6015 case T_SHORT:
6016 shift = 1;
6017 break;
6018 case T_INT:
6019 shift = 0;
6020 break;
6021 default: ShouldNotReachHere();
6022 }
6023
6024 if (t == T_BYTE) {
6025 andl(value, 0xff);
6026 movl(rtmp, value);
6027 shll(rtmp, 8);
6028 orl(value, rtmp);
6029 }
6030 if (t == T_SHORT) {
6031 andl(value, 0xffff);
6032 }
6033 if (t == T_BYTE || t == T_SHORT) {
6034 movl(rtmp, value);
6035 shll(rtmp, 16);
6036 orl(value, rtmp);
6037 }
6038
6039 cmpptr(count, 8 << shift); // Short arrays (< 32 bytes) fill by element
6040 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6041 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6042 Label L_skip_align2;
6043 // align source address at 4 bytes address boundary
6044 if (t == T_BYTE) {
6045 Label L_skip_align1;
6046 // One byte misalignment happens only for byte arrays
6047 testptr(to, 1);
6048 jccb(Assembler::zero, L_skip_align1);
6049 movb(Address(to, 0), value);
6050 increment(to);
6051 decrement(count);
6052 BIND(L_skip_align1);
6053 }
6054 // Two bytes misalignment happens only for byte and short (char) arrays
6055 testptr(to, 2);
6056 jccb(Assembler::zero, L_skip_align2);
6057 movw(Address(to, 0), value);
6058 addptr(to, 2);
6059 subptr(count, 1<<(shift-1));
6060 BIND(L_skip_align2);
6061 }
6062 {
6063 Label L_fill_32_bytes;
6064 if (!UseUnalignedLoadStores) {
6065 // align to 8 bytes, we know we are 4 byte aligned to start
6066 testptr(to, 4);
6067 jccb(Assembler::zero, L_fill_32_bytes);
6068 movl(Address(to, 0), value);
6069 addptr(to, 4);
6070 subptr(count, 1<<shift);
6071 }
6072 BIND(L_fill_32_bytes);
6073 {
6074 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6075 movdl(xtmp, value);
6076 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6077 Label L_check_fill_32_bytes;
6078 if (UseAVX > 2) {
6079 // Fill 64-byte chunks
6080 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6081
6082 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
6083 cmpptr(count, VM_Version::avx3_threshold());
6084 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6085
6086 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6087
6088 subptr(count, 16 << shift);
6089 jcc(Assembler::less, L_check_fill_32_bytes);
6090 align(16);
6091
6092 BIND(L_fill_64_bytes_loop_avx3);
6093 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6094 addptr(to, 64);
6095 subptr(count, 16 << shift);
6096 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6097 jmpb(L_check_fill_32_bytes);
6098
6099 BIND(L_check_fill_64_bytes_avx2);
6100 }
6101 // Fill 64-byte chunks
6102 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6103
6104 subptr(count, 16 << shift);
6105 jcc(Assembler::less, L_check_fill_32_bytes);
6106
6107 // align data for 64-byte chunks
6108 Label L_fill_64_bytes_loop, L_align_64_bytes_loop;
6109 if (EnableX86ECoreOpts) {
6110 // align 'big' arrays to cache lines to minimize split_stores
6111 cmpptr(count, 96 << shift);
6112 jcc(Assembler::below, L_fill_64_bytes_loop);
6113
6114 // Find the bytes needed for alignment
6115 movptr(rtmp, to);
6116 andptr(rtmp, 0x1c);
6117 jcc(Assembler::zero, L_fill_64_bytes_loop);
6118 negptr(rtmp); // number of bytes to fill 32-rtmp. it filled by 2 mov by 32
6119 addptr(rtmp, 32);
6120 shrptr(rtmp, 2 - shift);// get number of elements from bytes
6121 subptr(count, rtmp); // adjust count by number of elements
6122
6123 align(16);
6124 BIND(L_align_64_bytes_loop);
6125 movdl(Address(to, 0), xtmp);
6126 addptr(to, 4);
6127 subptr(rtmp, 1 << shift);
6128 jcc(Assembler::greater, L_align_64_bytes_loop);
6129 }
6130
6131 align(16);
6132 BIND(L_fill_64_bytes_loop);
6133 vmovdqu(Address(to, 0), xtmp);
6134 vmovdqu(Address(to, 32), xtmp);
6135 addptr(to, 64);
6136 subptr(count, 16 << shift);
6137 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6138
6139 align(16);
6140 BIND(L_check_fill_32_bytes);
6141 addptr(count, 8 << shift);
6142 jccb(Assembler::less, L_check_fill_8_bytes);
6143 vmovdqu(Address(to, 0), xtmp);
6144 addptr(to, 32);
6145 subptr(count, 8 << shift);
6146
6147 BIND(L_check_fill_8_bytes);
6148 // clean upper bits of YMM registers
6149 movdl(xtmp, value);
6150 pshufd(xtmp, xtmp, 0);
6151 } else {
6152 // Fill 32-byte chunks
6153 pshufd(xtmp, xtmp, 0);
6154
6155 subptr(count, 8 << shift);
6156 jcc(Assembler::less, L_check_fill_8_bytes);
6157 align(16);
6158
6159 BIND(L_fill_32_bytes_loop);
6160
6161 if (UseUnalignedLoadStores) {
6162 movdqu(Address(to, 0), xtmp);
6163 movdqu(Address(to, 16), xtmp);
6164 } else {
6165 movq(Address(to, 0), xtmp);
6166 movq(Address(to, 8), xtmp);
6167 movq(Address(to, 16), xtmp);
6168 movq(Address(to, 24), xtmp);
6169 }
6170
6171 addptr(to, 32);
6172 subptr(count, 8 << shift);
6173 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6174
6175 BIND(L_check_fill_8_bytes);
6176 }
6177 addptr(count, 8 << shift);
6178 jccb(Assembler::zero, L_exit);
6179 jmpb(L_fill_8_bytes);
6180
6181 //
6182 // length is too short, just fill qwords
6183 //
6184 align(16);
6185 BIND(L_fill_8_bytes_loop);
6186 movq(Address(to, 0), xtmp);
6187 addptr(to, 8);
6188 BIND(L_fill_8_bytes);
6189 subptr(count, 1 << (shift + 1));
6190 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6191 }
6192 }
6193
6194 Label L_fill_4_bytes_loop;
6195 testl(count, 1 << shift);
6196 jccb(Assembler::zero, L_fill_2_bytes);
6197
6198 align(16);
6199 BIND(L_fill_4_bytes_loop);
6200 movl(Address(to, 0), value);
6201 addptr(to, 4);
6202
6203 BIND(L_fill_4_bytes);
6204 subptr(count, 1 << shift);
6205 jccb(Assembler::greaterEqual, L_fill_4_bytes_loop);
6206
6207 if (t == T_BYTE || t == T_SHORT) {
6208 Label L_fill_byte;
6209 BIND(L_fill_2_bytes);
6210 // fill trailing 2 bytes
6211 testl(count, 1<<(shift-1));
6212 jccb(Assembler::zero, L_fill_byte);
6213 movw(Address(to, 0), value);
6214 if (t == T_BYTE) {
6215 addptr(to, 2);
6216 BIND(L_fill_byte);
6217 // fill trailing byte
6218 testl(count, 1);
6219 jccb(Assembler::zero, L_exit);
6220 movb(Address(to, 0), value);
6221 } else {
6222 BIND(L_fill_byte);
6223 }
6224 } else {
6225 BIND(L_fill_2_bytes);
6226 }
6227 BIND(L_exit);
6228 }
6229
6230 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6231 switch(type) {
6232 case T_BYTE:
6233 case T_BOOLEAN:
6234 evpbroadcastb(dst, src, vector_len);
6235 break;
6236 case T_SHORT:
6237 case T_CHAR:
6238 evpbroadcastw(dst, src, vector_len);
6239 break;
6240 case T_INT:
6241 case T_FLOAT:
6242 evpbroadcastd(dst, src, vector_len);
6243 break;
6244 case T_LONG:
6245 case T_DOUBLE:
6246 evpbroadcastq(dst, src, vector_len);
6247 break;
6248 default:
6249 fatal("Unhandled type : %s", type2name(type));
6250 break;
6251 }
6252 }
6253
6254 // encode char[] to byte[] in ISO_8859_1 or ASCII
6255 //@IntrinsicCandidate
6256 //private static int implEncodeISOArray(byte[] sa, int sp,
6257 //byte[] da, int dp, int len) {
6258 // int i = 0;
6259 // for (; i < len; i++) {
6260 // char c = StringUTF16.getChar(sa, sp++);
6261 // if (c > '\u00FF')
6262 // break;
6263 // da[dp++] = (byte)c;
6264 // }
6265 // return i;
6266 //}
6267 //
6268 //@IntrinsicCandidate
6269 //private static int implEncodeAsciiArray(char[] sa, int sp,
6270 // byte[] da, int dp, int len) {
6271 // int i = 0;
6272 // for (; i < len; i++) {
6273 // char c = sa[sp++];
6274 // if (c >= '\u0080')
6275 // break;
6276 // da[dp++] = (byte)c;
6277 // }
6278 // return i;
6279 //}
6280 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6281 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6282 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6283 Register tmp5, Register result, bool ascii) {
6284
6285 // rsi: src
6286 // rdi: dst
6287 // rdx: len
6288 // rcx: tmp5
6289 // rax: result
6290 ShortBranchVerifier sbv(this);
6291 assert_different_registers(src, dst, len, tmp5, result);
6292 Label L_done, L_copy_1_char, L_copy_1_char_exit;
6293
6294 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
6295 int short_mask = ascii ? 0xff80 : 0xff00;
6296
6297 // set result
6298 xorl(result, result);
6299 // check for zero length
6300 testl(len, len);
6301 jcc(Assembler::zero, L_done);
6302
6303 movl(result, len);
6304
6305 // Setup pointers
6306 lea(src, Address(src, len, Address::times_2)); // char[]
6307 lea(dst, Address(dst, len, Address::times_1)); // byte[]
6308 negptr(len);
6309
6310 if (UseSSE42Intrinsics || UseAVX >= 2) {
6311 Label L_copy_8_chars, L_copy_8_chars_exit;
6312 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
6313
6314 if (UseAVX >= 2) {
6315 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
6316 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6317 movdl(tmp1Reg, tmp5);
6318 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
6319 jmp(L_chars_32_check);
6320
6321 bind(L_copy_32_chars);
6322 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
6323 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
6324 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6325 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6326 jccb(Assembler::notZero, L_copy_32_chars_exit);
6327 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6328 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
6329 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
6330
6331 bind(L_chars_32_check);
6332 addptr(len, 32);
6333 jcc(Assembler::lessEqual, L_copy_32_chars);
6334
6335 bind(L_copy_32_chars_exit);
6336 subptr(len, 16);
6337 jccb(Assembler::greater, L_copy_16_chars_exit);
6338
6339 } else if (UseSSE42Intrinsics) {
6340 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6341 movdl(tmp1Reg, tmp5);
6342 pshufd(tmp1Reg, tmp1Reg, 0);
6343 jmpb(L_chars_16_check);
6344 }
6345
6346 bind(L_copy_16_chars);
6347 if (UseAVX >= 2) {
6348 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
6349 vptest(tmp2Reg, tmp1Reg);
6350 jcc(Assembler::notZero, L_copy_16_chars_exit);
6351 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
6352 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
6353 } else {
6354 if (UseAVX > 0) {
6355 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6356 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6357 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
6358 } else {
6359 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6360 por(tmp2Reg, tmp3Reg);
6361 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6362 por(tmp2Reg, tmp4Reg);
6363 }
6364 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6365 jccb(Assembler::notZero, L_copy_16_chars_exit);
6366 packuswb(tmp3Reg, tmp4Reg);
6367 }
6368 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
6369
6370 bind(L_chars_16_check);
6371 addptr(len, 16);
6372 jcc(Assembler::lessEqual, L_copy_16_chars);
6373
6374 bind(L_copy_16_chars_exit);
6375 if (UseAVX >= 2) {
6376 // clean upper bits of YMM registers
6377 vpxor(tmp2Reg, tmp2Reg);
6378 vpxor(tmp3Reg, tmp3Reg);
6379 vpxor(tmp4Reg, tmp4Reg);
6380 movdl(tmp1Reg, tmp5);
6381 pshufd(tmp1Reg, tmp1Reg, 0);
6382 }
6383 subptr(len, 8);
6384 jccb(Assembler::greater, L_copy_8_chars_exit);
6385
6386 bind(L_copy_8_chars);
6387 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
6388 ptest(tmp3Reg, tmp1Reg);
6389 jccb(Assembler::notZero, L_copy_8_chars_exit);
6390 packuswb(tmp3Reg, tmp1Reg);
6391 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
6392 addptr(len, 8);
6393 jccb(Assembler::lessEqual, L_copy_8_chars);
6394
6395 bind(L_copy_8_chars_exit);
6396 subptr(len, 8);
6397 jccb(Assembler::zero, L_done);
6398 }
6399
6400 bind(L_copy_1_char);
6401 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
6402 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
6403 jccb(Assembler::notZero, L_copy_1_char_exit);
6404 movb(Address(dst, len, Address::times_1, 0), tmp5);
6405 addptr(len, 1);
6406 jccb(Assembler::less, L_copy_1_char);
6407
6408 bind(L_copy_1_char_exit);
6409 addptr(result, len); // len is negative count of not processed elements
6410
6411 bind(L_done);
6412 }
6413
6414 /**
6415 * Helper for multiply_to_len().
6416 */
6417 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
6418 addq(dest_lo, src1);
6419 adcq(dest_hi, 0);
6420 addq(dest_lo, src2);
6421 adcq(dest_hi, 0);
6422 }
6423
6424 /**
6425 * Multiply 64 bit by 64 bit first loop.
6426 */
6427 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
6428 Register y, Register y_idx, Register z,
6429 Register carry, Register product,
6430 Register idx, Register kdx) {
6431 //
6432 // jlong carry, x[], y[], z[];
6433 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6434 // huge_128 product = y[idx] * x[xstart] + carry;
6435 // z[kdx] = (jlong)product;
6436 // carry = (jlong)(product >>> 64);
6437 // }
6438 // z[xstart] = carry;
6439 //
6440
6441 Label L_first_loop, L_first_loop_exit;
6442 Label L_one_x, L_one_y, L_multiply;
6443
6444 decrementl(xstart);
6445 jcc(Assembler::negative, L_one_x);
6446
6447 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
6448 rorq(x_xstart, 32); // convert big-endian to little-endian
6449
6450 bind(L_first_loop);
6451 decrementl(idx);
6452 jcc(Assembler::negative, L_first_loop_exit);
6453 decrementl(idx);
6454 jcc(Assembler::negative, L_one_y);
6455 movq(y_idx, Address(y, idx, Address::times_4, 0));
6456 rorq(y_idx, 32); // convert big-endian to little-endian
6457 bind(L_multiply);
6458 movq(product, x_xstart);
6459 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
6460 addq(product, carry);
6461 adcq(rdx, 0);
6462 subl(kdx, 2);
6463 movl(Address(z, kdx, Address::times_4, 4), product);
6464 shrq(product, 32);
6465 movl(Address(z, kdx, Address::times_4, 0), product);
6466 movq(carry, rdx);
6467 jmp(L_first_loop);
6468
6469 bind(L_one_y);
6470 movl(y_idx, Address(y, 0));
6471 jmp(L_multiply);
6472
6473 bind(L_one_x);
6474 movl(x_xstart, Address(x, 0));
6475 jmp(L_first_loop);
6476
6477 bind(L_first_loop_exit);
6478 }
6479
6480 /**
6481 * Multiply 64 bit by 64 bit and add 128 bit.
6482 */
6483 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
6484 Register yz_idx, Register idx,
6485 Register carry, Register product, int offset) {
6486 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
6487 // z[kdx] = (jlong)product;
6488
6489 movq(yz_idx, Address(y, idx, Address::times_4, offset));
6490 rorq(yz_idx, 32); // convert big-endian to little-endian
6491 movq(product, x_xstart);
6492 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
6493 movq(yz_idx, Address(z, idx, Address::times_4, offset));
6494 rorq(yz_idx, 32); // convert big-endian to little-endian
6495
6496 add2_with_carry(rdx, product, carry, yz_idx);
6497
6498 movl(Address(z, idx, Address::times_4, offset+4), product);
6499 shrq(product, 32);
6500 movl(Address(z, idx, Address::times_4, offset), product);
6501
6502 }
6503
6504 /**
6505 * Multiply 128 bit by 128 bit. Unrolled inner loop.
6506 */
6507 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
6508 Register yz_idx, Register idx, Register jdx,
6509 Register carry, Register product,
6510 Register carry2) {
6511 // jlong carry, x[], y[], z[];
6512 // int kdx = ystart+1;
6513 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6514 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
6515 // z[kdx+idx+1] = (jlong)product;
6516 // jlong carry2 = (jlong)(product >>> 64);
6517 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
6518 // z[kdx+idx] = (jlong)product;
6519 // carry = (jlong)(product >>> 64);
6520 // }
6521 // idx += 2;
6522 // if (idx > 0) {
6523 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
6524 // z[kdx+idx] = (jlong)product;
6525 // carry = (jlong)(product >>> 64);
6526 // }
6527 //
6528
6529 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6530
6531 movl(jdx, idx);
6532 andl(jdx, 0xFFFFFFFC);
6533 shrl(jdx, 2);
6534
6535 bind(L_third_loop);
6536 subl(jdx, 1);
6537 jcc(Assembler::negative, L_third_loop_exit);
6538 subl(idx, 4);
6539
6540 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
6541 movq(carry2, rdx);
6542
6543 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
6544 movq(carry, rdx);
6545 jmp(L_third_loop);
6546
6547 bind (L_third_loop_exit);
6548
6549 andl (idx, 0x3);
6550 jcc(Assembler::zero, L_post_third_loop_done);
6551
6552 Label L_check_1;
6553 subl(idx, 2);
6554 jcc(Assembler::negative, L_check_1);
6555
6556 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
6557 movq(carry, rdx);
6558
6559 bind (L_check_1);
6560 addl (idx, 0x2);
6561 andl (idx, 0x1);
6562 subl(idx, 1);
6563 jcc(Assembler::negative, L_post_third_loop_done);
6564
6565 movl(yz_idx, Address(y, idx, Address::times_4, 0));
6566 movq(product, x_xstart);
6567 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
6568 movl(yz_idx, Address(z, idx, Address::times_4, 0));
6569
6570 add2_with_carry(rdx, product, yz_idx, carry);
6571
6572 movl(Address(z, idx, Address::times_4, 0), product);
6573 shrq(product, 32);
6574
6575 shlq(rdx, 32);
6576 orq(product, rdx);
6577 movq(carry, product);
6578
6579 bind(L_post_third_loop_done);
6580 }
6581
6582 /**
6583 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
6584 *
6585 */
6586 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
6587 Register carry, Register carry2,
6588 Register idx, Register jdx,
6589 Register yz_idx1, Register yz_idx2,
6590 Register tmp, Register tmp3, Register tmp4) {
6591 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
6592
6593 // jlong carry, x[], y[], z[];
6594 // int kdx = ystart+1;
6595 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6596 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
6597 // jlong carry2 = (jlong)(tmp3 >>> 64);
6598 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
6599 // carry = (jlong)(tmp4 >>> 64);
6600 // z[kdx+idx+1] = (jlong)tmp3;
6601 // z[kdx+idx] = (jlong)tmp4;
6602 // }
6603 // idx += 2;
6604 // if (idx > 0) {
6605 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
6606 // z[kdx+idx] = (jlong)yz_idx1;
6607 // carry = (jlong)(yz_idx1 >>> 64);
6608 // }
6609 //
6610
6611 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6612
6613 movl(jdx, idx);
6614 andl(jdx, 0xFFFFFFFC);
6615 shrl(jdx, 2);
6616
6617 bind(L_third_loop);
6618 subl(jdx, 1);
6619 jcc(Assembler::negative, L_third_loop_exit);
6620 subl(idx, 4);
6621
6622 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
6623 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
6624 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
6625 rorxq(yz_idx2, yz_idx2, 32);
6626
6627 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
6628 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
6629
6630 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
6631 rorxq(yz_idx1, yz_idx1, 32);
6632 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
6633 rorxq(yz_idx2, yz_idx2, 32);
6634
6635 if (VM_Version::supports_adx()) {
6636 adcxq(tmp3, carry);
6637 adoxq(tmp3, yz_idx1);
6638
6639 adcxq(tmp4, tmp);
6640 adoxq(tmp4, yz_idx2);
6641
6642 movl(carry, 0); // does not affect flags
6643 adcxq(carry2, carry);
6644 adoxq(carry2, carry);
6645 } else {
6646 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
6647 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
6648 }
6649 movq(carry, carry2);
6650
6651 movl(Address(z, idx, Address::times_4, 12), tmp3);
6652 shrq(tmp3, 32);
6653 movl(Address(z, idx, Address::times_4, 8), tmp3);
6654
6655 movl(Address(z, idx, Address::times_4, 4), tmp4);
6656 shrq(tmp4, 32);
6657 movl(Address(z, idx, Address::times_4, 0), tmp4);
6658
6659 jmp(L_third_loop);
6660
6661 bind (L_third_loop_exit);
6662
6663 andl (idx, 0x3);
6664 jcc(Assembler::zero, L_post_third_loop_done);
6665
6666 Label L_check_1;
6667 subl(idx, 2);
6668 jcc(Assembler::negative, L_check_1);
6669
6670 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
6671 rorxq(yz_idx1, yz_idx1, 32);
6672 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
6673 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
6674 rorxq(yz_idx2, yz_idx2, 32);
6675
6676 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
6677
6678 movl(Address(z, idx, Address::times_4, 4), tmp3);
6679 shrq(tmp3, 32);
6680 movl(Address(z, idx, Address::times_4, 0), tmp3);
6681 movq(carry, tmp4);
6682
6683 bind (L_check_1);
6684 addl (idx, 0x2);
6685 andl (idx, 0x1);
6686 subl(idx, 1);
6687 jcc(Assembler::negative, L_post_third_loop_done);
6688 movl(tmp4, Address(y, idx, Address::times_4, 0));
6689 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
6690 movl(tmp4, Address(z, idx, Address::times_4, 0));
6691
6692 add2_with_carry(carry2, tmp3, tmp4, carry);
6693
6694 movl(Address(z, idx, Address::times_4, 0), tmp3);
6695 shrq(tmp3, 32);
6696
6697 shlq(carry2, 32);
6698 orq(tmp3, carry2);
6699 movq(carry, tmp3);
6700
6701 bind(L_post_third_loop_done);
6702 }
6703
6704 /**
6705 * Code for BigInteger::multiplyToLen() intrinsic.
6706 *
6707 * rdi: x
6708 * rax: xlen
6709 * rsi: y
6710 * rcx: ylen
6711 * r8: z
6712 * r11: tmp0
6713 * r12: tmp1
6714 * r13: tmp2
6715 * r14: tmp3
6716 * r15: tmp4
6717 * rbx: tmp5
6718 *
6719 */
6720 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
6721 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
6722 ShortBranchVerifier sbv(this);
6723 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
6724
6725 push(tmp0);
6726 push(tmp1);
6727 push(tmp2);
6728 push(tmp3);
6729 push(tmp4);
6730 push(tmp5);
6731
6732 push(xlen);
6733
6734 const Register idx = tmp1;
6735 const Register kdx = tmp2;
6736 const Register xstart = tmp3;
6737
6738 const Register y_idx = tmp4;
6739 const Register carry = tmp5;
6740 const Register product = xlen;
6741 const Register x_xstart = tmp0;
6742
6743 // First Loop.
6744 //
6745 // final static long LONG_MASK = 0xffffffffL;
6746 // int xstart = xlen - 1;
6747 // int ystart = ylen - 1;
6748 // long carry = 0;
6749 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6750 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
6751 // z[kdx] = (int)product;
6752 // carry = product >>> 32;
6753 // }
6754 // z[xstart] = (int)carry;
6755 //
6756
6757 movl(idx, ylen); // idx = ylen;
6758 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
6759 xorq(carry, carry); // carry = 0;
6760
6761 Label L_done;
6762
6763 movl(xstart, xlen);
6764 decrementl(xstart);
6765 jcc(Assembler::negative, L_done);
6766
6767 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
6768
6769 Label L_second_loop;
6770 testl(kdx, kdx);
6771 jcc(Assembler::zero, L_second_loop);
6772
6773 Label L_carry;
6774 subl(kdx, 1);
6775 jcc(Assembler::zero, L_carry);
6776
6777 movl(Address(z, kdx, Address::times_4, 0), carry);
6778 shrq(carry, 32);
6779 subl(kdx, 1);
6780
6781 bind(L_carry);
6782 movl(Address(z, kdx, Address::times_4, 0), carry);
6783
6784 // Second and third (nested) loops.
6785 //
6786 // for (int i = xstart-1; i >= 0; i--) { // Second loop
6787 // carry = 0;
6788 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
6789 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
6790 // (z[k] & LONG_MASK) + carry;
6791 // z[k] = (int)product;
6792 // carry = product >>> 32;
6793 // }
6794 // z[i] = (int)carry;
6795 // }
6796 //
6797 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
6798
6799 const Register jdx = tmp1;
6800
6801 bind(L_second_loop);
6802 xorl(carry, carry); // carry = 0;
6803 movl(jdx, ylen); // j = ystart+1
6804
6805 subl(xstart, 1); // i = xstart-1;
6806 jcc(Assembler::negative, L_done);
6807
6808 push (z);
6809
6810 Label L_last_x;
6811 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
6812 subl(xstart, 1); // i = xstart-1;
6813 jcc(Assembler::negative, L_last_x);
6814
6815 if (UseBMI2Instructions) {
6816 movq(rdx, Address(x, xstart, Address::times_4, 0));
6817 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
6818 } else {
6819 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
6820 rorq(x_xstart, 32); // convert big-endian to little-endian
6821 }
6822
6823 Label L_third_loop_prologue;
6824 bind(L_third_loop_prologue);
6825
6826 push (x);
6827 push (xstart);
6828 push (ylen);
6829
6830
6831 if (UseBMI2Instructions) {
6832 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
6833 } else { // !UseBMI2Instructions
6834 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
6835 }
6836
6837 pop(ylen);
6838 pop(xlen);
6839 pop(x);
6840 pop(z);
6841
6842 movl(tmp3, xlen);
6843 addl(tmp3, 1);
6844 movl(Address(z, tmp3, Address::times_4, 0), carry);
6845 subl(tmp3, 1);
6846 jccb(Assembler::negative, L_done);
6847
6848 shrq(carry, 32);
6849 movl(Address(z, tmp3, Address::times_4, 0), carry);
6850 jmp(L_second_loop);
6851
6852 // Next infrequent code is moved outside loops.
6853 bind(L_last_x);
6854 if (UseBMI2Instructions) {
6855 movl(rdx, Address(x, 0));
6856 } else {
6857 movl(x_xstart, Address(x, 0));
6858 }
6859 jmp(L_third_loop_prologue);
6860
6861 bind(L_done);
6862
6863 pop(xlen);
6864
6865 pop(tmp5);
6866 pop(tmp4);
6867 pop(tmp3);
6868 pop(tmp2);
6869 pop(tmp1);
6870 pop(tmp0);
6871 }
6872
6873 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
6874 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
6875 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
6876 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
6877 Label VECTOR8_TAIL, VECTOR4_TAIL;
6878 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
6879 Label SAME_TILL_END, DONE;
6880 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
6881
6882 //scale is in rcx in both Win64 and Unix
6883 ShortBranchVerifier sbv(this);
6884
6885 shlq(length);
6886 xorq(result, result);
6887
6888 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
6889 VM_Version::supports_avx512vlbw()) {
6890 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
6891
6892 cmpq(length, 64);
6893 jcc(Assembler::less, VECTOR32_TAIL);
6894
6895 movq(tmp1, length);
6896 andq(tmp1, 0x3F); // tail count
6897 andq(length, ~(0x3F)); //vector count
6898
6899 bind(VECTOR64_LOOP);
6900 // AVX512 code to compare 64 byte vectors.
6901 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
6902 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
6903 kortestql(k7, k7);
6904 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
6905 addq(result, 64);
6906 subq(length, 64);
6907 jccb(Assembler::notZero, VECTOR64_LOOP);
6908
6909 //bind(VECTOR64_TAIL);
6910 testq(tmp1, tmp1);
6911 jcc(Assembler::zero, SAME_TILL_END);
6912
6913 //bind(VECTOR64_TAIL);
6914 // AVX512 code to compare up to 63 byte vectors.
6915 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
6916 shlxq(tmp2, tmp2, tmp1);
6917 notq(tmp2);
6918 kmovql(k3, tmp2);
6919
6920 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
6921 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
6922
6923 ktestql(k7, k3);
6924 jcc(Assembler::below, SAME_TILL_END); // not mismatch
6925
6926 bind(VECTOR64_NOT_EQUAL);
6927 kmovql(tmp1, k7);
6928 notq(tmp1);
6929 tzcntq(tmp1, tmp1);
6930 addq(result, tmp1);
6931 shrq(result);
6932 jmp(DONE);
6933 bind(VECTOR32_TAIL);
6934 }
6935
6936 cmpq(length, 8);
6937 jcc(Assembler::equal, VECTOR8_LOOP);
6938 jcc(Assembler::less, VECTOR4_TAIL);
6939
6940 if (UseAVX >= 2) {
6941 Label VECTOR16_TAIL, VECTOR32_LOOP;
6942
6943 cmpq(length, 16);
6944 jcc(Assembler::equal, VECTOR16_LOOP);
6945 jcc(Assembler::less, VECTOR8_LOOP);
6946
6947 cmpq(length, 32);
6948 jccb(Assembler::less, VECTOR16_TAIL);
6949
6950 subq(length, 32);
6951 bind(VECTOR32_LOOP);
6952 vmovdqu(rymm0, Address(obja, result));
6953 vmovdqu(rymm1, Address(objb, result));
6954 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
6955 vptest(rymm2, rymm2);
6956 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
6957 addq(result, 32);
6958 subq(length, 32);
6959 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
6960 addq(length, 32);
6961 jcc(Assembler::equal, SAME_TILL_END);
6962 //falling through if less than 32 bytes left //close the branch here.
6963
6964 bind(VECTOR16_TAIL);
6965 cmpq(length, 16);
6966 jccb(Assembler::less, VECTOR8_TAIL);
6967 bind(VECTOR16_LOOP);
6968 movdqu(rymm0, Address(obja, result));
6969 movdqu(rymm1, Address(objb, result));
6970 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
6971 ptest(rymm2, rymm2);
6972 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
6973 addq(result, 16);
6974 subq(length, 16);
6975 jcc(Assembler::equal, SAME_TILL_END);
6976 //falling through if less than 16 bytes left
6977 } else {//regular intrinsics
6978
6979 cmpq(length, 16);
6980 jccb(Assembler::less, VECTOR8_TAIL);
6981
6982 subq(length, 16);
6983 bind(VECTOR16_LOOP);
6984 movdqu(rymm0, Address(obja, result));
6985 movdqu(rymm1, Address(objb, result));
6986 pxor(rymm0, rymm1);
6987 ptest(rymm0, rymm0);
6988 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
6989 addq(result, 16);
6990 subq(length, 16);
6991 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
6992 addq(length, 16);
6993 jcc(Assembler::equal, SAME_TILL_END);
6994 //falling through if less than 16 bytes left
6995 }
6996
6997 bind(VECTOR8_TAIL);
6998 cmpq(length, 8);
6999 jccb(Assembler::less, VECTOR4_TAIL);
7000 bind(VECTOR8_LOOP);
7001 movq(tmp1, Address(obja, result));
7002 movq(tmp2, Address(objb, result));
7003 xorq(tmp1, tmp2);
7004 testq(tmp1, tmp1);
7005 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7006 addq(result, 8);
7007 subq(length, 8);
7008 jcc(Assembler::equal, SAME_TILL_END);
7009 //falling through if less than 8 bytes left
7010
7011 bind(VECTOR4_TAIL);
7012 cmpq(length, 4);
7013 jccb(Assembler::less, BYTES_TAIL);
7014 bind(VECTOR4_LOOP);
7015 movl(tmp1, Address(obja, result));
7016 xorl(tmp1, Address(objb, result));
7017 testl(tmp1, tmp1);
7018 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7019 addq(result, 4);
7020 subq(length, 4);
7021 jcc(Assembler::equal, SAME_TILL_END);
7022 //falling through if less than 4 bytes left
7023
7024 bind(BYTES_TAIL);
7025 bind(BYTES_LOOP);
7026 load_unsigned_byte(tmp1, Address(obja, result));
7027 load_unsigned_byte(tmp2, Address(objb, result));
7028 xorl(tmp1, tmp2);
7029 testl(tmp1, tmp1);
7030 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7031 decq(length);
7032 jcc(Assembler::zero, SAME_TILL_END);
7033 incq(result);
7034 load_unsigned_byte(tmp1, Address(obja, result));
7035 load_unsigned_byte(tmp2, Address(objb, result));
7036 xorl(tmp1, tmp2);
7037 testl(tmp1, tmp1);
7038 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7039 decq(length);
7040 jcc(Assembler::zero, SAME_TILL_END);
7041 incq(result);
7042 load_unsigned_byte(tmp1, Address(obja, result));
7043 load_unsigned_byte(tmp2, Address(objb, result));
7044 xorl(tmp1, tmp2);
7045 testl(tmp1, tmp1);
7046 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7047 jmp(SAME_TILL_END);
7048
7049 if (UseAVX >= 2) {
7050 bind(VECTOR32_NOT_EQUAL);
7051 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7052 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7053 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7054 vpmovmskb(tmp1, rymm0);
7055 bsfq(tmp1, tmp1);
7056 addq(result, tmp1);
7057 shrq(result);
7058 jmp(DONE);
7059 }
7060
7061 bind(VECTOR16_NOT_EQUAL);
7062 if (UseAVX >= 2) {
7063 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7064 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7065 pxor(rymm0, rymm2);
7066 } else {
7067 pcmpeqb(rymm2, rymm2);
7068 pxor(rymm0, rymm1);
7069 pcmpeqb(rymm0, rymm1);
7070 pxor(rymm0, rymm2);
7071 }
7072 pmovmskb(tmp1, rymm0);
7073 bsfq(tmp1, tmp1);
7074 addq(result, tmp1);
7075 shrq(result);
7076 jmpb(DONE);
7077
7078 bind(VECTOR8_NOT_EQUAL);
7079 bind(VECTOR4_NOT_EQUAL);
7080 bsfq(tmp1, tmp1);
7081 shrq(tmp1, 3);
7082 addq(result, tmp1);
7083 bind(BYTES_NOT_EQUAL);
7084 shrq(result);
7085 jmpb(DONE);
7086
7087 bind(SAME_TILL_END);
7088 mov64(result, -1);
7089
7090 bind(DONE);
7091 }
7092
7093 //Helper functions for square_to_len()
7094
7095 /**
7096 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7097 * Preserves x and z and modifies rest of the registers.
7098 */
7099 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7100 // Perform square and right shift by 1
7101 // Handle odd xlen case first, then for even xlen do the following
7102 // jlong carry = 0;
7103 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7104 // huge_128 product = x[j:j+1] * x[j:j+1];
7105 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7106 // z[i+2:i+3] = (jlong)(product >>> 1);
7107 // carry = (jlong)product;
7108 // }
7109
7110 xorq(tmp5, tmp5); // carry
7111 xorq(rdxReg, rdxReg);
7112 xorl(tmp1, tmp1); // index for x
7113 xorl(tmp4, tmp4); // index for z
7114
7115 Label L_first_loop, L_first_loop_exit;
7116
7117 testl(xlen, 1);
7118 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7119
7120 // Square and right shift by 1 the odd element using 32 bit multiply
7121 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7122 imulq(raxReg, raxReg);
7123 shrq(raxReg, 1);
7124 adcq(tmp5, 0);
7125 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7126 incrementl(tmp1);
7127 addl(tmp4, 2);
7128
7129 // Square and right shift by 1 the rest using 64 bit multiply
7130 bind(L_first_loop);
7131 cmpptr(tmp1, xlen);
7132 jccb(Assembler::equal, L_first_loop_exit);
7133
7134 // Square
7135 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7136 rorq(raxReg, 32); // convert big-endian to little-endian
7137 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7138
7139 // Right shift by 1 and save carry
7140 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7141 rcrq(rdxReg, 1);
7142 rcrq(raxReg, 1);
7143 adcq(tmp5, 0);
7144
7145 // Store result in z
7146 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7147 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7148
7149 // Update indices for x and z
7150 addl(tmp1, 2);
7151 addl(tmp4, 4);
7152 jmp(L_first_loop);
7153
7154 bind(L_first_loop_exit);
7155 }
7156
7157
7158 /**
7159 * Perform the following multiply add operation using BMI2 instructions
7160 * carry:sum = sum + op1*op2 + carry
7161 * op2 should be in rdx
7162 * op2 is preserved, all other registers are modified
7163 */
7164 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7165 // assert op2 is rdx
7166 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7167 addq(sum, carry);
7168 adcq(tmp2, 0);
7169 addq(sum, op1);
7170 adcq(tmp2, 0);
7171 movq(carry, tmp2);
7172 }
7173
7174 /**
7175 * Perform the following multiply add operation:
7176 * carry:sum = sum + op1*op2 + carry
7177 * Preserves op1, op2 and modifies rest of registers
7178 */
7179 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7180 // rdx:rax = op1 * op2
7181 movq(raxReg, op2);
7182 mulq(op1);
7183
7184 // rdx:rax = sum + carry + rdx:rax
7185 addq(sum, carry);
7186 adcq(rdxReg, 0);
7187 addq(sum, raxReg);
7188 adcq(rdxReg, 0);
7189
7190 // carry:sum = rdx:sum
7191 movq(carry, rdxReg);
7192 }
7193
7194 /**
7195 * Add 64 bit long carry into z[] with carry propagation.
7196 * Preserves z and carry register values and modifies rest of registers.
7197 *
7198 */
7199 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7200 Label L_fourth_loop, L_fourth_loop_exit;
7201
7202 movl(tmp1, 1);
7203 subl(zlen, 2);
7204 addq(Address(z, zlen, Address::times_4, 0), carry);
7205
7206 bind(L_fourth_loop);
7207 jccb(Assembler::carryClear, L_fourth_loop_exit);
7208 subl(zlen, 2);
7209 jccb(Assembler::negative, L_fourth_loop_exit);
7210 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7211 jmp(L_fourth_loop);
7212 bind(L_fourth_loop_exit);
7213 }
7214
7215 /**
7216 * Shift z[] left by 1 bit.
7217 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7218 *
7219 */
7220 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7221
7222 Label L_fifth_loop, L_fifth_loop_exit;
7223
7224 // Fifth loop
7225 // Perform primitiveLeftShift(z, zlen, 1)
7226
7227 const Register prev_carry = tmp1;
7228 const Register new_carry = tmp4;
7229 const Register value = tmp2;
7230 const Register zidx = tmp3;
7231
7232 // int zidx, carry;
7233 // long value;
7234 // carry = 0;
7235 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7236 // (carry:value) = (z[i] << 1) | carry ;
7237 // z[i] = value;
7238 // }
7239
7240 movl(zidx, zlen);
7241 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7242
7243 bind(L_fifth_loop);
7244 decl(zidx); // Use decl to preserve carry flag
7245 decl(zidx);
7246 jccb(Assembler::negative, L_fifth_loop_exit);
7247
7248 if (UseBMI2Instructions) {
7249 movq(value, Address(z, zidx, Address::times_4, 0));
7250 rclq(value, 1);
7251 rorxq(value, value, 32);
7252 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7253 }
7254 else {
7255 // clear new_carry
7256 xorl(new_carry, new_carry);
7257
7258 // Shift z[i] by 1, or in previous carry and save new carry
7259 movq(value, Address(z, zidx, Address::times_4, 0));
7260 shlq(value, 1);
7261 adcl(new_carry, 0);
7262
7263 orq(value, prev_carry);
7264 rorq(value, 0x20);
7265 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7266
7267 // Set previous carry = new carry
7268 movl(prev_carry, new_carry);
7269 }
7270 jmp(L_fifth_loop);
7271
7272 bind(L_fifth_loop_exit);
7273 }
7274
7275
7276 /**
7277 * Code for BigInteger::squareToLen() intrinsic
7278 *
7279 * rdi: x
7280 * rsi: len
7281 * r8: z
7282 * rcx: zlen
7283 * r12: tmp1
7284 * r13: tmp2
7285 * r14: tmp3
7286 * r15: tmp4
7287 * rbx: tmp5
7288 *
7289 */
7290 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7291
7292 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
7293 push(tmp1);
7294 push(tmp2);
7295 push(tmp3);
7296 push(tmp4);
7297 push(tmp5);
7298
7299 // First loop
7300 // Store the squares, right shifted one bit (i.e., divided by 2).
7301 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7302
7303 // Add in off-diagonal sums.
7304 //
7305 // Second, third (nested) and fourth loops.
7306 // zlen +=2;
7307 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7308 // carry = 0;
7309 // long op2 = x[xidx:xidx+1];
7310 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7311 // k -= 2;
7312 // long op1 = x[j:j+1];
7313 // long sum = z[k:k+1];
7314 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7315 // z[k:k+1] = sum;
7316 // }
7317 // add_one_64(z, k, carry, tmp_regs);
7318 // }
7319
7320 const Register carry = tmp5;
7321 const Register sum = tmp3;
7322 const Register op1 = tmp4;
7323 Register op2 = tmp2;
7324
7325 push(zlen);
7326 push(len);
7327 addl(zlen,2);
7328 bind(L_second_loop);
7329 xorq(carry, carry);
7330 subl(zlen, 4);
7331 subl(len, 2);
7332 push(zlen);
7333 push(len);
7334 cmpl(len, 0);
7335 jccb(Assembler::lessEqual, L_second_loop_exit);
7336
7337 // Multiply an array by one 64 bit long.
7338 if (UseBMI2Instructions) {
7339 op2 = rdxReg;
7340 movq(op2, Address(x, len, Address::times_4, 0));
7341 rorxq(op2, op2, 32);
7342 }
7343 else {
7344 movq(op2, Address(x, len, Address::times_4, 0));
7345 rorq(op2, 32);
7346 }
7347
7348 bind(L_third_loop);
7349 decrementl(len);
7350 jccb(Assembler::negative, L_third_loop_exit);
7351 decrementl(len);
7352 jccb(Assembler::negative, L_last_x);
7353
7354 movq(op1, Address(x, len, Address::times_4, 0));
7355 rorq(op1, 32);
7356
7357 bind(L_multiply);
7358 subl(zlen, 2);
7359 movq(sum, Address(z, zlen, Address::times_4, 0));
7360
7361 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
7362 if (UseBMI2Instructions) {
7363 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
7364 }
7365 else {
7366 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7367 }
7368
7369 movq(Address(z, zlen, Address::times_4, 0), sum);
7370
7371 jmp(L_third_loop);
7372 bind(L_third_loop_exit);
7373
7374 // Fourth loop
7375 // Add 64 bit long carry into z with carry propagation.
7376 // Uses offsetted zlen.
7377 add_one_64(z, zlen, carry, tmp1);
7378
7379 pop(len);
7380 pop(zlen);
7381 jmp(L_second_loop);
7382
7383 // Next infrequent code is moved outside loops.
7384 bind(L_last_x);
7385 movl(op1, Address(x, 0));
7386 jmp(L_multiply);
7387
7388 bind(L_second_loop_exit);
7389 pop(len);
7390 pop(zlen);
7391 pop(len);
7392 pop(zlen);
7393
7394 // Fifth loop
7395 // Shift z left 1 bit.
7396 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
7397
7398 // z[zlen-1] |= x[len-1] & 1;
7399 movl(tmp3, Address(x, len, Address::times_4, -4));
7400 andl(tmp3, 1);
7401 orl(Address(z, zlen, Address::times_4, -4), tmp3);
7402
7403 pop(tmp5);
7404 pop(tmp4);
7405 pop(tmp3);
7406 pop(tmp2);
7407 pop(tmp1);
7408 }
7409
7410 /**
7411 * Helper function for mul_add()
7412 * Multiply the in[] by int k and add to out[] starting at offset offs using
7413 * 128 bit by 32 bit multiply and return the carry in tmp5.
7414 * Only quad int aligned length of in[] is operated on in this function.
7415 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
7416 * This function preserves out, in and k registers.
7417 * len and offset point to the appropriate index in "in" & "out" correspondingly
7418 * tmp5 has the carry.
7419 * other registers are temporary and are modified.
7420 *
7421 */
7422 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
7423 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
7424 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7425
7426 Label L_first_loop, L_first_loop_exit;
7427
7428 movl(tmp1, len);
7429 shrl(tmp1, 2);
7430
7431 bind(L_first_loop);
7432 subl(tmp1, 1);
7433 jccb(Assembler::negative, L_first_loop_exit);
7434
7435 subl(len, 4);
7436 subl(offset, 4);
7437
7438 Register op2 = tmp2;
7439 const Register sum = tmp3;
7440 const Register op1 = tmp4;
7441 const Register carry = tmp5;
7442
7443 if (UseBMI2Instructions) {
7444 op2 = rdxReg;
7445 }
7446
7447 movq(op1, Address(in, len, Address::times_4, 8));
7448 rorq(op1, 32);
7449 movq(sum, Address(out, offset, Address::times_4, 8));
7450 rorq(sum, 32);
7451 if (UseBMI2Instructions) {
7452 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7453 }
7454 else {
7455 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7456 }
7457 // Store back in big endian from little endian
7458 rorq(sum, 0x20);
7459 movq(Address(out, offset, Address::times_4, 8), sum);
7460
7461 movq(op1, Address(in, len, Address::times_4, 0));
7462 rorq(op1, 32);
7463 movq(sum, Address(out, offset, Address::times_4, 0));
7464 rorq(sum, 32);
7465 if (UseBMI2Instructions) {
7466 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7467 }
7468 else {
7469 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7470 }
7471 // Store back in big endian from little endian
7472 rorq(sum, 0x20);
7473 movq(Address(out, offset, Address::times_4, 0), sum);
7474
7475 jmp(L_first_loop);
7476 bind(L_first_loop_exit);
7477 }
7478
7479 /**
7480 * Code for BigInteger::mulAdd() intrinsic
7481 *
7482 * rdi: out
7483 * rsi: in
7484 * r11: offs (out.length - offset)
7485 * rcx: len
7486 * r8: k
7487 * r12: tmp1
7488 * r13: tmp2
7489 * r14: tmp3
7490 * r15: tmp4
7491 * rbx: tmp5
7492 * Multiply the in[] by word k and add to out[], return the carry in rax
7493 */
7494 void MacroAssembler::mul_add(Register out, Register in, Register offs,
7495 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
7496 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7497
7498 Label L_carry, L_last_in, L_done;
7499
7500 // carry = 0;
7501 // for (int j=len-1; j >= 0; j--) {
7502 // long product = (in[j] & LONG_MASK) * kLong +
7503 // (out[offs] & LONG_MASK) + carry;
7504 // out[offs--] = (int)product;
7505 // carry = product >>> 32;
7506 // }
7507 //
7508 push(tmp1);
7509 push(tmp2);
7510 push(tmp3);
7511 push(tmp4);
7512 push(tmp5);
7513
7514 Register op2 = tmp2;
7515 const Register sum = tmp3;
7516 const Register op1 = tmp4;
7517 const Register carry = tmp5;
7518
7519 if (UseBMI2Instructions) {
7520 op2 = rdxReg;
7521 movl(op2, k);
7522 }
7523 else {
7524 movl(op2, k);
7525 }
7526
7527 xorq(carry, carry);
7528
7529 //First loop
7530
7531 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
7532 //The carry is in tmp5
7533 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
7534
7535 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
7536 decrementl(len);
7537 jccb(Assembler::negative, L_carry);
7538 decrementl(len);
7539 jccb(Assembler::negative, L_last_in);
7540
7541 movq(op1, Address(in, len, Address::times_4, 0));
7542 rorq(op1, 32);
7543
7544 subl(offs, 2);
7545 movq(sum, Address(out, offs, Address::times_4, 0));
7546 rorq(sum, 32);
7547
7548 if (UseBMI2Instructions) {
7549 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7550 }
7551 else {
7552 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7553 }
7554
7555 // Store back in big endian from little endian
7556 rorq(sum, 0x20);
7557 movq(Address(out, offs, Address::times_4, 0), sum);
7558
7559 testl(len, len);
7560 jccb(Assembler::zero, L_carry);
7561
7562 //Multiply the last in[] entry, if any
7563 bind(L_last_in);
7564 movl(op1, Address(in, 0));
7565 movl(sum, Address(out, offs, Address::times_4, -4));
7566
7567 movl(raxReg, k);
7568 mull(op1); //tmp4 * eax -> edx:eax
7569 addl(sum, carry);
7570 adcl(rdxReg, 0);
7571 addl(sum, raxReg);
7572 adcl(rdxReg, 0);
7573 movl(carry, rdxReg);
7574
7575 movl(Address(out, offs, Address::times_4, -4), sum);
7576
7577 bind(L_carry);
7578 //return tmp5/carry as carry in rax
7579 movl(rax, carry);
7580
7581 bind(L_done);
7582 pop(tmp5);
7583 pop(tmp4);
7584 pop(tmp3);
7585 pop(tmp2);
7586 pop(tmp1);
7587 }
7588
7589 /**
7590 * Emits code to update CRC-32 with a byte value according to constants in table
7591 *
7592 * @param [in,out]crc Register containing the crc.
7593 * @param [in]val Register containing the byte to fold into the CRC.
7594 * @param [in]table Register containing the table of crc constants.
7595 *
7596 * uint32_t crc;
7597 * val = crc_table[(val ^ crc) & 0xFF];
7598 * crc = val ^ (crc >> 8);
7599 *
7600 */
7601 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
7602 xorl(val, crc);
7603 andl(val, 0xFF);
7604 shrl(crc, 8); // unsigned shift
7605 xorl(crc, Address(table, val, Address::times_4, 0));
7606 }
7607
7608 /**
7609 * Fold 128-bit data chunk
7610 */
7611 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
7612 if (UseAVX > 0) {
7613 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
7614 vpclmulldq(xcrc, xK, xcrc); // [63:0]
7615 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
7616 pxor(xcrc, xtmp);
7617 } else {
7618 movdqa(xtmp, xcrc);
7619 pclmulhdq(xtmp, xK); // [123:64]
7620 pclmulldq(xcrc, xK); // [63:0]
7621 pxor(xcrc, xtmp);
7622 movdqu(xtmp, Address(buf, offset));
7623 pxor(xcrc, xtmp);
7624 }
7625 }
7626
7627 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
7628 if (UseAVX > 0) {
7629 vpclmulhdq(xtmp, xK, xcrc);
7630 vpclmulldq(xcrc, xK, xcrc);
7631 pxor(xcrc, xbuf);
7632 pxor(xcrc, xtmp);
7633 } else {
7634 movdqa(xtmp, xcrc);
7635 pclmulhdq(xtmp, xK);
7636 pclmulldq(xcrc, xK);
7637 pxor(xcrc, xbuf);
7638 pxor(xcrc, xtmp);
7639 }
7640 }
7641
7642 /**
7643 * 8-bit folds to compute 32-bit CRC
7644 *
7645 * uint64_t xcrc;
7646 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
7647 */
7648 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
7649 movdl(tmp, xcrc);
7650 andl(tmp, 0xFF);
7651 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
7652 psrldq(xcrc, 1); // unsigned shift one byte
7653 pxor(xcrc, xtmp);
7654 }
7655
7656 /**
7657 * uint32_t crc;
7658 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
7659 */
7660 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
7661 movl(tmp, crc);
7662 andl(tmp, 0xFF);
7663 shrl(crc, 8);
7664 xorl(crc, Address(table, tmp, Address::times_4, 0));
7665 }
7666
7667 /**
7668 * @param crc register containing existing CRC (32-bit)
7669 * @param buf register pointing to input byte buffer (byte*)
7670 * @param len register containing number of bytes
7671 * @param table register that will contain address of CRC table
7672 * @param tmp scratch register
7673 */
7674 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
7675 assert_different_registers(crc, buf, len, table, tmp, rax);
7676
7677 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7678 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7679
7680 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
7681 // context for the registers used, where all instructions below are using 128-bit mode
7682 // On EVEX without VL and BW, these instructions will all be AVX.
7683 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
7684 notl(crc); // ~crc
7685 cmpl(len, 16);
7686 jcc(Assembler::less, L_tail);
7687
7688 // Align buffer to 16 bytes
7689 movl(tmp, buf);
7690 andl(tmp, 0xF);
7691 jccb(Assembler::zero, L_aligned);
7692 subl(tmp, 16);
7693 addl(len, tmp);
7694
7695 align(4);
7696 BIND(L_align_loop);
7697 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7698 update_byte_crc32(crc, rax, table);
7699 increment(buf);
7700 incrementl(tmp);
7701 jccb(Assembler::less, L_align_loop);
7702
7703 BIND(L_aligned);
7704 movl(tmp, len); // save
7705 shrl(len, 4);
7706 jcc(Assembler::zero, L_tail_restore);
7707
7708 // Fold crc into first bytes of vector
7709 movdqa(xmm1, Address(buf, 0));
7710 movdl(rax, xmm1);
7711 xorl(crc, rax);
7712 if (VM_Version::supports_sse4_1()) {
7713 pinsrd(xmm1, crc, 0);
7714 } else {
7715 pinsrw(xmm1, crc, 0);
7716 shrl(crc, 16);
7717 pinsrw(xmm1, crc, 1);
7718 }
7719 addptr(buf, 16);
7720 subl(len, 4); // len > 0
7721 jcc(Assembler::less, L_fold_tail);
7722
7723 movdqa(xmm2, Address(buf, 0));
7724 movdqa(xmm3, Address(buf, 16));
7725 movdqa(xmm4, Address(buf, 32));
7726 addptr(buf, 48);
7727 subl(len, 3);
7728 jcc(Assembler::lessEqual, L_fold_512b);
7729
7730 // Fold total 512 bits of polynomial on each iteration,
7731 // 128 bits per each of 4 parallel streams.
7732 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
7733
7734 align32();
7735 BIND(L_fold_512b_loop);
7736 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
7737 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
7738 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
7739 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
7740 addptr(buf, 64);
7741 subl(len, 4);
7742 jcc(Assembler::greater, L_fold_512b_loop);
7743
7744 // Fold 512 bits to 128 bits.
7745 BIND(L_fold_512b);
7746 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
7747 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
7748 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
7749 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
7750
7751 // Fold the rest of 128 bits data chunks
7752 BIND(L_fold_tail);
7753 addl(len, 3);
7754 jccb(Assembler::lessEqual, L_fold_128b);
7755 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
7756
7757 BIND(L_fold_tail_loop);
7758 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
7759 addptr(buf, 16);
7760 decrementl(len);
7761 jccb(Assembler::greater, L_fold_tail_loop);
7762
7763 // Fold 128 bits in xmm1 down into 32 bits in crc register.
7764 BIND(L_fold_128b);
7765 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
7766 if (UseAVX > 0) {
7767 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
7768 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
7769 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
7770 } else {
7771 movdqa(xmm2, xmm0);
7772 pclmulqdq(xmm2, xmm1, 0x1);
7773 movdqa(xmm3, xmm0);
7774 pand(xmm3, xmm2);
7775 pclmulqdq(xmm0, xmm3, 0x1);
7776 }
7777 psrldq(xmm1, 8);
7778 psrldq(xmm2, 4);
7779 pxor(xmm0, xmm1);
7780 pxor(xmm0, xmm2);
7781
7782 // 8 8-bit folds to compute 32-bit CRC.
7783 for (int j = 0; j < 4; j++) {
7784 fold_8bit_crc32(xmm0, table, xmm1, rax);
7785 }
7786 movdl(crc, xmm0); // mov 32 bits to general register
7787 for (int j = 0; j < 4; j++) {
7788 fold_8bit_crc32(crc, table, rax);
7789 }
7790
7791 BIND(L_tail_restore);
7792 movl(len, tmp); // restore
7793 BIND(L_tail);
7794 andl(len, 0xf);
7795 jccb(Assembler::zero, L_exit);
7796
7797 // Fold the rest of bytes
7798 align(4);
7799 BIND(L_tail_loop);
7800 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7801 update_byte_crc32(crc, rax, table);
7802 increment(buf);
7803 decrementl(len);
7804 jccb(Assembler::greater, L_tail_loop);
7805
7806 BIND(L_exit);
7807 notl(crc); // ~c
7808 }
7809
7810 // Helper function for AVX 512 CRC32
7811 // Fold 512-bit data chunks
7812 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
7813 Register pos, int offset) {
7814 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
7815 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
7816 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
7817 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
7818 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
7819 }
7820
7821 // Helper function for AVX 512 CRC32
7822 // Compute CRC32 for < 256B buffers
7823 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
7824 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
7825 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
7826
7827 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
7828 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
7829 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
7830
7831 // check if there is enough buffer to be able to fold 16B at a time
7832 cmpl(len, 32);
7833 jcc(Assembler::less, L_less_than_32);
7834
7835 // if there is, load the constants
7836 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
7837 movdl(xmm0, crc); // get the initial crc value
7838 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7839 pxor(xmm7, xmm0);
7840
7841 // update the buffer pointer
7842 addl(pos, 16);
7843 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
7844 subl(len, 32);
7845 jmp(L_16B_reduction_loop);
7846
7847 bind(L_less_than_32);
7848 //mov initial crc to the return value. this is necessary for zero - length buffers.
7849 movl(rax, crc);
7850 testl(len, len);
7851 jcc(Assembler::equal, L_cleanup);
7852
7853 movdl(xmm0, crc); //get the initial crc value
7854
7855 cmpl(len, 16);
7856 jcc(Assembler::equal, L_exact_16_left);
7857 jcc(Assembler::less, L_less_than_16_left);
7858
7859 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7860 pxor(xmm7, xmm0); //xor the initial crc value
7861 addl(pos, 16);
7862 subl(len, 16);
7863 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
7864 jmp(L_get_last_two_xmms);
7865
7866 bind(L_less_than_16_left);
7867 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
7868 pxor(xmm1, xmm1);
7869 movptr(tmp1, rsp);
7870 movdqu(Address(tmp1, 0 * 16), xmm1);
7871
7872 cmpl(len, 4);
7873 jcc(Assembler::less, L_only_less_than_4);
7874
7875 //backup the counter value
7876 movl(tmp2, len);
7877 cmpl(len, 8);
7878 jcc(Assembler::less, L_less_than_8_left);
7879
7880 //load 8 Bytes
7881 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
7882 movq(Address(tmp1, 0 * 16), rax);
7883 addptr(tmp1, 8);
7884 subl(len, 8);
7885 addl(pos, 8);
7886
7887 bind(L_less_than_8_left);
7888 cmpl(len, 4);
7889 jcc(Assembler::less, L_less_than_4_left);
7890
7891 //load 4 Bytes
7892 movl(rax, Address(buf, pos, Address::times_1, 0));
7893 movl(Address(tmp1, 0 * 16), rax);
7894 addptr(tmp1, 4);
7895 subl(len, 4);
7896 addl(pos, 4);
7897
7898 bind(L_less_than_4_left);
7899 cmpl(len, 2);
7900 jcc(Assembler::less, L_less_than_2_left);
7901
7902 // load 2 Bytes
7903 movw(rax, Address(buf, pos, Address::times_1, 0));
7904 movl(Address(tmp1, 0 * 16), rax);
7905 addptr(tmp1, 2);
7906 subl(len, 2);
7907 addl(pos, 2);
7908
7909 bind(L_less_than_2_left);
7910 cmpl(len, 1);
7911 jcc(Assembler::less, L_zero_left);
7912
7913 // load 1 Byte
7914 movb(rax, Address(buf, pos, Address::times_1, 0));
7915 movb(Address(tmp1, 0 * 16), rax);
7916
7917 bind(L_zero_left);
7918 movdqu(xmm7, Address(rsp, 0));
7919 pxor(xmm7, xmm0); //xor the initial crc value
7920
7921 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
7922 movdqu(xmm0, Address(rax, tmp2));
7923 pshufb(xmm7, xmm0);
7924 jmp(L_128_done);
7925
7926 bind(L_exact_16_left);
7927 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
7928 pxor(xmm7, xmm0); //xor the initial crc value
7929 jmp(L_128_done);
7930
7931 bind(L_only_less_than_4);
7932 cmpl(len, 3);
7933 jcc(Assembler::less, L_only_less_than_3);
7934
7935 // load 3 Bytes
7936 movb(rax, Address(buf, pos, Address::times_1, 0));
7937 movb(Address(tmp1, 0), rax);
7938
7939 movb(rax, Address(buf, pos, Address::times_1, 1));
7940 movb(Address(tmp1, 1), rax);
7941
7942 movb(rax, Address(buf, pos, Address::times_1, 2));
7943 movb(Address(tmp1, 2), rax);
7944
7945 movdqu(xmm7, Address(rsp, 0));
7946 pxor(xmm7, xmm0); //xor the initial crc value
7947
7948 pslldq(xmm7, 0x5);
7949 jmp(L_barrett);
7950 bind(L_only_less_than_3);
7951 cmpl(len, 2);
7952 jcc(Assembler::less, L_only_less_than_2);
7953
7954 // load 2 Bytes
7955 movb(rax, Address(buf, pos, Address::times_1, 0));
7956 movb(Address(tmp1, 0), rax);
7957
7958 movb(rax, Address(buf, pos, Address::times_1, 1));
7959 movb(Address(tmp1, 1), rax);
7960
7961 movdqu(xmm7, Address(rsp, 0));
7962 pxor(xmm7, xmm0); //xor the initial crc value
7963
7964 pslldq(xmm7, 0x6);
7965 jmp(L_barrett);
7966
7967 bind(L_only_less_than_2);
7968 //load 1 Byte
7969 movb(rax, Address(buf, pos, Address::times_1, 0));
7970 movb(Address(tmp1, 0), rax);
7971
7972 movdqu(xmm7, Address(rsp, 0));
7973 pxor(xmm7, xmm0); //xor the initial crc value
7974
7975 pslldq(xmm7, 0x7);
7976 }
7977
7978 /**
7979 * Compute CRC32 using AVX512 instructions
7980 * param crc register containing existing CRC (32-bit)
7981 * param buf register pointing to input byte buffer (byte*)
7982 * param len register containing number of bytes
7983 * param table address of crc or crc32c table
7984 * param tmp1 scratch register
7985 * param tmp2 scratch register
7986 * return rax result register
7987 *
7988 * This routine is identical for crc32c with the exception of the precomputed constant
7989 * table which will be passed as the table argument. The calculation steps are
7990 * the same for both variants.
7991 */
7992 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
7993 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
7994
7995 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7996 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7997 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
7998 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
7999 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8000
8001 const Register pos = r12;
8002 push(r12);
8003 subptr(rsp, 16 * 2 + 8);
8004
8005 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8006 // context for the registers used, where all instructions below are using 128-bit mode
8007 // On EVEX without VL and BW, these instructions will all be AVX.
8008 movl(pos, 0);
8009
8010 // check if smaller than 256B
8011 cmpl(len, 256);
8012 jcc(Assembler::less, L_less_than_256);
8013
8014 // load the initial crc value
8015 movdl(xmm10, crc);
8016
8017 // receive the initial 64B data, xor the initial crc value
8018 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8019 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8020 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8021 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8022
8023 subl(len, 256);
8024 cmpl(len, 256);
8025 jcc(Assembler::less, L_fold_128_B_loop);
8026
8027 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8028 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8029 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8030 subl(len, 256);
8031
8032 bind(L_fold_256_B_loop);
8033 addl(pos, 256);
8034 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8035 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8036 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8037 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8038
8039 subl(len, 256);
8040 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8041
8042 // Fold 256 into 128
8043 addl(pos, 256);
8044 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8045 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8046 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8047
8048 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8049 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8050 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8051
8052 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8053 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8054
8055 addl(len, 128);
8056 jmp(L_fold_128_B_register);
8057
8058 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8059 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8060
8061 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8062 bind(L_fold_128_B_loop);
8063 addl(pos, 128);
8064 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8065 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8066
8067 subl(len, 128);
8068 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8069
8070 addl(pos, 128);
8071
8072 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8073 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8074 bind(L_fold_128_B_register);
8075 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8076 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8077 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8078 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8079 // save last that has no multiplicand
8080 vextracti64x2(xmm7, xmm4, 3);
8081
8082 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8083 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8084 // Needed later in reduction loop
8085 movdqu(xmm10, Address(table, 1 * 16));
8086 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8087 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8088
8089 // Swap 1,0,3,2 - 01 00 11 10
8090 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8091 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8092 vextracti128(xmm5, xmm8, 1);
8093 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8094
8095 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8096 // instead of a cmp instruction, we use the negative flag with the jl instruction
8097 addl(len, 128 - 16);
8098 jcc(Assembler::less, L_final_reduction_for_128);
8099
8100 bind(L_16B_reduction_loop);
8101 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8102 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8103 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8104 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8105 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8106 addl(pos, 16);
8107 subl(len, 16);
8108 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8109
8110 bind(L_final_reduction_for_128);
8111 addl(len, 16);
8112 jcc(Assembler::equal, L_128_done);
8113
8114 bind(L_get_last_two_xmms);
8115 movdqu(xmm2, xmm7);
8116 addl(pos, len);
8117 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8118 subl(pos, len);
8119
8120 // get rid of the extra data that was loaded before
8121 // load the shift constant
8122 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8123 movdqu(xmm0, Address(rax, len));
8124 addl(rax, len);
8125
8126 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8127 //Change mask to 512
8128 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8129 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8130
8131 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8132 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8133 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8134 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8135 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8136
8137 bind(L_128_done);
8138 // compute crc of a 128-bit value
8139 movdqu(xmm10, Address(table, 3 * 16));
8140 movdqu(xmm0, xmm7);
8141
8142 // 64b fold
8143 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8144 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8145 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8146
8147 // 32b fold
8148 movdqu(xmm0, xmm7);
8149 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8150 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8151 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8152 jmp(L_barrett);
8153
8154 bind(L_less_than_256);
8155 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8156
8157 //barrett reduction
8158 bind(L_barrett);
8159 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8160 movdqu(xmm1, xmm7);
8161 movdqu(xmm2, xmm7);
8162 movdqu(xmm10, Address(table, 4 * 16));
8163
8164 pclmulqdq(xmm7, xmm10, 0x0);
8165 pxor(xmm7, xmm2);
8166 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8167 movdqu(xmm2, xmm7);
8168 pclmulqdq(xmm7, xmm10, 0x10);
8169 pxor(xmm7, xmm2);
8170 pxor(xmm7, xmm1);
8171 pextrd(crc, xmm7, 2);
8172
8173 bind(L_cleanup);
8174 addptr(rsp, 16 * 2 + 8);
8175 pop(r12);
8176 }
8177
8178 // S. Gueron / Information Processing Letters 112 (2012) 184
8179 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8180 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8181 // Output: the 64-bit carry-less product of B * CONST
8182 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8183 Register tmp1, Register tmp2, Register tmp3) {
8184 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8185 if (n > 0) {
8186 addq(tmp3, n * 256 * 8);
8187 }
8188 // Q1 = TABLEExt[n][B & 0xFF];
8189 movl(tmp1, in);
8190 andl(tmp1, 0x000000FF);
8191 shll(tmp1, 3);
8192 addq(tmp1, tmp3);
8193 movq(tmp1, Address(tmp1, 0));
8194
8195 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8196 movl(tmp2, in);
8197 shrl(tmp2, 8);
8198 andl(tmp2, 0x000000FF);
8199 shll(tmp2, 3);
8200 addq(tmp2, tmp3);
8201 movq(tmp2, Address(tmp2, 0));
8202
8203 shlq(tmp2, 8);
8204 xorq(tmp1, tmp2);
8205
8206 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8207 movl(tmp2, in);
8208 shrl(tmp2, 16);
8209 andl(tmp2, 0x000000FF);
8210 shll(tmp2, 3);
8211 addq(tmp2, tmp3);
8212 movq(tmp2, Address(tmp2, 0));
8213
8214 shlq(tmp2, 16);
8215 xorq(tmp1, tmp2);
8216
8217 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8218 shrl(in, 24);
8219 andl(in, 0x000000FF);
8220 shll(in, 3);
8221 addq(in, tmp3);
8222 movq(in, Address(in, 0));
8223
8224 shlq(in, 24);
8225 xorq(in, tmp1);
8226 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8227 }
8228
8229 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8230 Register in_out,
8231 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8232 XMMRegister w_xtmp2,
8233 Register tmp1,
8234 Register n_tmp2, Register n_tmp3) {
8235 if (is_pclmulqdq_supported) {
8236 movdl(w_xtmp1, in_out); // modified blindly
8237
8238 movl(tmp1, const_or_pre_comp_const_index);
8239 movdl(w_xtmp2, tmp1);
8240 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8241
8242 movdq(in_out, w_xtmp1);
8243 } else {
8244 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8245 }
8246 }
8247
8248 // Recombination Alternative 2: No bit-reflections
8249 // T1 = (CRC_A * U1) << 1
8250 // T2 = (CRC_B * U2) << 1
8251 // C1 = T1 >> 32
8252 // C2 = T2 >> 32
8253 // T1 = T1 & 0xFFFFFFFF
8254 // T2 = T2 & 0xFFFFFFFF
8255 // T1 = CRC32(0, T1)
8256 // T2 = CRC32(0, T2)
8257 // C1 = C1 ^ T1
8258 // C2 = C2 ^ T2
8259 // CRC = C1 ^ C2 ^ CRC_C
8260 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8261 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8262 Register tmp1, Register tmp2,
8263 Register n_tmp3) {
8264 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8265 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8266 shlq(in_out, 1);
8267 movl(tmp1, in_out);
8268 shrq(in_out, 32);
8269 xorl(tmp2, tmp2);
8270 crc32(tmp2, tmp1, 4);
8271 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8272 shlq(in1, 1);
8273 movl(tmp1, in1);
8274 shrq(in1, 32);
8275 xorl(tmp2, tmp2);
8276 crc32(tmp2, tmp1, 4);
8277 xorl(in1, tmp2);
8278 xorl(in_out, in1);
8279 xorl(in_out, in2);
8280 }
8281
8282 // Set N to predefined value
8283 // Subtract from a length of a buffer
8284 // execute in a loop:
8285 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8286 // for i = 1 to N do
8287 // CRC_A = CRC32(CRC_A, A[i])
8288 // CRC_B = CRC32(CRC_B, B[i])
8289 // CRC_C = CRC32(CRC_C, C[i])
8290 // end for
8291 // Recombine
8292 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8293 Register in_out1, Register in_out2, Register in_out3,
8294 Register tmp1, Register tmp2, Register tmp3,
8295 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8296 Register tmp4, Register tmp5,
8297 Register n_tmp6) {
8298 Label L_processPartitions;
8299 Label L_processPartition;
8300 Label L_exit;
8301
8302 bind(L_processPartitions);
8303 cmpl(in_out1, 3 * size);
8304 jcc(Assembler::less, L_exit);
8305 xorl(tmp1, tmp1);
8306 xorl(tmp2, tmp2);
8307 movq(tmp3, in_out2);
8308 addq(tmp3, size);
8309
8310 bind(L_processPartition);
8311 crc32(in_out3, Address(in_out2, 0), 8);
8312 crc32(tmp1, Address(in_out2, size), 8);
8313 crc32(tmp2, Address(in_out2, size * 2), 8);
8314 addq(in_out2, 8);
8315 cmpq(in_out2, tmp3);
8316 jcc(Assembler::less, L_processPartition);
8317 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8318 w_xtmp1, w_xtmp2, w_xtmp3,
8319 tmp4, tmp5,
8320 n_tmp6);
8321 addq(in_out2, 2 * size);
8322 subl(in_out1, 3 * size);
8323 jmp(L_processPartitions);
8324
8325 bind(L_exit);
8326 }
8327
8328 // Algorithm 2: Pipelined usage of the CRC32 instruction.
8329 // Input: A buffer I of L bytes.
8330 // Output: the CRC32C value of the buffer.
8331 // Notations:
8332 // Write L = 24N + r, with N = floor (L/24).
8333 // r = L mod 24 (0 <= r < 24).
8334 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
8335 // N quadwords, and R consists of r bytes.
8336 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
8337 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
8338 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
8339 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
8340 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
8341 Register tmp1, Register tmp2, Register tmp3,
8342 Register tmp4, Register tmp5, Register tmp6,
8343 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8344 bool is_pclmulqdq_supported) {
8345 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
8346 Label L_wordByWord;
8347 Label L_byteByByteProlog;
8348 Label L_byteByByte;
8349 Label L_exit;
8350
8351 if (is_pclmulqdq_supported ) {
8352 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
8353 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
8354
8355 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
8356 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
8357
8358 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
8359 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
8360 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
8361 } else {
8362 const_or_pre_comp_const_index[0] = 1;
8363 const_or_pre_comp_const_index[1] = 0;
8364
8365 const_or_pre_comp_const_index[2] = 3;
8366 const_or_pre_comp_const_index[3] = 2;
8367
8368 const_or_pre_comp_const_index[4] = 5;
8369 const_or_pre_comp_const_index[5] = 4;
8370 }
8371 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
8372 in2, in1, in_out,
8373 tmp1, tmp2, tmp3,
8374 w_xtmp1, w_xtmp2, w_xtmp3,
8375 tmp4, tmp5,
8376 tmp6);
8377 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
8378 in2, in1, in_out,
8379 tmp1, tmp2, tmp3,
8380 w_xtmp1, w_xtmp2, w_xtmp3,
8381 tmp4, tmp5,
8382 tmp6);
8383 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
8384 in2, in1, in_out,
8385 tmp1, tmp2, tmp3,
8386 w_xtmp1, w_xtmp2, w_xtmp3,
8387 tmp4, tmp5,
8388 tmp6);
8389 movl(tmp1, in2);
8390 andl(tmp1, 0x00000007);
8391 negl(tmp1);
8392 addl(tmp1, in2);
8393 addq(tmp1, in1);
8394
8395 cmpq(in1, tmp1);
8396 jccb(Assembler::greaterEqual, L_byteByByteProlog);
8397 align(16);
8398 BIND(L_wordByWord);
8399 crc32(in_out, Address(in1, 0), 8);
8400 addq(in1, 8);
8401 cmpq(in1, tmp1);
8402 jcc(Assembler::less, L_wordByWord);
8403
8404 BIND(L_byteByByteProlog);
8405 andl(in2, 0x00000007);
8406 movl(tmp2, 1);
8407
8408 cmpl(tmp2, in2);
8409 jccb(Assembler::greater, L_exit);
8410 BIND(L_byteByByte);
8411 crc32(in_out, Address(in1, 0), 1);
8412 incq(in1);
8413 incl(tmp2);
8414 cmpl(tmp2, in2);
8415 jcc(Assembler::lessEqual, L_byteByByte);
8416
8417 BIND(L_exit);
8418 }
8419 #undef BIND
8420 #undef BLOCK_COMMENT
8421
8422 // Compress char[] array to byte[].
8423 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
8424 // Return the array length if every element in array can be encoded,
8425 // otherwise, the index of first non-latin1 (> 0xff) character.
8426 // @IntrinsicCandidate
8427 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
8428 // for (int i = 0; i < len; i++) {
8429 // char c = src[srcOff];
8430 // if (c > 0xff) {
8431 // return i; // return index of non-latin1 char
8432 // }
8433 // dst[dstOff] = (byte)c;
8434 // srcOff++;
8435 // dstOff++;
8436 // }
8437 // return len;
8438 // }
8439 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
8440 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8441 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8442 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
8443 Label copy_chars_loop, done, reset_sp, copy_tail;
8444
8445 // rsi: src
8446 // rdi: dst
8447 // rdx: len
8448 // rcx: tmp5
8449 // rax: result
8450
8451 // rsi holds start addr of source char[] to be compressed
8452 // rdi holds start addr of destination byte[]
8453 // rdx holds length
8454
8455 assert(len != result, "");
8456
8457 // save length for return
8458 movl(result, len);
8459
8460 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
8461 VM_Version::supports_avx512vlbw() &&
8462 VM_Version::supports_bmi2()) {
8463
8464 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
8465
8466 // alignment
8467 Label post_alignment;
8468
8469 // if length of the string is less than 32, handle it the old fashioned way
8470 testl(len, -32);
8471 jcc(Assembler::zero, below_threshold);
8472
8473 // First check whether a character is compressible ( <= 0xFF).
8474 // Create mask to test for Unicode chars inside zmm vector
8475 movl(tmp5, 0x00FF);
8476 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
8477
8478 testl(len, -64);
8479 jccb(Assembler::zero, post_alignment);
8480
8481 movl(tmp5, dst);
8482 andl(tmp5, (32 - 1));
8483 negl(tmp5);
8484 andl(tmp5, (32 - 1));
8485
8486 // bail out when there is nothing to be done
8487 testl(tmp5, 0xFFFFFFFF);
8488 jccb(Assembler::zero, post_alignment);
8489
8490 // ~(~0 << len), where len is the # of remaining elements to process
8491 movl(len, 0xFFFFFFFF);
8492 shlxl(len, len, tmp5);
8493 notl(len);
8494 kmovdl(mask2, len);
8495 movl(len, result);
8496
8497 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
8498 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
8499 ktestd(mask1, mask2);
8500 jcc(Assembler::carryClear, copy_tail);
8501
8502 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
8503
8504 addptr(src, tmp5);
8505 addptr(src, tmp5);
8506 addptr(dst, tmp5);
8507 subl(len, tmp5);
8508
8509 bind(post_alignment);
8510 // end of alignment
8511
8512 movl(tmp5, len);
8513 andl(tmp5, (32 - 1)); // tail count (in chars)
8514 andl(len, ~(32 - 1)); // vector count (in chars)
8515 jccb(Assembler::zero, copy_loop_tail);
8516
8517 lea(src, Address(src, len, Address::times_2));
8518 lea(dst, Address(dst, len, Address::times_1));
8519 negptr(len);
8520
8521 bind(copy_32_loop);
8522 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
8523 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
8524 kortestdl(mask1, mask1);
8525 jccb(Assembler::carryClear, reset_for_copy_tail);
8526
8527 // All elements in current processed chunk are valid candidates for
8528 // compression. Write a truncated byte elements to the memory.
8529 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
8530 addptr(len, 32);
8531 jccb(Assembler::notZero, copy_32_loop);
8532
8533 bind(copy_loop_tail);
8534 // bail out when there is nothing to be done
8535 testl(tmp5, 0xFFFFFFFF);
8536 jcc(Assembler::zero, done);
8537
8538 movl(len, tmp5);
8539
8540 // ~(~0 << len), where len is the # of remaining elements to process
8541 movl(tmp5, 0xFFFFFFFF);
8542 shlxl(tmp5, tmp5, len);
8543 notl(tmp5);
8544
8545 kmovdl(mask2, tmp5);
8546
8547 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
8548 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
8549 ktestd(mask1, mask2);
8550 jcc(Assembler::carryClear, copy_tail);
8551
8552 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
8553 jmp(done);
8554
8555 bind(reset_for_copy_tail);
8556 lea(src, Address(src, tmp5, Address::times_2));
8557 lea(dst, Address(dst, tmp5, Address::times_1));
8558 subptr(len, tmp5);
8559 jmp(copy_chars_loop);
8560
8561 bind(below_threshold);
8562 }
8563
8564 if (UseSSE42Intrinsics) {
8565 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
8566
8567 // vectored compression
8568 testl(len, 0xfffffff8);
8569 jcc(Assembler::zero, copy_tail);
8570
8571 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
8572 movdl(tmp1Reg, tmp5);
8573 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
8574
8575 andl(len, 0xfffffff0);
8576 jccb(Assembler::zero, copy_16);
8577
8578 // compress 16 chars per iter
8579 pxor(tmp4Reg, tmp4Reg);
8580
8581 lea(src, Address(src, len, Address::times_2));
8582 lea(dst, Address(dst, len, Address::times_1));
8583 negptr(len);
8584
8585 bind(copy_32_loop);
8586 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
8587 por(tmp4Reg, tmp2Reg);
8588 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
8589 por(tmp4Reg, tmp3Reg);
8590 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
8591 jccb(Assembler::notZero, reset_for_copy_tail);
8592 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
8593 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
8594 addptr(len, 16);
8595 jccb(Assembler::notZero, copy_32_loop);
8596
8597 // compress next vector of 8 chars (if any)
8598 bind(copy_16);
8599 // len = 0
8600 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
8601 jccb(Assembler::zero, copy_tail_sse);
8602
8603 pxor(tmp3Reg, tmp3Reg);
8604
8605 movdqu(tmp2Reg, Address(src, 0));
8606 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8607 jccb(Assembler::notZero, reset_for_copy_tail);
8608 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
8609 movq(Address(dst, 0), tmp2Reg);
8610 addptr(src, 16);
8611 addptr(dst, 8);
8612 jmpb(copy_tail_sse);
8613
8614 bind(reset_for_copy_tail);
8615 movl(tmp5, result);
8616 andl(tmp5, 0x0000000f);
8617 lea(src, Address(src, tmp5, Address::times_2));
8618 lea(dst, Address(dst, tmp5, Address::times_1));
8619 subptr(len, tmp5);
8620 jmpb(copy_chars_loop);
8621
8622 bind(copy_tail_sse);
8623 movl(len, result);
8624 andl(len, 0x00000007); // tail count (in chars)
8625 }
8626 // compress 1 char per iter
8627 bind(copy_tail);
8628 testl(len, len);
8629 jccb(Assembler::zero, done);
8630 lea(src, Address(src, len, Address::times_2));
8631 lea(dst, Address(dst, len, Address::times_1));
8632 negptr(len);
8633
8634 bind(copy_chars_loop);
8635 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
8636 testl(tmp5, 0xff00); // check if Unicode char
8637 jccb(Assembler::notZero, reset_sp);
8638 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
8639 increment(len);
8640 jccb(Assembler::notZero, copy_chars_loop);
8641
8642 // add len then return (len will be zero if compress succeeded, otherwise negative)
8643 bind(reset_sp);
8644 addl(result, len);
8645
8646 bind(done);
8647 }
8648
8649 // Inflate byte[] array to char[].
8650 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
8651 // @IntrinsicCandidate
8652 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
8653 // for (int i = 0; i < len; i++) {
8654 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
8655 // }
8656 // }
8657 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
8658 XMMRegister tmp1, Register tmp2, KRegister mask) {
8659 Label copy_chars_loop, done, below_threshold, avx3_threshold;
8660 // rsi: src
8661 // rdi: dst
8662 // rdx: len
8663 // rcx: tmp2
8664
8665 // rsi holds start addr of source byte[] to be inflated
8666 // rdi holds start addr of destination char[]
8667 // rdx holds length
8668 assert_different_registers(src, dst, len, tmp2);
8669 movl(tmp2, len);
8670 if ((UseAVX > 2) && // AVX512
8671 VM_Version::supports_avx512vlbw() &&
8672 VM_Version::supports_bmi2()) {
8673
8674 Label copy_32_loop, copy_tail;
8675 Register tmp3_aliased = len;
8676
8677 // if length of the string is less than 16, handle it in an old fashioned way
8678 testl(len, -16);
8679 jcc(Assembler::zero, below_threshold);
8680
8681 testl(len, -1 * AVX3Threshold);
8682 jcc(Assembler::zero, avx3_threshold);
8683
8684 // In order to use only one arithmetic operation for the main loop we use
8685 // this pre-calculation
8686 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
8687 andl(len, -32); // vector count
8688 jccb(Assembler::zero, copy_tail);
8689
8690 lea(src, Address(src, len, Address::times_1));
8691 lea(dst, Address(dst, len, Address::times_2));
8692 negptr(len);
8693
8694
8695 // inflate 32 chars per iter
8696 bind(copy_32_loop);
8697 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
8698 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
8699 addptr(len, 32);
8700 jcc(Assembler::notZero, copy_32_loop);
8701
8702 bind(copy_tail);
8703 // bail out when there is nothing to be done
8704 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
8705 jcc(Assembler::zero, done);
8706
8707 // ~(~0 << length), where length is the # of remaining elements to process
8708 movl(tmp3_aliased, -1);
8709 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
8710 notl(tmp3_aliased);
8711 kmovdl(mask, tmp3_aliased);
8712 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
8713 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
8714
8715 jmp(done);
8716 bind(avx3_threshold);
8717 }
8718 if (UseSSE42Intrinsics) {
8719 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
8720
8721 if (UseAVX > 1) {
8722 andl(tmp2, (16 - 1));
8723 andl(len, -16);
8724 jccb(Assembler::zero, copy_new_tail);
8725 } else {
8726 andl(tmp2, 0x00000007); // tail count (in chars)
8727 andl(len, 0xfffffff8); // vector count (in chars)
8728 jccb(Assembler::zero, copy_tail);
8729 }
8730
8731 // vectored inflation
8732 lea(src, Address(src, len, Address::times_1));
8733 lea(dst, Address(dst, len, Address::times_2));
8734 negptr(len);
8735
8736 if (UseAVX > 1) {
8737 bind(copy_16_loop);
8738 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
8739 vmovdqu(Address(dst, len, Address::times_2), tmp1);
8740 addptr(len, 16);
8741 jcc(Assembler::notZero, copy_16_loop);
8742
8743 bind(below_threshold);
8744 bind(copy_new_tail);
8745 movl(len, tmp2);
8746 andl(tmp2, 0x00000007);
8747 andl(len, 0xFFFFFFF8);
8748 jccb(Assembler::zero, copy_tail);
8749
8750 pmovzxbw(tmp1, Address(src, 0));
8751 movdqu(Address(dst, 0), tmp1);
8752 addptr(src, 8);
8753 addptr(dst, 2 * 8);
8754
8755 jmp(copy_tail, true);
8756 }
8757
8758 // inflate 8 chars per iter
8759 bind(copy_8_loop);
8760 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
8761 movdqu(Address(dst, len, Address::times_2), tmp1);
8762 addptr(len, 8);
8763 jcc(Assembler::notZero, copy_8_loop);
8764
8765 bind(copy_tail);
8766 movl(len, tmp2);
8767
8768 cmpl(len, 4);
8769 jccb(Assembler::less, copy_bytes);
8770
8771 movdl(tmp1, Address(src, 0)); // load 4 byte chars
8772 pmovzxbw(tmp1, tmp1);
8773 movq(Address(dst, 0), tmp1);
8774 subptr(len, 4);
8775 addptr(src, 4);
8776 addptr(dst, 8);
8777
8778 bind(copy_bytes);
8779 } else {
8780 bind(below_threshold);
8781 }
8782
8783 testl(len, len);
8784 jccb(Assembler::zero, done);
8785 lea(src, Address(src, len, Address::times_1));
8786 lea(dst, Address(dst, len, Address::times_2));
8787 negptr(len);
8788
8789 // inflate 1 char per iter
8790 bind(copy_chars_loop);
8791 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
8792 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
8793 increment(len);
8794 jcc(Assembler::notZero, copy_chars_loop);
8795
8796 bind(done);
8797 }
8798
8799 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
8800 switch(type) {
8801 case T_BYTE:
8802 case T_BOOLEAN:
8803 evmovdqub(dst, kmask, src, merge, vector_len);
8804 break;
8805 case T_CHAR:
8806 case T_SHORT:
8807 evmovdquw(dst, kmask, src, merge, vector_len);
8808 break;
8809 case T_INT:
8810 case T_FLOAT:
8811 evmovdqul(dst, kmask, src, merge, vector_len);
8812 break;
8813 case T_LONG:
8814 case T_DOUBLE:
8815 evmovdquq(dst, kmask, src, merge, vector_len);
8816 break;
8817 default:
8818 fatal("Unexpected type argument %s", type2name(type));
8819 break;
8820 }
8821 }
8822
8823
8824 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
8825 switch(type) {
8826 case T_BYTE:
8827 case T_BOOLEAN:
8828 evmovdqub(dst, kmask, src, merge, vector_len);
8829 break;
8830 case T_CHAR:
8831 case T_SHORT:
8832 evmovdquw(dst, kmask, src, merge, vector_len);
8833 break;
8834 case T_INT:
8835 case T_FLOAT:
8836 evmovdqul(dst, kmask, src, merge, vector_len);
8837 break;
8838 case T_LONG:
8839 case T_DOUBLE:
8840 evmovdquq(dst, kmask, src, merge, vector_len);
8841 break;
8842 default:
8843 fatal("Unexpected type argument %s", type2name(type));
8844 break;
8845 }
8846 }
8847
8848 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
8849 switch(type) {
8850 case T_BYTE:
8851 case T_BOOLEAN:
8852 evmovdqub(dst, kmask, src, merge, vector_len);
8853 break;
8854 case T_CHAR:
8855 case T_SHORT:
8856 evmovdquw(dst, kmask, src, merge, vector_len);
8857 break;
8858 case T_INT:
8859 case T_FLOAT:
8860 evmovdqul(dst, kmask, src, merge, vector_len);
8861 break;
8862 case T_LONG:
8863 case T_DOUBLE:
8864 evmovdquq(dst, kmask, src, merge, vector_len);
8865 break;
8866 default:
8867 fatal("Unexpected type argument %s", type2name(type));
8868 break;
8869 }
8870 }
8871
8872 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
8873 switch(masklen) {
8874 case 2:
8875 knotbl(dst, src);
8876 movl(rtmp, 3);
8877 kmovbl(ktmp, rtmp);
8878 kandbl(dst, ktmp, dst);
8879 break;
8880 case 4:
8881 knotbl(dst, src);
8882 movl(rtmp, 15);
8883 kmovbl(ktmp, rtmp);
8884 kandbl(dst, ktmp, dst);
8885 break;
8886 case 8:
8887 knotbl(dst, src);
8888 break;
8889 case 16:
8890 knotwl(dst, src);
8891 break;
8892 case 32:
8893 knotdl(dst, src);
8894 break;
8895 case 64:
8896 knotql(dst, src);
8897 break;
8898 default:
8899 fatal("Unexpected vector length %d", masklen);
8900 break;
8901 }
8902 }
8903
8904 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8905 switch(type) {
8906 case T_BOOLEAN:
8907 case T_BYTE:
8908 kandbl(dst, src1, src2);
8909 break;
8910 case T_CHAR:
8911 case T_SHORT:
8912 kandwl(dst, src1, src2);
8913 break;
8914 case T_INT:
8915 case T_FLOAT:
8916 kanddl(dst, src1, src2);
8917 break;
8918 case T_LONG:
8919 case T_DOUBLE:
8920 kandql(dst, src1, src2);
8921 break;
8922 default:
8923 fatal("Unexpected type argument %s", type2name(type));
8924 break;
8925 }
8926 }
8927
8928 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8929 switch(type) {
8930 case T_BOOLEAN:
8931 case T_BYTE:
8932 korbl(dst, src1, src2);
8933 break;
8934 case T_CHAR:
8935 case T_SHORT:
8936 korwl(dst, src1, src2);
8937 break;
8938 case T_INT:
8939 case T_FLOAT:
8940 kordl(dst, src1, src2);
8941 break;
8942 case T_LONG:
8943 case T_DOUBLE:
8944 korql(dst, src1, src2);
8945 break;
8946 default:
8947 fatal("Unexpected type argument %s", type2name(type));
8948 break;
8949 }
8950 }
8951
8952 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8953 switch(type) {
8954 case T_BOOLEAN:
8955 case T_BYTE:
8956 kxorbl(dst, src1, src2);
8957 break;
8958 case T_CHAR:
8959 case T_SHORT:
8960 kxorwl(dst, src1, src2);
8961 break;
8962 case T_INT:
8963 case T_FLOAT:
8964 kxordl(dst, src1, src2);
8965 break;
8966 case T_LONG:
8967 case T_DOUBLE:
8968 kxorql(dst, src1, src2);
8969 break;
8970 default:
8971 fatal("Unexpected type argument %s", type2name(type));
8972 break;
8973 }
8974 }
8975
8976 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8977 switch(type) {
8978 case T_BOOLEAN:
8979 case T_BYTE:
8980 evpermb(dst, mask, nds, src, merge, vector_len); break;
8981 case T_CHAR:
8982 case T_SHORT:
8983 evpermw(dst, mask, nds, src, merge, vector_len); break;
8984 case T_INT:
8985 case T_FLOAT:
8986 evpermd(dst, mask, nds, src, merge, vector_len); break;
8987 case T_LONG:
8988 case T_DOUBLE:
8989 evpermq(dst, mask, nds, src, merge, vector_len); break;
8990 default:
8991 fatal("Unexpected type argument %s", type2name(type)); break;
8992 }
8993 }
8994
8995 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8996 switch(type) {
8997 case T_BOOLEAN:
8998 case T_BYTE:
8999 evpermb(dst, mask, nds, src, merge, vector_len); break;
9000 case T_CHAR:
9001 case T_SHORT:
9002 evpermw(dst, mask, nds, src, merge, vector_len); break;
9003 case T_INT:
9004 case T_FLOAT:
9005 evpermd(dst, mask, nds, src, merge, vector_len); break;
9006 case T_LONG:
9007 case T_DOUBLE:
9008 evpermq(dst, mask, nds, src, merge, vector_len); break;
9009 default:
9010 fatal("Unexpected type argument %s", type2name(type)); break;
9011 }
9012 }
9013
9014 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9015 switch(type) {
9016 case T_BYTE:
9017 evpminub(dst, mask, nds, src, merge, vector_len); break;
9018 case T_SHORT:
9019 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9020 case T_INT:
9021 evpminud(dst, mask, nds, src, merge, vector_len); break;
9022 case T_LONG:
9023 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9024 default:
9025 fatal("Unexpected type argument %s", type2name(type)); break;
9026 }
9027 }
9028
9029 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9030 switch(type) {
9031 case T_BYTE:
9032 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9033 case T_SHORT:
9034 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9035 case T_INT:
9036 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9037 case T_LONG:
9038 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9039 default:
9040 fatal("Unexpected type argument %s", type2name(type)); break;
9041 }
9042 }
9043
9044 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9045 switch(type) {
9046 case T_BYTE:
9047 evpminub(dst, mask, nds, src, merge, vector_len); break;
9048 case T_SHORT:
9049 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9050 case T_INT:
9051 evpminud(dst, mask, nds, src, merge, vector_len); break;
9052 case T_LONG:
9053 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9054 default:
9055 fatal("Unexpected type argument %s", type2name(type)); break;
9056 }
9057 }
9058
9059 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9060 switch(type) {
9061 case T_BYTE:
9062 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9063 case T_SHORT:
9064 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9065 case T_INT:
9066 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9067 case T_LONG:
9068 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9069 default:
9070 fatal("Unexpected type argument %s", type2name(type)); break;
9071 }
9072 }
9073
9074 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9075 switch(type) {
9076 case T_BYTE:
9077 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9078 case T_SHORT:
9079 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9080 case T_INT:
9081 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9082 case T_LONG:
9083 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9084 case T_FLOAT:
9085 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9086 case T_DOUBLE:
9087 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9088 default:
9089 fatal("Unexpected type argument %s", type2name(type)); break;
9090 }
9091 }
9092
9093 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9094 switch(type) {
9095 case T_BYTE:
9096 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9097 case T_SHORT:
9098 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9099 case T_INT:
9100 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9101 case T_LONG:
9102 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9103 case T_FLOAT:
9104 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9105 case T_DOUBLE:
9106 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9107 default:
9108 fatal("Unexpected type argument %s", type2name(type)); break;
9109 }
9110 }
9111
9112 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9113 switch(type) {
9114 case T_BYTE:
9115 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9116 case T_SHORT:
9117 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9118 case T_INT:
9119 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9120 case T_LONG:
9121 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9122 case T_FLOAT:
9123 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9124 case T_DOUBLE:
9125 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9126 default:
9127 fatal("Unexpected type argument %s", type2name(type)); break;
9128 }
9129 }
9130
9131 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9132 switch(type) {
9133 case T_BYTE:
9134 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9135 case T_SHORT:
9136 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9137 case T_INT:
9138 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9139 case T_LONG:
9140 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9141 case T_FLOAT:
9142 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9143 case T_DOUBLE:
9144 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9145 default:
9146 fatal("Unexpected type argument %s", type2name(type)); break;
9147 }
9148 }
9149
9150 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9151 switch(type) {
9152 case T_INT:
9153 evpxord(dst, mask, nds, src, merge, vector_len); break;
9154 case T_LONG:
9155 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9156 default:
9157 fatal("Unexpected type argument %s", type2name(type)); break;
9158 }
9159 }
9160
9161 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9162 switch(type) {
9163 case T_INT:
9164 evpxord(dst, mask, nds, src, merge, vector_len); break;
9165 case T_LONG:
9166 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9167 default:
9168 fatal("Unexpected type argument %s", type2name(type)); break;
9169 }
9170 }
9171
9172 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9173 switch(type) {
9174 case T_INT:
9175 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9176 case T_LONG:
9177 evporq(dst, mask, nds, src, merge, vector_len); break;
9178 default:
9179 fatal("Unexpected type argument %s", type2name(type)); break;
9180 }
9181 }
9182
9183 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9184 switch(type) {
9185 case T_INT:
9186 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9187 case T_LONG:
9188 evporq(dst, mask, nds, src, merge, vector_len); break;
9189 default:
9190 fatal("Unexpected type argument %s", type2name(type)); break;
9191 }
9192 }
9193
9194 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9195 switch(type) {
9196 case T_INT:
9197 evpandd(dst, mask, nds, src, merge, vector_len); break;
9198 case T_LONG:
9199 evpandq(dst, mask, nds, src, merge, vector_len); break;
9200 default:
9201 fatal("Unexpected type argument %s", type2name(type)); break;
9202 }
9203 }
9204
9205 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9206 switch(type) {
9207 case T_INT:
9208 evpandd(dst, mask, nds, src, merge, vector_len); break;
9209 case T_LONG:
9210 evpandq(dst, mask, nds, src, merge, vector_len); break;
9211 default:
9212 fatal("Unexpected type argument %s", type2name(type)); break;
9213 }
9214 }
9215
9216 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
9217 switch(masklen) {
9218 case 8:
9219 kortestbl(src1, src2);
9220 break;
9221 case 16:
9222 kortestwl(src1, src2);
9223 break;
9224 case 32:
9225 kortestdl(src1, src2);
9226 break;
9227 case 64:
9228 kortestql(src1, src2);
9229 break;
9230 default:
9231 fatal("Unexpected mask length %d", masklen);
9232 break;
9233 }
9234 }
9235
9236
9237 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
9238 switch(masklen) {
9239 case 8:
9240 ktestbl(src1, src2);
9241 break;
9242 case 16:
9243 ktestwl(src1, src2);
9244 break;
9245 case 32:
9246 ktestdl(src1, src2);
9247 break;
9248 case 64:
9249 ktestql(src1, src2);
9250 break;
9251 default:
9252 fatal("Unexpected mask length %d", masklen);
9253 break;
9254 }
9255 }
9256
9257 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9258 switch(type) {
9259 case T_INT:
9260 evprold(dst, mask, src, shift, merge, vlen_enc); break;
9261 case T_LONG:
9262 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
9263 default:
9264 fatal("Unexpected type argument %s", type2name(type)); break;
9265 break;
9266 }
9267 }
9268
9269 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9270 switch(type) {
9271 case T_INT:
9272 evprord(dst, mask, src, shift, merge, vlen_enc); break;
9273 case T_LONG:
9274 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
9275 default:
9276 fatal("Unexpected type argument %s", type2name(type)); break;
9277 }
9278 }
9279
9280 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
9281 switch(type) {
9282 case T_INT:
9283 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
9284 case T_LONG:
9285 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
9286 default:
9287 fatal("Unexpected type argument %s", type2name(type)); break;
9288 }
9289 }
9290
9291 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
9292 switch(type) {
9293 case T_INT:
9294 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
9295 case T_LONG:
9296 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
9297 default:
9298 fatal("Unexpected type argument %s", type2name(type)); break;
9299 }
9300 }
9301
9302 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9303 assert(rscratch != noreg || always_reachable(src), "missing");
9304
9305 if (reachable(src)) {
9306 evpandq(dst, nds, as_Address(src), vector_len);
9307 } else {
9308 lea(rscratch, src);
9309 evpandq(dst, nds, Address(rscratch, 0), vector_len);
9310 }
9311 }
9312
9313 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
9314 assert(rscratch != noreg || always_reachable(src), "missing");
9315
9316 if (reachable(src)) {
9317 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
9318 } else {
9319 lea(rscratch, src);
9320 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
9321 }
9322 }
9323
9324 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9325 assert(rscratch != noreg || always_reachable(src), "missing");
9326
9327 if (reachable(src)) {
9328 evporq(dst, nds, as_Address(src), vector_len);
9329 } else {
9330 lea(rscratch, src);
9331 evporq(dst, nds, Address(rscratch, 0), vector_len);
9332 }
9333 }
9334
9335 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9336 assert(rscratch != noreg || always_reachable(src), "missing");
9337
9338 if (reachable(src)) {
9339 vpshufb(dst, nds, as_Address(src), vector_len);
9340 } else {
9341 lea(rscratch, src);
9342 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
9343 }
9344 }
9345
9346 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9347 assert(rscratch != noreg || always_reachable(src), "missing");
9348
9349 if (reachable(src)) {
9350 Assembler::vpor(dst, nds, as_Address(src), vector_len);
9351 } else {
9352 lea(rscratch, src);
9353 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
9354 }
9355 }
9356
9357 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
9358 assert(rscratch != noreg || always_reachable(src3), "missing");
9359
9360 if (reachable(src3)) {
9361 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
9362 } else {
9363 lea(rscratch, src3);
9364 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
9365 }
9366 }
9367
9368 #if COMPILER2_OR_JVMCI
9369
9370 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
9371 Register length, Register temp, int vec_enc) {
9372 // Computing mask for predicated vector store.
9373 movptr(temp, -1);
9374 bzhiq(temp, temp, length);
9375 kmov(mask, temp);
9376 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
9377 }
9378
9379 // Set memory operation for length "less than" 64 bytes.
9380 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
9381 XMMRegister xmm, KRegister mask, Register length,
9382 Register temp, bool use64byteVector) {
9383 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9384 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
9385 if (!use64byteVector) {
9386 fill32(dst, disp, xmm);
9387 subptr(length, 32 >> shift);
9388 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
9389 } else {
9390 assert(MaxVectorSize == 64, "vector length != 64");
9391 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
9392 }
9393 }
9394
9395
9396 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
9397 XMMRegister xmm, KRegister mask, Register length,
9398 Register temp) {
9399 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9400 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
9401 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
9402 }
9403
9404
9405 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
9406 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9407 vmovdqu(dst, xmm);
9408 }
9409
9410 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
9411 fill32(Address(dst, disp), xmm);
9412 }
9413
9414 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
9415 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9416 if (!use64byteVector) {
9417 fill32(dst, xmm);
9418 fill32(dst.plus_disp(32), xmm);
9419 } else {
9420 evmovdquq(dst, xmm, Assembler::AVX_512bit);
9421 }
9422 }
9423
9424 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
9425 fill64(Address(dst, disp), xmm, use64byteVector);
9426 }
9427
9428 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
9429 Register count, Register rtmp, XMMRegister xtmp) {
9430 Label L_exit;
9431 Label L_fill_start;
9432 Label L_fill_64_bytes;
9433 Label L_fill_96_bytes;
9434 Label L_fill_128_bytes;
9435 Label L_fill_128_bytes_loop;
9436 Label L_fill_128_loop_header;
9437 Label L_fill_128_bytes_loop_header;
9438 Label L_fill_128_bytes_loop_pre_header;
9439 Label L_fill_zmm_sequence;
9440
9441 int shift = -1;
9442 int avx3threshold = VM_Version::avx3_threshold();
9443 switch(type) {
9444 case T_BYTE: shift = 0;
9445 break;
9446 case T_SHORT: shift = 1;
9447 break;
9448 case T_INT: shift = 2;
9449 break;
9450 /* Uncomment when LONG fill stubs are supported.
9451 case T_LONG: shift = 3;
9452 break;
9453 */
9454 default:
9455 fatal("Unhandled type: %s\n", type2name(type));
9456 }
9457
9458 if ((avx3threshold != 0) || (MaxVectorSize == 32)) {
9459
9460 if (MaxVectorSize == 64) {
9461 cmpq(count, avx3threshold >> shift);
9462 jcc(Assembler::greater, L_fill_zmm_sequence);
9463 }
9464
9465 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
9466
9467 bind(L_fill_start);
9468
9469 cmpq(count, 32 >> shift);
9470 jccb(Assembler::greater, L_fill_64_bytes);
9471 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
9472 jmp(L_exit);
9473
9474 bind(L_fill_64_bytes);
9475 cmpq(count, 64 >> shift);
9476 jccb(Assembler::greater, L_fill_96_bytes);
9477 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
9478 jmp(L_exit);
9479
9480 bind(L_fill_96_bytes);
9481 cmpq(count, 96 >> shift);
9482 jccb(Assembler::greater, L_fill_128_bytes);
9483 fill64(to, 0, xtmp);
9484 subq(count, 64 >> shift);
9485 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
9486 jmp(L_exit);
9487
9488 bind(L_fill_128_bytes);
9489 cmpq(count, 128 >> shift);
9490 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
9491 fill64(to, 0, xtmp);
9492 fill32(to, 64, xtmp);
9493 subq(count, 96 >> shift);
9494 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
9495 jmp(L_exit);
9496
9497 bind(L_fill_128_bytes_loop_pre_header);
9498 {
9499 mov(rtmp, to);
9500 andq(rtmp, 31);
9501 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
9502 negq(rtmp);
9503 addq(rtmp, 32);
9504 mov64(r8, -1L);
9505 bzhiq(r8, r8, rtmp);
9506 kmovql(k2, r8);
9507 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
9508 addq(to, rtmp);
9509 shrq(rtmp, shift);
9510 subq(count, rtmp);
9511 }
9512
9513 cmpq(count, 128 >> shift);
9514 jcc(Assembler::less, L_fill_start);
9515
9516 bind(L_fill_128_bytes_loop_header);
9517 subq(count, 128 >> shift);
9518
9519 align32();
9520 bind(L_fill_128_bytes_loop);
9521 fill64(to, 0, xtmp);
9522 fill64(to, 64, xtmp);
9523 addq(to, 128);
9524 subq(count, 128 >> shift);
9525 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
9526
9527 addq(count, 128 >> shift);
9528 jcc(Assembler::zero, L_exit);
9529 jmp(L_fill_start);
9530 }
9531
9532 if (MaxVectorSize == 64) {
9533 // Sequence using 64 byte ZMM register.
9534 Label L_fill_128_bytes_zmm;
9535 Label L_fill_192_bytes_zmm;
9536 Label L_fill_192_bytes_loop_zmm;
9537 Label L_fill_192_bytes_loop_header_zmm;
9538 Label L_fill_192_bytes_loop_pre_header_zmm;
9539 Label L_fill_start_zmm_sequence;
9540
9541 bind(L_fill_zmm_sequence);
9542 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
9543
9544 bind(L_fill_start_zmm_sequence);
9545 cmpq(count, 64 >> shift);
9546 jccb(Assembler::greater, L_fill_128_bytes_zmm);
9547 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
9548 jmp(L_exit);
9549
9550 bind(L_fill_128_bytes_zmm);
9551 cmpq(count, 128 >> shift);
9552 jccb(Assembler::greater, L_fill_192_bytes_zmm);
9553 fill64(to, 0, xtmp, true);
9554 subq(count, 64 >> shift);
9555 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
9556 jmp(L_exit);
9557
9558 bind(L_fill_192_bytes_zmm);
9559 cmpq(count, 192 >> shift);
9560 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
9561 fill64(to, 0, xtmp, true);
9562 fill64(to, 64, xtmp, true);
9563 subq(count, 128 >> shift);
9564 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
9565 jmp(L_exit);
9566
9567 bind(L_fill_192_bytes_loop_pre_header_zmm);
9568 {
9569 movq(rtmp, to);
9570 andq(rtmp, 63);
9571 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
9572 negq(rtmp);
9573 addq(rtmp, 64);
9574 mov64(r8, -1L);
9575 bzhiq(r8, r8, rtmp);
9576 kmovql(k2, r8);
9577 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
9578 addq(to, rtmp);
9579 shrq(rtmp, shift);
9580 subq(count, rtmp);
9581 }
9582
9583 cmpq(count, 192 >> shift);
9584 jcc(Assembler::less, L_fill_start_zmm_sequence);
9585
9586 bind(L_fill_192_bytes_loop_header_zmm);
9587 subq(count, 192 >> shift);
9588
9589 align32();
9590 bind(L_fill_192_bytes_loop_zmm);
9591 fill64(to, 0, xtmp, true);
9592 fill64(to, 64, xtmp, true);
9593 fill64(to, 128, xtmp, true);
9594 addq(to, 192);
9595 subq(count, 192 >> shift);
9596 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
9597
9598 addq(count, 192 >> shift);
9599 jcc(Assembler::zero, L_exit);
9600 jmp(L_fill_start_zmm_sequence);
9601 }
9602 bind(L_exit);
9603 }
9604 #endif //COMPILER2_OR_JVMCI
9605
9606
9607 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
9608 Label done;
9609 cvttss2sil(dst, src);
9610 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
9611 cmpl(dst, 0x80000000); // float_sign_flip
9612 jccb(Assembler::notEqual, done);
9613 subptr(rsp, 8);
9614 movflt(Address(rsp, 0), src);
9615 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9616 pop(dst);
9617 bind(done);
9618 }
9619
9620 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
9621 Label done;
9622 cvttsd2sil(dst, src);
9623 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
9624 cmpl(dst, 0x80000000); // float_sign_flip
9625 jccb(Assembler::notEqual, done);
9626 subptr(rsp, 8);
9627 movdbl(Address(rsp, 0), src);
9628 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
9629 pop(dst);
9630 bind(done);
9631 }
9632
9633 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
9634 Label done;
9635 cvttss2siq(dst, src);
9636 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9637 jccb(Assembler::notEqual, done);
9638 subptr(rsp, 8);
9639 movflt(Address(rsp, 0), src);
9640 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
9641 pop(dst);
9642 bind(done);
9643 }
9644
9645 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
9646 // Following code is line by line assembly translation rounding algorithm.
9647 // Please refer to java.lang.Math.round(float) algorithm for details.
9648 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
9649 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
9650 const int32_t FloatConsts_EXP_BIAS = 127;
9651 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
9652 const int32_t MINUS_32 = 0xFFFFFFE0;
9653 Label L_special_case, L_block1, L_exit;
9654 movl(rtmp, FloatConsts_EXP_BIT_MASK);
9655 movdl(dst, src);
9656 andl(dst, rtmp);
9657 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
9658 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
9659 subl(rtmp, dst);
9660 movl(rcx, rtmp);
9661 movl(dst, MINUS_32);
9662 testl(rtmp, dst);
9663 jccb(Assembler::notEqual, L_special_case);
9664 movdl(dst, src);
9665 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
9666 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
9667 movdl(rtmp, src);
9668 testl(rtmp, rtmp);
9669 jccb(Assembler::greaterEqual, L_block1);
9670 negl(dst);
9671 bind(L_block1);
9672 sarl(dst);
9673 addl(dst, 0x1);
9674 sarl(dst, 0x1);
9675 jmp(L_exit);
9676 bind(L_special_case);
9677 convert_f2i(dst, src);
9678 bind(L_exit);
9679 }
9680
9681 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
9682 // Following code is line by line assembly translation rounding algorithm.
9683 // Please refer to java.lang.Math.round(double) algorithm for details.
9684 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
9685 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
9686 const int64_t DoubleConsts_EXP_BIAS = 1023;
9687 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
9688 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
9689 Label L_special_case, L_block1, L_exit;
9690 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
9691 movq(dst, src);
9692 andq(dst, rtmp);
9693 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
9694 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
9695 subq(rtmp, dst);
9696 movq(rcx, rtmp);
9697 mov64(dst, MINUS_64);
9698 testq(rtmp, dst);
9699 jccb(Assembler::notEqual, L_special_case);
9700 movq(dst, src);
9701 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
9702 andq(dst, rtmp);
9703 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
9704 orq(dst, rtmp);
9705 movq(rtmp, src);
9706 testq(rtmp, rtmp);
9707 jccb(Assembler::greaterEqual, L_block1);
9708 negq(dst);
9709 bind(L_block1);
9710 sarq(dst);
9711 addq(dst, 0x1);
9712 sarq(dst, 0x1);
9713 jmp(L_exit);
9714 bind(L_special_case);
9715 convert_d2l(dst, src);
9716 bind(L_exit);
9717 }
9718
9719 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
9720 Label done;
9721 cvttsd2siq(dst, src);
9722 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9723 jccb(Assembler::notEqual, done);
9724 subptr(rsp, 8);
9725 movdbl(Address(rsp, 0), src);
9726 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
9727 pop(dst);
9728 bind(done);
9729 }
9730
9731 void MacroAssembler::cache_wb(Address line)
9732 {
9733 // 64 bit cpus always support clflush
9734 assert(VM_Version::supports_clflush(), "clflush should be available");
9735 bool optimized = VM_Version::supports_clflushopt();
9736 bool no_evict = VM_Version::supports_clwb();
9737
9738 // prefer clwb (writeback without evict) otherwise
9739 // prefer clflushopt (potentially parallel writeback with evict)
9740 // otherwise fallback on clflush (serial writeback with evict)
9741
9742 if (optimized) {
9743 if (no_evict) {
9744 clwb(line);
9745 } else {
9746 clflushopt(line);
9747 }
9748 } else {
9749 // no need for fence when using CLFLUSH
9750 clflush(line);
9751 }
9752 }
9753
9754 void MacroAssembler::cache_wbsync(bool is_pre)
9755 {
9756 assert(VM_Version::supports_clflush(), "clflush should be available");
9757 bool optimized = VM_Version::supports_clflushopt();
9758 bool no_evict = VM_Version::supports_clwb();
9759
9760 // pick the correct implementation
9761
9762 if (!is_pre && (optimized || no_evict)) {
9763 // need an sfence for post flush when using clflushopt or clwb
9764 // otherwise no no need for any synchroniaztion
9765
9766 sfence();
9767 }
9768 }
9769
9770 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
9771 switch (cond) {
9772 // Note some conditions are synonyms for others
9773 case Assembler::zero: return Assembler::notZero;
9774 case Assembler::notZero: return Assembler::zero;
9775 case Assembler::less: return Assembler::greaterEqual;
9776 case Assembler::lessEqual: return Assembler::greater;
9777 case Assembler::greater: return Assembler::lessEqual;
9778 case Assembler::greaterEqual: return Assembler::less;
9779 case Assembler::below: return Assembler::aboveEqual;
9780 case Assembler::belowEqual: return Assembler::above;
9781 case Assembler::above: return Assembler::belowEqual;
9782 case Assembler::aboveEqual: return Assembler::below;
9783 case Assembler::overflow: return Assembler::noOverflow;
9784 case Assembler::noOverflow: return Assembler::overflow;
9785 case Assembler::negative: return Assembler::positive;
9786 case Assembler::positive: return Assembler::negative;
9787 case Assembler::parity: return Assembler::noParity;
9788 case Assembler::noParity: return Assembler::parity;
9789 }
9790 ShouldNotReachHere(); return Assembler::overflow;
9791 }
9792
9793 // This is simply a call to Thread::current()
9794 void MacroAssembler::get_thread_slow(Register thread) {
9795 if (thread != rax) {
9796 push(rax);
9797 }
9798 push(rdi);
9799 push(rsi);
9800 push(rdx);
9801 push(rcx);
9802 push(r8);
9803 push(r9);
9804 push(r10);
9805 push(r11);
9806
9807 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
9808
9809 pop(r11);
9810 pop(r10);
9811 pop(r9);
9812 pop(r8);
9813 pop(rcx);
9814 pop(rdx);
9815 pop(rsi);
9816 pop(rdi);
9817 if (thread != rax) {
9818 mov(thread, rax);
9819 pop(rax);
9820 }
9821 }
9822
9823 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
9824 Label L_stack_ok;
9825 if (bias == 0) {
9826 testptr(sp, 2 * wordSize - 1);
9827 } else {
9828 // lea(tmp, Address(rsp, bias);
9829 mov(tmp, sp);
9830 addptr(tmp, bias);
9831 testptr(tmp, 2 * wordSize - 1);
9832 }
9833 jcc(Assembler::equal, L_stack_ok);
9834 block_comment(msg);
9835 stop(msg);
9836 bind(L_stack_ok);
9837 }
9838
9839 // Implements fast-locking.
9840 //
9841 // obj: the object to be locked
9842 // reg_rax: rax
9843 // thread: the thread which attempts to lock obj
9844 // tmp: a temporary register
9845 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register reg_rax, Register tmp, Label& slow) {
9846 Register thread = r15_thread;
9847
9848 assert(reg_rax == rax, "");
9849 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
9850
9851 Label push;
9852 const Register top = tmp;
9853
9854 // Preload the markWord. It is important that this is the first
9855 // instruction emitted as it is part of C1's null check semantics.
9856 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
9857
9858 if (UseObjectMonitorTable) {
9859 // Clear cache in case fast locking succeeds or we need to take the slow-path.
9860 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
9861 }
9862
9863 if (DiagnoseSyncOnValueBasedClasses != 0) {
9864 load_klass(tmp, obj, rscratch1);
9865 testb(Address(tmp, Klass::misc_flags_offset()), KlassFlags::_misc_is_value_based_class);
9866 jcc(Assembler::notZero, slow);
9867 }
9868
9869 // Load top.
9870 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
9871
9872 // Check if the lock-stack is full.
9873 cmpl(top, LockStack::end_offset());
9874 jcc(Assembler::greaterEqual, slow);
9875
9876 // Check for recursion.
9877 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
9878 jcc(Assembler::equal, push);
9879
9880 // Check header for monitor (0b10).
9881 testptr(reg_rax, markWord::monitor_value);
9882 jcc(Assembler::notZero, slow);
9883
9884 // Try to lock. Transition lock bits 0b01 => 0b00
9885 movptr(tmp, reg_rax);
9886 andptr(tmp, ~(int32_t)markWord::unlocked_value);
9887 orptr(reg_rax, markWord::unlocked_value);
9888 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
9889 jcc(Assembler::notEqual, slow);
9890
9891 // Restore top, CAS clobbers register.
9892 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
9893
9894 bind(push);
9895 // After successful lock, push object on lock-stack.
9896 movptr(Address(thread, top), obj);
9897 incrementl(top, oopSize);
9898 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
9899 }
9900
9901 // Implements fast-unlocking.
9902 //
9903 // obj: the object to be unlocked
9904 // reg_rax: rax
9905 // thread: the thread
9906 // tmp: a temporary register
9907 void MacroAssembler::fast_unlock(Register obj, Register reg_rax, Register tmp, Label& slow) {
9908 Register thread = r15_thread;
9909
9910 assert(reg_rax == rax, "");
9911 assert_different_registers(obj, reg_rax, thread, tmp);
9912
9913 Label unlocked, push_and_slow;
9914 const Register top = tmp;
9915
9916 // Check if obj is top of lock-stack.
9917 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
9918 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
9919 jcc(Assembler::notEqual, slow);
9920
9921 // Pop lock-stack.
9922 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
9923 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
9924
9925 // Check if recursive.
9926 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
9927 jcc(Assembler::equal, unlocked);
9928
9929 // Not recursive. Check header for monitor (0b10).
9930 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
9931 testptr(reg_rax, markWord::monitor_value);
9932 jcc(Assembler::notZero, push_and_slow);
9933
9934 #ifdef ASSERT
9935 // Check header not unlocked (0b01).
9936 Label not_unlocked;
9937 testptr(reg_rax, markWord::unlocked_value);
9938 jcc(Assembler::zero, not_unlocked);
9939 stop("fast_unlock already unlocked");
9940 bind(not_unlocked);
9941 #endif
9942
9943 // Try to unlock. Transition lock bits 0b00 => 0b01
9944 movptr(tmp, reg_rax);
9945 orptr(tmp, markWord::unlocked_value);
9946 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
9947 jcc(Assembler::equal, unlocked);
9948
9949 bind(push_and_slow);
9950 // Restore lock-stack and handle the unlock in runtime.
9951 #ifdef ASSERT
9952 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
9953 movptr(Address(thread, top), obj);
9954 #endif
9955 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
9956 jmp(slow);
9957
9958 bind(unlocked);
9959 }
9960
9961 // Saves legacy GPRs state on stack.
9962 void MacroAssembler::save_legacy_gprs() {
9963 subq(rsp, 16 * wordSize);
9964 movq(Address(rsp, 15 * wordSize), rax);
9965 movq(Address(rsp, 14 * wordSize), rcx);
9966 movq(Address(rsp, 13 * wordSize), rdx);
9967 movq(Address(rsp, 12 * wordSize), rbx);
9968 movq(Address(rsp, 10 * wordSize), rbp);
9969 movq(Address(rsp, 9 * wordSize), rsi);
9970 movq(Address(rsp, 8 * wordSize), rdi);
9971 movq(Address(rsp, 7 * wordSize), r8);
9972 movq(Address(rsp, 6 * wordSize), r9);
9973 movq(Address(rsp, 5 * wordSize), r10);
9974 movq(Address(rsp, 4 * wordSize), r11);
9975 movq(Address(rsp, 3 * wordSize), r12);
9976 movq(Address(rsp, 2 * wordSize), r13);
9977 movq(Address(rsp, wordSize), r14);
9978 movq(Address(rsp, 0), r15);
9979 }
9980
9981 // Resotres back legacy GPRs state from stack.
9982 void MacroAssembler::restore_legacy_gprs() {
9983 movq(r15, Address(rsp, 0));
9984 movq(r14, Address(rsp, wordSize));
9985 movq(r13, Address(rsp, 2 * wordSize));
9986 movq(r12, Address(rsp, 3 * wordSize));
9987 movq(r11, Address(rsp, 4 * wordSize));
9988 movq(r10, Address(rsp, 5 * wordSize));
9989 movq(r9, Address(rsp, 6 * wordSize));
9990 movq(r8, Address(rsp, 7 * wordSize));
9991 movq(rdi, Address(rsp, 8 * wordSize));
9992 movq(rsi, Address(rsp, 9 * wordSize));
9993 movq(rbp, Address(rsp, 10 * wordSize));
9994 movq(rbx, Address(rsp, 12 * wordSize));
9995 movq(rdx, Address(rsp, 13 * wordSize));
9996 movq(rcx, Address(rsp, 14 * wordSize));
9997 movq(rax, Address(rsp, 15 * wordSize));
9998 addq(rsp, 16 * wordSize);
9999 }
10000
10001 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10002 if (VM_Version::supports_apx_f()) {
10003 esetzucc(comparison, dst);
10004 } else {
10005 setb(comparison, dst);
10006 movzbl(dst, dst);
10007 }
10008 }