1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "code/SCCache.hpp"
29 #include "code/compiledIC.hpp"
30 #include "compiler/compiler_globals.hpp"
31 #include "compiler/disassembler.hpp"
32 #include "crc32c.h"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/collectedHeap.inline.hpp"
36 #include "gc/shared/tlab_globals.hpp"
37 #include "interpreter/bytecodeHistogram.hpp"
38 #include "interpreter/interpreter.hpp"
39 #include "jvm.h"
40 #include "memory/resourceArea.hpp"
41 #include "memory/universe.hpp"
42 #include "oops/accessDecorators.hpp"
43 #include "oops/compressedKlass.inline.hpp"
44 #include "oops/compressedOops.inline.hpp"
45 #include "oops/klass.inline.hpp"
46 #include "prims/methodHandles.hpp"
47 #include "runtime/continuation.hpp"
48 #include "runtime/interfaceSupport.inline.hpp"
49 #include "runtime/javaThread.hpp"
50 #include "runtime/jniHandles.hpp"
51 #include "runtime/objectMonitor.hpp"
52 #include "runtime/os.hpp"
53 #include "runtime/safepoint.hpp"
54 #include "runtime/safepointMechanism.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/checkedCast.hpp"
58 #include "utilities/macros.hpp"
59
60 #ifdef PRODUCT
61 #define BLOCK_COMMENT(str) /* nothing */
62 #define STOP(error) stop(error)
63 #else
64 #define BLOCK_COMMENT(str) block_comment(str)
65 #define STOP(error) block_comment(error); stop(error)
66 #endif
67
68 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
69
70 #ifdef ASSERT
71 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
72 #endif
73
74 static const Assembler::Condition reverse[] = {
75 Assembler::noOverflow /* overflow = 0x0 */ ,
76 Assembler::overflow /* noOverflow = 0x1 */ ,
77 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
78 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
79 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
80 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
81 Assembler::above /* belowEqual = 0x6 */ ,
82 Assembler::belowEqual /* above = 0x7 */ ,
83 Assembler::positive /* negative = 0x8 */ ,
84 Assembler::negative /* positive = 0x9 */ ,
85 Assembler::noParity /* parity = 0xa */ ,
86 Assembler::parity /* noParity = 0xb */ ,
87 Assembler::greaterEqual /* less = 0xc */ ,
88 Assembler::less /* greaterEqual = 0xd */ ,
89 Assembler::greater /* lessEqual = 0xe */ ,
90 Assembler::lessEqual /* greater = 0xf, */
91
92 };
93
94
95 // Implementation of MacroAssembler
96
97 // First all the versions that have distinct versions depending on 32/64 bit
98 // Unless the difference is trivial (1 line or so).
99
100 #ifndef _LP64
101
102 // 32bit versions
103
104 Address MacroAssembler::as_Address(AddressLiteral adr) {
105 return Address(adr.target(), adr.rspec());
106 }
107
108 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
109 assert(rscratch == noreg, "");
110 return Address::make_array(adr);
111 }
112
113 void MacroAssembler::call_VM_leaf_base(address entry_point,
114 int number_of_arguments) {
115 call(RuntimeAddress(entry_point));
116 increment(rsp, number_of_arguments * wordSize);
117 }
118
119 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
120 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
121 }
122
123
124 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
125 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
126 }
127
128 void MacroAssembler::cmpoop(Address src1, jobject obj) {
129 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
130 }
131
132 void MacroAssembler::cmpoop(Register src1, jobject obj, Register rscratch) {
133 assert(rscratch == noreg, "redundant");
134 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
135 }
136
137 void MacroAssembler::extend_sign(Register hi, Register lo) {
138 // According to Intel Doc. AP-526, "Integer Divide", p.18.
139 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
140 cdql();
141 } else {
142 movl(hi, lo);
143 sarl(hi, 31);
144 }
145 }
146
147 void MacroAssembler::jC2(Register tmp, Label& L) {
148 // set parity bit if FPU flag C2 is set (via rax)
149 save_rax(tmp);
150 fwait(); fnstsw_ax();
151 sahf();
152 restore_rax(tmp);
153 // branch
154 jcc(Assembler::parity, L);
155 }
156
157 void MacroAssembler::jnC2(Register tmp, Label& L) {
158 // set parity bit if FPU flag C2 is set (via rax)
159 save_rax(tmp);
160 fwait(); fnstsw_ax();
161 sahf();
162 restore_rax(tmp);
163 // branch
164 jcc(Assembler::noParity, L);
165 }
166
167 // 32bit can do a case table jump in one instruction but we no longer allow the base
168 // to be installed in the Address class
169 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
170 assert(rscratch == noreg, "not needed");
171 jmp(as_Address(entry, noreg));
172 }
173
174 // Note: y_lo will be destroyed
175 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
176 // Long compare for Java (semantics as described in JVM spec.)
177 Label high, low, done;
178
179 cmpl(x_hi, y_hi);
180 jcc(Assembler::less, low);
181 jcc(Assembler::greater, high);
182 // x_hi is the return register
183 xorl(x_hi, x_hi);
184 cmpl(x_lo, y_lo);
185 jcc(Assembler::below, low);
186 jcc(Assembler::equal, done);
187
188 bind(high);
189 xorl(x_hi, x_hi);
190 increment(x_hi);
191 jmp(done);
192
193 bind(low);
194 xorl(x_hi, x_hi);
195 decrementl(x_hi);
196
197 bind(done);
198 }
199
200 void MacroAssembler::lea(Register dst, AddressLiteral src) {
201 mov_literal32(dst, (int32_t)src.target(), src.rspec());
202 }
203
204 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
205 assert(rscratch == noreg, "not needed");
206
207 // leal(dst, as_Address(adr));
208 // see note in movl as to why we must use a move
209 mov_literal32(dst, (int32_t)adr.target(), adr.rspec());
210 }
211
212 void MacroAssembler::leave() {
213 mov(rsp, rbp);
214 pop(rbp);
215 }
216
217 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
218 // Multiplication of two Java long values stored on the stack
219 // as illustrated below. Result is in rdx:rax.
220 //
221 // rsp ---> [ ?? ] \ \
222 // .... | y_rsp_offset |
223 // [ y_lo ] / (in bytes) | x_rsp_offset
224 // [ y_hi ] | (in bytes)
225 // .... |
226 // [ x_lo ] /
227 // [ x_hi ]
228 // ....
229 //
230 // Basic idea: lo(result) = lo(x_lo * y_lo)
231 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
232 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
233 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
234 Label quick;
235 // load x_hi, y_hi and check if quick
236 // multiplication is possible
237 movl(rbx, x_hi);
238 movl(rcx, y_hi);
239 movl(rax, rbx);
240 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
241 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
242 // do full multiplication
243 // 1st step
244 mull(y_lo); // x_hi * y_lo
245 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
246 // 2nd step
247 movl(rax, x_lo);
248 mull(rcx); // x_lo * y_hi
249 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
250 // 3rd step
251 bind(quick); // note: rbx, = 0 if quick multiply!
252 movl(rax, x_lo);
253 mull(y_lo); // x_lo * y_lo
254 addl(rdx, rbx); // correct hi(x_lo * y_lo)
255 }
256
257 void MacroAssembler::lneg(Register hi, Register lo) {
258 negl(lo);
259 adcl(hi, 0);
260 negl(hi);
261 }
262
263 void MacroAssembler::lshl(Register hi, Register lo) {
264 // Java shift left long support (semantics as described in JVM spec., p.305)
265 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
266 // shift value is in rcx !
267 assert(hi != rcx, "must not use rcx");
268 assert(lo != rcx, "must not use rcx");
269 const Register s = rcx; // shift count
270 const int n = BitsPerWord;
271 Label L;
272 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
273 cmpl(s, n); // if (s < n)
274 jcc(Assembler::less, L); // else (s >= n)
275 movl(hi, lo); // x := x << n
276 xorl(lo, lo);
277 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
278 bind(L); // s (mod n) < n
279 shldl(hi, lo); // x := x << s
280 shll(lo);
281 }
282
283
284 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
285 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
286 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
287 assert(hi != rcx, "must not use rcx");
288 assert(lo != rcx, "must not use rcx");
289 const Register s = rcx; // shift count
290 const int n = BitsPerWord;
291 Label L;
292 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
293 cmpl(s, n); // if (s < n)
294 jcc(Assembler::less, L); // else (s >= n)
295 movl(lo, hi); // x := x >> n
296 if (sign_extension) sarl(hi, 31);
297 else xorl(hi, hi);
298 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
299 bind(L); // s (mod n) < n
300 shrdl(lo, hi); // x := x >> s
301 if (sign_extension) sarl(hi);
302 else shrl(hi);
303 }
304
305 void MacroAssembler::movoop(Register dst, jobject obj) {
306 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
307 }
308
309 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
310 assert(rscratch == noreg, "redundant");
311 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
312 }
313
314 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
315 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
316 }
317
318 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
319 assert(rscratch == noreg, "redundant");
320 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
321 }
322
323 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
324 if (src.is_lval()) {
325 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
326 } else {
327 movl(dst, as_Address(src));
328 }
329 }
330
331 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
332 assert(rscratch == noreg, "redundant");
333 movl(as_Address(dst, noreg), src);
334 }
335
336 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
337 movl(dst, as_Address(src, noreg));
338 }
339
340 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
341 assert(rscratch == noreg, "redundant");
342 movl(dst, src);
343 }
344
345 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
346 assert(rscratch == noreg, "redundant");
347 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
348 }
349
350 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
351 assert(rscratch == noreg, "redundant");
352 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
353 }
354
355 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
356 assert(rscratch == noreg, "redundant");
357 if (src.is_lval()) {
358 push_literal32((int32_t)src.target(), src.rspec());
359 } else {
360 pushl(as_Address(src));
361 }
362 }
363
364 static void pass_arg0(MacroAssembler* masm, Register arg) {
365 masm->push(arg);
366 }
367
368 static void pass_arg1(MacroAssembler* masm, Register arg) {
369 masm->push(arg);
370 }
371
372 static void pass_arg2(MacroAssembler* masm, Register arg) {
373 masm->push(arg);
374 }
375
376 static void pass_arg3(MacroAssembler* masm, Register arg) {
377 masm->push(arg);
378 }
379
380 #ifndef PRODUCT
381 extern "C" void findpc(intptr_t x);
382 #endif
383
384 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
385 // In order to get locks to work, we need to fake a in_VM state
386 JavaThread* thread = JavaThread::current();
387 JavaThreadState saved_state = thread->thread_state();
388 thread->set_thread_state(_thread_in_vm);
389 if (ShowMessageBoxOnError) {
390 JavaThread* thread = JavaThread::current();
391 JavaThreadState saved_state = thread->thread_state();
392 thread->set_thread_state(_thread_in_vm);
393 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
394 ttyLocker ttyl;
395 BytecodeCounter::print();
396 }
397 // To see where a verify_oop failed, get $ebx+40/X for this frame.
398 // This is the value of eip which points to where verify_oop will return.
399 if (os::message_box(msg, "Execution stopped, print registers?")) {
400 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
401 BREAKPOINT;
402 }
403 }
404 fatal("DEBUG MESSAGE: %s", msg);
405 }
406
407 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
408 ttyLocker ttyl;
409 DebuggingContext debugging{};
410 tty->print_cr("eip = 0x%08x", eip);
411 #ifndef PRODUCT
412 if ((WizardMode || Verbose) && PrintMiscellaneous) {
413 tty->cr();
414 findpc(eip);
415 tty->cr();
416 }
417 #endif
418 #define PRINT_REG(rax) \
419 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
420 PRINT_REG(rax);
421 PRINT_REG(rbx);
422 PRINT_REG(rcx);
423 PRINT_REG(rdx);
424 PRINT_REG(rdi);
425 PRINT_REG(rsi);
426 PRINT_REG(rbp);
427 PRINT_REG(rsp);
428 #undef PRINT_REG
429 // Print some words near top of staack.
430 int* dump_sp = (int*) rsp;
431 for (int col1 = 0; col1 < 8; col1++) {
432 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
433 os::print_location(tty, *dump_sp++);
434 }
435 for (int row = 0; row < 16; row++) {
436 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
437 for (int col = 0; col < 8; col++) {
438 tty->print(" 0x%08x", *dump_sp++);
439 }
440 tty->cr();
441 }
442 // Print some instructions around pc:
443 Disassembler::decode((address)eip-64, (address)eip);
444 tty->print_cr("--------");
445 Disassembler::decode((address)eip, (address)eip+32);
446 }
447
448 void MacroAssembler::stop(const char* msg) {
449 // push address of message
450 ExternalAddress message((address)msg);
451 pushptr(message.addr(), noreg);
452 { Label L; call(L, relocInfo::none); bind(L); } // push eip
453 pusha(); // push registers
454 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
455 hlt();
456 }
457
458 void MacroAssembler::warn(const char* msg) {
459 push_CPU_state();
460
461 // push address of message
462 ExternalAddress message((address)msg);
463 pushptr(message.addr(), noreg);
464
465 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
466 addl(rsp, wordSize); // discard argument
467 pop_CPU_state();
468 }
469
470 void MacroAssembler::print_state() {
471 { Label L; call(L, relocInfo::none); bind(L); } // push eip
472 pusha(); // push registers
473
474 push_CPU_state();
475 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
476 pop_CPU_state();
477
478 popa();
479 addl(rsp, wordSize);
480 }
481
482 #else // _LP64
483
484 // 64 bit versions
485
486 Address MacroAssembler::as_Address(AddressLiteral adr) {
487 // amd64 always does this as a pc-rel
488 // we can be absolute or disp based on the instruction type
489 // jmp/call are displacements others are absolute
490 assert(!adr.is_lval(), "must be rval");
491 assert(reachable(adr), "must be");
492 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
493
494 }
495
496 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
497 AddressLiteral base = adr.base();
498 lea(rscratch, base);
499 Address index = adr.index();
500 assert(index._disp == 0, "must not have disp"); // maybe it can?
501 Address array(rscratch, index._index, index._scale, index._disp);
502 return array;
503 }
504
505 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
506 Label L, E;
507
508 #ifdef _WIN64
509 // Windows always allocates space for it's register args
510 assert(num_args <= 4, "only register arguments supported");
511 subq(rsp, frame::arg_reg_save_area_bytes);
512 #endif
513
514 // Align stack if necessary
515 testl(rsp, 15);
516 jcc(Assembler::zero, L);
517
518 subq(rsp, 8);
519 call(RuntimeAddress(entry_point));
520 addq(rsp, 8);
521 jmp(E);
522
523 bind(L);
524 call(RuntimeAddress(entry_point));
525
526 bind(E);
527
528 #ifdef _WIN64
529 // restore stack pointer
530 addq(rsp, frame::arg_reg_save_area_bytes);
531 #endif
532
533 }
534
535 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
536 assert(!src2.is_lval(), "should use cmpptr");
537 assert(rscratch != noreg || always_reachable(src2), "missing");
538
539 if (reachable(src2)) {
540 cmpq(src1, as_Address(src2));
541 } else {
542 lea(rscratch, src2);
543 Assembler::cmpq(src1, Address(rscratch, 0));
544 }
545 }
546
547 int MacroAssembler::corrected_idivq(Register reg) {
548 // Full implementation of Java ldiv and lrem; checks for special
549 // case as described in JVM spec., p.243 & p.271. The function
550 // returns the (pc) offset of the idivl instruction - may be needed
551 // for implicit exceptions.
552 //
553 // normal case special case
554 //
555 // input : rax: dividend min_long
556 // reg: divisor (may not be eax/edx) -1
557 //
558 // output: rax: quotient (= rax idiv reg) min_long
559 // rdx: remainder (= rax irem reg) 0
560 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
561 static const int64_t min_long = 0x8000000000000000;
562 Label normal_case, special_case;
563
564 // check for special case
565 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
566 jcc(Assembler::notEqual, normal_case);
567 xorl(rdx, rdx); // prepare rdx for possible special case (where
568 // remainder = 0)
569 cmpq(reg, -1);
570 jcc(Assembler::equal, special_case);
571
572 // handle normal case
573 bind(normal_case);
574 cdqq();
575 int idivq_offset = offset();
576 idivq(reg);
577
578 // normal and special case exit
579 bind(special_case);
580
581 return idivq_offset;
582 }
583
584 void MacroAssembler::decrementq(Register reg, int value) {
585 if (value == min_jint) { subq(reg, value); return; }
586 if (value < 0) { incrementq(reg, -value); return; }
587 if (value == 0) { ; return; }
588 if (value == 1 && UseIncDec) { decq(reg) ; return; }
589 /* else */ { subq(reg, value) ; return; }
590 }
591
592 void MacroAssembler::decrementq(Address dst, int value) {
593 if (value == min_jint) { subq(dst, value); return; }
594 if (value < 0) { incrementq(dst, -value); return; }
595 if (value == 0) { ; return; }
596 if (value == 1 && UseIncDec) { decq(dst) ; return; }
597 /* else */ { subq(dst, value) ; return; }
598 }
599
600 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
601 assert(rscratch != noreg || always_reachable(dst), "missing");
602
603 if (reachable(dst)) {
604 incrementq(as_Address(dst));
605 } else {
606 lea(rscratch, dst);
607 incrementq(Address(rscratch, 0));
608 }
609 }
610
611 void MacroAssembler::incrementq(Register reg, int value) {
612 if (value == min_jint) { addq(reg, value); return; }
613 if (value < 0) { decrementq(reg, -value); return; }
614 if (value == 0) { ; return; }
615 if (value == 1 && UseIncDec) { incq(reg) ; return; }
616 /* else */ { addq(reg, value) ; return; }
617 }
618
619 void MacroAssembler::incrementq(Address dst, int value) {
620 if (value == min_jint) { addq(dst, value); return; }
621 if (value < 0) { decrementq(dst, -value); return; }
622 if (value == 0) { ; return; }
623 if (value == 1 && UseIncDec) { incq(dst) ; return; }
624 /* else */ { addq(dst, value) ; return; }
625 }
626
627 // 32bit can do a case table jump in one instruction but we no longer allow the base
628 // to be installed in the Address class
629 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
630 lea(rscratch, entry.base());
631 Address dispatch = entry.index();
632 assert(dispatch._base == noreg, "must be");
633 dispatch._base = rscratch;
634 jmp(dispatch);
635 }
636
637 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
638 ShouldNotReachHere(); // 64bit doesn't use two regs
639 cmpq(x_lo, y_lo);
640 }
641
642 void MacroAssembler::lea(Register dst, AddressLiteral src) {
643 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
644 }
645
646 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
647 lea(rscratch, adr);
648 movptr(dst, rscratch);
649 }
650
651 void MacroAssembler::leave() {
652 // %%% is this really better? Why not on 32bit too?
653 emit_int8((unsigned char)0xC9); // LEAVE
654 }
655
656 void MacroAssembler::lneg(Register hi, Register lo) {
657 ShouldNotReachHere(); // 64bit doesn't use two regs
658 negq(lo);
659 }
660
661 void MacroAssembler::movoop(Register dst, jobject obj) {
662 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
663 }
664
665 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
666 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
667 movq(dst, rscratch);
668 }
669
670 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
671 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
672 }
673
674 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
675 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
676 movq(dst, rscratch);
677 }
678
679 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
680 if (src.is_lval()) {
681 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
682 } else {
683 if (reachable(src)) {
684 movq(dst, as_Address(src));
685 } else {
686 lea(dst, src);
687 movq(dst, Address(dst, 0));
688 }
689 }
690 }
691
692 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
693 movq(as_Address(dst, rscratch), src);
694 }
695
696 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
697 movq(dst, as_Address(src, dst /*rscratch*/));
698 }
699
700 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
701 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
702 if (is_simm32(src)) {
703 movptr(dst, checked_cast<int32_t>(src));
704 } else {
705 mov64(rscratch, src);
706 movq(dst, rscratch);
707 }
708 }
709
710 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
711 movoop(rscratch, obj);
712 push(rscratch);
713 }
714
715 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
716 mov_metadata(rscratch, obj);
717 push(rscratch);
718 }
719
720 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
721 lea(rscratch, src);
722 if (src.is_lval()) {
723 push(rscratch);
724 } else {
725 pushq(Address(rscratch, 0));
726 }
727 }
728
729 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
730 reset_last_Java_frame(r15_thread, clear_fp);
731 }
732
733 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
734 Register last_java_fp,
735 address last_java_pc,
736 Register rscratch) {
737 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, last_java_pc, rscratch);
738 }
739
740 static void pass_arg0(MacroAssembler* masm, Register arg) {
741 if (c_rarg0 != arg ) {
742 masm->mov(c_rarg0, arg);
743 }
744 }
745
746 static void pass_arg1(MacroAssembler* masm, Register arg) {
747 if (c_rarg1 != arg ) {
748 masm->mov(c_rarg1, arg);
749 }
750 }
751
752 static void pass_arg2(MacroAssembler* masm, Register arg) {
753 if (c_rarg2 != arg ) {
754 masm->mov(c_rarg2, arg);
755 }
756 }
757
758 static void pass_arg3(MacroAssembler* masm, Register arg) {
759 if (c_rarg3 != arg ) {
760 masm->mov(c_rarg3, arg);
761 }
762 }
763
764 void MacroAssembler::stop(const char* msg) {
765 if (ShowMessageBoxOnError) {
766 address rip = pc();
767 pusha(); // get regs on stack
768 lea(c_rarg1, InternalAddress(rip));
769 movq(c_rarg2, rsp); // pass pointer to regs array
770 }
771 lea(c_rarg0, ExternalAddress((address) msg));
772 andq(rsp, -16); // align stack as required by ABI
773 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
774 hlt();
775 SCCache::add_C_string(msg);
776 }
777
778 void MacroAssembler::warn(const char* msg) {
779 push(rbp);
780 movq(rbp, rsp);
781 andq(rsp, -16); // align stack as required by push_CPU_state and call
782 push_CPU_state(); // keeps alignment at 16 bytes
783
784 lea(c_rarg0, ExternalAddress((address) msg));
785 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
786
787 pop_CPU_state();
788 mov(rsp, rbp);
789 pop(rbp);
790 }
791
792 void MacroAssembler::print_state() {
793 address rip = pc();
794 pusha(); // get regs on stack
795 push(rbp);
796 movq(rbp, rsp);
797 andq(rsp, -16); // align stack as required by push_CPU_state and call
798 push_CPU_state(); // keeps alignment at 16 bytes
799
800 lea(c_rarg0, InternalAddress(rip));
801 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
802 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
803
804 pop_CPU_state();
805 mov(rsp, rbp);
806 pop(rbp);
807 popa();
808 }
809
810 #ifndef PRODUCT
811 extern "C" void findpc(intptr_t x);
812 #endif
813
814 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
815 // In order to get locks to work, we need to fake a in_VM state
816 if (ShowMessageBoxOnError) {
817 JavaThread* thread = JavaThread::current();
818 JavaThreadState saved_state = thread->thread_state();
819 thread->set_thread_state(_thread_in_vm);
820 #ifndef PRODUCT
821 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
822 ttyLocker ttyl;
823 BytecodeCounter::print();
824 }
825 #endif
826 // To see where a verify_oop failed, get $ebx+40/X for this frame.
827 // XXX correct this offset for amd64
828 // This is the value of eip which points to where verify_oop will return.
829 if (os::message_box(msg, "Execution stopped, print registers?")) {
830 print_state64(pc, regs);
831 BREAKPOINT;
832 }
833 }
834 fatal("DEBUG MESSAGE: %s", msg);
835 }
836
837 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
838 ttyLocker ttyl;
839 DebuggingContext debugging{};
840 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
841 #ifndef PRODUCT
842 tty->cr();
843 findpc(pc);
844 tty->cr();
845 #endif
846 #define PRINT_REG(rax, value) \
847 { tty->print("%s = ", #rax); os::print_location(tty, value); }
848 PRINT_REG(rax, regs[15]);
849 PRINT_REG(rbx, regs[12]);
850 PRINT_REG(rcx, regs[14]);
851 PRINT_REG(rdx, regs[13]);
852 PRINT_REG(rdi, regs[8]);
853 PRINT_REG(rsi, regs[9]);
854 PRINT_REG(rbp, regs[10]);
855 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
856 PRINT_REG(rsp, (intptr_t)(®s[16]));
857 PRINT_REG(r8 , regs[7]);
858 PRINT_REG(r9 , regs[6]);
859 PRINT_REG(r10, regs[5]);
860 PRINT_REG(r11, regs[4]);
861 PRINT_REG(r12, regs[3]);
862 PRINT_REG(r13, regs[2]);
863 PRINT_REG(r14, regs[1]);
864 PRINT_REG(r15, regs[0]);
865 #undef PRINT_REG
866 // Print some words near the top of the stack.
867 int64_t* rsp = ®s[16];
868 int64_t* dump_sp = rsp;
869 for (int col1 = 0; col1 < 8; col1++) {
870 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
871 os::print_location(tty, *dump_sp++);
872 }
873 for (int row = 0; row < 25; row++) {
874 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
875 for (int col = 0; col < 4; col++) {
876 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
877 }
878 tty->cr();
879 }
880 // Print some instructions around pc:
881 Disassembler::decode((address)pc-64, (address)pc);
882 tty->print_cr("--------");
883 Disassembler::decode((address)pc, (address)pc+32);
884 }
885
886 // The java_calling_convention describes stack locations as ideal slots on
887 // a frame with no abi restrictions. Since we must observe abi restrictions
888 // (like the placement of the register window) the slots must be biased by
889 // the following value.
890 static int reg2offset_in(VMReg r) {
891 // Account for saved rbp and return address
892 // This should really be in_preserve_stack_slots
893 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
894 }
895
896 static int reg2offset_out(VMReg r) {
897 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
898 }
899
900 // A long move
901 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
902
903 // The calling conventions assures us that each VMregpair is either
904 // all really one physical register or adjacent stack slots.
905
906 if (src.is_single_phys_reg() ) {
907 if (dst.is_single_phys_reg()) {
908 if (dst.first() != src.first()) {
909 mov(dst.first()->as_Register(), src.first()->as_Register());
910 }
911 } else {
912 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
913 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
914 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
915 }
916 } else if (dst.is_single_phys_reg()) {
917 assert(src.is_single_reg(), "not a stack pair");
918 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
919 } else {
920 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
921 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
922 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
923 }
924 }
925
926 // A double move
927 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
928
929 // The calling conventions assures us that each VMregpair is either
930 // all really one physical register or adjacent stack slots.
931
932 if (src.is_single_phys_reg() ) {
933 if (dst.is_single_phys_reg()) {
934 // In theory these overlap but the ordering is such that this is likely a nop
935 if ( src.first() != dst.first()) {
936 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
937 }
938 } else {
939 assert(dst.is_single_reg(), "not a stack pair");
940 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
941 }
942 } else if (dst.is_single_phys_reg()) {
943 assert(src.is_single_reg(), "not a stack pair");
944 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
945 } else {
946 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
947 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
948 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
949 }
950 }
951
952
953 // A float arg may have to do float reg int reg conversion
954 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
955 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
956
957 // The calling conventions assures us that each VMregpair is either
958 // all really one physical register or adjacent stack slots.
959
960 if (src.first()->is_stack()) {
961 if (dst.first()->is_stack()) {
962 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
963 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
964 } else {
965 // stack to reg
966 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
967 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
968 }
969 } else if (dst.first()->is_stack()) {
970 // reg to stack
971 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
972 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
973 } else {
974 // reg to reg
975 // In theory these overlap but the ordering is such that this is likely a nop
976 if ( src.first() != dst.first()) {
977 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
978 }
979 }
980 }
981
982 // On 64 bit we will store integer like items to the stack as
983 // 64 bits items (x86_32/64 abi) even though java would only store
984 // 32bits for a parameter. On 32bit it will simply be 32 bits
985 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
986 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
987 if (src.first()->is_stack()) {
988 if (dst.first()->is_stack()) {
989 // stack to stack
990 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
991 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
992 } else {
993 // stack to reg
994 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
995 }
996 } else if (dst.first()->is_stack()) {
997 // reg to stack
998 // Do we really have to sign extend???
999 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1000 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
1001 } else {
1002 // Do we really have to sign extend???
1003 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1004 if (dst.first() != src.first()) {
1005 movq(dst.first()->as_Register(), src.first()->as_Register());
1006 }
1007 }
1008 }
1009
1010 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1011 if (src.first()->is_stack()) {
1012 if (dst.first()->is_stack()) {
1013 // stack to stack
1014 movq(rax, Address(rbp, reg2offset_in(src.first())));
1015 movq(Address(rsp, reg2offset_out(dst.first())), rax);
1016 } else {
1017 // stack to reg
1018 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1019 }
1020 } else if (dst.first()->is_stack()) {
1021 // reg to stack
1022 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1023 } else {
1024 if (dst.first() != src.first()) {
1025 movq(dst.first()->as_Register(), src.first()->as_Register());
1026 }
1027 }
1028 }
1029
1030 // An oop arg. Must pass a handle not the oop itself
1031 void MacroAssembler::object_move(OopMap* map,
1032 int oop_handle_offset,
1033 int framesize_in_slots,
1034 VMRegPair src,
1035 VMRegPair dst,
1036 bool is_receiver,
1037 int* receiver_offset) {
1038
1039 // must pass a handle. First figure out the location we use as a handle
1040
1041 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1042
1043 // See if oop is null if it is we need no handle
1044
1045 if (src.first()->is_stack()) {
1046
1047 // Oop is already on the stack as an argument
1048 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1049 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1050 if (is_receiver) {
1051 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1052 }
1053
1054 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
1055 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1056 // conditionally move a null
1057 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1058 } else {
1059
1060 // Oop is in a register we must store it to the space we reserve
1061 // on the stack for oop_handles and pass a handle if oop is non-null
1062
1063 const Register rOop = src.first()->as_Register();
1064 int oop_slot;
1065 if (rOop == j_rarg0)
1066 oop_slot = 0;
1067 else if (rOop == j_rarg1)
1068 oop_slot = 1;
1069 else if (rOop == j_rarg2)
1070 oop_slot = 2;
1071 else if (rOop == j_rarg3)
1072 oop_slot = 3;
1073 else if (rOop == j_rarg4)
1074 oop_slot = 4;
1075 else {
1076 assert(rOop == j_rarg5, "wrong register");
1077 oop_slot = 5;
1078 }
1079
1080 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1081 int offset = oop_slot*VMRegImpl::stack_slot_size;
1082
1083 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1084 // Store oop in handle area, may be null
1085 movptr(Address(rsp, offset), rOop);
1086 if (is_receiver) {
1087 *receiver_offset = offset;
1088 }
1089
1090 cmpptr(rOop, NULL_WORD);
1091 lea(rHandle, Address(rsp, offset));
1092 // conditionally move a null from the handle area where it was just stored
1093 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1094 }
1095
1096 // If arg is on the stack then place it otherwise it is already in correct reg.
1097 if (dst.first()->is_stack()) {
1098 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1099 }
1100 }
1101
1102 #endif // _LP64
1103
1104 // Now versions that are common to 32/64 bit
1105
1106 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1107 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1108 }
1109
1110 void MacroAssembler::addptr(Register dst, Register src) {
1111 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1112 }
1113
1114 void MacroAssembler::addptr(Address dst, Register src) {
1115 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1116 }
1117
1118 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1119 assert(rscratch != noreg || always_reachable(src), "missing");
1120
1121 if (reachable(src)) {
1122 Assembler::addsd(dst, as_Address(src));
1123 } else {
1124 lea(rscratch, src);
1125 Assembler::addsd(dst, Address(rscratch, 0));
1126 }
1127 }
1128
1129 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1130 assert(rscratch != noreg || always_reachable(src), "missing");
1131
1132 if (reachable(src)) {
1133 addss(dst, as_Address(src));
1134 } else {
1135 lea(rscratch, src);
1136 addss(dst, Address(rscratch, 0));
1137 }
1138 }
1139
1140 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1141 assert(rscratch != noreg || always_reachable(src), "missing");
1142
1143 if (reachable(src)) {
1144 Assembler::addpd(dst, as_Address(src));
1145 } else {
1146 lea(rscratch, src);
1147 Assembler::addpd(dst, Address(rscratch, 0));
1148 }
1149 }
1150
1151 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
1152 // Stub code is generated once and never copied.
1153 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1154 void MacroAssembler::align64() {
1155 align(64, (uint)(uintptr_t)pc());
1156 }
1157
1158 void MacroAssembler::align32() {
1159 align(32, (uint)(uintptr_t)pc());
1160 }
1161
1162 void MacroAssembler::align(uint modulus) {
1163 // 8273459: Ensure alignment is possible with current segment alignment
1164 assert(modulus <= (uintx)CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1165 align(modulus, offset());
1166 }
1167
1168 void MacroAssembler::align(uint modulus, uint target) {
1169 if (target % modulus != 0) {
1170 nop(modulus - (target % modulus));
1171 }
1172 }
1173
1174 void MacroAssembler::push_f(XMMRegister r) {
1175 subptr(rsp, wordSize);
1176 movflt(Address(rsp, 0), r);
1177 }
1178
1179 void MacroAssembler::pop_f(XMMRegister r) {
1180 movflt(r, Address(rsp, 0));
1181 addptr(rsp, wordSize);
1182 }
1183
1184 void MacroAssembler::push_d(XMMRegister r) {
1185 subptr(rsp, 2 * wordSize);
1186 movdbl(Address(rsp, 0), r);
1187 }
1188
1189 void MacroAssembler::pop_d(XMMRegister r) {
1190 movdbl(r, Address(rsp, 0));
1191 addptr(rsp, 2 * Interpreter::stackElementSize);
1192 }
1193
1194 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1195 // Used in sign-masking with aligned address.
1196 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1197 assert(rscratch != noreg || always_reachable(src), "missing");
1198
1199 if (reachable(src)) {
1200 Assembler::andpd(dst, as_Address(src));
1201 } else {
1202 lea(rscratch, src);
1203 Assembler::andpd(dst, Address(rscratch, 0));
1204 }
1205 }
1206
1207 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
1208 // Used in sign-masking with aligned address.
1209 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1210 assert(rscratch != noreg || always_reachable(src), "missing");
1211
1212 if (reachable(src)) {
1213 Assembler::andps(dst, as_Address(src));
1214 } else {
1215 lea(rscratch, src);
1216 Assembler::andps(dst, Address(rscratch, 0));
1217 }
1218 }
1219
1220 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1221 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1222 }
1223
1224 #ifdef _LP64
1225 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
1226 assert(rscratch != noreg || always_reachable(src), "missing");
1227
1228 if (reachable(src)) {
1229 andq(dst, as_Address(src));
1230 } else {
1231 lea(rscratch, src);
1232 andq(dst, Address(rscratch, 0));
1233 }
1234 }
1235 #endif
1236
1237 void MacroAssembler::atomic_incl(Address counter_addr) {
1238 lock();
1239 incrementl(counter_addr);
1240 }
1241
1242 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
1243 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1244
1245 if (reachable(counter_addr)) {
1246 atomic_incl(as_Address(counter_addr));
1247 } else {
1248 lea(rscratch, counter_addr);
1249 atomic_incl(Address(rscratch, 0));
1250 }
1251 }
1252
1253 #ifdef _LP64
1254 void MacroAssembler::atomic_incq(Address counter_addr) {
1255 lock();
1256 incrementq(counter_addr);
1257 }
1258
1259 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
1260 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1261
1262 if (reachable(counter_addr)) {
1263 atomic_incq(as_Address(counter_addr));
1264 } else {
1265 lea(rscratch, counter_addr);
1266 atomic_incq(Address(rscratch, 0));
1267 }
1268 }
1269 #endif
1270
1271 // Writes to stack successive pages until offset reached to check for
1272 // stack overflow + shadow pages. This clobbers tmp.
1273 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1274 movptr(tmp, rsp);
1275 // Bang stack for total size given plus shadow page size.
1276 // Bang one page at a time because large size can bang beyond yellow and
1277 // red zones.
1278 Label loop;
1279 bind(loop);
1280 movl(Address(tmp, (-(int)os::vm_page_size())), size );
1281 subptr(tmp, (int)os::vm_page_size());
1282 subl(size, (int)os::vm_page_size());
1283 jcc(Assembler::greater, loop);
1284
1285 // Bang down shadow pages too.
1286 // At this point, (tmp-0) is the last address touched, so don't
1287 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1288 // was post-decremented.) Skip this address by starting at i=1, and
1289 // touch a few more pages below. N.B. It is important to touch all
1290 // the way down including all pages in the shadow zone.
1291 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
1292 // this could be any sized move but this is can be a debugging crumb
1293 // so the bigger the better.
1294 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
1295 }
1296 }
1297
1298 void MacroAssembler::reserved_stack_check() {
1299 // testing if reserved zone needs to be enabled
1300 Label no_reserved_zone_enabling;
1301 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1302 NOT_LP64(get_thread(rsi);)
1303
1304 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1305 jcc(Assembler::below, no_reserved_zone_enabling);
1306
1307 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1308 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1309 should_not_reach_here();
1310
1311 bind(no_reserved_zone_enabling);
1312 }
1313
1314 void MacroAssembler::c2bool(Register x) {
1315 // implements x == 0 ? 0 : 1
1316 // note: must only look at least-significant byte of x
1317 // since C-style booleans are stored in one byte
1318 // only! (was bug)
1319 andl(x, 0xFF);
1320 setb(Assembler::notZero, x);
1321 }
1322
1323 // Wouldn't need if AddressLiteral version had new name
1324 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1325 Assembler::call(L, rtype);
1326 }
1327
1328 void MacroAssembler::call(Register entry) {
1329 Assembler::call(entry);
1330 }
1331
1332 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
1333 assert(rscratch != noreg || always_reachable(entry), "missing");
1334
1335 if (reachable(entry)) {
1336 Assembler::call_literal(entry.target(), entry.rspec());
1337 } else {
1338 lea(rscratch, entry);
1339 Assembler::call(rscratch);
1340 }
1341 }
1342
1343 void MacroAssembler::ic_call(address entry, jint method_index) {
1344 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1345 #ifdef _LP64
1346 // Needs full 64-bit immediate for later patching.
1347 mov64(rax, (int64_t)Universe::non_oop_word());
1348 #else
1349 movptr(rax, (intptr_t)Universe::non_oop_word());
1350 #endif
1351 call(AddressLiteral(entry, rh));
1352 }
1353
1354 int MacroAssembler::ic_check_size() {
1355 return LP64_ONLY(14) NOT_LP64(12);
1356 }
1357
1358 int MacroAssembler::ic_check(int end_alignment) {
1359 Register receiver = LP64_ONLY(j_rarg0) NOT_LP64(rcx);
1360 Register data = rax;
1361 Register temp = LP64_ONLY(rscratch1) NOT_LP64(rbx);
1362
1363 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1364 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1365 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1366 // before the inline cache check here, and not after
1367 align(end_alignment, offset() + ic_check_size());
1368
1369 int uep_offset = offset();
1370
1371 if (UseCompressedClassPointers) {
1372 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1373 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1374 } else {
1375 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1376 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
1377 }
1378
1379 // if inline cache check fails, then jump to runtime routine
1380 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1381 assert((offset() % end_alignment) == 0, "Misaligned verified entry point");
1382
1383 return uep_offset;
1384 }
1385
1386 void MacroAssembler::emit_static_call_stub() {
1387 // Static stub relocation also tags the Method* in the code-stream.
1388 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1389 // This is recognized as unresolved by relocs/nativeinst/ic code.
1390 jump(RuntimeAddress(pc()));
1391 }
1392
1393 // Implementation of call_VM versions
1394
1395 void MacroAssembler::call_VM(Register oop_result,
1396 address entry_point,
1397 bool check_exceptions) {
1398 Label C, E;
1399 call(C, relocInfo::none);
1400 jmp(E);
1401
1402 bind(C);
1403 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1404 ret(0);
1405
1406 bind(E);
1407 }
1408
1409 void MacroAssembler::call_VM(Register oop_result,
1410 address entry_point,
1411 Register arg_1,
1412 bool check_exceptions) {
1413 Label C, E;
1414 call(C, relocInfo::none);
1415 jmp(E);
1416
1417 bind(C);
1418 pass_arg1(this, arg_1);
1419 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1420 ret(0);
1421
1422 bind(E);
1423 }
1424
1425 void MacroAssembler::call_VM(Register oop_result,
1426 address entry_point,
1427 Register arg_1,
1428 Register arg_2,
1429 bool check_exceptions) {
1430 Label C, E;
1431 call(C, relocInfo::none);
1432 jmp(E);
1433
1434 bind(C);
1435
1436 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1437
1438 pass_arg2(this, arg_2);
1439 pass_arg1(this, arg_1);
1440 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1441 ret(0);
1442
1443 bind(E);
1444 }
1445
1446 void MacroAssembler::call_VM(Register oop_result,
1447 address entry_point,
1448 Register arg_1,
1449 Register arg_2,
1450 Register arg_3,
1451 bool check_exceptions) {
1452 Label C, E;
1453 call(C, relocInfo::none);
1454 jmp(E);
1455
1456 bind(C);
1457
1458 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1459 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1460 pass_arg3(this, arg_3);
1461 pass_arg2(this, arg_2);
1462 pass_arg1(this, arg_1);
1463 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1464 ret(0);
1465
1466 bind(E);
1467 }
1468
1469 void MacroAssembler::call_VM(Register oop_result,
1470 Register last_java_sp,
1471 address entry_point,
1472 int number_of_arguments,
1473 bool check_exceptions) {
1474 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1475 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1476 }
1477
1478 void MacroAssembler::call_VM(Register oop_result,
1479 Register last_java_sp,
1480 address entry_point,
1481 Register arg_1,
1482 bool check_exceptions) {
1483 pass_arg1(this, arg_1);
1484 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1485 }
1486
1487 void MacroAssembler::call_VM(Register oop_result,
1488 Register last_java_sp,
1489 address entry_point,
1490 Register arg_1,
1491 Register arg_2,
1492 bool check_exceptions) {
1493
1494 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1495 pass_arg2(this, arg_2);
1496 pass_arg1(this, arg_1);
1497 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1498 }
1499
1500 void MacroAssembler::call_VM(Register oop_result,
1501 Register last_java_sp,
1502 address entry_point,
1503 Register arg_1,
1504 Register arg_2,
1505 Register arg_3,
1506 bool check_exceptions) {
1507 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1508 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1509 pass_arg3(this, arg_3);
1510 pass_arg2(this, arg_2);
1511 pass_arg1(this, arg_1);
1512 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1513 }
1514
1515 void MacroAssembler::super_call_VM(Register oop_result,
1516 Register last_java_sp,
1517 address entry_point,
1518 int number_of_arguments,
1519 bool check_exceptions) {
1520 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1521 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1522 }
1523
1524 void MacroAssembler::super_call_VM(Register oop_result,
1525 Register last_java_sp,
1526 address entry_point,
1527 Register arg_1,
1528 bool check_exceptions) {
1529 pass_arg1(this, arg_1);
1530 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1531 }
1532
1533 void MacroAssembler::super_call_VM(Register oop_result,
1534 Register last_java_sp,
1535 address entry_point,
1536 Register arg_1,
1537 Register arg_2,
1538 bool check_exceptions) {
1539
1540 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1541 pass_arg2(this, arg_2);
1542 pass_arg1(this, arg_1);
1543 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1544 }
1545
1546 void MacroAssembler::super_call_VM(Register oop_result,
1547 Register last_java_sp,
1548 address entry_point,
1549 Register arg_1,
1550 Register arg_2,
1551 Register arg_3,
1552 bool check_exceptions) {
1553 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1554 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1555 pass_arg3(this, arg_3);
1556 pass_arg2(this, arg_2);
1557 pass_arg1(this, arg_1);
1558 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1559 }
1560
1561 void MacroAssembler::call_VM_base(Register oop_result,
1562 Register java_thread,
1563 Register last_java_sp,
1564 address entry_point,
1565 int number_of_arguments,
1566 bool check_exceptions) {
1567 // determine java_thread register
1568 if (!java_thread->is_valid()) {
1569 #ifdef _LP64
1570 java_thread = r15_thread;
1571 #else
1572 java_thread = rdi;
1573 get_thread(java_thread);
1574 #endif // LP64
1575 }
1576 // determine last_java_sp register
1577 if (!last_java_sp->is_valid()) {
1578 last_java_sp = rsp;
1579 }
1580 // debugging support
1581 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1582 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1583 #ifdef ASSERT
1584 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1585 // r12 is the heapbase.
1586 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1587 #endif // ASSERT
1588
1589 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1590 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1591
1592 // push java thread (becomes first argument of C function)
1593
1594 NOT_LP64(push(java_thread); number_of_arguments++);
1595 LP64_ONLY(mov(c_rarg0, r15_thread));
1596
1597 // set last Java frame before call
1598 assert(last_java_sp != rbp, "can't use ebp/rbp");
1599
1600 // Only interpreter should have to set fp
1601 set_last_Java_frame(java_thread, last_java_sp, rbp, nullptr, rscratch1);
1602
1603 // do the call, remove parameters
1604 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1605
1606 // restore the thread (cannot use the pushed argument since arguments
1607 // may be overwritten by C code generated by an optimizing compiler);
1608 // however can use the register value directly if it is callee saved.
1609 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1610 // rdi & rsi (also r15) are callee saved -> nothing to do
1611 #ifdef ASSERT
1612 guarantee(java_thread != rax, "change this code");
1613 push(rax);
1614 { Label L;
1615 get_thread(rax);
1616 cmpptr(java_thread, rax);
1617 jcc(Assembler::equal, L);
1618 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1619 bind(L);
1620 }
1621 pop(rax);
1622 #endif
1623 } else {
1624 get_thread(java_thread);
1625 }
1626 // reset last Java frame
1627 // Only interpreter should have to clear fp
1628 reset_last_Java_frame(java_thread, true);
1629
1630 // C++ interp handles this in the interpreter
1631 check_and_handle_popframe(java_thread);
1632 check_and_handle_earlyret(java_thread);
1633
1634 if (check_exceptions) {
1635 // check for pending exceptions (java_thread is set upon return)
1636 cmpptr(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
1637 #ifndef _LP64
1638 jump_cc(Assembler::notEqual,
1639 RuntimeAddress(StubRoutines::forward_exception_entry()));
1640 #else
1641 // This used to conditionally jump to forward_exception however it is
1642 // possible if we relocate that the branch will not reach. So we must jump
1643 // around so we can always reach
1644
1645 Label ok;
1646 jcc(Assembler::equal, ok);
1647 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1648 bind(ok);
1649 #endif // LP64
1650 }
1651
1652 // get oop result if there is one and reset the value in the thread
1653 if (oop_result->is_valid()) {
1654 get_vm_result(oop_result, java_thread);
1655 }
1656 }
1657
1658 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1659
1660 // Calculate the value for last_Java_sp
1661 // somewhat subtle. call_VM does an intermediate call
1662 // which places a return address on the stack just under the
1663 // stack pointer as the user finished with it. This allows
1664 // use to retrieve last_Java_pc from last_Java_sp[-1].
1665 // On 32bit we then have to push additional args on the stack to accomplish
1666 // the actual requested call. On 64bit call_VM only can use register args
1667 // so the only extra space is the return address that call_VM created.
1668 // This hopefully explains the calculations here.
1669
1670 #ifdef _LP64
1671 // We've pushed one address, correct last_Java_sp
1672 lea(rax, Address(rsp, wordSize));
1673 #else
1674 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1675 #endif // LP64
1676
1677 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1678
1679 }
1680
1681 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1682 void MacroAssembler::call_VM_leaf0(address entry_point) {
1683 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1684 }
1685
1686 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1687 call_VM_leaf_base(entry_point, number_of_arguments);
1688 }
1689
1690 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1691 pass_arg0(this, arg_0);
1692 call_VM_leaf(entry_point, 1);
1693 }
1694
1695 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1696
1697 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1698 pass_arg1(this, arg_1);
1699 pass_arg0(this, arg_0);
1700 call_VM_leaf(entry_point, 2);
1701 }
1702
1703 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1704 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1705 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1706 pass_arg2(this, arg_2);
1707 pass_arg1(this, arg_1);
1708 pass_arg0(this, arg_0);
1709 call_VM_leaf(entry_point, 3);
1710 }
1711
1712 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1713 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1714 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1715 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1716 pass_arg3(this, arg_3);
1717 pass_arg2(this, arg_2);
1718 pass_arg1(this, arg_1);
1719 pass_arg0(this, arg_0);
1720 call_VM_leaf(entry_point, 3);
1721 }
1722
1723 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1724 pass_arg0(this, arg_0);
1725 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1726 }
1727
1728 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1729 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1730 pass_arg1(this, arg_1);
1731 pass_arg0(this, arg_0);
1732 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1733 }
1734
1735 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1736 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1737 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1738 pass_arg2(this, arg_2);
1739 pass_arg1(this, arg_1);
1740 pass_arg0(this, arg_0);
1741 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1742 }
1743
1744 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1745 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1746 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1747 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1748 pass_arg3(this, arg_3);
1749 pass_arg2(this, arg_2);
1750 pass_arg1(this, arg_1);
1751 pass_arg0(this, arg_0);
1752 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1753 }
1754
1755 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1756 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1757 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1758 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1759 }
1760
1761 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1762 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1763 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1764 }
1765
1766 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1767 }
1768
1769 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1770 }
1771
1772 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1773 assert(rscratch != noreg || always_reachable(src1), "missing");
1774
1775 if (reachable(src1)) {
1776 cmpl(as_Address(src1), imm);
1777 } else {
1778 lea(rscratch, src1);
1779 cmpl(Address(rscratch, 0), imm);
1780 }
1781 }
1782
1783 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1784 assert(!src2.is_lval(), "use cmpptr");
1785 assert(rscratch != noreg || always_reachable(src2), "missing");
1786
1787 if (reachable(src2)) {
1788 cmpl(src1, as_Address(src2));
1789 } else {
1790 lea(rscratch, src2);
1791 cmpl(src1, Address(rscratch, 0));
1792 }
1793 }
1794
1795 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1796 Assembler::cmpl(src1, imm);
1797 }
1798
1799 void MacroAssembler::cmp32(Register src1, Address src2) {
1800 Assembler::cmpl(src1, src2);
1801 }
1802
1803 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1804 ucomisd(opr1, opr2);
1805
1806 Label L;
1807 if (unordered_is_less) {
1808 movl(dst, -1);
1809 jcc(Assembler::parity, L);
1810 jcc(Assembler::below , L);
1811 movl(dst, 0);
1812 jcc(Assembler::equal , L);
1813 increment(dst);
1814 } else { // unordered is greater
1815 movl(dst, 1);
1816 jcc(Assembler::parity, L);
1817 jcc(Assembler::above , L);
1818 movl(dst, 0);
1819 jcc(Assembler::equal , L);
1820 decrementl(dst);
1821 }
1822 bind(L);
1823 }
1824
1825 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1826 ucomiss(opr1, opr2);
1827
1828 Label L;
1829 if (unordered_is_less) {
1830 movl(dst, -1);
1831 jcc(Assembler::parity, L);
1832 jcc(Assembler::below , L);
1833 movl(dst, 0);
1834 jcc(Assembler::equal , L);
1835 increment(dst);
1836 } else { // unordered is greater
1837 movl(dst, 1);
1838 jcc(Assembler::parity, L);
1839 jcc(Assembler::above , L);
1840 movl(dst, 0);
1841 jcc(Assembler::equal , L);
1842 decrementl(dst);
1843 }
1844 bind(L);
1845 }
1846
1847
1848 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1849 assert(rscratch != noreg || always_reachable(src1), "missing");
1850
1851 if (reachable(src1)) {
1852 cmpb(as_Address(src1), imm);
1853 } else {
1854 lea(rscratch, src1);
1855 cmpb(Address(rscratch, 0), imm);
1856 }
1857 }
1858
1859 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1860 #ifdef _LP64
1861 assert(rscratch != noreg || always_reachable(src2), "missing");
1862
1863 if (src2.is_lval()) {
1864 movptr(rscratch, src2);
1865 Assembler::cmpq(src1, rscratch);
1866 } else if (reachable(src2)) {
1867 cmpq(src1, as_Address(src2));
1868 } else {
1869 lea(rscratch, src2);
1870 Assembler::cmpq(src1, Address(rscratch, 0));
1871 }
1872 #else
1873 assert(rscratch == noreg, "not needed");
1874 if (src2.is_lval()) {
1875 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1876 } else {
1877 cmpl(src1, as_Address(src2));
1878 }
1879 #endif // _LP64
1880 }
1881
1882 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1883 assert(src2.is_lval(), "not a mem-mem compare");
1884 #ifdef _LP64
1885 // moves src2's literal address
1886 movptr(rscratch, src2);
1887 Assembler::cmpq(src1, rscratch);
1888 #else
1889 assert(rscratch == noreg, "not needed");
1890 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1891 #endif // _LP64
1892 }
1893
1894 void MacroAssembler::cmpoop(Register src1, Register src2) {
1895 cmpptr(src1, src2);
1896 }
1897
1898 void MacroAssembler::cmpoop(Register src1, Address src2) {
1899 cmpptr(src1, src2);
1900 }
1901
1902 #ifdef _LP64
1903 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1904 movoop(rscratch, src2);
1905 cmpptr(src1, rscratch);
1906 }
1907 #endif
1908
1909 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1910 assert(rscratch != noreg || always_reachable(adr), "missing");
1911
1912 if (reachable(adr)) {
1913 lock();
1914 cmpxchgptr(reg, as_Address(adr));
1915 } else {
1916 lea(rscratch, adr);
1917 lock();
1918 cmpxchgptr(reg, Address(rscratch, 0));
1919 }
1920 }
1921
1922 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1923 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1924 }
1925
1926 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1927 assert(rscratch != noreg || always_reachable(src), "missing");
1928
1929 if (reachable(src)) {
1930 Assembler::comisd(dst, as_Address(src));
1931 } else {
1932 lea(rscratch, src);
1933 Assembler::comisd(dst, Address(rscratch, 0));
1934 }
1935 }
1936
1937 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1938 assert(rscratch != noreg || always_reachable(src), "missing");
1939
1940 if (reachable(src)) {
1941 Assembler::comiss(dst, as_Address(src));
1942 } else {
1943 lea(rscratch, src);
1944 Assembler::comiss(dst, Address(rscratch, 0));
1945 }
1946 }
1947
1948
1949 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1950 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1951
1952 Condition negated_cond = negate_condition(cond);
1953 Label L;
1954 jcc(negated_cond, L);
1955 pushf(); // Preserve flags
1956 atomic_incl(counter_addr, rscratch);
1957 popf();
1958 bind(L);
1959 }
1960
1961 int MacroAssembler::corrected_idivl(Register reg) {
1962 // Full implementation of Java idiv and irem; checks for
1963 // special case as described in JVM spec., p.243 & p.271.
1964 // The function returns the (pc) offset of the idivl
1965 // instruction - may be needed for implicit exceptions.
1966 //
1967 // normal case special case
1968 //
1969 // input : rax,: dividend min_int
1970 // reg: divisor (may not be rax,/rdx) -1
1971 //
1972 // output: rax,: quotient (= rax, idiv reg) min_int
1973 // rdx: remainder (= rax, irem reg) 0
1974 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1975 const int min_int = 0x80000000;
1976 Label normal_case, special_case;
1977
1978 // check for special case
1979 cmpl(rax, min_int);
1980 jcc(Assembler::notEqual, normal_case);
1981 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1982 cmpl(reg, -1);
1983 jcc(Assembler::equal, special_case);
1984
1985 // handle normal case
1986 bind(normal_case);
1987 cdql();
1988 int idivl_offset = offset();
1989 idivl(reg);
1990
1991 // normal and special case exit
1992 bind(special_case);
1993
1994 return idivl_offset;
1995 }
1996
1997
1998
1999 void MacroAssembler::decrementl(Register reg, int value) {
2000 if (value == min_jint) {subl(reg, value) ; return; }
2001 if (value < 0) { incrementl(reg, -value); return; }
2002 if (value == 0) { ; return; }
2003 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2004 /* else */ { subl(reg, value) ; return; }
2005 }
2006
2007 void MacroAssembler::decrementl(Address dst, int value) {
2008 if (value == min_jint) {subl(dst, value) ; return; }
2009 if (value < 0) { incrementl(dst, -value); return; }
2010 if (value == 0) { ; return; }
2011 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2012 /* else */ { subl(dst, value) ; return; }
2013 }
2014
2015 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2016 assert(shift_value > 0, "illegal shift value");
2017 Label _is_positive;
2018 testl (reg, reg);
2019 jcc (Assembler::positive, _is_positive);
2020 int offset = (1 << shift_value) - 1 ;
2021
2022 if (offset == 1) {
2023 incrementl(reg);
2024 } else {
2025 addl(reg, offset);
2026 }
2027
2028 bind (_is_positive);
2029 sarl(reg, shift_value);
2030 }
2031
2032 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2033 assert(rscratch != noreg || always_reachable(src), "missing");
2034
2035 if (reachable(src)) {
2036 Assembler::divsd(dst, as_Address(src));
2037 } else {
2038 lea(rscratch, src);
2039 Assembler::divsd(dst, Address(rscratch, 0));
2040 }
2041 }
2042
2043 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2044 assert(rscratch != noreg || always_reachable(src), "missing");
2045
2046 if (reachable(src)) {
2047 Assembler::divss(dst, as_Address(src));
2048 } else {
2049 lea(rscratch, src);
2050 Assembler::divss(dst, Address(rscratch, 0));
2051 }
2052 }
2053
2054 void MacroAssembler::enter() {
2055 push(rbp);
2056 mov(rbp, rsp);
2057 }
2058
2059 void MacroAssembler::post_call_nop() {
2060 if (!Continuations::enabled()) {
2061 return;
2062 }
2063 InstructionMark im(this);
2064 relocate(post_call_nop_Relocation::spec());
2065 InlineSkippedInstructionsCounter skipCounter(this);
2066 emit_int8((uint8_t)0x0f);
2067 emit_int8((uint8_t)0x1f);
2068 emit_int8((uint8_t)0x84);
2069 emit_int8((uint8_t)0x00);
2070 emit_int32(0x00);
2071 }
2072
2073 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2074 void MacroAssembler::fat_nop() {
2075 if (UseAddressNop) {
2076 addr_nop_5();
2077 } else {
2078 emit_int8((uint8_t)0x26); // es:
2079 emit_int8((uint8_t)0x2e); // cs:
2080 emit_int8((uint8_t)0x64); // fs:
2081 emit_int8((uint8_t)0x65); // gs:
2082 emit_int8((uint8_t)0x90);
2083 }
2084 }
2085
2086 #ifndef _LP64
2087 void MacroAssembler::fcmp(Register tmp) {
2088 fcmp(tmp, 1, true, true);
2089 }
2090
2091 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2092 assert(!pop_right || pop_left, "usage error");
2093 if (VM_Version::supports_cmov()) {
2094 assert(tmp == noreg, "unneeded temp");
2095 if (pop_left) {
2096 fucomip(index);
2097 } else {
2098 fucomi(index);
2099 }
2100 if (pop_right) {
2101 fpop();
2102 }
2103 } else {
2104 assert(tmp != noreg, "need temp");
2105 if (pop_left) {
2106 if (pop_right) {
2107 fcompp();
2108 } else {
2109 fcomp(index);
2110 }
2111 } else {
2112 fcom(index);
2113 }
2114 // convert FPU condition into eflags condition via rax,
2115 save_rax(tmp);
2116 fwait(); fnstsw_ax();
2117 sahf();
2118 restore_rax(tmp);
2119 }
2120 // condition codes set as follows:
2121 //
2122 // CF (corresponds to C0) if x < y
2123 // PF (corresponds to C2) if unordered
2124 // ZF (corresponds to C3) if x = y
2125 }
2126
2127 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2128 fcmp2int(dst, unordered_is_less, 1, true, true);
2129 }
2130
2131 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2132 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2133 Label L;
2134 if (unordered_is_less) {
2135 movl(dst, -1);
2136 jcc(Assembler::parity, L);
2137 jcc(Assembler::below , L);
2138 movl(dst, 0);
2139 jcc(Assembler::equal , L);
2140 increment(dst);
2141 } else { // unordered is greater
2142 movl(dst, 1);
2143 jcc(Assembler::parity, L);
2144 jcc(Assembler::above , L);
2145 movl(dst, 0);
2146 jcc(Assembler::equal , L);
2147 decrementl(dst);
2148 }
2149 bind(L);
2150 }
2151
2152 void MacroAssembler::fld_d(AddressLiteral src) {
2153 fld_d(as_Address(src));
2154 }
2155
2156 void MacroAssembler::fld_s(AddressLiteral src) {
2157 fld_s(as_Address(src));
2158 }
2159
2160 void MacroAssembler::fldcw(AddressLiteral src) {
2161 fldcw(as_Address(src));
2162 }
2163
2164 void MacroAssembler::fpop() {
2165 ffree();
2166 fincstp();
2167 }
2168
2169 void MacroAssembler::fremr(Register tmp) {
2170 save_rax(tmp);
2171 { Label L;
2172 bind(L);
2173 fprem();
2174 fwait(); fnstsw_ax();
2175 sahf();
2176 jcc(Assembler::parity, L);
2177 }
2178 restore_rax(tmp);
2179 // Result is in ST0.
2180 // Note: fxch & fpop to get rid of ST1
2181 // (otherwise FPU stack could overflow eventually)
2182 fxch(1);
2183 fpop();
2184 }
2185
2186 void MacroAssembler::empty_FPU_stack() {
2187 if (VM_Version::supports_mmx()) {
2188 emms();
2189 } else {
2190 for (int i = 8; i-- > 0; ) ffree(i);
2191 }
2192 }
2193 #endif // !LP64
2194
2195 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2196 assert(rscratch != noreg || always_reachable(src), "missing");
2197 if (reachable(src)) {
2198 Assembler::mulpd(dst, as_Address(src));
2199 } else {
2200 lea(rscratch, src);
2201 Assembler::mulpd(dst, Address(rscratch, 0));
2202 }
2203 }
2204
2205 void MacroAssembler::load_float(Address src) {
2206 #ifdef _LP64
2207 movflt(xmm0, src);
2208 #else
2209 if (UseSSE >= 1) {
2210 movflt(xmm0, src);
2211 } else {
2212 fld_s(src);
2213 }
2214 #endif // LP64
2215 }
2216
2217 void MacroAssembler::store_float(Address dst) {
2218 #ifdef _LP64
2219 movflt(dst, xmm0);
2220 #else
2221 if (UseSSE >= 1) {
2222 movflt(dst, xmm0);
2223 } else {
2224 fstp_s(dst);
2225 }
2226 #endif // LP64
2227 }
2228
2229 void MacroAssembler::load_double(Address src) {
2230 #ifdef _LP64
2231 movdbl(xmm0, src);
2232 #else
2233 if (UseSSE >= 2) {
2234 movdbl(xmm0, src);
2235 } else {
2236 fld_d(src);
2237 }
2238 #endif // LP64
2239 }
2240
2241 void MacroAssembler::store_double(Address dst) {
2242 #ifdef _LP64
2243 movdbl(dst, xmm0);
2244 #else
2245 if (UseSSE >= 2) {
2246 movdbl(dst, xmm0);
2247 } else {
2248 fstp_d(dst);
2249 }
2250 #endif // LP64
2251 }
2252
2253 // dst = c = a * b + c
2254 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2255 Assembler::vfmadd231sd(c, a, b);
2256 if (dst != c) {
2257 movdbl(dst, c);
2258 }
2259 }
2260
2261 // dst = c = a * b + c
2262 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2263 Assembler::vfmadd231ss(c, a, b);
2264 if (dst != c) {
2265 movflt(dst, c);
2266 }
2267 }
2268
2269 // dst = c = a * b + c
2270 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2271 Assembler::vfmadd231pd(c, a, b, vector_len);
2272 if (dst != c) {
2273 vmovdqu(dst, c);
2274 }
2275 }
2276
2277 // dst = c = a * b + c
2278 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2279 Assembler::vfmadd231ps(c, a, b, vector_len);
2280 if (dst != c) {
2281 vmovdqu(dst, c);
2282 }
2283 }
2284
2285 // dst = c = a * b + c
2286 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2287 Assembler::vfmadd231pd(c, a, b, vector_len);
2288 if (dst != c) {
2289 vmovdqu(dst, c);
2290 }
2291 }
2292
2293 // dst = c = a * b + c
2294 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2295 Assembler::vfmadd231ps(c, a, b, vector_len);
2296 if (dst != c) {
2297 vmovdqu(dst, c);
2298 }
2299 }
2300
2301 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
2302 assert(rscratch != noreg || always_reachable(dst), "missing");
2303
2304 if (reachable(dst)) {
2305 incrementl(as_Address(dst));
2306 } else {
2307 lea(rscratch, dst);
2308 incrementl(Address(rscratch, 0));
2309 }
2310 }
2311
2312 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
2313 incrementl(as_Address(dst, rscratch));
2314 }
2315
2316 void MacroAssembler::incrementl(Register reg, int value) {
2317 if (value == min_jint) {addl(reg, value) ; return; }
2318 if (value < 0) { decrementl(reg, -value); return; }
2319 if (value == 0) { ; return; }
2320 if (value == 1 && UseIncDec) { incl(reg) ; return; }
2321 /* else */ { addl(reg, value) ; return; }
2322 }
2323
2324 void MacroAssembler::incrementl(Address dst, int value) {
2325 if (value == min_jint) {addl(dst, value) ; return; }
2326 if (value < 0) { decrementl(dst, -value); return; }
2327 if (value == 0) { ; return; }
2328 if (value == 1 && UseIncDec) { incl(dst) ; return; }
2329 /* else */ { addl(dst, value) ; return; }
2330 }
2331
2332 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
2333 assert(rscratch != noreg || always_reachable(dst), "missing");
2334
2335 if (reachable(dst)) {
2336 jmp_literal(dst.target(), dst.rspec());
2337 } else {
2338 lea(rscratch, dst);
2339 jmp(rscratch);
2340 }
2341 }
2342
2343 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
2344 assert(rscratch != noreg || always_reachable(dst), "missing");
2345
2346 if (reachable(dst)) {
2347 InstructionMark im(this);
2348 relocate(dst.reloc());
2349 const int short_size = 2;
2350 const int long_size = 6;
2351 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2352 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2353 // 0111 tttn #8-bit disp
2354 emit_int8(0x70 | cc);
2355 emit_int8((offs - short_size) & 0xFF);
2356 } else {
2357 // 0000 1111 1000 tttn #32-bit disp
2358 emit_int8(0x0F);
2359 emit_int8((unsigned char)(0x80 | cc));
2360 emit_int32(offs - long_size);
2361 }
2362 } else {
2363 #ifdef ASSERT
2364 warning("reversing conditional branch");
2365 #endif /* ASSERT */
2366 Label skip;
2367 jccb(reverse[cc], skip);
2368 lea(rscratch, dst);
2369 Assembler::jmp(rscratch);
2370 bind(skip);
2371 }
2372 }
2373
2374 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
2375 assert(rscratch != noreg || always_reachable(src), "missing");
2376
2377 if (reachable(src)) {
2378 Assembler::ldmxcsr(as_Address(src));
2379 } else {
2380 lea(rscratch, src);
2381 Assembler::ldmxcsr(Address(rscratch, 0));
2382 }
2383 }
2384
2385 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2386 int off;
2387 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2388 off = offset();
2389 movsbl(dst, src); // movsxb
2390 } else {
2391 off = load_unsigned_byte(dst, src);
2392 shll(dst, 24);
2393 sarl(dst, 24);
2394 }
2395 return off;
2396 }
2397
2398 // Note: load_signed_short used to be called load_signed_word.
2399 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2400 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2401 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2402 int MacroAssembler::load_signed_short(Register dst, Address src) {
2403 int off;
2404 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2405 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2406 // version but this is what 64bit has always done. This seems to imply
2407 // that users are only using 32bits worth.
2408 off = offset();
2409 movswl(dst, src); // movsxw
2410 } else {
2411 off = load_unsigned_short(dst, src);
2412 shll(dst, 16);
2413 sarl(dst, 16);
2414 }
2415 return off;
2416 }
2417
2418 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2419 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2420 // and "3.9 Partial Register Penalties", p. 22).
2421 int off;
2422 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2423 off = offset();
2424 movzbl(dst, src); // movzxb
2425 } else {
2426 xorl(dst, dst);
2427 off = offset();
2428 movb(dst, src);
2429 }
2430 return off;
2431 }
2432
2433 // Note: load_unsigned_short used to be called load_unsigned_word.
2434 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2435 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2436 // and "3.9 Partial Register Penalties", p. 22).
2437 int off;
2438 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2439 off = offset();
2440 movzwl(dst, src); // movzxw
2441 } else {
2442 xorl(dst, dst);
2443 off = offset();
2444 movw(dst, src);
2445 }
2446 return off;
2447 }
2448
2449 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2450 switch (size_in_bytes) {
2451 #ifndef _LP64
2452 case 8:
2453 assert(dst2 != noreg, "second dest register required");
2454 movl(dst, src);
2455 movl(dst2, src.plus_disp(BytesPerInt));
2456 break;
2457 #else
2458 case 8: movq(dst, src); break;
2459 #endif
2460 case 4: movl(dst, src); break;
2461 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2462 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2463 default: ShouldNotReachHere();
2464 }
2465 }
2466
2467 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2468 switch (size_in_bytes) {
2469 #ifndef _LP64
2470 case 8:
2471 assert(src2 != noreg, "second source register required");
2472 movl(dst, src);
2473 movl(dst.plus_disp(BytesPerInt), src2);
2474 break;
2475 #else
2476 case 8: movq(dst, src); break;
2477 #endif
2478 case 4: movl(dst, src); break;
2479 case 2: movw(dst, src); break;
2480 case 1: movb(dst, src); break;
2481 default: ShouldNotReachHere();
2482 }
2483 }
2484
2485 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
2486 assert(rscratch != noreg || always_reachable(dst), "missing");
2487
2488 if (reachable(dst)) {
2489 movl(as_Address(dst), src);
2490 } else {
2491 lea(rscratch, dst);
2492 movl(Address(rscratch, 0), src);
2493 }
2494 }
2495
2496 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2497 if (reachable(src)) {
2498 movl(dst, as_Address(src));
2499 } else {
2500 lea(dst, src);
2501 movl(dst, Address(dst, 0));
2502 }
2503 }
2504
2505 // C++ bool manipulation
2506
2507 void MacroAssembler::movbool(Register dst, Address src) {
2508 if(sizeof(bool) == 1)
2509 movb(dst, src);
2510 else if(sizeof(bool) == 2)
2511 movw(dst, src);
2512 else if(sizeof(bool) == 4)
2513 movl(dst, src);
2514 else
2515 // unsupported
2516 ShouldNotReachHere();
2517 }
2518
2519 void MacroAssembler::movbool(Address dst, bool boolconst) {
2520 if(sizeof(bool) == 1)
2521 movb(dst, (int) boolconst);
2522 else if(sizeof(bool) == 2)
2523 movw(dst, (int) boolconst);
2524 else if(sizeof(bool) == 4)
2525 movl(dst, (int) boolconst);
2526 else
2527 // unsupported
2528 ShouldNotReachHere();
2529 }
2530
2531 void MacroAssembler::movbool(Address dst, Register src) {
2532 if(sizeof(bool) == 1)
2533 movb(dst, src);
2534 else if(sizeof(bool) == 2)
2535 movw(dst, src);
2536 else if(sizeof(bool) == 4)
2537 movl(dst, src);
2538 else
2539 // unsupported
2540 ShouldNotReachHere();
2541 }
2542
2543 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2544 assert(rscratch != noreg || always_reachable(src), "missing");
2545
2546 if (reachable(src)) {
2547 movdl(dst, as_Address(src));
2548 } else {
2549 lea(rscratch, src);
2550 movdl(dst, Address(rscratch, 0));
2551 }
2552 }
2553
2554 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
2555 assert(rscratch != noreg || always_reachable(src), "missing");
2556
2557 if (reachable(src)) {
2558 movq(dst, as_Address(src));
2559 } else {
2560 lea(rscratch, src);
2561 movq(dst, Address(rscratch, 0));
2562 }
2563 }
2564
2565 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2566 assert(rscratch != noreg || always_reachable(src), "missing");
2567
2568 if (reachable(src)) {
2569 if (UseXmmLoadAndClearUpper) {
2570 movsd (dst, as_Address(src));
2571 } else {
2572 movlpd(dst, as_Address(src));
2573 }
2574 } else {
2575 lea(rscratch, src);
2576 if (UseXmmLoadAndClearUpper) {
2577 movsd (dst, Address(rscratch, 0));
2578 } else {
2579 movlpd(dst, Address(rscratch, 0));
2580 }
2581 }
2582 }
2583
2584 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
2585 assert(rscratch != noreg || always_reachable(src), "missing");
2586
2587 if (reachable(src)) {
2588 movss(dst, as_Address(src));
2589 } else {
2590 lea(rscratch, src);
2591 movss(dst, Address(rscratch, 0));
2592 }
2593 }
2594
2595 void MacroAssembler::movptr(Register dst, Register src) {
2596 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2597 }
2598
2599 void MacroAssembler::movptr(Register dst, Address src) {
2600 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2601 }
2602
2603 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2604 void MacroAssembler::movptr(Register dst, intptr_t src) {
2605 #ifdef _LP64
2606 if (is_uimm32(src)) {
2607 movl(dst, checked_cast<uint32_t>(src));
2608 } else if (is_simm32(src)) {
2609 movq(dst, checked_cast<int32_t>(src));
2610 } else {
2611 mov64(dst, src);
2612 }
2613 #else
2614 movl(dst, src);
2615 #endif
2616 }
2617
2618 void MacroAssembler::movptr(Address dst, Register src) {
2619 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2620 }
2621
2622 void MacroAssembler::movptr(Address dst, int32_t src) {
2623 LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src));
2624 }
2625
2626 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2627 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2628 Assembler::movdqu(dst, src);
2629 }
2630
2631 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2632 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2633 Assembler::movdqu(dst, src);
2634 }
2635
2636 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2637 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2638 Assembler::movdqu(dst, src);
2639 }
2640
2641 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2642 assert(rscratch != noreg || always_reachable(src), "missing");
2643
2644 if (reachable(src)) {
2645 movdqu(dst, as_Address(src));
2646 } else {
2647 lea(rscratch, src);
2648 movdqu(dst, Address(rscratch, 0));
2649 }
2650 }
2651
2652 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2653 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2654 Assembler::vmovdqu(dst, src);
2655 }
2656
2657 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2658 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2659 Assembler::vmovdqu(dst, src);
2660 }
2661
2662 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2663 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2664 Assembler::vmovdqu(dst, src);
2665 }
2666
2667 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2668 assert(rscratch != noreg || always_reachable(src), "missing");
2669
2670 if (reachable(src)) {
2671 vmovdqu(dst, as_Address(src));
2672 }
2673 else {
2674 lea(rscratch, src);
2675 vmovdqu(dst, Address(rscratch, 0));
2676 }
2677 }
2678
2679 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2680 assert(rscratch != noreg || always_reachable(src), "missing");
2681
2682 if (vector_len == AVX_512bit) {
2683 evmovdquq(dst, src, AVX_512bit, rscratch);
2684 } else if (vector_len == AVX_256bit) {
2685 vmovdqu(dst, src, rscratch);
2686 } else {
2687 movdqu(dst, src, rscratch);
2688 }
2689 }
2690
2691 void MacroAssembler::kmov(KRegister dst, Address src) {
2692 if (VM_Version::supports_avx512bw()) {
2693 kmovql(dst, src);
2694 } else {
2695 assert(VM_Version::supports_evex(), "");
2696 kmovwl(dst, src);
2697 }
2698 }
2699
2700 void MacroAssembler::kmov(Address dst, KRegister src) {
2701 if (VM_Version::supports_avx512bw()) {
2702 kmovql(dst, src);
2703 } else {
2704 assert(VM_Version::supports_evex(), "");
2705 kmovwl(dst, src);
2706 }
2707 }
2708
2709 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2710 if (VM_Version::supports_avx512bw()) {
2711 kmovql(dst, src);
2712 } else {
2713 assert(VM_Version::supports_evex(), "");
2714 kmovwl(dst, src);
2715 }
2716 }
2717
2718 void MacroAssembler::kmov(Register dst, KRegister src) {
2719 if (VM_Version::supports_avx512bw()) {
2720 kmovql(dst, src);
2721 } else {
2722 assert(VM_Version::supports_evex(), "");
2723 kmovwl(dst, src);
2724 }
2725 }
2726
2727 void MacroAssembler::kmov(KRegister dst, Register src) {
2728 if (VM_Version::supports_avx512bw()) {
2729 kmovql(dst, src);
2730 } else {
2731 assert(VM_Version::supports_evex(), "");
2732 kmovwl(dst, src);
2733 }
2734 }
2735
2736 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2737 assert(rscratch != noreg || always_reachable(src), "missing");
2738
2739 if (reachable(src)) {
2740 kmovql(dst, as_Address(src));
2741 } else {
2742 lea(rscratch, src);
2743 kmovql(dst, Address(rscratch, 0));
2744 }
2745 }
2746
2747 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2748 assert(rscratch != noreg || always_reachable(src), "missing");
2749
2750 if (reachable(src)) {
2751 kmovwl(dst, as_Address(src));
2752 } else {
2753 lea(rscratch, src);
2754 kmovwl(dst, Address(rscratch, 0));
2755 }
2756 }
2757
2758 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2759 int vector_len, Register rscratch) {
2760 assert(rscratch != noreg || always_reachable(src), "missing");
2761
2762 if (reachable(src)) {
2763 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2764 } else {
2765 lea(rscratch, src);
2766 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2767 }
2768 }
2769
2770 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2771 int vector_len, Register rscratch) {
2772 assert(rscratch != noreg || always_reachable(src), "missing");
2773
2774 if (reachable(src)) {
2775 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2776 } else {
2777 lea(rscratch, src);
2778 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2779 }
2780 }
2781
2782 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2783 assert(rscratch != noreg || always_reachable(src), "missing");
2784
2785 if (reachable(src)) {
2786 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2787 } else {
2788 lea(rscratch, src);
2789 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2790 }
2791 }
2792
2793 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2794 assert(rscratch != noreg || always_reachable(src), "missing");
2795
2796 if (reachable(src)) {
2797 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2798 } else {
2799 lea(rscratch, src);
2800 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2801 }
2802 }
2803
2804 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2805 assert(rscratch != noreg || always_reachable(src), "missing");
2806
2807 if (reachable(src)) {
2808 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2809 } else {
2810 lea(rscratch, src);
2811 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2812 }
2813 }
2814
2815 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2816 assert(rscratch != noreg || always_reachable(src), "missing");
2817
2818 if (reachable(src)) {
2819 Assembler::movdqa(dst, as_Address(src));
2820 } else {
2821 lea(rscratch, src);
2822 Assembler::movdqa(dst, Address(rscratch, 0));
2823 }
2824 }
2825
2826 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2827 assert(rscratch != noreg || always_reachable(src), "missing");
2828
2829 if (reachable(src)) {
2830 Assembler::movsd(dst, as_Address(src));
2831 } else {
2832 lea(rscratch, src);
2833 Assembler::movsd(dst, Address(rscratch, 0));
2834 }
2835 }
2836
2837 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2838 assert(rscratch != noreg || always_reachable(src), "missing");
2839
2840 if (reachable(src)) {
2841 Assembler::movss(dst, as_Address(src));
2842 } else {
2843 lea(rscratch, src);
2844 Assembler::movss(dst, Address(rscratch, 0));
2845 }
2846 }
2847
2848 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2849 assert(rscratch != noreg || always_reachable(src), "missing");
2850
2851 if (reachable(src)) {
2852 Assembler::movddup(dst, as_Address(src));
2853 } else {
2854 lea(rscratch, src);
2855 Assembler::movddup(dst, Address(rscratch, 0));
2856 }
2857 }
2858
2859 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2860 assert(rscratch != noreg || always_reachable(src), "missing");
2861
2862 if (reachable(src)) {
2863 Assembler::vmovddup(dst, as_Address(src), vector_len);
2864 } else {
2865 lea(rscratch, src);
2866 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2867 }
2868 }
2869
2870 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2871 assert(rscratch != noreg || always_reachable(src), "missing");
2872
2873 if (reachable(src)) {
2874 Assembler::mulsd(dst, as_Address(src));
2875 } else {
2876 lea(rscratch, src);
2877 Assembler::mulsd(dst, Address(rscratch, 0));
2878 }
2879 }
2880
2881 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2882 assert(rscratch != noreg || always_reachable(src), "missing");
2883
2884 if (reachable(src)) {
2885 Assembler::mulss(dst, as_Address(src));
2886 } else {
2887 lea(rscratch, src);
2888 Assembler::mulss(dst, Address(rscratch, 0));
2889 }
2890 }
2891
2892 void MacroAssembler::null_check(Register reg, int offset) {
2893 if (needs_explicit_null_check(offset)) {
2894 // provoke OS null exception if reg is null by
2895 // accessing M[reg] w/o changing any (non-CC) registers
2896 // NOTE: cmpl is plenty here to provoke a segv
2897 cmpptr(rax, Address(reg, 0));
2898 // Note: should probably use testl(rax, Address(reg, 0));
2899 // may be shorter code (however, this version of
2900 // testl needs to be implemented first)
2901 } else {
2902 // nothing to do, (later) access of M[reg + offset]
2903 // will provoke OS null exception if reg is null
2904 }
2905 }
2906
2907 void MacroAssembler::os_breakpoint() {
2908 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2909 // (e.g., MSVC can't call ps() otherwise)
2910 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2911 }
2912
2913 void MacroAssembler::unimplemented(const char* what) {
2914 const char* buf = nullptr;
2915 {
2916 ResourceMark rm;
2917 stringStream ss;
2918 ss.print("unimplemented: %s", what);
2919 buf = code_string(ss.as_string());
2920 }
2921 stop(buf);
2922 }
2923
2924 #ifdef _LP64
2925 #define XSTATE_BV 0x200
2926 #endif
2927
2928 void MacroAssembler::pop_CPU_state() {
2929 pop_FPU_state();
2930 pop_IU_state();
2931 }
2932
2933 void MacroAssembler::pop_FPU_state() {
2934 #ifndef _LP64
2935 frstor(Address(rsp, 0));
2936 #else
2937 fxrstor(Address(rsp, 0));
2938 #endif
2939 addptr(rsp, FPUStateSizeInWords * wordSize);
2940 }
2941
2942 void MacroAssembler::pop_IU_state() {
2943 popa();
2944 LP64_ONLY(addq(rsp, 8));
2945 popf();
2946 }
2947
2948 // Save Integer and Float state
2949 // Warning: Stack must be 16 byte aligned (64bit)
2950 void MacroAssembler::push_CPU_state() {
2951 push_IU_state();
2952 push_FPU_state();
2953 }
2954
2955 void MacroAssembler::push_FPU_state() {
2956 subptr(rsp, FPUStateSizeInWords * wordSize);
2957 #ifndef _LP64
2958 fnsave(Address(rsp, 0));
2959 fwait();
2960 #else
2961 fxsave(Address(rsp, 0));
2962 #endif // LP64
2963 }
2964
2965 void MacroAssembler::push_IU_state() {
2966 // Push flags first because pusha kills them
2967 pushf();
2968 // Make sure rsp stays 16-byte aligned
2969 LP64_ONLY(subq(rsp, 8));
2970 pusha();
2971 }
2972
2973 void MacroAssembler::push_cont_fastpath() {
2974 if (!Continuations::enabled()) return;
2975
2976 #ifndef _LP64
2977 Register rthread = rax;
2978 Register rrealsp = rbx;
2979 push(rthread);
2980 push(rrealsp);
2981
2982 get_thread(rthread);
2983
2984 // The code below wants the original RSP.
2985 // Move it back after the pushes above.
2986 movptr(rrealsp, rsp);
2987 addptr(rrealsp, 2*wordSize);
2988 #else
2989 Register rthread = r15_thread;
2990 Register rrealsp = rsp;
2991 #endif
2992
2993 Label done;
2994 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
2995 jccb(Assembler::belowEqual, done);
2996 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), rrealsp);
2997 bind(done);
2998
2999 #ifndef _LP64
3000 pop(rrealsp);
3001 pop(rthread);
3002 #endif
3003 }
3004
3005 void MacroAssembler::pop_cont_fastpath() {
3006 if (!Continuations::enabled()) return;
3007
3008 #ifndef _LP64
3009 Register rthread = rax;
3010 Register rrealsp = rbx;
3011 push(rthread);
3012 push(rrealsp);
3013
3014 get_thread(rthread);
3015
3016 // The code below wants the original RSP.
3017 // Move it back after the pushes above.
3018 movptr(rrealsp, rsp);
3019 addptr(rrealsp, 2*wordSize);
3020 #else
3021 Register rthread = r15_thread;
3022 Register rrealsp = rsp;
3023 #endif
3024
3025 Label done;
3026 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3027 jccb(Assembler::below, done);
3028 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), 0);
3029 bind(done);
3030
3031 #ifndef _LP64
3032 pop(rrealsp);
3033 pop(rthread);
3034 #endif
3035 }
3036
3037 void MacroAssembler::inc_held_monitor_count() {
3038 #ifndef _LP64
3039 Register thread = rax;
3040 push(thread);
3041 get_thread(thread);
3042 incrementl(Address(thread, JavaThread::held_monitor_count_offset()));
3043 pop(thread);
3044 #else // LP64
3045 incrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3046 #endif
3047 }
3048
3049 void MacroAssembler::dec_held_monitor_count() {
3050 #ifndef _LP64
3051 Register thread = rax;
3052 push(thread);
3053 get_thread(thread);
3054 decrementl(Address(thread, JavaThread::held_monitor_count_offset()));
3055 pop(thread);
3056 #else // LP64
3057 decrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3058 #endif
3059 }
3060
3061 #ifdef ASSERT
3062 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
3063 #ifdef _LP64
3064 Label no_cont;
3065 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
3066 testl(cont, cont);
3067 jcc(Assembler::zero, no_cont);
3068 stop(name);
3069 bind(no_cont);
3070 #else
3071 Unimplemented();
3072 #endif
3073 }
3074 #endif
3075
3076 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3077 if (!java_thread->is_valid()) {
3078 java_thread = rdi;
3079 get_thread(java_thread);
3080 }
3081 // we must set sp to zero to clear frame
3082 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3083 // must clear fp, so that compiled frames are not confused; it is
3084 // possible that we need it only for debugging
3085 if (clear_fp) {
3086 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3087 }
3088 // Always clear the pc because it could have been set by make_walkable()
3089 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3090 vzeroupper();
3091 }
3092
3093 void MacroAssembler::restore_rax(Register tmp) {
3094 if (tmp == noreg) pop(rax);
3095 else if (tmp != rax) mov(rax, tmp);
3096 }
3097
3098 void MacroAssembler::round_to(Register reg, int modulus) {
3099 addptr(reg, modulus - 1);
3100 andptr(reg, -modulus);
3101 }
3102
3103 void MacroAssembler::save_rax(Register tmp) {
3104 if (tmp == noreg) push(rax);
3105 else if (tmp != rax) mov(tmp, rax);
3106 }
3107
3108 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
3109 if (at_return) {
3110 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
3111 // we may safely use rsp instead to perform the stack watermark check.
3112 cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
3113 jcc(Assembler::above, slow_path);
3114 return;
3115 }
3116 testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
3117 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3118 }
3119
3120 // Calls to C land
3121 //
3122 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3123 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3124 // has to be reset to 0. This is required to allow proper stack traversal.
3125 void MacroAssembler::set_last_Java_frame(Register java_thread,
3126 Register last_java_sp,
3127 Register last_java_fp,
3128 address last_java_pc,
3129 Register rscratch) {
3130 vzeroupper();
3131 // determine java_thread register
3132 if (!java_thread->is_valid()) {
3133 java_thread = rdi;
3134 get_thread(java_thread);
3135 }
3136 // determine last_java_sp register
3137 if (!last_java_sp->is_valid()) {
3138 last_java_sp = rsp;
3139 }
3140 // last_java_fp is optional
3141 if (last_java_fp->is_valid()) {
3142 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3143 }
3144 // last_java_pc is optional
3145 if (last_java_pc != nullptr) {
3146 Address java_pc(java_thread,
3147 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
3148 lea(java_pc, InternalAddress(last_java_pc), rscratch);
3149 }
3150 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3151 }
3152
3153 void MacroAssembler::shlptr(Register dst, int imm8) {
3154 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3155 }
3156
3157 void MacroAssembler::shrptr(Register dst, int imm8) {
3158 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3159 }
3160
3161 void MacroAssembler::sign_extend_byte(Register reg) {
3162 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3163 movsbl(reg, reg); // movsxb
3164 } else {
3165 shll(reg, 24);
3166 sarl(reg, 24);
3167 }
3168 }
3169
3170 void MacroAssembler::sign_extend_short(Register reg) {
3171 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3172 movswl(reg, reg); // movsxw
3173 } else {
3174 shll(reg, 16);
3175 sarl(reg, 16);
3176 }
3177 }
3178
3179 void MacroAssembler::testl(Address dst, int32_t imm32) {
3180 if (imm32 >= 0 && is8bit(imm32)) {
3181 testb(dst, imm32);
3182 } else {
3183 Assembler::testl(dst, imm32);
3184 }
3185 }
3186
3187 void MacroAssembler::testl(Register dst, int32_t imm32) {
3188 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
3189 testb(dst, imm32);
3190 } else {
3191 Assembler::testl(dst, imm32);
3192 }
3193 }
3194
3195 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3196 assert(always_reachable(src), "Address should be reachable");
3197 testl(dst, as_Address(src));
3198 }
3199
3200 #ifdef _LP64
3201
3202 void MacroAssembler::testq(Address dst, int32_t imm32) {
3203 if (imm32 >= 0) {
3204 testl(dst, imm32);
3205 } else {
3206 Assembler::testq(dst, imm32);
3207 }
3208 }
3209
3210 void MacroAssembler::testq(Register dst, int32_t imm32) {
3211 if (imm32 >= 0) {
3212 testl(dst, imm32);
3213 } else {
3214 Assembler::testq(dst, imm32);
3215 }
3216 }
3217
3218 #endif
3219
3220 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3221 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3222 Assembler::pcmpeqb(dst, src);
3223 }
3224
3225 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3226 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3227 Assembler::pcmpeqw(dst, src);
3228 }
3229
3230 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3231 assert((dst->encoding() < 16),"XMM register should be 0-15");
3232 Assembler::pcmpestri(dst, src, imm8);
3233 }
3234
3235 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3236 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3237 Assembler::pcmpestri(dst, src, imm8);
3238 }
3239
3240 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3241 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3242 Assembler::pmovzxbw(dst, src);
3243 }
3244
3245 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3246 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3247 Assembler::pmovzxbw(dst, src);
3248 }
3249
3250 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3251 assert((src->encoding() < 16),"XMM register should be 0-15");
3252 Assembler::pmovmskb(dst, src);
3253 }
3254
3255 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3256 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3257 Assembler::ptest(dst, src);
3258 }
3259
3260 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3261 assert(rscratch != noreg || always_reachable(src), "missing");
3262
3263 if (reachable(src)) {
3264 Assembler::sqrtss(dst, as_Address(src));
3265 } else {
3266 lea(rscratch, src);
3267 Assembler::sqrtss(dst, Address(rscratch, 0));
3268 }
3269 }
3270
3271 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3272 assert(rscratch != noreg || always_reachable(src), "missing");
3273
3274 if (reachable(src)) {
3275 Assembler::subsd(dst, as_Address(src));
3276 } else {
3277 lea(rscratch, src);
3278 Assembler::subsd(dst, Address(rscratch, 0));
3279 }
3280 }
3281
3282 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
3283 assert(rscratch != noreg || always_reachable(src), "missing");
3284
3285 if (reachable(src)) {
3286 Assembler::roundsd(dst, as_Address(src), rmode);
3287 } else {
3288 lea(rscratch, src);
3289 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
3290 }
3291 }
3292
3293 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3294 assert(rscratch != noreg || always_reachable(src), "missing");
3295
3296 if (reachable(src)) {
3297 Assembler::subss(dst, as_Address(src));
3298 } else {
3299 lea(rscratch, src);
3300 Assembler::subss(dst, Address(rscratch, 0));
3301 }
3302 }
3303
3304 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3305 assert(rscratch != noreg || always_reachable(src), "missing");
3306
3307 if (reachable(src)) {
3308 Assembler::ucomisd(dst, as_Address(src));
3309 } else {
3310 lea(rscratch, src);
3311 Assembler::ucomisd(dst, Address(rscratch, 0));
3312 }
3313 }
3314
3315 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3316 assert(rscratch != noreg || always_reachable(src), "missing");
3317
3318 if (reachable(src)) {
3319 Assembler::ucomiss(dst, as_Address(src));
3320 } else {
3321 lea(rscratch, src);
3322 Assembler::ucomiss(dst, Address(rscratch, 0));
3323 }
3324 }
3325
3326 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3327 assert(rscratch != noreg || always_reachable(src), "missing");
3328
3329 // Used in sign-bit flipping with aligned address.
3330 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3331 if (reachable(src)) {
3332 Assembler::xorpd(dst, as_Address(src));
3333 } else {
3334 lea(rscratch, src);
3335 Assembler::xorpd(dst, Address(rscratch, 0));
3336 }
3337 }
3338
3339 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3340 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3341 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3342 }
3343 else {
3344 Assembler::xorpd(dst, src);
3345 }
3346 }
3347
3348 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3349 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3350 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3351 } else {
3352 Assembler::xorps(dst, src);
3353 }
3354 }
3355
3356 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
3357 assert(rscratch != noreg || always_reachable(src), "missing");
3358
3359 // Used in sign-bit flipping with aligned address.
3360 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3361 if (reachable(src)) {
3362 Assembler::xorps(dst, as_Address(src));
3363 } else {
3364 lea(rscratch, src);
3365 Assembler::xorps(dst, Address(rscratch, 0));
3366 }
3367 }
3368
3369 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
3370 assert(rscratch != noreg || always_reachable(src), "missing");
3371
3372 // Used in sign-bit flipping with aligned address.
3373 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3374 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3375 if (reachable(src)) {
3376 Assembler::pshufb(dst, as_Address(src));
3377 } else {
3378 lea(rscratch, src);
3379 Assembler::pshufb(dst, Address(rscratch, 0));
3380 }
3381 }
3382
3383 // AVX 3-operands instructions
3384
3385 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3386 assert(rscratch != noreg || always_reachable(src), "missing");
3387
3388 if (reachable(src)) {
3389 vaddsd(dst, nds, as_Address(src));
3390 } else {
3391 lea(rscratch, src);
3392 vaddsd(dst, nds, Address(rscratch, 0));
3393 }
3394 }
3395
3396 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3397 assert(rscratch != noreg || always_reachable(src), "missing");
3398
3399 if (reachable(src)) {
3400 vaddss(dst, nds, as_Address(src));
3401 } else {
3402 lea(rscratch, src);
3403 vaddss(dst, nds, Address(rscratch, 0));
3404 }
3405 }
3406
3407 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3408 assert(UseAVX > 0, "requires some form of AVX");
3409 assert(rscratch != noreg || always_reachable(src), "missing");
3410
3411 if (reachable(src)) {
3412 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3413 } else {
3414 lea(rscratch, src);
3415 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3416 }
3417 }
3418
3419 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3420 assert(UseAVX > 0, "requires some form of AVX");
3421 assert(rscratch != noreg || always_reachable(src), "missing");
3422
3423 if (reachable(src)) {
3424 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3425 } else {
3426 lea(rscratch, src);
3427 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3428 }
3429 }
3430
3431 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3432 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3433 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3434
3435 vandps(dst, nds, negate_field, vector_len, rscratch);
3436 }
3437
3438 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3439 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3440 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3441
3442 vandpd(dst, nds, negate_field, vector_len, rscratch);
3443 }
3444
3445 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3446 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3447 Assembler::vpaddb(dst, nds, src, vector_len);
3448 }
3449
3450 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3451 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3452 Assembler::vpaddb(dst, nds, src, vector_len);
3453 }
3454
3455 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3456 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3457 Assembler::vpaddw(dst, nds, src, vector_len);
3458 }
3459
3460 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3461 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3462 Assembler::vpaddw(dst, nds, src, vector_len);
3463 }
3464
3465 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3466 assert(rscratch != noreg || always_reachable(src), "missing");
3467
3468 if (reachable(src)) {
3469 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3470 } else {
3471 lea(rscratch, src);
3472 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
3473 }
3474 }
3475
3476 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3477 assert(rscratch != noreg || always_reachable(src), "missing");
3478
3479 if (reachable(src)) {
3480 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
3481 } else {
3482 lea(rscratch, src);
3483 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
3484 }
3485 }
3486
3487 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3488 assert(rscratch != noreg || always_reachable(src), "missing");
3489
3490 if (reachable(src)) {
3491 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3492 } else {
3493 lea(rscratch, src);
3494 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3495 }
3496 }
3497
3498 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3499 assert(rscratch != noreg || always_reachable(src), "missing");
3500
3501 if (reachable(src)) {
3502 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3503 } else {
3504 lea(rscratch, src);
3505 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3506 }
3507 }
3508
3509 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3510 assert(rscratch != noreg || always_reachable(src), "missing");
3511
3512 if (reachable(src)) {
3513 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3514 } else {
3515 lea(rscratch, src);
3516 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3517 }
3518 }
3519
3520 // Vector float blend
3521 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3522 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3523 // WARN: Allow dst == (src1|src2), mask == scratch
3524 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3525 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3526 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3527 if (blend_emulation && scratch_available && dst_available) {
3528 if (compute_mask) {
3529 vpsrad(scratch, mask, 32, vector_len);
3530 mask = scratch;
3531 }
3532 if (dst == src1) {
3533 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3534 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3535 } else {
3536 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3537 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3538 }
3539 vpor(dst, dst, scratch, vector_len);
3540 } else {
3541 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3542 }
3543 }
3544
3545 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3546 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3547 // WARN: Allow dst == (src1|src2), mask == scratch
3548 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3549 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3550 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3551 if (blend_emulation && scratch_available && dst_available) {
3552 if (compute_mask) {
3553 vpxor(scratch, scratch, scratch, vector_len);
3554 vpcmpgtq(scratch, scratch, mask, vector_len);
3555 mask = scratch;
3556 }
3557 if (dst == src1) {
3558 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3559 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3560 } else {
3561 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3562 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3563 }
3564 vpor(dst, dst, scratch, vector_len);
3565 } else {
3566 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3567 }
3568 }
3569
3570 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3571 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3572 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3573 }
3574
3575 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3576 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3577 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3578 }
3579
3580 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3581 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3582 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3583 }
3584
3585 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3586 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3587 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3588 }
3589
3590 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3591 assert(rscratch != noreg || always_reachable(src), "missing");
3592
3593 if (reachable(src)) {
3594 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3595 } else {
3596 lea(rscratch, src);
3597 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3598 }
3599 }
3600
3601 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3602 int comparison, bool is_signed, int vector_len, Register rscratch) {
3603 assert(rscratch != noreg || always_reachable(src), "missing");
3604
3605 if (reachable(src)) {
3606 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3607 } else {
3608 lea(rscratch, src);
3609 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3610 }
3611 }
3612
3613 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3614 int comparison, bool is_signed, int vector_len, Register rscratch) {
3615 assert(rscratch != noreg || always_reachable(src), "missing");
3616
3617 if (reachable(src)) {
3618 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3619 } else {
3620 lea(rscratch, src);
3621 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3622 }
3623 }
3624
3625 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3626 int comparison, bool is_signed, int vector_len, Register rscratch) {
3627 assert(rscratch != noreg || always_reachable(src), "missing");
3628
3629 if (reachable(src)) {
3630 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3631 } else {
3632 lea(rscratch, src);
3633 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3634 }
3635 }
3636
3637 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3638 int comparison, bool is_signed, int vector_len, Register rscratch) {
3639 assert(rscratch != noreg || always_reachable(src), "missing");
3640
3641 if (reachable(src)) {
3642 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3643 } else {
3644 lea(rscratch, src);
3645 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3646 }
3647 }
3648
3649 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3650 if (width == Assembler::Q) {
3651 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3652 } else {
3653 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3654 }
3655 }
3656
3657 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3658 int eq_cond_enc = 0x29;
3659 int gt_cond_enc = 0x37;
3660 if (width != Assembler::Q) {
3661 eq_cond_enc = 0x74 + width;
3662 gt_cond_enc = 0x64 + width;
3663 }
3664 switch (cond) {
3665 case eq:
3666 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3667 break;
3668 case neq:
3669 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3670 vallones(xtmp, vector_len);
3671 vpxor(dst, xtmp, dst, vector_len);
3672 break;
3673 case le:
3674 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3675 vallones(xtmp, vector_len);
3676 vpxor(dst, xtmp, dst, vector_len);
3677 break;
3678 case nlt:
3679 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3680 vallones(xtmp, vector_len);
3681 vpxor(dst, xtmp, dst, vector_len);
3682 break;
3683 case lt:
3684 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3685 break;
3686 case nle:
3687 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3688 break;
3689 default:
3690 assert(false, "Should not reach here");
3691 }
3692 }
3693
3694 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3695 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3696 Assembler::vpmovzxbw(dst, src, vector_len);
3697 }
3698
3699 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3700 assert((src->encoding() < 16),"XMM register should be 0-15");
3701 Assembler::vpmovmskb(dst, src, vector_len);
3702 }
3703
3704 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3705 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3706 Assembler::vpmullw(dst, nds, src, vector_len);
3707 }
3708
3709 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3710 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3711 Assembler::vpmullw(dst, nds, src, vector_len);
3712 }
3713
3714 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3715 assert((UseAVX > 0), "AVX support is needed");
3716 assert(rscratch != noreg || always_reachable(src), "missing");
3717
3718 if (reachable(src)) {
3719 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3720 } else {
3721 lea(rscratch, src);
3722 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3723 }
3724 }
3725
3726 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3727 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3728 Assembler::vpsubb(dst, nds, src, vector_len);
3729 }
3730
3731 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3732 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3733 Assembler::vpsubb(dst, nds, src, vector_len);
3734 }
3735
3736 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3737 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3738 Assembler::vpsubw(dst, nds, src, vector_len);
3739 }
3740
3741 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3742 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3743 Assembler::vpsubw(dst, nds, src, vector_len);
3744 }
3745
3746 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3747 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3748 Assembler::vpsraw(dst, nds, shift, vector_len);
3749 }
3750
3751 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3752 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3753 Assembler::vpsraw(dst, nds, shift, vector_len);
3754 }
3755
3756 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3757 assert(UseAVX > 2,"");
3758 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3759 vector_len = 2;
3760 }
3761 Assembler::evpsraq(dst, nds, shift, vector_len);
3762 }
3763
3764 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3765 assert(UseAVX > 2,"");
3766 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3767 vector_len = 2;
3768 }
3769 Assembler::evpsraq(dst, nds, shift, vector_len);
3770 }
3771
3772 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3773 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3774 Assembler::vpsrlw(dst, nds, shift, vector_len);
3775 }
3776
3777 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3778 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3779 Assembler::vpsrlw(dst, nds, shift, vector_len);
3780 }
3781
3782 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3783 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3784 Assembler::vpsllw(dst, nds, shift, vector_len);
3785 }
3786
3787 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3788 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3789 Assembler::vpsllw(dst, nds, shift, vector_len);
3790 }
3791
3792 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3793 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3794 Assembler::vptest(dst, src);
3795 }
3796
3797 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3798 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3799 Assembler::punpcklbw(dst, src);
3800 }
3801
3802 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3803 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3804 Assembler::pshufd(dst, src, mode);
3805 }
3806
3807 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3808 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3809 Assembler::pshuflw(dst, src, mode);
3810 }
3811
3812 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3813 assert(rscratch != noreg || always_reachable(src), "missing");
3814
3815 if (reachable(src)) {
3816 vandpd(dst, nds, as_Address(src), vector_len);
3817 } else {
3818 lea(rscratch, src);
3819 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3820 }
3821 }
3822
3823 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3824 assert(rscratch != noreg || always_reachable(src), "missing");
3825
3826 if (reachable(src)) {
3827 vandps(dst, nds, as_Address(src), vector_len);
3828 } else {
3829 lea(rscratch, src);
3830 vandps(dst, nds, Address(rscratch, 0), vector_len);
3831 }
3832 }
3833
3834 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3835 bool merge, int vector_len, Register rscratch) {
3836 assert(rscratch != noreg || always_reachable(src), "missing");
3837
3838 if (reachable(src)) {
3839 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3840 } else {
3841 lea(rscratch, src);
3842 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3843 }
3844 }
3845
3846 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3847 assert(rscratch != noreg || always_reachable(src), "missing");
3848
3849 if (reachable(src)) {
3850 vdivsd(dst, nds, as_Address(src));
3851 } else {
3852 lea(rscratch, src);
3853 vdivsd(dst, nds, Address(rscratch, 0));
3854 }
3855 }
3856
3857 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3858 assert(rscratch != noreg || always_reachable(src), "missing");
3859
3860 if (reachable(src)) {
3861 vdivss(dst, nds, as_Address(src));
3862 } else {
3863 lea(rscratch, src);
3864 vdivss(dst, nds, Address(rscratch, 0));
3865 }
3866 }
3867
3868 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3869 assert(rscratch != noreg || always_reachable(src), "missing");
3870
3871 if (reachable(src)) {
3872 vmulsd(dst, nds, as_Address(src));
3873 } else {
3874 lea(rscratch, src);
3875 vmulsd(dst, nds, Address(rscratch, 0));
3876 }
3877 }
3878
3879 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3880 assert(rscratch != noreg || always_reachable(src), "missing");
3881
3882 if (reachable(src)) {
3883 vmulss(dst, nds, as_Address(src));
3884 } else {
3885 lea(rscratch, src);
3886 vmulss(dst, nds, Address(rscratch, 0));
3887 }
3888 }
3889
3890 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3891 assert(rscratch != noreg || always_reachable(src), "missing");
3892
3893 if (reachable(src)) {
3894 vsubsd(dst, nds, as_Address(src));
3895 } else {
3896 lea(rscratch, src);
3897 vsubsd(dst, nds, Address(rscratch, 0));
3898 }
3899 }
3900
3901 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3902 assert(rscratch != noreg || always_reachable(src), "missing");
3903
3904 if (reachable(src)) {
3905 vsubss(dst, nds, as_Address(src));
3906 } else {
3907 lea(rscratch, src);
3908 vsubss(dst, nds, Address(rscratch, 0));
3909 }
3910 }
3911
3912 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3913 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3914 assert(rscratch != noreg || always_reachable(src), "missing");
3915
3916 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3917 }
3918
3919 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3920 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3921 assert(rscratch != noreg || always_reachable(src), "missing");
3922
3923 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3924 }
3925
3926 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3927 assert(rscratch != noreg || always_reachable(src), "missing");
3928
3929 if (reachable(src)) {
3930 vxorpd(dst, nds, as_Address(src), vector_len);
3931 } else {
3932 lea(rscratch, src);
3933 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3934 }
3935 }
3936
3937 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3938 assert(rscratch != noreg || always_reachable(src), "missing");
3939
3940 if (reachable(src)) {
3941 vxorps(dst, nds, as_Address(src), vector_len);
3942 } else {
3943 lea(rscratch, src);
3944 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3945 }
3946 }
3947
3948 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3949 assert(rscratch != noreg || always_reachable(src), "missing");
3950
3951 if (UseAVX > 1 || (vector_len < 1)) {
3952 if (reachable(src)) {
3953 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3954 } else {
3955 lea(rscratch, src);
3956 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3957 }
3958 } else {
3959 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3960 }
3961 }
3962
3963 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3964 assert(rscratch != noreg || always_reachable(src), "missing");
3965
3966 if (reachable(src)) {
3967 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3968 } else {
3969 lea(rscratch, src);
3970 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3971 }
3972 }
3973
3974 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3975 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3976 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3977 // The inverted mask is sign-extended
3978 andptr(possibly_non_local, inverted_mask);
3979 }
3980
3981 void MacroAssembler::resolve_jobject(Register value,
3982 Register thread,
3983 Register tmp) {
3984 assert_different_registers(value, thread, tmp);
3985 Label done, tagged, weak_tagged;
3986 testptr(value, value);
3987 jcc(Assembler::zero, done); // Use null as-is.
3988 testptr(value, JNIHandles::tag_mask); // Test for tag.
3989 jcc(Assembler::notZero, tagged);
3990
3991 // Resolve local handle
3992 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp, thread);
3993 verify_oop(value);
3994 jmp(done);
3995
3996 bind(tagged);
3997 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
3998 jcc(Assembler::notZero, weak_tagged);
3999
4000 // Resolve global handle
4001 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4002 verify_oop(value);
4003 jmp(done);
4004
4005 bind(weak_tagged);
4006 // Resolve jweak.
4007 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4008 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp, thread);
4009 verify_oop(value);
4010
4011 bind(done);
4012 }
4013
4014 void MacroAssembler::resolve_global_jobject(Register value,
4015 Register thread,
4016 Register tmp) {
4017 assert_different_registers(value, thread, tmp);
4018 Label done;
4019
4020 testptr(value, value);
4021 jcc(Assembler::zero, done); // Use null as-is.
4022
4023 #ifdef ASSERT
4024 {
4025 Label valid_global_tag;
4026 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
4027 jcc(Assembler::notZero, valid_global_tag);
4028 stop("non global jobject using resolve_global_jobject");
4029 bind(valid_global_tag);
4030 }
4031 #endif
4032
4033 // Resolve global handle
4034 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4035 verify_oop(value);
4036
4037 bind(done);
4038 }
4039
4040 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4041 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4042 }
4043
4044 // Force generation of a 4 byte immediate value even if it fits into 8bit
4045 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4046 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4047 }
4048
4049 void MacroAssembler::subptr(Register dst, Register src) {
4050 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4051 }
4052
4053 // C++ bool manipulation
4054 void MacroAssembler::testbool(Register dst) {
4055 if(sizeof(bool) == 1)
4056 testb(dst, 0xff);
4057 else if(sizeof(bool) == 2) {
4058 // testw implementation needed for two byte bools
4059 ShouldNotReachHere();
4060 } else if(sizeof(bool) == 4)
4061 testl(dst, dst);
4062 else
4063 // unsupported
4064 ShouldNotReachHere();
4065 }
4066
4067 void MacroAssembler::testptr(Register dst, Register src) {
4068 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4069 }
4070
4071 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4072 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4073 Register var_size_in_bytes,
4074 int con_size_in_bytes,
4075 Register t1,
4076 Register t2,
4077 Label& slow_case) {
4078 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4079 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4080 }
4081
4082 RegSet MacroAssembler::call_clobbered_gp_registers() {
4083 RegSet regs;
4084 #ifdef _LP64
4085 regs += RegSet::of(rax, rcx, rdx);
4086 #ifndef WINDOWS
4087 regs += RegSet::of(rsi, rdi);
4088 #endif
4089 regs += RegSet::range(r8, r11);
4090 #else
4091 regs += RegSet::of(rax, rcx, rdx);
4092 #endif
4093 #ifdef _LP64
4094 if (UseAPX) {
4095 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
4096 }
4097 #endif
4098 return regs;
4099 }
4100
4101 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
4102 int num_xmm_registers = XMMRegister::available_xmm_registers();
4103 #if defined(WINDOWS) && defined(_LP64)
4104 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
4105 if (num_xmm_registers > 16) {
4106 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
4107 }
4108 return result;
4109 #else
4110 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
4111 #endif
4112 }
4113
4114 static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor
4115
4116 #ifndef _LP64
4117 static bool use_x87_registers() { return UseSSE < 2; }
4118 #endif
4119 static bool use_xmm_registers() { return UseSSE >= 1; }
4120
4121 // C1 only ever uses the first double/float of the XMM register.
4122 static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); }
4123
4124 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4125 if (UseSSE == 1) {
4126 masm->movflt(Address(rsp, offset), reg);
4127 } else {
4128 masm->movdbl(Address(rsp, offset), reg);
4129 }
4130 }
4131
4132 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4133 if (UseSSE == 1) {
4134 masm->movflt(reg, Address(rsp, offset));
4135 } else {
4136 masm->movdbl(reg, Address(rsp, offset));
4137 }
4138 }
4139
4140 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
4141 bool save_fpu, int& gp_area_size,
4142 int& fp_area_size, int& xmm_area_size) {
4143
4144 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
4145 StackAlignmentInBytes);
4146 #ifdef _LP64
4147 fp_area_size = 0;
4148 #else
4149 fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0;
4150 #endif
4151 xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0;
4152
4153 return gp_area_size + fp_area_size + xmm_area_size;
4154 }
4155
4156 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
4157 block_comment("push_call_clobbered_registers start");
4158 // Regular registers
4159 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
4160
4161 int gp_area_size;
4162 int fp_area_size;
4163 int xmm_area_size;
4164 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
4165 gp_area_size, fp_area_size, xmm_area_size);
4166 subptr(rsp, total_save_size);
4167
4168 push_set(gp_registers_to_push, 0);
4169
4170 #ifndef _LP64
4171 if (save_fpu && use_x87_registers()) {
4172 fnsave(Address(rsp, gp_area_size));
4173 fwait();
4174 }
4175 #endif
4176 if (save_fpu && use_xmm_registers()) {
4177 push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4178 }
4179
4180 block_comment("push_call_clobbered_registers end");
4181 }
4182
4183 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
4184 block_comment("pop_call_clobbered_registers start");
4185
4186 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
4187
4188 int gp_area_size;
4189 int fp_area_size;
4190 int xmm_area_size;
4191 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
4192 gp_area_size, fp_area_size, xmm_area_size);
4193
4194 if (restore_fpu && use_xmm_registers()) {
4195 pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4196 }
4197 #ifndef _LP64
4198 if (restore_fpu && use_x87_registers()) {
4199 frstor(Address(rsp, gp_area_size));
4200 }
4201 #endif
4202
4203 pop_set(gp_registers_to_pop, 0);
4204
4205 addptr(rsp, total_save_size);
4206
4207 vzeroupper();
4208
4209 block_comment("pop_call_clobbered_registers end");
4210 }
4211
4212 void MacroAssembler::push_set(XMMRegSet set, int offset) {
4213 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
4214 int spill_offset = offset;
4215
4216 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
4217 save_xmm_register(this, spill_offset, *it);
4218 spill_offset += xmm_save_size();
4219 }
4220 }
4221
4222 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
4223 int restore_size = set.size() * xmm_save_size();
4224 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
4225
4226 int restore_offset = offset + restore_size - xmm_save_size();
4227
4228 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
4229 restore_xmm_register(this, restore_offset, *it);
4230 restore_offset -= xmm_save_size();
4231 }
4232 }
4233
4234 void MacroAssembler::push_set(RegSet set, int offset) {
4235 int spill_offset;
4236 if (offset == -1) {
4237 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4238 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4239 subptr(rsp, aligned_size);
4240 spill_offset = 0;
4241 } else {
4242 spill_offset = offset;
4243 }
4244
4245 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
4246 movptr(Address(rsp, spill_offset), *it);
4247 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4248 }
4249 }
4250
4251 void MacroAssembler::pop_set(RegSet set, int offset) {
4252
4253 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4254 int restore_size = set.size() * gp_reg_size;
4255 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
4256
4257 int restore_offset;
4258 if (offset == -1) {
4259 restore_offset = restore_size - gp_reg_size;
4260 } else {
4261 restore_offset = offset + restore_size - gp_reg_size;
4262 }
4263 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
4264 movptr(*it, Address(rsp, restore_offset));
4265 restore_offset -= gp_reg_size;
4266 }
4267
4268 if (offset == -1) {
4269 addptr(rsp, aligned_size);
4270 }
4271 }
4272
4273 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4274 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4275 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4276 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4277 Label done;
4278
4279 testptr(length_in_bytes, length_in_bytes);
4280 jcc(Assembler::zero, done);
4281
4282 // initialize topmost word, divide index by 2, check if odd and test if zero
4283 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4284 #ifdef ASSERT
4285 {
4286 Label L;
4287 testptr(length_in_bytes, BytesPerWord - 1);
4288 jcc(Assembler::zero, L);
4289 stop("length must be a multiple of BytesPerWord");
4290 bind(L);
4291 }
4292 #endif
4293 Register index = length_in_bytes;
4294 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4295 if (UseIncDec) {
4296 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4297 } else {
4298 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4299 shrptr(index, 1);
4300 }
4301 #ifndef _LP64
4302 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4303 {
4304 Label even;
4305 // note: if index was a multiple of 8, then it cannot
4306 // be 0 now otherwise it must have been 0 before
4307 // => if it is even, we don't need to check for 0 again
4308 jcc(Assembler::carryClear, even);
4309 // clear topmost word (no jump would be needed if conditional assignment worked here)
4310 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4311 // index could be 0 now, must check again
4312 jcc(Assembler::zero, done);
4313 bind(even);
4314 }
4315 #endif // !_LP64
4316 // initialize remaining object fields: index is a multiple of 2 now
4317 {
4318 Label loop;
4319 bind(loop);
4320 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4321 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4322 decrement(index);
4323 jcc(Assembler::notZero, loop);
4324 }
4325
4326 bind(done);
4327 }
4328
4329 // Look up the method for a megamorphic invokeinterface call.
4330 // The target method is determined by <intf_klass, itable_index>.
4331 // The receiver klass is in recv_klass.
4332 // On success, the result will be in method_result, and execution falls through.
4333 // On failure, execution transfers to the given label.
4334 void MacroAssembler::lookup_interface_method(Register recv_klass,
4335 Register intf_klass,
4336 RegisterOrConstant itable_index,
4337 Register method_result,
4338 Register scan_temp,
4339 Label& L_no_such_interface,
4340 bool return_method) {
4341 assert_different_registers(recv_klass, intf_klass, scan_temp);
4342 assert_different_registers(method_result, intf_klass, scan_temp);
4343 assert(recv_klass != method_result || !return_method,
4344 "recv_klass can be destroyed when method isn't needed");
4345
4346 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4347 "caller must use same register for non-constant itable index as for method");
4348
4349 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4350 int vtable_base = in_bytes(Klass::vtable_start_offset());
4351 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4352 int scan_step = itableOffsetEntry::size() * wordSize;
4353 int vte_size = vtableEntry::size_in_bytes();
4354 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4355 assert(vte_size == wordSize, "else adjust times_vte_scale");
4356
4357 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4358
4359 // Could store the aligned, prescaled offset in the klass.
4360 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4361
4362 if (return_method) {
4363 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4364 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4365 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4366 }
4367
4368 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
4369 // if (scan->interface() == intf) {
4370 // result = (klass + scan->offset() + itable_index);
4371 // }
4372 // }
4373 Label search, found_method;
4374
4375 for (int peel = 1; peel >= 0; peel--) {
4376 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
4377 cmpptr(intf_klass, method_result);
4378
4379 if (peel) {
4380 jccb(Assembler::equal, found_method);
4381 } else {
4382 jccb(Assembler::notEqual, search);
4383 // (invert the test to fall through to found_method...)
4384 }
4385
4386 if (!peel) break;
4387
4388 bind(search);
4389
4390 // Check that the previous entry is non-null. A null entry means that
4391 // the receiver class doesn't implement the interface, and wasn't the
4392 // same as when the caller was compiled.
4393 testptr(method_result, method_result);
4394 jcc(Assembler::zero, L_no_such_interface);
4395 addptr(scan_temp, scan_step);
4396 }
4397
4398 bind(found_method);
4399
4400 if (return_method) {
4401 // Got a hit.
4402 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
4403 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4404 }
4405 }
4406
4407 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
4408 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
4409 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
4410 // The target method is determined by <holder_klass, itable_index>.
4411 // The receiver klass is in recv_klass.
4412 // On success, the result will be in method_result, and execution falls through.
4413 // On failure, execution transfers to the given label.
4414 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
4415 Register holder_klass,
4416 Register resolved_klass,
4417 Register method_result,
4418 Register scan_temp,
4419 Register temp_reg2,
4420 Register receiver,
4421 int itable_index,
4422 Label& L_no_such_interface) {
4423 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
4424 Register temp_itbl_klass = method_result;
4425 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
4426
4427 int vtable_base = in_bytes(Klass::vtable_start_offset());
4428 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4429 int scan_step = itableOffsetEntry::size() * wordSize;
4430 int vte_size = vtableEntry::size_in_bytes();
4431 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
4432 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
4433 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4434 assert(vte_size == wordSize, "adjust times_vte_scale");
4435
4436 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
4437
4438 // temp_itbl_klass = recv_klass.itable[0]
4439 // scan_temp = &recv_klass.itable[0] + step
4440 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4441 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
4442 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
4443 xorptr(temp_reg, temp_reg);
4444
4445 // Initial checks:
4446 // - if (holder_klass != resolved_klass), go to "scan for resolved"
4447 // - if (itable[0] == 0), no such interface
4448 // - if (itable[0] == holder_klass), shortcut to "holder found"
4449 cmpptr(holder_klass, resolved_klass);
4450 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
4451 testptr(temp_itbl_klass, temp_itbl_klass);
4452 jccb(Assembler::zero, L_no_such_interface);
4453 cmpptr(holder_klass, temp_itbl_klass);
4454 jccb(Assembler::equal, L_holder_found);
4455
4456 // Loop: Look for holder_klass record in itable
4457 // do {
4458 // tmp = itable[index];
4459 // index += step;
4460 // if (tmp == holder_klass) {
4461 // goto L_holder_found; // Found!
4462 // }
4463 // } while (tmp != 0);
4464 // goto L_no_such_interface // Not found.
4465 Label L_scan_holder;
4466 bind(L_scan_holder);
4467 movptr(temp_itbl_klass, Address(scan_temp, 0));
4468 addptr(scan_temp, scan_step);
4469 cmpptr(holder_klass, temp_itbl_klass);
4470 jccb(Assembler::equal, L_holder_found);
4471 testptr(temp_itbl_klass, temp_itbl_klass);
4472 jccb(Assembler::notZero, L_scan_holder);
4473
4474 jmpb(L_no_such_interface);
4475
4476 // Loop: Look for resolved_class record in itable
4477 // do {
4478 // tmp = itable[index];
4479 // index += step;
4480 // if (tmp == holder_klass) {
4481 // // Also check if we have met a holder klass
4482 // holder_tmp = itable[index-step-ioffset];
4483 // }
4484 // if (tmp == resolved_klass) {
4485 // goto L_resolved_found; // Found!
4486 // }
4487 // } while (tmp != 0);
4488 // goto L_no_such_interface // Not found.
4489 //
4490 Label L_loop_scan_resolved;
4491 bind(L_loop_scan_resolved);
4492 movptr(temp_itbl_klass, Address(scan_temp, 0));
4493 addptr(scan_temp, scan_step);
4494 bind(L_loop_scan_resolved_entry);
4495 cmpptr(holder_klass, temp_itbl_klass);
4496 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4497 cmpptr(resolved_klass, temp_itbl_klass);
4498 jccb(Assembler::equal, L_resolved_found);
4499 testptr(temp_itbl_klass, temp_itbl_klass);
4500 jccb(Assembler::notZero, L_loop_scan_resolved);
4501
4502 jmpb(L_no_such_interface);
4503
4504 Label L_ready;
4505
4506 // See if we already have a holder klass. If not, go and scan for it.
4507 bind(L_resolved_found);
4508 testptr(temp_reg, temp_reg);
4509 jccb(Assembler::zero, L_scan_holder);
4510 jmpb(L_ready);
4511
4512 bind(L_holder_found);
4513 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4514
4515 // Finally, temp_reg contains holder_klass vtable offset
4516 bind(L_ready);
4517 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4518 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4519 load_klass(scan_temp, receiver, noreg);
4520 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4521 } else {
4522 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4523 }
4524 }
4525
4526
4527 // virtual method calling
4528 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4529 RegisterOrConstant vtable_index,
4530 Register method_result) {
4531 const ByteSize base = Klass::vtable_start_offset();
4532 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4533 Address vtable_entry_addr(recv_klass,
4534 vtable_index, Address::times_ptr,
4535 base + vtableEntry::method_offset());
4536 movptr(method_result, vtable_entry_addr);
4537 }
4538
4539
4540 void MacroAssembler::check_klass_subtype(Register sub_klass,
4541 Register super_klass,
4542 Register temp_reg,
4543 Label& L_success) {
4544 Label L_failure;
4545 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4546 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4547 bind(L_failure);
4548 }
4549
4550
4551 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4552 Register super_klass,
4553 Register temp_reg,
4554 Label* L_success,
4555 Label* L_failure,
4556 Label* L_slow_path,
4557 RegisterOrConstant super_check_offset) {
4558 assert_different_registers(sub_klass, super_klass, temp_reg);
4559 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4560 if (super_check_offset.is_register()) {
4561 assert_different_registers(sub_klass, super_klass,
4562 super_check_offset.as_register());
4563 } else if (must_load_sco) {
4564 assert(temp_reg != noreg, "supply either a temp or a register offset");
4565 }
4566
4567 Label L_fallthrough;
4568 int label_nulls = 0;
4569 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4570 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4571 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4572 assert(label_nulls <= 1, "at most one null in the batch");
4573
4574 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4575 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4576 Address super_check_offset_addr(super_klass, sco_offset);
4577
4578 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4579 // range of a jccb. If this routine grows larger, reconsider at
4580 // least some of these.
4581 #define local_jcc(assembler_cond, label) \
4582 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4583 else jcc( assembler_cond, label) /*omit semi*/
4584
4585 // Hacked jmp, which may only be used just before L_fallthrough.
4586 #define final_jmp(label) \
4587 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4588 else jmp(label) /*omit semi*/
4589
4590 // If the pointers are equal, we are done (e.g., String[] elements).
4591 // This self-check enables sharing of secondary supertype arrays among
4592 // non-primary types such as array-of-interface. Otherwise, each such
4593 // type would need its own customized SSA.
4594 // We move this check to the front of the fast path because many
4595 // type checks are in fact trivially successful in this manner,
4596 // so we get a nicely predicted branch right at the start of the check.
4597 cmpptr(sub_klass, super_klass);
4598 local_jcc(Assembler::equal, *L_success);
4599
4600 // Check the supertype display:
4601 if (must_load_sco) {
4602 // Positive movl does right thing on LP64.
4603 movl(temp_reg, super_check_offset_addr);
4604 super_check_offset = RegisterOrConstant(temp_reg);
4605 }
4606 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4607 cmpptr(super_klass, super_check_addr); // load displayed supertype
4608
4609 // This check has worked decisively for primary supers.
4610 // Secondary supers are sought in the super_cache ('super_cache_addr').
4611 // (Secondary supers are interfaces and very deeply nested subtypes.)
4612 // This works in the same check above because of a tricky aliasing
4613 // between the super_cache and the primary super display elements.
4614 // (The 'super_check_addr' can address either, as the case requires.)
4615 // Note that the cache is updated below if it does not help us find
4616 // what we need immediately.
4617 // So if it was a primary super, we can just fail immediately.
4618 // Otherwise, it's the slow path for us (no success at this point).
4619
4620 if (super_check_offset.is_register()) {
4621 local_jcc(Assembler::equal, *L_success);
4622 cmpl(super_check_offset.as_register(), sc_offset);
4623 if (L_failure == &L_fallthrough) {
4624 local_jcc(Assembler::equal, *L_slow_path);
4625 } else {
4626 local_jcc(Assembler::notEqual, *L_failure);
4627 final_jmp(*L_slow_path);
4628 }
4629 } else if (super_check_offset.as_constant() == sc_offset) {
4630 // Need a slow path; fast failure is impossible.
4631 if (L_slow_path == &L_fallthrough) {
4632 local_jcc(Assembler::equal, *L_success);
4633 } else {
4634 local_jcc(Assembler::notEqual, *L_slow_path);
4635 final_jmp(*L_success);
4636 }
4637 } else {
4638 // No slow path; it's a fast decision.
4639 if (L_failure == &L_fallthrough) {
4640 local_jcc(Assembler::equal, *L_success);
4641 } else {
4642 local_jcc(Assembler::notEqual, *L_failure);
4643 final_jmp(*L_success);
4644 }
4645 }
4646
4647 bind(L_fallthrough);
4648
4649 #undef local_jcc
4650 #undef final_jmp
4651 }
4652
4653
4654 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4655 Register super_klass,
4656 Register temp_reg,
4657 Register temp2_reg,
4658 Label* L_success,
4659 Label* L_failure,
4660 bool set_cond_codes) {
4661 assert_different_registers(sub_klass, super_klass, temp_reg);
4662 if (temp2_reg != noreg)
4663 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4664 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4665
4666 Label L_fallthrough;
4667 int label_nulls = 0;
4668 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4669 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4670 assert(label_nulls <= 1, "at most one null in the batch");
4671
4672 // a couple of useful fields in sub_klass:
4673 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4674 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4675 Address secondary_supers_addr(sub_klass, ss_offset);
4676 Address super_cache_addr( sub_klass, sc_offset);
4677
4678 // Do a linear scan of the secondary super-klass chain.
4679 // This code is rarely used, so simplicity is a virtue here.
4680 // The repne_scan instruction uses fixed registers, which we must spill.
4681 // Don't worry too much about pre-existing connections with the input regs.
4682
4683 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4684 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4685
4686 // Get super_klass value into rax (even if it was in rdi or rcx).
4687 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4688 if (super_klass != rax) {
4689 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4690 mov(rax, super_klass);
4691 }
4692 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4693 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4694
4695 #ifndef PRODUCT
4696 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4697 ExternalAddress pst_counter_addr((address) pst_counter);
4698 NOT_LP64( incrementl(pst_counter_addr) );
4699 LP64_ONLY( lea(rcx, pst_counter_addr) );
4700 LP64_ONLY( incrementl(Address(rcx, 0)) );
4701 #endif //PRODUCT
4702
4703 // We will consult the secondary-super array.
4704 movptr(rdi, secondary_supers_addr);
4705 // Load the array length. (Positive movl does right thing on LP64.)
4706 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4707 // Skip to start of data.
4708 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4709
4710 // Scan RCX words at [RDI] for an occurrence of RAX.
4711 // Set NZ/Z based on last compare.
4712 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4713 // not change flags (only scas instruction which is repeated sets flags).
4714 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4715
4716 testptr(rax,rax); // Set Z = 0
4717 repne_scan();
4718
4719 // Unspill the temp. registers:
4720 if (pushed_rdi) pop(rdi);
4721 if (pushed_rcx) pop(rcx);
4722 if (pushed_rax) pop(rax);
4723
4724 if (set_cond_codes) {
4725 // Special hack for the AD files: rdi is guaranteed non-zero.
4726 assert(!pushed_rdi, "rdi must be left non-null");
4727 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4728 }
4729
4730 if (L_failure == &L_fallthrough)
4731 jccb(Assembler::notEqual, *L_failure);
4732 else jcc(Assembler::notEqual, *L_failure);
4733
4734 // Success. Cache the super we found and proceed in triumph.
4735 movptr(super_cache_addr, super_klass);
4736
4737 if (L_success != &L_fallthrough) {
4738 jmp(*L_success);
4739 }
4740
4741 #undef IS_A_TEMP
4742
4743 bind(L_fallthrough);
4744 }
4745
4746 #ifdef _LP64
4747
4748 // population_count variant for running without the POPCNT
4749 // instruction, which was introduced with SSE4.2 in 2008.
4750 void MacroAssembler::population_count(Register dst, Register src,
4751 Register scratch1, Register scratch2) {
4752 assert_different_registers(src, scratch1, scratch2);
4753 if (UsePopCountInstruction) {
4754 Assembler::popcntq(dst, src);
4755 } else {
4756 assert_different_registers(src, scratch1, scratch2);
4757 assert_different_registers(dst, scratch1, scratch2);
4758 Label loop, done;
4759
4760 mov(scratch1, src);
4761 // dst = 0;
4762 // while(scratch1 != 0) {
4763 // dst++;
4764 // scratch1 &= (scratch1 - 1);
4765 // }
4766 xorl(dst, dst);
4767 testq(scratch1, scratch1);
4768 jccb(Assembler::equal, done);
4769 {
4770 bind(loop);
4771 incq(dst);
4772 movq(scratch2, scratch1);
4773 decq(scratch2);
4774 andq(scratch1, scratch2);
4775 jccb(Assembler::notEqual, loop);
4776 }
4777 bind(done);
4778 }
4779 }
4780
4781 // Ensure that the inline code and the stub are using the same registers.
4782 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4783 do { \
4784 assert(r_super_klass == rax, "mismatch"); \
4785 assert(r_array_base == rbx, "mismatch"); \
4786 assert(r_array_length == rcx, "mismatch"); \
4787 assert(r_array_index == rdx, "mismatch"); \
4788 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4789 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4790 assert(result == rdi || result == noreg, "mismatch"); \
4791 } while(0)
4792
4793 void MacroAssembler::lookup_secondary_supers_table(Register r_sub_klass,
4794 Register r_super_klass,
4795 Register temp1,
4796 Register temp2,
4797 Register temp3,
4798 Register temp4,
4799 Register result,
4800 u1 super_klass_slot) {
4801 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4802
4803 Label L_fallthrough, L_success, L_failure;
4804
4805 BLOCK_COMMENT("lookup_secondary_supers_table {");
4806
4807 const Register
4808 r_array_index = temp1,
4809 r_array_length = temp2,
4810 r_array_base = temp3,
4811 r_bitmap = temp4;
4812
4813 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4814
4815 xorq(result, result); // = 0
4816
4817 movq(r_bitmap, Address(r_sub_klass, Klass::bitmap_offset()));
4818 movq(r_array_index, r_bitmap);
4819
4820 // First check the bitmap to see if super_klass might be present. If
4821 // the bit is zero, we are certain that super_klass is not one of
4822 // the secondary supers.
4823 u1 bit = super_klass_slot;
4824 {
4825 // NB: If the count in a x86 shift instruction is 0, the flags are
4826 // not affected, so we do a testq instead.
4827 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4828 if (shift_count != 0) {
4829 salq(r_array_index, shift_count);
4830 } else {
4831 testq(r_array_index, r_array_index);
4832 }
4833 }
4834 // We test the MSB of r_array_index, i.e. its sign bit
4835 jcc(Assembler::positive, L_failure);
4836
4837 // Get the first array index that can contain super_klass into r_array_index.
4838 if (bit != 0) {
4839 population_count(r_array_index, r_array_index, temp2, temp3);
4840 } else {
4841 movl(r_array_index, 1);
4842 }
4843 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4844
4845 // We will consult the secondary-super array.
4846 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4847
4848 // We're asserting that the first word in an Array<Klass*> is the
4849 // length, and the second word is the first word of the data. If
4850 // that ever changes, r_array_base will have to be adjusted here.
4851 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4852 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4853
4854 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4855 jccb(Assembler::equal, L_success);
4856
4857 // Is there another entry to check? Consult the bitmap.
4858 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
4859 jccb(Assembler::carryClear, L_failure);
4860
4861 // Linear probe. Rotate the bitmap so that the next bit to test is
4862 // in Bit 1.
4863 if (bit != 0) {
4864 rorq(r_bitmap, bit);
4865 }
4866
4867 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4868 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4869 // Kills: r_array_length.
4870 // Returns: result.
4871 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
4872 // Result (0/1) is in rdi
4873 jmpb(L_fallthrough);
4874
4875 bind(L_failure);
4876 incq(result); // 0 => 1
4877
4878 bind(L_success);
4879 // result = 0;
4880
4881 bind(L_fallthrough);
4882 BLOCK_COMMENT("} lookup_secondary_supers_table");
4883
4884 if (VerifySecondarySupers) {
4885 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4886 temp1, temp2, temp3);
4887 }
4888 }
4889
4890 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
4891 Label* L_success, Label* L_failure) {
4892 Label L_loop, L_fallthrough;
4893 {
4894 int label_nulls = 0;
4895 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4896 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4897 assert(label_nulls <= 1, "at most one null in the batch");
4898 }
4899 bind(L_loop);
4900 cmpq(value, Address(addr, count, Address::times_8));
4901 jcc(Assembler::equal, *L_success);
4902 addl(count, 1);
4903 cmpl(count, limit);
4904 jcc(Assembler::less, L_loop);
4905
4906 if (&L_fallthrough != L_failure) {
4907 jmp(*L_failure);
4908 }
4909 bind(L_fallthrough);
4910 }
4911
4912 // Called by code generated by check_klass_subtype_slow_path
4913 // above. This is called when there is a collision in the hashed
4914 // lookup in the secondary supers array.
4915 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
4916 Register r_array_base,
4917 Register r_array_index,
4918 Register r_bitmap,
4919 Register temp1,
4920 Register temp2,
4921 Label* L_success,
4922 Label* L_failure) {
4923 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
4924
4925 const Register
4926 r_array_length = temp1,
4927 r_sub_klass = noreg,
4928 result = noreg;
4929
4930 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4931
4932 Label L_fallthrough;
4933 int label_nulls = 0;
4934 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4935 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4936 assert(label_nulls <= 1, "at most one null in the batch");
4937
4938 // Load the array length.
4939 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4940 // And adjust the array base to point to the data.
4941 // NB! Effectively increments current slot index by 1.
4942 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
4943 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4944
4945 // Linear probe
4946 Label L_huge;
4947
4948 // The bitmap is full to bursting.
4949 // Implicit invariant: BITMAP_FULL implies (length > 0)
4950 assert(Klass::SECONDARY_SUPERS_BITMAP_FULL == ~uintx(0), "");
4951 cmpq(r_bitmap, (int32_t)-1); // sign-extends immediate to 64-bit value
4952 jcc(Assembler::equal, L_huge);
4953
4954 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
4955 // current slot (at secondary_supers[r_array_index]) has not yet
4956 // been inspected, and r_array_index may be out of bounds if we
4957 // wrapped around the end of the array.
4958
4959 { // This is conventional linear probing, but instead of terminating
4960 // when a null entry is found in the table, we maintain a bitmap
4961 // in which a 0 indicates missing entries.
4962 // The check above guarantees there are 0s in the bitmap, so the loop
4963 // eventually terminates.
4964
4965 xorl(temp2, temp2); // = 0;
4966
4967 Label L_again;
4968 bind(L_again);
4969
4970 // Check for array wraparound.
4971 cmpl(r_array_index, r_array_length);
4972 cmovl(Assembler::greaterEqual, r_array_index, temp2);
4973
4974 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4975 jcc(Assembler::equal, *L_success);
4976
4977 // If the next bit in bitmap is zero, we're done.
4978 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
4979 jcc(Assembler::carryClear, *L_failure);
4980
4981 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
4982 addl(r_array_index, 1);
4983
4984 jmp(L_again);
4985 }
4986
4987 { // Degenerate case: more than 64 secondary supers.
4988 // FIXME: We could do something smarter here, maybe a vectorized
4989 // comparison or a binary search, but is that worth any added
4990 // complexity?
4991 bind(L_huge);
4992 xorl(r_array_index, r_array_index); // = 0
4993 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
4994 L_success,
4995 (&L_fallthrough != L_failure ? L_failure : nullptr));
4996
4997 bind(L_fallthrough);
4998 }
4999 }
5000
5001 struct VerifyHelperArguments {
5002 Klass* _super;
5003 Klass* _sub;
5004 intptr_t _linear_result;
5005 intptr_t _table_result;
5006 };
5007
5008 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
5009 Klass::on_secondary_supers_verification_failure(args->_super,
5010 args->_sub,
5011 args->_linear_result,
5012 args->_table_result,
5013 msg);
5014 }
5015
5016 // Make sure that the hashed lookup and a linear scan agree.
5017 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
5018 Register r_super_klass,
5019 Register result,
5020 Register temp1,
5021 Register temp2,
5022 Register temp3) {
5023 const Register
5024 r_array_index = temp1,
5025 r_array_length = temp2,
5026 r_array_base = temp3,
5027 r_bitmap = noreg;
5028
5029 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
5030
5031 BLOCK_COMMENT("verify_secondary_supers_table {");
5032
5033 Label L_success, L_failure, L_check, L_done;
5034
5035 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5036 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5037 // And adjust the array base to point to the data.
5038 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5039
5040 testl(r_array_length, r_array_length); // array_length == 0?
5041 jcc(Assembler::zero, L_failure);
5042
5043 movl(r_array_index, 0);
5044 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
5045 // fall through to L_failure
5046
5047 const Register linear_result = r_array_index; // reuse temp1
5048
5049 bind(L_failure); // not present
5050 movl(linear_result, 1);
5051 jmp(L_check);
5052
5053 bind(L_success); // present
5054 movl(linear_result, 0);
5055
5056 bind(L_check);
5057 cmpl(linear_result, result);
5058 jcc(Assembler::equal, L_done);
5059
5060 { // To avoid calling convention issues, build a record on the stack
5061 // and pass the pointer to that instead.
5062 push(result);
5063 push(linear_result);
5064 push(r_sub_klass);
5065 push(r_super_klass);
5066 movptr(c_rarg1, rsp);
5067 movptr(c_rarg0, (uintptr_t) "mismatch");
5068 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
5069 should_not_reach_here();
5070 }
5071 bind(L_done);
5072
5073 BLOCK_COMMENT("} verify_secondary_supers_table");
5074 }
5075
5076 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
5077
5078 #endif // LP64
5079
5080 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
5081 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
5082
5083 Label L_fallthrough;
5084 if (L_fast_path == nullptr) {
5085 L_fast_path = &L_fallthrough;
5086 } else if (L_slow_path == nullptr) {
5087 L_slow_path = &L_fallthrough;
5088 }
5089
5090 // Fast path check: class is fully initialized
5091 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
5092 jcc(Assembler::equal, *L_fast_path);
5093
5094 // Fast path check: current thread is initializer thread
5095 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
5096 if (L_slow_path == &L_fallthrough) {
5097 jcc(Assembler::equal, *L_fast_path);
5098 bind(*L_slow_path);
5099 } else if (L_fast_path == &L_fallthrough) {
5100 jcc(Assembler::notEqual, *L_slow_path);
5101 bind(*L_fast_path);
5102 } else {
5103 Unimplemented();
5104 }
5105 }
5106
5107 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5108 if (VM_Version::supports_cmov()) {
5109 cmovl(cc, dst, src);
5110 } else {
5111 Label L;
5112 jccb(negate_condition(cc), L);
5113 movl(dst, src);
5114 bind(L);
5115 }
5116 }
5117
5118 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5119 if (VM_Version::supports_cmov()) {
5120 cmovl(cc, dst, src);
5121 } else {
5122 Label L;
5123 jccb(negate_condition(cc), L);
5124 movl(dst, src);
5125 bind(L);
5126 }
5127 }
5128
5129 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
5130 if (!VerifyOops) return;
5131
5132 BLOCK_COMMENT("verify_oop {");
5133 #ifdef _LP64
5134 push(rscratch1);
5135 #endif
5136 push(rax); // save rax
5137 push(reg); // pass register argument
5138
5139 // Pass register number to verify_oop_subroutine
5140 const char* b = nullptr;
5141 {
5142 ResourceMark rm;
5143 stringStream ss;
5144 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5145 b = code_string(ss.as_string());
5146 }
5147 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5148 pushptr(buffer.addr(), rscratch1);
5149
5150 // call indirectly to solve generation ordering problem
5151 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5152 call(rax);
5153 // Caller pops the arguments (oop, message) and restores rax, r10
5154 BLOCK_COMMENT("} verify_oop");
5155 }
5156
5157 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
5158 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
5159 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
5160 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
5161 vpternlogd(dst, 0xFF, dst, dst, vector_len);
5162 } else if (VM_Version::supports_avx()) {
5163 vpcmpeqd(dst, dst, dst, vector_len);
5164 } else {
5165 assert(VM_Version::supports_sse2(), "");
5166 pcmpeqd(dst, dst);
5167 }
5168 }
5169
5170 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5171 int extra_slot_offset) {
5172 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5173 int stackElementSize = Interpreter::stackElementSize;
5174 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5175 #ifdef ASSERT
5176 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5177 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5178 #endif
5179 Register scale_reg = noreg;
5180 Address::ScaleFactor scale_factor = Address::no_scale;
5181 if (arg_slot.is_constant()) {
5182 offset += arg_slot.as_constant() * stackElementSize;
5183 } else {
5184 scale_reg = arg_slot.as_register();
5185 scale_factor = Address::times(stackElementSize);
5186 }
5187 offset += wordSize; // return PC is on stack
5188 return Address(rsp, scale_reg, scale_factor, offset);
5189 }
5190
5191 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5192 if (!VerifyOops) return;
5193
5194 #ifdef _LP64
5195 push(rscratch1);
5196 #endif
5197 push(rax); // save rax,
5198 // addr may contain rsp so we will have to adjust it based on the push
5199 // we just did (and on 64 bit we do two pushes)
5200 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5201 // stores rax into addr which is backwards of what was intended.
5202 if (addr.uses(rsp)) {
5203 lea(rax, addr);
5204 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5205 } else {
5206 pushptr(addr);
5207 }
5208
5209 // Pass register number to verify_oop_subroutine
5210 const char* b = nullptr;
5211 {
5212 ResourceMark rm;
5213 stringStream ss;
5214 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5215 b = code_string(ss.as_string());
5216 }
5217 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5218 pushptr(buffer.addr(), rscratch1);
5219
5220 // call indirectly to solve generation ordering problem
5221 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5222 call(rax);
5223 // Caller pops the arguments (addr, message) and restores rax, r10.
5224 }
5225
5226 void MacroAssembler::verify_tlab() {
5227 #ifdef ASSERT
5228 if (UseTLAB && VerifyOops) {
5229 Label next, ok;
5230 Register t1 = rsi;
5231 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5232
5233 push(t1);
5234 NOT_LP64(push(thread_reg));
5235 NOT_LP64(get_thread(thread_reg));
5236
5237 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5238 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5239 jcc(Assembler::aboveEqual, next);
5240 STOP("assert(top >= start)");
5241 should_not_reach_here();
5242
5243 bind(next);
5244 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5245 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5246 jcc(Assembler::aboveEqual, ok);
5247 STOP("assert(top <= end)");
5248 should_not_reach_here();
5249
5250 bind(ok);
5251 NOT_LP64(pop(thread_reg));
5252 pop(t1);
5253 }
5254 #endif
5255 }
5256
5257 class ControlWord {
5258 public:
5259 int32_t _value;
5260
5261 int rounding_control() const { return (_value >> 10) & 3 ; }
5262 int precision_control() const { return (_value >> 8) & 3 ; }
5263 bool precision() const { return ((_value >> 5) & 1) != 0; }
5264 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5265 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5266 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5267 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5268 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5269
5270 void print() const {
5271 // rounding control
5272 const char* rc;
5273 switch (rounding_control()) {
5274 case 0: rc = "round near"; break;
5275 case 1: rc = "round down"; break;
5276 case 2: rc = "round up "; break;
5277 case 3: rc = "chop "; break;
5278 default:
5279 rc = nullptr; // silence compiler warnings
5280 fatal("Unknown rounding control: %d", rounding_control());
5281 };
5282 // precision control
5283 const char* pc;
5284 switch (precision_control()) {
5285 case 0: pc = "24 bits "; break;
5286 case 1: pc = "reserved"; break;
5287 case 2: pc = "53 bits "; break;
5288 case 3: pc = "64 bits "; break;
5289 default:
5290 pc = nullptr; // silence compiler warnings
5291 fatal("Unknown precision control: %d", precision_control());
5292 };
5293 // flags
5294 char f[9];
5295 f[0] = ' ';
5296 f[1] = ' ';
5297 f[2] = (precision ()) ? 'P' : 'p';
5298 f[3] = (underflow ()) ? 'U' : 'u';
5299 f[4] = (overflow ()) ? 'O' : 'o';
5300 f[5] = (zero_divide ()) ? 'Z' : 'z';
5301 f[6] = (denormalized()) ? 'D' : 'd';
5302 f[7] = (invalid ()) ? 'I' : 'i';
5303 f[8] = '\x0';
5304 // output
5305 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5306 }
5307
5308 };
5309
5310 class StatusWord {
5311 public:
5312 int32_t _value;
5313
5314 bool busy() const { return ((_value >> 15) & 1) != 0; }
5315 bool C3() const { return ((_value >> 14) & 1) != 0; }
5316 bool C2() const { return ((_value >> 10) & 1) != 0; }
5317 bool C1() const { return ((_value >> 9) & 1) != 0; }
5318 bool C0() const { return ((_value >> 8) & 1) != 0; }
5319 int top() const { return (_value >> 11) & 7 ; }
5320 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5321 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5322 bool precision() const { return ((_value >> 5) & 1) != 0; }
5323 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5324 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5325 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5326 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5327 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5328
5329 void print() const {
5330 // condition codes
5331 char c[5];
5332 c[0] = (C3()) ? '3' : '-';
5333 c[1] = (C2()) ? '2' : '-';
5334 c[2] = (C1()) ? '1' : '-';
5335 c[3] = (C0()) ? '0' : '-';
5336 c[4] = '\x0';
5337 // flags
5338 char f[9];
5339 f[0] = (error_status()) ? 'E' : '-';
5340 f[1] = (stack_fault ()) ? 'S' : '-';
5341 f[2] = (precision ()) ? 'P' : '-';
5342 f[3] = (underflow ()) ? 'U' : '-';
5343 f[4] = (overflow ()) ? 'O' : '-';
5344 f[5] = (zero_divide ()) ? 'Z' : '-';
5345 f[6] = (denormalized()) ? 'D' : '-';
5346 f[7] = (invalid ()) ? 'I' : '-';
5347 f[8] = '\x0';
5348 // output
5349 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5350 }
5351
5352 };
5353
5354 class TagWord {
5355 public:
5356 int32_t _value;
5357
5358 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5359
5360 void print() const {
5361 printf("%04x", _value & 0xFFFF);
5362 }
5363
5364 };
5365
5366 class FPU_Register {
5367 public:
5368 int32_t _m0;
5369 int32_t _m1;
5370 int16_t _ex;
5371
5372 bool is_indefinite() const {
5373 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5374 }
5375
5376 void print() const {
5377 char sign = (_ex < 0) ? '-' : '+';
5378 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5379 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5380 };
5381
5382 };
5383
5384 class FPU_State {
5385 public:
5386 enum {
5387 register_size = 10,
5388 number_of_registers = 8,
5389 register_mask = 7
5390 };
5391
5392 ControlWord _control_word;
5393 StatusWord _status_word;
5394 TagWord _tag_word;
5395 int32_t _error_offset;
5396 int32_t _error_selector;
5397 int32_t _data_offset;
5398 int32_t _data_selector;
5399 int8_t _register[register_size * number_of_registers];
5400
5401 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5402 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5403
5404 const char* tag_as_string(int tag) const {
5405 switch (tag) {
5406 case 0: return "valid";
5407 case 1: return "zero";
5408 case 2: return "special";
5409 case 3: return "empty";
5410 }
5411 ShouldNotReachHere();
5412 return nullptr;
5413 }
5414
5415 void print() const {
5416 // print computation registers
5417 { int t = _status_word.top();
5418 for (int i = 0; i < number_of_registers; i++) {
5419 int j = (i - t) & register_mask;
5420 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5421 st(j)->print();
5422 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5423 }
5424 }
5425 printf("\n");
5426 // print control registers
5427 printf("ctrl = "); _control_word.print(); printf("\n");
5428 printf("stat = "); _status_word .print(); printf("\n");
5429 printf("tags = "); _tag_word .print(); printf("\n");
5430 }
5431
5432 };
5433
5434 class Flag_Register {
5435 public:
5436 int32_t _value;
5437
5438 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5439 bool direction() const { return ((_value >> 10) & 1) != 0; }
5440 bool sign() const { return ((_value >> 7) & 1) != 0; }
5441 bool zero() const { return ((_value >> 6) & 1) != 0; }
5442 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5443 bool parity() const { return ((_value >> 2) & 1) != 0; }
5444 bool carry() const { return ((_value >> 0) & 1) != 0; }
5445
5446 void print() const {
5447 // flags
5448 char f[8];
5449 f[0] = (overflow ()) ? 'O' : '-';
5450 f[1] = (direction ()) ? 'D' : '-';
5451 f[2] = (sign ()) ? 'S' : '-';
5452 f[3] = (zero ()) ? 'Z' : '-';
5453 f[4] = (auxiliary_carry()) ? 'A' : '-';
5454 f[5] = (parity ()) ? 'P' : '-';
5455 f[6] = (carry ()) ? 'C' : '-';
5456 f[7] = '\x0';
5457 // output
5458 printf("%08x flags = %s", _value, f);
5459 }
5460
5461 };
5462
5463 class IU_Register {
5464 public:
5465 int32_t _value;
5466
5467 void print() const {
5468 printf("%08x %11d", _value, _value);
5469 }
5470
5471 };
5472
5473 class IU_State {
5474 public:
5475 Flag_Register _eflags;
5476 IU_Register _rdi;
5477 IU_Register _rsi;
5478 IU_Register _rbp;
5479 IU_Register _rsp;
5480 IU_Register _rbx;
5481 IU_Register _rdx;
5482 IU_Register _rcx;
5483 IU_Register _rax;
5484
5485 void print() const {
5486 // computation registers
5487 printf("rax, = "); _rax.print(); printf("\n");
5488 printf("rbx, = "); _rbx.print(); printf("\n");
5489 printf("rcx = "); _rcx.print(); printf("\n");
5490 printf("rdx = "); _rdx.print(); printf("\n");
5491 printf("rdi = "); _rdi.print(); printf("\n");
5492 printf("rsi = "); _rsi.print(); printf("\n");
5493 printf("rbp, = "); _rbp.print(); printf("\n");
5494 printf("rsp = "); _rsp.print(); printf("\n");
5495 printf("\n");
5496 // control registers
5497 printf("flgs = "); _eflags.print(); printf("\n");
5498 }
5499 };
5500
5501
5502 class CPU_State {
5503 public:
5504 FPU_State _fpu_state;
5505 IU_State _iu_state;
5506
5507 void print() const {
5508 printf("--------------------------------------------------\n");
5509 _iu_state .print();
5510 printf("\n");
5511 _fpu_state.print();
5512 printf("--------------------------------------------------\n");
5513 }
5514
5515 };
5516
5517
5518 static void _print_CPU_state(CPU_State* state) {
5519 state->print();
5520 };
5521
5522
5523 void MacroAssembler::print_CPU_state() {
5524 push_CPU_state();
5525 push(rsp); // pass CPU state
5526 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5527 addptr(rsp, wordSize); // discard argument
5528 pop_CPU_state();
5529 }
5530
5531
5532 #ifndef _LP64
5533 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5534 static int counter = 0;
5535 FPU_State* fs = &state->_fpu_state;
5536 counter++;
5537 // For leaf calls, only verify that the top few elements remain empty.
5538 // We only need 1 empty at the top for C2 code.
5539 if( stack_depth < 0 ) {
5540 if( fs->tag_for_st(7) != 3 ) {
5541 printf("FPR7 not empty\n");
5542 state->print();
5543 assert(false, "error");
5544 return false;
5545 }
5546 return true; // All other stack states do not matter
5547 }
5548
5549 assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
5550 "bad FPU control word");
5551
5552 // compute stack depth
5553 int i = 0;
5554 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5555 int d = i;
5556 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5557 // verify findings
5558 if (i != FPU_State::number_of_registers) {
5559 // stack not contiguous
5560 printf("%s: stack not contiguous at ST%d\n", s, i);
5561 state->print();
5562 assert(false, "error");
5563 return false;
5564 }
5565 // check if computed stack depth corresponds to expected stack depth
5566 if (stack_depth < 0) {
5567 // expected stack depth is -stack_depth or less
5568 if (d > -stack_depth) {
5569 // too many elements on the stack
5570 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5571 state->print();
5572 assert(false, "error");
5573 return false;
5574 }
5575 } else {
5576 // expected stack depth is stack_depth
5577 if (d != stack_depth) {
5578 // wrong stack depth
5579 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5580 state->print();
5581 assert(false, "error");
5582 return false;
5583 }
5584 }
5585 // everything is cool
5586 return true;
5587 }
5588
5589 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5590 if (!VerifyFPU) return;
5591 push_CPU_state();
5592 push(rsp); // pass CPU state
5593 ExternalAddress msg((address) s);
5594 // pass message string s
5595 pushptr(msg.addr(), noreg);
5596 push(stack_depth); // pass stack depth
5597 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5598 addptr(rsp, 3 * wordSize); // discard arguments
5599 // check for error
5600 { Label L;
5601 testl(rax, rax);
5602 jcc(Assembler::notZero, L);
5603 int3(); // break if error condition
5604 bind(L);
5605 }
5606 pop_CPU_state();
5607 }
5608 #endif // _LP64
5609
5610 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5611 // Either restore the MXCSR register after returning from the JNI Call
5612 // or verify that it wasn't changed (with -Xcheck:jni flag).
5613 if (VM_Version::supports_sse()) {
5614 if (RestoreMXCSROnJNICalls) {
5615 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5616 } else if (CheckJNICalls) {
5617 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5618 }
5619 }
5620 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5621 vzeroupper();
5622
5623 #ifndef _LP64
5624 // Either restore the x87 floating pointer control word after returning
5625 // from the JNI call or verify that it wasn't changed.
5626 if (CheckJNICalls) {
5627 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5628 }
5629 #endif // _LP64
5630 }
5631
5632 // ((OopHandle)result).resolve();
5633 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5634 assert_different_registers(result, tmp);
5635
5636 // Only 64 bit platforms support GCs that require a tmp register
5637 // Only IN_HEAP loads require a thread_tmp register
5638 // OopHandle::resolve is an indirection like jobject.
5639 access_load_at(T_OBJECT, IN_NATIVE,
5640 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5641 }
5642
5643 // ((WeakHandle)result).resolve();
5644 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5645 assert_different_registers(rresult, rtmp);
5646 Label resolved;
5647
5648 // A null weak handle resolves to null.
5649 cmpptr(rresult, 0);
5650 jcc(Assembler::equal, resolved);
5651
5652 // Only 64 bit platforms support GCs that require a tmp register
5653 // Only IN_HEAP loads require a thread_tmp register
5654 // WeakHandle::resolve is an indirection like jweak.
5655 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5656 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
5657 bind(resolved);
5658 }
5659
5660 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5661 // get mirror
5662 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5663 load_method_holder(mirror, method);
5664 movptr(mirror, Address(mirror, mirror_offset));
5665 resolve_oop_handle(mirror, tmp);
5666 }
5667
5668 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5669 load_method_holder(rresult, rmethod);
5670 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5671 }
5672
5673 void MacroAssembler::load_method_holder(Register holder, Register method) {
5674 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5675 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5676 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5677 }
5678
5679 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5680 assert_different_registers(src, tmp);
5681 assert_different_registers(dst, tmp);
5682 #ifdef _LP64
5683 if (UseCompressedClassPointers) {
5684 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5685 decode_klass_not_null(dst, tmp);
5686 } else
5687 #endif
5688 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5689 }
5690
5691 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5692 assert_different_registers(src, tmp);
5693 assert_different_registers(dst, tmp);
5694 #ifdef _LP64
5695 if (UseCompressedClassPointers) {
5696 encode_klass_not_null(src, tmp);
5697 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5698 } else
5699 #endif
5700 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5701 }
5702
5703 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5704 Register tmp1, Register thread_tmp) {
5705 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5706 decorators = AccessInternal::decorator_fixup(decorators, type);
5707 bool as_raw = (decorators & AS_RAW) != 0;
5708 if (as_raw) {
5709 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5710 } else {
5711 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5712 }
5713 }
5714
5715 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5716 Register tmp1, Register tmp2, Register tmp3) {
5717 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5718 decorators = AccessInternal::decorator_fixup(decorators, type);
5719 bool as_raw = (decorators & AS_RAW) != 0;
5720 if (as_raw) {
5721 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5722 } else {
5723 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5724 }
5725 }
5726
5727 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5728 Register thread_tmp, DecoratorSet decorators) {
5729 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
5730 }
5731
5732 // Doesn't do verification, generates fixed size code
5733 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5734 Register thread_tmp, DecoratorSet decorators) {
5735 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
5736 }
5737
5738 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5739 Register tmp2, Register tmp3, DecoratorSet decorators) {
5740 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5741 }
5742
5743 // Used for storing nulls.
5744 void MacroAssembler::store_heap_oop_null(Address dst) {
5745 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5746 }
5747
5748 #ifdef _LP64
5749 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5750 if (UseCompressedClassPointers) {
5751 // Store to klass gap in destination
5752 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5753 }
5754 }
5755
5756 #ifdef ASSERT
5757 void MacroAssembler::verify_heapbase(const char* msg) {
5758 assert (UseCompressedOops, "should be compressed");
5759 assert (Universe::heap() != nullptr, "java heap should be initialized");
5760 if (CheckCompressedOops) {
5761 Label ok;
5762 ExternalAddress src2(CompressedOops::ptrs_base_addr());
5763 const bool is_src2_reachable = reachable(src2);
5764 if (!is_src2_reachable) {
5765 push(rscratch1); // cmpptr trashes rscratch1
5766 }
5767 cmpptr(r12_heapbase, src2, rscratch1);
5768 jcc(Assembler::equal, ok);
5769 STOP(msg);
5770 bind(ok);
5771 if (!is_src2_reachable) {
5772 pop(rscratch1);
5773 }
5774 }
5775 }
5776 #endif
5777
5778 // Algorithm must match oop.inline.hpp encode_heap_oop.
5779 void MacroAssembler::encode_heap_oop(Register r) {
5780 #ifdef ASSERT
5781 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5782 #endif
5783 verify_oop_msg(r, "broken oop in encode_heap_oop");
5784 if (CompressedOops::base() == nullptr) {
5785 if (CompressedOops::shift() != 0) {
5786 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5787 shrq(r, LogMinObjAlignmentInBytes);
5788 }
5789 return;
5790 }
5791 testq(r, r);
5792 cmovq(Assembler::equal, r, r12_heapbase);
5793 subq(r, r12_heapbase);
5794 shrq(r, LogMinObjAlignmentInBytes);
5795 }
5796
5797 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5798 #ifdef ASSERT
5799 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5800 if (CheckCompressedOops) {
5801 Label ok;
5802 testq(r, r);
5803 jcc(Assembler::notEqual, ok);
5804 STOP("null oop passed to encode_heap_oop_not_null");
5805 bind(ok);
5806 }
5807 #endif
5808 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5809 if (CompressedOops::base() != nullptr) {
5810 subq(r, r12_heapbase);
5811 }
5812 if (CompressedOops::shift() != 0) {
5813 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5814 shrq(r, LogMinObjAlignmentInBytes);
5815 }
5816 }
5817
5818 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5819 #ifdef ASSERT
5820 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5821 if (CheckCompressedOops) {
5822 Label ok;
5823 testq(src, src);
5824 jcc(Assembler::notEqual, ok);
5825 STOP("null oop passed to encode_heap_oop_not_null2");
5826 bind(ok);
5827 }
5828 #endif
5829 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5830 if (dst != src) {
5831 movq(dst, src);
5832 }
5833 if (CompressedOops::base() != nullptr) {
5834 subq(dst, r12_heapbase);
5835 }
5836 if (CompressedOops::shift() != 0) {
5837 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5838 shrq(dst, LogMinObjAlignmentInBytes);
5839 }
5840 }
5841
5842 void MacroAssembler::decode_heap_oop(Register r) {
5843 #ifdef ASSERT
5844 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5845 #endif
5846 if (CompressedOops::base() == nullptr) {
5847 if (CompressedOops::shift() != 0) {
5848 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5849 shlq(r, LogMinObjAlignmentInBytes);
5850 }
5851 } else {
5852 Label done;
5853 shlq(r, LogMinObjAlignmentInBytes);
5854 jccb(Assembler::equal, done);
5855 addq(r, r12_heapbase);
5856 bind(done);
5857 }
5858 verify_oop_msg(r, "broken oop in decode_heap_oop");
5859 }
5860
5861 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5862 // Note: it will change flags
5863 assert (UseCompressedOops, "should only be used for compressed headers");
5864 assert (Universe::heap() != nullptr, "java heap should be initialized");
5865 // Cannot assert, unverified entry point counts instructions (see .ad file)
5866 // vtableStubs also counts instructions in pd_code_size_limit.
5867 // Also do not verify_oop as this is called by verify_oop.
5868 if (CompressedOops::shift() != 0) {
5869 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5870 shlq(r, LogMinObjAlignmentInBytes);
5871 if (CompressedOops::base() != nullptr) {
5872 addq(r, r12_heapbase);
5873 }
5874 } else {
5875 assert (CompressedOops::base() == nullptr, "sanity");
5876 }
5877 }
5878
5879 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5880 // Note: it will change flags
5881 assert (UseCompressedOops, "should only be used for compressed headers");
5882 assert (Universe::heap() != nullptr, "java heap should be initialized");
5883 // Cannot assert, unverified entry point counts instructions (see .ad file)
5884 // vtableStubs also counts instructions in pd_code_size_limit.
5885 // Also do not verify_oop as this is called by verify_oop.
5886 if (CompressedOops::shift() != 0) {
5887 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5888 if (LogMinObjAlignmentInBytes == Address::times_8) {
5889 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5890 } else {
5891 if (dst != src) {
5892 movq(dst, src);
5893 }
5894 shlq(dst, LogMinObjAlignmentInBytes);
5895 if (CompressedOops::base() != nullptr) {
5896 addq(dst, r12_heapbase);
5897 }
5898 }
5899 } else {
5900 assert (CompressedOops::base() == nullptr, "sanity");
5901 if (dst != src) {
5902 movq(dst, src);
5903 }
5904 }
5905 }
5906
5907 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
5908 assert_different_registers(r, tmp);
5909 if (CompressedKlassPointers::base() != nullptr) {
5910 mov64(tmp, (int64_t)CompressedKlassPointers::base());
5911 subq(r, tmp);
5912 }
5913 if (CompressedKlassPointers::shift() != 0) {
5914 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5915 shrq(r, LogKlassAlignmentInBytes);
5916 }
5917 }
5918
5919 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
5920 assert_different_registers(src, dst);
5921 if (CompressedKlassPointers::base() != nullptr) {
5922 mov64(dst, -(int64_t)CompressedKlassPointers::base());
5923 addq(dst, src);
5924 } else {
5925 movptr(dst, src);
5926 }
5927 if (CompressedKlassPointers::shift() != 0) {
5928 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5929 shrq(dst, LogKlassAlignmentInBytes);
5930 }
5931 }
5932
5933 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
5934 assert_different_registers(r, tmp);
5935 // Note: it will change flags
5936 assert(UseCompressedClassPointers, "should only be used for compressed headers");
5937 // Cannot assert, unverified entry point counts instructions (see .ad file)
5938 // vtableStubs also counts instructions in pd_code_size_limit.
5939 // Also do not verify_oop as this is called by verify_oop.
5940 if (CompressedKlassPointers::shift() != 0) {
5941 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5942 shlq(r, LogKlassAlignmentInBytes);
5943 }
5944 if (CompressedKlassPointers::base() != nullptr) {
5945 mov64(tmp, (int64_t)CompressedKlassPointers::base());
5946 addq(r, tmp);
5947 }
5948 }
5949
5950 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
5951 assert_different_registers(src, dst);
5952 // Note: it will change flags
5953 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5954 // Cannot assert, unverified entry point counts instructions (see .ad file)
5955 // vtableStubs also counts instructions in pd_code_size_limit.
5956 // Also do not verify_oop as this is called by verify_oop.
5957
5958 if (CompressedKlassPointers::base() == nullptr &&
5959 CompressedKlassPointers::shift() == 0) {
5960 // The best case scenario is that there is no base or shift. Then it is already
5961 // a pointer that needs nothing but a register rename.
5962 movl(dst, src);
5963 } else {
5964 if (CompressedKlassPointers::base() != nullptr) {
5965 mov64(dst, (int64_t)CompressedKlassPointers::base());
5966 } else {
5967 xorq(dst, dst);
5968 }
5969 if (CompressedKlassPointers::shift() != 0) {
5970 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5971 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
5972 leaq(dst, Address(dst, src, Address::times_8, 0));
5973 } else {
5974 addq(dst, src);
5975 }
5976 }
5977 }
5978
5979 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5980 assert (UseCompressedOops, "should only be used for compressed headers");
5981 assert (Universe::heap() != nullptr, "java heap should be initialized");
5982 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5983 int oop_index = oop_recorder()->find_index(obj);
5984 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5985 mov_narrow_oop(dst, oop_index, rspec);
5986 }
5987
5988 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5989 assert (UseCompressedOops, "should only be used for compressed headers");
5990 assert (Universe::heap() != nullptr, "java heap should be initialized");
5991 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5992 int oop_index = oop_recorder()->find_index(obj);
5993 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5994 mov_narrow_oop(dst, oop_index, rspec);
5995 }
5996
5997 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5998 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5999 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6000 int klass_index = oop_recorder()->find_index(k);
6001 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6002 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6003 }
6004
6005 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6006 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6007 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6008 int klass_index = oop_recorder()->find_index(k);
6009 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6010 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6011 }
6012
6013 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6014 assert (UseCompressedOops, "should only be used for compressed headers");
6015 assert (Universe::heap() != nullptr, "java heap should be initialized");
6016 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6017 int oop_index = oop_recorder()->find_index(obj);
6018 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6019 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6020 }
6021
6022 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6023 assert (UseCompressedOops, "should only be used for compressed headers");
6024 assert (Universe::heap() != nullptr, "java heap should be initialized");
6025 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6026 int oop_index = oop_recorder()->find_index(obj);
6027 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6028 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6029 }
6030
6031 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6032 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6033 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6034 int klass_index = oop_recorder()->find_index(k);
6035 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6036 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6037 }
6038
6039 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6040 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6041 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6042 int klass_index = oop_recorder()->find_index(k);
6043 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6044 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6045 }
6046
6047 void MacroAssembler::reinit_heapbase() {
6048 if (UseCompressedOops) {
6049 if (Universe::heap() != nullptr) {
6050 if (CompressedOops::base() == nullptr) {
6051 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6052 } else {
6053 mov64(r12_heapbase, (int64_t)CompressedOops::ptrs_base());
6054 }
6055 } else {
6056 movptr(r12_heapbase, ExternalAddress(CompressedOops::ptrs_base_addr()));
6057 }
6058 }
6059 }
6060
6061 #endif // _LP64
6062
6063 #if COMPILER2_OR_JVMCI
6064
6065 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6066 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6067 // cnt - number of qwords (8-byte words).
6068 // base - start address, qword aligned.
6069 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6070 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
6071 if (use64byteVector) {
6072 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
6073 } else if (MaxVectorSize >= 32) {
6074 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
6075 } else {
6076 pxor(xtmp, xtmp);
6077 }
6078 jmp(L_zero_64_bytes);
6079
6080 BIND(L_loop);
6081 if (MaxVectorSize >= 32) {
6082 fill64(base, 0, xtmp, use64byteVector);
6083 } else {
6084 movdqu(Address(base, 0), xtmp);
6085 movdqu(Address(base, 16), xtmp);
6086 movdqu(Address(base, 32), xtmp);
6087 movdqu(Address(base, 48), xtmp);
6088 }
6089 addptr(base, 64);
6090
6091 BIND(L_zero_64_bytes);
6092 subptr(cnt, 8);
6093 jccb(Assembler::greaterEqual, L_loop);
6094
6095 // Copy trailing 64 bytes
6096 if (use64byteVector) {
6097 addptr(cnt, 8);
6098 jccb(Assembler::equal, L_end);
6099 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
6100 jmp(L_end);
6101 } else {
6102 addptr(cnt, 4);
6103 jccb(Assembler::less, L_tail);
6104 if (MaxVectorSize >= 32) {
6105 vmovdqu(Address(base, 0), xtmp);
6106 } else {
6107 movdqu(Address(base, 0), xtmp);
6108 movdqu(Address(base, 16), xtmp);
6109 }
6110 }
6111 addptr(base, 32);
6112 subptr(cnt, 4);
6113
6114 BIND(L_tail);
6115 addptr(cnt, 4);
6116 jccb(Assembler::lessEqual, L_end);
6117 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6118 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
6119 } else {
6120 decrement(cnt);
6121
6122 BIND(L_sloop);
6123 movq(Address(base, 0), xtmp);
6124 addptr(base, 8);
6125 decrement(cnt);
6126 jccb(Assembler::greaterEqual, L_sloop);
6127 }
6128 BIND(L_end);
6129 }
6130
6131 // Clearing constant sized memory using YMM/ZMM registers.
6132 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6133 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6134 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
6135
6136 int vector64_count = (cnt & (~0x7)) >> 3;
6137 cnt = cnt & 0x7;
6138 const int fill64_per_loop = 4;
6139 const int max_unrolled_fill64 = 8;
6140
6141 // 64 byte initialization loop.
6142 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6143 int start64 = 0;
6144 if (vector64_count > max_unrolled_fill64) {
6145 Label LOOP;
6146 Register index = rtmp;
6147
6148 start64 = vector64_count - (vector64_count % fill64_per_loop);
6149
6150 movl(index, 0);
6151 BIND(LOOP);
6152 for (int i = 0; i < fill64_per_loop; i++) {
6153 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6154 }
6155 addl(index, fill64_per_loop * 64);
6156 cmpl(index, start64 * 64);
6157 jccb(Assembler::less, LOOP);
6158 }
6159 for (int i = start64; i < vector64_count; i++) {
6160 fill64(base, i * 64, xtmp, use64byteVector);
6161 }
6162
6163 // Clear remaining 64 byte tail.
6164 int disp = vector64_count * 64;
6165 if (cnt) {
6166 switch (cnt) {
6167 case 1:
6168 movq(Address(base, disp), xtmp);
6169 break;
6170 case 2:
6171 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6172 break;
6173 case 3:
6174 movl(rtmp, 0x7);
6175 kmovwl(mask, rtmp);
6176 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6177 break;
6178 case 4:
6179 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6180 break;
6181 case 5:
6182 if (use64byteVector) {
6183 movl(rtmp, 0x1F);
6184 kmovwl(mask, rtmp);
6185 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6186 } else {
6187 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6188 movq(Address(base, disp + 32), xtmp);
6189 }
6190 break;
6191 case 6:
6192 if (use64byteVector) {
6193 movl(rtmp, 0x3F);
6194 kmovwl(mask, rtmp);
6195 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6196 } else {
6197 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6198 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6199 }
6200 break;
6201 case 7:
6202 if (use64byteVector) {
6203 movl(rtmp, 0x7F);
6204 kmovwl(mask, rtmp);
6205 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6206 } else {
6207 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6208 movl(rtmp, 0x7);
6209 kmovwl(mask, rtmp);
6210 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6211 }
6212 break;
6213 default:
6214 fatal("Unexpected length : %d\n",cnt);
6215 break;
6216 }
6217 }
6218 }
6219
6220 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
6221 bool is_large, KRegister mask) {
6222 // cnt - number of qwords (8-byte words).
6223 // base - start address, qword aligned.
6224 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6225 assert(base==rdi, "base register must be edi for rep stos");
6226 assert(tmp==rax, "tmp register must be eax for rep stos");
6227 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6228 assert(InitArrayShortSize % BytesPerLong == 0,
6229 "InitArrayShortSize should be the multiple of BytesPerLong");
6230
6231 Label DONE;
6232 if (!is_large || !UseXMMForObjInit) {
6233 xorptr(tmp, tmp);
6234 }
6235
6236 if (!is_large) {
6237 Label LOOP, LONG;
6238 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6239 jccb(Assembler::greater, LONG);
6240
6241 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6242
6243 decrement(cnt);
6244 jccb(Assembler::negative, DONE); // Zero length
6245
6246 // Use individual pointer-sized stores for small counts:
6247 BIND(LOOP);
6248 movptr(Address(base, cnt, Address::times_ptr), tmp);
6249 decrement(cnt);
6250 jccb(Assembler::greaterEqual, LOOP);
6251 jmpb(DONE);
6252
6253 BIND(LONG);
6254 }
6255
6256 // Use longer rep-prefixed ops for non-small counts:
6257 if (UseFastStosb) {
6258 shlptr(cnt, 3); // convert to number of bytes
6259 rep_stosb();
6260 } else if (UseXMMForObjInit) {
6261 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
6262 } else {
6263 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6264 rep_stos();
6265 }
6266
6267 BIND(DONE);
6268 }
6269
6270 #endif //COMPILER2_OR_JVMCI
6271
6272
6273 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6274 Register to, Register value, Register count,
6275 Register rtmp, XMMRegister xtmp) {
6276 ShortBranchVerifier sbv(this);
6277 assert_different_registers(to, value, count, rtmp);
6278 Label L_exit;
6279 Label L_fill_2_bytes, L_fill_4_bytes;
6280
6281 #if defined(COMPILER2) && defined(_LP64)
6282 if(MaxVectorSize >=32 &&
6283 VM_Version::supports_avx512vlbw() &&
6284 VM_Version::supports_bmi2()) {
6285 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6286 return;
6287 }
6288 #endif
6289
6290 int shift = -1;
6291 switch (t) {
6292 case T_BYTE:
6293 shift = 2;
6294 break;
6295 case T_SHORT:
6296 shift = 1;
6297 break;
6298 case T_INT:
6299 shift = 0;
6300 break;
6301 default: ShouldNotReachHere();
6302 }
6303
6304 if (t == T_BYTE) {
6305 andl(value, 0xff);
6306 movl(rtmp, value);
6307 shll(rtmp, 8);
6308 orl(value, rtmp);
6309 }
6310 if (t == T_SHORT) {
6311 andl(value, 0xffff);
6312 }
6313 if (t == T_BYTE || t == T_SHORT) {
6314 movl(rtmp, value);
6315 shll(rtmp, 16);
6316 orl(value, rtmp);
6317 }
6318
6319 cmpptr(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
6320 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6321 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6322 Label L_skip_align2;
6323 // align source address at 4 bytes address boundary
6324 if (t == T_BYTE) {
6325 Label L_skip_align1;
6326 // One byte misalignment happens only for byte arrays
6327 testptr(to, 1);
6328 jccb(Assembler::zero, L_skip_align1);
6329 movb(Address(to, 0), value);
6330 increment(to);
6331 decrement(count);
6332 BIND(L_skip_align1);
6333 }
6334 // Two bytes misalignment happens only for byte and short (char) arrays
6335 testptr(to, 2);
6336 jccb(Assembler::zero, L_skip_align2);
6337 movw(Address(to, 0), value);
6338 addptr(to, 2);
6339 subptr(count, 1<<(shift-1));
6340 BIND(L_skip_align2);
6341 }
6342 if (UseSSE < 2) {
6343 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6344 // Fill 32-byte chunks
6345 subptr(count, 8 << shift);
6346 jcc(Assembler::less, L_check_fill_8_bytes);
6347 align(16);
6348
6349 BIND(L_fill_32_bytes_loop);
6350
6351 for (int i = 0; i < 32; i += 4) {
6352 movl(Address(to, i), value);
6353 }
6354
6355 addptr(to, 32);
6356 subptr(count, 8 << shift);
6357 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6358 BIND(L_check_fill_8_bytes);
6359 addptr(count, 8 << shift);
6360 jccb(Assembler::zero, L_exit);
6361 jmpb(L_fill_8_bytes);
6362
6363 //
6364 // length is too short, just fill qwords
6365 //
6366 BIND(L_fill_8_bytes_loop);
6367 movl(Address(to, 0), value);
6368 movl(Address(to, 4), value);
6369 addptr(to, 8);
6370 BIND(L_fill_8_bytes);
6371 subptr(count, 1 << (shift + 1));
6372 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6373 // fall through to fill 4 bytes
6374 } else {
6375 Label L_fill_32_bytes;
6376 if (!UseUnalignedLoadStores) {
6377 // align to 8 bytes, we know we are 4 byte aligned to start
6378 testptr(to, 4);
6379 jccb(Assembler::zero, L_fill_32_bytes);
6380 movl(Address(to, 0), value);
6381 addptr(to, 4);
6382 subptr(count, 1<<shift);
6383 }
6384 BIND(L_fill_32_bytes);
6385 {
6386 assert( UseSSE >= 2, "supported cpu only" );
6387 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6388 movdl(xtmp, value);
6389 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6390 Label L_check_fill_32_bytes;
6391 if (UseAVX > 2) {
6392 // Fill 64-byte chunks
6393 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6394
6395 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
6396 cmpptr(count, VM_Version::avx3_threshold());
6397 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6398
6399 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6400
6401 subptr(count, 16 << shift);
6402 jccb(Assembler::less, L_check_fill_32_bytes);
6403 align(16);
6404
6405 BIND(L_fill_64_bytes_loop_avx3);
6406 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6407 addptr(to, 64);
6408 subptr(count, 16 << shift);
6409 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6410 jmpb(L_check_fill_32_bytes);
6411
6412 BIND(L_check_fill_64_bytes_avx2);
6413 }
6414 // Fill 64-byte chunks
6415 Label L_fill_64_bytes_loop;
6416 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6417
6418 subptr(count, 16 << shift);
6419 jcc(Assembler::less, L_check_fill_32_bytes);
6420 align(16);
6421
6422 BIND(L_fill_64_bytes_loop);
6423 vmovdqu(Address(to, 0), xtmp);
6424 vmovdqu(Address(to, 32), xtmp);
6425 addptr(to, 64);
6426 subptr(count, 16 << shift);
6427 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6428
6429 BIND(L_check_fill_32_bytes);
6430 addptr(count, 8 << shift);
6431 jccb(Assembler::less, L_check_fill_8_bytes);
6432 vmovdqu(Address(to, 0), xtmp);
6433 addptr(to, 32);
6434 subptr(count, 8 << shift);
6435
6436 BIND(L_check_fill_8_bytes);
6437 // clean upper bits of YMM registers
6438 movdl(xtmp, value);
6439 pshufd(xtmp, xtmp, 0);
6440 } else {
6441 // Fill 32-byte chunks
6442 pshufd(xtmp, xtmp, 0);
6443
6444 subptr(count, 8 << shift);
6445 jcc(Assembler::less, L_check_fill_8_bytes);
6446 align(16);
6447
6448 BIND(L_fill_32_bytes_loop);
6449
6450 if (UseUnalignedLoadStores) {
6451 movdqu(Address(to, 0), xtmp);
6452 movdqu(Address(to, 16), xtmp);
6453 } else {
6454 movq(Address(to, 0), xtmp);
6455 movq(Address(to, 8), xtmp);
6456 movq(Address(to, 16), xtmp);
6457 movq(Address(to, 24), xtmp);
6458 }
6459
6460 addptr(to, 32);
6461 subptr(count, 8 << shift);
6462 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6463
6464 BIND(L_check_fill_8_bytes);
6465 }
6466 addptr(count, 8 << shift);
6467 jccb(Assembler::zero, L_exit);
6468 jmpb(L_fill_8_bytes);
6469
6470 //
6471 // length is too short, just fill qwords
6472 //
6473 BIND(L_fill_8_bytes_loop);
6474 movq(Address(to, 0), xtmp);
6475 addptr(to, 8);
6476 BIND(L_fill_8_bytes);
6477 subptr(count, 1 << (shift + 1));
6478 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6479 }
6480 }
6481 // fill trailing 4 bytes
6482 BIND(L_fill_4_bytes);
6483 testl(count, 1<<shift);
6484 jccb(Assembler::zero, L_fill_2_bytes);
6485 movl(Address(to, 0), value);
6486 if (t == T_BYTE || t == T_SHORT) {
6487 Label L_fill_byte;
6488 addptr(to, 4);
6489 BIND(L_fill_2_bytes);
6490 // fill trailing 2 bytes
6491 testl(count, 1<<(shift-1));
6492 jccb(Assembler::zero, L_fill_byte);
6493 movw(Address(to, 0), value);
6494 if (t == T_BYTE) {
6495 addptr(to, 2);
6496 BIND(L_fill_byte);
6497 // fill trailing byte
6498 testl(count, 1);
6499 jccb(Assembler::zero, L_exit);
6500 movb(Address(to, 0), value);
6501 } else {
6502 BIND(L_fill_byte);
6503 }
6504 } else {
6505 BIND(L_fill_2_bytes);
6506 }
6507 BIND(L_exit);
6508 }
6509
6510 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6511 switch(type) {
6512 case T_BYTE:
6513 case T_BOOLEAN:
6514 evpbroadcastb(dst, src, vector_len);
6515 break;
6516 case T_SHORT:
6517 case T_CHAR:
6518 evpbroadcastw(dst, src, vector_len);
6519 break;
6520 case T_INT:
6521 case T_FLOAT:
6522 evpbroadcastd(dst, src, vector_len);
6523 break;
6524 case T_LONG:
6525 case T_DOUBLE:
6526 evpbroadcastq(dst, src, vector_len);
6527 break;
6528 default:
6529 fatal("Unhandled type : %s", type2name(type));
6530 break;
6531 }
6532 }
6533
6534 // encode char[] to byte[] in ISO_8859_1 or ASCII
6535 //@IntrinsicCandidate
6536 //private static int implEncodeISOArray(byte[] sa, int sp,
6537 //byte[] da, int dp, int len) {
6538 // int i = 0;
6539 // for (; i < len; i++) {
6540 // char c = StringUTF16.getChar(sa, sp++);
6541 // if (c > '\u00FF')
6542 // break;
6543 // da[dp++] = (byte)c;
6544 // }
6545 // return i;
6546 //}
6547 //
6548 //@IntrinsicCandidate
6549 //private static int implEncodeAsciiArray(char[] sa, int sp,
6550 // byte[] da, int dp, int len) {
6551 // int i = 0;
6552 // for (; i < len; i++) {
6553 // char c = sa[sp++];
6554 // if (c >= '\u0080')
6555 // break;
6556 // da[dp++] = (byte)c;
6557 // }
6558 // return i;
6559 //}
6560 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6561 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6562 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6563 Register tmp5, Register result, bool ascii) {
6564
6565 // rsi: src
6566 // rdi: dst
6567 // rdx: len
6568 // rcx: tmp5
6569 // rax: result
6570 ShortBranchVerifier sbv(this);
6571 assert_different_registers(src, dst, len, tmp5, result);
6572 Label L_done, L_copy_1_char, L_copy_1_char_exit;
6573
6574 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
6575 int short_mask = ascii ? 0xff80 : 0xff00;
6576
6577 // set result
6578 xorl(result, result);
6579 // check for zero length
6580 testl(len, len);
6581 jcc(Assembler::zero, L_done);
6582
6583 movl(result, len);
6584
6585 // Setup pointers
6586 lea(src, Address(src, len, Address::times_2)); // char[]
6587 lea(dst, Address(dst, len, Address::times_1)); // byte[]
6588 negptr(len);
6589
6590 if (UseSSE42Intrinsics || UseAVX >= 2) {
6591 Label L_copy_8_chars, L_copy_8_chars_exit;
6592 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
6593
6594 if (UseAVX >= 2) {
6595 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
6596 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6597 movdl(tmp1Reg, tmp5);
6598 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
6599 jmp(L_chars_32_check);
6600
6601 bind(L_copy_32_chars);
6602 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
6603 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
6604 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6605 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6606 jccb(Assembler::notZero, L_copy_32_chars_exit);
6607 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6608 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
6609 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
6610
6611 bind(L_chars_32_check);
6612 addptr(len, 32);
6613 jcc(Assembler::lessEqual, L_copy_32_chars);
6614
6615 bind(L_copy_32_chars_exit);
6616 subptr(len, 16);
6617 jccb(Assembler::greater, L_copy_16_chars_exit);
6618
6619 } else if (UseSSE42Intrinsics) {
6620 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6621 movdl(tmp1Reg, tmp5);
6622 pshufd(tmp1Reg, tmp1Reg, 0);
6623 jmpb(L_chars_16_check);
6624 }
6625
6626 bind(L_copy_16_chars);
6627 if (UseAVX >= 2) {
6628 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
6629 vptest(tmp2Reg, tmp1Reg);
6630 jcc(Assembler::notZero, L_copy_16_chars_exit);
6631 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
6632 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
6633 } else {
6634 if (UseAVX > 0) {
6635 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6636 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6637 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
6638 } else {
6639 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6640 por(tmp2Reg, tmp3Reg);
6641 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6642 por(tmp2Reg, tmp4Reg);
6643 }
6644 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6645 jccb(Assembler::notZero, L_copy_16_chars_exit);
6646 packuswb(tmp3Reg, tmp4Reg);
6647 }
6648 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
6649
6650 bind(L_chars_16_check);
6651 addptr(len, 16);
6652 jcc(Assembler::lessEqual, L_copy_16_chars);
6653
6654 bind(L_copy_16_chars_exit);
6655 if (UseAVX >= 2) {
6656 // clean upper bits of YMM registers
6657 vpxor(tmp2Reg, tmp2Reg);
6658 vpxor(tmp3Reg, tmp3Reg);
6659 vpxor(tmp4Reg, tmp4Reg);
6660 movdl(tmp1Reg, tmp5);
6661 pshufd(tmp1Reg, tmp1Reg, 0);
6662 }
6663 subptr(len, 8);
6664 jccb(Assembler::greater, L_copy_8_chars_exit);
6665
6666 bind(L_copy_8_chars);
6667 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
6668 ptest(tmp3Reg, tmp1Reg);
6669 jccb(Assembler::notZero, L_copy_8_chars_exit);
6670 packuswb(tmp3Reg, tmp1Reg);
6671 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
6672 addptr(len, 8);
6673 jccb(Assembler::lessEqual, L_copy_8_chars);
6674
6675 bind(L_copy_8_chars_exit);
6676 subptr(len, 8);
6677 jccb(Assembler::zero, L_done);
6678 }
6679
6680 bind(L_copy_1_char);
6681 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
6682 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
6683 jccb(Assembler::notZero, L_copy_1_char_exit);
6684 movb(Address(dst, len, Address::times_1, 0), tmp5);
6685 addptr(len, 1);
6686 jccb(Assembler::less, L_copy_1_char);
6687
6688 bind(L_copy_1_char_exit);
6689 addptr(result, len); // len is negative count of not processed elements
6690
6691 bind(L_done);
6692 }
6693
6694 #ifdef _LP64
6695 /**
6696 * Helper for multiply_to_len().
6697 */
6698 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
6699 addq(dest_lo, src1);
6700 adcq(dest_hi, 0);
6701 addq(dest_lo, src2);
6702 adcq(dest_hi, 0);
6703 }
6704
6705 /**
6706 * Multiply 64 bit by 64 bit first loop.
6707 */
6708 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
6709 Register y, Register y_idx, Register z,
6710 Register carry, Register product,
6711 Register idx, Register kdx) {
6712 //
6713 // jlong carry, x[], y[], z[];
6714 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6715 // huge_128 product = y[idx] * x[xstart] + carry;
6716 // z[kdx] = (jlong)product;
6717 // carry = (jlong)(product >>> 64);
6718 // }
6719 // z[xstart] = carry;
6720 //
6721
6722 Label L_first_loop, L_first_loop_exit;
6723 Label L_one_x, L_one_y, L_multiply;
6724
6725 decrementl(xstart);
6726 jcc(Assembler::negative, L_one_x);
6727
6728 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
6729 rorq(x_xstart, 32); // convert big-endian to little-endian
6730
6731 bind(L_first_loop);
6732 decrementl(idx);
6733 jcc(Assembler::negative, L_first_loop_exit);
6734 decrementl(idx);
6735 jcc(Assembler::negative, L_one_y);
6736 movq(y_idx, Address(y, idx, Address::times_4, 0));
6737 rorq(y_idx, 32); // convert big-endian to little-endian
6738 bind(L_multiply);
6739 movq(product, x_xstart);
6740 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
6741 addq(product, carry);
6742 adcq(rdx, 0);
6743 subl(kdx, 2);
6744 movl(Address(z, kdx, Address::times_4, 4), product);
6745 shrq(product, 32);
6746 movl(Address(z, kdx, Address::times_4, 0), product);
6747 movq(carry, rdx);
6748 jmp(L_first_loop);
6749
6750 bind(L_one_y);
6751 movl(y_idx, Address(y, 0));
6752 jmp(L_multiply);
6753
6754 bind(L_one_x);
6755 movl(x_xstart, Address(x, 0));
6756 jmp(L_first_loop);
6757
6758 bind(L_first_loop_exit);
6759 }
6760
6761 /**
6762 * Multiply 64 bit by 64 bit and add 128 bit.
6763 */
6764 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
6765 Register yz_idx, Register idx,
6766 Register carry, Register product, int offset) {
6767 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
6768 // z[kdx] = (jlong)product;
6769
6770 movq(yz_idx, Address(y, idx, Address::times_4, offset));
6771 rorq(yz_idx, 32); // convert big-endian to little-endian
6772 movq(product, x_xstart);
6773 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
6774 movq(yz_idx, Address(z, idx, Address::times_4, offset));
6775 rorq(yz_idx, 32); // convert big-endian to little-endian
6776
6777 add2_with_carry(rdx, product, carry, yz_idx);
6778
6779 movl(Address(z, idx, Address::times_4, offset+4), product);
6780 shrq(product, 32);
6781 movl(Address(z, idx, Address::times_4, offset), product);
6782
6783 }
6784
6785 /**
6786 * Multiply 128 bit by 128 bit. Unrolled inner loop.
6787 */
6788 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
6789 Register yz_idx, Register idx, Register jdx,
6790 Register carry, Register product,
6791 Register carry2) {
6792 // jlong carry, x[], y[], z[];
6793 // int kdx = ystart+1;
6794 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6795 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
6796 // z[kdx+idx+1] = (jlong)product;
6797 // jlong carry2 = (jlong)(product >>> 64);
6798 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
6799 // z[kdx+idx] = (jlong)product;
6800 // carry = (jlong)(product >>> 64);
6801 // }
6802 // idx += 2;
6803 // if (idx > 0) {
6804 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
6805 // z[kdx+idx] = (jlong)product;
6806 // carry = (jlong)(product >>> 64);
6807 // }
6808 //
6809
6810 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6811
6812 movl(jdx, idx);
6813 andl(jdx, 0xFFFFFFFC);
6814 shrl(jdx, 2);
6815
6816 bind(L_third_loop);
6817 subl(jdx, 1);
6818 jcc(Assembler::negative, L_third_loop_exit);
6819 subl(idx, 4);
6820
6821 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
6822 movq(carry2, rdx);
6823
6824 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
6825 movq(carry, rdx);
6826 jmp(L_third_loop);
6827
6828 bind (L_third_loop_exit);
6829
6830 andl (idx, 0x3);
6831 jcc(Assembler::zero, L_post_third_loop_done);
6832
6833 Label L_check_1;
6834 subl(idx, 2);
6835 jcc(Assembler::negative, L_check_1);
6836
6837 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
6838 movq(carry, rdx);
6839
6840 bind (L_check_1);
6841 addl (idx, 0x2);
6842 andl (idx, 0x1);
6843 subl(idx, 1);
6844 jcc(Assembler::negative, L_post_third_loop_done);
6845
6846 movl(yz_idx, Address(y, idx, Address::times_4, 0));
6847 movq(product, x_xstart);
6848 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
6849 movl(yz_idx, Address(z, idx, Address::times_4, 0));
6850
6851 add2_with_carry(rdx, product, yz_idx, carry);
6852
6853 movl(Address(z, idx, Address::times_4, 0), product);
6854 shrq(product, 32);
6855
6856 shlq(rdx, 32);
6857 orq(product, rdx);
6858 movq(carry, product);
6859
6860 bind(L_post_third_loop_done);
6861 }
6862
6863 /**
6864 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
6865 *
6866 */
6867 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
6868 Register carry, Register carry2,
6869 Register idx, Register jdx,
6870 Register yz_idx1, Register yz_idx2,
6871 Register tmp, Register tmp3, Register tmp4) {
6872 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
6873
6874 // jlong carry, x[], y[], z[];
6875 // int kdx = ystart+1;
6876 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6877 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
6878 // jlong carry2 = (jlong)(tmp3 >>> 64);
6879 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
6880 // carry = (jlong)(tmp4 >>> 64);
6881 // z[kdx+idx+1] = (jlong)tmp3;
6882 // z[kdx+idx] = (jlong)tmp4;
6883 // }
6884 // idx += 2;
6885 // if (idx > 0) {
6886 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
6887 // z[kdx+idx] = (jlong)yz_idx1;
6888 // carry = (jlong)(yz_idx1 >>> 64);
6889 // }
6890 //
6891
6892 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6893
6894 movl(jdx, idx);
6895 andl(jdx, 0xFFFFFFFC);
6896 shrl(jdx, 2);
6897
6898 bind(L_third_loop);
6899 subl(jdx, 1);
6900 jcc(Assembler::negative, L_third_loop_exit);
6901 subl(idx, 4);
6902
6903 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
6904 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
6905 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
6906 rorxq(yz_idx2, yz_idx2, 32);
6907
6908 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
6909 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
6910
6911 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
6912 rorxq(yz_idx1, yz_idx1, 32);
6913 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
6914 rorxq(yz_idx2, yz_idx2, 32);
6915
6916 if (VM_Version::supports_adx()) {
6917 adcxq(tmp3, carry);
6918 adoxq(tmp3, yz_idx1);
6919
6920 adcxq(tmp4, tmp);
6921 adoxq(tmp4, yz_idx2);
6922
6923 movl(carry, 0); // does not affect flags
6924 adcxq(carry2, carry);
6925 adoxq(carry2, carry);
6926 } else {
6927 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
6928 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
6929 }
6930 movq(carry, carry2);
6931
6932 movl(Address(z, idx, Address::times_4, 12), tmp3);
6933 shrq(tmp3, 32);
6934 movl(Address(z, idx, Address::times_4, 8), tmp3);
6935
6936 movl(Address(z, idx, Address::times_4, 4), tmp4);
6937 shrq(tmp4, 32);
6938 movl(Address(z, idx, Address::times_4, 0), tmp4);
6939
6940 jmp(L_third_loop);
6941
6942 bind (L_third_loop_exit);
6943
6944 andl (idx, 0x3);
6945 jcc(Assembler::zero, L_post_third_loop_done);
6946
6947 Label L_check_1;
6948 subl(idx, 2);
6949 jcc(Assembler::negative, L_check_1);
6950
6951 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
6952 rorxq(yz_idx1, yz_idx1, 32);
6953 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
6954 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
6955 rorxq(yz_idx2, yz_idx2, 32);
6956
6957 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
6958
6959 movl(Address(z, idx, Address::times_4, 4), tmp3);
6960 shrq(tmp3, 32);
6961 movl(Address(z, idx, Address::times_4, 0), tmp3);
6962 movq(carry, tmp4);
6963
6964 bind (L_check_1);
6965 addl (idx, 0x2);
6966 andl (idx, 0x1);
6967 subl(idx, 1);
6968 jcc(Assembler::negative, L_post_third_loop_done);
6969 movl(tmp4, Address(y, idx, Address::times_4, 0));
6970 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
6971 movl(tmp4, Address(z, idx, Address::times_4, 0));
6972
6973 add2_with_carry(carry2, tmp3, tmp4, carry);
6974
6975 movl(Address(z, idx, Address::times_4, 0), tmp3);
6976 shrq(tmp3, 32);
6977
6978 shlq(carry2, 32);
6979 orq(tmp3, carry2);
6980 movq(carry, tmp3);
6981
6982 bind(L_post_third_loop_done);
6983 }
6984
6985 /**
6986 * Code for BigInteger::multiplyToLen() intrinsic.
6987 *
6988 * rdi: x
6989 * rax: xlen
6990 * rsi: y
6991 * rcx: ylen
6992 * r8: z
6993 * r11: tmp0
6994 * r12: tmp1
6995 * r13: tmp2
6996 * r14: tmp3
6997 * r15: tmp4
6998 * rbx: tmp5
6999 *
7000 */
7001 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7002 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7003 ShortBranchVerifier sbv(this);
7004 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7005
7006 push(tmp0);
7007 push(tmp1);
7008 push(tmp2);
7009 push(tmp3);
7010 push(tmp4);
7011 push(tmp5);
7012
7013 push(xlen);
7014
7015 const Register idx = tmp1;
7016 const Register kdx = tmp2;
7017 const Register xstart = tmp3;
7018
7019 const Register y_idx = tmp4;
7020 const Register carry = tmp5;
7021 const Register product = xlen;
7022 const Register x_xstart = tmp0;
7023
7024 // First Loop.
7025 //
7026 // final static long LONG_MASK = 0xffffffffL;
7027 // int xstart = xlen - 1;
7028 // int ystart = ylen - 1;
7029 // long carry = 0;
7030 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7031 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7032 // z[kdx] = (int)product;
7033 // carry = product >>> 32;
7034 // }
7035 // z[xstart] = (int)carry;
7036 //
7037
7038 movl(idx, ylen); // idx = ylen;
7039 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7040 xorq(carry, carry); // carry = 0;
7041
7042 Label L_done;
7043
7044 movl(xstart, xlen);
7045 decrementl(xstart);
7046 jcc(Assembler::negative, L_done);
7047
7048 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7049
7050 Label L_second_loop;
7051 testl(kdx, kdx);
7052 jcc(Assembler::zero, L_second_loop);
7053
7054 Label L_carry;
7055 subl(kdx, 1);
7056 jcc(Assembler::zero, L_carry);
7057
7058 movl(Address(z, kdx, Address::times_4, 0), carry);
7059 shrq(carry, 32);
7060 subl(kdx, 1);
7061
7062 bind(L_carry);
7063 movl(Address(z, kdx, Address::times_4, 0), carry);
7064
7065 // Second and third (nested) loops.
7066 //
7067 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7068 // carry = 0;
7069 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7070 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7071 // (z[k] & LONG_MASK) + carry;
7072 // z[k] = (int)product;
7073 // carry = product >>> 32;
7074 // }
7075 // z[i] = (int)carry;
7076 // }
7077 //
7078 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7079
7080 const Register jdx = tmp1;
7081
7082 bind(L_second_loop);
7083 xorl(carry, carry); // carry = 0;
7084 movl(jdx, ylen); // j = ystart+1
7085
7086 subl(xstart, 1); // i = xstart-1;
7087 jcc(Assembler::negative, L_done);
7088
7089 push (z);
7090
7091 Label L_last_x;
7092 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7093 subl(xstart, 1); // i = xstart-1;
7094 jcc(Assembler::negative, L_last_x);
7095
7096 if (UseBMI2Instructions) {
7097 movq(rdx, Address(x, xstart, Address::times_4, 0));
7098 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7099 } else {
7100 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7101 rorq(x_xstart, 32); // convert big-endian to little-endian
7102 }
7103
7104 Label L_third_loop_prologue;
7105 bind(L_third_loop_prologue);
7106
7107 push (x);
7108 push (xstart);
7109 push (ylen);
7110
7111
7112 if (UseBMI2Instructions) {
7113 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7114 } else { // !UseBMI2Instructions
7115 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7116 }
7117
7118 pop(ylen);
7119 pop(xlen);
7120 pop(x);
7121 pop(z);
7122
7123 movl(tmp3, xlen);
7124 addl(tmp3, 1);
7125 movl(Address(z, tmp3, Address::times_4, 0), carry);
7126 subl(tmp3, 1);
7127 jccb(Assembler::negative, L_done);
7128
7129 shrq(carry, 32);
7130 movl(Address(z, tmp3, Address::times_4, 0), carry);
7131 jmp(L_second_loop);
7132
7133 // Next infrequent code is moved outside loops.
7134 bind(L_last_x);
7135 if (UseBMI2Instructions) {
7136 movl(rdx, Address(x, 0));
7137 } else {
7138 movl(x_xstart, Address(x, 0));
7139 }
7140 jmp(L_third_loop_prologue);
7141
7142 bind(L_done);
7143
7144 pop(xlen);
7145
7146 pop(tmp5);
7147 pop(tmp4);
7148 pop(tmp3);
7149 pop(tmp2);
7150 pop(tmp1);
7151 pop(tmp0);
7152 }
7153
7154 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7155 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7156 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7157 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7158 Label VECTOR8_TAIL, VECTOR4_TAIL;
7159 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7160 Label SAME_TILL_END, DONE;
7161 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7162
7163 //scale is in rcx in both Win64 and Unix
7164 ShortBranchVerifier sbv(this);
7165
7166 shlq(length);
7167 xorq(result, result);
7168
7169 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7170 VM_Version::supports_avx512vlbw()) {
7171 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7172
7173 cmpq(length, 64);
7174 jcc(Assembler::less, VECTOR32_TAIL);
7175
7176 movq(tmp1, length);
7177 andq(tmp1, 0x3F); // tail count
7178 andq(length, ~(0x3F)); //vector count
7179
7180 bind(VECTOR64_LOOP);
7181 // AVX512 code to compare 64 byte vectors.
7182 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7183 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7184 kortestql(k7, k7);
7185 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7186 addq(result, 64);
7187 subq(length, 64);
7188 jccb(Assembler::notZero, VECTOR64_LOOP);
7189
7190 //bind(VECTOR64_TAIL);
7191 testq(tmp1, tmp1);
7192 jcc(Assembler::zero, SAME_TILL_END);
7193
7194 //bind(VECTOR64_TAIL);
7195 // AVX512 code to compare up to 63 byte vectors.
7196 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7197 shlxq(tmp2, tmp2, tmp1);
7198 notq(tmp2);
7199 kmovql(k3, tmp2);
7200
7201 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7202 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7203
7204 ktestql(k7, k3);
7205 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7206
7207 bind(VECTOR64_NOT_EQUAL);
7208 kmovql(tmp1, k7);
7209 notq(tmp1);
7210 tzcntq(tmp1, tmp1);
7211 addq(result, tmp1);
7212 shrq(result);
7213 jmp(DONE);
7214 bind(VECTOR32_TAIL);
7215 }
7216
7217 cmpq(length, 8);
7218 jcc(Assembler::equal, VECTOR8_LOOP);
7219 jcc(Assembler::less, VECTOR4_TAIL);
7220
7221 if (UseAVX >= 2) {
7222 Label VECTOR16_TAIL, VECTOR32_LOOP;
7223
7224 cmpq(length, 16);
7225 jcc(Assembler::equal, VECTOR16_LOOP);
7226 jcc(Assembler::less, VECTOR8_LOOP);
7227
7228 cmpq(length, 32);
7229 jccb(Assembler::less, VECTOR16_TAIL);
7230
7231 subq(length, 32);
7232 bind(VECTOR32_LOOP);
7233 vmovdqu(rymm0, Address(obja, result));
7234 vmovdqu(rymm1, Address(objb, result));
7235 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7236 vptest(rymm2, rymm2);
7237 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7238 addq(result, 32);
7239 subq(length, 32);
7240 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7241 addq(length, 32);
7242 jcc(Assembler::equal, SAME_TILL_END);
7243 //falling through if less than 32 bytes left //close the branch here.
7244
7245 bind(VECTOR16_TAIL);
7246 cmpq(length, 16);
7247 jccb(Assembler::less, VECTOR8_TAIL);
7248 bind(VECTOR16_LOOP);
7249 movdqu(rymm0, Address(obja, result));
7250 movdqu(rymm1, Address(objb, result));
7251 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7252 ptest(rymm2, rymm2);
7253 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7254 addq(result, 16);
7255 subq(length, 16);
7256 jcc(Assembler::equal, SAME_TILL_END);
7257 //falling through if less than 16 bytes left
7258 } else {//regular intrinsics
7259
7260 cmpq(length, 16);
7261 jccb(Assembler::less, VECTOR8_TAIL);
7262
7263 subq(length, 16);
7264 bind(VECTOR16_LOOP);
7265 movdqu(rymm0, Address(obja, result));
7266 movdqu(rymm1, Address(objb, result));
7267 pxor(rymm0, rymm1);
7268 ptest(rymm0, rymm0);
7269 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7270 addq(result, 16);
7271 subq(length, 16);
7272 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7273 addq(length, 16);
7274 jcc(Assembler::equal, SAME_TILL_END);
7275 //falling through if less than 16 bytes left
7276 }
7277
7278 bind(VECTOR8_TAIL);
7279 cmpq(length, 8);
7280 jccb(Assembler::less, VECTOR4_TAIL);
7281 bind(VECTOR8_LOOP);
7282 movq(tmp1, Address(obja, result));
7283 movq(tmp2, Address(objb, result));
7284 xorq(tmp1, tmp2);
7285 testq(tmp1, tmp1);
7286 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7287 addq(result, 8);
7288 subq(length, 8);
7289 jcc(Assembler::equal, SAME_TILL_END);
7290 //falling through if less than 8 bytes left
7291
7292 bind(VECTOR4_TAIL);
7293 cmpq(length, 4);
7294 jccb(Assembler::less, BYTES_TAIL);
7295 bind(VECTOR4_LOOP);
7296 movl(tmp1, Address(obja, result));
7297 xorl(tmp1, Address(objb, result));
7298 testl(tmp1, tmp1);
7299 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7300 addq(result, 4);
7301 subq(length, 4);
7302 jcc(Assembler::equal, SAME_TILL_END);
7303 //falling through if less than 4 bytes left
7304
7305 bind(BYTES_TAIL);
7306 bind(BYTES_LOOP);
7307 load_unsigned_byte(tmp1, Address(obja, result));
7308 load_unsigned_byte(tmp2, Address(objb, result));
7309 xorl(tmp1, tmp2);
7310 testl(tmp1, tmp1);
7311 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7312 decq(length);
7313 jcc(Assembler::zero, SAME_TILL_END);
7314 incq(result);
7315 load_unsigned_byte(tmp1, Address(obja, result));
7316 load_unsigned_byte(tmp2, Address(objb, result));
7317 xorl(tmp1, tmp2);
7318 testl(tmp1, tmp1);
7319 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7320 decq(length);
7321 jcc(Assembler::zero, SAME_TILL_END);
7322 incq(result);
7323 load_unsigned_byte(tmp1, Address(obja, result));
7324 load_unsigned_byte(tmp2, Address(objb, result));
7325 xorl(tmp1, tmp2);
7326 testl(tmp1, tmp1);
7327 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7328 jmp(SAME_TILL_END);
7329
7330 if (UseAVX >= 2) {
7331 bind(VECTOR32_NOT_EQUAL);
7332 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7333 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7334 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7335 vpmovmskb(tmp1, rymm0);
7336 bsfq(tmp1, tmp1);
7337 addq(result, tmp1);
7338 shrq(result);
7339 jmp(DONE);
7340 }
7341
7342 bind(VECTOR16_NOT_EQUAL);
7343 if (UseAVX >= 2) {
7344 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7345 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7346 pxor(rymm0, rymm2);
7347 } else {
7348 pcmpeqb(rymm2, rymm2);
7349 pxor(rymm0, rymm1);
7350 pcmpeqb(rymm0, rymm1);
7351 pxor(rymm0, rymm2);
7352 }
7353 pmovmskb(tmp1, rymm0);
7354 bsfq(tmp1, tmp1);
7355 addq(result, tmp1);
7356 shrq(result);
7357 jmpb(DONE);
7358
7359 bind(VECTOR8_NOT_EQUAL);
7360 bind(VECTOR4_NOT_EQUAL);
7361 bsfq(tmp1, tmp1);
7362 shrq(tmp1, 3);
7363 addq(result, tmp1);
7364 bind(BYTES_NOT_EQUAL);
7365 shrq(result);
7366 jmpb(DONE);
7367
7368 bind(SAME_TILL_END);
7369 mov64(result, -1);
7370
7371 bind(DONE);
7372 }
7373
7374 //Helper functions for square_to_len()
7375
7376 /**
7377 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7378 * Preserves x and z and modifies rest of the registers.
7379 */
7380 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7381 // Perform square and right shift by 1
7382 // Handle odd xlen case first, then for even xlen do the following
7383 // jlong carry = 0;
7384 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7385 // huge_128 product = x[j:j+1] * x[j:j+1];
7386 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7387 // z[i+2:i+3] = (jlong)(product >>> 1);
7388 // carry = (jlong)product;
7389 // }
7390
7391 xorq(tmp5, tmp5); // carry
7392 xorq(rdxReg, rdxReg);
7393 xorl(tmp1, tmp1); // index for x
7394 xorl(tmp4, tmp4); // index for z
7395
7396 Label L_first_loop, L_first_loop_exit;
7397
7398 testl(xlen, 1);
7399 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7400
7401 // Square and right shift by 1 the odd element using 32 bit multiply
7402 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7403 imulq(raxReg, raxReg);
7404 shrq(raxReg, 1);
7405 adcq(tmp5, 0);
7406 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7407 incrementl(tmp1);
7408 addl(tmp4, 2);
7409
7410 // Square and right shift by 1 the rest using 64 bit multiply
7411 bind(L_first_loop);
7412 cmpptr(tmp1, xlen);
7413 jccb(Assembler::equal, L_first_loop_exit);
7414
7415 // Square
7416 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7417 rorq(raxReg, 32); // convert big-endian to little-endian
7418 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7419
7420 // Right shift by 1 and save carry
7421 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7422 rcrq(rdxReg, 1);
7423 rcrq(raxReg, 1);
7424 adcq(tmp5, 0);
7425
7426 // Store result in z
7427 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7428 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7429
7430 // Update indices for x and z
7431 addl(tmp1, 2);
7432 addl(tmp4, 4);
7433 jmp(L_first_loop);
7434
7435 bind(L_first_loop_exit);
7436 }
7437
7438
7439 /**
7440 * Perform the following multiply add operation using BMI2 instructions
7441 * carry:sum = sum + op1*op2 + carry
7442 * op2 should be in rdx
7443 * op2 is preserved, all other registers are modified
7444 */
7445 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7446 // assert op2 is rdx
7447 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7448 addq(sum, carry);
7449 adcq(tmp2, 0);
7450 addq(sum, op1);
7451 adcq(tmp2, 0);
7452 movq(carry, tmp2);
7453 }
7454
7455 /**
7456 * Perform the following multiply add operation:
7457 * carry:sum = sum + op1*op2 + carry
7458 * Preserves op1, op2 and modifies rest of registers
7459 */
7460 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7461 // rdx:rax = op1 * op2
7462 movq(raxReg, op2);
7463 mulq(op1);
7464
7465 // rdx:rax = sum + carry + rdx:rax
7466 addq(sum, carry);
7467 adcq(rdxReg, 0);
7468 addq(sum, raxReg);
7469 adcq(rdxReg, 0);
7470
7471 // carry:sum = rdx:sum
7472 movq(carry, rdxReg);
7473 }
7474
7475 /**
7476 * Add 64 bit long carry into z[] with carry propagation.
7477 * Preserves z and carry register values and modifies rest of registers.
7478 *
7479 */
7480 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7481 Label L_fourth_loop, L_fourth_loop_exit;
7482
7483 movl(tmp1, 1);
7484 subl(zlen, 2);
7485 addq(Address(z, zlen, Address::times_4, 0), carry);
7486
7487 bind(L_fourth_loop);
7488 jccb(Assembler::carryClear, L_fourth_loop_exit);
7489 subl(zlen, 2);
7490 jccb(Assembler::negative, L_fourth_loop_exit);
7491 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7492 jmp(L_fourth_loop);
7493 bind(L_fourth_loop_exit);
7494 }
7495
7496 /**
7497 * Shift z[] left by 1 bit.
7498 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7499 *
7500 */
7501 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7502
7503 Label L_fifth_loop, L_fifth_loop_exit;
7504
7505 // Fifth loop
7506 // Perform primitiveLeftShift(z, zlen, 1)
7507
7508 const Register prev_carry = tmp1;
7509 const Register new_carry = tmp4;
7510 const Register value = tmp2;
7511 const Register zidx = tmp3;
7512
7513 // int zidx, carry;
7514 // long value;
7515 // carry = 0;
7516 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7517 // (carry:value) = (z[i] << 1) | carry ;
7518 // z[i] = value;
7519 // }
7520
7521 movl(zidx, zlen);
7522 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7523
7524 bind(L_fifth_loop);
7525 decl(zidx); // Use decl to preserve carry flag
7526 decl(zidx);
7527 jccb(Assembler::negative, L_fifth_loop_exit);
7528
7529 if (UseBMI2Instructions) {
7530 movq(value, Address(z, zidx, Address::times_4, 0));
7531 rclq(value, 1);
7532 rorxq(value, value, 32);
7533 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7534 }
7535 else {
7536 // clear new_carry
7537 xorl(new_carry, new_carry);
7538
7539 // Shift z[i] by 1, or in previous carry and save new carry
7540 movq(value, Address(z, zidx, Address::times_4, 0));
7541 shlq(value, 1);
7542 adcl(new_carry, 0);
7543
7544 orq(value, prev_carry);
7545 rorq(value, 0x20);
7546 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7547
7548 // Set previous carry = new carry
7549 movl(prev_carry, new_carry);
7550 }
7551 jmp(L_fifth_loop);
7552
7553 bind(L_fifth_loop_exit);
7554 }
7555
7556
7557 /**
7558 * Code for BigInteger::squareToLen() intrinsic
7559 *
7560 * rdi: x
7561 * rsi: len
7562 * r8: z
7563 * rcx: zlen
7564 * r12: tmp1
7565 * r13: tmp2
7566 * r14: tmp3
7567 * r15: tmp4
7568 * rbx: tmp5
7569 *
7570 */
7571 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7572
7573 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
7574 push(tmp1);
7575 push(tmp2);
7576 push(tmp3);
7577 push(tmp4);
7578 push(tmp5);
7579
7580 // First loop
7581 // Store the squares, right shifted one bit (i.e., divided by 2).
7582 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7583
7584 // Add in off-diagonal sums.
7585 //
7586 // Second, third (nested) and fourth loops.
7587 // zlen +=2;
7588 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7589 // carry = 0;
7590 // long op2 = x[xidx:xidx+1];
7591 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7592 // k -= 2;
7593 // long op1 = x[j:j+1];
7594 // long sum = z[k:k+1];
7595 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7596 // z[k:k+1] = sum;
7597 // }
7598 // add_one_64(z, k, carry, tmp_regs);
7599 // }
7600
7601 const Register carry = tmp5;
7602 const Register sum = tmp3;
7603 const Register op1 = tmp4;
7604 Register op2 = tmp2;
7605
7606 push(zlen);
7607 push(len);
7608 addl(zlen,2);
7609 bind(L_second_loop);
7610 xorq(carry, carry);
7611 subl(zlen, 4);
7612 subl(len, 2);
7613 push(zlen);
7614 push(len);
7615 cmpl(len, 0);
7616 jccb(Assembler::lessEqual, L_second_loop_exit);
7617
7618 // Multiply an array by one 64 bit long.
7619 if (UseBMI2Instructions) {
7620 op2 = rdxReg;
7621 movq(op2, Address(x, len, Address::times_4, 0));
7622 rorxq(op2, op2, 32);
7623 }
7624 else {
7625 movq(op2, Address(x, len, Address::times_4, 0));
7626 rorq(op2, 32);
7627 }
7628
7629 bind(L_third_loop);
7630 decrementl(len);
7631 jccb(Assembler::negative, L_third_loop_exit);
7632 decrementl(len);
7633 jccb(Assembler::negative, L_last_x);
7634
7635 movq(op1, Address(x, len, Address::times_4, 0));
7636 rorq(op1, 32);
7637
7638 bind(L_multiply);
7639 subl(zlen, 2);
7640 movq(sum, Address(z, zlen, Address::times_4, 0));
7641
7642 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
7643 if (UseBMI2Instructions) {
7644 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
7645 }
7646 else {
7647 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7648 }
7649
7650 movq(Address(z, zlen, Address::times_4, 0), sum);
7651
7652 jmp(L_third_loop);
7653 bind(L_third_loop_exit);
7654
7655 // Fourth loop
7656 // Add 64 bit long carry into z with carry propagation.
7657 // Uses offsetted zlen.
7658 add_one_64(z, zlen, carry, tmp1);
7659
7660 pop(len);
7661 pop(zlen);
7662 jmp(L_second_loop);
7663
7664 // Next infrequent code is moved outside loops.
7665 bind(L_last_x);
7666 movl(op1, Address(x, 0));
7667 jmp(L_multiply);
7668
7669 bind(L_second_loop_exit);
7670 pop(len);
7671 pop(zlen);
7672 pop(len);
7673 pop(zlen);
7674
7675 // Fifth loop
7676 // Shift z left 1 bit.
7677 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
7678
7679 // z[zlen-1] |= x[len-1] & 1;
7680 movl(tmp3, Address(x, len, Address::times_4, -4));
7681 andl(tmp3, 1);
7682 orl(Address(z, zlen, Address::times_4, -4), tmp3);
7683
7684 pop(tmp5);
7685 pop(tmp4);
7686 pop(tmp3);
7687 pop(tmp2);
7688 pop(tmp1);
7689 }
7690
7691 /**
7692 * Helper function for mul_add()
7693 * Multiply the in[] by int k and add to out[] starting at offset offs using
7694 * 128 bit by 32 bit multiply and return the carry in tmp5.
7695 * Only quad int aligned length of in[] is operated on in this function.
7696 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
7697 * This function preserves out, in and k registers.
7698 * len and offset point to the appropriate index in "in" & "out" correspondingly
7699 * tmp5 has the carry.
7700 * other registers are temporary and are modified.
7701 *
7702 */
7703 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
7704 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
7705 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7706
7707 Label L_first_loop, L_first_loop_exit;
7708
7709 movl(tmp1, len);
7710 shrl(tmp1, 2);
7711
7712 bind(L_first_loop);
7713 subl(tmp1, 1);
7714 jccb(Assembler::negative, L_first_loop_exit);
7715
7716 subl(len, 4);
7717 subl(offset, 4);
7718
7719 Register op2 = tmp2;
7720 const Register sum = tmp3;
7721 const Register op1 = tmp4;
7722 const Register carry = tmp5;
7723
7724 if (UseBMI2Instructions) {
7725 op2 = rdxReg;
7726 }
7727
7728 movq(op1, Address(in, len, Address::times_4, 8));
7729 rorq(op1, 32);
7730 movq(sum, Address(out, offset, Address::times_4, 8));
7731 rorq(sum, 32);
7732 if (UseBMI2Instructions) {
7733 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7734 }
7735 else {
7736 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7737 }
7738 // Store back in big endian from little endian
7739 rorq(sum, 0x20);
7740 movq(Address(out, offset, Address::times_4, 8), sum);
7741
7742 movq(op1, Address(in, len, Address::times_4, 0));
7743 rorq(op1, 32);
7744 movq(sum, Address(out, offset, Address::times_4, 0));
7745 rorq(sum, 32);
7746 if (UseBMI2Instructions) {
7747 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7748 }
7749 else {
7750 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7751 }
7752 // Store back in big endian from little endian
7753 rorq(sum, 0x20);
7754 movq(Address(out, offset, Address::times_4, 0), sum);
7755
7756 jmp(L_first_loop);
7757 bind(L_first_loop_exit);
7758 }
7759
7760 /**
7761 * Code for BigInteger::mulAdd() intrinsic
7762 *
7763 * rdi: out
7764 * rsi: in
7765 * r11: offs (out.length - offset)
7766 * rcx: len
7767 * r8: k
7768 * r12: tmp1
7769 * r13: tmp2
7770 * r14: tmp3
7771 * r15: tmp4
7772 * rbx: tmp5
7773 * Multiply the in[] by word k and add to out[], return the carry in rax
7774 */
7775 void MacroAssembler::mul_add(Register out, Register in, Register offs,
7776 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
7777 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7778
7779 Label L_carry, L_last_in, L_done;
7780
7781 // carry = 0;
7782 // for (int j=len-1; j >= 0; j--) {
7783 // long product = (in[j] & LONG_MASK) * kLong +
7784 // (out[offs] & LONG_MASK) + carry;
7785 // out[offs--] = (int)product;
7786 // carry = product >>> 32;
7787 // }
7788 //
7789 push(tmp1);
7790 push(tmp2);
7791 push(tmp3);
7792 push(tmp4);
7793 push(tmp5);
7794
7795 Register op2 = tmp2;
7796 const Register sum = tmp3;
7797 const Register op1 = tmp4;
7798 const Register carry = tmp5;
7799
7800 if (UseBMI2Instructions) {
7801 op2 = rdxReg;
7802 movl(op2, k);
7803 }
7804 else {
7805 movl(op2, k);
7806 }
7807
7808 xorq(carry, carry);
7809
7810 //First loop
7811
7812 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
7813 //The carry is in tmp5
7814 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
7815
7816 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
7817 decrementl(len);
7818 jccb(Assembler::negative, L_carry);
7819 decrementl(len);
7820 jccb(Assembler::negative, L_last_in);
7821
7822 movq(op1, Address(in, len, Address::times_4, 0));
7823 rorq(op1, 32);
7824
7825 subl(offs, 2);
7826 movq(sum, Address(out, offs, Address::times_4, 0));
7827 rorq(sum, 32);
7828
7829 if (UseBMI2Instructions) {
7830 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7831 }
7832 else {
7833 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7834 }
7835
7836 // Store back in big endian from little endian
7837 rorq(sum, 0x20);
7838 movq(Address(out, offs, Address::times_4, 0), sum);
7839
7840 testl(len, len);
7841 jccb(Assembler::zero, L_carry);
7842
7843 //Multiply the last in[] entry, if any
7844 bind(L_last_in);
7845 movl(op1, Address(in, 0));
7846 movl(sum, Address(out, offs, Address::times_4, -4));
7847
7848 movl(raxReg, k);
7849 mull(op1); //tmp4 * eax -> edx:eax
7850 addl(sum, carry);
7851 adcl(rdxReg, 0);
7852 addl(sum, raxReg);
7853 adcl(rdxReg, 0);
7854 movl(carry, rdxReg);
7855
7856 movl(Address(out, offs, Address::times_4, -4), sum);
7857
7858 bind(L_carry);
7859 //return tmp5/carry as carry in rax
7860 movl(rax, carry);
7861
7862 bind(L_done);
7863 pop(tmp5);
7864 pop(tmp4);
7865 pop(tmp3);
7866 pop(tmp2);
7867 pop(tmp1);
7868 }
7869 #endif
7870
7871 /**
7872 * Emits code to update CRC-32 with a byte value according to constants in table
7873 *
7874 * @param [in,out]crc Register containing the crc.
7875 * @param [in]val Register containing the byte to fold into the CRC.
7876 * @param [in]table Register containing the table of crc constants.
7877 *
7878 * uint32_t crc;
7879 * val = crc_table[(val ^ crc) & 0xFF];
7880 * crc = val ^ (crc >> 8);
7881 *
7882 */
7883 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
7884 xorl(val, crc);
7885 andl(val, 0xFF);
7886 shrl(crc, 8); // unsigned shift
7887 xorl(crc, Address(table, val, Address::times_4, 0));
7888 }
7889
7890 /**
7891 * Fold 128-bit data chunk
7892 */
7893 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
7894 if (UseAVX > 0) {
7895 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
7896 vpclmulldq(xcrc, xK, xcrc); // [63:0]
7897 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
7898 pxor(xcrc, xtmp);
7899 } else {
7900 movdqa(xtmp, xcrc);
7901 pclmulhdq(xtmp, xK); // [123:64]
7902 pclmulldq(xcrc, xK); // [63:0]
7903 pxor(xcrc, xtmp);
7904 movdqu(xtmp, Address(buf, offset));
7905 pxor(xcrc, xtmp);
7906 }
7907 }
7908
7909 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
7910 if (UseAVX > 0) {
7911 vpclmulhdq(xtmp, xK, xcrc);
7912 vpclmulldq(xcrc, xK, xcrc);
7913 pxor(xcrc, xbuf);
7914 pxor(xcrc, xtmp);
7915 } else {
7916 movdqa(xtmp, xcrc);
7917 pclmulhdq(xtmp, xK);
7918 pclmulldq(xcrc, xK);
7919 pxor(xcrc, xbuf);
7920 pxor(xcrc, xtmp);
7921 }
7922 }
7923
7924 /**
7925 * 8-bit folds to compute 32-bit CRC
7926 *
7927 * uint64_t xcrc;
7928 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
7929 */
7930 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
7931 movdl(tmp, xcrc);
7932 andl(tmp, 0xFF);
7933 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
7934 psrldq(xcrc, 1); // unsigned shift one byte
7935 pxor(xcrc, xtmp);
7936 }
7937
7938 /**
7939 * uint32_t crc;
7940 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
7941 */
7942 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
7943 movl(tmp, crc);
7944 andl(tmp, 0xFF);
7945 shrl(crc, 8);
7946 xorl(crc, Address(table, tmp, Address::times_4, 0));
7947 }
7948
7949 /**
7950 * @param crc register containing existing CRC (32-bit)
7951 * @param buf register pointing to input byte buffer (byte*)
7952 * @param len register containing number of bytes
7953 * @param table register that will contain address of CRC table
7954 * @param tmp scratch register
7955 */
7956 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
7957 assert_different_registers(crc, buf, len, table, tmp, rax);
7958
7959 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7960 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7961
7962 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
7963 // context for the registers used, where all instructions below are using 128-bit mode
7964 // On EVEX without VL and BW, these instructions will all be AVX.
7965 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
7966 notl(crc); // ~crc
7967 cmpl(len, 16);
7968 jcc(Assembler::less, L_tail);
7969
7970 // Align buffer to 16 bytes
7971 movl(tmp, buf);
7972 andl(tmp, 0xF);
7973 jccb(Assembler::zero, L_aligned);
7974 subl(tmp, 16);
7975 addl(len, tmp);
7976
7977 align(4);
7978 BIND(L_align_loop);
7979 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7980 update_byte_crc32(crc, rax, table);
7981 increment(buf);
7982 incrementl(tmp);
7983 jccb(Assembler::less, L_align_loop);
7984
7985 BIND(L_aligned);
7986 movl(tmp, len); // save
7987 shrl(len, 4);
7988 jcc(Assembler::zero, L_tail_restore);
7989
7990 // Fold crc into first bytes of vector
7991 movdqa(xmm1, Address(buf, 0));
7992 movdl(rax, xmm1);
7993 xorl(crc, rax);
7994 if (VM_Version::supports_sse4_1()) {
7995 pinsrd(xmm1, crc, 0);
7996 } else {
7997 pinsrw(xmm1, crc, 0);
7998 shrl(crc, 16);
7999 pinsrw(xmm1, crc, 1);
8000 }
8001 addptr(buf, 16);
8002 subl(len, 4); // len > 0
8003 jcc(Assembler::less, L_fold_tail);
8004
8005 movdqa(xmm2, Address(buf, 0));
8006 movdqa(xmm3, Address(buf, 16));
8007 movdqa(xmm4, Address(buf, 32));
8008 addptr(buf, 48);
8009 subl(len, 3);
8010 jcc(Assembler::lessEqual, L_fold_512b);
8011
8012 // Fold total 512 bits of polynomial on each iteration,
8013 // 128 bits per each of 4 parallel streams.
8014 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8015
8016 align32();
8017 BIND(L_fold_512b_loop);
8018 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8019 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8020 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8021 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8022 addptr(buf, 64);
8023 subl(len, 4);
8024 jcc(Assembler::greater, L_fold_512b_loop);
8025
8026 // Fold 512 bits to 128 bits.
8027 BIND(L_fold_512b);
8028 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8029 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8030 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8031 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8032
8033 // Fold the rest of 128 bits data chunks
8034 BIND(L_fold_tail);
8035 addl(len, 3);
8036 jccb(Assembler::lessEqual, L_fold_128b);
8037 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8038
8039 BIND(L_fold_tail_loop);
8040 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8041 addptr(buf, 16);
8042 decrementl(len);
8043 jccb(Assembler::greater, L_fold_tail_loop);
8044
8045 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8046 BIND(L_fold_128b);
8047 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8048 if (UseAVX > 0) {
8049 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8050 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8051 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8052 } else {
8053 movdqa(xmm2, xmm0);
8054 pclmulqdq(xmm2, xmm1, 0x1);
8055 movdqa(xmm3, xmm0);
8056 pand(xmm3, xmm2);
8057 pclmulqdq(xmm0, xmm3, 0x1);
8058 }
8059 psrldq(xmm1, 8);
8060 psrldq(xmm2, 4);
8061 pxor(xmm0, xmm1);
8062 pxor(xmm0, xmm2);
8063
8064 // 8 8-bit folds to compute 32-bit CRC.
8065 for (int j = 0; j < 4; j++) {
8066 fold_8bit_crc32(xmm0, table, xmm1, rax);
8067 }
8068 movdl(crc, xmm0); // mov 32 bits to general register
8069 for (int j = 0; j < 4; j++) {
8070 fold_8bit_crc32(crc, table, rax);
8071 }
8072
8073 BIND(L_tail_restore);
8074 movl(len, tmp); // restore
8075 BIND(L_tail);
8076 andl(len, 0xf);
8077 jccb(Assembler::zero, L_exit);
8078
8079 // Fold the rest of bytes
8080 align(4);
8081 BIND(L_tail_loop);
8082 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8083 update_byte_crc32(crc, rax, table);
8084 increment(buf);
8085 decrementl(len);
8086 jccb(Assembler::greater, L_tail_loop);
8087
8088 BIND(L_exit);
8089 notl(crc); // ~c
8090 }
8091
8092 #ifdef _LP64
8093 // Helper function for AVX 512 CRC32
8094 // Fold 512-bit data chunks
8095 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8096 Register pos, int offset) {
8097 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8098 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8099 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8100 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8101 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8102 }
8103
8104 // Helper function for AVX 512 CRC32
8105 // Compute CRC32 for < 256B buffers
8106 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8107 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8108 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8109
8110 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8111 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8112 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8113
8114 // check if there is enough buffer to be able to fold 16B at a time
8115 cmpl(len, 32);
8116 jcc(Assembler::less, L_less_than_32);
8117
8118 // if there is, load the constants
8119 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8120 movdl(xmm0, crc); // get the initial crc value
8121 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8122 pxor(xmm7, xmm0);
8123
8124 // update the buffer pointer
8125 addl(pos, 16);
8126 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8127 subl(len, 32);
8128 jmp(L_16B_reduction_loop);
8129
8130 bind(L_less_than_32);
8131 //mov initial crc to the return value. this is necessary for zero - length buffers.
8132 movl(rax, crc);
8133 testl(len, len);
8134 jcc(Assembler::equal, L_cleanup);
8135
8136 movdl(xmm0, crc); //get the initial crc value
8137
8138 cmpl(len, 16);
8139 jcc(Assembler::equal, L_exact_16_left);
8140 jcc(Assembler::less, L_less_than_16_left);
8141
8142 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8143 pxor(xmm7, xmm0); //xor the initial crc value
8144 addl(pos, 16);
8145 subl(len, 16);
8146 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8147 jmp(L_get_last_two_xmms);
8148
8149 bind(L_less_than_16_left);
8150 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8151 pxor(xmm1, xmm1);
8152 movptr(tmp1, rsp);
8153 movdqu(Address(tmp1, 0 * 16), xmm1);
8154
8155 cmpl(len, 4);
8156 jcc(Assembler::less, L_only_less_than_4);
8157
8158 //backup the counter value
8159 movl(tmp2, len);
8160 cmpl(len, 8);
8161 jcc(Assembler::less, L_less_than_8_left);
8162
8163 //load 8 Bytes
8164 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8165 movq(Address(tmp1, 0 * 16), rax);
8166 addptr(tmp1, 8);
8167 subl(len, 8);
8168 addl(pos, 8);
8169
8170 bind(L_less_than_8_left);
8171 cmpl(len, 4);
8172 jcc(Assembler::less, L_less_than_4_left);
8173
8174 //load 4 Bytes
8175 movl(rax, Address(buf, pos, Address::times_1, 0));
8176 movl(Address(tmp1, 0 * 16), rax);
8177 addptr(tmp1, 4);
8178 subl(len, 4);
8179 addl(pos, 4);
8180
8181 bind(L_less_than_4_left);
8182 cmpl(len, 2);
8183 jcc(Assembler::less, L_less_than_2_left);
8184
8185 // load 2 Bytes
8186 movw(rax, Address(buf, pos, Address::times_1, 0));
8187 movl(Address(tmp1, 0 * 16), rax);
8188 addptr(tmp1, 2);
8189 subl(len, 2);
8190 addl(pos, 2);
8191
8192 bind(L_less_than_2_left);
8193 cmpl(len, 1);
8194 jcc(Assembler::less, L_zero_left);
8195
8196 // load 1 Byte
8197 movb(rax, Address(buf, pos, Address::times_1, 0));
8198 movb(Address(tmp1, 0 * 16), rax);
8199
8200 bind(L_zero_left);
8201 movdqu(xmm7, Address(rsp, 0));
8202 pxor(xmm7, xmm0); //xor the initial crc value
8203
8204 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8205 movdqu(xmm0, Address(rax, tmp2));
8206 pshufb(xmm7, xmm0);
8207 jmp(L_128_done);
8208
8209 bind(L_exact_16_left);
8210 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8211 pxor(xmm7, xmm0); //xor the initial crc value
8212 jmp(L_128_done);
8213
8214 bind(L_only_less_than_4);
8215 cmpl(len, 3);
8216 jcc(Assembler::less, L_only_less_than_3);
8217
8218 // load 3 Bytes
8219 movb(rax, Address(buf, pos, Address::times_1, 0));
8220 movb(Address(tmp1, 0), rax);
8221
8222 movb(rax, Address(buf, pos, Address::times_1, 1));
8223 movb(Address(tmp1, 1), rax);
8224
8225 movb(rax, Address(buf, pos, Address::times_1, 2));
8226 movb(Address(tmp1, 2), rax);
8227
8228 movdqu(xmm7, Address(rsp, 0));
8229 pxor(xmm7, xmm0); //xor the initial crc value
8230
8231 pslldq(xmm7, 0x5);
8232 jmp(L_barrett);
8233 bind(L_only_less_than_3);
8234 cmpl(len, 2);
8235 jcc(Assembler::less, L_only_less_than_2);
8236
8237 // load 2 Bytes
8238 movb(rax, Address(buf, pos, Address::times_1, 0));
8239 movb(Address(tmp1, 0), rax);
8240
8241 movb(rax, Address(buf, pos, Address::times_1, 1));
8242 movb(Address(tmp1, 1), rax);
8243
8244 movdqu(xmm7, Address(rsp, 0));
8245 pxor(xmm7, xmm0); //xor the initial crc value
8246
8247 pslldq(xmm7, 0x6);
8248 jmp(L_barrett);
8249
8250 bind(L_only_less_than_2);
8251 //load 1 Byte
8252 movb(rax, Address(buf, pos, Address::times_1, 0));
8253 movb(Address(tmp1, 0), rax);
8254
8255 movdqu(xmm7, Address(rsp, 0));
8256 pxor(xmm7, xmm0); //xor the initial crc value
8257
8258 pslldq(xmm7, 0x7);
8259 }
8260
8261 /**
8262 * Compute CRC32 using AVX512 instructions
8263 * param crc register containing existing CRC (32-bit)
8264 * param buf register pointing to input byte buffer (byte*)
8265 * param len register containing number of bytes
8266 * param table address of crc or crc32c table
8267 * param tmp1 scratch register
8268 * param tmp2 scratch register
8269 * return rax result register
8270 *
8271 * This routine is identical for crc32c with the exception of the precomputed constant
8272 * table which will be passed as the table argument. The calculation steps are
8273 * the same for both variants.
8274 */
8275 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8276 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8277
8278 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8279 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8280 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8281 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8282 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8283
8284 const Register pos = r12;
8285 push(r12);
8286 subptr(rsp, 16 * 2 + 8);
8287
8288 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8289 // context for the registers used, where all instructions below are using 128-bit mode
8290 // On EVEX without VL and BW, these instructions will all be AVX.
8291 movl(pos, 0);
8292
8293 // check if smaller than 256B
8294 cmpl(len, 256);
8295 jcc(Assembler::less, L_less_than_256);
8296
8297 // load the initial crc value
8298 movdl(xmm10, crc);
8299
8300 // receive the initial 64B data, xor the initial crc value
8301 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8302 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8303 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8304 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8305
8306 subl(len, 256);
8307 cmpl(len, 256);
8308 jcc(Assembler::less, L_fold_128_B_loop);
8309
8310 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8311 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8312 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8313 subl(len, 256);
8314
8315 bind(L_fold_256_B_loop);
8316 addl(pos, 256);
8317 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8318 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8319 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8320 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8321
8322 subl(len, 256);
8323 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8324
8325 // Fold 256 into 128
8326 addl(pos, 256);
8327 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8328 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8329 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8330
8331 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8332 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8333 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8334
8335 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8336 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8337
8338 addl(len, 128);
8339 jmp(L_fold_128_B_register);
8340
8341 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8342 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8343
8344 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8345 bind(L_fold_128_B_loop);
8346 addl(pos, 128);
8347 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8348 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8349
8350 subl(len, 128);
8351 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8352
8353 addl(pos, 128);
8354
8355 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8356 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8357 bind(L_fold_128_B_register);
8358 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8359 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8360 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8361 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8362 // save last that has no multiplicand
8363 vextracti64x2(xmm7, xmm4, 3);
8364
8365 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8366 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8367 // Needed later in reduction loop
8368 movdqu(xmm10, Address(table, 1 * 16));
8369 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8370 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8371
8372 // Swap 1,0,3,2 - 01 00 11 10
8373 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8374 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8375 vextracti128(xmm5, xmm8, 1);
8376 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8377
8378 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8379 // instead of a cmp instruction, we use the negative flag with the jl instruction
8380 addl(len, 128 - 16);
8381 jcc(Assembler::less, L_final_reduction_for_128);
8382
8383 bind(L_16B_reduction_loop);
8384 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8385 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8386 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8387 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8388 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8389 addl(pos, 16);
8390 subl(len, 16);
8391 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8392
8393 bind(L_final_reduction_for_128);
8394 addl(len, 16);
8395 jcc(Assembler::equal, L_128_done);
8396
8397 bind(L_get_last_two_xmms);
8398 movdqu(xmm2, xmm7);
8399 addl(pos, len);
8400 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8401 subl(pos, len);
8402
8403 // get rid of the extra data that was loaded before
8404 // load the shift constant
8405 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8406 movdqu(xmm0, Address(rax, len));
8407 addl(rax, len);
8408
8409 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8410 //Change mask to 512
8411 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8412 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8413
8414 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8415 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8416 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8417 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8418 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8419
8420 bind(L_128_done);
8421 // compute crc of a 128-bit value
8422 movdqu(xmm10, Address(table, 3 * 16));
8423 movdqu(xmm0, xmm7);
8424
8425 // 64b fold
8426 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8427 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8428 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8429
8430 // 32b fold
8431 movdqu(xmm0, xmm7);
8432 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8433 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8434 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8435 jmp(L_barrett);
8436
8437 bind(L_less_than_256);
8438 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8439
8440 //barrett reduction
8441 bind(L_barrett);
8442 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8443 movdqu(xmm1, xmm7);
8444 movdqu(xmm2, xmm7);
8445 movdqu(xmm10, Address(table, 4 * 16));
8446
8447 pclmulqdq(xmm7, xmm10, 0x0);
8448 pxor(xmm7, xmm2);
8449 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8450 movdqu(xmm2, xmm7);
8451 pclmulqdq(xmm7, xmm10, 0x10);
8452 pxor(xmm7, xmm2);
8453 pxor(xmm7, xmm1);
8454 pextrd(crc, xmm7, 2);
8455
8456 bind(L_cleanup);
8457 addptr(rsp, 16 * 2 + 8);
8458 pop(r12);
8459 }
8460
8461 // S. Gueron / Information Processing Letters 112 (2012) 184
8462 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8463 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8464 // Output: the 64-bit carry-less product of B * CONST
8465 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8466 Register tmp1, Register tmp2, Register tmp3) {
8467 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8468 if (n > 0) {
8469 addq(tmp3, n * 256 * 8);
8470 }
8471 // Q1 = TABLEExt[n][B & 0xFF];
8472 movl(tmp1, in);
8473 andl(tmp1, 0x000000FF);
8474 shll(tmp1, 3);
8475 addq(tmp1, tmp3);
8476 movq(tmp1, Address(tmp1, 0));
8477
8478 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8479 movl(tmp2, in);
8480 shrl(tmp2, 8);
8481 andl(tmp2, 0x000000FF);
8482 shll(tmp2, 3);
8483 addq(tmp2, tmp3);
8484 movq(tmp2, Address(tmp2, 0));
8485
8486 shlq(tmp2, 8);
8487 xorq(tmp1, tmp2);
8488
8489 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8490 movl(tmp2, in);
8491 shrl(tmp2, 16);
8492 andl(tmp2, 0x000000FF);
8493 shll(tmp2, 3);
8494 addq(tmp2, tmp3);
8495 movq(tmp2, Address(tmp2, 0));
8496
8497 shlq(tmp2, 16);
8498 xorq(tmp1, tmp2);
8499
8500 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8501 shrl(in, 24);
8502 andl(in, 0x000000FF);
8503 shll(in, 3);
8504 addq(in, tmp3);
8505 movq(in, Address(in, 0));
8506
8507 shlq(in, 24);
8508 xorq(in, tmp1);
8509 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8510 }
8511
8512 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8513 Register in_out,
8514 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8515 XMMRegister w_xtmp2,
8516 Register tmp1,
8517 Register n_tmp2, Register n_tmp3) {
8518 if (is_pclmulqdq_supported) {
8519 movdl(w_xtmp1, in_out); // modified blindly
8520
8521 movl(tmp1, const_or_pre_comp_const_index);
8522 movdl(w_xtmp2, tmp1);
8523 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8524
8525 movdq(in_out, w_xtmp1);
8526 } else {
8527 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8528 }
8529 }
8530
8531 // Recombination Alternative 2: No bit-reflections
8532 // T1 = (CRC_A * U1) << 1
8533 // T2 = (CRC_B * U2) << 1
8534 // C1 = T1 >> 32
8535 // C2 = T2 >> 32
8536 // T1 = T1 & 0xFFFFFFFF
8537 // T2 = T2 & 0xFFFFFFFF
8538 // T1 = CRC32(0, T1)
8539 // T2 = CRC32(0, T2)
8540 // C1 = C1 ^ T1
8541 // C2 = C2 ^ T2
8542 // CRC = C1 ^ C2 ^ CRC_C
8543 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8544 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8545 Register tmp1, Register tmp2,
8546 Register n_tmp3) {
8547 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8548 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8549 shlq(in_out, 1);
8550 movl(tmp1, in_out);
8551 shrq(in_out, 32);
8552 xorl(tmp2, tmp2);
8553 crc32(tmp2, tmp1, 4);
8554 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8555 shlq(in1, 1);
8556 movl(tmp1, in1);
8557 shrq(in1, 32);
8558 xorl(tmp2, tmp2);
8559 crc32(tmp2, tmp1, 4);
8560 xorl(in1, tmp2);
8561 xorl(in_out, in1);
8562 xorl(in_out, in2);
8563 }
8564
8565 // Set N to predefined value
8566 // Subtract from a length of a buffer
8567 // execute in a loop:
8568 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8569 // for i = 1 to N do
8570 // CRC_A = CRC32(CRC_A, A[i])
8571 // CRC_B = CRC32(CRC_B, B[i])
8572 // CRC_C = CRC32(CRC_C, C[i])
8573 // end for
8574 // Recombine
8575 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8576 Register in_out1, Register in_out2, Register in_out3,
8577 Register tmp1, Register tmp2, Register tmp3,
8578 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8579 Register tmp4, Register tmp5,
8580 Register n_tmp6) {
8581 Label L_processPartitions;
8582 Label L_processPartition;
8583 Label L_exit;
8584
8585 bind(L_processPartitions);
8586 cmpl(in_out1, 3 * size);
8587 jcc(Assembler::less, L_exit);
8588 xorl(tmp1, tmp1);
8589 xorl(tmp2, tmp2);
8590 movq(tmp3, in_out2);
8591 addq(tmp3, size);
8592
8593 bind(L_processPartition);
8594 crc32(in_out3, Address(in_out2, 0), 8);
8595 crc32(tmp1, Address(in_out2, size), 8);
8596 crc32(tmp2, Address(in_out2, size * 2), 8);
8597 addq(in_out2, 8);
8598 cmpq(in_out2, tmp3);
8599 jcc(Assembler::less, L_processPartition);
8600 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8601 w_xtmp1, w_xtmp2, w_xtmp3,
8602 tmp4, tmp5,
8603 n_tmp6);
8604 addq(in_out2, 2 * size);
8605 subl(in_out1, 3 * size);
8606 jmp(L_processPartitions);
8607
8608 bind(L_exit);
8609 }
8610 #else
8611 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
8612 Register tmp1, Register tmp2, Register tmp3,
8613 XMMRegister xtmp1, XMMRegister xtmp2) {
8614 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8615 if (n > 0) {
8616 addl(tmp3, n * 256 * 8);
8617 }
8618 // Q1 = TABLEExt[n][B & 0xFF];
8619 movl(tmp1, in_out);
8620 andl(tmp1, 0x000000FF);
8621 shll(tmp1, 3);
8622 addl(tmp1, tmp3);
8623 movq(xtmp1, Address(tmp1, 0));
8624
8625 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8626 movl(tmp2, in_out);
8627 shrl(tmp2, 8);
8628 andl(tmp2, 0x000000FF);
8629 shll(tmp2, 3);
8630 addl(tmp2, tmp3);
8631 movq(xtmp2, Address(tmp2, 0));
8632
8633 psllq(xtmp2, 8);
8634 pxor(xtmp1, xtmp2);
8635
8636 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8637 movl(tmp2, in_out);
8638 shrl(tmp2, 16);
8639 andl(tmp2, 0x000000FF);
8640 shll(tmp2, 3);
8641 addl(tmp2, tmp3);
8642 movq(xtmp2, Address(tmp2, 0));
8643
8644 psllq(xtmp2, 16);
8645 pxor(xtmp1, xtmp2);
8646
8647 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8648 shrl(in_out, 24);
8649 andl(in_out, 0x000000FF);
8650 shll(in_out, 3);
8651 addl(in_out, tmp3);
8652 movq(xtmp2, Address(in_out, 0));
8653
8654 psllq(xtmp2, 24);
8655 pxor(xtmp1, xtmp2); // Result in CXMM
8656 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8657 }
8658
8659 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8660 Register in_out,
8661 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8662 XMMRegister w_xtmp2,
8663 Register tmp1,
8664 Register n_tmp2, Register n_tmp3) {
8665 if (is_pclmulqdq_supported) {
8666 movdl(w_xtmp1, in_out);
8667
8668 movl(tmp1, const_or_pre_comp_const_index);
8669 movdl(w_xtmp2, tmp1);
8670 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8671 // Keep result in XMM since GPR is 32 bit in length
8672 } else {
8673 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
8674 }
8675 }
8676
8677 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8678 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8679 Register tmp1, Register tmp2,
8680 Register n_tmp3) {
8681 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8682 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8683
8684 psllq(w_xtmp1, 1);
8685 movdl(tmp1, w_xtmp1);
8686 psrlq(w_xtmp1, 32);
8687 movdl(in_out, w_xtmp1);
8688
8689 xorl(tmp2, tmp2);
8690 crc32(tmp2, tmp1, 4);
8691 xorl(in_out, tmp2);
8692
8693 psllq(w_xtmp2, 1);
8694 movdl(tmp1, w_xtmp2);
8695 psrlq(w_xtmp2, 32);
8696 movdl(in1, w_xtmp2);
8697
8698 xorl(tmp2, tmp2);
8699 crc32(tmp2, tmp1, 4);
8700 xorl(in1, tmp2);
8701 xorl(in_out, in1);
8702 xorl(in_out, in2);
8703 }
8704
8705 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8706 Register in_out1, Register in_out2, Register in_out3,
8707 Register tmp1, Register tmp2, Register tmp3,
8708 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8709 Register tmp4, Register tmp5,
8710 Register n_tmp6) {
8711 Label L_processPartitions;
8712 Label L_processPartition;
8713 Label L_exit;
8714
8715 bind(L_processPartitions);
8716 cmpl(in_out1, 3 * size);
8717 jcc(Assembler::less, L_exit);
8718 xorl(tmp1, tmp1);
8719 xorl(tmp2, tmp2);
8720 movl(tmp3, in_out2);
8721 addl(tmp3, size);
8722
8723 bind(L_processPartition);
8724 crc32(in_out3, Address(in_out2, 0), 4);
8725 crc32(tmp1, Address(in_out2, size), 4);
8726 crc32(tmp2, Address(in_out2, size*2), 4);
8727 crc32(in_out3, Address(in_out2, 0+4), 4);
8728 crc32(tmp1, Address(in_out2, size+4), 4);
8729 crc32(tmp2, Address(in_out2, size*2+4), 4);
8730 addl(in_out2, 8);
8731 cmpl(in_out2, tmp3);
8732 jcc(Assembler::less, L_processPartition);
8733
8734 push(tmp3);
8735 push(in_out1);
8736 push(in_out2);
8737 tmp4 = tmp3;
8738 tmp5 = in_out1;
8739 n_tmp6 = in_out2;
8740
8741 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8742 w_xtmp1, w_xtmp2, w_xtmp3,
8743 tmp4, tmp5,
8744 n_tmp6);
8745
8746 pop(in_out2);
8747 pop(in_out1);
8748 pop(tmp3);
8749
8750 addl(in_out2, 2 * size);
8751 subl(in_out1, 3 * size);
8752 jmp(L_processPartitions);
8753
8754 bind(L_exit);
8755 }
8756 #endif //LP64
8757
8758 #ifdef _LP64
8759 // Algorithm 2: Pipelined usage of the CRC32 instruction.
8760 // Input: A buffer I of L bytes.
8761 // Output: the CRC32C value of the buffer.
8762 // Notations:
8763 // Write L = 24N + r, with N = floor (L/24).
8764 // r = L mod 24 (0 <= r < 24).
8765 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
8766 // N quadwords, and R consists of r bytes.
8767 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
8768 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
8769 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
8770 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
8771 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
8772 Register tmp1, Register tmp2, Register tmp3,
8773 Register tmp4, Register tmp5, Register tmp6,
8774 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8775 bool is_pclmulqdq_supported) {
8776 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
8777 Label L_wordByWord;
8778 Label L_byteByByteProlog;
8779 Label L_byteByByte;
8780 Label L_exit;
8781
8782 if (is_pclmulqdq_supported ) {
8783 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
8784 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
8785
8786 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
8787 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
8788
8789 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
8790 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
8791 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
8792 } else {
8793 const_or_pre_comp_const_index[0] = 1;
8794 const_or_pre_comp_const_index[1] = 0;
8795
8796 const_or_pre_comp_const_index[2] = 3;
8797 const_or_pre_comp_const_index[3] = 2;
8798
8799 const_or_pre_comp_const_index[4] = 5;
8800 const_or_pre_comp_const_index[5] = 4;
8801 }
8802 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
8803 in2, in1, in_out,
8804 tmp1, tmp2, tmp3,
8805 w_xtmp1, w_xtmp2, w_xtmp3,
8806 tmp4, tmp5,
8807 tmp6);
8808 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
8809 in2, in1, in_out,
8810 tmp1, tmp2, tmp3,
8811 w_xtmp1, w_xtmp2, w_xtmp3,
8812 tmp4, tmp5,
8813 tmp6);
8814 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
8815 in2, in1, in_out,
8816 tmp1, tmp2, tmp3,
8817 w_xtmp1, w_xtmp2, w_xtmp3,
8818 tmp4, tmp5,
8819 tmp6);
8820 movl(tmp1, in2);
8821 andl(tmp1, 0x00000007);
8822 negl(tmp1);
8823 addl(tmp1, in2);
8824 addq(tmp1, in1);
8825
8826 cmpq(in1, tmp1);
8827 jccb(Assembler::greaterEqual, L_byteByByteProlog);
8828 align(16);
8829 BIND(L_wordByWord);
8830 crc32(in_out, Address(in1, 0), 8);
8831 addq(in1, 8);
8832 cmpq(in1, tmp1);
8833 jcc(Assembler::less, L_wordByWord);
8834
8835 BIND(L_byteByByteProlog);
8836 andl(in2, 0x00000007);
8837 movl(tmp2, 1);
8838
8839 cmpl(tmp2, in2);
8840 jccb(Assembler::greater, L_exit);
8841 BIND(L_byteByByte);
8842 crc32(in_out, Address(in1, 0), 1);
8843 incq(in1);
8844 incl(tmp2);
8845 cmpl(tmp2, in2);
8846 jcc(Assembler::lessEqual, L_byteByByte);
8847
8848 BIND(L_exit);
8849 }
8850 #else
8851 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
8852 Register tmp1, Register tmp2, Register tmp3,
8853 Register tmp4, Register tmp5, Register tmp6,
8854 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8855 bool is_pclmulqdq_supported) {
8856 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
8857 Label L_wordByWord;
8858 Label L_byteByByteProlog;
8859 Label L_byteByByte;
8860 Label L_exit;
8861
8862 if (is_pclmulqdq_supported) {
8863 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
8864 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
8865
8866 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
8867 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
8868
8869 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
8870 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
8871 } else {
8872 const_or_pre_comp_const_index[0] = 1;
8873 const_or_pre_comp_const_index[1] = 0;
8874
8875 const_or_pre_comp_const_index[2] = 3;
8876 const_or_pre_comp_const_index[3] = 2;
8877
8878 const_or_pre_comp_const_index[4] = 5;
8879 const_or_pre_comp_const_index[5] = 4;
8880 }
8881 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
8882 in2, in1, in_out,
8883 tmp1, tmp2, tmp3,
8884 w_xtmp1, w_xtmp2, w_xtmp3,
8885 tmp4, tmp5,
8886 tmp6);
8887 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
8888 in2, in1, in_out,
8889 tmp1, tmp2, tmp3,
8890 w_xtmp1, w_xtmp2, w_xtmp3,
8891 tmp4, tmp5,
8892 tmp6);
8893 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
8894 in2, in1, in_out,
8895 tmp1, tmp2, tmp3,
8896 w_xtmp1, w_xtmp2, w_xtmp3,
8897 tmp4, tmp5,
8898 tmp6);
8899 movl(tmp1, in2);
8900 andl(tmp1, 0x00000007);
8901 negl(tmp1);
8902 addl(tmp1, in2);
8903 addl(tmp1, in1);
8904
8905 BIND(L_wordByWord);
8906 cmpl(in1, tmp1);
8907 jcc(Assembler::greaterEqual, L_byteByByteProlog);
8908 crc32(in_out, Address(in1,0), 4);
8909 addl(in1, 4);
8910 jmp(L_wordByWord);
8911
8912 BIND(L_byteByByteProlog);
8913 andl(in2, 0x00000007);
8914 movl(tmp2, 1);
8915
8916 BIND(L_byteByByte);
8917 cmpl(tmp2, in2);
8918 jccb(Assembler::greater, L_exit);
8919 movb(tmp1, Address(in1, 0));
8920 crc32(in_out, tmp1, 1);
8921 incl(in1);
8922 incl(tmp2);
8923 jmp(L_byteByByte);
8924
8925 BIND(L_exit);
8926 }
8927 #endif // LP64
8928 #undef BIND
8929 #undef BLOCK_COMMENT
8930
8931 // Compress char[] array to byte[].
8932 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
8933 // Return the array length if every element in array can be encoded,
8934 // otherwise, the index of first non-latin1 (> 0xff) character.
8935 // @IntrinsicCandidate
8936 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
8937 // for (int i = 0; i < len; i++) {
8938 // char c = src[srcOff];
8939 // if (c > 0xff) {
8940 // return i; // return index of non-latin1 char
8941 // }
8942 // dst[dstOff] = (byte)c;
8943 // srcOff++;
8944 // dstOff++;
8945 // }
8946 // return len;
8947 // }
8948 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
8949 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8950 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8951 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
8952 Label copy_chars_loop, done, reset_sp, copy_tail;
8953
8954 // rsi: src
8955 // rdi: dst
8956 // rdx: len
8957 // rcx: tmp5
8958 // rax: result
8959
8960 // rsi holds start addr of source char[] to be compressed
8961 // rdi holds start addr of destination byte[]
8962 // rdx holds length
8963
8964 assert(len != result, "");
8965
8966 // save length for return
8967 movl(result, len);
8968
8969 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
8970 VM_Version::supports_avx512vlbw() &&
8971 VM_Version::supports_bmi2()) {
8972
8973 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
8974
8975 // alignment
8976 Label post_alignment;
8977
8978 // if length of the string is less than 32, handle it the old fashioned way
8979 testl(len, -32);
8980 jcc(Assembler::zero, below_threshold);
8981
8982 // First check whether a character is compressible ( <= 0xFF).
8983 // Create mask to test for Unicode chars inside zmm vector
8984 movl(tmp5, 0x00FF);
8985 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
8986
8987 testl(len, -64);
8988 jccb(Assembler::zero, post_alignment);
8989
8990 movl(tmp5, dst);
8991 andl(tmp5, (32 - 1));
8992 negl(tmp5);
8993 andl(tmp5, (32 - 1));
8994
8995 // bail out when there is nothing to be done
8996 testl(tmp5, 0xFFFFFFFF);
8997 jccb(Assembler::zero, post_alignment);
8998
8999 // ~(~0 << len), where len is the # of remaining elements to process
9000 movl(len, 0xFFFFFFFF);
9001 shlxl(len, len, tmp5);
9002 notl(len);
9003 kmovdl(mask2, len);
9004 movl(len, result);
9005
9006 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9007 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9008 ktestd(mask1, mask2);
9009 jcc(Assembler::carryClear, copy_tail);
9010
9011 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9012
9013 addptr(src, tmp5);
9014 addptr(src, tmp5);
9015 addptr(dst, tmp5);
9016 subl(len, tmp5);
9017
9018 bind(post_alignment);
9019 // end of alignment
9020
9021 movl(tmp5, len);
9022 andl(tmp5, (32 - 1)); // tail count (in chars)
9023 andl(len, ~(32 - 1)); // vector count (in chars)
9024 jccb(Assembler::zero, copy_loop_tail);
9025
9026 lea(src, Address(src, len, Address::times_2));
9027 lea(dst, Address(dst, len, Address::times_1));
9028 negptr(len);
9029
9030 bind(copy_32_loop);
9031 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9032 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9033 kortestdl(mask1, mask1);
9034 jccb(Assembler::carryClear, reset_for_copy_tail);
9035
9036 // All elements in current processed chunk are valid candidates for
9037 // compression. Write a truncated byte elements to the memory.
9038 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9039 addptr(len, 32);
9040 jccb(Assembler::notZero, copy_32_loop);
9041
9042 bind(copy_loop_tail);
9043 // bail out when there is nothing to be done
9044 testl(tmp5, 0xFFFFFFFF);
9045 jcc(Assembler::zero, done);
9046
9047 movl(len, tmp5);
9048
9049 // ~(~0 << len), where len is the # of remaining elements to process
9050 movl(tmp5, 0xFFFFFFFF);
9051 shlxl(tmp5, tmp5, len);
9052 notl(tmp5);
9053
9054 kmovdl(mask2, tmp5);
9055
9056 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9057 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9058 ktestd(mask1, mask2);
9059 jcc(Assembler::carryClear, copy_tail);
9060
9061 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9062 jmp(done);
9063
9064 bind(reset_for_copy_tail);
9065 lea(src, Address(src, tmp5, Address::times_2));
9066 lea(dst, Address(dst, tmp5, Address::times_1));
9067 subptr(len, tmp5);
9068 jmp(copy_chars_loop);
9069
9070 bind(below_threshold);
9071 }
9072
9073 if (UseSSE42Intrinsics) {
9074 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9075
9076 // vectored compression
9077 testl(len, 0xfffffff8);
9078 jcc(Assembler::zero, copy_tail);
9079
9080 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9081 movdl(tmp1Reg, tmp5);
9082 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9083
9084 andl(len, 0xfffffff0);
9085 jccb(Assembler::zero, copy_16);
9086
9087 // compress 16 chars per iter
9088 pxor(tmp4Reg, tmp4Reg);
9089
9090 lea(src, Address(src, len, Address::times_2));
9091 lea(dst, Address(dst, len, Address::times_1));
9092 negptr(len);
9093
9094 bind(copy_32_loop);
9095 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9096 por(tmp4Reg, tmp2Reg);
9097 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9098 por(tmp4Reg, tmp3Reg);
9099 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9100 jccb(Assembler::notZero, reset_for_copy_tail);
9101 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9102 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9103 addptr(len, 16);
9104 jccb(Assembler::notZero, copy_32_loop);
9105
9106 // compress next vector of 8 chars (if any)
9107 bind(copy_16);
9108 // len = 0
9109 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9110 jccb(Assembler::zero, copy_tail_sse);
9111
9112 pxor(tmp3Reg, tmp3Reg);
9113
9114 movdqu(tmp2Reg, Address(src, 0));
9115 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9116 jccb(Assembler::notZero, reset_for_copy_tail);
9117 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9118 movq(Address(dst, 0), tmp2Reg);
9119 addptr(src, 16);
9120 addptr(dst, 8);
9121 jmpb(copy_tail_sse);
9122
9123 bind(reset_for_copy_tail);
9124 movl(tmp5, result);
9125 andl(tmp5, 0x0000000f);
9126 lea(src, Address(src, tmp5, Address::times_2));
9127 lea(dst, Address(dst, tmp5, Address::times_1));
9128 subptr(len, tmp5);
9129 jmpb(copy_chars_loop);
9130
9131 bind(copy_tail_sse);
9132 movl(len, result);
9133 andl(len, 0x00000007); // tail count (in chars)
9134 }
9135 // compress 1 char per iter
9136 bind(copy_tail);
9137 testl(len, len);
9138 jccb(Assembler::zero, done);
9139 lea(src, Address(src, len, Address::times_2));
9140 lea(dst, Address(dst, len, Address::times_1));
9141 negptr(len);
9142
9143 bind(copy_chars_loop);
9144 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9145 testl(tmp5, 0xff00); // check if Unicode char
9146 jccb(Assembler::notZero, reset_sp);
9147 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9148 increment(len);
9149 jccb(Assembler::notZero, copy_chars_loop);
9150
9151 // add len then return (len will be zero if compress succeeded, otherwise negative)
9152 bind(reset_sp);
9153 addl(result, len);
9154
9155 bind(done);
9156 }
9157
9158 // Inflate byte[] array to char[].
9159 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9160 // @IntrinsicCandidate
9161 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9162 // for (int i = 0; i < len; i++) {
9163 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9164 // }
9165 // }
9166 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9167 XMMRegister tmp1, Register tmp2, KRegister mask) {
9168 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9169 // rsi: src
9170 // rdi: dst
9171 // rdx: len
9172 // rcx: tmp2
9173
9174 // rsi holds start addr of source byte[] to be inflated
9175 // rdi holds start addr of destination char[]
9176 // rdx holds length
9177 assert_different_registers(src, dst, len, tmp2);
9178 movl(tmp2, len);
9179 if ((UseAVX > 2) && // AVX512
9180 VM_Version::supports_avx512vlbw() &&
9181 VM_Version::supports_bmi2()) {
9182
9183 Label copy_32_loop, copy_tail;
9184 Register tmp3_aliased = len;
9185
9186 // if length of the string is less than 16, handle it in an old fashioned way
9187 testl(len, -16);
9188 jcc(Assembler::zero, below_threshold);
9189
9190 testl(len, -1 * AVX3Threshold);
9191 jcc(Assembler::zero, avx3_threshold);
9192
9193 // In order to use only one arithmetic operation for the main loop we use
9194 // this pre-calculation
9195 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9196 andl(len, -32); // vector count
9197 jccb(Assembler::zero, copy_tail);
9198
9199 lea(src, Address(src, len, Address::times_1));
9200 lea(dst, Address(dst, len, Address::times_2));
9201 negptr(len);
9202
9203
9204 // inflate 32 chars per iter
9205 bind(copy_32_loop);
9206 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9207 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9208 addptr(len, 32);
9209 jcc(Assembler::notZero, copy_32_loop);
9210
9211 bind(copy_tail);
9212 // bail out when there is nothing to be done
9213 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9214 jcc(Assembler::zero, done);
9215
9216 // ~(~0 << length), where length is the # of remaining elements to process
9217 movl(tmp3_aliased, -1);
9218 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9219 notl(tmp3_aliased);
9220 kmovdl(mask, tmp3_aliased);
9221 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9222 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9223
9224 jmp(done);
9225 bind(avx3_threshold);
9226 }
9227 if (UseSSE42Intrinsics) {
9228 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9229
9230 if (UseAVX > 1) {
9231 andl(tmp2, (16 - 1));
9232 andl(len, -16);
9233 jccb(Assembler::zero, copy_new_tail);
9234 } else {
9235 andl(tmp2, 0x00000007); // tail count (in chars)
9236 andl(len, 0xfffffff8); // vector count (in chars)
9237 jccb(Assembler::zero, copy_tail);
9238 }
9239
9240 // vectored inflation
9241 lea(src, Address(src, len, Address::times_1));
9242 lea(dst, Address(dst, len, Address::times_2));
9243 negptr(len);
9244
9245 if (UseAVX > 1) {
9246 bind(copy_16_loop);
9247 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9248 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9249 addptr(len, 16);
9250 jcc(Assembler::notZero, copy_16_loop);
9251
9252 bind(below_threshold);
9253 bind(copy_new_tail);
9254 movl(len, tmp2);
9255 andl(tmp2, 0x00000007);
9256 andl(len, 0xFFFFFFF8);
9257 jccb(Assembler::zero, copy_tail);
9258
9259 pmovzxbw(tmp1, Address(src, 0));
9260 movdqu(Address(dst, 0), tmp1);
9261 addptr(src, 8);
9262 addptr(dst, 2 * 8);
9263
9264 jmp(copy_tail, true);
9265 }
9266
9267 // inflate 8 chars per iter
9268 bind(copy_8_loop);
9269 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9270 movdqu(Address(dst, len, Address::times_2), tmp1);
9271 addptr(len, 8);
9272 jcc(Assembler::notZero, copy_8_loop);
9273
9274 bind(copy_tail);
9275 movl(len, tmp2);
9276
9277 cmpl(len, 4);
9278 jccb(Assembler::less, copy_bytes);
9279
9280 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9281 pmovzxbw(tmp1, tmp1);
9282 movq(Address(dst, 0), tmp1);
9283 subptr(len, 4);
9284 addptr(src, 4);
9285 addptr(dst, 8);
9286
9287 bind(copy_bytes);
9288 } else {
9289 bind(below_threshold);
9290 }
9291
9292 testl(len, len);
9293 jccb(Assembler::zero, done);
9294 lea(src, Address(src, len, Address::times_1));
9295 lea(dst, Address(dst, len, Address::times_2));
9296 negptr(len);
9297
9298 // inflate 1 char per iter
9299 bind(copy_chars_loop);
9300 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9301 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9302 increment(len);
9303 jcc(Assembler::notZero, copy_chars_loop);
9304
9305 bind(done);
9306 }
9307
9308
9309 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9310 switch(type) {
9311 case T_BYTE:
9312 case T_BOOLEAN:
9313 evmovdqub(dst, kmask, src, merge, vector_len);
9314 break;
9315 case T_CHAR:
9316 case T_SHORT:
9317 evmovdquw(dst, kmask, src, merge, vector_len);
9318 break;
9319 case T_INT:
9320 case T_FLOAT:
9321 evmovdqul(dst, kmask, src, merge, vector_len);
9322 break;
9323 case T_LONG:
9324 case T_DOUBLE:
9325 evmovdquq(dst, kmask, src, merge, vector_len);
9326 break;
9327 default:
9328 fatal("Unexpected type argument %s", type2name(type));
9329 break;
9330 }
9331 }
9332
9333 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9334 switch(type) {
9335 case T_BYTE:
9336 case T_BOOLEAN:
9337 evmovdqub(dst, kmask, src, merge, vector_len);
9338 break;
9339 case T_CHAR:
9340 case T_SHORT:
9341 evmovdquw(dst, kmask, src, merge, vector_len);
9342 break;
9343 case T_INT:
9344 case T_FLOAT:
9345 evmovdqul(dst, kmask, src, merge, vector_len);
9346 break;
9347 case T_LONG:
9348 case T_DOUBLE:
9349 evmovdquq(dst, kmask, src, merge, vector_len);
9350 break;
9351 default:
9352 fatal("Unexpected type argument %s", type2name(type));
9353 break;
9354 }
9355 }
9356
9357 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9358 switch(masklen) {
9359 case 2:
9360 knotbl(dst, src);
9361 movl(rtmp, 3);
9362 kmovbl(ktmp, rtmp);
9363 kandbl(dst, ktmp, dst);
9364 break;
9365 case 4:
9366 knotbl(dst, src);
9367 movl(rtmp, 15);
9368 kmovbl(ktmp, rtmp);
9369 kandbl(dst, ktmp, dst);
9370 break;
9371 case 8:
9372 knotbl(dst, src);
9373 break;
9374 case 16:
9375 knotwl(dst, src);
9376 break;
9377 case 32:
9378 knotdl(dst, src);
9379 break;
9380 case 64:
9381 knotql(dst, src);
9382 break;
9383 default:
9384 fatal("Unexpected vector length %d", masklen);
9385 break;
9386 }
9387 }
9388
9389 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9390 switch(type) {
9391 case T_BOOLEAN:
9392 case T_BYTE:
9393 kandbl(dst, src1, src2);
9394 break;
9395 case T_CHAR:
9396 case T_SHORT:
9397 kandwl(dst, src1, src2);
9398 break;
9399 case T_INT:
9400 case T_FLOAT:
9401 kanddl(dst, src1, src2);
9402 break;
9403 case T_LONG:
9404 case T_DOUBLE:
9405 kandql(dst, src1, src2);
9406 break;
9407 default:
9408 fatal("Unexpected type argument %s", type2name(type));
9409 break;
9410 }
9411 }
9412
9413 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9414 switch(type) {
9415 case T_BOOLEAN:
9416 case T_BYTE:
9417 korbl(dst, src1, src2);
9418 break;
9419 case T_CHAR:
9420 case T_SHORT:
9421 korwl(dst, src1, src2);
9422 break;
9423 case T_INT:
9424 case T_FLOAT:
9425 kordl(dst, src1, src2);
9426 break;
9427 case T_LONG:
9428 case T_DOUBLE:
9429 korql(dst, src1, src2);
9430 break;
9431 default:
9432 fatal("Unexpected type argument %s", type2name(type));
9433 break;
9434 }
9435 }
9436
9437 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9438 switch(type) {
9439 case T_BOOLEAN:
9440 case T_BYTE:
9441 kxorbl(dst, src1, src2);
9442 break;
9443 case T_CHAR:
9444 case T_SHORT:
9445 kxorwl(dst, src1, src2);
9446 break;
9447 case T_INT:
9448 case T_FLOAT:
9449 kxordl(dst, src1, src2);
9450 break;
9451 case T_LONG:
9452 case T_DOUBLE:
9453 kxorql(dst, src1, src2);
9454 break;
9455 default:
9456 fatal("Unexpected type argument %s", type2name(type));
9457 break;
9458 }
9459 }
9460
9461 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9462 switch(type) {
9463 case T_BOOLEAN:
9464 case T_BYTE:
9465 evpermb(dst, mask, nds, src, merge, vector_len); break;
9466 case T_CHAR:
9467 case T_SHORT:
9468 evpermw(dst, mask, nds, src, merge, vector_len); break;
9469 case T_INT:
9470 case T_FLOAT:
9471 evpermd(dst, mask, nds, src, merge, vector_len); break;
9472 case T_LONG:
9473 case T_DOUBLE:
9474 evpermq(dst, mask, nds, src, merge, vector_len); break;
9475 default:
9476 fatal("Unexpected type argument %s", type2name(type)); break;
9477 }
9478 }
9479
9480 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9481 switch(type) {
9482 case T_BOOLEAN:
9483 case T_BYTE:
9484 evpermb(dst, mask, nds, src, merge, vector_len); break;
9485 case T_CHAR:
9486 case T_SHORT:
9487 evpermw(dst, mask, nds, src, merge, vector_len); break;
9488 case T_INT:
9489 case T_FLOAT:
9490 evpermd(dst, mask, nds, src, merge, vector_len); break;
9491 case T_LONG:
9492 case T_DOUBLE:
9493 evpermq(dst, mask, nds, src, merge, vector_len); break;
9494 default:
9495 fatal("Unexpected type argument %s", type2name(type)); break;
9496 }
9497 }
9498
9499 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9500 switch(type) {
9501 case T_BYTE:
9502 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9503 case T_SHORT:
9504 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9505 case T_INT:
9506 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9507 case T_LONG:
9508 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9509 default:
9510 fatal("Unexpected type argument %s", type2name(type)); break;
9511 }
9512 }
9513
9514 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9515 switch(type) {
9516 case T_BYTE:
9517 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9518 case T_SHORT:
9519 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9520 case T_INT:
9521 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9522 case T_LONG:
9523 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9524 default:
9525 fatal("Unexpected type argument %s", type2name(type)); break;
9526 }
9527 }
9528
9529 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9530 switch(type) {
9531 case T_BYTE:
9532 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9533 case T_SHORT:
9534 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9535 case T_INT:
9536 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9537 case T_LONG:
9538 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9539 default:
9540 fatal("Unexpected type argument %s", type2name(type)); break;
9541 }
9542 }
9543
9544 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9545 switch(type) {
9546 case T_BYTE:
9547 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9548 case T_SHORT:
9549 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9550 case T_INT:
9551 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9552 case T_LONG:
9553 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9554 default:
9555 fatal("Unexpected type argument %s", type2name(type)); break;
9556 }
9557 }
9558
9559 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9560 switch(type) {
9561 case T_INT:
9562 evpxord(dst, mask, nds, src, merge, vector_len); break;
9563 case T_LONG:
9564 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9565 default:
9566 fatal("Unexpected type argument %s", type2name(type)); break;
9567 }
9568 }
9569
9570 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9571 switch(type) {
9572 case T_INT:
9573 evpxord(dst, mask, nds, src, merge, vector_len); break;
9574 case T_LONG:
9575 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9576 default:
9577 fatal("Unexpected type argument %s", type2name(type)); break;
9578 }
9579 }
9580
9581 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9582 switch(type) {
9583 case T_INT:
9584 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9585 case T_LONG:
9586 evporq(dst, mask, nds, src, merge, vector_len); break;
9587 default:
9588 fatal("Unexpected type argument %s", type2name(type)); break;
9589 }
9590 }
9591
9592 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9593 switch(type) {
9594 case T_INT:
9595 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9596 case T_LONG:
9597 evporq(dst, mask, nds, src, merge, vector_len); break;
9598 default:
9599 fatal("Unexpected type argument %s", type2name(type)); break;
9600 }
9601 }
9602
9603 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9604 switch(type) {
9605 case T_INT:
9606 evpandd(dst, mask, nds, src, merge, vector_len); break;
9607 case T_LONG:
9608 evpandq(dst, mask, nds, src, merge, vector_len); break;
9609 default:
9610 fatal("Unexpected type argument %s", type2name(type)); break;
9611 }
9612 }
9613
9614 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9615 switch(type) {
9616 case T_INT:
9617 evpandd(dst, mask, nds, src, merge, vector_len); break;
9618 case T_LONG:
9619 evpandq(dst, mask, nds, src, merge, vector_len); break;
9620 default:
9621 fatal("Unexpected type argument %s", type2name(type)); break;
9622 }
9623 }
9624
9625 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
9626 switch(masklen) {
9627 case 8:
9628 kortestbl(src1, src2);
9629 break;
9630 case 16:
9631 kortestwl(src1, src2);
9632 break;
9633 case 32:
9634 kortestdl(src1, src2);
9635 break;
9636 case 64:
9637 kortestql(src1, src2);
9638 break;
9639 default:
9640 fatal("Unexpected mask length %d", masklen);
9641 break;
9642 }
9643 }
9644
9645
9646 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
9647 switch(masklen) {
9648 case 8:
9649 ktestbl(src1, src2);
9650 break;
9651 case 16:
9652 ktestwl(src1, src2);
9653 break;
9654 case 32:
9655 ktestdl(src1, src2);
9656 break;
9657 case 64:
9658 ktestql(src1, src2);
9659 break;
9660 default:
9661 fatal("Unexpected mask length %d", masklen);
9662 break;
9663 }
9664 }
9665
9666 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9667 switch(type) {
9668 case T_INT:
9669 evprold(dst, mask, src, shift, merge, vlen_enc); break;
9670 case T_LONG:
9671 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
9672 default:
9673 fatal("Unexpected type argument %s", type2name(type)); break;
9674 break;
9675 }
9676 }
9677
9678 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9679 switch(type) {
9680 case T_INT:
9681 evprord(dst, mask, src, shift, merge, vlen_enc); break;
9682 case T_LONG:
9683 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
9684 default:
9685 fatal("Unexpected type argument %s", type2name(type)); break;
9686 }
9687 }
9688
9689 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
9690 switch(type) {
9691 case T_INT:
9692 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
9693 case T_LONG:
9694 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
9695 default:
9696 fatal("Unexpected type argument %s", type2name(type)); break;
9697 }
9698 }
9699
9700 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
9701 switch(type) {
9702 case T_INT:
9703 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
9704 case T_LONG:
9705 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
9706 default:
9707 fatal("Unexpected type argument %s", type2name(type)); break;
9708 }
9709 }
9710
9711 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9712 assert(rscratch != noreg || always_reachable(src), "missing");
9713
9714 if (reachable(src)) {
9715 evpandq(dst, nds, as_Address(src), vector_len);
9716 } else {
9717 lea(rscratch, src);
9718 evpandq(dst, nds, Address(rscratch, 0), vector_len);
9719 }
9720 }
9721
9722 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
9723 assert(rscratch != noreg || always_reachable(src), "missing");
9724
9725 if (reachable(src)) {
9726 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
9727 } else {
9728 lea(rscratch, src);
9729 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
9730 }
9731 }
9732
9733 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9734 assert(rscratch != noreg || always_reachable(src), "missing");
9735
9736 if (reachable(src)) {
9737 evporq(dst, nds, as_Address(src), vector_len);
9738 } else {
9739 lea(rscratch, src);
9740 evporq(dst, nds, Address(rscratch, 0), vector_len);
9741 }
9742 }
9743
9744 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9745 assert(rscratch != noreg || always_reachable(src), "missing");
9746
9747 if (reachable(src)) {
9748 vpshufb(dst, nds, as_Address(src), vector_len);
9749 } else {
9750 lea(rscratch, src);
9751 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
9752 }
9753 }
9754
9755 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9756 assert(rscratch != noreg || always_reachable(src), "missing");
9757
9758 if (reachable(src)) {
9759 Assembler::vpor(dst, nds, as_Address(src), vector_len);
9760 } else {
9761 lea(rscratch, src);
9762 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
9763 }
9764 }
9765
9766 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
9767 assert(rscratch != noreg || always_reachable(src3), "missing");
9768
9769 if (reachable(src3)) {
9770 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
9771 } else {
9772 lea(rscratch, src3);
9773 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
9774 }
9775 }
9776
9777 #if COMPILER2_OR_JVMCI
9778
9779 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
9780 Register length, Register temp, int vec_enc) {
9781 // Computing mask for predicated vector store.
9782 movptr(temp, -1);
9783 bzhiq(temp, temp, length);
9784 kmov(mask, temp);
9785 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
9786 }
9787
9788 // Set memory operation for length "less than" 64 bytes.
9789 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
9790 XMMRegister xmm, KRegister mask, Register length,
9791 Register temp, bool use64byteVector) {
9792 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9793 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
9794 if (!use64byteVector) {
9795 fill32(dst, disp, xmm);
9796 subptr(length, 32 >> shift);
9797 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
9798 } else {
9799 assert(MaxVectorSize == 64, "vector length != 64");
9800 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
9801 }
9802 }
9803
9804
9805 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
9806 XMMRegister xmm, KRegister mask, Register length,
9807 Register temp) {
9808 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9809 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
9810 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
9811 }
9812
9813
9814 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
9815 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9816 vmovdqu(dst, xmm);
9817 }
9818
9819 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
9820 fill32(Address(dst, disp), xmm);
9821 }
9822
9823 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
9824 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9825 if (!use64byteVector) {
9826 fill32(dst, xmm);
9827 fill32(dst.plus_disp(32), xmm);
9828 } else {
9829 evmovdquq(dst, xmm, Assembler::AVX_512bit);
9830 }
9831 }
9832
9833 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
9834 fill64(Address(dst, disp), xmm, use64byteVector);
9835 }
9836
9837 #ifdef _LP64
9838 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
9839 Register count, Register rtmp, XMMRegister xtmp) {
9840 Label L_exit;
9841 Label L_fill_start;
9842 Label L_fill_64_bytes;
9843 Label L_fill_96_bytes;
9844 Label L_fill_128_bytes;
9845 Label L_fill_128_bytes_loop;
9846 Label L_fill_128_loop_header;
9847 Label L_fill_128_bytes_loop_header;
9848 Label L_fill_128_bytes_loop_pre_header;
9849 Label L_fill_zmm_sequence;
9850
9851 int shift = -1;
9852 int avx3threshold = VM_Version::avx3_threshold();
9853 switch(type) {
9854 case T_BYTE: shift = 0;
9855 break;
9856 case T_SHORT: shift = 1;
9857 break;
9858 case T_INT: shift = 2;
9859 break;
9860 /* Uncomment when LONG fill stubs are supported.
9861 case T_LONG: shift = 3;
9862 break;
9863 */
9864 default:
9865 fatal("Unhandled type: %s\n", type2name(type));
9866 }
9867
9868 if ((avx3threshold != 0) || (MaxVectorSize == 32)) {
9869
9870 if (MaxVectorSize == 64) {
9871 cmpq(count, avx3threshold >> shift);
9872 jcc(Assembler::greater, L_fill_zmm_sequence);
9873 }
9874
9875 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
9876
9877 bind(L_fill_start);
9878
9879 cmpq(count, 32 >> shift);
9880 jccb(Assembler::greater, L_fill_64_bytes);
9881 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
9882 jmp(L_exit);
9883
9884 bind(L_fill_64_bytes);
9885 cmpq(count, 64 >> shift);
9886 jccb(Assembler::greater, L_fill_96_bytes);
9887 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
9888 jmp(L_exit);
9889
9890 bind(L_fill_96_bytes);
9891 cmpq(count, 96 >> shift);
9892 jccb(Assembler::greater, L_fill_128_bytes);
9893 fill64(to, 0, xtmp);
9894 subq(count, 64 >> shift);
9895 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
9896 jmp(L_exit);
9897
9898 bind(L_fill_128_bytes);
9899 cmpq(count, 128 >> shift);
9900 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
9901 fill64(to, 0, xtmp);
9902 fill32(to, 64, xtmp);
9903 subq(count, 96 >> shift);
9904 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
9905 jmp(L_exit);
9906
9907 bind(L_fill_128_bytes_loop_pre_header);
9908 {
9909 mov(rtmp, to);
9910 andq(rtmp, 31);
9911 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
9912 negq(rtmp);
9913 addq(rtmp, 32);
9914 mov64(r8, -1L);
9915 bzhiq(r8, r8, rtmp);
9916 kmovql(k2, r8);
9917 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
9918 addq(to, rtmp);
9919 shrq(rtmp, shift);
9920 subq(count, rtmp);
9921 }
9922
9923 cmpq(count, 128 >> shift);
9924 jcc(Assembler::less, L_fill_start);
9925
9926 bind(L_fill_128_bytes_loop_header);
9927 subq(count, 128 >> shift);
9928
9929 align32();
9930 bind(L_fill_128_bytes_loop);
9931 fill64(to, 0, xtmp);
9932 fill64(to, 64, xtmp);
9933 addq(to, 128);
9934 subq(count, 128 >> shift);
9935 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
9936
9937 addq(count, 128 >> shift);
9938 jcc(Assembler::zero, L_exit);
9939 jmp(L_fill_start);
9940 }
9941
9942 if (MaxVectorSize == 64) {
9943 // Sequence using 64 byte ZMM register.
9944 Label L_fill_128_bytes_zmm;
9945 Label L_fill_192_bytes_zmm;
9946 Label L_fill_192_bytes_loop_zmm;
9947 Label L_fill_192_bytes_loop_header_zmm;
9948 Label L_fill_192_bytes_loop_pre_header_zmm;
9949 Label L_fill_start_zmm_sequence;
9950
9951 bind(L_fill_zmm_sequence);
9952 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
9953
9954 bind(L_fill_start_zmm_sequence);
9955 cmpq(count, 64 >> shift);
9956 jccb(Assembler::greater, L_fill_128_bytes_zmm);
9957 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
9958 jmp(L_exit);
9959
9960 bind(L_fill_128_bytes_zmm);
9961 cmpq(count, 128 >> shift);
9962 jccb(Assembler::greater, L_fill_192_bytes_zmm);
9963 fill64(to, 0, xtmp, true);
9964 subq(count, 64 >> shift);
9965 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
9966 jmp(L_exit);
9967
9968 bind(L_fill_192_bytes_zmm);
9969 cmpq(count, 192 >> shift);
9970 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
9971 fill64(to, 0, xtmp, true);
9972 fill64(to, 64, xtmp, true);
9973 subq(count, 128 >> shift);
9974 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
9975 jmp(L_exit);
9976
9977 bind(L_fill_192_bytes_loop_pre_header_zmm);
9978 {
9979 movq(rtmp, to);
9980 andq(rtmp, 63);
9981 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
9982 negq(rtmp);
9983 addq(rtmp, 64);
9984 mov64(r8, -1L);
9985 bzhiq(r8, r8, rtmp);
9986 kmovql(k2, r8);
9987 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
9988 addq(to, rtmp);
9989 shrq(rtmp, shift);
9990 subq(count, rtmp);
9991 }
9992
9993 cmpq(count, 192 >> shift);
9994 jcc(Assembler::less, L_fill_start_zmm_sequence);
9995
9996 bind(L_fill_192_bytes_loop_header_zmm);
9997 subq(count, 192 >> shift);
9998
9999 align32();
10000 bind(L_fill_192_bytes_loop_zmm);
10001 fill64(to, 0, xtmp, true);
10002 fill64(to, 64, xtmp, true);
10003 fill64(to, 128, xtmp, true);
10004 addq(to, 192);
10005 subq(count, 192 >> shift);
10006 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10007
10008 addq(count, 192 >> shift);
10009 jcc(Assembler::zero, L_exit);
10010 jmp(L_fill_start_zmm_sequence);
10011 }
10012 bind(L_exit);
10013 }
10014 #endif
10015 #endif //COMPILER2_OR_JVMCI
10016
10017
10018 #ifdef _LP64
10019 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10020 Label done;
10021 cvttss2sil(dst, src);
10022 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10023 cmpl(dst, 0x80000000); // float_sign_flip
10024 jccb(Assembler::notEqual, done);
10025 subptr(rsp, 8);
10026 movflt(Address(rsp, 0), src);
10027 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10028 pop(dst);
10029 bind(done);
10030 }
10031
10032 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10033 Label done;
10034 cvttsd2sil(dst, src);
10035 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10036 cmpl(dst, 0x80000000); // float_sign_flip
10037 jccb(Assembler::notEqual, done);
10038 subptr(rsp, 8);
10039 movdbl(Address(rsp, 0), src);
10040 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10041 pop(dst);
10042 bind(done);
10043 }
10044
10045 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10046 Label done;
10047 cvttss2siq(dst, src);
10048 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10049 jccb(Assembler::notEqual, done);
10050 subptr(rsp, 8);
10051 movflt(Address(rsp, 0), src);
10052 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10053 pop(dst);
10054 bind(done);
10055 }
10056
10057 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10058 // Following code is line by line assembly translation rounding algorithm.
10059 // Please refer to java.lang.Math.round(float) algorithm for details.
10060 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10061 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10062 const int32_t FloatConsts_EXP_BIAS = 127;
10063 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10064 const int32_t MINUS_32 = 0xFFFFFFE0;
10065 Label L_special_case, L_block1, L_exit;
10066 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10067 movdl(dst, src);
10068 andl(dst, rtmp);
10069 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10070 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10071 subl(rtmp, dst);
10072 movl(rcx, rtmp);
10073 movl(dst, MINUS_32);
10074 testl(rtmp, dst);
10075 jccb(Assembler::notEqual, L_special_case);
10076 movdl(dst, src);
10077 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10078 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10079 movdl(rtmp, src);
10080 testl(rtmp, rtmp);
10081 jccb(Assembler::greaterEqual, L_block1);
10082 negl(dst);
10083 bind(L_block1);
10084 sarl(dst);
10085 addl(dst, 0x1);
10086 sarl(dst, 0x1);
10087 jmp(L_exit);
10088 bind(L_special_case);
10089 convert_f2i(dst, src);
10090 bind(L_exit);
10091 }
10092
10093 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10094 // Following code is line by line assembly translation rounding algorithm.
10095 // Please refer to java.lang.Math.round(double) algorithm for details.
10096 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10097 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10098 const int64_t DoubleConsts_EXP_BIAS = 1023;
10099 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10100 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10101 Label L_special_case, L_block1, L_exit;
10102 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10103 movq(dst, src);
10104 andq(dst, rtmp);
10105 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10106 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10107 subq(rtmp, dst);
10108 movq(rcx, rtmp);
10109 mov64(dst, MINUS_64);
10110 testq(rtmp, dst);
10111 jccb(Assembler::notEqual, L_special_case);
10112 movq(dst, src);
10113 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10114 andq(dst, rtmp);
10115 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10116 orq(dst, rtmp);
10117 movq(rtmp, src);
10118 testq(rtmp, rtmp);
10119 jccb(Assembler::greaterEqual, L_block1);
10120 negq(dst);
10121 bind(L_block1);
10122 sarq(dst);
10123 addq(dst, 0x1);
10124 sarq(dst, 0x1);
10125 jmp(L_exit);
10126 bind(L_special_case);
10127 convert_d2l(dst, src);
10128 bind(L_exit);
10129 }
10130
10131 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10132 Label done;
10133 cvttsd2siq(dst, src);
10134 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10135 jccb(Assembler::notEqual, done);
10136 subptr(rsp, 8);
10137 movdbl(Address(rsp, 0), src);
10138 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10139 pop(dst);
10140 bind(done);
10141 }
10142
10143 void MacroAssembler::cache_wb(Address line)
10144 {
10145 // 64 bit cpus always support clflush
10146 assert(VM_Version::supports_clflush(), "clflush should be available");
10147 bool optimized = VM_Version::supports_clflushopt();
10148 bool no_evict = VM_Version::supports_clwb();
10149
10150 // prefer clwb (writeback without evict) otherwise
10151 // prefer clflushopt (potentially parallel writeback with evict)
10152 // otherwise fallback on clflush (serial writeback with evict)
10153
10154 if (optimized) {
10155 if (no_evict) {
10156 clwb(line);
10157 } else {
10158 clflushopt(line);
10159 }
10160 } else {
10161 // no need for fence when using CLFLUSH
10162 clflush(line);
10163 }
10164 }
10165
10166 void MacroAssembler::cache_wbsync(bool is_pre)
10167 {
10168 assert(VM_Version::supports_clflush(), "clflush should be available");
10169 bool optimized = VM_Version::supports_clflushopt();
10170 bool no_evict = VM_Version::supports_clwb();
10171
10172 // pick the correct implementation
10173
10174 if (!is_pre && (optimized || no_evict)) {
10175 // need an sfence for post flush when using clflushopt or clwb
10176 // otherwise no no need for any synchroniaztion
10177
10178 sfence();
10179 }
10180 }
10181
10182 #endif // _LP64
10183
10184 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10185 switch (cond) {
10186 // Note some conditions are synonyms for others
10187 case Assembler::zero: return Assembler::notZero;
10188 case Assembler::notZero: return Assembler::zero;
10189 case Assembler::less: return Assembler::greaterEqual;
10190 case Assembler::lessEqual: return Assembler::greater;
10191 case Assembler::greater: return Assembler::lessEqual;
10192 case Assembler::greaterEqual: return Assembler::less;
10193 case Assembler::below: return Assembler::aboveEqual;
10194 case Assembler::belowEqual: return Assembler::above;
10195 case Assembler::above: return Assembler::belowEqual;
10196 case Assembler::aboveEqual: return Assembler::below;
10197 case Assembler::overflow: return Assembler::noOverflow;
10198 case Assembler::noOverflow: return Assembler::overflow;
10199 case Assembler::negative: return Assembler::positive;
10200 case Assembler::positive: return Assembler::negative;
10201 case Assembler::parity: return Assembler::noParity;
10202 case Assembler::noParity: return Assembler::parity;
10203 }
10204 ShouldNotReachHere(); return Assembler::overflow;
10205 }
10206
10207 SkipIfEqual::SkipIfEqual(
10208 MacroAssembler* masm, const bool* flag_addr, bool value, Register rscratch) {
10209 _masm = masm;
10210 _masm->cmp8(ExternalAddress((address)flag_addr), value, rscratch);
10211 _masm->jcc(Assembler::equal, _label);
10212 }
10213
10214 SkipIfEqual::~SkipIfEqual() {
10215 _masm->bind(_label);
10216 }
10217
10218 // 32-bit Windows has its own fast-path implementation
10219 // of get_thread
10220 #if !defined(WIN32) || defined(_LP64)
10221
10222 // This is simply a call to Thread::current()
10223 void MacroAssembler::get_thread(Register thread) {
10224 if (thread != rax) {
10225 push(rax);
10226 }
10227 LP64_ONLY(push(rdi);)
10228 LP64_ONLY(push(rsi);)
10229 push(rdx);
10230 push(rcx);
10231 #ifdef _LP64
10232 push(r8);
10233 push(r9);
10234 push(r10);
10235 push(r11);
10236 #endif
10237
10238 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10239
10240 #ifdef _LP64
10241 pop(r11);
10242 pop(r10);
10243 pop(r9);
10244 pop(r8);
10245 #endif
10246 pop(rcx);
10247 pop(rdx);
10248 LP64_ONLY(pop(rsi);)
10249 LP64_ONLY(pop(rdi);)
10250 if (thread != rax) {
10251 mov(thread, rax);
10252 pop(rax);
10253 }
10254 }
10255
10256
10257 #endif // !WIN32 || _LP64
10258
10259 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10260 Label L_stack_ok;
10261 if (bias == 0) {
10262 testptr(sp, 2 * wordSize - 1);
10263 } else {
10264 // lea(tmp, Address(rsp, bias);
10265 mov(tmp, sp);
10266 addptr(tmp, bias);
10267 testptr(tmp, 2 * wordSize - 1);
10268 }
10269 jcc(Assembler::equal, L_stack_ok);
10270 block_comment(msg);
10271 stop(msg);
10272 bind(L_stack_ok);
10273 }
10274
10275 // Implements lightweight-locking.
10276 //
10277 // obj: the object to be locked
10278 // reg_rax: rax
10279 // thread: the thread which attempts to lock obj
10280 // tmp: a temporary register
10281 void MacroAssembler::lightweight_lock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10282 assert(reg_rax == rax, "");
10283 assert_different_registers(obj, reg_rax, thread, tmp);
10284
10285 Label push;
10286 const Register top = tmp;
10287
10288 // Preload the markWord. It is important that this is the first
10289 // instruction emitted as it is part of C1's null check semantics.
10290 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10291
10292 // Load top.
10293 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10294
10295 // Check if the lock-stack is full.
10296 cmpl(top, LockStack::end_offset());
10297 jcc(Assembler::greaterEqual, slow);
10298
10299 // Check for recursion.
10300 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10301 jcc(Assembler::equal, push);
10302
10303 // Check header for monitor (0b10).
10304 testptr(reg_rax, markWord::monitor_value);
10305 jcc(Assembler::notZero, slow);
10306
10307 // Try to lock. Transition lock bits 0b01 => 0b00
10308 movptr(tmp, reg_rax);
10309 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10310 orptr(reg_rax, markWord::unlocked_value);
10311 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10312 jcc(Assembler::notEqual, slow);
10313
10314 // Restore top, CAS clobbers register.
10315 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10316
10317 bind(push);
10318 // After successful lock, push object on lock-stack.
10319 movptr(Address(thread, top), obj);
10320 incrementl(top, oopSize);
10321 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10322 }
10323
10324 // Implements lightweight-unlocking.
10325 //
10326 // obj: the object to be unlocked
10327 // reg_rax: rax
10328 // thread: the thread
10329 // tmp: a temporary register
10330 //
10331 // x86_32 Note: reg_rax and thread may alias each other due to limited register
10332 // availiability.
10333 void MacroAssembler::lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10334 assert(reg_rax == rax, "");
10335 assert_different_registers(obj, reg_rax, tmp);
10336 LP64_ONLY(assert_different_registers(obj, reg_rax, thread, tmp);)
10337
10338 Label unlocked, push_and_slow;
10339 const Register top = tmp;
10340
10341 // Check if obj is top of lock-stack.
10342 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10343 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10344 jcc(Assembler::notEqual, slow);
10345
10346 // Pop lock-stack.
10347 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10348 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10349
10350 // Check if recursive.
10351 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10352 jcc(Assembler::equal, unlocked);
10353
10354 // Not recursive. Check header for monitor (0b10).
10355 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10356 testptr(reg_rax, markWord::monitor_value);
10357 jcc(Assembler::notZero, push_and_slow);
10358
10359 #ifdef ASSERT
10360 // Check header not unlocked (0b01).
10361 Label not_unlocked;
10362 testptr(reg_rax, markWord::unlocked_value);
10363 jcc(Assembler::zero, not_unlocked);
10364 stop("lightweight_unlock already unlocked");
10365 bind(not_unlocked);
10366 #endif
10367
10368 // Try to unlock. Transition lock bits 0b00 => 0b01
10369 movptr(tmp, reg_rax);
10370 orptr(tmp, markWord::unlocked_value);
10371 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10372 jcc(Assembler::equal, unlocked);
10373
10374 bind(push_and_slow);
10375 // Restore lock-stack and handle the unlock in runtime.
10376 if (thread == reg_rax) {
10377 // On x86_32 we may lose the thread.
10378 get_thread(thread);
10379 }
10380 #ifdef ASSERT
10381 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10382 movptr(Address(thread, top), obj);
10383 #endif
10384 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10385 jmp(slow);
10386
10387 bind(unlocked);
10388 }
10389
10390 #ifdef _LP64
10391 // Saves legacy GPRs state on stack.
10392 void MacroAssembler::save_legacy_gprs() {
10393 subq(rsp, 16 * wordSize);
10394 movq(Address(rsp, 15 * wordSize), rax);
10395 movq(Address(rsp, 14 * wordSize), rcx);
10396 movq(Address(rsp, 13 * wordSize), rdx);
10397 movq(Address(rsp, 12 * wordSize), rbx);
10398 movq(Address(rsp, 10 * wordSize), rbp);
10399 movq(Address(rsp, 9 * wordSize), rsi);
10400 movq(Address(rsp, 8 * wordSize), rdi);
10401 movq(Address(rsp, 7 * wordSize), r8);
10402 movq(Address(rsp, 6 * wordSize), r9);
10403 movq(Address(rsp, 5 * wordSize), r10);
10404 movq(Address(rsp, 4 * wordSize), r11);
10405 movq(Address(rsp, 3 * wordSize), r12);
10406 movq(Address(rsp, 2 * wordSize), r13);
10407 movq(Address(rsp, wordSize), r14);
10408 movq(Address(rsp, 0), r15);
10409 }
10410
10411 // Resotres back legacy GPRs state from stack.
10412 void MacroAssembler::restore_legacy_gprs() {
10413 movq(r15, Address(rsp, 0));
10414 movq(r14, Address(rsp, wordSize));
10415 movq(r13, Address(rsp, 2 * wordSize));
10416 movq(r12, Address(rsp, 3 * wordSize));
10417 movq(r11, Address(rsp, 4 * wordSize));
10418 movq(r10, Address(rsp, 5 * wordSize));
10419 movq(r9, Address(rsp, 6 * wordSize));
10420 movq(r8, Address(rsp, 7 * wordSize));
10421 movq(rdi, Address(rsp, 8 * wordSize));
10422 movq(rsi, Address(rsp, 9 * wordSize));
10423 movq(rbp, Address(rsp, 10 * wordSize));
10424 movq(rbx, Address(rsp, 12 * wordSize));
10425 movq(rdx, Address(rsp, 13 * wordSize));
10426 movq(rcx, Address(rsp, 14 * wordSize));
10427 movq(rax, Address(rsp, 15 * wordSize));
10428 addq(rsp, 16 * wordSize);
10429 }
10430 #endif