1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "code/SCCache.hpp"
29 #include "code/compiledIC.hpp"
30 #include "compiler/compiler_globals.hpp"
31 #include "compiler/disassembler.hpp"
32 #include "crc32c.h"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/collectedHeap.inline.hpp"
36 #include "gc/shared/tlab_globals.hpp"
37 #include "interpreter/bytecodeHistogram.hpp"
38 #include "interpreter/interpreter.hpp"
39 #include "interpreter/interpreterRuntime.hpp"
40 #include "jvm.h"
41 #include "memory/resourceArea.hpp"
42 #include "memory/universe.hpp"
43 #include "oops/accessDecorators.hpp"
44 #include "oops/compressedKlass.inline.hpp"
45 #include "oops/compressedOops.inline.hpp"
46 #include "oops/klass.inline.hpp"
47 #include "prims/methodHandles.hpp"
48 #include "runtime/continuation.hpp"
49 #include "runtime/interfaceSupport.inline.hpp"
50 #include "runtime/javaThread.hpp"
51 #include "runtime/jniHandles.hpp"
52 #include "runtime/objectMonitor.hpp"
53 #include "runtime/os.hpp"
54 #include "runtime/safepoint.hpp"
55 #include "runtime/safepointMechanism.hpp"
56 #include "runtime/sharedRuntime.hpp"
57 #include "runtime/stubRoutines.hpp"
58 #include "utilities/checkedCast.hpp"
59 #include "utilities/macros.hpp"
60
61 #ifdef PRODUCT
62 #define BLOCK_COMMENT(str) /* nothing */
63 #define STOP(error) stop(error)
64 #else
65 #define BLOCK_COMMENT(str) block_comment(str)
66 #define STOP(error) block_comment(error); stop(error)
67 #endif
68
69 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
70
71 #ifdef ASSERT
72 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
73 #endif
74
75 static const Assembler::Condition reverse[] = {
76 Assembler::noOverflow /* overflow = 0x0 */ ,
77 Assembler::overflow /* noOverflow = 0x1 */ ,
78 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
79 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
80 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
81 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
82 Assembler::above /* belowEqual = 0x6 */ ,
83 Assembler::belowEqual /* above = 0x7 */ ,
84 Assembler::positive /* negative = 0x8 */ ,
85 Assembler::negative /* positive = 0x9 */ ,
86 Assembler::noParity /* parity = 0xa */ ,
87 Assembler::parity /* noParity = 0xb */ ,
88 Assembler::greaterEqual /* less = 0xc */ ,
89 Assembler::less /* greaterEqual = 0xd */ ,
90 Assembler::greater /* lessEqual = 0xe */ ,
91 Assembler::lessEqual /* greater = 0xf, */
92
93 };
94
95
96 // Implementation of MacroAssembler
97
98 // First all the versions that have distinct versions depending on 32/64 bit
99 // Unless the difference is trivial (1 line or so).
100
101 #ifndef _LP64
102
103 // 32bit versions
104
105 Address MacroAssembler::as_Address(AddressLiteral adr) {
106 return Address(adr.target(), adr.rspec());
107 }
108
109 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
110 assert(rscratch == noreg, "");
111 return Address::make_array(adr);
112 }
113
114 void MacroAssembler::call_VM_leaf_base(address entry_point,
115 int number_of_arguments) {
116 call(RuntimeAddress(entry_point));
117 increment(rsp, number_of_arguments * wordSize);
118 }
119
120 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
121 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
122 }
123
124
125 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
126 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
127 }
128
129 void MacroAssembler::cmpoop(Address src1, jobject obj) {
130 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
131 }
132
133 void MacroAssembler::cmpoop(Register src1, jobject obj, Register rscratch) {
134 assert(rscratch == noreg, "redundant");
135 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
136 }
137
138 void MacroAssembler::extend_sign(Register hi, Register lo) {
139 // According to Intel Doc. AP-526, "Integer Divide", p.18.
140 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
141 cdql();
142 } else {
143 movl(hi, lo);
144 sarl(hi, 31);
145 }
146 }
147
148 void MacroAssembler::jC2(Register tmp, Label& L) {
149 // set parity bit if FPU flag C2 is set (via rax)
150 save_rax(tmp);
151 fwait(); fnstsw_ax();
152 sahf();
153 restore_rax(tmp);
154 // branch
155 jcc(Assembler::parity, L);
156 }
157
158 void MacroAssembler::jnC2(Register tmp, Label& L) {
159 // set parity bit if FPU flag C2 is set (via rax)
160 save_rax(tmp);
161 fwait(); fnstsw_ax();
162 sahf();
163 restore_rax(tmp);
164 // branch
165 jcc(Assembler::noParity, L);
166 }
167
168 // 32bit can do a case table jump in one instruction but we no longer allow the base
169 // to be installed in the Address class
170 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
171 assert(rscratch == noreg, "not needed");
172 jmp(as_Address(entry, noreg));
173 }
174
175 // Note: y_lo will be destroyed
176 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
177 // Long compare for Java (semantics as described in JVM spec.)
178 Label high, low, done;
179
180 cmpl(x_hi, y_hi);
181 jcc(Assembler::less, low);
182 jcc(Assembler::greater, high);
183 // x_hi is the return register
184 xorl(x_hi, x_hi);
185 cmpl(x_lo, y_lo);
186 jcc(Assembler::below, low);
187 jcc(Assembler::equal, done);
188
189 bind(high);
190 xorl(x_hi, x_hi);
191 increment(x_hi);
192 jmp(done);
193
194 bind(low);
195 xorl(x_hi, x_hi);
196 decrementl(x_hi);
197
198 bind(done);
199 }
200
201 void MacroAssembler::lea(Register dst, AddressLiteral src) {
202 mov_literal32(dst, (int32_t)src.target(), src.rspec());
203 }
204
205 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
206 assert(rscratch == noreg, "not needed");
207
208 // leal(dst, as_Address(adr));
209 // see note in movl as to why we must use a move
210 mov_literal32(dst, (int32_t)adr.target(), adr.rspec());
211 }
212
213 void MacroAssembler::leave() {
214 mov(rsp, rbp);
215 pop(rbp);
216 }
217
218 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
219 // Multiplication of two Java long values stored on the stack
220 // as illustrated below. Result is in rdx:rax.
221 //
222 // rsp ---> [ ?? ] \ \
223 // .... | y_rsp_offset |
224 // [ y_lo ] / (in bytes) | x_rsp_offset
225 // [ y_hi ] | (in bytes)
226 // .... |
227 // [ x_lo ] /
228 // [ x_hi ]
229 // ....
230 //
231 // Basic idea: lo(result) = lo(x_lo * y_lo)
232 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
233 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
234 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
235 Label quick;
236 // load x_hi, y_hi and check if quick
237 // multiplication is possible
238 movl(rbx, x_hi);
239 movl(rcx, y_hi);
240 movl(rax, rbx);
241 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
242 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
243 // do full multiplication
244 // 1st step
245 mull(y_lo); // x_hi * y_lo
246 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
247 // 2nd step
248 movl(rax, x_lo);
249 mull(rcx); // x_lo * y_hi
250 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
251 // 3rd step
252 bind(quick); // note: rbx, = 0 if quick multiply!
253 movl(rax, x_lo);
254 mull(y_lo); // x_lo * y_lo
255 addl(rdx, rbx); // correct hi(x_lo * y_lo)
256 }
257
258 void MacroAssembler::lneg(Register hi, Register lo) {
259 negl(lo);
260 adcl(hi, 0);
261 negl(hi);
262 }
263
264 void MacroAssembler::lshl(Register hi, Register lo) {
265 // Java shift left long support (semantics as described in JVM spec., p.305)
266 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
267 // shift value is in rcx !
268 assert(hi != rcx, "must not use rcx");
269 assert(lo != rcx, "must not use rcx");
270 const Register s = rcx; // shift count
271 const int n = BitsPerWord;
272 Label L;
273 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
274 cmpl(s, n); // if (s < n)
275 jcc(Assembler::less, L); // else (s >= n)
276 movl(hi, lo); // x := x << n
277 xorl(lo, lo);
278 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
279 bind(L); // s (mod n) < n
280 shldl(hi, lo); // x := x << s
281 shll(lo);
282 }
283
284
285 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
286 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
287 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
288 assert(hi != rcx, "must not use rcx");
289 assert(lo != rcx, "must not use rcx");
290 const Register s = rcx; // shift count
291 const int n = BitsPerWord;
292 Label L;
293 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
294 cmpl(s, n); // if (s < n)
295 jcc(Assembler::less, L); // else (s >= n)
296 movl(lo, hi); // x := x >> n
297 if (sign_extension) sarl(hi, 31);
298 else xorl(hi, hi);
299 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
300 bind(L); // s (mod n) < n
301 shrdl(lo, hi); // x := x >> s
302 if (sign_extension) sarl(hi);
303 else shrl(hi);
304 }
305
306 void MacroAssembler::movoop(Register dst, jobject obj) {
307 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
308 }
309
310 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
311 assert(rscratch == noreg, "redundant");
312 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
313 }
314
315 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
316 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
317 }
318
319 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
320 assert(rscratch == noreg, "redundant");
321 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
322 }
323
324 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
325 if (src.is_lval()) {
326 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
327 } else {
328 movl(dst, as_Address(src));
329 }
330 }
331
332 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
333 assert(rscratch == noreg, "redundant");
334 movl(as_Address(dst, noreg), src);
335 }
336
337 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
338 movl(dst, as_Address(src, noreg));
339 }
340
341 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
342 assert(rscratch == noreg, "redundant");
343 movl(dst, src);
344 }
345
346 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
347 assert(rscratch == noreg, "redundant");
348 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
349 }
350
351 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
352 assert(rscratch == noreg, "redundant");
353 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
354 }
355
356 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
357 assert(rscratch == noreg, "redundant");
358 if (src.is_lval()) {
359 push_literal32((int32_t)src.target(), src.rspec());
360 } else {
361 pushl(as_Address(src));
362 }
363 }
364
365 static void pass_arg0(MacroAssembler* masm, Register arg) {
366 masm->push(arg);
367 }
368
369 static void pass_arg1(MacroAssembler* masm, Register arg) {
370 masm->push(arg);
371 }
372
373 static void pass_arg2(MacroAssembler* masm, Register arg) {
374 masm->push(arg);
375 }
376
377 static void pass_arg3(MacroAssembler* masm, Register arg) {
378 masm->push(arg);
379 }
380
381 #ifndef PRODUCT
382 extern "C" void findpc(intptr_t x);
383 #endif
384
385 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
386 // In order to get locks to work, we need to fake a in_VM state
387 JavaThread* thread = JavaThread::current();
388 JavaThreadState saved_state = thread->thread_state();
389 thread->set_thread_state(_thread_in_vm);
390 if (ShowMessageBoxOnError) {
391 JavaThread* thread = JavaThread::current();
392 JavaThreadState saved_state = thread->thread_state();
393 thread->set_thread_state(_thread_in_vm);
394 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
395 ttyLocker ttyl;
396 BytecodeCounter::print();
397 }
398 // To see where a verify_oop failed, get $ebx+40/X for this frame.
399 // This is the value of eip which points to where verify_oop will return.
400 if (os::message_box(msg, "Execution stopped, print registers?")) {
401 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
402 BREAKPOINT;
403 }
404 }
405 fatal("DEBUG MESSAGE: %s", msg);
406 }
407
408 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
409 ttyLocker ttyl;
410 DebuggingContext debugging{};
411 tty->print_cr("eip = 0x%08x", eip);
412 #ifndef PRODUCT
413 if ((WizardMode || Verbose) && PrintMiscellaneous) {
414 tty->cr();
415 findpc(eip);
416 tty->cr();
417 }
418 #endif
419 #define PRINT_REG(rax) \
420 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
421 PRINT_REG(rax);
422 PRINT_REG(rbx);
423 PRINT_REG(rcx);
424 PRINT_REG(rdx);
425 PRINT_REG(rdi);
426 PRINT_REG(rsi);
427 PRINT_REG(rbp);
428 PRINT_REG(rsp);
429 #undef PRINT_REG
430 // Print some words near top of staack.
431 int* dump_sp = (int*) rsp;
432 for (int col1 = 0; col1 < 8; col1++) {
433 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
434 os::print_location(tty, *dump_sp++);
435 }
436 for (int row = 0; row < 16; row++) {
437 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
438 for (int col = 0; col < 8; col++) {
439 tty->print(" 0x%08x", *dump_sp++);
440 }
441 tty->cr();
442 }
443 // Print some instructions around pc:
444 Disassembler::decode((address)eip-64, (address)eip);
445 tty->print_cr("--------");
446 Disassembler::decode((address)eip, (address)eip+32);
447 }
448
449 void MacroAssembler::stop(const char* msg) {
450 // push address of message
451 ExternalAddress message((address)msg);
452 pushptr(message.addr(), noreg);
453 { Label L; call(L, relocInfo::none); bind(L); } // push eip
454 pusha(); // push registers
455 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
456 hlt();
457 }
458
459 void MacroAssembler::warn(const char* msg) {
460 push_CPU_state();
461
462 // push address of message
463 ExternalAddress message((address)msg);
464 pushptr(message.addr(), noreg);
465
466 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
467 addl(rsp, wordSize); // discard argument
468 pop_CPU_state();
469 }
470
471 void MacroAssembler::print_state() {
472 { Label L; call(L, relocInfo::none); bind(L); } // push eip
473 pusha(); // push registers
474
475 push_CPU_state();
476 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
477 pop_CPU_state();
478
479 popa();
480 addl(rsp, wordSize);
481 }
482
483 #else // _LP64
484
485 // 64 bit versions
486
487 Address MacroAssembler::as_Address(AddressLiteral adr) {
488 // amd64 always does this as a pc-rel
489 // we can be absolute or disp based on the instruction type
490 // jmp/call are displacements others are absolute
491 assert(!adr.is_lval(), "must be rval");
492 assert(reachable(adr), "must be");
493 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
494
495 }
496
497 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
498 AddressLiteral base = adr.base();
499 lea(rscratch, base);
500 Address index = adr.index();
501 assert(index._disp == 0, "must not have disp"); // maybe it can?
502 Address array(rscratch, index._index, index._scale, index._disp);
503 return array;
504 }
505
506 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
507 Label L, E;
508
509 #ifdef _WIN64
510 // Windows always allocates space for it's register args
511 assert(num_args <= 4, "only register arguments supported");
512 subq(rsp, frame::arg_reg_save_area_bytes);
513 #endif
514
515 // Align stack if necessary
516 testl(rsp, 15);
517 jcc(Assembler::zero, L);
518
519 subq(rsp, 8);
520 call(RuntimeAddress(entry_point));
521 addq(rsp, 8);
522 jmp(E);
523
524 bind(L);
525 call(RuntimeAddress(entry_point));
526
527 bind(E);
528
529 #ifdef _WIN64
530 // restore stack pointer
531 addq(rsp, frame::arg_reg_save_area_bytes);
532 #endif
533 }
534
535 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
536 assert(!src2.is_lval(), "should use cmpptr");
537 assert(rscratch != noreg || always_reachable(src2), "missing");
538
539 if (reachable(src2)) {
540 cmpq(src1, as_Address(src2));
541 } else {
542 lea(rscratch, src2);
543 Assembler::cmpq(src1, Address(rscratch, 0));
544 }
545 }
546
547 int MacroAssembler::corrected_idivq(Register reg) {
548 // Full implementation of Java ldiv and lrem; checks for special
549 // case as described in JVM spec., p.243 & p.271. The function
550 // returns the (pc) offset of the idivl instruction - may be needed
551 // for implicit exceptions.
552 //
553 // normal case special case
554 //
555 // input : rax: dividend min_long
556 // reg: divisor (may not be eax/edx) -1
557 //
558 // output: rax: quotient (= rax idiv reg) min_long
559 // rdx: remainder (= rax irem reg) 0
560 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
561 static const int64_t min_long = 0x8000000000000000;
562 Label normal_case, special_case;
563
564 // check for special case
565 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
566 jcc(Assembler::notEqual, normal_case);
567 xorl(rdx, rdx); // prepare rdx for possible special case (where
568 // remainder = 0)
569 cmpq(reg, -1);
570 jcc(Assembler::equal, special_case);
571
572 // handle normal case
573 bind(normal_case);
574 cdqq();
575 int idivq_offset = offset();
576 idivq(reg);
577
578 // normal and special case exit
579 bind(special_case);
580
581 return idivq_offset;
582 }
583
584 void MacroAssembler::decrementq(Register reg, int value) {
585 if (value == min_jint) { subq(reg, value); return; }
586 if (value < 0) { incrementq(reg, -value); return; }
587 if (value == 0) { ; return; }
588 if (value == 1 && UseIncDec) { decq(reg) ; return; }
589 /* else */ { subq(reg, value) ; return; }
590 }
591
592 void MacroAssembler::decrementq(Address dst, int value) {
593 if (value == min_jint) { subq(dst, value); return; }
594 if (value < 0) { incrementq(dst, -value); return; }
595 if (value == 0) { ; return; }
596 if (value == 1 && UseIncDec) { decq(dst) ; return; }
597 /* else */ { subq(dst, value) ; return; }
598 }
599
600 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
601 assert(rscratch != noreg || always_reachable(dst), "missing");
602
603 if (reachable(dst)) {
604 incrementq(as_Address(dst));
605 } else {
606 lea(rscratch, dst);
607 incrementq(Address(rscratch, 0));
608 }
609 }
610
611 void MacroAssembler::incrementq(Register reg, int value) {
612 if (value == min_jint) { addq(reg, value); return; }
613 if (value < 0) { decrementq(reg, -value); return; }
614 if (value == 0) { ; return; }
615 if (value == 1 && UseIncDec) { incq(reg) ; return; }
616 /* else */ { addq(reg, value) ; return; }
617 }
618
619 void MacroAssembler::incrementq(Address dst, int value) {
620 if (value == min_jint) { addq(dst, value); return; }
621 if (value < 0) { decrementq(dst, -value); return; }
622 if (value == 0) { ; return; }
623 if (value == 1 && UseIncDec) { incq(dst) ; return; }
624 /* else */ { addq(dst, value) ; return; }
625 }
626
627 // 32bit can do a case table jump in one instruction but we no longer allow the base
628 // to be installed in the Address class
629 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
630 lea(rscratch, entry.base());
631 Address dispatch = entry.index();
632 assert(dispatch._base == noreg, "must be");
633 dispatch._base = rscratch;
634 jmp(dispatch);
635 }
636
637 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
638 ShouldNotReachHere(); // 64bit doesn't use two regs
639 cmpq(x_lo, y_lo);
640 }
641
642 void MacroAssembler::lea(Register dst, AddressLiteral src) {
643 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
644 }
645
646 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
647 lea(rscratch, adr);
648 movptr(dst, rscratch);
649 }
650
651 void MacroAssembler::leave() {
652 // %%% is this really better? Why not on 32bit too?
653 emit_int8((unsigned char)0xC9); // LEAVE
654 }
655
656 void MacroAssembler::lneg(Register hi, Register lo) {
657 ShouldNotReachHere(); // 64bit doesn't use two regs
658 negq(lo);
659 }
660
661 void MacroAssembler::movoop(Register dst, jobject obj) {
662 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
663 }
664
665 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
666 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
667 movq(dst, rscratch);
668 }
669
670 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
671 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
672 }
673
674 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
675 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
676 movq(dst, rscratch);
677 }
678
679 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
680 if (src.is_lval()) {
681 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
682 } else {
683 if (reachable(src)) {
684 movq(dst, as_Address(src));
685 } else {
686 lea(dst, src);
687 movq(dst, Address(dst, 0));
688 }
689 }
690 }
691
692 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
693 movq(as_Address(dst, rscratch), src);
694 }
695
696 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
697 movq(dst, as_Address(src, dst /*rscratch*/));
698 }
699
700 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
701 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
702 if (is_simm32(src)) {
703 movptr(dst, checked_cast<int32_t>(src));
704 } else {
705 mov64(rscratch, src);
706 movq(dst, rscratch);
707 }
708 }
709
710 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
711 movoop(rscratch, obj);
712 push(rscratch);
713 }
714
715 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
716 mov_metadata(rscratch, obj);
717 push(rscratch);
718 }
719
720 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
721 lea(rscratch, src);
722 if (src.is_lval()) {
723 push(rscratch);
724 } else {
725 pushq(Address(rscratch, 0));
726 }
727 }
728
729 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
730 reset_last_Java_frame(r15_thread, clear_fp);
731 }
732
733 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
734 Register last_java_fp,
735 address last_java_pc,
736 Register rscratch) {
737 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, last_java_pc, rscratch);
738 }
739
740 static void pass_arg0(MacroAssembler* masm, Register arg) {
741 if (c_rarg0 != arg ) {
742 masm->mov(c_rarg0, arg);
743 }
744 }
745
746 static void pass_arg1(MacroAssembler* masm, Register arg) {
747 if (c_rarg1 != arg ) {
748 masm->mov(c_rarg1, arg);
749 }
750 }
751
752 static void pass_arg2(MacroAssembler* masm, Register arg) {
753 if (c_rarg2 != arg ) {
754 masm->mov(c_rarg2, arg);
755 }
756 }
757
758 static void pass_arg3(MacroAssembler* masm, Register arg) {
759 if (c_rarg3 != arg ) {
760 masm->mov(c_rarg3, arg);
761 }
762 }
763
764 void MacroAssembler::stop(const char* msg) {
765 if (ShowMessageBoxOnError) {
766 address rip = pc();
767 pusha(); // get regs on stack
768 lea(c_rarg1, InternalAddress(rip));
769 movq(c_rarg2, rsp); // pass pointer to regs array
770 }
771 lea(c_rarg0, ExternalAddress((address) msg));
772 andq(rsp, -16); // align stack as required by ABI
773 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
774 hlt();
775 SCCache::add_C_string(msg);
776 }
777
778 void MacroAssembler::warn(const char* msg) {
779 push(rbp);
780 movq(rbp, rsp);
781 andq(rsp, -16); // align stack as required by push_CPU_state and call
782 push_CPU_state(); // keeps alignment at 16 bytes
783
784 lea(c_rarg0, ExternalAddress((address) msg));
785 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
786
787 pop_CPU_state();
788 mov(rsp, rbp);
789 pop(rbp);
790 }
791
792 void MacroAssembler::print_state() {
793 address rip = pc();
794 pusha(); // get regs on stack
795 push(rbp);
796 movq(rbp, rsp);
797 andq(rsp, -16); // align stack as required by push_CPU_state and call
798 push_CPU_state(); // keeps alignment at 16 bytes
799
800 lea(c_rarg0, InternalAddress(rip));
801 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
802 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
803
804 pop_CPU_state();
805 mov(rsp, rbp);
806 pop(rbp);
807 popa();
808 }
809
810 #ifndef PRODUCT
811 extern "C" void findpc(intptr_t x);
812 #endif
813
814 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
815 // In order to get locks to work, we need to fake a in_VM state
816 if (ShowMessageBoxOnError) {
817 JavaThread* thread = JavaThread::current();
818 JavaThreadState saved_state = thread->thread_state();
819 thread->set_thread_state(_thread_in_vm);
820 #ifndef PRODUCT
821 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
822 ttyLocker ttyl;
823 BytecodeCounter::print();
824 }
825 #endif
826 // To see where a verify_oop failed, get $ebx+40/X for this frame.
827 // XXX correct this offset for amd64
828 // This is the value of eip which points to where verify_oop will return.
829 if (os::message_box(msg, "Execution stopped, print registers?")) {
830 print_state64(pc, regs);
831 BREAKPOINT;
832 }
833 }
834 fatal("DEBUG MESSAGE: %s", msg);
835 }
836
837 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
838 ttyLocker ttyl;
839 DebuggingContext debugging{};
840 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
841 #ifndef PRODUCT
842 tty->cr();
843 findpc(pc);
844 tty->cr();
845 #endif
846 #define PRINT_REG(rax, value) \
847 { tty->print("%s = ", #rax); os::print_location(tty, value); }
848 PRINT_REG(rax, regs[15]);
849 PRINT_REG(rbx, regs[12]);
850 PRINT_REG(rcx, regs[14]);
851 PRINT_REG(rdx, regs[13]);
852 PRINT_REG(rdi, regs[8]);
853 PRINT_REG(rsi, regs[9]);
854 PRINT_REG(rbp, regs[10]);
855 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
856 PRINT_REG(rsp, (intptr_t)(®s[16]));
857 PRINT_REG(r8 , regs[7]);
858 PRINT_REG(r9 , regs[6]);
859 PRINT_REG(r10, regs[5]);
860 PRINT_REG(r11, regs[4]);
861 PRINT_REG(r12, regs[3]);
862 PRINT_REG(r13, regs[2]);
863 PRINT_REG(r14, regs[1]);
864 PRINT_REG(r15, regs[0]);
865 #undef PRINT_REG
866 // Print some words near the top of the stack.
867 int64_t* rsp = ®s[16];
868 int64_t* dump_sp = rsp;
869 for (int col1 = 0; col1 < 8; col1++) {
870 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
871 os::print_location(tty, *dump_sp++);
872 }
873 for (int row = 0; row < 25; row++) {
874 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
875 for (int col = 0; col < 4; col++) {
876 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
877 }
878 tty->cr();
879 }
880 // Print some instructions around pc:
881 Disassembler::decode((address)pc-64, (address)pc);
882 tty->print_cr("--------");
883 Disassembler::decode((address)pc, (address)pc+32);
884 }
885
886 // The java_calling_convention describes stack locations as ideal slots on
887 // a frame with no abi restrictions. Since we must observe abi restrictions
888 // (like the placement of the register window) the slots must be biased by
889 // the following value.
890 static int reg2offset_in(VMReg r) {
891 // Account for saved rbp and return address
892 // This should really be in_preserve_stack_slots
893 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
894 }
895
896 static int reg2offset_out(VMReg r) {
897 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
898 }
899
900 // A long move
901 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
902
903 // The calling conventions assures us that each VMregpair is either
904 // all really one physical register or adjacent stack slots.
905
906 if (src.is_single_phys_reg() ) {
907 if (dst.is_single_phys_reg()) {
908 if (dst.first() != src.first()) {
909 mov(dst.first()->as_Register(), src.first()->as_Register());
910 }
911 } else {
912 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
913 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
914 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
915 }
916 } else if (dst.is_single_phys_reg()) {
917 assert(src.is_single_reg(), "not a stack pair");
918 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
919 } else {
920 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
921 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
922 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
923 }
924 }
925
926 // A double move
927 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
928
929 // The calling conventions assures us that each VMregpair is either
930 // all really one physical register or adjacent stack slots.
931
932 if (src.is_single_phys_reg() ) {
933 if (dst.is_single_phys_reg()) {
934 // In theory these overlap but the ordering is such that this is likely a nop
935 if ( src.first() != dst.first()) {
936 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
937 }
938 } else {
939 assert(dst.is_single_reg(), "not a stack pair");
940 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
941 }
942 } else if (dst.is_single_phys_reg()) {
943 assert(src.is_single_reg(), "not a stack pair");
944 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
945 } else {
946 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
947 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
948 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
949 }
950 }
951
952
953 // A float arg may have to do float reg int reg conversion
954 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
955 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
956
957 // The calling conventions assures us that each VMregpair is either
958 // all really one physical register or adjacent stack slots.
959
960 if (src.first()->is_stack()) {
961 if (dst.first()->is_stack()) {
962 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
963 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
964 } else {
965 // stack to reg
966 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
967 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
968 }
969 } else if (dst.first()->is_stack()) {
970 // reg to stack
971 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
972 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
973 } else {
974 // reg to reg
975 // In theory these overlap but the ordering is such that this is likely a nop
976 if ( src.first() != dst.first()) {
977 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
978 }
979 }
980 }
981
982 // On 64 bit we will store integer like items to the stack as
983 // 64 bits items (x86_32/64 abi) even though java would only store
984 // 32bits for a parameter. On 32bit it will simply be 32 bits
985 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
986 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
987 if (src.first()->is_stack()) {
988 if (dst.first()->is_stack()) {
989 // stack to stack
990 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
991 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
992 } else {
993 // stack to reg
994 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
995 }
996 } else if (dst.first()->is_stack()) {
997 // reg to stack
998 // Do we really have to sign extend???
999 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1000 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
1001 } else {
1002 // Do we really have to sign extend???
1003 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1004 if (dst.first() != src.first()) {
1005 movq(dst.first()->as_Register(), src.first()->as_Register());
1006 }
1007 }
1008 }
1009
1010 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1011 if (src.first()->is_stack()) {
1012 if (dst.first()->is_stack()) {
1013 // stack to stack
1014 movq(rax, Address(rbp, reg2offset_in(src.first())));
1015 movq(Address(rsp, reg2offset_out(dst.first())), rax);
1016 } else {
1017 // stack to reg
1018 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1019 }
1020 } else if (dst.first()->is_stack()) {
1021 // reg to stack
1022 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1023 } else {
1024 if (dst.first() != src.first()) {
1025 movq(dst.first()->as_Register(), src.first()->as_Register());
1026 }
1027 }
1028 }
1029
1030 // An oop arg. Must pass a handle not the oop itself
1031 void MacroAssembler::object_move(OopMap* map,
1032 int oop_handle_offset,
1033 int framesize_in_slots,
1034 VMRegPair src,
1035 VMRegPair dst,
1036 bool is_receiver,
1037 int* receiver_offset) {
1038
1039 // must pass a handle. First figure out the location we use as a handle
1040
1041 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1042
1043 // See if oop is null if it is we need no handle
1044
1045 if (src.first()->is_stack()) {
1046
1047 // Oop is already on the stack as an argument
1048 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1049 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1050 if (is_receiver) {
1051 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1052 }
1053
1054 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
1055 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1056 // conditionally move a null
1057 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1058 } else {
1059
1060 // Oop is in a register we must store it to the space we reserve
1061 // on the stack for oop_handles and pass a handle if oop is non-null
1062
1063 const Register rOop = src.first()->as_Register();
1064 int oop_slot;
1065 if (rOop == j_rarg0)
1066 oop_slot = 0;
1067 else if (rOop == j_rarg1)
1068 oop_slot = 1;
1069 else if (rOop == j_rarg2)
1070 oop_slot = 2;
1071 else if (rOop == j_rarg3)
1072 oop_slot = 3;
1073 else if (rOop == j_rarg4)
1074 oop_slot = 4;
1075 else {
1076 assert(rOop == j_rarg5, "wrong register");
1077 oop_slot = 5;
1078 }
1079
1080 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1081 int offset = oop_slot*VMRegImpl::stack_slot_size;
1082
1083 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1084 // Store oop in handle area, may be null
1085 movptr(Address(rsp, offset), rOop);
1086 if (is_receiver) {
1087 *receiver_offset = offset;
1088 }
1089
1090 cmpptr(rOop, NULL_WORD);
1091 lea(rHandle, Address(rsp, offset));
1092 // conditionally move a null from the handle area where it was just stored
1093 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1094 }
1095
1096 // If arg is on the stack then place it otherwise it is already in correct reg.
1097 if (dst.first()->is_stack()) {
1098 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1099 }
1100 }
1101
1102 #endif // _LP64
1103
1104 // Now versions that are common to 32/64 bit
1105
1106 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1107 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1108 }
1109
1110 void MacroAssembler::addptr(Register dst, Register src) {
1111 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1112 }
1113
1114 void MacroAssembler::addptr(Address dst, Register src) {
1115 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1116 }
1117
1118 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1119 assert(rscratch != noreg || always_reachable(src), "missing");
1120
1121 if (reachable(src)) {
1122 Assembler::addsd(dst, as_Address(src));
1123 } else {
1124 lea(rscratch, src);
1125 Assembler::addsd(dst, Address(rscratch, 0));
1126 }
1127 }
1128
1129 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1130 assert(rscratch != noreg || always_reachable(src), "missing");
1131
1132 if (reachable(src)) {
1133 addss(dst, as_Address(src));
1134 } else {
1135 lea(rscratch, src);
1136 addss(dst, Address(rscratch, 0));
1137 }
1138 }
1139
1140 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1141 assert(rscratch != noreg || always_reachable(src), "missing");
1142
1143 if (reachable(src)) {
1144 Assembler::addpd(dst, as_Address(src));
1145 } else {
1146 lea(rscratch, src);
1147 Assembler::addpd(dst, Address(rscratch, 0));
1148 }
1149 }
1150
1151 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
1152 // Stub code is generated once and never copied.
1153 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1154 void MacroAssembler::align64() {
1155 align(64, (uint)(uintptr_t)pc());
1156 }
1157
1158 void MacroAssembler::align32() {
1159 align(32, (uint)(uintptr_t)pc());
1160 }
1161
1162 void MacroAssembler::align(uint modulus) {
1163 // 8273459: Ensure alignment is possible with current segment alignment
1164 assert(modulus <= (uintx)CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1165 align(modulus, offset());
1166 }
1167
1168 void MacroAssembler::align(uint modulus, uint target) {
1169 if (target % modulus != 0) {
1170 nop(modulus - (target % modulus));
1171 }
1172 }
1173
1174 void MacroAssembler::push_f(XMMRegister r) {
1175 subptr(rsp, wordSize);
1176 movflt(Address(rsp, 0), r);
1177 }
1178
1179 void MacroAssembler::pop_f(XMMRegister r) {
1180 movflt(r, Address(rsp, 0));
1181 addptr(rsp, wordSize);
1182 }
1183
1184 void MacroAssembler::push_d(XMMRegister r) {
1185 subptr(rsp, 2 * wordSize);
1186 movdbl(Address(rsp, 0), r);
1187 }
1188
1189 void MacroAssembler::pop_d(XMMRegister r) {
1190 movdbl(r, Address(rsp, 0));
1191 addptr(rsp, 2 * Interpreter::stackElementSize);
1192 }
1193
1194 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1195 // Used in sign-masking with aligned address.
1196 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1197 assert(rscratch != noreg || always_reachable(src), "missing");
1198
1199 if (reachable(src)) {
1200 Assembler::andpd(dst, as_Address(src));
1201 } else {
1202 lea(rscratch, src);
1203 Assembler::andpd(dst, Address(rscratch, 0));
1204 }
1205 }
1206
1207 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
1208 // Used in sign-masking with aligned address.
1209 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1210 assert(rscratch != noreg || always_reachable(src), "missing");
1211
1212 if (reachable(src)) {
1213 Assembler::andps(dst, as_Address(src));
1214 } else {
1215 lea(rscratch, src);
1216 Assembler::andps(dst, Address(rscratch, 0));
1217 }
1218 }
1219
1220 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1221 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1222 }
1223
1224 #ifdef _LP64
1225 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
1226 assert(rscratch != noreg || always_reachable(src), "missing");
1227
1228 if (reachable(src)) {
1229 andq(dst, as_Address(src));
1230 } else {
1231 lea(rscratch, src);
1232 andq(dst, Address(rscratch, 0));
1233 }
1234 }
1235 #endif
1236
1237 void MacroAssembler::atomic_incl(Address counter_addr) {
1238 lock();
1239 incrementl(counter_addr);
1240 }
1241
1242 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
1243 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1244
1245 if (reachable(counter_addr)) {
1246 atomic_incl(as_Address(counter_addr));
1247 } else {
1248 lea(rscratch, counter_addr);
1249 atomic_incl(Address(rscratch, 0));
1250 }
1251 }
1252
1253 #ifdef _LP64
1254 void MacroAssembler::atomic_incq(Address counter_addr) {
1255 lock();
1256 incrementq(counter_addr);
1257 }
1258
1259 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
1260 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1261
1262 if (reachable(counter_addr)) {
1263 atomic_incq(as_Address(counter_addr));
1264 } else {
1265 lea(rscratch, counter_addr);
1266 atomic_incq(Address(rscratch, 0));
1267 }
1268 }
1269 #endif
1270
1271 // Writes to stack successive pages until offset reached to check for
1272 // stack overflow + shadow pages. This clobbers tmp.
1273 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1274 movptr(tmp, rsp);
1275 // Bang stack for total size given plus shadow page size.
1276 // Bang one page at a time because large size can bang beyond yellow and
1277 // red zones.
1278 Label loop;
1279 bind(loop);
1280 movl(Address(tmp, (-(int)os::vm_page_size())), size );
1281 subptr(tmp, (int)os::vm_page_size());
1282 subl(size, (int)os::vm_page_size());
1283 jcc(Assembler::greater, loop);
1284
1285 // Bang down shadow pages too.
1286 // At this point, (tmp-0) is the last address touched, so don't
1287 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1288 // was post-decremented.) Skip this address by starting at i=1, and
1289 // touch a few more pages below. N.B. It is important to touch all
1290 // the way down including all pages in the shadow zone.
1291 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
1292 // this could be any sized move but this is can be a debugging crumb
1293 // so the bigger the better.
1294 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
1295 }
1296 }
1297
1298 void MacroAssembler::reserved_stack_check() {
1299 // testing if reserved zone needs to be enabled
1300 Label no_reserved_zone_enabling;
1301 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1302 NOT_LP64(get_thread(rsi);)
1303
1304 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1305 jcc(Assembler::below, no_reserved_zone_enabling);
1306
1307 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1308 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
1309 should_not_reach_here();
1310
1311 bind(no_reserved_zone_enabling);
1312 }
1313
1314 void MacroAssembler::c2bool(Register x) {
1315 // implements x == 0 ? 0 : 1
1316 // note: must only look at least-significant byte of x
1317 // since C-style booleans are stored in one byte
1318 // only! (was bug)
1319 andl(x, 0xFF);
1320 setb(Assembler::notZero, x);
1321 }
1322
1323 // Wouldn't need if AddressLiteral version had new name
1324 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1325 Assembler::call(L, rtype);
1326 }
1327
1328 void MacroAssembler::call(Register entry) {
1329 Assembler::call(entry);
1330 }
1331
1332 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
1333 assert(rscratch != noreg || always_reachable(entry), "missing");
1334
1335 if (reachable(entry)) {
1336 Assembler::call_literal(entry.target(), entry.rspec());
1337 } else {
1338 lea(rscratch, entry);
1339 Assembler::call(rscratch);
1340 }
1341 }
1342
1343 void MacroAssembler::ic_call(address entry, jint method_index) {
1344 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1345 #ifdef _LP64
1346 // Needs full 64-bit immediate for later patching.
1347 mov64(rax, (int64_t)Universe::non_oop_word());
1348 #else
1349 movptr(rax, (intptr_t)Universe::non_oop_word());
1350 #endif
1351 call(AddressLiteral(entry, rh));
1352 }
1353
1354 int MacroAssembler::ic_check_size() {
1355 return
1356 LP64_ONLY(UseCompactObjectHeaders ? 17 : 14) NOT_LP64(12);
1357 }
1358
1359 int MacroAssembler::ic_check(int end_alignment) {
1360 Register receiver = LP64_ONLY(j_rarg0) NOT_LP64(rcx);
1361 Register data = rax;
1362 Register temp = LP64_ONLY(rscratch1) NOT_LP64(rbx);
1363
1364 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1365 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1366 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1367 // before the inline cache check here, and not after
1368 align(end_alignment, offset() + ic_check_size());
1369
1370 int uep_offset = offset();
1371
1372 #ifdef _LP64
1373 if (UseCompactObjectHeaders) {
1374 load_narrow_klass_compact(temp, receiver);
1375 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1376 } else
1377 #endif
1378 if (UseCompressedClassPointers) {
1379 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1380 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1381 } else {
1382 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1383 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
1384 }
1385
1386 // if inline cache check fails, then jump to runtime routine
1387 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1388 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
1389
1390 return uep_offset;
1391 }
1392
1393 void MacroAssembler::emit_static_call_stub() {
1394 // Static stub relocation also tags the Method* in the code-stream.
1395 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1396 // This is recognized as unresolved by relocs/nativeinst/ic code.
1397 jump(RuntimeAddress(pc()));
1398 }
1399
1400 // Implementation of call_VM versions
1401
1402 void MacroAssembler::call_VM(Register oop_result,
1403 address entry_point,
1404 bool check_exceptions) {
1405 Label C, E;
1406 call(C, relocInfo::none);
1407 jmp(E);
1408
1409 bind(C);
1410 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1411 ret(0);
1412
1413 bind(E);
1414 }
1415
1416 void MacroAssembler::call_VM(Register oop_result,
1417 address entry_point,
1418 Register arg_1,
1419 bool check_exceptions) {
1420 Label C, E;
1421 call(C, relocInfo::none);
1422 jmp(E);
1423
1424 bind(C);
1425 pass_arg1(this, arg_1);
1426 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1427 ret(0);
1428
1429 bind(E);
1430 }
1431
1432 void MacroAssembler::call_VM(Register oop_result,
1433 address entry_point,
1434 Register arg_1,
1435 Register arg_2,
1436 bool check_exceptions) {
1437 Label C, E;
1438 call(C, relocInfo::none);
1439 jmp(E);
1440
1441 bind(C);
1442
1443 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1444
1445 pass_arg2(this, arg_2);
1446 pass_arg1(this, arg_1);
1447 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1448 ret(0);
1449
1450 bind(E);
1451 }
1452
1453 void MacroAssembler::call_VM(Register oop_result,
1454 address entry_point,
1455 Register arg_1,
1456 Register arg_2,
1457 Register arg_3,
1458 bool check_exceptions) {
1459 Label C, E;
1460 call(C, relocInfo::none);
1461 jmp(E);
1462
1463 bind(C);
1464
1465 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1466 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1467 pass_arg3(this, arg_3);
1468 pass_arg2(this, arg_2);
1469 pass_arg1(this, arg_1);
1470 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1471 ret(0);
1472
1473 bind(E);
1474 }
1475
1476 void MacroAssembler::call_VM(Register oop_result,
1477 Register last_java_sp,
1478 address entry_point,
1479 int number_of_arguments,
1480 bool check_exceptions) {
1481 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1482 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1483 }
1484
1485 void MacroAssembler::call_VM(Register oop_result,
1486 Register last_java_sp,
1487 address entry_point,
1488 Register arg_1,
1489 bool check_exceptions) {
1490 pass_arg1(this, arg_1);
1491 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1492 }
1493
1494 void MacroAssembler::call_VM(Register oop_result,
1495 Register last_java_sp,
1496 address entry_point,
1497 Register arg_1,
1498 Register arg_2,
1499 bool check_exceptions) {
1500
1501 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1502 pass_arg2(this, arg_2);
1503 pass_arg1(this, arg_1);
1504 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1505 }
1506
1507 void MacroAssembler::call_VM(Register oop_result,
1508 Register last_java_sp,
1509 address entry_point,
1510 Register arg_1,
1511 Register arg_2,
1512 Register arg_3,
1513 bool check_exceptions) {
1514 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1515 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1516 pass_arg3(this, arg_3);
1517 pass_arg2(this, arg_2);
1518 pass_arg1(this, arg_1);
1519 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1520 }
1521
1522 void MacroAssembler::super_call_VM(Register oop_result,
1523 Register last_java_sp,
1524 address entry_point,
1525 int number_of_arguments,
1526 bool check_exceptions) {
1527 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1528 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1529 }
1530
1531 void MacroAssembler::super_call_VM(Register oop_result,
1532 Register last_java_sp,
1533 address entry_point,
1534 Register arg_1,
1535 bool check_exceptions) {
1536 pass_arg1(this, arg_1);
1537 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1538 }
1539
1540 void MacroAssembler::super_call_VM(Register oop_result,
1541 Register last_java_sp,
1542 address entry_point,
1543 Register arg_1,
1544 Register arg_2,
1545 bool check_exceptions) {
1546
1547 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1548 pass_arg2(this, arg_2);
1549 pass_arg1(this, arg_1);
1550 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1551 }
1552
1553 void MacroAssembler::super_call_VM(Register oop_result,
1554 Register last_java_sp,
1555 address entry_point,
1556 Register arg_1,
1557 Register arg_2,
1558 Register arg_3,
1559 bool check_exceptions) {
1560 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1561 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1562 pass_arg3(this, arg_3);
1563 pass_arg2(this, arg_2);
1564 pass_arg1(this, arg_1);
1565 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1566 }
1567
1568 void MacroAssembler::call_VM_base(Register oop_result,
1569 Register java_thread,
1570 Register last_java_sp,
1571 address entry_point,
1572 int number_of_arguments,
1573 bool check_exceptions) {
1574 // determine java_thread register
1575 if (!java_thread->is_valid()) {
1576 #ifdef _LP64
1577 java_thread = r15_thread;
1578 #else
1579 java_thread = rdi;
1580 get_thread(java_thread);
1581 #endif // LP64
1582 }
1583 // determine last_java_sp register
1584 if (!last_java_sp->is_valid()) {
1585 last_java_sp = rsp;
1586 }
1587 // debugging support
1588 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1589 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1590 #ifdef ASSERT
1591 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1592 // r12 is the heapbase.
1593 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1594 #endif // ASSERT
1595
1596 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1597 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1598
1599 // push java thread (becomes first argument of C function)
1600
1601 NOT_LP64(push(java_thread); number_of_arguments++);
1602 LP64_ONLY(mov(c_rarg0, r15_thread));
1603
1604 // set last Java frame before call
1605 assert(last_java_sp != rbp, "can't use ebp/rbp");
1606
1607 // Only interpreter should have to set fp
1608 set_last_Java_frame(java_thread, last_java_sp, rbp, nullptr, rscratch1);
1609
1610 // do the call, remove parameters
1611 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1612
1613 // restore the thread (cannot use the pushed argument since arguments
1614 // may be overwritten by C code generated by an optimizing compiler);
1615 // however can use the register value directly if it is callee saved.
1616 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1617 // rdi & rsi (also r15) are callee saved -> nothing to do
1618 #ifdef ASSERT
1619 guarantee(java_thread != rax, "change this code");
1620 push(rax);
1621 { Label L;
1622 get_thread(rax);
1623 cmpptr(java_thread, rax);
1624 jcc(Assembler::equal, L);
1625 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1626 bind(L);
1627 }
1628 pop(rax);
1629 #endif
1630 } else {
1631 get_thread(java_thread);
1632 }
1633 // reset last Java frame
1634 // Only interpreter should have to clear fp
1635 reset_last_Java_frame(java_thread, true);
1636
1637 // C++ interp handles this in the interpreter
1638 check_and_handle_popframe(java_thread);
1639 check_and_handle_earlyret(java_thread);
1640
1641 if (check_exceptions) {
1642 // check for pending exceptions (java_thread is set upon return)
1643 cmpptr(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
1644 #ifndef _LP64
1645 jump_cc(Assembler::notEqual,
1646 RuntimeAddress(StubRoutines::forward_exception_entry()));
1647 #else
1648 // This used to conditionally jump to forward_exception however it is
1649 // possible if we relocate that the branch will not reach. So we must jump
1650 // around so we can always reach
1651
1652 Label ok;
1653 jcc(Assembler::equal, ok);
1654 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1655 bind(ok);
1656 #endif // LP64
1657 }
1658
1659 // get oop result if there is one and reset the value in the thread
1660 if (oop_result->is_valid()) {
1661 get_vm_result(oop_result, java_thread);
1662 }
1663 }
1664
1665 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1666
1667 // Calculate the value for last_Java_sp
1668 // somewhat subtle. call_VM does an intermediate call
1669 // which places a return address on the stack just under the
1670 // stack pointer as the user finished with it. This allows
1671 // use to retrieve last_Java_pc from last_Java_sp[-1].
1672 // On 32bit we then have to push additional args on the stack to accomplish
1673 // the actual requested call. On 64bit call_VM only can use register args
1674 // so the only extra space is the return address that call_VM created.
1675 // This hopefully explains the calculations here.
1676
1677 #ifdef _LP64
1678 // We've pushed one address, correct last_Java_sp
1679 lea(rax, Address(rsp, wordSize));
1680 #else
1681 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1682 #endif // LP64
1683
1684 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1685
1686 }
1687
1688 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1689 void MacroAssembler::call_VM_leaf0(address entry_point) {
1690 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1691 }
1692
1693 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1694 call_VM_leaf_base(entry_point, number_of_arguments);
1695 }
1696
1697 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1698 pass_arg0(this, arg_0);
1699 call_VM_leaf(entry_point, 1);
1700 }
1701
1702 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1703
1704 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1705 pass_arg1(this, arg_1);
1706 pass_arg0(this, arg_0);
1707 call_VM_leaf(entry_point, 2);
1708 }
1709
1710 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1711 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1712 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1713 pass_arg2(this, arg_2);
1714 pass_arg1(this, arg_1);
1715 pass_arg0(this, arg_0);
1716 call_VM_leaf(entry_point, 3);
1717 }
1718
1719 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1720 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1721 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1722 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1723 pass_arg3(this, arg_3);
1724 pass_arg2(this, arg_2);
1725 pass_arg1(this, arg_1);
1726 pass_arg0(this, arg_0);
1727 call_VM_leaf(entry_point, 3);
1728 }
1729
1730 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1731 pass_arg0(this, arg_0);
1732 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1733 }
1734
1735 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1736 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1737 pass_arg1(this, arg_1);
1738 pass_arg0(this, arg_0);
1739 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1740 }
1741
1742 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1743 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1744 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1745 pass_arg2(this, arg_2);
1746 pass_arg1(this, arg_1);
1747 pass_arg0(this, arg_0);
1748 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1749 }
1750
1751 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1752 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1753 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1754 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1755 pass_arg3(this, arg_3);
1756 pass_arg2(this, arg_2);
1757 pass_arg1(this, arg_1);
1758 pass_arg0(this, arg_0);
1759 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1760 }
1761
1762 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1763 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1764 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1765 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1766 }
1767
1768 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1769 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1770 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1771 }
1772
1773 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1774 }
1775
1776 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1777 }
1778
1779 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1780 assert(rscratch != noreg || always_reachable(src1), "missing");
1781
1782 if (reachable(src1)) {
1783 cmpl(as_Address(src1), imm);
1784 } else {
1785 lea(rscratch, src1);
1786 cmpl(Address(rscratch, 0), imm);
1787 }
1788 }
1789
1790 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1791 assert(!src2.is_lval(), "use cmpptr");
1792 assert(rscratch != noreg || always_reachable(src2), "missing");
1793
1794 if (reachable(src2)) {
1795 cmpl(src1, as_Address(src2));
1796 } else {
1797 lea(rscratch, src2);
1798 cmpl(src1, Address(rscratch, 0));
1799 }
1800 }
1801
1802 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1803 Assembler::cmpl(src1, imm);
1804 }
1805
1806 void MacroAssembler::cmp32(Register src1, Address src2) {
1807 Assembler::cmpl(src1, src2);
1808 }
1809
1810 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1811 ucomisd(opr1, opr2);
1812
1813 Label L;
1814 if (unordered_is_less) {
1815 movl(dst, -1);
1816 jcc(Assembler::parity, L);
1817 jcc(Assembler::below , L);
1818 movl(dst, 0);
1819 jcc(Assembler::equal , L);
1820 increment(dst);
1821 } else { // unordered is greater
1822 movl(dst, 1);
1823 jcc(Assembler::parity, L);
1824 jcc(Assembler::above , L);
1825 movl(dst, 0);
1826 jcc(Assembler::equal , L);
1827 decrementl(dst);
1828 }
1829 bind(L);
1830 }
1831
1832 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1833 ucomiss(opr1, opr2);
1834
1835 Label L;
1836 if (unordered_is_less) {
1837 movl(dst, -1);
1838 jcc(Assembler::parity, L);
1839 jcc(Assembler::below , L);
1840 movl(dst, 0);
1841 jcc(Assembler::equal , L);
1842 increment(dst);
1843 } else { // unordered is greater
1844 movl(dst, 1);
1845 jcc(Assembler::parity, L);
1846 jcc(Assembler::above , L);
1847 movl(dst, 0);
1848 jcc(Assembler::equal , L);
1849 decrementl(dst);
1850 }
1851 bind(L);
1852 }
1853
1854
1855 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1856 assert(rscratch != noreg || always_reachable(src1), "missing");
1857
1858 if (reachable(src1)) {
1859 cmpb(as_Address(src1), imm);
1860 } else {
1861 lea(rscratch, src1);
1862 cmpb(Address(rscratch, 0), imm);
1863 }
1864 }
1865
1866 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1867 #ifdef _LP64
1868 assert(rscratch != noreg || always_reachable(src2), "missing");
1869
1870 if (src2.is_lval()) {
1871 movptr(rscratch, src2);
1872 Assembler::cmpq(src1, rscratch);
1873 } else if (reachable(src2)) {
1874 cmpq(src1, as_Address(src2));
1875 } else {
1876 lea(rscratch, src2);
1877 Assembler::cmpq(src1, Address(rscratch, 0));
1878 }
1879 #else
1880 assert(rscratch == noreg, "not needed");
1881 if (src2.is_lval()) {
1882 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1883 } else {
1884 cmpl(src1, as_Address(src2));
1885 }
1886 #endif // _LP64
1887 }
1888
1889 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1890 assert(src2.is_lval(), "not a mem-mem compare");
1891 #ifdef _LP64
1892 // moves src2's literal address
1893 movptr(rscratch, src2);
1894 Assembler::cmpq(src1, rscratch);
1895 #else
1896 assert(rscratch == noreg, "not needed");
1897 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1898 #endif // _LP64
1899 }
1900
1901 void MacroAssembler::cmpoop(Register src1, Register src2) {
1902 cmpptr(src1, src2);
1903 }
1904
1905 void MacroAssembler::cmpoop(Register src1, Address src2) {
1906 cmpptr(src1, src2);
1907 }
1908
1909 #ifdef _LP64
1910 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1911 movoop(rscratch, src2);
1912 cmpptr(src1, rscratch);
1913 }
1914 #endif
1915
1916 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1917 assert(rscratch != noreg || always_reachable(adr), "missing");
1918
1919 if (reachable(adr)) {
1920 lock();
1921 cmpxchgptr(reg, as_Address(adr));
1922 } else {
1923 lea(rscratch, adr);
1924 lock();
1925 cmpxchgptr(reg, Address(rscratch, 0));
1926 }
1927 }
1928
1929 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1930 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1931 }
1932
1933 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1934 assert(rscratch != noreg || always_reachable(src), "missing");
1935
1936 if (reachable(src)) {
1937 Assembler::comisd(dst, as_Address(src));
1938 } else {
1939 lea(rscratch, src);
1940 Assembler::comisd(dst, Address(rscratch, 0));
1941 }
1942 }
1943
1944 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1945 assert(rscratch != noreg || always_reachable(src), "missing");
1946
1947 if (reachable(src)) {
1948 Assembler::comiss(dst, as_Address(src));
1949 } else {
1950 lea(rscratch, src);
1951 Assembler::comiss(dst, Address(rscratch, 0));
1952 }
1953 }
1954
1955
1956 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1957 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1958
1959 Condition negated_cond = negate_condition(cond);
1960 Label L;
1961 jcc(negated_cond, L);
1962 pushf(); // Preserve flags
1963 atomic_incl(counter_addr, rscratch);
1964 popf();
1965 bind(L);
1966 }
1967
1968 int MacroAssembler::corrected_idivl(Register reg) {
1969 // Full implementation of Java idiv and irem; checks for
1970 // special case as described in JVM spec., p.243 & p.271.
1971 // The function returns the (pc) offset of the idivl
1972 // instruction - may be needed for implicit exceptions.
1973 //
1974 // normal case special case
1975 //
1976 // input : rax,: dividend min_int
1977 // reg: divisor (may not be rax,/rdx) -1
1978 //
1979 // output: rax,: quotient (= rax, idiv reg) min_int
1980 // rdx: remainder (= rax, irem reg) 0
1981 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1982 const int min_int = 0x80000000;
1983 Label normal_case, special_case;
1984
1985 // check for special case
1986 cmpl(rax, min_int);
1987 jcc(Assembler::notEqual, normal_case);
1988 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1989 cmpl(reg, -1);
1990 jcc(Assembler::equal, special_case);
1991
1992 // handle normal case
1993 bind(normal_case);
1994 cdql();
1995 int idivl_offset = offset();
1996 idivl(reg);
1997
1998 // normal and special case exit
1999 bind(special_case);
2000
2001 return idivl_offset;
2002 }
2003
2004
2005
2006 void MacroAssembler::decrementl(Register reg, int value) {
2007 if (value == min_jint) {subl(reg, value) ; return; }
2008 if (value < 0) { incrementl(reg, -value); return; }
2009 if (value == 0) { ; return; }
2010 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2011 /* else */ { subl(reg, value) ; return; }
2012 }
2013
2014 void MacroAssembler::decrementl(Address dst, int value) {
2015 if (value == min_jint) {subl(dst, value) ; return; }
2016 if (value < 0) { incrementl(dst, -value); return; }
2017 if (value == 0) { ; return; }
2018 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2019 /* else */ { subl(dst, value) ; return; }
2020 }
2021
2022 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2023 assert(shift_value > 0, "illegal shift value");
2024 Label _is_positive;
2025 testl (reg, reg);
2026 jcc (Assembler::positive, _is_positive);
2027 int offset = (1 << shift_value) - 1 ;
2028
2029 if (offset == 1) {
2030 incrementl(reg);
2031 } else {
2032 addl(reg, offset);
2033 }
2034
2035 bind (_is_positive);
2036 sarl(reg, shift_value);
2037 }
2038
2039 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2040 assert(rscratch != noreg || always_reachable(src), "missing");
2041
2042 if (reachable(src)) {
2043 Assembler::divsd(dst, as_Address(src));
2044 } else {
2045 lea(rscratch, src);
2046 Assembler::divsd(dst, Address(rscratch, 0));
2047 }
2048 }
2049
2050 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2051 assert(rscratch != noreg || always_reachable(src), "missing");
2052
2053 if (reachable(src)) {
2054 Assembler::divss(dst, as_Address(src));
2055 } else {
2056 lea(rscratch, src);
2057 Assembler::divss(dst, Address(rscratch, 0));
2058 }
2059 }
2060
2061 void MacroAssembler::enter() {
2062 push(rbp);
2063 mov(rbp, rsp);
2064 }
2065
2066 void MacroAssembler::post_call_nop() {
2067 if (!Continuations::enabled()) {
2068 return;
2069 }
2070 InstructionMark im(this);
2071 relocate(post_call_nop_Relocation::spec());
2072 InlineSkippedInstructionsCounter skipCounter(this);
2073 emit_int8((uint8_t)0x0f);
2074 emit_int8((uint8_t)0x1f);
2075 emit_int8((uint8_t)0x84);
2076 emit_int8((uint8_t)0x00);
2077 emit_int32(0x00);
2078 }
2079
2080 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2081 void MacroAssembler::fat_nop() {
2082 if (UseAddressNop) {
2083 addr_nop_5();
2084 } else {
2085 emit_int8((uint8_t)0x26); // es:
2086 emit_int8((uint8_t)0x2e); // cs:
2087 emit_int8((uint8_t)0x64); // fs:
2088 emit_int8((uint8_t)0x65); // gs:
2089 emit_int8((uint8_t)0x90);
2090 }
2091 }
2092
2093 #ifndef _LP64
2094 void MacroAssembler::fcmp(Register tmp) {
2095 fcmp(tmp, 1, true, true);
2096 }
2097
2098 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2099 assert(!pop_right || pop_left, "usage error");
2100 if (VM_Version::supports_cmov()) {
2101 assert(tmp == noreg, "unneeded temp");
2102 if (pop_left) {
2103 fucomip(index);
2104 } else {
2105 fucomi(index);
2106 }
2107 if (pop_right) {
2108 fpop();
2109 }
2110 } else {
2111 assert(tmp != noreg, "need temp");
2112 if (pop_left) {
2113 if (pop_right) {
2114 fcompp();
2115 } else {
2116 fcomp(index);
2117 }
2118 } else {
2119 fcom(index);
2120 }
2121 // convert FPU condition into eflags condition via rax,
2122 save_rax(tmp);
2123 fwait(); fnstsw_ax();
2124 sahf();
2125 restore_rax(tmp);
2126 }
2127 // condition codes set as follows:
2128 //
2129 // CF (corresponds to C0) if x < y
2130 // PF (corresponds to C2) if unordered
2131 // ZF (corresponds to C3) if x = y
2132 }
2133
2134 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2135 fcmp2int(dst, unordered_is_less, 1, true, true);
2136 }
2137
2138 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2139 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2140 Label L;
2141 if (unordered_is_less) {
2142 movl(dst, -1);
2143 jcc(Assembler::parity, L);
2144 jcc(Assembler::below , L);
2145 movl(dst, 0);
2146 jcc(Assembler::equal , L);
2147 increment(dst);
2148 } else { // unordered is greater
2149 movl(dst, 1);
2150 jcc(Assembler::parity, L);
2151 jcc(Assembler::above , L);
2152 movl(dst, 0);
2153 jcc(Assembler::equal , L);
2154 decrementl(dst);
2155 }
2156 bind(L);
2157 }
2158
2159 void MacroAssembler::fld_d(AddressLiteral src) {
2160 fld_d(as_Address(src));
2161 }
2162
2163 void MacroAssembler::fld_s(AddressLiteral src) {
2164 fld_s(as_Address(src));
2165 }
2166
2167 void MacroAssembler::fldcw(AddressLiteral src) {
2168 fldcw(as_Address(src));
2169 }
2170
2171 void MacroAssembler::fpop() {
2172 ffree();
2173 fincstp();
2174 }
2175
2176 void MacroAssembler::fremr(Register tmp) {
2177 save_rax(tmp);
2178 { Label L;
2179 bind(L);
2180 fprem();
2181 fwait(); fnstsw_ax();
2182 sahf();
2183 jcc(Assembler::parity, L);
2184 }
2185 restore_rax(tmp);
2186 // Result is in ST0.
2187 // Note: fxch & fpop to get rid of ST1
2188 // (otherwise FPU stack could overflow eventually)
2189 fxch(1);
2190 fpop();
2191 }
2192
2193 void MacroAssembler::empty_FPU_stack() {
2194 if (VM_Version::supports_mmx()) {
2195 emms();
2196 } else {
2197 for (int i = 8; i-- > 0; ) ffree(i);
2198 }
2199 }
2200 #endif // !LP64
2201
2202 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2203 assert(rscratch != noreg || always_reachable(src), "missing");
2204 if (reachable(src)) {
2205 Assembler::mulpd(dst, as_Address(src));
2206 } else {
2207 lea(rscratch, src);
2208 Assembler::mulpd(dst, Address(rscratch, 0));
2209 }
2210 }
2211
2212 void MacroAssembler::load_float(Address src) {
2213 #ifdef _LP64
2214 movflt(xmm0, src);
2215 #else
2216 if (UseSSE >= 1) {
2217 movflt(xmm0, src);
2218 } else {
2219 fld_s(src);
2220 }
2221 #endif // LP64
2222 }
2223
2224 void MacroAssembler::store_float(Address dst) {
2225 #ifdef _LP64
2226 movflt(dst, xmm0);
2227 #else
2228 if (UseSSE >= 1) {
2229 movflt(dst, xmm0);
2230 } else {
2231 fstp_s(dst);
2232 }
2233 #endif // LP64
2234 }
2235
2236 void MacroAssembler::load_double(Address src) {
2237 #ifdef _LP64
2238 movdbl(xmm0, src);
2239 #else
2240 if (UseSSE >= 2) {
2241 movdbl(xmm0, src);
2242 } else {
2243 fld_d(src);
2244 }
2245 #endif // LP64
2246 }
2247
2248 void MacroAssembler::store_double(Address dst) {
2249 #ifdef _LP64
2250 movdbl(dst, xmm0);
2251 #else
2252 if (UseSSE >= 2) {
2253 movdbl(dst, xmm0);
2254 } else {
2255 fstp_d(dst);
2256 }
2257 #endif // LP64
2258 }
2259
2260 // dst = c = a * b + c
2261 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2262 Assembler::vfmadd231sd(c, a, b);
2263 if (dst != c) {
2264 movdbl(dst, c);
2265 }
2266 }
2267
2268 // dst = c = a * b + c
2269 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2270 Assembler::vfmadd231ss(c, a, b);
2271 if (dst != c) {
2272 movflt(dst, c);
2273 }
2274 }
2275
2276 // dst = c = a * b + c
2277 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2278 Assembler::vfmadd231pd(c, a, b, vector_len);
2279 if (dst != c) {
2280 vmovdqu(dst, c);
2281 }
2282 }
2283
2284 // dst = c = a * b + c
2285 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2286 Assembler::vfmadd231ps(c, a, b, vector_len);
2287 if (dst != c) {
2288 vmovdqu(dst, c);
2289 }
2290 }
2291
2292 // dst = c = a * b + c
2293 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2294 Assembler::vfmadd231pd(c, a, b, vector_len);
2295 if (dst != c) {
2296 vmovdqu(dst, c);
2297 }
2298 }
2299
2300 // dst = c = a * b + c
2301 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2302 Assembler::vfmadd231ps(c, a, b, vector_len);
2303 if (dst != c) {
2304 vmovdqu(dst, c);
2305 }
2306 }
2307
2308 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
2309 assert(rscratch != noreg || always_reachable(dst), "missing");
2310
2311 if (reachable(dst)) {
2312 incrementl(as_Address(dst));
2313 } else {
2314 lea(rscratch, dst);
2315 incrementl(Address(rscratch, 0));
2316 }
2317 }
2318
2319 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
2320 incrementl(as_Address(dst, rscratch));
2321 }
2322
2323 void MacroAssembler::incrementl(Register reg, int value) {
2324 if (value == min_jint) {addl(reg, value) ; return; }
2325 if (value < 0) { decrementl(reg, -value); return; }
2326 if (value == 0) { ; return; }
2327 if (value == 1 && UseIncDec) { incl(reg) ; return; }
2328 /* else */ { addl(reg, value) ; return; }
2329 }
2330
2331 void MacroAssembler::incrementl(Address dst, int value) {
2332 if (value == min_jint) {addl(dst, value) ; return; }
2333 if (value < 0) { decrementl(dst, -value); return; }
2334 if (value == 0) { ; return; }
2335 if (value == 1 && UseIncDec) { incl(dst) ; return; }
2336 /* else */ { addl(dst, value) ; return; }
2337 }
2338
2339 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
2340 assert(rscratch != noreg || always_reachable(dst), "missing");
2341 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
2342 if (reachable(dst)) {
2343 jmp_literal(dst.target(), dst.rspec());
2344 } else {
2345 lea(rscratch, dst);
2346 jmp(rscratch);
2347 }
2348 }
2349
2350 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
2351 assert(rscratch != noreg || always_reachable(dst), "missing");
2352 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
2353 if (reachable(dst)) {
2354 InstructionMark im(this);
2355 relocate(dst.reloc());
2356 const int short_size = 2;
2357 const int long_size = 6;
2358 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2359 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2360 // 0111 tttn #8-bit disp
2361 emit_int8(0x70 | cc);
2362 emit_int8((offs - short_size) & 0xFF);
2363 } else {
2364 // 0000 1111 1000 tttn #32-bit disp
2365 emit_int8(0x0F);
2366 emit_int8((unsigned char)(0x80 | cc));
2367 emit_int32(offs - long_size);
2368 }
2369 } else {
2370 #ifdef ASSERT
2371 warning("reversing conditional branch");
2372 #endif /* ASSERT */
2373 Label skip;
2374 jccb(reverse[cc], skip);
2375 lea(rscratch, dst);
2376 Assembler::jmp(rscratch);
2377 bind(skip);
2378 }
2379 }
2380
2381 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
2382 assert(rscratch != noreg || always_reachable(src), "missing");
2383
2384 if (reachable(src)) {
2385 Assembler::ldmxcsr(as_Address(src));
2386 } else {
2387 lea(rscratch, src);
2388 Assembler::ldmxcsr(Address(rscratch, 0));
2389 }
2390 }
2391
2392 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2393 int off;
2394 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2395 off = offset();
2396 movsbl(dst, src); // movsxb
2397 } else {
2398 off = load_unsigned_byte(dst, src);
2399 shll(dst, 24);
2400 sarl(dst, 24);
2401 }
2402 return off;
2403 }
2404
2405 // Note: load_signed_short used to be called load_signed_word.
2406 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2407 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2408 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2409 int MacroAssembler::load_signed_short(Register dst, Address src) {
2410 int off;
2411 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2412 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2413 // version but this is what 64bit has always done. This seems to imply
2414 // that users are only using 32bits worth.
2415 off = offset();
2416 movswl(dst, src); // movsxw
2417 } else {
2418 off = load_unsigned_short(dst, src);
2419 shll(dst, 16);
2420 sarl(dst, 16);
2421 }
2422 return off;
2423 }
2424
2425 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2426 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2427 // and "3.9 Partial Register Penalties", p. 22).
2428 int off;
2429 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2430 off = offset();
2431 movzbl(dst, src); // movzxb
2432 } else {
2433 xorl(dst, dst);
2434 off = offset();
2435 movb(dst, src);
2436 }
2437 return off;
2438 }
2439
2440 // Note: load_unsigned_short used to be called load_unsigned_word.
2441 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2442 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2443 // and "3.9 Partial Register Penalties", p. 22).
2444 int off;
2445 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2446 off = offset();
2447 movzwl(dst, src); // movzxw
2448 } else {
2449 xorl(dst, dst);
2450 off = offset();
2451 movw(dst, src);
2452 }
2453 return off;
2454 }
2455
2456 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2457 switch (size_in_bytes) {
2458 #ifndef _LP64
2459 case 8:
2460 assert(dst2 != noreg, "second dest register required");
2461 movl(dst, src);
2462 movl(dst2, src.plus_disp(BytesPerInt));
2463 break;
2464 #else
2465 case 8: movq(dst, src); break;
2466 #endif
2467 case 4: movl(dst, src); break;
2468 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2469 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2470 default: ShouldNotReachHere();
2471 }
2472 }
2473
2474 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2475 switch (size_in_bytes) {
2476 #ifndef _LP64
2477 case 8:
2478 assert(src2 != noreg, "second source register required");
2479 movl(dst, src);
2480 movl(dst.plus_disp(BytesPerInt), src2);
2481 break;
2482 #else
2483 case 8: movq(dst, src); break;
2484 #endif
2485 case 4: movl(dst, src); break;
2486 case 2: movw(dst, src); break;
2487 case 1: movb(dst, src); break;
2488 default: ShouldNotReachHere();
2489 }
2490 }
2491
2492 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
2493 assert(rscratch != noreg || always_reachable(dst), "missing");
2494
2495 if (reachable(dst)) {
2496 movl(as_Address(dst), src);
2497 } else {
2498 lea(rscratch, dst);
2499 movl(Address(rscratch, 0), src);
2500 }
2501 }
2502
2503 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2504 if (reachable(src)) {
2505 movl(dst, as_Address(src));
2506 } else {
2507 lea(dst, src);
2508 movl(dst, Address(dst, 0));
2509 }
2510 }
2511
2512 // C++ bool manipulation
2513
2514 void MacroAssembler::movbool(Register dst, Address src) {
2515 if(sizeof(bool) == 1)
2516 movb(dst, src);
2517 else if(sizeof(bool) == 2)
2518 movw(dst, src);
2519 else if(sizeof(bool) == 4)
2520 movl(dst, src);
2521 else
2522 // unsupported
2523 ShouldNotReachHere();
2524 }
2525
2526 void MacroAssembler::movbool(Address dst, bool boolconst) {
2527 if(sizeof(bool) == 1)
2528 movb(dst, (int) boolconst);
2529 else if(sizeof(bool) == 2)
2530 movw(dst, (int) boolconst);
2531 else if(sizeof(bool) == 4)
2532 movl(dst, (int) boolconst);
2533 else
2534 // unsupported
2535 ShouldNotReachHere();
2536 }
2537
2538 void MacroAssembler::movbool(Address dst, Register src) {
2539 if(sizeof(bool) == 1)
2540 movb(dst, src);
2541 else if(sizeof(bool) == 2)
2542 movw(dst, src);
2543 else if(sizeof(bool) == 4)
2544 movl(dst, src);
2545 else
2546 // unsupported
2547 ShouldNotReachHere();
2548 }
2549
2550 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2551 assert(rscratch != noreg || always_reachable(src), "missing");
2552
2553 if (reachable(src)) {
2554 movdl(dst, as_Address(src));
2555 } else {
2556 lea(rscratch, src);
2557 movdl(dst, Address(rscratch, 0));
2558 }
2559 }
2560
2561 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
2562 assert(rscratch != noreg || always_reachable(src), "missing");
2563
2564 if (reachable(src)) {
2565 movq(dst, as_Address(src));
2566 } else {
2567 lea(rscratch, src);
2568 movq(dst, Address(rscratch, 0));
2569 }
2570 }
2571
2572 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2573 assert(rscratch != noreg || always_reachable(src), "missing");
2574
2575 if (reachable(src)) {
2576 if (UseXmmLoadAndClearUpper) {
2577 movsd (dst, as_Address(src));
2578 } else {
2579 movlpd(dst, as_Address(src));
2580 }
2581 } else {
2582 lea(rscratch, src);
2583 if (UseXmmLoadAndClearUpper) {
2584 movsd (dst, Address(rscratch, 0));
2585 } else {
2586 movlpd(dst, Address(rscratch, 0));
2587 }
2588 }
2589 }
2590
2591 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
2592 assert(rscratch != noreg || always_reachable(src), "missing");
2593
2594 if (reachable(src)) {
2595 movss(dst, as_Address(src));
2596 } else {
2597 lea(rscratch, src);
2598 movss(dst, Address(rscratch, 0));
2599 }
2600 }
2601
2602 void MacroAssembler::movptr(Register dst, Register src) {
2603 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2604 }
2605
2606 void MacroAssembler::movptr(Register dst, Address src) {
2607 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2608 }
2609
2610 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2611 void MacroAssembler::movptr(Register dst, intptr_t src) {
2612 #ifdef _LP64
2613 if (is_uimm32(src)) {
2614 movl(dst, checked_cast<uint32_t>(src));
2615 } else if (is_simm32(src)) {
2616 movq(dst, checked_cast<int32_t>(src));
2617 } else {
2618 mov64(dst, src);
2619 }
2620 #else
2621 movl(dst, src);
2622 #endif
2623 }
2624
2625 void MacroAssembler::movptr(Address dst, Register src) {
2626 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2627 }
2628
2629 void MacroAssembler::movptr(Address dst, int32_t src) {
2630 LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src));
2631 }
2632
2633 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2634 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2635 Assembler::movdqu(dst, src);
2636 }
2637
2638 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2639 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2640 Assembler::movdqu(dst, src);
2641 }
2642
2643 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2644 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2645 Assembler::movdqu(dst, src);
2646 }
2647
2648 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2649 assert(rscratch != noreg || always_reachable(src), "missing");
2650
2651 if (reachable(src)) {
2652 movdqu(dst, as_Address(src));
2653 } else {
2654 lea(rscratch, src);
2655 movdqu(dst, Address(rscratch, 0));
2656 }
2657 }
2658
2659 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2660 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2661 Assembler::vmovdqu(dst, src);
2662 }
2663
2664 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2665 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2666 Assembler::vmovdqu(dst, src);
2667 }
2668
2669 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2670 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2671 Assembler::vmovdqu(dst, src);
2672 }
2673
2674 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2675 assert(rscratch != noreg || always_reachable(src), "missing");
2676
2677 if (reachable(src)) {
2678 vmovdqu(dst, as_Address(src));
2679 }
2680 else {
2681 lea(rscratch, src);
2682 vmovdqu(dst, Address(rscratch, 0));
2683 }
2684 }
2685
2686 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2687 assert(rscratch != noreg || always_reachable(src), "missing");
2688
2689 if (vector_len == AVX_512bit) {
2690 evmovdquq(dst, src, AVX_512bit, rscratch);
2691 } else if (vector_len == AVX_256bit) {
2692 vmovdqu(dst, src, rscratch);
2693 } else {
2694 movdqu(dst, src, rscratch);
2695 }
2696 }
2697
2698 void MacroAssembler::kmov(KRegister dst, Address src) {
2699 if (VM_Version::supports_avx512bw()) {
2700 kmovql(dst, src);
2701 } else {
2702 assert(VM_Version::supports_evex(), "");
2703 kmovwl(dst, src);
2704 }
2705 }
2706
2707 void MacroAssembler::kmov(Address dst, KRegister src) {
2708 if (VM_Version::supports_avx512bw()) {
2709 kmovql(dst, src);
2710 } else {
2711 assert(VM_Version::supports_evex(), "");
2712 kmovwl(dst, src);
2713 }
2714 }
2715
2716 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2717 if (VM_Version::supports_avx512bw()) {
2718 kmovql(dst, src);
2719 } else {
2720 assert(VM_Version::supports_evex(), "");
2721 kmovwl(dst, src);
2722 }
2723 }
2724
2725 void MacroAssembler::kmov(Register dst, KRegister src) {
2726 if (VM_Version::supports_avx512bw()) {
2727 kmovql(dst, src);
2728 } else {
2729 assert(VM_Version::supports_evex(), "");
2730 kmovwl(dst, src);
2731 }
2732 }
2733
2734 void MacroAssembler::kmov(KRegister dst, Register src) {
2735 if (VM_Version::supports_avx512bw()) {
2736 kmovql(dst, src);
2737 } else {
2738 assert(VM_Version::supports_evex(), "");
2739 kmovwl(dst, src);
2740 }
2741 }
2742
2743 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2744 assert(rscratch != noreg || always_reachable(src), "missing");
2745
2746 if (reachable(src)) {
2747 kmovql(dst, as_Address(src));
2748 } else {
2749 lea(rscratch, src);
2750 kmovql(dst, Address(rscratch, 0));
2751 }
2752 }
2753
2754 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2755 assert(rscratch != noreg || always_reachable(src), "missing");
2756
2757 if (reachable(src)) {
2758 kmovwl(dst, as_Address(src));
2759 } else {
2760 lea(rscratch, src);
2761 kmovwl(dst, Address(rscratch, 0));
2762 }
2763 }
2764
2765 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2766 int vector_len, Register rscratch) {
2767 assert(rscratch != noreg || always_reachable(src), "missing");
2768
2769 if (reachable(src)) {
2770 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2771 } else {
2772 lea(rscratch, src);
2773 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2774 }
2775 }
2776
2777 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2778 int vector_len, Register rscratch) {
2779 assert(rscratch != noreg || always_reachable(src), "missing");
2780
2781 if (reachable(src)) {
2782 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2783 } else {
2784 lea(rscratch, src);
2785 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2786 }
2787 }
2788
2789 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2790 assert(rscratch != noreg || always_reachable(src), "missing");
2791
2792 if (reachable(src)) {
2793 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2794 } else {
2795 lea(rscratch, src);
2796 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2797 }
2798 }
2799
2800 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2801 assert(rscratch != noreg || always_reachable(src), "missing");
2802
2803 if (reachable(src)) {
2804 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2805 } else {
2806 lea(rscratch, src);
2807 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2808 }
2809 }
2810
2811 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2812 assert(rscratch != noreg || always_reachable(src), "missing");
2813
2814 if (reachable(src)) {
2815 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2816 } else {
2817 lea(rscratch, src);
2818 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2819 }
2820 }
2821
2822 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2823 assert(rscratch != noreg || always_reachable(src), "missing");
2824
2825 if (reachable(src)) {
2826 Assembler::movdqa(dst, as_Address(src));
2827 } else {
2828 lea(rscratch, src);
2829 Assembler::movdqa(dst, Address(rscratch, 0));
2830 }
2831 }
2832
2833 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2834 assert(rscratch != noreg || always_reachable(src), "missing");
2835
2836 if (reachable(src)) {
2837 Assembler::movsd(dst, as_Address(src));
2838 } else {
2839 lea(rscratch, src);
2840 Assembler::movsd(dst, Address(rscratch, 0));
2841 }
2842 }
2843
2844 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2845 assert(rscratch != noreg || always_reachable(src), "missing");
2846
2847 if (reachable(src)) {
2848 Assembler::movss(dst, as_Address(src));
2849 } else {
2850 lea(rscratch, src);
2851 Assembler::movss(dst, Address(rscratch, 0));
2852 }
2853 }
2854
2855 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2856 assert(rscratch != noreg || always_reachable(src), "missing");
2857
2858 if (reachable(src)) {
2859 Assembler::movddup(dst, as_Address(src));
2860 } else {
2861 lea(rscratch, src);
2862 Assembler::movddup(dst, Address(rscratch, 0));
2863 }
2864 }
2865
2866 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2867 assert(rscratch != noreg || always_reachable(src), "missing");
2868
2869 if (reachable(src)) {
2870 Assembler::vmovddup(dst, as_Address(src), vector_len);
2871 } else {
2872 lea(rscratch, src);
2873 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2874 }
2875 }
2876
2877 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2878 assert(rscratch != noreg || always_reachable(src), "missing");
2879
2880 if (reachable(src)) {
2881 Assembler::mulsd(dst, as_Address(src));
2882 } else {
2883 lea(rscratch, src);
2884 Assembler::mulsd(dst, Address(rscratch, 0));
2885 }
2886 }
2887
2888 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2889 assert(rscratch != noreg || always_reachable(src), "missing");
2890
2891 if (reachable(src)) {
2892 Assembler::mulss(dst, as_Address(src));
2893 } else {
2894 lea(rscratch, src);
2895 Assembler::mulss(dst, Address(rscratch, 0));
2896 }
2897 }
2898
2899 void MacroAssembler::null_check(Register reg, int offset) {
2900 if (needs_explicit_null_check(offset)) {
2901 // provoke OS null exception if reg is null by
2902 // accessing M[reg] w/o changing any (non-CC) registers
2903 // NOTE: cmpl is plenty here to provoke a segv
2904 cmpptr(rax, Address(reg, 0));
2905 // Note: should probably use testl(rax, Address(reg, 0));
2906 // may be shorter code (however, this version of
2907 // testl needs to be implemented first)
2908 } else {
2909 // nothing to do, (later) access of M[reg + offset]
2910 // will provoke OS null exception if reg is null
2911 }
2912 }
2913
2914 void MacroAssembler::os_breakpoint() {
2915 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2916 // (e.g., MSVC can't call ps() otherwise)
2917 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2918 }
2919
2920 void MacroAssembler::unimplemented(const char* what) {
2921 const char* buf = nullptr;
2922 {
2923 ResourceMark rm;
2924 stringStream ss;
2925 ss.print("unimplemented: %s", what);
2926 buf = code_string(ss.as_string());
2927 }
2928 stop(buf);
2929 }
2930
2931 #ifdef _LP64
2932 #define XSTATE_BV 0x200
2933 #endif
2934
2935 void MacroAssembler::pop_CPU_state() {
2936 pop_FPU_state();
2937 pop_IU_state();
2938 }
2939
2940 void MacroAssembler::pop_FPU_state() {
2941 #ifndef _LP64
2942 frstor(Address(rsp, 0));
2943 #else
2944 fxrstor(Address(rsp, 0));
2945 #endif
2946 addptr(rsp, FPUStateSizeInWords * wordSize);
2947 }
2948
2949 void MacroAssembler::pop_IU_state() {
2950 popa();
2951 LP64_ONLY(addq(rsp, 8));
2952 popf();
2953 }
2954
2955 // Save Integer and Float state
2956 // Warning: Stack must be 16 byte aligned (64bit)
2957 void MacroAssembler::push_CPU_state() {
2958 push_IU_state();
2959 push_FPU_state();
2960 }
2961
2962 void MacroAssembler::push_FPU_state() {
2963 subptr(rsp, FPUStateSizeInWords * wordSize);
2964 #ifndef _LP64
2965 fnsave(Address(rsp, 0));
2966 fwait();
2967 #else
2968 fxsave(Address(rsp, 0));
2969 #endif // LP64
2970 }
2971
2972 void MacroAssembler::push_IU_state() {
2973 // Push flags first because pusha kills them
2974 pushf();
2975 // Make sure rsp stays 16-byte aligned
2976 LP64_ONLY(subq(rsp, 8));
2977 pusha();
2978 }
2979
2980 void MacroAssembler::push_cont_fastpath() {
2981 if (!Continuations::enabled()) return;
2982
2983 #ifndef _LP64
2984 Register rthread = rax;
2985 Register rrealsp = rbx;
2986 push(rthread);
2987 push(rrealsp);
2988
2989 get_thread(rthread);
2990
2991 // The code below wants the original RSP.
2992 // Move it back after the pushes above.
2993 movptr(rrealsp, rsp);
2994 addptr(rrealsp, 2*wordSize);
2995 #else
2996 Register rthread = r15_thread;
2997 Register rrealsp = rsp;
2998 #endif
2999
3000 Label done;
3001 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3002 jccb(Assembler::belowEqual, done);
3003 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), rrealsp);
3004 bind(done);
3005
3006 #ifndef _LP64
3007 pop(rrealsp);
3008 pop(rthread);
3009 #endif
3010 }
3011
3012 void MacroAssembler::pop_cont_fastpath() {
3013 if (!Continuations::enabled()) return;
3014
3015 #ifndef _LP64
3016 Register rthread = rax;
3017 Register rrealsp = rbx;
3018 push(rthread);
3019 push(rrealsp);
3020
3021 get_thread(rthread);
3022
3023 // The code below wants the original RSP.
3024 // Move it back after the pushes above.
3025 movptr(rrealsp, rsp);
3026 addptr(rrealsp, 2*wordSize);
3027 #else
3028 Register rthread = r15_thread;
3029 Register rrealsp = rsp;
3030 #endif
3031
3032 Label done;
3033 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3034 jccb(Assembler::below, done);
3035 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), 0);
3036 bind(done);
3037
3038 #ifndef _LP64
3039 pop(rrealsp);
3040 pop(rthread);
3041 #endif
3042 }
3043
3044 void MacroAssembler::inc_held_monitor_count() {
3045 #ifdef _LP64
3046 incrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3047 #endif
3048 }
3049
3050 void MacroAssembler::dec_held_monitor_count() {
3051 #ifdef _LP64
3052 decrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3053 #endif
3054 }
3055
3056 #ifdef ASSERT
3057 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
3058 #ifdef _LP64
3059 Label no_cont;
3060 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
3061 testl(cont, cont);
3062 jcc(Assembler::zero, no_cont);
3063 stop(name);
3064 bind(no_cont);
3065 #else
3066 Unimplemented();
3067 #endif
3068 }
3069 #endif
3070
3071 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3072 if (!java_thread->is_valid()) {
3073 java_thread = rdi;
3074 get_thread(java_thread);
3075 }
3076 // we must set sp to zero to clear frame
3077 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3078 // must clear fp, so that compiled frames are not confused; it is
3079 // possible that we need it only for debugging
3080 if (clear_fp) {
3081 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3082 }
3083 // Always clear the pc because it could have been set by make_walkable()
3084 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3085 vzeroupper();
3086 }
3087
3088 void MacroAssembler::restore_rax(Register tmp) {
3089 if (tmp == noreg) pop(rax);
3090 else if (tmp != rax) mov(rax, tmp);
3091 }
3092
3093 void MacroAssembler::round_to(Register reg, int modulus) {
3094 addptr(reg, modulus - 1);
3095 andptr(reg, -modulus);
3096 }
3097
3098 void MacroAssembler::save_rax(Register tmp) {
3099 if (tmp == noreg) push(rax);
3100 else if (tmp != rax) mov(tmp, rax);
3101 }
3102
3103 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
3104 if (at_return) {
3105 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
3106 // we may safely use rsp instead to perform the stack watermark check.
3107 cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
3108 jcc(Assembler::above, slow_path);
3109 return;
3110 }
3111 testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
3112 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3113 }
3114
3115 // Calls to C land
3116 //
3117 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3118 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3119 // has to be reset to 0. This is required to allow proper stack traversal.
3120 void MacroAssembler::set_last_Java_frame(Register java_thread,
3121 Register last_java_sp,
3122 Register last_java_fp,
3123 address last_java_pc,
3124 Register rscratch) {
3125 vzeroupper();
3126 // determine java_thread register
3127 if (!java_thread->is_valid()) {
3128 java_thread = rdi;
3129 get_thread(java_thread);
3130 }
3131 // determine last_java_sp register
3132 if (!last_java_sp->is_valid()) {
3133 last_java_sp = rsp;
3134 }
3135 // last_java_fp is optional
3136 if (last_java_fp->is_valid()) {
3137 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3138 }
3139 // last_java_pc is optional
3140 if (last_java_pc != nullptr) {
3141 Address java_pc(java_thread,
3142 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
3143 lea(java_pc, InternalAddress(last_java_pc), rscratch);
3144 }
3145 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3146 }
3147
3148 #ifdef _LP64
3149 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
3150 Register last_java_fp,
3151 Label &L,
3152 Register scratch) {
3153 lea(scratch, L);
3154 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
3155 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, nullptr, scratch);
3156 }
3157 #endif
3158
3159 void MacroAssembler::shlptr(Register dst, int imm8) {
3160 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3161 }
3162
3163 void MacroAssembler::shrptr(Register dst, int imm8) {
3164 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3165 }
3166
3167 void MacroAssembler::sign_extend_byte(Register reg) {
3168 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3169 movsbl(reg, reg); // movsxb
3170 } else {
3171 shll(reg, 24);
3172 sarl(reg, 24);
3173 }
3174 }
3175
3176 void MacroAssembler::sign_extend_short(Register reg) {
3177 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3178 movswl(reg, reg); // movsxw
3179 } else {
3180 shll(reg, 16);
3181 sarl(reg, 16);
3182 }
3183 }
3184
3185 void MacroAssembler::testl(Address dst, int32_t imm32) {
3186 if (imm32 >= 0 && is8bit(imm32)) {
3187 testb(dst, imm32);
3188 } else {
3189 Assembler::testl(dst, imm32);
3190 }
3191 }
3192
3193 void MacroAssembler::testl(Register dst, int32_t imm32) {
3194 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
3195 testb(dst, imm32);
3196 } else {
3197 Assembler::testl(dst, imm32);
3198 }
3199 }
3200
3201 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3202 assert(always_reachable(src), "Address should be reachable");
3203 testl(dst, as_Address(src));
3204 }
3205
3206 #ifdef _LP64
3207
3208 void MacroAssembler::testq(Address dst, int32_t imm32) {
3209 if (imm32 >= 0) {
3210 testl(dst, imm32);
3211 } else {
3212 Assembler::testq(dst, imm32);
3213 }
3214 }
3215
3216 void MacroAssembler::testq(Register dst, int32_t imm32) {
3217 if (imm32 >= 0) {
3218 testl(dst, imm32);
3219 } else {
3220 Assembler::testq(dst, imm32);
3221 }
3222 }
3223
3224 #endif
3225
3226 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3227 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3228 Assembler::pcmpeqb(dst, src);
3229 }
3230
3231 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3232 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3233 Assembler::pcmpeqw(dst, src);
3234 }
3235
3236 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3237 assert((dst->encoding() < 16),"XMM register should be 0-15");
3238 Assembler::pcmpestri(dst, src, imm8);
3239 }
3240
3241 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3242 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3243 Assembler::pcmpestri(dst, src, imm8);
3244 }
3245
3246 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3247 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3248 Assembler::pmovzxbw(dst, src);
3249 }
3250
3251 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3252 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3253 Assembler::pmovzxbw(dst, src);
3254 }
3255
3256 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3257 assert((src->encoding() < 16),"XMM register should be 0-15");
3258 Assembler::pmovmskb(dst, src);
3259 }
3260
3261 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3262 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3263 Assembler::ptest(dst, src);
3264 }
3265
3266 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3267 assert(rscratch != noreg || always_reachable(src), "missing");
3268
3269 if (reachable(src)) {
3270 Assembler::sqrtss(dst, as_Address(src));
3271 } else {
3272 lea(rscratch, src);
3273 Assembler::sqrtss(dst, Address(rscratch, 0));
3274 }
3275 }
3276
3277 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3278 assert(rscratch != noreg || always_reachable(src), "missing");
3279
3280 if (reachable(src)) {
3281 Assembler::subsd(dst, as_Address(src));
3282 } else {
3283 lea(rscratch, src);
3284 Assembler::subsd(dst, Address(rscratch, 0));
3285 }
3286 }
3287
3288 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
3289 assert(rscratch != noreg || always_reachable(src), "missing");
3290
3291 if (reachable(src)) {
3292 Assembler::roundsd(dst, as_Address(src), rmode);
3293 } else {
3294 lea(rscratch, src);
3295 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
3296 }
3297 }
3298
3299 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3300 assert(rscratch != noreg || always_reachable(src), "missing");
3301
3302 if (reachable(src)) {
3303 Assembler::subss(dst, as_Address(src));
3304 } else {
3305 lea(rscratch, src);
3306 Assembler::subss(dst, Address(rscratch, 0));
3307 }
3308 }
3309
3310 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3311 assert(rscratch != noreg || always_reachable(src), "missing");
3312
3313 if (reachable(src)) {
3314 Assembler::ucomisd(dst, as_Address(src));
3315 } else {
3316 lea(rscratch, src);
3317 Assembler::ucomisd(dst, Address(rscratch, 0));
3318 }
3319 }
3320
3321 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3322 assert(rscratch != noreg || always_reachable(src), "missing");
3323
3324 if (reachable(src)) {
3325 Assembler::ucomiss(dst, as_Address(src));
3326 } else {
3327 lea(rscratch, src);
3328 Assembler::ucomiss(dst, Address(rscratch, 0));
3329 }
3330 }
3331
3332 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3333 assert(rscratch != noreg || always_reachable(src), "missing");
3334
3335 // Used in sign-bit flipping with aligned address.
3336 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3337 if (reachable(src)) {
3338 Assembler::xorpd(dst, as_Address(src));
3339 } else {
3340 lea(rscratch, src);
3341 Assembler::xorpd(dst, Address(rscratch, 0));
3342 }
3343 }
3344
3345 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3346 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3347 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3348 }
3349 else {
3350 Assembler::xorpd(dst, src);
3351 }
3352 }
3353
3354 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3355 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3356 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3357 } else {
3358 Assembler::xorps(dst, src);
3359 }
3360 }
3361
3362 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
3363 assert(rscratch != noreg || always_reachable(src), "missing");
3364
3365 // Used in sign-bit flipping with aligned address.
3366 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3367 if (reachable(src)) {
3368 Assembler::xorps(dst, as_Address(src));
3369 } else {
3370 lea(rscratch, src);
3371 Assembler::xorps(dst, Address(rscratch, 0));
3372 }
3373 }
3374
3375 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
3376 assert(rscratch != noreg || always_reachable(src), "missing");
3377
3378 // Used in sign-bit flipping with aligned address.
3379 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3380 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3381 if (reachable(src)) {
3382 Assembler::pshufb(dst, as_Address(src));
3383 } else {
3384 lea(rscratch, src);
3385 Assembler::pshufb(dst, Address(rscratch, 0));
3386 }
3387 }
3388
3389 // AVX 3-operands instructions
3390
3391 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3392 assert(rscratch != noreg || always_reachable(src), "missing");
3393
3394 if (reachable(src)) {
3395 vaddsd(dst, nds, as_Address(src));
3396 } else {
3397 lea(rscratch, src);
3398 vaddsd(dst, nds, Address(rscratch, 0));
3399 }
3400 }
3401
3402 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3403 assert(rscratch != noreg || always_reachable(src), "missing");
3404
3405 if (reachable(src)) {
3406 vaddss(dst, nds, as_Address(src));
3407 } else {
3408 lea(rscratch, src);
3409 vaddss(dst, nds, Address(rscratch, 0));
3410 }
3411 }
3412
3413 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3414 assert(UseAVX > 0, "requires some form of AVX");
3415 assert(rscratch != noreg || always_reachable(src), "missing");
3416
3417 if (reachable(src)) {
3418 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3419 } else {
3420 lea(rscratch, src);
3421 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3422 }
3423 }
3424
3425 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3426 assert(UseAVX > 0, "requires some form of AVX");
3427 assert(rscratch != noreg || always_reachable(src), "missing");
3428
3429 if (reachable(src)) {
3430 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3431 } else {
3432 lea(rscratch, src);
3433 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3434 }
3435 }
3436
3437 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3438 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3439 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3440
3441 vandps(dst, nds, negate_field, vector_len, rscratch);
3442 }
3443
3444 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3445 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3446 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3447
3448 vandpd(dst, nds, negate_field, vector_len, rscratch);
3449 }
3450
3451 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3452 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3453 Assembler::vpaddb(dst, nds, src, vector_len);
3454 }
3455
3456 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3457 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3458 Assembler::vpaddb(dst, nds, src, vector_len);
3459 }
3460
3461 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3462 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3463 Assembler::vpaddw(dst, nds, src, vector_len);
3464 }
3465
3466 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3467 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3468 Assembler::vpaddw(dst, nds, src, vector_len);
3469 }
3470
3471 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3472 assert(rscratch != noreg || always_reachable(src), "missing");
3473
3474 if (reachable(src)) {
3475 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3476 } else {
3477 lea(rscratch, src);
3478 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
3479 }
3480 }
3481
3482 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3483 assert(rscratch != noreg || always_reachable(src), "missing");
3484
3485 if (reachable(src)) {
3486 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
3487 } else {
3488 lea(rscratch, src);
3489 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
3490 }
3491 }
3492
3493 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3494 assert(rscratch != noreg || always_reachable(src), "missing");
3495
3496 if (reachable(src)) {
3497 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
3498 } else {
3499 lea(rscratch, src);
3500 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
3501 }
3502 }
3503
3504 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3505 assert(rscratch != noreg || always_reachable(src), "missing");
3506
3507 if (reachable(src)) {
3508 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3509 } else {
3510 lea(rscratch, src);
3511 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3512 }
3513 }
3514
3515 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3516 assert(rscratch != noreg || always_reachable(src), "missing");
3517
3518 if (reachable(src)) {
3519 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3520 } else {
3521 lea(rscratch, src);
3522 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3523 }
3524 }
3525
3526 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3527 assert(rscratch != noreg || always_reachable(src), "missing");
3528
3529 if (reachable(src)) {
3530 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3531 } else {
3532 lea(rscratch, src);
3533 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3534 }
3535 }
3536
3537 // Vector float blend
3538 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3539 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3540 // WARN: Allow dst == (src1|src2), mask == scratch
3541 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3542 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3543 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3544 if (blend_emulation && scratch_available && dst_available) {
3545 if (compute_mask) {
3546 vpsrad(scratch, mask, 32, vector_len);
3547 mask = scratch;
3548 }
3549 if (dst == src1) {
3550 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3551 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3552 } else {
3553 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3554 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3555 }
3556 vpor(dst, dst, scratch, vector_len);
3557 } else {
3558 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3559 }
3560 }
3561
3562 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3563 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3564 // WARN: Allow dst == (src1|src2), mask == scratch
3565 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3566 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3567 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3568 if (blend_emulation && scratch_available && dst_available) {
3569 if (compute_mask) {
3570 vpxor(scratch, scratch, scratch, vector_len);
3571 vpcmpgtq(scratch, scratch, mask, vector_len);
3572 mask = scratch;
3573 }
3574 if (dst == src1) {
3575 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3576 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3577 } else {
3578 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3579 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3580 }
3581 vpor(dst, dst, scratch, vector_len);
3582 } else {
3583 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3584 }
3585 }
3586
3587 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3588 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3589 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3590 }
3591
3592 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3593 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3594 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3595 }
3596
3597 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3598 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3599 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3600 }
3601
3602 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3603 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3604 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3605 }
3606
3607 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3608 assert(rscratch != noreg || always_reachable(src), "missing");
3609
3610 if (reachable(src)) {
3611 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3612 } else {
3613 lea(rscratch, src);
3614 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3615 }
3616 }
3617
3618 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3619 int comparison, bool is_signed, int vector_len, Register rscratch) {
3620 assert(rscratch != noreg || always_reachable(src), "missing");
3621
3622 if (reachable(src)) {
3623 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3624 } else {
3625 lea(rscratch, src);
3626 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3627 }
3628 }
3629
3630 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3631 int comparison, bool is_signed, int vector_len, Register rscratch) {
3632 assert(rscratch != noreg || always_reachable(src), "missing");
3633
3634 if (reachable(src)) {
3635 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3636 } else {
3637 lea(rscratch, src);
3638 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3639 }
3640 }
3641
3642 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3643 int comparison, bool is_signed, int vector_len, Register rscratch) {
3644 assert(rscratch != noreg || always_reachable(src), "missing");
3645
3646 if (reachable(src)) {
3647 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3648 } else {
3649 lea(rscratch, src);
3650 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3651 }
3652 }
3653
3654 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3655 int comparison, bool is_signed, int vector_len, Register rscratch) {
3656 assert(rscratch != noreg || always_reachable(src), "missing");
3657
3658 if (reachable(src)) {
3659 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3660 } else {
3661 lea(rscratch, src);
3662 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3663 }
3664 }
3665
3666 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3667 if (width == Assembler::Q) {
3668 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3669 } else {
3670 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3671 }
3672 }
3673
3674 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3675 int eq_cond_enc = 0x29;
3676 int gt_cond_enc = 0x37;
3677 if (width != Assembler::Q) {
3678 eq_cond_enc = 0x74 + width;
3679 gt_cond_enc = 0x64 + width;
3680 }
3681 switch (cond) {
3682 case eq:
3683 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3684 break;
3685 case neq:
3686 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3687 vallones(xtmp, vector_len);
3688 vpxor(dst, xtmp, dst, vector_len);
3689 break;
3690 case le:
3691 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3692 vallones(xtmp, vector_len);
3693 vpxor(dst, xtmp, dst, vector_len);
3694 break;
3695 case nlt:
3696 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3697 vallones(xtmp, vector_len);
3698 vpxor(dst, xtmp, dst, vector_len);
3699 break;
3700 case lt:
3701 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3702 break;
3703 case nle:
3704 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3705 break;
3706 default:
3707 assert(false, "Should not reach here");
3708 }
3709 }
3710
3711 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3712 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3713 Assembler::vpmovzxbw(dst, src, vector_len);
3714 }
3715
3716 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3717 assert((src->encoding() < 16),"XMM register should be 0-15");
3718 Assembler::vpmovmskb(dst, src, vector_len);
3719 }
3720
3721 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3722 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3723 Assembler::vpmullw(dst, nds, src, vector_len);
3724 }
3725
3726 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3727 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3728 Assembler::vpmullw(dst, nds, src, vector_len);
3729 }
3730
3731 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3732 assert((UseAVX > 0), "AVX support is needed");
3733 assert(rscratch != noreg || always_reachable(src), "missing");
3734
3735 if (reachable(src)) {
3736 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3737 } else {
3738 lea(rscratch, src);
3739 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3740 }
3741 }
3742
3743 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3744 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3745 Assembler::vpsubb(dst, nds, src, vector_len);
3746 }
3747
3748 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3749 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3750 Assembler::vpsubb(dst, nds, src, vector_len);
3751 }
3752
3753 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3754 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3755 Assembler::vpsubw(dst, nds, src, vector_len);
3756 }
3757
3758 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3759 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3760 Assembler::vpsubw(dst, nds, src, vector_len);
3761 }
3762
3763 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3764 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3765 Assembler::vpsraw(dst, nds, shift, vector_len);
3766 }
3767
3768 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3769 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3770 Assembler::vpsraw(dst, nds, shift, vector_len);
3771 }
3772
3773 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3774 assert(UseAVX > 2,"");
3775 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3776 vector_len = 2;
3777 }
3778 Assembler::evpsraq(dst, nds, shift, vector_len);
3779 }
3780
3781 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3782 assert(UseAVX > 2,"");
3783 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3784 vector_len = 2;
3785 }
3786 Assembler::evpsraq(dst, nds, shift, vector_len);
3787 }
3788
3789 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3790 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3791 Assembler::vpsrlw(dst, nds, shift, vector_len);
3792 }
3793
3794 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3795 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3796 Assembler::vpsrlw(dst, nds, shift, vector_len);
3797 }
3798
3799 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3800 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3801 Assembler::vpsllw(dst, nds, shift, vector_len);
3802 }
3803
3804 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3805 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3806 Assembler::vpsllw(dst, nds, shift, vector_len);
3807 }
3808
3809 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3810 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3811 Assembler::vptest(dst, src);
3812 }
3813
3814 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3815 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3816 Assembler::punpcklbw(dst, src);
3817 }
3818
3819 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3820 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3821 Assembler::pshufd(dst, src, mode);
3822 }
3823
3824 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3825 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3826 Assembler::pshuflw(dst, src, mode);
3827 }
3828
3829 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3830 assert(rscratch != noreg || always_reachable(src), "missing");
3831
3832 if (reachable(src)) {
3833 vandpd(dst, nds, as_Address(src), vector_len);
3834 } else {
3835 lea(rscratch, src);
3836 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3837 }
3838 }
3839
3840 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3841 assert(rscratch != noreg || always_reachable(src), "missing");
3842
3843 if (reachable(src)) {
3844 vandps(dst, nds, as_Address(src), vector_len);
3845 } else {
3846 lea(rscratch, src);
3847 vandps(dst, nds, Address(rscratch, 0), vector_len);
3848 }
3849 }
3850
3851 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3852 bool merge, int vector_len, Register rscratch) {
3853 assert(rscratch != noreg || always_reachable(src), "missing");
3854
3855 if (reachable(src)) {
3856 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3857 } else {
3858 lea(rscratch, src);
3859 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3860 }
3861 }
3862
3863 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3864 assert(rscratch != noreg || always_reachable(src), "missing");
3865
3866 if (reachable(src)) {
3867 vdivsd(dst, nds, as_Address(src));
3868 } else {
3869 lea(rscratch, src);
3870 vdivsd(dst, nds, Address(rscratch, 0));
3871 }
3872 }
3873
3874 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3875 assert(rscratch != noreg || always_reachable(src), "missing");
3876
3877 if (reachable(src)) {
3878 vdivss(dst, nds, as_Address(src));
3879 } else {
3880 lea(rscratch, src);
3881 vdivss(dst, nds, Address(rscratch, 0));
3882 }
3883 }
3884
3885 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3886 assert(rscratch != noreg || always_reachable(src), "missing");
3887
3888 if (reachable(src)) {
3889 vmulsd(dst, nds, as_Address(src));
3890 } else {
3891 lea(rscratch, src);
3892 vmulsd(dst, nds, Address(rscratch, 0));
3893 }
3894 }
3895
3896 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3897 assert(rscratch != noreg || always_reachable(src), "missing");
3898
3899 if (reachable(src)) {
3900 vmulss(dst, nds, as_Address(src));
3901 } else {
3902 lea(rscratch, src);
3903 vmulss(dst, nds, Address(rscratch, 0));
3904 }
3905 }
3906
3907 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3908 assert(rscratch != noreg || always_reachable(src), "missing");
3909
3910 if (reachable(src)) {
3911 vsubsd(dst, nds, as_Address(src));
3912 } else {
3913 lea(rscratch, src);
3914 vsubsd(dst, nds, Address(rscratch, 0));
3915 }
3916 }
3917
3918 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3919 assert(rscratch != noreg || always_reachable(src), "missing");
3920
3921 if (reachable(src)) {
3922 vsubss(dst, nds, as_Address(src));
3923 } else {
3924 lea(rscratch, src);
3925 vsubss(dst, nds, Address(rscratch, 0));
3926 }
3927 }
3928
3929 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3930 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3931 assert(rscratch != noreg || always_reachable(src), "missing");
3932
3933 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3934 }
3935
3936 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3937 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3938 assert(rscratch != noreg || always_reachable(src), "missing");
3939
3940 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3941 }
3942
3943 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3944 assert(rscratch != noreg || always_reachable(src), "missing");
3945
3946 if (reachable(src)) {
3947 vxorpd(dst, nds, as_Address(src), vector_len);
3948 } else {
3949 lea(rscratch, src);
3950 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3951 }
3952 }
3953
3954 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3955 assert(rscratch != noreg || always_reachable(src), "missing");
3956
3957 if (reachable(src)) {
3958 vxorps(dst, nds, as_Address(src), vector_len);
3959 } else {
3960 lea(rscratch, src);
3961 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3962 }
3963 }
3964
3965 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3966 assert(rscratch != noreg || always_reachable(src), "missing");
3967
3968 if (UseAVX > 1 || (vector_len < 1)) {
3969 if (reachable(src)) {
3970 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3971 } else {
3972 lea(rscratch, src);
3973 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3974 }
3975 } else {
3976 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3977 }
3978 }
3979
3980 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3981 assert(rscratch != noreg || always_reachable(src), "missing");
3982
3983 if (reachable(src)) {
3984 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3985 } else {
3986 lea(rscratch, src);
3987 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3988 }
3989 }
3990
3991 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3992 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3993 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3994 // The inverted mask is sign-extended
3995 andptr(possibly_non_local, inverted_mask);
3996 }
3997
3998 void MacroAssembler::resolve_jobject(Register value,
3999 Register thread,
4000 Register tmp) {
4001 assert_different_registers(value, thread, tmp);
4002 Label done, tagged, weak_tagged;
4003 testptr(value, value);
4004 jcc(Assembler::zero, done); // Use null as-is.
4005 testptr(value, JNIHandles::tag_mask); // Test for tag.
4006 jcc(Assembler::notZero, tagged);
4007
4008 // Resolve local handle
4009 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp, thread);
4010 verify_oop(value);
4011 jmp(done);
4012
4013 bind(tagged);
4014 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
4015 jcc(Assembler::notZero, weak_tagged);
4016
4017 // Resolve global handle
4018 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4019 verify_oop(value);
4020 jmp(done);
4021
4022 bind(weak_tagged);
4023 // Resolve jweak.
4024 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4025 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp, thread);
4026 verify_oop(value);
4027
4028 bind(done);
4029 }
4030
4031 void MacroAssembler::resolve_global_jobject(Register value,
4032 Register thread,
4033 Register tmp) {
4034 assert_different_registers(value, thread, tmp);
4035 Label done;
4036
4037 testptr(value, value);
4038 jcc(Assembler::zero, done); // Use null as-is.
4039
4040 #ifdef ASSERT
4041 {
4042 Label valid_global_tag;
4043 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
4044 jcc(Assembler::notZero, valid_global_tag);
4045 stop("non global jobject using resolve_global_jobject");
4046 bind(valid_global_tag);
4047 }
4048 #endif
4049
4050 // Resolve global handle
4051 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4052 verify_oop(value);
4053
4054 bind(done);
4055 }
4056
4057 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4058 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4059 }
4060
4061 // Force generation of a 4 byte immediate value even if it fits into 8bit
4062 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4063 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4064 }
4065
4066 void MacroAssembler::subptr(Register dst, Register src) {
4067 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4068 }
4069
4070 // C++ bool manipulation
4071 void MacroAssembler::testbool(Register dst) {
4072 if(sizeof(bool) == 1)
4073 testb(dst, 0xff);
4074 else if(sizeof(bool) == 2) {
4075 // testw implementation needed for two byte bools
4076 ShouldNotReachHere();
4077 } else if(sizeof(bool) == 4)
4078 testl(dst, dst);
4079 else
4080 // unsupported
4081 ShouldNotReachHere();
4082 }
4083
4084 void MacroAssembler::testptr(Register dst, Register src) {
4085 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4086 }
4087
4088 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4089 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4090 Register var_size_in_bytes,
4091 int con_size_in_bytes,
4092 Register t1,
4093 Register t2,
4094 Label& slow_case) {
4095 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4096 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4097 }
4098
4099 RegSet MacroAssembler::call_clobbered_gp_registers() {
4100 RegSet regs;
4101 #ifdef _LP64
4102 regs += RegSet::of(rax, rcx, rdx);
4103 #ifndef _WINDOWS
4104 regs += RegSet::of(rsi, rdi);
4105 #endif
4106 regs += RegSet::range(r8, r11);
4107 #else
4108 regs += RegSet::of(rax, rcx, rdx);
4109 #endif
4110 #ifdef _LP64
4111 if (UseAPX) {
4112 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
4113 }
4114 #endif
4115 return regs;
4116 }
4117
4118 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
4119 int num_xmm_registers = XMMRegister::available_xmm_registers();
4120 #if defined(_WINDOWS)
4121 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
4122 if (num_xmm_registers > 16) {
4123 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
4124 }
4125 return result;
4126 #else
4127 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
4128 #endif
4129 }
4130
4131 static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor
4132
4133 #ifndef _LP64
4134 static bool use_x87_registers() { return UseSSE < 2; }
4135 #endif
4136 static bool use_xmm_registers() { return UseSSE >= 1; }
4137
4138 // C1 only ever uses the first double/float of the XMM register.
4139 static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); }
4140
4141 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4142 if (UseSSE == 1) {
4143 masm->movflt(Address(rsp, offset), reg);
4144 } else {
4145 masm->movdbl(Address(rsp, offset), reg);
4146 }
4147 }
4148
4149 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4150 if (UseSSE == 1) {
4151 masm->movflt(reg, Address(rsp, offset));
4152 } else {
4153 masm->movdbl(reg, Address(rsp, offset));
4154 }
4155 }
4156
4157 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
4158 bool save_fpu, int& gp_area_size,
4159 int& fp_area_size, int& xmm_area_size) {
4160
4161 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
4162 StackAlignmentInBytes);
4163 #ifdef _LP64
4164 fp_area_size = 0;
4165 #else
4166 fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0;
4167 #endif
4168 xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0;
4169
4170 return gp_area_size + fp_area_size + xmm_area_size;
4171 }
4172
4173 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
4174 block_comment("push_call_clobbered_registers start");
4175 // Regular registers
4176 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
4177
4178 int gp_area_size;
4179 int fp_area_size;
4180 int xmm_area_size;
4181 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
4182 gp_area_size, fp_area_size, xmm_area_size);
4183 subptr(rsp, total_save_size);
4184
4185 push_set(gp_registers_to_push, 0);
4186
4187 #ifndef _LP64
4188 if (save_fpu && use_x87_registers()) {
4189 fnsave(Address(rsp, gp_area_size));
4190 fwait();
4191 }
4192 #endif
4193 if (save_fpu && use_xmm_registers()) {
4194 push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4195 }
4196
4197 block_comment("push_call_clobbered_registers end");
4198 }
4199
4200 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
4201 block_comment("pop_call_clobbered_registers start");
4202
4203 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
4204
4205 int gp_area_size;
4206 int fp_area_size;
4207 int xmm_area_size;
4208 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
4209 gp_area_size, fp_area_size, xmm_area_size);
4210
4211 if (restore_fpu && use_xmm_registers()) {
4212 pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4213 }
4214 #ifndef _LP64
4215 if (restore_fpu && use_x87_registers()) {
4216 frstor(Address(rsp, gp_area_size));
4217 }
4218 #endif
4219
4220 pop_set(gp_registers_to_pop, 0);
4221
4222 addptr(rsp, total_save_size);
4223
4224 vzeroupper();
4225
4226 block_comment("pop_call_clobbered_registers end");
4227 }
4228
4229 void MacroAssembler::push_set(XMMRegSet set, int offset) {
4230 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
4231 int spill_offset = offset;
4232
4233 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
4234 save_xmm_register(this, spill_offset, *it);
4235 spill_offset += xmm_save_size();
4236 }
4237 }
4238
4239 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
4240 int restore_size = set.size() * xmm_save_size();
4241 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
4242
4243 int restore_offset = offset + restore_size - xmm_save_size();
4244
4245 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
4246 restore_xmm_register(this, restore_offset, *it);
4247 restore_offset -= xmm_save_size();
4248 }
4249 }
4250
4251 void MacroAssembler::push_set(RegSet set, int offset) {
4252 int spill_offset;
4253 if (offset == -1) {
4254 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4255 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4256 subptr(rsp, aligned_size);
4257 spill_offset = 0;
4258 } else {
4259 spill_offset = offset;
4260 }
4261
4262 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
4263 movptr(Address(rsp, spill_offset), *it);
4264 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4265 }
4266 }
4267
4268 void MacroAssembler::pop_set(RegSet set, int offset) {
4269
4270 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4271 int restore_size = set.size() * gp_reg_size;
4272 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
4273
4274 int restore_offset;
4275 if (offset == -1) {
4276 restore_offset = restore_size - gp_reg_size;
4277 } else {
4278 restore_offset = offset + restore_size - gp_reg_size;
4279 }
4280 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
4281 movptr(*it, Address(rsp, restore_offset));
4282 restore_offset -= gp_reg_size;
4283 }
4284
4285 if (offset == -1) {
4286 addptr(rsp, aligned_size);
4287 }
4288 }
4289
4290 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4291 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4292 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4293 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4294 Label done;
4295
4296 testptr(length_in_bytes, length_in_bytes);
4297 jcc(Assembler::zero, done);
4298
4299 // initialize topmost word, divide index by 2, check if odd and test if zero
4300 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4301 #ifdef ASSERT
4302 {
4303 Label L;
4304 testptr(length_in_bytes, BytesPerWord - 1);
4305 jcc(Assembler::zero, L);
4306 stop("length must be a multiple of BytesPerWord");
4307 bind(L);
4308 }
4309 #endif
4310 Register index = length_in_bytes;
4311 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4312 if (UseIncDec) {
4313 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4314 } else {
4315 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4316 shrptr(index, 1);
4317 }
4318 #ifndef _LP64
4319 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4320 {
4321 Label even;
4322 // note: if index was a multiple of 8, then it cannot
4323 // be 0 now otherwise it must have been 0 before
4324 // => if it is even, we don't need to check for 0 again
4325 jcc(Assembler::carryClear, even);
4326 // clear topmost word (no jump would be needed if conditional assignment worked here)
4327 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4328 // index could be 0 now, must check again
4329 jcc(Assembler::zero, done);
4330 bind(even);
4331 }
4332 #endif // !_LP64
4333 // initialize remaining object fields: index is a multiple of 2 now
4334 {
4335 Label loop;
4336 bind(loop);
4337 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4338 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4339 decrement(index);
4340 jcc(Assembler::notZero, loop);
4341 }
4342
4343 bind(done);
4344 }
4345
4346 // Look up the method for a megamorphic invokeinterface call.
4347 // The target method is determined by <intf_klass, itable_index>.
4348 // The receiver klass is in recv_klass.
4349 // On success, the result will be in method_result, and execution falls through.
4350 // On failure, execution transfers to the given label.
4351 void MacroAssembler::lookup_interface_method(Register recv_klass,
4352 Register intf_klass,
4353 RegisterOrConstant itable_index,
4354 Register method_result,
4355 Register scan_temp,
4356 Label& L_no_such_interface,
4357 bool return_method) {
4358 assert_different_registers(recv_klass, intf_klass, scan_temp);
4359 assert_different_registers(method_result, intf_klass, scan_temp);
4360 assert(recv_klass != method_result || !return_method,
4361 "recv_klass can be destroyed when method isn't needed");
4362
4363 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4364 "caller must use same register for non-constant itable index as for method");
4365
4366 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4367 int vtable_base = in_bytes(Klass::vtable_start_offset());
4368 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4369 int scan_step = itableOffsetEntry::size() * wordSize;
4370 int vte_size = vtableEntry::size_in_bytes();
4371 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4372 assert(vte_size == wordSize, "else adjust times_vte_scale");
4373
4374 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4375
4376 // Could store the aligned, prescaled offset in the klass.
4377 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4378
4379 if (return_method) {
4380 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4381 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4382 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4383 }
4384
4385 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
4386 // if (scan->interface() == intf) {
4387 // result = (klass + scan->offset() + itable_index);
4388 // }
4389 // }
4390 Label search, found_method;
4391
4392 for (int peel = 1; peel >= 0; peel--) {
4393 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
4394 cmpptr(intf_klass, method_result);
4395
4396 if (peel) {
4397 jccb(Assembler::equal, found_method);
4398 } else {
4399 jccb(Assembler::notEqual, search);
4400 // (invert the test to fall through to found_method...)
4401 }
4402
4403 if (!peel) break;
4404
4405 bind(search);
4406
4407 // Check that the previous entry is non-null. A null entry means that
4408 // the receiver class doesn't implement the interface, and wasn't the
4409 // same as when the caller was compiled.
4410 testptr(method_result, method_result);
4411 jcc(Assembler::zero, L_no_such_interface);
4412 addptr(scan_temp, scan_step);
4413 }
4414
4415 bind(found_method);
4416
4417 if (return_method) {
4418 // Got a hit.
4419 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
4420 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4421 }
4422 }
4423
4424 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
4425 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
4426 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
4427 // The target method is determined by <holder_klass, itable_index>.
4428 // The receiver klass is in recv_klass.
4429 // On success, the result will be in method_result, and execution falls through.
4430 // On failure, execution transfers to the given label.
4431 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
4432 Register holder_klass,
4433 Register resolved_klass,
4434 Register method_result,
4435 Register scan_temp,
4436 Register temp_reg2,
4437 Register receiver,
4438 int itable_index,
4439 Label& L_no_such_interface) {
4440 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
4441 Register temp_itbl_klass = method_result;
4442 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
4443
4444 int vtable_base = in_bytes(Klass::vtable_start_offset());
4445 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4446 int scan_step = itableOffsetEntry::size() * wordSize;
4447 int vte_size = vtableEntry::size_in_bytes();
4448 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
4449 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
4450 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4451 assert(vte_size == wordSize, "adjust times_vte_scale");
4452
4453 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
4454
4455 // temp_itbl_klass = recv_klass.itable[0]
4456 // scan_temp = &recv_klass.itable[0] + step
4457 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4458 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
4459 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
4460 xorptr(temp_reg, temp_reg);
4461
4462 // Initial checks:
4463 // - if (holder_klass != resolved_klass), go to "scan for resolved"
4464 // - if (itable[0] == 0), no such interface
4465 // - if (itable[0] == holder_klass), shortcut to "holder found"
4466 cmpptr(holder_klass, resolved_klass);
4467 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
4468 testptr(temp_itbl_klass, temp_itbl_klass);
4469 jccb(Assembler::zero, L_no_such_interface);
4470 cmpptr(holder_klass, temp_itbl_klass);
4471 jccb(Assembler::equal, L_holder_found);
4472
4473 // Loop: Look for holder_klass record in itable
4474 // do {
4475 // tmp = itable[index];
4476 // index += step;
4477 // if (tmp == holder_klass) {
4478 // goto L_holder_found; // Found!
4479 // }
4480 // } while (tmp != 0);
4481 // goto L_no_such_interface // Not found.
4482 Label L_scan_holder;
4483 bind(L_scan_holder);
4484 movptr(temp_itbl_klass, Address(scan_temp, 0));
4485 addptr(scan_temp, scan_step);
4486 cmpptr(holder_klass, temp_itbl_klass);
4487 jccb(Assembler::equal, L_holder_found);
4488 testptr(temp_itbl_klass, temp_itbl_klass);
4489 jccb(Assembler::notZero, L_scan_holder);
4490
4491 jmpb(L_no_such_interface);
4492
4493 // Loop: Look for resolved_class record in itable
4494 // do {
4495 // tmp = itable[index];
4496 // index += step;
4497 // if (tmp == holder_klass) {
4498 // // Also check if we have met a holder klass
4499 // holder_tmp = itable[index-step-ioffset];
4500 // }
4501 // if (tmp == resolved_klass) {
4502 // goto L_resolved_found; // Found!
4503 // }
4504 // } while (tmp != 0);
4505 // goto L_no_such_interface // Not found.
4506 //
4507 Label L_loop_scan_resolved;
4508 bind(L_loop_scan_resolved);
4509 movptr(temp_itbl_klass, Address(scan_temp, 0));
4510 addptr(scan_temp, scan_step);
4511 bind(L_loop_scan_resolved_entry);
4512 cmpptr(holder_klass, temp_itbl_klass);
4513 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4514 cmpptr(resolved_klass, temp_itbl_klass);
4515 jccb(Assembler::equal, L_resolved_found);
4516 testptr(temp_itbl_klass, temp_itbl_klass);
4517 jccb(Assembler::notZero, L_loop_scan_resolved);
4518
4519 jmpb(L_no_such_interface);
4520
4521 Label L_ready;
4522
4523 // See if we already have a holder klass. If not, go and scan for it.
4524 bind(L_resolved_found);
4525 testptr(temp_reg, temp_reg);
4526 jccb(Assembler::zero, L_scan_holder);
4527 jmpb(L_ready);
4528
4529 bind(L_holder_found);
4530 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4531
4532 // Finally, temp_reg contains holder_klass vtable offset
4533 bind(L_ready);
4534 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4535 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4536 load_klass(scan_temp, receiver, noreg);
4537 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4538 } else {
4539 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4540 }
4541 }
4542
4543
4544 // virtual method calling
4545 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4546 RegisterOrConstant vtable_index,
4547 Register method_result) {
4548 const ByteSize base = Klass::vtable_start_offset();
4549 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4550 Address vtable_entry_addr(recv_klass,
4551 vtable_index, Address::times_ptr,
4552 base + vtableEntry::method_offset());
4553 movptr(method_result, vtable_entry_addr);
4554 }
4555
4556
4557 void MacroAssembler::check_klass_subtype(Register sub_klass,
4558 Register super_klass,
4559 Register temp_reg,
4560 Label& L_success) {
4561 Label L_failure;
4562 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4563 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4564 bind(L_failure);
4565 }
4566
4567
4568 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4569 Register super_klass,
4570 Register temp_reg,
4571 Label* L_success,
4572 Label* L_failure,
4573 Label* L_slow_path,
4574 RegisterOrConstant super_check_offset) {
4575 assert_different_registers(sub_klass, super_klass, temp_reg);
4576 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4577 if (super_check_offset.is_register()) {
4578 assert_different_registers(sub_klass, super_klass,
4579 super_check_offset.as_register());
4580 } else if (must_load_sco) {
4581 assert(temp_reg != noreg, "supply either a temp or a register offset");
4582 }
4583
4584 Label L_fallthrough;
4585 int label_nulls = 0;
4586 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4587 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4588 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4589 assert(label_nulls <= 1, "at most one null in the batch");
4590
4591 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4592 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4593 Address super_check_offset_addr(super_klass, sco_offset);
4594
4595 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4596 // range of a jccb. If this routine grows larger, reconsider at
4597 // least some of these.
4598 #define local_jcc(assembler_cond, label) \
4599 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4600 else jcc( assembler_cond, label) /*omit semi*/
4601
4602 // Hacked jmp, which may only be used just before L_fallthrough.
4603 #define final_jmp(label) \
4604 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4605 else jmp(label) /*omit semi*/
4606
4607 // If the pointers are equal, we are done (e.g., String[] elements).
4608 // This self-check enables sharing of secondary supertype arrays among
4609 // non-primary types such as array-of-interface. Otherwise, each such
4610 // type would need its own customized SSA.
4611 // We move this check to the front of the fast path because many
4612 // type checks are in fact trivially successful in this manner,
4613 // so we get a nicely predicted branch right at the start of the check.
4614 cmpptr(sub_klass, super_klass);
4615 local_jcc(Assembler::equal, *L_success);
4616
4617 // Check the supertype display:
4618 if (must_load_sco) {
4619 // Positive movl does right thing on LP64.
4620 movl(temp_reg, super_check_offset_addr);
4621 super_check_offset = RegisterOrConstant(temp_reg);
4622 }
4623 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4624 cmpptr(super_klass, super_check_addr); // load displayed supertype
4625
4626 // This check has worked decisively for primary supers.
4627 // Secondary supers are sought in the super_cache ('super_cache_addr').
4628 // (Secondary supers are interfaces and very deeply nested subtypes.)
4629 // This works in the same check above because of a tricky aliasing
4630 // between the super_cache and the primary super display elements.
4631 // (The 'super_check_addr' can address either, as the case requires.)
4632 // Note that the cache is updated below if it does not help us find
4633 // what we need immediately.
4634 // So if it was a primary super, we can just fail immediately.
4635 // Otherwise, it's the slow path for us (no success at this point).
4636
4637 if (super_check_offset.is_register()) {
4638 local_jcc(Assembler::equal, *L_success);
4639 cmpl(super_check_offset.as_register(), sc_offset);
4640 if (L_failure == &L_fallthrough) {
4641 local_jcc(Assembler::equal, *L_slow_path);
4642 } else {
4643 local_jcc(Assembler::notEqual, *L_failure);
4644 final_jmp(*L_slow_path);
4645 }
4646 } else if (super_check_offset.as_constant() == sc_offset) {
4647 // Need a slow path; fast failure is impossible.
4648 if (L_slow_path == &L_fallthrough) {
4649 local_jcc(Assembler::equal, *L_success);
4650 } else {
4651 local_jcc(Assembler::notEqual, *L_slow_path);
4652 final_jmp(*L_success);
4653 }
4654 } else {
4655 // No slow path; it's a fast decision.
4656 if (L_failure == &L_fallthrough) {
4657 local_jcc(Assembler::equal, *L_success);
4658 } else {
4659 local_jcc(Assembler::notEqual, *L_failure);
4660 final_jmp(*L_success);
4661 }
4662 }
4663
4664 bind(L_fallthrough);
4665
4666 #undef local_jcc
4667 #undef final_jmp
4668 }
4669
4670
4671 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4672 Register super_klass,
4673 Register temp_reg,
4674 Register temp2_reg,
4675 Label* L_success,
4676 Label* L_failure,
4677 bool set_cond_codes) {
4678 assert_different_registers(sub_klass, super_klass, temp_reg);
4679 if (temp2_reg != noreg)
4680 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4681 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4682
4683 Label L_fallthrough;
4684 int label_nulls = 0;
4685 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4686 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4687 assert(label_nulls <= 1, "at most one null in the batch");
4688
4689 // a couple of useful fields in sub_klass:
4690 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4691 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4692 Address secondary_supers_addr(sub_klass, ss_offset);
4693 Address super_cache_addr( sub_klass, sc_offset);
4694
4695 // Do a linear scan of the secondary super-klass chain.
4696 // This code is rarely used, so simplicity is a virtue here.
4697 // The repne_scan instruction uses fixed registers, which we must spill.
4698 // Don't worry too much about pre-existing connections with the input regs.
4699
4700 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4701 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4702
4703 // Get super_klass value into rax (even if it was in rdi or rcx).
4704 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4705 if (super_klass != rax) {
4706 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4707 mov(rax, super_klass);
4708 }
4709 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4710 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4711
4712 #ifndef PRODUCT
4713 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4714 ExternalAddress pst_counter_addr((address) pst_counter);
4715 NOT_LP64( incrementl(pst_counter_addr) );
4716 LP64_ONLY( lea(rcx, pst_counter_addr) );
4717 LP64_ONLY( incrementl(Address(rcx, 0)) );
4718 #endif //PRODUCT
4719
4720 // We will consult the secondary-super array.
4721 movptr(rdi, secondary_supers_addr);
4722 // Load the array length. (Positive movl does right thing on LP64.)
4723 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4724 // Skip to start of data.
4725 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4726
4727 // Scan RCX words at [RDI] for an occurrence of RAX.
4728 // Set NZ/Z based on last compare.
4729 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4730 // not change flags (only scas instruction which is repeated sets flags).
4731 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4732
4733 testptr(rax,rax); // Set Z = 0
4734 repne_scan();
4735
4736 // Unspill the temp. registers:
4737 if (pushed_rdi) pop(rdi);
4738 if (pushed_rcx) pop(rcx);
4739 if (pushed_rax) pop(rax);
4740
4741 if (set_cond_codes) {
4742 // Special hack for the AD files: rdi is guaranteed non-zero.
4743 assert(!pushed_rdi, "rdi must be left non-null");
4744 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4745 }
4746
4747 if (L_failure == &L_fallthrough)
4748 jccb(Assembler::notEqual, *L_failure);
4749 else jcc(Assembler::notEqual, *L_failure);
4750
4751 // Success. Cache the super we found and proceed in triumph.
4752 movptr(super_cache_addr, super_klass);
4753
4754 if (L_success != &L_fallthrough) {
4755 jmp(*L_success);
4756 }
4757
4758 #undef IS_A_TEMP
4759
4760 bind(L_fallthrough);
4761 }
4762
4763 #ifndef _LP64
4764
4765 // 32-bit x86 only: always use the linear search.
4766 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4767 Register super_klass,
4768 Register temp_reg,
4769 Register temp2_reg,
4770 Label* L_success,
4771 Label* L_failure,
4772 bool set_cond_codes) {
4773 check_klass_subtype_slow_path_linear
4774 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
4775 }
4776
4777 #else // _LP64
4778
4779 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4780 Register super_klass,
4781 Register temp_reg,
4782 Register temp2_reg,
4783 Label* L_success,
4784 Label* L_failure,
4785 bool set_cond_codes) {
4786 assert(set_cond_codes == false, "must be false on 64-bit x86");
4787 check_klass_subtype_slow_path
4788 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4789 L_success, L_failure);
4790 }
4791
4792 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4793 Register super_klass,
4794 Register temp_reg,
4795 Register temp2_reg,
4796 Register temp3_reg,
4797 Register temp4_reg,
4798 Label* L_success,
4799 Label* L_failure) {
4800 if (UseSecondarySupersTable) {
4801 check_klass_subtype_slow_path_table
4802 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4803 L_success, L_failure);
4804 } else {
4805 check_klass_subtype_slow_path_linear
4806 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4807 }
4808 }
4809
4810 Register MacroAssembler::allocate_if_noreg(Register r,
4811 RegSetIterator<Register> &available_regs,
4812 RegSet ®s_to_push) {
4813 if (!r->is_valid()) {
4814 r = *available_regs++;
4815 regs_to_push += r;
4816 }
4817 return r;
4818 }
4819
4820 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4821 Register super_klass,
4822 Register temp_reg,
4823 Register temp2_reg,
4824 Register temp3_reg,
4825 Register result_reg,
4826 Label* L_success,
4827 Label* L_failure) {
4828 // NB! Callers may assume that, when temp2_reg is a valid register,
4829 // this code sets it to a nonzero value.
4830 bool temp2_reg_was_valid = temp2_reg->is_valid();
4831
4832 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4833
4834 Label L_fallthrough;
4835 int label_nulls = 0;
4836 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4837 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4838 assert(label_nulls <= 1, "at most one null in the batch");
4839
4840 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4841
4842 RegSetIterator<Register> available_regs
4843 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4844
4845 RegSet pushed_regs;
4846
4847 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4848 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4849 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4850 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4851 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4852
4853 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4854
4855 {
4856
4857 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4858 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4859 subptr(rsp, aligned_size);
4860 push_set(pushed_regs, 0);
4861
4862 lookup_secondary_supers_table_var(sub_klass,
4863 super_klass,
4864 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4865 cmpq(result_reg, 0);
4866
4867 // Unspill the temp. registers:
4868 pop_set(pushed_regs, 0);
4869 // Increment SP but do not clobber flags.
4870 lea(rsp, Address(rsp, aligned_size));
4871 }
4872
4873 if (temp2_reg_was_valid) {
4874 movq(temp2_reg, 1);
4875 }
4876
4877 jcc(Assembler::notEqual, *L_failure);
4878
4879 if (L_success != &L_fallthrough) {
4880 jmp(*L_success);
4881 }
4882
4883 bind(L_fallthrough);
4884 }
4885
4886 // population_count variant for running without the POPCNT
4887 // instruction, which was introduced with SSE4.2 in 2008.
4888 void MacroAssembler::population_count(Register dst, Register src,
4889 Register scratch1, Register scratch2) {
4890 assert_different_registers(src, scratch1, scratch2);
4891 if (UsePopCountInstruction) {
4892 Assembler::popcntq(dst, src);
4893 } else {
4894 assert_different_registers(src, scratch1, scratch2);
4895 assert_different_registers(dst, scratch1, scratch2);
4896 Label loop, done;
4897
4898 mov(scratch1, src);
4899 // dst = 0;
4900 // while(scratch1 != 0) {
4901 // dst++;
4902 // scratch1 &= (scratch1 - 1);
4903 // }
4904 xorl(dst, dst);
4905 testq(scratch1, scratch1);
4906 jccb(Assembler::equal, done);
4907 {
4908 bind(loop);
4909 incq(dst);
4910 movq(scratch2, scratch1);
4911 decq(scratch2);
4912 andq(scratch1, scratch2);
4913 jccb(Assembler::notEqual, loop);
4914 }
4915 bind(done);
4916 }
4917 }
4918
4919 // Ensure that the inline code and the stub are using the same registers.
4920 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4921 do { \
4922 assert(r_super_klass == rax, "mismatch"); \
4923 assert(r_array_base == rbx, "mismatch"); \
4924 assert(r_array_length == rcx, "mismatch"); \
4925 assert(r_array_index == rdx, "mismatch"); \
4926 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4927 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4928 assert(result == rdi || result == noreg, "mismatch"); \
4929 } while(0)
4930
4931 // Versions of salq and rorq that don't need count to be in rcx
4932
4933 void MacroAssembler::salq(Register dest, Register count) {
4934 if (count == rcx) {
4935 Assembler::salq(dest);
4936 } else {
4937 assert_different_registers(rcx, dest);
4938 xchgq(rcx, count);
4939 Assembler::salq(dest);
4940 xchgq(rcx, count);
4941 }
4942 }
4943
4944 void MacroAssembler::rorq(Register dest, Register count) {
4945 if (count == rcx) {
4946 Assembler::rorq(dest);
4947 } else {
4948 assert_different_registers(rcx, dest);
4949 xchgq(rcx, count);
4950 Assembler::rorq(dest);
4951 xchgq(rcx, count);
4952 }
4953 }
4954
4955 // Return true: we succeeded in generating this code
4956 //
4957 // At runtime, return 0 in result if r_super_klass is a superclass of
4958 // r_sub_klass, otherwise return nonzero. Use this if you know the
4959 // super_klass_slot of the class you're looking for. This is always
4960 // the case for instanceof and checkcast.
4961 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4962 Register r_super_klass,
4963 Register temp1,
4964 Register temp2,
4965 Register temp3,
4966 Register temp4,
4967 Register result,
4968 u1 super_klass_slot) {
4969 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4970
4971 Label L_fallthrough, L_success, L_failure;
4972
4973 BLOCK_COMMENT("lookup_secondary_supers_table {");
4974
4975 const Register
4976 r_array_index = temp1,
4977 r_array_length = temp2,
4978 r_array_base = temp3,
4979 r_bitmap = temp4;
4980
4981 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4982
4983 xorq(result, result); // = 0
4984
4985 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4986 movq(r_array_index, r_bitmap);
4987
4988 // First check the bitmap to see if super_klass might be present. If
4989 // the bit is zero, we are certain that super_klass is not one of
4990 // the secondary supers.
4991 u1 bit = super_klass_slot;
4992 {
4993 // NB: If the count in a x86 shift instruction is 0, the flags are
4994 // not affected, so we do a testq instead.
4995 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4996 if (shift_count != 0) {
4997 salq(r_array_index, shift_count);
4998 } else {
4999 testq(r_array_index, r_array_index);
5000 }
5001 }
5002 // We test the MSB of r_array_index, i.e. its sign bit
5003 jcc(Assembler::positive, L_failure);
5004
5005 // Get the first array index that can contain super_klass into r_array_index.
5006 if (bit != 0) {
5007 population_count(r_array_index, r_array_index, temp2, temp3);
5008 } else {
5009 movl(r_array_index, 1);
5010 }
5011 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5012
5013 // We will consult the secondary-super array.
5014 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5015
5016 // We're asserting that the first word in an Array<Klass*> is the
5017 // length, and the second word is the first word of the data. If
5018 // that ever changes, r_array_base will have to be adjusted here.
5019 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5020 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5021
5022 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5023 jccb(Assembler::equal, L_success);
5024
5025 // Is there another entry to check? Consult the bitmap.
5026 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
5027 jccb(Assembler::carryClear, L_failure);
5028
5029 // Linear probe. Rotate the bitmap so that the next bit to test is
5030 // in Bit 1.
5031 if (bit != 0) {
5032 rorq(r_bitmap, bit);
5033 }
5034
5035 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5036 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5037 // Kills: r_array_length.
5038 // Returns: result.
5039 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
5040 // Result (0/1) is in rdi
5041 jmpb(L_fallthrough);
5042
5043 bind(L_failure);
5044 incq(result); // 0 => 1
5045
5046 bind(L_success);
5047 // result = 0;
5048
5049 bind(L_fallthrough);
5050 BLOCK_COMMENT("} lookup_secondary_supers_table");
5051
5052 if (VerifySecondarySupers) {
5053 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5054 temp1, temp2, temp3);
5055 }
5056 }
5057
5058 // At runtime, return 0 in result if r_super_klass is a superclass of
5059 // r_sub_klass, otherwise return nonzero. Use this version of
5060 // lookup_secondary_supers_table() if you don't know ahead of time
5061 // which superclass will be searched for. Used by interpreter and
5062 // runtime stubs. It is larger and has somewhat greater latency than
5063 // the version above, which takes a constant super_klass_slot.
5064 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
5065 Register r_super_klass,
5066 Register temp1,
5067 Register temp2,
5068 Register temp3,
5069 Register temp4,
5070 Register result) {
5071 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
5072 assert_different_registers(r_sub_klass, r_super_klass, rcx);
5073 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
5074
5075 Label L_fallthrough, L_success, L_failure;
5076
5077 BLOCK_COMMENT("lookup_secondary_supers_table {");
5078
5079 RegSetIterator<Register> available_regs = (temps - rcx).begin();
5080
5081 // FIXME. Once we are sure that all paths reaching this point really
5082 // do pass rcx as one of our temps we can get rid of the following
5083 // workaround.
5084 assert(temps.contains(rcx), "fix this code");
5085
5086 // We prefer to have our shift count in rcx. If rcx is one of our
5087 // temps, use it for slot. If not, pick any of our temps.
5088 Register slot;
5089 if (!temps.contains(rcx)) {
5090 slot = *available_regs++;
5091 } else {
5092 slot = rcx;
5093 }
5094
5095 const Register r_array_index = *available_regs++;
5096 const Register r_bitmap = *available_regs++;
5097
5098 // The logic above guarantees this property, but we state it here.
5099 assert_different_registers(r_array_index, r_bitmap, rcx);
5100
5101 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
5102 movq(r_array_index, r_bitmap);
5103
5104 // First check the bitmap to see if super_klass might be present. If
5105 // the bit is zero, we are certain that super_klass is not one of
5106 // the secondary supers.
5107 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
5108 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
5109 salq(r_array_index, slot);
5110
5111 testq(r_array_index, r_array_index);
5112 // We test the MSB of r_array_index, i.e. its sign bit
5113 jcc(Assembler::positive, L_failure);
5114
5115 const Register r_array_base = *available_regs++;
5116
5117 // Get the first array index that can contain super_klass into r_array_index.
5118 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
5119
5120 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5121
5122 // We will consult the secondary-super array.
5123 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5124
5125 // We're asserting that the first word in an Array<Klass*> is the
5126 // length, and the second word is the first word of the data. If
5127 // that ever changes, r_array_base will have to be adjusted here.
5128 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5129 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5130
5131 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5132 jccb(Assembler::equal, L_success);
5133
5134 // Restore slot to its true value
5135 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
5136
5137 // Linear probe. Rotate the bitmap so that the next bit to test is
5138 // in Bit 1.
5139 rorq(r_bitmap, slot);
5140
5141 // Is there another entry to check? Consult the bitmap.
5142 btq(r_bitmap, 1);
5143 jccb(Assembler::carryClear, L_failure);
5144
5145 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5146 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5147 // Kills: r_array_length.
5148 // Returns: result.
5149 lookup_secondary_supers_table_slow_path(r_super_klass,
5150 r_array_base,
5151 r_array_index,
5152 r_bitmap,
5153 /*temp1*/result,
5154 /*temp2*/slot,
5155 &L_success,
5156 nullptr);
5157
5158 bind(L_failure);
5159 movq(result, 1);
5160 jmpb(L_fallthrough);
5161
5162 bind(L_success);
5163 xorq(result, result); // = 0
5164
5165 bind(L_fallthrough);
5166 BLOCK_COMMENT("} lookup_secondary_supers_table");
5167
5168 if (VerifySecondarySupers) {
5169 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5170 temp1, temp2, temp3);
5171 }
5172 }
5173
5174 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
5175 Label* L_success, Label* L_failure) {
5176 Label L_loop, L_fallthrough;
5177 {
5178 int label_nulls = 0;
5179 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5180 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5181 assert(label_nulls <= 1, "at most one null in the batch");
5182 }
5183 bind(L_loop);
5184 cmpq(value, Address(addr, count, Address::times_8));
5185 jcc(Assembler::equal, *L_success);
5186 addl(count, 1);
5187 cmpl(count, limit);
5188 jcc(Assembler::less, L_loop);
5189
5190 if (&L_fallthrough != L_failure) {
5191 jmp(*L_failure);
5192 }
5193 bind(L_fallthrough);
5194 }
5195
5196 // Called by code generated by check_klass_subtype_slow_path
5197 // above. This is called when there is a collision in the hashed
5198 // lookup in the secondary supers array.
5199 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
5200 Register r_array_base,
5201 Register r_array_index,
5202 Register r_bitmap,
5203 Register temp1,
5204 Register temp2,
5205 Label* L_success,
5206 Label* L_failure) {
5207 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
5208
5209 const Register
5210 r_array_length = temp1,
5211 r_sub_klass = noreg,
5212 result = noreg;
5213
5214 Label L_fallthrough;
5215 int label_nulls = 0;
5216 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5217 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5218 assert(label_nulls <= 1, "at most one null in the batch");
5219
5220 // Load the array length.
5221 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5222 // And adjust the array base to point to the data.
5223 // NB! Effectively increments current slot index by 1.
5224 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
5225 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5226
5227 // Linear probe
5228 Label L_huge;
5229
5230 // The bitmap is full to bursting.
5231 // Implicit invariant: BITMAP_FULL implies (length > 0)
5232 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
5233 jcc(Assembler::greater, L_huge);
5234
5235 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
5236 // current slot (at secondary_supers[r_array_index]) has not yet
5237 // been inspected, and r_array_index may be out of bounds if we
5238 // wrapped around the end of the array.
5239
5240 { // This is conventional linear probing, but instead of terminating
5241 // when a null entry is found in the table, we maintain a bitmap
5242 // in which a 0 indicates missing entries.
5243 // The check above guarantees there are 0s in the bitmap, so the loop
5244 // eventually terminates.
5245
5246 xorl(temp2, temp2); // = 0;
5247
5248 Label L_again;
5249 bind(L_again);
5250
5251 // Check for array wraparound.
5252 cmpl(r_array_index, r_array_length);
5253 cmovl(Assembler::greaterEqual, r_array_index, temp2);
5254
5255 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5256 jcc(Assembler::equal, *L_success);
5257
5258 // If the next bit in bitmap is zero, we're done.
5259 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
5260 jcc(Assembler::carryClear, *L_failure);
5261
5262 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
5263 addl(r_array_index, 1);
5264
5265 jmp(L_again);
5266 }
5267
5268 { // Degenerate case: more than 64 secondary supers.
5269 // FIXME: We could do something smarter here, maybe a vectorized
5270 // comparison or a binary search, but is that worth any added
5271 // complexity?
5272 bind(L_huge);
5273 xorl(r_array_index, r_array_index); // = 0
5274 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
5275 L_success,
5276 (&L_fallthrough != L_failure ? L_failure : nullptr));
5277
5278 bind(L_fallthrough);
5279 }
5280 }
5281
5282 struct VerifyHelperArguments {
5283 Klass* _super;
5284 Klass* _sub;
5285 intptr_t _linear_result;
5286 intptr_t _table_result;
5287 };
5288
5289 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
5290 Klass::on_secondary_supers_verification_failure(args->_super,
5291 args->_sub,
5292 args->_linear_result,
5293 args->_table_result,
5294 msg);
5295 }
5296
5297 // Make sure that the hashed lookup and a linear scan agree.
5298 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
5299 Register r_super_klass,
5300 Register result,
5301 Register temp1,
5302 Register temp2,
5303 Register temp3) {
5304 const Register
5305 r_array_index = temp1,
5306 r_array_length = temp2,
5307 r_array_base = temp3,
5308 r_bitmap = noreg;
5309
5310 BLOCK_COMMENT("verify_secondary_supers_table {");
5311
5312 Label L_success, L_failure, L_check, L_done;
5313
5314 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5315 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5316 // And adjust the array base to point to the data.
5317 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5318
5319 testl(r_array_length, r_array_length); // array_length == 0?
5320 jcc(Assembler::zero, L_failure);
5321
5322 movl(r_array_index, 0);
5323 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
5324 // fall through to L_failure
5325
5326 const Register linear_result = r_array_index; // reuse temp1
5327
5328 bind(L_failure); // not present
5329 movl(linear_result, 1);
5330 jmp(L_check);
5331
5332 bind(L_success); // present
5333 movl(linear_result, 0);
5334
5335 bind(L_check);
5336 cmpl(linear_result, result);
5337 jcc(Assembler::equal, L_done);
5338
5339 { // To avoid calling convention issues, build a record on the stack
5340 // and pass the pointer to that instead.
5341 push(result);
5342 push(linear_result);
5343 push(r_sub_klass);
5344 push(r_super_klass);
5345 movptr(c_rarg1, rsp);
5346 movptr(c_rarg0, (uintptr_t) "mismatch");
5347 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
5348 should_not_reach_here();
5349 }
5350 bind(L_done);
5351
5352 BLOCK_COMMENT("} verify_secondary_supers_table");
5353 }
5354
5355 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
5356
5357 #endif // LP64
5358
5359 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
5360 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
5361
5362 Label L_fallthrough;
5363 if (L_fast_path == nullptr) {
5364 L_fast_path = &L_fallthrough;
5365 } else if (L_slow_path == nullptr) {
5366 L_slow_path = &L_fallthrough;
5367 }
5368
5369 // Fast path check: class is fully initialized.
5370 // init_state needs acquire, but x86 is TSO, and so we are already good.
5371 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
5372 jcc(Assembler::equal, *L_fast_path);
5373
5374 // Fast path check: current thread is initializer thread
5375 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
5376 if (L_slow_path == &L_fallthrough) {
5377 jcc(Assembler::equal, *L_fast_path);
5378 bind(*L_slow_path);
5379 } else if (L_fast_path == &L_fallthrough) {
5380 jcc(Assembler::notEqual, *L_slow_path);
5381 bind(*L_fast_path);
5382 } else {
5383 Unimplemented();
5384 }
5385 }
5386
5387 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5388 if (VM_Version::supports_cmov()) {
5389 cmovl(cc, dst, src);
5390 } else {
5391 Label L;
5392 jccb(negate_condition(cc), L);
5393 movl(dst, src);
5394 bind(L);
5395 }
5396 }
5397
5398 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5399 if (VM_Version::supports_cmov()) {
5400 cmovl(cc, dst, src);
5401 } else {
5402 Label L;
5403 jccb(negate_condition(cc), L);
5404 movl(dst, src);
5405 bind(L);
5406 }
5407 }
5408
5409 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
5410 if (!VerifyOops) return;
5411
5412 BLOCK_COMMENT("verify_oop {");
5413 #ifdef _LP64
5414 push(rscratch1);
5415 #endif
5416 push(rax); // save rax
5417 push(reg); // pass register argument
5418
5419 // Pass register number to verify_oop_subroutine
5420 const char* b = nullptr;
5421 {
5422 ResourceMark rm;
5423 stringStream ss;
5424 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5425 b = code_string(ss.as_string());
5426 }
5427 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5428 pushptr(buffer.addr(), rscratch1);
5429
5430 // call indirectly to solve generation ordering problem
5431 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5432 call(rax);
5433 // Caller pops the arguments (oop, message) and restores rax, r10
5434 BLOCK_COMMENT("} verify_oop");
5435 }
5436
5437 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
5438 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
5439 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
5440 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
5441 vpternlogd(dst, 0xFF, dst, dst, vector_len);
5442 } else if (VM_Version::supports_avx()) {
5443 vpcmpeqd(dst, dst, dst, vector_len);
5444 } else {
5445 assert(VM_Version::supports_sse2(), "");
5446 pcmpeqd(dst, dst);
5447 }
5448 }
5449
5450 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5451 int extra_slot_offset) {
5452 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5453 int stackElementSize = Interpreter::stackElementSize;
5454 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5455 #ifdef ASSERT
5456 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5457 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5458 #endif
5459 Register scale_reg = noreg;
5460 Address::ScaleFactor scale_factor = Address::no_scale;
5461 if (arg_slot.is_constant()) {
5462 offset += arg_slot.as_constant() * stackElementSize;
5463 } else {
5464 scale_reg = arg_slot.as_register();
5465 scale_factor = Address::times(stackElementSize);
5466 }
5467 offset += wordSize; // return PC is on stack
5468 return Address(rsp, scale_reg, scale_factor, offset);
5469 }
5470
5471 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5472 if (!VerifyOops) return;
5473
5474 #ifdef _LP64
5475 push(rscratch1);
5476 #endif
5477 push(rax); // save rax,
5478 // addr may contain rsp so we will have to adjust it based on the push
5479 // we just did (and on 64 bit we do two pushes)
5480 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5481 // stores rax into addr which is backwards of what was intended.
5482 if (addr.uses(rsp)) {
5483 lea(rax, addr);
5484 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5485 } else {
5486 pushptr(addr);
5487 }
5488
5489 // Pass register number to verify_oop_subroutine
5490 const char* b = nullptr;
5491 {
5492 ResourceMark rm;
5493 stringStream ss;
5494 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5495 b = code_string(ss.as_string());
5496 }
5497 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5498 pushptr(buffer.addr(), rscratch1);
5499
5500 // call indirectly to solve generation ordering problem
5501 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5502 call(rax);
5503 // Caller pops the arguments (addr, message) and restores rax, r10.
5504 }
5505
5506 void MacroAssembler::verify_tlab() {
5507 #ifdef ASSERT
5508 if (UseTLAB && VerifyOops) {
5509 Label next, ok;
5510 Register t1 = rsi;
5511 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5512
5513 push(t1);
5514 NOT_LP64(push(thread_reg));
5515 NOT_LP64(get_thread(thread_reg));
5516
5517 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5518 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5519 jcc(Assembler::aboveEqual, next);
5520 STOP("assert(top >= start)");
5521 should_not_reach_here();
5522
5523 bind(next);
5524 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5525 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5526 jcc(Assembler::aboveEqual, ok);
5527 STOP("assert(top <= end)");
5528 should_not_reach_here();
5529
5530 bind(ok);
5531 NOT_LP64(pop(thread_reg));
5532 pop(t1);
5533 }
5534 #endif
5535 }
5536
5537 class ControlWord {
5538 public:
5539 int32_t _value;
5540
5541 int rounding_control() const { return (_value >> 10) & 3 ; }
5542 int precision_control() const { return (_value >> 8) & 3 ; }
5543 bool precision() const { return ((_value >> 5) & 1) != 0; }
5544 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5545 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5546 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5547 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5548 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5549
5550 void print() const {
5551 // rounding control
5552 const char* rc;
5553 switch (rounding_control()) {
5554 case 0: rc = "round near"; break;
5555 case 1: rc = "round down"; break;
5556 case 2: rc = "round up "; break;
5557 case 3: rc = "chop "; break;
5558 default:
5559 rc = nullptr; // silence compiler warnings
5560 fatal("Unknown rounding control: %d", rounding_control());
5561 };
5562 // precision control
5563 const char* pc;
5564 switch (precision_control()) {
5565 case 0: pc = "24 bits "; break;
5566 case 1: pc = "reserved"; break;
5567 case 2: pc = "53 bits "; break;
5568 case 3: pc = "64 bits "; break;
5569 default:
5570 pc = nullptr; // silence compiler warnings
5571 fatal("Unknown precision control: %d", precision_control());
5572 };
5573 // flags
5574 char f[9];
5575 f[0] = ' ';
5576 f[1] = ' ';
5577 f[2] = (precision ()) ? 'P' : 'p';
5578 f[3] = (underflow ()) ? 'U' : 'u';
5579 f[4] = (overflow ()) ? 'O' : 'o';
5580 f[5] = (zero_divide ()) ? 'Z' : 'z';
5581 f[6] = (denormalized()) ? 'D' : 'd';
5582 f[7] = (invalid ()) ? 'I' : 'i';
5583 f[8] = '\x0';
5584 // output
5585 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5586 }
5587
5588 };
5589
5590 class StatusWord {
5591 public:
5592 int32_t _value;
5593
5594 bool busy() const { return ((_value >> 15) & 1) != 0; }
5595 bool C3() const { return ((_value >> 14) & 1) != 0; }
5596 bool C2() const { return ((_value >> 10) & 1) != 0; }
5597 bool C1() const { return ((_value >> 9) & 1) != 0; }
5598 bool C0() const { return ((_value >> 8) & 1) != 0; }
5599 int top() const { return (_value >> 11) & 7 ; }
5600 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5601 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5602 bool precision() const { return ((_value >> 5) & 1) != 0; }
5603 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5604 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5605 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5606 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5607 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5608
5609 void print() const {
5610 // condition codes
5611 char c[5];
5612 c[0] = (C3()) ? '3' : '-';
5613 c[1] = (C2()) ? '2' : '-';
5614 c[2] = (C1()) ? '1' : '-';
5615 c[3] = (C0()) ? '0' : '-';
5616 c[4] = '\x0';
5617 // flags
5618 char f[9];
5619 f[0] = (error_status()) ? 'E' : '-';
5620 f[1] = (stack_fault ()) ? 'S' : '-';
5621 f[2] = (precision ()) ? 'P' : '-';
5622 f[3] = (underflow ()) ? 'U' : '-';
5623 f[4] = (overflow ()) ? 'O' : '-';
5624 f[5] = (zero_divide ()) ? 'Z' : '-';
5625 f[6] = (denormalized()) ? 'D' : '-';
5626 f[7] = (invalid ()) ? 'I' : '-';
5627 f[8] = '\x0';
5628 // output
5629 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5630 }
5631
5632 };
5633
5634 class TagWord {
5635 public:
5636 int32_t _value;
5637
5638 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5639
5640 void print() const {
5641 printf("%04x", _value & 0xFFFF);
5642 }
5643
5644 };
5645
5646 class FPU_Register {
5647 public:
5648 int32_t _m0;
5649 int32_t _m1;
5650 int16_t _ex;
5651
5652 bool is_indefinite() const {
5653 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5654 }
5655
5656 void print() const {
5657 char sign = (_ex < 0) ? '-' : '+';
5658 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5659 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5660 };
5661
5662 };
5663
5664 class FPU_State {
5665 public:
5666 enum {
5667 register_size = 10,
5668 number_of_registers = 8,
5669 register_mask = 7
5670 };
5671
5672 ControlWord _control_word;
5673 StatusWord _status_word;
5674 TagWord _tag_word;
5675 int32_t _error_offset;
5676 int32_t _error_selector;
5677 int32_t _data_offset;
5678 int32_t _data_selector;
5679 int8_t _register[register_size * number_of_registers];
5680
5681 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5682 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5683
5684 const char* tag_as_string(int tag) const {
5685 switch (tag) {
5686 case 0: return "valid";
5687 case 1: return "zero";
5688 case 2: return "special";
5689 case 3: return "empty";
5690 }
5691 ShouldNotReachHere();
5692 return nullptr;
5693 }
5694
5695 void print() const {
5696 // print computation registers
5697 { int t = _status_word.top();
5698 for (int i = 0; i < number_of_registers; i++) {
5699 int j = (i - t) & register_mask;
5700 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5701 st(j)->print();
5702 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5703 }
5704 }
5705 printf("\n");
5706 // print control registers
5707 printf("ctrl = "); _control_word.print(); printf("\n");
5708 printf("stat = "); _status_word .print(); printf("\n");
5709 printf("tags = "); _tag_word .print(); printf("\n");
5710 }
5711
5712 };
5713
5714 class Flag_Register {
5715 public:
5716 int32_t _value;
5717
5718 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5719 bool direction() const { return ((_value >> 10) & 1) != 0; }
5720 bool sign() const { return ((_value >> 7) & 1) != 0; }
5721 bool zero() const { return ((_value >> 6) & 1) != 0; }
5722 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5723 bool parity() const { return ((_value >> 2) & 1) != 0; }
5724 bool carry() const { return ((_value >> 0) & 1) != 0; }
5725
5726 void print() const {
5727 // flags
5728 char f[8];
5729 f[0] = (overflow ()) ? 'O' : '-';
5730 f[1] = (direction ()) ? 'D' : '-';
5731 f[2] = (sign ()) ? 'S' : '-';
5732 f[3] = (zero ()) ? 'Z' : '-';
5733 f[4] = (auxiliary_carry()) ? 'A' : '-';
5734 f[5] = (parity ()) ? 'P' : '-';
5735 f[6] = (carry ()) ? 'C' : '-';
5736 f[7] = '\x0';
5737 // output
5738 printf("%08x flags = %s", _value, f);
5739 }
5740
5741 };
5742
5743 class IU_Register {
5744 public:
5745 int32_t _value;
5746
5747 void print() const {
5748 printf("%08x %11d", _value, _value);
5749 }
5750
5751 };
5752
5753 class IU_State {
5754 public:
5755 Flag_Register _eflags;
5756 IU_Register _rdi;
5757 IU_Register _rsi;
5758 IU_Register _rbp;
5759 IU_Register _rsp;
5760 IU_Register _rbx;
5761 IU_Register _rdx;
5762 IU_Register _rcx;
5763 IU_Register _rax;
5764
5765 void print() const {
5766 // computation registers
5767 printf("rax, = "); _rax.print(); printf("\n");
5768 printf("rbx, = "); _rbx.print(); printf("\n");
5769 printf("rcx = "); _rcx.print(); printf("\n");
5770 printf("rdx = "); _rdx.print(); printf("\n");
5771 printf("rdi = "); _rdi.print(); printf("\n");
5772 printf("rsi = "); _rsi.print(); printf("\n");
5773 printf("rbp, = "); _rbp.print(); printf("\n");
5774 printf("rsp = "); _rsp.print(); printf("\n");
5775 printf("\n");
5776 // control registers
5777 printf("flgs = "); _eflags.print(); printf("\n");
5778 }
5779 };
5780
5781
5782 class CPU_State {
5783 public:
5784 FPU_State _fpu_state;
5785 IU_State _iu_state;
5786
5787 void print() const {
5788 printf("--------------------------------------------------\n");
5789 _iu_state .print();
5790 printf("\n");
5791 _fpu_state.print();
5792 printf("--------------------------------------------------\n");
5793 }
5794
5795 };
5796
5797
5798 static void _print_CPU_state(CPU_State* state) {
5799 state->print();
5800 };
5801
5802
5803 void MacroAssembler::print_CPU_state() {
5804 push_CPU_state();
5805 push(rsp); // pass CPU state
5806 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5807 addptr(rsp, wordSize); // discard argument
5808 pop_CPU_state();
5809 }
5810
5811
5812 #ifndef _LP64
5813 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5814 static int counter = 0;
5815 FPU_State* fs = &state->_fpu_state;
5816 counter++;
5817 // For leaf calls, only verify that the top few elements remain empty.
5818 // We only need 1 empty at the top for C2 code.
5819 if( stack_depth < 0 ) {
5820 if( fs->tag_for_st(7) != 3 ) {
5821 printf("FPR7 not empty\n");
5822 state->print();
5823 assert(false, "error");
5824 return false;
5825 }
5826 return true; // All other stack states do not matter
5827 }
5828
5829 assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
5830 "bad FPU control word");
5831
5832 // compute stack depth
5833 int i = 0;
5834 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5835 int d = i;
5836 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5837 // verify findings
5838 if (i != FPU_State::number_of_registers) {
5839 // stack not contiguous
5840 printf("%s: stack not contiguous at ST%d\n", s, i);
5841 state->print();
5842 assert(false, "error");
5843 return false;
5844 }
5845 // check if computed stack depth corresponds to expected stack depth
5846 if (stack_depth < 0) {
5847 // expected stack depth is -stack_depth or less
5848 if (d > -stack_depth) {
5849 // too many elements on the stack
5850 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5851 state->print();
5852 assert(false, "error");
5853 return false;
5854 }
5855 } else {
5856 // expected stack depth is stack_depth
5857 if (d != stack_depth) {
5858 // wrong stack depth
5859 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5860 state->print();
5861 assert(false, "error");
5862 return false;
5863 }
5864 }
5865 // everything is cool
5866 return true;
5867 }
5868
5869 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5870 if (!VerifyFPU) return;
5871 push_CPU_state();
5872 push(rsp); // pass CPU state
5873 ExternalAddress msg((address) s);
5874 // pass message string s
5875 pushptr(msg.addr(), noreg);
5876 push(stack_depth); // pass stack depth
5877 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5878 addptr(rsp, 3 * wordSize); // discard arguments
5879 // check for error
5880 { Label L;
5881 testl(rax, rax);
5882 jcc(Assembler::notZero, L);
5883 int3(); // break if error condition
5884 bind(L);
5885 }
5886 pop_CPU_state();
5887 }
5888 #endif // _LP64
5889
5890 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5891 // Either restore the MXCSR register after returning from the JNI Call
5892 // or verify that it wasn't changed (with -Xcheck:jni flag).
5893 if (VM_Version::supports_sse()) {
5894 if (RestoreMXCSROnJNICalls) {
5895 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5896 } else if (CheckJNICalls) {
5897 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5898 }
5899 }
5900 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5901 vzeroupper();
5902
5903 #ifndef _LP64
5904 // Either restore the x87 floating pointer control word after returning
5905 // from the JNI call or verify that it wasn't changed.
5906 if (CheckJNICalls) {
5907 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5908 }
5909 #endif // _LP64
5910 }
5911
5912 // ((OopHandle)result).resolve();
5913 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5914 assert_different_registers(result, tmp);
5915
5916 // Only 64 bit platforms support GCs that require a tmp register
5917 // Only IN_HEAP loads require a thread_tmp register
5918 // OopHandle::resolve is an indirection like jobject.
5919 access_load_at(T_OBJECT, IN_NATIVE,
5920 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5921 }
5922
5923 // ((WeakHandle)result).resolve();
5924 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5925 assert_different_registers(rresult, rtmp);
5926 Label resolved;
5927
5928 // A null weak handle resolves to null.
5929 cmpptr(rresult, 0);
5930 jcc(Assembler::equal, resolved);
5931
5932 // Only 64 bit platforms support GCs that require a tmp register
5933 // Only IN_HEAP loads require a thread_tmp register
5934 // WeakHandle::resolve is an indirection like jweak.
5935 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5936 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
5937 bind(resolved);
5938 }
5939
5940 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5941 // get mirror
5942 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5943 load_method_holder(mirror, method);
5944 movptr(mirror, Address(mirror, mirror_offset));
5945 resolve_oop_handle(mirror, tmp);
5946 }
5947
5948 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5949 load_method_holder(rresult, rmethod);
5950 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5951 }
5952
5953 void MacroAssembler::load_method_holder(Register holder, Register method) {
5954 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5955 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5956 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5957 }
5958
5959 #ifdef _LP64
5960 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5961 assert(UseCompactObjectHeaders, "expect compact object headers");
5962 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5963 shrq(dst, markWord::klass_shift);
5964 }
5965 #endif
5966
5967 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5968 assert_different_registers(src, tmp);
5969 assert_different_registers(dst, tmp);
5970 #ifdef _LP64
5971 if (UseCompactObjectHeaders) {
5972 load_narrow_klass_compact(dst, src);
5973 decode_klass_not_null(dst, tmp);
5974 } else if (UseCompressedClassPointers) {
5975 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5976 decode_klass_not_null(dst, tmp);
5977 } else
5978 #endif
5979 {
5980 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5981 }
5982 }
5983
5984 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5985 assert(!UseCompactObjectHeaders, "not with compact headers");
5986 assert_different_registers(src, tmp);
5987 assert_different_registers(dst, tmp);
5988 #ifdef _LP64
5989 if (UseCompressedClassPointers) {
5990 encode_klass_not_null(src, tmp);
5991 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5992 } else
5993 #endif
5994 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5995 }
5996
5997 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
5998 #ifdef _LP64
5999 if (UseCompactObjectHeaders) {
6000 assert(tmp != noreg, "need tmp");
6001 assert_different_registers(klass, obj, tmp);
6002 load_narrow_klass_compact(tmp, obj);
6003 cmpl(klass, tmp);
6004 } else if (UseCompressedClassPointers) {
6005 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
6006 } else
6007 #endif
6008 {
6009 cmpptr(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
6010 }
6011 }
6012
6013 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
6014 #ifdef _LP64
6015 if (UseCompactObjectHeaders) {
6016 assert(tmp2 != noreg, "need tmp2");
6017 assert_different_registers(obj1, obj2, tmp1, tmp2);
6018 load_narrow_klass_compact(tmp1, obj1);
6019 load_narrow_klass_compact(tmp2, obj2);
6020 cmpl(tmp1, tmp2);
6021 } else if (UseCompressedClassPointers) {
6022 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
6023 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
6024 } else
6025 #endif
6026 {
6027 movptr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
6028 cmpptr(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
6029 }
6030 }
6031
6032 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
6033 Register tmp1, Register thread_tmp) {
6034 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6035 decorators = AccessInternal::decorator_fixup(decorators, type);
6036 bool as_raw = (decorators & AS_RAW) != 0;
6037 if (as_raw) {
6038 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6039 } else {
6040 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6041 }
6042 }
6043
6044 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
6045 Register tmp1, Register tmp2, Register tmp3) {
6046 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6047 decorators = AccessInternal::decorator_fixup(decorators, type);
6048 bool as_raw = (decorators & AS_RAW) != 0;
6049 if (as_raw) {
6050 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6051 } else {
6052 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6053 }
6054 }
6055
6056 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
6057 Register thread_tmp, DecoratorSet decorators) {
6058 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
6059 }
6060
6061 // Doesn't do verification, generates fixed size code
6062 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
6063 Register thread_tmp, DecoratorSet decorators) {
6064 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
6065 }
6066
6067 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
6068 Register tmp2, Register tmp3, DecoratorSet decorators) {
6069 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
6070 }
6071
6072 // Used for storing nulls.
6073 void MacroAssembler::store_heap_oop_null(Address dst) {
6074 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
6075 }
6076
6077 #ifdef _LP64
6078 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6079 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
6080 if (UseCompressedClassPointers) {
6081 // Store to klass gap in destination
6082 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6083 }
6084 }
6085
6086 #ifdef ASSERT
6087 void MacroAssembler::verify_heapbase(const char* msg) {
6088 assert (UseCompressedOops, "should be compressed");
6089 assert (Universe::heap() != nullptr, "java heap should be initialized");
6090 if (CheckCompressedOops) {
6091 Label ok;
6092 ExternalAddress src2(CompressedOops::base_addr());
6093 const bool is_src2_reachable = reachable(src2);
6094 if (!is_src2_reachable) {
6095 push(rscratch1); // cmpptr trashes rscratch1
6096 }
6097 cmpptr(r12_heapbase, src2, rscratch1);
6098 jcc(Assembler::equal, ok);
6099 STOP(msg);
6100 bind(ok);
6101 if (!is_src2_reachable) {
6102 pop(rscratch1);
6103 }
6104 }
6105 }
6106 #endif
6107
6108 // Algorithm must match oop.inline.hpp encode_heap_oop.
6109 void MacroAssembler::encode_heap_oop(Register r) {
6110 #ifdef ASSERT
6111 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6112 #endif
6113 verify_oop_msg(r, "broken oop in encode_heap_oop");
6114 if (CompressedOops::base() == nullptr) {
6115 if (CompressedOops::shift() != 0) {
6116 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6117 shrq(r, LogMinObjAlignmentInBytes);
6118 }
6119 return;
6120 }
6121 testq(r, r);
6122 cmovq(Assembler::equal, r, r12_heapbase);
6123 subq(r, r12_heapbase);
6124 shrq(r, LogMinObjAlignmentInBytes);
6125 }
6126
6127 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6128 #ifdef ASSERT
6129 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6130 if (CheckCompressedOops) {
6131 Label ok;
6132 testq(r, r);
6133 jcc(Assembler::notEqual, ok);
6134 STOP("null oop passed to encode_heap_oop_not_null");
6135 bind(ok);
6136 }
6137 #endif
6138 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
6139 if (CompressedOops::base() != nullptr) {
6140 subq(r, r12_heapbase);
6141 }
6142 if (CompressedOops::shift() != 0) {
6143 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6144 shrq(r, LogMinObjAlignmentInBytes);
6145 }
6146 }
6147
6148 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6149 #ifdef ASSERT
6150 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6151 if (CheckCompressedOops) {
6152 Label ok;
6153 testq(src, src);
6154 jcc(Assembler::notEqual, ok);
6155 STOP("null oop passed to encode_heap_oop_not_null2");
6156 bind(ok);
6157 }
6158 #endif
6159 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
6160 if (dst != src) {
6161 movq(dst, src);
6162 }
6163 if (CompressedOops::base() != nullptr) {
6164 subq(dst, r12_heapbase);
6165 }
6166 if (CompressedOops::shift() != 0) {
6167 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6168 shrq(dst, LogMinObjAlignmentInBytes);
6169 }
6170 }
6171
6172 void MacroAssembler::decode_heap_oop(Register r) {
6173 #ifdef ASSERT
6174 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6175 #endif
6176 if (CompressedOops::base() == nullptr) {
6177 if (CompressedOops::shift() != 0) {
6178 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6179 shlq(r, LogMinObjAlignmentInBytes);
6180 }
6181 } else {
6182 Label done;
6183 shlq(r, LogMinObjAlignmentInBytes);
6184 jccb(Assembler::equal, done);
6185 addq(r, r12_heapbase);
6186 bind(done);
6187 }
6188 verify_oop_msg(r, "broken oop in decode_heap_oop");
6189 }
6190
6191 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6192 // Note: it will change flags
6193 assert (UseCompressedOops, "should only be used for compressed headers");
6194 assert (Universe::heap() != nullptr, "java heap should be initialized");
6195 // Cannot assert, unverified entry point counts instructions (see .ad file)
6196 // vtableStubs also counts instructions in pd_code_size_limit.
6197 // Also do not verify_oop as this is called by verify_oop.
6198 if (CompressedOops::shift() != 0) {
6199 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6200 shlq(r, LogMinObjAlignmentInBytes);
6201 if (CompressedOops::base() != nullptr) {
6202 addq(r, r12_heapbase);
6203 }
6204 } else {
6205 assert (CompressedOops::base() == nullptr, "sanity");
6206 }
6207 }
6208
6209 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6210 // Note: it will change flags
6211 assert (UseCompressedOops, "should only be used for compressed headers");
6212 assert (Universe::heap() != nullptr, "java heap should be initialized");
6213 // Cannot assert, unverified entry point counts instructions (see .ad file)
6214 // vtableStubs also counts instructions in pd_code_size_limit.
6215 // Also do not verify_oop as this is called by verify_oop.
6216 if (CompressedOops::shift() != 0) {
6217 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6218 if (LogMinObjAlignmentInBytes == Address::times_8) {
6219 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6220 } else {
6221 if (dst != src) {
6222 movq(dst, src);
6223 }
6224 shlq(dst, LogMinObjAlignmentInBytes);
6225 if (CompressedOops::base() != nullptr) {
6226 addq(dst, r12_heapbase);
6227 }
6228 }
6229 } else {
6230 assert (CompressedOops::base() == nullptr, "sanity");
6231 if (dst != src) {
6232 movq(dst, src);
6233 }
6234 }
6235 }
6236
6237 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
6238 assert_different_registers(r, tmp);
6239 if (CompressedKlassPointers::base() != nullptr) {
6240 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6241 subq(r, tmp);
6242 }
6243 if (CompressedKlassPointers::shift() != 0) {
6244 shrq(r, CompressedKlassPointers::shift());
6245 }
6246 }
6247
6248 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
6249 assert_different_registers(src, dst);
6250 if (CompressedKlassPointers::base() != nullptr) {
6251 mov64(dst, -(int64_t)CompressedKlassPointers::base());
6252 addq(dst, src);
6253 } else {
6254 movptr(dst, src);
6255 }
6256 if (CompressedKlassPointers::shift() != 0) {
6257 shrq(dst, CompressedKlassPointers::shift());
6258 }
6259 }
6260
6261 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
6262 assert_different_registers(r, tmp);
6263 // Note: it will change flags
6264 assert(UseCompressedClassPointers, "should only be used for compressed headers");
6265 // Cannot assert, unverified entry point counts instructions (see .ad file)
6266 // vtableStubs also counts instructions in pd_code_size_limit.
6267 // Also do not verify_oop as this is called by verify_oop.
6268 if (CompressedKlassPointers::shift() != 0) {
6269 shlq(r, CompressedKlassPointers::shift());
6270 }
6271 if (CompressedKlassPointers::base() != nullptr) {
6272 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6273 addq(r, tmp);
6274 }
6275 }
6276
6277 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
6278 assert_different_registers(src, dst);
6279 // Note: it will change flags
6280 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6281 // Cannot assert, unverified entry point counts instructions (see .ad file)
6282 // vtableStubs also counts instructions in pd_code_size_limit.
6283 // Also do not verify_oop as this is called by verify_oop.
6284
6285 if (CompressedKlassPointers::base() == nullptr &&
6286 CompressedKlassPointers::shift() == 0) {
6287 // The best case scenario is that there is no base or shift. Then it is already
6288 // a pointer that needs nothing but a register rename.
6289 movl(dst, src);
6290 } else {
6291 if (CompressedKlassPointers::shift() <= Address::times_8) {
6292 if (CompressedKlassPointers::base() != nullptr) {
6293 mov64(dst, (int64_t)CompressedKlassPointers::base());
6294 } else {
6295 xorq(dst, dst);
6296 }
6297 if (CompressedKlassPointers::shift() != 0) {
6298 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
6299 leaq(dst, Address(dst, src, Address::times_8, 0));
6300 } else {
6301 addq(dst, src);
6302 }
6303 } else {
6304 if (CompressedKlassPointers::base() != nullptr) {
6305 const uint64_t base_right_shifted =
6306 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
6307 mov64(dst, base_right_shifted);
6308 } else {
6309 xorq(dst, dst);
6310 }
6311 addq(dst, src);
6312 shlq(dst, CompressedKlassPointers::shift());
6313 }
6314 }
6315 }
6316
6317 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6318 assert (UseCompressedOops, "should only be used for compressed headers");
6319 assert (Universe::heap() != nullptr, "java heap should be initialized");
6320 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6321 int oop_index = oop_recorder()->find_index(obj);
6322 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6323 mov_narrow_oop(dst, oop_index, rspec);
6324 }
6325
6326 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6327 assert (UseCompressedOops, "should only be used for compressed headers");
6328 assert (Universe::heap() != nullptr, "java heap should be initialized");
6329 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6330 int oop_index = oop_recorder()->find_index(obj);
6331 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6332 mov_narrow_oop(dst, oop_index, rspec);
6333 }
6334
6335 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6336 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6337 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6338 int klass_index = oop_recorder()->find_index(k);
6339 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6340 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6341 }
6342
6343 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6344 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6345 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6346 int klass_index = oop_recorder()->find_index(k);
6347 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6348 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6349 }
6350
6351 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6352 assert (UseCompressedOops, "should only be used for compressed headers");
6353 assert (Universe::heap() != nullptr, "java heap should be initialized");
6354 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6355 int oop_index = oop_recorder()->find_index(obj);
6356 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6357 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6358 }
6359
6360 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6361 assert (UseCompressedOops, "should only be used for compressed headers");
6362 assert (Universe::heap() != nullptr, "java heap should be initialized");
6363 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6364 int oop_index = oop_recorder()->find_index(obj);
6365 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6366 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6367 }
6368
6369 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6370 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6371 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6372 int klass_index = oop_recorder()->find_index(k);
6373 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6374 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6375 }
6376
6377 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6378 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6379 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6380 int klass_index = oop_recorder()->find_index(k);
6381 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6382 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6383 }
6384
6385 void MacroAssembler::reinit_heapbase() {
6386 if (UseCompressedOops) {
6387 if (Universe::heap() != nullptr) {
6388 if (CompressedOops::base() == nullptr) {
6389 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6390 } else {
6391 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6392 }
6393 } else {
6394 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6395 }
6396 }
6397 }
6398
6399 #endif // _LP64
6400
6401 #if COMPILER2_OR_JVMCI
6402
6403 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6404 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6405 // cnt - number of qwords (8-byte words).
6406 // base - start address, qword aligned.
6407 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6408 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
6409 if (use64byteVector) {
6410 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
6411 } else if (MaxVectorSize >= 32) {
6412 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
6413 } else {
6414 pxor(xtmp, xtmp);
6415 }
6416 jmp(L_zero_64_bytes);
6417
6418 BIND(L_loop);
6419 if (MaxVectorSize >= 32) {
6420 fill64(base, 0, xtmp, use64byteVector);
6421 } else {
6422 movdqu(Address(base, 0), xtmp);
6423 movdqu(Address(base, 16), xtmp);
6424 movdqu(Address(base, 32), xtmp);
6425 movdqu(Address(base, 48), xtmp);
6426 }
6427 addptr(base, 64);
6428
6429 BIND(L_zero_64_bytes);
6430 subptr(cnt, 8);
6431 jccb(Assembler::greaterEqual, L_loop);
6432
6433 // Copy trailing 64 bytes
6434 if (use64byteVector) {
6435 addptr(cnt, 8);
6436 jccb(Assembler::equal, L_end);
6437 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
6438 jmp(L_end);
6439 } else {
6440 addptr(cnt, 4);
6441 jccb(Assembler::less, L_tail);
6442 if (MaxVectorSize >= 32) {
6443 vmovdqu(Address(base, 0), xtmp);
6444 } else {
6445 movdqu(Address(base, 0), xtmp);
6446 movdqu(Address(base, 16), xtmp);
6447 }
6448 }
6449 addptr(base, 32);
6450 subptr(cnt, 4);
6451
6452 BIND(L_tail);
6453 addptr(cnt, 4);
6454 jccb(Assembler::lessEqual, L_end);
6455 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6456 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
6457 } else {
6458 decrement(cnt);
6459
6460 BIND(L_sloop);
6461 movq(Address(base, 0), xtmp);
6462 addptr(base, 8);
6463 decrement(cnt);
6464 jccb(Assembler::greaterEqual, L_sloop);
6465 }
6466 BIND(L_end);
6467 }
6468
6469 // Clearing constant sized memory using YMM/ZMM registers.
6470 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6471 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6472 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
6473
6474 int vector64_count = (cnt & (~0x7)) >> 3;
6475 cnt = cnt & 0x7;
6476 const int fill64_per_loop = 4;
6477 const int max_unrolled_fill64 = 8;
6478
6479 // 64 byte initialization loop.
6480 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6481 int start64 = 0;
6482 if (vector64_count > max_unrolled_fill64) {
6483 Label LOOP;
6484 Register index = rtmp;
6485
6486 start64 = vector64_count - (vector64_count % fill64_per_loop);
6487
6488 movl(index, 0);
6489 BIND(LOOP);
6490 for (int i = 0; i < fill64_per_loop; i++) {
6491 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6492 }
6493 addl(index, fill64_per_loop * 64);
6494 cmpl(index, start64 * 64);
6495 jccb(Assembler::less, LOOP);
6496 }
6497 for (int i = start64; i < vector64_count; i++) {
6498 fill64(base, i * 64, xtmp, use64byteVector);
6499 }
6500
6501 // Clear remaining 64 byte tail.
6502 int disp = vector64_count * 64;
6503 if (cnt) {
6504 switch (cnt) {
6505 case 1:
6506 movq(Address(base, disp), xtmp);
6507 break;
6508 case 2:
6509 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6510 break;
6511 case 3:
6512 movl(rtmp, 0x7);
6513 kmovwl(mask, rtmp);
6514 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6515 break;
6516 case 4:
6517 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6518 break;
6519 case 5:
6520 if (use64byteVector) {
6521 movl(rtmp, 0x1F);
6522 kmovwl(mask, rtmp);
6523 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6524 } else {
6525 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6526 movq(Address(base, disp + 32), xtmp);
6527 }
6528 break;
6529 case 6:
6530 if (use64byteVector) {
6531 movl(rtmp, 0x3F);
6532 kmovwl(mask, rtmp);
6533 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6534 } else {
6535 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6536 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6537 }
6538 break;
6539 case 7:
6540 if (use64byteVector) {
6541 movl(rtmp, 0x7F);
6542 kmovwl(mask, rtmp);
6543 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6544 } else {
6545 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6546 movl(rtmp, 0x7);
6547 kmovwl(mask, rtmp);
6548 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6549 }
6550 break;
6551 default:
6552 fatal("Unexpected length : %d\n",cnt);
6553 break;
6554 }
6555 }
6556 }
6557
6558 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
6559 bool is_large, KRegister mask) {
6560 // cnt - number of qwords (8-byte words).
6561 // base - start address, qword aligned.
6562 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6563 assert(base==rdi, "base register must be edi for rep stos");
6564 assert(tmp==rax, "tmp register must be eax for rep stos");
6565 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6566 assert(InitArrayShortSize % BytesPerLong == 0,
6567 "InitArrayShortSize should be the multiple of BytesPerLong");
6568
6569 Label DONE;
6570 if (!is_large || !UseXMMForObjInit) {
6571 xorptr(tmp, tmp);
6572 }
6573
6574 if (!is_large) {
6575 Label LOOP, LONG;
6576 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6577 jccb(Assembler::greater, LONG);
6578
6579 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6580
6581 decrement(cnt);
6582 jccb(Assembler::negative, DONE); // Zero length
6583
6584 // Use individual pointer-sized stores for small counts:
6585 BIND(LOOP);
6586 movptr(Address(base, cnt, Address::times_ptr), tmp);
6587 decrement(cnt);
6588 jccb(Assembler::greaterEqual, LOOP);
6589 jmpb(DONE);
6590
6591 BIND(LONG);
6592 }
6593
6594 // Use longer rep-prefixed ops for non-small counts:
6595 if (UseFastStosb) {
6596 shlptr(cnt, 3); // convert to number of bytes
6597 rep_stosb();
6598 } else if (UseXMMForObjInit) {
6599 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
6600 } else {
6601 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6602 rep_stos();
6603 }
6604
6605 BIND(DONE);
6606 }
6607
6608 #endif //COMPILER2_OR_JVMCI
6609
6610
6611 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6612 Register to, Register value, Register count,
6613 Register rtmp, XMMRegister xtmp) {
6614 ShortBranchVerifier sbv(this);
6615 assert_different_registers(to, value, count, rtmp);
6616 Label L_exit;
6617 Label L_fill_2_bytes, L_fill_4_bytes;
6618
6619 #if defined(COMPILER2) && defined(_LP64)
6620 if(MaxVectorSize >=32 &&
6621 VM_Version::supports_avx512vlbw() &&
6622 VM_Version::supports_bmi2()) {
6623 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6624 return;
6625 }
6626 #endif
6627
6628 int shift = -1;
6629 switch (t) {
6630 case T_BYTE:
6631 shift = 2;
6632 break;
6633 case T_SHORT:
6634 shift = 1;
6635 break;
6636 case T_INT:
6637 shift = 0;
6638 break;
6639 default: ShouldNotReachHere();
6640 }
6641
6642 if (t == T_BYTE) {
6643 andl(value, 0xff);
6644 movl(rtmp, value);
6645 shll(rtmp, 8);
6646 orl(value, rtmp);
6647 }
6648 if (t == T_SHORT) {
6649 andl(value, 0xffff);
6650 }
6651 if (t == T_BYTE || t == T_SHORT) {
6652 movl(rtmp, value);
6653 shll(rtmp, 16);
6654 orl(value, rtmp);
6655 }
6656
6657 cmpptr(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
6658 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6659 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6660 Label L_skip_align2;
6661 // align source address at 4 bytes address boundary
6662 if (t == T_BYTE) {
6663 Label L_skip_align1;
6664 // One byte misalignment happens only for byte arrays
6665 testptr(to, 1);
6666 jccb(Assembler::zero, L_skip_align1);
6667 movb(Address(to, 0), value);
6668 increment(to);
6669 decrement(count);
6670 BIND(L_skip_align1);
6671 }
6672 // Two bytes misalignment happens only for byte and short (char) arrays
6673 testptr(to, 2);
6674 jccb(Assembler::zero, L_skip_align2);
6675 movw(Address(to, 0), value);
6676 addptr(to, 2);
6677 subptr(count, 1<<(shift-1));
6678 BIND(L_skip_align2);
6679 }
6680 if (UseSSE < 2) {
6681 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6682 // Fill 32-byte chunks
6683 subptr(count, 8 << shift);
6684 jcc(Assembler::less, L_check_fill_8_bytes);
6685 align(16);
6686
6687 BIND(L_fill_32_bytes_loop);
6688
6689 for (int i = 0; i < 32; i += 4) {
6690 movl(Address(to, i), value);
6691 }
6692
6693 addptr(to, 32);
6694 subptr(count, 8 << shift);
6695 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6696 BIND(L_check_fill_8_bytes);
6697 addptr(count, 8 << shift);
6698 jccb(Assembler::zero, L_exit);
6699 jmpb(L_fill_8_bytes);
6700
6701 //
6702 // length is too short, just fill qwords
6703 //
6704 BIND(L_fill_8_bytes_loop);
6705 movl(Address(to, 0), value);
6706 movl(Address(to, 4), value);
6707 addptr(to, 8);
6708 BIND(L_fill_8_bytes);
6709 subptr(count, 1 << (shift + 1));
6710 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6711 // fall through to fill 4 bytes
6712 } else {
6713 Label L_fill_32_bytes;
6714 if (!UseUnalignedLoadStores) {
6715 // align to 8 bytes, we know we are 4 byte aligned to start
6716 testptr(to, 4);
6717 jccb(Assembler::zero, L_fill_32_bytes);
6718 movl(Address(to, 0), value);
6719 addptr(to, 4);
6720 subptr(count, 1<<shift);
6721 }
6722 BIND(L_fill_32_bytes);
6723 {
6724 assert( UseSSE >= 2, "supported cpu only" );
6725 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6726 movdl(xtmp, value);
6727 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6728 Label L_check_fill_32_bytes;
6729 if (UseAVX > 2) {
6730 // Fill 64-byte chunks
6731 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6732
6733 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
6734 cmpptr(count, VM_Version::avx3_threshold());
6735 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6736
6737 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6738
6739 subptr(count, 16 << shift);
6740 jccb(Assembler::less, L_check_fill_32_bytes);
6741 align(16);
6742
6743 BIND(L_fill_64_bytes_loop_avx3);
6744 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6745 addptr(to, 64);
6746 subptr(count, 16 << shift);
6747 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6748 jmpb(L_check_fill_32_bytes);
6749
6750 BIND(L_check_fill_64_bytes_avx2);
6751 }
6752 // Fill 64-byte chunks
6753 Label L_fill_64_bytes_loop;
6754 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6755
6756 subptr(count, 16 << shift);
6757 jcc(Assembler::less, L_check_fill_32_bytes);
6758 align(16);
6759
6760 BIND(L_fill_64_bytes_loop);
6761 vmovdqu(Address(to, 0), xtmp);
6762 vmovdqu(Address(to, 32), xtmp);
6763 addptr(to, 64);
6764 subptr(count, 16 << shift);
6765 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6766
6767 BIND(L_check_fill_32_bytes);
6768 addptr(count, 8 << shift);
6769 jccb(Assembler::less, L_check_fill_8_bytes);
6770 vmovdqu(Address(to, 0), xtmp);
6771 addptr(to, 32);
6772 subptr(count, 8 << shift);
6773
6774 BIND(L_check_fill_8_bytes);
6775 // clean upper bits of YMM registers
6776 movdl(xtmp, value);
6777 pshufd(xtmp, xtmp, 0);
6778 } else {
6779 // Fill 32-byte chunks
6780 pshufd(xtmp, xtmp, 0);
6781
6782 subptr(count, 8 << shift);
6783 jcc(Assembler::less, L_check_fill_8_bytes);
6784 align(16);
6785
6786 BIND(L_fill_32_bytes_loop);
6787
6788 if (UseUnalignedLoadStores) {
6789 movdqu(Address(to, 0), xtmp);
6790 movdqu(Address(to, 16), xtmp);
6791 } else {
6792 movq(Address(to, 0), xtmp);
6793 movq(Address(to, 8), xtmp);
6794 movq(Address(to, 16), xtmp);
6795 movq(Address(to, 24), xtmp);
6796 }
6797
6798 addptr(to, 32);
6799 subptr(count, 8 << shift);
6800 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6801
6802 BIND(L_check_fill_8_bytes);
6803 }
6804 addptr(count, 8 << shift);
6805 jccb(Assembler::zero, L_exit);
6806 jmpb(L_fill_8_bytes);
6807
6808 //
6809 // length is too short, just fill qwords
6810 //
6811 BIND(L_fill_8_bytes_loop);
6812 movq(Address(to, 0), xtmp);
6813 addptr(to, 8);
6814 BIND(L_fill_8_bytes);
6815 subptr(count, 1 << (shift + 1));
6816 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6817 }
6818 }
6819 // fill trailing 4 bytes
6820 BIND(L_fill_4_bytes);
6821 testl(count, 1<<shift);
6822 jccb(Assembler::zero, L_fill_2_bytes);
6823 movl(Address(to, 0), value);
6824 if (t == T_BYTE || t == T_SHORT) {
6825 Label L_fill_byte;
6826 addptr(to, 4);
6827 BIND(L_fill_2_bytes);
6828 // fill trailing 2 bytes
6829 testl(count, 1<<(shift-1));
6830 jccb(Assembler::zero, L_fill_byte);
6831 movw(Address(to, 0), value);
6832 if (t == T_BYTE) {
6833 addptr(to, 2);
6834 BIND(L_fill_byte);
6835 // fill trailing byte
6836 testl(count, 1);
6837 jccb(Assembler::zero, L_exit);
6838 movb(Address(to, 0), value);
6839 } else {
6840 BIND(L_fill_byte);
6841 }
6842 } else {
6843 BIND(L_fill_2_bytes);
6844 }
6845 BIND(L_exit);
6846 }
6847
6848 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6849 switch(type) {
6850 case T_BYTE:
6851 case T_BOOLEAN:
6852 evpbroadcastb(dst, src, vector_len);
6853 break;
6854 case T_SHORT:
6855 case T_CHAR:
6856 evpbroadcastw(dst, src, vector_len);
6857 break;
6858 case T_INT:
6859 case T_FLOAT:
6860 evpbroadcastd(dst, src, vector_len);
6861 break;
6862 case T_LONG:
6863 case T_DOUBLE:
6864 evpbroadcastq(dst, src, vector_len);
6865 break;
6866 default:
6867 fatal("Unhandled type : %s", type2name(type));
6868 break;
6869 }
6870 }
6871
6872 // encode char[] to byte[] in ISO_8859_1 or ASCII
6873 //@IntrinsicCandidate
6874 //private static int implEncodeISOArray(byte[] sa, int sp,
6875 //byte[] da, int dp, int len) {
6876 // int i = 0;
6877 // for (; i < len; i++) {
6878 // char c = StringUTF16.getChar(sa, sp++);
6879 // if (c > '\u00FF')
6880 // break;
6881 // da[dp++] = (byte)c;
6882 // }
6883 // return i;
6884 //}
6885 //
6886 //@IntrinsicCandidate
6887 //private static int implEncodeAsciiArray(char[] sa, int sp,
6888 // byte[] da, int dp, int len) {
6889 // int i = 0;
6890 // for (; i < len; i++) {
6891 // char c = sa[sp++];
6892 // if (c >= '\u0080')
6893 // break;
6894 // da[dp++] = (byte)c;
6895 // }
6896 // return i;
6897 //}
6898 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6899 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6900 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6901 Register tmp5, Register result, bool ascii) {
6902
6903 // rsi: src
6904 // rdi: dst
6905 // rdx: len
6906 // rcx: tmp5
6907 // rax: result
6908 ShortBranchVerifier sbv(this);
6909 assert_different_registers(src, dst, len, tmp5, result);
6910 Label L_done, L_copy_1_char, L_copy_1_char_exit;
6911
6912 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
6913 int short_mask = ascii ? 0xff80 : 0xff00;
6914
6915 // set result
6916 xorl(result, result);
6917 // check for zero length
6918 testl(len, len);
6919 jcc(Assembler::zero, L_done);
6920
6921 movl(result, len);
6922
6923 // Setup pointers
6924 lea(src, Address(src, len, Address::times_2)); // char[]
6925 lea(dst, Address(dst, len, Address::times_1)); // byte[]
6926 negptr(len);
6927
6928 if (UseSSE42Intrinsics || UseAVX >= 2) {
6929 Label L_copy_8_chars, L_copy_8_chars_exit;
6930 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
6931
6932 if (UseAVX >= 2) {
6933 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
6934 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6935 movdl(tmp1Reg, tmp5);
6936 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
6937 jmp(L_chars_32_check);
6938
6939 bind(L_copy_32_chars);
6940 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
6941 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
6942 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6943 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6944 jccb(Assembler::notZero, L_copy_32_chars_exit);
6945 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6946 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
6947 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
6948
6949 bind(L_chars_32_check);
6950 addptr(len, 32);
6951 jcc(Assembler::lessEqual, L_copy_32_chars);
6952
6953 bind(L_copy_32_chars_exit);
6954 subptr(len, 16);
6955 jccb(Assembler::greater, L_copy_16_chars_exit);
6956
6957 } else if (UseSSE42Intrinsics) {
6958 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6959 movdl(tmp1Reg, tmp5);
6960 pshufd(tmp1Reg, tmp1Reg, 0);
6961 jmpb(L_chars_16_check);
6962 }
6963
6964 bind(L_copy_16_chars);
6965 if (UseAVX >= 2) {
6966 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
6967 vptest(tmp2Reg, tmp1Reg);
6968 jcc(Assembler::notZero, L_copy_16_chars_exit);
6969 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
6970 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
6971 } else {
6972 if (UseAVX > 0) {
6973 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6974 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6975 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
6976 } else {
6977 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6978 por(tmp2Reg, tmp3Reg);
6979 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6980 por(tmp2Reg, tmp4Reg);
6981 }
6982 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6983 jccb(Assembler::notZero, L_copy_16_chars_exit);
6984 packuswb(tmp3Reg, tmp4Reg);
6985 }
6986 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
6987
6988 bind(L_chars_16_check);
6989 addptr(len, 16);
6990 jcc(Assembler::lessEqual, L_copy_16_chars);
6991
6992 bind(L_copy_16_chars_exit);
6993 if (UseAVX >= 2) {
6994 // clean upper bits of YMM registers
6995 vpxor(tmp2Reg, tmp2Reg);
6996 vpxor(tmp3Reg, tmp3Reg);
6997 vpxor(tmp4Reg, tmp4Reg);
6998 movdl(tmp1Reg, tmp5);
6999 pshufd(tmp1Reg, tmp1Reg, 0);
7000 }
7001 subptr(len, 8);
7002 jccb(Assembler::greater, L_copy_8_chars_exit);
7003
7004 bind(L_copy_8_chars);
7005 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7006 ptest(tmp3Reg, tmp1Reg);
7007 jccb(Assembler::notZero, L_copy_8_chars_exit);
7008 packuswb(tmp3Reg, tmp1Reg);
7009 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7010 addptr(len, 8);
7011 jccb(Assembler::lessEqual, L_copy_8_chars);
7012
7013 bind(L_copy_8_chars_exit);
7014 subptr(len, 8);
7015 jccb(Assembler::zero, L_done);
7016 }
7017
7018 bind(L_copy_1_char);
7019 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7020 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
7021 jccb(Assembler::notZero, L_copy_1_char_exit);
7022 movb(Address(dst, len, Address::times_1, 0), tmp5);
7023 addptr(len, 1);
7024 jccb(Assembler::less, L_copy_1_char);
7025
7026 bind(L_copy_1_char_exit);
7027 addptr(result, len); // len is negative count of not processed elements
7028
7029 bind(L_done);
7030 }
7031
7032 #ifdef _LP64
7033 /**
7034 * Helper for multiply_to_len().
7035 */
7036 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7037 addq(dest_lo, src1);
7038 adcq(dest_hi, 0);
7039 addq(dest_lo, src2);
7040 adcq(dest_hi, 0);
7041 }
7042
7043 /**
7044 * Multiply 64 bit by 64 bit first loop.
7045 */
7046 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7047 Register y, Register y_idx, Register z,
7048 Register carry, Register product,
7049 Register idx, Register kdx) {
7050 //
7051 // jlong carry, x[], y[], z[];
7052 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7053 // huge_128 product = y[idx] * x[xstart] + carry;
7054 // z[kdx] = (jlong)product;
7055 // carry = (jlong)(product >>> 64);
7056 // }
7057 // z[xstart] = carry;
7058 //
7059
7060 Label L_first_loop, L_first_loop_exit;
7061 Label L_one_x, L_one_y, L_multiply;
7062
7063 decrementl(xstart);
7064 jcc(Assembler::negative, L_one_x);
7065
7066 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7067 rorq(x_xstart, 32); // convert big-endian to little-endian
7068
7069 bind(L_first_loop);
7070 decrementl(idx);
7071 jcc(Assembler::negative, L_first_loop_exit);
7072 decrementl(idx);
7073 jcc(Assembler::negative, L_one_y);
7074 movq(y_idx, Address(y, idx, Address::times_4, 0));
7075 rorq(y_idx, 32); // convert big-endian to little-endian
7076 bind(L_multiply);
7077 movq(product, x_xstart);
7078 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7079 addq(product, carry);
7080 adcq(rdx, 0);
7081 subl(kdx, 2);
7082 movl(Address(z, kdx, Address::times_4, 4), product);
7083 shrq(product, 32);
7084 movl(Address(z, kdx, Address::times_4, 0), product);
7085 movq(carry, rdx);
7086 jmp(L_first_loop);
7087
7088 bind(L_one_y);
7089 movl(y_idx, Address(y, 0));
7090 jmp(L_multiply);
7091
7092 bind(L_one_x);
7093 movl(x_xstart, Address(x, 0));
7094 jmp(L_first_loop);
7095
7096 bind(L_first_loop_exit);
7097 }
7098
7099 /**
7100 * Multiply 64 bit by 64 bit and add 128 bit.
7101 */
7102 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7103 Register yz_idx, Register idx,
7104 Register carry, Register product, int offset) {
7105 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7106 // z[kdx] = (jlong)product;
7107
7108 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7109 rorq(yz_idx, 32); // convert big-endian to little-endian
7110 movq(product, x_xstart);
7111 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7112 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7113 rorq(yz_idx, 32); // convert big-endian to little-endian
7114
7115 add2_with_carry(rdx, product, carry, yz_idx);
7116
7117 movl(Address(z, idx, Address::times_4, offset+4), product);
7118 shrq(product, 32);
7119 movl(Address(z, idx, Address::times_4, offset), product);
7120
7121 }
7122
7123 /**
7124 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7125 */
7126 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7127 Register yz_idx, Register idx, Register jdx,
7128 Register carry, Register product,
7129 Register carry2) {
7130 // jlong carry, x[], y[], z[];
7131 // int kdx = ystart+1;
7132 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7133 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7134 // z[kdx+idx+1] = (jlong)product;
7135 // jlong carry2 = (jlong)(product >>> 64);
7136 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7137 // z[kdx+idx] = (jlong)product;
7138 // carry = (jlong)(product >>> 64);
7139 // }
7140 // idx += 2;
7141 // if (idx > 0) {
7142 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7143 // z[kdx+idx] = (jlong)product;
7144 // carry = (jlong)(product >>> 64);
7145 // }
7146 //
7147
7148 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7149
7150 movl(jdx, idx);
7151 andl(jdx, 0xFFFFFFFC);
7152 shrl(jdx, 2);
7153
7154 bind(L_third_loop);
7155 subl(jdx, 1);
7156 jcc(Assembler::negative, L_third_loop_exit);
7157 subl(idx, 4);
7158
7159 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7160 movq(carry2, rdx);
7161
7162 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7163 movq(carry, rdx);
7164 jmp(L_third_loop);
7165
7166 bind (L_third_loop_exit);
7167
7168 andl (idx, 0x3);
7169 jcc(Assembler::zero, L_post_third_loop_done);
7170
7171 Label L_check_1;
7172 subl(idx, 2);
7173 jcc(Assembler::negative, L_check_1);
7174
7175 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7176 movq(carry, rdx);
7177
7178 bind (L_check_1);
7179 addl (idx, 0x2);
7180 andl (idx, 0x1);
7181 subl(idx, 1);
7182 jcc(Assembler::negative, L_post_third_loop_done);
7183
7184 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7185 movq(product, x_xstart);
7186 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7187 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7188
7189 add2_with_carry(rdx, product, yz_idx, carry);
7190
7191 movl(Address(z, idx, Address::times_4, 0), product);
7192 shrq(product, 32);
7193
7194 shlq(rdx, 32);
7195 orq(product, rdx);
7196 movq(carry, product);
7197
7198 bind(L_post_third_loop_done);
7199 }
7200
7201 /**
7202 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7203 *
7204 */
7205 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7206 Register carry, Register carry2,
7207 Register idx, Register jdx,
7208 Register yz_idx1, Register yz_idx2,
7209 Register tmp, Register tmp3, Register tmp4) {
7210 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7211
7212 // jlong carry, x[], y[], z[];
7213 // int kdx = ystart+1;
7214 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7215 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7216 // jlong carry2 = (jlong)(tmp3 >>> 64);
7217 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7218 // carry = (jlong)(tmp4 >>> 64);
7219 // z[kdx+idx+1] = (jlong)tmp3;
7220 // z[kdx+idx] = (jlong)tmp4;
7221 // }
7222 // idx += 2;
7223 // if (idx > 0) {
7224 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7225 // z[kdx+idx] = (jlong)yz_idx1;
7226 // carry = (jlong)(yz_idx1 >>> 64);
7227 // }
7228 //
7229
7230 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7231
7232 movl(jdx, idx);
7233 andl(jdx, 0xFFFFFFFC);
7234 shrl(jdx, 2);
7235
7236 bind(L_third_loop);
7237 subl(jdx, 1);
7238 jcc(Assembler::negative, L_third_loop_exit);
7239 subl(idx, 4);
7240
7241 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7242 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7243 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7244 rorxq(yz_idx2, yz_idx2, 32);
7245
7246 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7247 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7248
7249 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7250 rorxq(yz_idx1, yz_idx1, 32);
7251 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7252 rorxq(yz_idx2, yz_idx2, 32);
7253
7254 if (VM_Version::supports_adx()) {
7255 adcxq(tmp3, carry);
7256 adoxq(tmp3, yz_idx1);
7257
7258 adcxq(tmp4, tmp);
7259 adoxq(tmp4, yz_idx2);
7260
7261 movl(carry, 0); // does not affect flags
7262 adcxq(carry2, carry);
7263 adoxq(carry2, carry);
7264 } else {
7265 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7266 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7267 }
7268 movq(carry, carry2);
7269
7270 movl(Address(z, idx, Address::times_4, 12), tmp3);
7271 shrq(tmp3, 32);
7272 movl(Address(z, idx, Address::times_4, 8), tmp3);
7273
7274 movl(Address(z, idx, Address::times_4, 4), tmp4);
7275 shrq(tmp4, 32);
7276 movl(Address(z, idx, Address::times_4, 0), tmp4);
7277
7278 jmp(L_third_loop);
7279
7280 bind (L_third_loop_exit);
7281
7282 andl (idx, 0x3);
7283 jcc(Assembler::zero, L_post_third_loop_done);
7284
7285 Label L_check_1;
7286 subl(idx, 2);
7287 jcc(Assembler::negative, L_check_1);
7288
7289 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7290 rorxq(yz_idx1, yz_idx1, 32);
7291 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7292 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7293 rorxq(yz_idx2, yz_idx2, 32);
7294
7295 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7296
7297 movl(Address(z, idx, Address::times_4, 4), tmp3);
7298 shrq(tmp3, 32);
7299 movl(Address(z, idx, Address::times_4, 0), tmp3);
7300 movq(carry, tmp4);
7301
7302 bind (L_check_1);
7303 addl (idx, 0x2);
7304 andl (idx, 0x1);
7305 subl(idx, 1);
7306 jcc(Assembler::negative, L_post_third_loop_done);
7307 movl(tmp4, Address(y, idx, Address::times_4, 0));
7308 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7309 movl(tmp4, Address(z, idx, Address::times_4, 0));
7310
7311 add2_with_carry(carry2, tmp3, tmp4, carry);
7312
7313 movl(Address(z, idx, Address::times_4, 0), tmp3);
7314 shrq(tmp3, 32);
7315
7316 shlq(carry2, 32);
7317 orq(tmp3, carry2);
7318 movq(carry, tmp3);
7319
7320 bind(L_post_third_loop_done);
7321 }
7322
7323 /**
7324 * Code for BigInteger::multiplyToLen() intrinsic.
7325 *
7326 * rdi: x
7327 * rax: xlen
7328 * rsi: y
7329 * rcx: ylen
7330 * r8: z
7331 * r11: tmp0
7332 * r12: tmp1
7333 * r13: tmp2
7334 * r14: tmp3
7335 * r15: tmp4
7336 * rbx: tmp5
7337 *
7338 */
7339 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7340 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7341 ShortBranchVerifier sbv(this);
7342 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7343
7344 push(tmp0);
7345 push(tmp1);
7346 push(tmp2);
7347 push(tmp3);
7348 push(tmp4);
7349 push(tmp5);
7350
7351 push(xlen);
7352
7353 const Register idx = tmp1;
7354 const Register kdx = tmp2;
7355 const Register xstart = tmp3;
7356
7357 const Register y_idx = tmp4;
7358 const Register carry = tmp5;
7359 const Register product = xlen;
7360 const Register x_xstart = tmp0;
7361
7362 // First Loop.
7363 //
7364 // final static long LONG_MASK = 0xffffffffL;
7365 // int xstart = xlen - 1;
7366 // int ystart = ylen - 1;
7367 // long carry = 0;
7368 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7369 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7370 // z[kdx] = (int)product;
7371 // carry = product >>> 32;
7372 // }
7373 // z[xstart] = (int)carry;
7374 //
7375
7376 movl(idx, ylen); // idx = ylen;
7377 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7378 xorq(carry, carry); // carry = 0;
7379
7380 Label L_done;
7381
7382 movl(xstart, xlen);
7383 decrementl(xstart);
7384 jcc(Assembler::negative, L_done);
7385
7386 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7387
7388 Label L_second_loop;
7389 testl(kdx, kdx);
7390 jcc(Assembler::zero, L_second_loop);
7391
7392 Label L_carry;
7393 subl(kdx, 1);
7394 jcc(Assembler::zero, L_carry);
7395
7396 movl(Address(z, kdx, Address::times_4, 0), carry);
7397 shrq(carry, 32);
7398 subl(kdx, 1);
7399
7400 bind(L_carry);
7401 movl(Address(z, kdx, Address::times_4, 0), carry);
7402
7403 // Second and third (nested) loops.
7404 //
7405 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7406 // carry = 0;
7407 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7408 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7409 // (z[k] & LONG_MASK) + carry;
7410 // z[k] = (int)product;
7411 // carry = product >>> 32;
7412 // }
7413 // z[i] = (int)carry;
7414 // }
7415 //
7416 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7417
7418 const Register jdx = tmp1;
7419
7420 bind(L_second_loop);
7421 xorl(carry, carry); // carry = 0;
7422 movl(jdx, ylen); // j = ystart+1
7423
7424 subl(xstart, 1); // i = xstart-1;
7425 jcc(Assembler::negative, L_done);
7426
7427 push (z);
7428
7429 Label L_last_x;
7430 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7431 subl(xstart, 1); // i = xstart-1;
7432 jcc(Assembler::negative, L_last_x);
7433
7434 if (UseBMI2Instructions) {
7435 movq(rdx, Address(x, xstart, Address::times_4, 0));
7436 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7437 } else {
7438 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7439 rorq(x_xstart, 32); // convert big-endian to little-endian
7440 }
7441
7442 Label L_third_loop_prologue;
7443 bind(L_third_loop_prologue);
7444
7445 push (x);
7446 push (xstart);
7447 push (ylen);
7448
7449
7450 if (UseBMI2Instructions) {
7451 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7452 } else { // !UseBMI2Instructions
7453 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7454 }
7455
7456 pop(ylen);
7457 pop(xlen);
7458 pop(x);
7459 pop(z);
7460
7461 movl(tmp3, xlen);
7462 addl(tmp3, 1);
7463 movl(Address(z, tmp3, Address::times_4, 0), carry);
7464 subl(tmp3, 1);
7465 jccb(Assembler::negative, L_done);
7466
7467 shrq(carry, 32);
7468 movl(Address(z, tmp3, Address::times_4, 0), carry);
7469 jmp(L_second_loop);
7470
7471 // Next infrequent code is moved outside loops.
7472 bind(L_last_x);
7473 if (UseBMI2Instructions) {
7474 movl(rdx, Address(x, 0));
7475 } else {
7476 movl(x_xstart, Address(x, 0));
7477 }
7478 jmp(L_third_loop_prologue);
7479
7480 bind(L_done);
7481
7482 pop(xlen);
7483
7484 pop(tmp5);
7485 pop(tmp4);
7486 pop(tmp3);
7487 pop(tmp2);
7488 pop(tmp1);
7489 pop(tmp0);
7490 }
7491
7492 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7493 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7494 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7495 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7496 Label VECTOR8_TAIL, VECTOR4_TAIL;
7497 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7498 Label SAME_TILL_END, DONE;
7499 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7500
7501 //scale is in rcx in both Win64 and Unix
7502 ShortBranchVerifier sbv(this);
7503
7504 shlq(length);
7505 xorq(result, result);
7506
7507 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7508 VM_Version::supports_avx512vlbw()) {
7509 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7510
7511 cmpq(length, 64);
7512 jcc(Assembler::less, VECTOR32_TAIL);
7513
7514 movq(tmp1, length);
7515 andq(tmp1, 0x3F); // tail count
7516 andq(length, ~(0x3F)); //vector count
7517
7518 bind(VECTOR64_LOOP);
7519 // AVX512 code to compare 64 byte vectors.
7520 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7521 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7522 kortestql(k7, k7);
7523 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7524 addq(result, 64);
7525 subq(length, 64);
7526 jccb(Assembler::notZero, VECTOR64_LOOP);
7527
7528 //bind(VECTOR64_TAIL);
7529 testq(tmp1, tmp1);
7530 jcc(Assembler::zero, SAME_TILL_END);
7531
7532 //bind(VECTOR64_TAIL);
7533 // AVX512 code to compare up to 63 byte vectors.
7534 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7535 shlxq(tmp2, tmp2, tmp1);
7536 notq(tmp2);
7537 kmovql(k3, tmp2);
7538
7539 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7540 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7541
7542 ktestql(k7, k3);
7543 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7544
7545 bind(VECTOR64_NOT_EQUAL);
7546 kmovql(tmp1, k7);
7547 notq(tmp1);
7548 tzcntq(tmp1, tmp1);
7549 addq(result, tmp1);
7550 shrq(result);
7551 jmp(DONE);
7552 bind(VECTOR32_TAIL);
7553 }
7554
7555 cmpq(length, 8);
7556 jcc(Assembler::equal, VECTOR8_LOOP);
7557 jcc(Assembler::less, VECTOR4_TAIL);
7558
7559 if (UseAVX >= 2) {
7560 Label VECTOR16_TAIL, VECTOR32_LOOP;
7561
7562 cmpq(length, 16);
7563 jcc(Assembler::equal, VECTOR16_LOOP);
7564 jcc(Assembler::less, VECTOR8_LOOP);
7565
7566 cmpq(length, 32);
7567 jccb(Assembler::less, VECTOR16_TAIL);
7568
7569 subq(length, 32);
7570 bind(VECTOR32_LOOP);
7571 vmovdqu(rymm0, Address(obja, result));
7572 vmovdqu(rymm1, Address(objb, result));
7573 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7574 vptest(rymm2, rymm2);
7575 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7576 addq(result, 32);
7577 subq(length, 32);
7578 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7579 addq(length, 32);
7580 jcc(Assembler::equal, SAME_TILL_END);
7581 //falling through if less than 32 bytes left //close the branch here.
7582
7583 bind(VECTOR16_TAIL);
7584 cmpq(length, 16);
7585 jccb(Assembler::less, VECTOR8_TAIL);
7586 bind(VECTOR16_LOOP);
7587 movdqu(rymm0, Address(obja, result));
7588 movdqu(rymm1, Address(objb, result));
7589 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7590 ptest(rymm2, rymm2);
7591 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7592 addq(result, 16);
7593 subq(length, 16);
7594 jcc(Assembler::equal, SAME_TILL_END);
7595 //falling through if less than 16 bytes left
7596 } else {//regular intrinsics
7597
7598 cmpq(length, 16);
7599 jccb(Assembler::less, VECTOR8_TAIL);
7600
7601 subq(length, 16);
7602 bind(VECTOR16_LOOP);
7603 movdqu(rymm0, Address(obja, result));
7604 movdqu(rymm1, Address(objb, result));
7605 pxor(rymm0, rymm1);
7606 ptest(rymm0, rymm0);
7607 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7608 addq(result, 16);
7609 subq(length, 16);
7610 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7611 addq(length, 16);
7612 jcc(Assembler::equal, SAME_TILL_END);
7613 //falling through if less than 16 bytes left
7614 }
7615
7616 bind(VECTOR8_TAIL);
7617 cmpq(length, 8);
7618 jccb(Assembler::less, VECTOR4_TAIL);
7619 bind(VECTOR8_LOOP);
7620 movq(tmp1, Address(obja, result));
7621 movq(tmp2, Address(objb, result));
7622 xorq(tmp1, tmp2);
7623 testq(tmp1, tmp1);
7624 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7625 addq(result, 8);
7626 subq(length, 8);
7627 jcc(Assembler::equal, SAME_TILL_END);
7628 //falling through if less than 8 bytes left
7629
7630 bind(VECTOR4_TAIL);
7631 cmpq(length, 4);
7632 jccb(Assembler::less, BYTES_TAIL);
7633 bind(VECTOR4_LOOP);
7634 movl(tmp1, Address(obja, result));
7635 xorl(tmp1, Address(objb, result));
7636 testl(tmp1, tmp1);
7637 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7638 addq(result, 4);
7639 subq(length, 4);
7640 jcc(Assembler::equal, SAME_TILL_END);
7641 //falling through if less than 4 bytes left
7642
7643 bind(BYTES_TAIL);
7644 bind(BYTES_LOOP);
7645 load_unsigned_byte(tmp1, Address(obja, result));
7646 load_unsigned_byte(tmp2, Address(objb, result));
7647 xorl(tmp1, tmp2);
7648 testl(tmp1, tmp1);
7649 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7650 decq(length);
7651 jcc(Assembler::zero, SAME_TILL_END);
7652 incq(result);
7653 load_unsigned_byte(tmp1, Address(obja, result));
7654 load_unsigned_byte(tmp2, Address(objb, result));
7655 xorl(tmp1, tmp2);
7656 testl(tmp1, tmp1);
7657 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7658 decq(length);
7659 jcc(Assembler::zero, SAME_TILL_END);
7660 incq(result);
7661 load_unsigned_byte(tmp1, Address(obja, result));
7662 load_unsigned_byte(tmp2, Address(objb, result));
7663 xorl(tmp1, tmp2);
7664 testl(tmp1, tmp1);
7665 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7666 jmp(SAME_TILL_END);
7667
7668 if (UseAVX >= 2) {
7669 bind(VECTOR32_NOT_EQUAL);
7670 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7671 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7672 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7673 vpmovmskb(tmp1, rymm0);
7674 bsfq(tmp1, tmp1);
7675 addq(result, tmp1);
7676 shrq(result);
7677 jmp(DONE);
7678 }
7679
7680 bind(VECTOR16_NOT_EQUAL);
7681 if (UseAVX >= 2) {
7682 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7683 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7684 pxor(rymm0, rymm2);
7685 } else {
7686 pcmpeqb(rymm2, rymm2);
7687 pxor(rymm0, rymm1);
7688 pcmpeqb(rymm0, rymm1);
7689 pxor(rymm0, rymm2);
7690 }
7691 pmovmskb(tmp1, rymm0);
7692 bsfq(tmp1, tmp1);
7693 addq(result, tmp1);
7694 shrq(result);
7695 jmpb(DONE);
7696
7697 bind(VECTOR8_NOT_EQUAL);
7698 bind(VECTOR4_NOT_EQUAL);
7699 bsfq(tmp1, tmp1);
7700 shrq(tmp1, 3);
7701 addq(result, tmp1);
7702 bind(BYTES_NOT_EQUAL);
7703 shrq(result);
7704 jmpb(DONE);
7705
7706 bind(SAME_TILL_END);
7707 mov64(result, -1);
7708
7709 bind(DONE);
7710 }
7711
7712 //Helper functions for square_to_len()
7713
7714 /**
7715 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7716 * Preserves x and z and modifies rest of the registers.
7717 */
7718 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7719 // Perform square and right shift by 1
7720 // Handle odd xlen case first, then for even xlen do the following
7721 // jlong carry = 0;
7722 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7723 // huge_128 product = x[j:j+1] * x[j:j+1];
7724 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7725 // z[i+2:i+3] = (jlong)(product >>> 1);
7726 // carry = (jlong)product;
7727 // }
7728
7729 xorq(tmp5, tmp5); // carry
7730 xorq(rdxReg, rdxReg);
7731 xorl(tmp1, tmp1); // index for x
7732 xorl(tmp4, tmp4); // index for z
7733
7734 Label L_first_loop, L_first_loop_exit;
7735
7736 testl(xlen, 1);
7737 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7738
7739 // Square and right shift by 1 the odd element using 32 bit multiply
7740 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7741 imulq(raxReg, raxReg);
7742 shrq(raxReg, 1);
7743 adcq(tmp5, 0);
7744 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7745 incrementl(tmp1);
7746 addl(tmp4, 2);
7747
7748 // Square and right shift by 1 the rest using 64 bit multiply
7749 bind(L_first_loop);
7750 cmpptr(tmp1, xlen);
7751 jccb(Assembler::equal, L_first_loop_exit);
7752
7753 // Square
7754 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7755 rorq(raxReg, 32); // convert big-endian to little-endian
7756 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7757
7758 // Right shift by 1 and save carry
7759 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7760 rcrq(rdxReg, 1);
7761 rcrq(raxReg, 1);
7762 adcq(tmp5, 0);
7763
7764 // Store result in z
7765 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7766 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7767
7768 // Update indices for x and z
7769 addl(tmp1, 2);
7770 addl(tmp4, 4);
7771 jmp(L_first_loop);
7772
7773 bind(L_first_loop_exit);
7774 }
7775
7776
7777 /**
7778 * Perform the following multiply add operation using BMI2 instructions
7779 * carry:sum = sum + op1*op2 + carry
7780 * op2 should be in rdx
7781 * op2 is preserved, all other registers are modified
7782 */
7783 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7784 // assert op2 is rdx
7785 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7786 addq(sum, carry);
7787 adcq(tmp2, 0);
7788 addq(sum, op1);
7789 adcq(tmp2, 0);
7790 movq(carry, tmp2);
7791 }
7792
7793 /**
7794 * Perform the following multiply add operation:
7795 * carry:sum = sum + op1*op2 + carry
7796 * Preserves op1, op2 and modifies rest of registers
7797 */
7798 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7799 // rdx:rax = op1 * op2
7800 movq(raxReg, op2);
7801 mulq(op1);
7802
7803 // rdx:rax = sum + carry + rdx:rax
7804 addq(sum, carry);
7805 adcq(rdxReg, 0);
7806 addq(sum, raxReg);
7807 adcq(rdxReg, 0);
7808
7809 // carry:sum = rdx:sum
7810 movq(carry, rdxReg);
7811 }
7812
7813 /**
7814 * Add 64 bit long carry into z[] with carry propagation.
7815 * Preserves z and carry register values and modifies rest of registers.
7816 *
7817 */
7818 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7819 Label L_fourth_loop, L_fourth_loop_exit;
7820
7821 movl(tmp1, 1);
7822 subl(zlen, 2);
7823 addq(Address(z, zlen, Address::times_4, 0), carry);
7824
7825 bind(L_fourth_loop);
7826 jccb(Assembler::carryClear, L_fourth_loop_exit);
7827 subl(zlen, 2);
7828 jccb(Assembler::negative, L_fourth_loop_exit);
7829 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7830 jmp(L_fourth_loop);
7831 bind(L_fourth_loop_exit);
7832 }
7833
7834 /**
7835 * Shift z[] left by 1 bit.
7836 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7837 *
7838 */
7839 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7840
7841 Label L_fifth_loop, L_fifth_loop_exit;
7842
7843 // Fifth loop
7844 // Perform primitiveLeftShift(z, zlen, 1)
7845
7846 const Register prev_carry = tmp1;
7847 const Register new_carry = tmp4;
7848 const Register value = tmp2;
7849 const Register zidx = tmp3;
7850
7851 // int zidx, carry;
7852 // long value;
7853 // carry = 0;
7854 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7855 // (carry:value) = (z[i] << 1) | carry ;
7856 // z[i] = value;
7857 // }
7858
7859 movl(zidx, zlen);
7860 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7861
7862 bind(L_fifth_loop);
7863 decl(zidx); // Use decl to preserve carry flag
7864 decl(zidx);
7865 jccb(Assembler::negative, L_fifth_loop_exit);
7866
7867 if (UseBMI2Instructions) {
7868 movq(value, Address(z, zidx, Address::times_4, 0));
7869 rclq(value, 1);
7870 rorxq(value, value, 32);
7871 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7872 }
7873 else {
7874 // clear new_carry
7875 xorl(new_carry, new_carry);
7876
7877 // Shift z[i] by 1, or in previous carry and save new carry
7878 movq(value, Address(z, zidx, Address::times_4, 0));
7879 shlq(value, 1);
7880 adcl(new_carry, 0);
7881
7882 orq(value, prev_carry);
7883 rorq(value, 0x20);
7884 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7885
7886 // Set previous carry = new carry
7887 movl(prev_carry, new_carry);
7888 }
7889 jmp(L_fifth_loop);
7890
7891 bind(L_fifth_loop_exit);
7892 }
7893
7894
7895 /**
7896 * Code for BigInteger::squareToLen() intrinsic
7897 *
7898 * rdi: x
7899 * rsi: len
7900 * r8: z
7901 * rcx: zlen
7902 * r12: tmp1
7903 * r13: tmp2
7904 * r14: tmp3
7905 * r15: tmp4
7906 * rbx: tmp5
7907 *
7908 */
7909 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7910
7911 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
7912 push(tmp1);
7913 push(tmp2);
7914 push(tmp3);
7915 push(tmp4);
7916 push(tmp5);
7917
7918 // First loop
7919 // Store the squares, right shifted one bit (i.e., divided by 2).
7920 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7921
7922 // Add in off-diagonal sums.
7923 //
7924 // Second, third (nested) and fourth loops.
7925 // zlen +=2;
7926 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7927 // carry = 0;
7928 // long op2 = x[xidx:xidx+1];
7929 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7930 // k -= 2;
7931 // long op1 = x[j:j+1];
7932 // long sum = z[k:k+1];
7933 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7934 // z[k:k+1] = sum;
7935 // }
7936 // add_one_64(z, k, carry, tmp_regs);
7937 // }
7938
7939 const Register carry = tmp5;
7940 const Register sum = tmp3;
7941 const Register op1 = tmp4;
7942 Register op2 = tmp2;
7943
7944 push(zlen);
7945 push(len);
7946 addl(zlen,2);
7947 bind(L_second_loop);
7948 xorq(carry, carry);
7949 subl(zlen, 4);
7950 subl(len, 2);
7951 push(zlen);
7952 push(len);
7953 cmpl(len, 0);
7954 jccb(Assembler::lessEqual, L_second_loop_exit);
7955
7956 // Multiply an array by one 64 bit long.
7957 if (UseBMI2Instructions) {
7958 op2 = rdxReg;
7959 movq(op2, Address(x, len, Address::times_4, 0));
7960 rorxq(op2, op2, 32);
7961 }
7962 else {
7963 movq(op2, Address(x, len, Address::times_4, 0));
7964 rorq(op2, 32);
7965 }
7966
7967 bind(L_third_loop);
7968 decrementl(len);
7969 jccb(Assembler::negative, L_third_loop_exit);
7970 decrementl(len);
7971 jccb(Assembler::negative, L_last_x);
7972
7973 movq(op1, Address(x, len, Address::times_4, 0));
7974 rorq(op1, 32);
7975
7976 bind(L_multiply);
7977 subl(zlen, 2);
7978 movq(sum, Address(z, zlen, Address::times_4, 0));
7979
7980 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
7981 if (UseBMI2Instructions) {
7982 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
7983 }
7984 else {
7985 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7986 }
7987
7988 movq(Address(z, zlen, Address::times_4, 0), sum);
7989
7990 jmp(L_third_loop);
7991 bind(L_third_loop_exit);
7992
7993 // Fourth loop
7994 // Add 64 bit long carry into z with carry propagation.
7995 // Uses offsetted zlen.
7996 add_one_64(z, zlen, carry, tmp1);
7997
7998 pop(len);
7999 pop(zlen);
8000 jmp(L_second_loop);
8001
8002 // Next infrequent code is moved outside loops.
8003 bind(L_last_x);
8004 movl(op1, Address(x, 0));
8005 jmp(L_multiply);
8006
8007 bind(L_second_loop_exit);
8008 pop(len);
8009 pop(zlen);
8010 pop(len);
8011 pop(zlen);
8012
8013 // Fifth loop
8014 // Shift z left 1 bit.
8015 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8016
8017 // z[zlen-1] |= x[len-1] & 1;
8018 movl(tmp3, Address(x, len, Address::times_4, -4));
8019 andl(tmp3, 1);
8020 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8021
8022 pop(tmp5);
8023 pop(tmp4);
8024 pop(tmp3);
8025 pop(tmp2);
8026 pop(tmp1);
8027 }
8028
8029 /**
8030 * Helper function for mul_add()
8031 * Multiply the in[] by int k and add to out[] starting at offset offs using
8032 * 128 bit by 32 bit multiply and return the carry in tmp5.
8033 * Only quad int aligned length of in[] is operated on in this function.
8034 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8035 * This function preserves out, in and k registers.
8036 * len and offset point to the appropriate index in "in" & "out" correspondingly
8037 * tmp5 has the carry.
8038 * other registers are temporary and are modified.
8039 *
8040 */
8041 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8042 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8043 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8044
8045 Label L_first_loop, L_first_loop_exit;
8046
8047 movl(tmp1, len);
8048 shrl(tmp1, 2);
8049
8050 bind(L_first_loop);
8051 subl(tmp1, 1);
8052 jccb(Assembler::negative, L_first_loop_exit);
8053
8054 subl(len, 4);
8055 subl(offset, 4);
8056
8057 Register op2 = tmp2;
8058 const Register sum = tmp3;
8059 const Register op1 = tmp4;
8060 const Register carry = tmp5;
8061
8062 if (UseBMI2Instructions) {
8063 op2 = rdxReg;
8064 }
8065
8066 movq(op1, Address(in, len, Address::times_4, 8));
8067 rorq(op1, 32);
8068 movq(sum, Address(out, offset, Address::times_4, 8));
8069 rorq(sum, 32);
8070 if (UseBMI2Instructions) {
8071 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8072 }
8073 else {
8074 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8075 }
8076 // Store back in big endian from little endian
8077 rorq(sum, 0x20);
8078 movq(Address(out, offset, Address::times_4, 8), sum);
8079
8080 movq(op1, Address(in, len, Address::times_4, 0));
8081 rorq(op1, 32);
8082 movq(sum, Address(out, offset, Address::times_4, 0));
8083 rorq(sum, 32);
8084 if (UseBMI2Instructions) {
8085 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8086 }
8087 else {
8088 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8089 }
8090 // Store back in big endian from little endian
8091 rorq(sum, 0x20);
8092 movq(Address(out, offset, Address::times_4, 0), sum);
8093
8094 jmp(L_first_loop);
8095 bind(L_first_loop_exit);
8096 }
8097
8098 /**
8099 * Code for BigInteger::mulAdd() intrinsic
8100 *
8101 * rdi: out
8102 * rsi: in
8103 * r11: offs (out.length - offset)
8104 * rcx: len
8105 * r8: k
8106 * r12: tmp1
8107 * r13: tmp2
8108 * r14: tmp3
8109 * r15: tmp4
8110 * rbx: tmp5
8111 * Multiply the in[] by word k and add to out[], return the carry in rax
8112 */
8113 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8114 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8115 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8116
8117 Label L_carry, L_last_in, L_done;
8118
8119 // carry = 0;
8120 // for (int j=len-1; j >= 0; j--) {
8121 // long product = (in[j] & LONG_MASK) * kLong +
8122 // (out[offs] & LONG_MASK) + carry;
8123 // out[offs--] = (int)product;
8124 // carry = product >>> 32;
8125 // }
8126 //
8127 push(tmp1);
8128 push(tmp2);
8129 push(tmp3);
8130 push(tmp4);
8131 push(tmp5);
8132
8133 Register op2 = tmp2;
8134 const Register sum = tmp3;
8135 const Register op1 = tmp4;
8136 const Register carry = tmp5;
8137
8138 if (UseBMI2Instructions) {
8139 op2 = rdxReg;
8140 movl(op2, k);
8141 }
8142 else {
8143 movl(op2, k);
8144 }
8145
8146 xorq(carry, carry);
8147
8148 //First loop
8149
8150 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8151 //The carry is in tmp5
8152 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8153
8154 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8155 decrementl(len);
8156 jccb(Assembler::negative, L_carry);
8157 decrementl(len);
8158 jccb(Assembler::negative, L_last_in);
8159
8160 movq(op1, Address(in, len, Address::times_4, 0));
8161 rorq(op1, 32);
8162
8163 subl(offs, 2);
8164 movq(sum, Address(out, offs, Address::times_4, 0));
8165 rorq(sum, 32);
8166
8167 if (UseBMI2Instructions) {
8168 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8169 }
8170 else {
8171 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8172 }
8173
8174 // Store back in big endian from little endian
8175 rorq(sum, 0x20);
8176 movq(Address(out, offs, Address::times_4, 0), sum);
8177
8178 testl(len, len);
8179 jccb(Assembler::zero, L_carry);
8180
8181 //Multiply the last in[] entry, if any
8182 bind(L_last_in);
8183 movl(op1, Address(in, 0));
8184 movl(sum, Address(out, offs, Address::times_4, -4));
8185
8186 movl(raxReg, k);
8187 mull(op1); //tmp4 * eax -> edx:eax
8188 addl(sum, carry);
8189 adcl(rdxReg, 0);
8190 addl(sum, raxReg);
8191 adcl(rdxReg, 0);
8192 movl(carry, rdxReg);
8193
8194 movl(Address(out, offs, Address::times_4, -4), sum);
8195
8196 bind(L_carry);
8197 //return tmp5/carry as carry in rax
8198 movl(rax, carry);
8199
8200 bind(L_done);
8201 pop(tmp5);
8202 pop(tmp4);
8203 pop(tmp3);
8204 pop(tmp2);
8205 pop(tmp1);
8206 }
8207 #endif
8208
8209 /**
8210 * Emits code to update CRC-32 with a byte value according to constants in table
8211 *
8212 * @param [in,out]crc Register containing the crc.
8213 * @param [in]val Register containing the byte to fold into the CRC.
8214 * @param [in]table Register containing the table of crc constants.
8215 *
8216 * uint32_t crc;
8217 * val = crc_table[(val ^ crc) & 0xFF];
8218 * crc = val ^ (crc >> 8);
8219 *
8220 */
8221 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8222 xorl(val, crc);
8223 andl(val, 0xFF);
8224 shrl(crc, 8); // unsigned shift
8225 xorl(crc, Address(table, val, Address::times_4, 0));
8226 }
8227
8228 /**
8229 * Fold 128-bit data chunk
8230 */
8231 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8232 if (UseAVX > 0) {
8233 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8234 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8235 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8236 pxor(xcrc, xtmp);
8237 } else {
8238 movdqa(xtmp, xcrc);
8239 pclmulhdq(xtmp, xK); // [123:64]
8240 pclmulldq(xcrc, xK); // [63:0]
8241 pxor(xcrc, xtmp);
8242 movdqu(xtmp, Address(buf, offset));
8243 pxor(xcrc, xtmp);
8244 }
8245 }
8246
8247 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8248 if (UseAVX > 0) {
8249 vpclmulhdq(xtmp, xK, xcrc);
8250 vpclmulldq(xcrc, xK, xcrc);
8251 pxor(xcrc, xbuf);
8252 pxor(xcrc, xtmp);
8253 } else {
8254 movdqa(xtmp, xcrc);
8255 pclmulhdq(xtmp, xK);
8256 pclmulldq(xcrc, xK);
8257 pxor(xcrc, xbuf);
8258 pxor(xcrc, xtmp);
8259 }
8260 }
8261
8262 /**
8263 * 8-bit folds to compute 32-bit CRC
8264 *
8265 * uint64_t xcrc;
8266 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8267 */
8268 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8269 movdl(tmp, xcrc);
8270 andl(tmp, 0xFF);
8271 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8272 psrldq(xcrc, 1); // unsigned shift one byte
8273 pxor(xcrc, xtmp);
8274 }
8275
8276 /**
8277 * uint32_t crc;
8278 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8279 */
8280 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8281 movl(tmp, crc);
8282 andl(tmp, 0xFF);
8283 shrl(crc, 8);
8284 xorl(crc, Address(table, tmp, Address::times_4, 0));
8285 }
8286
8287 /**
8288 * @param crc register containing existing CRC (32-bit)
8289 * @param buf register pointing to input byte buffer (byte*)
8290 * @param len register containing number of bytes
8291 * @param table register that will contain address of CRC table
8292 * @param tmp scratch register
8293 */
8294 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8295 assert_different_registers(crc, buf, len, table, tmp, rax);
8296
8297 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8298 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8299
8300 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8301 // context for the registers used, where all instructions below are using 128-bit mode
8302 // On EVEX without VL and BW, these instructions will all be AVX.
8303 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8304 notl(crc); // ~crc
8305 cmpl(len, 16);
8306 jcc(Assembler::less, L_tail);
8307
8308 // Align buffer to 16 bytes
8309 movl(tmp, buf);
8310 andl(tmp, 0xF);
8311 jccb(Assembler::zero, L_aligned);
8312 subl(tmp, 16);
8313 addl(len, tmp);
8314
8315 align(4);
8316 BIND(L_align_loop);
8317 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8318 update_byte_crc32(crc, rax, table);
8319 increment(buf);
8320 incrementl(tmp);
8321 jccb(Assembler::less, L_align_loop);
8322
8323 BIND(L_aligned);
8324 movl(tmp, len); // save
8325 shrl(len, 4);
8326 jcc(Assembler::zero, L_tail_restore);
8327
8328 // Fold crc into first bytes of vector
8329 movdqa(xmm1, Address(buf, 0));
8330 movdl(rax, xmm1);
8331 xorl(crc, rax);
8332 if (VM_Version::supports_sse4_1()) {
8333 pinsrd(xmm1, crc, 0);
8334 } else {
8335 pinsrw(xmm1, crc, 0);
8336 shrl(crc, 16);
8337 pinsrw(xmm1, crc, 1);
8338 }
8339 addptr(buf, 16);
8340 subl(len, 4); // len > 0
8341 jcc(Assembler::less, L_fold_tail);
8342
8343 movdqa(xmm2, Address(buf, 0));
8344 movdqa(xmm3, Address(buf, 16));
8345 movdqa(xmm4, Address(buf, 32));
8346 addptr(buf, 48);
8347 subl(len, 3);
8348 jcc(Assembler::lessEqual, L_fold_512b);
8349
8350 // Fold total 512 bits of polynomial on each iteration,
8351 // 128 bits per each of 4 parallel streams.
8352 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8353
8354 align32();
8355 BIND(L_fold_512b_loop);
8356 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8357 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8358 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8359 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8360 addptr(buf, 64);
8361 subl(len, 4);
8362 jcc(Assembler::greater, L_fold_512b_loop);
8363
8364 // Fold 512 bits to 128 bits.
8365 BIND(L_fold_512b);
8366 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8367 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8368 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8369 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8370
8371 // Fold the rest of 128 bits data chunks
8372 BIND(L_fold_tail);
8373 addl(len, 3);
8374 jccb(Assembler::lessEqual, L_fold_128b);
8375 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8376
8377 BIND(L_fold_tail_loop);
8378 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8379 addptr(buf, 16);
8380 decrementl(len);
8381 jccb(Assembler::greater, L_fold_tail_loop);
8382
8383 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8384 BIND(L_fold_128b);
8385 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8386 if (UseAVX > 0) {
8387 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8388 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8389 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8390 } else {
8391 movdqa(xmm2, xmm0);
8392 pclmulqdq(xmm2, xmm1, 0x1);
8393 movdqa(xmm3, xmm0);
8394 pand(xmm3, xmm2);
8395 pclmulqdq(xmm0, xmm3, 0x1);
8396 }
8397 psrldq(xmm1, 8);
8398 psrldq(xmm2, 4);
8399 pxor(xmm0, xmm1);
8400 pxor(xmm0, xmm2);
8401
8402 // 8 8-bit folds to compute 32-bit CRC.
8403 for (int j = 0; j < 4; j++) {
8404 fold_8bit_crc32(xmm0, table, xmm1, rax);
8405 }
8406 movdl(crc, xmm0); // mov 32 bits to general register
8407 for (int j = 0; j < 4; j++) {
8408 fold_8bit_crc32(crc, table, rax);
8409 }
8410
8411 BIND(L_tail_restore);
8412 movl(len, tmp); // restore
8413 BIND(L_tail);
8414 andl(len, 0xf);
8415 jccb(Assembler::zero, L_exit);
8416
8417 // Fold the rest of bytes
8418 align(4);
8419 BIND(L_tail_loop);
8420 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8421 update_byte_crc32(crc, rax, table);
8422 increment(buf);
8423 decrementl(len);
8424 jccb(Assembler::greater, L_tail_loop);
8425
8426 BIND(L_exit);
8427 notl(crc); // ~c
8428 }
8429
8430 #ifdef _LP64
8431 // Helper function for AVX 512 CRC32
8432 // Fold 512-bit data chunks
8433 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8434 Register pos, int offset) {
8435 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8436 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8437 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8438 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8439 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8440 }
8441
8442 // Helper function for AVX 512 CRC32
8443 // Compute CRC32 for < 256B buffers
8444 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8445 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8446 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8447
8448 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8449 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8450 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8451
8452 // check if there is enough buffer to be able to fold 16B at a time
8453 cmpl(len, 32);
8454 jcc(Assembler::less, L_less_than_32);
8455
8456 // if there is, load the constants
8457 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8458 movdl(xmm0, crc); // get the initial crc value
8459 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8460 pxor(xmm7, xmm0);
8461
8462 // update the buffer pointer
8463 addl(pos, 16);
8464 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8465 subl(len, 32);
8466 jmp(L_16B_reduction_loop);
8467
8468 bind(L_less_than_32);
8469 //mov initial crc to the return value. this is necessary for zero - length buffers.
8470 movl(rax, crc);
8471 testl(len, len);
8472 jcc(Assembler::equal, L_cleanup);
8473
8474 movdl(xmm0, crc); //get the initial crc value
8475
8476 cmpl(len, 16);
8477 jcc(Assembler::equal, L_exact_16_left);
8478 jcc(Assembler::less, L_less_than_16_left);
8479
8480 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8481 pxor(xmm7, xmm0); //xor the initial crc value
8482 addl(pos, 16);
8483 subl(len, 16);
8484 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8485 jmp(L_get_last_two_xmms);
8486
8487 bind(L_less_than_16_left);
8488 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8489 pxor(xmm1, xmm1);
8490 movptr(tmp1, rsp);
8491 movdqu(Address(tmp1, 0 * 16), xmm1);
8492
8493 cmpl(len, 4);
8494 jcc(Assembler::less, L_only_less_than_4);
8495
8496 //backup the counter value
8497 movl(tmp2, len);
8498 cmpl(len, 8);
8499 jcc(Assembler::less, L_less_than_8_left);
8500
8501 //load 8 Bytes
8502 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8503 movq(Address(tmp1, 0 * 16), rax);
8504 addptr(tmp1, 8);
8505 subl(len, 8);
8506 addl(pos, 8);
8507
8508 bind(L_less_than_8_left);
8509 cmpl(len, 4);
8510 jcc(Assembler::less, L_less_than_4_left);
8511
8512 //load 4 Bytes
8513 movl(rax, Address(buf, pos, Address::times_1, 0));
8514 movl(Address(tmp1, 0 * 16), rax);
8515 addptr(tmp1, 4);
8516 subl(len, 4);
8517 addl(pos, 4);
8518
8519 bind(L_less_than_4_left);
8520 cmpl(len, 2);
8521 jcc(Assembler::less, L_less_than_2_left);
8522
8523 // load 2 Bytes
8524 movw(rax, Address(buf, pos, Address::times_1, 0));
8525 movl(Address(tmp1, 0 * 16), rax);
8526 addptr(tmp1, 2);
8527 subl(len, 2);
8528 addl(pos, 2);
8529
8530 bind(L_less_than_2_left);
8531 cmpl(len, 1);
8532 jcc(Assembler::less, L_zero_left);
8533
8534 // load 1 Byte
8535 movb(rax, Address(buf, pos, Address::times_1, 0));
8536 movb(Address(tmp1, 0 * 16), rax);
8537
8538 bind(L_zero_left);
8539 movdqu(xmm7, Address(rsp, 0));
8540 pxor(xmm7, xmm0); //xor the initial crc value
8541
8542 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8543 movdqu(xmm0, Address(rax, tmp2));
8544 pshufb(xmm7, xmm0);
8545 jmp(L_128_done);
8546
8547 bind(L_exact_16_left);
8548 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8549 pxor(xmm7, xmm0); //xor the initial crc value
8550 jmp(L_128_done);
8551
8552 bind(L_only_less_than_4);
8553 cmpl(len, 3);
8554 jcc(Assembler::less, L_only_less_than_3);
8555
8556 // load 3 Bytes
8557 movb(rax, Address(buf, pos, Address::times_1, 0));
8558 movb(Address(tmp1, 0), rax);
8559
8560 movb(rax, Address(buf, pos, Address::times_1, 1));
8561 movb(Address(tmp1, 1), rax);
8562
8563 movb(rax, Address(buf, pos, Address::times_1, 2));
8564 movb(Address(tmp1, 2), rax);
8565
8566 movdqu(xmm7, Address(rsp, 0));
8567 pxor(xmm7, xmm0); //xor the initial crc value
8568
8569 pslldq(xmm7, 0x5);
8570 jmp(L_barrett);
8571 bind(L_only_less_than_3);
8572 cmpl(len, 2);
8573 jcc(Assembler::less, L_only_less_than_2);
8574
8575 // load 2 Bytes
8576 movb(rax, Address(buf, pos, Address::times_1, 0));
8577 movb(Address(tmp1, 0), rax);
8578
8579 movb(rax, Address(buf, pos, Address::times_1, 1));
8580 movb(Address(tmp1, 1), rax);
8581
8582 movdqu(xmm7, Address(rsp, 0));
8583 pxor(xmm7, xmm0); //xor the initial crc value
8584
8585 pslldq(xmm7, 0x6);
8586 jmp(L_barrett);
8587
8588 bind(L_only_less_than_2);
8589 //load 1 Byte
8590 movb(rax, Address(buf, pos, Address::times_1, 0));
8591 movb(Address(tmp1, 0), rax);
8592
8593 movdqu(xmm7, Address(rsp, 0));
8594 pxor(xmm7, xmm0); //xor the initial crc value
8595
8596 pslldq(xmm7, 0x7);
8597 }
8598
8599 /**
8600 * Compute CRC32 using AVX512 instructions
8601 * param crc register containing existing CRC (32-bit)
8602 * param buf register pointing to input byte buffer (byte*)
8603 * param len register containing number of bytes
8604 * param table address of crc or crc32c table
8605 * param tmp1 scratch register
8606 * param tmp2 scratch register
8607 * return rax result register
8608 *
8609 * This routine is identical for crc32c with the exception of the precomputed constant
8610 * table which will be passed as the table argument. The calculation steps are
8611 * the same for both variants.
8612 */
8613 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8614 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8615
8616 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8617 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8618 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8619 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8620 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8621
8622 const Register pos = r12;
8623 push(r12);
8624 subptr(rsp, 16 * 2 + 8);
8625
8626 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8627 // context for the registers used, where all instructions below are using 128-bit mode
8628 // On EVEX without VL and BW, these instructions will all be AVX.
8629 movl(pos, 0);
8630
8631 // check if smaller than 256B
8632 cmpl(len, 256);
8633 jcc(Assembler::less, L_less_than_256);
8634
8635 // load the initial crc value
8636 movdl(xmm10, crc);
8637
8638 // receive the initial 64B data, xor the initial crc value
8639 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8640 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8641 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8642 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8643
8644 subl(len, 256);
8645 cmpl(len, 256);
8646 jcc(Assembler::less, L_fold_128_B_loop);
8647
8648 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8649 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8650 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8651 subl(len, 256);
8652
8653 bind(L_fold_256_B_loop);
8654 addl(pos, 256);
8655 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8656 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8657 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8658 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8659
8660 subl(len, 256);
8661 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8662
8663 // Fold 256 into 128
8664 addl(pos, 256);
8665 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8666 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8667 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8668
8669 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8670 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8671 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8672
8673 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8674 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8675
8676 addl(len, 128);
8677 jmp(L_fold_128_B_register);
8678
8679 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8680 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8681
8682 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8683 bind(L_fold_128_B_loop);
8684 addl(pos, 128);
8685 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8686 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8687
8688 subl(len, 128);
8689 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8690
8691 addl(pos, 128);
8692
8693 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8694 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8695 bind(L_fold_128_B_register);
8696 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8697 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8698 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8699 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8700 // save last that has no multiplicand
8701 vextracti64x2(xmm7, xmm4, 3);
8702
8703 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8704 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8705 // Needed later in reduction loop
8706 movdqu(xmm10, Address(table, 1 * 16));
8707 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8708 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8709
8710 // Swap 1,0,3,2 - 01 00 11 10
8711 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8712 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8713 vextracti128(xmm5, xmm8, 1);
8714 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8715
8716 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8717 // instead of a cmp instruction, we use the negative flag with the jl instruction
8718 addl(len, 128 - 16);
8719 jcc(Assembler::less, L_final_reduction_for_128);
8720
8721 bind(L_16B_reduction_loop);
8722 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8723 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8724 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8725 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8726 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8727 addl(pos, 16);
8728 subl(len, 16);
8729 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8730
8731 bind(L_final_reduction_for_128);
8732 addl(len, 16);
8733 jcc(Assembler::equal, L_128_done);
8734
8735 bind(L_get_last_two_xmms);
8736 movdqu(xmm2, xmm7);
8737 addl(pos, len);
8738 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8739 subl(pos, len);
8740
8741 // get rid of the extra data that was loaded before
8742 // load the shift constant
8743 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8744 movdqu(xmm0, Address(rax, len));
8745 addl(rax, len);
8746
8747 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8748 //Change mask to 512
8749 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8750 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8751
8752 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8753 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8754 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8755 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8756 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8757
8758 bind(L_128_done);
8759 // compute crc of a 128-bit value
8760 movdqu(xmm10, Address(table, 3 * 16));
8761 movdqu(xmm0, xmm7);
8762
8763 // 64b fold
8764 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8765 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8766 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8767
8768 // 32b fold
8769 movdqu(xmm0, xmm7);
8770 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8771 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8772 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8773 jmp(L_barrett);
8774
8775 bind(L_less_than_256);
8776 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8777
8778 //barrett reduction
8779 bind(L_barrett);
8780 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8781 movdqu(xmm1, xmm7);
8782 movdqu(xmm2, xmm7);
8783 movdqu(xmm10, Address(table, 4 * 16));
8784
8785 pclmulqdq(xmm7, xmm10, 0x0);
8786 pxor(xmm7, xmm2);
8787 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8788 movdqu(xmm2, xmm7);
8789 pclmulqdq(xmm7, xmm10, 0x10);
8790 pxor(xmm7, xmm2);
8791 pxor(xmm7, xmm1);
8792 pextrd(crc, xmm7, 2);
8793
8794 bind(L_cleanup);
8795 addptr(rsp, 16 * 2 + 8);
8796 pop(r12);
8797 }
8798
8799 // S. Gueron / Information Processing Letters 112 (2012) 184
8800 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8801 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8802 // Output: the 64-bit carry-less product of B * CONST
8803 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8804 Register tmp1, Register tmp2, Register tmp3) {
8805 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8806 if (n > 0) {
8807 addq(tmp3, n * 256 * 8);
8808 }
8809 // Q1 = TABLEExt[n][B & 0xFF];
8810 movl(tmp1, in);
8811 andl(tmp1, 0x000000FF);
8812 shll(tmp1, 3);
8813 addq(tmp1, tmp3);
8814 movq(tmp1, Address(tmp1, 0));
8815
8816 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8817 movl(tmp2, in);
8818 shrl(tmp2, 8);
8819 andl(tmp2, 0x000000FF);
8820 shll(tmp2, 3);
8821 addq(tmp2, tmp3);
8822 movq(tmp2, Address(tmp2, 0));
8823
8824 shlq(tmp2, 8);
8825 xorq(tmp1, tmp2);
8826
8827 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8828 movl(tmp2, in);
8829 shrl(tmp2, 16);
8830 andl(tmp2, 0x000000FF);
8831 shll(tmp2, 3);
8832 addq(tmp2, tmp3);
8833 movq(tmp2, Address(tmp2, 0));
8834
8835 shlq(tmp2, 16);
8836 xorq(tmp1, tmp2);
8837
8838 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8839 shrl(in, 24);
8840 andl(in, 0x000000FF);
8841 shll(in, 3);
8842 addq(in, tmp3);
8843 movq(in, Address(in, 0));
8844
8845 shlq(in, 24);
8846 xorq(in, tmp1);
8847 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8848 }
8849
8850 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8851 Register in_out,
8852 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8853 XMMRegister w_xtmp2,
8854 Register tmp1,
8855 Register n_tmp2, Register n_tmp3) {
8856 if (is_pclmulqdq_supported) {
8857 movdl(w_xtmp1, in_out); // modified blindly
8858
8859 movl(tmp1, const_or_pre_comp_const_index);
8860 movdl(w_xtmp2, tmp1);
8861 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8862
8863 movdq(in_out, w_xtmp1);
8864 } else {
8865 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8866 }
8867 }
8868
8869 // Recombination Alternative 2: No bit-reflections
8870 // T1 = (CRC_A * U1) << 1
8871 // T2 = (CRC_B * U2) << 1
8872 // C1 = T1 >> 32
8873 // C2 = T2 >> 32
8874 // T1 = T1 & 0xFFFFFFFF
8875 // T2 = T2 & 0xFFFFFFFF
8876 // T1 = CRC32(0, T1)
8877 // T2 = CRC32(0, T2)
8878 // C1 = C1 ^ T1
8879 // C2 = C2 ^ T2
8880 // CRC = C1 ^ C2 ^ CRC_C
8881 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8882 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8883 Register tmp1, Register tmp2,
8884 Register n_tmp3) {
8885 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8886 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8887 shlq(in_out, 1);
8888 movl(tmp1, in_out);
8889 shrq(in_out, 32);
8890 xorl(tmp2, tmp2);
8891 crc32(tmp2, tmp1, 4);
8892 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8893 shlq(in1, 1);
8894 movl(tmp1, in1);
8895 shrq(in1, 32);
8896 xorl(tmp2, tmp2);
8897 crc32(tmp2, tmp1, 4);
8898 xorl(in1, tmp2);
8899 xorl(in_out, in1);
8900 xorl(in_out, in2);
8901 }
8902
8903 // Set N to predefined value
8904 // Subtract from a length of a buffer
8905 // execute in a loop:
8906 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8907 // for i = 1 to N do
8908 // CRC_A = CRC32(CRC_A, A[i])
8909 // CRC_B = CRC32(CRC_B, B[i])
8910 // CRC_C = CRC32(CRC_C, C[i])
8911 // end for
8912 // Recombine
8913 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8914 Register in_out1, Register in_out2, Register in_out3,
8915 Register tmp1, Register tmp2, Register tmp3,
8916 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8917 Register tmp4, Register tmp5,
8918 Register n_tmp6) {
8919 Label L_processPartitions;
8920 Label L_processPartition;
8921 Label L_exit;
8922
8923 bind(L_processPartitions);
8924 cmpl(in_out1, 3 * size);
8925 jcc(Assembler::less, L_exit);
8926 xorl(tmp1, tmp1);
8927 xorl(tmp2, tmp2);
8928 movq(tmp3, in_out2);
8929 addq(tmp3, size);
8930
8931 bind(L_processPartition);
8932 crc32(in_out3, Address(in_out2, 0), 8);
8933 crc32(tmp1, Address(in_out2, size), 8);
8934 crc32(tmp2, Address(in_out2, size * 2), 8);
8935 addq(in_out2, 8);
8936 cmpq(in_out2, tmp3);
8937 jcc(Assembler::less, L_processPartition);
8938 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8939 w_xtmp1, w_xtmp2, w_xtmp3,
8940 tmp4, tmp5,
8941 n_tmp6);
8942 addq(in_out2, 2 * size);
8943 subl(in_out1, 3 * size);
8944 jmp(L_processPartitions);
8945
8946 bind(L_exit);
8947 }
8948 #else
8949 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
8950 Register tmp1, Register tmp2, Register tmp3,
8951 XMMRegister xtmp1, XMMRegister xtmp2) {
8952 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8953 if (n > 0) {
8954 addl(tmp3, n * 256 * 8);
8955 }
8956 // Q1 = TABLEExt[n][B & 0xFF];
8957 movl(tmp1, in_out);
8958 andl(tmp1, 0x000000FF);
8959 shll(tmp1, 3);
8960 addl(tmp1, tmp3);
8961 movq(xtmp1, Address(tmp1, 0));
8962
8963 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8964 movl(tmp2, in_out);
8965 shrl(tmp2, 8);
8966 andl(tmp2, 0x000000FF);
8967 shll(tmp2, 3);
8968 addl(tmp2, tmp3);
8969 movq(xtmp2, Address(tmp2, 0));
8970
8971 psllq(xtmp2, 8);
8972 pxor(xtmp1, xtmp2);
8973
8974 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8975 movl(tmp2, in_out);
8976 shrl(tmp2, 16);
8977 andl(tmp2, 0x000000FF);
8978 shll(tmp2, 3);
8979 addl(tmp2, tmp3);
8980 movq(xtmp2, Address(tmp2, 0));
8981
8982 psllq(xtmp2, 16);
8983 pxor(xtmp1, xtmp2);
8984
8985 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8986 shrl(in_out, 24);
8987 andl(in_out, 0x000000FF);
8988 shll(in_out, 3);
8989 addl(in_out, tmp3);
8990 movq(xtmp2, Address(in_out, 0));
8991
8992 psllq(xtmp2, 24);
8993 pxor(xtmp1, xtmp2); // Result in CXMM
8994 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8995 }
8996
8997 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8998 Register in_out,
8999 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9000 XMMRegister w_xtmp2,
9001 Register tmp1,
9002 Register n_tmp2, Register n_tmp3) {
9003 if (is_pclmulqdq_supported) {
9004 movdl(w_xtmp1, in_out);
9005
9006 movl(tmp1, const_or_pre_comp_const_index);
9007 movdl(w_xtmp2, tmp1);
9008 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9009 // Keep result in XMM since GPR is 32 bit in length
9010 } else {
9011 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
9012 }
9013 }
9014
9015 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9016 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9017 Register tmp1, Register tmp2,
9018 Register n_tmp3) {
9019 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9020 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9021
9022 psllq(w_xtmp1, 1);
9023 movdl(tmp1, w_xtmp1);
9024 psrlq(w_xtmp1, 32);
9025 movdl(in_out, w_xtmp1);
9026
9027 xorl(tmp2, tmp2);
9028 crc32(tmp2, tmp1, 4);
9029 xorl(in_out, tmp2);
9030
9031 psllq(w_xtmp2, 1);
9032 movdl(tmp1, w_xtmp2);
9033 psrlq(w_xtmp2, 32);
9034 movdl(in1, w_xtmp2);
9035
9036 xorl(tmp2, tmp2);
9037 crc32(tmp2, tmp1, 4);
9038 xorl(in1, tmp2);
9039 xorl(in_out, in1);
9040 xorl(in_out, in2);
9041 }
9042
9043 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9044 Register in_out1, Register in_out2, Register in_out3,
9045 Register tmp1, Register tmp2, Register tmp3,
9046 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9047 Register tmp4, Register tmp5,
9048 Register n_tmp6) {
9049 Label L_processPartitions;
9050 Label L_processPartition;
9051 Label L_exit;
9052
9053 bind(L_processPartitions);
9054 cmpl(in_out1, 3 * size);
9055 jcc(Assembler::less, L_exit);
9056 xorl(tmp1, tmp1);
9057 xorl(tmp2, tmp2);
9058 movl(tmp3, in_out2);
9059 addl(tmp3, size);
9060
9061 bind(L_processPartition);
9062 crc32(in_out3, Address(in_out2, 0), 4);
9063 crc32(tmp1, Address(in_out2, size), 4);
9064 crc32(tmp2, Address(in_out2, size*2), 4);
9065 crc32(in_out3, Address(in_out2, 0+4), 4);
9066 crc32(tmp1, Address(in_out2, size+4), 4);
9067 crc32(tmp2, Address(in_out2, size*2+4), 4);
9068 addl(in_out2, 8);
9069 cmpl(in_out2, tmp3);
9070 jcc(Assembler::less, L_processPartition);
9071
9072 push(tmp3);
9073 push(in_out1);
9074 push(in_out2);
9075 tmp4 = tmp3;
9076 tmp5 = in_out1;
9077 n_tmp6 = in_out2;
9078
9079 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9080 w_xtmp1, w_xtmp2, w_xtmp3,
9081 tmp4, tmp5,
9082 n_tmp6);
9083
9084 pop(in_out2);
9085 pop(in_out1);
9086 pop(tmp3);
9087
9088 addl(in_out2, 2 * size);
9089 subl(in_out1, 3 * size);
9090 jmp(L_processPartitions);
9091
9092 bind(L_exit);
9093 }
9094 #endif //LP64
9095
9096 #ifdef _LP64
9097 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9098 // Input: A buffer I of L bytes.
9099 // Output: the CRC32C value of the buffer.
9100 // Notations:
9101 // Write L = 24N + r, with N = floor (L/24).
9102 // r = L mod 24 (0 <= r < 24).
9103 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9104 // N quadwords, and R consists of r bytes.
9105 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9106 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9107 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9108 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9109 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9110 Register tmp1, Register tmp2, Register tmp3,
9111 Register tmp4, Register tmp5, Register tmp6,
9112 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9113 bool is_pclmulqdq_supported) {
9114 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9115 Label L_wordByWord;
9116 Label L_byteByByteProlog;
9117 Label L_byteByByte;
9118 Label L_exit;
9119
9120 if (is_pclmulqdq_supported ) {
9121 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9122 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
9123
9124 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9125 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9126
9127 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9128 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9129 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9130 } else {
9131 const_or_pre_comp_const_index[0] = 1;
9132 const_or_pre_comp_const_index[1] = 0;
9133
9134 const_or_pre_comp_const_index[2] = 3;
9135 const_or_pre_comp_const_index[3] = 2;
9136
9137 const_or_pre_comp_const_index[4] = 5;
9138 const_or_pre_comp_const_index[5] = 4;
9139 }
9140 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9141 in2, in1, in_out,
9142 tmp1, tmp2, tmp3,
9143 w_xtmp1, w_xtmp2, w_xtmp3,
9144 tmp4, tmp5,
9145 tmp6);
9146 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9147 in2, in1, in_out,
9148 tmp1, tmp2, tmp3,
9149 w_xtmp1, w_xtmp2, w_xtmp3,
9150 tmp4, tmp5,
9151 tmp6);
9152 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9153 in2, in1, in_out,
9154 tmp1, tmp2, tmp3,
9155 w_xtmp1, w_xtmp2, w_xtmp3,
9156 tmp4, tmp5,
9157 tmp6);
9158 movl(tmp1, in2);
9159 andl(tmp1, 0x00000007);
9160 negl(tmp1);
9161 addl(tmp1, in2);
9162 addq(tmp1, in1);
9163
9164 cmpq(in1, tmp1);
9165 jccb(Assembler::greaterEqual, L_byteByByteProlog);
9166 align(16);
9167 BIND(L_wordByWord);
9168 crc32(in_out, Address(in1, 0), 8);
9169 addq(in1, 8);
9170 cmpq(in1, tmp1);
9171 jcc(Assembler::less, L_wordByWord);
9172
9173 BIND(L_byteByByteProlog);
9174 andl(in2, 0x00000007);
9175 movl(tmp2, 1);
9176
9177 cmpl(tmp2, in2);
9178 jccb(Assembler::greater, L_exit);
9179 BIND(L_byteByByte);
9180 crc32(in_out, Address(in1, 0), 1);
9181 incq(in1);
9182 incl(tmp2);
9183 cmpl(tmp2, in2);
9184 jcc(Assembler::lessEqual, L_byteByByte);
9185
9186 BIND(L_exit);
9187 }
9188 #else
9189 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9190 Register tmp1, Register tmp2, Register tmp3,
9191 Register tmp4, Register tmp5, Register tmp6,
9192 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9193 bool is_pclmulqdq_supported) {
9194 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9195 Label L_wordByWord;
9196 Label L_byteByByteProlog;
9197 Label L_byteByByte;
9198 Label L_exit;
9199
9200 if (is_pclmulqdq_supported) {
9201 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9202 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
9203
9204 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9205 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9206
9207 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9208 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9209 } else {
9210 const_or_pre_comp_const_index[0] = 1;
9211 const_or_pre_comp_const_index[1] = 0;
9212
9213 const_or_pre_comp_const_index[2] = 3;
9214 const_or_pre_comp_const_index[3] = 2;
9215
9216 const_or_pre_comp_const_index[4] = 5;
9217 const_or_pre_comp_const_index[5] = 4;
9218 }
9219 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9220 in2, in1, in_out,
9221 tmp1, tmp2, tmp3,
9222 w_xtmp1, w_xtmp2, w_xtmp3,
9223 tmp4, tmp5,
9224 tmp6);
9225 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9226 in2, in1, in_out,
9227 tmp1, tmp2, tmp3,
9228 w_xtmp1, w_xtmp2, w_xtmp3,
9229 tmp4, tmp5,
9230 tmp6);
9231 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9232 in2, in1, in_out,
9233 tmp1, tmp2, tmp3,
9234 w_xtmp1, w_xtmp2, w_xtmp3,
9235 tmp4, tmp5,
9236 tmp6);
9237 movl(tmp1, in2);
9238 andl(tmp1, 0x00000007);
9239 negl(tmp1);
9240 addl(tmp1, in2);
9241 addl(tmp1, in1);
9242
9243 BIND(L_wordByWord);
9244 cmpl(in1, tmp1);
9245 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9246 crc32(in_out, Address(in1,0), 4);
9247 addl(in1, 4);
9248 jmp(L_wordByWord);
9249
9250 BIND(L_byteByByteProlog);
9251 andl(in2, 0x00000007);
9252 movl(tmp2, 1);
9253
9254 BIND(L_byteByByte);
9255 cmpl(tmp2, in2);
9256 jccb(Assembler::greater, L_exit);
9257 movb(tmp1, Address(in1, 0));
9258 crc32(in_out, tmp1, 1);
9259 incl(in1);
9260 incl(tmp2);
9261 jmp(L_byteByByte);
9262
9263 BIND(L_exit);
9264 }
9265 #endif // LP64
9266 #undef BIND
9267 #undef BLOCK_COMMENT
9268
9269 // Compress char[] array to byte[].
9270 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
9271 // Return the array length if every element in array can be encoded,
9272 // otherwise, the index of first non-latin1 (> 0xff) character.
9273 // @IntrinsicCandidate
9274 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9275 // for (int i = 0; i < len; i++) {
9276 // char c = src[srcOff];
9277 // if (c > 0xff) {
9278 // return i; // return index of non-latin1 char
9279 // }
9280 // dst[dstOff] = (byte)c;
9281 // srcOff++;
9282 // dstOff++;
9283 // }
9284 // return len;
9285 // }
9286 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9287 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9288 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9289 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9290 Label copy_chars_loop, done, reset_sp, copy_tail;
9291
9292 // rsi: src
9293 // rdi: dst
9294 // rdx: len
9295 // rcx: tmp5
9296 // rax: result
9297
9298 // rsi holds start addr of source char[] to be compressed
9299 // rdi holds start addr of destination byte[]
9300 // rdx holds length
9301
9302 assert(len != result, "");
9303
9304 // save length for return
9305 movl(result, len);
9306
9307 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9308 VM_Version::supports_avx512vlbw() &&
9309 VM_Version::supports_bmi2()) {
9310
9311 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9312
9313 // alignment
9314 Label post_alignment;
9315
9316 // if length of the string is less than 32, handle it the old fashioned way
9317 testl(len, -32);
9318 jcc(Assembler::zero, below_threshold);
9319
9320 // First check whether a character is compressible ( <= 0xFF).
9321 // Create mask to test for Unicode chars inside zmm vector
9322 movl(tmp5, 0x00FF);
9323 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9324
9325 testl(len, -64);
9326 jccb(Assembler::zero, post_alignment);
9327
9328 movl(tmp5, dst);
9329 andl(tmp5, (32 - 1));
9330 negl(tmp5);
9331 andl(tmp5, (32 - 1));
9332
9333 // bail out when there is nothing to be done
9334 testl(tmp5, 0xFFFFFFFF);
9335 jccb(Assembler::zero, post_alignment);
9336
9337 // ~(~0 << len), where len is the # of remaining elements to process
9338 movl(len, 0xFFFFFFFF);
9339 shlxl(len, len, tmp5);
9340 notl(len);
9341 kmovdl(mask2, len);
9342 movl(len, result);
9343
9344 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9345 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9346 ktestd(mask1, mask2);
9347 jcc(Assembler::carryClear, copy_tail);
9348
9349 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9350
9351 addptr(src, tmp5);
9352 addptr(src, tmp5);
9353 addptr(dst, tmp5);
9354 subl(len, tmp5);
9355
9356 bind(post_alignment);
9357 // end of alignment
9358
9359 movl(tmp5, len);
9360 andl(tmp5, (32 - 1)); // tail count (in chars)
9361 andl(len, ~(32 - 1)); // vector count (in chars)
9362 jccb(Assembler::zero, copy_loop_tail);
9363
9364 lea(src, Address(src, len, Address::times_2));
9365 lea(dst, Address(dst, len, Address::times_1));
9366 negptr(len);
9367
9368 bind(copy_32_loop);
9369 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9370 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9371 kortestdl(mask1, mask1);
9372 jccb(Assembler::carryClear, reset_for_copy_tail);
9373
9374 // All elements in current processed chunk are valid candidates for
9375 // compression. Write a truncated byte elements to the memory.
9376 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9377 addptr(len, 32);
9378 jccb(Assembler::notZero, copy_32_loop);
9379
9380 bind(copy_loop_tail);
9381 // bail out when there is nothing to be done
9382 testl(tmp5, 0xFFFFFFFF);
9383 jcc(Assembler::zero, done);
9384
9385 movl(len, tmp5);
9386
9387 // ~(~0 << len), where len is the # of remaining elements to process
9388 movl(tmp5, 0xFFFFFFFF);
9389 shlxl(tmp5, tmp5, len);
9390 notl(tmp5);
9391
9392 kmovdl(mask2, tmp5);
9393
9394 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9395 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9396 ktestd(mask1, mask2);
9397 jcc(Assembler::carryClear, copy_tail);
9398
9399 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9400 jmp(done);
9401
9402 bind(reset_for_copy_tail);
9403 lea(src, Address(src, tmp5, Address::times_2));
9404 lea(dst, Address(dst, tmp5, Address::times_1));
9405 subptr(len, tmp5);
9406 jmp(copy_chars_loop);
9407
9408 bind(below_threshold);
9409 }
9410
9411 if (UseSSE42Intrinsics) {
9412 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9413
9414 // vectored compression
9415 testl(len, 0xfffffff8);
9416 jcc(Assembler::zero, copy_tail);
9417
9418 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9419 movdl(tmp1Reg, tmp5);
9420 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9421
9422 andl(len, 0xfffffff0);
9423 jccb(Assembler::zero, copy_16);
9424
9425 // compress 16 chars per iter
9426 pxor(tmp4Reg, tmp4Reg);
9427
9428 lea(src, Address(src, len, Address::times_2));
9429 lea(dst, Address(dst, len, Address::times_1));
9430 negptr(len);
9431
9432 bind(copy_32_loop);
9433 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9434 por(tmp4Reg, tmp2Reg);
9435 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9436 por(tmp4Reg, tmp3Reg);
9437 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9438 jccb(Assembler::notZero, reset_for_copy_tail);
9439 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9440 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9441 addptr(len, 16);
9442 jccb(Assembler::notZero, copy_32_loop);
9443
9444 // compress next vector of 8 chars (if any)
9445 bind(copy_16);
9446 // len = 0
9447 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9448 jccb(Assembler::zero, copy_tail_sse);
9449
9450 pxor(tmp3Reg, tmp3Reg);
9451
9452 movdqu(tmp2Reg, Address(src, 0));
9453 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9454 jccb(Assembler::notZero, reset_for_copy_tail);
9455 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9456 movq(Address(dst, 0), tmp2Reg);
9457 addptr(src, 16);
9458 addptr(dst, 8);
9459 jmpb(copy_tail_sse);
9460
9461 bind(reset_for_copy_tail);
9462 movl(tmp5, result);
9463 andl(tmp5, 0x0000000f);
9464 lea(src, Address(src, tmp5, Address::times_2));
9465 lea(dst, Address(dst, tmp5, Address::times_1));
9466 subptr(len, tmp5);
9467 jmpb(copy_chars_loop);
9468
9469 bind(copy_tail_sse);
9470 movl(len, result);
9471 andl(len, 0x00000007); // tail count (in chars)
9472 }
9473 // compress 1 char per iter
9474 bind(copy_tail);
9475 testl(len, len);
9476 jccb(Assembler::zero, done);
9477 lea(src, Address(src, len, Address::times_2));
9478 lea(dst, Address(dst, len, Address::times_1));
9479 negptr(len);
9480
9481 bind(copy_chars_loop);
9482 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9483 testl(tmp5, 0xff00); // check if Unicode char
9484 jccb(Assembler::notZero, reset_sp);
9485 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9486 increment(len);
9487 jccb(Assembler::notZero, copy_chars_loop);
9488
9489 // add len then return (len will be zero if compress succeeded, otherwise negative)
9490 bind(reset_sp);
9491 addl(result, len);
9492
9493 bind(done);
9494 }
9495
9496 // Inflate byte[] array to char[].
9497 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9498 // @IntrinsicCandidate
9499 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9500 // for (int i = 0; i < len; i++) {
9501 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9502 // }
9503 // }
9504 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9505 XMMRegister tmp1, Register tmp2, KRegister mask) {
9506 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9507 // rsi: src
9508 // rdi: dst
9509 // rdx: len
9510 // rcx: tmp2
9511
9512 // rsi holds start addr of source byte[] to be inflated
9513 // rdi holds start addr of destination char[]
9514 // rdx holds length
9515 assert_different_registers(src, dst, len, tmp2);
9516 movl(tmp2, len);
9517 if ((UseAVX > 2) && // AVX512
9518 VM_Version::supports_avx512vlbw() &&
9519 VM_Version::supports_bmi2()) {
9520
9521 Label copy_32_loop, copy_tail;
9522 Register tmp3_aliased = len;
9523
9524 // if length of the string is less than 16, handle it in an old fashioned way
9525 testl(len, -16);
9526 jcc(Assembler::zero, below_threshold);
9527
9528 testl(len, -1 * AVX3Threshold);
9529 jcc(Assembler::zero, avx3_threshold);
9530
9531 // In order to use only one arithmetic operation for the main loop we use
9532 // this pre-calculation
9533 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9534 andl(len, -32); // vector count
9535 jccb(Assembler::zero, copy_tail);
9536
9537 lea(src, Address(src, len, Address::times_1));
9538 lea(dst, Address(dst, len, Address::times_2));
9539 negptr(len);
9540
9541
9542 // inflate 32 chars per iter
9543 bind(copy_32_loop);
9544 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9545 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9546 addptr(len, 32);
9547 jcc(Assembler::notZero, copy_32_loop);
9548
9549 bind(copy_tail);
9550 // bail out when there is nothing to be done
9551 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9552 jcc(Assembler::zero, done);
9553
9554 // ~(~0 << length), where length is the # of remaining elements to process
9555 movl(tmp3_aliased, -1);
9556 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9557 notl(tmp3_aliased);
9558 kmovdl(mask, tmp3_aliased);
9559 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9560 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9561
9562 jmp(done);
9563 bind(avx3_threshold);
9564 }
9565 if (UseSSE42Intrinsics) {
9566 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9567
9568 if (UseAVX > 1) {
9569 andl(tmp2, (16 - 1));
9570 andl(len, -16);
9571 jccb(Assembler::zero, copy_new_tail);
9572 } else {
9573 andl(tmp2, 0x00000007); // tail count (in chars)
9574 andl(len, 0xfffffff8); // vector count (in chars)
9575 jccb(Assembler::zero, copy_tail);
9576 }
9577
9578 // vectored inflation
9579 lea(src, Address(src, len, Address::times_1));
9580 lea(dst, Address(dst, len, Address::times_2));
9581 negptr(len);
9582
9583 if (UseAVX > 1) {
9584 bind(copy_16_loop);
9585 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9586 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9587 addptr(len, 16);
9588 jcc(Assembler::notZero, copy_16_loop);
9589
9590 bind(below_threshold);
9591 bind(copy_new_tail);
9592 movl(len, tmp2);
9593 andl(tmp2, 0x00000007);
9594 andl(len, 0xFFFFFFF8);
9595 jccb(Assembler::zero, copy_tail);
9596
9597 pmovzxbw(tmp1, Address(src, 0));
9598 movdqu(Address(dst, 0), tmp1);
9599 addptr(src, 8);
9600 addptr(dst, 2 * 8);
9601
9602 jmp(copy_tail, true);
9603 }
9604
9605 // inflate 8 chars per iter
9606 bind(copy_8_loop);
9607 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9608 movdqu(Address(dst, len, Address::times_2), tmp1);
9609 addptr(len, 8);
9610 jcc(Assembler::notZero, copy_8_loop);
9611
9612 bind(copy_tail);
9613 movl(len, tmp2);
9614
9615 cmpl(len, 4);
9616 jccb(Assembler::less, copy_bytes);
9617
9618 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9619 pmovzxbw(tmp1, tmp1);
9620 movq(Address(dst, 0), tmp1);
9621 subptr(len, 4);
9622 addptr(src, 4);
9623 addptr(dst, 8);
9624
9625 bind(copy_bytes);
9626 } else {
9627 bind(below_threshold);
9628 }
9629
9630 testl(len, len);
9631 jccb(Assembler::zero, done);
9632 lea(src, Address(src, len, Address::times_1));
9633 lea(dst, Address(dst, len, Address::times_2));
9634 negptr(len);
9635
9636 // inflate 1 char per iter
9637 bind(copy_chars_loop);
9638 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9639 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9640 increment(len);
9641 jcc(Assembler::notZero, copy_chars_loop);
9642
9643 bind(done);
9644 }
9645
9646 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
9647 switch(type) {
9648 case T_BYTE:
9649 case T_BOOLEAN:
9650 evmovdqub(dst, kmask, src, merge, vector_len);
9651 break;
9652 case T_CHAR:
9653 case T_SHORT:
9654 evmovdquw(dst, kmask, src, merge, vector_len);
9655 break;
9656 case T_INT:
9657 case T_FLOAT:
9658 evmovdqul(dst, kmask, src, merge, vector_len);
9659 break;
9660 case T_LONG:
9661 case T_DOUBLE:
9662 evmovdquq(dst, kmask, src, merge, vector_len);
9663 break;
9664 default:
9665 fatal("Unexpected type argument %s", type2name(type));
9666 break;
9667 }
9668 }
9669
9670
9671 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9672 switch(type) {
9673 case T_BYTE:
9674 case T_BOOLEAN:
9675 evmovdqub(dst, kmask, src, merge, vector_len);
9676 break;
9677 case T_CHAR:
9678 case T_SHORT:
9679 evmovdquw(dst, kmask, src, merge, vector_len);
9680 break;
9681 case T_INT:
9682 case T_FLOAT:
9683 evmovdqul(dst, kmask, src, merge, vector_len);
9684 break;
9685 case T_LONG:
9686 case T_DOUBLE:
9687 evmovdquq(dst, kmask, src, merge, vector_len);
9688 break;
9689 default:
9690 fatal("Unexpected type argument %s", type2name(type));
9691 break;
9692 }
9693 }
9694
9695 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9696 switch(type) {
9697 case T_BYTE:
9698 case T_BOOLEAN:
9699 evmovdqub(dst, kmask, src, merge, vector_len);
9700 break;
9701 case T_CHAR:
9702 case T_SHORT:
9703 evmovdquw(dst, kmask, src, merge, vector_len);
9704 break;
9705 case T_INT:
9706 case T_FLOAT:
9707 evmovdqul(dst, kmask, src, merge, vector_len);
9708 break;
9709 case T_LONG:
9710 case T_DOUBLE:
9711 evmovdquq(dst, kmask, src, merge, vector_len);
9712 break;
9713 default:
9714 fatal("Unexpected type argument %s", type2name(type));
9715 break;
9716 }
9717 }
9718
9719 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9720 switch(masklen) {
9721 case 2:
9722 knotbl(dst, src);
9723 movl(rtmp, 3);
9724 kmovbl(ktmp, rtmp);
9725 kandbl(dst, ktmp, dst);
9726 break;
9727 case 4:
9728 knotbl(dst, src);
9729 movl(rtmp, 15);
9730 kmovbl(ktmp, rtmp);
9731 kandbl(dst, ktmp, dst);
9732 break;
9733 case 8:
9734 knotbl(dst, src);
9735 break;
9736 case 16:
9737 knotwl(dst, src);
9738 break;
9739 case 32:
9740 knotdl(dst, src);
9741 break;
9742 case 64:
9743 knotql(dst, src);
9744 break;
9745 default:
9746 fatal("Unexpected vector length %d", masklen);
9747 break;
9748 }
9749 }
9750
9751 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9752 switch(type) {
9753 case T_BOOLEAN:
9754 case T_BYTE:
9755 kandbl(dst, src1, src2);
9756 break;
9757 case T_CHAR:
9758 case T_SHORT:
9759 kandwl(dst, src1, src2);
9760 break;
9761 case T_INT:
9762 case T_FLOAT:
9763 kanddl(dst, src1, src2);
9764 break;
9765 case T_LONG:
9766 case T_DOUBLE:
9767 kandql(dst, src1, src2);
9768 break;
9769 default:
9770 fatal("Unexpected type argument %s", type2name(type));
9771 break;
9772 }
9773 }
9774
9775 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9776 switch(type) {
9777 case T_BOOLEAN:
9778 case T_BYTE:
9779 korbl(dst, src1, src2);
9780 break;
9781 case T_CHAR:
9782 case T_SHORT:
9783 korwl(dst, src1, src2);
9784 break;
9785 case T_INT:
9786 case T_FLOAT:
9787 kordl(dst, src1, src2);
9788 break;
9789 case T_LONG:
9790 case T_DOUBLE:
9791 korql(dst, src1, src2);
9792 break;
9793 default:
9794 fatal("Unexpected type argument %s", type2name(type));
9795 break;
9796 }
9797 }
9798
9799 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9800 switch(type) {
9801 case T_BOOLEAN:
9802 case T_BYTE:
9803 kxorbl(dst, src1, src2);
9804 break;
9805 case T_CHAR:
9806 case T_SHORT:
9807 kxorwl(dst, src1, src2);
9808 break;
9809 case T_INT:
9810 case T_FLOAT:
9811 kxordl(dst, src1, src2);
9812 break;
9813 case T_LONG:
9814 case T_DOUBLE:
9815 kxorql(dst, src1, src2);
9816 break;
9817 default:
9818 fatal("Unexpected type argument %s", type2name(type));
9819 break;
9820 }
9821 }
9822
9823 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9824 switch(type) {
9825 case T_BOOLEAN:
9826 case T_BYTE:
9827 evpermb(dst, mask, nds, src, merge, vector_len); break;
9828 case T_CHAR:
9829 case T_SHORT:
9830 evpermw(dst, mask, nds, src, merge, vector_len); break;
9831 case T_INT:
9832 case T_FLOAT:
9833 evpermd(dst, mask, nds, src, merge, vector_len); break;
9834 case T_LONG:
9835 case T_DOUBLE:
9836 evpermq(dst, mask, nds, src, merge, vector_len); break;
9837 default:
9838 fatal("Unexpected type argument %s", type2name(type)); break;
9839 }
9840 }
9841
9842 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9843 switch(type) {
9844 case T_BOOLEAN:
9845 case T_BYTE:
9846 evpermb(dst, mask, nds, src, merge, vector_len); break;
9847 case T_CHAR:
9848 case T_SHORT:
9849 evpermw(dst, mask, nds, src, merge, vector_len); break;
9850 case T_INT:
9851 case T_FLOAT:
9852 evpermd(dst, mask, nds, src, merge, vector_len); break;
9853 case T_LONG:
9854 case T_DOUBLE:
9855 evpermq(dst, mask, nds, src, merge, vector_len); break;
9856 default:
9857 fatal("Unexpected type argument %s", type2name(type)); break;
9858 }
9859 }
9860
9861 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9862 switch(type) {
9863 case T_BYTE:
9864 evpminub(dst, mask, nds, src, merge, vector_len); break;
9865 case T_SHORT:
9866 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9867 case T_INT:
9868 evpminud(dst, mask, nds, src, merge, vector_len); break;
9869 case T_LONG:
9870 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9871 default:
9872 fatal("Unexpected type argument %s", type2name(type)); break;
9873 }
9874 }
9875
9876 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9877 switch(type) {
9878 case T_BYTE:
9879 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9880 case T_SHORT:
9881 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9882 case T_INT:
9883 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9884 case T_LONG:
9885 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9886 default:
9887 fatal("Unexpected type argument %s", type2name(type)); break;
9888 }
9889 }
9890
9891 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9892 switch(type) {
9893 case T_BYTE:
9894 evpminub(dst, mask, nds, src, merge, vector_len); break;
9895 case T_SHORT:
9896 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9897 case T_INT:
9898 evpminud(dst, mask, nds, src, merge, vector_len); break;
9899 case T_LONG:
9900 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9901 default:
9902 fatal("Unexpected type argument %s", type2name(type)); break;
9903 }
9904 }
9905
9906 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9907 switch(type) {
9908 case T_BYTE:
9909 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9910 case T_SHORT:
9911 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9912 case T_INT:
9913 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9914 case T_LONG:
9915 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9916 default:
9917 fatal("Unexpected type argument %s", type2name(type)); break;
9918 }
9919 }
9920
9921 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9922 switch(type) {
9923 case T_BYTE:
9924 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9925 case T_SHORT:
9926 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9927 case T_INT:
9928 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9929 case T_LONG:
9930 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9931 default:
9932 fatal("Unexpected type argument %s", type2name(type)); break;
9933 }
9934 }
9935
9936 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9937 switch(type) {
9938 case T_BYTE:
9939 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9940 case T_SHORT:
9941 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9942 case T_INT:
9943 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9944 case T_LONG:
9945 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9946 default:
9947 fatal("Unexpected type argument %s", type2name(type)); break;
9948 }
9949 }
9950
9951 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9952 switch(type) {
9953 case T_BYTE:
9954 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9955 case T_SHORT:
9956 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9957 case T_INT:
9958 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9959 case T_LONG:
9960 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9961 default:
9962 fatal("Unexpected type argument %s", type2name(type)); break;
9963 }
9964 }
9965
9966 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9967 switch(type) {
9968 case T_BYTE:
9969 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9970 case T_SHORT:
9971 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9972 case T_INT:
9973 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9974 case T_LONG:
9975 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9976 default:
9977 fatal("Unexpected type argument %s", type2name(type)); break;
9978 }
9979 }
9980
9981 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9982 switch(type) {
9983 case T_INT:
9984 evpxord(dst, mask, nds, src, merge, vector_len); break;
9985 case T_LONG:
9986 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9987 default:
9988 fatal("Unexpected type argument %s", type2name(type)); break;
9989 }
9990 }
9991
9992 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9993 switch(type) {
9994 case T_INT:
9995 evpxord(dst, mask, nds, src, merge, vector_len); break;
9996 case T_LONG:
9997 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9998 default:
9999 fatal("Unexpected type argument %s", type2name(type)); break;
10000 }
10001 }
10002
10003 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10004 switch(type) {
10005 case T_INT:
10006 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10007 case T_LONG:
10008 evporq(dst, mask, nds, src, merge, vector_len); break;
10009 default:
10010 fatal("Unexpected type argument %s", type2name(type)); break;
10011 }
10012 }
10013
10014 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10015 switch(type) {
10016 case T_INT:
10017 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10018 case T_LONG:
10019 evporq(dst, mask, nds, src, merge, vector_len); break;
10020 default:
10021 fatal("Unexpected type argument %s", type2name(type)); break;
10022 }
10023 }
10024
10025 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10026 switch(type) {
10027 case T_INT:
10028 evpandd(dst, mask, nds, src, merge, vector_len); break;
10029 case T_LONG:
10030 evpandq(dst, mask, nds, src, merge, vector_len); break;
10031 default:
10032 fatal("Unexpected type argument %s", type2name(type)); break;
10033 }
10034 }
10035
10036 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10037 switch(type) {
10038 case T_INT:
10039 evpandd(dst, mask, nds, src, merge, vector_len); break;
10040 case T_LONG:
10041 evpandq(dst, mask, nds, src, merge, vector_len); break;
10042 default:
10043 fatal("Unexpected type argument %s", type2name(type)); break;
10044 }
10045 }
10046
10047 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
10048 switch(masklen) {
10049 case 8:
10050 kortestbl(src1, src2);
10051 break;
10052 case 16:
10053 kortestwl(src1, src2);
10054 break;
10055 case 32:
10056 kortestdl(src1, src2);
10057 break;
10058 case 64:
10059 kortestql(src1, src2);
10060 break;
10061 default:
10062 fatal("Unexpected mask length %d", masklen);
10063 break;
10064 }
10065 }
10066
10067
10068 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
10069 switch(masklen) {
10070 case 8:
10071 ktestbl(src1, src2);
10072 break;
10073 case 16:
10074 ktestwl(src1, src2);
10075 break;
10076 case 32:
10077 ktestdl(src1, src2);
10078 break;
10079 case 64:
10080 ktestql(src1, src2);
10081 break;
10082 default:
10083 fatal("Unexpected mask length %d", masklen);
10084 break;
10085 }
10086 }
10087
10088 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10089 switch(type) {
10090 case T_INT:
10091 evprold(dst, mask, src, shift, merge, vlen_enc); break;
10092 case T_LONG:
10093 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
10094 default:
10095 fatal("Unexpected type argument %s", type2name(type)); break;
10096 break;
10097 }
10098 }
10099
10100 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10101 switch(type) {
10102 case T_INT:
10103 evprord(dst, mask, src, shift, merge, vlen_enc); break;
10104 case T_LONG:
10105 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
10106 default:
10107 fatal("Unexpected type argument %s", type2name(type)); break;
10108 }
10109 }
10110
10111 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10112 switch(type) {
10113 case T_INT:
10114 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
10115 case T_LONG:
10116 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
10117 default:
10118 fatal("Unexpected type argument %s", type2name(type)); break;
10119 }
10120 }
10121
10122 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10123 switch(type) {
10124 case T_INT:
10125 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
10126 case T_LONG:
10127 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
10128 default:
10129 fatal("Unexpected type argument %s", type2name(type)); break;
10130 }
10131 }
10132
10133 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10134 assert(rscratch != noreg || always_reachable(src), "missing");
10135
10136 if (reachable(src)) {
10137 evpandq(dst, nds, as_Address(src), vector_len);
10138 } else {
10139 lea(rscratch, src);
10140 evpandq(dst, nds, Address(rscratch, 0), vector_len);
10141 }
10142 }
10143
10144 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
10145 assert(rscratch != noreg || always_reachable(src), "missing");
10146
10147 if (reachable(src)) {
10148 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
10149 } else {
10150 lea(rscratch, src);
10151 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
10152 }
10153 }
10154
10155 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10156 assert(rscratch != noreg || always_reachable(src), "missing");
10157
10158 if (reachable(src)) {
10159 evporq(dst, nds, as_Address(src), vector_len);
10160 } else {
10161 lea(rscratch, src);
10162 evporq(dst, nds, Address(rscratch, 0), vector_len);
10163 }
10164 }
10165
10166 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10167 assert(rscratch != noreg || always_reachable(src), "missing");
10168
10169 if (reachable(src)) {
10170 vpshufb(dst, nds, as_Address(src), vector_len);
10171 } else {
10172 lea(rscratch, src);
10173 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
10174 }
10175 }
10176
10177 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10178 assert(rscratch != noreg || always_reachable(src), "missing");
10179
10180 if (reachable(src)) {
10181 Assembler::vpor(dst, nds, as_Address(src), vector_len);
10182 } else {
10183 lea(rscratch, src);
10184 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
10185 }
10186 }
10187
10188 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
10189 assert(rscratch != noreg || always_reachable(src3), "missing");
10190
10191 if (reachable(src3)) {
10192 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
10193 } else {
10194 lea(rscratch, src3);
10195 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
10196 }
10197 }
10198
10199 #if COMPILER2_OR_JVMCI
10200
10201 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
10202 Register length, Register temp, int vec_enc) {
10203 // Computing mask for predicated vector store.
10204 movptr(temp, -1);
10205 bzhiq(temp, temp, length);
10206 kmov(mask, temp);
10207 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
10208 }
10209
10210 // Set memory operation for length "less than" 64 bytes.
10211 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
10212 XMMRegister xmm, KRegister mask, Register length,
10213 Register temp, bool use64byteVector) {
10214 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10215 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10216 if (!use64byteVector) {
10217 fill32(dst, disp, xmm);
10218 subptr(length, 32 >> shift);
10219 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
10220 } else {
10221 assert(MaxVectorSize == 64, "vector length != 64");
10222 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
10223 }
10224 }
10225
10226
10227 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
10228 XMMRegister xmm, KRegister mask, Register length,
10229 Register temp) {
10230 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10231 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10232 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
10233 }
10234
10235
10236 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
10237 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10238 vmovdqu(dst, xmm);
10239 }
10240
10241 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
10242 fill32(Address(dst, disp), xmm);
10243 }
10244
10245 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
10246 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10247 if (!use64byteVector) {
10248 fill32(dst, xmm);
10249 fill32(dst.plus_disp(32), xmm);
10250 } else {
10251 evmovdquq(dst, xmm, Assembler::AVX_512bit);
10252 }
10253 }
10254
10255 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
10256 fill64(Address(dst, disp), xmm, use64byteVector);
10257 }
10258
10259 #ifdef _LP64
10260 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
10261 Register count, Register rtmp, XMMRegister xtmp) {
10262 Label L_exit;
10263 Label L_fill_start;
10264 Label L_fill_64_bytes;
10265 Label L_fill_96_bytes;
10266 Label L_fill_128_bytes;
10267 Label L_fill_128_bytes_loop;
10268 Label L_fill_128_loop_header;
10269 Label L_fill_128_bytes_loop_header;
10270 Label L_fill_128_bytes_loop_pre_header;
10271 Label L_fill_zmm_sequence;
10272
10273 int shift = -1;
10274 int avx3threshold = VM_Version::avx3_threshold();
10275 switch(type) {
10276 case T_BYTE: shift = 0;
10277 break;
10278 case T_SHORT: shift = 1;
10279 break;
10280 case T_INT: shift = 2;
10281 break;
10282 /* Uncomment when LONG fill stubs are supported.
10283 case T_LONG: shift = 3;
10284 break;
10285 */
10286 default:
10287 fatal("Unhandled type: %s\n", type2name(type));
10288 }
10289
10290 if ((avx3threshold != 0) || (MaxVectorSize == 32)) {
10291
10292 if (MaxVectorSize == 64) {
10293 cmpq(count, avx3threshold >> shift);
10294 jcc(Assembler::greater, L_fill_zmm_sequence);
10295 }
10296
10297 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
10298
10299 bind(L_fill_start);
10300
10301 cmpq(count, 32 >> shift);
10302 jccb(Assembler::greater, L_fill_64_bytes);
10303 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
10304 jmp(L_exit);
10305
10306 bind(L_fill_64_bytes);
10307 cmpq(count, 64 >> shift);
10308 jccb(Assembler::greater, L_fill_96_bytes);
10309 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10310 jmp(L_exit);
10311
10312 bind(L_fill_96_bytes);
10313 cmpq(count, 96 >> shift);
10314 jccb(Assembler::greater, L_fill_128_bytes);
10315 fill64(to, 0, xtmp);
10316 subq(count, 64 >> shift);
10317 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10318 jmp(L_exit);
10319
10320 bind(L_fill_128_bytes);
10321 cmpq(count, 128 >> shift);
10322 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10323 fill64(to, 0, xtmp);
10324 fill32(to, 64, xtmp);
10325 subq(count, 96 >> shift);
10326 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10327 jmp(L_exit);
10328
10329 bind(L_fill_128_bytes_loop_pre_header);
10330 {
10331 mov(rtmp, to);
10332 andq(rtmp, 31);
10333 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10334 negq(rtmp);
10335 addq(rtmp, 32);
10336 mov64(r8, -1L);
10337 bzhiq(r8, r8, rtmp);
10338 kmovql(k2, r8);
10339 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10340 addq(to, rtmp);
10341 shrq(rtmp, shift);
10342 subq(count, rtmp);
10343 }
10344
10345 cmpq(count, 128 >> shift);
10346 jcc(Assembler::less, L_fill_start);
10347
10348 bind(L_fill_128_bytes_loop_header);
10349 subq(count, 128 >> shift);
10350
10351 align32();
10352 bind(L_fill_128_bytes_loop);
10353 fill64(to, 0, xtmp);
10354 fill64(to, 64, xtmp);
10355 addq(to, 128);
10356 subq(count, 128 >> shift);
10357 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10358
10359 addq(count, 128 >> shift);
10360 jcc(Assembler::zero, L_exit);
10361 jmp(L_fill_start);
10362 }
10363
10364 if (MaxVectorSize == 64) {
10365 // Sequence using 64 byte ZMM register.
10366 Label L_fill_128_bytes_zmm;
10367 Label L_fill_192_bytes_zmm;
10368 Label L_fill_192_bytes_loop_zmm;
10369 Label L_fill_192_bytes_loop_header_zmm;
10370 Label L_fill_192_bytes_loop_pre_header_zmm;
10371 Label L_fill_start_zmm_sequence;
10372
10373 bind(L_fill_zmm_sequence);
10374 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10375
10376 bind(L_fill_start_zmm_sequence);
10377 cmpq(count, 64 >> shift);
10378 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10379 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10380 jmp(L_exit);
10381
10382 bind(L_fill_128_bytes_zmm);
10383 cmpq(count, 128 >> shift);
10384 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10385 fill64(to, 0, xtmp, true);
10386 subq(count, 64 >> shift);
10387 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10388 jmp(L_exit);
10389
10390 bind(L_fill_192_bytes_zmm);
10391 cmpq(count, 192 >> shift);
10392 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10393 fill64(to, 0, xtmp, true);
10394 fill64(to, 64, xtmp, true);
10395 subq(count, 128 >> shift);
10396 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10397 jmp(L_exit);
10398
10399 bind(L_fill_192_bytes_loop_pre_header_zmm);
10400 {
10401 movq(rtmp, to);
10402 andq(rtmp, 63);
10403 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10404 negq(rtmp);
10405 addq(rtmp, 64);
10406 mov64(r8, -1L);
10407 bzhiq(r8, r8, rtmp);
10408 kmovql(k2, r8);
10409 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10410 addq(to, rtmp);
10411 shrq(rtmp, shift);
10412 subq(count, rtmp);
10413 }
10414
10415 cmpq(count, 192 >> shift);
10416 jcc(Assembler::less, L_fill_start_zmm_sequence);
10417
10418 bind(L_fill_192_bytes_loop_header_zmm);
10419 subq(count, 192 >> shift);
10420
10421 align32();
10422 bind(L_fill_192_bytes_loop_zmm);
10423 fill64(to, 0, xtmp, true);
10424 fill64(to, 64, xtmp, true);
10425 fill64(to, 128, xtmp, true);
10426 addq(to, 192);
10427 subq(count, 192 >> shift);
10428 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10429
10430 addq(count, 192 >> shift);
10431 jcc(Assembler::zero, L_exit);
10432 jmp(L_fill_start_zmm_sequence);
10433 }
10434 bind(L_exit);
10435 }
10436 #endif
10437 #endif //COMPILER2_OR_JVMCI
10438
10439
10440 #ifdef _LP64
10441 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10442 Label done;
10443 cvttss2sil(dst, src);
10444 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10445 cmpl(dst, 0x80000000); // float_sign_flip
10446 jccb(Assembler::notEqual, done);
10447 subptr(rsp, 8);
10448 movflt(Address(rsp, 0), src);
10449 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10450 pop(dst);
10451 bind(done);
10452 }
10453
10454 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10455 Label done;
10456 cvttsd2sil(dst, src);
10457 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10458 cmpl(dst, 0x80000000); // float_sign_flip
10459 jccb(Assembler::notEqual, done);
10460 subptr(rsp, 8);
10461 movdbl(Address(rsp, 0), src);
10462 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10463 pop(dst);
10464 bind(done);
10465 }
10466
10467 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10468 Label done;
10469 cvttss2siq(dst, src);
10470 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10471 jccb(Assembler::notEqual, done);
10472 subptr(rsp, 8);
10473 movflt(Address(rsp, 0), src);
10474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10475 pop(dst);
10476 bind(done);
10477 }
10478
10479 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10480 // Following code is line by line assembly translation rounding algorithm.
10481 // Please refer to java.lang.Math.round(float) algorithm for details.
10482 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10483 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10484 const int32_t FloatConsts_EXP_BIAS = 127;
10485 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10486 const int32_t MINUS_32 = 0xFFFFFFE0;
10487 Label L_special_case, L_block1, L_exit;
10488 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10489 movdl(dst, src);
10490 andl(dst, rtmp);
10491 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10492 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10493 subl(rtmp, dst);
10494 movl(rcx, rtmp);
10495 movl(dst, MINUS_32);
10496 testl(rtmp, dst);
10497 jccb(Assembler::notEqual, L_special_case);
10498 movdl(dst, src);
10499 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10500 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10501 movdl(rtmp, src);
10502 testl(rtmp, rtmp);
10503 jccb(Assembler::greaterEqual, L_block1);
10504 negl(dst);
10505 bind(L_block1);
10506 sarl(dst);
10507 addl(dst, 0x1);
10508 sarl(dst, 0x1);
10509 jmp(L_exit);
10510 bind(L_special_case);
10511 convert_f2i(dst, src);
10512 bind(L_exit);
10513 }
10514
10515 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10516 // Following code is line by line assembly translation rounding algorithm.
10517 // Please refer to java.lang.Math.round(double) algorithm for details.
10518 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10519 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10520 const int64_t DoubleConsts_EXP_BIAS = 1023;
10521 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10522 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10523 Label L_special_case, L_block1, L_exit;
10524 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10525 movq(dst, src);
10526 andq(dst, rtmp);
10527 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10528 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10529 subq(rtmp, dst);
10530 movq(rcx, rtmp);
10531 mov64(dst, MINUS_64);
10532 testq(rtmp, dst);
10533 jccb(Assembler::notEqual, L_special_case);
10534 movq(dst, src);
10535 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10536 andq(dst, rtmp);
10537 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10538 orq(dst, rtmp);
10539 movq(rtmp, src);
10540 testq(rtmp, rtmp);
10541 jccb(Assembler::greaterEqual, L_block1);
10542 negq(dst);
10543 bind(L_block1);
10544 sarq(dst);
10545 addq(dst, 0x1);
10546 sarq(dst, 0x1);
10547 jmp(L_exit);
10548 bind(L_special_case);
10549 convert_d2l(dst, src);
10550 bind(L_exit);
10551 }
10552
10553 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10554 Label done;
10555 cvttsd2siq(dst, src);
10556 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10557 jccb(Assembler::notEqual, done);
10558 subptr(rsp, 8);
10559 movdbl(Address(rsp, 0), src);
10560 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10561 pop(dst);
10562 bind(done);
10563 }
10564
10565 void MacroAssembler::cache_wb(Address line)
10566 {
10567 // 64 bit cpus always support clflush
10568 assert(VM_Version::supports_clflush(), "clflush should be available");
10569 bool optimized = VM_Version::supports_clflushopt();
10570 bool no_evict = VM_Version::supports_clwb();
10571
10572 // prefer clwb (writeback without evict) otherwise
10573 // prefer clflushopt (potentially parallel writeback with evict)
10574 // otherwise fallback on clflush (serial writeback with evict)
10575
10576 if (optimized) {
10577 if (no_evict) {
10578 clwb(line);
10579 } else {
10580 clflushopt(line);
10581 }
10582 } else {
10583 // no need for fence when using CLFLUSH
10584 clflush(line);
10585 }
10586 }
10587
10588 void MacroAssembler::cache_wbsync(bool is_pre)
10589 {
10590 assert(VM_Version::supports_clflush(), "clflush should be available");
10591 bool optimized = VM_Version::supports_clflushopt();
10592 bool no_evict = VM_Version::supports_clwb();
10593
10594 // pick the correct implementation
10595
10596 if (!is_pre && (optimized || no_evict)) {
10597 // need an sfence for post flush when using clflushopt or clwb
10598 // otherwise no no need for any synchroniaztion
10599
10600 sfence();
10601 }
10602 }
10603
10604 #endif // _LP64
10605
10606 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10607 switch (cond) {
10608 // Note some conditions are synonyms for others
10609 case Assembler::zero: return Assembler::notZero;
10610 case Assembler::notZero: return Assembler::zero;
10611 case Assembler::less: return Assembler::greaterEqual;
10612 case Assembler::lessEqual: return Assembler::greater;
10613 case Assembler::greater: return Assembler::lessEqual;
10614 case Assembler::greaterEqual: return Assembler::less;
10615 case Assembler::below: return Assembler::aboveEqual;
10616 case Assembler::belowEqual: return Assembler::above;
10617 case Assembler::above: return Assembler::belowEqual;
10618 case Assembler::aboveEqual: return Assembler::below;
10619 case Assembler::overflow: return Assembler::noOverflow;
10620 case Assembler::noOverflow: return Assembler::overflow;
10621 case Assembler::negative: return Assembler::positive;
10622 case Assembler::positive: return Assembler::negative;
10623 case Assembler::parity: return Assembler::noParity;
10624 case Assembler::noParity: return Assembler::parity;
10625 }
10626 ShouldNotReachHere(); return Assembler::overflow;
10627 }
10628
10629 // This is simply a call to Thread::current()
10630 void MacroAssembler::get_thread(Register thread) {
10631 if (thread != rax) {
10632 push(rax);
10633 }
10634 LP64_ONLY(push(rdi);)
10635 LP64_ONLY(push(rsi);)
10636 push(rdx);
10637 push(rcx);
10638 #ifdef _LP64
10639 push(r8);
10640 push(r9);
10641 push(r10);
10642 push(r11);
10643 #endif
10644
10645 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10646
10647 #ifdef _LP64
10648 pop(r11);
10649 pop(r10);
10650 pop(r9);
10651 pop(r8);
10652 #endif
10653 pop(rcx);
10654 pop(rdx);
10655 LP64_ONLY(pop(rsi);)
10656 LP64_ONLY(pop(rdi);)
10657 if (thread != rax) {
10658 mov(thread, rax);
10659 pop(rax);
10660 }
10661 }
10662
10663 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10664 Label L_stack_ok;
10665 if (bias == 0) {
10666 testptr(sp, 2 * wordSize - 1);
10667 } else {
10668 // lea(tmp, Address(rsp, bias);
10669 mov(tmp, sp);
10670 addptr(tmp, bias);
10671 testptr(tmp, 2 * wordSize - 1);
10672 }
10673 jcc(Assembler::equal, L_stack_ok);
10674 block_comment(msg);
10675 stop(msg);
10676 bind(L_stack_ok);
10677 }
10678
10679 // Implements lightweight-locking.
10680 //
10681 // obj: the object to be locked
10682 // reg_rax: rax
10683 // thread: the thread which attempts to lock obj
10684 // tmp: a temporary register
10685 void MacroAssembler::lightweight_lock(Register basic_lock, Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10686 assert(reg_rax == rax, "");
10687 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10688
10689 Label push;
10690 const Register top = tmp;
10691
10692 // Preload the markWord. It is important that this is the first
10693 // instruction emitted as it is part of C1's null check semantics.
10694 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10695
10696 if (UseObjectMonitorTable) {
10697 // Clear cache in case fast locking succeeds.
10698 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10699 }
10700
10701 // Load top.
10702 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10703
10704 // Check if the lock-stack is full.
10705 cmpl(top, LockStack::end_offset());
10706 jcc(Assembler::greaterEqual, slow);
10707
10708 // Check for recursion.
10709 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10710 jcc(Assembler::equal, push);
10711
10712 // Check header for monitor (0b10).
10713 testptr(reg_rax, markWord::monitor_value);
10714 jcc(Assembler::notZero, slow);
10715
10716 // Try to lock. Transition lock bits 0b01 => 0b00
10717 movptr(tmp, reg_rax);
10718 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10719 orptr(reg_rax, markWord::unlocked_value);
10720 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10721 jcc(Assembler::notEqual, slow);
10722
10723 // Restore top, CAS clobbers register.
10724 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10725
10726 bind(push);
10727 // After successful lock, push object on lock-stack.
10728 movptr(Address(thread, top), obj);
10729 incrementl(top, oopSize);
10730 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10731 }
10732
10733 // Implements lightweight-unlocking.
10734 //
10735 // obj: the object to be unlocked
10736 // reg_rax: rax
10737 // thread: the thread
10738 // tmp: a temporary register
10739 void MacroAssembler::lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10740 assert(reg_rax == rax, "");
10741 assert_different_registers(obj, reg_rax, thread, tmp);
10742
10743 Label unlocked, push_and_slow;
10744 const Register top = tmp;
10745
10746 // Check if obj is top of lock-stack.
10747 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10748 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10749 jcc(Assembler::notEqual, slow);
10750
10751 // Pop lock-stack.
10752 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10753 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10754
10755 // Check if recursive.
10756 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10757 jcc(Assembler::equal, unlocked);
10758
10759 // Not recursive. Check header for monitor (0b10).
10760 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10761 testptr(reg_rax, markWord::monitor_value);
10762 jcc(Assembler::notZero, push_and_slow);
10763
10764 #ifdef ASSERT
10765 // Check header not unlocked (0b01).
10766 Label not_unlocked;
10767 testptr(reg_rax, markWord::unlocked_value);
10768 jcc(Assembler::zero, not_unlocked);
10769 stop("lightweight_unlock already unlocked");
10770 bind(not_unlocked);
10771 #endif
10772
10773 // Try to unlock. Transition lock bits 0b00 => 0b01
10774 movptr(tmp, reg_rax);
10775 orptr(tmp, markWord::unlocked_value);
10776 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10777 jcc(Assembler::equal, unlocked);
10778
10779 bind(push_and_slow);
10780 // Restore lock-stack and handle the unlock in runtime.
10781 #ifdef ASSERT
10782 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10783 movptr(Address(thread, top), obj);
10784 #endif
10785 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10786 jmp(slow);
10787
10788 bind(unlocked);
10789 }
10790
10791 #ifdef _LP64
10792 // Saves legacy GPRs state on stack.
10793 void MacroAssembler::save_legacy_gprs() {
10794 subq(rsp, 16 * wordSize);
10795 movq(Address(rsp, 15 * wordSize), rax);
10796 movq(Address(rsp, 14 * wordSize), rcx);
10797 movq(Address(rsp, 13 * wordSize), rdx);
10798 movq(Address(rsp, 12 * wordSize), rbx);
10799 movq(Address(rsp, 10 * wordSize), rbp);
10800 movq(Address(rsp, 9 * wordSize), rsi);
10801 movq(Address(rsp, 8 * wordSize), rdi);
10802 movq(Address(rsp, 7 * wordSize), r8);
10803 movq(Address(rsp, 6 * wordSize), r9);
10804 movq(Address(rsp, 5 * wordSize), r10);
10805 movq(Address(rsp, 4 * wordSize), r11);
10806 movq(Address(rsp, 3 * wordSize), r12);
10807 movq(Address(rsp, 2 * wordSize), r13);
10808 movq(Address(rsp, wordSize), r14);
10809 movq(Address(rsp, 0), r15);
10810 }
10811
10812 // Resotres back legacy GPRs state from stack.
10813 void MacroAssembler::restore_legacy_gprs() {
10814 movq(r15, Address(rsp, 0));
10815 movq(r14, Address(rsp, wordSize));
10816 movq(r13, Address(rsp, 2 * wordSize));
10817 movq(r12, Address(rsp, 3 * wordSize));
10818 movq(r11, Address(rsp, 4 * wordSize));
10819 movq(r10, Address(rsp, 5 * wordSize));
10820 movq(r9, Address(rsp, 6 * wordSize));
10821 movq(r8, Address(rsp, 7 * wordSize));
10822 movq(rdi, Address(rsp, 8 * wordSize));
10823 movq(rsi, Address(rsp, 9 * wordSize));
10824 movq(rbp, Address(rsp, 10 * wordSize));
10825 movq(rbx, Address(rsp, 12 * wordSize));
10826 movq(rdx, Address(rsp, 13 * wordSize));
10827 movq(rcx, Address(rsp, 14 * wordSize));
10828 movq(rax, Address(rsp, 15 * wordSize));
10829 addq(rsp, 16 * wordSize);
10830 }
10831
10832 void MacroAssembler::load_aotrc_address(Register reg, address a) {
10833 #if INCLUDE_CDS
10834 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
10835 if (SCCache::is_on_for_write()) {
10836 // all aotrc field addresses should be registered in the SCC address table
10837 lea(reg, ExternalAddress(a));
10838 } else {
10839 mov64(reg, (uint64_t)a);
10840 }
10841 #else
10842 ShouldNotReachHere();
10843 #endif
10844 }
10845
10846 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10847 if (VM_Version::supports_apx_f()) {
10848 esetzucc(comparison, dst);
10849 } else {
10850 setb(comparison, dst);
10851 movzbl(dst, dst);
10852 }
10853 }
10854
10855 #endif