1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.hpp"
26 #include "asm/assembler.inline.hpp"
27 #include "code/SCCache.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "crc32c.h"
32 #include "gc/shared/barrierSet.hpp"
33 #include "gc/shared/barrierSetAssembler.hpp"
34 #include "gc/shared/collectedHeap.inline.hpp"
35 #include "gc/shared/tlab_globals.hpp"
36 #include "interpreter/bytecodeHistogram.hpp"
37 #include "interpreter/interpreter.hpp"
38 #include "interpreter/interpreterRuntime.hpp"
39 #include "jvm.h"
40 #include "memory/resourceArea.hpp"
41 #include "memory/universe.hpp"
42 #include "oops/accessDecorators.hpp"
43 #include "oops/compressedKlass.inline.hpp"
44 #include "oops/compressedOops.inline.hpp"
45 #include "oops/klass.inline.hpp"
46 #include "prims/methodHandles.hpp"
47 #include "runtime/continuation.hpp"
48 #include "runtime/interfaceSupport.inline.hpp"
49 #include "runtime/javaThread.hpp"
50 #include "runtime/jniHandles.hpp"
51 #include "runtime/objectMonitor.hpp"
52 #include "runtime/os.hpp"
53 #include "runtime/safepoint.hpp"
54 #include "runtime/safepointMechanism.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/checkedCast.hpp"
58 #include "utilities/macros.hpp"
59
60 #ifdef PRODUCT
61 #define BLOCK_COMMENT(str) /* nothing */
62 #define STOP(error) stop(error)
63 #else
64 #define BLOCK_COMMENT(str) block_comment(str)
65 #define STOP(error) block_comment(error); stop(error)
66 #endif
67
68 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
69
70 #ifdef ASSERT
71 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
72 #endif
73
74 static const Assembler::Condition reverse[] = {
75 Assembler::noOverflow /* overflow = 0x0 */ ,
76 Assembler::overflow /* noOverflow = 0x1 */ ,
77 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
78 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
79 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
80 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
81 Assembler::above /* belowEqual = 0x6 */ ,
82 Assembler::belowEqual /* above = 0x7 */ ,
83 Assembler::positive /* negative = 0x8 */ ,
84 Assembler::negative /* positive = 0x9 */ ,
85 Assembler::noParity /* parity = 0xa */ ,
86 Assembler::parity /* noParity = 0xb */ ,
87 Assembler::greaterEqual /* less = 0xc */ ,
88 Assembler::less /* greaterEqual = 0xd */ ,
89 Assembler::greater /* lessEqual = 0xe */ ,
90 Assembler::lessEqual /* greater = 0xf, */
91
92 };
93
94
95 // Implementation of MacroAssembler
96
97 // First all the versions that have distinct versions depending on 32/64 bit
98 // Unless the difference is trivial (1 line or so).
99
100 #ifndef _LP64
101
102 // 32bit versions
103
104 Address MacroAssembler::as_Address(AddressLiteral adr) {
105 return Address(adr.target(), adr.rspec());
106 }
107
108 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
109 assert(rscratch == noreg, "");
110 return Address::make_array(adr);
111 }
112
113 void MacroAssembler::call_VM_leaf_base(address entry_point,
114 int number_of_arguments) {
115 call(RuntimeAddress(entry_point));
116 increment(rsp, number_of_arguments * wordSize);
117 }
118
119 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
120 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
121 }
122
123
124 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
125 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
126 }
127
128 void MacroAssembler::cmpoop(Address src1, jobject obj) {
129 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
130 }
131
132 void MacroAssembler::cmpoop(Register src1, jobject obj, Register rscratch) {
133 assert(rscratch == noreg, "redundant");
134 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
135 }
136
137 void MacroAssembler::extend_sign(Register hi, Register lo) {
138 // According to Intel Doc. AP-526, "Integer Divide", p.18.
139 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
140 cdql();
141 } else {
142 movl(hi, lo);
143 sarl(hi, 31);
144 }
145 }
146
147 void MacroAssembler::jC2(Register tmp, Label& L) {
148 // set parity bit if FPU flag C2 is set (via rax)
149 save_rax(tmp);
150 fwait(); fnstsw_ax();
151 sahf();
152 restore_rax(tmp);
153 // branch
154 jcc(Assembler::parity, L);
155 }
156
157 void MacroAssembler::jnC2(Register tmp, Label& L) {
158 // set parity bit if FPU flag C2 is set (via rax)
159 save_rax(tmp);
160 fwait(); fnstsw_ax();
161 sahf();
162 restore_rax(tmp);
163 // branch
164 jcc(Assembler::noParity, L);
165 }
166
167 // 32bit can do a case table jump in one instruction but we no longer allow the base
168 // to be installed in the Address class
169 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
170 assert(rscratch == noreg, "not needed");
171 jmp(as_Address(entry, noreg));
172 }
173
174 // Note: y_lo will be destroyed
175 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
176 // Long compare for Java (semantics as described in JVM spec.)
177 Label high, low, done;
178
179 cmpl(x_hi, y_hi);
180 jcc(Assembler::less, low);
181 jcc(Assembler::greater, high);
182 // x_hi is the return register
183 xorl(x_hi, x_hi);
184 cmpl(x_lo, y_lo);
185 jcc(Assembler::below, low);
186 jcc(Assembler::equal, done);
187
188 bind(high);
189 xorl(x_hi, x_hi);
190 increment(x_hi);
191 jmp(done);
192
193 bind(low);
194 xorl(x_hi, x_hi);
195 decrementl(x_hi);
196
197 bind(done);
198 }
199
200 void MacroAssembler::lea(Register dst, AddressLiteral src) {
201 mov_literal32(dst, (int32_t)src.target(), src.rspec());
202 }
203
204 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
205 assert(rscratch == noreg, "not needed");
206
207 // leal(dst, as_Address(adr));
208 // see note in movl as to why we must use a move
209 mov_literal32(dst, (int32_t)adr.target(), adr.rspec());
210 }
211
212 void MacroAssembler::leave() {
213 mov(rsp, rbp);
214 pop(rbp);
215 }
216
217 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
218 // Multiplication of two Java long values stored on the stack
219 // as illustrated below. Result is in rdx:rax.
220 //
221 // rsp ---> [ ?? ] \ \
222 // .... | y_rsp_offset |
223 // [ y_lo ] / (in bytes) | x_rsp_offset
224 // [ y_hi ] | (in bytes)
225 // .... |
226 // [ x_lo ] /
227 // [ x_hi ]
228 // ....
229 //
230 // Basic idea: lo(result) = lo(x_lo * y_lo)
231 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
232 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
233 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
234 Label quick;
235 // load x_hi, y_hi and check if quick
236 // multiplication is possible
237 movl(rbx, x_hi);
238 movl(rcx, y_hi);
239 movl(rax, rbx);
240 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
241 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
242 // do full multiplication
243 // 1st step
244 mull(y_lo); // x_hi * y_lo
245 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
246 // 2nd step
247 movl(rax, x_lo);
248 mull(rcx); // x_lo * y_hi
249 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
250 // 3rd step
251 bind(quick); // note: rbx, = 0 if quick multiply!
252 movl(rax, x_lo);
253 mull(y_lo); // x_lo * y_lo
254 addl(rdx, rbx); // correct hi(x_lo * y_lo)
255 }
256
257 void MacroAssembler::lneg(Register hi, Register lo) {
258 negl(lo);
259 adcl(hi, 0);
260 negl(hi);
261 }
262
263 void MacroAssembler::lshl(Register hi, Register lo) {
264 // Java shift left long support (semantics as described in JVM spec., p.305)
265 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
266 // shift value is in rcx !
267 assert(hi != rcx, "must not use rcx");
268 assert(lo != rcx, "must not use rcx");
269 const Register s = rcx; // shift count
270 const int n = BitsPerWord;
271 Label L;
272 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
273 cmpl(s, n); // if (s < n)
274 jcc(Assembler::less, L); // else (s >= n)
275 movl(hi, lo); // x := x << n
276 xorl(lo, lo);
277 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
278 bind(L); // s (mod n) < n
279 shldl(hi, lo); // x := x << s
280 shll(lo);
281 }
282
283
284 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
285 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
286 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
287 assert(hi != rcx, "must not use rcx");
288 assert(lo != rcx, "must not use rcx");
289 const Register s = rcx; // shift count
290 const int n = BitsPerWord;
291 Label L;
292 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
293 cmpl(s, n); // if (s < n)
294 jcc(Assembler::less, L); // else (s >= n)
295 movl(lo, hi); // x := x >> n
296 if (sign_extension) sarl(hi, 31);
297 else xorl(hi, hi);
298 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
299 bind(L); // s (mod n) < n
300 shrdl(lo, hi); // x := x >> s
301 if (sign_extension) sarl(hi);
302 else shrl(hi);
303 }
304
305 void MacroAssembler::movoop(Register dst, jobject obj) {
306 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
307 }
308
309 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
310 assert(rscratch == noreg, "redundant");
311 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
312 }
313
314 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
315 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
316 }
317
318 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
319 assert(rscratch == noreg, "redundant");
320 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
321 }
322
323 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
324 if (src.is_lval()) {
325 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
326 } else {
327 movl(dst, as_Address(src));
328 }
329 }
330
331 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
332 assert(rscratch == noreg, "redundant");
333 movl(as_Address(dst, noreg), src);
334 }
335
336 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
337 movl(dst, as_Address(src, noreg));
338 }
339
340 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
341 assert(rscratch == noreg, "redundant");
342 movl(dst, src);
343 }
344
345 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
346 assert(rscratch == noreg, "redundant");
347 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
348 }
349
350 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
351 assert(rscratch == noreg, "redundant");
352 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
353 }
354
355 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
356 assert(rscratch == noreg, "redundant");
357 if (src.is_lval()) {
358 push_literal32((int32_t)src.target(), src.rspec());
359 } else {
360 pushl(as_Address(src));
361 }
362 }
363
364 static void pass_arg0(MacroAssembler* masm, Register arg) {
365 masm->push(arg);
366 }
367
368 static void pass_arg1(MacroAssembler* masm, Register arg) {
369 masm->push(arg);
370 }
371
372 static void pass_arg2(MacroAssembler* masm, Register arg) {
373 masm->push(arg);
374 }
375
376 static void pass_arg3(MacroAssembler* masm, Register arg) {
377 masm->push(arg);
378 }
379
380 #ifndef PRODUCT
381 extern "C" void findpc(intptr_t x);
382 #endif
383
384 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
385 // In order to get locks to work, we need to fake a in_VM state
386 JavaThread* thread = JavaThread::current();
387 JavaThreadState saved_state = thread->thread_state();
388 thread->set_thread_state(_thread_in_vm);
389 if (ShowMessageBoxOnError) {
390 JavaThread* thread = JavaThread::current();
391 JavaThreadState saved_state = thread->thread_state();
392 thread->set_thread_state(_thread_in_vm);
393 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
394 ttyLocker ttyl;
395 BytecodeCounter::print();
396 }
397 // To see where a verify_oop failed, get $ebx+40/X for this frame.
398 // This is the value of eip which points to where verify_oop will return.
399 if (os::message_box(msg, "Execution stopped, print registers?")) {
400 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
401 BREAKPOINT;
402 }
403 }
404 fatal("DEBUG MESSAGE: %s", msg);
405 }
406
407 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
408 ttyLocker ttyl;
409 DebuggingContext debugging{};
410 tty->print_cr("eip = 0x%08x", eip);
411 #ifndef PRODUCT
412 if ((WizardMode || Verbose) && PrintMiscellaneous) {
413 tty->cr();
414 findpc(eip);
415 tty->cr();
416 }
417 #endif
418 #define PRINT_REG(rax) \
419 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
420 PRINT_REG(rax);
421 PRINT_REG(rbx);
422 PRINT_REG(rcx);
423 PRINT_REG(rdx);
424 PRINT_REG(rdi);
425 PRINT_REG(rsi);
426 PRINT_REG(rbp);
427 PRINT_REG(rsp);
428 #undef PRINT_REG
429 // Print some words near top of staack.
430 int* dump_sp = (int*) rsp;
431 for (int col1 = 0; col1 < 8; col1++) {
432 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
433 os::print_location(tty, *dump_sp++);
434 }
435 for (int row = 0; row < 16; row++) {
436 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
437 for (int col = 0; col < 8; col++) {
438 tty->print(" 0x%08x", *dump_sp++);
439 }
440 tty->cr();
441 }
442 // Print some instructions around pc:
443 Disassembler::decode((address)eip-64, (address)eip);
444 tty->print_cr("--------");
445 Disassembler::decode((address)eip, (address)eip+32);
446 }
447
448 void MacroAssembler::stop(const char* msg) {
449 // push address of message
450 ExternalAddress message((address)msg);
451 pushptr(message.addr(), noreg);
452 { Label L; call(L, relocInfo::none); bind(L); } // push eip
453 pusha(); // push registers
454 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
455 hlt();
456 }
457
458 void MacroAssembler::warn(const char* msg) {
459 push_CPU_state();
460
461 // push address of message
462 ExternalAddress message((address)msg);
463 pushptr(message.addr(), noreg);
464
465 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
466 addl(rsp, wordSize); // discard argument
467 pop_CPU_state();
468 }
469
470 void MacroAssembler::print_state() {
471 { Label L; call(L, relocInfo::none); bind(L); } // push eip
472 pusha(); // push registers
473
474 push_CPU_state();
475 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
476 pop_CPU_state();
477
478 popa();
479 addl(rsp, wordSize);
480 }
481
482 #else // _LP64
483
484 // 64 bit versions
485
486 Address MacroAssembler::as_Address(AddressLiteral adr) {
487 // amd64 always does this as a pc-rel
488 // we can be absolute or disp based on the instruction type
489 // jmp/call are displacements others are absolute
490 assert(!adr.is_lval(), "must be rval");
491 assert(reachable(adr), "must be");
492 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
493
494 }
495
496 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
497 AddressLiteral base = adr.base();
498 lea(rscratch, base);
499 Address index = adr.index();
500 assert(index._disp == 0, "must not have disp"); // maybe it can?
501 Address array(rscratch, index._index, index._scale, index._disp);
502 return array;
503 }
504
505 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
506 Label L, E;
507
508 #ifdef _WIN64
509 // Windows always allocates space for it's register args
510 assert(num_args <= 4, "only register arguments supported");
511 subq(rsp, frame::arg_reg_save_area_bytes);
512 #endif
513
514 // Align stack if necessary
515 testl(rsp, 15);
516 jcc(Assembler::zero, L);
517
518 subq(rsp, 8);
519 call(RuntimeAddress(entry_point));
520 addq(rsp, 8);
521 jmp(E);
522
523 bind(L);
524 call(RuntimeAddress(entry_point));
525
526 bind(E);
527
528 #ifdef _WIN64
529 // restore stack pointer
530 addq(rsp, frame::arg_reg_save_area_bytes);
531 #endif
532 }
533
534 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
535 assert(!src2.is_lval(), "should use cmpptr");
536 assert(rscratch != noreg || always_reachable(src2), "missing");
537
538 if (reachable(src2)) {
539 cmpq(src1, as_Address(src2));
540 } else {
541 lea(rscratch, src2);
542 Assembler::cmpq(src1, Address(rscratch, 0));
543 }
544 }
545
546 int MacroAssembler::corrected_idivq(Register reg) {
547 // Full implementation of Java ldiv and lrem; checks for special
548 // case as described in JVM spec., p.243 & p.271. The function
549 // returns the (pc) offset of the idivl instruction - may be needed
550 // for implicit exceptions.
551 //
552 // normal case special case
553 //
554 // input : rax: dividend min_long
555 // reg: divisor (may not be eax/edx) -1
556 //
557 // output: rax: quotient (= rax idiv reg) min_long
558 // rdx: remainder (= rax irem reg) 0
559 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
560 static const int64_t min_long = 0x8000000000000000;
561 Label normal_case, special_case;
562
563 // check for special case
564 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
565 jcc(Assembler::notEqual, normal_case);
566 xorl(rdx, rdx); // prepare rdx for possible special case (where
567 // remainder = 0)
568 cmpq(reg, -1);
569 jcc(Assembler::equal, special_case);
570
571 // handle normal case
572 bind(normal_case);
573 cdqq();
574 int idivq_offset = offset();
575 idivq(reg);
576
577 // normal and special case exit
578 bind(special_case);
579
580 return idivq_offset;
581 }
582
583 void MacroAssembler::decrementq(Register reg, int value) {
584 if (value == min_jint) { subq(reg, value); return; }
585 if (value < 0) { incrementq(reg, -value); return; }
586 if (value == 0) { ; return; }
587 if (value == 1 && UseIncDec) { decq(reg) ; return; }
588 /* else */ { subq(reg, value) ; return; }
589 }
590
591 void MacroAssembler::decrementq(Address dst, int value) {
592 if (value == min_jint) { subq(dst, value); return; }
593 if (value < 0) { incrementq(dst, -value); return; }
594 if (value == 0) { ; return; }
595 if (value == 1 && UseIncDec) { decq(dst) ; return; }
596 /* else */ { subq(dst, value) ; return; }
597 }
598
599 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
600 assert(rscratch != noreg || always_reachable(dst), "missing");
601
602 if (reachable(dst)) {
603 incrementq(as_Address(dst));
604 } else {
605 lea(rscratch, dst);
606 incrementq(Address(rscratch, 0));
607 }
608 }
609
610 void MacroAssembler::incrementq(Register reg, int value) {
611 if (value == min_jint) { addq(reg, value); return; }
612 if (value < 0) { decrementq(reg, -value); return; }
613 if (value == 0) { ; return; }
614 if (value == 1 && UseIncDec) { incq(reg) ; return; }
615 /* else */ { addq(reg, value) ; return; }
616 }
617
618 void MacroAssembler::incrementq(Address dst, int value) {
619 if (value == min_jint) { addq(dst, value); return; }
620 if (value < 0) { decrementq(dst, -value); return; }
621 if (value == 0) { ; return; }
622 if (value == 1 && UseIncDec) { incq(dst) ; return; }
623 /* else */ { addq(dst, value) ; return; }
624 }
625
626 // 32bit can do a case table jump in one instruction but we no longer allow the base
627 // to be installed in the Address class
628 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
629 lea(rscratch, entry.base());
630 Address dispatch = entry.index();
631 assert(dispatch._base == noreg, "must be");
632 dispatch._base = rscratch;
633 jmp(dispatch);
634 }
635
636 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
637 ShouldNotReachHere(); // 64bit doesn't use two regs
638 cmpq(x_lo, y_lo);
639 }
640
641 void MacroAssembler::lea(Register dst, AddressLiteral src) {
642 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
643 }
644
645 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
646 lea(rscratch, adr);
647 movptr(dst, rscratch);
648 }
649
650 void MacroAssembler::leave() {
651 // %%% is this really better? Why not on 32bit too?
652 emit_int8((unsigned char)0xC9); // LEAVE
653 }
654
655 void MacroAssembler::lneg(Register hi, Register lo) {
656 ShouldNotReachHere(); // 64bit doesn't use two regs
657 negq(lo);
658 }
659
660 void MacroAssembler::movoop(Register dst, jobject obj) {
661 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
662 }
663
664 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
665 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
666 movq(dst, rscratch);
667 }
668
669 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
670 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
671 }
672
673 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
674 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
675 movq(dst, rscratch);
676 }
677
678 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
679 if (src.is_lval()) {
680 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
681 } else {
682 if (reachable(src)) {
683 movq(dst, as_Address(src));
684 } else {
685 lea(dst, src);
686 movq(dst, Address(dst, 0));
687 }
688 }
689 }
690
691 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
692 movq(as_Address(dst, rscratch), src);
693 }
694
695 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
696 movq(dst, as_Address(src, dst /*rscratch*/));
697 }
698
699 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
700 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
701 if (is_simm32(src)) {
702 movptr(dst, checked_cast<int32_t>(src));
703 } else {
704 mov64(rscratch, src);
705 movq(dst, rscratch);
706 }
707 }
708
709 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
710 movoop(rscratch, obj);
711 push(rscratch);
712 }
713
714 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
715 mov_metadata(rscratch, obj);
716 push(rscratch);
717 }
718
719 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
720 lea(rscratch, src);
721 if (src.is_lval()) {
722 push(rscratch);
723 } else {
724 pushq(Address(rscratch, 0));
725 }
726 }
727
728 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
729 reset_last_Java_frame(r15_thread, clear_fp);
730 }
731
732 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
733 Register last_java_fp,
734 address last_java_pc,
735 Register rscratch) {
736 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, last_java_pc, rscratch);
737 }
738
739 static void pass_arg0(MacroAssembler* masm, Register arg) {
740 if (c_rarg0 != arg ) {
741 masm->mov(c_rarg0, arg);
742 }
743 }
744
745 static void pass_arg1(MacroAssembler* masm, Register arg) {
746 if (c_rarg1 != arg ) {
747 masm->mov(c_rarg1, arg);
748 }
749 }
750
751 static void pass_arg2(MacroAssembler* masm, Register arg) {
752 if (c_rarg2 != arg ) {
753 masm->mov(c_rarg2, arg);
754 }
755 }
756
757 static void pass_arg3(MacroAssembler* masm, Register arg) {
758 if (c_rarg3 != arg ) {
759 masm->mov(c_rarg3, arg);
760 }
761 }
762
763 void MacroAssembler::stop(const char* msg) {
764 if (ShowMessageBoxOnError) {
765 address rip = pc();
766 pusha(); // get regs on stack
767 lea(c_rarg1, InternalAddress(rip));
768 movq(c_rarg2, rsp); // pass pointer to regs array
769 }
770 lea(c_rarg0, ExternalAddress((address) msg));
771 andq(rsp, -16); // align stack as required by ABI
772 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
773 hlt();
774 SCCache::add_C_string(msg);
775 }
776
777 void MacroAssembler::warn(const char* msg) {
778 push(rbp);
779 movq(rbp, rsp);
780 andq(rsp, -16); // align stack as required by push_CPU_state and call
781 push_CPU_state(); // keeps alignment at 16 bytes
782
783 #ifdef _WIN64
784 // Windows always allocates space for its register args
785 subq(rsp, frame::arg_reg_save_area_bytes);
786 #endif
787 lea(c_rarg0, ExternalAddress((address) msg));
788 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
789
790 #ifdef _WIN64
791 // restore stack pointer
792 addq(rsp, frame::arg_reg_save_area_bytes);
793 #endif
794 pop_CPU_state();
795 mov(rsp, rbp);
796 pop(rbp);
797 }
798
799 void MacroAssembler::print_state() {
800 address rip = pc();
801 pusha(); // get regs on stack
802 push(rbp);
803 movq(rbp, rsp);
804 andq(rsp, -16); // align stack as required by push_CPU_state and call
805 push_CPU_state(); // keeps alignment at 16 bytes
806
807 lea(c_rarg0, InternalAddress(rip));
808 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
809 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
810
811 pop_CPU_state();
812 mov(rsp, rbp);
813 pop(rbp);
814 popa();
815 }
816
817 #ifndef PRODUCT
818 extern "C" void findpc(intptr_t x);
819 #endif
820
821 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
822 // In order to get locks to work, we need to fake a in_VM state
823 if (ShowMessageBoxOnError) {
824 JavaThread* thread = JavaThread::current();
825 JavaThreadState saved_state = thread->thread_state();
826 thread->set_thread_state(_thread_in_vm);
827 #ifndef PRODUCT
828 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
829 ttyLocker ttyl;
830 BytecodeCounter::print();
831 }
832 #endif
833 // To see where a verify_oop failed, get $ebx+40/X for this frame.
834 // XXX correct this offset for amd64
835 // This is the value of eip which points to where verify_oop will return.
836 if (os::message_box(msg, "Execution stopped, print registers?")) {
837 print_state64(pc, regs);
838 BREAKPOINT;
839 }
840 }
841 fatal("DEBUG MESSAGE: %s", msg);
842 }
843
844 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
845 ttyLocker ttyl;
846 DebuggingContext debugging{};
847 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
848 #ifndef PRODUCT
849 tty->cr();
850 findpc(pc);
851 tty->cr();
852 #endif
853 #define PRINT_REG(rax, value) \
854 { tty->print("%s = ", #rax); os::print_location(tty, value); }
855 PRINT_REG(rax, regs[15]);
856 PRINT_REG(rbx, regs[12]);
857 PRINT_REG(rcx, regs[14]);
858 PRINT_REG(rdx, regs[13]);
859 PRINT_REG(rdi, regs[8]);
860 PRINT_REG(rsi, regs[9]);
861 PRINT_REG(rbp, regs[10]);
862 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
863 PRINT_REG(rsp, (intptr_t)(®s[16]));
864 PRINT_REG(r8 , regs[7]);
865 PRINT_REG(r9 , regs[6]);
866 PRINT_REG(r10, regs[5]);
867 PRINT_REG(r11, regs[4]);
868 PRINT_REG(r12, regs[3]);
869 PRINT_REG(r13, regs[2]);
870 PRINT_REG(r14, regs[1]);
871 PRINT_REG(r15, regs[0]);
872 #undef PRINT_REG
873 // Print some words near the top of the stack.
874 int64_t* rsp = ®s[16];
875 int64_t* dump_sp = rsp;
876 for (int col1 = 0; col1 < 8; col1++) {
877 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
878 os::print_location(tty, *dump_sp++);
879 }
880 for (int row = 0; row < 25; row++) {
881 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
882 for (int col = 0; col < 4; col++) {
883 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
884 }
885 tty->cr();
886 }
887 // Print some instructions around pc:
888 Disassembler::decode((address)pc-64, (address)pc);
889 tty->print_cr("--------");
890 Disassembler::decode((address)pc, (address)pc+32);
891 }
892
893 // The java_calling_convention describes stack locations as ideal slots on
894 // a frame with no abi restrictions. Since we must observe abi restrictions
895 // (like the placement of the register window) the slots must be biased by
896 // the following value.
897 static int reg2offset_in(VMReg r) {
898 // Account for saved rbp and return address
899 // This should really be in_preserve_stack_slots
900 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
901 }
902
903 static int reg2offset_out(VMReg r) {
904 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
905 }
906
907 // A long move
908 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
909
910 // The calling conventions assures us that each VMregpair is either
911 // all really one physical register or adjacent stack slots.
912
913 if (src.is_single_phys_reg() ) {
914 if (dst.is_single_phys_reg()) {
915 if (dst.first() != src.first()) {
916 mov(dst.first()->as_Register(), src.first()->as_Register());
917 }
918 } else {
919 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
920 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
921 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
922 }
923 } else if (dst.is_single_phys_reg()) {
924 assert(src.is_single_reg(), "not a stack pair");
925 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
926 } else {
927 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
928 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
929 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
930 }
931 }
932
933 // A double move
934 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
935
936 // The calling conventions assures us that each VMregpair is either
937 // all really one physical register or adjacent stack slots.
938
939 if (src.is_single_phys_reg() ) {
940 if (dst.is_single_phys_reg()) {
941 // In theory these overlap but the ordering is such that this is likely a nop
942 if ( src.first() != dst.first()) {
943 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
944 }
945 } else {
946 assert(dst.is_single_reg(), "not a stack pair");
947 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
948 }
949 } else if (dst.is_single_phys_reg()) {
950 assert(src.is_single_reg(), "not a stack pair");
951 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
952 } else {
953 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
954 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
955 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
956 }
957 }
958
959
960 // A float arg may have to do float reg int reg conversion
961 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
962 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
963
964 // The calling conventions assures us that each VMregpair is either
965 // all really one physical register or adjacent stack slots.
966
967 if (src.first()->is_stack()) {
968 if (dst.first()->is_stack()) {
969 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
970 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
971 } else {
972 // stack to reg
973 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
974 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
975 }
976 } else if (dst.first()->is_stack()) {
977 // reg to stack
978 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
979 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
980 } else {
981 // reg to reg
982 // In theory these overlap but the ordering is such that this is likely a nop
983 if ( src.first() != dst.first()) {
984 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
985 }
986 }
987 }
988
989 // On 64 bit we will store integer like items to the stack as
990 // 64 bits items (x86_32/64 abi) even though java would only store
991 // 32bits for a parameter. On 32bit it will simply be 32 bits
992 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
993 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
994 if (src.first()->is_stack()) {
995 if (dst.first()->is_stack()) {
996 // stack to stack
997 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
998 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
999 } else {
1000 // stack to reg
1001 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
1002 }
1003 } else if (dst.first()->is_stack()) {
1004 // reg to stack
1005 // Do we really have to sign extend???
1006 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1007 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
1008 } else {
1009 // Do we really have to sign extend???
1010 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1011 if (dst.first() != src.first()) {
1012 movq(dst.first()->as_Register(), src.first()->as_Register());
1013 }
1014 }
1015 }
1016
1017 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1018 if (src.first()->is_stack()) {
1019 if (dst.first()->is_stack()) {
1020 // stack to stack
1021 movq(rax, Address(rbp, reg2offset_in(src.first())));
1022 movq(Address(rsp, reg2offset_out(dst.first())), rax);
1023 } else {
1024 // stack to reg
1025 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1026 }
1027 } else if (dst.first()->is_stack()) {
1028 // reg to stack
1029 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1030 } else {
1031 if (dst.first() != src.first()) {
1032 movq(dst.first()->as_Register(), src.first()->as_Register());
1033 }
1034 }
1035 }
1036
1037 // An oop arg. Must pass a handle not the oop itself
1038 void MacroAssembler::object_move(OopMap* map,
1039 int oop_handle_offset,
1040 int framesize_in_slots,
1041 VMRegPair src,
1042 VMRegPair dst,
1043 bool is_receiver,
1044 int* receiver_offset) {
1045
1046 // must pass a handle. First figure out the location we use as a handle
1047
1048 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1049
1050 // See if oop is null if it is we need no handle
1051
1052 if (src.first()->is_stack()) {
1053
1054 // Oop is already on the stack as an argument
1055 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1056 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1057 if (is_receiver) {
1058 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1059 }
1060
1061 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
1062 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1063 // conditionally move a null
1064 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1065 } else {
1066
1067 // Oop is in a register we must store it to the space we reserve
1068 // on the stack for oop_handles and pass a handle if oop is non-null
1069
1070 const Register rOop = src.first()->as_Register();
1071 int oop_slot;
1072 if (rOop == j_rarg0)
1073 oop_slot = 0;
1074 else if (rOop == j_rarg1)
1075 oop_slot = 1;
1076 else if (rOop == j_rarg2)
1077 oop_slot = 2;
1078 else if (rOop == j_rarg3)
1079 oop_slot = 3;
1080 else if (rOop == j_rarg4)
1081 oop_slot = 4;
1082 else {
1083 assert(rOop == j_rarg5, "wrong register");
1084 oop_slot = 5;
1085 }
1086
1087 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1088 int offset = oop_slot*VMRegImpl::stack_slot_size;
1089
1090 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1091 // Store oop in handle area, may be null
1092 movptr(Address(rsp, offset), rOop);
1093 if (is_receiver) {
1094 *receiver_offset = offset;
1095 }
1096
1097 cmpptr(rOop, NULL_WORD);
1098 lea(rHandle, Address(rsp, offset));
1099 // conditionally move a null from the handle area where it was just stored
1100 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1101 }
1102
1103 // If arg is on the stack then place it otherwise it is already in correct reg.
1104 if (dst.first()->is_stack()) {
1105 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1106 }
1107 }
1108
1109 #endif // _LP64
1110
1111 // Now versions that are common to 32/64 bit
1112
1113 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1114 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1115 }
1116
1117 void MacroAssembler::addptr(Register dst, Register src) {
1118 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1119 }
1120
1121 void MacroAssembler::addptr(Address dst, Register src) {
1122 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1123 }
1124
1125 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1126 assert(rscratch != noreg || always_reachable(src), "missing");
1127
1128 if (reachable(src)) {
1129 Assembler::addsd(dst, as_Address(src));
1130 } else {
1131 lea(rscratch, src);
1132 Assembler::addsd(dst, Address(rscratch, 0));
1133 }
1134 }
1135
1136 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1137 assert(rscratch != noreg || always_reachable(src), "missing");
1138
1139 if (reachable(src)) {
1140 addss(dst, as_Address(src));
1141 } else {
1142 lea(rscratch, src);
1143 addss(dst, Address(rscratch, 0));
1144 }
1145 }
1146
1147 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1148 assert(rscratch != noreg || always_reachable(src), "missing");
1149
1150 if (reachable(src)) {
1151 Assembler::addpd(dst, as_Address(src));
1152 } else {
1153 lea(rscratch, src);
1154 Assembler::addpd(dst, Address(rscratch, 0));
1155 }
1156 }
1157
1158 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
1159 // Stub code is generated once and never copied.
1160 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1161 void MacroAssembler::align64() {
1162 align(64, (uint)(uintptr_t)pc());
1163 }
1164
1165 void MacroAssembler::align32() {
1166 align(32, (uint)(uintptr_t)pc());
1167 }
1168
1169 void MacroAssembler::align(uint modulus) {
1170 // 8273459: Ensure alignment is possible with current segment alignment
1171 assert(modulus <= (uintx)CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1172 align(modulus, offset());
1173 }
1174
1175 void MacroAssembler::align(uint modulus, uint target) {
1176 if (target % modulus != 0) {
1177 nop(modulus - (target % modulus));
1178 }
1179 }
1180
1181 void MacroAssembler::push_f(XMMRegister r) {
1182 subptr(rsp, wordSize);
1183 movflt(Address(rsp, 0), r);
1184 }
1185
1186 void MacroAssembler::pop_f(XMMRegister r) {
1187 movflt(r, Address(rsp, 0));
1188 addptr(rsp, wordSize);
1189 }
1190
1191 void MacroAssembler::push_d(XMMRegister r) {
1192 subptr(rsp, 2 * wordSize);
1193 movdbl(Address(rsp, 0), r);
1194 }
1195
1196 void MacroAssembler::pop_d(XMMRegister r) {
1197 movdbl(r, Address(rsp, 0));
1198 addptr(rsp, 2 * Interpreter::stackElementSize);
1199 }
1200
1201 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1202 // Used in sign-masking with aligned address.
1203 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1204 assert(rscratch != noreg || always_reachable(src), "missing");
1205
1206 if (UseAVX > 2 &&
1207 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
1208 (dst->encoding() >= 16)) {
1209 vpand(dst, dst, src, AVX_512bit, rscratch);
1210 } else if (reachable(src)) {
1211 Assembler::andpd(dst, as_Address(src));
1212 } else {
1213 lea(rscratch, src);
1214 Assembler::andpd(dst, Address(rscratch, 0));
1215 }
1216 }
1217
1218 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
1219 // Used in sign-masking with aligned address.
1220 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1221 assert(rscratch != noreg || always_reachable(src), "missing");
1222
1223 if (reachable(src)) {
1224 Assembler::andps(dst, as_Address(src));
1225 } else {
1226 lea(rscratch, src);
1227 Assembler::andps(dst, Address(rscratch, 0));
1228 }
1229 }
1230
1231 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1232 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1233 }
1234
1235 #ifdef _LP64
1236 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
1237 assert(rscratch != noreg || always_reachable(src), "missing");
1238
1239 if (reachable(src)) {
1240 andq(dst, as_Address(src));
1241 } else {
1242 lea(rscratch, src);
1243 andq(dst, Address(rscratch, 0));
1244 }
1245 }
1246 #endif
1247
1248 void MacroAssembler::atomic_incl(Address counter_addr) {
1249 lock();
1250 incrementl(counter_addr);
1251 }
1252
1253 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
1254 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1255
1256 if (reachable(counter_addr)) {
1257 atomic_incl(as_Address(counter_addr));
1258 } else {
1259 lea(rscratch, counter_addr);
1260 atomic_incl(Address(rscratch, 0));
1261 }
1262 }
1263
1264 #ifdef _LP64
1265 void MacroAssembler::atomic_incq(Address counter_addr) {
1266 lock();
1267 incrementq(counter_addr);
1268 }
1269
1270 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
1271 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1272
1273 if (reachable(counter_addr)) {
1274 atomic_incq(as_Address(counter_addr));
1275 } else {
1276 lea(rscratch, counter_addr);
1277 atomic_incq(Address(rscratch, 0));
1278 }
1279 }
1280 #endif
1281
1282 // Writes to stack successive pages until offset reached to check for
1283 // stack overflow + shadow pages. This clobbers tmp.
1284 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1285 movptr(tmp, rsp);
1286 // Bang stack for total size given plus shadow page size.
1287 // Bang one page at a time because large size can bang beyond yellow and
1288 // red zones.
1289 Label loop;
1290 bind(loop);
1291 movl(Address(tmp, (-(int)os::vm_page_size())), size );
1292 subptr(tmp, (int)os::vm_page_size());
1293 subl(size, (int)os::vm_page_size());
1294 jcc(Assembler::greater, loop);
1295
1296 // Bang down shadow pages too.
1297 // At this point, (tmp-0) is the last address touched, so don't
1298 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1299 // was post-decremented.) Skip this address by starting at i=1, and
1300 // touch a few more pages below. N.B. It is important to touch all
1301 // the way down including all pages in the shadow zone.
1302 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
1303 // this could be any sized move but this is can be a debugging crumb
1304 // so the bigger the better.
1305 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
1306 }
1307 }
1308
1309 void MacroAssembler::reserved_stack_check() {
1310 // testing if reserved zone needs to be enabled
1311 Label no_reserved_zone_enabling;
1312 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1313 NOT_LP64(get_thread(rsi);)
1314
1315 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1316 jcc(Assembler::below, no_reserved_zone_enabling);
1317
1318 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1319 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
1320 should_not_reach_here();
1321
1322 bind(no_reserved_zone_enabling);
1323 }
1324
1325 void MacroAssembler::c2bool(Register x) {
1326 // implements x == 0 ? 0 : 1
1327 // note: must only look at least-significant byte of x
1328 // since C-style booleans are stored in one byte
1329 // only! (was bug)
1330 andl(x, 0xFF);
1331 setb(Assembler::notZero, x);
1332 }
1333
1334 // Wouldn't need if AddressLiteral version had new name
1335 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1336 Assembler::call(L, rtype);
1337 }
1338
1339 void MacroAssembler::call(Register entry) {
1340 Assembler::call(entry);
1341 }
1342
1343 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
1344 assert(rscratch != noreg || always_reachable(entry), "missing");
1345
1346 if (reachable(entry)) {
1347 Assembler::call_literal(entry.target(), entry.rspec());
1348 } else {
1349 lea(rscratch, entry);
1350 Assembler::call(rscratch);
1351 }
1352 }
1353
1354 void MacroAssembler::ic_call(address entry, jint method_index) {
1355 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1356 #ifdef _LP64
1357 // Needs full 64-bit immediate for later patching.
1358 mov64(rax, (int64_t)Universe::non_oop_word());
1359 #else
1360 movptr(rax, (intptr_t)Universe::non_oop_word());
1361 #endif
1362 call(AddressLiteral(entry, rh));
1363 }
1364
1365 int MacroAssembler::ic_check_size() {
1366 return
1367 LP64_ONLY(UseCompactObjectHeaders ? 17 : 14) NOT_LP64(12);
1368 }
1369
1370 int MacroAssembler::ic_check(int end_alignment) {
1371 Register receiver = LP64_ONLY(j_rarg0) NOT_LP64(rcx);
1372 Register data = rax;
1373 Register temp = LP64_ONLY(rscratch1) NOT_LP64(rbx);
1374
1375 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1376 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1377 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1378 // before the inline cache check here, and not after
1379 align(end_alignment, offset() + ic_check_size());
1380
1381 int uep_offset = offset();
1382
1383 #ifdef _LP64
1384 if (UseCompactObjectHeaders) {
1385 load_narrow_klass_compact(temp, receiver);
1386 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1387 } else
1388 #endif
1389 if (UseCompressedClassPointers) {
1390 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1391 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1392 } else {
1393 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1394 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
1395 }
1396
1397 // if inline cache check fails, then jump to runtime routine
1398 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1399 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
1400
1401 return uep_offset;
1402 }
1403
1404 void MacroAssembler::emit_static_call_stub() {
1405 // Static stub relocation also tags the Method* in the code-stream.
1406 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1407 // This is recognized as unresolved by relocs/nativeinst/ic code.
1408 jump(RuntimeAddress(pc()));
1409 }
1410
1411 // Implementation of call_VM versions
1412
1413 void MacroAssembler::call_VM(Register oop_result,
1414 address entry_point,
1415 bool check_exceptions) {
1416 Label C, E;
1417 call(C, relocInfo::none);
1418 jmp(E);
1419
1420 bind(C);
1421 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1422 ret(0);
1423
1424 bind(E);
1425 }
1426
1427 void MacroAssembler::call_VM(Register oop_result,
1428 address entry_point,
1429 Register arg_1,
1430 bool check_exceptions) {
1431 Label C, E;
1432 call(C, relocInfo::none);
1433 jmp(E);
1434
1435 bind(C);
1436 pass_arg1(this, arg_1);
1437 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1438 ret(0);
1439
1440 bind(E);
1441 }
1442
1443 void MacroAssembler::call_VM(Register oop_result,
1444 address entry_point,
1445 Register arg_1,
1446 Register arg_2,
1447 bool check_exceptions) {
1448 Label C, E;
1449 call(C, relocInfo::none);
1450 jmp(E);
1451
1452 bind(C);
1453
1454 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1455
1456 pass_arg2(this, arg_2);
1457 pass_arg1(this, arg_1);
1458 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1459 ret(0);
1460
1461 bind(E);
1462 }
1463
1464 void MacroAssembler::call_VM(Register oop_result,
1465 address entry_point,
1466 Register arg_1,
1467 Register arg_2,
1468 Register arg_3,
1469 bool check_exceptions) {
1470 Label C, E;
1471 call(C, relocInfo::none);
1472 jmp(E);
1473
1474 bind(C);
1475
1476 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1477 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1478 pass_arg3(this, arg_3);
1479 pass_arg2(this, arg_2);
1480 pass_arg1(this, arg_1);
1481 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1482 ret(0);
1483
1484 bind(E);
1485 }
1486
1487 void MacroAssembler::call_VM(Register oop_result,
1488 Register last_java_sp,
1489 address entry_point,
1490 int number_of_arguments,
1491 bool check_exceptions) {
1492 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1493 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1494 }
1495
1496 void MacroAssembler::call_VM(Register oop_result,
1497 Register last_java_sp,
1498 address entry_point,
1499 Register arg_1,
1500 bool check_exceptions) {
1501 pass_arg1(this, arg_1);
1502 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1503 }
1504
1505 void MacroAssembler::call_VM(Register oop_result,
1506 Register last_java_sp,
1507 address entry_point,
1508 Register arg_1,
1509 Register arg_2,
1510 bool check_exceptions) {
1511
1512 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1513 pass_arg2(this, arg_2);
1514 pass_arg1(this, arg_1);
1515 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1516 }
1517
1518 void MacroAssembler::call_VM(Register oop_result,
1519 Register last_java_sp,
1520 address entry_point,
1521 Register arg_1,
1522 Register arg_2,
1523 Register arg_3,
1524 bool check_exceptions) {
1525 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1526 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1527 pass_arg3(this, arg_3);
1528 pass_arg2(this, arg_2);
1529 pass_arg1(this, arg_1);
1530 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1531 }
1532
1533 void MacroAssembler::super_call_VM(Register oop_result,
1534 Register last_java_sp,
1535 address entry_point,
1536 int number_of_arguments,
1537 bool check_exceptions) {
1538 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1539 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1540 }
1541
1542 void MacroAssembler::super_call_VM(Register oop_result,
1543 Register last_java_sp,
1544 address entry_point,
1545 Register arg_1,
1546 bool check_exceptions) {
1547 pass_arg1(this, arg_1);
1548 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1549 }
1550
1551 void MacroAssembler::super_call_VM(Register oop_result,
1552 Register last_java_sp,
1553 address entry_point,
1554 Register arg_1,
1555 Register arg_2,
1556 bool check_exceptions) {
1557
1558 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1559 pass_arg2(this, arg_2);
1560 pass_arg1(this, arg_1);
1561 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1562 }
1563
1564 void MacroAssembler::super_call_VM(Register oop_result,
1565 Register last_java_sp,
1566 address entry_point,
1567 Register arg_1,
1568 Register arg_2,
1569 Register arg_3,
1570 bool check_exceptions) {
1571 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1572 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1573 pass_arg3(this, arg_3);
1574 pass_arg2(this, arg_2);
1575 pass_arg1(this, arg_1);
1576 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1577 }
1578
1579 void MacroAssembler::call_VM_base(Register oop_result,
1580 Register java_thread,
1581 Register last_java_sp,
1582 address entry_point,
1583 int number_of_arguments,
1584 bool check_exceptions) {
1585 // determine java_thread register
1586 if (!java_thread->is_valid()) {
1587 #ifdef _LP64
1588 java_thread = r15_thread;
1589 #else
1590 java_thread = rdi;
1591 get_thread(java_thread);
1592 #endif // LP64
1593 }
1594 // determine last_java_sp register
1595 if (!last_java_sp->is_valid()) {
1596 last_java_sp = rsp;
1597 }
1598 // debugging support
1599 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1600 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1601 #ifdef ASSERT
1602 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1603 // r12 is the heapbase.
1604 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1605 #endif // ASSERT
1606
1607 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1608 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1609
1610 // push java thread (becomes first argument of C function)
1611
1612 NOT_LP64(push(java_thread); number_of_arguments++);
1613 LP64_ONLY(mov(c_rarg0, r15_thread));
1614
1615 // set last Java frame before call
1616 assert(last_java_sp != rbp, "can't use ebp/rbp");
1617
1618 // Only interpreter should have to set fp
1619 set_last_Java_frame(java_thread, last_java_sp, rbp, nullptr, rscratch1);
1620
1621 // do the call, remove parameters
1622 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1623
1624 // restore the thread (cannot use the pushed argument since arguments
1625 // may be overwritten by C code generated by an optimizing compiler);
1626 // however can use the register value directly if it is callee saved.
1627 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1628 // rdi & rsi (also r15) are callee saved -> nothing to do
1629 #ifdef ASSERT
1630 guarantee(java_thread != rax, "change this code");
1631 push(rax);
1632 { Label L;
1633 get_thread(rax);
1634 cmpptr(java_thread, rax);
1635 jcc(Assembler::equal, L);
1636 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1637 bind(L);
1638 }
1639 pop(rax);
1640 #endif
1641 } else {
1642 get_thread(java_thread);
1643 }
1644 // reset last Java frame
1645 // Only interpreter should have to clear fp
1646 reset_last_Java_frame(java_thread, true);
1647
1648 // C++ interp handles this in the interpreter
1649 check_and_handle_popframe(java_thread);
1650 check_and_handle_earlyret(java_thread);
1651
1652 if (check_exceptions) {
1653 // check for pending exceptions (java_thread is set upon return)
1654 cmpptr(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
1655 #ifndef _LP64
1656 jump_cc(Assembler::notEqual,
1657 RuntimeAddress(StubRoutines::forward_exception_entry()));
1658 #else
1659 // This used to conditionally jump to forward_exception however it is
1660 // possible if we relocate that the branch will not reach. So we must jump
1661 // around so we can always reach
1662
1663 Label ok;
1664 jcc(Assembler::equal, ok);
1665 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1666 bind(ok);
1667 #endif // LP64
1668 }
1669
1670 // get oop result if there is one and reset the value in the thread
1671 if (oop_result->is_valid()) {
1672 get_vm_result(oop_result, java_thread);
1673 }
1674 }
1675
1676 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1677
1678 // Calculate the value for last_Java_sp
1679 // somewhat subtle. call_VM does an intermediate call
1680 // which places a return address on the stack just under the
1681 // stack pointer as the user finished with it. This allows
1682 // use to retrieve last_Java_pc from last_Java_sp[-1].
1683 // On 32bit we then have to push additional args on the stack to accomplish
1684 // the actual requested call. On 64bit call_VM only can use register args
1685 // so the only extra space is the return address that call_VM created.
1686 // This hopefully explains the calculations here.
1687
1688 #ifdef _LP64
1689 // We've pushed one address, correct last_Java_sp
1690 lea(rax, Address(rsp, wordSize));
1691 #else
1692 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1693 #endif // LP64
1694
1695 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1696
1697 }
1698
1699 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1700 void MacroAssembler::call_VM_leaf0(address entry_point) {
1701 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1702 }
1703
1704 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1705 call_VM_leaf_base(entry_point, number_of_arguments);
1706 }
1707
1708 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1709 pass_arg0(this, arg_0);
1710 call_VM_leaf(entry_point, 1);
1711 }
1712
1713 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1714
1715 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1716 pass_arg1(this, arg_1);
1717 pass_arg0(this, arg_0);
1718 call_VM_leaf(entry_point, 2);
1719 }
1720
1721 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1722 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1723 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1724 pass_arg2(this, arg_2);
1725 pass_arg1(this, arg_1);
1726 pass_arg0(this, arg_0);
1727 call_VM_leaf(entry_point, 3);
1728 }
1729
1730 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1731 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1732 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1733 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1734 pass_arg3(this, arg_3);
1735 pass_arg2(this, arg_2);
1736 pass_arg1(this, arg_1);
1737 pass_arg0(this, arg_0);
1738 call_VM_leaf(entry_point, 3);
1739 }
1740
1741 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1742 pass_arg0(this, arg_0);
1743 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1744 }
1745
1746 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1747 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1748 pass_arg1(this, arg_1);
1749 pass_arg0(this, arg_0);
1750 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1751 }
1752
1753 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1754 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1755 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1756 pass_arg2(this, arg_2);
1757 pass_arg1(this, arg_1);
1758 pass_arg0(this, arg_0);
1759 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1760 }
1761
1762 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1763 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1764 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1765 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1766 pass_arg3(this, arg_3);
1767 pass_arg2(this, arg_2);
1768 pass_arg1(this, arg_1);
1769 pass_arg0(this, arg_0);
1770 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1771 }
1772
1773 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1774 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1775 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1776 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1777 }
1778
1779 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1780 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1781 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1782 }
1783
1784 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1785 }
1786
1787 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1788 }
1789
1790 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1791 assert(rscratch != noreg || always_reachable(src1), "missing");
1792
1793 if (reachable(src1)) {
1794 cmpl(as_Address(src1), imm);
1795 } else {
1796 lea(rscratch, src1);
1797 cmpl(Address(rscratch, 0), imm);
1798 }
1799 }
1800
1801 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1802 assert(!src2.is_lval(), "use cmpptr");
1803 assert(rscratch != noreg || always_reachable(src2), "missing");
1804
1805 if (reachable(src2)) {
1806 cmpl(src1, as_Address(src2));
1807 } else {
1808 lea(rscratch, src2);
1809 cmpl(src1, Address(rscratch, 0));
1810 }
1811 }
1812
1813 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1814 Assembler::cmpl(src1, imm);
1815 }
1816
1817 void MacroAssembler::cmp32(Register src1, Address src2) {
1818 Assembler::cmpl(src1, src2);
1819 }
1820
1821 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1822 ucomisd(opr1, opr2);
1823
1824 Label L;
1825 if (unordered_is_less) {
1826 movl(dst, -1);
1827 jcc(Assembler::parity, L);
1828 jcc(Assembler::below , L);
1829 movl(dst, 0);
1830 jcc(Assembler::equal , L);
1831 increment(dst);
1832 } else { // unordered is greater
1833 movl(dst, 1);
1834 jcc(Assembler::parity, L);
1835 jcc(Assembler::above , L);
1836 movl(dst, 0);
1837 jcc(Assembler::equal , L);
1838 decrementl(dst);
1839 }
1840 bind(L);
1841 }
1842
1843 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1844 ucomiss(opr1, opr2);
1845
1846 Label L;
1847 if (unordered_is_less) {
1848 movl(dst, -1);
1849 jcc(Assembler::parity, L);
1850 jcc(Assembler::below , L);
1851 movl(dst, 0);
1852 jcc(Assembler::equal , L);
1853 increment(dst);
1854 } else { // unordered is greater
1855 movl(dst, 1);
1856 jcc(Assembler::parity, L);
1857 jcc(Assembler::above , L);
1858 movl(dst, 0);
1859 jcc(Assembler::equal , L);
1860 decrementl(dst);
1861 }
1862 bind(L);
1863 }
1864
1865
1866 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1867 assert(rscratch != noreg || always_reachable(src1), "missing");
1868
1869 if (reachable(src1)) {
1870 cmpb(as_Address(src1), imm);
1871 } else {
1872 lea(rscratch, src1);
1873 cmpb(Address(rscratch, 0), imm);
1874 }
1875 }
1876
1877 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1878 #ifdef _LP64
1879 assert(rscratch != noreg || always_reachable(src2), "missing");
1880
1881 if (src2.is_lval()) {
1882 movptr(rscratch, src2);
1883 Assembler::cmpq(src1, rscratch);
1884 } else if (reachable(src2)) {
1885 cmpq(src1, as_Address(src2));
1886 } else {
1887 lea(rscratch, src2);
1888 Assembler::cmpq(src1, Address(rscratch, 0));
1889 }
1890 #else
1891 assert(rscratch == noreg, "not needed");
1892 if (src2.is_lval()) {
1893 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1894 } else {
1895 cmpl(src1, as_Address(src2));
1896 }
1897 #endif // _LP64
1898 }
1899
1900 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1901 assert(src2.is_lval(), "not a mem-mem compare");
1902 #ifdef _LP64
1903 // moves src2's literal address
1904 movptr(rscratch, src2);
1905 Assembler::cmpq(src1, rscratch);
1906 #else
1907 assert(rscratch == noreg, "not needed");
1908 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1909 #endif // _LP64
1910 }
1911
1912 void MacroAssembler::cmpoop(Register src1, Register src2) {
1913 cmpptr(src1, src2);
1914 }
1915
1916 void MacroAssembler::cmpoop(Register src1, Address src2) {
1917 cmpptr(src1, src2);
1918 }
1919
1920 #ifdef _LP64
1921 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1922 movoop(rscratch, src2);
1923 cmpptr(src1, rscratch);
1924 }
1925 #endif
1926
1927 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1928 assert(rscratch != noreg || always_reachable(adr), "missing");
1929
1930 if (reachable(adr)) {
1931 lock();
1932 cmpxchgptr(reg, as_Address(adr));
1933 } else {
1934 lea(rscratch, adr);
1935 lock();
1936 cmpxchgptr(reg, Address(rscratch, 0));
1937 }
1938 }
1939
1940 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1941 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1942 }
1943
1944 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1945 assert(rscratch != noreg || always_reachable(src), "missing");
1946
1947 if (reachable(src)) {
1948 Assembler::comisd(dst, as_Address(src));
1949 } else {
1950 lea(rscratch, src);
1951 Assembler::comisd(dst, Address(rscratch, 0));
1952 }
1953 }
1954
1955 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1956 assert(rscratch != noreg || always_reachable(src), "missing");
1957
1958 if (reachable(src)) {
1959 Assembler::comiss(dst, as_Address(src));
1960 } else {
1961 lea(rscratch, src);
1962 Assembler::comiss(dst, Address(rscratch, 0));
1963 }
1964 }
1965
1966
1967 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1968 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1969
1970 Condition negated_cond = negate_condition(cond);
1971 Label L;
1972 jcc(negated_cond, L);
1973 pushf(); // Preserve flags
1974 atomic_incl(counter_addr, rscratch);
1975 popf();
1976 bind(L);
1977 }
1978
1979 int MacroAssembler::corrected_idivl(Register reg) {
1980 // Full implementation of Java idiv and irem; checks for
1981 // special case as described in JVM spec., p.243 & p.271.
1982 // The function returns the (pc) offset of the idivl
1983 // instruction - may be needed for implicit exceptions.
1984 //
1985 // normal case special case
1986 //
1987 // input : rax,: dividend min_int
1988 // reg: divisor (may not be rax,/rdx) -1
1989 //
1990 // output: rax,: quotient (= rax, idiv reg) min_int
1991 // rdx: remainder (= rax, irem reg) 0
1992 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1993 const int min_int = 0x80000000;
1994 Label normal_case, special_case;
1995
1996 // check for special case
1997 cmpl(rax, min_int);
1998 jcc(Assembler::notEqual, normal_case);
1999 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2000 cmpl(reg, -1);
2001 jcc(Assembler::equal, special_case);
2002
2003 // handle normal case
2004 bind(normal_case);
2005 cdql();
2006 int idivl_offset = offset();
2007 idivl(reg);
2008
2009 // normal and special case exit
2010 bind(special_case);
2011
2012 return idivl_offset;
2013 }
2014
2015
2016
2017 void MacroAssembler::decrementl(Register reg, int value) {
2018 if (value == min_jint) {subl(reg, value) ; return; }
2019 if (value < 0) { incrementl(reg, -value); return; }
2020 if (value == 0) { ; return; }
2021 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2022 /* else */ { subl(reg, value) ; return; }
2023 }
2024
2025 void MacroAssembler::decrementl(Address dst, int value) {
2026 if (value == min_jint) {subl(dst, value) ; return; }
2027 if (value < 0) { incrementl(dst, -value); return; }
2028 if (value == 0) { ; return; }
2029 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2030 /* else */ { subl(dst, value) ; return; }
2031 }
2032
2033 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2034 assert(shift_value > 0, "illegal shift value");
2035 Label _is_positive;
2036 testl (reg, reg);
2037 jcc (Assembler::positive, _is_positive);
2038 int offset = (1 << shift_value) - 1 ;
2039
2040 if (offset == 1) {
2041 incrementl(reg);
2042 } else {
2043 addl(reg, offset);
2044 }
2045
2046 bind (_is_positive);
2047 sarl(reg, shift_value);
2048 }
2049
2050 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2051 assert(rscratch != noreg || always_reachable(src), "missing");
2052
2053 if (reachable(src)) {
2054 Assembler::divsd(dst, as_Address(src));
2055 } else {
2056 lea(rscratch, src);
2057 Assembler::divsd(dst, Address(rscratch, 0));
2058 }
2059 }
2060
2061 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2062 assert(rscratch != noreg || always_reachable(src), "missing");
2063
2064 if (reachable(src)) {
2065 Assembler::divss(dst, as_Address(src));
2066 } else {
2067 lea(rscratch, src);
2068 Assembler::divss(dst, Address(rscratch, 0));
2069 }
2070 }
2071
2072 void MacroAssembler::enter() {
2073 push(rbp);
2074 mov(rbp, rsp);
2075 }
2076
2077 void MacroAssembler::post_call_nop() {
2078 if (!Continuations::enabled()) {
2079 return;
2080 }
2081 InstructionMark im(this);
2082 relocate(post_call_nop_Relocation::spec());
2083 InlineSkippedInstructionsCounter skipCounter(this);
2084 emit_int8((uint8_t)0x0f);
2085 emit_int8((uint8_t)0x1f);
2086 emit_int8((uint8_t)0x84);
2087 emit_int8((uint8_t)0x00);
2088 emit_int32(0x00);
2089 }
2090
2091 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2092 void MacroAssembler::fat_nop() {
2093 if (UseAddressNop) {
2094 addr_nop_5();
2095 } else {
2096 emit_int8((uint8_t)0x26); // es:
2097 emit_int8((uint8_t)0x2e); // cs:
2098 emit_int8((uint8_t)0x64); // fs:
2099 emit_int8((uint8_t)0x65); // gs:
2100 emit_int8((uint8_t)0x90);
2101 }
2102 }
2103
2104 #ifndef _LP64
2105 void MacroAssembler::fcmp(Register tmp) {
2106 fcmp(tmp, 1, true, true);
2107 }
2108
2109 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2110 assert(!pop_right || pop_left, "usage error");
2111 if (VM_Version::supports_cmov()) {
2112 assert(tmp == noreg, "unneeded temp");
2113 if (pop_left) {
2114 fucomip(index);
2115 } else {
2116 fucomi(index);
2117 }
2118 if (pop_right) {
2119 fpop();
2120 }
2121 } else {
2122 assert(tmp != noreg, "need temp");
2123 if (pop_left) {
2124 if (pop_right) {
2125 fcompp();
2126 } else {
2127 fcomp(index);
2128 }
2129 } else {
2130 fcom(index);
2131 }
2132 // convert FPU condition into eflags condition via rax,
2133 save_rax(tmp);
2134 fwait(); fnstsw_ax();
2135 sahf();
2136 restore_rax(tmp);
2137 }
2138 // condition codes set as follows:
2139 //
2140 // CF (corresponds to C0) if x < y
2141 // PF (corresponds to C2) if unordered
2142 // ZF (corresponds to C3) if x = y
2143 }
2144
2145 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2146 fcmp2int(dst, unordered_is_less, 1, true, true);
2147 }
2148
2149 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2150 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2151 Label L;
2152 if (unordered_is_less) {
2153 movl(dst, -1);
2154 jcc(Assembler::parity, L);
2155 jcc(Assembler::below , L);
2156 movl(dst, 0);
2157 jcc(Assembler::equal , L);
2158 increment(dst);
2159 } else { // unordered is greater
2160 movl(dst, 1);
2161 jcc(Assembler::parity, L);
2162 jcc(Assembler::above , L);
2163 movl(dst, 0);
2164 jcc(Assembler::equal , L);
2165 decrementl(dst);
2166 }
2167 bind(L);
2168 }
2169
2170 void MacroAssembler::fld_d(AddressLiteral src) {
2171 fld_d(as_Address(src));
2172 }
2173
2174 void MacroAssembler::fld_s(AddressLiteral src) {
2175 fld_s(as_Address(src));
2176 }
2177
2178 void MacroAssembler::fldcw(AddressLiteral src) {
2179 fldcw(as_Address(src));
2180 }
2181
2182 void MacroAssembler::fpop() {
2183 ffree();
2184 fincstp();
2185 }
2186
2187 void MacroAssembler::fremr(Register tmp) {
2188 save_rax(tmp);
2189 { Label L;
2190 bind(L);
2191 fprem();
2192 fwait(); fnstsw_ax();
2193 sahf();
2194 jcc(Assembler::parity, L);
2195 }
2196 restore_rax(tmp);
2197 // Result is in ST0.
2198 // Note: fxch & fpop to get rid of ST1
2199 // (otherwise FPU stack could overflow eventually)
2200 fxch(1);
2201 fpop();
2202 }
2203
2204 void MacroAssembler::empty_FPU_stack() {
2205 if (VM_Version::supports_mmx()) {
2206 emms();
2207 } else {
2208 for (int i = 8; i-- > 0; ) ffree(i);
2209 }
2210 }
2211 #endif // !LP64
2212
2213 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2214 assert(rscratch != noreg || always_reachable(src), "missing");
2215 if (reachable(src)) {
2216 Assembler::mulpd(dst, as_Address(src));
2217 } else {
2218 lea(rscratch, src);
2219 Assembler::mulpd(dst, Address(rscratch, 0));
2220 }
2221 }
2222
2223 void MacroAssembler::load_float(Address src) {
2224 #ifdef _LP64
2225 movflt(xmm0, src);
2226 #else
2227 if (UseSSE >= 1) {
2228 movflt(xmm0, src);
2229 } else {
2230 fld_s(src);
2231 }
2232 #endif // LP64
2233 }
2234
2235 void MacroAssembler::store_float(Address dst) {
2236 #ifdef _LP64
2237 movflt(dst, xmm0);
2238 #else
2239 if (UseSSE >= 1) {
2240 movflt(dst, xmm0);
2241 } else {
2242 fstp_s(dst);
2243 }
2244 #endif // LP64
2245 }
2246
2247 void MacroAssembler::load_double(Address src) {
2248 #ifdef _LP64
2249 movdbl(xmm0, src);
2250 #else
2251 if (UseSSE >= 2) {
2252 movdbl(xmm0, src);
2253 } else {
2254 fld_d(src);
2255 }
2256 #endif // LP64
2257 }
2258
2259 void MacroAssembler::store_double(Address dst) {
2260 #ifdef _LP64
2261 movdbl(dst, xmm0);
2262 #else
2263 if (UseSSE >= 2) {
2264 movdbl(dst, xmm0);
2265 } else {
2266 fstp_d(dst);
2267 }
2268 #endif // LP64
2269 }
2270
2271 // dst = c = a * b + c
2272 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2273 Assembler::vfmadd231sd(c, a, b);
2274 if (dst != c) {
2275 movdbl(dst, c);
2276 }
2277 }
2278
2279 // dst = c = a * b + c
2280 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2281 Assembler::vfmadd231ss(c, a, b);
2282 if (dst != c) {
2283 movflt(dst, c);
2284 }
2285 }
2286
2287 // dst = c = a * b + c
2288 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2289 Assembler::vfmadd231pd(c, a, b, vector_len);
2290 if (dst != c) {
2291 vmovdqu(dst, c);
2292 }
2293 }
2294
2295 // dst = c = a * b + c
2296 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2297 Assembler::vfmadd231ps(c, a, b, vector_len);
2298 if (dst != c) {
2299 vmovdqu(dst, c);
2300 }
2301 }
2302
2303 // dst = c = a * b + c
2304 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2305 Assembler::vfmadd231pd(c, a, b, vector_len);
2306 if (dst != c) {
2307 vmovdqu(dst, c);
2308 }
2309 }
2310
2311 // dst = c = a * b + c
2312 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2313 Assembler::vfmadd231ps(c, a, b, vector_len);
2314 if (dst != c) {
2315 vmovdqu(dst, c);
2316 }
2317 }
2318
2319 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
2320 assert(rscratch != noreg || always_reachable(dst), "missing");
2321
2322 if (reachable(dst)) {
2323 incrementl(as_Address(dst));
2324 } else {
2325 lea(rscratch, dst);
2326 incrementl(Address(rscratch, 0));
2327 }
2328 }
2329
2330 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
2331 incrementl(as_Address(dst, rscratch));
2332 }
2333
2334 void MacroAssembler::incrementl(Register reg, int value) {
2335 if (value == min_jint) {addl(reg, value) ; return; }
2336 if (value < 0) { decrementl(reg, -value); return; }
2337 if (value == 0) { ; return; }
2338 if (value == 1 && UseIncDec) { incl(reg) ; return; }
2339 /* else */ { addl(reg, value) ; return; }
2340 }
2341
2342 void MacroAssembler::incrementl(Address dst, int value) {
2343 if (value == min_jint) {addl(dst, value) ; return; }
2344 if (value < 0) { decrementl(dst, -value); return; }
2345 if (value == 0) { ; return; }
2346 if (value == 1 && UseIncDec) { incl(dst) ; return; }
2347 /* else */ { addl(dst, value) ; return; }
2348 }
2349
2350 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
2351 assert(rscratch != noreg || always_reachable(dst), "missing");
2352 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
2353 if (reachable(dst)) {
2354 jmp_literal(dst.target(), dst.rspec());
2355 } else {
2356 lea(rscratch, dst);
2357 jmp(rscratch);
2358 }
2359 }
2360
2361 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
2362 assert(rscratch != noreg || always_reachable(dst), "missing");
2363 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
2364 if (reachable(dst)) {
2365 InstructionMark im(this);
2366 relocate(dst.reloc());
2367 const int short_size = 2;
2368 const int long_size = 6;
2369 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2370 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2371 // 0111 tttn #8-bit disp
2372 emit_int8(0x70 | cc);
2373 emit_int8((offs - short_size) & 0xFF);
2374 } else {
2375 // 0000 1111 1000 tttn #32-bit disp
2376 emit_int8(0x0F);
2377 emit_int8((unsigned char)(0x80 | cc));
2378 emit_int32(offs - long_size);
2379 }
2380 } else {
2381 #ifdef ASSERT
2382 warning("reversing conditional branch");
2383 #endif /* ASSERT */
2384 Label skip;
2385 jccb(reverse[cc], skip);
2386 lea(rscratch, dst);
2387 Assembler::jmp(rscratch);
2388 bind(skip);
2389 }
2390 }
2391
2392 void MacroAssembler::cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch) {
2393 ExternalAddress mxcsr_std(StubRoutines::x86::addr_mxcsr_std());
2394 assert(rscratch != noreg || always_reachable(mxcsr_std), "missing");
2395
2396 stmxcsr(mxcsr_save);
2397 movl(tmp, mxcsr_save);
2398 if (EnableX86ECoreOpts) {
2399 // The mxcsr_std has status bits set for performance on ECore
2400 orl(tmp, 0x003f);
2401 } else {
2402 // Mask out status bits (only check control and mask bits)
2403 andl(tmp, 0xFFC0);
2404 }
2405 cmp32(tmp, mxcsr_std, rscratch);
2406 }
2407
2408 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
2409 assert(rscratch != noreg || always_reachable(src), "missing");
2410
2411 if (reachable(src)) {
2412 Assembler::ldmxcsr(as_Address(src));
2413 } else {
2414 lea(rscratch, src);
2415 Assembler::ldmxcsr(Address(rscratch, 0));
2416 }
2417 }
2418
2419 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2420 int off;
2421 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2422 off = offset();
2423 movsbl(dst, src); // movsxb
2424 } else {
2425 off = load_unsigned_byte(dst, src);
2426 shll(dst, 24);
2427 sarl(dst, 24);
2428 }
2429 return off;
2430 }
2431
2432 // Note: load_signed_short used to be called load_signed_word.
2433 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2434 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2435 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2436 int MacroAssembler::load_signed_short(Register dst, Address src) {
2437 int off;
2438 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2439 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2440 // version but this is what 64bit has always done. This seems to imply
2441 // that users are only using 32bits worth.
2442 off = offset();
2443 movswl(dst, src); // movsxw
2444 } else {
2445 off = load_unsigned_short(dst, src);
2446 shll(dst, 16);
2447 sarl(dst, 16);
2448 }
2449 return off;
2450 }
2451
2452 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2453 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2454 // and "3.9 Partial Register Penalties", p. 22).
2455 int off;
2456 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2457 off = offset();
2458 movzbl(dst, src); // movzxb
2459 } else {
2460 xorl(dst, dst);
2461 off = offset();
2462 movb(dst, src);
2463 }
2464 return off;
2465 }
2466
2467 // Note: load_unsigned_short used to be called load_unsigned_word.
2468 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2469 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2470 // and "3.9 Partial Register Penalties", p. 22).
2471 int off;
2472 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2473 off = offset();
2474 movzwl(dst, src); // movzxw
2475 } else {
2476 xorl(dst, dst);
2477 off = offset();
2478 movw(dst, src);
2479 }
2480 return off;
2481 }
2482
2483 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2484 switch (size_in_bytes) {
2485 #ifndef _LP64
2486 case 8:
2487 assert(dst2 != noreg, "second dest register required");
2488 movl(dst, src);
2489 movl(dst2, src.plus_disp(BytesPerInt));
2490 break;
2491 #else
2492 case 8: movq(dst, src); break;
2493 #endif
2494 case 4: movl(dst, src); break;
2495 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2496 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2497 default: ShouldNotReachHere();
2498 }
2499 }
2500
2501 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2502 switch (size_in_bytes) {
2503 #ifndef _LP64
2504 case 8:
2505 assert(src2 != noreg, "second source register required");
2506 movl(dst, src);
2507 movl(dst.plus_disp(BytesPerInt), src2);
2508 break;
2509 #else
2510 case 8: movq(dst, src); break;
2511 #endif
2512 case 4: movl(dst, src); break;
2513 case 2: movw(dst, src); break;
2514 case 1: movb(dst, src); break;
2515 default: ShouldNotReachHere();
2516 }
2517 }
2518
2519 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
2520 assert(rscratch != noreg || always_reachable(dst), "missing");
2521
2522 if (reachable(dst)) {
2523 movl(as_Address(dst), src);
2524 } else {
2525 lea(rscratch, dst);
2526 movl(Address(rscratch, 0), src);
2527 }
2528 }
2529
2530 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2531 if (reachable(src)) {
2532 movl(dst, as_Address(src));
2533 } else {
2534 lea(dst, src);
2535 movl(dst, Address(dst, 0));
2536 }
2537 }
2538
2539 // C++ bool manipulation
2540
2541 void MacroAssembler::movbool(Register dst, Address src) {
2542 if(sizeof(bool) == 1)
2543 movb(dst, src);
2544 else if(sizeof(bool) == 2)
2545 movw(dst, src);
2546 else if(sizeof(bool) == 4)
2547 movl(dst, src);
2548 else
2549 // unsupported
2550 ShouldNotReachHere();
2551 }
2552
2553 void MacroAssembler::movbool(Address dst, bool boolconst) {
2554 if(sizeof(bool) == 1)
2555 movb(dst, (int) boolconst);
2556 else if(sizeof(bool) == 2)
2557 movw(dst, (int) boolconst);
2558 else if(sizeof(bool) == 4)
2559 movl(dst, (int) boolconst);
2560 else
2561 // unsupported
2562 ShouldNotReachHere();
2563 }
2564
2565 void MacroAssembler::movbool(Address dst, Register src) {
2566 if(sizeof(bool) == 1)
2567 movb(dst, src);
2568 else if(sizeof(bool) == 2)
2569 movw(dst, src);
2570 else if(sizeof(bool) == 4)
2571 movl(dst, src);
2572 else
2573 // unsupported
2574 ShouldNotReachHere();
2575 }
2576
2577 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2578 assert(rscratch != noreg || always_reachable(src), "missing");
2579
2580 if (reachable(src)) {
2581 movdl(dst, as_Address(src));
2582 } else {
2583 lea(rscratch, src);
2584 movdl(dst, Address(rscratch, 0));
2585 }
2586 }
2587
2588 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
2589 assert(rscratch != noreg || always_reachable(src), "missing");
2590
2591 if (reachable(src)) {
2592 movq(dst, as_Address(src));
2593 } else {
2594 lea(rscratch, src);
2595 movq(dst, Address(rscratch, 0));
2596 }
2597 }
2598
2599 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2600 assert(rscratch != noreg || always_reachable(src), "missing");
2601
2602 if (reachable(src)) {
2603 if (UseXmmLoadAndClearUpper) {
2604 movsd (dst, as_Address(src));
2605 } else {
2606 movlpd(dst, as_Address(src));
2607 }
2608 } else {
2609 lea(rscratch, src);
2610 if (UseXmmLoadAndClearUpper) {
2611 movsd (dst, Address(rscratch, 0));
2612 } else {
2613 movlpd(dst, Address(rscratch, 0));
2614 }
2615 }
2616 }
2617
2618 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
2619 assert(rscratch != noreg || always_reachable(src), "missing");
2620
2621 if (reachable(src)) {
2622 movss(dst, as_Address(src));
2623 } else {
2624 lea(rscratch, src);
2625 movss(dst, Address(rscratch, 0));
2626 }
2627 }
2628
2629 void MacroAssembler::movptr(Register dst, Register src) {
2630 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2631 }
2632
2633 void MacroAssembler::movptr(Register dst, Address src) {
2634 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2635 }
2636
2637 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2638 void MacroAssembler::movptr(Register dst, intptr_t src) {
2639 #ifdef _LP64
2640 if (is_uimm32(src)) {
2641 movl(dst, checked_cast<uint32_t>(src));
2642 } else if (is_simm32(src)) {
2643 movq(dst, checked_cast<int32_t>(src));
2644 } else {
2645 mov64(dst, src);
2646 }
2647 #else
2648 movl(dst, src);
2649 #endif
2650 }
2651
2652 void MacroAssembler::movptr(Address dst, Register src) {
2653 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2654 }
2655
2656 void MacroAssembler::movptr(Address dst, int32_t src) {
2657 LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src));
2658 }
2659
2660 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2661 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2662 Assembler::movdqu(dst, src);
2663 }
2664
2665 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2666 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2667 Assembler::movdqu(dst, src);
2668 }
2669
2670 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2671 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2672 Assembler::movdqu(dst, src);
2673 }
2674
2675 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2676 assert(rscratch != noreg || always_reachable(src), "missing");
2677
2678 if (reachable(src)) {
2679 movdqu(dst, as_Address(src));
2680 } else {
2681 lea(rscratch, src);
2682 movdqu(dst, Address(rscratch, 0));
2683 }
2684 }
2685
2686 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2687 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2688 Assembler::vmovdqu(dst, src);
2689 }
2690
2691 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2692 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2693 Assembler::vmovdqu(dst, src);
2694 }
2695
2696 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2697 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2698 Assembler::vmovdqu(dst, src);
2699 }
2700
2701 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2702 assert(rscratch != noreg || always_reachable(src), "missing");
2703
2704 if (reachable(src)) {
2705 vmovdqu(dst, as_Address(src));
2706 }
2707 else {
2708 lea(rscratch, src);
2709 vmovdqu(dst, Address(rscratch, 0));
2710 }
2711 }
2712
2713 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2714 assert(rscratch != noreg || always_reachable(src), "missing");
2715
2716 if (vector_len == AVX_512bit) {
2717 evmovdquq(dst, src, AVX_512bit, rscratch);
2718 } else if (vector_len == AVX_256bit) {
2719 vmovdqu(dst, src, rscratch);
2720 } else {
2721 movdqu(dst, src, rscratch);
2722 }
2723 }
2724
2725 void MacroAssembler::kmov(KRegister dst, Address src) {
2726 if (VM_Version::supports_avx512bw()) {
2727 kmovql(dst, src);
2728 } else {
2729 assert(VM_Version::supports_evex(), "");
2730 kmovwl(dst, src);
2731 }
2732 }
2733
2734 void MacroAssembler::kmov(Address dst, KRegister src) {
2735 if (VM_Version::supports_avx512bw()) {
2736 kmovql(dst, src);
2737 } else {
2738 assert(VM_Version::supports_evex(), "");
2739 kmovwl(dst, src);
2740 }
2741 }
2742
2743 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2744 if (VM_Version::supports_avx512bw()) {
2745 kmovql(dst, src);
2746 } else {
2747 assert(VM_Version::supports_evex(), "");
2748 kmovwl(dst, src);
2749 }
2750 }
2751
2752 void MacroAssembler::kmov(Register dst, KRegister src) {
2753 if (VM_Version::supports_avx512bw()) {
2754 kmovql(dst, src);
2755 } else {
2756 assert(VM_Version::supports_evex(), "");
2757 kmovwl(dst, src);
2758 }
2759 }
2760
2761 void MacroAssembler::kmov(KRegister dst, Register src) {
2762 if (VM_Version::supports_avx512bw()) {
2763 kmovql(dst, src);
2764 } else {
2765 assert(VM_Version::supports_evex(), "");
2766 kmovwl(dst, src);
2767 }
2768 }
2769
2770 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2771 assert(rscratch != noreg || always_reachable(src), "missing");
2772
2773 if (reachable(src)) {
2774 kmovql(dst, as_Address(src));
2775 } else {
2776 lea(rscratch, src);
2777 kmovql(dst, Address(rscratch, 0));
2778 }
2779 }
2780
2781 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2782 assert(rscratch != noreg || always_reachable(src), "missing");
2783
2784 if (reachable(src)) {
2785 kmovwl(dst, as_Address(src));
2786 } else {
2787 lea(rscratch, src);
2788 kmovwl(dst, Address(rscratch, 0));
2789 }
2790 }
2791
2792 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2793 int vector_len, Register rscratch) {
2794 assert(rscratch != noreg || always_reachable(src), "missing");
2795
2796 if (reachable(src)) {
2797 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2798 } else {
2799 lea(rscratch, src);
2800 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2801 }
2802 }
2803
2804 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2805 int vector_len, Register rscratch) {
2806 assert(rscratch != noreg || always_reachable(src), "missing");
2807
2808 if (reachable(src)) {
2809 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2810 } else {
2811 lea(rscratch, src);
2812 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2813 }
2814 }
2815
2816 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2817 assert(rscratch != noreg || always_reachable(src), "missing");
2818
2819 if (reachable(src)) {
2820 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2821 } else {
2822 lea(rscratch, src);
2823 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2824 }
2825 }
2826
2827 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2828 assert(rscratch != noreg || always_reachable(src), "missing");
2829
2830 if (reachable(src)) {
2831 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2832 } else {
2833 lea(rscratch, src);
2834 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2835 }
2836 }
2837
2838 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2839 assert(rscratch != noreg || always_reachable(src), "missing");
2840
2841 if (reachable(src)) {
2842 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2843 } else {
2844 lea(rscratch, src);
2845 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2846 }
2847 }
2848
2849 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2850 assert(rscratch != noreg || always_reachable(src), "missing");
2851
2852 if (reachable(src)) {
2853 Assembler::movdqa(dst, as_Address(src));
2854 } else {
2855 lea(rscratch, src);
2856 Assembler::movdqa(dst, Address(rscratch, 0));
2857 }
2858 }
2859
2860 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2861 assert(rscratch != noreg || always_reachable(src), "missing");
2862
2863 if (reachable(src)) {
2864 Assembler::movsd(dst, as_Address(src));
2865 } else {
2866 lea(rscratch, src);
2867 Assembler::movsd(dst, Address(rscratch, 0));
2868 }
2869 }
2870
2871 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2872 assert(rscratch != noreg || always_reachable(src), "missing");
2873
2874 if (reachable(src)) {
2875 Assembler::movss(dst, as_Address(src));
2876 } else {
2877 lea(rscratch, src);
2878 Assembler::movss(dst, Address(rscratch, 0));
2879 }
2880 }
2881
2882 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2883 assert(rscratch != noreg || always_reachable(src), "missing");
2884
2885 if (reachable(src)) {
2886 Assembler::movddup(dst, as_Address(src));
2887 } else {
2888 lea(rscratch, src);
2889 Assembler::movddup(dst, Address(rscratch, 0));
2890 }
2891 }
2892
2893 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2894 assert(rscratch != noreg || always_reachable(src), "missing");
2895
2896 if (reachable(src)) {
2897 Assembler::vmovddup(dst, as_Address(src), vector_len);
2898 } else {
2899 lea(rscratch, src);
2900 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2901 }
2902 }
2903
2904 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2905 assert(rscratch != noreg || always_reachable(src), "missing");
2906
2907 if (reachable(src)) {
2908 Assembler::mulsd(dst, as_Address(src));
2909 } else {
2910 lea(rscratch, src);
2911 Assembler::mulsd(dst, Address(rscratch, 0));
2912 }
2913 }
2914
2915 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2916 assert(rscratch != noreg || always_reachable(src), "missing");
2917
2918 if (reachable(src)) {
2919 Assembler::mulss(dst, as_Address(src));
2920 } else {
2921 lea(rscratch, src);
2922 Assembler::mulss(dst, Address(rscratch, 0));
2923 }
2924 }
2925
2926 void MacroAssembler::null_check(Register reg, int offset) {
2927 if (needs_explicit_null_check(offset)) {
2928 // provoke OS null exception if reg is null by
2929 // accessing M[reg] w/o changing any (non-CC) registers
2930 // NOTE: cmpl is plenty here to provoke a segv
2931 cmpptr(rax, Address(reg, 0));
2932 // Note: should probably use testl(rax, Address(reg, 0));
2933 // may be shorter code (however, this version of
2934 // testl needs to be implemented first)
2935 } else {
2936 // nothing to do, (later) access of M[reg + offset]
2937 // will provoke OS null exception if reg is null
2938 }
2939 }
2940
2941 void MacroAssembler::os_breakpoint() {
2942 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2943 // (e.g., MSVC can't call ps() otherwise)
2944 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2945 }
2946
2947 void MacroAssembler::unimplemented(const char* what) {
2948 const char* buf = nullptr;
2949 {
2950 ResourceMark rm;
2951 stringStream ss;
2952 ss.print("unimplemented: %s", what);
2953 buf = code_string(ss.as_string());
2954 }
2955 stop(buf);
2956 }
2957
2958 #ifdef _LP64
2959 #define XSTATE_BV 0x200
2960 #endif
2961
2962 void MacroAssembler::pop_CPU_state() {
2963 pop_FPU_state();
2964 pop_IU_state();
2965 }
2966
2967 void MacroAssembler::pop_FPU_state() {
2968 #ifndef _LP64
2969 frstor(Address(rsp, 0));
2970 #else
2971 fxrstor(Address(rsp, 0));
2972 #endif
2973 addptr(rsp, FPUStateSizeInWords * wordSize);
2974 }
2975
2976 void MacroAssembler::pop_IU_state() {
2977 popa();
2978 LP64_ONLY(addq(rsp, 8));
2979 popf();
2980 }
2981
2982 // Save Integer and Float state
2983 // Warning: Stack must be 16 byte aligned (64bit)
2984 void MacroAssembler::push_CPU_state() {
2985 push_IU_state();
2986 push_FPU_state();
2987 }
2988
2989 void MacroAssembler::push_FPU_state() {
2990 subptr(rsp, FPUStateSizeInWords * wordSize);
2991 #ifndef _LP64
2992 fnsave(Address(rsp, 0));
2993 fwait();
2994 #else
2995 fxsave(Address(rsp, 0));
2996 #endif // LP64
2997 }
2998
2999 void MacroAssembler::push_IU_state() {
3000 // Push flags first because pusha kills them
3001 pushf();
3002 // Make sure rsp stays 16-byte aligned
3003 LP64_ONLY(subq(rsp, 8));
3004 pusha();
3005 }
3006
3007 void MacroAssembler::push_cont_fastpath() {
3008 if (!Continuations::enabled()) return;
3009
3010 #ifndef _LP64
3011 Register rthread = rax;
3012 Register rrealsp = rbx;
3013 push(rthread);
3014 push(rrealsp);
3015
3016 get_thread(rthread);
3017
3018 // The code below wants the original RSP.
3019 // Move it back after the pushes above.
3020 movptr(rrealsp, rsp);
3021 addptr(rrealsp, 2*wordSize);
3022 #else
3023 Register rthread = r15_thread;
3024 Register rrealsp = rsp;
3025 #endif
3026
3027 Label done;
3028 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3029 jccb(Assembler::belowEqual, done);
3030 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), rrealsp);
3031 bind(done);
3032
3033 #ifndef _LP64
3034 pop(rrealsp);
3035 pop(rthread);
3036 #endif
3037 }
3038
3039 void MacroAssembler::pop_cont_fastpath() {
3040 if (!Continuations::enabled()) return;
3041
3042 #ifndef _LP64
3043 Register rthread = rax;
3044 Register rrealsp = rbx;
3045 push(rthread);
3046 push(rrealsp);
3047
3048 get_thread(rthread);
3049
3050 // The code below wants the original RSP.
3051 // Move it back after the pushes above.
3052 movptr(rrealsp, rsp);
3053 addptr(rrealsp, 2*wordSize);
3054 #else
3055 Register rthread = r15_thread;
3056 Register rrealsp = rsp;
3057 #endif
3058
3059 Label done;
3060 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3061 jccb(Assembler::below, done);
3062 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), 0);
3063 bind(done);
3064
3065 #ifndef _LP64
3066 pop(rrealsp);
3067 pop(rthread);
3068 #endif
3069 }
3070
3071 void MacroAssembler::inc_held_monitor_count() {
3072 #ifdef _LP64
3073 incrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3074 #endif
3075 }
3076
3077 void MacroAssembler::dec_held_monitor_count() {
3078 #ifdef _LP64
3079 decrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3080 #endif
3081 }
3082
3083 #ifdef ASSERT
3084 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
3085 #ifdef _LP64
3086 Label no_cont;
3087 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
3088 testl(cont, cont);
3089 jcc(Assembler::zero, no_cont);
3090 stop(name);
3091 bind(no_cont);
3092 #else
3093 Unimplemented();
3094 #endif
3095 }
3096 #endif
3097
3098 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3099 if (!java_thread->is_valid()) {
3100 java_thread = rdi;
3101 get_thread(java_thread);
3102 }
3103 // we must set sp to zero to clear frame
3104 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3105 // must clear fp, so that compiled frames are not confused; it is
3106 // possible that we need it only for debugging
3107 if (clear_fp) {
3108 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3109 }
3110 // Always clear the pc because it could have been set by make_walkable()
3111 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3112 vzeroupper();
3113 }
3114
3115 void MacroAssembler::restore_rax(Register tmp) {
3116 if (tmp == noreg) pop(rax);
3117 else if (tmp != rax) mov(rax, tmp);
3118 }
3119
3120 void MacroAssembler::round_to(Register reg, int modulus) {
3121 addptr(reg, modulus - 1);
3122 andptr(reg, -modulus);
3123 }
3124
3125 void MacroAssembler::save_rax(Register tmp) {
3126 if (tmp == noreg) push(rax);
3127 else if (tmp != rax) mov(tmp, rax);
3128 }
3129
3130 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
3131 if (at_return) {
3132 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
3133 // we may safely use rsp instead to perform the stack watermark check.
3134 cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
3135 jcc(Assembler::above, slow_path);
3136 return;
3137 }
3138 testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
3139 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3140 }
3141
3142 // Calls to C land
3143 //
3144 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3145 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3146 // has to be reset to 0. This is required to allow proper stack traversal.
3147 void MacroAssembler::set_last_Java_frame(Register java_thread,
3148 Register last_java_sp,
3149 Register last_java_fp,
3150 address last_java_pc,
3151 Register rscratch) {
3152 vzeroupper();
3153 // determine java_thread register
3154 if (!java_thread->is_valid()) {
3155 java_thread = rdi;
3156 get_thread(java_thread);
3157 }
3158 // determine last_java_sp register
3159 if (!last_java_sp->is_valid()) {
3160 last_java_sp = rsp;
3161 }
3162 // last_java_fp is optional
3163 if (last_java_fp->is_valid()) {
3164 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3165 }
3166 // last_java_pc is optional
3167 if (last_java_pc != nullptr) {
3168 Address java_pc(java_thread,
3169 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
3170 lea(java_pc, InternalAddress(last_java_pc), rscratch);
3171 }
3172 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3173 }
3174
3175 #ifdef _LP64
3176 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
3177 Register last_java_fp,
3178 Label &L,
3179 Register scratch) {
3180 lea(scratch, L);
3181 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
3182 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, nullptr, scratch);
3183 }
3184 #endif
3185
3186 void MacroAssembler::shlptr(Register dst, int imm8) {
3187 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3188 }
3189
3190 void MacroAssembler::shrptr(Register dst, int imm8) {
3191 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3192 }
3193
3194 void MacroAssembler::sign_extend_byte(Register reg) {
3195 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3196 movsbl(reg, reg); // movsxb
3197 } else {
3198 shll(reg, 24);
3199 sarl(reg, 24);
3200 }
3201 }
3202
3203 void MacroAssembler::sign_extend_short(Register reg) {
3204 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3205 movswl(reg, reg); // movsxw
3206 } else {
3207 shll(reg, 16);
3208 sarl(reg, 16);
3209 }
3210 }
3211
3212 void MacroAssembler::testl(Address dst, int32_t imm32) {
3213 if (imm32 >= 0 && is8bit(imm32)) {
3214 testb(dst, imm32);
3215 } else {
3216 Assembler::testl(dst, imm32);
3217 }
3218 }
3219
3220 void MacroAssembler::testl(Register dst, int32_t imm32) {
3221 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
3222 testb(dst, imm32);
3223 } else {
3224 Assembler::testl(dst, imm32);
3225 }
3226 }
3227
3228 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3229 assert(always_reachable(src), "Address should be reachable");
3230 testl(dst, as_Address(src));
3231 }
3232
3233 #ifdef _LP64
3234
3235 void MacroAssembler::testq(Address dst, int32_t imm32) {
3236 if (imm32 >= 0) {
3237 testl(dst, imm32);
3238 } else {
3239 Assembler::testq(dst, imm32);
3240 }
3241 }
3242
3243 void MacroAssembler::testq(Register dst, int32_t imm32) {
3244 if (imm32 >= 0) {
3245 testl(dst, imm32);
3246 } else {
3247 Assembler::testq(dst, imm32);
3248 }
3249 }
3250
3251 #endif
3252
3253 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3254 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3255 Assembler::pcmpeqb(dst, src);
3256 }
3257
3258 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3259 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3260 Assembler::pcmpeqw(dst, src);
3261 }
3262
3263 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3264 assert((dst->encoding() < 16),"XMM register should be 0-15");
3265 Assembler::pcmpestri(dst, src, imm8);
3266 }
3267
3268 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3269 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3270 Assembler::pcmpestri(dst, src, imm8);
3271 }
3272
3273 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3274 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3275 Assembler::pmovzxbw(dst, src);
3276 }
3277
3278 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3279 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3280 Assembler::pmovzxbw(dst, src);
3281 }
3282
3283 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3284 assert((src->encoding() < 16),"XMM register should be 0-15");
3285 Assembler::pmovmskb(dst, src);
3286 }
3287
3288 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3289 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3290 Assembler::ptest(dst, src);
3291 }
3292
3293 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3294 assert(rscratch != noreg || always_reachable(src), "missing");
3295
3296 if (reachable(src)) {
3297 Assembler::sqrtss(dst, as_Address(src));
3298 } else {
3299 lea(rscratch, src);
3300 Assembler::sqrtss(dst, Address(rscratch, 0));
3301 }
3302 }
3303
3304 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3305 assert(rscratch != noreg || always_reachable(src), "missing");
3306
3307 if (reachable(src)) {
3308 Assembler::subsd(dst, as_Address(src));
3309 } else {
3310 lea(rscratch, src);
3311 Assembler::subsd(dst, Address(rscratch, 0));
3312 }
3313 }
3314
3315 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
3316 assert(rscratch != noreg || always_reachable(src), "missing");
3317
3318 if (reachable(src)) {
3319 Assembler::roundsd(dst, as_Address(src), rmode);
3320 } else {
3321 lea(rscratch, src);
3322 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
3323 }
3324 }
3325
3326 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3327 assert(rscratch != noreg || always_reachable(src), "missing");
3328
3329 if (reachable(src)) {
3330 Assembler::subss(dst, as_Address(src));
3331 } else {
3332 lea(rscratch, src);
3333 Assembler::subss(dst, Address(rscratch, 0));
3334 }
3335 }
3336
3337 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3338 assert(rscratch != noreg || always_reachable(src), "missing");
3339
3340 if (reachable(src)) {
3341 Assembler::ucomisd(dst, as_Address(src));
3342 } else {
3343 lea(rscratch, src);
3344 Assembler::ucomisd(dst, Address(rscratch, 0));
3345 }
3346 }
3347
3348 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3349 assert(rscratch != noreg || always_reachable(src), "missing");
3350
3351 if (reachable(src)) {
3352 Assembler::ucomiss(dst, as_Address(src));
3353 } else {
3354 lea(rscratch, src);
3355 Assembler::ucomiss(dst, Address(rscratch, 0));
3356 }
3357 }
3358
3359 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3360 assert(rscratch != noreg || always_reachable(src), "missing");
3361
3362 // Used in sign-bit flipping with aligned address.
3363 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3364
3365 if (UseAVX > 2 &&
3366 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3367 (dst->encoding() >= 16)) {
3368 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
3369 } else if (reachable(src)) {
3370 Assembler::xorpd(dst, as_Address(src));
3371 } else {
3372 lea(rscratch, src);
3373 Assembler::xorpd(dst, Address(rscratch, 0));
3374 }
3375 }
3376
3377 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3378 if (UseAVX > 2 &&
3379 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3380 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
3381 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3382 } else {
3383 Assembler::xorpd(dst, src);
3384 }
3385 }
3386
3387 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3388 if (UseAVX > 2 &&
3389 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3390 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
3391 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3392 } else {
3393 Assembler::xorps(dst, src);
3394 }
3395 }
3396
3397 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
3398 assert(rscratch != noreg || always_reachable(src), "missing");
3399
3400 // Used in sign-bit flipping with aligned address.
3401 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3402
3403 if (UseAVX > 2 &&
3404 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3405 (dst->encoding() >= 16)) {
3406 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
3407 } else if (reachable(src)) {
3408 Assembler::xorps(dst, as_Address(src));
3409 } else {
3410 lea(rscratch, src);
3411 Assembler::xorps(dst, Address(rscratch, 0));
3412 }
3413 }
3414
3415 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
3416 assert(rscratch != noreg || always_reachable(src), "missing");
3417
3418 // Used in sign-bit flipping with aligned address.
3419 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3420 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3421 if (reachable(src)) {
3422 Assembler::pshufb(dst, as_Address(src));
3423 } else {
3424 lea(rscratch, src);
3425 Assembler::pshufb(dst, Address(rscratch, 0));
3426 }
3427 }
3428
3429 // AVX 3-operands instructions
3430
3431 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3432 assert(rscratch != noreg || always_reachable(src), "missing");
3433
3434 if (reachable(src)) {
3435 vaddsd(dst, nds, as_Address(src));
3436 } else {
3437 lea(rscratch, src);
3438 vaddsd(dst, nds, Address(rscratch, 0));
3439 }
3440 }
3441
3442 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3443 assert(rscratch != noreg || always_reachable(src), "missing");
3444
3445 if (reachable(src)) {
3446 vaddss(dst, nds, as_Address(src));
3447 } else {
3448 lea(rscratch, src);
3449 vaddss(dst, nds, Address(rscratch, 0));
3450 }
3451 }
3452
3453 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3454 assert(UseAVX > 0, "requires some form of AVX");
3455 assert(rscratch != noreg || always_reachable(src), "missing");
3456
3457 if (reachable(src)) {
3458 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3459 } else {
3460 lea(rscratch, src);
3461 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3462 }
3463 }
3464
3465 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3466 assert(UseAVX > 0, "requires some form of AVX");
3467 assert(rscratch != noreg || always_reachable(src), "missing");
3468
3469 if (reachable(src)) {
3470 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3471 } else {
3472 lea(rscratch, src);
3473 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3474 }
3475 }
3476
3477 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3478 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3479 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3480
3481 vandps(dst, nds, negate_field, vector_len, rscratch);
3482 }
3483
3484 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3485 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3486 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3487
3488 vandpd(dst, nds, negate_field, vector_len, rscratch);
3489 }
3490
3491 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3492 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3493 Assembler::vpaddb(dst, nds, src, vector_len);
3494 }
3495
3496 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3497 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3498 Assembler::vpaddb(dst, nds, src, vector_len);
3499 }
3500
3501 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3502 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3503 Assembler::vpaddw(dst, nds, src, vector_len);
3504 }
3505
3506 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3507 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3508 Assembler::vpaddw(dst, nds, src, vector_len);
3509 }
3510
3511 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3512 assert(rscratch != noreg || always_reachable(src), "missing");
3513
3514 if (reachable(src)) {
3515 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3516 } else {
3517 lea(rscratch, src);
3518 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
3519 }
3520 }
3521
3522 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3523 assert(rscratch != noreg || always_reachable(src), "missing");
3524
3525 if (reachable(src)) {
3526 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
3527 } else {
3528 lea(rscratch, src);
3529 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
3530 }
3531 }
3532
3533 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3534 assert(rscratch != noreg || always_reachable(src), "missing");
3535
3536 if (reachable(src)) {
3537 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
3538 } else {
3539 lea(rscratch, src);
3540 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
3541 }
3542 }
3543
3544 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3545 assert(rscratch != noreg || always_reachable(src), "missing");
3546
3547 if (reachable(src)) {
3548 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3549 } else {
3550 lea(rscratch, src);
3551 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3552 }
3553 }
3554
3555 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3556 assert(rscratch != noreg || always_reachable(src), "missing");
3557
3558 if (reachable(src)) {
3559 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3560 } else {
3561 lea(rscratch, src);
3562 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3563 }
3564 }
3565
3566 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3567 assert(rscratch != noreg || always_reachable(src), "missing");
3568
3569 if (reachable(src)) {
3570 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3571 } else {
3572 lea(rscratch, src);
3573 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3574 }
3575 }
3576
3577 // Vector float blend
3578 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3579 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3580 // WARN: Allow dst == (src1|src2), mask == scratch
3581 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3582 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3583 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3584 if (blend_emulation && scratch_available && dst_available) {
3585 if (compute_mask) {
3586 vpsrad(scratch, mask, 32, vector_len);
3587 mask = scratch;
3588 }
3589 if (dst == src1) {
3590 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3591 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3592 } else {
3593 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3594 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3595 }
3596 vpor(dst, dst, scratch, vector_len);
3597 } else {
3598 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3599 }
3600 }
3601
3602 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3603 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3604 // WARN: Allow dst == (src1|src2), mask == scratch
3605 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3606 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3607 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3608 if (blend_emulation && scratch_available && dst_available) {
3609 if (compute_mask) {
3610 vpxor(scratch, scratch, scratch, vector_len);
3611 vpcmpgtq(scratch, scratch, mask, vector_len);
3612 mask = scratch;
3613 }
3614 if (dst == src1) {
3615 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3616 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3617 } else {
3618 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3619 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3620 }
3621 vpor(dst, dst, scratch, vector_len);
3622 } else {
3623 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3624 }
3625 }
3626
3627 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3628 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3629 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3630 }
3631
3632 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3633 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3634 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3635 }
3636
3637 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3638 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3639 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3640 }
3641
3642 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3643 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3644 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3645 }
3646
3647 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3648 assert(rscratch != noreg || always_reachable(src), "missing");
3649
3650 if (reachable(src)) {
3651 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3652 } else {
3653 lea(rscratch, src);
3654 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3655 }
3656 }
3657
3658 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3659 int comparison, bool is_signed, int vector_len, Register rscratch) {
3660 assert(rscratch != noreg || always_reachable(src), "missing");
3661
3662 if (reachable(src)) {
3663 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3664 } else {
3665 lea(rscratch, src);
3666 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3667 }
3668 }
3669
3670 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3671 int comparison, bool is_signed, int vector_len, Register rscratch) {
3672 assert(rscratch != noreg || always_reachable(src), "missing");
3673
3674 if (reachable(src)) {
3675 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3676 } else {
3677 lea(rscratch, src);
3678 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3679 }
3680 }
3681
3682 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3683 int comparison, bool is_signed, int vector_len, Register rscratch) {
3684 assert(rscratch != noreg || always_reachable(src), "missing");
3685
3686 if (reachable(src)) {
3687 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3688 } else {
3689 lea(rscratch, src);
3690 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3691 }
3692 }
3693
3694 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3695 int comparison, bool is_signed, int vector_len, Register rscratch) {
3696 assert(rscratch != noreg || always_reachable(src), "missing");
3697
3698 if (reachable(src)) {
3699 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3700 } else {
3701 lea(rscratch, src);
3702 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3703 }
3704 }
3705
3706 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3707 if (width == Assembler::Q) {
3708 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3709 } else {
3710 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3711 }
3712 }
3713
3714 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3715 int eq_cond_enc = 0x29;
3716 int gt_cond_enc = 0x37;
3717 if (width != Assembler::Q) {
3718 eq_cond_enc = 0x74 + width;
3719 gt_cond_enc = 0x64 + width;
3720 }
3721 switch (cond) {
3722 case eq:
3723 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3724 break;
3725 case neq:
3726 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3727 vallones(xtmp, vector_len);
3728 vpxor(dst, xtmp, dst, vector_len);
3729 break;
3730 case le:
3731 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3732 vallones(xtmp, vector_len);
3733 vpxor(dst, xtmp, dst, vector_len);
3734 break;
3735 case nlt:
3736 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3737 vallones(xtmp, vector_len);
3738 vpxor(dst, xtmp, dst, vector_len);
3739 break;
3740 case lt:
3741 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3742 break;
3743 case nle:
3744 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3745 break;
3746 default:
3747 assert(false, "Should not reach here");
3748 }
3749 }
3750
3751 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3752 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3753 Assembler::vpmovzxbw(dst, src, vector_len);
3754 }
3755
3756 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3757 assert((src->encoding() < 16),"XMM register should be 0-15");
3758 Assembler::vpmovmskb(dst, src, vector_len);
3759 }
3760
3761 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3762 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3763 Assembler::vpmullw(dst, nds, src, vector_len);
3764 }
3765
3766 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3767 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3768 Assembler::vpmullw(dst, nds, src, vector_len);
3769 }
3770
3771 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3772 assert((UseAVX > 0), "AVX support is needed");
3773 assert(rscratch != noreg || always_reachable(src), "missing");
3774
3775 if (reachable(src)) {
3776 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3777 } else {
3778 lea(rscratch, src);
3779 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3780 }
3781 }
3782
3783 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3784 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3785 Assembler::vpsubb(dst, nds, src, vector_len);
3786 }
3787
3788 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3789 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3790 Assembler::vpsubb(dst, nds, src, vector_len);
3791 }
3792
3793 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3794 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3795 Assembler::vpsubw(dst, nds, src, vector_len);
3796 }
3797
3798 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3799 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3800 Assembler::vpsubw(dst, nds, src, vector_len);
3801 }
3802
3803 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3804 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3805 Assembler::vpsraw(dst, nds, shift, vector_len);
3806 }
3807
3808 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3809 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3810 Assembler::vpsraw(dst, nds, shift, vector_len);
3811 }
3812
3813 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3814 assert(UseAVX > 2,"");
3815 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3816 vector_len = 2;
3817 }
3818 Assembler::evpsraq(dst, nds, shift, vector_len);
3819 }
3820
3821 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3822 assert(UseAVX > 2,"");
3823 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3824 vector_len = 2;
3825 }
3826 Assembler::evpsraq(dst, nds, shift, vector_len);
3827 }
3828
3829 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3830 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3831 Assembler::vpsrlw(dst, nds, shift, vector_len);
3832 }
3833
3834 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3835 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3836 Assembler::vpsrlw(dst, nds, shift, vector_len);
3837 }
3838
3839 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3840 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3841 Assembler::vpsllw(dst, nds, shift, vector_len);
3842 }
3843
3844 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3845 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3846 Assembler::vpsllw(dst, nds, shift, vector_len);
3847 }
3848
3849 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3850 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3851 Assembler::vptest(dst, src);
3852 }
3853
3854 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3855 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3856 Assembler::punpcklbw(dst, src);
3857 }
3858
3859 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3860 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3861 Assembler::pshufd(dst, src, mode);
3862 }
3863
3864 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3865 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3866 Assembler::pshuflw(dst, src, mode);
3867 }
3868
3869 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3870 assert(rscratch != noreg || always_reachable(src), "missing");
3871
3872 if (reachable(src)) {
3873 vandpd(dst, nds, as_Address(src), vector_len);
3874 } else {
3875 lea(rscratch, src);
3876 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3877 }
3878 }
3879
3880 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3881 assert(rscratch != noreg || always_reachable(src), "missing");
3882
3883 if (reachable(src)) {
3884 vandps(dst, nds, as_Address(src), vector_len);
3885 } else {
3886 lea(rscratch, src);
3887 vandps(dst, nds, Address(rscratch, 0), vector_len);
3888 }
3889 }
3890
3891 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3892 bool merge, int vector_len, Register rscratch) {
3893 assert(rscratch != noreg || always_reachable(src), "missing");
3894
3895 if (reachable(src)) {
3896 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3897 } else {
3898 lea(rscratch, src);
3899 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3900 }
3901 }
3902
3903 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3904 assert(rscratch != noreg || always_reachable(src), "missing");
3905
3906 if (reachable(src)) {
3907 vdivsd(dst, nds, as_Address(src));
3908 } else {
3909 lea(rscratch, src);
3910 vdivsd(dst, nds, Address(rscratch, 0));
3911 }
3912 }
3913
3914 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3915 assert(rscratch != noreg || always_reachable(src), "missing");
3916
3917 if (reachable(src)) {
3918 vdivss(dst, nds, as_Address(src));
3919 } else {
3920 lea(rscratch, src);
3921 vdivss(dst, nds, Address(rscratch, 0));
3922 }
3923 }
3924
3925 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3926 assert(rscratch != noreg || always_reachable(src), "missing");
3927
3928 if (reachable(src)) {
3929 vmulsd(dst, nds, as_Address(src));
3930 } else {
3931 lea(rscratch, src);
3932 vmulsd(dst, nds, Address(rscratch, 0));
3933 }
3934 }
3935
3936 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3937 assert(rscratch != noreg || always_reachable(src), "missing");
3938
3939 if (reachable(src)) {
3940 vmulss(dst, nds, as_Address(src));
3941 } else {
3942 lea(rscratch, src);
3943 vmulss(dst, nds, Address(rscratch, 0));
3944 }
3945 }
3946
3947 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3948 assert(rscratch != noreg || always_reachable(src), "missing");
3949
3950 if (reachable(src)) {
3951 vsubsd(dst, nds, as_Address(src));
3952 } else {
3953 lea(rscratch, src);
3954 vsubsd(dst, nds, Address(rscratch, 0));
3955 }
3956 }
3957
3958 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3959 assert(rscratch != noreg || always_reachable(src), "missing");
3960
3961 if (reachable(src)) {
3962 vsubss(dst, nds, as_Address(src));
3963 } else {
3964 lea(rscratch, src);
3965 vsubss(dst, nds, Address(rscratch, 0));
3966 }
3967 }
3968
3969 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3970 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3971 assert(rscratch != noreg || always_reachable(src), "missing");
3972
3973 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3974 }
3975
3976 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3977 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3978 assert(rscratch != noreg || always_reachable(src), "missing");
3979
3980 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3981 }
3982
3983 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3984 assert(rscratch != noreg || always_reachable(src), "missing");
3985
3986 if (reachable(src)) {
3987 vxorpd(dst, nds, as_Address(src), vector_len);
3988 } else {
3989 lea(rscratch, src);
3990 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3991 }
3992 }
3993
3994 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3995 assert(rscratch != noreg || always_reachable(src), "missing");
3996
3997 if (reachable(src)) {
3998 vxorps(dst, nds, as_Address(src), vector_len);
3999 } else {
4000 lea(rscratch, src);
4001 vxorps(dst, nds, Address(rscratch, 0), vector_len);
4002 }
4003 }
4004
4005 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
4006 assert(rscratch != noreg || always_reachable(src), "missing");
4007
4008 if (UseAVX > 1 || (vector_len < 1)) {
4009 if (reachable(src)) {
4010 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
4011 } else {
4012 lea(rscratch, src);
4013 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
4014 }
4015 } else {
4016 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
4017 }
4018 }
4019
4020 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
4021 assert(rscratch != noreg || always_reachable(src), "missing");
4022
4023 if (reachable(src)) {
4024 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
4025 } else {
4026 lea(rscratch, src);
4027 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
4028 }
4029 }
4030
4031 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
4032 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
4033 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
4034 // The inverted mask is sign-extended
4035 andptr(possibly_non_local, inverted_mask);
4036 }
4037
4038 void MacroAssembler::resolve_jobject(Register value,
4039 Register thread,
4040 Register tmp) {
4041 assert_different_registers(value, thread, tmp);
4042 Label done, tagged, weak_tagged;
4043 testptr(value, value);
4044 jcc(Assembler::zero, done); // Use null as-is.
4045 testptr(value, JNIHandles::tag_mask); // Test for tag.
4046 jcc(Assembler::notZero, tagged);
4047
4048 // Resolve local handle
4049 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp, thread);
4050 verify_oop(value);
4051 jmp(done);
4052
4053 bind(tagged);
4054 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
4055 jcc(Assembler::notZero, weak_tagged);
4056
4057 // Resolve global handle
4058 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4059 verify_oop(value);
4060 jmp(done);
4061
4062 bind(weak_tagged);
4063 // Resolve jweak.
4064 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4065 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp, thread);
4066 verify_oop(value);
4067
4068 bind(done);
4069 }
4070
4071 void MacroAssembler::resolve_global_jobject(Register value,
4072 Register thread,
4073 Register tmp) {
4074 assert_different_registers(value, thread, tmp);
4075 Label done;
4076
4077 testptr(value, value);
4078 jcc(Assembler::zero, done); // Use null as-is.
4079
4080 #ifdef ASSERT
4081 {
4082 Label valid_global_tag;
4083 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
4084 jcc(Assembler::notZero, valid_global_tag);
4085 stop("non global jobject using resolve_global_jobject");
4086 bind(valid_global_tag);
4087 }
4088 #endif
4089
4090 // Resolve global handle
4091 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4092 verify_oop(value);
4093
4094 bind(done);
4095 }
4096
4097 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4098 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4099 }
4100
4101 // Force generation of a 4 byte immediate value even if it fits into 8bit
4102 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4103 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4104 }
4105
4106 void MacroAssembler::subptr(Register dst, Register src) {
4107 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4108 }
4109
4110 // C++ bool manipulation
4111 void MacroAssembler::testbool(Register dst) {
4112 if(sizeof(bool) == 1)
4113 testb(dst, 0xff);
4114 else if(sizeof(bool) == 2) {
4115 // testw implementation needed for two byte bools
4116 ShouldNotReachHere();
4117 } else if(sizeof(bool) == 4)
4118 testl(dst, dst);
4119 else
4120 // unsupported
4121 ShouldNotReachHere();
4122 }
4123
4124 void MacroAssembler::testptr(Register dst, Register src) {
4125 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4126 }
4127
4128 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4129 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4130 Register var_size_in_bytes,
4131 int con_size_in_bytes,
4132 Register t1,
4133 Register t2,
4134 Label& slow_case) {
4135 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4136 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4137 }
4138
4139 RegSet MacroAssembler::call_clobbered_gp_registers() {
4140 RegSet regs;
4141 #ifdef _LP64
4142 regs += RegSet::of(rax, rcx, rdx);
4143 #ifndef _WINDOWS
4144 regs += RegSet::of(rsi, rdi);
4145 #endif
4146 regs += RegSet::range(r8, r11);
4147 #else
4148 regs += RegSet::of(rax, rcx, rdx);
4149 #endif
4150 #ifdef _LP64
4151 if (UseAPX) {
4152 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
4153 }
4154 #endif
4155 return regs;
4156 }
4157
4158 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
4159 int num_xmm_registers = XMMRegister::available_xmm_registers();
4160 #if defined(_WINDOWS)
4161 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
4162 if (num_xmm_registers > 16) {
4163 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
4164 }
4165 return result;
4166 #else
4167 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
4168 #endif
4169 }
4170
4171 static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor
4172
4173 #ifndef _LP64
4174 static bool use_x87_registers() { return UseSSE < 2; }
4175 #endif
4176 static bool use_xmm_registers() { return UseSSE >= 1; }
4177
4178 // C1 only ever uses the first double/float of the XMM register.
4179 static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); }
4180
4181 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4182 if (UseSSE == 1) {
4183 masm->movflt(Address(rsp, offset), reg);
4184 } else {
4185 masm->movdbl(Address(rsp, offset), reg);
4186 }
4187 }
4188
4189 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4190 if (UseSSE == 1) {
4191 masm->movflt(reg, Address(rsp, offset));
4192 } else {
4193 masm->movdbl(reg, Address(rsp, offset));
4194 }
4195 }
4196
4197 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
4198 bool save_fpu, int& gp_area_size,
4199 int& fp_area_size, int& xmm_area_size) {
4200
4201 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
4202 StackAlignmentInBytes);
4203 #ifdef _LP64
4204 fp_area_size = 0;
4205 #else
4206 fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0;
4207 #endif
4208 xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0;
4209
4210 return gp_area_size + fp_area_size + xmm_area_size;
4211 }
4212
4213 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
4214 block_comment("push_call_clobbered_registers start");
4215 // Regular registers
4216 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
4217
4218 int gp_area_size;
4219 int fp_area_size;
4220 int xmm_area_size;
4221 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
4222 gp_area_size, fp_area_size, xmm_area_size);
4223 subptr(rsp, total_save_size);
4224
4225 push_set(gp_registers_to_push, 0);
4226
4227 #ifndef _LP64
4228 if (save_fpu && use_x87_registers()) {
4229 fnsave(Address(rsp, gp_area_size));
4230 fwait();
4231 }
4232 #endif
4233 if (save_fpu && use_xmm_registers()) {
4234 push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4235 }
4236
4237 block_comment("push_call_clobbered_registers end");
4238 }
4239
4240 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
4241 block_comment("pop_call_clobbered_registers start");
4242
4243 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
4244
4245 int gp_area_size;
4246 int fp_area_size;
4247 int xmm_area_size;
4248 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
4249 gp_area_size, fp_area_size, xmm_area_size);
4250
4251 if (restore_fpu && use_xmm_registers()) {
4252 pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4253 }
4254 #ifndef _LP64
4255 if (restore_fpu && use_x87_registers()) {
4256 frstor(Address(rsp, gp_area_size));
4257 }
4258 #endif
4259
4260 pop_set(gp_registers_to_pop, 0);
4261
4262 addptr(rsp, total_save_size);
4263
4264 vzeroupper();
4265
4266 block_comment("pop_call_clobbered_registers end");
4267 }
4268
4269 void MacroAssembler::push_set(XMMRegSet set, int offset) {
4270 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
4271 int spill_offset = offset;
4272
4273 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
4274 save_xmm_register(this, spill_offset, *it);
4275 spill_offset += xmm_save_size();
4276 }
4277 }
4278
4279 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
4280 int restore_size = set.size() * xmm_save_size();
4281 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
4282
4283 int restore_offset = offset + restore_size - xmm_save_size();
4284
4285 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
4286 restore_xmm_register(this, restore_offset, *it);
4287 restore_offset -= xmm_save_size();
4288 }
4289 }
4290
4291 void MacroAssembler::push_set(RegSet set, int offset) {
4292 int spill_offset;
4293 if (offset == -1) {
4294 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4295 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4296 subptr(rsp, aligned_size);
4297 spill_offset = 0;
4298 } else {
4299 spill_offset = offset;
4300 }
4301
4302 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
4303 movptr(Address(rsp, spill_offset), *it);
4304 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4305 }
4306 }
4307
4308 void MacroAssembler::pop_set(RegSet set, int offset) {
4309
4310 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4311 int restore_size = set.size() * gp_reg_size;
4312 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
4313
4314 int restore_offset;
4315 if (offset == -1) {
4316 restore_offset = restore_size - gp_reg_size;
4317 } else {
4318 restore_offset = offset + restore_size - gp_reg_size;
4319 }
4320 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
4321 movptr(*it, Address(rsp, restore_offset));
4322 restore_offset -= gp_reg_size;
4323 }
4324
4325 if (offset == -1) {
4326 addptr(rsp, aligned_size);
4327 }
4328 }
4329
4330 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4331 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4332 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4333 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4334 Label done;
4335
4336 testptr(length_in_bytes, length_in_bytes);
4337 jcc(Assembler::zero, done);
4338
4339 // initialize topmost word, divide index by 2, check if odd and test if zero
4340 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4341 #ifdef ASSERT
4342 {
4343 Label L;
4344 testptr(length_in_bytes, BytesPerWord - 1);
4345 jcc(Assembler::zero, L);
4346 stop("length must be a multiple of BytesPerWord");
4347 bind(L);
4348 }
4349 #endif
4350 Register index = length_in_bytes;
4351 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4352 if (UseIncDec) {
4353 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4354 } else {
4355 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4356 shrptr(index, 1);
4357 }
4358 #ifndef _LP64
4359 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4360 {
4361 Label even;
4362 // note: if index was a multiple of 8, then it cannot
4363 // be 0 now otherwise it must have been 0 before
4364 // => if it is even, we don't need to check for 0 again
4365 jcc(Assembler::carryClear, even);
4366 // clear topmost word (no jump would be needed if conditional assignment worked here)
4367 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4368 // index could be 0 now, must check again
4369 jcc(Assembler::zero, done);
4370 bind(even);
4371 }
4372 #endif // !_LP64
4373 // initialize remaining object fields: index is a multiple of 2 now
4374 {
4375 Label loop;
4376 bind(loop);
4377 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4378 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4379 decrement(index);
4380 jcc(Assembler::notZero, loop);
4381 }
4382
4383 bind(done);
4384 }
4385
4386 // Look up the method for a megamorphic invokeinterface call.
4387 // The target method is determined by <intf_klass, itable_index>.
4388 // The receiver klass is in recv_klass.
4389 // On success, the result will be in method_result, and execution falls through.
4390 // On failure, execution transfers to the given label.
4391 void MacroAssembler::lookup_interface_method(Register recv_klass,
4392 Register intf_klass,
4393 RegisterOrConstant itable_index,
4394 Register method_result,
4395 Register scan_temp,
4396 Label& L_no_such_interface,
4397 bool return_method) {
4398 assert_different_registers(recv_klass, intf_klass, scan_temp);
4399 assert_different_registers(method_result, intf_klass, scan_temp);
4400 assert(recv_klass != method_result || !return_method,
4401 "recv_klass can be destroyed when method isn't needed");
4402
4403 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4404 "caller must use same register for non-constant itable index as for method");
4405
4406 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4407 int vtable_base = in_bytes(Klass::vtable_start_offset());
4408 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4409 int scan_step = itableOffsetEntry::size() * wordSize;
4410 int vte_size = vtableEntry::size_in_bytes();
4411 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4412 assert(vte_size == wordSize, "else adjust times_vte_scale");
4413
4414 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4415
4416 // Could store the aligned, prescaled offset in the klass.
4417 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4418
4419 if (return_method) {
4420 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4421 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4422 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4423 }
4424
4425 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
4426 // if (scan->interface() == intf) {
4427 // result = (klass + scan->offset() + itable_index);
4428 // }
4429 // }
4430 Label search, found_method;
4431
4432 for (int peel = 1; peel >= 0; peel--) {
4433 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
4434 cmpptr(intf_klass, method_result);
4435
4436 if (peel) {
4437 jccb(Assembler::equal, found_method);
4438 } else {
4439 jccb(Assembler::notEqual, search);
4440 // (invert the test to fall through to found_method...)
4441 }
4442
4443 if (!peel) break;
4444
4445 bind(search);
4446
4447 // Check that the previous entry is non-null. A null entry means that
4448 // the receiver class doesn't implement the interface, and wasn't the
4449 // same as when the caller was compiled.
4450 testptr(method_result, method_result);
4451 jcc(Assembler::zero, L_no_such_interface);
4452 addptr(scan_temp, scan_step);
4453 }
4454
4455 bind(found_method);
4456
4457 if (return_method) {
4458 // Got a hit.
4459 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
4460 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4461 }
4462 }
4463
4464 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
4465 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
4466 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
4467 // The target method is determined by <holder_klass, itable_index>.
4468 // The receiver klass is in recv_klass.
4469 // On success, the result will be in method_result, and execution falls through.
4470 // On failure, execution transfers to the given label.
4471 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
4472 Register holder_klass,
4473 Register resolved_klass,
4474 Register method_result,
4475 Register scan_temp,
4476 Register temp_reg2,
4477 Register receiver,
4478 int itable_index,
4479 Label& L_no_such_interface) {
4480 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
4481 Register temp_itbl_klass = method_result;
4482 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
4483
4484 int vtable_base = in_bytes(Klass::vtable_start_offset());
4485 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4486 int scan_step = itableOffsetEntry::size() * wordSize;
4487 int vte_size = vtableEntry::size_in_bytes();
4488 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
4489 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
4490 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4491 assert(vte_size == wordSize, "adjust times_vte_scale");
4492
4493 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
4494
4495 // temp_itbl_klass = recv_klass.itable[0]
4496 // scan_temp = &recv_klass.itable[0] + step
4497 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4498 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
4499 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
4500 xorptr(temp_reg, temp_reg);
4501
4502 // Initial checks:
4503 // - if (holder_klass != resolved_klass), go to "scan for resolved"
4504 // - if (itable[0] == 0), no such interface
4505 // - if (itable[0] == holder_klass), shortcut to "holder found"
4506 cmpptr(holder_klass, resolved_klass);
4507 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
4508 testptr(temp_itbl_klass, temp_itbl_klass);
4509 jccb(Assembler::zero, L_no_such_interface);
4510 cmpptr(holder_klass, temp_itbl_klass);
4511 jccb(Assembler::equal, L_holder_found);
4512
4513 // Loop: Look for holder_klass record in itable
4514 // do {
4515 // tmp = itable[index];
4516 // index += step;
4517 // if (tmp == holder_klass) {
4518 // goto L_holder_found; // Found!
4519 // }
4520 // } while (tmp != 0);
4521 // goto L_no_such_interface // Not found.
4522 Label L_scan_holder;
4523 bind(L_scan_holder);
4524 movptr(temp_itbl_klass, Address(scan_temp, 0));
4525 addptr(scan_temp, scan_step);
4526 cmpptr(holder_klass, temp_itbl_klass);
4527 jccb(Assembler::equal, L_holder_found);
4528 testptr(temp_itbl_klass, temp_itbl_klass);
4529 jccb(Assembler::notZero, L_scan_holder);
4530
4531 jmpb(L_no_such_interface);
4532
4533 // Loop: Look for resolved_class record in itable
4534 // do {
4535 // tmp = itable[index];
4536 // index += step;
4537 // if (tmp == holder_klass) {
4538 // // Also check if we have met a holder klass
4539 // holder_tmp = itable[index-step-ioffset];
4540 // }
4541 // if (tmp == resolved_klass) {
4542 // goto L_resolved_found; // Found!
4543 // }
4544 // } while (tmp != 0);
4545 // goto L_no_such_interface // Not found.
4546 //
4547 Label L_loop_scan_resolved;
4548 bind(L_loop_scan_resolved);
4549 movptr(temp_itbl_klass, Address(scan_temp, 0));
4550 addptr(scan_temp, scan_step);
4551 bind(L_loop_scan_resolved_entry);
4552 cmpptr(holder_klass, temp_itbl_klass);
4553 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4554 cmpptr(resolved_klass, temp_itbl_klass);
4555 jccb(Assembler::equal, L_resolved_found);
4556 testptr(temp_itbl_klass, temp_itbl_klass);
4557 jccb(Assembler::notZero, L_loop_scan_resolved);
4558
4559 jmpb(L_no_such_interface);
4560
4561 Label L_ready;
4562
4563 // See if we already have a holder klass. If not, go and scan for it.
4564 bind(L_resolved_found);
4565 testptr(temp_reg, temp_reg);
4566 jccb(Assembler::zero, L_scan_holder);
4567 jmpb(L_ready);
4568
4569 bind(L_holder_found);
4570 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4571
4572 // Finally, temp_reg contains holder_klass vtable offset
4573 bind(L_ready);
4574 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4575 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4576 load_klass(scan_temp, receiver, noreg);
4577 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4578 } else {
4579 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4580 }
4581 }
4582
4583
4584 // virtual method calling
4585 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4586 RegisterOrConstant vtable_index,
4587 Register method_result) {
4588 const ByteSize base = Klass::vtable_start_offset();
4589 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4590 Address vtable_entry_addr(recv_klass,
4591 vtable_index, Address::times_ptr,
4592 base + vtableEntry::method_offset());
4593 movptr(method_result, vtable_entry_addr);
4594 }
4595
4596
4597 void MacroAssembler::check_klass_subtype(Register sub_klass,
4598 Register super_klass,
4599 Register temp_reg,
4600 Label& L_success) {
4601 Label L_failure;
4602 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4603 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4604 bind(L_failure);
4605 }
4606
4607
4608 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4609 Register super_klass,
4610 Register temp_reg,
4611 Label* L_success,
4612 Label* L_failure,
4613 Label* L_slow_path,
4614 RegisterOrConstant super_check_offset) {
4615 assert_different_registers(sub_klass, super_klass, temp_reg);
4616 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4617 if (super_check_offset.is_register()) {
4618 assert_different_registers(sub_klass, super_klass,
4619 super_check_offset.as_register());
4620 } else if (must_load_sco) {
4621 assert(temp_reg != noreg, "supply either a temp or a register offset");
4622 }
4623
4624 Label L_fallthrough;
4625 int label_nulls = 0;
4626 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4627 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4628 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4629 assert(label_nulls <= 1, "at most one null in the batch");
4630
4631 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4632 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4633 Address super_check_offset_addr(super_klass, sco_offset);
4634
4635 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4636 // range of a jccb. If this routine grows larger, reconsider at
4637 // least some of these.
4638 #define local_jcc(assembler_cond, label) \
4639 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4640 else jcc( assembler_cond, label) /*omit semi*/
4641
4642 // Hacked jmp, which may only be used just before L_fallthrough.
4643 #define final_jmp(label) \
4644 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4645 else jmp(label) /*omit semi*/
4646
4647 // If the pointers are equal, we are done (e.g., String[] elements).
4648 // This self-check enables sharing of secondary supertype arrays among
4649 // non-primary types such as array-of-interface. Otherwise, each such
4650 // type would need its own customized SSA.
4651 // We move this check to the front of the fast path because many
4652 // type checks are in fact trivially successful in this manner,
4653 // so we get a nicely predicted branch right at the start of the check.
4654 cmpptr(sub_klass, super_klass);
4655 local_jcc(Assembler::equal, *L_success);
4656
4657 // Check the supertype display:
4658 if (must_load_sco) {
4659 // Positive movl does right thing on LP64.
4660 movl(temp_reg, super_check_offset_addr);
4661 super_check_offset = RegisterOrConstant(temp_reg);
4662 }
4663 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4664 cmpptr(super_klass, super_check_addr); // load displayed supertype
4665
4666 // This check has worked decisively for primary supers.
4667 // Secondary supers are sought in the super_cache ('super_cache_addr').
4668 // (Secondary supers are interfaces and very deeply nested subtypes.)
4669 // This works in the same check above because of a tricky aliasing
4670 // between the super_cache and the primary super display elements.
4671 // (The 'super_check_addr' can address either, as the case requires.)
4672 // Note that the cache is updated below if it does not help us find
4673 // what we need immediately.
4674 // So if it was a primary super, we can just fail immediately.
4675 // Otherwise, it's the slow path for us (no success at this point).
4676
4677 if (super_check_offset.is_register()) {
4678 local_jcc(Assembler::equal, *L_success);
4679 cmpl(super_check_offset.as_register(), sc_offset);
4680 if (L_failure == &L_fallthrough) {
4681 local_jcc(Assembler::equal, *L_slow_path);
4682 } else {
4683 local_jcc(Assembler::notEqual, *L_failure);
4684 final_jmp(*L_slow_path);
4685 }
4686 } else if (super_check_offset.as_constant() == sc_offset) {
4687 // Need a slow path; fast failure is impossible.
4688 if (L_slow_path == &L_fallthrough) {
4689 local_jcc(Assembler::equal, *L_success);
4690 } else {
4691 local_jcc(Assembler::notEqual, *L_slow_path);
4692 final_jmp(*L_success);
4693 }
4694 } else {
4695 // No slow path; it's a fast decision.
4696 if (L_failure == &L_fallthrough) {
4697 local_jcc(Assembler::equal, *L_success);
4698 } else {
4699 local_jcc(Assembler::notEqual, *L_failure);
4700 final_jmp(*L_success);
4701 }
4702 }
4703
4704 bind(L_fallthrough);
4705
4706 #undef local_jcc
4707 #undef final_jmp
4708 }
4709
4710
4711 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4712 Register super_klass,
4713 Register temp_reg,
4714 Register temp2_reg,
4715 Label* L_success,
4716 Label* L_failure,
4717 bool set_cond_codes) {
4718 assert_different_registers(sub_klass, super_klass, temp_reg);
4719 if (temp2_reg != noreg)
4720 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4721 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4722
4723 Label L_fallthrough;
4724 int label_nulls = 0;
4725 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4726 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4727 assert(label_nulls <= 1, "at most one null in the batch");
4728
4729 // a couple of useful fields in sub_klass:
4730 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4731 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4732 Address secondary_supers_addr(sub_klass, ss_offset);
4733 Address super_cache_addr( sub_klass, sc_offset);
4734
4735 // Do a linear scan of the secondary super-klass chain.
4736 // This code is rarely used, so simplicity is a virtue here.
4737 // The repne_scan instruction uses fixed registers, which we must spill.
4738 // Don't worry too much about pre-existing connections with the input regs.
4739
4740 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4741 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4742
4743 // Get super_klass value into rax (even if it was in rdi or rcx).
4744 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4745 if (super_klass != rax) {
4746 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4747 mov(rax, super_klass);
4748 }
4749 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4750 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4751
4752 #ifndef PRODUCT
4753 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4754 ExternalAddress pst_counter_addr((address) pst_counter);
4755 NOT_LP64( incrementl(pst_counter_addr) );
4756 LP64_ONLY( lea(rcx, pst_counter_addr) );
4757 LP64_ONLY( incrementl(Address(rcx, 0)) );
4758 #endif //PRODUCT
4759
4760 // We will consult the secondary-super array.
4761 movptr(rdi, secondary_supers_addr);
4762 // Load the array length. (Positive movl does right thing on LP64.)
4763 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4764 // Skip to start of data.
4765 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4766
4767 // Scan RCX words at [RDI] for an occurrence of RAX.
4768 // Set NZ/Z based on last compare.
4769 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4770 // not change flags (only scas instruction which is repeated sets flags).
4771 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4772
4773 testptr(rax,rax); // Set Z = 0
4774 repne_scan();
4775
4776 // Unspill the temp. registers:
4777 if (pushed_rdi) pop(rdi);
4778 if (pushed_rcx) pop(rcx);
4779 if (pushed_rax) pop(rax);
4780
4781 if (set_cond_codes) {
4782 // Special hack for the AD files: rdi is guaranteed non-zero.
4783 assert(!pushed_rdi, "rdi must be left non-null");
4784 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4785 }
4786
4787 if (L_failure == &L_fallthrough)
4788 jccb(Assembler::notEqual, *L_failure);
4789 else jcc(Assembler::notEqual, *L_failure);
4790
4791 // Success. Cache the super we found and proceed in triumph.
4792 movptr(super_cache_addr, super_klass);
4793
4794 if (L_success != &L_fallthrough) {
4795 jmp(*L_success);
4796 }
4797
4798 #undef IS_A_TEMP
4799
4800 bind(L_fallthrough);
4801 }
4802
4803 #ifndef _LP64
4804
4805 // 32-bit x86 only: always use the linear search.
4806 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4807 Register super_klass,
4808 Register temp_reg,
4809 Register temp2_reg,
4810 Label* L_success,
4811 Label* L_failure,
4812 bool set_cond_codes) {
4813 check_klass_subtype_slow_path_linear
4814 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
4815 }
4816
4817 #else // _LP64
4818
4819 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4820 Register super_klass,
4821 Register temp_reg,
4822 Register temp2_reg,
4823 Label* L_success,
4824 Label* L_failure,
4825 bool set_cond_codes) {
4826 assert(set_cond_codes == false, "must be false on 64-bit x86");
4827 check_klass_subtype_slow_path
4828 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4829 L_success, L_failure);
4830 }
4831
4832 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4833 Register super_klass,
4834 Register temp_reg,
4835 Register temp2_reg,
4836 Register temp3_reg,
4837 Register temp4_reg,
4838 Label* L_success,
4839 Label* L_failure) {
4840 if (UseSecondarySupersTable) {
4841 check_klass_subtype_slow_path_table
4842 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4843 L_success, L_failure);
4844 } else {
4845 check_klass_subtype_slow_path_linear
4846 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4847 }
4848 }
4849
4850 Register MacroAssembler::allocate_if_noreg(Register r,
4851 RegSetIterator<Register> &available_regs,
4852 RegSet ®s_to_push) {
4853 if (!r->is_valid()) {
4854 r = *available_regs++;
4855 regs_to_push += r;
4856 }
4857 return r;
4858 }
4859
4860 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4861 Register super_klass,
4862 Register temp_reg,
4863 Register temp2_reg,
4864 Register temp3_reg,
4865 Register result_reg,
4866 Label* L_success,
4867 Label* L_failure) {
4868 // NB! Callers may assume that, when temp2_reg is a valid register,
4869 // this code sets it to a nonzero value.
4870 bool temp2_reg_was_valid = temp2_reg->is_valid();
4871
4872 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4873
4874 Label L_fallthrough;
4875 int label_nulls = 0;
4876 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4877 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4878 assert(label_nulls <= 1, "at most one null in the batch");
4879
4880 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4881
4882 RegSetIterator<Register> available_regs
4883 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4884
4885 RegSet pushed_regs;
4886
4887 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4888 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4889 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4890 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4891 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4892
4893 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4894
4895 {
4896
4897 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4898 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4899 subptr(rsp, aligned_size);
4900 push_set(pushed_regs, 0);
4901
4902 lookup_secondary_supers_table_var(sub_klass,
4903 super_klass,
4904 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4905 cmpq(result_reg, 0);
4906
4907 // Unspill the temp. registers:
4908 pop_set(pushed_regs, 0);
4909 // Increment SP but do not clobber flags.
4910 lea(rsp, Address(rsp, aligned_size));
4911 }
4912
4913 if (temp2_reg_was_valid) {
4914 movq(temp2_reg, 1);
4915 }
4916
4917 jcc(Assembler::notEqual, *L_failure);
4918
4919 if (L_success != &L_fallthrough) {
4920 jmp(*L_success);
4921 }
4922
4923 bind(L_fallthrough);
4924 }
4925
4926 // population_count variant for running without the POPCNT
4927 // instruction, which was introduced with SSE4.2 in 2008.
4928 void MacroAssembler::population_count(Register dst, Register src,
4929 Register scratch1, Register scratch2) {
4930 assert_different_registers(src, scratch1, scratch2);
4931 if (UsePopCountInstruction) {
4932 Assembler::popcntq(dst, src);
4933 } else {
4934 assert_different_registers(src, scratch1, scratch2);
4935 assert_different_registers(dst, scratch1, scratch2);
4936 Label loop, done;
4937
4938 mov(scratch1, src);
4939 // dst = 0;
4940 // while(scratch1 != 0) {
4941 // dst++;
4942 // scratch1 &= (scratch1 - 1);
4943 // }
4944 xorl(dst, dst);
4945 testq(scratch1, scratch1);
4946 jccb(Assembler::equal, done);
4947 {
4948 bind(loop);
4949 incq(dst);
4950 movq(scratch2, scratch1);
4951 decq(scratch2);
4952 andq(scratch1, scratch2);
4953 jccb(Assembler::notEqual, loop);
4954 }
4955 bind(done);
4956 }
4957 #ifdef ASSERT
4958 mov64(scratch1, 0xCafeBabeDeadBeef);
4959 movq(scratch2, scratch1);
4960 #endif
4961 }
4962
4963 // Ensure that the inline code and the stub are using the same registers.
4964 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4965 do { \
4966 assert(r_super_klass == rax, "mismatch"); \
4967 assert(r_array_base == rbx, "mismatch"); \
4968 assert(r_array_length == rcx, "mismatch"); \
4969 assert(r_array_index == rdx, "mismatch"); \
4970 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4971 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4972 assert(result == rdi || result == noreg, "mismatch"); \
4973 } while(0)
4974
4975 // Versions of salq and rorq that don't need count to be in rcx
4976
4977 void MacroAssembler::salq(Register dest, Register count) {
4978 if (count == rcx) {
4979 Assembler::salq(dest);
4980 } else {
4981 assert_different_registers(rcx, dest);
4982 xchgq(rcx, count);
4983 Assembler::salq(dest);
4984 xchgq(rcx, count);
4985 }
4986 }
4987
4988 void MacroAssembler::rorq(Register dest, Register count) {
4989 if (count == rcx) {
4990 Assembler::rorq(dest);
4991 } else {
4992 assert_different_registers(rcx, dest);
4993 xchgq(rcx, count);
4994 Assembler::rorq(dest);
4995 xchgq(rcx, count);
4996 }
4997 }
4998
4999 // Return true: we succeeded in generating this code
5000 //
5001 // At runtime, return 0 in result if r_super_klass is a superclass of
5002 // r_sub_klass, otherwise return nonzero. Use this if you know the
5003 // super_klass_slot of the class you're looking for. This is always
5004 // the case for instanceof and checkcast.
5005 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
5006 Register r_super_klass,
5007 Register temp1,
5008 Register temp2,
5009 Register temp3,
5010 Register temp4,
5011 Register result,
5012 u1 super_klass_slot) {
5013 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
5014
5015 Label L_fallthrough, L_success, L_failure;
5016
5017 BLOCK_COMMENT("lookup_secondary_supers_table {");
5018
5019 const Register
5020 r_array_index = temp1,
5021 r_array_length = temp2,
5022 r_array_base = temp3,
5023 r_bitmap = temp4;
5024
5025 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
5026
5027 xorq(result, result); // = 0
5028
5029 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
5030 movq(r_array_index, r_bitmap);
5031
5032 // First check the bitmap to see if super_klass might be present. If
5033 // the bit is zero, we are certain that super_klass is not one of
5034 // the secondary supers.
5035 u1 bit = super_klass_slot;
5036 {
5037 // NB: If the count in a x86 shift instruction is 0, the flags are
5038 // not affected, so we do a testq instead.
5039 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
5040 if (shift_count != 0) {
5041 salq(r_array_index, shift_count);
5042 } else {
5043 testq(r_array_index, r_array_index);
5044 }
5045 }
5046 // We test the MSB of r_array_index, i.e. its sign bit
5047 jcc(Assembler::positive, L_failure);
5048
5049 // Get the first array index that can contain super_klass into r_array_index.
5050 if (bit != 0) {
5051 population_count(r_array_index, r_array_index, temp2, temp3);
5052 } else {
5053 movl(r_array_index, 1);
5054 }
5055 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5056
5057 // We will consult the secondary-super array.
5058 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5059
5060 // We're asserting that the first word in an Array<Klass*> is the
5061 // length, and the second word is the first word of the data. If
5062 // that ever changes, r_array_base will have to be adjusted here.
5063 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5064 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5065
5066 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5067 jccb(Assembler::equal, L_success);
5068
5069 // Is there another entry to check? Consult the bitmap.
5070 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
5071 jccb(Assembler::carryClear, L_failure);
5072
5073 // Linear probe. Rotate the bitmap so that the next bit to test is
5074 // in Bit 1.
5075 if (bit != 0) {
5076 rorq(r_bitmap, bit);
5077 }
5078
5079 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5080 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5081 // Kills: r_array_length.
5082 // Returns: result.
5083 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
5084 // Result (0/1) is in rdi
5085 jmpb(L_fallthrough);
5086
5087 bind(L_failure);
5088 incq(result); // 0 => 1
5089
5090 bind(L_success);
5091 // result = 0;
5092
5093 bind(L_fallthrough);
5094 BLOCK_COMMENT("} lookup_secondary_supers_table");
5095
5096 if (VerifySecondarySupers) {
5097 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5098 temp1, temp2, temp3);
5099 }
5100 }
5101
5102 // At runtime, return 0 in result if r_super_klass is a superclass of
5103 // r_sub_klass, otherwise return nonzero. Use this version of
5104 // lookup_secondary_supers_table() if you don't know ahead of time
5105 // which superclass will be searched for. Used by interpreter and
5106 // runtime stubs. It is larger and has somewhat greater latency than
5107 // the version above, which takes a constant super_klass_slot.
5108 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
5109 Register r_super_klass,
5110 Register temp1,
5111 Register temp2,
5112 Register temp3,
5113 Register temp4,
5114 Register result) {
5115 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
5116 assert_different_registers(r_sub_klass, r_super_klass, rcx);
5117 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
5118
5119 Label L_fallthrough, L_success, L_failure;
5120
5121 BLOCK_COMMENT("lookup_secondary_supers_table {");
5122
5123 RegSetIterator<Register> available_regs = (temps - rcx).begin();
5124
5125 // FIXME. Once we are sure that all paths reaching this point really
5126 // do pass rcx as one of our temps we can get rid of the following
5127 // workaround.
5128 assert(temps.contains(rcx), "fix this code");
5129
5130 // We prefer to have our shift count in rcx. If rcx is one of our
5131 // temps, use it for slot. If not, pick any of our temps.
5132 Register slot;
5133 if (!temps.contains(rcx)) {
5134 slot = *available_regs++;
5135 } else {
5136 slot = rcx;
5137 }
5138
5139 const Register r_array_index = *available_regs++;
5140 const Register r_bitmap = *available_regs++;
5141
5142 // The logic above guarantees this property, but we state it here.
5143 assert_different_registers(r_array_index, r_bitmap, rcx);
5144
5145 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
5146 movq(r_array_index, r_bitmap);
5147
5148 // First check the bitmap to see if super_klass might be present. If
5149 // the bit is zero, we are certain that super_klass is not one of
5150 // the secondary supers.
5151 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
5152 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
5153 salq(r_array_index, slot);
5154
5155 testq(r_array_index, r_array_index);
5156 // We test the MSB of r_array_index, i.e. its sign bit
5157 jcc(Assembler::positive, L_failure);
5158
5159 const Register r_array_base = *available_regs++;
5160
5161 // Get the first array index that can contain super_klass into r_array_index.
5162 // Note: Clobbers r_array_base and slot.
5163 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
5164
5165 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5166
5167 // We will consult the secondary-super array.
5168 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5169
5170 // We're asserting that the first word in an Array<Klass*> is the
5171 // length, and the second word is the first word of the data. If
5172 // that ever changes, r_array_base will have to be adjusted here.
5173 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5174 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5175
5176 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5177 jccb(Assembler::equal, L_success);
5178
5179 // Restore slot to its true value
5180 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
5181
5182 // Linear probe. Rotate the bitmap so that the next bit to test is
5183 // in Bit 1.
5184 rorq(r_bitmap, slot);
5185
5186 // Is there another entry to check? Consult the bitmap.
5187 btq(r_bitmap, 1);
5188 jccb(Assembler::carryClear, L_failure);
5189
5190 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5191 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5192 // Kills: r_array_length.
5193 // Returns: result.
5194 lookup_secondary_supers_table_slow_path(r_super_klass,
5195 r_array_base,
5196 r_array_index,
5197 r_bitmap,
5198 /*temp1*/result,
5199 /*temp2*/slot,
5200 &L_success,
5201 nullptr);
5202
5203 bind(L_failure);
5204 movq(result, 1);
5205 jmpb(L_fallthrough);
5206
5207 bind(L_success);
5208 xorq(result, result); // = 0
5209
5210 bind(L_fallthrough);
5211 BLOCK_COMMENT("} lookup_secondary_supers_table");
5212
5213 if (VerifySecondarySupers) {
5214 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5215 temp1, temp2, temp3);
5216 }
5217 }
5218
5219 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
5220 Label* L_success, Label* L_failure) {
5221 Label L_loop, L_fallthrough;
5222 {
5223 int label_nulls = 0;
5224 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5225 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5226 assert(label_nulls <= 1, "at most one null in the batch");
5227 }
5228 bind(L_loop);
5229 cmpq(value, Address(addr, count, Address::times_8));
5230 jcc(Assembler::equal, *L_success);
5231 addl(count, 1);
5232 cmpl(count, limit);
5233 jcc(Assembler::less, L_loop);
5234
5235 if (&L_fallthrough != L_failure) {
5236 jmp(*L_failure);
5237 }
5238 bind(L_fallthrough);
5239 }
5240
5241 // Called by code generated by check_klass_subtype_slow_path
5242 // above. This is called when there is a collision in the hashed
5243 // lookup in the secondary supers array.
5244 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
5245 Register r_array_base,
5246 Register r_array_index,
5247 Register r_bitmap,
5248 Register temp1,
5249 Register temp2,
5250 Label* L_success,
5251 Label* L_failure) {
5252 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
5253
5254 const Register
5255 r_array_length = temp1,
5256 r_sub_klass = noreg,
5257 result = noreg;
5258
5259 Label L_fallthrough;
5260 int label_nulls = 0;
5261 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5262 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5263 assert(label_nulls <= 1, "at most one null in the batch");
5264
5265 // Load the array length.
5266 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5267 // And adjust the array base to point to the data.
5268 // NB! Effectively increments current slot index by 1.
5269 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
5270 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5271
5272 // Linear probe
5273 Label L_huge;
5274
5275 // The bitmap is full to bursting.
5276 // Implicit invariant: BITMAP_FULL implies (length > 0)
5277 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
5278 jcc(Assembler::greater, L_huge);
5279
5280 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
5281 // current slot (at secondary_supers[r_array_index]) has not yet
5282 // been inspected, and r_array_index may be out of bounds if we
5283 // wrapped around the end of the array.
5284
5285 { // This is conventional linear probing, but instead of terminating
5286 // when a null entry is found in the table, we maintain a bitmap
5287 // in which a 0 indicates missing entries.
5288 // The check above guarantees there are 0s in the bitmap, so the loop
5289 // eventually terminates.
5290
5291 xorl(temp2, temp2); // = 0;
5292
5293 Label L_again;
5294 bind(L_again);
5295
5296 // Check for array wraparound.
5297 cmpl(r_array_index, r_array_length);
5298 cmovl(Assembler::greaterEqual, r_array_index, temp2);
5299
5300 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5301 jcc(Assembler::equal, *L_success);
5302
5303 // If the next bit in bitmap is zero, we're done.
5304 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
5305 jcc(Assembler::carryClear, *L_failure);
5306
5307 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
5308 addl(r_array_index, 1);
5309
5310 jmp(L_again);
5311 }
5312
5313 { // Degenerate case: more than 64 secondary supers.
5314 // FIXME: We could do something smarter here, maybe a vectorized
5315 // comparison or a binary search, but is that worth any added
5316 // complexity?
5317 bind(L_huge);
5318 xorl(r_array_index, r_array_index); // = 0
5319 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
5320 L_success,
5321 (&L_fallthrough != L_failure ? L_failure : nullptr));
5322
5323 bind(L_fallthrough);
5324 }
5325 }
5326
5327 struct VerifyHelperArguments {
5328 Klass* _super;
5329 Klass* _sub;
5330 intptr_t _linear_result;
5331 intptr_t _table_result;
5332 };
5333
5334 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
5335 Klass::on_secondary_supers_verification_failure(args->_super,
5336 args->_sub,
5337 args->_linear_result,
5338 args->_table_result,
5339 msg);
5340 }
5341
5342 // Make sure that the hashed lookup and a linear scan agree.
5343 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
5344 Register r_super_klass,
5345 Register result,
5346 Register temp1,
5347 Register temp2,
5348 Register temp3) {
5349 const Register
5350 r_array_index = temp1,
5351 r_array_length = temp2,
5352 r_array_base = temp3,
5353 r_bitmap = noreg;
5354
5355 BLOCK_COMMENT("verify_secondary_supers_table {");
5356
5357 Label L_success, L_failure, L_check, L_done;
5358
5359 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5360 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5361 // And adjust the array base to point to the data.
5362 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5363
5364 testl(r_array_length, r_array_length); // array_length == 0?
5365 jcc(Assembler::zero, L_failure);
5366
5367 movl(r_array_index, 0);
5368 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
5369 // fall through to L_failure
5370
5371 const Register linear_result = r_array_index; // reuse temp1
5372
5373 bind(L_failure); // not present
5374 movl(linear_result, 1);
5375 jmp(L_check);
5376
5377 bind(L_success); // present
5378 movl(linear_result, 0);
5379
5380 bind(L_check);
5381 cmpl(linear_result, result);
5382 jcc(Assembler::equal, L_done);
5383
5384 { // To avoid calling convention issues, build a record on the stack
5385 // and pass the pointer to that instead.
5386 push(result);
5387 push(linear_result);
5388 push(r_sub_klass);
5389 push(r_super_klass);
5390 movptr(c_rarg1, rsp);
5391 movptr(c_rarg0, (uintptr_t) "mismatch");
5392 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
5393 should_not_reach_here();
5394 }
5395 bind(L_done);
5396
5397 BLOCK_COMMENT("} verify_secondary_supers_table");
5398 }
5399
5400 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
5401
5402 #endif // LP64
5403
5404 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
5405 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
5406
5407 Label L_fallthrough;
5408 if (L_fast_path == nullptr) {
5409 L_fast_path = &L_fallthrough;
5410 } else if (L_slow_path == nullptr) {
5411 L_slow_path = &L_fallthrough;
5412 }
5413
5414 // Fast path check: class is fully initialized.
5415 // init_state needs acquire, but x86 is TSO, and so we are already good.
5416 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
5417 jcc(Assembler::equal, *L_fast_path);
5418
5419 // Fast path check: current thread is initializer thread
5420 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
5421 if (L_slow_path == &L_fallthrough) {
5422 jcc(Assembler::equal, *L_fast_path);
5423 bind(*L_slow_path);
5424 } else if (L_fast_path == &L_fallthrough) {
5425 jcc(Assembler::notEqual, *L_slow_path);
5426 bind(*L_fast_path);
5427 } else {
5428 Unimplemented();
5429 }
5430 }
5431
5432 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5433 if (VM_Version::supports_cmov()) {
5434 cmovl(cc, dst, src);
5435 } else {
5436 Label L;
5437 jccb(negate_condition(cc), L);
5438 movl(dst, src);
5439 bind(L);
5440 }
5441 }
5442
5443 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5444 if (VM_Version::supports_cmov()) {
5445 cmovl(cc, dst, src);
5446 } else {
5447 Label L;
5448 jccb(negate_condition(cc), L);
5449 movl(dst, src);
5450 bind(L);
5451 }
5452 }
5453
5454 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
5455 if (!VerifyOops) return;
5456
5457 BLOCK_COMMENT("verify_oop {");
5458 #ifdef _LP64
5459 push(rscratch1);
5460 #endif
5461 push(rax); // save rax
5462 push(reg); // pass register argument
5463
5464 // Pass register number to verify_oop_subroutine
5465 const char* b = nullptr;
5466 {
5467 ResourceMark rm;
5468 stringStream ss;
5469 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5470 b = code_string(ss.as_string());
5471 }
5472 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5473 pushptr(buffer.addr(), rscratch1);
5474
5475 // call indirectly to solve generation ordering problem
5476 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5477 call(rax);
5478 // Caller pops the arguments (oop, message) and restores rax, r10
5479 BLOCK_COMMENT("} verify_oop");
5480 }
5481
5482 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
5483 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
5484 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
5485 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
5486 vpternlogd(dst, 0xFF, dst, dst, vector_len);
5487 } else if (VM_Version::supports_avx()) {
5488 vpcmpeqd(dst, dst, dst, vector_len);
5489 } else {
5490 pcmpeqd(dst, dst);
5491 }
5492 }
5493
5494 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5495 int extra_slot_offset) {
5496 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5497 int stackElementSize = Interpreter::stackElementSize;
5498 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5499 #ifdef ASSERT
5500 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5501 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5502 #endif
5503 Register scale_reg = noreg;
5504 Address::ScaleFactor scale_factor = Address::no_scale;
5505 if (arg_slot.is_constant()) {
5506 offset += arg_slot.as_constant() * stackElementSize;
5507 } else {
5508 scale_reg = arg_slot.as_register();
5509 scale_factor = Address::times(stackElementSize);
5510 }
5511 offset += wordSize; // return PC is on stack
5512 return Address(rsp, scale_reg, scale_factor, offset);
5513 }
5514
5515 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5516 if (!VerifyOops) return;
5517
5518 #ifdef _LP64
5519 push(rscratch1);
5520 #endif
5521 push(rax); // save rax,
5522 // addr may contain rsp so we will have to adjust it based on the push
5523 // we just did (and on 64 bit we do two pushes)
5524 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5525 // stores rax into addr which is backwards of what was intended.
5526 if (addr.uses(rsp)) {
5527 lea(rax, addr);
5528 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5529 } else {
5530 pushptr(addr);
5531 }
5532
5533 // Pass register number to verify_oop_subroutine
5534 const char* b = nullptr;
5535 {
5536 ResourceMark rm;
5537 stringStream ss;
5538 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5539 b = code_string(ss.as_string());
5540 }
5541 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5542 pushptr(buffer.addr(), rscratch1);
5543
5544 // call indirectly to solve generation ordering problem
5545 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5546 call(rax);
5547 // Caller pops the arguments (addr, message) and restores rax, r10.
5548 }
5549
5550 void MacroAssembler::verify_tlab() {
5551 #ifdef ASSERT
5552 if (UseTLAB && VerifyOops) {
5553 Label next, ok;
5554 Register t1 = rsi;
5555 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5556
5557 push(t1);
5558 NOT_LP64(push(thread_reg));
5559 NOT_LP64(get_thread(thread_reg));
5560
5561 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5562 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5563 jcc(Assembler::aboveEqual, next);
5564 STOP("assert(top >= start)");
5565 should_not_reach_here();
5566
5567 bind(next);
5568 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5569 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5570 jcc(Assembler::aboveEqual, ok);
5571 STOP("assert(top <= end)");
5572 should_not_reach_here();
5573
5574 bind(ok);
5575 NOT_LP64(pop(thread_reg));
5576 pop(t1);
5577 }
5578 #endif
5579 }
5580
5581 class ControlWord {
5582 public:
5583 int32_t _value;
5584
5585 int rounding_control() const { return (_value >> 10) & 3 ; }
5586 int precision_control() const { return (_value >> 8) & 3 ; }
5587 bool precision() const { return ((_value >> 5) & 1) != 0; }
5588 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5589 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5590 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5591 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5592 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5593
5594 void print() const {
5595 // rounding control
5596 const char* rc;
5597 switch (rounding_control()) {
5598 case 0: rc = "round near"; break;
5599 case 1: rc = "round down"; break;
5600 case 2: rc = "round up "; break;
5601 case 3: rc = "chop "; break;
5602 default:
5603 rc = nullptr; // silence compiler warnings
5604 fatal("Unknown rounding control: %d", rounding_control());
5605 };
5606 // precision control
5607 const char* pc;
5608 switch (precision_control()) {
5609 case 0: pc = "24 bits "; break;
5610 case 1: pc = "reserved"; break;
5611 case 2: pc = "53 bits "; break;
5612 case 3: pc = "64 bits "; break;
5613 default:
5614 pc = nullptr; // silence compiler warnings
5615 fatal("Unknown precision control: %d", precision_control());
5616 };
5617 // flags
5618 char f[9];
5619 f[0] = ' ';
5620 f[1] = ' ';
5621 f[2] = (precision ()) ? 'P' : 'p';
5622 f[3] = (underflow ()) ? 'U' : 'u';
5623 f[4] = (overflow ()) ? 'O' : 'o';
5624 f[5] = (zero_divide ()) ? 'Z' : 'z';
5625 f[6] = (denormalized()) ? 'D' : 'd';
5626 f[7] = (invalid ()) ? 'I' : 'i';
5627 f[8] = '\x0';
5628 // output
5629 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5630 }
5631
5632 };
5633
5634 class StatusWord {
5635 public:
5636 int32_t _value;
5637
5638 bool busy() const { return ((_value >> 15) & 1) != 0; }
5639 bool C3() const { return ((_value >> 14) & 1) != 0; }
5640 bool C2() const { return ((_value >> 10) & 1) != 0; }
5641 bool C1() const { return ((_value >> 9) & 1) != 0; }
5642 bool C0() const { return ((_value >> 8) & 1) != 0; }
5643 int top() const { return (_value >> 11) & 7 ; }
5644 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5645 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5646 bool precision() const { return ((_value >> 5) & 1) != 0; }
5647 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5648 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5649 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5650 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5651 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5652
5653 void print() const {
5654 // condition codes
5655 char c[5];
5656 c[0] = (C3()) ? '3' : '-';
5657 c[1] = (C2()) ? '2' : '-';
5658 c[2] = (C1()) ? '1' : '-';
5659 c[3] = (C0()) ? '0' : '-';
5660 c[4] = '\x0';
5661 // flags
5662 char f[9];
5663 f[0] = (error_status()) ? 'E' : '-';
5664 f[1] = (stack_fault ()) ? 'S' : '-';
5665 f[2] = (precision ()) ? 'P' : '-';
5666 f[3] = (underflow ()) ? 'U' : '-';
5667 f[4] = (overflow ()) ? 'O' : '-';
5668 f[5] = (zero_divide ()) ? 'Z' : '-';
5669 f[6] = (denormalized()) ? 'D' : '-';
5670 f[7] = (invalid ()) ? 'I' : '-';
5671 f[8] = '\x0';
5672 // output
5673 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5674 }
5675
5676 };
5677
5678 class TagWord {
5679 public:
5680 int32_t _value;
5681
5682 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5683
5684 void print() const {
5685 printf("%04x", _value & 0xFFFF);
5686 }
5687
5688 };
5689
5690 class FPU_Register {
5691 public:
5692 int32_t _m0;
5693 int32_t _m1;
5694 int16_t _ex;
5695
5696 bool is_indefinite() const {
5697 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5698 }
5699
5700 void print() const {
5701 char sign = (_ex < 0) ? '-' : '+';
5702 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5703 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5704 };
5705
5706 };
5707
5708 class FPU_State {
5709 public:
5710 enum {
5711 register_size = 10,
5712 number_of_registers = 8,
5713 register_mask = 7
5714 };
5715
5716 ControlWord _control_word;
5717 StatusWord _status_word;
5718 TagWord _tag_word;
5719 int32_t _error_offset;
5720 int32_t _error_selector;
5721 int32_t _data_offset;
5722 int32_t _data_selector;
5723 int8_t _register[register_size * number_of_registers];
5724
5725 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5726 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5727
5728 const char* tag_as_string(int tag) const {
5729 switch (tag) {
5730 case 0: return "valid";
5731 case 1: return "zero";
5732 case 2: return "special";
5733 case 3: return "empty";
5734 }
5735 ShouldNotReachHere();
5736 return nullptr;
5737 }
5738
5739 void print() const {
5740 // print computation registers
5741 { int t = _status_word.top();
5742 for (int i = 0; i < number_of_registers; i++) {
5743 int j = (i - t) & register_mask;
5744 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5745 st(j)->print();
5746 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5747 }
5748 }
5749 printf("\n");
5750 // print control registers
5751 printf("ctrl = "); _control_word.print(); printf("\n");
5752 printf("stat = "); _status_word .print(); printf("\n");
5753 printf("tags = "); _tag_word .print(); printf("\n");
5754 }
5755
5756 };
5757
5758 class Flag_Register {
5759 public:
5760 int32_t _value;
5761
5762 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5763 bool direction() const { return ((_value >> 10) & 1) != 0; }
5764 bool sign() const { return ((_value >> 7) & 1) != 0; }
5765 bool zero() const { return ((_value >> 6) & 1) != 0; }
5766 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5767 bool parity() const { return ((_value >> 2) & 1) != 0; }
5768 bool carry() const { return ((_value >> 0) & 1) != 0; }
5769
5770 void print() const {
5771 // flags
5772 char f[8];
5773 f[0] = (overflow ()) ? 'O' : '-';
5774 f[1] = (direction ()) ? 'D' : '-';
5775 f[2] = (sign ()) ? 'S' : '-';
5776 f[3] = (zero ()) ? 'Z' : '-';
5777 f[4] = (auxiliary_carry()) ? 'A' : '-';
5778 f[5] = (parity ()) ? 'P' : '-';
5779 f[6] = (carry ()) ? 'C' : '-';
5780 f[7] = '\x0';
5781 // output
5782 printf("%08x flags = %s", _value, f);
5783 }
5784
5785 };
5786
5787 class IU_Register {
5788 public:
5789 int32_t _value;
5790
5791 void print() const {
5792 printf("%08x %11d", _value, _value);
5793 }
5794
5795 };
5796
5797 class IU_State {
5798 public:
5799 Flag_Register _eflags;
5800 IU_Register _rdi;
5801 IU_Register _rsi;
5802 IU_Register _rbp;
5803 IU_Register _rsp;
5804 IU_Register _rbx;
5805 IU_Register _rdx;
5806 IU_Register _rcx;
5807 IU_Register _rax;
5808
5809 void print() const {
5810 // computation registers
5811 printf("rax, = "); _rax.print(); printf("\n");
5812 printf("rbx, = "); _rbx.print(); printf("\n");
5813 printf("rcx = "); _rcx.print(); printf("\n");
5814 printf("rdx = "); _rdx.print(); printf("\n");
5815 printf("rdi = "); _rdi.print(); printf("\n");
5816 printf("rsi = "); _rsi.print(); printf("\n");
5817 printf("rbp, = "); _rbp.print(); printf("\n");
5818 printf("rsp = "); _rsp.print(); printf("\n");
5819 printf("\n");
5820 // control registers
5821 printf("flgs = "); _eflags.print(); printf("\n");
5822 }
5823 };
5824
5825
5826 class CPU_State {
5827 public:
5828 FPU_State _fpu_state;
5829 IU_State _iu_state;
5830
5831 void print() const {
5832 printf("--------------------------------------------------\n");
5833 _iu_state .print();
5834 printf("\n");
5835 _fpu_state.print();
5836 printf("--------------------------------------------------\n");
5837 }
5838
5839 };
5840
5841
5842 static void _print_CPU_state(CPU_State* state) {
5843 state->print();
5844 };
5845
5846
5847 void MacroAssembler::print_CPU_state() {
5848 push_CPU_state();
5849 push(rsp); // pass CPU state
5850 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5851 addptr(rsp, wordSize); // discard argument
5852 pop_CPU_state();
5853 }
5854
5855
5856 #ifndef _LP64
5857 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5858 static int counter = 0;
5859 FPU_State* fs = &state->_fpu_state;
5860 counter++;
5861 // For leaf calls, only verify that the top few elements remain empty.
5862 // We only need 1 empty at the top for C2 code.
5863 if( stack_depth < 0 ) {
5864 if( fs->tag_for_st(7) != 3 ) {
5865 printf("FPR7 not empty\n");
5866 state->print();
5867 assert(false, "error");
5868 return false;
5869 }
5870 return true; // All other stack states do not matter
5871 }
5872
5873 assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
5874 "bad FPU control word");
5875
5876 // compute stack depth
5877 int i = 0;
5878 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5879 int d = i;
5880 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5881 // verify findings
5882 if (i != FPU_State::number_of_registers) {
5883 // stack not contiguous
5884 printf("%s: stack not contiguous at ST%d\n", s, i);
5885 state->print();
5886 assert(false, "error");
5887 return false;
5888 }
5889 // check if computed stack depth corresponds to expected stack depth
5890 if (stack_depth < 0) {
5891 // expected stack depth is -stack_depth or less
5892 if (d > -stack_depth) {
5893 // too many elements on the stack
5894 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5895 state->print();
5896 assert(false, "error");
5897 return false;
5898 }
5899 } else {
5900 // expected stack depth is stack_depth
5901 if (d != stack_depth) {
5902 // wrong stack depth
5903 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5904 state->print();
5905 assert(false, "error");
5906 return false;
5907 }
5908 }
5909 // everything is cool
5910 return true;
5911 }
5912
5913 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5914 if (!VerifyFPU) return;
5915 push_CPU_state();
5916 push(rsp); // pass CPU state
5917 ExternalAddress msg((address) s);
5918 // pass message string s
5919 pushptr(msg.addr(), noreg);
5920 push(stack_depth); // pass stack depth
5921 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5922 addptr(rsp, 3 * wordSize); // discard arguments
5923 // check for error
5924 { Label L;
5925 testl(rax, rax);
5926 jcc(Assembler::notZero, L);
5927 int3(); // break if error condition
5928 bind(L);
5929 }
5930 pop_CPU_state();
5931 }
5932 #endif // _LP64
5933
5934 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5935 // Either restore the MXCSR register after returning from the JNI Call
5936 // or verify that it wasn't changed (with -Xcheck:jni flag).
5937 if (VM_Version::supports_sse()) {
5938 if (RestoreMXCSROnJNICalls) {
5939 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5940 } else if (CheckJNICalls) {
5941 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5942 }
5943 }
5944 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5945 vzeroupper();
5946
5947 #ifndef _LP64
5948 // Either restore the x87 floating pointer control word after returning
5949 // from the JNI call or verify that it wasn't changed.
5950 if (CheckJNICalls) {
5951 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5952 }
5953 #endif // _LP64
5954 }
5955
5956 // ((OopHandle)result).resolve();
5957 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5958 assert_different_registers(result, tmp);
5959
5960 // Only 64 bit platforms support GCs that require a tmp register
5961 // Only IN_HEAP loads require a thread_tmp register
5962 // OopHandle::resolve is an indirection like jobject.
5963 access_load_at(T_OBJECT, IN_NATIVE,
5964 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5965 }
5966
5967 // ((WeakHandle)result).resolve();
5968 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5969 assert_different_registers(rresult, rtmp);
5970 Label resolved;
5971
5972 // A null weak handle resolves to null.
5973 cmpptr(rresult, 0);
5974 jcc(Assembler::equal, resolved);
5975
5976 // Only 64 bit platforms support GCs that require a tmp register
5977 // Only IN_HEAP loads require a thread_tmp register
5978 // WeakHandle::resolve is an indirection like jweak.
5979 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5980 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
5981 bind(resolved);
5982 }
5983
5984 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5985 // get mirror
5986 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5987 load_method_holder(mirror, method);
5988 movptr(mirror, Address(mirror, mirror_offset));
5989 resolve_oop_handle(mirror, tmp);
5990 }
5991
5992 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5993 load_method_holder(rresult, rmethod);
5994 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5995 }
5996
5997 void MacroAssembler::load_method_holder(Register holder, Register method) {
5998 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5999 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
6000 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
6001 }
6002
6003 #ifdef _LP64
6004 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
6005 assert(UseCompactObjectHeaders, "expect compact object headers");
6006 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
6007 shrq(dst, markWord::klass_shift);
6008 }
6009 #endif
6010
6011 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
6012 assert_different_registers(src, tmp);
6013 assert_different_registers(dst, tmp);
6014 #ifdef _LP64
6015 if (UseCompactObjectHeaders) {
6016 load_narrow_klass_compact(dst, src);
6017 decode_klass_not_null(dst, tmp);
6018 } else if (UseCompressedClassPointers) {
6019 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6020 decode_klass_not_null(dst, tmp);
6021 } else
6022 #endif
6023 {
6024 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6025 }
6026 }
6027
6028 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
6029 assert(!UseCompactObjectHeaders, "not with compact headers");
6030 assert_different_registers(src, tmp);
6031 assert_different_registers(dst, tmp);
6032 #ifdef _LP64
6033 if (UseCompressedClassPointers) {
6034 encode_klass_not_null(src, tmp);
6035 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6036 } else
6037 #endif
6038 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6039 }
6040
6041 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
6042 #ifdef _LP64
6043 if (UseCompactObjectHeaders) {
6044 assert(tmp != noreg, "need tmp");
6045 assert_different_registers(klass, obj, tmp);
6046 load_narrow_klass_compact(tmp, obj);
6047 cmpl(klass, tmp);
6048 } else if (UseCompressedClassPointers) {
6049 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
6050 } else
6051 #endif
6052 {
6053 cmpptr(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
6054 }
6055 }
6056
6057 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
6058 #ifdef _LP64
6059 if (UseCompactObjectHeaders) {
6060 assert(tmp2 != noreg, "need tmp2");
6061 assert_different_registers(obj1, obj2, tmp1, tmp2);
6062 load_narrow_klass_compact(tmp1, obj1);
6063 load_narrow_klass_compact(tmp2, obj2);
6064 cmpl(tmp1, tmp2);
6065 } else if (UseCompressedClassPointers) {
6066 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
6067 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
6068 } else
6069 #endif
6070 {
6071 movptr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
6072 cmpptr(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
6073 }
6074 }
6075
6076 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
6077 Register tmp1, Register thread_tmp) {
6078 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6079 decorators = AccessInternal::decorator_fixup(decorators, type);
6080 bool as_raw = (decorators & AS_RAW) != 0;
6081 if (as_raw) {
6082 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6083 } else {
6084 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6085 }
6086 }
6087
6088 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
6089 Register tmp1, Register tmp2, Register tmp3) {
6090 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6091 decorators = AccessInternal::decorator_fixup(decorators, type);
6092 bool as_raw = (decorators & AS_RAW) != 0;
6093 if (as_raw) {
6094 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6095 } else {
6096 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6097 }
6098 }
6099
6100 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
6101 Register thread_tmp, DecoratorSet decorators) {
6102 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
6103 }
6104
6105 // Doesn't do verification, generates fixed size code
6106 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
6107 Register thread_tmp, DecoratorSet decorators) {
6108 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
6109 }
6110
6111 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
6112 Register tmp2, Register tmp3, DecoratorSet decorators) {
6113 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
6114 }
6115
6116 // Used for storing nulls.
6117 void MacroAssembler::store_heap_oop_null(Address dst) {
6118 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
6119 }
6120
6121 #ifdef _LP64
6122 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6123 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
6124 if (UseCompressedClassPointers) {
6125 // Store to klass gap in destination
6126 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6127 }
6128 }
6129
6130 #ifdef ASSERT
6131 void MacroAssembler::verify_heapbase(const char* msg) {
6132 assert (UseCompressedOops, "should be compressed");
6133 assert (Universe::heap() != nullptr, "java heap should be initialized");
6134 if (CheckCompressedOops) {
6135 Label ok;
6136 ExternalAddress src2(CompressedOops::base_addr());
6137 const bool is_src2_reachable = reachable(src2);
6138 if (!is_src2_reachable) {
6139 push(rscratch1); // cmpptr trashes rscratch1
6140 }
6141 cmpptr(r12_heapbase, src2, rscratch1);
6142 jcc(Assembler::equal, ok);
6143 STOP(msg);
6144 bind(ok);
6145 if (!is_src2_reachable) {
6146 pop(rscratch1);
6147 }
6148 }
6149 }
6150 #endif
6151
6152 // Algorithm must match oop.inline.hpp encode_heap_oop.
6153 void MacroAssembler::encode_heap_oop(Register r) {
6154 #ifdef ASSERT
6155 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6156 #endif
6157 verify_oop_msg(r, "broken oop in encode_heap_oop");
6158 if (CompressedOops::base() == nullptr) {
6159 if (CompressedOops::shift() != 0) {
6160 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6161 shrq(r, LogMinObjAlignmentInBytes);
6162 }
6163 return;
6164 }
6165 testq(r, r);
6166 cmovq(Assembler::equal, r, r12_heapbase);
6167 subq(r, r12_heapbase);
6168 shrq(r, LogMinObjAlignmentInBytes);
6169 }
6170
6171 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6172 #ifdef ASSERT
6173 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6174 if (CheckCompressedOops) {
6175 Label ok;
6176 testq(r, r);
6177 jcc(Assembler::notEqual, ok);
6178 STOP("null oop passed to encode_heap_oop_not_null");
6179 bind(ok);
6180 }
6181 #endif
6182 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
6183 if (CompressedOops::base() != nullptr) {
6184 subq(r, r12_heapbase);
6185 }
6186 if (CompressedOops::shift() != 0) {
6187 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6188 shrq(r, LogMinObjAlignmentInBytes);
6189 }
6190 }
6191
6192 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6193 #ifdef ASSERT
6194 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6195 if (CheckCompressedOops) {
6196 Label ok;
6197 testq(src, src);
6198 jcc(Assembler::notEqual, ok);
6199 STOP("null oop passed to encode_heap_oop_not_null2");
6200 bind(ok);
6201 }
6202 #endif
6203 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
6204 if (dst != src) {
6205 movq(dst, src);
6206 }
6207 if (CompressedOops::base() != nullptr) {
6208 subq(dst, r12_heapbase);
6209 }
6210 if (CompressedOops::shift() != 0) {
6211 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6212 shrq(dst, LogMinObjAlignmentInBytes);
6213 }
6214 }
6215
6216 void MacroAssembler::decode_heap_oop(Register r) {
6217 #ifdef ASSERT
6218 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6219 #endif
6220 if (CompressedOops::base() == nullptr) {
6221 if (CompressedOops::shift() != 0) {
6222 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6223 shlq(r, LogMinObjAlignmentInBytes);
6224 }
6225 } else {
6226 Label done;
6227 shlq(r, LogMinObjAlignmentInBytes);
6228 jccb(Assembler::equal, done);
6229 addq(r, r12_heapbase);
6230 bind(done);
6231 }
6232 verify_oop_msg(r, "broken oop in decode_heap_oop");
6233 }
6234
6235 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6236 // Note: it will change flags
6237 assert (UseCompressedOops, "should only be used for compressed headers");
6238 assert (Universe::heap() != nullptr, "java heap should be initialized");
6239 // Cannot assert, unverified entry point counts instructions (see .ad file)
6240 // vtableStubs also counts instructions in pd_code_size_limit.
6241 // Also do not verify_oop as this is called by verify_oop.
6242 if (CompressedOops::shift() != 0) {
6243 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6244 shlq(r, LogMinObjAlignmentInBytes);
6245 if (CompressedOops::base() != nullptr) {
6246 addq(r, r12_heapbase);
6247 }
6248 } else {
6249 assert (CompressedOops::base() == nullptr, "sanity");
6250 }
6251 }
6252
6253 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6254 // Note: it will change flags
6255 assert (UseCompressedOops, "should only be used for compressed headers");
6256 assert (Universe::heap() != nullptr, "java heap should be initialized");
6257 // Cannot assert, unverified entry point counts instructions (see .ad file)
6258 // vtableStubs also counts instructions in pd_code_size_limit.
6259 // Also do not verify_oop as this is called by verify_oop.
6260 if (CompressedOops::shift() != 0) {
6261 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6262 if (LogMinObjAlignmentInBytes == Address::times_8) {
6263 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6264 } else {
6265 if (dst != src) {
6266 movq(dst, src);
6267 }
6268 shlq(dst, LogMinObjAlignmentInBytes);
6269 if (CompressedOops::base() != nullptr) {
6270 addq(dst, r12_heapbase);
6271 }
6272 }
6273 } else {
6274 assert (CompressedOops::base() == nullptr, "sanity");
6275 if (dst != src) {
6276 movq(dst, src);
6277 }
6278 }
6279 }
6280
6281 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
6282 assert_different_registers(r, tmp);
6283 if (CompressedKlassPointers::base() != nullptr) {
6284 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6285 subq(r, tmp);
6286 }
6287 if (CompressedKlassPointers::shift() != 0) {
6288 shrq(r, CompressedKlassPointers::shift());
6289 }
6290 }
6291
6292 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
6293 assert_different_registers(src, dst);
6294 if (CompressedKlassPointers::base() != nullptr) {
6295 mov64(dst, -(int64_t)CompressedKlassPointers::base());
6296 addq(dst, src);
6297 } else {
6298 movptr(dst, src);
6299 }
6300 if (CompressedKlassPointers::shift() != 0) {
6301 shrq(dst, CompressedKlassPointers::shift());
6302 }
6303 }
6304
6305 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
6306 assert_different_registers(r, tmp);
6307 // Note: it will change flags
6308 assert(UseCompressedClassPointers, "should only be used for compressed headers");
6309 // Cannot assert, unverified entry point counts instructions (see .ad file)
6310 // vtableStubs also counts instructions in pd_code_size_limit.
6311 // Also do not verify_oop as this is called by verify_oop.
6312 if (CompressedKlassPointers::shift() != 0) {
6313 shlq(r, CompressedKlassPointers::shift());
6314 }
6315 if (CompressedKlassPointers::base() != nullptr) {
6316 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6317 addq(r, tmp);
6318 }
6319 }
6320
6321 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
6322 assert_different_registers(src, dst);
6323 // Note: it will change flags
6324 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6325 // Cannot assert, unverified entry point counts instructions (see .ad file)
6326 // vtableStubs also counts instructions in pd_code_size_limit.
6327 // Also do not verify_oop as this is called by verify_oop.
6328
6329 if (CompressedKlassPointers::base() == nullptr &&
6330 CompressedKlassPointers::shift() == 0) {
6331 // The best case scenario is that there is no base or shift. Then it is already
6332 // a pointer that needs nothing but a register rename.
6333 movl(dst, src);
6334 } else {
6335 if (CompressedKlassPointers::shift() <= Address::times_8) {
6336 if (CompressedKlassPointers::base() != nullptr) {
6337 mov64(dst, (int64_t)CompressedKlassPointers::base());
6338 } else {
6339 xorq(dst, dst);
6340 }
6341 if (CompressedKlassPointers::shift() != 0) {
6342 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
6343 leaq(dst, Address(dst, src, Address::times_8, 0));
6344 } else {
6345 addq(dst, src);
6346 }
6347 } else {
6348 if (CompressedKlassPointers::base() != nullptr) {
6349 const uint64_t base_right_shifted =
6350 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
6351 mov64(dst, base_right_shifted);
6352 } else {
6353 xorq(dst, dst);
6354 }
6355 addq(dst, src);
6356 shlq(dst, CompressedKlassPointers::shift());
6357 }
6358 }
6359 }
6360
6361 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6362 assert (UseCompressedOops, "should only be used for compressed headers");
6363 assert (Universe::heap() != nullptr, "java heap should be initialized");
6364 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6365 int oop_index = oop_recorder()->find_index(obj);
6366 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6367 mov_narrow_oop(dst, oop_index, rspec);
6368 }
6369
6370 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6371 assert (UseCompressedOops, "should only be used for compressed headers");
6372 assert (Universe::heap() != nullptr, "java heap should be initialized");
6373 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6374 int oop_index = oop_recorder()->find_index(obj);
6375 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6376 mov_narrow_oop(dst, oop_index, rspec);
6377 }
6378
6379 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6380 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6381 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6382 int klass_index = oop_recorder()->find_index(k);
6383 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6384 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6385 }
6386
6387 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6388 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6389 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6390 int klass_index = oop_recorder()->find_index(k);
6391 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6392 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6393 }
6394
6395 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6396 assert (UseCompressedOops, "should only be used for compressed headers");
6397 assert (Universe::heap() != nullptr, "java heap should be initialized");
6398 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6399 int oop_index = oop_recorder()->find_index(obj);
6400 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6401 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6402 }
6403
6404 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6405 assert (UseCompressedOops, "should only be used for compressed headers");
6406 assert (Universe::heap() != nullptr, "java heap should be initialized");
6407 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6408 int oop_index = oop_recorder()->find_index(obj);
6409 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6410 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6411 }
6412
6413 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6414 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6415 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6416 int klass_index = oop_recorder()->find_index(k);
6417 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6418 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6419 }
6420
6421 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6422 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6423 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6424 int klass_index = oop_recorder()->find_index(k);
6425 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6426 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6427 }
6428
6429 void MacroAssembler::reinit_heapbase() {
6430 if (UseCompressedOops) {
6431 if (Universe::heap() != nullptr) {
6432 if (CompressedOops::base() == nullptr) {
6433 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6434 } else {
6435 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6436 }
6437 } else {
6438 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6439 }
6440 }
6441 }
6442
6443 #endif // _LP64
6444
6445 #if COMPILER2_OR_JVMCI
6446
6447 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6448 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6449 // cnt - number of qwords (8-byte words).
6450 // base - start address, qword aligned.
6451 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6452 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
6453 if (use64byteVector) {
6454 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
6455 } else if (MaxVectorSize >= 32) {
6456 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
6457 } else {
6458 pxor(xtmp, xtmp);
6459 }
6460 jmp(L_zero_64_bytes);
6461
6462 BIND(L_loop);
6463 if (MaxVectorSize >= 32) {
6464 fill64(base, 0, xtmp, use64byteVector);
6465 } else {
6466 movdqu(Address(base, 0), xtmp);
6467 movdqu(Address(base, 16), xtmp);
6468 movdqu(Address(base, 32), xtmp);
6469 movdqu(Address(base, 48), xtmp);
6470 }
6471 addptr(base, 64);
6472
6473 BIND(L_zero_64_bytes);
6474 subptr(cnt, 8);
6475 jccb(Assembler::greaterEqual, L_loop);
6476
6477 // Copy trailing 64 bytes
6478 if (use64byteVector) {
6479 addptr(cnt, 8);
6480 jccb(Assembler::equal, L_end);
6481 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
6482 jmp(L_end);
6483 } else {
6484 addptr(cnt, 4);
6485 jccb(Assembler::less, L_tail);
6486 if (MaxVectorSize >= 32) {
6487 vmovdqu(Address(base, 0), xtmp);
6488 } else {
6489 movdqu(Address(base, 0), xtmp);
6490 movdqu(Address(base, 16), xtmp);
6491 }
6492 }
6493 addptr(base, 32);
6494 subptr(cnt, 4);
6495
6496 BIND(L_tail);
6497 addptr(cnt, 4);
6498 jccb(Assembler::lessEqual, L_end);
6499 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6500 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
6501 } else {
6502 decrement(cnt);
6503
6504 BIND(L_sloop);
6505 movq(Address(base, 0), xtmp);
6506 addptr(base, 8);
6507 decrement(cnt);
6508 jccb(Assembler::greaterEqual, L_sloop);
6509 }
6510 BIND(L_end);
6511 }
6512
6513 // Clearing constant sized memory using YMM/ZMM registers.
6514 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6515 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6516 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
6517
6518 int vector64_count = (cnt & (~0x7)) >> 3;
6519 cnt = cnt & 0x7;
6520 const int fill64_per_loop = 4;
6521 const int max_unrolled_fill64 = 8;
6522
6523 // 64 byte initialization loop.
6524 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6525 int start64 = 0;
6526 if (vector64_count > max_unrolled_fill64) {
6527 Label LOOP;
6528 Register index = rtmp;
6529
6530 start64 = vector64_count - (vector64_count % fill64_per_loop);
6531
6532 movl(index, 0);
6533 BIND(LOOP);
6534 for (int i = 0; i < fill64_per_loop; i++) {
6535 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6536 }
6537 addl(index, fill64_per_loop * 64);
6538 cmpl(index, start64 * 64);
6539 jccb(Assembler::less, LOOP);
6540 }
6541 for (int i = start64; i < vector64_count; i++) {
6542 fill64(base, i * 64, xtmp, use64byteVector);
6543 }
6544
6545 // Clear remaining 64 byte tail.
6546 int disp = vector64_count * 64;
6547 if (cnt) {
6548 switch (cnt) {
6549 case 1:
6550 movq(Address(base, disp), xtmp);
6551 break;
6552 case 2:
6553 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6554 break;
6555 case 3:
6556 movl(rtmp, 0x7);
6557 kmovwl(mask, rtmp);
6558 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6559 break;
6560 case 4:
6561 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6562 break;
6563 case 5:
6564 if (use64byteVector) {
6565 movl(rtmp, 0x1F);
6566 kmovwl(mask, rtmp);
6567 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6568 } else {
6569 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6570 movq(Address(base, disp + 32), xtmp);
6571 }
6572 break;
6573 case 6:
6574 if (use64byteVector) {
6575 movl(rtmp, 0x3F);
6576 kmovwl(mask, rtmp);
6577 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6578 } else {
6579 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6580 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6581 }
6582 break;
6583 case 7:
6584 if (use64byteVector) {
6585 movl(rtmp, 0x7F);
6586 kmovwl(mask, rtmp);
6587 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6588 } else {
6589 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6590 movl(rtmp, 0x7);
6591 kmovwl(mask, rtmp);
6592 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6593 }
6594 break;
6595 default:
6596 fatal("Unexpected length : %d\n",cnt);
6597 break;
6598 }
6599 }
6600 }
6601
6602 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
6603 bool is_large, KRegister mask) {
6604 // cnt - number of qwords (8-byte words).
6605 // base - start address, qword aligned.
6606 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6607 assert(base==rdi, "base register must be edi for rep stos");
6608 assert(tmp==rax, "tmp register must be eax for rep stos");
6609 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6610 assert(InitArrayShortSize % BytesPerLong == 0,
6611 "InitArrayShortSize should be the multiple of BytesPerLong");
6612
6613 Label DONE;
6614 if (!is_large || !UseXMMForObjInit) {
6615 xorptr(tmp, tmp);
6616 }
6617
6618 if (!is_large) {
6619 Label LOOP, LONG;
6620 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6621 jccb(Assembler::greater, LONG);
6622
6623 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6624
6625 decrement(cnt);
6626 jccb(Assembler::negative, DONE); // Zero length
6627
6628 // Use individual pointer-sized stores for small counts:
6629 BIND(LOOP);
6630 movptr(Address(base, cnt, Address::times_ptr), tmp);
6631 decrement(cnt);
6632 jccb(Assembler::greaterEqual, LOOP);
6633 jmpb(DONE);
6634
6635 BIND(LONG);
6636 }
6637
6638 // Use longer rep-prefixed ops for non-small counts:
6639 if (UseFastStosb) {
6640 shlptr(cnt, 3); // convert to number of bytes
6641 rep_stosb();
6642 } else if (UseXMMForObjInit) {
6643 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
6644 } else {
6645 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6646 rep_stos();
6647 }
6648
6649 BIND(DONE);
6650 }
6651
6652 #endif //COMPILER2_OR_JVMCI
6653
6654
6655 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6656 Register to, Register value, Register count,
6657 Register rtmp, XMMRegister xtmp) {
6658 ShortBranchVerifier sbv(this);
6659 assert_different_registers(to, value, count, rtmp);
6660 Label L_exit;
6661 Label L_fill_2_bytes, L_fill_4_bytes;
6662
6663 #if defined(COMPILER2) && defined(_LP64)
6664 if(MaxVectorSize >=32 &&
6665 VM_Version::supports_avx512vlbw() &&
6666 VM_Version::supports_bmi2()) {
6667 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6668 return;
6669 }
6670 #endif
6671
6672 int shift = -1;
6673 switch (t) {
6674 case T_BYTE:
6675 shift = 2;
6676 break;
6677 case T_SHORT:
6678 shift = 1;
6679 break;
6680 case T_INT:
6681 shift = 0;
6682 break;
6683 default: ShouldNotReachHere();
6684 }
6685
6686 if (t == T_BYTE) {
6687 andl(value, 0xff);
6688 movl(rtmp, value);
6689 shll(rtmp, 8);
6690 orl(value, rtmp);
6691 }
6692 if (t == T_SHORT) {
6693 andl(value, 0xffff);
6694 }
6695 if (t == T_BYTE || t == T_SHORT) {
6696 movl(rtmp, value);
6697 shll(rtmp, 16);
6698 orl(value, rtmp);
6699 }
6700
6701 cmpptr(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
6702 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6703 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6704 Label L_skip_align2;
6705 // align source address at 4 bytes address boundary
6706 if (t == T_BYTE) {
6707 Label L_skip_align1;
6708 // One byte misalignment happens only for byte arrays
6709 testptr(to, 1);
6710 jccb(Assembler::zero, L_skip_align1);
6711 movb(Address(to, 0), value);
6712 increment(to);
6713 decrement(count);
6714 BIND(L_skip_align1);
6715 }
6716 // Two bytes misalignment happens only for byte and short (char) arrays
6717 testptr(to, 2);
6718 jccb(Assembler::zero, L_skip_align2);
6719 movw(Address(to, 0), value);
6720 addptr(to, 2);
6721 subptr(count, 1<<(shift-1));
6722 BIND(L_skip_align2);
6723 }
6724 if (UseSSE < 2) {
6725 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6726 // Fill 32-byte chunks
6727 subptr(count, 8 << shift);
6728 jcc(Assembler::less, L_check_fill_8_bytes);
6729 align(16);
6730
6731 BIND(L_fill_32_bytes_loop);
6732
6733 for (int i = 0; i < 32; i += 4) {
6734 movl(Address(to, i), value);
6735 }
6736
6737 addptr(to, 32);
6738 subptr(count, 8 << shift);
6739 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6740 BIND(L_check_fill_8_bytes);
6741 addptr(count, 8 << shift);
6742 jccb(Assembler::zero, L_exit);
6743 jmpb(L_fill_8_bytes);
6744
6745 //
6746 // length is too short, just fill qwords
6747 //
6748 BIND(L_fill_8_bytes_loop);
6749 movl(Address(to, 0), value);
6750 movl(Address(to, 4), value);
6751 addptr(to, 8);
6752 BIND(L_fill_8_bytes);
6753 subptr(count, 1 << (shift + 1));
6754 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6755 // fall through to fill 4 bytes
6756 } else {
6757 Label L_fill_32_bytes;
6758 if (!UseUnalignedLoadStores) {
6759 // align to 8 bytes, we know we are 4 byte aligned to start
6760 testptr(to, 4);
6761 jccb(Assembler::zero, L_fill_32_bytes);
6762 movl(Address(to, 0), value);
6763 addptr(to, 4);
6764 subptr(count, 1<<shift);
6765 }
6766 BIND(L_fill_32_bytes);
6767 {
6768 assert( UseSSE >= 2, "supported cpu only" );
6769 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6770 movdl(xtmp, value);
6771 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6772 Label L_check_fill_32_bytes;
6773 if (UseAVX > 2) {
6774 // Fill 64-byte chunks
6775 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6776
6777 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
6778 cmpptr(count, VM_Version::avx3_threshold());
6779 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6780
6781 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6782
6783 subptr(count, 16 << shift);
6784 jccb(Assembler::less, L_check_fill_32_bytes);
6785 align(16);
6786
6787 BIND(L_fill_64_bytes_loop_avx3);
6788 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6789 addptr(to, 64);
6790 subptr(count, 16 << shift);
6791 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6792 jmpb(L_check_fill_32_bytes);
6793
6794 BIND(L_check_fill_64_bytes_avx2);
6795 }
6796 // Fill 64-byte chunks
6797 Label L_fill_64_bytes_loop;
6798 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6799
6800 subptr(count, 16 << shift);
6801 jcc(Assembler::less, L_check_fill_32_bytes);
6802 align(16);
6803
6804 BIND(L_fill_64_bytes_loop);
6805 vmovdqu(Address(to, 0), xtmp);
6806 vmovdqu(Address(to, 32), xtmp);
6807 addptr(to, 64);
6808 subptr(count, 16 << shift);
6809 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6810
6811 BIND(L_check_fill_32_bytes);
6812 addptr(count, 8 << shift);
6813 jccb(Assembler::less, L_check_fill_8_bytes);
6814 vmovdqu(Address(to, 0), xtmp);
6815 addptr(to, 32);
6816 subptr(count, 8 << shift);
6817
6818 BIND(L_check_fill_8_bytes);
6819 // clean upper bits of YMM registers
6820 movdl(xtmp, value);
6821 pshufd(xtmp, xtmp, 0);
6822 } else {
6823 // Fill 32-byte chunks
6824 pshufd(xtmp, xtmp, 0);
6825
6826 subptr(count, 8 << shift);
6827 jcc(Assembler::less, L_check_fill_8_bytes);
6828 align(16);
6829
6830 BIND(L_fill_32_bytes_loop);
6831
6832 if (UseUnalignedLoadStores) {
6833 movdqu(Address(to, 0), xtmp);
6834 movdqu(Address(to, 16), xtmp);
6835 } else {
6836 movq(Address(to, 0), xtmp);
6837 movq(Address(to, 8), xtmp);
6838 movq(Address(to, 16), xtmp);
6839 movq(Address(to, 24), xtmp);
6840 }
6841
6842 addptr(to, 32);
6843 subptr(count, 8 << shift);
6844 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6845
6846 BIND(L_check_fill_8_bytes);
6847 }
6848 addptr(count, 8 << shift);
6849 jccb(Assembler::zero, L_exit);
6850 jmpb(L_fill_8_bytes);
6851
6852 //
6853 // length is too short, just fill qwords
6854 //
6855 BIND(L_fill_8_bytes_loop);
6856 movq(Address(to, 0), xtmp);
6857 addptr(to, 8);
6858 BIND(L_fill_8_bytes);
6859 subptr(count, 1 << (shift + 1));
6860 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6861 }
6862 }
6863 // fill trailing 4 bytes
6864 BIND(L_fill_4_bytes);
6865 testl(count, 1<<shift);
6866 jccb(Assembler::zero, L_fill_2_bytes);
6867 movl(Address(to, 0), value);
6868 if (t == T_BYTE || t == T_SHORT) {
6869 Label L_fill_byte;
6870 addptr(to, 4);
6871 BIND(L_fill_2_bytes);
6872 // fill trailing 2 bytes
6873 testl(count, 1<<(shift-1));
6874 jccb(Assembler::zero, L_fill_byte);
6875 movw(Address(to, 0), value);
6876 if (t == T_BYTE) {
6877 addptr(to, 2);
6878 BIND(L_fill_byte);
6879 // fill trailing byte
6880 testl(count, 1);
6881 jccb(Assembler::zero, L_exit);
6882 movb(Address(to, 0), value);
6883 } else {
6884 BIND(L_fill_byte);
6885 }
6886 } else {
6887 BIND(L_fill_2_bytes);
6888 }
6889 BIND(L_exit);
6890 }
6891
6892 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6893 switch(type) {
6894 case T_BYTE:
6895 case T_BOOLEAN:
6896 evpbroadcastb(dst, src, vector_len);
6897 break;
6898 case T_SHORT:
6899 case T_CHAR:
6900 evpbroadcastw(dst, src, vector_len);
6901 break;
6902 case T_INT:
6903 case T_FLOAT:
6904 evpbroadcastd(dst, src, vector_len);
6905 break;
6906 case T_LONG:
6907 case T_DOUBLE:
6908 evpbroadcastq(dst, src, vector_len);
6909 break;
6910 default:
6911 fatal("Unhandled type : %s", type2name(type));
6912 break;
6913 }
6914 }
6915
6916 // encode char[] to byte[] in ISO_8859_1 or ASCII
6917 //@IntrinsicCandidate
6918 //private static int implEncodeISOArray(byte[] sa, int sp,
6919 //byte[] da, int dp, int len) {
6920 // int i = 0;
6921 // for (; i < len; i++) {
6922 // char c = StringUTF16.getChar(sa, sp++);
6923 // if (c > '\u00FF')
6924 // break;
6925 // da[dp++] = (byte)c;
6926 // }
6927 // return i;
6928 //}
6929 //
6930 //@IntrinsicCandidate
6931 //private static int implEncodeAsciiArray(char[] sa, int sp,
6932 // byte[] da, int dp, int len) {
6933 // int i = 0;
6934 // for (; i < len; i++) {
6935 // char c = sa[sp++];
6936 // if (c >= '\u0080')
6937 // break;
6938 // da[dp++] = (byte)c;
6939 // }
6940 // return i;
6941 //}
6942 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6943 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6944 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6945 Register tmp5, Register result, bool ascii) {
6946
6947 // rsi: src
6948 // rdi: dst
6949 // rdx: len
6950 // rcx: tmp5
6951 // rax: result
6952 ShortBranchVerifier sbv(this);
6953 assert_different_registers(src, dst, len, tmp5, result);
6954 Label L_done, L_copy_1_char, L_copy_1_char_exit;
6955
6956 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
6957 int short_mask = ascii ? 0xff80 : 0xff00;
6958
6959 // set result
6960 xorl(result, result);
6961 // check for zero length
6962 testl(len, len);
6963 jcc(Assembler::zero, L_done);
6964
6965 movl(result, len);
6966
6967 // Setup pointers
6968 lea(src, Address(src, len, Address::times_2)); // char[]
6969 lea(dst, Address(dst, len, Address::times_1)); // byte[]
6970 negptr(len);
6971
6972 if (UseSSE42Intrinsics || UseAVX >= 2) {
6973 Label L_copy_8_chars, L_copy_8_chars_exit;
6974 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
6975
6976 if (UseAVX >= 2) {
6977 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
6978 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6979 movdl(tmp1Reg, tmp5);
6980 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
6981 jmp(L_chars_32_check);
6982
6983 bind(L_copy_32_chars);
6984 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
6985 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
6986 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6987 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6988 jccb(Assembler::notZero, L_copy_32_chars_exit);
6989 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6990 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
6991 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
6992
6993 bind(L_chars_32_check);
6994 addptr(len, 32);
6995 jcc(Assembler::lessEqual, L_copy_32_chars);
6996
6997 bind(L_copy_32_chars_exit);
6998 subptr(len, 16);
6999 jccb(Assembler::greater, L_copy_16_chars_exit);
7000
7001 } else if (UseSSE42Intrinsics) {
7002 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7003 movdl(tmp1Reg, tmp5);
7004 pshufd(tmp1Reg, tmp1Reg, 0);
7005 jmpb(L_chars_16_check);
7006 }
7007
7008 bind(L_copy_16_chars);
7009 if (UseAVX >= 2) {
7010 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7011 vptest(tmp2Reg, tmp1Reg);
7012 jcc(Assembler::notZero, L_copy_16_chars_exit);
7013 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7014 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7015 } else {
7016 if (UseAVX > 0) {
7017 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7018 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7019 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7020 } else {
7021 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7022 por(tmp2Reg, tmp3Reg);
7023 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7024 por(tmp2Reg, tmp4Reg);
7025 }
7026 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7027 jccb(Assembler::notZero, L_copy_16_chars_exit);
7028 packuswb(tmp3Reg, tmp4Reg);
7029 }
7030 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7031
7032 bind(L_chars_16_check);
7033 addptr(len, 16);
7034 jcc(Assembler::lessEqual, L_copy_16_chars);
7035
7036 bind(L_copy_16_chars_exit);
7037 if (UseAVX >= 2) {
7038 // clean upper bits of YMM registers
7039 vpxor(tmp2Reg, tmp2Reg);
7040 vpxor(tmp3Reg, tmp3Reg);
7041 vpxor(tmp4Reg, tmp4Reg);
7042 movdl(tmp1Reg, tmp5);
7043 pshufd(tmp1Reg, tmp1Reg, 0);
7044 }
7045 subptr(len, 8);
7046 jccb(Assembler::greater, L_copy_8_chars_exit);
7047
7048 bind(L_copy_8_chars);
7049 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7050 ptest(tmp3Reg, tmp1Reg);
7051 jccb(Assembler::notZero, L_copy_8_chars_exit);
7052 packuswb(tmp3Reg, tmp1Reg);
7053 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7054 addptr(len, 8);
7055 jccb(Assembler::lessEqual, L_copy_8_chars);
7056
7057 bind(L_copy_8_chars_exit);
7058 subptr(len, 8);
7059 jccb(Assembler::zero, L_done);
7060 }
7061
7062 bind(L_copy_1_char);
7063 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7064 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
7065 jccb(Assembler::notZero, L_copy_1_char_exit);
7066 movb(Address(dst, len, Address::times_1, 0), tmp5);
7067 addptr(len, 1);
7068 jccb(Assembler::less, L_copy_1_char);
7069
7070 bind(L_copy_1_char_exit);
7071 addptr(result, len); // len is negative count of not processed elements
7072
7073 bind(L_done);
7074 }
7075
7076 #ifdef _LP64
7077 /**
7078 * Helper for multiply_to_len().
7079 */
7080 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7081 addq(dest_lo, src1);
7082 adcq(dest_hi, 0);
7083 addq(dest_lo, src2);
7084 adcq(dest_hi, 0);
7085 }
7086
7087 /**
7088 * Multiply 64 bit by 64 bit first loop.
7089 */
7090 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7091 Register y, Register y_idx, Register z,
7092 Register carry, Register product,
7093 Register idx, Register kdx) {
7094 //
7095 // jlong carry, x[], y[], z[];
7096 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7097 // huge_128 product = y[idx] * x[xstart] + carry;
7098 // z[kdx] = (jlong)product;
7099 // carry = (jlong)(product >>> 64);
7100 // }
7101 // z[xstart] = carry;
7102 //
7103
7104 Label L_first_loop, L_first_loop_exit;
7105 Label L_one_x, L_one_y, L_multiply;
7106
7107 decrementl(xstart);
7108 jcc(Assembler::negative, L_one_x);
7109
7110 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7111 rorq(x_xstart, 32); // convert big-endian to little-endian
7112
7113 bind(L_first_loop);
7114 decrementl(idx);
7115 jcc(Assembler::negative, L_first_loop_exit);
7116 decrementl(idx);
7117 jcc(Assembler::negative, L_one_y);
7118 movq(y_idx, Address(y, idx, Address::times_4, 0));
7119 rorq(y_idx, 32); // convert big-endian to little-endian
7120 bind(L_multiply);
7121 movq(product, x_xstart);
7122 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7123 addq(product, carry);
7124 adcq(rdx, 0);
7125 subl(kdx, 2);
7126 movl(Address(z, kdx, Address::times_4, 4), product);
7127 shrq(product, 32);
7128 movl(Address(z, kdx, Address::times_4, 0), product);
7129 movq(carry, rdx);
7130 jmp(L_first_loop);
7131
7132 bind(L_one_y);
7133 movl(y_idx, Address(y, 0));
7134 jmp(L_multiply);
7135
7136 bind(L_one_x);
7137 movl(x_xstart, Address(x, 0));
7138 jmp(L_first_loop);
7139
7140 bind(L_first_loop_exit);
7141 }
7142
7143 /**
7144 * Multiply 64 bit by 64 bit and add 128 bit.
7145 */
7146 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7147 Register yz_idx, Register idx,
7148 Register carry, Register product, int offset) {
7149 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7150 // z[kdx] = (jlong)product;
7151
7152 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7153 rorq(yz_idx, 32); // convert big-endian to little-endian
7154 movq(product, x_xstart);
7155 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7156 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7157 rorq(yz_idx, 32); // convert big-endian to little-endian
7158
7159 add2_with_carry(rdx, product, carry, yz_idx);
7160
7161 movl(Address(z, idx, Address::times_4, offset+4), product);
7162 shrq(product, 32);
7163 movl(Address(z, idx, Address::times_4, offset), product);
7164
7165 }
7166
7167 /**
7168 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7169 */
7170 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7171 Register yz_idx, Register idx, Register jdx,
7172 Register carry, Register product,
7173 Register carry2) {
7174 // jlong carry, x[], y[], z[];
7175 // int kdx = ystart+1;
7176 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7177 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7178 // z[kdx+idx+1] = (jlong)product;
7179 // jlong carry2 = (jlong)(product >>> 64);
7180 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7181 // z[kdx+idx] = (jlong)product;
7182 // carry = (jlong)(product >>> 64);
7183 // }
7184 // idx += 2;
7185 // if (idx > 0) {
7186 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7187 // z[kdx+idx] = (jlong)product;
7188 // carry = (jlong)(product >>> 64);
7189 // }
7190 //
7191
7192 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7193
7194 movl(jdx, idx);
7195 andl(jdx, 0xFFFFFFFC);
7196 shrl(jdx, 2);
7197
7198 bind(L_third_loop);
7199 subl(jdx, 1);
7200 jcc(Assembler::negative, L_third_loop_exit);
7201 subl(idx, 4);
7202
7203 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7204 movq(carry2, rdx);
7205
7206 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7207 movq(carry, rdx);
7208 jmp(L_third_loop);
7209
7210 bind (L_third_loop_exit);
7211
7212 andl (idx, 0x3);
7213 jcc(Assembler::zero, L_post_third_loop_done);
7214
7215 Label L_check_1;
7216 subl(idx, 2);
7217 jcc(Assembler::negative, L_check_1);
7218
7219 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7220 movq(carry, rdx);
7221
7222 bind (L_check_1);
7223 addl (idx, 0x2);
7224 andl (idx, 0x1);
7225 subl(idx, 1);
7226 jcc(Assembler::negative, L_post_third_loop_done);
7227
7228 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7229 movq(product, x_xstart);
7230 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7231 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7232
7233 add2_with_carry(rdx, product, yz_idx, carry);
7234
7235 movl(Address(z, idx, Address::times_4, 0), product);
7236 shrq(product, 32);
7237
7238 shlq(rdx, 32);
7239 orq(product, rdx);
7240 movq(carry, product);
7241
7242 bind(L_post_third_loop_done);
7243 }
7244
7245 /**
7246 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7247 *
7248 */
7249 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7250 Register carry, Register carry2,
7251 Register idx, Register jdx,
7252 Register yz_idx1, Register yz_idx2,
7253 Register tmp, Register tmp3, Register tmp4) {
7254 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7255
7256 // jlong carry, x[], y[], z[];
7257 // int kdx = ystart+1;
7258 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7259 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7260 // jlong carry2 = (jlong)(tmp3 >>> 64);
7261 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7262 // carry = (jlong)(tmp4 >>> 64);
7263 // z[kdx+idx+1] = (jlong)tmp3;
7264 // z[kdx+idx] = (jlong)tmp4;
7265 // }
7266 // idx += 2;
7267 // if (idx > 0) {
7268 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7269 // z[kdx+idx] = (jlong)yz_idx1;
7270 // carry = (jlong)(yz_idx1 >>> 64);
7271 // }
7272 //
7273
7274 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7275
7276 movl(jdx, idx);
7277 andl(jdx, 0xFFFFFFFC);
7278 shrl(jdx, 2);
7279
7280 bind(L_third_loop);
7281 subl(jdx, 1);
7282 jcc(Assembler::negative, L_third_loop_exit);
7283 subl(idx, 4);
7284
7285 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7286 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7287 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7288 rorxq(yz_idx2, yz_idx2, 32);
7289
7290 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7291 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7292
7293 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7294 rorxq(yz_idx1, yz_idx1, 32);
7295 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7296 rorxq(yz_idx2, yz_idx2, 32);
7297
7298 if (VM_Version::supports_adx()) {
7299 adcxq(tmp3, carry);
7300 adoxq(tmp3, yz_idx1);
7301
7302 adcxq(tmp4, tmp);
7303 adoxq(tmp4, yz_idx2);
7304
7305 movl(carry, 0); // does not affect flags
7306 adcxq(carry2, carry);
7307 adoxq(carry2, carry);
7308 } else {
7309 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7310 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7311 }
7312 movq(carry, carry2);
7313
7314 movl(Address(z, idx, Address::times_4, 12), tmp3);
7315 shrq(tmp3, 32);
7316 movl(Address(z, idx, Address::times_4, 8), tmp3);
7317
7318 movl(Address(z, idx, Address::times_4, 4), tmp4);
7319 shrq(tmp4, 32);
7320 movl(Address(z, idx, Address::times_4, 0), tmp4);
7321
7322 jmp(L_third_loop);
7323
7324 bind (L_third_loop_exit);
7325
7326 andl (idx, 0x3);
7327 jcc(Assembler::zero, L_post_third_loop_done);
7328
7329 Label L_check_1;
7330 subl(idx, 2);
7331 jcc(Assembler::negative, L_check_1);
7332
7333 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7334 rorxq(yz_idx1, yz_idx1, 32);
7335 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7336 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7337 rorxq(yz_idx2, yz_idx2, 32);
7338
7339 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7340
7341 movl(Address(z, idx, Address::times_4, 4), tmp3);
7342 shrq(tmp3, 32);
7343 movl(Address(z, idx, Address::times_4, 0), tmp3);
7344 movq(carry, tmp4);
7345
7346 bind (L_check_1);
7347 addl (idx, 0x2);
7348 andl (idx, 0x1);
7349 subl(idx, 1);
7350 jcc(Assembler::negative, L_post_third_loop_done);
7351 movl(tmp4, Address(y, idx, Address::times_4, 0));
7352 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7353 movl(tmp4, Address(z, idx, Address::times_4, 0));
7354
7355 add2_with_carry(carry2, tmp3, tmp4, carry);
7356
7357 movl(Address(z, idx, Address::times_4, 0), tmp3);
7358 shrq(tmp3, 32);
7359
7360 shlq(carry2, 32);
7361 orq(tmp3, carry2);
7362 movq(carry, tmp3);
7363
7364 bind(L_post_third_loop_done);
7365 }
7366
7367 /**
7368 * Code for BigInteger::multiplyToLen() intrinsic.
7369 *
7370 * rdi: x
7371 * rax: xlen
7372 * rsi: y
7373 * rcx: ylen
7374 * r8: z
7375 * r11: tmp0
7376 * r12: tmp1
7377 * r13: tmp2
7378 * r14: tmp3
7379 * r15: tmp4
7380 * rbx: tmp5
7381 *
7382 */
7383 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7384 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7385 ShortBranchVerifier sbv(this);
7386 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7387
7388 push(tmp0);
7389 push(tmp1);
7390 push(tmp2);
7391 push(tmp3);
7392 push(tmp4);
7393 push(tmp5);
7394
7395 push(xlen);
7396
7397 const Register idx = tmp1;
7398 const Register kdx = tmp2;
7399 const Register xstart = tmp3;
7400
7401 const Register y_idx = tmp4;
7402 const Register carry = tmp5;
7403 const Register product = xlen;
7404 const Register x_xstart = tmp0;
7405
7406 // First Loop.
7407 //
7408 // final static long LONG_MASK = 0xffffffffL;
7409 // int xstart = xlen - 1;
7410 // int ystart = ylen - 1;
7411 // long carry = 0;
7412 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7413 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7414 // z[kdx] = (int)product;
7415 // carry = product >>> 32;
7416 // }
7417 // z[xstart] = (int)carry;
7418 //
7419
7420 movl(idx, ylen); // idx = ylen;
7421 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7422 xorq(carry, carry); // carry = 0;
7423
7424 Label L_done;
7425
7426 movl(xstart, xlen);
7427 decrementl(xstart);
7428 jcc(Assembler::negative, L_done);
7429
7430 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7431
7432 Label L_second_loop;
7433 testl(kdx, kdx);
7434 jcc(Assembler::zero, L_second_loop);
7435
7436 Label L_carry;
7437 subl(kdx, 1);
7438 jcc(Assembler::zero, L_carry);
7439
7440 movl(Address(z, kdx, Address::times_4, 0), carry);
7441 shrq(carry, 32);
7442 subl(kdx, 1);
7443
7444 bind(L_carry);
7445 movl(Address(z, kdx, Address::times_4, 0), carry);
7446
7447 // Second and third (nested) loops.
7448 //
7449 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7450 // carry = 0;
7451 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7452 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7453 // (z[k] & LONG_MASK) + carry;
7454 // z[k] = (int)product;
7455 // carry = product >>> 32;
7456 // }
7457 // z[i] = (int)carry;
7458 // }
7459 //
7460 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7461
7462 const Register jdx = tmp1;
7463
7464 bind(L_second_loop);
7465 xorl(carry, carry); // carry = 0;
7466 movl(jdx, ylen); // j = ystart+1
7467
7468 subl(xstart, 1); // i = xstart-1;
7469 jcc(Assembler::negative, L_done);
7470
7471 push (z);
7472
7473 Label L_last_x;
7474 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7475 subl(xstart, 1); // i = xstart-1;
7476 jcc(Assembler::negative, L_last_x);
7477
7478 if (UseBMI2Instructions) {
7479 movq(rdx, Address(x, xstart, Address::times_4, 0));
7480 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7481 } else {
7482 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7483 rorq(x_xstart, 32); // convert big-endian to little-endian
7484 }
7485
7486 Label L_third_loop_prologue;
7487 bind(L_third_loop_prologue);
7488
7489 push (x);
7490 push (xstart);
7491 push (ylen);
7492
7493
7494 if (UseBMI2Instructions) {
7495 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7496 } else { // !UseBMI2Instructions
7497 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7498 }
7499
7500 pop(ylen);
7501 pop(xlen);
7502 pop(x);
7503 pop(z);
7504
7505 movl(tmp3, xlen);
7506 addl(tmp3, 1);
7507 movl(Address(z, tmp3, Address::times_4, 0), carry);
7508 subl(tmp3, 1);
7509 jccb(Assembler::negative, L_done);
7510
7511 shrq(carry, 32);
7512 movl(Address(z, tmp3, Address::times_4, 0), carry);
7513 jmp(L_second_loop);
7514
7515 // Next infrequent code is moved outside loops.
7516 bind(L_last_x);
7517 if (UseBMI2Instructions) {
7518 movl(rdx, Address(x, 0));
7519 } else {
7520 movl(x_xstart, Address(x, 0));
7521 }
7522 jmp(L_third_loop_prologue);
7523
7524 bind(L_done);
7525
7526 pop(xlen);
7527
7528 pop(tmp5);
7529 pop(tmp4);
7530 pop(tmp3);
7531 pop(tmp2);
7532 pop(tmp1);
7533 pop(tmp0);
7534 }
7535
7536 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7537 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7538 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7539 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7540 Label VECTOR8_TAIL, VECTOR4_TAIL;
7541 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7542 Label SAME_TILL_END, DONE;
7543 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7544
7545 //scale is in rcx in both Win64 and Unix
7546 ShortBranchVerifier sbv(this);
7547
7548 shlq(length);
7549 xorq(result, result);
7550
7551 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7552 VM_Version::supports_avx512vlbw()) {
7553 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7554
7555 cmpq(length, 64);
7556 jcc(Assembler::less, VECTOR32_TAIL);
7557
7558 movq(tmp1, length);
7559 andq(tmp1, 0x3F); // tail count
7560 andq(length, ~(0x3F)); //vector count
7561
7562 bind(VECTOR64_LOOP);
7563 // AVX512 code to compare 64 byte vectors.
7564 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7565 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7566 kortestql(k7, k7);
7567 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7568 addq(result, 64);
7569 subq(length, 64);
7570 jccb(Assembler::notZero, VECTOR64_LOOP);
7571
7572 //bind(VECTOR64_TAIL);
7573 testq(tmp1, tmp1);
7574 jcc(Assembler::zero, SAME_TILL_END);
7575
7576 //bind(VECTOR64_TAIL);
7577 // AVX512 code to compare up to 63 byte vectors.
7578 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7579 shlxq(tmp2, tmp2, tmp1);
7580 notq(tmp2);
7581 kmovql(k3, tmp2);
7582
7583 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7584 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7585
7586 ktestql(k7, k3);
7587 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7588
7589 bind(VECTOR64_NOT_EQUAL);
7590 kmovql(tmp1, k7);
7591 notq(tmp1);
7592 tzcntq(tmp1, tmp1);
7593 addq(result, tmp1);
7594 shrq(result);
7595 jmp(DONE);
7596 bind(VECTOR32_TAIL);
7597 }
7598
7599 cmpq(length, 8);
7600 jcc(Assembler::equal, VECTOR8_LOOP);
7601 jcc(Assembler::less, VECTOR4_TAIL);
7602
7603 if (UseAVX >= 2) {
7604 Label VECTOR16_TAIL, VECTOR32_LOOP;
7605
7606 cmpq(length, 16);
7607 jcc(Assembler::equal, VECTOR16_LOOP);
7608 jcc(Assembler::less, VECTOR8_LOOP);
7609
7610 cmpq(length, 32);
7611 jccb(Assembler::less, VECTOR16_TAIL);
7612
7613 subq(length, 32);
7614 bind(VECTOR32_LOOP);
7615 vmovdqu(rymm0, Address(obja, result));
7616 vmovdqu(rymm1, Address(objb, result));
7617 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7618 vptest(rymm2, rymm2);
7619 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7620 addq(result, 32);
7621 subq(length, 32);
7622 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7623 addq(length, 32);
7624 jcc(Assembler::equal, SAME_TILL_END);
7625 //falling through if less than 32 bytes left //close the branch here.
7626
7627 bind(VECTOR16_TAIL);
7628 cmpq(length, 16);
7629 jccb(Assembler::less, VECTOR8_TAIL);
7630 bind(VECTOR16_LOOP);
7631 movdqu(rymm0, Address(obja, result));
7632 movdqu(rymm1, Address(objb, result));
7633 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7634 ptest(rymm2, rymm2);
7635 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7636 addq(result, 16);
7637 subq(length, 16);
7638 jcc(Assembler::equal, SAME_TILL_END);
7639 //falling through if less than 16 bytes left
7640 } else {//regular intrinsics
7641
7642 cmpq(length, 16);
7643 jccb(Assembler::less, VECTOR8_TAIL);
7644
7645 subq(length, 16);
7646 bind(VECTOR16_LOOP);
7647 movdqu(rymm0, Address(obja, result));
7648 movdqu(rymm1, Address(objb, result));
7649 pxor(rymm0, rymm1);
7650 ptest(rymm0, rymm0);
7651 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7652 addq(result, 16);
7653 subq(length, 16);
7654 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7655 addq(length, 16);
7656 jcc(Assembler::equal, SAME_TILL_END);
7657 //falling through if less than 16 bytes left
7658 }
7659
7660 bind(VECTOR8_TAIL);
7661 cmpq(length, 8);
7662 jccb(Assembler::less, VECTOR4_TAIL);
7663 bind(VECTOR8_LOOP);
7664 movq(tmp1, Address(obja, result));
7665 movq(tmp2, Address(objb, result));
7666 xorq(tmp1, tmp2);
7667 testq(tmp1, tmp1);
7668 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7669 addq(result, 8);
7670 subq(length, 8);
7671 jcc(Assembler::equal, SAME_TILL_END);
7672 //falling through if less than 8 bytes left
7673
7674 bind(VECTOR4_TAIL);
7675 cmpq(length, 4);
7676 jccb(Assembler::less, BYTES_TAIL);
7677 bind(VECTOR4_LOOP);
7678 movl(tmp1, Address(obja, result));
7679 xorl(tmp1, Address(objb, result));
7680 testl(tmp1, tmp1);
7681 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7682 addq(result, 4);
7683 subq(length, 4);
7684 jcc(Assembler::equal, SAME_TILL_END);
7685 //falling through if less than 4 bytes left
7686
7687 bind(BYTES_TAIL);
7688 bind(BYTES_LOOP);
7689 load_unsigned_byte(tmp1, Address(obja, result));
7690 load_unsigned_byte(tmp2, Address(objb, result));
7691 xorl(tmp1, tmp2);
7692 testl(tmp1, tmp1);
7693 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7694 decq(length);
7695 jcc(Assembler::zero, SAME_TILL_END);
7696 incq(result);
7697 load_unsigned_byte(tmp1, Address(obja, result));
7698 load_unsigned_byte(tmp2, Address(objb, result));
7699 xorl(tmp1, tmp2);
7700 testl(tmp1, tmp1);
7701 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7702 decq(length);
7703 jcc(Assembler::zero, SAME_TILL_END);
7704 incq(result);
7705 load_unsigned_byte(tmp1, Address(obja, result));
7706 load_unsigned_byte(tmp2, Address(objb, result));
7707 xorl(tmp1, tmp2);
7708 testl(tmp1, tmp1);
7709 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7710 jmp(SAME_TILL_END);
7711
7712 if (UseAVX >= 2) {
7713 bind(VECTOR32_NOT_EQUAL);
7714 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7715 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7716 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7717 vpmovmskb(tmp1, rymm0);
7718 bsfq(tmp1, tmp1);
7719 addq(result, tmp1);
7720 shrq(result);
7721 jmp(DONE);
7722 }
7723
7724 bind(VECTOR16_NOT_EQUAL);
7725 if (UseAVX >= 2) {
7726 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7727 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7728 pxor(rymm0, rymm2);
7729 } else {
7730 pcmpeqb(rymm2, rymm2);
7731 pxor(rymm0, rymm1);
7732 pcmpeqb(rymm0, rymm1);
7733 pxor(rymm0, rymm2);
7734 }
7735 pmovmskb(tmp1, rymm0);
7736 bsfq(tmp1, tmp1);
7737 addq(result, tmp1);
7738 shrq(result);
7739 jmpb(DONE);
7740
7741 bind(VECTOR8_NOT_EQUAL);
7742 bind(VECTOR4_NOT_EQUAL);
7743 bsfq(tmp1, tmp1);
7744 shrq(tmp1, 3);
7745 addq(result, tmp1);
7746 bind(BYTES_NOT_EQUAL);
7747 shrq(result);
7748 jmpb(DONE);
7749
7750 bind(SAME_TILL_END);
7751 mov64(result, -1);
7752
7753 bind(DONE);
7754 }
7755
7756 //Helper functions for square_to_len()
7757
7758 /**
7759 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7760 * Preserves x and z and modifies rest of the registers.
7761 */
7762 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7763 // Perform square and right shift by 1
7764 // Handle odd xlen case first, then for even xlen do the following
7765 // jlong carry = 0;
7766 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7767 // huge_128 product = x[j:j+1] * x[j:j+1];
7768 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7769 // z[i+2:i+3] = (jlong)(product >>> 1);
7770 // carry = (jlong)product;
7771 // }
7772
7773 xorq(tmp5, tmp5); // carry
7774 xorq(rdxReg, rdxReg);
7775 xorl(tmp1, tmp1); // index for x
7776 xorl(tmp4, tmp4); // index for z
7777
7778 Label L_first_loop, L_first_loop_exit;
7779
7780 testl(xlen, 1);
7781 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7782
7783 // Square and right shift by 1 the odd element using 32 bit multiply
7784 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7785 imulq(raxReg, raxReg);
7786 shrq(raxReg, 1);
7787 adcq(tmp5, 0);
7788 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7789 incrementl(tmp1);
7790 addl(tmp4, 2);
7791
7792 // Square and right shift by 1 the rest using 64 bit multiply
7793 bind(L_first_loop);
7794 cmpptr(tmp1, xlen);
7795 jccb(Assembler::equal, L_first_loop_exit);
7796
7797 // Square
7798 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7799 rorq(raxReg, 32); // convert big-endian to little-endian
7800 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7801
7802 // Right shift by 1 and save carry
7803 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7804 rcrq(rdxReg, 1);
7805 rcrq(raxReg, 1);
7806 adcq(tmp5, 0);
7807
7808 // Store result in z
7809 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7810 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7811
7812 // Update indices for x and z
7813 addl(tmp1, 2);
7814 addl(tmp4, 4);
7815 jmp(L_first_loop);
7816
7817 bind(L_first_loop_exit);
7818 }
7819
7820
7821 /**
7822 * Perform the following multiply add operation using BMI2 instructions
7823 * carry:sum = sum + op1*op2 + carry
7824 * op2 should be in rdx
7825 * op2 is preserved, all other registers are modified
7826 */
7827 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7828 // assert op2 is rdx
7829 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7830 addq(sum, carry);
7831 adcq(tmp2, 0);
7832 addq(sum, op1);
7833 adcq(tmp2, 0);
7834 movq(carry, tmp2);
7835 }
7836
7837 /**
7838 * Perform the following multiply add operation:
7839 * carry:sum = sum + op1*op2 + carry
7840 * Preserves op1, op2 and modifies rest of registers
7841 */
7842 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7843 // rdx:rax = op1 * op2
7844 movq(raxReg, op2);
7845 mulq(op1);
7846
7847 // rdx:rax = sum + carry + rdx:rax
7848 addq(sum, carry);
7849 adcq(rdxReg, 0);
7850 addq(sum, raxReg);
7851 adcq(rdxReg, 0);
7852
7853 // carry:sum = rdx:sum
7854 movq(carry, rdxReg);
7855 }
7856
7857 /**
7858 * Add 64 bit long carry into z[] with carry propagation.
7859 * Preserves z and carry register values and modifies rest of registers.
7860 *
7861 */
7862 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7863 Label L_fourth_loop, L_fourth_loop_exit;
7864
7865 movl(tmp1, 1);
7866 subl(zlen, 2);
7867 addq(Address(z, zlen, Address::times_4, 0), carry);
7868
7869 bind(L_fourth_loop);
7870 jccb(Assembler::carryClear, L_fourth_loop_exit);
7871 subl(zlen, 2);
7872 jccb(Assembler::negative, L_fourth_loop_exit);
7873 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7874 jmp(L_fourth_loop);
7875 bind(L_fourth_loop_exit);
7876 }
7877
7878 /**
7879 * Shift z[] left by 1 bit.
7880 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7881 *
7882 */
7883 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7884
7885 Label L_fifth_loop, L_fifth_loop_exit;
7886
7887 // Fifth loop
7888 // Perform primitiveLeftShift(z, zlen, 1)
7889
7890 const Register prev_carry = tmp1;
7891 const Register new_carry = tmp4;
7892 const Register value = tmp2;
7893 const Register zidx = tmp3;
7894
7895 // int zidx, carry;
7896 // long value;
7897 // carry = 0;
7898 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7899 // (carry:value) = (z[i] << 1) | carry ;
7900 // z[i] = value;
7901 // }
7902
7903 movl(zidx, zlen);
7904 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7905
7906 bind(L_fifth_loop);
7907 decl(zidx); // Use decl to preserve carry flag
7908 decl(zidx);
7909 jccb(Assembler::negative, L_fifth_loop_exit);
7910
7911 if (UseBMI2Instructions) {
7912 movq(value, Address(z, zidx, Address::times_4, 0));
7913 rclq(value, 1);
7914 rorxq(value, value, 32);
7915 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7916 }
7917 else {
7918 // clear new_carry
7919 xorl(new_carry, new_carry);
7920
7921 // Shift z[i] by 1, or in previous carry and save new carry
7922 movq(value, Address(z, zidx, Address::times_4, 0));
7923 shlq(value, 1);
7924 adcl(new_carry, 0);
7925
7926 orq(value, prev_carry);
7927 rorq(value, 0x20);
7928 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7929
7930 // Set previous carry = new carry
7931 movl(prev_carry, new_carry);
7932 }
7933 jmp(L_fifth_loop);
7934
7935 bind(L_fifth_loop_exit);
7936 }
7937
7938
7939 /**
7940 * Code for BigInteger::squareToLen() intrinsic
7941 *
7942 * rdi: x
7943 * rsi: len
7944 * r8: z
7945 * rcx: zlen
7946 * r12: tmp1
7947 * r13: tmp2
7948 * r14: tmp3
7949 * r15: tmp4
7950 * rbx: tmp5
7951 *
7952 */
7953 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7954
7955 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
7956 push(tmp1);
7957 push(tmp2);
7958 push(tmp3);
7959 push(tmp4);
7960 push(tmp5);
7961
7962 // First loop
7963 // Store the squares, right shifted one bit (i.e., divided by 2).
7964 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7965
7966 // Add in off-diagonal sums.
7967 //
7968 // Second, third (nested) and fourth loops.
7969 // zlen +=2;
7970 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7971 // carry = 0;
7972 // long op2 = x[xidx:xidx+1];
7973 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7974 // k -= 2;
7975 // long op1 = x[j:j+1];
7976 // long sum = z[k:k+1];
7977 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7978 // z[k:k+1] = sum;
7979 // }
7980 // add_one_64(z, k, carry, tmp_regs);
7981 // }
7982
7983 const Register carry = tmp5;
7984 const Register sum = tmp3;
7985 const Register op1 = tmp4;
7986 Register op2 = tmp2;
7987
7988 push(zlen);
7989 push(len);
7990 addl(zlen,2);
7991 bind(L_second_loop);
7992 xorq(carry, carry);
7993 subl(zlen, 4);
7994 subl(len, 2);
7995 push(zlen);
7996 push(len);
7997 cmpl(len, 0);
7998 jccb(Assembler::lessEqual, L_second_loop_exit);
7999
8000 // Multiply an array by one 64 bit long.
8001 if (UseBMI2Instructions) {
8002 op2 = rdxReg;
8003 movq(op2, Address(x, len, Address::times_4, 0));
8004 rorxq(op2, op2, 32);
8005 }
8006 else {
8007 movq(op2, Address(x, len, Address::times_4, 0));
8008 rorq(op2, 32);
8009 }
8010
8011 bind(L_third_loop);
8012 decrementl(len);
8013 jccb(Assembler::negative, L_third_loop_exit);
8014 decrementl(len);
8015 jccb(Assembler::negative, L_last_x);
8016
8017 movq(op1, Address(x, len, Address::times_4, 0));
8018 rorq(op1, 32);
8019
8020 bind(L_multiply);
8021 subl(zlen, 2);
8022 movq(sum, Address(z, zlen, Address::times_4, 0));
8023
8024 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8025 if (UseBMI2Instructions) {
8026 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8027 }
8028 else {
8029 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8030 }
8031
8032 movq(Address(z, zlen, Address::times_4, 0), sum);
8033
8034 jmp(L_third_loop);
8035 bind(L_third_loop_exit);
8036
8037 // Fourth loop
8038 // Add 64 bit long carry into z with carry propagation.
8039 // Uses offsetted zlen.
8040 add_one_64(z, zlen, carry, tmp1);
8041
8042 pop(len);
8043 pop(zlen);
8044 jmp(L_second_loop);
8045
8046 // Next infrequent code is moved outside loops.
8047 bind(L_last_x);
8048 movl(op1, Address(x, 0));
8049 jmp(L_multiply);
8050
8051 bind(L_second_loop_exit);
8052 pop(len);
8053 pop(zlen);
8054 pop(len);
8055 pop(zlen);
8056
8057 // Fifth loop
8058 // Shift z left 1 bit.
8059 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8060
8061 // z[zlen-1] |= x[len-1] & 1;
8062 movl(tmp3, Address(x, len, Address::times_4, -4));
8063 andl(tmp3, 1);
8064 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8065
8066 pop(tmp5);
8067 pop(tmp4);
8068 pop(tmp3);
8069 pop(tmp2);
8070 pop(tmp1);
8071 }
8072
8073 /**
8074 * Helper function for mul_add()
8075 * Multiply the in[] by int k and add to out[] starting at offset offs using
8076 * 128 bit by 32 bit multiply and return the carry in tmp5.
8077 * Only quad int aligned length of in[] is operated on in this function.
8078 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8079 * This function preserves out, in and k registers.
8080 * len and offset point to the appropriate index in "in" & "out" correspondingly
8081 * tmp5 has the carry.
8082 * other registers are temporary and are modified.
8083 *
8084 */
8085 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8086 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8087 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8088
8089 Label L_first_loop, L_first_loop_exit;
8090
8091 movl(tmp1, len);
8092 shrl(tmp1, 2);
8093
8094 bind(L_first_loop);
8095 subl(tmp1, 1);
8096 jccb(Assembler::negative, L_first_loop_exit);
8097
8098 subl(len, 4);
8099 subl(offset, 4);
8100
8101 Register op2 = tmp2;
8102 const Register sum = tmp3;
8103 const Register op1 = tmp4;
8104 const Register carry = tmp5;
8105
8106 if (UseBMI2Instructions) {
8107 op2 = rdxReg;
8108 }
8109
8110 movq(op1, Address(in, len, Address::times_4, 8));
8111 rorq(op1, 32);
8112 movq(sum, Address(out, offset, Address::times_4, 8));
8113 rorq(sum, 32);
8114 if (UseBMI2Instructions) {
8115 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8116 }
8117 else {
8118 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8119 }
8120 // Store back in big endian from little endian
8121 rorq(sum, 0x20);
8122 movq(Address(out, offset, Address::times_4, 8), sum);
8123
8124 movq(op1, Address(in, len, Address::times_4, 0));
8125 rorq(op1, 32);
8126 movq(sum, Address(out, offset, Address::times_4, 0));
8127 rorq(sum, 32);
8128 if (UseBMI2Instructions) {
8129 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8130 }
8131 else {
8132 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8133 }
8134 // Store back in big endian from little endian
8135 rorq(sum, 0x20);
8136 movq(Address(out, offset, Address::times_4, 0), sum);
8137
8138 jmp(L_first_loop);
8139 bind(L_first_loop_exit);
8140 }
8141
8142 /**
8143 * Code for BigInteger::mulAdd() intrinsic
8144 *
8145 * rdi: out
8146 * rsi: in
8147 * r11: offs (out.length - offset)
8148 * rcx: len
8149 * r8: k
8150 * r12: tmp1
8151 * r13: tmp2
8152 * r14: tmp3
8153 * r15: tmp4
8154 * rbx: tmp5
8155 * Multiply the in[] by word k and add to out[], return the carry in rax
8156 */
8157 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8158 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8159 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8160
8161 Label L_carry, L_last_in, L_done;
8162
8163 // carry = 0;
8164 // for (int j=len-1; j >= 0; j--) {
8165 // long product = (in[j] & LONG_MASK) * kLong +
8166 // (out[offs] & LONG_MASK) + carry;
8167 // out[offs--] = (int)product;
8168 // carry = product >>> 32;
8169 // }
8170 //
8171 push(tmp1);
8172 push(tmp2);
8173 push(tmp3);
8174 push(tmp4);
8175 push(tmp5);
8176
8177 Register op2 = tmp2;
8178 const Register sum = tmp3;
8179 const Register op1 = tmp4;
8180 const Register carry = tmp5;
8181
8182 if (UseBMI2Instructions) {
8183 op2 = rdxReg;
8184 movl(op2, k);
8185 }
8186 else {
8187 movl(op2, k);
8188 }
8189
8190 xorq(carry, carry);
8191
8192 //First loop
8193
8194 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8195 //The carry is in tmp5
8196 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8197
8198 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8199 decrementl(len);
8200 jccb(Assembler::negative, L_carry);
8201 decrementl(len);
8202 jccb(Assembler::negative, L_last_in);
8203
8204 movq(op1, Address(in, len, Address::times_4, 0));
8205 rorq(op1, 32);
8206
8207 subl(offs, 2);
8208 movq(sum, Address(out, offs, Address::times_4, 0));
8209 rorq(sum, 32);
8210
8211 if (UseBMI2Instructions) {
8212 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8213 }
8214 else {
8215 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8216 }
8217
8218 // Store back in big endian from little endian
8219 rorq(sum, 0x20);
8220 movq(Address(out, offs, Address::times_4, 0), sum);
8221
8222 testl(len, len);
8223 jccb(Assembler::zero, L_carry);
8224
8225 //Multiply the last in[] entry, if any
8226 bind(L_last_in);
8227 movl(op1, Address(in, 0));
8228 movl(sum, Address(out, offs, Address::times_4, -4));
8229
8230 movl(raxReg, k);
8231 mull(op1); //tmp4 * eax -> edx:eax
8232 addl(sum, carry);
8233 adcl(rdxReg, 0);
8234 addl(sum, raxReg);
8235 adcl(rdxReg, 0);
8236 movl(carry, rdxReg);
8237
8238 movl(Address(out, offs, Address::times_4, -4), sum);
8239
8240 bind(L_carry);
8241 //return tmp5/carry as carry in rax
8242 movl(rax, carry);
8243
8244 bind(L_done);
8245 pop(tmp5);
8246 pop(tmp4);
8247 pop(tmp3);
8248 pop(tmp2);
8249 pop(tmp1);
8250 }
8251 #endif
8252
8253 /**
8254 * Emits code to update CRC-32 with a byte value according to constants in table
8255 *
8256 * @param [in,out]crc Register containing the crc.
8257 * @param [in]val Register containing the byte to fold into the CRC.
8258 * @param [in]table Register containing the table of crc constants.
8259 *
8260 * uint32_t crc;
8261 * val = crc_table[(val ^ crc) & 0xFF];
8262 * crc = val ^ (crc >> 8);
8263 *
8264 */
8265 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8266 xorl(val, crc);
8267 andl(val, 0xFF);
8268 shrl(crc, 8); // unsigned shift
8269 xorl(crc, Address(table, val, Address::times_4, 0));
8270 }
8271
8272 /**
8273 * Fold 128-bit data chunk
8274 */
8275 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8276 if (UseAVX > 0) {
8277 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8278 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8279 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8280 pxor(xcrc, xtmp);
8281 } else {
8282 movdqa(xtmp, xcrc);
8283 pclmulhdq(xtmp, xK); // [123:64]
8284 pclmulldq(xcrc, xK); // [63:0]
8285 pxor(xcrc, xtmp);
8286 movdqu(xtmp, Address(buf, offset));
8287 pxor(xcrc, xtmp);
8288 }
8289 }
8290
8291 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8292 if (UseAVX > 0) {
8293 vpclmulhdq(xtmp, xK, xcrc);
8294 vpclmulldq(xcrc, xK, xcrc);
8295 pxor(xcrc, xbuf);
8296 pxor(xcrc, xtmp);
8297 } else {
8298 movdqa(xtmp, xcrc);
8299 pclmulhdq(xtmp, xK);
8300 pclmulldq(xcrc, xK);
8301 pxor(xcrc, xbuf);
8302 pxor(xcrc, xtmp);
8303 }
8304 }
8305
8306 /**
8307 * 8-bit folds to compute 32-bit CRC
8308 *
8309 * uint64_t xcrc;
8310 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8311 */
8312 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8313 movdl(tmp, xcrc);
8314 andl(tmp, 0xFF);
8315 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8316 psrldq(xcrc, 1); // unsigned shift one byte
8317 pxor(xcrc, xtmp);
8318 }
8319
8320 /**
8321 * uint32_t crc;
8322 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8323 */
8324 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8325 movl(tmp, crc);
8326 andl(tmp, 0xFF);
8327 shrl(crc, 8);
8328 xorl(crc, Address(table, tmp, Address::times_4, 0));
8329 }
8330
8331 /**
8332 * @param crc register containing existing CRC (32-bit)
8333 * @param buf register pointing to input byte buffer (byte*)
8334 * @param len register containing number of bytes
8335 * @param table register that will contain address of CRC table
8336 * @param tmp scratch register
8337 */
8338 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8339 assert_different_registers(crc, buf, len, table, tmp, rax);
8340
8341 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8342 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8343
8344 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8345 // context for the registers used, where all instructions below are using 128-bit mode
8346 // On EVEX without VL and BW, these instructions will all be AVX.
8347 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8348 notl(crc); // ~crc
8349 cmpl(len, 16);
8350 jcc(Assembler::less, L_tail);
8351
8352 // Align buffer to 16 bytes
8353 movl(tmp, buf);
8354 andl(tmp, 0xF);
8355 jccb(Assembler::zero, L_aligned);
8356 subl(tmp, 16);
8357 addl(len, tmp);
8358
8359 align(4);
8360 BIND(L_align_loop);
8361 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8362 update_byte_crc32(crc, rax, table);
8363 increment(buf);
8364 incrementl(tmp);
8365 jccb(Assembler::less, L_align_loop);
8366
8367 BIND(L_aligned);
8368 movl(tmp, len); // save
8369 shrl(len, 4);
8370 jcc(Assembler::zero, L_tail_restore);
8371
8372 // Fold crc into first bytes of vector
8373 movdqa(xmm1, Address(buf, 0));
8374 movdl(rax, xmm1);
8375 xorl(crc, rax);
8376 if (VM_Version::supports_sse4_1()) {
8377 pinsrd(xmm1, crc, 0);
8378 } else {
8379 pinsrw(xmm1, crc, 0);
8380 shrl(crc, 16);
8381 pinsrw(xmm1, crc, 1);
8382 }
8383 addptr(buf, 16);
8384 subl(len, 4); // len > 0
8385 jcc(Assembler::less, L_fold_tail);
8386
8387 movdqa(xmm2, Address(buf, 0));
8388 movdqa(xmm3, Address(buf, 16));
8389 movdqa(xmm4, Address(buf, 32));
8390 addptr(buf, 48);
8391 subl(len, 3);
8392 jcc(Assembler::lessEqual, L_fold_512b);
8393
8394 // Fold total 512 bits of polynomial on each iteration,
8395 // 128 bits per each of 4 parallel streams.
8396 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8397
8398 align32();
8399 BIND(L_fold_512b_loop);
8400 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8401 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8402 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8403 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8404 addptr(buf, 64);
8405 subl(len, 4);
8406 jcc(Assembler::greater, L_fold_512b_loop);
8407
8408 // Fold 512 bits to 128 bits.
8409 BIND(L_fold_512b);
8410 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8411 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8412 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8413 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8414
8415 // Fold the rest of 128 bits data chunks
8416 BIND(L_fold_tail);
8417 addl(len, 3);
8418 jccb(Assembler::lessEqual, L_fold_128b);
8419 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8420
8421 BIND(L_fold_tail_loop);
8422 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8423 addptr(buf, 16);
8424 decrementl(len);
8425 jccb(Assembler::greater, L_fold_tail_loop);
8426
8427 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8428 BIND(L_fold_128b);
8429 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8430 if (UseAVX > 0) {
8431 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8432 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8433 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8434 } else {
8435 movdqa(xmm2, xmm0);
8436 pclmulqdq(xmm2, xmm1, 0x1);
8437 movdqa(xmm3, xmm0);
8438 pand(xmm3, xmm2);
8439 pclmulqdq(xmm0, xmm3, 0x1);
8440 }
8441 psrldq(xmm1, 8);
8442 psrldq(xmm2, 4);
8443 pxor(xmm0, xmm1);
8444 pxor(xmm0, xmm2);
8445
8446 // 8 8-bit folds to compute 32-bit CRC.
8447 for (int j = 0; j < 4; j++) {
8448 fold_8bit_crc32(xmm0, table, xmm1, rax);
8449 }
8450 movdl(crc, xmm0); // mov 32 bits to general register
8451 for (int j = 0; j < 4; j++) {
8452 fold_8bit_crc32(crc, table, rax);
8453 }
8454
8455 BIND(L_tail_restore);
8456 movl(len, tmp); // restore
8457 BIND(L_tail);
8458 andl(len, 0xf);
8459 jccb(Assembler::zero, L_exit);
8460
8461 // Fold the rest of bytes
8462 align(4);
8463 BIND(L_tail_loop);
8464 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8465 update_byte_crc32(crc, rax, table);
8466 increment(buf);
8467 decrementl(len);
8468 jccb(Assembler::greater, L_tail_loop);
8469
8470 BIND(L_exit);
8471 notl(crc); // ~c
8472 }
8473
8474 #ifdef _LP64
8475 // Helper function for AVX 512 CRC32
8476 // Fold 512-bit data chunks
8477 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8478 Register pos, int offset) {
8479 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8480 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8481 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8482 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8483 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8484 }
8485
8486 // Helper function for AVX 512 CRC32
8487 // Compute CRC32 for < 256B buffers
8488 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8489 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8490 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8491
8492 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8493 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8494 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8495
8496 // check if there is enough buffer to be able to fold 16B at a time
8497 cmpl(len, 32);
8498 jcc(Assembler::less, L_less_than_32);
8499
8500 // if there is, load the constants
8501 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8502 movdl(xmm0, crc); // get the initial crc value
8503 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8504 pxor(xmm7, xmm0);
8505
8506 // update the buffer pointer
8507 addl(pos, 16);
8508 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8509 subl(len, 32);
8510 jmp(L_16B_reduction_loop);
8511
8512 bind(L_less_than_32);
8513 //mov initial crc to the return value. this is necessary for zero - length buffers.
8514 movl(rax, crc);
8515 testl(len, len);
8516 jcc(Assembler::equal, L_cleanup);
8517
8518 movdl(xmm0, crc); //get the initial crc value
8519
8520 cmpl(len, 16);
8521 jcc(Assembler::equal, L_exact_16_left);
8522 jcc(Assembler::less, L_less_than_16_left);
8523
8524 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8525 pxor(xmm7, xmm0); //xor the initial crc value
8526 addl(pos, 16);
8527 subl(len, 16);
8528 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8529 jmp(L_get_last_two_xmms);
8530
8531 bind(L_less_than_16_left);
8532 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8533 pxor(xmm1, xmm1);
8534 movptr(tmp1, rsp);
8535 movdqu(Address(tmp1, 0 * 16), xmm1);
8536
8537 cmpl(len, 4);
8538 jcc(Assembler::less, L_only_less_than_4);
8539
8540 //backup the counter value
8541 movl(tmp2, len);
8542 cmpl(len, 8);
8543 jcc(Assembler::less, L_less_than_8_left);
8544
8545 //load 8 Bytes
8546 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8547 movq(Address(tmp1, 0 * 16), rax);
8548 addptr(tmp1, 8);
8549 subl(len, 8);
8550 addl(pos, 8);
8551
8552 bind(L_less_than_8_left);
8553 cmpl(len, 4);
8554 jcc(Assembler::less, L_less_than_4_left);
8555
8556 //load 4 Bytes
8557 movl(rax, Address(buf, pos, Address::times_1, 0));
8558 movl(Address(tmp1, 0 * 16), rax);
8559 addptr(tmp1, 4);
8560 subl(len, 4);
8561 addl(pos, 4);
8562
8563 bind(L_less_than_4_left);
8564 cmpl(len, 2);
8565 jcc(Assembler::less, L_less_than_2_left);
8566
8567 // load 2 Bytes
8568 movw(rax, Address(buf, pos, Address::times_1, 0));
8569 movl(Address(tmp1, 0 * 16), rax);
8570 addptr(tmp1, 2);
8571 subl(len, 2);
8572 addl(pos, 2);
8573
8574 bind(L_less_than_2_left);
8575 cmpl(len, 1);
8576 jcc(Assembler::less, L_zero_left);
8577
8578 // load 1 Byte
8579 movb(rax, Address(buf, pos, Address::times_1, 0));
8580 movb(Address(tmp1, 0 * 16), rax);
8581
8582 bind(L_zero_left);
8583 movdqu(xmm7, Address(rsp, 0));
8584 pxor(xmm7, xmm0); //xor the initial crc value
8585
8586 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8587 movdqu(xmm0, Address(rax, tmp2));
8588 pshufb(xmm7, xmm0);
8589 jmp(L_128_done);
8590
8591 bind(L_exact_16_left);
8592 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8593 pxor(xmm7, xmm0); //xor the initial crc value
8594 jmp(L_128_done);
8595
8596 bind(L_only_less_than_4);
8597 cmpl(len, 3);
8598 jcc(Assembler::less, L_only_less_than_3);
8599
8600 // load 3 Bytes
8601 movb(rax, Address(buf, pos, Address::times_1, 0));
8602 movb(Address(tmp1, 0), rax);
8603
8604 movb(rax, Address(buf, pos, Address::times_1, 1));
8605 movb(Address(tmp1, 1), rax);
8606
8607 movb(rax, Address(buf, pos, Address::times_1, 2));
8608 movb(Address(tmp1, 2), rax);
8609
8610 movdqu(xmm7, Address(rsp, 0));
8611 pxor(xmm7, xmm0); //xor the initial crc value
8612
8613 pslldq(xmm7, 0x5);
8614 jmp(L_barrett);
8615 bind(L_only_less_than_3);
8616 cmpl(len, 2);
8617 jcc(Assembler::less, L_only_less_than_2);
8618
8619 // load 2 Bytes
8620 movb(rax, Address(buf, pos, Address::times_1, 0));
8621 movb(Address(tmp1, 0), rax);
8622
8623 movb(rax, Address(buf, pos, Address::times_1, 1));
8624 movb(Address(tmp1, 1), rax);
8625
8626 movdqu(xmm7, Address(rsp, 0));
8627 pxor(xmm7, xmm0); //xor the initial crc value
8628
8629 pslldq(xmm7, 0x6);
8630 jmp(L_barrett);
8631
8632 bind(L_only_less_than_2);
8633 //load 1 Byte
8634 movb(rax, Address(buf, pos, Address::times_1, 0));
8635 movb(Address(tmp1, 0), rax);
8636
8637 movdqu(xmm7, Address(rsp, 0));
8638 pxor(xmm7, xmm0); //xor the initial crc value
8639
8640 pslldq(xmm7, 0x7);
8641 }
8642
8643 /**
8644 * Compute CRC32 using AVX512 instructions
8645 * param crc register containing existing CRC (32-bit)
8646 * param buf register pointing to input byte buffer (byte*)
8647 * param len register containing number of bytes
8648 * param table address of crc or crc32c table
8649 * param tmp1 scratch register
8650 * param tmp2 scratch register
8651 * return rax result register
8652 *
8653 * This routine is identical for crc32c with the exception of the precomputed constant
8654 * table which will be passed as the table argument. The calculation steps are
8655 * the same for both variants.
8656 */
8657 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8658 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8659
8660 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8661 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8662 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8663 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8664 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8665
8666 const Register pos = r12;
8667 push(r12);
8668 subptr(rsp, 16 * 2 + 8);
8669
8670 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8671 // context for the registers used, where all instructions below are using 128-bit mode
8672 // On EVEX without VL and BW, these instructions will all be AVX.
8673 movl(pos, 0);
8674
8675 // check if smaller than 256B
8676 cmpl(len, 256);
8677 jcc(Assembler::less, L_less_than_256);
8678
8679 // load the initial crc value
8680 movdl(xmm10, crc);
8681
8682 // receive the initial 64B data, xor the initial crc value
8683 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8684 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8685 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8686 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8687
8688 subl(len, 256);
8689 cmpl(len, 256);
8690 jcc(Assembler::less, L_fold_128_B_loop);
8691
8692 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8693 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8694 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8695 subl(len, 256);
8696
8697 bind(L_fold_256_B_loop);
8698 addl(pos, 256);
8699 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8700 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8701 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8702 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8703
8704 subl(len, 256);
8705 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8706
8707 // Fold 256 into 128
8708 addl(pos, 256);
8709 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8710 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8711 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8712
8713 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8714 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8715 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8716
8717 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8718 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8719
8720 addl(len, 128);
8721 jmp(L_fold_128_B_register);
8722
8723 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8724 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8725
8726 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8727 bind(L_fold_128_B_loop);
8728 addl(pos, 128);
8729 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8730 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8731
8732 subl(len, 128);
8733 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8734
8735 addl(pos, 128);
8736
8737 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8738 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8739 bind(L_fold_128_B_register);
8740 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8741 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8742 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8743 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8744 // save last that has no multiplicand
8745 vextracti64x2(xmm7, xmm4, 3);
8746
8747 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8748 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8749 // Needed later in reduction loop
8750 movdqu(xmm10, Address(table, 1 * 16));
8751 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8752 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8753
8754 // Swap 1,0,3,2 - 01 00 11 10
8755 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8756 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8757 vextracti128(xmm5, xmm8, 1);
8758 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8759
8760 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8761 // instead of a cmp instruction, we use the negative flag with the jl instruction
8762 addl(len, 128 - 16);
8763 jcc(Assembler::less, L_final_reduction_for_128);
8764
8765 bind(L_16B_reduction_loop);
8766 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8767 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8768 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8769 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8770 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8771 addl(pos, 16);
8772 subl(len, 16);
8773 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8774
8775 bind(L_final_reduction_for_128);
8776 addl(len, 16);
8777 jcc(Assembler::equal, L_128_done);
8778
8779 bind(L_get_last_two_xmms);
8780 movdqu(xmm2, xmm7);
8781 addl(pos, len);
8782 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8783 subl(pos, len);
8784
8785 // get rid of the extra data that was loaded before
8786 // load the shift constant
8787 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8788 movdqu(xmm0, Address(rax, len));
8789 addl(rax, len);
8790
8791 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8792 //Change mask to 512
8793 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8794 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8795
8796 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8797 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8798 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8799 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8800 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8801
8802 bind(L_128_done);
8803 // compute crc of a 128-bit value
8804 movdqu(xmm10, Address(table, 3 * 16));
8805 movdqu(xmm0, xmm7);
8806
8807 // 64b fold
8808 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8809 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8810 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8811
8812 // 32b fold
8813 movdqu(xmm0, xmm7);
8814 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8815 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8816 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8817 jmp(L_barrett);
8818
8819 bind(L_less_than_256);
8820 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8821
8822 //barrett reduction
8823 bind(L_barrett);
8824 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8825 movdqu(xmm1, xmm7);
8826 movdqu(xmm2, xmm7);
8827 movdqu(xmm10, Address(table, 4 * 16));
8828
8829 pclmulqdq(xmm7, xmm10, 0x0);
8830 pxor(xmm7, xmm2);
8831 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8832 movdqu(xmm2, xmm7);
8833 pclmulqdq(xmm7, xmm10, 0x10);
8834 pxor(xmm7, xmm2);
8835 pxor(xmm7, xmm1);
8836 pextrd(crc, xmm7, 2);
8837
8838 bind(L_cleanup);
8839 addptr(rsp, 16 * 2 + 8);
8840 pop(r12);
8841 }
8842
8843 // S. Gueron / Information Processing Letters 112 (2012) 184
8844 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8845 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8846 // Output: the 64-bit carry-less product of B * CONST
8847 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8848 Register tmp1, Register tmp2, Register tmp3) {
8849 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8850 if (n > 0) {
8851 addq(tmp3, n * 256 * 8);
8852 }
8853 // Q1 = TABLEExt[n][B & 0xFF];
8854 movl(tmp1, in);
8855 andl(tmp1, 0x000000FF);
8856 shll(tmp1, 3);
8857 addq(tmp1, tmp3);
8858 movq(tmp1, Address(tmp1, 0));
8859
8860 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8861 movl(tmp2, in);
8862 shrl(tmp2, 8);
8863 andl(tmp2, 0x000000FF);
8864 shll(tmp2, 3);
8865 addq(tmp2, tmp3);
8866 movq(tmp2, Address(tmp2, 0));
8867
8868 shlq(tmp2, 8);
8869 xorq(tmp1, tmp2);
8870
8871 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8872 movl(tmp2, in);
8873 shrl(tmp2, 16);
8874 andl(tmp2, 0x000000FF);
8875 shll(tmp2, 3);
8876 addq(tmp2, tmp3);
8877 movq(tmp2, Address(tmp2, 0));
8878
8879 shlq(tmp2, 16);
8880 xorq(tmp1, tmp2);
8881
8882 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8883 shrl(in, 24);
8884 andl(in, 0x000000FF);
8885 shll(in, 3);
8886 addq(in, tmp3);
8887 movq(in, Address(in, 0));
8888
8889 shlq(in, 24);
8890 xorq(in, tmp1);
8891 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8892 }
8893
8894 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8895 Register in_out,
8896 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8897 XMMRegister w_xtmp2,
8898 Register tmp1,
8899 Register n_tmp2, Register n_tmp3) {
8900 if (is_pclmulqdq_supported) {
8901 movdl(w_xtmp1, in_out); // modified blindly
8902
8903 movl(tmp1, const_or_pre_comp_const_index);
8904 movdl(w_xtmp2, tmp1);
8905 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8906
8907 movdq(in_out, w_xtmp1);
8908 } else {
8909 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8910 }
8911 }
8912
8913 // Recombination Alternative 2: No bit-reflections
8914 // T1 = (CRC_A * U1) << 1
8915 // T2 = (CRC_B * U2) << 1
8916 // C1 = T1 >> 32
8917 // C2 = T2 >> 32
8918 // T1 = T1 & 0xFFFFFFFF
8919 // T2 = T2 & 0xFFFFFFFF
8920 // T1 = CRC32(0, T1)
8921 // T2 = CRC32(0, T2)
8922 // C1 = C1 ^ T1
8923 // C2 = C2 ^ T2
8924 // CRC = C1 ^ C2 ^ CRC_C
8925 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8926 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8927 Register tmp1, Register tmp2,
8928 Register n_tmp3) {
8929 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8930 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8931 shlq(in_out, 1);
8932 movl(tmp1, in_out);
8933 shrq(in_out, 32);
8934 xorl(tmp2, tmp2);
8935 crc32(tmp2, tmp1, 4);
8936 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8937 shlq(in1, 1);
8938 movl(tmp1, in1);
8939 shrq(in1, 32);
8940 xorl(tmp2, tmp2);
8941 crc32(tmp2, tmp1, 4);
8942 xorl(in1, tmp2);
8943 xorl(in_out, in1);
8944 xorl(in_out, in2);
8945 }
8946
8947 // Set N to predefined value
8948 // Subtract from a length of a buffer
8949 // execute in a loop:
8950 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8951 // for i = 1 to N do
8952 // CRC_A = CRC32(CRC_A, A[i])
8953 // CRC_B = CRC32(CRC_B, B[i])
8954 // CRC_C = CRC32(CRC_C, C[i])
8955 // end for
8956 // Recombine
8957 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8958 Register in_out1, Register in_out2, Register in_out3,
8959 Register tmp1, Register tmp2, Register tmp3,
8960 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8961 Register tmp4, Register tmp5,
8962 Register n_tmp6) {
8963 Label L_processPartitions;
8964 Label L_processPartition;
8965 Label L_exit;
8966
8967 bind(L_processPartitions);
8968 cmpl(in_out1, 3 * size);
8969 jcc(Assembler::less, L_exit);
8970 xorl(tmp1, tmp1);
8971 xorl(tmp2, tmp2);
8972 movq(tmp3, in_out2);
8973 addq(tmp3, size);
8974
8975 bind(L_processPartition);
8976 crc32(in_out3, Address(in_out2, 0), 8);
8977 crc32(tmp1, Address(in_out2, size), 8);
8978 crc32(tmp2, Address(in_out2, size * 2), 8);
8979 addq(in_out2, 8);
8980 cmpq(in_out2, tmp3);
8981 jcc(Assembler::less, L_processPartition);
8982 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8983 w_xtmp1, w_xtmp2, w_xtmp3,
8984 tmp4, tmp5,
8985 n_tmp6);
8986 addq(in_out2, 2 * size);
8987 subl(in_out1, 3 * size);
8988 jmp(L_processPartitions);
8989
8990 bind(L_exit);
8991 }
8992 #else
8993 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
8994 Register tmp1, Register tmp2, Register tmp3,
8995 XMMRegister xtmp1, XMMRegister xtmp2) {
8996 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8997 if (n > 0) {
8998 addl(tmp3, n * 256 * 8);
8999 }
9000 // Q1 = TABLEExt[n][B & 0xFF];
9001 movl(tmp1, in_out);
9002 andl(tmp1, 0x000000FF);
9003 shll(tmp1, 3);
9004 addl(tmp1, tmp3);
9005 movq(xtmp1, Address(tmp1, 0));
9006
9007 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9008 movl(tmp2, in_out);
9009 shrl(tmp2, 8);
9010 andl(tmp2, 0x000000FF);
9011 shll(tmp2, 3);
9012 addl(tmp2, tmp3);
9013 movq(xtmp2, Address(tmp2, 0));
9014
9015 psllq(xtmp2, 8);
9016 pxor(xtmp1, xtmp2);
9017
9018 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9019 movl(tmp2, in_out);
9020 shrl(tmp2, 16);
9021 andl(tmp2, 0x000000FF);
9022 shll(tmp2, 3);
9023 addl(tmp2, tmp3);
9024 movq(xtmp2, Address(tmp2, 0));
9025
9026 psllq(xtmp2, 16);
9027 pxor(xtmp1, xtmp2);
9028
9029 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9030 shrl(in_out, 24);
9031 andl(in_out, 0x000000FF);
9032 shll(in_out, 3);
9033 addl(in_out, tmp3);
9034 movq(xtmp2, Address(in_out, 0));
9035
9036 psllq(xtmp2, 24);
9037 pxor(xtmp1, xtmp2); // Result in CXMM
9038 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9039 }
9040
9041 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9042 Register in_out,
9043 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9044 XMMRegister w_xtmp2,
9045 Register tmp1,
9046 Register n_tmp2, Register n_tmp3) {
9047 if (is_pclmulqdq_supported) {
9048 movdl(w_xtmp1, in_out);
9049
9050 movl(tmp1, const_or_pre_comp_const_index);
9051 movdl(w_xtmp2, tmp1);
9052 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9053 // Keep result in XMM since GPR is 32 bit in length
9054 } else {
9055 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
9056 }
9057 }
9058
9059 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9060 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9061 Register tmp1, Register tmp2,
9062 Register n_tmp3) {
9063 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9064 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9065
9066 psllq(w_xtmp1, 1);
9067 movdl(tmp1, w_xtmp1);
9068 psrlq(w_xtmp1, 32);
9069 movdl(in_out, w_xtmp1);
9070
9071 xorl(tmp2, tmp2);
9072 crc32(tmp2, tmp1, 4);
9073 xorl(in_out, tmp2);
9074
9075 psllq(w_xtmp2, 1);
9076 movdl(tmp1, w_xtmp2);
9077 psrlq(w_xtmp2, 32);
9078 movdl(in1, w_xtmp2);
9079
9080 xorl(tmp2, tmp2);
9081 crc32(tmp2, tmp1, 4);
9082 xorl(in1, tmp2);
9083 xorl(in_out, in1);
9084 xorl(in_out, in2);
9085 }
9086
9087 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9088 Register in_out1, Register in_out2, Register in_out3,
9089 Register tmp1, Register tmp2, Register tmp3,
9090 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9091 Register tmp4, Register tmp5,
9092 Register n_tmp6) {
9093 Label L_processPartitions;
9094 Label L_processPartition;
9095 Label L_exit;
9096
9097 bind(L_processPartitions);
9098 cmpl(in_out1, 3 * size);
9099 jcc(Assembler::less, L_exit);
9100 xorl(tmp1, tmp1);
9101 xorl(tmp2, tmp2);
9102 movl(tmp3, in_out2);
9103 addl(tmp3, size);
9104
9105 bind(L_processPartition);
9106 crc32(in_out3, Address(in_out2, 0), 4);
9107 crc32(tmp1, Address(in_out2, size), 4);
9108 crc32(tmp2, Address(in_out2, size*2), 4);
9109 crc32(in_out3, Address(in_out2, 0+4), 4);
9110 crc32(tmp1, Address(in_out2, size+4), 4);
9111 crc32(tmp2, Address(in_out2, size*2+4), 4);
9112 addl(in_out2, 8);
9113 cmpl(in_out2, tmp3);
9114 jcc(Assembler::less, L_processPartition);
9115
9116 push(tmp3);
9117 push(in_out1);
9118 push(in_out2);
9119 tmp4 = tmp3;
9120 tmp5 = in_out1;
9121 n_tmp6 = in_out2;
9122
9123 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9124 w_xtmp1, w_xtmp2, w_xtmp3,
9125 tmp4, tmp5,
9126 n_tmp6);
9127
9128 pop(in_out2);
9129 pop(in_out1);
9130 pop(tmp3);
9131
9132 addl(in_out2, 2 * size);
9133 subl(in_out1, 3 * size);
9134 jmp(L_processPartitions);
9135
9136 bind(L_exit);
9137 }
9138 #endif //LP64
9139
9140 #ifdef _LP64
9141 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9142 // Input: A buffer I of L bytes.
9143 // Output: the CRC32C value of the buffer.
9144 // Notations:
9145 // Write L = 24N + r, with N = floor (L/24).
9146 // r = L mod 24 (0 <= r < 24).
9147 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9148 // N quadwords, and R consists of r bytes.
9149 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9150 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9151 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9152 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9153 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9154 Register tmp1, Register tmp2, Register tmp3,
9155 Register tmp4, Register tmp5, Register tmp6,
9156 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9157 bool is_pclmulqdq_supported) {
9158 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9159 Label L_wordByWord;
9160 Label L_byteByByteProlog;
9161 Label L_byteByByte;
9162 Label L_exit;
9163
9164 if (is_pclmulqdq_supported ) {
9165 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
9166 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
9167
9168 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
9169 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
9170
9171 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
9172 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
9173 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9174 } else {
9175 const_or_pre_comp_const_index[0] = 1;
9176 const_or_pre_comp_const_index[1] = 0;
9177
9178 const_or_pre_comp_const_index[2] = 3;
9179 const_or_pre_comp_const_index[3] = 2;
9180
9181 const_or_pre_comp_const_index[4] = 5;
9182 const_or_pre_comp_const_index[5] = 4;
9183 }
9184 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9185 in2, in1, in_out,
9186 tmp1, tmp2, tmp3,
9187 w_xtmp1, w_xtmp2, w_xtmp3,
9188 tmp4, tmp5,
9189 tmp6);
9190 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9191 in2, in1, in_out,
9192 tmp1, tmp2, tmp3,
9193 w_xtmp1, w_xtmp2, w_xtmp3,
9194 tmp4, tmp5,
9195 tmp6);
9196 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9197 in2, in1, in_out,
9198 tmp1, tmp2, tmp3,
9199 w_xtmp1, w_xtmp2, w_xtmp3,
9200 tmp4, tmp5,
9201 tmp6);
9202 movl(tmp1, in2);
9203 andl(tmp1, 0x00000007);
9204 negl(tmp1);
9205 addl(tmp1, in2);
9206 addq(tmp1, in1);
9207
9208 cmpq(in1, tmp1);
9209 jccb(Assembler::greaterEqual, L_byteByByteProlog);
9210 align(16);
9211 BIND(L_wordByWord);
9212 crc32(in_out, Address(in1, 0), 8);
9213 addq(in1, 8);
9214 cmpq(in1, tmp1);
9215 jcc(Assembler::less, L_wordByWord);
9216
9217 BIND(L_byteByByteProlog);
9218 andl(in2, 0x00000007);
9219 movl(tmp2, 1);
9220
9221 cmpl(tmp2, in2);
9222 jccb(Assembler::greater, L_exit);
9223 BIND(L_byteByByte);
9224 crc32(in_out, Address(in1, 0), 1);
9225 incq(in1);
9226 incl(tmp2);
9227 cmpl(tmp2, in2);
9228 jcc(Assembler::lessEqual, L_byteByByte);
9229
9230 BIND(L_exit);
9231 }
9232 #else
9233 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9234 Register tmp1, Register tmp2, Register tmp3,
9235 Register tmp4, Register tmp5, Register tmp6,
9236 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9237 bool is_pclmulqdq_supported) {
9238 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9239 Label L_wordByWord;
9240 Label L_byteByByteProlog;
9241 Label L_byteByByte;
9242 Label L_exit;
9243
9244 if (is_pclmulqdq_supported) {
9245 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
9246 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
9247
9248 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
9249 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
9250
9251 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
9252 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
9253 } else {
9254 const_or_pre_comp_const_index[0] = 1;
9255 const_or_pre_comp_const_index[1] = 0;
9256
9257 const_or_pre_comp_const_index[2] = 3;
9258 const_or_pre_comp_const_index[3] = 2;
9259
9260 const_or_pre_comp_const_index[4] = 5;
9261 const_or_pre_comp_const_index[5] = 4;
9262 }
9263 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9264 in2, in1, in_out,
9265 tmp1, tmp2, tmp3,
9266 w_xtmp1, w_xtmp2, w_xtmp3,
9267 tmp4, tmp5,
9268 tmp6);
9269 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9270 in2, in1, in_out,
9271 tmp1, tmp2, tmp3,
9272 w_xtmp1, w_xtmp2, w_xtmp3,
9273 tmp4, tmp5,
9274 tmp6);
9275 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9276 in2, in1, in_out,
9277 tmp1, tmp2, tmp3,
9278 w_xtmp1, w_xtmp2, w_xtmp3,
9279 tmp4, tmp5,
9280 tmp6);
9281 movl(tmp1, in2);
9282 andl(tmp1, 0x00000007);
9283 negl(tmp1);
9284 addl(tmp1, in2);
9285 addl(tmp1, in1);
9286
9287 BIND(L_wordByWord);
9288 cmpl(in1, tmp1);
9289 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9290 crc32(in_out, Address(in1,0), 4);
9291 addl(in1, 4);
9292 jmp(L_wordByWord);
9293
9294 BIND(L_byteByByteProlog);
9295 andl(in2, 0x00000007);
9296 movl(tmp2, 1);
9297
9298 BIND(L_byteByByte);
9299 cmpl(tmp2, in2);
9300 jccb(Assembler::greater, L_exit);
9301 movb(tmp1, Address(in1, 0));
9302 crc32(in_out, tmp1, 1);
9303 incl(in1);
9304 incl(tmp2);
9305 jmp(L_byteByByte);
9306
9307 BIND(L_exit);
9308 }
9309 #endif // LP64
9310 #undef BIND
9311 #undef BLOCK_COMMENT
9312
9313 // Compress char[] array to byte[].
9314 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
9315 // Return the array length if every element in array can be encoded,
9316 // otherwise, the index of first non-latin1 (> 0xff) character.
9317 // @IntrinsicCandidate
9318 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9319 // for (int i = 0; i < len; i++) {
9320 // char c = src[srcOff];
9321 // if (c > 0xff) {
9322 // return i; // return index of non-latin1 char
9323 // }
9324 // dst[dstOff] = (byte)c;
9325 // srcOff++;
9326 // dstOff++;
9327 // }
9328 // return len;
9329 // }
9330 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9331 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9332 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9333 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9334 Label copy_chars_loop, done, reset_sp, copy_tail;
9335
9336 // rsi: src
9337 // rdi: dst
9338 // rdx: len
9339 // rcx: tmp5
9340 // rax: result
9341
9342 // rsi holds start addr of source char[] to be compressed
9343 // rdi holds start addr of destination byte[]
9344 // rdx holds length
9345
9346 assert(len != result, "");
9347
9348 // save length for return
9349 movl(result, len);
9350
9351 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9352 VM_Version::supports_avx512vlbw() &&
9353 VM_Version::supports_bmi2()) {
9354
9355 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9356
9357 // alignment
9358 Label post_alignment;
9359
9360 // if length of the string is less than 32, handle it the old fashioned way
9361 testl(len, -32);
9362 jcc(Assembler::zero, below_threshold);
9363
9364 // First check whether a character is compressible ( <= 0xFF).
9365 // Create mask to test for Unicode chars inside zmm vector
9366 movl(tmp5, 0x00FF);
9367 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9368
9369 testl(len, -64);
9370 jccb(Assembler::zero, post_alignment);
9371
9372 movl(tmp5, dst);
9373 andl(tmp5, (32 - 1));
9374 negl(tmp5);
9375 andl(tmp5, (32 - 1));
9376
9377 // bail out when there is nothing to be done
9378 testl(tmp5, 0xFFFFFFFF);
9379 jccb(Assembler::zero, post_alignment);
9380
9381 // ~(~0 << len), where len is the # of remaining elements to process
9382 movl(len, 0xFFFFFFFF);
9383 shlxl(len, len, tmp5);
9384 notl(len);
9385 kmovdl(mask2, len);
9386 movl(len, result);
9387
9388 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9389 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9390 ktestd(mask1, mask2);
9391 jcc(Assembler::carryClear, copy_tail);
9392
9393 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9394
9395 addptr(src, tmp5);
9396 addptr(src, tmp5);
9397 addptr(dst, tmp5);
9398 subl(len, tmp5);
9399
9400 bind(post_alignment);
9401 // end of alignment
9402
9403 movl(tmp5, len);
9404 andl(tmp5, (32 - 1)); // tail count (in chars)
9405 andl(len, ~(32 - 1)); // vector count (in chars)
9406 jccb(Assembler::zero, copy_loop_tail);
9407
9408 lea(src, Address(src, len, Address::times_2));
9409 lea(dst, Address(dst, len, Address::times_1));
9410 negptr(len);
9411
9412 bind(copy_32_loop);
9413 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9414 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9415 kortestdl(mask1, mask1);
9416 jccb(Assembler::carryClear, reset_for_copy_tail);
9417
9418 // All elements in current processed chunk are valid candidates for
9419 // compression. Write a truncated byte elements to the memory.
9420 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9421 addptr(len, 32);
9422 jccb(Assembler::notZero, copy_32_loop);
9423
9424 bind(copy_loop_tail);
9425 // bail out when there is nothing to be done
9426 testl(tmp5, 0xFFFFFFFF);
9427 jcc(Assembler::zero, done);
9428
9429 movl(len, tmp5);
9430
9431 // ~(~0 << len), where len is the # of remaining elements to process
9432 movl(tmp5, 0xFFFFFFFF);
9433 shlxl(tmp5, tmp5, len);
9434 notl(tmp5);
9435
9436 kmovdl(mask2, tmp5);
9437
9438 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9439 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9440 ktestd(mask1, mask2);
9441 jcc(Assembler::carryClear, copy_tail);
9442
9443 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9444 jmp(done);
9445
9446 bind(reset_for_copy_tail);
9447 lea(src, Address(src, tmp5, Address::times_2));
9448 lea(dst, Address(dst, tmp5, Address::times_1));
9449 subptr(len, tmp5);
9450 jmp(copy_chars_loop);
9451
9452 bind(below_threshold);
9453 }
9454
9455 if (UseSSE42Intrinsics) {
9456 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9457
9458 // vectored compression
9459 testl(len, 0xfffffff8);
9460 jcc(Assembler::zero, copy_tail);
9461
9462 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9463 movdl(tmp1Reg, tmp5);
9464 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9465
9466 andl(len, 0xfffffff0);
9467 jccb(Assembler::zero, copy_16);
9468
9469 // compress 16 chars per iter
9470 pxor(tmp4Reg, tmp4Reg);
9471
9472 lea(src, Address(src, len, Address::times_2));
9473 lea(dst, Address(dst, len, Address::times_1));
9474 negptr(len);
9475
9476 bind(copy_32_loop);
9477 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9478 por(tmp4Reg, tmp2Reg);
9479 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9480 por(tmp4Reg, tmp3Reg);
9481 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9482 jccb(Assembler::notZero, reset_for_copy_tail);
9483 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9484 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9485 addptr(len, 16);
9486 jccb(Assembler::notZero, copy_32_loop);
9487
9488 // compress next vector of 8 chars (if any)
9489 bind(copy_16);
9490 // len = 0
9491 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9492 jccb(Assembler::zero, copy_tail_sse);
9493
9494 pxor(tmp3Reg, tmp3Reg);
9495
9496 movdqu(tmp2Reg, Address(src, 0));
9497 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9498 jccb(Assembler::notZero, reset_for_copy_tail);
9499 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9500 movq(Address(dst, 0), tmp2Reg);
9501 addptr(src, 16);
9502 addptr(dst, 8);
9503 jmpb(copy_tail_sse);
9504
9505 bind(reset_for_copy_tail);
9506 movl(tmp5, result);
9507 andl(tmp5, 0x0000000f);
9508 lea(src, Address(src, tmp5, Address::times_2));
9509 lea(dst, Address(dst, tmp5, Address::times_1));
9510 subptr(len, tmp5);
9511 jmpb(copy_chars_loop);
9512
9513 bind(copy_tail_sse);
9514 movl(len, result);
9515 andl(len, 0x00000007); // tail count (in chars)
9516 }
9517 // compress 1 char per iter
9518 bind(copy_tail);
9519 testl(len, len);
9520 jccb(Assembler::zero, done);
9521 lea(src, Address(src, len, Address::times_2));
9522 lea(dst, Address(dst, len, Address::times_1));
9523 negptr(len);
9524
9525 bind(copy_chars_loop);
9526 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9527 testl(tmp5, 0xff00); // check if Unicode char
9528 jccb(Assembler::notZero, reset_sp);
9529 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9530 increment(len);
9531 jccb(Assembler::notZero, copy_chars_loop);
9532
9533 // add len then return (len will be zero if compress succeeded, otherwise negative)
9534 bind(reset_sp);
9535 addl(result, len);
9536
9537 bind(done);
9538 }
9539
9540 // Inflate byte[] array to char[].
9541 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9542 // @IntrinsicCandidate
9543 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9544 // for (int i = 0; i < len; i++) {
9545 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9546 // }
9547 // }
9548 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9549 XMMRegister tmp1, Register tmp2, KRegister mask) {
9550 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9551 // rsi: src
9552 // rdi: dst
9553 // rdx: len
9554 // rcx: tmp2
9555
9556 // rsi holds start addr of source byte[] to be inflated
9557 // rdi holds start addr of destination char[]
9558 // rdx holds length
9559 assert_different_registers(src, dst, len, tmp2);
9560 movl(tmp2, len);
9561 if ((UseAVX > 2) && // AVX512
9562 VM_Version::supports_avx512vlbw() &&
9563 VM_Version::supports_bmi2()) {
9564
9565 Label copy_32_loop, copy_tail;
9566 Register tmp3_aliased = len;
9567
9568 // if length of the string is less than 16, handle it in an old fashioned way
9569 testl(len, -16);
9570 jcc(Assembler::zero, below_threshold);
9571
9572 testl(len, -1 * AVX3Threshold);
9573 jcc(Assembler::zero, avx3_threshold);
9574
9575 // In order to use only one arithmetic operation for the main loop we use
9576 // this pre-calculation
9577 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9578 andl(len, -32); // vector count
9579 jccb(Assembler::zero, copy_tail);
9580
9581 lea(src, Address(src, len, Address::times_1));
9582 lea(dst, Address(dst, len, Address::times_2));
9583 negptr(len);
9584
9585
9586 // inflate 32 chars per iter
9587 bind(copy_32_loop);
9588 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9589 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9590 addptr(len, 32);
9591 jcc(Assembler::notZero, copy_32_loop);
9592
9593 bind(copy_tail);
9594 // bail out when there is nothing to be done
9595 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9596 jcc(Assembler::zero, done);
9597
9598 // ~(~0 << length), where length is the # of remaining elements to process
9599 movl(tmp3_aliased, -1);
9600 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9601 notl(tmp3_aliased);
9602 kmovdl(mask, tmp3_aliased);
9603 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9604 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9605
9606 jmp(done);
9607 bind(avx3_threshold);
9608 }
9609 if (UseSSE42Intrinsics) {
9610 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9611
9612 if (UseAVX > 1) {
9613 andl(tmp2, (16 - 1));
9614 andl(len, -16);
9615 jccb(Assembler::zero, copy_new_tail);
9616 } else {
9617 andl(tmp2, 0x00000007); // tail count (in chars)
9618 andl(len, 0xfffffff8); // vector count (in chars)
9619 jccb(Assembler::zero, copy_tail);
9620 }
9621
9622 // vectored inflation
9623 lea(src, Address(src, len, Address::times_1));
9624 lea(dst, Address(dst, len, Address::times_2));
9625 negptr(len);
9626
9627 if (UseAVX > 1) {
9628 bind(copy_16_loop);
9629 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9630 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9631 addptr(len, 16);
9632 jcc(Assembler::notZero, copy_16_loop);
9633
9634 bind(below_threshold);
9635 bind(copy_new_tail);
9636 movl(len, tmp2);
9637 andl(tmp2, 0x00000007);
9638 andl(len, 0xFFFFFFF8);
9639 jccb(Assembler::zero, copy_tail);
9640
9641 pmovzxbw(tmp1, Address(src, 0));
9642 movdqu(Address(dst, 0), tmp1);
9643 addptr(src, 8);
9644 addptr(dst, 2 * 8);
9645
9646 jmp(copy_tail, true);
9647 }
9648
9649 // inflate 8 chars per iter
9650 bind(copy_8_loop);
9651 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9652 movdqu(Address(dst, len, Address::times_2), tmp1);
9653 addptr(len, 8);
9654 jcc(Assembler::notZero, copy_8_loop);
9655
9656 bind(copy_tail);
9657 movl(len, tmp2);
9658
9659 cmpl(len, 4);
9660 jccb(Assembler::less, copy_bytes);
9661
9662 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9663 pmovzxbw(tmp1, tmp1);
9664 movq(Address(dst, 0), tmp1);
9665 subptr(len, 4);
9666 addptr(src, 4);
9667 addptr(dst, 8);
9668
9669 bind(copy_bytes);
9670 } else {
9671 bind(below_threshold);
9672 }
9673
9674 testl(len, len);
9675 jccb(Assembler::zero, done);
9676 lea(src, Address(src, len, Address::times_1));
9677 lea(dst, Address(dst, len, Address::times_2));
9678 negptr(len);
9679
9680 // inflate 1 char per iter
9681 bind(copy_chars_loop);
9682 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9683 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9684 increment(len);
9685 jcc(Assembler::notZero, copy_chars_loop);
9686
9687 bind(done);
9688 }
9689
9690 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
9691 switch(type) {
9692 case T_BYTE:
9693 case T_BOOLEAN:
9694 evmovdqub(dst, kmask, src, merge, vector_len);
9695 break;
9696 case T_CHAR:
9697 case T_SHORT:
9698 evmovdquw(dst, kmask, src, merge, vector_len);
9699 break;
9700 case T_INT:
9701 case T_FLOAT:
9702 evmovdqul(dst, kmask, src, merge, vector_len);
9703 break;
9704 case T_LONG:
9705 case T_DOUBLE:
9706 evmovdquq(dst, kmask, src, merge, vector_len);
9707 break;
9708 default:
9709 fatal("Unexpected type argument %s", type2name(type));
9710 break;
9711 }
9712 }
9713
9714
9715 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9716 switch(type) {
9717 case T_BYTE:
9718 case T_BOOLEAN:
9719 evmovdqub(dst, kmask, src, merge, vector_len);
9720 break;
9721 case T_CHAR:
9722 case T_SHORT:
9723 evmovdquw(dst, kmask, src, merge, vector_len);
9724 break;
9725 case T_INT:
9726 case T_FLOAT:
9727 evmovdqul(dst, kmask, src, merge, vector_len);
9728 break;
9729 case T_LONG:
9730 case T_DOUBLE:
9731 evmovdquq(dst, kmask, src, merge, vector_len);
9732 break;
9733 default:
9734 fatal("Unexpected type argument %s", type2name(type));
9735 break;
9736 }
9737 }
9738
9739 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9740 switch(type) {
9741 case T_BYTE:
9742 case T_BOOLEAN:
9743 evmovdqub(dst, kmask, src, merge, vector_len);
9744 break;
9745 case T_CHAR:
9746 case T_SHORT:
9747 evmovdquw(dst, kmask, src, merge, vector_len);
9748 break;
9749 case T_INT:
9750 case T_FLOAT:
9751 evmovdqul(dst, kmask, src, merge, vector_len);
9752 break;
9753 case T_LONG:
9754 case T_DOUBLE:
9755 evmovdquq(dst, kmask, src, merge, vector_len);
9756 break;
9757 default:
9758 fatal("Unexpected type argument %s", type2name(type));
9759 break;
9760 }
9761 }
9762
9763 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9764 switch(masklen) {
9765 case 2:
9766 knotbl(dst, src);
9767 movl(rtmp, 3);
9768 kmovbl(ktmp, rtmp);
9769 kandbl(dst, ktmp, dst);
9770 break;
9771 case 4:
9772 knotbl(dst, src);
9773 movl(rtmp, 15);
9774 kmovbl(ktmp, rtmp);
9775 kandbl(dst, ktmp, dst);
9776 break;
9777 case 8:
9778 knotbl(dst, src);
9779 break;
9780 case 16:
9781 knotwl(dst, src);
9782 break;
9783 case 32:
9784 knotdl(dst, src);
9785 break;
9786 case 64:
9787 knotql(dst, src);
9788 break;
9789 default:
9790 fatal("Unexpected vector length %d", masklen);
9791 break;
9792 }
9793 }
9794
9795 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9796 switch(type) {
9797 case T_BOOLEAN:
9798 case T_BYTE:
9799 kandbl(dst, src1, src2);
9800 break;
9801 case T_CHAR:
9802 case T_SHORT:
9803 kandwl(dst, src1, src2);
9804 break;
9805 case T_INT:
9806 case T_FLOAT:
9807 kanddl(dst, src1, src2);
9808 break;
9809 case T_LONG:
9810 case T_DOUBLE:
9811 kandql(dst, src1, src2);
9812 break;
9813 default:
9814 fatal("Unexpected type argument %s", type2name(type));
9815 break;
9816 }
9817 }
9818
9819 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9820 switch(type) {
9821 case T_BOOLEAN:
9822 case T_BYTE:
9823 korbl(dst, src1, src2);
9824 break;
9825 case T_CHAR:
9826 case T_SHORT:
9827 korwl(dst, src1, src2);
9828 break;
9829 case T_INT:
9830 case T_FLOAT:
9831 kordl(dst, src1, src2);
9832 break;
9833 case T_LONG:
9834 case T_DOUBLE:
9835 korql(dst, src1, src2);
9836 break;
9837 default:
9838 fatal("Unexpected type argument %s", type2name(type));
9839 break;
9840 }
9841 }
9842
9843 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9844 switch(type) {
9845 case T_BOOLEAN:
9846 case T_BYTE:
9847 kxorbl(dst, src1, src2);
9848 break;
9849 case T_CHAR:
9850 case T_SHORT:
9851 kxorwl(dst, src1, src2);
9852 break;
9853 case T_INT:
9854 case T_FLOAT:
9855 kxordl(dst, src1, src2);
9856 break;
9857 case T_LONG:
9858 case T_DOUBLE:
9859 kxorql(dst, src1, src2);
9860 break;
9861 default:
9862 fatal("Unexpected type argument %s", type2name(type));
9863 break;
9864 }
9865 }
9866
9867 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9868 switch(type) {
9869 case T_BOOLEAN:
9870 case T_BYTE:
9871 evpermb(dst, mask, nds, src, merge, vector_len); break;
9872 case T_CHAR:
9873 case T_SHORT:
9874 evpermw(dst, mask, nds, src, merge, vector_len); break;
9875 case T_INT:
9876 case T_FLOAT:
9877 evpermd(dst, mask, nds, src, merge, vector_len); break;
9878 case T_LONG:
9879 case T_DOUBLE:
9880 evpermq(dst, mask, nds, src, merge, vector_len); break;
9881 default:
9882 fatal("Unexpected type argument %s", type2name(type)); break;
9883 }
9884 }
9885
9886 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9887 switch(type) {
9888 case T_BOOLEAN:
9889 case T_BYTE:
9890 evpermb(dst, mask, nds, src, merge, vector_len); break;
9891 case T_CHAR:
9892 case T_SHORT:
9893 evpermw(dst, mask, nds, src, merge, vector_len); break;
9894 case T_INT:
9895 case T_FLOAT:
9896 evpermd(dst, mask, nds, src, merge, vector_len); break;
9897 case T_LONG:
9898 case T_DOUBLE:
9899 evpermq(dst, mask, nds, src, merge, vector_len); break;
9900 default:
9901 fatal("Unexpected type argument %s", type2name(type)); break;
9902 }
9903 }
9904
9905 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9906 switch(type) {
9907 case T_BYTE:
9908 evpminub(dst, mask, nds, src, merge, vector_len); break;
9909 case T_SHORT:
9910 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9911 case T_INT:
9912 evpminud(dst, mask, nds, src, merge, vector_len); break;
9913 case T_LONG:
9914 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9915 default:
9916 fatal("Unexpected type argument %s", type2name(type)); break;
9917 }
9918 }
9919
9920 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9921 switch(type) {
9922 case T_BYTE:
9923 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9924 case T_SHORT:
9925 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9926 case T_INT:
9927 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9928 case T_LONG:
9929 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9930 default:
9931 fatal("Unexpected type argument %s", type2name(type)); break;
9932 }
9933 }
9934
9935 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9936 switch(type) {
9937 case T_BYTE:
9938 evpminub(dst, mask, nds, src, merge, vector_len); break;
9939 case T_SHORT:
9940 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9941 case T_INT:
9942 evpminud(dst, mask, nds, src, merge, vector_len); break;
9943 case T_LONG:
9944 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9945 default:
9946 fatal("Unexpected type argument %s", type2name(type)); break;
9947 }
9948 }
9949
9950 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9951 switch(type) {
9952 case T_BYTE:
9953 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9954 case T_SHORT:
9955 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9956 case T_INT:
9957 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9958 case T_LONG:
9959 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9960 default:
9961 fatal("Unexpected type argument %s", type2name(type)); break;
9962 }
9963 }
9964
9965 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9966 switch(type) {
9967 case T_BYTE:
9968 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9969 case T_SHORT:
9970 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9971 case T_INT:
9972 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9973 case T_LONG:
9974 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9975 default:
9976 fatal("Unexpected type argument %s", type2name(type)); break;
9977 }
9978 }
9979
9980 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9981 switch(type) {
9982 case T_BYTE:
9983 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9984 case T_SHORT:
9985 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9986 case T_INT:
9987 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9988 case T_LONG:
9989 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9990 default:
9991 fatal("Unexpected type argument %s", type2name(type)); break;
9992 }
9993 }
9994
9995 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9996 switch(type) {
9997 case T_BYTE:
9998 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9999 case T_SHORT:
10000 evpminsw(dst, mask, nds, src, merge, vector_len); break;
10001 case T_INT:
10002 evpminsd(dst, mask, nds, src, merge, vector_len); break;
10003 case T_LONG:
10004 evpminsq(dst, mask, nds, src, merge, vector_len); break;
10005 default:
10006 fatal("Unexpected type argument %s", type2name(type)); break;
10007 }
10008 }
10009
10010 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10011 switch(type) {
10012 case T_BYTE:
10013 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
10014 case T_SHORT:
10015 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
10016 case T_INT:
10017 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
10018 case T_LONG:
10019 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
10020 default:
10021 fatal("Unexpected type argument %s", type2name(type)); break;
10022 }
10023 }
10024
10025 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10026 switch(type) {
10027 case T_INT:
10028 evpxord(dst, mask, nds, src, merge, vector_len); break;
10029 case T_LONG:
10030 evpxorq(dst, mask, nds, src, merge, vector_len); break;
10031 default:
10032 fatal("Unexpected type argument %s", type2name(type)); break;
10033 }
10034 }
10035
10036 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10037 switch(type) {
10038 case T_INT:
10039 evpxord(dst, mask, nds, src, merge, vector_len); break;
10040 case T_LONG:
10041 evpxorq(dst, mask, nds, src, merge, vector_len); break;
10042 default:
10043 fatal("Unexpected type argument %s", type2name(type)); break;
10044 }
10045 }
10046
10047 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10048 switch(type) {
10049 case T_INT:
10050 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10051 case T_LONG:
10052 evporq(dst, mask, nds, src, merge, vector_len); break;
10053 default:
10054 fatal("Unexpected type argument %s", type2name(type)); break;
10055 }
10056 }
10057
10058 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10059 switch(type) {
10060 case T_INT:
10061 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10062 case T_LONG:
10063 evporq(dst, mask, nds, src, merge, vector_len); break;
10064 default:
10065 fatal("Unexpected type argument %s", type2name(type)); break;
10066 }
10067 }
10068
10069 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10070 switch(type) {
10071 case T_INT:
10072 evpandd(dst, mask, nds, src, merge, vector_len); break;
10073 case T_LONG:
10074 evpandq(dst, mask, nds, src, merge, vector_len); break;
10075 default:
10076 fatal("Unexpected type argument %s", type2name(type)); break;
10077 }
10078 }
10079
10080 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10081 switch(type) {
10082 case T_INT:
10083 evpandd(dst, mask, nds, src, merge, vector_len); break;
10084 case T_LONG:
10085 evpandq(dst, mask, nds, src, merge, vector_len); break;
10086 default:
10087 fatal("Unexpected type argument %s", type2name(type)); break;
10088 }
10089 }
10090
10091 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
10092 switch(masklen) {
10093 case 8:
10094 kortestbl(src1, src2);
10095 break;
10096 case 16:
10097 kortestwl(src1, src2);
10098 break;
10099 case 32:
10100 kortestdl(src1, src2);
10101 break;
10102 case 64:
10103 kortestql(src1, src2);
10104 break;
10105 default:
10106 fatal("Unexpected mask length %d", masklen);
10107 break;
10108 }
10109 }
10110
10111
10112 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
10113 switch(masklen) {
10114 case 8:
10115 ktestbl(src1, src2);
10116 break;
10117 case 16:
10118 ktestwl(src1, src2);
10119 break;
10120 case 32:
10121 ktestdl(src1, src2);
10122 break;
10123 case 64:
10124 ktestql(src1, src2);
10125 break;
10126 default:
10127 fatal("Unexpected mask length %d", masklen);
10128 break;
10129 }
10130 }
10131
10132 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10133 switch(type) {
10134 case T_INT:
10135 evprold(dst, mask, src, shift, merge, vlen_enc); break;
10136 case T_LONG:
10137 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
10138 default:
10139 fatal("Unexpected type argument %s", type2name(type)); break;
10140 break;
10141 }
10142 }
10143
10144 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10145 switch(type) {
10146 case T_INT:
10147 evprord(dst, mask, src, shift, merge, vlen_enc); break;
10148 case T_LONG:
10149 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
10150 default:
10151 fatal("Unexpected type argument %s", type2name(type)); break;
10152 }
10153 }
10154
10155 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10156 switch(type) {
10157 case T_INT:
10158 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
10159 case T_LONG:
10160 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
10161 default:
10162 fatal("Unexpected type argument %s", type2name(type)); break;
10163 }
10164 }
10165
10166 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10167 switch(type) {
10168 case T_INT:
10169 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
10170 case T_LONG:
10171 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
10172 default:
10173 fatal("Unexpected type argument %s", type2name(type)); break;
10174 }
10175 }
10176
10177 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10178 assert(rscratch != noreg || always_reachable(src), "missing");
10179
10180 if (reachable(src)) {
10181 evpandq(dst, nds, as_Address(src), vector_len);
10182 } else {
10183 lea(rscratch, src);
10184 evpandq(dst, nds, Address(rscratch, 0), vector_len);
10185 }
10186 }
10187
10188 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
10189 assert(rscratch != noreg || always_reachable(src), "missing");
10190
10191 if (reachable(src)) {
10192 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
10193 } else {
10194 lea(rscratch, src);
10195 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
10196 }
10197 }
10198
10199 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10200 assert(rscratch != noreg || always_reachable(src), "missing");
10201
10202 if (reachable(src)) {
10203 evporq(dst, nds, as_Address(src), vector_len);
10204 } else {
10205 lea(rscratch, src);
10206 evporq(dst, nds, Address(rscratch, 0), vector_len);
10207 }
10208 }
10209
10210 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10211 assert(rscratch != noreg || always_reachable(src), "missing");
10212
10213 if (reachable(src)) {
10214 vpshufb(dst, nds, as_Address(src), vector_len);
10215 } else {
10216 lea(rscratch, src);
10217 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
10218 }
10219 }
10220
10221 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10222 assert(rscratch != noreg || always_reachable(src), "missing");
10223
10224 if (reachable(src)) {
10225 Assembler::vpor(dst, nds, as_Address(src), vector_len);
10226 } else {
10227 lea(rscratch, src);
10228 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
10229 }
10230 }
10231
10232 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
10233 assert(rscratch != noreg || always_reachable(src3), "missing");
10234
10235 if (reachable(src3)) {
10236 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
10237 } else {
10238 lea(rscratch, src3);
10239 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
10240 }
10241 }
10242
10243 #if COMPILER2_OR_JVMCI
10244
10245 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
10246 Register length, Register temp, int vec_enc) {
10247 // Computing mask for predicated vector store.
10248 movptr(temp, -1);
10249 bzhiq(temp, temp, length);
10250 kmov(mask, temp);
10251 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
10252 }
10253
10254 // Set memory operation for length "less than" 64 bytes.
10255 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
10256 XMMRegister xmm, KRegister mask, Register length,
10257 Register temp, bool use64byteVector) {
10258 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10259 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10260 if (!use64byteVector) {
10261 fill32(dst, disp, xmm);
10262 subptr(length, 32 >> shift);
10263 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
10264 } else {
10265 assert(MaxVectorSize == 64, "vector length != 64");
10266 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
10267 }
10268 }
10269
10270
10271 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
10272 XMMRegister xmm, KRegister mask, Register length,
10273 Register temp) {
10274 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10275 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10276 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
10277 }
10278
10279
10280 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
10281 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10282 vmovdqu(dst, xmm);
10283 }
10284
10285 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
10286 fill32(Address(dst, disp), xmm);
10287 }
10288
10289 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
10290 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10291 if (!use64byteVector) {
10292 fill32(dst, xmm);
10293 fill32(dst.plus_disp(32), xmm);
10294 } else {
10295 evmovdquq(dst, xmm, Assembler::AVX_512bit);
10296 }
10297 }
10298
10299 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
10300 fill64(Address(dst, disp), xmm, use64byteVector);
10301 }
10302
10303 #ifdef _LP64
10304 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
10305 Register count, Register rtmp, XMMRegister xtmp) {
10306 Label L_exit;
10307 Label L_fill_start;
10308 Label L_fill_64_bytes;
10309 Label L_fill_96_bytes;
10310 Label L_fill_128_bytes;
10311 Label L_fill_128_bytes_loop;
10312 Label L_fill_128_loop_header;
10313 Label L_fill_128_bytes_loop_header;
10314 Label L_fill_128_bytes_loop_pre_header;
10315 Label L_fill_zmm_sequence;
10316
10317 int shift = -1;
10318 int avx3threshold = VM_Version::avx3_threshold();
10319 switch(type) {
10320 case T_BYTE: shift = 0;
10321 break;
10322 case T_SHORT: shift = 1;
10323 break;
10324 case T_INT: shift = 2;
10325 break;
10326 /* Uncomment when LONG fill stubs are supported.
10327 case T_LONG: shift = 3;
10328 break;
10329 */
10330 default:
10331 fatal("Unhandled type: %s\n", type2name(type));
10332 }
10333
10334 if ((avx3threshold != 0) || (MaxVectorSize == 32)) {
10335
10336 if (MaxVectorSize == 64) {
10337 cmpq(count, avx3threshold >> shift);
10338 jcc(Assembler::greater, L_fill_zmm_sequence);
10339 }
10340
10341 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
10342
10343 bind(L_fill_start);
10344
10345 cmpq(count, 32 >> shift);
10346 jccb(Assembler::greater, L_fill_64_bytes);
10347 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
10348 jmp(L_exit);
10349
10350 bind(L_fill_64_bytes);
10351 cmpq(count, 64 >> shift);
10352 jccb(Assembler::greater, L_fill_96_bytes);
10353 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10354 jmp(L_exit);
10355
10356 bind(L_fill_96_bytes);
10357 cmpq(count, 96 >> shift);
10358 jccb(Assembler::greater, L_fill_128_bytes);
10359 fill64(to, 0, xtmp);
10360 subq(count, 64 >> shift);
10361 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10362 jmp(L_exit);
10363
10364 bind(L_fill_128_bytes);
10365 cmpq(count, 128 >> shift);
10366 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10367 fill64(to, 0, xtmp);
10368 fill32(to, 64, xtmp);
10369 subq(count, 96 >> shift);
10370 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10371 jmp(L_exit);
10372
10373 bind(L_fill_128_bytes_loop_pre_header);
10374 {
10375 mov(rtmp, to);
10376 andq(rtmp, 31);
10377 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10378 negq(rtmp);
10379 addq(rtmp, 32);
10380 mov64(r8, -1L);
10381 bzhiq(r8, r8, rtmp);
10382 kmovql(k2, r8);
10383 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10384 addq(to, rtmp);
10385 shrq(rtmp, shift);
10386 subq(count, rtmp);
10387 }
10388
10389 cmpq(count, 128 >> shift);
10390 jcc(Assembler::less, L_fill_start);
10391
10392 bind(L_fill_128_bytes_loop_header);
10393 subq(count, 128 >> shift);
10394
10395 align32();
10396 bind(L_fill_128_bytes_loop);
10397 fill64(to, 0, xtmp);
10398 fill64(to, 64, xtmp);
10399 addq(to, 128);
10400 subq(count, 128 >> shift);
10401 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10402
10403 addq(count, 128 >> shift);
10404 jcc(Assembler::zero, L_exit);
10405 jmp(L_fill_start);
10406 }
10407
10408 if (MaxVectorSize == 64) {
10409 // Sequence using 64 byte ZMM register.
10410 Label L_fill_128_bytes_zmm;
10411 Label L_fill_192_bytes_zmm;
10412 Label L_fill_192_bytes_loop_zmm;
10413 Label L_fill_192_bytes_loop_header_zmm;
10414 Label L_fill_192_bytes_loop_pre_header_zmm;
10415 Label L_fill_start_zmm_sequence;
10416
10417 bind(L_fill_zmm_sequence);
10418 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10419
10420 bind(L_fill_start_zmm_sequence);
10421 cmpq(count, 64 >> shift);
10422 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10423 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10424 jmp(L_exit);
10425
10426 bind(L_fill_128_bytes_zmm);
10427 cmpq(count, 128 >> shift);
10428 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10429 fill64(to, 0, xtmp, true);
10430 subq(count, 64 >> shift);
10431 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10432 jmp(L_exit);
10433
10434 bind(L_fill_192_bytes_zmm);
10435 cmpq(count, 192 >> shift);
10436 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10437 fill64(to, 0, xtmp, true);
10438 fill64(to, 64, xtmp, true);
10439 subq(count, 128 >> shift);
10440 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10441 jmp(L_exit);
10442
10443 bind(L_fill_192_bytes_loop_pre_header_zmm);
10444 {
10445 movq(rtmp, to);
10446 andq(rtmp, 63);
10447 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10448 negq(rtmp);
10449 addq(rtmp, 64);
10450 mov64(r8, -1L);
10451 bzhiq(r8, r8, rtmp);
10452 kmovql(k2, r8);
10453 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10454 addq(to, rtmp);
10455 shrq(rtmp, shift);
10456 subq(count, rtmp);
10457 }
10458
10459 cmpq(count, 192 >> shift);
10460 jcc(Assembler::less, L_fill_start_zmm_sequence);
10461
10462 bind(L_fill_192_bytes_loop_header_zmm);
10463 subq(count, 192 >> shift);
10464
10465 align32();
10466 bind(L_fill_192_bytes_loop_zmm);
10467 fill64(to, 0, xtmp, true);
10468 fill64(to, 64, xtmp, true);
10469 fill64(to, 128, xtmp, true);
10470 addq(to, 192);
10471 subq(count, 192 >> shift);
10472 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10473
10474 addq(count, 192 >> shift);
10475 jcc(Assembler::zero, L_exit);
10476 jmp(L_fill_start_zmm_sequence);
10477 }
10478 bind(L_exit);
10479 }
10480 #endif
10481 #endif //COMPILER2_OR_JVMCI
10482
10483
10484 #ifdef _LP64
10485 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10486 Label done;
10487 cvttss2sil(dst, src);
10488 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10489 cmpl(dst, 0x80000000); // float_sign_flip
10490 jccb(Assembler::notEqual, done);
10491 subptr(rsp, 8);
10492 movflt(Address(rsp, 0), src);
10493 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10494 pop(dst);
10495 bind(done);
10496 }
10497
10498 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10499 Label done;
10500 cvttsd2sil(dst, src);
10501 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10502 cmpl(dst, 0x80000000); // float_sign_flip
10503 jccb(Assembler::notEqual, done);
10504 subptr(rsp, 8);
10505 movdbl(Address(rsp, 0), src);
10506 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10507 pop(dst);
10508 bind(done);
10509 }
10510
10511 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10512 Label done;
10513 cvttss2siq(dst, src);
10514 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10515 jccb(Assembler::notEqual, done);
10516 subptr(rsp, 8);
10517 movflt(Address(rsp, 0), src);
10518 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10519 pop(dst);
10520 bind(done);
10521 }
10522
10523 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10524 // Following code is line by line assembly translation rounding algorithm.
10525 // Please refer to java.lang.Math.round(float) algorithm for details.
10526 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10527 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10528 const int32_t FloatConsts_EXP_BIAS = 127;
10529 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10530 const int32_t MINUS_32 = 0xFFFFFFE0;
10531 Label L_special_case, L_block1, L_exit;
10532 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10533 movdl(dst, src);
10534 andl(dst, rtmp);
10535 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10536 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10537 subl(rtmp, dst);
10538 movl(rcx, rtmp);
10539 movl(dst, MINUS_32);
10540 testl(rtmp, dst);
10541 jccb(Assembler::notEqual, L_special_case);
10542 movdl(dst, src);
10543 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10544 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10545 movdl(rtmp, src);
10546 testl(rtmp, rtmp);
10547 jccb(Assembler::greaterEqual, L_block1);
10548 negl(dst);
10549 bind(L_block1);
10550 sarl(dst);
10551 addl(dst, 0x1);
10552 sarl(dst, 0x1);
10553 jmp(L_exit);
10554 bind(L_special_case);
10555 convert_f2i(dst, src);
10556 bind(L_exit);
10557 }
10558
10559 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10560 // Following code is line by line assembly translation rounding algorithm.
10561 // Please refer to java.lang.Math.round(double) algorithm for details.
10562 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10563 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10564 const int64_t DoubleConsts_EXP_BIAS = 1023;
10565 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10566 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10567 Label L_special_case, L_block1, L_exit;
10568 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10569 movq(dst, src);
10570 andq(dst, rtmp);
10571 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10572 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10573 subq(rtmp, dst);
10574 movq(rcx, rtmp);
10575 mov64(dst, MINUS_64);
10576 testq(rtmp, dst);
10577 jccb(Assembler::notEqual, L_special_case);
10578 movq(dst, src);
10579 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10580 andq(dst, rtmp);
10581 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10582 orq(dst, rtmp);
10583 movq(rtmp, src);
10584 testq(rtmp, rtmp);
10585 jccb(Assembler::greaterEqual, L_block1);
10586 negq(dst);
10587 bind(L_block1);
10588 sarq(dst);
10589 addq(dst, 0x1);
10590 sarq(dst, 0x1);
10591 jmp(L_exit);
10592 bind(L_special_case);
10593 convert_d2l(dst, src);
10594 bind(L_exit);
10595 }
10596
10597 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10598 Label done;
10599 cvttsd2siq(dst, src);
10600 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10601 jccb(Assembler::notEqual, done);
10602 subptr(rsp, 8);
10603 movdbl(Address(rsp, 0), src);
10604 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10605 pop(dst);
10606 bind(done);
10607 }
10608
10609 void MacroAssembler::cache_wb(Address line)
10610 {
10611 // 64 bit cpus always support clflush
10612 assert(VM_Version::supports_clflush(), "clflush should be available");
10613 bool optimized = VM_Version::supports_clflushopt();
10614 bool no_evict = VM_Version::supports_clwb();
10615
10616 // prefer clwb (writeback without evict) otherwise
10617 // prefer clflushopt (potentially parallel writeback with evict)
10618 // otherwise fallback on clflush (serial writeback with evict)
10619
10620 if (optimized) {
10621 if (no_evict) {
10622 clwb(line);
10623 } else {
10624 clflushopt(line);
10625 }
10626 } else {
10627 // no need for fence when using CLFLUSH
10628 clflush(line);
10629 }
10630 }
10631
10632 void MacroAssembler::cache_wbsync(bool is_pre)
10633 {
10634 assert(VM_Version::supports_clflush(), "clflush should be available");
10635 bool optimized = VM_Version::supports_clflushopt();
10636 bool no_evict = VM_Version::supports_clwb();
10637
10638 // pick the correct implementation
10639
10640 if (!is_pre && (optimized || no_evict)) {
10641 // need an sfence for post flush when using clflushopt or clwb
10642 // otherwise no no need for any synchroniaztion
10643
10644 sfence();
10645 }
10646 }
10647
10648 #endif // _LP64
10649
10650 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10651 switch (cond) {
10652 // Note some conditions are synonyms for others
10653 case Assembler::zero: return Assembler::notZero;
10654 case Assembler::notZero: return Assembler::zero;
10655 case Assembler::less: return Assembler::greaterEqual;
10656 case Assembler::lessEqual: return Assembler::greater;
10657 case Assembler::greater: return Assembler::lessEqual;
10658 case Assembler::greaterEqual: return Assembler::less;
10659 case Assembler::below: return Assembler::aboveEqual;
10660 case Assembler::belowEqual: return Assembler::above;
10661 case Assembler::above: return Assembler::belowEqual;
10662 case Assembler::aboveEqual: return Assembler::below;
10663 case Assembler::overflow: return Assembler::noOverflow;
10664 case Assembler::noOverflow: return Assembler::overflow;
10665 case Assembler::negative: return Assembler::positive;
10666 case Assembler::positive: return Assembler::negative;
10667 case Assembler::parity: return Assembler::noParity;
10668 case Assembler::noParity: return Assembler::parity;
10669 }
10670 ShouldNotReachHere(); return Assembler::overflow;
10671 }
10672
10673 // This is simply a call to Thread::current()
10674 void MacroAssembler::get_thread(Register thread) {
10675 if (thread != rax) {
10676 push(rax);
10677 }
10678 LP64_ONLY(push(rdi);)
10679 LP64_ONLY(push(rsi);)
10680 push(rdx);
10681 push(rcx);
10682 #ifdef _LP64
10683 push(r8);
10684 push(r9);
10685 push(r10);
10686 push(r11);
10687 #endif
10688
10689 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10690
10691 #ifdef _LP64
10692 pop(r11);
10693 pop(r10);
10694 pop(r9);
10695 pop(r8);
10696 #endif
10697 pop(rcx);
10698 pop(rdx);
10699 LP64_ONLY(pop(rsi);)
10700 LP64_ONLY(pop(rdi);)
10701 if (thread != rax) {
10702 mov(thread, rax);
10703 pop(rax);
10704 }
10705 }
10706
10707 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10708 Label L_stack_ok;
10709 if (bias == 0) {
10710 testptr(sp, 2 * wordSize - 1);
10711 } else {
10712 // lea(tmp, Address(rsp, bias);
10713 mov(tmp, sp);
10714 addptr(tmp, bias);
10715 testptr(tmp, 2 * wordSize - 1);
10716 }
10717 jcc(Assembler::equal, L_stack_ok);
10718 block_comment(msg);
10719 stop(msg);
10720 bind(L_stack_ok);
10721 }
10722
10723 // Implements lightweight-locking.
10724 //
10725 // obj: the object to be locked
10726 // reg_rax: rax
10727 // thread: the thread which attempts to lock obj
10728 // tmp: a temporary register
10729 void MacroAssembler::lightweight_lock(Register basic_lock, Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10730 assert(reg_rax == rax, "");
10731 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10732
10733 Label push;
10734 const Register top = tmp;
10735
10736 // Preload the markWord. It is important that this is the first
10737 // instruction emitted as it is part of C1's null check semantics.
10738 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10739
10740 if (UseObjectMonitorTable) {
10741 // Clear cache in case fast locking succeeds.
10742 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10743 }
10744
10745 // Load top.
10746 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10747
10748 // Check if the lock-stack is full.
10749 cmpl(top, LockStack::end_offset());
10750 jcc(Assembler::greaterEqual, slow);
10751
10752 // Check for recursion.
10753 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10754 jcc(Assembler::equal, push);
10755
10756 // Check header for monitor (0b10).
10757 testptr(reg_rax, markWord::monitor_value);
10758 jcc(Assembler::notZero, slow);
10759
10760 // Try to lock. Transition lock bits 0b01 => 0b00
10761 movptr(tmp, reg_rax);
10762 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10763 orptr(reg_rax, markWord::unlocked_value);
10764 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10765 jcc(Assembler::notEqual, slow);
10766
10767 // Restore top, CAS clobbers register.
10768 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10769
10770 bind(push);
10771 // After successful lock, push object on lock-stack.
10772 movptr(Address(thread, top), obj);
10773 incrementl(top, oopSize);
10774 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10775 }
10776
10777 // Implements lightweight-unlocking.
10778 //
10779 // obj: the object to be unlocked
10780 // reg_rax: rax
10781 // thread: the thread
10782 // tmp: a temporary register
10783 void MacroAssembler::lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10784 assert(reg_rax == rax, "");
10785 assert_different_registers(obj, reg_rax, thread, tmp);
10786
10787 Label unlocked, push_and_slow;
10788 const Register top = tmp;
10789
10790 // Check if obj is top of lock-stack.
10791 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10792 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10793 jcc(Assembler::notEqual, slow);
10794
10795 // Pop lock-stack.
10796 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10797 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10798
10799 // Check if recursive.
10800 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10801 jcc(Assembler::equal, unlocked);
10802
10803 // Not recursive. Check header for monitor (0b10).
10804 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10805 testptr(reg_rax, markWord::monitor_value);
10806 jcc(Assembler::notZero, push_and_slow);
10807
10808 #ifdef ASSERT
10809 // Check header not unlocked (0b01).
10810 Label not_unlocked;
10811 testptr(reg_rax, markWord::unlocked_value);
10812 jcc(Assembler::zero, not_unlocked);
10813 stop("lightweight_unlock already unlocked");
10814 bind(not_unlocked);
10815 #endif
10816
10817 // Try to unlock. Transition lock bits 0b00 => 0b01
10818 movptr(tmp, reg_rax);
10819 orptr(tmp, markWord::unlocked_value);
10820 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10821 jcc(Assembler::equal, unlocked);
10822
10823 bind(push_and_slow);
10824 // Restore lock-stack and handle the unlock in runtime.
10825 #ifdef ASSERT
10826 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10827 movptr(Address(thread, top), obj);
10828 #endif
10829 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10830 jmp(slow);
10831
10832 bind(unlocked);
10833 }
10834
10835 #ifdef _LP64
10836 // Saves legacy GPRs state on stack.
10837 void MacroAssembler::save_legacy_gprs() {
10838 subq(rsp, 16 * wordSize);
10839 movq(Address(rsp, 15 * wordSize), rax);
10840 movq(Address(rsp, 14 * wordSize), rcx);
10841 movq(Address(rsp, 13 * wordSize), rdx);
10842 movq(Address(rsp, 12 * wordSize), rbx);
10843 movq(Address(rsp, 10 * wordSize), rbp);
10844 movq(Address(rsp, 9 * wordSize), rsi);
10845 movq(Address(rsp, 8 * wordSize), rdi);
10846 movq(Address(rsp, 7 * wordSize), r8);
10847 movq(Address(rsp, 6 * wordSize), r9);
10848 movq(Address(rsp, 5 * wordSize), r10);
10849 movq(Address(rsp, 4 * wordSize), r11);
10850 movq(Address(rsp, 3 * wordSize), r12);
10851 movq(Address(rsp, 2 * wordSize), r13);
10852 movq(Address(rsp, wordSize), r14);
10853 movq(Address(rsp, 0), r15);
10854 }
10855
10856 // Resotres back legacy GPRs state from stack.
10857 void MacroAssembler::restore_legacy_gprs() {
10858 movq(r15, Address(rsp, 0));
10859 movq(r14, Address(rsp, wordSize));
10860 movq(r13, Address(rsp, 2 * wordSize));
10861 movq(r12, Address(rsp, 3 * wordSize));
10862 movq(r11, Address(rsp, 4 * wordSize));
10863 movq(r10, Address(rsp, 5 * wordSize));
10864 movq(r9, Address(rsp, 6 * wordSize));
10865 movq(r8, Address(rsp, 7 * wordSize));
10866 movq(rdi, Address(rsp, 8 * wordSize));
10867 movq(rsi, Address(rsp, 9 * wordSize));
10868 movq(rbp, Address(rsp, 10 * wordSize));
10869 movq(rbx, Address(rsp, 12 * wordSize));
10870 movq(rdx, Address(rsp, 13 * wordSize));
10871 movq(rcx, Address(rsp, 14 * wordSize));
10872 movq(rax, Address(rsp, 15 * wordSize));
10873 addq(rsp, 16 * wordSize);
10874 }
10875
10876 void MacroAssembler::load_aotrc_address(Register reg, address a) {
10877 #if INCLUDE_CDS
10878 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
10879 if (SCCache::is_on_for_write()) {
10880 // all aotrc field addresses should be registered in the SCC address table
10881 lea(reg, ExternalAddress(a));
10882 } else {
10883 mov64(reg, (uint64_t)a);
10884 }
10885 #else
10886 ShouldNotReachHere();
10887 #endif
10888 }
10889
10890 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10891 if (VM_Version::supports_apx_f()) {
10892 esetzucc(comparison, dst);
10893 } else {
10894 setb(comparison, dst);
10895 movzbl(dst, dst);
10896 }
10897 }
10898
10899 #endif