1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.hpp"
26 #include "asm/assembler.inline.hpp"
27 #include "code/aotCodeCache.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "crc32c.h"
32 #include "gc/shared/barrierSet.hpp"
33 #include "gc/shared/barrierSetAssembler.hpp"
34 #include "gc/shared/collectedHeap.inline.hpp"
35 #include "gc/shared/tlab_globals.hpp"
36 #include "interpreter/bytecodeHistogram.hpp"
37 #include "interpreter/interpreter.hpp"
38 #include "interpreter/interpreterRuntime.hpp"
39 #include "jvm.h"
40 #include "memory/resourceArea.hpp"
41 #include "memory/universe.hpp"
42 #include "oops/accessDecorators.hpp"
43 #include "oops/compressedKlass.inline.hpp"
44 #include "oops/compressedOops.inline.hpp"
45 #include "oops/klass.inline.hpp"
46 #include "prims/methodHandles.hpp"
47 #include "runtime/continuation.hpp"
48 #include "runtime/interfaceSupport.inline.hpp"
49 #include "runtime/javaThread.hpp"
50 #include "runtime/jniHandles.hpp"
51 #include "runtime/objectMonitor.hpp"
52 #include "runtime/os.hpp"
53 #include "runtime/safepoint.hpp"
54 #include "runtime/safepointMechanism.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/checkedCast.hpp"
58 #include "utilities/macros.hpp"
59
60 #ifdef PRODUCT
61 #define BLOCK_COMMENT(str) /* nothing */
62 #define STOP(error) stop(error)
63 #else
64 #define BLOCK_COMMENT(str) block_comment(str)
65 #define STOP(error) block_comment(error); stop(error)
66 #endif
67
68 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
69
70 #ifdef ASSERT
71 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
72 #endif
73
74 static const Assembler::Condition reverse[] = {
75 Assembler::noOverflow /* overflow = 0x0 */ ,
76 Assembler::overflow /* noOverflow = 0x1 */ ,
77 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
78 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
79 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
80 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
81 Assembler::above /* belowEqual = 0x6 */ ,
82 Assembler::belowEqual /* above = 0x7 */ ,
83 Assembler::positive /* negative = 0x8 */ ,
84 Assembler::negative /* positive = 0x9 */ ,
85 Assembler::noParity /* parity = 0xa */ ,
86 Assembler::parity /* noParity = 0xb */ ,
87 Assembler::greaterEqual /* less = 0xc */ ,
88 Assembler::less /* greaterEqual = 0xd */ ,
89 Assembler::greater /* lessEqual = 0xe */ ,
90 Assembler::lessEqual /* greater = 0xf, */
91
92 };
93
94
95 // Implementation of MacroAssembler
96
97 Address MacroAssembler::as_Address(AddressLiteral adr) {
98 // amd64 always does this as a pc-rel
99 // we can be absolute or disp based on the instruction type
100 // jmp/call are displacements others are absolute
101 assert(!adr.is_lval(), "must be rval");
102 assert(reachable(adr), "must be");
103 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
104
105 }
106
107 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
108 AddressLiteral base = adr.base();
109 lea(rscratch, base);
110 Address index = adr.index();
111 assert(index._disp == 0, "must not have disp"); // maybe it can?
112 Address array(rscratch, index._index, index._scale, index._disp);
113 return array;
114 }
115
116 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
117 Label L, E;
118
119 #ifdef _WIN64
120 // Windows always allocates space for it's register args
121 assert(num_args <= 4, "only register arguments supported");
122 subq(rsp, frame::arg_reg_save_area_bytes);
123 #endif
124
125 // Align stack if necessary
126 testl(rsp, 15);
127 jcc(Assembler::zero, L);
128
129 subq(rsp, 8);
130 call(RuntimeAddress(entry_point));
131 addq(rsp, 8);
132 jmp(E);
133
134 bind(L);
135 call(RuntimeAddress(entry_point));
136
137 bind(E);
138
139 #ifdef _WIN64
140 // restore stack pointer
141 addq(rsp, frame::arg_reg_save_area_bytes);
142 #endif
143 }
144
145 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
146 assert(!src2.is_lval(), "should use cmpptr");
147 assert(rscratch != noreg || always_reachable(src2), "missing");
148
149 if (reachable(src2)) {
150 cmpq(src1, as_Address(src2));
151 } else {
152 lea(rscratch, src2);
153 Assembler::cmpq(src1, Address(rscratch, 0));
154 }
155 }
156
157 int MacroAssembler::corrected_idivq(Register reg) {
158 // Full implementation of Java ldiv and lrem; checks for special
159 // case as described in JVM spec., p.243 & p.271. The function
160 // returns the (pc) offset of the idivl instruction - may be needed
161 // for implicit exceptions.
162 //
163 // normal case special case
164 //
165 // input : rax: dividend min_long
166 // reg: divisor (may not be eax/edx) -1
167 //
168 // output: rax: quotient (= rax idiv reg) min_long
169 // rdx: remainder (= rax irem reg) 0
170 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
171 static const int64_t min_long = 0x8000000000000000;
172 Label normal_case, special_case;
173
174 // check for special case
175 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
176 jcc(Assembler::notEqual, normal_case);
177 xorl(rdx, rdx); // prepare rdx for possible special case (where
178 // remainder = 0)
179 cmpq(reg, -1);
180 jcc(Assembler::equal, special_case);
181
182 // handle normal case
183 bind(normal_case);
184 cdqq();
185 int idivq_offset = offset();
186 idivq(reg);
187
188 // normal and special case exit
189 bind(special_case);
190
191 return idivq_offset;
192 }
193
194 void MacroAssembler::decrementq(Register reg, int value) {
195 if (value == min_jint) { subq(reg, value); return; }
196 if (value < 0) { incrementq(reg, -value); return; }
197 if (value == 0) { ; return; }
198 if (value == 1 && UseIncDec) { decq(reg) ; return; }
199 /* else */ { subq(reg, value) ; return; }
200 }
201
202 void MacroAssembler::decrementq(Address dst, int value) {
203 if (value == min_jint) { subq(dst, value); return; }
204 if (value < 0) { incrementq(dst, -value); return; }
205 if (value == 0) { ; return; }
206 if (value == 1 && UseIncDec) { decq(dst) ; return; }
207 /* else */ { subq(dst, value) ; return; }
208 }
209
210 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
211 assert(rscratch != noreg || always_reachable(dst), "missing");
212
213 if (reachable(dst)) {
214 incrementq(as_Address(dst));
215 } else {
216 lea(rscratch, dst);
217 incrementq(Address(rscratch, 0));
218 }
219 }
220
221 void MacroAssembler::incrementq(Register reg, int value) {
222 if (value == min_jint) { addq(reg, value); return; }
223 if (value < 0) { decrementq(reg, -value); return; }
224 if (value == 0) { ; return; }
225 if (value == 1 && UseIncDec) { incq(reg) ; return; }
226 /* else */ { addq(reg, value) ; return; }
227 }
228
229 void MacroAssembler::incrementq(Address dst, int value) {
230 if (value == min_jint) { addq(dst, value); return; }
231 if (value < 0) { decrementq(dst, -value); return; }
232 if (value == 0) { ; return; }
233 if (value == 1 && UseIncDec) { incq(dst) ; return; }
234 /* else */ { addq(dst, value) ; return; }
235 }
236
237 // 32bit can do a case table jump in one instruction but we no longer allow the base
238 // to be installed in the Address class
239 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
240 lea(rscratch, entry.base());
241 Address dispatch = entry.index();
242 assert(dispatch._base == noreg, "must be");
243 dispatch._base = rscratch;
244 jmp(dispatch);
245 }
246
247 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
248 ShouldNotReachHere(); // 64bit doesn't use two regs
249 cmpq(x_lo, y_lo);
250 }
251
252 void MacroAssembler::lea(Register dst, AddressLiteral src) {
253 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
254 }
255
256 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
257 lea(rscratch, adr);
258 movptr(dst, rscratch);
259 }
260
261 void MacroAssembler::leave() {
262 // %%% is this really better? Why not on 32bit too?
263 emit_int8((unsigned char)0xC9); // LEAVE
264 }
265
266 void MacroAssembler::lneg(Register hi, Register lo) {
267 ShouldNotReachHere(); // 64bit doesn't use two regs
268 negq(lo);
269 }
270
271 void MacroAssembler::movoop(Register dst, jobject obj) {
272 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
273 }
274
275 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
276 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
277 movq(dst, rscratch);
278 }
279
280 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
281 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
282 }
283
284 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
285 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
286 movq(dst, rscratch);
287 }
288
289 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
290 if (src.is_lval()) {
291 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
292 } else {
293 if (reachable(src)) {
294 movq(dst, as_Address(src));
295 } else {
296 lea(dst, src);
297 movq(dst, Address(dst, 0));
298 }
299 }
300 }
301
302 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
303 movq(as_Address(dst, rscratch), src);
304 }
305
306 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
307 movq(dst, as_Address(src, dst /*rscratch*/));
308 }
309
310 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
311 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
312 if (is_simm32(src)) {
313 movptr(dst, checked_cast<int32_t>(src));
314 } else {
315 mov64(rscratch, src);
316 movq(dst, rscratch);
317 }
318 }
319
320 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
321 movoop(rscratch, obj);
322 push(rscratch);
323 }
324
325 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
326 mov_metadata(rscratch, obj);
327 push(rscratch);
328 }
329
330 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
331 lea(rscratch, src);
332 if (src.is_lval()) {
333 push(rscratch);
334 } else {
335 pushq(Address(rscratch, 0));
336 }
337 }
338
339 static void pass_arg0(MacroAssembler* masm, Register arg) {
340 if (c_rarg0 != arg ) {
341 masm->mov(c_rarg0, arg);
342 }
343 }
344
345 static void pass_arg1(MacroAssembler* masm, Register arg) {
346 if (c_rarg1 != arg ) {
347 masm->mov(c_rarg1, arg);
348 }
349 }
350
351 static void pass_arg2(MacroAssembler* masm, Register arg) {
352 if (c_rarg2 != arg ) {
353 masm->mov(c_rarg2, arg);
354 }
355 }
356
357 static void pass_arg3(MacroAssembler* masm, Register arg) {
358 if (c_rarg3 != arg ) {
359 masm->mov(c_rarg3, arg);
360 }
361 }
362
363 void MacroAssembler::stop(const char* msg) {
364 if (ShowMessageBoxOnError) {
365 address rip = pc();
366 pusha(); // get regs on stack
367 lea(c_rarg1, InternalAddress(rip));
368 movq(c_rarg2, rsp); // pass pointer to regs array
369 }
370 // Skip AOT caching C strings in scratch buffer.
371 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
372 lea(c_rarg0, ExternalAddress((address) str));
373 andq(rsp, -16); // align stack as required by ABI
374 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
375 hlt();
376 }
377
378 void MacroAssembler::warn(const char* msg) {
379 push(rbp);
380 movq(rbp, rsp);
381 andq(rsp, -16); // align stack as required by push_CPU_state and call
382 push_CPU_state(); // keeps alignment at 16 bytes
383
384 #ifdef _WIN64
385 // Windows always allocates space for its register args
386 subq(rsp, frame::arg_reg_save_area_bytes);
387 #endif
388 lea(c_rarg0, ExternalAddress((address) msg));
389 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
390
391 #ifdef _WIN64
392 // restore stack pointer
393 addq(rsp, frame::arg_reg_save_area_bytes);
394 #endif
395 pop_CPU_state();
396 mov(rsp, rbp);
397 pop(rbp);
398 }
399
400 void MacroAssembler::print_state() {
401 address rip = pc();
402 pusha(); // get regs on stack
403 push(rbp);
404 movq(rbp, rsp);
405 andq(rsp, -16); // align stack as required by push_CPU_state and call
406 push_CPU_state(); // keeps alignment at 16 bytes
407
408 lea(c_rarg0, InternalAddress(rip));
409 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
410 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
411
412 pop_CPU_state();
413 mov(rsp, rbp);
414 pop(rbp);
415 popa();
416 }
417
418 #ifndef PRODUCT
419 extern "C" void findpc(intptr_t x);
420 #endif
421
422 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
423 // In order to get locks to work, we need to fake a in_VM state
424 if (ShowMessageBoxOnError) {
425 JavaThread* thread = JavaThread::current();
426 JavaThreadState saved_state = thread->thread_state();
427 thread->set_thread_state(_thread_in_vm);
428 #ifndef PRODUCT
429 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
430 ttyLocker ttyl;
431 BytecodeCounter::print();
432 }
433 #endif
434 // To see where a verify_oop failed, get $ebx+40/X for this frame.
435 // XXX correct this offset for amd64
436 // This is the value of eip which points to where verify_oop will return.
437 if (os::message_box(msg, "Execution stopped, print registers?")) {
438 print_state64(pc, regs);
439 BREAKPOINT;
440 }
441 }
442 fatal("DEBUG MESSAGE: %s", msg);
443 }
444
445 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
446 ttyLocker ttyl;
447 DebuggingContext debugging{};
448 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
449 #ifndef PRODUCT
450 tty->cr();
451 findpc(pc);
452 tty->cr();
453 #endif
454 #define PRINT_REG(rax, value) \
455 { tty->print("%s = ", #rax); os::print_location(tty, value); }
456 PRINT_REG(rax, regs[15]);
457 PRINT_REG(rbx, regs[12]);
458 PRINT_REG(rcx, regs[14]);
459 PRINT_REG(rdx, regs[13]);
460 PRINT_REG(rdi, regs[8]);
461 PRINT_REG(rsi, regs[9]);
462 PRINT_REG(rbp, regs[10]);
463 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
464 PRINT_REG(rsp, (intptr_t)(®s[16]));
465 PRINT_REG(r8 , regs[7]);
466 PRINT_REG(r9 , regs[6]);
467 PRINT_REG(r10, regs[5]);
468 PRINT_REG(r11, regs[4]);
469 PRINT_REG(r12, regs[3]);
470 PRINT_REG(r13, regs[2]);
471 PRINT_REG(r14, regs[1]);
472 PRINT_REG(r15, regs[0]);
473 #undef PRINT_REG
474 // Print some words near the top of the stack.
475 int64_t* rsp = ®s[16];
476 int64_t* dump_sp = rsp;
477 for (int col1 = 0; col1 < 8; col1++) {
478 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
479 os::print_location(tty, *dump_sp++);
480 }
481 for (int row = 0; row < 25; row++) {
482 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
483 for (int col = 0; col < 4; col++) {
484 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
485 }
486 tty->cr();
487 }
488 // Print some instructions around pc:
489 Disassembler::decode((address)pc-64, (address)pc);
490 tty->print_cr("--------");
491 Disassembler::decode((address)pc, (address)pc+32);
492 }
493
494 // The java_calling_convention describes stack locations as ideal slots on
495 // a frame with no abi restrictions. Since we must observe abi restrictions
496 // (like the placement of the register window) the slots must be biased by
497 // the following value.
498 static int reg2offset_in(VMReg r) {
499 // Account for saved rbp and return address
500 // This should really be in_preserve_stack_slots
501 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
502 }
503
504 static int reg2offset_out(VMReg r) {
505 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
506 }
507
508 // A long move
509 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
510
511 // The calling conventions assures us that each VMregpair is either
512 // all really one physical register or adjacent stack slots.
513
514 if (src.is_single_phys_reg() ) {
515 if (dst.is_single_phys_reg()) {
516 if (dst.first() != src.first()) {
517 mov(dst.first()->as_Register(), src.first()->as_Register());
518 }
519 } else {
520 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
521 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
522 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
523 }
524 } else if (dst.is_single_phys_reg()) {
525 assert(src.is_single_reg(), "not a stack pair");
526 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
527 } else {
528 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
529 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
530 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
531 }
532 }
533
534 // A double move
535 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
536
537 // The calling conventions assures us that each VMregpair is either
538 // all really one physical register or adjacent stack slots.
539
540 if (src.is_single_phys_reg() ) {
541 if (dst.is_single_phys_reg()) {
542 // In theory these overlap but the ordering is such that this is likely a nop
543 if ( src.first() != dst.first()) {
544 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
545 }
546 } else {
547 assert(dst.is_single_reg(), "not a stack pair");
548 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
549 }
550 } else if (dst.is_single_phys_reg()) {
551 assert(src.is_single_reg(), "not a stack pair");
552 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
553 } else {
554 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
555 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
556 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
557 }
558 }
559
560
561 // A float arg may have to do float reg int reg conversion
562 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
563 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
564
565 // The calling conventions assures us that each VMregpair is either
566 // all really one physical register or adjacent stack slots.
567
568 if (src.first()->is_stack()) {
569 if (dst.first()->is_stack()) {
570 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
571 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
572 } else {
573 // stack to reg
574 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
575 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
576 }
577 } else if (dst.first()->is_stack()) {
578 // reg to stack
579 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
580 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
581 } else {
582 // reg to reg
583 // In theory these overlap but the ordering is such that this is likely a nop
584 if ( src.first() != dst.first()) {
585 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
586 }
587 }
588 }
589
590 // On 64 bit we will store integer like items to the stack as
591 // 64 bits items (x86_32/64 abi) even though java would only store
592 // 32bits for a parameter. On 32bit it will simply be 32 bits
593 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
594 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
595 if (src.first()->is_stack()) {
596 if (dst.first()->is_stack()) {
597 // stack to stack
598 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
599 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
600 } else {
601 // stack to reg
602 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
603 }
604 } else if (dst.first()->is_stack()) {
605 // reg to stack
606 // Do we really have to sign extend???
607 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
608 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
609 } else {
610 // Do we really have to sign extend???
611 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
612 if (dst.first() != src.first()) {
613 movq(dst.first()->as_Register(), src.first()->as_Register());
614 }
615 }
616 }
617
618 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
619 if (src.first()->is_stack()) {
620 if (dst.first()->is_stack()) {
621 // stack to stack
622 movq(rax, Address(rbp, reg2offset_in(src.first())));
623 movq(Address(rsp, reg2offset_out(dst.first())), rax);
624 } else {
625 // stack to reg
626 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
627 }
628 } else if (dst.first()->is_stack()) {
629 // reg to stack
630 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
631 } else {
632 if (dst.first() != src.first()) {
633 movq(dst.first()->as_Register(), src.first()->as_Register());
634 }
635 }
636 }
637
638 // An oop arg. Must pass a handle not the oop itself
639 void MacroAssembler::object_move(OopMap* map,
640 int oop_handle_offset,
641 int framesize_in_slots,
642 VMRegPair src,
643 VMRegPair dst,
644 bool is_receiver,
645 int* receiver_offset) {
646
647 // must pass a handle. First figure out the location we use as a handle
648
649 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
650
651 // See if oop is null if it is we need no handle
652
653 if (src.first()->is_stack()) {
654
655 // Oop is already on the stack as an argument
656 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
657 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
658 if (is_receiver) {
659 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
660 }
661
662 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
663 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
664 // conditionally move a null
665 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
666 } else {
667
668 // Oop is in a register we must store it to the space we reserve
669 // on the stack for oop_handles and pass a handle if oop is non-null
670
671 const Register rOop = src.first()->as_Register();
672 int oop_slot;
673 if (rOop == j_rarg0)
674 oop_slot = 0;
675 else if (rOop == j_rarg1)
676 oop_slot = 1;
677 else if (rOop == j_rarg2)
678 oop_slot = 2;
679 else if (rOop == j_rarg3)
680 oop_slot = 3;
681 else if (rOop == j_rarg4)
682 oop_slot = 4;
683 else {
684 assert(rOop == j_rarg5, "wrong register");
685 oop_slot = 5;
686 }
687
688 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
689 int offset = oop_slot*VMRegImpl::stack_slot_size;
690
691 map->set_oop(VMRegImpl::stack2reg(oop_slot));
692 // Store oop in handle area, may be null
693 movptr(Address(rsp, offset), rOop);
694 if (is_receiver) {
695 *receiver_offset = offset;
696 }
697
698 cmpptr(rOop, NULL_WORD);
699 lea(rHandle, Address(rsp, offset));
700 // conditionally move a null from the handle area where it was just stored
701 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
702 }
703
704 // If arg is on the stack then place it otherwise it is already in correct reg.
705 if (dst.first()->is_stack()) {
706 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
707 }
708 }
709
710 void MacroAssembler::addptr(Register dst, int32_t imm32) {
711 addq(dst, imm32);
712 }
713
714 void MacroAssembler::addptr(Register dst, Register src) {
715 addq(dst, src);
716 }
717
718 void MacroAssembler::addptr(Address dst, Register src) {
719 addq(dst, src);
720 }
721
722 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
723 assert(rscratch != noreg || always_reachable(src), "missing");
724
725 if (reachable(src)) {
726 Assembler::addsd(dst, as_Address(src));
727 } else {
728 lea(rscratch, src);
729 Assembler::addsd(dst, Address(rscratch, 0));
730 }
731 }
732
733 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
734 assert(rscratch != noreg || always_reachable(src), "missing");
735
736 if (reachable(src)) {
737 addss(dst, as_Address(src));
738 } else {
739 lea(rscratch, src);
740 addss(dst, Address(rscratch, 0));
741 }
742 }
743
744 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
745 assert(rscratch != noreg || always_reachable(src), "missing");
746
747 if (reachable(src)) {
748 Assembler::addpd(dst, as_Address(src));
749 } else {
750 lea(rscratch, src);
751 Assembler::addpd(dst, Address(rscratch, 0));
752 }
753 }
754
755 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
756 // Stub code is generated once and never copied.
757 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
758 void MacroAssembler::align64() {
759 align(64, (uint)(uintptr_t)pc());
760 }
761
762 void MacroAssembler::align32() {
763 align(32, (uint)(uintptr_t)pc());
764 }
765
766 void MacroAssembler::align(uint modulus) {
767 // 8273459: Ensure alignment is possible with current segment alignment
768 assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
769 align(modulus, offset());
770 }
771
772 void MacroAssembler::align(uint modulus, uint target) {
773 if (target % modulus != 0) {
774 nop(modulus - (target % modulus));
775 }
776 }
777
778 void MacroAssembler::push_f(XMMRegister r) {
779 subptr(rsp, wordSize);
780 movflt(Address(rsp, 0), r);
781 }
782
783 void MacroAssembler::pop_f(XMMRegister r) {
784 movflt(r, Address(rsp, 0));
785 addptr(rsp, wordSize);
786 }
787
788 void MacroAssembler::push_d(XMMRegister r) {
789 subptr(rsp, 2 * wordSize);
790 movdbl(Address(rsp, 0), r);
791 }
792
793 void MacroAssembler::pop_d(XMMRegister r) {
794 movdbl(r, Address(rsp, 0));
795 addptr(rsp, 2 * Interpreter::stackElementSize);
796 }
797
798 void MacroAssembler::push_ppx(Register src) {
799 if (VM_Version::supports_apx_f()) {
800 pushp(src);
801 } else {
802 Assembler::push(src);
803 }
804 }
805
806 void MacroAssembler::pop_ppx(Register dst) {
807 if (VM_Version::supports_apx_f()) {
808 popp(dst);
809 } else {
810 Assembler::pop(dst);
811 }
812 }
813
814 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
815 // Used in sign-masking with aligned address.
816 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
817 assert(rscratch != noreg || always_reachable(src), "missing");
818
819 if (UseAVX > 2 &&
820 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
821 (dst->encoding() >= 16)) {
822 vpand(dst, dst, src, AVX_512bit, rscratch);
823 } else if (reachable(src)) {
824 Assembler::andpd(dst, as_Address(src));
825 } else {
826 lea(rscratch, src);
827 Assembler::andpd(dst, Address(rscratch, 0));
828 }
829 }
830
831 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
832 // Used in sign-masking with aligned address.
833 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
834 assert(rscratch != noreg || always_reachable(src), "missing");
835
836 if (reachable(src)) {
837 Assembler::andps(dst, as_Address(src));
838 } else {
839 lea(rscratch, src);
840 Assembler::andps(dst, Address(rscratch, 0));
841 }
842 }
843
844 void MacroAssembler::andptr(Register dst, int32_t imm32) {
845 andq(dst, imm32);
846 }
847
848 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
849 assert(rscratch != noreg || always_reachable(src), "missing");
850
851 if (reachable(src)) {
852 andq(dst, as_Address(src));
853 } else {
854 lea(rscratch, src);
855 andq(dst, Address(rscratch, 0));
856 }
857 }
858
859 void MacroAssembler::atomic_incl(Address counter_addr) {
860 lock();
861 incrementl(counter_addr);
862 }
863
864 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
865 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
866
867 if (reachable(counter_addr)) {
868 atomic_incl(as_Address(counter_addr));
869 } else {
870 lea(rscratch, counter_addr);
871 atomic_incl(Address(rscratch, 0));
872 }
873 }
874
875 void MacroAssembler::atomic_incq(Address counter_addr) {
876 lock();
877 incrementq(counter_addr);
878 }
879
880 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
881 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
882
883 if (reachable(counter_addr)) {
884 atomic_incq(as_Address(counter_addr));
885 } else {
886 lea(rscratch, counter_addr);
887 atomic_incq(Address(rscratch, 0));
888 }
889 }
890
891 // Writes to stack successive pages until offset reached to check for
892 // stack overflow + shadow pages. This clobbers tmp.
893 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
894 movptr(tmp, rsp);
895 // Bang stack for total size given plus shadow page size.
896 // Bang one page at a time because large size can bang beyond yellow and
897 // red zones.
898 Label loop;
899 bind(loop);
900 movl(Address(tmp, (-(int)os::vm_page_size())), size );
901 subptr(tmp, (int)os::vm_page_size());
902 subl(size, (int)os::vm_page_size());
903 jcc(Assembler::greater, loop);
904
905 // Bang down shadow pages too.
906 // At this point, (tmp-0) is the last address touched, so don't
907 // touch it again. (It was touched as (tmp-pagesize) but then tmp
908 // was post-decremented.) Skip this address by starting at i=1, and
909 // touch a few more pages below. N.B. It is important to touch all
910 // the way down including all pages in the shadow zone.
911 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
912 // this could be any sized move but this is can be a debugging crumb
913 // so the bigger the better.
914 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
915 }
916 }
917
918 void MacroAssembler::reserved_stack_check() {
919 // testing if reserved zone needs to be enabled
920 Label no_reserved_zone_enabling;
921
922 cmpptr(rsp, Address(r15_thread, JavaThread::reserved_stack_activation_offset()));
923 jcc(Assembler::below, no_reserved_zone_enabling);
924
925 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), r15_thread);
926 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
927 should_not_reach_here();
928
929 bind(no_reserved_zone_enabling);
930 }
931
932 void MacroAssembler::c2bool(Register x) {
933 // implements x == 0 ? 0 : 1
934 // note: must only look at least-significant byte of x
935 // since C-style booleans are stored in one byte
936 // only! (was bug)
937 andl(x, 0xFF);
938 setb(Assembler::notZero, x);
939 }
940
941 // Wouldn't need if AddressLiteral version had new name
942 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
943 Assembler::call(L, rtype);
944 }
945
946 void MacroAssembler::call(Register entry) {
947 Assembler::call(entry);
948 }
949
950 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
951 assert(rscratch != noreg || always_reachable(entry), "missing");
952
953 if (reachable(entry)) {
954 Assembler::call_literal(entry.target(), entry.rspec());
955 } else {
956 lea(rscratch, entry);
957 Assembler::call(rscratch);
958 }
959 }
960
961 void MacroAssembler::ic_call(address entry, jint method_index) {
962 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
963 // Needs full 64-bit immediate for later patching.
964 mov64(rax, (int64_t)Universe::non_oop_word());
965 call(AddressLiteral(entry, rh));
966 }
967
968 int MacroAssembler::ic_check_size() {
969 return UseCompactObjectHeaders ? 17 : 14;
970 }
971
972 int MacroAssembler::ic_check(int end_alignment) {
973 Register receiver = j_rarg0;
974 Register data = rax;
975 Register temp = rscratch1;
976
977 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
978 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
979 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
980 // before the inline cache check here, and not after
981 align(end_alignment, offset() + ic_check_size());
982
983 int uep_offset = offset();
984
985 if (UseCompactObjectHeaders) {
986 load_narrow_klass_compact(temp, receiver);
987 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
988 } else if (UseCompressedClassPointers) {
989 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
990 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
991 } else {
992 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
993 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
994 }
995
996 // if inline cache check fails, then jump to runtime routine
997 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
998 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
999
1000 return uep_offset;
1001 }
1002
1003 void MacroAssembler::emit_static_call_stub() {
1004 // Static stub relocation also tags the Method* in the code-stream.
1005 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1006 // This is recognized as unresolved by relocs/nativeinst/ic code.
1007 jump(RuntimeAddress(pc()));
1008 }
1009
1010 // Implementation of call_VM versions
1011
1012 void MacroAssembler::call_VM(Register oop_result,
1013 address entry_point,
1014 bool check_exceptions) {
1015 Label C, E;
1016 call(C, relocInfo::none);
1017 jmp(E);
1018
1019 bind(C);
1020 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1021 ret(0);
1022
1023 bind(E);
1024 }
1025
1026 void MacroAssembler::call_VM(Register oop_result,
1027 address entry_point,
1028 Register arg_1,
1029 bool check_exceptions) {
1030 Label C, E;
1031 call(C, relocInfo::none);
1032 jmp(E);
1033
1034 bind(C);
1035 pass_arg1(this, arg_1);
1036 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1037 ret(0);
1038
1039 bind(E);
1040 }
1041
1042 void MacroAssembler::call_VM(Register oop_result,
1043 address entry_point,
1044 Register arg_1,
1045 Register arg_2,
1046 bool check_exceptions) {
1047 Label C, E;
1048 call(C, relocInfo::none);
1049 jmp(E);
1050
1051 bind(C);
1052
1053 assert_different_registers(arg_1, c_rarg2);
1054
1055 pass_arg2(this, arg_2);
1056 pass_arg1(this, arg_1);
1057 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1058 ret(0);
1059
1060 bind(E);
1061 }
1062
1063 void MacroAssembler::call_VM(Register oop_result,
1064 address entry_point,
1065 Register arg_1,
1066 Register arg_2,
1067 Register arg_3,
1068 bool check_exceptions) {
1069 Label C, E;
1070 call(C, relocInfo::none);
1071 jmp(E);
1072
1073 bind(C);
1074
1075 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1076 assert_different_registers(arg_2, c_rarg3);
1077 pass_arg3(this, arg_3);
1078 pass_arg2(this, arg_2);
1079 pass_arg1(this, arg_1);
1080 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1081 ret(0);
1082
1083 bind(E);
1084 }
1085
1086 void MacroAssembler::call_VM(Register oop_result,
1087 Register last_java_sp,
1088 address entry_point,
1089 int number_of_arguments,
1090 bool check_exceptions) {
1091 call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1092 }
1093
1094 void MacroAssembler::call_VM(Register oop_result,
1095 Register last_java_sp,
1096 address entry_point,
1097 Register arg_1,
1098 bool check_exceptions) {
1099 pass_arg1(this, arg_1);
1100 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1101 }
1102
1103 void MacroAssembler::call_VM(Register oop_result,
1104 Register last_java_sp,
1105 address entry_point,
1106 Register arg_1,
1107 Register arg_2,
1108 bool check_exceptions) {
1109
1110 assert_different_registers(arg_1, c_rarg2);
1111 pass_arg2(this, arg_2);
1112 pass_arg1(this, arg_1);
1113 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1114 }
1115
1116 void MacroAssembler::call_VM(Register oop_result,
1117 Register last_java_sp,
1118 address entry_point,
1119 Register arg_1,
1120 Register arg_2,
1121 Register arg_3,
1122 bool check_exceptions) {
1123 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1124 assert_different_registers(arg_2, c_rarg3);
1125 pass_arg3(this, arg_3);
1126 pass_arg2(this, arg_2);
1127 pass_arg1(this, arg_1);
1128 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1129 }
1130
1131 void MacroAssembler::super_call_VM(Register oop_result,
1132 Register last_java_sp,
1133 address entry_point,
1134 int number_of_arguments,
1135 bool check_exceptions) {
1136 MacroAssembler::call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1137 }
1138
1139 void MacroAssembler::super_call_VM(Register oop_result,
1140 Register last_java_sp,
1141 address entry_point,
1142 Register arg_1,
1143 bool check_exceptions) {
1144 pass_arg1(this, arg_1);
1145 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1146 }
1147
1148 void MacroAssembler::super_call_VM(Register oop_result,
1149 Register last_java_sp,
1150 address entry_point,
1151 Register arg_1,
1152 Register arg_2,
1153 bool check_exceptions) {
1154
1155 assert_different_registers(arg_1, c_rarg2);
1156 pass_arg2(this, arg_2);
1157 pass_arg1(this, arg_1);
1158 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1159 }
1160
1161 void MacroAssembler::super_call_VM(Register oop_result,
1162 Register last_java_sp,
1163 address entry_point,
1164 Register arg_1,
1165 Register arg_2,
1166 Register arg_3,
1167 bool check_exceptions) {
1168 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1169 assert_different_registers(arg_2, c_rarg3);
1170 pass_arg3(this, arg_3);
1171 pass_arg2(this, arg_2);
1172 pass_arg1(this, arg_1);
1173 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1174 }
1175
1176 void MacroAssembler::call_VM_base(Register oop_result,
1177 Register last_java_sp,
1178 address entry_point,
1179 int number_of_arguments,
1180 bool check_exceptions) {
1181 Register java_thread = r15_thread;
1182
1183 // determine last_java_sp register
1184 if (!last_java_sp->is_valid()) {
1185 last_java_sp = rsp;
1186 }
1187 // debugging support
1188 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1189 #ifdef ASSERT
1190 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1191 // r12 is the heapbase.
1192 if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
1193 #endif // ASSERT
1194
1195 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1196 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1197
1198 // push java thread (becomes first argument of C function)
1199
1200 mov(c_rarg0, r15_thread);
1201
1202 // set last Java frame before call
1203 assert(last_java_sp != rbp, "can't use ebp/rbp");
1204
1205 // Only interpreter should have to set fp
1206 set_last_Java_frame(last_java_sp, rbp, nullptr, rscratch1);
1207
1208 // do the call, remove parameters
1209 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1210
1211 #ifdef ASSERT
1212 // Check that thread register is not clobbered.
1213 guarantee(java_thread != rax, "change this code");
1214 push(rax);
1215 { Label L;
1216 get_thread_slow(rax);
1217 cmpptr(java_thread, rax);
1218 jcc(Assembler::equal, L);
1219 STOP("MacroAssembler::call_VM_base: java_thread not callee saved?");
1220 bind(L);
1221 }
1222 pop(rax);
1223 #endif
1224
1225 // reset last Java frame
1226 // Only interpreter should have to clear fp
1227 reset_last_Java_frame(true);
1228
1229 // C++ interp handles this in the interpreter
1230 check_and_handle_popframe();
1231 check_and_handle_earlyret();
1232
1233 if (check_exceptions) {
1234 // check for pending exceptions (java_thread is set upon return)
1235 cmpptr(Address(r15_thread, Thread::pending_exception_offset()), NULL_WORD);
1236 // This used to conditionally jump to forward_exception however it is
1237 // possible if we relocate that the branch will not reach. So we must jump
1238 // around so we can always reach
1239
1240 Label ok;
1241 jcc(Assembler::equal, ok);
1242 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1243 bind(ok);
1244 }
1245
1246 // get oop result if there is one and reset the value in the thread
1247 if (oop_result->is_valid()) {
1248 get_vm_result_oop(oop_result);
1249 }
1250 }
1251
1252 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1253 // Calculate the value for last_Java_sp somewhat subtle.
1254 // call_VM does an intermediate call which places a return address on
1255 // the stack just under the stack pointer as the user finished with it.
1256 // This allows use to retrieve last_Java_pc from last_Java_sp[-1].
1257
1258 // We've pushed one address, correct last_Java_sp
1259 lea(rax, Address(rsp, wordSize));
1260
1261 call_VM_base(oop_result, rax, entry_point, number_of_arguments, check_exceptions);
1262 }
1263
1264 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1265 void MacroAssembler::call_VM_leaf0(address entry_point) {
1266 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1267 }
1268
1269 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1270 call_VM_leaf_base(entry_point, number_of_arguments);
1271 }
1272
1273 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1274 pass_arg0(this, arg_0);
1275 call_VM_leaf(entry_point, 1);
1276 }
1277
1278 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1279
1280 assert_different_registers(arg_0, c_rarg1);
1281 pass_arg1(this, arg_1);
1282 pass_arg0(this, arg_0);
1283 call_VM_leaf(entry_point, 2);
1284 }
1285
1286 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1287 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1288 assert_different_registers(arg_1, c_rarg2);
1289 pass_arg2(this, arg_2);
1290 pass_arg1(this, arg_1);
1291 pass_arg0(this, arg_0);
1292 call_VM_leaf(entry_point, 3);
1293 }
1294
1295 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1296 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1297 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1298 assert_different_registers(arg_2, c_rarg3);
1299 pass_arg3(this, arg_3);
1300 pass_arg2(this, arg_2);
1301 pass_arg1(this, arg_1);
1302 pass_arg0(this, arg_0);
1303 call_VM_leaf(entry_point, 3);
1304 }
1305
1306 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1307 pass_arg0(this, arg_0);
1308 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1309 }
1310
1311 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1312 assert_different_registers(arg_0, c_rarg1);
1313 pass_arg1(this, arg_1);
1314 pass_arg0(this, arg_0);
1315 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1316 }
1317
1318 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1319 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1320 assert_different_registers(arg_1, c_rarg2);
1321 pass_arg2(this, arg_2);
1322 pass_arg1(this, arg_1);
1323 pass_arg0(this, arg_0);
1324 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1325 }
1326
1327 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1328 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1329 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1330 assert_different_registers(arg_2, c_rarg3);
1331 pass_arg3(this, arg_3);
1332 pass_arg2(this, arg_2);
1333 pass_arg1(this, arg_1);
1334 pass_arg0(this, arg_0);
1335 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1336 }
1337
1338 void MacroAssembler::get_vm_result_oop(Register oop_result) {
1339 movptr(oop_result, Address(r15_thread, JavaThread::vm_result_oop_offset()));
1340 movptr(Address(r15_thread, JavaThread::vm_result_oop_offset()), NULL_WORD);
1341 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1342 }
1343
1344 void MacroAssembler::get_vm_result_metadata(Register metadata_result) {
1345 movptr(metadata_result, Address(r15_thread, JavaThread::vm_result_metadata_offset()));
1346 movptr(Address(r15_thread, JavaThread::vm_result_metadata_offset()), NULL_WORD);
1347 }
1348
1349 void MacroAssembler::check_and_handle_earlyret() {
1350 }
1351
1352 void MacroAssembler::check_and_handle_popframe() {
1353 }
1354
1355 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1356 assert(rscratch != noreg || always_reachable(src1), "missing");
1357
1358 if (reachable(src1)) {
1359 cmpl(as_Address(src1), imm);
1360 } else {
1361 lea(rscratch, src1);
1362 cmpl(Address(rscratch, 0), imm);
1363 }
1364 }
1365
1366 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1367 assert(!src2.is_lval(), "use cmpptr");
1368 assert(rscratch != noreg || always_reachable(src2), "missing");
1369
1370 if (reachable(src2)) {
1371 cmpl(src1, as_Address(src2));
1372 } else {
1373 lea(rscratch, src2);
1374 cmpl(src1, Address(rscratch, 0));
1375 }
1376 }
1377
1378 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1379 Assembler::cmpl(src1, imm);
1380 }
1381
1382 void MacroAssembler::cmp32(Register src1, Address src2) {
1383 Assembler::cmpl(src1, src2);
1384 }
1385
1386 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1387 ucomisd(opr1, opr2);
1388
1389 Label L;
1390 if (unordered_is_less) {
1391 movl(dst, -1);
1392 jcc(Assembler::parity, L);
1393 jcc(Assembler::below , L);
1394 movl(dst, 0);
1395 jcc(Assembler::equal , L);
1396 increment(dst);
1397 } else { // unordered is greater
1398 movl(dst, 1);
1399 jcc(Assembler::parity, L);
1400 jcc(Assembler::above , L);
1401 movl(dst, 0);
1402 jcc(Assembler::equal , L);
1403 decrementl(dst);
1404 }
1405 bind(L);
1406 }
1407
1408 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1409 ucomiss(opr1, opr2);
1410
1411 Label L;
1412 if (unordered_is_less) {
1413 movl(dst, -1);
1414 jcc(Assembler::parity, L);
1415 jcc(Assembler::below , L);
1416 movl(dst, 0);
1417 jcc(Assembler::equal , L);
1418 increment(dst);
1419 } else { // unordered is greater
1420 movl(dst, 1);
1421 jcc(Assembler::parity, L);
1422 jcc(Assembler::above , L);
1423 movl(dst, 0);
1424 jcc(Assembler::equal , L);
1425 decrementl(dst);
1426 }
1427 bind(L);
1428 }
1429
1430
1431 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1432 assert(rscratch != noreg || always_reachable(src1), "missing");
1433
1434 if (reachable(src1)) {
1435 cmpb(as_Address(src1), imm);
1436 } else {
1437 lea(rscratch, src1);
1438 cmpb(Address(rscratch, 0), imm);
1439 }
1440 }
1441
1442 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1443 assert(rscratch != noreg || always_reachable(src2), "missing");
1444
1445 if (src2.is_lval()) {
1446 movptr(rscratch, src2);
1447 Assembler::cmpq(src1, rscratch);
1448 } else if (reachable(src2)) {
1449 cmpq(src1, as_Address(src2));
1450 } else {
1451 lea(rscratch, src2);
1452 Assembler::cmpq(src1, Address(rscratch, 0));
1453 }
1454 }
1455
1456 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1457 assert(src2.is_lval(), "not a mem-mem compare");
1458 // moves src2's literal address
1459 movptr(rscratch, src2);
1460 Assembler::cmpq(src1, rscratch);
1461 }
1462
1463 void MacroAssembler::cmpoop(Register src1, Register src2) {
1464 cmpptr(src1, src2);
1465 }
1466
1467 void MacroAssembler::cmpoop(Register src1, Address src2) {
1468 cmpptr(src1, src2);
1469 }
1470
1471 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1472 movoop(rscratch, src2);
1473 cmpptr(src1, rscratch);
1474 }
1475
1476 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1477 assert(rscratch != noreg || always_reachable(adr), "missing");
1478
1479 if (reachable(adr)) {
1480 lock();
1481 cmpxchgptr(reg, as_Address(adr));
1482 } else {
1483 lea(rscratch, adr);
1484 lock();
1485 cmpxchgptr(reg, Address(rscratch, 0));
1486 }
1487 }
1488
1489 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1490 cmpxchgq(reg, adr);
1491 }
1492
1493 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1494 assert(rscratch != noreg || always_reachable(src), "missing");
1495
1496 if (reachable(src)) {
1497 Assembler::comisd(dst, as_Address(src));
1498 } else {
1499 lea(rscratch, src);
1500 Assembler::comisd(dst, Address(rscratch, 0));
1501 }
1502 }
1503
1504 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1505 assert(rscratch != noreg || always_reachable(src), "missing");
1506
1507 if (reachable(src)) {
1508 Assembler::comiss(dst, as_Address(src));
1509 } else {
1510 lea(rscratch, src);
1511 Assembler::comiss(dst, Address(rscratch, 0));
1512 }
1513 }
1514
1515
1516 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1517 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1518
1519 Condition negated_cond = negate_condition(cond);
1520 Label L;
1521 jcc(negated_cond, L);
1522 pushf(); // Preserve flags
1523 atomic_incl(counter_addr, rscratch);
1524 popf();
1525 bind(L);
1526 }
1527
1528 int MacroAssembler::corrected_idivl(Register reg) {
1529 // Full implementation of Java idiv and irem; checks for
1530 // special case as described in JVM spec., p.243 & p.271.
1531 // The function returns the (pc) offset of the idivl
1532 // instruction - may be needed for implicit exceptions.
1533 //
1534 // normal case special case
1535 //
1536 // input : rax,: dividend min_int
1537 // reg: divisor (may not be rax,/rdx) -1
1538 //
1539 // output: rax,: quotient (= rax, idiv reg) min_int
1540 // rdx: remainder (= rax, irem reg) 0
1541 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1542 const int min_int = 0x80000000;
1543 Label normal_case, special_case;
1544
1545 // check for special case
1546 cmpl(rax, min_int);
1547 jcc(Assembler::notEqual, normal_case);
1548 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1549 cmpl(reg, -1);
1550 jcc(Assembler::equal, special_case);
1551
1552 // handle normal case
1553 bind(normal_case);
1554 cdql();
1555 int idivl_offset = offset();
1556 idivl(reg);
1557
1558 // normal and special case exit
1559 bind(special_case);
1560
1561 return idivl_offset;
1562 }
1563
1564
1565
1566 void MacroAssembler::decrementl(Register reg, int value) {
1567 if (value == min_jint) {subl(reg, value) ; return; }
1568 if (value < 0) { incrementl(reg, -value); return; }
1569 if (value == 0) { ; return; }
1570 if (value == 1 && UseIncDec) { decl(reg) ; return; }
1571 /* else */ { subl(reg, value) ; return; }
1572 }
1573
1574 void MacroAssembler::decrementl(Address dst, int value) {
1575 if (value == min_jint) {subl(dst, value) ; return; }
1576 if (value < 0) { incrementl(dst, -value); return; }
1577 if (value == 0) { ; return; }
1578 if (value == 1 && UseIncDec) { decl(dst) ; return; }
1579 /* else */ { subl(dst, value) ; return; }
1580 }
1581
1582 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1583 assert(shift_value > 0, "illegal shift value");
1584 Label _is_positive;
1585 testl (reg, reg);
1586 jcc (Assembler::positive, _is_positive);
1587 int offset = (1 << shift_value) - 1 ;
1588
1589 if (offset == 1) {
1590 incrementl(reg);
1591 } else {
1592 addl(reg, offset);
1593 }
1594
1595 bind (_is_positive);
1596 sarl(reg, shift_value);
1597 }
1598
1599 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1600 assert(rscratch != noreg || always_reachable(src), "missing");
1601
1602 if (reachable(src)) {
1603 Assembler::divsd(dst, as_Address(src));
1604 } else {
1605 lea(rscratch, src);
1606 Assembler::divsd(dst, Address(rscratch, 0));
1607 }
1608 }
1609
1610 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1611 assert(rscratch != noreg || always_reachable(src), "missing");
1612
1613 if (reachable(src)) {
1614 Assembler::divss(dst, as_Address(src));
1615 } else {
1616 lea(rscratch, src);
1617 Assembler::divss(dst, Address(rscratch, 0));
1618 }
1619 }
1620
1621 void MacroAssembler::enter() {
1622 push(rbp);
1623 mov(rbp, rsp);
1624 }
1625
1626 void MacroAssembler::post_call_nop() {
1627 if (!Continuations::enabled()) {
1628 return;
1629 }
1630 InstructionMark im(this);
1631 relocate(post_call_nop_Relocation::spec());
1632 InlineSkippedInstructionsCounter skipCounter(this);
1633 emit_int8((uint8_t)0x0f);
1634 emit_int8((uint8_t)0x1f);
1635 emit_int8((uint8_t)0x84);
1636 emit_int8((uint8_t)0x00);
1637 emit_int32(0x00);
1638 }
1639
1640 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1641 assert(rscratch != noreg || always_reachable(src), "missing");
1642 if (reachable(src)) {
1643 Assembler::mulpd(dst, as_Address(src));
1644 } else {
1645 lea(rscratch, src);
1646 Assembler::mulpd(dst, Address(rscratch, 0));
1647 }
1648 }
1649
1650 // dst = c = a * b + c
1651 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1652 Assembler::vfmadd231sd(c, a, b);
1653 if (dst != c) {
1654 movdbl(dst, c);
1655 }
1656 }
1657
1658 // dst = c = a * b + c
1659 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1660 Assembler::vfmadd231ss(c, a, b);
1661 if (dst != c) {
1662 movflt(dst, c);
1663 }
1664 }
1665
1666 // dst = c = a * b + c
1667 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1668 Assembler::vfmadd231pd(c, a, b, vector_len);
1669 if (dst != c) {
1670 vmovdqu(dst, c);
1671 }
1672 }
1673
1674 // dst = c = a * b + c
1675 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1676 Assembler::vfmadd231ps(c, a, b, vector_len);
1677 if (dst != c) {
1678 vmovdqu(dst, c);
1679 }
1680 }
1681
1682 // dst = c = a * b + c
1683 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1684 Assembler::vfmadd231pd(c, a, b, vector_len);
1685 if (dst != c) {
1686 vmovdqu(dst, c);
1687 }
1688 }
1689
1690 // dst = c = a * b + c
1691 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1692 Assembler::vfmadd231ps(c, a, b, vector_len);
1693 if (dst != c) {
1694 vmovdqu(dst, c);
1695 }
1696 }
1697
1698 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
1699 assert(rscratch != noreg || always_reachable(dst), "missing");
1700
1701 if (reachable(dst)) {
1702 incrementl(as_Address(dst));
1703 } else {
1704 lea(rscratch, dst);
1705 incrementl(Address(rscratch, 0));
1706 }
1707 }
1708
1709 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
1710 incrementl(as_Address(dst, rscratch));
1711 }
1712
1713 void MacroAssembler::incrementl(Register reg, int value) {
1714 if (value == min_jint) {addl(reg, value) ; return; }
1715 if (value < 0) { decrementl(reg, -value); return; }
1716 if (value == 0) { ; return; }
1717 if (value == 1 && UseIncDec) { incl(reg) ; return; }
1718 /* else */ { addl(reg, value) ; return; }
1719 }
1720
1721 void MacroAssembler::incrementl(Address dst, int value) {
1722 if (value == min_jint) {addl(dst, value) ; return; }
1723 if (value < 0) { decrementl(dst, -value); return; }
1724 if (value == 0) { ; return; }
1725 if (value == 1 && UseIncDec) { incl(dst) ; return; }
1726 /* else */ { addl(dst, value) ; return; }
1727 }
1728
1729 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
1730 assert(rscratch != noreg || always_reachable(dst), "missing");
1731 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
1732 if (reachable(dst)) {
1733 jmp_literal(dst.target(), dst.rspec());
1734 } else {
1735 lea(rscratch, dst);
1736 jmp(rscratch);
1737 }
1738 }
1739
1740 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
1741 assert(rscratch != noreg || always_reachable(dst), "missing");
1742 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
1743 if (reachable(dst)) {
1744 InstructionMark im(this);
1745 relocate(dst.reloc());
1746 const int short_size = 2;
1747 const int long_size = 6;
1748 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
1749 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
1750 // 0111 tttn #8-bit disp
1751 emit_int8(0x70 | cc);
1752 emit_int8((offs - short_size) & 0xFF);
1753 } else {
1754 // 0000 1111 1000 tttn #32-bit disp
1755 emit_int8(0x0F);
1756 emit_int8((unsigned char)(0x80 | cc));
1757 emit_int32(offs - long_size);
1758 }
1759 } else {
1760 #ifdef ASSERT
1761 warning("reversing conditional branch");
1762 #endif /* ASSERT */
1763 Label skip;
1764 jccb(reverse[cc], skip);
1765 lea(rscratch, dst);
1766 Assembler::jmp(rscratch);
1767 bind(skip);
1768 }
1769 }
1770
1771 void MacroAssembler::cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch) {
1772 ExternalAddress mxcsr_std(StubRoutines::x86::addr_mxcsr_std());
1773 assert(rscratch != noreg || always_reachable(mxcsr_std), "missing");
1774
1775 stmxcsr(mxcsr_save);
1776 movl(tmp, mxcsr_save);
1777 if (EnableX86ECoreOpts) {
1778 // The mxcsr_std has status bits set for performance on ECore
1779 orl(tmp, 0x003f);
1780 } else {
1781 // Mask out status bits (only check control and mask bits)
1782 andl(tmp, 0xFFC0);
1783 }
1784 cmp32(tmp, mxcsr_std, rscratch);
1785 }
1786
1787 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
1788 assert(rscratch != noreg || always_reachable(src), "missing");
1789
1790 if (reachable(src)) {
1791 Assembler::ldmxcsr(as_Address(src));
1792 } else {
1793 lea(rscratch, src);
1794 Assembler::ldmxcsr(Address(rscratch, 0));
1795 }
1796 }
1797
1798 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1799 int off = offset();
1800 movsbl(dst, src); // movsxb
1801 return off;
1802 }
1803
1804 // Note: load_signed_short used to be called load_signed_word.
1805 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
1806 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
1807 // The term "word" in HotSpot means a 32- or 64-bit machine word.
1808 int MacroAssembler::load_signed_short(Register dst, Address src) {
1809 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
1810 // version but this is what 64bit has always done. This seems to imply
1811 // that users are only using 32bits worth.
1812 int off = offset();
1813 movswl(dst, src); // movsxw
1814 return off;
1815 }
1816
1817 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1818 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1819 // and "3.9 Partial Register Penalties", p. 22).
1820 int off = offset();
1821 movzbl(dst, src); // movzxb
1822 return off;
1823 }
1824
1825 // Note: load_unsigned_short used to be called load_unsigned_word.
1826 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1827 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1828 // and "3.9 Partial Register Penalties", p. 22).
1829 int off = offset();
1830 movzwl(dst, src); // movzxw
1831 return off;
1832 }
1833
1834 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1835 switch (size_in_bytes) {
1836 case 8: movq(dst, src); break;
1837 case 4: movl(dst, src); break;
1838 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1839 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1840 default: ShouldNotReachHere();
1841 }
1842 }
1843
1844 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1845 switch (size_in_bytes) {
1846 case 8: movq(dst, src); break;
1847 case 4: movl(dst, src); break;
1848 case 2: movw(dst, src); break;
1849 case 1: movb(dst, src); break;
1850 default: ShouldNotReachHere();
1851 }
1852 }
1853
1854 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
1855 assert(rscratch != noreg || always_reachable(dst), "missing");
1856
1857 if (reachable(dst)) {
1858 movl(as_Address(dst), src);
1859 } else {
1860 lea(rscratch, dst);
1861 movl(Address(rscratch, 0), src);
1862 }
1863 }
1864
1865 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
1866 if (reachable(src)) {
1867 movl(dst, as_Address(src));
1868 } else {
1869 lea(dst, src);
1870 movl(dst, Address(dst, 0));
1871 }
1872 }
1873
1874 // C++ bool manipulation
1875
1876 void MacroAssembler::movbool(Register dst, Address src) {
1877 if(sizeof(bool) == 1)
1878 movb(dst, src);
1879 else if(sizeof(bool) == 2)
1880 movw(dst, src);
1881 else if(sizeof(bool) == 4)
1882 movl(dst, src);
1883 else
1884 // unsupported
1885 ShouldNotReachHere();
1886 }
1887
1888 void MacroAssembler::movbool(Address dst, bool boolconst) {
1889 if(sizeof(bool) == 1)
1890 movb(dst, (int) boolconst);
1891 else if(sizeof(bool) == 2)
1892 movw(dst, (int) boolconst);
1893 else if(sizeof(bool) == 4)
1894 movl(dst, (int) boolconst);
1895 else
1896 // unsupported
1897 ShouldNotReachHere();
1898 }
1899
1900 void MacroAssembler::movbool(Address dst, Register src) {
1901 if(sizeof(bool) == 1)
1902 movb(dst, src);
1903 else if(sizeof(bool) == 2)
1904 movw(dst, src);
1905 else if(sizeof(bool) == 4)
1906 movl(dst, src);
1907 else
1908 // unsupported
1909 ShouldNotReachHere();
1910 }
1911
1912 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1913 assert(rscratch != noreg || always_reachable(src), "missing");
1914
1915 if (reachable(src)) {
1916 movdl(dst, as_Address(src));
1917 } else {
1918 lea(rscratch, src);
1919 movdl(dst, Address(rscratch, 0));
1920 }
1921 }
1922
1923 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
1924 assert(rscratch != noreg || always_reachable(src), "missing");
1925
1926 if (reachable(src)) {
1927 movq(dst, as_Address(src));
1928 } else {
1929 lea(rscratch, src);
1930 movq(dst, Address(rscratch, 0));
1931 }
1932 }
1933
1934 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1935 assert(rscratch != noreg || always_reachable(src), "missing");
1936
1937 if (reachable(src)) {
1938 if (UseXmmLoadAndClearUpper) {
1939 movsd (dst, as_Address(src));
1940 } else {
1941 movlpd(dst, as_Address(src));
1942 }
1943 } else {
1944 lea(rscratch, src);
1945 if (UseXmmLoadAndClearUpper) {
1946 movsd (dst, Address(rscratch, 0));
1947 } else {
1948 movlpd(dst, Address(rscratch, 0));
1949 }
1950 }
1951 }
1952
1953 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
1954 assert(rscratch != noreg || always_reachable(src), "missing");
1955
1956 if (reachable(src)) {
1957 movss(dst, as_Address(src));
1958 } else {
1959 lea(rscratch, src);
1960 movss(dst, Address(rscratch, 0));
1961 }
1962 }
1963
1964 void MacroAssembler::movptr(Register dst, Register src) {
1965 movq(dst, src);
1966 }
1967
1968 void MacroAssembler::movptr(Register dst, Address src) {
1969 movq(dst, src);
1970 }
1971
1972 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
1973 void MacroAssembler::movptr(Register dst, intptr_t src) {
1974 if (is_uimm32(src)) {
1975 movl(dst, checked_cast<uint32_t>(src));
1976 } else if (is_simm32(src)) {
1977 movq(dst, checked_cast<int32_t>(src));
1978 } else {
1979 mov64(dst, src);
1980 }
1981 }
1982
1983 void MacroAssembler::movptr(Address dst, Register src) {
1984 movq(dst, src);
1985 }
1986
1987 void MacroAssembler::movptr(Address dst, int32_t src) {
1988 movslq(dst, src);
1989 }
1990
1991 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
1992 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
1993 Assembler::movdqu(dst, src);
1994 }
1995
1996 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
1997 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
1998 Assembler::movdqu(dst, src);
1999 }
2000
2001 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2002 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2003 Assembler::movdqu(dst, src);
2004 }
2005
2006 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2007 assert(rscratch != noreg || always_reachable(src), "missing");
2008
2009 if (reachable(src)) {
2010 movdqu(dst, as_Address(src));
2011 } else {
2012 lea(rscratch, src);
2013 movdqu(dst, Address(rscratch, 0));
2014 }
2015 }
2016
2017 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2018 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2019 Assembler::vmovdqu(dst, src);
2020 }
2021
2022 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2023 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2024 Assembler::vmovdqu(dst, src);
2025 }
2026
2027 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2028 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2029 Assembler::vmovdqu(dst, src);
2030 }
2031
2032 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2033 assert(rscratch != noreg || always_reachable(src), "missing");
2034
2035 if (reachable(src)) {
2036 vmovdqu(dst, as_Address(src));
2037 }
2038 else {
2039 lea(rscratch, src);
2040 vmovdqu(dst, Address(rscratch, 0));
2041 }
2042 }
2043
2044 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2045 assert(rscratch != noreg || always_reachable(src), "missing");
2046
2047 if (vector_len == AVX_512bit) {
2048 evmovdquq(dst, src, AVX_512bit, rscratch);
2049 } else if (vector_len == AVX_256bit) {
2050 vmovdqu(dst, src, rscratch);
2051 } else {
2052 movdqu(dst, src, rscratch);
2053 }
2054 }
2055
2056 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2057 if (vector_len == AVX_512bit) {
2058 evmovdquq(dst, src, AVX_512bit);
2059 } else if (vector_len == AVX_256bit) {
2060 vmovdqu(dst, src);
2061 } else {
2062 movdqu(dst, src);
2063 }
2064 }
2065
2066 void MacroAssembler::vmovdqu(Address dst, XMMRegister src, int vector_len) {
2067 if (vector_len == AVX_512bit) {
2068 evmovdquq(dst, src, AVX_512bit);
2069 } else if (vector_len == AVX_256bit) {
2070 vmovdqu(dst, src);
2071 } else {
2072 movdqu(dst, src);
2073 }
2074 }
2075
2076 void MacroAssembler::vmovdqu(XMMRegister dst, Address src, int vector_len) {
2077 if (vector_len == AVX_512bit) {
2078 evmovdquq(dst, src, AVX_512bit);
2079 } else if (vector_len == AVX_256bit) {
2080 vmovdqu(dst, src);
2081 } else {
2082 movdqu(dst, src);
2083 }
2084 }
2085
2086 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2087 assert(rscratch != noreg || always_reachable(src), "missing");
2088
2089 if (reachable(src)) {
2090 vmovdqa(dst, as_Address(src));
2091 }
2092 else {
2093 lea(rscratch, src);
2094 vmovdqa(dst, Address(rscratch, 0));
2095 }
2096 }
2097
2098 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2099 assert(rscratch != noreg || always_reachable(src), "missing");
2100
2101 if (vector_len == AVX_512bit) {
2102 evmovdqaq(dst, src, AVX_512bit, rscratch);
2103 } else if (vector_len == AVX_256bit) {
2104 vmovdqa(dst, src, rscratch);
2105 } else {
2106 movdqa(dst, src, rscratch);
2107 }
2108 }
2109
2110 void MacroAssembler::kmov(KRegister dst, Address src) {
2111 if (VM_Version::supports_avx512bw()) {
2112 kmovql(dst, src);
2113 } else {
2114 assert(VM_Version::supports_evex(), "");
2115 kmovwl(dst, src);
2116 }
2117 }
2118
2119 void MacroAssembler::kmov(Address dst, KRegister src) {
2120 if (VM_Version::supports_avx512bw()) {
2121 kmovql(dst, src);
2122 } else {
2123 assert(VM_Version::supports_evex(), "");
2124 kmovwl(dst, src);
2125 }
2126 }
2127
2128 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2129 if (VM_Version::supports_avx512bw()) {
2130 kmovql(dst, src);
2131 } else {
2132 assert(VM_Version::supports_evex(), "");
2133 kmovwl(dst, src);
2134 }
2135 }
2136
2137 void MacroAssembler::kmov(Register dst, KRegister src) {
2138 if (VM_Version::supports_avx512bw()) {
2139 kmovql(dst, src);
2140 } else {
2141 assert(VM_Version::supports_evex(), "");
2142 kmovwl(dst, src);
2143 }
2144 }
2145
2146 void MacroAssembler::kmov(KRegister dst, Register src) {
2147 if (VM_Version::supports_avx512bw()) {
2148 kmovql(dst, src);
2149 } else {
2150 assert(VM_Version::supports_evex(), "");
2151 kmovwl(dst, src);
2152 }
2153 }
2154
2155 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2156 assert(rscratch != noreg || always_reachable(src), "missing");
2157
2158 if (reachable(src)) {
2159 kmovql(dst, as_Address(src));
2160 } else {
2161 lea(rscratch, src);
2162 kmovql(dst, Address(rscratch, 0));
2163 }
2164 }
2165
2166 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2167 assert(rscratch != noreg || always_reachable(src), "missing");
2168
2169 if (reachable(src)) {
2170 kmovwl(dst, as_Address(src));
2171 } else {
2172 lea(rscratch, src);
2173 kmovwl(dst, Address(rscratch, 0));
2174 }
2175 }
2176
2177 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2178 int vector_len, Register rscratch) {
2179 assert(rscratch != noreg || always_reachable(src), "missing");
2180
2181 if (reachable(src)) {
2182 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2183 } else {
2184 lea(rscratch, src);
2185 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2186 }
2187 }
2188
2189 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2190 int vector_len, Register rscratch) {
2191 assert(rscratch != noreg || always_reachable(src), "missing");
2192
2193 if (reachable(src)) {
2194 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2195 } else {
2196 lea(rscratch, src);
2197 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2198 }
2199 }
2200
2201 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2202 assert(rscratch != noreg || always_reachable(src), "missing");
2203
2204 if (reachable(src)) {
2205 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2206 } else {
2207 lea(rscratch, src);
2208 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2209 }
2210 }
2211
2212 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2213 assert(rscratch != noreg || always_reachable(src), "missing");
2214
2215 if (reachable(src)) {
2216 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2217 } else {
2218 lea(rscratch, src);
2219 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2220 }
2221 }
2222
2223 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2224 assert(rscratch != noreg || always_reachable(src), "missing");
2225
2226 if (reachable(src)) {
2227 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2228 } else {
2229 lea(rscratch, src);
2230 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2231 }
2232 }
2233
2234 void MacroAssembler::evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2235 assert(rscratch != noreg || always_reachable(src), "missing");
2236
2237 if (reachable(src)) {
2238 Assembler::evmovdqaq(dst, mask, as_Address(src), merge, vector_len);
2239 } else {
2240 lea(rscratch, src);
2241 Assembler::evmovdqaq(dst, mask, Address(rscratch, 0), merge, vector_len);
2242 }
2243 }
2244
2245 void MacroAssembler::evmovdqaq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2246 assert(rscratch != noreg || always_reachable(src), "missing");
2247
2248 if (reachable(src)) {
2249 Assembler::evmovdqaq(dst, as_Address(src), vector_len);
2250 } else {
2251 lea(rscratch, src);
2252 Assembler::evmovdqaq(dst, Address(rscratch, 0), vector_len);
2253 }
2254 }
2255
2256 void MacroAssembler::movapd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2257 assert(rscratch != noreg || always_reachable(src), "missing");
2258
2259 if (reachable(src)) {
2260 Assembler::movapd(dst, as_Address(src));
2261 } else {
2262 lea(rscratch, src);
2263 Assembler::movapd(dst, Address(rscratch, 0));
2264 }
2265 }
2266
2267 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2268 assert(rscratch != noreg || always_reachable(src), "missing");
2269
2270 if (reachable(src)) {
2271 Assembler::movdqa(dst, as_Address(src));
2272 } else {
2273 lea(rscratch, src);
2274 Assembler::movdqa(dst, Address(rscratch, 0));
2275 }
2276 }
2277
2278 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2279 assert(rscratch != noreg || always_reachable(src), "missing");
2280
2281 if (reachable(src)) {
2282 Assembler::movsd(dst, as_Address(src));
2283 } else {
2284 lea(rscratch, src);
2285 Assembler::movsd(dst, Address(rscratch, 0));
2286 }
2287 }
2288
2289 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2290 assert(rscratch != noreg || always_reachable(src), "missing");
2291
2292 if (reachable(src)) {
2293 Assembler::movss(dst, as_Address(src));
2294 } else {
2295 lea(rscratch, src);
2296 Assembler::movss(dst, Address(rscratch, 0));
2297 }
2298 }
2299
2300 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2301 assert(rscratch != noreg || always_reachable(src), "missing");
2302
2303 if (reachable(src)) {
2304 Assembler::movddup(dst, as_Address(src));
2305 } else {
2306 lea(rscratch, src);
2307 Assembler::movddup(dst, Address(rscratch, 0));
2308 }
2309 }
2310
2311 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2312 assert(rscratch != noreg || always_reachable(src), "missing");
2313
2314 if (reachable(src)) {
2315 Assembler::vmovddup(dst, as_Address(src), vector_len);
2316 } else {
2317 lea(rscratch, src);
2318 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2319 }
2320 }
2321
2322 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2323 assert(rscratch != noreg || always_reachable(src), "missing");
2324
2325 if (reachable(src)) {
2326 Assembler::mulsd(dst, as_Address(src));
2327 } else {
2328 lea(rscratch, src);
2329 Assembler::mulsd(dst, Address(rscratch, 0));
2330 }
2331 }
2332
2333 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2334 assert(rscratch != noreg || always_reachable(src), "missing");
2335
2336 if (reachable(src)) {
2337 Assembler::mulss(dst, as_Address(src));
2338 } else {
2339 lea(rscratch, src);
2340 Assembler::mulss(dst, Address(rscratch, 0));
2341 }
2342 }
2343
2344 void MacroAssembler::null_check(Register reg, int offset) {
2345 if (needs_explicit_null_check(offset)) {
2346 // provoke OS null exception if reg is null by
2347 // accessing M[reg] w/o changing any (non-CC) registers
2348 // NOTE: cmpl is plenty here to provoke a segv
2349 cmpptr(rax, Address(reg, 0));
2350 // Note: should probably use testl(rax, Address(reg, 0));
2351 // may be shorter code (however, this version of
2352 // testl needs to be implemented first)
2353 } else {
2354 // nothing to do, (later) access of M[reg + offset]
2355 // will provoke OS null exception if reg is null
2356 }
2357 }
2358
2359 void MacroAssembler::os_breakpoint() {
2360 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2361 // (e.g., MSVC can't call ps() otherwise)
2362 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2363 }
2364
2365 void MacroAssembler::unimplemented(const char* what) {
2366 const char* buf = nullptr;
2367 {
2368 ResourceMark rm;
2369 stringStream ss;
2370 ss.print("unimplemented: %s", what);
2371 buf = code_string(ss.as_string());
2372 }
2373 stop(buf);
2374 }
2375
2376 #define XSTATE_BV 0x200
2377
2378 void MacroAssembler::pop_CPU_state() {
2379 pop_FPU_state();
2380 pop_IU_state();
2381 }
2382
2383 void MacroAssembler::pop_FPU_state() {
2384 fxrstor(Address(rsp, 0));
2385 addptr(rsp, FPUStateSizeInWords * wordSize);
2386 }
2387
2388 void MacroAssembler::pop_IU_state() {
2389 popa();
2390 addq(rsp, 8);
2391 popf();
2392 }
2393
2394 // Save Integer and Float state
2395 // Warning: Stack must be 16 byte aligned (64bit)
2396 void MacroAssembler::push_CPU_state() {
2397 push_IU_state();
2398 push_FPU_state();
2399 }
2400
2401 void MacroAssembler::push_FPU_state() {
2402 subptr(rsp, FPUStateSizeInWords * wordSize);
2403 fxsave(Address(rsp, 0));
2404 }
2405
2406 void MacroAssembler::push_IU_state() {
2407 // Push flags first because pusha kills them
2408 pushf();
2409 // Make sure rsp stays 16-byte aligned
2410 subq(rsp, 8);
2411 pusha();
2412 }
2413
2414 void MacroAssembler::push_cont_fastpath() {
2415 if (!Continuations::enabled()) return;
2416
2417 Label L_done;
2418 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2419 jccb(Assembler::belowEqual, L_done);
2420 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), rsp);
2421 bind(L_done);
2422 }
2423
2424 void MacroAssembler::pop_cont_fastpath() {
2425 if (!Continuations::enabled()) return;
2426
2427 Label L_done;
2428 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2429 jccb(Assembler::below, L_done);
2430 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), 0);
2431 bind(L_done);
2432 }
2433
2434 #ifdef ASSERT
2435 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
2436 Label no_cont;
2437 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
2438 testl(cont, cont);
2439 jcc(Assembler::zero, no_cont);
2440 stop(name);
2441 bind(no_cont);
2442 }
2443 #endif
2444
2445 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { // determine java_thread register
2446 // we must set sp to zero to clear frame
2447 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2448 // must clear fp, so that compiled frames are not confused; it is
2449 // possible that we need it only for debugging
2450 if (clear_fp) {
2451 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2452 }
2453 // Always clear the pc because it could have been set by make_walkable()
2454 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2455 vzeroupper();
2456 }
2457
2458 void MacroAssembler::round_to(Register reg, int modulus) {
2459 addptr(reg, modulus - 1);
2460 andptr(reg, -modulus);
2461 }
2462
2463 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod) {
2464 if (at_return) {
2465 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2466 // we may safely use rsp instead to perform the stack watermark check.
2467 cmpptr(in_nmethod ? rsp : rbp, Address(r15_thread, JavaThread::polling_word_offset()));
2468 jcc(Assembler::above, slow_path);
2469 return;
2470 }
2471 testb(Address(r15_thread, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2472 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2473 }
2474
2475 // Calls to C land
2476 //
2477 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2478 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2479 // has to be reset to 0. This is required to allow proper stack traversal.
2480 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2481 Register last_java_fp,
2482 address last_java_pc,
2483 Register rscratch) {
2484 vzeroupper();
2485 // determine last_java_sp register
2486 if (!last_java_sp->is_valid()) {
2487 last_java_sp = rsp;
2488 }
2489 // last_java_fp is optional
2490 if (last_java_fp->is_valid()) {
2491 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2492 }
2493 // last_java_pc is optional
2494 if (last_java_pc != nullptr) {
2495 Address java_pc(r15_thread,
2496 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
2497 lea(java_pc, InternalAddress(last_java_pc), rscratch);
2498 }
2499 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2500 }
2501
2502 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2503 Register last_java_fp,
2504 Label &L,
2505 Register scratch) {
2506 lea(scratch, L);
2507 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
2508 set_last_Java_frame(last_java_sp, last_java_fp, nullptr, scratch);
2509 }
2510
2511 void MacroAssembler::shlptr(Register dst, int imm8) {
2512 shlq(dst, imm8);
2513 }
2514
2515 void MacroAssembler::shrptr(Register dst, int imm8) {
2516 shrq(dst, imm8);
2517 }
2518
2519 void MacroAssembler::sign_extend_byte(Register reg) {
2520 movsbl(reg, reg); // movsxb
2521 }
2522
2523 void MacroAssembler::sign_extend_short(Register reg) {
2524 movswl(reg, reg); // movsxw
2525 }
2526
2527 void MacroAssembler::testl(Address dst, int32_t imm32) {
2528 if (imm32 >= 0 && is8bit(imm32)) {
2529 testb(dst, imm32);
2530 } else {
2531 Assembler::testl(dst, imm32);
2532 }
2533 }
2534
2535 void MacroAssembler::testl(Register dst, int32_t imm32) {
2536 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
2537 testb(dst, imm32);
2538 } else {
2539 Assembler::testl(dst, imm32);
2540 }
2541 }
2542
2543 void MacroAssembler::testl(Register dst, AddressLiteral src) {
2544 assert(always_reachable(src), "Address should be reachable");
2545 testl(dst, as_Address(src));
2546 }
2547
2548 void MacroAssembler::testq(Address dst, int32_t imm32) {
2549 if (imm32 >= 0) {
2550 testl(dst, imm32);
2551 } else {
2552 Assembler::testq(dst, imm32);
2553 }
2554 }
2555
2556 void MacroAssembler::testq(Register dst, int32_t imm32) {
2557 if (imm32 >= 0) {
2558 testl(dst, imm32);
2559 } else {
2560 Assembler::testq(dst, imm32);
2561 }
2562 }
2563
2564 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
2565 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2566 Assembler::pcmpeqb(dst, src);
2567 }
2568
2569 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
2570 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2571 Assembler::pcmpeqw(dst, src);
2572 }
2573
2574 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2575 assert((dst->encoding() < 16),"XMM register should be 0-15");
2576 Assembler::pcmpestri(dst, src, imm8);
2577 }
2578
2579 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2580 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2581 Assembler::pcmpestri(dst, src, imm8);
2582 }
2583
2584 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2585 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2586 Assembler::pmovzxbw(dst, src);
2587 }
2588
2589 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
2590 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2591 Assembler::pmovzxbw(dst, src);
2592 }
2593
2594 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
2595 assert((src->encoding() < 16),"XMM register should be 0-15");
2596 Assembler::pmovmskb(dst, src);
2597 }
2598
2599 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
2600 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2601 Assembler::ptest(dst, src);
2602 }
2603
2604 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2605 assert(rscratch != noreg || always_reachable(src), "missing");
2606
2607 if (reachable(src)) {
2608 Assembler::sqrtss(dst, as_Address(src));
2609 } else {
2610 lea(rscratch, src);
2611 Assembler::sqrtss(dst, Address(rscratch, 0));
2612 }
2613 }
2614
2615 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2616 assert(rscratch != noreg || always_reachable(src), "missing");
2617
2618 if (reachable(src)) {
2619 Assembler::subsd(dst, as_Address(src));
2620 } else {
2621 lea(rscratch, src);
2622 Assembler::subsd(dst, Address(rscratch, 0));
2623 }
2624 }
2625
2626 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
2627 assert(rscratch != noreg || always_reachable(src), "missing");
2628
2629 if (reachable(src)) {
2630 Assembler::roundsd(dst, as_Address(src), rmode);
2631 } else {
2632 lea(rscratch, src);
2633 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
2634 }
2635 }
2636
2637 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2638 assert(rscratch != noreg || always_reachable(src), "missing");
2639
2640 if (reachable(src)) {
2641 Assembler::subss(dst, as_Address(src));
2642 } else {
2643 lea(rscratch, src);
2644 Assembler::subss(dst, Address(rscratch, 0));
2645 }
2646 }
2647
2648 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2649 assert(rscratch != noreg || always_reachable(src), "missing");
2650
2651 if (reachable(src)) {
2652 Assembler::ucomisd(dst, as_Address(src));
2653 } else {
2654 lea(rscratch, src);
2655 Assembler::ucomisd(dst, Address(rscratch, 0));
2656 }
2657 }
2658
2659 void MacroAssembler::vucomxsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2660 assert(rscratch != noreg || always_reachable(src), "missing");
2661
2662 if (reachable(src)) {
2663 Assembler::vucomxsd(dst, as_Address(src));
2664 } else {
2665 lea(rscratch, src);
2666 Assembler::vucomxsd(dst, Address(rscratch, 0));
2667 }
2668 }
2669
2670 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2671 assert(rscratch != noreg || always_reachable(src), "missing");
2672
2673 if (reachable(src)) {
2674 Assembler::ucomiss(dst, as_Address(src));
2675 } else {
2676 lea(rscratch, src);
2677 Assembler::ucomiss(dst, Address(rscratch, 0));
2678 }
2679 }
2680
2681 void MacroAssembler::vucomxss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2682 assert(rscratch != noreg || always_reachable(src), "missing");
2683
2684 if (reachable(src)) {
2685 Assembler::vucomxss(dst, as_Address(src));
2686 } else {
2687 lea(rscratch, src);
2688 Assembler::vucomxss(dst, Address(rscratch, 0));
2689 }
2690 }
2691
2692 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2693 assert(rscratch != noreg || always_reachable(src), "missing");
2694
2695 // Used in sign-bit flipping with aligned address.
2696 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2697
2698 if (UseAVX > 2 &&
2699 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2700 (dst->encoding() >= 16)) {
2701 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2702 } else if (reachable(src)) {
2703 Assembler::xorpd(dst, as_Address(src));
2704 } else {
2705 lea(rscratch, src);
2706 Assembler::xorpd(dst, Address(rscratch, 0));
2707 }
2708 }
2709
2710 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
2711 if (UseAVX > 2 &&
2712 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2713 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2714 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2715 } else {
2716 Assembler::xorpd(dst, src);
2717 }
2718 }
2719
2720 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
2721 if (UseAVX > 2 &&
2722 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2723 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2724 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2725 } else {
2726 Assembler::xorps(dst, src);
2727 }
2728 }
2729
2730 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
2731 assert(rscratch != noreg || always_reachable(src), "missing");
2732
2733 // Used in sign-bit flipping with aligned address.
2734 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2735
2736 if (UseAVX > 2 &&
2737 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2738 (dst->encoding() >= 16)) {
2739 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2740 } else if (reachable(src)) {
2741 Assembler::xorps(dst, as_Address(src));
2742 } else {
2743 lea(rscratch, src);
2744 Assembler::xorps(dst, Address(rscratch, 0));
2745 }
2746 }
2747
2748 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
2749 assert(rscratch != noreg || always_reachable(src), "missing");
2750
2751 // Used in sign-bit flipping with aligned address.
2752 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
2753 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
2754 if (reachable(src)) {
2755 Assembler::pshufb(dst, as_Address(src));
2756 } else {
2757 lea(rscratch, src);
2758 Assembler::pshufb(dst, Address(rscratch, 0));
2759 }
2760 }
2761
2762 // AVX 3-operands instructions
2763
2764 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2765 assert(rscratch != noreg || always_reachable(src), "missing");
2766
2767 if (reachable(src)) {
2768 vaddsd(dst, nds, as_Address(src));
2769 } else {
2770 lea(rscratch, src);
2771 vaddsd(dst, nds, Address(rscratch, 0));
2772 }
2773 }
2774
2775 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2776 assert(rscratch != noreg || always_reachable(src), "missing");
2777
2778 if (reachable(src)) {
2779 vaddss(dst, nds, as_Address(src));
2780 } else {
2781 lea(rscratch, src);
2782 vaddss(dst, nds, Address(rscratch, 0));
2783 }
2784 }
2785
2786 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2787 assert(UseAVX > 0, "requires some form of AVX");
2788 assert(rscratch != noreg || always_reachable(src), "missing");
2789
2790 if (reachable(src)) {
2791 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
2792 } else {
2793 lea(rscratch, src);
2794 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
2795 }
2796 }
2797
2798 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2799 assert(UseAVX > 0, "requires some form of AVX");
2800 assert(rscratch != noreg || always_reachable(src), "missing");
2801
2802 if (reachable(src)) {
2803 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
2804 } else {
2805 lea(rscratch, src);
2806 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
2807 }
2808 }
2809
2810 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2811 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2812 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2813
2814 vandps(dst, nds, negate_field, vector_len, rscratch);
2815 }
2816
2817 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2818 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2819 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2820
2821 vandpd(dst, nds, negate_field, vector_len, rscratch);
2822 }
2823
2824 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2825 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2826 Assembler::vpaddb(dst, nds, src, vector_len);
2827 }
2828
2829 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2830 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2831 Assembler::vpaddb(dst, nds, src, vector_len);
2832 }
2833
2834 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2835 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2836 Assembler::vpaddw(dst, nds, src, vector_len);
2837 }
2838
2839 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2840 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2841 Assembler::vpaddw(dst, nds, src, vector_len);
2842 }
2843
2844 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2845 assert(rscratch != noreg || always_reachable(src), "missing");
2846
2847 if (reachable(src)) {
2848 Assembler::vpand(dst, nds, as_Address(src), vector_len);
2849 } else {
2850 lea(rscratch, src);
2851 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
2852 }
2853 }
2854
2855 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2856 assert(rscratch != noreg || always_reachable(src), "missing");
2857
2858 if (reachable(src)) {
2859 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
2860 } else {
2861 lea(rscratch, src);
2862 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
2863 }
2864 }
2865
2866 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2867 assert(rscratch != noreg || always_reachable(src), "missing");
2868
2869 if (reachable(src)) {
2870 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
2871 } else {
2872 lea(rscratch, src);
2873 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
2874 }
2875 }
2876
2877 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2878 assert(rscratch != noreg || always_reachable(src), "missing");
2879
2880 if (reachable(src)) {
2881 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
2882 } else {
2883 lea(rscratch, src);
2884 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
2885 }
2886 }
2887
2888 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2889 assert(rscratch != noreg || always_reachable(src), "missing");
2890
2891 if (reachable(src)) {
2892 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
2893 } else {
2894 lea(rscratch, src);
2895 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
2896 }
2897 }
2898
2899 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2900 assert(rscratch != noreg || always_reachable(src), "missing");
2901
2902 if (reachable(src)) {
2903 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
2904 } else {
2905 lea(rscratch, src);
2906 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
2907 }
2908 }
2909
2910 // Vector float blend
2911 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
2912 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
2913 // WARN: Allow dst == (src1|src2), mask == scratch
2914 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
2915 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
2916 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
2917 bool dst_available = dst != mask && (dst != src1 || dst != src2);
2918 if (blend_emulation && scratch_available && dst_available) {
2919 if (compute_mask) {
2920 vpsrad(scratch, mask, 32, vector_len);
2921 mask = scratch;
2922 }
2923 if (dst == src1) {
2924 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
2925 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
2926 } else {
2927 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
2928 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
2929 }
2930 vpor(dst, dst, scratch, vector_len);
2931 } else {
2932 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
2933 }
2934 }
2935
2936 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
2937 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
2938 // WARN: Allow dst == (src1|src2), mask == scratch
2939 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
2940 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
2941 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
2942 bool dst_available = dst != mask && (dst != src1 || dst != src2);
2943 if (blend_emulation && scratch_available && dst_available) {
2944 if (compute_mask) {
2945 vpxor(scratch, scratch, scratch, vector_len);
2946 vpcmpgtq(scratch, scratch, mask, vector_len);
2947 mask = scratch;
2948 }
2949 if (dst == src1) {
2950 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
2951 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
2952 } else {
2953 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
2954 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
2955 }
2956 vpor(dst, dst, scratch, vector_len);
2957 } else {
2958 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
2959 }
2960 }
2961
2962 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2963 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2964 Assembler::vpcmpeqb(dst, nds, src, vector_len);
2965 }
2966
2967 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
2968 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2969 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
2970 }
2971
2972 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2973 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2974 Assembler::vpcmpeqw(dst, nds, src, vector_len);
2975 }
2976
2977 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2978 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2979 Assembler::vpcmpeqw(dst, nds, src, vector_len);
2980 }
2981
2982 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2983 assert(rscratch != noreg || always_reachable(src), "missing");
2984
2985 if (reachable(src)) {
2986 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
2987 } else {
2988 lea(rscratch, src);
2989 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
2990 }
2991 }
2992
2993 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
2994 int comparison, bool is_signed, int vector_len, Register rscratch) {
2995 assert(rscratch != noreg || always_reachable(src), "missing");
2996
2997 if (reachable(src)) {
2998 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
2999 } else {
3000 lea(rscratch, src);
3001 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3002 }
3003 }
3004
3005 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3006 int comparison, bool is_signed, int vector_len, Register rscratch) {
3007 assert(rscratch != noreg || always_reachable(src), "missing");
3008
3009 if (reachable(src)) {
3010 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3011 } else {
3012 lea(rscratch, src);
3013 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3014 }
3015 }
3016
3017 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3018 int comparison, bool is_signed, int vector_len, Register rscratch) {
3019 assert(rscratch != noreg || always_reachable(src), "missing");
3020
3021 if (reachable(src)) {
3022 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3023 } else {
3024 lea(rscratch, src);
3025 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3026 }
3027 }
3028
3029 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3030 int comparison, bool is_signed, int vector_len, Register rscratch) {
3031 assert(rscratch != noreg || always_reachable(src), "missing");
3032
3033 if (reachable(src)) {
3034 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3035 } else {
3036 lea(rscratch, src);
3037 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3038 }
3039 }
3040
3041 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3042 if (width == Assembler::Q) {
3043 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3044 } else {
3045 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3046 }
3047 }
3048
3049 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3050 int eq_cond_enc = 0x29;
3051 int gt_cond_enc = 0x37;
3052 if (width != Assembler::Q) {
3053 eq_cond_enc = 0x74 + width;
3054 gt_cond_enc = 0x64 + width;
3055 }
3056 switch (cond) {
3057 case eq:
3058 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3059 break;
3060 case neq:
3061 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3062 vallones(xtmp, vector_len);
3063 vpxor(dst, xtmp, dst, vector_len);
3064 break;
3065 case le:
3066 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3067 vallones(xtmp, vector_len);
3068 vpxor(dst, xtmp, dst, vector_len);
3069 break;
3070 case nlt:
3071 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3072 vallones(xtmp, vector_len);
3073 vpxor(dst, xtmp, dst, vector_len);
3074 break;
3075 case lt:
3076 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3077 break;
3078 case nle:
3079 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3080 break;
3081 default:
3082 assert(false, "Should not reach here");
3083 }
3084 }
3085
3086 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3087 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3088 Assembler::vpmovzxbw(dst, src, vector_len);
3089 }
3090
3091 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3092 assert((src->encoding() < 16),"XMM register should be 0-15");
3093 Assembler::vpmovmskb(dst, src, vector_len);
3094 }
3095
3096 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3097 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3098 Assembler::vpmullw(dst, nds, src, vector_len);
3099 }
3100
3101 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3102 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3103 Assembler::vpmullw(dst, nds, src, vector_len);
3104 }
3105
3106 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3107 assert((UseAVX > 0), "AVX support is needed");
3108 assert(rscratch != noreg || always_reachable(src), "missing");
3109
3110 if (reachable(src)) {
3111 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3112 } else {
3113 lea(rscratch, src);
3114 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3115 }
3116 }
3117
3118 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3119 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3120 Assembler::vpsubb(dst, nds, src, vector_len);
3121 }
3122
3123 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3124 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3125 Assembler::vpsubb(dst, nds, src, vector_len);
3126 }
3127
3128 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3129 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3130 Assembler::vpsubw(dst, nds, src, vector_len);
3131 }
3132
3133 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3134 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3135 Assembler::vpsubw(dst, nds, src, vector_len);
3136 }
3137
3138 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3139 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3140 Assembler::vpsraw(dst, nds, shift, vector_len);
3141 }
3142
3143 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3144 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3145 Assembler::vpsraw(dst, nds, shift, vector_len);
3146 }
3147
3148 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3149 assert(UseAVX > 2,"");
3150 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3151 vector_len = 2;
3152 }
3153 Assembler::evpsraq(dst, nds, shift, vector_len);
3154 }
3155
3156 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3157 assert(UseAVX > 2,"");
3158 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3159 vector_len = 2;
3160 }
3161 Assembler::evpsraq(dst, nds, shift, vector_len);
3162 }
3163
3164 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3165 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3166 Assembler::vpsrlw(dst, nds, shift, vector_len);
3167 }
3168
3169 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3170 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3171 Assembler::vpsrlw(dst, nds, shift, vector_len);
3172 }
3173
3174 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3175 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3176 Assembler::vpsllw(dst, nds, shift, vector_len);
3177 }
3178
3179 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3180 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3181 Assembler::vpsllw(dst, nds, shift, vector_len);
3182 }
3183
3184 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3185 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3186 Assembler::vptest(dst, src);
3187 }
3188
3189 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3190 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3191 Assembler::punpcklbw(dst, src);
3192 }
3193
3194 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3195 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3196 Assembler::pshufd(dst, src, mode);
3197 }
3198
3199 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3200 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3201 Assembler::pshuflw(dst, src, mode);
3202 }
3203
3204 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3205 assert(rscratch != noreg || always_reachable(src), "missing");
3206
3207 if (reachable(src)) {
3208 vandpd(dst, nds, as_Address(src), vector_len);
3209 } else {
3210 lea(rscratch, src);
3211 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3212 }
3213 }
3214
3215 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3216 assert(rscratch != noreg || always_reachable(src), "missing");
3217
3218 if (reachable(src)) {
3219 vandps(dst, nds, as_Address(src), vector_len);
3220 } else {
3221 lea(rscratch, src);
3222 vandps(dst, nds, Address(rscratch, 0), vector_len);
3223 }
3224 }
3225
3226 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3227 bool merge, int vector_len, Register rscratch) {
3228 assert(rscratch != noreg || always_reachable(src), "missing");
3229
3230 if (reachable(src)) {
3231 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3232 } else {
3233 lea(rscratch, src);
3234 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3235 }
3236 }
3237
3238 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3239 assert(rscratch != noreg || always_reachable(src), "missing");
3240
3241 if (reachable(src)) {
3242 vdivsd(dst, nds, as_Address(src));
3243 } else {
3244 lea(rscratch, src);
3245 vdivsd(dst, nds, Address(rscratch, 0));
3246 }
3247 }
3248
3249 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3250 assert(rscratch != noreg || always_reachable(src), "missing");
3251
3252 if (reachable(src)) {
3253 vdivss(dst, nds, as_Address(src));
3254 } else {
3255 lea(rscratch, src);
3256 vdivss(dst, nds, Address(rscratch, 0));
3257 }
3258 }
3259
3260 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3261 assert(rscratch != noreg || always_reachable(src), "missing");
3262
3263 if (reachable(src)) {
3264 vmulsd(dst, nds, as_Address(src));
3265 } else {
3266 lea(rscratch, src);
3267 vmulsd(dst, nds, Address(rscratch, 0));
3268 }
3269 }
3270
3271 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3272 assert(rscratch != noreg || always_reachable(src), "missing");
3273
3274 if (reachable(src)) {
3275 vmulss(dst, nds, as_Address(src));
3276 } else {
3277 lea(rscratch, src);
3278 vmulss(dst, nds, Address(rscratch, 0));
3279 }
3280 }
3281
3282 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3283 assert(rscratch != noreg || always_reachable(src), "missing");
3284
3285 if (reachable(src)) {
3286 vsubsd(dst, nds, as_Address(src));
3287 } else {
3288 lea(rscratch, src);
3289 vsubsd(dst, nds, Address(rscratch, 0));
3290 }
3291 }
3292
3293 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3294 assert(rscratch != noreg || always_reachable(src), "missing");
3295
3296 if (reachable(src)) {
3297 vsubss(dst, nds, as_Address(src));
3298 } else {
3299 lea(rscratch, src);
3300 vsubss(dst, nds, Address(rscratch, 0));
3301 }
3302 }
3303
3304 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3305 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3306 assert(rscratch != noreg || always_reachable(src), "missing");
3307
3308 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3309 }
3310
3311 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3312 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3313 assert(rscratch != noreg || always_reachable(src), "missing");
3314
3315 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3316 }
3317
3318 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3319 assert(rscratch != noreg || always_reachable(src), "missing");
3320
3321 if (reachable(src)) {
3322 vxorpd(dst, nds, as_Address(src), vector_len);
3323 } else {
3324 lea(rscratch, src);
3325 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3326 }
3327 }
3328
3329 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3330 assert(rscratch != noreg || always_reachable(src), "missing");
3331
3332 if (reachable(src)) {
3333 vxorps(dst, nds, as_Address(src), vector_len);
3334 } else {
3335 lea(rscratch, src);
3336 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3337 }
3338 }
3339
3340 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3341 assert(rscratch != noreg || always_reachable(src), "missing");
3342
3343 if (UseAVX > 1 || (vector_len < 1)) {
3344 if (reachable(src)) {
3345 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3346 } else {
3347 lea(rscratch, src);
3348 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3349 }
3350 } else {
3351 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3352 }
3353 }
3354
3355 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3356 assert(rscratch != noreg || always_reachable(src), "missing");
3357
3358 if (reachable(src)) {
3359 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3360 } else {
3361 lea(rscratch, src);
3362 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3363 }
3364 }
3365
3366 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3367 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3368 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3369 // The inverted mask is sign-extended
3370 andptr(possibly_non_local, inverted_mask);
3371 }
3372
3373 void MacroAssembler::resolve_jobject(Register value,
3374 Register tmp) {
3375 Register thread = r15_thread;
3376 assert_different_registers(value, thread, tmp);
3377 Label done, tagged, weak_tagged;
3378 testptr(value, value);
3379 jcc(Assembler::zero, done); // Use null as-is.
3380 testptr(value, JNIHandles::tag_mask); // Test for tag.
3381 jcc(Assembler::notZero, tagged);
3382
3383 // Resolve local handle
3384 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp);
3385 verify_oop(value);
3386 jmp(done);
3387
3388 bind(tagged);
3389 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
3390 jcc(Assembler::notZero, weak_tagged);
3391
3392 // Resolve global handle
3393 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3394 verify_oop(value);
3395 jmp(done);
3396
3397 bind(weak_tagged);
3398 // Resolve jweak.
3399 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3400 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp);
3401 verify_oop(value);
3402
3403 bind(done);
3404 }
3405
3406 void MacroAssembler::resolve_global_jobject(Register value,
3407 Register tmp) {
3408 Register thread = r15_thread;
3409 assert_different_registers(value, thread, tmp);
3410 Label done;
3411
3412 testptr(value, value);
3413 jcc(Assembler::zero, done); // Use null as-is.
3414
3415 #ifdef ASSERT
3416 {
3417 Label valid_global_tag;
3418 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
3419 jcc(Assembler::notZero, valid_global_tag);
3420 stop("non global jobject using resolve_global_jobject");
3421 bind(valid_global_tag);
3422 }
3423 #endif
3424
3425 // Resolve global handle
3426 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3427 verify_oop(value);
3428
3429 bind(done);
3430 }
3431
3432 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3433 subq(dst, imm32);
3434 }
3435
3436 // Force generation of a 4 byte immediate value even if it fits into 8bit
3437 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3438 subq_imm32(dst, imm32);
3439 }
3440
3441 void MacroAssembler::subptr(Register dst, Register src) {
3442 subq(dst, src);
3443 }
3444
3445 // C++ bool manipulation
3446 void MacroAssembler::testbool(Register dst) {
3447 if(sizeof(bool) == 1)
3448 testb(dst, 0xff);
3449 else if(sizeof(bool) == 2) {
3450 // testw implementation needed for two byte bools
3451 ShouldNotReachHere();
3452 } else if(sizeof(bool) == 4)
3453 testl(dst, dst);
3454 else
3455 // unsupported
3456 ShouldNotReachHere();
3457 }
3458
3459 void MacroAssembler::testptr(Register dst, Register src) {
3460 testq(dst, src);
3461 }
3462
3463 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3464 void MacroAssembler::tlab_allocate(Register obj,
3465 Register var_size_in_bytes,
3466 int con_size_in_bytes,
3467 Register t1,
3468 Register t2,
3469 Label& slow_case) {
3470 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3471 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3472 }
3473
3474 RegSet MacroAssembler::call_clobbered_gp_registers() {
3475 RegSet regs;
3476 regs += RegSet::of(rax, rcx, rdx);
3477 #ifndef _WINDOWS
3478 regs += RegSet::of(rsi, rdi);
3479 #endif
3480 regs += RegSet::range(r8, r11);
3481 if (UseAPX) {
3482 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
3483 }
3484 return regs;
3485 }
3486
3487 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
3488 int num_xmm_registers = XMMRegister::available_xmm_registers();
3489 #if defined(_WINDOWS)
3490 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
3491 if (num_xmm_registers > 16) {
3492 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
3493 }
3494 return result;
3495 #else
3496 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
3497 #endif
3498 }
3499
3500 // C1 only ever uses the first double/float of the XMM register.
3501 static int xmm_save_size() { return sizeof(double); }
3502
3503 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3504 masm->movdbl(Address(rsp, offset), reg);
3505 }
3506
3507 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3508 masm->movdbl(reg, Address(rsp, offset));
3509 }
3510
3511 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
3512 bool save_fpu, int& gp_area_size, int& xmm_area_size) {
3513
3514 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
3515 StackAlignmentInBytes);
3516 xmm_area_size = save_fpu ? xmm_registers.size() * xmm_save_size() : 0;
3517
3518 return gp_area_size + xmm_area_size;
3519 }
3520
3521 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
3522 block_comment("push_call_clobbered_registers start");
3523 // Regular registers
3524 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
3525
3526 int gp_area_size;
3527 int xmm_area_size;
3528 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
3529 gp_area_size, xmm_area_size);
3530 subptr(rsp, total_save_size);
3531
3532 push_set(gp_registers_to_push, 0);
3533
3534 if (save_fpu) {
3535 push_set(call_clobbered_xmm_registers(), gp_area_size);
3536 }
3537
3538 block_comment("push_call_clobbered_registers end");
3539 }
3540
3541 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
3542 block_comment("pop_call_clobbered_registers start");
3543
3544 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
3545
3546 int gp_area_size;
3547 int xmm_area_size;
3548 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
3549 gp_area_size, xmm_area_size);
3550
3551 if (restore_fpu) {
3552 pop_set(call_clobbered_xmm_registers(), gp_area_size);
3553 }
3554
3555 pop_set(gp_registers_to_pop, 0);
3556
3557 addptr(rsp, total_save_size);
3558
3559 vzeroupper();
3560
3561 block_comment("pop_call_clobbered_registers end");
3562 }
3563
3564 void MacroAssembler::push_set(XMMRegSet set, int offset) {
3565 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
3566 int spill_offset = offset;
3567
3568 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
3569 save_xmm_register(this, spill_offset, *it);
3570 spill_offset += xmm_save_size();
3571 }
3572 }
3573
3574 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
3575 int restore_size = set.size() * xmm_save_size();
3576 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
3577
3578 int restore_offset = offset + restore_size - xmm_save_size();
3579
3580 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
3581 restore_xmm_register(this, restore_offset, *it);
3582 restore_offset -= xmm_save_size();
3583 }
3584 }
3585
3586 void MacroAssembler::push_set(RegSet set, int offset) {
3587 int spill_offset;
3588 if (offset == -1) {
3589 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3590 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
3591 subptr(rsp, aligned_size);
3592 spill_offset = 0;
3593 } else {
3594 spill_offset = offset;
3595 }
3596
3597 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
3598 movptr(Address(rsp, spill_offset), *it);
3599 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3600 }
3601 }
3602
3603 void MacroAssembler::pop_set(RegSet set, int offset) {
3604
3605 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3606 int restore_size = set.size() * gp_reg_size;
3607 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
3608
3609 int restore_offset;
3610 if (offset == -1) {
3611 restore_offset = restore_size - gp_reg_size;
3612 } else {
3613 restore_offset = offset + restore_size - gp_reg_size;
3614 }
3615 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
3616 movptr(*it, Address(rsp, restore_offset));
3617 restore_offset -= gp_reg_size;
3618 }
3619
3620 if (offset == -1) {
3621 addptr(rsp, aligned_size);
3622 }
3623 }
3624
3625 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3626 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3627 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3628 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3629 Label done;
3630
3631 testptr(length_in_bytes, length_in_bytes);
3632 jcc(Assembler::zero, done);
3633
3634 // initialize topmost word, divide index by 2, check if odd and test if zero
3635 // note: for the remaining code to work, index must be a multiple of BytesPerWord
3636 #ifdef ASSERT
3637 {
3638 Label L;
3639 testptr(length_in_bytes, BytesPerWord - 1);
3640 jcc(Assembler::zero, L);
3641 stop("length must be a multiple of BytesPerWord");
3642 bind(L);
3643 }
3644 #endif
3645 Register index = length_in_bytes;
3646 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
3647 if (UseIncDec) {
3648 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
3649 } else {
3650 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
3651 shrptr(index, 1);
3652 }
3653
3654 // initialize remaining object fields: index is a multiple of 2 now
3655 {
3656 Label loop;
3657 bind(loop);
3658 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3659 decrement(index);
3660 jcc(Assembler::notZero, loop);
3661 }
3662
3663 bind(done);
3664 }
3665
3666 // Look up the method for a megamorphic invokeinterface call.
3667 // The target method is determined by <intf_klass, itable_index>.
3668 // The receiver klass is in recv_klass.
3669 // On success, the result will be in method_result, and execution falls through.
3670 // On failure, execution transfers to the given label.
3671 void MacroAssembler::lookup_interface_method(Register recv_klass,
3672 Register intf_klass,
3673 RegisterOrConstant itable_index,
3674 Register method_result,
3675 Register scan_temp,
3676 Label& L_no_such_interface,
3677 bool return_method) {
3678 assert_different_registers(recv_klass, intf_klass, scan_temp);
3679 assert_different_registers(method_result, intf_klass, scan_temp);
3680 assert(recv_klass != method_result || !return_method,
3681 "recv_klass can be destroyed when method isn't needed");
3682
3683 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3684 "caller must use same register for non-constant itable index as for method");
3685
3686 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3687 int vtable_base = in_bytes(Klass::vtable_start_offset());
3688 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3689 int scan_step = itableOffsetEntry::size() * wordSize;
3690 int vte_size = vtableEntry::size_in_bytes();
3691 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3692 assert(vte_size == wordSize, "else adjust times_vte_scale");
3693
3694 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3695
3696 // Could store the aligned, prescaled offset in the klass.
3697 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3698
3699 if (return_method) {
3700 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3701 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3702 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3703 }
3704
3705 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
3706 // if (scan->interface() == intf) {
3707 // result = (klass + scan->offset() + itable_index);
3708 // }
3709 // }
3710 Label search, found_method;
3711
3712 for (int peel = 1; peel >= 0; peel--) {
3713 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
3714 cmpptr(intf_klass, method_result);
3715
3716 if (peel) {
3717 jccb(Assembler::equal, found_method);
3718 } else {
3719 jccb(Assembler::notEqual, search);
3720 // (invert the test to fall through to found_method...)
3721 }
3722
3723 if (!peel) break;
3724
3725 bind(search);
3726
3727 // Check that the previous entry is non-null. A null entry means that
3728 // the receiver class doesn't implement the interface, and wasn't the
3729 // same as when the caller was compiled.
3730 testptr(method_result, method_result);
3731 jcc(Assembler::zero, L_no_such_interface);
3732 addptr(scan_temp, scan_step);
3733 }
3734
3735 bind(found_method);
3736
3737 if (return_method) {
3738 // Got a hit.
3739 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
3740 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
3741 }
3742 }
3743
3744 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
3745 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
3746 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
3747 // The target method is determined by <holder_klass, itable_index>.
3748 // The receiver klass is in recv_klass.
3749 // On success, the result will be in method_result, and execution falls through.
3750 // On failure, execution transfers to the given label.
3751 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
3752 Register holder_klass,
3753 Register resolved_klass,
3754 Register method_result,
3755 Register scan_temp,
3756 Register temp_reg2,
3757 Register receiver,
3758 int itable_index,
3759 Label& L_no_such_interface) {
3760 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
3761 Register temp_itbl_klass = method_result;
3762 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
3763
3764 int vtable_base = in_bytes(Klass::vtable_start_offset());
3765 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3766 int scan_step = itableOffsetEntry::size() * wordSize;
3767 int vte_size = vtableEntry::size_in_bytes();
3768 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
3769 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
3770 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3771 assert(vte_size == wordSize, "adjust times_vte_scale");
3772
3773 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
3774
3775 // temp_itbl_klass = recv_klass.itable[0]
3776 // scan_temp = &recv_klass.itable[0] + step
3777 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3778 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
3779 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
3780 xorptr(temp_reg, temp_reg);
3781
3782 // Initial checks:
3783 // - if (holder_klass != resolved_klass), go to "scan for resolved"
3784 // - if (itable[0] == 0), no such interface
3785 // - if (itable[0] == holder_klass), shortcut to "holder found"
3786 cmpptr(holder_klass, resolved_klass);
3787 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
3788 testptr(temp_itbl_klass, temp_itbl_klass);
3789 jccb(Assembler::zero, L_no_such_interface);
3790 cmpptr(holder_klass, temp_itbl_klass);
3791 jccb(Assembler::equal, L_holder_found);
3792
3793 // Loop: Look for holder_klass record in itable
3794 // do {
3795 // tmp = itable[index];
3796 // index += step;
3797 // if (tmp == holder_klass) {
3798 // goto L_holder_found; // Found!
3799 // }
3800 // } while (tmp != 0);
3801 // goto L_no_such_interface // Not found.
3802 Label L_scan_holder;
3803 bind(L_scan_holder);
3804 movptr(temp_itbl_klass, Address(scan_temp, 0));
3805 addptr(scan_temp, scan_step);
3806 cmpptr(holder_klass, temp_itbl_klass);
3807 jccb(Assembler::equal, L_holder_found);
3808 testptr(temp_itbl_klass, temp_itbl_klass);
3809 jccb(Assembler::notZero, L_scan_holder);
3810
3811 jmpb(L_no_such_interface);
3812
3813 // Loop: Look for resolved_class record in itable
3814 // do {
3815 // tmp = itable[index];
3816 // index += step;
3817 // if (tmp == holder_klass) {
3818 // // Also check if we have met a holder klass
3819 // holder_tmp = itable[index-step-ioffset];
3820 // }
3821 // if (tmp == resolved_klass) {
3822 // goto L_resolved_found; // Found!
3823 // }
3824 // } while (tmp != 0);
3825 // goto L_no_such_interface // Not found.
3826 //
3827 Label L_loop_scan_resolved;
3828 bind(L_loop_scan_resolved);
3829 movptr(temp_itbl_klass, Address(scan_temp, 0));
3830 addptr(scan_temp, scan_step);
3831 bind(L_loop_scan_resolved_entry);
3832 cmpptr(holder_klass, temp_itbl_klass);
3833 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
3834 cmpptr(resolved_klass, temp_itbl_klass);
3835 jccb(Assembler::equal, L_resolved_found);
3836 testptr(temp_itbl_klass, temp_itbl_klass);
3837 jccb(Assembler::notZero, L_loop_scan_resolved);
3838
3839 jmpb(L_no_such_interface);
3840
3841 Label L_ready;
3842
3843 // See if we already have a holder klass. If not, go and scan for it.
3844 bind(L_resolved_found);
3845 testptr(temp_reg, temp_reg);
3846 jccb(Assembler::zero, L_scan_holder);
3847 jmpb(L_ready);
3848
3849 bind(L_holder_found);
3850 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
3851
3852 // Finally, temp_reg contains holder_klass vtable offset
3853 bind(L_ready);
3854 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3855 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
3856 load_klass(scan_temp, receiver, noreg);
3857 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
3858 } else {
3859 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
3860 }
3861 }
3862
3863
3864 // virtual method calling
3865 void MacroAssembler::lookup_virtual_method(Register recv_klass,
3866 RegisterOrConstant vtable_index,
3867 Register method_result) {
3868 const ByteSize base = Klass::vtable_start_offset();
3869 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
3870 Address vtable_entry_addr(recv_klass,
3871 vtable_index, Address::times_ptr,
3872 base + vtableEntry::method_offset());
3873 movptr(method_result, vtable_entry_addr);
3874 }
3875
3876
3877 void MacroAssembler::check_klass_subtype(Register sub_klass,
3878 Register super_klass,
3879 Register temp_reg,
3880 Label& L_success) {
3881 Label L_failure;
3882 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
3883 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
3884 bind(L_failure);
3885 }
3886
3887
3888 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
3889 Register super_klass,
3890 Register temp_reg,
3891 Label* L_success,
3892 Label* L_failure,
3893 Label* L_slow_path,
3894 RegisterOrConstant super_check_offset) {
3895 assert_different_registers(sub_klass, super_klass, temp_reg);
3896 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
3897 if (super_check_offset.is_register()) {
3898 assert_different_registers(sub_klass, super_klass,
3899 super_check_offset.as_register());
3900 } else if (must_load_sco) {
3901 assert(temp_reg != noreg, "supply either a temp or a register offset");
3902 }
3903
3904 Label L_fallthrough;
3905 int label_nulls = 0;
3906 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
3907 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
3908 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
3909 assert(label_nulls <= 1, "at most one null in the batch");
3910
3911 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3912 int sco_offset = in_bytes(Klass::super_check_offset_offset());
3913 Address super_check_offset_addr(super_klass, sco_offset);
3914
3915 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
3916 // range of a jccb. If this routine grows larger, reconsider at
3917 // least some of these.
3918 #define local_jcc(assembler_cond, label) \
3919 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
3920 else jcc( assembler_cond, label) /*omit semi*/
3921
3922 // Hacked jmp, which may only be used just before L_fallthrough.
3923 #define final_jmp(label) \
3924 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
3925 else jmp(label) /*omit semi*/
3926
3927 // If the pointers are equal, we are done (e.g., String[] elements).
3928 // This self-check enables sharing of secondary supertype arrays among
3929 // non-primary types such as array-of-interface. Otherwise, each such
3930 // type would need its own customized SSA.
3931 // We move this check to the front of the fast path because many
3932 // type checks are in fact trivially successful in this manner,
3933 // so we get a nicely predicted branch right at the start of the check.
3934 cmpptr(sub_klass, super_klass);
3935 local_jcc(Assembler::equal, *L_success);
3936
3937 // Check the supertype display:
3938 if (must_load_sco) {
3939 // Positive movl does right thing on LP64.
3940 movl(temp_reg, super_check_offset_addr);
3941 super_check_offset = RegisterOrConstant(temp_reg);
3942 }
3943 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
3944 cmpptr(super_klass, super_check_addr); // load displayed supertype
3945
3946 // This check has worked decisively for primary supers.
3947 // Secondary supers are sought in the super_cache ('super_cache_addr').
3948 // (Secondary supers are interfaces and very deeply nested subtypes.)
3949 // This works in the same check above because of a tricky aliasing
3950 // between the super_cache and the primary super display elements.
3951 // (The 'super_check_addr' can address either, as the case requires.)
3952 // Note that the cache is updated below if it does not help us find
3953 // what we need immediately.
3954 // So if it was a primary super, we can just fail immediately.
3955 // Otherwise, it's the slow path for us (no success at this point).
3956
3957 if (super_check_offset.is_register()) {
3958 local_jcc(Assembler::equal, *L_success);
3959 cmpl(super_check_offset.as_register(), sc_offset);
3960 if (L_failure == &L_fallthrough) {
3961 local_jcc(Assembler::equal, *L_slow_path);
3962 } else {
3963 local_jcc(Assembler::notEqual, *L_failure);
3964 final_jmp(*L_slow_path);
3965 }
3966 } else if (super_check_offset.as_constant() == sc_offset) {
3967 // Need a slow path; fast failure is impossible.
3968 if (L_slow_path == &L_fallthrough) {
3969 local_jcc(Assembler::equal, *L_success);
3970 } else {
3971 local_jcc(Assembler::notEqual, *L_slow_path);
3972 final_jmp(*L_success);
3973 }
3974 } else {
3975 // No slow path; it's a fast decision.
3976 if (L_failure == &L_fallthrough) {
3977 local_jcc(Assembler::equal, *L_success);
3978 } else {
3979 local_jcc(Assembler::notEqual, *L_failure);
3980 final_jmp(*L_success);
3981 }
3982 }
3983
3984 bind(L_fallthrough);
3985
3986 #undef local_jcc
3987 #undef final_jmp
3988 }
3989
3990
3991 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
3992 Register super_klass,
3993 Register temp_reg,
3994 Register temp2_reg,
3995 Label* L_success,
3996 Label* L_failure,
3997 bool set_cond_codes) {
3998 assert_different_registers(sub_klass, super_klass, temp_reg);
3999 if (temp2_reg != noreg)
4000 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4001 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4002
4003 Label L_fallthrough;
4004 int label_nulls = 0;
4005 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4006 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4007 assert(label_nulls <= 1, "at most one null in the batch");
4008
4009 // a couple of useful fields in sub_klass:
4010 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4011 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4012 Address secondary_supers_addr(sub_klass, ss_offset);
4013 Address super_cache_addr( sub_klass, sc_offset);
4014
4015 // Do a linear scan of the secondary super-klass chain.
4016 // This code is rarely used, so simplicity is a virtue here.
4017 // The repne_scan instruction uses fixed registers, which we must spill.
4018 // Don't worry too much about pre-existing connections with the input regs.
4019
4020 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4021 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4022
4023 // Get super_klass value into rax (even if it was in rdi or rcx).
4024 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4025 if (super_klass != rax) {
4026 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4027 mov(rax, super_klass);
4028 }
4029 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4030 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4031
4032 #ifndef PRODUCT
4033 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4034 ExternalAddress pst_counter_addr((address) pst_counter);
4035 lea(rcx, pst_counter_addr);
4036 incrementl(Address(rcx, 0));
4037 #endif //PRODUCT
4038
4039 // We will consult the secondary-super array.
4040 movptr(rdi, secondary_supers_addr);
4041 // Load the array length. (Positive movl does right thing on LP64.)
4042 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4043 // Skip to start of data.
4044 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4045
4046 // Scan RCX words at [RDI] for an occurrence of RAX.
4047 // Set NZ/Z based on last compare.
4048 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4049 // not change flags (only scas instruction which is repeated sets flags).
4050 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4051
4052 testptr(rax,rax); // Set Z = 0
4053 repne_scan();
4054
4055 // Unspill the temp. registers:
4056 if (pushed_rdi) pop(rdi);
4057 if (pushed_rcx) pop(rcx);
4058 if (pushed_rax) pop(rax);
4059
4060 if (set_cond_codes) {
4061 // Special hack for the AD files: rdi is guaranteed non-zero.
4062 assert(!pushed_rdi, "rdi must be left non-null");
4063 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4064 }
4065
4066 if (L_failure == &L_fallthrough)
4067 jccb(Assembler::notEqual, *L_failure);
4068 else jcc(Assembler::notEqual, *L_failure);
4069
4070 // Success. Cache the super we found and proceed in triumph.
4071 movptr(super_cache_addr, super_klass);
4072
4073 if (L_success != &L_fallthrough) {
4074 jmp(*L_success);
4075 }
4076
4077 #undef IS_A_TEMP
4078
4079 bind(L_fallthrough);
4080 }
4081
4082 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4083 Register super_klass,
4084 Register temp_reg,
4085 Register temp2_reg,
4086 Label* L_success,
4087 Label* L_failure,
4088 bool set_cond_codes) {
4089 assert(set_cond_codes == false, "must be false on 64-bit x86");
4090 check_klass_subtype_slow_path
4091 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4092 L_success, L_failure);
4093 }
4094
4095 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4096 Register super_klass,
4097 Register temp_reg,
4098 Register temp2_reg,
4099 Register temp3_reg,
4100 Register temp4_reg,
4101 Label* L_success,
4102 Label* L_failure) {
4103 if (UseSecondarySupersTable) {
4104 check_klass_subtype_slow_path_table
4105 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4106 L_success, L_failure);
4107 } else {
4108 check_klass_subtype_slow_path_linear
4109 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4110 }
4111 }
4112
4113 Register MacroAssembler::allocate_if_noreg(Register r,
4114 RegSetIterator<Register> &available_regs,
4115 RegSet ®s_to_push) {
4116 if (!r->is_valid()) {
4117 r = *available_regs++;
4118 regs_to_push += r;
4119 }
4120 return r;
4121 }
4122
4123 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4124 Register super_klass,
4125 Register temp_reg,
4126 Register temp2_reg,
4127 Register temp3_reg,
4128 Register result_reg,
4129 Label* L_success,
4130 Label* L_failure) {
4131 // NB! Callers may assume that, when temp2_reg is a valid register,
4132 // this code sets it to a nonzero value.
4133 bool temp2_reg_was_valid = temp2_reg->is_valid();
4134
4135 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4136
4137 Label L_fallthrough;
4138 int label_nulls = 0;
4139 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4140 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4141 assert(label_nulls <= 1, "at most one null in the batch");
4142
4143 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4144
4145 RegSetIterator<Register> available_regs
4146 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4147
4148 RegSet pushed_regs;
4149
4150 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4151 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4152 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4153 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4154 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4155
4156 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4157
4158 {
4159
4160 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4161 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4162 subptr(rsp, aligned_size);
4163 push_set(pushed_regs, 0);
4164
4165 lookup_secondary_supers_table_var(sub_klass,
4166 super_klass,
4167 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4168 cmpq(result_reg, 0);
4169
4170 // Unspill the temp. registers:
4171 pop_set(pushed_regs, 0);
4172 // Increment SP but do not clobber flags.
4173 lea(rsp, Address(rsp, aligned_size));
4174 }
4175
4176 if (temp2_reg_was_valid) {
4177 movq(temp2_reg, 1);
4178 }
4179
4180 jcc(Assembler::notEqual, *L_failure);
4181
4182 if (L_success != &L_fallthrough) {
4183 jmp(*L_success);
4184 }
4185
4186 bind(L_fallthrough);
4187 }
4188
4189 // population_count variant for running without the POPCNT
4190 // instruction, which was introduced with SSE4.2 in 2008.
4191 void MacroAssembler::population_count(Register dst, Register src,
4192 Register scratch1, Register scratch2) {
4193 assert_different_registers(src, scratch1, scratch2);
4194 if (UsePopCountInstruction) {
4195 Assembler::popcntq(dst, src);
4196 } else {
4197 assert_different_registers(src, scratch1, scratch2);
4198 assert_different_registers(dst, scratch1, scratch2);
4199 Label loop, done;
4200
4201 mov(scratch1, src);
4202 // dst = 0;
4203 // while(scratch1 != 0) {
4204 // dst++;
4205 // scratch1 &= (scratch1 - 1);
4206 // }
4207 xorl(dst, dst);
4208 testq(scratch1, scratch1);
4209 jccb(Assembler::equal, done);
4210 {
4211 bind(loop);
4212 incq(dst);
4213 movq(scratch2, scratch1);
4214 decq(scratch2);
4215 andq(scratch1, scratch2);
4216 jccb(Assembler::notEqual, loop);
4217 }
4218 bind(done);
4219 }
4220 #ifdef ASSERT
4221 mov64(scratch1, 0xCafeBabeDeadBeef);
4222 movq(scratch2, scratch1);
4223 #endif
4224 }
4225
4226 // Ensure that the inline code and the stub are using the same registers.
4227 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4228 do { \
4229 assert(r_super_klass == rax, "mismatch"); \
4230 assert(r_array_base == rbx, "mismatch"); \
4231 assert(r_array_length == rcx, "mismatch"); \
4232 assert(r_array_index == rdx, "mismatch"); \
4233 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4234 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4235 assert(result == rdi || result == noreg, "mismatch"); \
4236 } while(0)
4237
4238 // Versions of salq and rorq that don't need count to be in rcx
4239
4240 void MacroAssembler::salq(Register dest, Register count) {
4241 if (count == rcx) {
4242 Assembler::salq(dest);
4243 } else {
4244 assert_different_registers(rcx, dest);
4245 xchgq(rcx, count);
4246 Assembler::salq(dest);
4247 xchgq(rcx, count);
4248 }
4249 }
4250
4251 void MacroAssembler::rorq(Register dest, Register count) {
4252 if (count == rcx) {
4253 Assembler::rorq(dest);
4254 } else {
4255 assert_different_registers(rcx, dest);
4256 xchgq(rcx, count);
4257 Assembler::rorq(dest);
4258 xchgq(rcx, count);
4259 }
4260 }
4261
4262 // Return true: we succeeded in generating this code
4263 //
4264 // At runtime, return 0 in result if r_super_klass is a superclass of
4265 // r_sub_klass, otherwise return nonzero. Use this if you know the
4266 // super_klass_slot of the class you're looking for. This is always
4267 // the case for instanceof and checkcast.
4268 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4269 Register r_super_klass,
4270 Register temp1,
4271 Register temp2,
4272 Register temp3,
4273 Register temp4,
4274 Register result,
4275 u1 super_klass_slot) {
4276 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4277
4278 Label L_fallthrough, L_success, L_failure;
4279
4280 BLOCK_COMMENT("lookup_secondary_supers_table {");
4281
4282 const Register
4283 r_array_index = temp1,
4284 r_array_length = temp2,
4285 r_array_base = temp3,
4286 r_bitmap = temp4;
4287
4288 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4289
4290 xorq(result, result); // = 0
4291
4292 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4293 movq(r_array_index, r_bitmap);
4294
4295 // First check the bitmap to see if super_klass might be present. If
4296 // the bit is zero, we are certain that super_klass is not one of
4297 // the secondary supers.
4298 u1 bit = super_klass_slot;
4299 {
4300 // NB: If the count in a x86 shift instruction is 0, the flags are
4301 // not affected, so we do a testq instead.
4302 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4303 if (shift_count != 0) {
4304 salq(r_array_index, shift_count);
4305 } else {
4306 testq(r_array_index, r_array_index);
4307 }
4308 }
4309 // We test the MSB of r_array_index, i.e. its sign bit
4310 jcc(Assembler::positive, L_failure);
4311
4312 // Get the first array index that can contain super_klass into r_array_index.
4313 if (bit != 0) {
4314 population_count(r_array_index, r_array_index, temp2, temp3);
4315 } else {
4316 movl(r_array_index, 1);
4317 }
4318 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4319
4320 // We will consult the secondary-super array.
4321 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4322
4323 // We're asserting that the first word in an Array<Klass*> is the
4324 // length, and the second word is the first word of the data. If
4325 // that ever changes, r_array_base will have to be adjusted here.
4326 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4327 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4328
4329 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4330 jccb(Assembler::equal, L_success);
4331
4332 // Is there another entry to check? Consult the bitmap.
4333 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
4334 jccb(Assembler::carryClear, L_failure);
4335
4336 // Linear probe. Rotate the bitmap so that the next bit to test is
4337 // in Bit 1.
4338 if (bit != 0) {
4339 rorq(r_bitmap, bit);
4340 }
4341
4342 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4343 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4344 // Kills: r_array_length.
4345 // Returns: result.
4346 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
4347 // Result (0/1) is in rdi
4348 jmpb(L_fallthrough);
4349
4350 bind(L_failure);
4351 incq(result); // 0 => 1
4352
4353 bind(L_success);
4354 // result = 0;
4355
4356 bind(L_fallthrough);
4357 BLOCK_COMMENT("} lookup_secondary_supers_table");
4358
4359 if (VerifySecondarySupers) {
4360 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4361 temp1, temp2, temp3);
4362 }
4363 }
4364
4365 // At runtime, return 0 in result if r_super_klass is a superclass of
4366 // r_sub_klass, otherwise return nonzero. Use this version of
4367 // lookup_secondary_supers_table() if you don't know ahead of time
4368 // which superclass will be searched for. Used by interpreter and
4369 // runtime stubs. It is larger and has somewhat greater latency than
4370 // the version above, which takes a constant super_klass_slot.
4371 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
4372 Register r_super_klass,
4373 Register temp1,
4374 Register temp2,
4375 Register temp3,
4376 Register temp4,
4377 Register result) {
4378 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4379 assert_different_registers(r_sub_klass, r_super_klass, rcx);
4380 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
4381
4382 Label L_fallthrough, L_success, L_failure;
4383
4384 BLOCK_COMMENT("lookup_secondary_supers_table {");
4385
4386 RegSetIterator<Register> available_regs = (temps - rcx).begin();
4387
4388 // FIXME. Once we are sure that all paths reaching this point really
4389 // do pass rcx as one of our temps we can get rid of the following
4390 // workaround.
4391 assert(temps.contains(rcx), "fix this code");
4392
4393 // We prefer to have our shift count in rcx. If rcx is one of our
4394 // temps, use it for slot. If not, pick any of our temps.
4395 Register slot;
4396 if (!temps.contains(rcx)) {
4397 slot = *available_regs++;
4398 } else {
4399 slot = rcx;
4400 }
4401
4402 const Register r_array_index = *available_regs++;
4403 const Register r_bitmap = *available_regs++;
4404
4405 // The logic above guarantees this property, but we state it here.
4406 assert_different_registers(r_array_index, r_bitmap, rcx);
4407
4408 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4409 movq(r_array_index, r_bitmap);
4410
4411 // First check the bitmap to see if super_klass might be present. If
4412 // the bit is zero, we are certain that super_klass is not one of
4413 // the secondary supers.
4414 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4415 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
4416 salq(r_array_index, slot);
4417
4418 testq(r_array_index, r_array_index);
4419 // We test the MSB of r_array_index, i.e. its sign bit
4420 jcc(Assembler::positive, L_failure);
4421
4422 const Register r_array_base = *available_regs++;
4423
4424 // Get the first array index that can contain super_klass into r_array_index.
4425 // Note: Clobbers r_array_base and slot.
4426 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
4427
4428 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4429
4430 // We will consult the secondary-super array.
4431 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4432
4433 // We're asserting that the first word in an Array<Klass*> is the
4434 // length, and the second word is the first word of the data. If
4435 // that ever changes, r_array_base will have to be adjusted here.
4436 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4437 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4438
4439 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4440 jccb(Assembler::equal, L_success);
4441
4442 // Restore slot to its true value
4443 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4444
4445 // Linear probe. Rotate the bitmap so that the next bit to test is
4446 // in Bit 1.
4447 rorq(r_bitmap, slot);
4448
4449 // Is there another entry to check? Consult the bitmap.
4450 btq(r_bitmap, 1);
4451 jccb(Assembler::carryClear, L_failure);
4452
4453 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4454 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4455 // Kills: r_array_length.
4456 // Returns: result.
4457 lookup_secondary_supers_table_slow_path(r_super_klass,
4458 r_array_base,
4459 r_array_index,
4460 r_bitmap,
4461 /*temp1*/result,
4462 /*temp2*/slot,
4463 &L_success,
4464 nullptr);
4465
4466 bind(L_failure);
4467 movq(result, 1);
4468 jmpb(L_fallthrough);
4469
4470 bind(L_success);
4471 xorq(result, result); // = 0
4472
4473 bind(L_fallthrough);
4474 BLOCK_COMMENT("} lookup_secondary_supers_table");
4475
4476 if (VerifySecondarySupers) {
4477 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4478 temp1, temp2, temp3);
4479 }
4480 }
4481
4482 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
4483 Label* L_success, Label* L_failure) {
4484 Label L_loop, L_fallthrough;
4485 {
4486 int label_nulls = 0;
4487 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4488 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4489 assert(label_nulls <= 1, "at most one null in the batch");
4490 }
4491 bind(L_loop);
4492 cmpq(value, Address(addr, count, Address::times_8));
4493 jcc(Assembler::equal, *L_success);
4494 addl(count, 1);
4495 cmpl(count, limit);
4496 jcc(Assembler::less, L_loop);
4497
4498 if (&L_fallthrough != L_failure) {
4499 jmp(*L_failure);
4500 }
4501 bind(L_fallthrough);
4502 }
4503
4504 // Called by code generated by check_klass_subtype_slow_path
4505 // above. This is called when there is a collision in the hashed
4506 // lookup in the secondary supers array.
4507 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
4508 Register r_array_base,
4509 Register r_array_index,
4510 Register r_bitmap,
4511 Register temp1,
4512 Register temp2,
4513 Label* L_success,
4514 Label* L_failure) {
4515 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
4516
4517 const Register
4518 r_array_length = temp1,
4519 r_sub_klass = noreg,
4520 result = noreg;
4521
4522 Label L_fallthrough;
4523 int label_nulls = 0;
4524 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4525 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4526 assert(label_nulls <= 1, "at most one null in the batch");
4527
4528 // Load the array length.
4529 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4530 // And adjust the array base to point to the data.
4531 // NB! Effectively increments current slot index by 1.
4532 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
4533 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4534
4535 // Linear probe
4536 Label L_huge;
4537
4538 // The bitmap is full to bursting.
4539 // Implicit invariant: BITMAP_FULL implies (length > 0)
4540 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
4541 jcc(Assembler::greater, L_huge);
4542
4543 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
4544 // current slot (at secondary_supers[r_array_index]) has not yet
4545 // been inspected, and r_array_index may be out of bounds if we
4546 // wrapped around the end of the array.
4547
4548 { // This is conventional linear probing, but instead of terminating
4549 // when a null entry is found in the table, we maintain a bitmap
4550 // in which a 0 indicates missing entries.
4551 // The check above guarantees there are 0s in the bitmap, so the loop
4552 // eventually terminates.
4553
4554 xorl(temp2, temp2); // = 0;
4555
4556 Label L_again;
4557 bind(L_again);
4558
4559 // Check for array wraparound.
4560 cmpl(r_array_index, r_array_length);
4561 cmovl(Assembler::greaterEqual, r_array_index, temp2);
4562
4563 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4564 jcc(Assembler::equal, *L_success);
4565
4566 // If the next bit in bitmap is zero, we're done.
4567 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
4568 jcc(Assembler::carryClear, *L_failure);
4569
4570 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
4571 addl(r_array_index, 1);
4572
4573 jmp(L_again);
4574 }
4575
4576 { // Degenerate case: more than 64 secondary supers.
4577 // FIXME: We could do something smarter here, maybe a vectorized
4578 // comparison or a binary search, but is that worth any added
4579 // complexity?
4580 bind(L_huge);
4581 xorl(r_array_index, r_array_index); // = 0
4582 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
4583 L_success,
4584 (&L_fallthrough != L_failure ? L_failure : nullptr));
4585
4586 bind(L_fallthrough);
4587 }
4588 }
4589
4590 struct VerifyHelperArguments {
4591 Klass* _super;
4592 Klass* _sub;
4593 intptr_t _linear_result;
4594 intptr_t _table_result;
4595 };
4596
4597 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
4598 Klass::on_secondary_supers_verification_failure(args->_super,
4599 args->_sub,
4600 args->_linear_result,
4601 args->_table_result,
4602 msg);
4603 }
4604
4605 // Make sure that the hashed lookup and a linear scan agree.
4606 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
4607 Register r_super_klass,
4608 Register result,
4609 Register temp1,
4610 Register temp2,
4611 Register temp3) {
4612 const Register
4613 r_array_index = temp1,
4614 r_array_length = temp2,
4615 r_array_base = temp3,
4616 r_bitmap = noreg;
4617
4618 BLOCK_COMMENT("verify_secondary_supers_table {");
4619
4620 Label L_success, L_failure, L_check, L_done;
4621
4622 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4623 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4624 // And adjust the array base to point to the data.
4625 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4626
4627 testl(r_array_length, r_array_length); // array_length == 0?
4628 jcc(Assembler::zero, L_failure);
4629
4630 movl(r_array_index, 0);
4631 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
4632 // fall through to L_failure
4633
4634 const Register linear_result = r_array_index; // reuse temp1
4635
4636 bind(L_failure); // not present
4637 movl(linear_result, 1);
4638 jmp(L_check);
4639
4640 bind(L_success); // present
4641 movl(linear_result, 0);
4642
4643 bind(L_check);
4644 cmpl(linear_result, result);
4645 jcc(Assembler::equal, L_done);
4646
4647 { // To avoid calling convention issues, build a record on the stack
4648 // and pass the pointer to that instead.
4649 push(result);
4650 push(linear_result);
4651 push(r_sub_klass);
4652 push(r_super_klass);
4653 movptr(c_rarg1, rsp);
4654 movptr(c_rarg0, (uintptr_t) "mismatch");
4655 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
4656 should_not_reach_here();
4657 }
4658 bind(L_done);
4659
4660 BLOCK_COMMENT("} verify_secondary_supers_table");
4661 }
4662
4663 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
4664
4665 void MacroAssembler::clinit_barrier(Register klass, Label* L_fast_path, Label* L_slow_path) {
4666 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
4667
4668 Label L_fallthrough;
4669 if (L_fast_path == nullptr) {
4670 L_fast_path = &L_fallthrough;
4671 } else if (L_slow_path == nullptr) {
4672 L_slow_path = &L_fallthrough;
4673 }
4674
4675 // Fast path check: class is fully initialized.
4676 // init_state needs acquire, but x86 is TSO, and so we are already good.
4677 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4678 jcc(Assembler::equal, *L_fast_path);
4679
4680 // Fast path check: current thread is initializer thread
4681 cmpptr(r15_thread, Address(klass, InstanceKlass::init_thread_offset()));
4682 if (L_slow_path == &L_fallthrough) {
4683 jcc(Assembler::equal, *L_fast_path);
4684 bind(*L_slow_path);
4685 } else if (L_fast_path == &L_fallthrough) {
4686 jcc(Assembler::notEqual, *L_slow_path);
4687 bind(*L_fast_path);
4688 } else {
4689 Unimplemented();
4690 }
4691 }
4692
4693 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4694 if (VM_Version::supports_cmov()) {
4695 cmovl(cc, dst, src);
4696 } else {
4697 Label L;
4698 jccb(negate_condition(cc), L);
4699 movl(dst, src);
4700 bind(L);
4701 }
4702 }
4703
4704 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4705 if (VM_Version::supports_cmov()) {
4706 cmovl(cc, dst, src);
4707 } else {
4708 Label L;
4709 jccb(negate_condition(cc), L);
4710 movl(dst, src);
4711 bind(L);
4712 }
4713 }
4714
4715 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
4716 if (!VerifyOops) return;
4717
4718 BLOCK_COMMENT("verify_oop {");
4719 push(rscratch1);
4720 push(rax); // save rax
4721 push(reg); // pass register argument
4722
4723 // Pass register number to verify_oop_subroutine
4724 const char* b = nullptr;
4725 {
4726 ResourceMark rm;
4727 stringStream ss;
4728 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
4729 b = code_string(ss.as_string());
4730 }
4731 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
4732 pushptr(buffer.addr(), rscratch1);
4733
4734 // call indirectly to solve generation ordering problem
4735 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4736 call(rax);
4737 // Caller pops the arguments (oop, message) and restores rax, r10
4738 BLOCK_COMMENT("} verify_oop");
4739 }
4740
4741 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
4742 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
4743 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
4744 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
4745 vpternlogd(dst, 0xFF, dst, dst, vector_len);
4746 } else if (VM_Version::supports_avx()) {
4747 vpcmpeqd(dst, dst, dst, vector_len);
4748 } else {
4749 pcmpeqd(dst, dst);
4750 }
4751 }
4752
4753 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4754 int extra_slot_offset) {
4755 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4756 int stackElementSize = Interpreter::stackElementSize;
4757 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4758 #ifdef ASSERT
4759 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4760 assert(offset1 - offset == stackElementSize, "correct arithmetic");
4761 #endif
4762 Register scale_reg = noreg;
4763 Address::ScaleFactor scale_factor = Address::no_scale;
4764 if (arg_slot.is_constant()) {
4765 offset += arg_slot.as_constant() * stackElementSize;
4766 } else {
4767 scale_reg = arg_slot.as_register();
4768 scale_factor = Address::times(stackElementSize);
4769 }
4770 offset += wordSize; // return PC is on stack
4771 return Address(rsp, scale_reg, scale_factor, offset);
4772 }
4773
4774 // Handle the receiver type profile update given the "recv" klass.
4775 //
4776 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
4777 // If there are no matching or claimable receiver entries in RD, updates
4778 // the polymorphic counter.
4779 //
4780 // This code expected to run by either the interpreter or JIT-ed code, without
4781 // extra synchronization. For safety, receiver cells are claimed atomically, which
4782 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
4783 // counter updates are not atomic.
4784 //
4785 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
4786 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
4787 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
4788 int poly_count_offset = in_bytes(CounterData::count_offset());
4789 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
4790 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
4791
4792 // Adjust for MDP offsets. Slots are pointer-sized, so is the global offset.
4793 assert(is_aligned(mdp_offset, BytesPerWord), "sanity");
4794 base_receiver_offset += mdp_offset;
4795 end_receiver_offset += mdp_offset;
4796 poly_count_offset += mdp_offset;
4797
4798 // Scale down to optimize encoding. Slots are pointer-sized.
4799 assert(is_aligned(base_receiver_offset, BytesPerWord), "sanity");
4800 assert(is_aligned(end_receiver_offset, BytesPerWord), "sanity");
4801 assert(is_aligned(poly_count_offset, BytesPerWord), "sanity");
4802 assert(is_aligned(receiver_step, BytesPerWord), "sanity");
4803 assert(is_aligned(receiver_to_count_step, BytesPerWord), "sanity");
4804 base_receiver_offset >>= LogBytesPerWord;
4805 end_receiver_offset >>= LogBytesPerWord;
4806 poly_count_offset >>= LogBytesPerWord;
4807 receiver_step >>= LogBytesPerWord;
4808 receiver_to_count_step >>= LogBytesPerWord;
4809
4810 #ifdef ASSERT
4811 // We are about to walk the MDO slots without asking for offsets.
4812 // Check that our math hits all the right spots.
4813 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
4814 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
4815 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
4816 int offset = base_receiver_offset + receiver_step*c;
4817 int count_offset = offset + receiver_to_count_step;
4818 assert((offset << LogBytesPerWord) == real_recv_offset, "receiver slot math");
4819 assert((count_offset << LogBytesPerWord) == real_count_offset, "receiver count math");
4820 }
4821 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
4822 assert(poly_count_offset << LogBytesPerWord == real_poly_count_offset, "poly counter math");
4823 #endif
4824
4825 // Corner case: no profile table. Increment poly counter and exit.
4826 if (ReceiverTypeData::row_limit() == 0) {
4827 addptr(Address(mdp, poly_count_offset, Address::times_ptr), DataLayout::counter_increment);
4828 return;
4829 }
4830
4831 Register offset = rscratch1;
4832
4833 Label L_loop_search_receiver, L_loop_search_empty;
4834 Label L_restart, L_found_recv, L_found_empty, L_polymorphic, L_count_update;
4835
4836 // The code here recognizes three major cases:
4837 // A. Fastest: receiver found in the table
4838 // B. Fast: no receiver in the table, and the table is full
4839 // C. Slow: no receiver in the table, free slots in the table
4840 //
4841 // The case A performance is most important, as perfectly-behaved code would end up
4842 // there, especially with larger TypeProfileWidth. The case B performance is
4843 // important as well, this is where bulk of code would land for normally megamorphic
4844 // cases. The case C performance is not essential, its job is to deal with installation
4845 // races, we optimize for code density instead. Case C needs to make sure that receiver
4846 // rows are only claimed once. This makes sure we never overwrite a row for another
4847 // receiver and never duplicate the receivers in the list, making profile type-accurate.
4848 //
4849 // It is very tempting to handle these cases in a single loop, and claim the first slot
4850 // without checking the rest of the table. But, profiling code should tolerate free slots
4851 // in the table, as class unloading can clear them. After such cleanup, the receiver
4852 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
4853 // to complete, before trying to install new slots. Splitting the code in several tight
4854 // loops also helpfully optimizes for cases A and B.
4855 //
4856 // This code is effectively:
4857 //
4858 // restart:
4859 // // Fastest: receiver is already installed
4860 // for (i = 0; i < receiver_count(); i++) {
4861 // if (receiver(i) == recv) goto found_recv(i);
4862 // }
4863 //
4864 // // Fast: no receiver, but profile is full
4865 // for (i = 0; i < receiver_count(); i++) {
4866 // if (receiver(i) == null) goto found_null(i);
4867 // }
4868 // goto polymorphic
4869 //
4870 // // Slow: try to install receiver
4871 // found_null(i):
4872 // CAS(&receiver(i), null, recv);
4873 // goto restart
4874 //
4875 // polymorphic:
4876 // count++;
4877 // return
4878 //
4879 // found_recv(i):
4880 // *receiver_count(i)++
4881 //
4882
4883 bind(L_restart);
4884
4885 // Fastest: receiver is already installed
4886 movptr(offset, base_receiver_offset);
4887 bind(L_loop_search_receiver);
4888 cmpptr(recv, Address(mdp, offset, Address::times_ptr));
4889 jccb(Assembler::equal, L_found_recv);
4890 addptr(offset, receiver_step);
4891 cmpptr(offset, end_receiver_offset);
4892 jccb(Assembler::notEqual, L_loop_search_receiver);
4893
4894 // Fast: no receiver, but profile is full
4895 movptr(offset, base_receiver_offset);
4896 bind(L_loop_search_empty);
4897 cmpptr(Address(mdp, offset, Address::times_ptr), NULL_WORD);
4898 jccb(Assembler::equal, L_found_empty);
4899 addptr(offset, receiver_step);
4900 cmpptr(offset, end_receiver_offset);
4901 jccb(Assembler::notEqual, L_loop_search_empty);
4902 jmpb(L_polymorphic);
4903
4904 // Slow: try to install receiver
4905 bind(L_found_empty);
4906
4907 // Atomically swing receiver slot: null -> recv.
4908 //
4909 // The update code uses CAS, which wants RAX register specifically, *and* it needs
4910 // other important registers untouched, as they form the address. Therefore, we need
4911 // to shift any important registers from RAX into some other spare register. If we
4912 // have a spare register, we are forced to save it on stack here.
4913
4914 Register spare_reg = noreg;
4915 Register shifted_mdp = mdp;
4916 Register shifted_recv = recv;
4917 if (recv == rax || mdp == rax) {
4918 spare_reg = (recv != rbx && mdp != rbx) ? rbx :
4919 (recv != rcx && mdp != rcx) ? rcx :
4920 rdx;
4921 assert_different_registers(mdp, recv, offset, spare_reg);
4922
4923 push(spare_reg);
4924 if (recv == rax) {
4925 movptr(spare_reg, recv);
4926 shifted_recv = spare_reg;
4927 } else {
4928 assert(mdp == rax, "Remaining case");
4929 movptr(spare_reg, mdp);
4930 shifted_mdp = spare_reg;
4931 }
4932 } else {
4933 push(rax);
4934 }
4935
4936 // None of the important registers are in RAX after this shuffle.
4937 assert_different_registers(rax, shifted_mdp, shifted_recv, offset);
4938
4939 xorptr(rax, rax);
4940 cmpxchgptr(shifted_recv, Address(shifted_mdp, offset, Address::times_ptr));
4941
4942 // Unshift registers.
4943 if (recv == rax || mdp == rax) {
4944 movptr(rax, spare_reg);
4945 pop(spare_reg);
4946 } else {
4947 pop(rax);
4948 }
4949
4950 // CAS success means the slot now has the receiver we want. CAS failure means
4951 // something had claimed the slot concurrently: it can be the same receiver we want,
4952 // or something else. Since this is a slow path, we can optimize for code density,
4953 // and just restart the search from the beginning.
4954 jmpb(L_restart);
4955
4956 // Counter updates:
4957
4958 // Increment polymorphic counter instead of receiver slot.
4959 bind(L_polymorphic);
4960 movptr(offset, poly_count_offset);
4961 jmpb(L_count_update);
4962
4963 // Found a receiver, convert its slot offset to corresponding count offset.
4964 bind(L_found_recv);
4965 addptr(offset, receiver_to_count_step);
4966
4967 bind(L_count_update);
4968 addptr(Address(mdp, offset, Address::times_ptr), DataLayout::counter_increment);
4969 }
4970
4971 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
4972 if (!VerifyOops) return;
4973
4974 push(rscratch1);
4975 push(rax); // save rax,
4976 // addr may contain rsp so we will have to adjust it based on the push
4977 // we just did (and on 64 bit we do two pushes)
4978 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4979 // stores rax into addr which is backwards of what was intended.
4980 if (addr.uses(rsp)) {
4981 lea(rax, addr);
4982 pushptr(Address(rax, 2 * BytesPerWord));
4983 } else {
4984 pushptr(addr);
4985 }
4986
4987 // Pass register number to verify_oop_subroutine
4988 const char* b = nullptr;
4989 {
4990 ResourceMark rm;
4991 stringStream ss;
4992 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
4993 b = code_string(ss.as_string());
4994 }
4995 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
4996 pushptr(buffer.addr(), rscratch1);
4997
4998 // call indirectly to solve generation ordering problem
4999 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5000 call(rax);
5001 // Caller pops the arguments (addr, message) and restores rax, r10.
5002 }
5003
5004 void MacroAssembler::verify_tlab() {
5005 #ifdef ASSERT
5006 if (UseTLAB && VerifyOops) {
5007 Label next, ok;
5008 Register t1 = rsi;
5009
5010 push(t1);
5011
5012 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5013 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_start_offset())));
5014 jcc(Assembler::aboveEqual, next);
5015 STOP("assert(top >= start)");
5016 should_not_reach_here();
5017
5018 bind(next);
5019 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_end_offset())));
5020 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5021 jcc(Assembler::aboveEqual, ok);
5022 STOP("assert(top <= end)");
5023 should_not_reach_here();
5024
5025 bind(ok);
5026 pop(t1);
5027 }
5028 #endif
5029 }
5030
5031 class ControlWord {
5032 public:
5033 int32_t _value;
5034
5035 int rounding_control() const { return (_value >> 10) & 3 ; }
5036 int precision_control() const { return (_value >> 8) & 3 ; }
5037 bool precision() const { return ((_value >> 5) & 1) != 0; }
5038 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5039 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5040 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5041 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5042 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5043
5044 void print() const {
5045 // rounding control
5046 const char* rc;
5047 switch (rounding_control()) {
5048 case 0: rc = "round near"; break;
5049 case 1: rc = "round down"; break;
5050 case 2: rc = "round up "; break;
5051 case 3: rc = "chop "; break;
5052 default:
5053 rc = nullptr; // silence compiler warnings
5054 fatal("Unknown rounding control: %d", rounding_control());
5055 };
5056 // precision control
5057 const char* pc;
5058 switch (precision_control()) {
5059 case 0: pc = "24 bits "; break;
5060 case 1: pc = "reserved"; break;
5061 case 2: pc = "53 bits "; break;
5062 case 3: pc = "64 bits "; break;
5063 default:
5064 pc = nullptr; // silence compiler warnings
5065 fatal("Unknown precision control: %d", precision_control());
5066 };
5067 // flags
5068 char f[9];
5069 f[0] = ' ';
5070 f[1] = ' ';
5071 f[2] = (precision ()) ? 'P' : 'p';
5072 f[3] = (underflow ()) ? 'U' : 'u';
5073 f[4] = (overflow ()) ? 'O' : 'o';
5074 f[5] = (zero_divide ()) ? 'Z' : 'z';
5075 f[6] = (denormalized()) ? 'D' : 'd';
5076 f[7] = (invalid ()) ? 'I' : 'i';
5077 f[8] = '\x0';
5078 // output
5079 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5080 }
5081
5082 };
5083
5084 class StatusWord {
5085 public:
5086 int32_t _value;
5087
5088 bool busy() const { return ((_value >> 15) & 1) != 0; }
5089 bool C3() const { return ((_value >> 14) & 1) != 0; }
5090 bool C2() const { return ((_value >> 10) & 1) != 0; }
5091 bool C1() const { return ((_value >> 9) & 1) != 0; }
5092 bool C0() const { return ((_value >> 8) & 1) != 0; }
5093 int top() const { return (_value >> 11) & 7 ; }
5094 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5095 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5096 bool precision() const { return ((_value >> 5) & 1) != 0; }
5097 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5098 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5099 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5100 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5101 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5102
5103 void print() const {
5104 // condition codes
5105 char c[5];
5106 c[0] = (C3()) ? '3' : '-';
5107 c[1] = (C2()) ? '2' : '-';
5108 c[2] = (C1()) ? '1' : '-';
5109 c[3] = (C0()) ? '0' : '-';
5110 c[4] = '\x0';
5111 // flags
5112 char f[9];
5113 f[0] = (error_status()) ? 'E' : '-';
5114 f[1] = (stack_fault ()) ? 'S' : '-';
5115 f[2] = (precision ()) ? 'P' : '-';
5116 f[3] = (underflow ()) ? 'U' : '-';
5117 f[4] = (overflow ()) ? 'O' : '-';
5118 f[5] = (zero_divide ()) ? 'Z' : '-';
5119 f[6] = (denormalized()) ? 'D' : '-';
5120 f[7] = (invalid ()) ? 'I' : '-';
5121 f[8] = '\x0';
5122 // output
5123 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5124 }
5125
5126 };
5127
5128 class TagWord {
5129 public:
5130 int32_t _value;
5131
5132 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5133
5134 void print() const {
5135 printf("%04x", _value & 0xFFFF);
5136 }
5137
5138 };
5139
5140 class FPU_Register {
5141 public:
5142 int32_t _m0;
5143 int32_t _m1;
5144 int16_t _ex;
5145
5146 bool is_indefinite() const {
5147 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5148 }
5149
5150 void print() const {
5151 char sign = (_ex < 0) ? '-' : '+';
5152 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5153 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5154 };
5155
5156 };
5157
5158 class FPU_State {
5159 public:
5160 enum {
5161 register_size = 10,
5162 number_of_registers = 8,
5163 register_mask = 7
5164 };
5165
5166 ControlWord _control_word;
5167 StatusWord _status_word;
5168 TagWord _tag_word;
5169 int32_t _error_offset;
5170 int32_t _error_selector;
5171 int32_t _data_offset;
5172 int32_t _data_selector;
5173 int8_t _register[register_size * number_of_registers];
5174
5175 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5176 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5177
5178 const char* tag_as_string(int tag) const {
5179 switch (tag) {
5180 case 0: return "valid";
5181 case 1: return "zero";
5182 case 2: return "special";
5183 case 3: return "empty";
5184 }
5185 ShouldNotReachHere();
5186 return nullptr;
5187 }
5188
5189 void print() const {
5190 // print computation registers
5191 { int t = _status_word.top();
5192 for (int i = 0; i < number_of_registers; i++) {
5193 int j = (i - t) & register_mask;
5194 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5195 st(j)->print();
5196 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5197 }
5198 }
5199 printf("\n");
5200 // print control registers
5201 printf("ctrl = "); _control_word.print(); printf("\n");
5202 printf("stat = "); _status_word .print(); printf("\n");
5203 printf("tags = "); _tag_word .print(); printf("\n");
5204 }
5205
5206 };
5207
5208 class Flag_Register {
5209 public:
5210 int32_t _value;
5211
5212 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5213 bool direction() const { return ((_value >> 10) & 1) != 0; }
5214 bool sign() const { return ((_value >> 7) & 1) != 0; }
5215 bool zero() const { return ((_value >> 6) & 1) != 0; }
5216 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5217 bool parity() const { return ((_value >> 2) & 1) != 0; }
5218 bool carry() const { return ((_value >> 0) & 1) != 0; }
5219
5220 void print() const {
5221 // flags
5222 char f[8];
5223 f[0] = (overflow ()) ? 'O' : '-';
5224 f[1] = (direction ()) ? 'D' : '-';
5225 f[2] = (sign ()) ? 'S' : '-';
5226 f[3] = (zero ()) ? 'Z' : '-';
5227 f[4] = (auxiliary_carry()) ? 'A' : '-';
5228 f[5] = (parity ()) ? 'P' : '-';
5229 f[6] = (carry ()) ? 'C' : '-';
5230 f[7] = '\x0';
5231 // output
5232 printf("%08x flags = %s", _value, f);
5233 }
5234
5235 };
5236
5237 class IU_Register {
5238 public:
5239 int32_t _value;
5240
5241 void print() const {
5242 printf("%08x %11d", _value, _value);
5243 }
5244
5245 };
5246
5247 class IU_State {
5248 public:
5249 Flag_Register _eflags;
5250 IU_Register _rdi;
5251 IU_Register _rsi;
5252 IU_Register _rbp;
5253 IU_Register _rsp;
5254 IU_Register _rbx;
5255 IU_Register _rdx;
5256 IU_Register _rcx;
5257 IU_Register _rax;
5258
5259 void print() const {
5260 // computation registers
5261 printf("rax, = "); _rax.print(); printf("\n");
5262 printf("rbx, = "); _rbx.print(); printf("\n");
5263 printf("rcx = "); _rcx.print(); printf("\n");
5264 printf("rdx = "); _rdx.print(); printf("\n");
5265 printf("rdi = "); _rdi.print(); printf("\n");
5266 printf("rsi = "); _rsi.print(); printf("\n");
5267 printf("rbp, = "); _rbp.print(); printf("\n");
5268 printf("rsp = "); _rsp.print(); printf("\n");
5269 printf("\n");
5270 // control registers
5271 printf("flgs = "); _eflags.print(); printf("\n");
5272 }
5273 };
5274
5275
5276 class CPU_State {
5277 public:
5278 FPU_State _fpu_state;
5279 IU_State _iu_state;
5280
5281 void print() const {
5282 printf("--------------------------------------------------\n");
5283 _iu_state .print();
5284 printf("\n");
5285 _fpu_state.print();
5286 printf("--------------------------------------------------\n");
5287 }
5288
5289 };
5290
5291
5292 static void _print_CPU_state(CPU_State* state) {
5293 state->print();
5294 };
5295
5296
5297 void MacroAssembler::print_CPU_state() {
5298 push_CPU_state();
5299 push(rsp); // pass CPU state
5300 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5301 addptr(rsp, wordSize); // discard argument
5302 pop_CPU_state();
5303 }
5304
5305 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5306 // Either restore the MXCSR register after returning from the JNI Call
5307 // or verify that it wasn't changed (with -Xcheck:jni flag).
5308 if (VM_Version::supports_sse()) {
5309 if (RestoreMXCSROnJNICalls) {
5310 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5311 } else if (CheckJNICalls) {
5312 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5313 }
5314 }
5315 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5316 vzeroupper();
5317 }
5318
5319 // ((OopHandle)result).resolve();
5320 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5321 assert_different_registers(result, tmp);
5322
5323 // Only 64 bit platforms support GCs that require a tmp register
5324 // Only IN_HEAP loads require a thread_tmp register
5325 // OopHandle::resolve is an indirection like jobject.
5326 access_load_at(T_OBJECT, IN_NATIVE,
5327 result, Address(result, 0), tmp);
5328 }
5329
5330 // ((WeakHandle)result).resolve();
5331 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5332 assert_different_registers(rresult, rtmp);
5333 Label resolved;
5334
5335 // A null weak handle resolves to null.
5336 cmpptr(rresult, 0);
5337 jcc(Assembler::equal, resolved);
5338
5339 // Only 64 bit platforms support GCs that require a tmp register
5340 // Only IN_HEAP loads require a thread_tmp register
5341 // WeakHandle::resolve is an indirection like jweak.
5342 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5343 rresult, Address(rresult, 0), rtmp);
5344 bind(resolved);
5345 }
5346
5347 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5348 // get mirror
5349 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5350 load_method_holder(mirror, method);
5351 movptr(mirror, Address(mirror, mirror_offset));
5352 resolve_oop_handle(mirror, tmp);
5353 }
5354
5355 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5356 load_method_holder(rresult, rmethod);
5357 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5358 }
5359
5360 void MacroAssembler::load_method_holder(Register holder, Register method) {
5361 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5362 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5363 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5364 }
5365
5366 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5367 assert(UseCompactObjectHeaders, "expect compact object headers");
5368 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5369 shrq(dst, markWord::klass_shift);
5370 }
5371
5372 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5373 assert_different_registers(src, tmp);
5374 assert_different_registers(dst, tmp);
5375
5376 if (UseCompactObjectHeaders) {
5377 load_narrow_klass_compact(dst, src);
5378 decode_klass_not_null(dst, tmp);
5379 } else if (UseCompressedClassPointers) {
5380 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5381 decode_klass_not_null(dst, tmp);
5382 } else {
5383 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5384 }
5385 }
5386
5387 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5388 assert(!UseCompactObjectHeaders, "not with compact headers");
5389 assert_different_registers(src, tmp);
5390 assert_different_registers(dst, tmp);
5391 if (UseCompressedClassPointers) {
5392 encode_klass_not_null(src, tmp);
5393 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5394 } else {
5395 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5396 }
5397 }
5398
5399 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
5400 if (UseCompactObjectHeaders) {
5401 assert(tmp != noreg, "need tmp");
5402 assert_different_registers(klass, obj, tmp);
5403 load_narrow_klass_compact(tmp, obj);
5404 cmpl(klass, tmp);
5405 } else if (UseCompressedClassPointers) {
5406 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5407 } else {
5408 cmpptr(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5409 }
5410 }
5411
5412 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5413 if (UseCompactObjectHeaders) {
5414 assert(tmp2 != noreg, "need tmp2");
5415 assert_different_registers(obj1, obj2, tmp1, tmp2);
5416 load_narrow_klass_compact(tmp1, obj1);
5417 load_narrow_klass_compact(tmp2, obj2);
5418 cmpl(tmp1, tmp2);
5419 } else if (UseCompressedClassPointers) {
5420 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5421 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5422 } else {
5423 movptr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5424 cmpptr(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5425 }
5426 }
5427
5428 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5429 Register tmp1) {
5430 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5431 decorators = AccessInternal::decorator_fixup(decorators, type);
5432 bool as_raw = (decorators & AS_RAW) != 0;
5433 if (as_raw) {
5434 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1);
5435 } else {
5436 bs->load_at(this, decorators, type, dst, src, tmp1);
5437 }
5438 }
5439
5440 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5441 Register tmp1, Register tmp2, Register tmp3) {
5442 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5443 decorators = AccessInternal::decorator_fixup(decorators, type);
5444 bool as_raw = (decorators & AS_RAW) != 0;
5445 if (as_raw) {
5446 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5447 } else {
5448 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5449 }
5450 }
5451
5452 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5453 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1);
5454 }
5455
5456 // Doesn't do verification, generates fixed size code
5457 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5458 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1);
5459 }
5460
5461 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5462 Register tmp2, Register tmp3, DecoratorSet decorators) {
5463 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5464 }
5465
5466 // Used for storing nulls.
5467 void MacroAssembler::store_heap_oop_null(Address dst) {
5468 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5469 }
5470
5471 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5472 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
5473 if (UseCompressedClassPointers) {
5474 // Store to klass gap in destination
5475 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5476 }
5477 }
5478
5479 #ifdef ASSERT
5480 void MacroAssembler::verify_heapbase(const char* msg) {
5481 assert (UseCompressedOops, "should be compressed");
5482 assert (Universe::heap() != nullptr, "java heap should be initialized");
5483 if (CheckCompressedOops) {
5484 Label ok;
5485 ExternalAddress src2(CompressedOops::base_addr());
5486 const bool is_src2_reachable = reachable(src2);
5487 if (!is_src2_reachable) {
5488 push(rscratch1); // cmpptr trashes rscratch1
5489 }
5490 cmpptr(r12_heapbase, src2, rscratch1);
5491 jcc(Assembler::equal, ok);
5492 STOP(msg);
5493 bind(ok);
5494 if (!is_src2_reachable) {
5495 pop(rscratch1);
5496 }
5497 }
5498 }
5499 #endif
5500
5501 // Algorithm must match oop.inline.hpp encode_heap_oop.
5502 void MacroAssembler::encode_heap_oop(Register r) {
5503 #ifdef ASSERT
5504 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5505 #endif
5506 verify_oop_msg(r, "broken oop in encode_heap_oop");
5507 if (CompressedOops::base() == nullptr) {
5508 if (CompressedOops::shift() != 0) {
5509 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5510 shrq(r, LogMinObjAlignmentInBytes);
5511 }
5512 return;
5513 }
5514 testq(r, r);
5515 cmovq(Assembler::equal, r, r12_heapbase);
5516 subq(r, r12_heapbase);
5517 shrq(r, LogMinObjAlignmentInBytes);
5518 }
5519
5520 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5521 #ifdef ASSERT
5522 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5523 if (CheckCompressedOops) {
5524 Label ok;
5525 testq(r, r);
5526 jcc(Assembler::notEqual, ok);
5527 STOP("null oop passed to encode_heap_oop_not_null");
5528 bind(ok);
5529 }
5530 #endif
5531 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5532 if (CompressedOops::base() != nullptr) {
5533 subq(r, r12_heapbase);
5534 }
5535 if (CompressedOops::shift() != 0) {
5536 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5537 shrq(r, LogMinObjAlignmentInBytes);
5538 }
5539 }
5540
5541 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5542 #ifdef ASSERT
5543 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5544 if (CheckCompressedOops) {
5545 Label ok;
5546 testq(src, src);
5547 jcc(Assembler::notEqual, ok);
5548 STOP("null oop passed to encode_heap_oop_not_null2");
5549 bind(ok);
5550 }
5551 #endif
5552 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5553 if (dst != src) {
5554 movq(dst, src);
5555 }
5556 if (CompressedOops::base() != nullptr) {
5557 subq(dst, r12_heapbase);
5558 }
5559 if (CompressedOops::shift() != 0) {
5560 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5561 shrq(dst, LogMinObjAlignmentInBytes);
5562 }
5563 }
5564
5565 void MacroAssembler::decode_heap_oop(Register r) {
5566 #ifdef ASSERT
5567 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5568 #endif
5569 if (CompressedOops::base() == nullptr) {
5570 if (CompressedOops::shift() != 0) {
5571 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5572 shlq(r, LogMinObjAlignmentInBytes);
5573 }
5574 } else {
5575 Label done;
5576 shlq(r, LogMinObjAlignmentInBytes);
5577 jccb(Assembler::equal, done);
5578 addq(r, r12_heapbase);
5579 bind(done);
5580 }
5581 verify_oop_msg(r, "broken oop in decode_heap_oop");
5582 }
5583
5584 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5585 // Note: it will change flags
5586 assert (UseCompressedOops, "should only be used for compressed headers");
5587 assert (Universe::heap() != nullptr, "java heap should be initialized");
5588 // Cannot assert, unverified entry point counts instructions (see .ad file)
5589 // vtableStubs also counts instructions in pd_code_size_limit.
5590 // Also do not verify_oop as this is called by verify_oop.
5591 if (CompressedOops::shift() != 0) {
5592 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5593 shlq(r, LogMinObjAlignmentInBytes);
5594 if (CompressedOops::base() != nullptr) {
5595 addq(r, r12_heapbase);
5596 }
5597 } else {
5598 assert (CompressedOops::base() == nullptr, "sanity");
5599 }
5600 }
5601
5602 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5603 // Note: it will change flags
5604 assert (UseCompressedOops, "should only be used for compressed headers");
5605 assert (Universe::heap() != nullptr, "java heap should be initialized");
5606 // Cannot assert, unverified entry point counts instructions (see .ad file)
5607 // vtableStubs also counts instructions in pd_code_size_limit.
5608 // Also do not verify_oop as this is called by verify_oop.
5609 if (CompressedOops::shift() != 0) {
5610 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5611 if (LogMinObjAlignmentInBytes == Address::times_8) {
5612 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5613 } else {
5614 if (dst != src) {
5615 movq(dst, src);
5616 }
5617 shlq(dst, LogMinObjAlignmentInBytes);
5618 if (CompressedOops::base() != nullptr) {
5619 addq(dst, r12_heapbase);
5620 }
5621 }
5622 } else {
5623 assert (CompressedOops::base() == nullptr, "sanity");
5624 if (dst != src) {
5625 movq(dst, src);
5626 }
5627 }
5628 }
5629
5630 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
5631 BLOCK_COMMENT("encode_klass_not_null {");
5632 assert_different_registers(r, tmp);
5633 if (CompressedKlassPointers::base() != nullptr) {
5634 if (AOTCodeCache::is_on_for_dump()) {
5635 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5636 } else {
5637 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5638 }
5639 subq(r, tmp);
5640 }
5641 if (CompressedKlassPointers::shift() != 0) {
5642 shrq(r, CompressedKlassPointers::shift());
5643 }
5644 BLOCK_COMMENT("} encode_klass_not_null");
5645 }
5646
5647 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
5648 BLOCK_COMMENT("encode_and_move_klass_not_null {");
5649 assert_different_registers(src, dst);
5650 if (CompressedKlassPointers::base() != nullptr) {
5651 if (AOTCodeCache::is_on_for_dump()) {
5652 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5653 negq(dst);
5654 } else {
5655 movptr(dst, -(intptr_t)CompressedKlassPointers::base());
5656 }
5657 addq(dst, src);
5658 } else {
5659 movptr(dst, src);
5660 }
5661 if (CompressedKlassPointers::shift() != 0) {
5662 shrq(dst, CompressedKlassPointers::shift());
5663 }
5664 BLOCK_COMMENT("} encode_and_move_klass_not_null");
5665 }
5666
5667 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
5668 BLOCK_COMMENT("decode_klass_not_null {");
5669 assert_different_registers(r, tmp);
5670 // Note: it will change flags
5671 assert(UseCompressedClassPointers, "should only be used for compressed headers");
5672 // Cannot assert, unverified entry point counts instructions (see .ad file)
5673 // vtableStubs also counts instructions in pd_code_size_limit.
5674 // Also do not verify_oop as this is called by verify_oop.
5675 if (CompressedKlassPointers::shift() != 0) {
5676 shlq(r, CompressedKlassPointers::shift());
5677 }
5678 if (CompressedKlassPointers::base() != nullptr) {
5679 if (AOTCodeCache::is_on_for_dump()) {
5680 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5681 } else {
5682 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5683 }
5684 addq(r, tmp);
5685 }
5686 BLOCK_COMMENT("} decode_klass_not_null");
5687 }
5688
5689 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
5690 BLOCK_COMMENT("decode_and_move_klass_not_null {");
5691 assert_different_registers(src, dst);
5692 // Note: it will change flags
5693 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5694 // Cannot assert, unverified entry point counts instructions (see .ad file)
5695 // vtableStubs also counts instructions in pd_code_size_limit.
5696 // Also do not verify_oop as this is called by verify_oop.
5697
5698 if (CompressedKlassPointers::base() == nullptr &&
5699 CompressedKlassPointers::shift() == 0) {
5700 // The best case scenario is that there is no base or shift. Then it is already
5701 // a pointer that needs nothing but a register rename.
5702 movptr(dst, src);
5703 } else {
5704 if (CompressedKlassPointers::shift() <= Address::times_8) {
5705 if (CompressedKlassPointers::base() != nullptr) {
5706 if (AOTCodeCache::is_on_for_dump()) {
5707 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5708 } else {
5709 movptr(dst, (intptr_t)CompressedKlassPointers::base());
5710 }
5711 } else {
5712 xorq(dst, dst);
5713 }
5714 if (CompressedKlassPointers::shift() != 0) {
5715 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
5716 leaq(dst, Address(dst, src, Address::times_8, 0));
5717 } else {
5718 addq(dst, src);
5719 }
5720 } else {
5721 if (CompressedKlassPointers::base() != nullptr) {
5722 if (AOTCodeCache::is_on_for_dump()) {
5723 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5724 shrq(dst, CompressedKlassPointers::shift());
5725 } else {
5726 const intptr_t base_right_shifted =
5727 (intptr_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5728 movptr(dst, base_right_shifted);
5729 }
5730 } else {
5731 xorq(dst, dst);
5732 }
5733 addq(dst, src);
5734 shlq(dst, CompressedKlassPointers::shift());
5735 }
5736 }
5737 BLOCK_COMMENT("} decode_and_move_klass_not_null");
5738 }
5739
5740 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5741 assert (UseCompressedOops, "should only be used for compressed headers");
5742 assert (Universe::heap() != nullptr, "java heap should be initialized");
5743 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5744 int oop_index = oop_recorder()->find_index(obj);
5745 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5746 mov_narrow_oop(dst, oop_index, rspec);
5747 }
5748
5749 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5750 assert (UseCompressedOops, "should only be used for compressed headers");
5751 assert (Universe::heap() != nullptr, "java heap should be initialized");
5752 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5753 int oop_index = oop_recorder()->find_index(obj);
5754 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5755 mov_narrow_oop(dst, oop_index, rspec);
5756 }
5757
5758 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5759 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5760 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5761 int klass_index = oop_recorder()->find_index(k);
5762 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5763 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5764 }
5765
5766 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5767 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5768 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5769 int klass_index = oop_recorder()->find_index(k);
5770 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5771 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5772 }
5773
5774 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5775 assert (UseCompressedOops, "should only be used for compressed headers");
5776 assert (Universe::heap() != nullptr, "java heap should be initialized");
5777 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5778 int oop_index = oop_recorder()->find_index(obj);
5779 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5780 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5781 }
5782
5783 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5784 assert (UseCompressedOops, "should only be used for compressed headers");
5785 assert (Universe::heap() != nullptr, "java heap should be initialized");
5786 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5787 int oop_index = oop_recorder()->find_index(obj);
5788 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5789 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5790 }
5791
5792 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5793 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5794 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5795 int klass_index = oop_recorder()->find_index(k);
5796 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5797 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5798 }
5799
5800 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5801 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5802 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5803 int klass_index = oop_recorder()->find_index(k);
5804 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5805 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5806 }
5807
5808 void MacroAssembler::reinit_heapbase() {
5809 if (UseCompressedOops) {
5810 if (Universe::heap() != nullptr) { // GC was initialized
5811 if (CompressedOops::base() == nullptr) {
5812 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5813 } else if (AOTCodeCache::is_on_for_dump()) {
5814 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
5815 } else {
5816 mov64(r12_heapbase, (int64_t)CompressedOops::base());
5817 }
5818 } else {
5819 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
5820 }
5821 }
5822 }
5823
5824 #if COMPILER2_OR_JVMCI
5825
5826 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
5827 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5828 // cnt - number of qwords (8-byte words).
5829 // base - start address, qword aligned.
5830 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5831 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
5832 if (use64byteVector) {
5833 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
5834 } else if (MaxVectorSize >= 32) {
5835 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5836 } else {
5837 pxor(xtmp, xtmp);
5838 }
5839 jmp(L_zero_64_bytes);
5840
5841 BIND(L_loop);
5842 if (MaxVectorSize >= 32) {
5843 fill64(base, 0, xtmp, use64byteVector);
5844 } else {
5845 movdqu(Address(base, 0), xtmp);
5846 movdqu(Address(base, 16), xtmp);
5847 movdqu(Address(base, 32), xtmp);
5848 movdqu(Address(base, 48), xtmp);
5849 }
5850 addptr(base, 64);
5851
5852 BIND(L_zero_64_bytes);
5853 subptr(cnt, 8);
5854 jccb(Assembler::greaterEqual, L_loop);
5855
5856 // Copy trailing 64 bytes
5857 if (use64byteVector) {
5858 addptr(cnt, 8);
5859 jccb(Assembler::equal, L_end);
5860 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
5861 jmp(L_end);
5862 } else {
5863 addptr(cnt, 4);
5864 jccb(Assembler::less, L_tail);
5865 if (MaxVectorSize >= 32) {
5866 vmovdqu(Address(base, 0), xtmp);
5867 } else {
5868 movdqu(Address(base, 0), xtmp);
5869 movdqu(Address(base, 16), xtmp);
5870 }
5871 }
5872 addptr(base, 32);
5873 subptr(cnt, 4);
5874
5875 BIND(L_tail);
5876 addptr(cnt, 4);
5877 jccb(Assembler::lessEqual, L_end);
5878 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
5879 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
5880 } else {
5881 decrement(cnt);
5882
5883 BIND(L_sloop);
5884 movq(Address(base, 0), xtmp);
5885 addptr(base, 8);
5886 decrement(cnt);
5887 jccb(Assembler::greaterEqual, L_sloop);
5888 }
5889 BIND(L_end);
5890 }
5891
5892 // Clearing constant sized memory using YMM/ZMM registers.
5893 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5894 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
5895 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
5896
5897 int vector64_count = (cnt & (~0x7)) >> 3;
5898 cnt = cnt & 0x7;
5899 const int fill64_per_loop = 4;
5900 const int max_unrolled_fill64 = 8;
5901
5902 // 64 byte initialization loop.
5903 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
5904 int start64 = 0;
5905 if (vector64_count > max_unrolled_fill64) {
5906 Label LOOP;
5907 Register index = rtmp;
5908
5909 start64 = vector64_count - (vector64_count % fill64_per_loop);
5910
5911 movl(index, 0);
5912 BIND(LOOP);
5913 for (int i = 0; i < fill64_per_loop; i++) {
5914 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
5915 }
5916 addl(index, fill64_per_loop * 64);
5917 cmpl(index, start64 * 64);
5918 jccb(Assembler::less, LOOP);
5919 }
5920 for (int i = start64; i < vector64_count; i++) {
5921 fill64(base, i * 64, xtmp, use64byteVector);
5922 }
5923
5924 // Clear remaining 64 byte tail.
5925 int disp = vector64_count * 64;
5926 if (cnt) {
5927 switch (cnt) {
5928 case 1:
5929 movq(Address(base, disp), xtmp);
5930 break;
5931 case 2:
5932 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
5933 break;
5934 case 3:
5935 movl(rtmp, 0x7);
5936 kmovwl(mask, rtmp);
5937 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
5938 break;
5939 case 4:
5940 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
5941 break;
5942 case 5:
5943 if (use64byteVector) {
5944 movl(rtmp, 0x1F);
5945 kmovwl(mask, rtmp);
5946 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
5947 } else {
5948 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
5949 movq(Address(base, disp + 32), xtmp);
5950 }
5951 break;
5952 case 6:
5953 if (use64byteVector) {
5954 movl(rtmp, 0x3F);
5955 kmovwl(mask, rtmp);
5956 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
5957 } else {
5958 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
5959 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
5960 }
5961 break;
5962 case 7:
5963 if (use64byteVector) {
5964 movl(rtmp, 0x7F);
5965 kmovwl(mask, rtmp);
5966 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
5967 } else {
5968 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
5969 movl(rtmp, 0x7);
5970 kmovwl(mask, rtmp);
5971 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
5972 }
5973 break;
5974 default:
5975 fatal("Unexpected length : %d\n",cnt);
5976 break;
5977 }
5978 }
5979 }
5980
5981 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
5982 bool is_large, KRegister mask) {
5983 // cnt - number of qwords (8-byte words).
5984 // base - start address, qword aligned.
5985 // is_large - if optimizers know cnt is larger than InitArrayShortSize
5986 assert(base==rdi, "base register must be edi for rep stos");
5987 assert(tmp==rax, "tmp register must be eax for rep stos");
5988 assert(cnt==rcx, "cnt register must be ecx for rep stos");
5989 assert(InitArrayShortSize % BytesPerLong == 0,
5990 "InitArrayShortSize should be the multiple of BytesPerLong");
5991
5992 Label DONE;
5993 if (!is_large || !UseXMMForObjInit) {
5994 xorptr(tmp, tmp);
5995 }
5996
5997 if (!is_large) {
5998 Label LOOP, LONG;
5999 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6000 jccb(Assembler::greater, LONG);
6001
6002 decrement(cnt);
6003 jccb(Assembler::negative, DONE); // Zero length
6004
6005 // Use individual pointer-sized stores for small counts:
6006 BIND(LOOP);
6007 movptr(Address(base, cnt, Address::times_ptr), tmp);
6008 decrement(cnt);
6009 jccb(Assembler::greaterEqual, LOOP);
6010 jmpb(DONE);
6011
6012 BIND(LONG);
6013 }
6014
6015 // Use longer rep-prefixed ops for non-small counts:
6016 if (UseFastStosb) {
6017 shlptr(cnt, 3); // convert to number of bytes
6018 rep_stosb();
6019 } else if (UseXMMForObjInit) {
6020 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
6021 } else {
6022 rep_stos();
6023 }
6024
6025 BIND(DONE);
6026 }
6027
6028 #endif //COMPILER2_OR_JVMCI
6029
6030
6031 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6032 Register to, Register value, Register count,
6033 Register rtmp, XMMRegister xtmp) {
6034 ShortBranchVerifier sbv(this);
6035 assert_different_registers(to, value, count, rtmp);
6036 Label L_exit;
6037 Label L_fill_2_bytes, L_fill_4_bytes;
6038
6039 #if defined(COMPILER2)
6040 if(MaxVectorSize >=32 &&
6041 VM_Version::supports_avx512vlbw() &&
6042 VM_Version::supports_bmi2()) {
6043 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6044 return;
6045 }
6046 #endif
6047
6048 int shift = -1;
6049 switch (t) {
6050 case T_BYTE:
6051 shift = 2;
6052 break;
6053 case T_SHORT:
6054 shift = 1;
6055 break;
6056 case T_INT:
6057 shift = 0;
6058 break;
6059 default: ShouldNotReachHere();
6060 }
6061
6062 if (t == T_BYTE) {
6063 andl(value, 0xff);
6064 movl(rtmp, value);
6065 shll(rtmp, 8);
6066 orl(value, rtmp);
6067 }
6068 if (t == T_SHORT) {
6069 andl(value, 0xffff);
6070 }
6071 if (t == T_BYTE || t == T_SHORT) {
6072 movl(rtmp, value);
6073 shll(rtmp, 16);
6074 orl(value, rtmp);
6075 }
6076
6077 cmpptr(count, 8 << shift); // Short arrays (< 32 bytes) fill by element
6078 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6079 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6080 Label L_skip_align2;
6081 // align source address at 4 bytes address boundary
6082 if (t == T_BYTE) {
6083 Label L_skip_align1;
6084 // One byte misalignment happens only for byte arrays
6085 testptr(to, 1);
6086 jccb(Assembler::zero, L_skip_align1);
6087 movb(Address(to, 0), value);
6088 increment(to);
6089 decrement(count);
6090 BIND(L_skip_align1);
6091 }
6092 // Two bytes misalignment happens only for byte and short (char) arrays
6093 testptr(to, 2);
6094 jccb(Assembler::zero, L_skip_align2);
6095 movw(Address(to, 0), value);
6096 addptr(to, 2);
6097 subptr(count, 1<<(shift-1));
6098 BIND(L_skip_align2);
6099 }
6100 {
6101 Label L_fill_32_bytes;
6102 if (!UseUnalignedLoadStores) {
6103 // align to 8 bytes, we know we are 4 byte aligned to start
6104 testptr(to, 4);
6105 jccb(Assembler::zero, L_fill_32_bytes);
6106 movl(Address(to, 0), value);
6107 addptr(to, 4);
6108 subptr(count, 1<<shift);
6109 }
6110 BIND(L_fill_32_bytes);
6111 {
6112 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6113 movdl(xtmp, value);
6114 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6115 Label L_check_fill_32_bytes;
6116 if (UseAVX > 2) {
6117 // Fill 64-byte chunks
6118 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6119
6120 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
6121 cmpptr(count, VM_Version::avx3_threshold());
6122 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6123
6124 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6125
6126 subptr(count, 16 << shift);
6127 jcc(Assembler::less, L_check_fill_32_bytes);
6128 align(16);
6129
6130 BIND(L_fill_64_bytes_loop_avx3);
6131 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6132 addptr(to, 64);
6133 subptr(count, 16 << shift);
6134 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6135 jmpb(L_check_fill_32_bytes);
6136
6137 BIND(L_check_fill_64_bytes_avx2);
6138 }
6139 // Fill 64-byte chunks
6140 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6141
6142 subptr(count, 16 << shift);
6143 jcc(Assembler::less, L_check_fill_32_bytes);
6144
6145 // align data for 64-byte chunks
6146 Label L_fill_64_bytes_loop, L_align_64_bytes_loop;
6147 if (EnableX86ECoreOpts) {
6148 // align 'big' arrays to cache lines to minimize split_stores
6149 cmpptr(count, 96 << shift);
6150 jcc(Assembler::below, L_fill_64_bytes_loop);
6151
6152 // Find the bytes needed for alignment
6153 movptr(rtmp, to);
6154 andptr(rtmp, 0x1c);
6155 jcc(Assembler::zero, L_fill_64_bytes_loop);
6156 negptr(rtmp); // number of bytes to fill 32-rtmp. it filled by 2 mov by 32
6157 addptr(rtmp, 32);
6158 shrptr(rtmp, 2 - shift);// get number of elements from bytes
6159 subptr(count, rtmp); // adjust count by number of elements
6160
6161 align(16);
6162 BIND(L_align_64_bytes_loop);
6163 movdl(Address(to, 0), xtmp);
6164 addptr(to, 4);
6165 subptr(rtmp, 1 << shift);
6166 jcc(Assembler::greater, L_align_64_bytes_loop);
6167 }
6168
6169 align(16);
6170 BIND(L_fill_64_bytes_loop);
6171 vmovdqu(Address(to, 0), xtmp);
6172 vmovdqu(Address(to, 32), xtmp);
6173 addptr(to, 64);
6174 subptr(count, 16 << shift);
6175 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6176
6177 align(16);
6178 BIND(L_check_fill_32_bytes);
6179 addptr(count, 8 << shift);
6180 jccb(Assembler::less, L_check_fill_8_bytes);
6181 vmovdqu(Address(to, 0), xtmp);
6182 addptr(to, 32);
6183 subptr(count, 8 << shift);
6184
6185 BIND(L_check_fill_8_bytes);
6186 // clean upper bits of YMM registers
6187 movdl(xtmp, value);
6188 pshufd(xtmp, xtmp, 0);
6189 } else {
6190 // Fill 32-byte chunks
6191 pshufd(xtmp, xtmp, 0);
6192
6193 subptr(count, 8 << shift);
6194 jcc(Assembler::less, L_check_fill_8_bytes);
6195 align(16);
6196
6197 BIND(L_fill_32_bytes_loop);
6198
6199 if (UseUnalignedLoadStores) {
6200 movdqu(Address(to, 0), xtmp);
6201 movdqu(Address(to, 16), xtmp);
6202 } else {
6203 movq(Address(to, 0), xtmp);
6204 movq(Address(to, 8), xtmp);
6205 movq(Address(to, 16), xtmp);
6206 movq(Address(to, 24), xtmp);
6207 }
6208
6209 addptr(to, 32);
6210 subptr(count, 8 << shift);
6211 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6212
6213 BIND(L_check_fill_8_bytes);
6214 }
6215 addptr(count, 8 << shift);
6216 jccb(Assembler::zero, L_exit);
6217 jmpb(L_fill_8_bytes);
6218
6219 //
6220 // length is too short, just fill qwords
6221 //
6222 align(16);
6223 BIND(L_fill_8_bytes_loop);
6224 movq(Address(to, 0), xtmp);
6225 addptr(to, 8);
6226 BIND(L_fill_8_bytes);
6227 subptr(count, 1 << (shift + 1));
6228 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6229 }
6230 }
6231
6232 Label L_fill_4_bytes_loop;
6233 testl(count, 1 << shift);
6234 jccb(Assembler::zero, L_fill_2_bytes);
6235
6236 align(16);
6237 BIND(L_fill_4_bytes_loop);
6238 movl(Address(to, 0), value);
6239 addptr(to, 4);
6240
6241 BIND(L_fill_4_bytes);
6242 subptr(count, 1 << shift);
6243 jccb(Assembler::greaterEqual, L_fill_4_bytes_loop);
6244
6245 if (t == T_BYTE || t == T_SHORT) {
6246 Label L_fill_byte;
6247 BIND(L_fill_2_bytes);
6248 // fill trailing 2 bytes
6249 testl(count, 1<<(shift-1));
6250 jccb(Assembler::zero, L_fill_byte);
6251 movw(Address(to, 0), value);
6252 if (t == T_BYTE) {
6253 addptr(to, 2);
6254 BIND(L_fill_byte);
6255 // fill trailing byte
6256 testl(count, 1);
6257 jccb(Assembler::zero, L_exit);
6258 movb(Address(to, 0), value);
6259 } else {
6260 BIND(L_fill_byte);
6261 }
6262 } else {
6263 BIND(L_fill_2_bytes);
6264 }
6265 BIND(L_exit);
6266 }
6267
6268 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6269 switch(type) {
6270 case T_BYTE:
6271 case T_BOOLEAN:
6272 evpbroadcastb(dst, src, vector_len);
6273 break;
6274 case T_SHORT:
6275 case T_CHAR:
6276 evpbroadcastw(dst, src, vector_len);
6277 break;
6278 case T_INT:
6279 case T_FLOAT:
6280 evpbroadcastd(dst, src, vector_len);
6281 break;
6282 case T_LONG:
6283 case T_DOUBLE:
6284 evpbroadcastq(dst, src, vector_len);
6285 break;
6286 default:
6287 fatal("Unhandled type : %s", type2name(type));
6288 break;
6289 }
6290 }
6291
6292 // Encode given char[]/byte[] to byte[] in ISO_8859_1 or ASCII
6293 //
6294 // @IntrinsicCandidate
6295 // int sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(
6296 // char[] sa, int sp, byte[] da, int dp, int len) {
6297 // int i = 0;
6298 // for (; i < len; i++) {
6299 // char c = sa[sp++];
6300 // if (c > '\u00FF')
6301 // break;
6302 // da[dp++] = (byte) c;
6303 // }
6304 // return i;
6305 // }
6306 //
6307 // @IntrinsicCandidate
6308 // int java.lang.StringCoding.encodeISOArray0(
6309 // byte[] sa, int sp, byte[] da, int dp, int len) {
6310 // int i = 0;
6311 // for (; i < len; i++) {
6312 // char c = StringUTF16.getChar(sa, sp++);
6313 // if (c > '\u00FF')
6314 // break;
6315 // da[dp++] = (byte) c;
6316 // }
6317 // return i;
6318 // }
6319 //
6320 // @IntrinsicCandidate
6321 // int java.lang.StringCoding.encodeAsciiArray0(
6322 // char[] sa, int sp, byte[] da, int dp, int len) {
6323 // int i = 0;
6324 // for (; i < len; i++) {
6325 // char c = sa[sp++];
6326 // if (c >= '\u0080')
6327 // break;
6328 // da[dp++] = (byte) c;
6329 // }
6330 // return i;
6331 // }
6332 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6333 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6334 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6335 Register tmp5, Register result, bool ascii) {
6336
6337 // rsi: src
6338 // rdi: dst
6339 // rdx: len
6340 // rcx: tmp5
6341 // rax: result
6342 ShortBranchVerifier sbv(this);
6343 assert_different_registers(src, dst, len, tmp5, result);
6344 Label L_done, L_copy_1_char, L_copy_1_char_exit;
6345
6346 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
6347 int short_mask = ascii ? 0xff80 : 0xff00;
6348
6349 // set result
6350 xorl(result, result);
6351 // check for zero length
6352 testl(len, len);
6353 jcc(Assembler::zero, L_done);
6354
6355 movl(result, len);
6356
6357 // Setup pointers
6358 lea(src, Address(src, len, Address::times_2)); // char[]
6359 lea(dst, Address(dst, len, Address::times_1)); // byte[]
6360 negptr(len);
6361
6362 if (UseSSE42Intrinsics || UseAVX >= 2) {
6363 Label L_copy_8_chars, L_copy_8_chars_exit;
6364 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
6365
6366 if (UseAVX >= 2) {
6367 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
6368 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6369 movdl(tmp1Reg, tmp5);
6370 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
6371 jmp(L_chars_32_check);
6372
6373 bind(L_copy_32_chars);
6374 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
6375 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
6376 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6377 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6378 jccb(Assembler::notZero, L_copy_32_chars_exit);
6379 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6380 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
6381 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
6382
6383 bind(L_chars_32_check);
6384 addptr(len, 32);
6385 jcc(Assembler::lessEqual, L_copy_32_chars);
6386
6387 bind(L_copy_32_chars_exit);
6388 subptr(len, 16);
6389 jccb(Assembler::greater, L_copy_16_chars_exit);
6390
6391 } else if (UseSSE42Intrinsics) {
6392 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6393 movdl(tmp1Reg, tmp5);
6394 pshufd(tmp1Reg, tmp1Reg, 0);
6395 jmpb(L_chars_16_check);
6396 }
6397
6398 bind(L_copy_16_chars);
6399 if (UseAVX >= 2) {
6400 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
6401 vptest(tmp2Reg, tmp1Reg);
6402 jcc(Assembler::notZero, L_copy_16_chars_exit);
6403 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
6404 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
6405 } else {
6406 if (UseAVX > 0) {
6407 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6408 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6409 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
6410 } else {
6411 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6412 por(tmp2Reg, tmp3Reg);
6413 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6414 por(tmp2Reg, tmp4Reg);
6415 }
6416 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6417 jccb(Assembler::notZero, L_copy_16_chars_exit);
6418 packuswb(tmp3Reg, tmp4Reg);
6419 }
6420 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
6421
6422 bind(L_chars_16_check);
6423 addptr(len, 16);
6424 jcc(Assembler::lessEqual, L_copy_16_chars);
6425
6426 bind(L_copy_16_chars_exit);
6427 if (UseAVX >= 2) {
6428 // clean upper bits of YMM registers
6429 vpxor(tmp2Reg, tmp2Reg);
6430 vpxor(tmp3Reg, tmp3Reg);
6431 vpxor(tmp4Reg, tmp4Reg);
6432 movdl(tmp1Reg, tmp5);
6433 pshufd(tmp1Reg, tmp1Reg, 0);
6434 }
6435 subptr(len, 8);
6436 jccb(Assembler::greater, L_copy_8_chars_exit);
6437
6438 bind(L_copy_8_chars);
6439 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
6440 ptest(tmp3Reg, tmp1Reg);
6441 jccb(Assembler::notZero, L_copy_8_chars_exit);
6442 packuswb(tmp3Reg, tmp1Reg);
6443 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
6444 addptr(len, 8);
6445 jccb(Assembler::lessEqual, L_copy_8_chars);
6446
6447 bind(L_copy_8_chars_exit);
6448 subptr(len, 8);
6449 jccb(Assembler::zero, L_done);
6450 }
6451
6452 bind(L_copy_1_char);
6453 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
6454 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
6455 jccb(Assembler::notZero, L_copy_1_char_exit);
6456 movb(Address(dst, len, Address::times_1, 0), tmp5);
6457 addptr(len, 1);
6458 jccb(Assembler::less, L_copy_1_char);
6459
6460 bind(L_copy_1_char_exit);
6461 addptr(result, len); // len is negative count of not processed elements
6462
6463 bind(L_done);
6464 }
6465
6466 /**
6467 * Helper for multiply_to_len().
6468 */
6469 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
6470 addq(dest_lo, src1);
6471 adcq(dest_hi, 0);
6472 addq(dest_lo, src2);
6473 adcq(dest_hi, 0);
6474 }
6475
6476 /**
6477 * Multiply 64 bit by 64 bit first loop.
6478 */
6479 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
6480 Register y, Register y_idx, Register z,
6481 Register carry, Register product,
6482 Register idx, Register kdx) {
6483 //
6484 // jlong carry, x[], y[], z[];
6485 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6486 // huge_128 product = y[idx] * x[xstart] + carry;
6487 // z[kdx] = (jlong)product;
6488 // carry = (jlong)(product >>> 64);
6489 // }
6490 // z[xstart] = carry;
6491 //
6492
6493 Label L_first_loop, L_first_loop_exit;
6494 Label L_one_x, L_one_y, L_multiply;
6495
6496 decrementl(xstart);
6497 jcc(Assembler::negative, L_one_x);
6498
6499 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
6500 rorq(x_xstart, 32); // convert big-endian to little-endian
6501
6502 bind(L_first_loop);
6503 decrementl(idx);
6504 jcc(Assembler::negative, L_first_loop_exit);
6505 decrementl(idx);
6506 jcc(Assembler::negative, L_one_y);
6507 movq(y_idx, Address(y, idx, Address::times_4, 0));
6508 rorq(y_idx, 32); // convert big-endian to little-endian
6509 bind(L_multiply);
6510 movq(product, x_xstart);
6511 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
6512 addq(product, carry);
6513 adcq(rdx, 0);
6514 subl(kdx, 2);
6515 movl(Address(z, kdx, Address::times_4, 4), product);
6516 shrq(product, 32);
6517 movl(Address(z, kdx, Address::times_4, 0), product);
6518 movq(carry, rdx);
6519 jmp(L_first_loop);
6520
6521 bind(L_one_y);
6522 movl(y_idx, Address(y, 0));
6523 jmp(L_multiply);
6524
6525 bind(L_one_x);
6526 movl(x_xstart, Address(x, 0));
6527 jmp(L_first_loop);
6528
6529 bind(L_first_loop_exit);
6530 }
6531
6532 /**
6533 * Multiply 64 bit by 64 bit and add 128 bit.
6534 */
6535 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
6536 Register yz_idx, Register idx,
6537 Register carry, Register product, int offset) {
6538 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
6539 // z[kdx] = (jlong)product;
6540
6541 movq(yz_idx, Address(y, idx, Address::times_4, offset));
6542 rorq(yz_idx, 32); // convert big-endian to little-endian
6543 movq(product, x_xstart);
6544 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
6545 movq(yz_idx, Address(z, idx, Address::times_4, offset));
6546 rorq(yz_idx, 32); // convert big-endian to little-endian
6547
6548 add2_with_carry(rdx, product, carry, yz_idx);
6549
6550 movl(Address(z, idx, Address::times_4, offset+4), product);
6551 shrq(product, 32);
6552 movl(Address(z, idx, Address::times_4, offset), product);
6553
6554 }
6555
6556 /**
6557 * Multiply 128 bit by 128 bit. Unrolled inner loop.
6558 */
6559 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
6560 Register yz_idx, Register idx, Register jdx,
6561 Register carry, Register product,
6562 Register carry2) {
6563 // jlong carry, x[], y[], z[];
6564 // int kdx = ystart+1;
6565 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6566 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
6567 // z[kdx+idx+1] = (jlong)product;
6568 // jlong carry2 = (jlong)(product >>> 64);
6569 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
6570 // z[kdx+idx] = (jlong)product;
6571 // carry = (jlong)(product >>> 64);
6572 // }
6573 // idx += 2;
6574 // if (idx > 0) {
6575 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
6576 // z[kdx+idx] = (jlong)product;
6577 // carry = (jlong)(product >>> 64);
6578 // }
6579 //
6580
6581 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6582
6583 movl(jdx, idx);
6584 andl(jdx, 0xFFFFFFFC);
6585 shrl(jdx, 2);
6586
6587 bind(L_third_loop);
6588 subl(jdx, 1);
6589 jcc(Assembler::negative, L_third_loop_exit);
6590 subl(idx, 4);
6591
6592 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
6593 movq(carry2, rdx);
6594
6595 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
6596 movq(carry, rdx);
6597 jmp(L_third_loop);
6598
6599 bind (L_third_loop_exit);
6600
6601 andl (idx, 0x3);
6602 jcc(Assembler::zero, L_post_third_loop_done);
6603
6604 Label L_check_1;
6605 subl(idx, 2);
6606 jcc(Assembler::negative, L_check_1);
6607
6608 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
6609 movq(carry, rdx);
6610
6611 bind (L_check_1);
6612 addl (idx, 0x2);
6613 andl (idx, 0x1);
6614 subl(idx, 1);
6615 jcc(Assembler::negative, L_post_third_loop_done);
6616
6617 movl(yz_idx, Address(y, idx, Address::times_4, 0));
6618 movq(product, x_xstart);
6619 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
6620 movl(yz_idx, Address(z, idx, Address::times_4, 0));
6621
6622 add2_with_carry(rdx, product, yz_idx, carry);
6623
6624 movl(Address(z, idx, Address::times_4, 0), product);
6625 shrq(product, 32);
6626
6627 shlq(rdx, 32);
6628 orq(product, rdx);
6629 movq(carry, product);
6630
6631 bind(L_post_third_loop_done);
6632 }
6633
6634 /**
6635 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
6636 *
6637 */
6638 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
6639 Register carry, Register carry2,
6640 Register idx, Register jdx,
6641 Register yz_idx1, Register yz_idx2,
6642 Register tmp, Register tmp3, Register tmp4) {
6643 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
6644
6645 // jlong carry, x[], y[], z[];
6646 // int kdx = ystart+1;
6647 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6648 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
6649 // jlong carry2 = (jlong)(tmp3 >>> 64);
6650 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
6651 // carry = (jlong)(tmp4 >>> 64);
6652 // z[kdx+idx+1] = (jlong)tmp3;
6653 // z[kdx+idx] = (jlong)tmp4;
6654 // }
6655 // idx += 2;
6656 // if (idx > 0) {
6657 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
6658 // z[kdx+idx] = (jlong)yz_idx1;
6659 // carry = (jlong)(yz_idx1 >>> 64);
6660 // }
6661 //
6662
6663 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6664
6665 movl(jdx, idx);
6666 andl(jdx, 0xFFFFFFFC);
6667 shrl(jdx, 2);
6668
6669 bind(L_third_loop);
6670 subl(jdx, 1);
6671 jcc(Assembler::negative, L_third_loop_exit);
6672 subl(idx, 4);
6673
6674 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
6675 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
6676 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
6677 rorxq(yz_idx2, yz_idx2, 32);
6678
6679 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
6680 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
6681
6682 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
6683 rorxq(yz_idx1, yz_idx1, 32);
6684 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
6685 rorxq(yz_idx2, yz_idx2, 32);
6686
6687 if (VM_Version::supports_adx()) {
6688 adcxq(tmp3, carry);
6689 adoxq(tmp3, yz_idx1);
6690
6691 adcxq(tmp4, tmp);
6692 adoxq(tmp4, yz_idx2);
6693
6694 movl(carry, 0); // does not affect flags
6695 adcxq(carry2, carry);
6696 adoxq(carry2, carry);
6697 } else {
6698 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
6699 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
6700 }
6701 movq(carry, carry2);
6702
6703 movl(Address(z, idx, Address::times_4, 12), tmp3);
6704 shrq(tmp3, 32);
6705 movl(Address(z, idx, Address::times_4, 8), tmp3);
6706
6707 movl(Address(z, idx, Address::times_4, 4), tmp4);
6708 shrq(tmp4, 32);
6709 movl(Address(z, idx, Address::times_4, 0), tmp4);
6710
6711 jmp(L_third_loop);
6712
6713 bind (L_third_loop_exit);
6714
6715 andl (idx, 0x3);
6716 jcc(Assembler::zero, L_post_third_loop_done);
6717
6718 Label L_check_1;
6719 subl(idx, 2);
6720 jcc(Assembler::negative, L_check_1);
6721
6722 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
6723 rorxq(yz_idx1, yz_idx1, 32);
6724 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
6725 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
6726 rorxq(yz_idx2, yz_idx2, 32);
6727
6728 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
6729
6730 movl(Address(z, idx, Address::times_4, 4), tmp3);
6731 shrq(tmp3, 32);
6732 movl(Address(z, idx, Address::times_4, 0), tmp3);
6733 movq(carry, tmp4);
6734
6735 bind (L_check_1);
6736 addl (idx, 0x2);
6737 andl (idx, 0x1);
6738 subl(idx, 1);
6739 jcc(Assembler::negative, L_post_third_loop_done);
6740 movl(tmp4, Address(y, idx, Address::times_4, 0));
6741 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
6742 movl(tmp4, Address(z, idx, Address::times_4, 0));
6743
6744 add2_with_carry(carry2, tmp3, tmp4, carry);
6745
6746 movl(Address(z, idx, Address::times_4, 0), tmp3);
6747 shrq(tmp3, 32);
6748
6749 shlq(carry2, 32);
6750 orq(tmp3, carry2);
6751 movq(carry, tmp3);
6752
6753 bind(L_post_third_loop_done);
6754 }
6755
6756 /**
6757 * Code for BigInteger::multiplyToLen() intrinsic.
6758 *
6759 * rdi: x
6760 * rax: xlen
6761 * rsi: y
6762 * rcx: ylen
6763 * r8: z
6764 * r11: tmp0
6765 * r12: tmp1
6766 * r13: tmp2
6767 * r14: tmp3
6768 * r15: tmp4
6769 * rbx: tmp5
6770 *
6771 */
6772 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
6773 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
6774 ShortBranchVerifier sbv(this);
6775 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
6776
6777 push(tmp0);
6778 push(tmp1);
6779 push(tmp2);
6780 push(tmp3);
6781 push(tmp4);
6782 push(tmp5);
6783
6784 push(xlen);
6785
6786 const Register idx = tmp1;
6787 const Register kdx = tmp2;
6788 const Register xstart = tmp3;
6789
6790 const Register y_idx = tmp4;
6791 const Register carry = tmp5;
6792 const Register product = xlen;
6793 const Register x_xstart = tmp0;
6794
6795 // First Loop.
6796 //
6797 // final static long LONG_MASK = 0xffffffffL;
6798 // int xstart = xlen - 1;
6799 // int ystart = ylen - 1;
6800 // long carry = 0;
6801 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6802 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
6803 // z[kdx] = (int)product;
6804 // carry = product >>> 32;
6805 // }
6806 // z[xstart] = (int)carry;
6807 //
6808
6809 movl(idx, ylen); // idx = ylen;
6810 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
6811 xorq(carry, carry); // carry = 0;
6812
6813 Label L_done;
6814
6815 movl(xstart, xlen);
6816 decrementl(xstart);
6817 jcc(Assembler::negative, L_done);
6818
6819 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
6820
6821 Label L_second_loop;
6822 testl(kdx, kdx);
6823 jcc(Assembler::zero, L_second_loop);
6824
6825 Label L_carry;
6826 subl(kdx, 1);
6827 jcc(Assembler::zero, L_carry);
6828
6829 movl(Address(z, kdx, Address::times_4, 0), carry);
6830 shrq(carry, 32);
6831 subl(kdx, 1);
6832
6833 bind(L_carry);
6834 movl(Address(z, kdx, Address::times_4, 0), carry);
6835
6836 // Second and third (nested) loops.
6837 //
6838 // for (int i = xstart-1; i >= 0; i--) { // Second loop
6839 // carry = 0;
6840 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
6841 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
6842 // (z[k] & LONG_MASK) + carry;
6843 // z[k] = (int)product;
6844 // carry = product >>> 32;
6845 // }
6846 // z[i] = (int)carry;
6847 // }
6848 //
6849 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
6850
6851 const Register jdx = tmp1;
6852
6853 bind(L_second_loop);
6854 xorl(carry, carry); // carry = 0;
6855 movl(jdx, ylen); // j = ystart+1
6856
6857 subl(xstart, 1); // i = xstart-1;
6858 jcc(Assembler::negative, L_done);
6859
6860 push (z);
6861
6862 Label L_last_x;
6863 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
6864 subl(xstart, 1); // i = xstart-1;
6865 jcc(Assembler::negative, L_last_x);
6866
6867 if (UseBMI2Instructions) {
6868 movq(rdx, Address(x, xstart, Address::times_4, 0));
6869 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
6870 } else {
6871 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
6872 rorq(x_xstart, 32); // convert big-endian to little-endian
6873 }
6874
6875 Label L_third_loop_prologue;
6876 bind(L_third_loop_prologue);
6877
6878 push (x);
6879 push (xstart);
6880 push (ylen);
6881
6882
6883 if (UseBMI2Instructions) {
6884 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
6885 } else { // !UseBMI2Instructions
6886 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
6887 }
6888
6889 pop(ylen);
6890 pop(xlen);
6891 pop(x);
6892 pop(z);
6893
6894 movl(tmp3, xlen);
6895 addl(tmp3, 1);
6896 movl(Address(z, tmp3, Address::times_4, 0), carry);
6897 subl(tmp3, 1);
6898 jccb(Assembler::negative, L_done);
6899
6900 shrq(carry, 32);
6901 movl(Address(z, tmp3, Address::times_4, 0), carry);
6902 jmp(L_second_loop);
6903
6904 // Next infrequent code is moved outside loops.
6905 bind(L_last_x);
6906 if (UseBMI2Instructions) {
6907 movl(rdx, Address(x, 0));
6908 } else {
6909 movl(x_xstart, Address(x, 0));
6910 }
6911 jmp(L_third_loop_prologue);
6912
6913 bind(L_done);
6914
6915 pop(xlen);
6916
6917 pop(tmp5);
6918 pop(tmp4);
6919 pop(tmp3);
6920 pop(tmp2);
6921 pop(tmp1);
6922 pop(tmp0);
6923 }
6924
6925 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
6926 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
6927 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
6928 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
6929 Label VECTOR8_TAIL, VECTOR4_TAIL;
6930 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
6931 Label SAME_TILL_END, DONE;
6932 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
6933
6934 //scale is in rcx in both Win64 and Unix
6935 ShortBranchVerifier sbv(this);
6936
6937 shlq(length);
6938 xorq(result, result);
6939
6940 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
6941 VM_Version::supports_avx512vlbw()) {
6942 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
6943
6944 cmpq(length, 64);
6945 jcc(Assembler::less, VECTOR32_TAIL);
6946
6947 movq(tmp1, length);
6948 andq(tmp1, 0x3F); // tail count
6949 andq(length, ~(0x3F)); //vector count
6950
6951 bind(VECTOR64_LOOP);
6952 // AVX512 code to compare 64 byte vectors.
6953 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
6954 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
6955 kortestql(k7, k7);
6956 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
6957 addq(result, 64);
6958 subq(length, 64);
6959 jccb(Assembler::notZero, VECTOR64_LOOP);
6960
6961 //bind(VECTOR64_TAIL);
6962 testq(tmp1, tmp1);
6963 jcc(Assembler::zero, SAME_TILL_END);
6964
6965 //bind(VECTOR64_TAIL);
6966 // AVX512 code to compare up to 63 byte vectors.
6967 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
6968 shlxq(tmp2, tmp2, tmp1);
6969 notq(tmp2);
6970 kmovql(k3, tmp2);
6971
6972 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
6973 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
6974
6975 ktestql(k7, k3);
6976 jcc(Assembler::below, SAME_TILL_END); // not mismatch
6977
6978 bind(VECTOR64_NOT_EQUAL);
6979 kmovql(tmp1, k7);
6980 notq(tmp1);
6981 tzcntq(tmp1, tmp1);
6982 addq(result, tmp1);
6983 shrq(result);
6984 jmp(DONE);
6985 bind(VECTOR32_TAIL);
6986 }
6987
6988 cmpq(length, 8);
6989 jcc(Assembler::equal, VECTOR8_LOOP);
6990 jcc(Assembler::less, VECTOR4_TAIL);
6991
6992 if (UseAVX >= 2) {
6993 Label VECTOR16_TAIL, VECTOR32_LOOP;
6994
6995 cmpq(length, 16);
6996 jcc(Assembler::equal, VECTOR16_LOOP);
6997 jcc(Assembler::less, VECTOR8_LOOP);
6998
6999 cmpq(length, 32);
7000 jccb(Assembler::less, VECTOR16_TAIL);
7001
7002 subq(length, 32);
7003 bind(VECTOR32_LOOP);
7004 vmovdqu(rymm0, Address(obja, result));
7005 vmovdqu(rymm1, Address(objb, result));
7006 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7007 vptest(rymm2, rymm2);
7008 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7009 addq(result, 32);
7010 subq(length, 32);
7011 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7012 addq(length, 32);
7013 jcc(Assembler::equal, SAME_TILL_END);
7014 //falling through if less than 32 bytes left //close the branch here.
7015
7016 bind(VECTOR16_TAIL);
7017 cmpq(length, 16);
7018 jccb(Assembler::less, VECTOR8_TAIL);
7019 bind(VECTOR16_LOOP);
7020 movdqu(rymm0, Address(obja, result));
7021 movdqu(rymm1, Address(objb, result));
7022 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7023 ptest(rymm2, rymm2);
7024 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7025 addq(result, 16);
7026 subq(length, 16);
7027 jcc(Assembler::equal, SAME_TILL_END);
7028 //falling through if less than 16 bytes left
7029 } else {//regular intrinsics
7030
7031 cmpq(length, 16);
7032 jccb(Assembler::less, VECTOR8_TAIL);
7033
7034 subq(length, 16);
7035 bind(VECTOR16_LOOP);
7036 movdqu(rymm0, Address(obja, result));
7037 movdqu(rymm1, Address(objb, result));
7038 pxor(rymm0, rymm1);
7039 ptest(rymm0, rymm0);
7040 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7041 addq(result, 16);
7042 subq(length, 16);
7043 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7044 addq(length, 16);
7045 jcc(Assembler::equal, SAME_TILL_END);
7046 //falling through if less than 16 bytes left
7047 }
7048
7049 bind(VECTOR8_TAIL);
7050 cmpq(length, 8);
7051 jccb(Assembler::less, VECTOR4_TAIL);
7052 bind(VECTOR8_LOOP);
7053 movq(tmp1, Address(obja, result));
7054 movq(tmp2, Address(objb, result));
7055 xorq(tmp1, tmp2);
7056 testq(tmp1, tmp1);
7057 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7058 addq(result, 8);
7059 subq(length, 8);
7060 jcc(Assembler::equal, SAME_TILL_END);
7061 //falling through if less than 8 bytes left
7062
7063 bind(VECTOR4_TAIL);
7064 cmpq(length, 4);
7065 jccb(Assembler::less, BYTES_TAIL);
7066 bind(VECTOR4_LOOP);
7067 movl(tmp1, Address(obja, result));
7068 xorl(tmp1, Address(objb, result));
7069 testl(tmp1, tmp1);
7070 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7071 addq(result, 4);
7072 subq(length, 4);
7073 jcc(Assembler::equal, SAME_TILL_END);
7074 //falling through if less than 4 bytes left
7075
7076 bind(BYTES_TAIL);
7077 bind(BYTES_LOOP);
7078 load_unsigned_byte(tmp1, Address(obja, result));
7079 load_unsigned_byte(tmp2, Address(objb, result));
7080 xorl(tmp1, tmp2);
7081 testl(tmp1, tmp1);
7082 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7083 decq(length);
7084 jcc(Assembler::zero, SAME_TILL_END);
7085 incq(result);
7086 load_unsigned_byte(tmp1, Address(obja, result));
7087 load_unsigned_byte(tmp2, Address(objb, result));
7088 xorl(tmp1, tmp2);
7089 testl(tmp1, tmp1);
7090 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7091 decq(length);
7092 jcc(Assembler::zero, SAME_TILL_END);
7093 incq(result);
7094 load_unsigned_byte(tmp1, Address(obja, result));
7095 load_unsigned_byte(tmp2, Address(objb, result));
7096 xorl(tmp1, tmp2);
7097 testl(tmp1, tmp1);
7098 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7099 jmp(SAME_TILL_END);
7100
7101 if (UseAVX >= 2) {
7102 bind(VECTOR32_NOT_EQUAL);
7103 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7104 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7105 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7106 vpmovmskb(tmp1, rymm0);
7107 bsfq(tmp1, tmp1);
7108 addq(result, tmp1);
7109 shrq(result);
7110 jmp(DONE);
7111 }
7112
7113 bind(VECTOR16_NOT_EQUAL);
7114 if (UseAVX >= 2) {
7115 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7116 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7117 pxor(rymm0, rymm2);
7118 } else {
7119 pcmpeqb(rymm2, rymm2);
7120 pxor(rymm0, rymm1);
7121 pcmpeqb(rymm0, rymm1);
7122 pxor(rymm0, rymm2);
7123 }
7124 pmovmskb(tmp1, rymm0);
7125 bsfq(tmp1, tmp1);
7126 addq(result, tmp1);
7127 shrq(result);
7128 jmpb(DONE);
7129
7130 bind(VECTOR8_NOT_EQUAL);
7131 bind(VECTOR4_NOT_EQUAL);
7132 bsfq(tmp1, tmp1);
7133 shrq(tmp1, 3);
7134 addq(result, tmp1);
7135 bind(BYTES_NOT_EQUAL);
7136 shrq(result);
7137 jmpb(DONE);
7138
7139 bind(SAME_TILL_END);
7140 mov64(result, -1);
7141
7142 bind(DONE);
7143 }
7144
7145 //Helper functions for square_to_len()
7146
7147 /**
7148 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7149 * Preserves x and z and modifies rest of the registers.
7150 */
7151 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7152 // Perform square and right shift by 1
7153 // Handle odd xlen case first, then for even xlen do the following
7154 // jlong carry = 0;
7155 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7156 // huge_128 product = x[j:j+1] * x[j:j+1];
7157 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7158 // z[i+2:i+3] = (jlong)(product >>> 1);
7159 // carry = (jlong)product;
7160 // }
7161
7162 xorq(tmp5, tmp5); // carry
7163 xorq(rdxReg, rdxReg);
7164 xorl(tmp1, tmp1); // index for x
7165 xorl(tmp4, tmp4); // index for z
7166
7167 Label L_first_loop, L_first_loop_exit;
7168
7169 testl(xlen, 1);
7170 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7171
7172 // Square and right shift by 1 the odd element using 32 bit multiply
7173 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7174 imulq(raxReg, raxReg);
7175 shrq(raxReg, 1);
7176 adcq(tmp5, 0);
7177 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7178 incrementl(tmp1);
7179 addl(tmp4, 2);
7180
7181 // Square and right shift by 1 the rest using 64 bit multiply
7182 bind(L_first_loop);
7183 cmpptr(tmp1, xlen);
7184 jccb(Assembler::equal, L_first_loop_exit);
7185
7186 // Square
7187 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7188 rorq(raxReg, 32); // convert big-endian to little-endian
7189 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7190
7191 // Right shift by 1 and save carry
7192 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7193 rcrq(rdxReg, 1);
7194 rcrq(raxReg, 1);
7195 adcq(tmp5, 0);
7196
7197 // Store result in z
7198 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7199 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7200
7201 // Update indices for x and z
7202 addl(tmp1, 2);
7203 addl(tmp4, 4);
7204 jmp(L_first_loop);
7205
7206 bind(L_first_loop_exit);
7207 }
7208
7209
7210 /**
7211 * Perform the following multiply add operation using BMI2 instructions
7212 * carry:sum = sum + op1*op2 + carry
7213 * op2 should be in rdx
7214 * op2 is preserved, all other registers are modified
7215 */
7216 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7217 // assert op2 is rdx
7218 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7219 addq(sum, carry);
7220 adcq(tmp2, 0);
7221 addq(sum, op1);
7222 adcq(tmp2, 0);
7223 movq(carry, tmp2);
7224 }
7225
7226 /**
7227 * Perform the following multiply add operation:
7228 * carry:sum = sum + op1*op2 + carry
7229 * Preserves op1, op2 and modifies rest of registers
7230 */
7231 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7232 // rdx:rax = op1 * op2
7233 movq(raxReg, op2);
7234 mulq(op1);
7235
7236 // rdx:rax = sum + carry + rdx:rax
7237 addq(sum, carry);
7238 adcq(rdxReg, 0);
7239 addq(sum, raxReg);
7240 adcq(rdxReg, 0);
7241
7242 // carry:sum = rdx:sum
7243 movq(carry, rdxReg);
7244 }
7245
7246 /**
7247 * Add 64 bit long carry into z[] with carry propagation.
7248 * Preserves z and carry register values and modifies rest of registers.
7249 *
7250 */
7251 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7252 Label L_fourth_loop, L_fourth_loop_exit;
7253
7254 movl(tmp1, 1);
7255 subl(zlen, 2);
7256 addq(Address(z, zlen, Address::times_4, 0), carry);
7257
7258 bind(L_fourth_loop);
7259 jccb(Assembler::carryClear, L_fourth_loop_exit);
7260 subl(zlen, 2);
7261 jccb(Assembler::negative, L_fourth_loop_exit);
7262 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7263 jmp(L_fourth_loop);
7264 bind(L_fourth_loop_exit);
7265 }
7266
7267 /**
7268 * Shift z[] left by 1 bit.
7269 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7270 *
7271 */
7272 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7273
7274 Label L_fifth_loop, L_fifth_loop_exit;
7275
7276 // Fifth loop
7277 // Perform primitiveLeftShift(z, zlen, 1)
7278
7279 const Register prev_carry = tmp1;
7280 const Register new_carry = tmp4;
7281 const Register value = tmp2;
7282 const Register zidx = tmp3;
7283
7284 // int zidx, carry;
7285 // long value;
7286 // carry = 0;
7287 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7288 // (carry:value) = (z[i] << 1) | carry ;
7289 // z[i] = value;
7290 // }
7291
7292 movl(zidx, zlen);
7293 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7294
7295 bind(L_fifth_loop);
7296 decl(zidx); // Use decl to preserve carry flag
7297 decl(zidx);
7298 jccb(Assembler::negative, L_fifth_loop_exit);
7299
7300 if (UseBMI2Instructions) {
7301 movq(value, Address(z, zidx, Address::times_4, 0));
7302 rclq(value, 1);
7303 rorxq(value, value, 32);
7304 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7305 }
7306 else {
7307 // clear new_carry
7308 xorl(new_carry, new_carry);
7309
7310 // Shift z[i] by 1, or in previous carry and save new carry
7311 movq(value, Address(z, zidx, Address::times_4, 0));
7312 shlq(value, 1);
7313 adcl(new_carry, 0);
7314
7315 orq(value, prev_carry);
7316 rorq(value, 0x20);
7317 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7318
7319 // Set previous carry = new carry
7320 movl(prev_carry, new_carry);
7321 }
7322 jmp(L_fifth_loop);
7323
7324 bind(L_fifth_loop_exit);
7325 }
7326
7327
7328 /**
7329 * Code for BigInteger::squareToLen() intrinsic
7330 *
7331 * rdi: x
7332 * rsi: len
7333 * r8: z
7334 * rcx: zlen
7335 * r12: tmp1
7336 * r13: tmp2
7337 * r14: tmp3
7338 * r15: tmp4
7339 * rbx: tmp5
7340 *
7341 */
7342 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7343
7344 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
7345 push(tmp1);
7346 push(tmp2);
7347 push(tmp3);
7348 push(tmp4);
7349 push(tmp5);
7350
7351 // First loop
7352 // Store the squares, right shifted one bit (i.e., divided by 2).
7353 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7354
7355 // Add in off-diagonal sums.
7356 //
7357 // Second, third (nested) and fourth loops.
7358 // zlen +=2;
7359 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7360 // carry = 0;
7361 // long op2 = x[xidx:xidx+1];
7362 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7363 // k -= 2;
7364 // long op1 = x[j:j+1];
7365 // long sum = z[k:k+1];
7366 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7367 // z[k:k+1] = sum;
7368 // }
7369 // add_one_64(z, k, carry, tmp_regs);
7370 // }
7371
7372 const Register carry = tmp5;
7373 const Register sum = tmp3;
7374 const Register op1 = tmp4;
7375 Register op2 = tmp2;
7376
7377 push(zlen);
7378 push(len);
7379 addl(zlen,2);
7380 bind(L_second_loop);
7381 xorq(carry, carry);
7382 subl(zlen, 4);
7383 subl(len, 2);
7384 push(zlen);
7385 push(len);
7386 cmpl(len, 0);
7387 jccb(Assembler::lessEqual, L_second_loop_exit);
7388
7389 // Multiply an array by one 64 bit long.
7390 if (UseBMI2Instructions) {
7391 op2 = rdxReg;
7392 movq(op2, Address(x, len, Address::times_4, 0));
7393 rorxq(op2, op2, 32);
7394 }
7395 else {
7396 movq(op2, Address(x, len, Address::times_4, 0));
7397 rorq(op2, 32);
7398 }
7399
7400 bind(L_third_loop);
7401 decrementl(len);
7402 jccb(Assembler::negative, L_third_loop_exit);
7403 decrementl(len);
7404 jccb(Assembler::negative, L_last_x);
7405
7406 movq(op1, Address(x, len, Address::times_4, 0));
7407 rorq(op1, 32);
7408
7409 bind(L_multiply);
7410 subl(zlen, 2);
7411 movq(sum, Address(z, zlen, Address::times_4, 0));
7412
7413 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
7414 if (UseBMI2Instructions) {
7415 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
7416 }
7417 else {
7418 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7419 }
7420
7421 movq(Address(z, zlen, Address::times_4, 0), sum);
7422
7423 jmp(L_third_loop);
7424 bind(L_third_loop_exit);
7425
7426 // Fourth loop
7427 // Add 64 bit long carry into z with carry propagation.
7428 // Uses offsetted zlen.
7429 add_one_64(z, zlen, carry, tmp1);
7430
7431 pop(len);
7432 pop(zlen);
7433 jmp(L_second_loop);
7434
7435 // Next infrequent code is moved outside loops.
7436 bind(L_last_x);
7437 movl(op1, Address(x, 0));
7438 jmp(L_multiply);
7439
7440 bind(L_second_loop_exit);
7441 pop(len);
7442 pop(zlen);
7443 pop(len);
7444 pop(zlen);
7445
7446 // Fifth loop
7447 // Shift z left 1 bit.
7448 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
7449
7450 // z[zlen-1] |= x[len-1] & 1;
7451 movl(tmp3, Address(x, len, Address::times_4, -4));
7452 andl(tmp3, 1);
7453 orl(Address(z, zlen, Address::times_4, -4), tmp3);
7454
7455 pop(tmp5);
7456 pop(tmp4);
7457 pop(tmp3);
7458 pop(tmp2);
7459 pop(tmp1);
7460 }
7461
7462 /**
7463 * Helper function for mul_add()
7464 * Multiply the in[] by int k and add to out[] starting at offset offs using
7465 * 128 bit by 32 bit multiply and return the carry in tmp5.
7466 * Only quad int aligned length of in[] is operated on in this function.
7467 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
7468 * This function preserves out, in and k registers.
7469 * len and offset point to the appropriate index in "in" & "out" correspondingly
7470 * tmp5 has the carry.
7471 * other registers are temporary and are modified.
7472 *
7473 */
7474 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
7475 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
7476 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7477
7478 Label L_first_loop, L_first_loop_exit;
7479
7480 movl(tmp1, len);
7481 shrl(tmp1, 2);
7482
7483 bind(L_first_loop);
7484 subl(tmp1, 1);
7485 jccb(Assembler::negative, L_first_loop_exit);
7486
7487 subl(len, 4);
7488 subl(offset, 4);
7489
7490 Register op2 = tmp2;
7491 const Register sum = tmp3;
7492 const Register op1 = tmp4;
7493 const Register carry = tmp5;
7494
7495 if (UseBMI2Instructions) {
7496 op2 = rdxReg;
7497 }
7498
7499 movq(op1, Address(in, len, Address::times_4, 8));
7500 rorq(op1, 32);
7501 movq(sum, Address(out, offset, Address::times_4, 8));
7502 rorq(sum, 32);
7503 if (UseBMI2Instructions) {
7504 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7505 }
7506 else {
7507 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7508 }
7509 // Store back in big endian from little endian
7510 rorq(sum, 0x20);
7511 movq(Address(out, offset, Address::times_4, 8), sum);
7512
7513 movq(op1, Address(in, len, Address::times_4, 0));
7514 rorq(op1, 32);
7515 movq(sum, Address(out, offset, Address::times_4, 0));
7516 rorq(sum, 32);
7517 if (UseBMI2Instructions) {
7518 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7519 }
7520 else {
7521 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7522 }
7523 // Store back in big endian from little endian
7524 rorq(sum, 0x20);
7525 movq(Address(out, offset, Address::times_4, 0), sum);
7526
7527 jmp(L_first_loop);
7528 bind(L_first_loop_exit);
7529 }
7530
7531 /**
7532 * Code for BigInteger::mulAdd() intrinsic
7533 *
7534 * rdi: out
7535 * rsi: in
7536 * r11: offs (out.length - offset)
7537 * rcx: len
7538 * r8: k
7539 * r12: tmp1
7540 * r13: tmp2
7541 * r14: tmp3
7542 * r15: tmp4
7543 * rbx: tmp5
7544 * Multiply the in[] by word k and add to out[], return the carry in rax
7545 */
7546 void MacroAssembler::mul_add(Register out, Register in, Register offs,
7547 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
7548 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7549
7550 Label L_carry, L_last_in, L_done;
7551
7552 // carry = 0;
7553 // for (int j=len-1; j >= 0; j--) {
7554 // long product = (in[j] & LONG_MASK) * kLong +
7555 // (out[offs] & LONG_MASK) + carry;
7556 // out[offs--] = (int)product;
7557 // carry = product >>> 32;
7558 // }
7559 //
7560 push(tmp1);
7561 push(tmp2);
7562 push(tmp3);
7563 push(tmp4);
7564 push(tmp5);
7565
7566 Register op2 = tmp2;
7567 const Register sum = tmp3;
7568 const Register op1 = tmp4;
7569 const Register carry = tmp5;
7570
7571 if (UseBMI2Instructions) {
7572 op2 = rdxReg;
7573 movl(op2, k);
7574 }
7575 else {
7576 movl(op2, k);
7577 }
7578
7579 xorq(carry, carry);
7580
7581 //First loop
7582
7583 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
7584 //The carry is in tmp5
7585 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
7586
7587 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
7588 decrementl(len);
7589 jccb(Assembler::negative, L_carry);
7590 decrementl(len);
7591 jccb(Assembler::negative, L_last_in);
7592
7593 movq(op1, Address(in, len, Address::times_4, 0));
7594 rorq(op1, 32);
7595
7596 subl(offs, 2);
7597 movq(sum, Address(out, offs, Address::times_4, 0));
7598 rorq(sum, 32);
7599
7600 if (UseBMI2Instructions) {
7601 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7602 }
7603 else {
7604 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7605 }
7606
7607 // Store back in big endian from little endian
7608 rorq(sum, 0x20);
7609 movq(Address(out, offs, Address::times_4, 0), sum);
7610
7611 testl(len, len);
7612 jccb(Assembler::zero, L_carry);
7613
7614 //Multiply the last in[] entry, if any
7615 bind(L_last_in);
7616 movl(op1, Address(in, 0));
7617 movl(sum, Address(out, offs, Address::times_4, -4));
7618
7619 movl(raxReg, k);
7620 mull(op1); //tmp4 * eax -> edx:eax
7621 addl(sum, carry);
7622 adcl(rdxReg, 0);
7623 addl(sum, raxReg);
7624 adcl(rdxReg, 0);
7625 movl(carry, rdxReg);
7626
7627 movl(Address(out, offs, Address::times_4, -4), sum);
7628
7629 bind(L_carry);
7630 //return tmp5/carry as carry in rax
7631 movl(rax, carry);
7632
7633 bind(L_done);
7634 pop(tmp5);
7635 pop(tmp4);
7636 pop(tmp3);
7637 pop(tmp2);
7638 pop(tmp1);
7639 }
7640
7641 /**
7642 * Emits code to update CRC-32 with a byte value according to constants in table
7643 *
7644 * @param [in,out]crc Register containing the crc.
7645 * @param [in]val Register containing the byte to fold into the CRC.
7646 * @param [in]table Register containing the table of crc constants.
7647 *
7648 * uint32_t crc;
7649 * val = crc_table[(val ^ crc) & 0xFF];
7650 * crc = val ^ (crc >> 8);
7651 *
7652 */
7653 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
7654 xorl(val, crc);
7655 andl(val, 0xFF);
7656 shrl(crc, 8); // unsigned shift
7657 xorl(crc, Address(table, val, Address::times_4, 0));
7658 }
7659
7660 /**
7661 * Fold 128-bit data chunk
7662 */
7663 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
7664 if (UseAVX > 0) {
7665 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
7666 vpclmulldq(xcrc, xK, xcrc); // [63:0]
7667 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
7668 pxor(xcrc, xtmp);
7669 } else {
7670 movdqa(xtmp, xcrc);
7671 pclmulhdq(xtmp, xK); // [123:64]
7672 pclmulldq(xcrc, xK); // [63:0]
7673 pxor(xcrc, xtmp);
7674 movdqu(xtmp, Address(buf, offset));
7675 pxor(xcrc, xtmp);
7676 }
7677 }
7678
7679 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
7680 if (UseAVX > 0) {
7681 vpclmulhdq(xtmp, xK, xcrc);
7682 vpclmulldq(xcrc, xK, xcrc);
7683 pxor(xcrc, xbuf);
7684 pxor(xcrc, xtmp);
7685 } else {
7686 movdqa(xtmp, xcrc);
7687 pclmulhdq(xtmp, xK);
7688 pclmulldq(xcrc, xK);
7689 pxor(xcrc, xbuf);
7690 pxor(xcrc, xtmp);
7691 }
7692 }
7693
7694 /**
7695 * 8-bit folds to compute 32-bit CRC
7696 *
7697 * uint64_t xcrc;
7698 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
7699 */
7700 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
7701 movdl(tmp, xcrc);
7702 andl(tmp, 0xFF);
7703 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
7704 psrldq(xcrc, 1); // unsigned shift one byte
7705 pxor(xcrc, xtmp);
7706 }
7707
7708 /**
7709 * uint32_t crc;
7710 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
7711 */
7712 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
7713 movl(tmp, crc);
7714 andl(tmp, 0xFF);
7715 shrl(crc, 8);
7716 xorl(crc, Address(table, tmp, Address::times_4, 0));
7717 }
7718
7719 /**
7720 * @param crc register containing existing CRC (32-bit)
7721 * @param buf register pointing to input byte buffer (byte*)
7722 * @param len register containing number of bytes
7723 * @param table register that will contain address of CRC table
7724 * @param tmp scratch register
7725 */
7726 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
7727 assert_different_registers(crc, buf, len, table, tmp, rax);
7728
7729 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7730 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7731
7732 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
7733 // context for the registers used, where all instructions below are using 128-bit mode
7734 // On EVEX without VL and BW, these instructions will all be AVX.
7735 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
7736 notl(crc); // ~crc
7737 cmpl(len, 16);
7738 jcc(Assembler::less, L_tail);
7739
7740 // Align buffer to 16 bytes
7741 movl(tmp, buf);
7742 andl(tmp, 0xF);
7743 jccb(Assembler::zero, L_aligned);
7744 subl(tmp, 16);
7745 addl(len, tmp);
7746
7747 align(4);
7748 BIND(L_align_loop);
7749 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7750 update_byte_crc32(crc, rax, table);
7751 increment(buf);
7752 incrementl(tmp);
7753 jccb(Assembler::less, L_align_loop);
7754
7755 BIND(L_aligned);
7756 movl(tmp, len); // save
7757 shrl(len, 4);
7758 jcc(Assembler::zero, L_tail_restore);
7759
7760 // Fold crc into first bytes of vector
7761 movdqa(xmm1, Address(buf, 0));
7762 movdl(rax, xmm1);
7763 xorl(crc, rax);
7764 if (VM_Version::supports_sse4_1()) {
7765 pinsrd(xmm1, crc, 0);
7766 } else {
7767 pinsrw(xmm1, crc, 0);
7768 shrl(crc, 16);
7769 pinsrw(xmm1, crc, 1);
7770 }
7771 addptr(buf, 16);
7772 subl(len, 4); // len > 0
7773 jcc(Assembler::less, L_fold_tail);
7774
7775 movdqa(xmm2, Address(buf, 0));
7776 movdqa(xmm3, Address(buf, 16));
7777 movdqa(xmm4, Address(buf, 32));
7778 addptr(buf, 48);
7779 subl(len, 3);
7780 jcc(Assembler::lessEqual, L_fold_512b);
7781
7782 // Fold total 512 bits of polynomial on each iteration,
7783 // 128 bits per each of 4 parallel streams.
7784 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
7785
7786 align32();
7787 BIND(L_fold_512b_loop);
7788 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
7789 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
7790 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
7791 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
7792 addptr(buf, 64);
7793 subl(len, 4);
7794 jcc(Assembler::greater, L_fold_512b_loop);
7795
7796 // Fold 512 bits to 128 bits.
7797 BIND(L_fold_512b);
7798 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
7799 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
7800 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
7801 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
7802
7803 // Fold the rest of 128 bits data chunks
7804 BIND(L_fold_tail);
7805 addl(len, 3);
7806 jccb(Assembler::lessEqual, L_fold_128b);
7807 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
7808
7809 BIND(L_fold_tail_loop);
7810 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
7811 addptr(buf, 16);
7812 decrementl(len);
7813 jccb(Assembler::greater, L_fold_tail_loop);
7814
7815 // Fold 128 bits in xmm1 down into 32 bits in crc register.
7816 BIND(L_fold_128b);
7817 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
7818 if (UseAVX > 0) {
7819 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
7820 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
7821 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
7822 } else {
7823 movdqa(xmm2, xmm0);
7824 pclmulqdq(xmm2, xmm1, 0x1);
7825 movdqa(xmm3, xmm0);
7826 pand(xmm3, xmm2);
7827 pclmulqdq(xmm0, xmm3, 0x1);
7828 }
7829 psrldq(xmm1, 8);
7830 psrldq(xmm2, 4);
7831 pxor(xmm0, xmm1);
7832 pxor(xmm0, xmm2);
7833
7834 // 8 8-bit folds to compute 32-bit CRC.
7835 for (int j = 0; j < 4; j++) {
7836 fold_8bit_crc32(xmm0, table, xmm1, rax);
7837 }
7838 movdl(crc, xmm0); // mov 32 bits to general register
7839 for (int j = 0; j < 4; j++) {
7840 fold_8bit_crc32(crc, table, rax);
7841 }
7842
7843 BIND(L_tail_restore);
7844 movl(len, tmp); // restore
7845 BIND(L_tail);
7846 andl(len, 0xf);
7847 jccb(Assembler::zero, L_exit);
7848
7849 // Fold the rest of bytes
7850 align(4);
7851 BIND(L_tail_loop);
7852 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7853 update_byte_crc32(crc, rax, table);
7854 increment(buf);
7855 decrementl(len);
7856 jccb(Assembler::greater, L_tail_loop);
7857
7858 BIND(L_exit);
7859 notl(crc); // ~c
7860 }
7861
7862 // Helper function for AVX 512 CRC32
7863 // Fold 512-bit data chunks
7864 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
7865 Register pos, int offset) {
7866 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
7867 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
7868 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
7869 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
7870 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
7871 }
7872
7873 // Helper function for AVX 512 CRC32
7874 // Compute CRC32 for < 256B buffers
7875 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
7876 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
7877 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
7878
7879 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
7880 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
7881 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
7882
7883 // check if there is enough buffer to be able to fold 16B at a time
7884 cmpl(len, 32);
7885 jcc(Assembler::less, L_less_than_32);
7886
7887 // if there is, load the constants
7888 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
7889 movdl(xmm0, crc); // get the initial crc value
7890 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7891 pxor(xmm7, xmm0);
7892
7893 // update the buffer pointer
7894 addl(pos, 16);
7895 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
7896 subl(len, 32);
7897 jmp(L_16B_reduction_loop);
7898
7899 bind(L_less_than_32);
7900 //mov initial crc to the return value. this is necessary for zero - length buffers.
7901 movl(rax, crc);
7902 testl(len, len);
7903 jcc(Assembler::equal, L_cleanup);
7904
7905 movdl(xmm0, crc); //get the initial crc value
7906
7907 cmpl(len, 16);
7908 jcc(Assembler::equal, L_exact_16_left);
7909 jcc(Assembler::less, L_less_than_16_left);
7910
7911 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7912 pxor(xmm7, xmm0); //xor the initial crc value
7913 addl(pos, 16);
7914 subl(len, 16);
7915 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
7916 jmp(L_get_last_two_xmms);
7917
7918 bind(L_less_than_16_left);
7919 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
7920 pxor(xmm1, xmm1);
7921 movptr(tmp1, rsp);
7922 movdqu(Address(tmp1, 0 * 16), xmm1);
7923
7924 cmpl(len, 4);
7925 jcc(Assembler::less, L_only_less_than_4);
7926
7927 //backup the counter value
7928 movl(tmp2, len);
7929 cmpl(len, 8);
7930 jcc(Assembler::less, L_less_than_8_left);
7931
7932 //load 8 Bytes
7933 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
7934 movq(Address(tmp1, 0 * 16), rax);
7935 addptr(tmp1, 8);
7936 subl(len, 8);
7937 addl(pos, 8);
7938
7939 bind(L_less_than_8_left);
7940 cmpl(len, 4);
7941 jcc(Assembler::less, L_less_than_4_left);
7942
7943 //load 4 Bytes
7944 movl(rax, Address(buf, pos, Address::times_1, 0));
7945 movl(Address(tmp1, 0 * 16), rax);
7946 addptr(tmp1, 4);
7947 subl(len, 4);
7948 addl(pos, 4);
7949
7950 bind(L_less_than_4_left);
7951 cmpl(len, 2);
7952 jcc(Assembler::less, L_less_than_2_left);
7953
7954 // load 2 Bytes
7955 movw(rax, Address(buf, pos, Address::times_1, 0));
7956 movl(Address(tmp1, 0 * 16), rax);
7957 addptr(tmp1, 2);
7958 subl(len, 2);
7959 addl(pos, 2);
7960
7961 bind(L_less_than_2_left);
7962 cmpl(len, 1);
7963 jcc(Assembler::less, L_zero_left);
7964
7965 // load 1 Byte
7966 movb(rax, Address(buf, pos, Address::times_1, 0));
7967 movb(Address(tmp1, 0 * 16), rax);
7968
7969 bind(L_zero_left);
7970 movdqu(xmm7, Address(rsp, 0));
7971 pxor(xmm7, xmm0); //xor the initial crc value
7972
7973 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
7974 movdqu(xmm0, Address(rax, tmp2));
7975 pshufb(xmm7, xmm0);
7976 jmp(L_128_done);
7977
7978 bind(L_exact_16_left);
7979 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
7980 pxor(xmm7, xmm0); //xor the initial crc value
7981 jmp(L_128_done);
7982
7983 bind(L_only_less_than_4);
7984 cmpl(len, 3);
7985 jcc(Assembler::less, L_only_less_than_3);
7986
7987 // load 3 Bytes
7988 movb(rax, Address(buf, pos, Address::times_1, 0));
7989 movb(Address(tmp1, 0), rax);
7990
7991 movb(rax, Address(buf, pos, Address::times_1, 1));
7992 movb(Address(tmp1, 1), rax);
7993
7994 movb(rax, Address(buf, pos, Address::times_1, 2));
7995 movb(Address(tmp1, 2), rax);
7996
7997 movdqu(xmm7, Address(rsp, 0));
7998 pxor(xmm7, xmm0); //xor the initial crc value
7999
8000 pslldq(xmm7, 0x5);
8001 jmp(L_barrett);
8002 bind(L_only_less_than_3);
8003 cmpl(len, 2);
8004 jcc(Assembler::less, L_only_less_than_2);
8005
8006 // load 2 Bytes
8007 movb(rax, Address(buf, pos, Address::times_1, 0));
8008 movb(Address(tmp1, 0), rax);
8009
8010 movb(rax, Address(buf, pos, Address::times_1, 1));
8011 movb(Address(tmp1, 1), rax);
8012
8013 movdqu(xmm7, Address(rsp, 0));
8014 pxor(xmm7, xmm0); //xor the initial crc value
8015
8016 pslldq(xmm7, 0x6);
8017 jmp(L_barrett);
8018
8019 bind(L_only_less_than_2);
8020 //load 1 Byte
8021 movb(rax, Address(buf, pos, Address::times_1, 0));
8022 movb(Address(tmp1, 0), rax);
8023
8024 movdqu(xmm7, Address(rsp, 0));
8025 pxor(xmm7, xmm0); //xor the initial crc value
8026
8027 pslldq(xmm7, 0x7);
8028 }
8029
8030 /**
8031 * Compute CRC32 using AVX512 instructions
8032 * param crc register containing existing CRC (32-bit)
8033 * param buf register pointing to input byte buffer (byte*)
8034 * param len register containing number of bytes
8035 * param table address of crc or crc32c table
8036 * param tmp1 scratch register
8037 * param tmp2 scratch register
8038 * return rax result register
8039 *
8040 * This routine is identical for crc32c with the exception of the precomputed constant
8041 * table which will be passed as the table argument. The calculation steps are
8042 * the same for both variants.
8043 */
8044 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8045 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8046
8047 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8048 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8049 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8050 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8051 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8052
8053 const Register pos = r12;
8054 push(r12);
8055 subptr(rsp, 16 * 2 + 8);
8056
8057 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8058 // context for the registers used, where all instructions below are using 128-bit mode
8059 // On EVEX without VL and BW, these instructions will all be AVX.
8060 movl(pos, 0);
8061
8062 // check if smaller than 256B
8063 cmpl(len, 256);
8064 jcc(Assembler::less, L_less_than_256);
8065
8066 // load the initial crc value
8067 movdl(xmm10, crc);
8068
8069 // receive the initial 64B data, xor the initial crc value
8070 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8071 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8072 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8073 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8074
8075 subl(len, 256);
8076 cmpl(len, 256);
8077 jcc(Assembler::less, L_fold_128_B_loop);
8078
8079 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8080 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8081 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8082 subl(len, 256);
8083
8084 bind(L_fold_256_B_loop);
8085 addl(pos, 256);
8086 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8087 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8088 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8089 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8090
8091 subl(len, 256);
8092 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8093
8094 // Fold 256 into 128
8095 addl(pos, 256);
8096 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8097 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8098 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8099
8100 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8101 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8102 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8103
8104 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8105 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8106
8107 addl(len, 128);
8108 jmp(L_fold_128_B_register);
8109
8110 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8111 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8112
8113 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8114 bind(L_fold_128_B_loop);
8115 addl(pos, 128);
8116 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8117 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8118
8119 subl(len, 128);
8120 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8121
8122 addl(pos, 128);
8123
8124 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8125 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8126 bind(L_fold_128_B_register);
8127 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8128 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8129 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8130 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8131 // save last that has no multiplicand
8132 vextracti64x2(xmm7, xmm4, 3);
8133
8134 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8135 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8136 // Needed later in reduction loop
8137 movdqu(xmm10, Address(table, 1 * 16));
8138 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8139 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8140
8141 // Swap 1,0,3,2 - 01 00 11 10
8142 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8143 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8144 vextracti128(xmm5, xmm8, 1);
8145 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8146
8147 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8148 // instead of a cmp instruction, we use the negative flag with the jl instruction
8149 addl(len, 128 - 16);
8150 jcc(Assembler::less, L_final_reduction_for_128);
8151
8152 bind(L_16B_reduction_loop);
8153 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8154 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8155 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8156 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8157 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8158 addl(pos, 16);
8159 subl(len, 16);
8160 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8161
8162 bind(L_final_reduction_for_128);
8163 addl(len, 16);
8164 jcc(Assembler::equal, L_128_done);
8165
8166 bind(L_get_last_two_xmms);
8167 movdqu(xmm2, xmm7);
8168 addl(pos, len);
8169 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8170 subl(pos, len);
8171
8172 // get rid of the extra data that was loaded before
8173 // load the shift constant
8174 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8175 movdqu(xmm0, Address(rax, len));
8176 addl(rax, len);
8177
8178 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8179 //Change mask to 512
8180 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8181 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8182
8183 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8184 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8185 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8186 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8187 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8188
8189 bind(L_128_done);
8190 // compute crc of a 128-bit value
8191 movdqu(xmm10, Address(table, 3 * 16));
8192 movdqu(xmm0, xmm7);
8193
8194 // 64b fold
8195 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8196 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8197 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8198
8199 // 32b fold
8200 movdqu(xmm0, xmm7);
8201 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8202 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8203 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8204 jmp(L_barrett);
8205
8206 bind(L_less_than_256);
8207 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8208
8209 //barrett reduction
8210 bind(L_barrett);
8211 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8212 movdqu(xmm1, xmm7);
8213 movdqu(xmm2, xmm7);
8214 movdqu(xmm10, Address(table, 4 * 16));
8215
8216 pclmulqdq(xmm7, xmm10, 0x0);
8217 pxor(xmm7, xmm2);
8218 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8219 movdqu(xmm2, xmm7);
8220 pclmulqdq(xmm7, xmm10, 0x10);
8221 pxor(xmm7, xmm2);
8222 pxor(xmm7, xmm1);
8223 pextrd(crc, xmm7, 2);
8224
8225 bind(L_cleanup);
8226 addptr(rsp, 16 * 2 + 8);
8227 pop(r12);
8228 }
8229
8230 // S. Gueron / Information Processing Letters 112 (2012) 184
8231 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8232 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8233 // Output: the 64-bit carry-less product of B * CONST
8234 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8235 Register tmp1, Register tmp2, Register tmp3) {
8236 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8237 if (n > 0) {
8238 addq(tmp3, n * 256 * 8);
8239 }
8240 // Q1 = TABLEExt[n][B & 0xFF];
8241 movl(tmp1, in);
8242 andl(tmp1, 0x000000FF);
8243 shll(tmp1, 3);
8244 addq(tmp1, tmp3);
8245 movq(tmp1, Address(tmp1, 0));
8246
8247 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8248 movl(tmp2, in);
8249 shrl(tmp2, 8);
8250 andl(tmp2, 0x000000FF);
8251 shll(tmp2, 3);
8252 addq(tmp2, tmp3);
8253 movq(tmp2, Address(tmp2, 0));
8254
8255 shlq(tmp2, 8);
8256 xorq(tmp1, tmp2);
8257
8258 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8259 movl(tmp2, in);
8260 shrl(tmp2, 16);
8261 andl(tmp2, 0x000000FF);
8262 shll(tmp2, 3);
8263 addq(tmp2, tmp3);
8264 movq(tmp2, Address(tmp2, 0));
8265
8266 shlq(tmp2, 16);
8267 xorq(tmp1, tmp2);
8268
8269 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8270 shrl(in, 24);
8271 andl(in, 0x000000FF);
8272 shll(in, 3);
8273 addq(in, tmp3);
8274 movq(in, Address(in, 0));
8275
8276 shlq(in, 24);
8277 xorq(in, tmp1);
8278 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8279 }
8280
8281 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8282 Register in_out,
8283 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8284 XMMRegister w_xtmp2,
8285 Register tmp1,
8286 Register n_tmp2, Register n_tmp3) {
8287 if (is_pclmulqdq_supported) {
8288 movdl(w_xtmp1, in_out); // modified blindly
8289
8290 movl(tmp1, const_or_pre_comp_const_index);
8291 movdl(w_xtmp2, tmp1);
8292 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8293
8294 movdq(in_out, w_xtmp1);
8295 } else {
8296 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8297 }
8298 }
8299
8300 // Recombination Alternative 2: No bit-reflections
8301 // T1 = (CRC_A * U1) << 1
8302 // T2 = (CRC_B * U2) << 1
8303 // C1 = T1 >> 32
8304 // C2 = T2 >> 32
8305 // T1 = T1 & 0xFFFFFFFF
8306 // T2 = T2 & 0xFFFFFFFF
8307 // T1 = CRC32(0, T1)
8308 // T2 = CRC32(0, T2)
8309 // C1 = C1 ^ T1
8310 // C2 = C2 ^ T2
8311 // CRC = C1 ^ C2 ^ CRC_C
8312 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8313 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8314 Register tmp1, Register tmp2,
8315 Register n_tmp3) {
8316 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8317 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8318 shlq(in_out, 1);
8319 movl(tmp1, in_out);
8320 shrq(in_out, 32);
8321 xorl(tmp2, tmp2);
8322 crc32(tmp2, tmp1, 4);
8323 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8324 shlq(in1, 1);
8325 movl(tmp1, in1);
8326 shrq(in1, 32);
8327 xorl(tmp2, tmp2);
8328 crc32(tmp2, tmp1, 4);
8329 xorl(in1, tmp2);
8330 xorl(in_out, in1);
8331 xorl(in_out, in2);
8332 }
8333
8334 // Set N to predefined value
8335 // Subtract from a length of a buffer
8336 // execute in a loop:
8337 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8338 // for i = 1 to N do
8339 // CRC_A = CRC32(CRC_A, A[i])
8340 // CRC_B = CRC32(CRC_B, B[i])
8341 // CRC_C = CRC32(CRC_C, C[i])
8342 // end for
8343 // Recombine
8344 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8345 Register in_out1, Register in_out2, Register in_out3,
8346 Register tmp1, Register tmp2, Register tmp3,
8347 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8348 Register tmp4, Register tmp5,
8349 Register n_tmp6) {
8350 Label L_processPartitions;
8351 Label L_processPartition;
8352 Label L_exit;
8353
8354 bind(L_processPartitions);
8355 cmpl(in_out1, 3 * size);
8356 jcc(Assembler::less, L_exit);
8357 xorl(tmp1, tmp1);
8358 xorl(tmp2, tmp2);
8359 movq(tmp3, in_out2);
8360 addq(tmp3, size);
8361
8362 bind(L_processPartition);
8363 crc32(in_out3, Address(in_out2, 0), 8);
8364 crc32(tmp1, Address(in_out2, size), 8);
8365 crc32(tmp2, Address(in_out2, size * 2), 8);
8366 addq(in_out2, 8);
8367 cmpq(in_out2, tmp3);
8368 jcc(Assembler::less, L_processPartition);
8369 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8370 w_xtmp1, w_xtmp2, w_xtmp3,
8371 tmp4, tmp5,
8372 n_tmp6);
8373 addq(in_out2, 2 * size);
8374 subl(in_out1, 3 * size);
8375 jmp(L_processPartitions);
8376
8377 bind(L_exit);
8378 }
8379
8380 // Algorithm 2: Pipelined usage of the CRC32 instruction.
8381 // Input: A buffer I of L bytes.
8382 // Output: the CRC32C value of the buffer.
8383 // Notations:
8384 // Write L = 24N + r, with N = floor (L/24).
8385 // r = L mod 24 (0 <= r < 24).
8386 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
8387 // N quadwords, and R consists of r bytes.
8388 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
8389 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
8390 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
8391 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
8392 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
8393 Register tmp1, Register tmp2, Register tmp3,
8394 Register tmp4, Register tmp5, Register tmp6,
8395 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8396 bool is_pclmulqdq_supported) {
8397 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
8398 Label L_wordByWord;
8399 Label L_byteByByteProlog;
8400 Label L_byteByByte;
8401 Label L_exit;
8402
8403 if (is_pclmulqdq_supported ) {
8404 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
8405 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
8406
8407 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
8408 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
8409
8410 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
8411 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
8412 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
8413 } else {
8414 const_or_pre_comp_const_index[0] = 1;
8415 const_or_pre_comp_const_index[1] = 0;
8416
8417 const_or_pre_comp_const_index[2] = 3;
8418 const_or_pre_comp_const_index[3] = 2;
8419
8420 const_or_pre_comp_const_index[4] = 5;
8421 const_or_pre_comp_const_index[5] = 4;
8422 }
8423 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
8424 in2, in1, in_out,
8425 tmp1, tmp2, tmp3,
8426 w_xtmp1, w_xtmp2, w_xtmp3,
8427 tmp4, tmp5,
8428 tmp6);
8429 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
8430 in2, in1, in_out,
8431 tmp1, tmp2, tmp3,
8432 w_xtmp1, w_xtmp2, w_xtmp3,
8433 tmp4, tmp5,
8434 tmp6);
8435 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
8436 in2, in1, in_out,
8437 tmp1, tmp2, tmp3,
8438 w_xtmp1, w_xtmp2, w_xtmp3,
8439 tmp4, tmp5,
8440 tmp6);
8441 movl(tmp1, in2);
8442 andl(tmp1, 0x00000007);
8443 negl(tmp1);
8444 addl(tmp1, in2);
8445 addq(tmp1, in1);
8446
8447 cmpq(in1, tmp1);
8448 jccb(Assembler::greaterEqual, L_byteByByteProlog);
8449 align(16);
8450 BIND(L_wordByWord);
8451 crc32(in_out, Address(in1, 0), 8);
8452 addq(in1, 8);
8453 cmpq(in1, tmp1);
8454 jcc(Assembler::less, L_wordByWord);
8455
8456 BIND(L_byteByByteProlog);
8457 andl(in2, 0x00000007);
8458 movl(tmp2, 1);
8459
8460 cmpl(tmp2, in2);
8461 jccb(Assembler::greater, L_exit);
8462 BIND(L_byteByByte);
8463 crc32(in_out, Address(in1, 0), 1);
8464 incq(in1);
8465 incl(tmp2);
8466 cmpl(tmp2, in2);
8467 jcc(Assembler::lessEqual, L_byteByByte);
8468
8469 BIND(L_exit);
8470 }
8471 #undef BIND
8472 #undef BLOCK_COMMENT
8473
8474 // Compress char[] array to byte[].
8475 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
8476 // Return the array length if every element in array can be encoded,
8477 // otherwise, the index of first non-latin1 (> 0xff) character.
8478 // @IntrinsicCandidate
8479 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
8480 // for (int i = 0; i < len; i++) {
8481 // char c = src[srcOff];
8482 // if (c > 0xff) {
8483 // return i; // return index of non-latin1 char
8484 // }
8485 // dst[dstOff] = (byte)c;
8486 // srcOff++;
8487 // dstOff++;
8488 // }
8489 // return len;
8490 // }
8491 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
8492 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8493 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8494 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
8495 Label copy_chars_loop, done, reset_sp, copy_tail;
8496
8497 // rsi: src
8498 // rdi: dst
8499 // rdx: len
8500 // rcx: tmp5
8501 // rax: result
8502
8503 // rsi holds start addr of source char[] to be compressed
8504 // rdi holds start addr of destination byte[]
8505 // rdx holds length
8506
8507 assert(len != result, "");
8508
8509 // save length for return
8510 movl(result, len);
8511
8512 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
8513 VM_Version::supports_avx512vlbw() &&
8514 VM_Version::supports_bmi2()) {
8515
8516 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
8517
8518 // alignment
8519 Label post_alignment;
8520
8521 // if length of the string is less than 32, handle it the old fashioned way
8522 testl(len, -32);
8523 jcc(Assembler::zero, below_threshold);
8524
8525 // First check whether a character is compressible ( <= 0xFF).
8526 // Create mask to test for Unicode chars inside zmm vector
8527 movl(tmp5, 0x00FF);
8528 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
8529
8530 testl(len, -64);
8531 jccb(Assembler::zero, post_alignment);
8532
8533 movl(tmp5, dst);
8534 andl(tmp5, (32 - 1));
8535 negl(tmp5);
8536 andl(tmp5, (32 - 1));
8537
8538 // bail out when there is nothing to be done
8539 testl(tmp5, 0xFFFFFFFF);
8540 jccb(Assembler::zero, post_alignment);
8541
8542 // ~(~0 << len), where len is the # of remaining elements to process
8543 movl(len, 0xFFFFFFFF);
8544 shlxl(len, len, tmp5);
8545 notl(len);
8546 kmovdl(mask2, len);
8547 movl(len, result);
8548
8549 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
8550 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
8551 ktestd(mask1, mask2);
8552 jcc(Assembler::carryClear, copy_tail);
8553
8554 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
8555
8556 addptr(src, tmp5);
8557 addptr(src, tmp5);
8558 addptr(dst, tmp5);
8559 subl(len, tmp5);
8560
8561 bind(post_alignment);
8562 // end of alignment
8563
8564 movl(tmp5, len);
8565 andl(tmp5, (32 - 1)); // tail count (in chars)
8566 andl(len, ~(32 - 1)); // vector count (in chars)
8567 jccb(Assembler::zero, copy_loop_tail);
8568
8569 lea(src, Address(src, len, Address::times_2));
8570 lea(dst, Address(dst, len, Address::times_1));
8571 negptr(len);
8572
8573 bind(copy_32_loop);
8574 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
8575 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
8576 kortestdl(mask1, mask1);
8577 jccb(Assembler::carryClear, reset_for_copy_tail);
8578
8579 // All elements in current processed chunk are valid candidates for
8580 // compression. Write a truncated byte elements to the memory.
8581 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
8582 addptr(len, 32);
8583 jccb(Assembler::notZero, copy_32_loop);
8584
8585 bind(copy_loop_tail);
8586 // bail out when there is nothing to be done
8587 testl(tmp5, 0xFFFFFFFF);
8588 jcc(Assembler::zero, done);
8589
8590 movl(len, tmp5);
8591
8592 // ~(~0 << len), where len is the # of remaining elements to process
8593 movl(tmp5, 0xFFFFFFFF);
8594 shlxl(tmp5, tmp5, len);
8595 notl(tmp5);
8596
8597 kmovdl(mask2, tmp5);
8598
8599 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
8600 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
8601 ktestd(mask1, mask2);
8602 jcc(Assembler::carryClear, copy_tail);
8603
8604 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
8605 jmp(done);
8606
8607 bind(reset_for_copy_tail);
8608 lea(src, Address(src, tmp5, Address::times_2));
8609 lea(dst, Address(dst, tmp5, Address::times_1));
8610 subptr(len, tmp5);
8611 jmp(copy_chars_loop);
8612
8613 bind(below_threshold);
8614 }
8615
8616 if (UseSSE42Intrinsics) {
8617 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
8618
8619 // vectored compression
8620 testl(len, 0xfffffff8);
8621 jcc(Assembler::zero, copy_tail);
8622
8623 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
8624 movdl(tmp1Reg, tmp5);
8625 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
8626
8627 andl(len, 0xfffffff0);
8628 jccb(Assembler::zero, copy_16);
8629
8630 // compress 16 chars per iter
8631 pxor(tmp4Reg, tmp4Reg);
8632
8633 lea(src, Address(src, len, Address::times_2));
8634 lea(dst, Address(dst, len, Address::times_1));
8635 negptr(len);
8636
8637 bind(copy_32_loop);
8638 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
8639 por(tmp4Reg, tmp2Reg);
8640 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
8641 por(tmp4Reg, tmp3Reg);
8642 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
8643 jccb(Assembler::notZero, reset_for_copy_tail);
8644 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
8645 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
8646 addptr(len, 16);
8647 jccb(Assembler::notZero, copy_32_loop);
8648
8649 // compress next vector of 8 chars (if any)
8650 bind(copy_16);
8651 // len = 0
8652 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
8653 jccb(Assembler::zero, copy_tail_sse);
8654
8655 pxor(tmp3Reg, tmp3Reg);
8656
8657 movdqu(tmp2Reg, Address(src, 0));
8658 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8659 jccb(Assembler::notZero, reset_for_copy_tail);
8660 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
8661 movq(Address(dst, 0), tmp2Reg);
8662 addptr(src, 16);
8663 addptr(dst, 8);
8664 jmpb(copy_tail_sse);
8665
8666 bind(reset_for_copy_tail);
8667 movl(tmp5, result);
8668 andl(tmp5, 0x0000000f);
8669 lea(src, Address(src, tmp5, Address::times_2));
8670 lea(dst, Address(dst, tmp5, Address::times_1));
8671 subptr(len, tmp5);
8672 jmpb(copy_chars_loop);
8673
8674 bind(copy_tail_sse);
8675 movl(len, result);
8676 andl(len, 0x00000007); // tail count (in chars)
8677 }
8678 // compress 1 char per iter
8679 bind(copy_tail);
8680 testl(len, len);
8681 jccb(Assembler::zero, done);
8682 lea(src, Address(src, len, Address::times_2));
8683 lea(dst, Address(dst, len, Address::times_1));
8684 negptr(len);
8685
8686 bind(copy_chars_loop);
8687 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
8688 testl(tmp5, 0xff00); // check if Unicode char
8689 jccb(Assembler::notZero, reset_sp);
8690 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
8691 increment(len);
8692 jccb(Assembler::notZero, copy_chars_loop);
8693
8694 // add len then return (len will be zero if compress succeeded, otherwise negative)
8695 bind(reset_sp);
8696 addl(result, len);
8697
8698 bind(done);
8699 }
8700
8701 // Inflate byte[] array to char[].
8702 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
8703 // @IntrinsicCandidate
8704 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
8705 // for (int i = 0; i < len; i++) {
8706 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
8707 // }
8708 // }
8709 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
8710 XMMRegister tmp1, Register tmp2, KRegister mask) {
8711 Label copy_chars_loop, done, below_threshold, avx3_threshold;
8712 // rsi: src
8713 // rdi: dst
8714 // rdx: len
8715 // rcx: tmp2
8716
8717 // rsi holds start addr of source byte[] to be inflated
8718 // rdi holds start addr of destination char[]
8719 // rdx holds length
8720 assert_different_registers(src, dst, len, tmp2);
8721 movl(tmp2, len);
8722 if ((UseAVX > 2) && // AVX512
8723 VM_Version::supports_avx512vlbw() &&
8724 VM_Version::supports_bmi2()) {
8725
8726 Label copy_32_loop, copy_tail;
8727 Register tmp3_aliased = len;
8728
8729 // if length of the string is less than 16, handle it in an old fashioned way
8730 testl(len, -16);
8731 jcc(Assembler::zero, below_threshold);
8732
8733 testl(len, -1 * AVX3Threshold);
8734 jcc(Assembler::zero, avx3_threshold);
8735
8736 // In order to use only one arithmetic operation for the main loop we use
8737 // this pre-calculation
8738 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
8739 andl(len, -32); // vector count
8740 jccb(Assembler::zero, copy_tail);
8741
8742 lea(src, Address(src, len, Address::times_1));
8743 lea(dst, Address(dst, len, Address::times_2));
8744 negptr(len);
8745
8746
8747 // inflate 32 chars per iter
8748 bind(copy_32_loop);
8749 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
8750 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
8751 addptr(len, 32);
8752 jcc(Assembler::notZero, copy_32_loop);
8753
8754 bind(copy_tail);
8755 // bail out when there is nothing to be done
8756 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
8757 jcc(Assembler::zero, done);
8758
8759 // ~(~0 << length), where length is the # of remaining elements to process
8760 movl(tmp3_aliased, -1);
8761 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
8762 notl(tmp3_aliased);
8763 kmovdl(mask, tmp3_aliased);
8764 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
8765 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
8766
8767 jmp(done);
8768 bind(avx3_threshold);
8769 }
8770 if (UseSSE42Intrinsics) {
8771 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
8772
8773 if (UseAVX > 1) {
8774 andl(tmp2, (16 - 1));
8775 andl(len, -16);
8776 jccb(Assembler::zero, copy_new_tail);
8777 } else {
8778 andl(tmp2, 0x00000007); // tail count (in chars)
8779 andl(len, 0xfffffff8); // vector count (in chars)
8780 jccb(Assembler::zero, copy_tail);
8781 }
8782
8783 // vectored inflation
8784 lea(src, Address(src, len, Address::times_1));
8785 lea(dst, Address(dst, len, Address::times_2));
8786 negptr(len);
8787
8788 if (UseAVX > 1) {
8789 bind(copy_16_loop);
8790 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
8791 vmovdqu(Address(dst, len, Address::times_2), tmp1);
8792 addptr(len, 16);
8793 jcc(Assembler::notZero, copy_16_loop);
8794
8795 bind(below_threshold);
8796 bind(copy_new_tail);
8797 movl(len, tmp2);
8798 andl(tmp2, 0x00000007);
8799 andl(len, 0xFFFFFFF8);
8800 jccb(Assembler::zero, copy_tail);
8801
8802 pmovzxbw(tmp1, Address(src, 0));
8803 movdqu(Address(dst, 0), tmp1);
8804 addptr(src, 8);
8805 addptr(dst, 2 * 8);
8806
8807 jmp(copy_tail, true);
8808 }
8809
8810 // inflate 8 chars per iter
8811 bind(copy_8_loop);
8812 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
8813 movdqu(Address(dst, len, Address::times_2), tmp1);
8814 addptr(len, 8);
8815 jcc(Assembler::notZero, copy_8_loop);
8816
8817 bind(copy_tail);
8818 movl(len, tmp2);
8819
8820 cmpl(len, 4);
8821 jccb(Assembler::less, copy_bytes);
8822
8823 movdl(tmp1, Address(src, 0)); // load 4 byte chars
8824 pmovzxbw(tmp1, tmp1);
8825 movq(Address(dst, 0), tmp1);
8826 subptr(len, 4);
8827 addptr(src, 4);
8828 addptr(dst, 8);
8829
8830 bind(copy_bytes);
8831 } else {
8832 bind(below_threshold);
8833 }
8834
8835 testl(len, len);
8836 jccb(Assembler::zero, done);
8837 lea(src, Address(src, len, Address::times_1));
8838 lea(dst, Address(dst, len, Address::times_2));
8839 negptr(len);
8840
8841 // inflate 1 char per iter
8842 bind(copy_chars_loop);
8843 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
8844 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
8845 increment(len);
8846 jcc(Assembler::notZero, copy_chars_loop);
8847
8848 bind(done);
8849 }
8850
8851 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
8852 switch(type) {
8853 case T_BYTE:
8854 case T_BOOLEAN:
8855 evmovdqub(dst, kmask, src, merge, vector_len);
8856 break;
8857 case T_CHAR:
8858 case T_SHORT:
8859 evmovdquw(dst, kmask, src, merge, vector_len);
8860 break;
8861 case T_INT:
8862 case T_FLOAT:
8863 evmovdqul(dst, kmask, src, merge, vector_len);
8864 break;
8865 case T_LONG:
8866 case T_DOUBLE:
8867 evmovdquq(dst, kmask, src, merge, vector_len);
8868 break;
8869 default:
8870 fatal("Unexpected type argument %s", type2name(type));
8871 break;
8872 }
8873 }
8874
8875
8876 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
8877 switch(type) {
8878 case T_BYTE:
8879 case T_BOOLEAN:
8880 evmovdqub(dst, kmask, src, merge, vector_len);
8881 break;
8882 case T_CHAR:
8883 case T_SHORT:
8884 evmovdquw(dst, kmask, src, merge, vector_len);
8885 break;
8886 case T_INT:
8887 case T_FLOAT:
8888 evmovdqul(dst, kmask, src, merge, vector_len);
8889 break;
8890 case T_LONG:
8891 case T_DOUBLE:
8892 evmovdquq(dst, kmask, src, merge, vector_len);
8893 break;
8894 default:
8895 fatal("Unexpected type argument %s", type2name(type));
8896 break;
8897 }
8898 }
8899
8900 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
8901 switch(type) {
8902 case T_BYTE:
8903 case T_BOOLEAN:
8904 evmovdqub(dst, kmask, src, merge, vector_len);
8905 break;
8906 case T_CHAR:
8907 case T_SHORT:
8908 evmovdquw(dst, kmask, src, merge, vector_len);
8909 break;
8910 case T_INT:
8911 case T_FLOAT:
8912 evmovdqul(dst, kmask, src, merge, vector_len);
8913 break;
8914 case T_LONG:
8915 case T_DOUBLE:
8916 evmovdquq(dst, kmask, src, merge, vector_len);
8917 break;
8918 default:
8919 fatal("Unexpected type argument %s", type2name(type));
8920 break;
8921 }
8922 }
8923
8924 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
8925 switch(masklen) {
8926 case 2:
8927 knotbl(dst, src);
8928 movl(rtmp, 3);
8929 kmovbl(ktmp, rtmp);
8930 kandbl(dst, ktmp, dst);
8931 break;
8932 case 4:
8933 knotbl(dst, src);
8934 movl(rtmp, 15);
8935 kmovbl(ktmp, rtmp);
8936 kandbl(dst, ktmp, dst);
8937 break;
8938 case 8:
8939 knotbl(dst, src);
8940 break;
8941 case 16:
8942 knotwl(dst, src);
8943 break;
8944 case 32:
8945 knotdl(dst, src);
8946 break;
8947 case 64:
8948 knotql(dst, src);
8949 break;
8950 default:
8951 fatal("Unexpected vector length %d", masklen);
8952 break;
8953 }
8954 }
8955
8956 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8957 switch(type) {
8958 case T_BOOLEAN:
8959 case T_BYTE:
8960 kandbl(dst, src1, src2);
8961 break;
8962 case T_CHAR:
8963 case T_SHORT:
8964 kandwl(dst, src1, src2);
8965 break;
8966 case T_INT:
8967 case T_FLOAT:
8968 kanddl(dst, src1, src2);
8969 break;
8970 case T_LONG:
8971 case T_DOUBLE:
8972 kandql(dst, src1, src2);
8973 break;
8974 default:
8975 fatal("Unexpected type argument %s", type2name(type));
8976 break;
8977 }
8978 }
8979
8980 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8981 switch(type) {
8982 case T_BOOLEAN:
8983 case T_BYTE:
8984 korbl(dst, src1, src2);
8985 break;
8986 case T_CHAR:
8987 case T_SHORT:
8988 korwl(dst, src1, src2);
8989 break;
8990 case T_INT:
8991 case T_FLOAT:
8992 kordl(dst, src1, src2);
8993 break;
8994 case T_LONG:
8995 case T_DOUBLE:
8996 korql(dst, src1, src2);
8997 break;
8998 default:
8999 fatal("Unexpected type argument %s", type2name(type));
9000 break;
9001 }
9002 }
9003
9004 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9005 switch(type) {
9006 case T_BOOLEAN:
9007 case T_BYTE:
9008 kxorbl(dst, src1, src2);
9009 break;
9010 case T_CHAR:
9011 case T_SHORT:
9012 kxorwl(dst, src1, src2);
9013 break;
9014 case T_INT:
9015 case T_FLOAT:
9016 kxordl(dst, src1, src2);
9017 break;
9018 case T_LONG:
9019 case T_DOUBLE:
9020 kxorql(dst, src1, src2);
9021 break;
9022 default:
9023 fatal("Unexpected type argument %s", type2name(type));
9024 break;
9025 }
9026 }
9027
9028 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9029 switch(type) {
9030 case T_BOOLEAN:
9031 case T_BYTE:
9032 evpermb(dst, mask, nds, src, merge, vector_len); break;
9033 case T_CHAR:
9034 case T_SHORT:
9035 evpermw(dst, mask, nds, src, merge, vector_len); break;
9036 case T_INT:
9037 case T_FLOAT:
9038 evpermd(dst, mask, nds, src, merge, vector_len); break;
9039 case T_LONG:
9040 case T_DOUBLE:
9041 evpermq(dst, mask, nds, src, merge, vector_len); break;
9042 default:
9043 fatal("Unexpected type argument %s", type2name(type)); break;
9044 }
9045 }
9046
9047 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9048 switch(type) {
9049 case T_BOOLEAN:
9050 case T_BYTE:
9051 evpermb(dst, mask, nds, src, merge, vector_len); break;
9052 case T_CHAR:
9053 case T_SHORT:
9054 evpermw(dst, mask, nds, src, merge, vector_len); break;
9055 case T_INT:
9056 case T_FLOAT:
9057 evpermd(dst, mask, nds, src, merge, vector_len); break;
9058 case T_LONG:
9059 case T_DOUBLE:
9060 evpermq(dst, mask, nds, src, merge, vector_len); break;
9061 default:
9062 fatal("Unexpected type argument %s", type2name(type)); break;
9063 }
9064 }
9065
9066 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9067 switch(type) {
9068 case T_BYTE:
9069 evpminub(dst, mask, nds, src, merge, vector_len); break;
9070 case T_SHORT:
9071 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9072 case T_INT:
9073 evpminud(dst, mask, nds, src, merge, vector_len); break;
9074 case T_LONG:
9075 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9076 default:
9077 fatal("Unexpected type argument %s", type2name(type)); break;
9078 }
9079 }
9080
9081 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9082 switch(type) {
9083 case T_BYTE:
9084 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9085 case T_SHORT:
9086 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9087 case T_INT:
9088 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9089 case T_LONG:
9090 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9091 default:
9092 fatal("Unexpected type argument %s", type2name(type)); break;
9093 }
9094 }
9095
9096 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9097 switch(type) {
9098 case T_BYTE:
9099 evpminub(dst, mask, nds, src, merge, vector_len); break;
9100 case T_SHORT:
9101 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9102 case T_INT:
9103 evpminud(dst, mask, nds, src, merge, vector_len); break;
9104 case T_LONG:
9105 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9106 default:
9107 fatal("Unexpected type argument %s", type2name(type)); break;
9108 }
9109 }
9110
9111 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9112 switch(type) {
9113 case T_BYTE:
9114 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9115 case T_SHORT:
9116 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9117 case T_INT:
9118 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9119 case T_LONG:
9120 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9121 default:
9122 fatal("Unexpected type argument %s", type2name(type)); break;
9123 }
9124 }
9125
9126 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9127 switch(type) {
9128 case T_BYTE:
9129 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9130 case T_SHORT:
9131 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9132 case T_INT:
9133 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9134 case T_LONG:
9135 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9136 case T_FLOAT:
9137 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9138 case T_DOUBLE:
9139 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9140 default:
9141 fatal("Unexpected type argument %s", type2name(type)); break;
9142 }
9143 }
9144
9145 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9146 switch(type) {
9147 case T_BYTE:
9148 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9149 case T_SHORT:
9150 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9151 case T_INT:
9152 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9153 case T_LONG:
9154 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9155 case T_FLOAT:
9156 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9157 case T_DOUBLE:
9158 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9159 default:
9160 fatal("Unexpected type argument %s", type2name(type)); break;
9161 }
9162 }
9163
9164 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9165 switch(type) {
9166 case T_BYTE:
9167 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9168 case T_SHORT:
9169 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9170 case T_INT:
9171 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9172 case T_LONG:
9173 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9174 case T_FLOAT:
9175 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9176 case T_DOUBLE:
9177 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9178 default:
9179 fatal("Unexpected type argument %s", type2name(type)); break;
9180 }
9181 }
9182
9183 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9184 switch(type) {
9185 case T_BYTE:
9186 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9187 case T_SHORT:
9188 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9189 case T_INT:
9190 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9191 case T_LONG:
9192 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9193 case T_FLOAT:
9194 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9195 case T_DOUBLE:
9196 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9197 default:
9198 fatal("Unexpected type argument %s", type2name(type)); break;
9199 }
9200 }
9201
9202 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9203 switch(type) {
9204 case T_INT:
9205 evpxord(dst, mask, nds, src, merge, vector_len); break;
9206 case T_LONG:
9207 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9208 default:
9209 fatal("Unexpected type argument %s", type2name(type)); break;
9210 }
9211 }
9212
9213 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9214 switch(type) {
9215 case T_INT:
9216 evpxord(dst, mask, nds, src, merge, vector_len); break;
9217 case T_LONG:
9218 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9219 default:
9220 fatal("Unexpected type argument %s", type2name(type)); break;
9221 }
9222 }
9223
9224 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9225 switch(type) {
9226 case T_INT:
9227 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9228 case T_LONG:
9229 evporq(dst, mask, nds, src, merge, vector_len); break;
9230 default:
9231 fatal("Unexpected type argument %s", type2name(type)); break;
9232 }
9233 }
9234
9235 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9236 switch(type) {
9237 case T_INT:
9238 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9239 case T_LONG:
9240 evporq(dst, mask, nds, src, merge, vector_len); break;
9241 default:
9242 fatal("Unexpected type argument %s", type2name(type)); break;
9243 }
9244 }
9245
9246 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9247 switch(type) {
9248 case T_INT:
9249 evpandd(dst, mask, nds, src, merge, vector_len); break;
9250 case T_LONG:
9251 evpandq(dst, mask, nds, src, merge, vector_len); break;
9252 default:
9253 fatal("Unexpected type argument %s", type2name(type)); break;
9254 }
9255 }
9256
9257 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9258 switch(type) {
9259 case T_INT:
9260 evpandd(dst, mask, nds, src, merge, vector_len); break;
9261 case T_LONG:
9262 evpandq(dst, mask, nds, src, merge, vector_len); break;
9263 default:
9264 fatal("Unexpected type argument %s", type2name(type)); break;
9265 }
9266 }
9267
9268 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
9269 switch(masklen) {
9270 case 8:
9271 kortestbl(src1, src2);
9272 break;
9273 case 16:
9274 kortestwl(src1, src2);
9275 break;
9276 case 32:
9277 kortestdl(src1, src2);
9278 break;
9279 case 64:
9280 kortestql(src1, src2);
9281 break;
9282 default:
9283 fatal("Unexpected mask length %d", masklen);
9284 break;
9285 }
9286 }
9287
9288
9289 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
9290 switch(masklen) {
9291 case 8:
9292 ktestbl(src1, src2);
9293 break;
9294 case 16:
9295 ktestwl(src1, src2);
9296 break;
9297 case 32:
9298 ktestdl(src1, src2);
9299 break;
9300 case 64:
9301 ktestql(src1, src2);
9302 break;
9303 default:
9304 fatal("Unexpected mask length %d", masklen);
9305 break;
9306 }
9307 }
9308
9309 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9310 switch(type) {
9311 case T_INT:
9312 evprold(dst, mask, src, shift, merge, vlen_enc); break;
9313 case T_LONG:
9314 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
9315 default:
9316 fatal("Unexpected type argument %s", type2name(type)); break;
9317 break;
9318 }
9319 }
9320
9321 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9322 switch(type) {
9323 case T_INT:
9324 evprord(dst, mask, src, shift, merge, vlen_enc); break;
9325 case T_LONG:
9326 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
9327 default:
9328 fatal("Unexpected type argument %s", type2name(type)); break;
9329 }
9330 }
9331
9332 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
9333 switch(type) {
9334 case T_INT:
9335 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
9336 case T_LONG:
9337 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
9338 default:
9339 fatal("Unexpected type argument %s", type2name(type)); break;
9340 }
9341 }
9342
9343 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
9344 switch(type) {
9345 case T_INT:
9346 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
9347 case T_LONG:
9348 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
9349 default:
9350 fatal("Unexpected type argument %s", type2name(type)); break;
9351 }
9352 }
9353
9354 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9355 assert(rscratch != noreg || always_reachable(src), "missing");
9356
9357 if (reachable(src)) {
9358 evpandq(dst, nds, as_Address(src), vector_len);
9359 } else {
9360 lea(rscratch, src);
9361 evpandq(dst, nds, Address(rscratch, 0), vector_len);
9362 }
9363 }
9364
9365 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
9366 assert(rscratch != noreg || always_reachable(src), "missing");
9367
9368 if (reachable(src)) {
9369 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
9370 } else {
9371 lea(rscratch, src);
9372 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
9373 }
9374 }
9375
9376 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9377 assert(rscratch != noreg || always_reachable(src), "missing");
9378
9379 if (reachable(src)) {
9380 evporq(dst, nds, as_Address(src), vector_len);
9381 } else {
9382 lea(rscratch, src);
9383 evporq(dst, nds, Address(rscratch, 0), vector_len);
9384 }
9385 }
9386
9387 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9388 assert(rscratch != noreg || always_reachable(src), "missing");
9389
9390 if (reachable(src)) {
9391 vpshufb(dst, nds, as_Address(src), vector_len);
9392 } else {
9393 lea(rscratch, src);
9394 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
9395 }
9396 }
9397
9398 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9399 assert(rscratch != noreg || always_reachable(src), "missing");
9400
9401 if (reachable(src)) {
9402 Assembler::vpor(dst, nds, as_Address(src), vector_len);
9403 } else {
9404 lea(rscratch, src);
9405 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
9406 }
9407 }
9408
9409 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
9410 assert(rscratch != noreg || always_reachable(src3), "missing");
9411
9412 if (reachable(src3)) {
9413 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
9414 } else {
9415 lea(rscratch, src3);
9416 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
9417 }
9418 }
9419
9420 #if COMPILER2_OR_JVMCI
9421
9422 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
9423 Register length, Register temp, int vec_enc) {
9424 // Computing mask for predicated vector store.
9425 movptr(temp, -1);
9426 bzhiq(temp, temp, length);
9427 kmov(mask, temp);
9428 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
9429 }
9430
9431 // Set memory operation for length "less than" 64 bytes.
9432 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
9433 XMMRegister xmm, KRegister mask, Register length,
9434 Register temp, bool use64byteVector) {
9435 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9436 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
9437 if (!use64byteVector) {
9438 fill32(dst, disp, xmm);
9439 subptr(length, 32 >> shift);
9440 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
9441 } else {
9442 assert(MaxVectorSize == 64, "vector length != 64");
9443 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
9444 }
9445 }
9446
9447
9448 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
9449 XMMRegister xmm, KRegister mask, Register length,
9450 Register temp) {
9451 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9452 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
9453 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
9454 }
9455
9456
9457 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
9458 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9459 vmovdqu(dst, xmm);
9460 }
9461
9462 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
9463 fill32(Address(dst, disp), xmm);
9464 }
9465
9466 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
9467 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9468 if (!use64byteVector) {
9469 fill32(dst, xmm);
9470 fill32(dst.plus_disp(32), xmm);
9471 } else {
9472 evmovdquq(dst, xmm, Assembler::AVX_512bit);
9473 }
9474 }
9475
9476 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
9477 fill64(Address(dst, disp), xmm, use64byteVector);
9478 }
9479
9480 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
9481 Register count, Register rtmp, XMMRegister xtmp) {
9482 Label L_exit;
9483 Label L_fill_start;
9484 Label L_fill_64_bytes;
9485 Label L_fill_96_bytes;
9486 Label L_fill_128_bytes;
9487 Label L_fill_128_bytes_loop;
9488 Label L_fill_128_loop_header;
9489 Label L_fill_128_bytes_loop_header;
9490 Label L_fill_128_bytes_loop_pre_header;
9491 Label L_fill_zmm_sequence;
9492
9493 int shift = -1;
9494 int avx3threshold = VM_Version::avx3_threshold();
9495 switch(type) {
9496 case T_BYTE: shift = 0;
9497 break;
9498 case T_SHORT: shift = 1;
9499 break;
9500 case T_INT: shift = 2;
9501 break;
9502 /* Uncomment when LONG fill stubs are supported.
9503 case T_LONG: shift = 3;
9504 break;
9505 */
9506 default:
9507 fatal("Unhandled type: %s\n", type2name(type));
9508 }
9509
9510 if ((avx3threshold != 0) || (MaxVectorSize == 32)) {
9511
9512 if (MaxVectorSize == 64) {
9513 cmpq(count, avx3threshold >> shift);
9514 jcc(Assembler::greater, L_fill_zmm_sequence);
9515 }
9516
9517 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
9518
9519 bind(L_fill_start);
9520
9521 cmpq(count, 32 >> shift);
9522 jccb(Assembler::greater, L_fill_64_bytes);
9523 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
9524 jmp(L_exit);
9525
9526 bind(L_fill_64_bytes);
9527 cmpq(count, 64 >> shift);
9528 jccb(Assembler::greater, L_fill_96_bytes);
9529 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
9530 jmp(L_exit);
9531
9532 bind(L_fill_96_bytes);
9533 cmpq(count, 96 >> shift);
9534 jccb(Assembler::greater, L_fill_128_bytes);
9535 fill64(to, 0, xtmp);
9536 subq(count, 64 >> shift);
9537 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
9538 jmp(L_exit);
9539
9540 bind(L_fill_128_bytes);
9541 cmpq(count, 128 >> shift);
9542 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
9543 fill64(to, 0, xtmp);
9544 fill32(to, 64, xtmp);
9545 subq(count, 96 >> shift);
9546 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
9547 jmp(L_exit);
9548
9549 bind(L_fill_128_bytes_loop_pre_header);
9550 {
9551 mov(rtmp, to);
9552 andq(rtmp, 31);
9553 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
9554 negq(rtmp);
9555 addq(rtmp, 32);
9556 mov64(r8, -1L);
9557 bzhiq(r8, r8, rtmp);
9558 kmovql(k2, r8);
9559 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
9560 addq(to, rtmp);
9561 shrq(rtmp, shift);
9562 subq(count, rtmp);
9563 }
9564
9565 cmpq(count, 128 >> shift);
9566 jcc(Assembler::less, L_fill_start);
9567
9568 bind(L_fill_128_bytes_loop_header);
9569 subq(count, 128 >> shift);
9570
9571 align32();
9572 bind(L_fill_128_bytes_loop);
9573 fill64(to, 0, xtmp);
9574 fill64(to, 64, xtmp);
9575 addq(to, 128);
9576 subq(count, 128 >> shift);
9577 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
9578
9579 addq(count, 128 >> shift);
9580 jcc(Assembler::zero, L_exit);
9581 jmp(L_fill_start);
9582 }
9583
9584 if (MaxVectorSize == 64) {
9585 // Sequence using 64 byte ZMM register.
9586 Label L_fill_128_bytes_zmm;
9587 Label L_fill_192_bytes_zmm;
9588 Label L_fill_192_bytes_loop_zmm;
9589 Label L_fill_192_bytes_loop_header_zmm;
9590 Label L_fill_192_bytes_loop_pre_header_zmm;
9591 Label L_fill_start_zmm_sequence;
9592
9593 bind(L_fill_zmm_sequence);
9594 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
9595
9596 bind(L_fill_start_zmm_sequence);
9597 cmpq(count, 64 >> shift);
9598 jccb(Assembler::greater, L_fill_128_bytes_zmm);
9599 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
9600 jmp(L_exit);
9601
9602 bind(L_fill_128_bytes_zmm);
9603 cmpq(count, 128 >> shift);
9604 jccb(Assembler::greater, L_fill_192_bytes_zmm);
9605 fill64(to, 0, xtmp, true);
9606 subq(count, 64 >> shift);
9607 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
9608 jmp(L_exit);
9609
9610 bind(L_fill_192_bytes_zmm);
9611 cmpq(count, 192 >> shift);
9612 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
9613 fill64(to, 0, xtmp, true);
9614 fill64(to, 64, xtmp, true);
9615 subq(count, 128 >> shift);
9616 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
9617 jmp(L_exit);
9618
9619 bind(L_fill_192_bytes_loop_pre_header_zmm);
9620 {
9621 movq(rtmp, to);
9622 andq(rtmp, 63);
9623 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
9624 negq(rtmp);
9625 addq(rtmp, 64);
9626 mov64(r8, -1L);
9627 bzhiq(r8, r8, rtmp);
9628 kmovql(k2, r8);
9629 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
9630 addq(to, rtmp);
9631 shrq(rtmp, shift);
9632 subq(count, rtmp);
9633 }
9634
9635 cmpq(count, 192 >> shift);
9636 jcc(Assembler::less, L_fill_start_zmm_sequence);
9637
9638 bind(L_fill_192_bytes_loop_header_zmm);
9639 subq(count, 192 >> shift);
9640
9641 align32();
9642 bind(L_fill_192_bytes_loop_zmm);
9643 fill64(to, 0, xtmp, true);
9644 fill64(to, 64, xtmp, true);
9645 fill64(to, 128, xtmp, true);
9646 addq(to, 192);
9647 subq(count, 192 >> shift);
9648 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
9649
9650 addq(count, 192 >> shift);
9651 jcc(Assembler::zero, L_exit);
9652 jmp(L_fill_start_zmm_sequence);
9653 }
9654 bind(L_exit);
9655 }
9656 #endif //COMPILER2_OR_JVMCI
9657
9658
9659 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
9660 Label done;
9661 cvttss2sil(dst, src);
9662 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
9663 cmpl(dst, 0x80000000); // float_sign_flip
9664 jccb(Assembler::notEqual, done);
9665 subptr(rsp, 8);
9666 movflt(Address(rsp, 0), src);
9667 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9668 pop(dst);
9669 bind(done);
9670 }
9671
9672 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
9673 Label done;
9674 cvttsd2sil(dst, src);
9675 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
9676 cmpl(dst, 0x80000000); // float_sign_flip
9677 jccb(Assembler::notEqual, done);
9678 subptr(rsp, 8);
9679 movdbl(Address(rsp, 0), src);
9680 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
9681 pop(dst);
9682 bind(done);
9683 }
9684
9685 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
9686 Label done;
9687 cvttss2siq(dst, src);
9688 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9689 jccb(Assembler::notEqual, done);
9690 subptr(rsp, 8);
9691 movflt(Address(rsp, 0), src);
9692 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
9693 pop(dst);
9694 bind(done);
9695 }
9696
9697 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
9698 // Following code is line by line assembly translation rounding algorithm.
9699 // Please refer to java.lang.Math.round(float) algorithm for details.
9700 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
9701 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
9702 const int32_t FloatConsts_EXP_BIAS = 127;
9703 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
9704 const int32_t MINUS_32 = 0xFFFFFFE0;
9705 Label L_special_case, L_block1, L_exit;
9706 movl(rtmp, FloatConsts_EXP_BIT_MASK);
9707 movdl(dst, src);
9708 andl(dst, rtmp);
9709 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
9710 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
9711 subl(rtmp, dst);
9712 movl(rcx, rtmp);
9713 movl(dst, MINUS_32);
9714 testl(rtmp, dst);
9715 jccb(Assembler::notEqual, L_special_case);
9716 movdl(dst, src);
9717 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
9718 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
9719 movdl(rtmp, src);
9720 testl(rtmp, rtmp);
9721 jccb(Assembler::greaterEqual, L_block1);
9722 negl(dst);
9723 bind(L_block1);
9724 sarl(dst);
9725 addl(dst, 0x1);
9726 sarl(dst, 0x1);
9727 jmp(L_exit);
9728 bind(L_special_case);
9729 convert_f2i(dst, src);
9730 bind(L_exit);
9731 }
9732
9733 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
9734 // Following code is line by line assembly translation rounding algorithm.
9735 // Please refer to java.lang.Math.round(double) algorithm for details.
9736 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
9737 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
9738 const int64_t DoubleConsts_EXP_BIAS = 1023;
9739 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
9740 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
9741 Label L_special_case, L_block1, L_exit;
9742 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
9743 movq(dst, src);
9744 andq(dst, rtmp);
9745 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
9746 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
9747 subq(rtmp, dst);
9748 movq(rcx, rtmp);
9749 mov64(dst, MINUS_64);
9750 testq(rtmp, dst);
9751 jccb(Assembler::notEqual, L_special_case);
9752 movq(dst, src);
9753 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
9754 andq(dst, rtmp);
9755 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
9756 orq(dst, rtmp);
9757 movq(rtmp, src);
9758 testq(rtmp, rtmp);
9759 jccb(Assembler::greaterEqual, L_block1);
9760 negq(dst);
9761 bind(L_block1);
9762 sarq(dst);
9763 addq(dst, 0x1);
9764 sarq(dst, 0x1);
9765 jmp(L_exit);
9766 bind(L_special_case);
9767 convert_d2l(dst, src);
9768 bind(L_exit);
9769 }
9770
9771 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
9772 Label done;
9773 cvttsd2siq(dst, src);
9774 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9775 jccb(Assembler::notEqual, done);
9776 subptr(rsp, 8);
9777 movdbl(Address(rsp, 0), src);
9778 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
9779 pop(dst);
9780 bind(done);
9781 }
9782
9783 void MacroAssembler::cache_wb(Address line)
9784 {
9785 // 64 bit cpus always support clflush
9786 assert(VM_Version::supports_clflush(), "clflush should be available");
9787 bool optimized = VM_Version::supports_clflushopt();
9788 bool no_evict = VM_Version::supports_clwb();
9789
9790 // prefer clwb (writeback without evict) otherwise
9791 // prefer clflushopt (potentially parallel writeback with evict)
9792 // otherwise fallback on clflush (serial writeback with evict)
9793
9794 if (optimized) {
9795 if (no_evict) {
9796 clwb(line);
9797 } else {
9798 clflushopt(line);
9799 }
9800 } else {
9801 // no need for fence when using CLFLUSH
9802 clflush(line);
9803 }
9804 }
9805
9806 void MacroAssembler::cache_wbsync(bool is_pre)
9807 {
9808 assert(VM_Version::supports_clflush(), "clflush should be available");
9809 bool optimized = VM_Version::supports_clflushopt();
9810 bool no_evict = VM_Version::supports_clwb();
9811
9812 // pick the correct implementation
9813
9814 if (!is_pre && (optimized || no_evict)) {
9815 // need an sfence for post flush when using clflushopt or clwb
9816 // otherwise no no need for any synchroniaztion
9817
9818 sfence();
9819 }
9820 }
9821
9822 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
9823 switch (cond) {
9824 // Note some conditions are synonyms for others
9825 case Assembler::zero: return Assembler::notZero;
9826 case Assembler::notZero: return Assembler::zero;
9827 case Assembler::less: return Assembler::greaterEqual;
9828 case Assembler::lessEqual: return Assembler::greater;
9829 case Assembler::greater: return Assembler::lessEqual;
9830 case Assembler::greaterEqual: return Assembler::less;
9831 case Assembler::below: return Assembler::aboveEqual;
9832 case Assembler::belowEqual: return Assembler::above;
9833 case Assembler::above: return Assembler::belowEqual;
9834 case Assembler::aboveEqual: return Assembler::below;
9835 case Assembler::overflow: return Assembler::noOverflow;
9836 case Assembler::noOverflow: return Assembler::overflow;
9837 case Assembler::negative: return Assembler::positive;
9838 case Assembler::positive: return Assembler::negative;
9839 case Assembler::parity: return Assembler::noParity;
9840 case Assembler::noParity: return Assembler::parity;
9841 }
9842 ShouldNotReachHere(); return Assembler::overflow;
9843 }
9844
9845 // This is simply a call to Thread::current()
9846 void MacroAssembler::get_thread_slow(Register thread) {
9847 if (thread != rax) {
9848 push(rax);
9849 }
9850 push(rdi);
9851 push(rsi);
9852 push(rdx);
9853 push(rcx);
9854 push(r8);
9855 push(r9);
9856 push(r10);
9857 push(r11);
9858
9859 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
9860
9861 pop(r11);
9862 pop(r10);
9863 pop(r9);
9864 pop(r8);
9865 pop(rcx);
9866 pop(rdx);
9867 pop(rsi);
9868 pop(rdi);
9869 if (thread != rax) {
9870 mov(thread, rax);
9871 pop(rax);
9872 }
9873 }
9874
9875 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
9876 Label L_stack_ok;
9877 if (bias == 0) {
9878 testptr(sp, 2 * wordSize - 1);
9879 } else {
9880 // lea(tmp, Address(rsp, bias);
9881 mov(tmp, sp);
9882 addptr(tmp, bias);
9883 testptr(tmp, 2 * wordSize - 1);
9884 }
9885 jcc(Assembler::equal, L_stack_ok);
9886 block_comment(msg);
9887 stop(msg);
9888 bind(L_stack_ok);
9889 }
9890
9891 // Implements fast-locking.
9892 //
9893 // obj: the object to be locked
9894 // reg_rax: rax
9895 // thread: the thread which attempts to lock obj
9896 // tmp: a temporary register
9897 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register reg_rax, Register tmp, Label& slow) {
9898 Register thread = r15_thread;
9899
9900 assert(reg_rax == rax, "");
9901 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
9902
9903 Label push;
9904 const Register top = tmp;
9905
9906 // Preload the markWord. It is important that this is the first
9907 // instruction emitted as it is part of C1's null check semantics.
9908 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
9909
9910 if (UseObjectMonitorTable) {
9911 // Clear cache in case fast locking succeeds or we need to take the slow-path.
9912 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
9913 }
9914
9915 if (DiagnoseSyncOnValueBasedClasses != 0) {
9916 load_klass(tmp, obj, rscratch1);
9917 testb(Address(tmp, Klass::misc_flags_offset()), KlassFlags::_misc_is_value_based_class);
9918 jcc(Assembler::notZero, slow);
9919 }
9920
9921 // Load top.
9922 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
9923
9924 // Check if the lock-stack is full.
9925 cmpl(top, LockStack::end_offset());
9926 jcc(Assembler::greaterEqual, slow);
9927
9928 // Check for recursion.
9929 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
9930 jcc(Assembler::equal, push);
9931
9932 // Check header for monitor (0b10).
9933 testptr(reg_rax, markWord::monitor_value);
9934 jcc(Assembler::notZero, slow);
9935
9936 // Try to lock. Transition lock bits 0b01 => 0b00
9937 movptr(tmp, reg_rax);
9938 andptr(tmp, ~(int32_t)markWord::unlocked_value);
9939 orptr(reg_rax, markWord::unlocked_value);
9940 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
9941 jcc(Assembler::notEqual, slow);
9942
9943 // Restore top, CAS clobbers register.
9944 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
9945
9946 bind(push);
9947 // After successful lock, push object on lock-stack.
9948 movptr(Address(thread, top), obj);
9949 incrementl(top, oopSize);
9950 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
9951 }
9952
9953 // Implements fast-unlocking.
9954 //
9955 // obj: the object to be unlocked
9956 // reg_rax: rax
9957 // thread: the thread
9958 // tmp: a temporary register
9959 void MacroAssembler::fast_unlock(Register obj, Register reg_rax, Register tmp, Label& slow) {
9960 Register thread = r15_thread;
9961
9962 assert(reg_rax == rax, "");
9963 assert_different_registers(obj, reg_rax, thread, tmp);
9964
9965 Label unlocked, push_and_slow;
9966 const Register top = tmp;
9967
9968 // Check if obj is top of lock-stack.
9969 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
9970 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
9971 jcc(Assembler::notEqual, slow);
9972
9973 // Pop lock-stack.
9974 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
9975 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
9976
9977 // Check if recursive.
9978 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
9979 jcc(Assembler::equal, unlocked);
9980
9981 // Not recursive. Check header for monitor (0b10).
9982 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
9983 testptr(reg_rax, markWord::monitor_value);
9984 jcc(Assembler::notZero, push_and_slow);
9985
9986 #ifdef ASSERT
9987 // Check header not unlocked (0b01).
9988 Label not_unlocked;
9989 testptr(reg_rax, markWord::unlocked_value);
9990 jcc(Assembler::zero, not_unlocked);
9991 stop("fast_unlock already unlocked");
9992 bind(not_unlocked);
9993 #endif
9994
9995 // Try to unlock. Transition lock bits 0b00 => 0b01
9996 movptr(tmp, reg_rax);
9997 orptr(tmp, markWord::unlocked_value);
9998 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
9999 jcc(Assembler::equal, unlocked);
10000
10001 bind(push_and_slow);
10002 // Restore lock-stack and handle the unlock in runtime.
10003 #ifdef ASSERT
10004 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10005 movptr(Address(thread, top), obj);
10006 #endif
10007 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10008 jmp(slow);
10009
10010 bind(unlocked);
10011 }
10012
10013 // Saves legacy GPRs state on stack.
10014 void MacroAssembler::save_legacy_gprs() {
10015 subq(rsp, 16 * wordSize);
10016 movq(Address(rsp, 15 * wordSize), rax);
10017 movq(Address(rsp, 14 * wordSize), rcx);
10018 movq(Address(rsp, 13 * wordSize), rdx);
10019 movq(Address(rsp, 12 * wordSize), rbx);
10020 movq(Address(rsp, 10 * wordSize), rbp);
10021 movq(Address(rsp, 9 * wordSize), rsi);
10022 movq(Address(rsp, 8 * wordSize), rdi);
10023 movq(Address(rsp, 7 * wordSize), r8);
10024 movq(Address(rsp, 6 * wordSize), r9);
10025 movq(Address(rsp, 5 * wordSize), r10);
10026 movq(Address(rsp, 4 * wordSize), r11);
10027 movq(Address(rsp, 3 * wordSize), r12);
10028 movq(Address(rsp, 2 * wordSize), r13);
10029 movq(Address(rsp, wordSize), r14);
10030 movq(Address(rsp, 0), r15);
10031 }
10032
10033 // Resotres back legacy GPRs state from stack.
10034 void MacroAssembler::restore_legacy_gprs() {
10035 movq(r15, Address(rsp, 0));
10036 movq(r14, Address(rsp, wordSize));
10037 movq(r13, Address(rsp, 2 * wordSize));
10038 movq(r12, Address(rsp, 3 * wordSize));
10039 movq(r11, Address(rsp, 4 * wordSize));
10040 movq(r10, Address(rsp, 5 * wordSize));
10041 movq(r9, Address(rsp, 6 * wordSize));
10042 movq(r8, Address(rsp, 7 * wordSize));
10043 movq(rdi, Address(rsp, 8 * wordSize));
10044 movq(rsi, Address(rsp, 9 * wordSize));
10045 movq(rbp, Address(rsp, 10 * wordSize));
10046 movq(rbx, Address(rsp, 12 * wordSize));
10047 movq(rdx, Address(rsp, 13 * wordSize));
10048 movq(rcx, Address(rsp, 14 * wordSize));
10049 movq(rax, Address(rsp, 15 * wordSize));
10050 addq(rsp, 16 * wordSize);
10051 }
10052
10053 void MacroAssembler::load_aotrc_address(Register reg, address a) {
10054 #if INCLUDE_CDS
10055 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
10056 if (AOTCodeCache::is_on_for_dump()) {
10057 // all aotrc field addresses should be registered in the AOTCodeCache address table
10058 lea(reg, ExternalAddress(a));
10059 } else {
10060 mov64(reg, (uint64_t)a);
10061 }
10062 #else
10063 ShouldNotReachHere();
10064 #endif
10065 }
10066
10067 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10068 if (VM_Version::supports_apx_f()) {
10069 esetzucc(comparison, dst);
10070 } else {
10071 setb(comparison, dst);
10072 movzbl(dst, dst);
10073 }
10074 }