1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.hpp"
26 #include "asm/assembler.inline.hpp"
27 #include "code/aotCodeCache.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "crc32c.h"
32 #include "gc/shared/barrierSet.hpp"
33 #include "gc/shared/barrierSetAssembler.hpp"
34 #include "gc/shared/collectedHeap.inline.hpp"
35 #include "gc/shared/tlab_globals.hpp"
36 #include "interpreter/bytecodeHistogram.hpp"
37 #include "interpreter/interpreter.hpp"
38 #include "interpreter/interpreterRuntime.hpp"
39 #include "jvm.h"
40 #include "memory/resourceArea.hpp"
41 #include "memory/universe.hpp"
42 #include "oops/accessDecorators.hpp"
43 #include "oops/compressedKlass.inline.hpp"
44 #include "oops/compressedOops.inline.hpp"
45 #include "oops/klass.inline.hpp"
46 #include "prims/methodHandles.hpp"
47 #include "runtime/continuation.hpp"
48 #include "runtime/interfaceSupport.inline.hpp"
49 #include "runtime/javaThread.hpp"
50 #include "runtime/jniHandles.hpp"
51 #include "runtime/objectMonitor.hpp"
52 #include "runtime/os.hpp"
53 #include "runtime/safepoint.hpp"
54 #include "runtime/safepointMechanism.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/checkedCast.hpp"
58 #include "utilities/macros.hpp"
59
60 #ifdef PRODUCT
61 #define BLOCK_COMMENT(str) /* nothing */
62 #define STOP(error) stop(error)
63 #else
64 #define BLOCK_COMMENT(str) block_comment(str)
65 #define STOP(error) block_comment(error); stop(error)
66 #endif
67
68 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
69
70 #ifdef ASSERT
71 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
72 #endif
73
74 static const Assembler::Condition reverse[] = {
75 Assembler::noOverflow /* overflow = 0x0 */ ,
76 Assembler::overflow /* noOverflow = 0x1 */ ,
77 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
78 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
79 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
80 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
81 Assembler::above /* belowEqual = 0x6 */ ,
82 Assembler::belowEqual /* above = 0x7 */ ,
83 Assembler::positive /* negative = 0x8 */ ,
84 Assembler::negative /* positive = 0x9 */ ,
85 Assembler::noParity /* parity = 0xa */ ,
86 Assembler::parity /* noParity = 0xb */ ,
87 Assembler::greaterEqual /* less = 0xc */ ,
88 Assembler::less /* greaterEqual = 0xd */ ,
89 Assembler::greater /* lessEqual = 0xe */ ,
90 Assembler::lessEqual /* greater = 0xf, */
91
92 };
93
94
95 // Implementation of MacroAssembler
96
97 Address MacroAssembler::as_Address(AddressLiteral adr) {
98 // amd64 always does this as a pc-rel
99 // we can be absolute or disp based on the instruction type
100 // jmp/call are displacements others are absolute
101 assert(!adr.is_lval(), "must be rval");
102 assert(reachable(adr), "must be");
103 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
104
105 }
106
107 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
108 AddressLiteral base = adr.base();
109 lea(rscratch, base);
110 Address index = adr.index();
111 assert(index._disp == 0, "must not have disp"); // maybe it can?
112 Address array(rscratch, index._index, index._scale, index._disp);
113 return array;
114 }
115
116 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
117 Label L, E;
118
119 #ifdef _WIN64
120 // Windows always allocates space for it's register args
121 assert(num_args <= 4, "only register arguments supported");
122 subq(rsp, frame::arg_reg_save_area_bytes);
123 #endif
124
125 // Align stack if necessary
126 testl(rsp, 15);
127 jcc(Assembler::zero, L);
128
129 subq(rsp, 8);
130 call(RuntimeAddress(entry_point));
131 addq(rsp, 8);
132 jmp(E);
133
134 bind(L);
135 call(RuntimeAddress(entry_point));
136
137 bind(E);
138
139 #ifdef _WIN64
140 // restore stack pointer
141 addq(rsp, frame::arg_reg_save_area_bytes);
142 #endif
143 }
144
145 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
146 assert(!src2.is_lval(), "should use cmpptr");
147 assert(rscratch != noreg || always_reachable(src2), "missing");
148
149 if (reachable(src2)) {
150 cmpq(src1, as_Address(src2));
151 } else {
152 lea(rscratch, src2);
153 Assembler::cmpq(src1, Address(rscratch, 0));
154 }
155 }
156
157 int MacroAssembler::corrected_idivq(Register reg) {
158 // Full implementation of Java ldiv and lrem; checks for special
159 // case as described in JVM spec., p.243 & p.271. The function
160 // returns the (pc) offset of the idivl instruction - may be needed
161 // for implicit exceptions.
162 //
163 // normal case special case
164 //
165 // input : rax: dividend min_long
166 // reg: divisor (may not be eax/edx) -1
167 //
168 // output: rax: quotient (= rax idiv reg) min_long
169 // rdx: remainder (= rax irem reg) 0
170 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
171 static const int64_t min_long = 0x8000000000000000;
172 Label normal_case, special_case;
173
174 // check for special case
175 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
176 jcc(Assembler::notEqual, normal_case);
177 xorl(rdx, rdx); // prepare rdx for possible special case (where
178 // remainder = 0)
179 cmpq(reg, -1);
180 jcc(Assembler::equal, special_case);
181
182 // handle normal case
183 bind(normal_case);
184 cdqq();
185 int idivq_offset = offset();
186 idivq(reg);
187
188 // normal and special case exit
189 bind(special_case);
190
191 return idivq_offset;
192 }
193
194 void MacroAssembler::decrementq(Register reg, int value) {
195 if (value == min_jint) { subq(reg, value); return; }
196 if (value < 0) { incrementq(reg, -value); return; }
197 if (value == 0) { ; return; }
198 if (value == 1 && UseIncDec) { decq(reg) ; return; }
199 /* else */ { subq(reg, value) ; return; }
200 }
201
202 void MacroAssembler::decrementq(Address dst, int value) {
203 if (value == min_jint) { subq(dst, value); return; }
204 if (value < 0) { incrementq(dst, -value); return; }
205 if (value == 0) { ; return; }
206 if (value == 1 && UseIncDec) { decq(dst) ; return; }
207 /* else */ { subq(dst, value) ; return; }
208 }
209
210 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
211 assert(rscratch != noreg || always_reachable(dst), "missing");
212
213 if (reachable(dst)) {
214 incrementq(as_Address(dst));
215 } else {
216 lea(rscratch, dst);
217 incrementq(Address(rscratch, 0));
218 }
219 }
220
221 void MacroAssembler::incrementq(Register reg, int value) {
222 if (value == min_jint) { addq(reg, value); return; }
223 if (value < 0) { decrementq(reg, -value); return; }
224 if (value == 0) { ; return; }
225 if (value == 1 && UseIncDec) { incq(reg) ; return; }
226 /* else */ { addq(reg, value) ; return; }
227 }
228
229 void MacroAssembler::incrementq(Address dst, int value) {
230 if (value == min_jint) { addq(dst, value); return; }
231 if (value < 0) { decrementq(dst, -value); return; }
232 if (value == 0) { ; return; }
233 if (value == 1 && UseIncDec) { incq(dst) ; return; }
234 /* else */ { addq(dst, value) ; return; }
235 }
236
237 // 32bit can do a case table jump in one instruction but we no longer allow the base
238 // to be installed in the Address class
239 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
240 lea(rscratch, entry.base());
241 Address dispatch = entry.index();
242 assert(dispatch._base == noreg, "must be");
243 dispatch._base = rscratch;
244 jmp(dispatch);
245 }
246
247 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
248 ShouldNotReachHere(); // 64bit doesn't use two regs
249 cmpq(x_lo, y_lo);
250 }
251
252 void MacroAssembler::lea(Register dst, AddressLiteral src) {
253 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
254 }
255
256 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
257 lea(rscratch, adr);
258 movptr(dst, rscratch);
259 }
260
261 void MacroAssembler::leave() {
262 // %%% is this really better? Why not on 32bit too?
263 emit_int8((unsigned char)0xC9); // LEAVE
264 }
265
266 void MacroAssembler::lneg(Register hi, Register lo) {
267 ShouldNotReachHere(); // 64bit doesn't use two regs
268 negq(lo);
269 }
270
271 void MacroAssembler::movoop(Register dst, jobject obj) {
272 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
273 }
274
275 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
276 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
277 movq(dst, rscratch);
278 }
279
280 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
281 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
282 }
283
284 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
285 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
286 movq(dst, rscratch);
287 }
288
289 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
290 if (src.is_lval()) {
291 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
292 } else {
293 if (reachable(src)) {
294 movq(dst, as_Address(src));
295 } else {
296 lea(dst, src);
297 movq(dst, Address(dst, 0));
298 }
299 }
300 }
301
302 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
303 movq(as_Address(dst, rscratch), src);
304 }
305
306 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
307 movq(dst, as_Address(src, dst /*rscratch*/));
308 }
309
310 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
311 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
312 if (is_simm32(src)) {
313 movptr(dst, checked_cast<int32_t>(src));
314 } else {
315 mov64(rscratch, src);
316 movq(dst, rscratch);
317 }
318 }
319
320 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
321 movoop(rscratch, obj);
322 push(rscratch);
323 }
324
325 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
326 mov_metadata(rscratch, obj);
327 push(rscratch);
328 }
329
330 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
331 lea(rscratch, src);
332 if (src.is_lval()) {
333 push(rscratch);
334 } else {
335 pushq(Address(rscratch, 0));
336 }
337 }
338
339 static void pass_arg0(MacroAssembler* masm, Register arg) {
340 if (c_rarg0 != arg ) {
341 masm->mov(c_rarg0, arg);
342 }
343 }
344
345 static void pass_arg1(MacroAssembler* masm, Register arg) {
346 if (c_rarg1 != arg ) {
347 masm->mov(c_rarg1, arg);
348 }
349 }
350
351 static void pass_arg2(MacroAssembler* masm, Register arg) {
352 if (c_rarg2 != arg ) {
353 masm->mov(c_rarg2, arg);
354 }
355 }
356
357 static void pass_arg3(MacroAssembler* masm, Register arg) {
358 if (c_rarg3 != arg ) {
359 masm->mov(c_rarg3, arg);
360 }
361 }
362
363 void MacroAssembler::stop(const char* msg) {
364 if (ShowMessageBoxOnError) {
365 address rip = pc();
366 pusha(); // get regs on stack
367 lea(c_rarg1, InternalAddress(rip));
368 movq(c_rarg2, rsp); // pass pointer to regs array
369 }
370 // Skip AOT caching C strings in scratch buffer.
371 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
372 lea(c_rarg0, ExternalAddress((address) str));
373 andq(rsp, -16); // align stack as required by ABI
374 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
375 hlt();
376 }
377
378 void MacroAssembler::warn(const char* msg) {
379 push(rbp);
380 movq(rbp, rsp);
381 andq(rsp, -16); // align stack as required by push_CPU_state and call
382 push_CPU_state(); // keeps alignment at 16 bytes
383
384 #ifdef _WIN64
385 // Windows always allocates space for its register args
386 subq(rsp, frame::arg_reg_save_area_bytes);
387 #endif
388 lea(c_rarg0, ExternalAddress((address) msg));
389 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
390
391 #ifdef _WIN64
392 // restore stack pointer
393 addq(rsp, frame::arg_reg_save_area_bytes);
394 #endif
395 pop_CPU_state();
396 mov(rsp, rbp);
397 pop(rbp);
398 }
399
400 void MacroAssembler::print_state() {
401 address rip = pc();
402 pusha(); // get regs on stack
403 push(rbp);
404 movq(rbp, rsp);
405 andq(rsp, -16); // align stack as required by push_CPU_state and call
406 push_CPU_state(); // keeps alignment at 16 bytes
407
408 lea(c_rarg0, InternalAddress(rip));
409 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
410 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
411
412 pop_CPU_state();
413 mov(rsp, rbp);
414 pop(rbp);
415 popa();
416 }
417
418 #ifndef PRODUCT
419 extern "C" void findpc(intptr_t x);
420 #endif
421
422 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
423 // In order to get locks to work, we need to fake a in_VM state
424 if (ShowMessageBoxOnError) {
425 JavaThread* thread = JavaThread::current();
426 JavaThreadState saved_state = thread->thread_state();
427 thread->set_thread_state(_thread_in_vm);
428 #ifndef PRODUCT
429 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
430 ttyLocker ttyl;
431 BytecodeCounter::print();
432 }
433 #endif
434 // To see where a verify_oop failed, get $ebx+40/X for this frame.
435 // XXX correct this offset for amd64
436 // This is the value of eip which points to where verify_oop will return.
437 if (os::message_box(msg, "Execution stopped, print registers?")) {
438 print_state64(pc, regs);
439 BREAKPOINT;
440 }
441 }
442 fatal("DEBUG MESSAGE: %s", msg);
443 }
444
445 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
446 ttyLocker ttyl;
447 DebuggingContext debugging{};
448 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
449 #ifndef PRODUCT
450 tty->cr();
451 findpc(pc);
452 tty->cr();
453 #endif
454 #define PRINT_REG(rax, value) \
455 { tty->print("%s = ", #rax); os::print_location(tty, value); }
456 PRINT_REG(rax, regs[15]);
457 PRINT_REG(rbx, regs[12]);
458 PRINT_REG(rcx, regs[14]);
459 PRINT_REG(rdx, regs[13]);
460 PRINT_REG(rdi, regs[8]);
461 PRINT_REG(rsi, regs[9]);
462 PRINT_REG(rbp, regs[10]);
463 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
464 PRINT_REG(rsp, (intptr_t)(®s[16]));
465 PRINT_REG(r8 , regs[7]);
466 PRINT_REG(r9 , regs[6]);
467 PRINT_REG(r10, regs[5]);
468 PRINT_REG(r11, regs[4]);
469 PRINT_REG(r12, regs[3]);
470 PRINT_REG(r13, regs[2]);
471 PRINT_REG(r14, regs[1]);
472 PRINT_REG(r15, regs[0]);
473 #undef PRINT_REG
474 // Print some words near the top of the stack.
475 int64_t* rsp = ®s[16];
476 int64_t* dump_sp = rsp;
477 for (int col1 = 0; col1 < 8; col1++) {
478 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
479 os::print_location(tty, *dump_sp++);
480 }
481 for (int row = 0; row < 25; row++) {
482 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
483 for (int col = 0; col < 4; col++) {
484 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
485 }
486 tty->cr();
487 }
488 // Print some instructions around pc:
489 Disassembler::decode((address)pc-64, (address)pc);
490 tty->print_cr("--------");
491 Disassembler::decode((address)pc, (address)pc+32);
492 }
493
494 // The java_calling_convention describes stack locations as ideal slots on
495 // a frame with no abi restrictions. Since we must observe abi restrictions
496 // (like the placement of the register window) the slots must be biased by
497 // the following value.
498 static int reg2offset_in(VMReg r) {
499 // Account for saved rbp and return address
500 // This should really be in_preserve_stack_slots
501 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
502 }
503
504 static int reg2offset_out(VMReg r) {
505 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
506 }
507
508 // A long move
509 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
510
511 // The calling conventions assures us that each VMregpair is either
512 // all really one physical register or adjacent stack slots.
513
514 if (src.is_single_phys_reg() ) {
515 if (dst.is_single_phys_reg()) {
516 if (dst.first() != src.first()) {
517 mov(dst.first()->as_Register(), src.first()->as_Register());
518 }
519 } else {
520 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
521 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
522 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
523 }
524 } else if (dst.is_single_phys_reg()) {
525 assert(src.is_single_reg(), "not a stack pair");
526 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
527 } else {
528 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
529 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
530 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
531 }
532 }
533
534 // A double move
535 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
536
537 // The calling conventions assures us that each VMregpair is either
538 // all really one physical register or adjacent stack slots.
539
540 if (src.is_single_phys_reg() ) {
541 if (dst.is_single_phys_reg()) {
542 // In theory these overlap but the ordering is such that this is likely a nop
543 if ( src.first() != dst.first()) {
544 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
545 }
546 } else {
547 assert(dst.is_single_reg(), "not a stack pair");
548 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
549 }
550 } else if (dst.is_single_phys_reg()) {
551 assert(src.is_single_reg(), "not a stack pair");
552 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
553 } else {
554 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
555 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
556 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
557 }
558 }
559
560
561 // A float arg may have to do float reg int reg conversion
562 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
563 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
564
565 // The calling conventions assures us that each VMregpair is either
566 // all really one physical register or adjacent stack slots.
567
568 if (src.first()->is_stack()) {
569 if (dst.first()->is_stack()) {
570 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
571 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
572 } else {
573 // stack to reg
574 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
575 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
576 }
577 } else if (dst.first()->is_stack()) {
578 // reg to stack
579 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
580 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
581 } else {
582 // reg to reg
583 // In theory these overlap but the ordering is such that this is likely a nop
584 if ( src.first() != dst.first()) {
585 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
586 }
587 }
588 }
589
590 // On 64 bit we will store integer like items to the stack as
591 // 64 bits items (x86_32/64 abi) even though java would only store
592 // 32bits for a parameter. On 32bit it will simply be 32 bits
593 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
594 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
595 if (src.first()->is_stack()) {
596 if (dst.first()->is_stack()) {
597 // stack to stack
598 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
599 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
600 } else {
601 // stack to reg
602 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
603 }
604 } else if (dst.first()->is_stack()) {
605 // reg to stack
606 // Do we really have to sign extend???
607 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
608 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
609 } else {
610 // Do we really have to sign extend???
611 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
612 if (dst.first() != src.first()) {
613 movq(dst.first()->as_Register(), src.first()->as_Register());
614 }
615 }
616 }
617
618 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
619 if (src.first()->is_stack()) {
620 if (dst.first()->is_stack()) {
621 // stack to stack
622 movq(rax, Address(rbp, reg2offset_in(src.first())));
623 movq(Address(rsp, reg2offset_out(dst.first())), rax);
624 } else {
625 // stack to reg
626 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
627 }
628 } else if (dst.first()->is_stack()) {
629 // reg to stack
630 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
631 } else {
632 if (dst.first() != src.first()) {
633 movq(dst.first()->as_Register(), src.first()->as_Register());
634 }
635 }
636 }
637
638 // An oop arg. Must pass a handle not the oop itself
639 void MacroAssembler::object_move(OopMap* map,
640 int oop_handle_offset,
641 int framesize_in_slots,
642 VMRegPair src,
643 VMRegPair dst,
644 bool is_receiver,
645 int* receiver_offset) {
646
647 // must pass a handle. First figure out the location we use as a handle
648
649 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
650
651 // See if oop is null if it is we need no handle
652
653 if (src.first()->is_stack()) {
654
655 // Oop is already on the stack as an argument
656 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
657 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
658 if (is_receiver) {
659 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
660 }
661
662 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
663 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
664 // conditionally move a null
665 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
666 } else {
667
668 // Oop is in a register we must store it to the space we reserve
669 // on the stack for oop_handles and pass a handle if oop is non-null
670
671 const Register rOop = src.first()->as_Register();
672 int oop_slot;
673 if (rOop == j_rarg0)
674 oop_slot = 0;
675 else if (rOop == j_rarg1)
676 oop_slot = 1;
677 else if (rOop == j_rarg2)
678 oop_slot = 2;
679 else if (rOop == j_rarg3)
680 oop_slot = 3;
681 else if (rOop == j_rarg4)
682 oop_slot = 4;
683 else {
684 assert(rOop == j_rarg5, "wrong register");
685 oop_slot = 5;
686 }
687
688 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
689 int offset = oop_slot*VMRegImpl::stack_slot_size;
690
691 map->set_oop(VMRegImpl::stack2reg(oop_slot));
692 // Store oop in handle area, may be null
693 movptr(Address(rsp, offset), rOop);
694 if (is_receiver) {
695 *receiver_offset = offset;
696 }
697
698 cmpptr(rOop, NULL_WORD);
699 lea(rHandle, Address(rsp, offset));
700 // conditionally move a null from the handle area where it was just stored
701 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
702 }
703
704 // If arg is on the stack then place it otherwise it is already in correct reg.
705 if (dst.first()->is_stack()) {
706 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
707 }
708 }
709
710 void MacroAssembler::addptr(Register dst, int32_t imm32) {
711 addq(dst, imm32);
712 }
713
714 void MacroAssembler::addptr(Register dst, Register src) {
715 addq(dst, src);
716 }
717
718 void MacroAssembler::addptr(Address dst, Register src) {
719 addq(dst, src);
720 }
721
722 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
723 assert(rscratch != noreg || always_reachable(src), "missing");
724
725 if (reachable(src)) {
726 Assembler::addsd(dst, as_Address(src));
727 } else {
728 lea(rscratch, src);
729 Assembler::addsd(dst, Address(rscratch, 0));
730 }
731 }
732
733 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
734 assert(rscratch != noreg || always_reachable(src), "missing");
735
736 if (reachable(src)) {
737 addss(dst, as_Address(src));
738 } else {
739 lea(rscratch, src);
740 addss(dst, Address(rscratch, 0));
741 }
742 }
743
744 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
745 assert(rscratch != noreg || always_reachable(src), "missing");
746
747 if (reachable(src)) {
748 Assembler::addpd(dst, as_Address(src));
749 } else {
750 lea(rscratch, src);
751 Assembler::addpd(dst, Address(rscratch, 0));
752 }
753 }
754
755 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
756 // Stub code is generated once and never copied.
757 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
758 void MacroAssembler::align64() {
759 align(64, (uint)(uintptr_t)pc());
760 }
761
762 void MacroAssembler::align32() {
763 align(32, (uint)(uintptr_t)pc());
764 }
765
766 void MacroAssembler::align(uint modulus) {
767 // 8273459: Ensure alignment is possible with current segment alignment
768 assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
769 align(modulus, offset());
770 }
771
772 void MacroAssembler::align(uint modulus, uint target) {
773 if (target % modulus != 0) {
774 nop(modulus - (target % modulus));
775 }
776 }
777
778 void MacroAssembler::push_f(XMMRegister r) {
779 subptr(rsp, wordSize);
780 movflt(Address(rsp, 0), r);
781 }
782
783 void MacroAssembler::pop_f(XMMRegister r) {
784 movflt(r, Address(rsp, 0));
785 addptr(rsp, wordSize);
786 }
787
788 void MacroAssembler::push_d(XMMRegister r) {
789 subptr(rsp, 2 * wordSize);
790 movdbl(Address(rsp, 0), r);
791 }
792
793 void MacroAssembler::pop_d(XMMRegister r) {
794 movdbl(r, Address(rsp, 0));
795 addptr(rsp, 2 * Interpreter::stackElementSize);
796 }
797
798 void MacroAssembler::push_ppx(Register src) {
799 if (VM_Version::supports_apx_f()) {
800 pushp(src);
801 } else {
802 Assembler::push(src);
803 }
804 }
805
806 void MacroAssembler::pop_ppx(Register dst) {
807 if (VM_Version::supports_apx_f()) {
808 popp(dst);
809 } else {
810 Assembler::pop(dst);
811 }
812 }
813
814 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
815 // Used in sign-masking with aligned address.
816 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
817 assert(rscratch != noreg || always_reachable(src), "missing");
818
819 if (UseAVX > 2 &&
820 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
821 (dst->encoding() >= 16)) {
822 vpand(dst, dst, src, AVX_512bit, rscratch);
823 } else if (reachable(src)) {
824 Assembler::andpd(dst, as_Address(src));
825 } else {
826 lea(rscratch, src);
827 Assembler::andpd(dst, Address(rscratch, 0));
828 }
829 }
830
831 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
832 // Used in sign-masking with aligned address.
833 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
834 assert(rscratch != noreg || always_reachable(src), "missing");
835
836 if (reachable(src)) {
837 Assembler::andps(dst, as_Address(src));
838 } else {
839 lea(rscratch, src);
840 Assembler::andps(dst, Address(rscratch, 0));
841 }
842 }
843
844 void MacroAssembler::andptr(Register dst, int32_t imm32) {
845 andq(dst, imm32);
846 }
847
848 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
849 assert(rscratch != noreg || always_reachable(src), "missing");
850
851 if (reachable(src)) {
852 andq(dst, as_Address(src));
853 } else {
854 lea(rscratch, src);
855 andq(dst, Address(rscratch, 0));
856 }
857 }
858
859 void MacroAssembler::atomic_incl(Address counter_addr) {
860 lock();
861 incrementl(counter_addr);
862 }
863
864 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
865 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
866
867 if (reachable(counter_addr)) {
868 atomic_incl(as_Address(counter_addr));
869 } else {
870 lea(rscratch, counter_addr);
871 atomic_incl(Address(rscratch, 0));
872 }
873 }
874
875 void MacroAssembler::atomic_incq(Address counter_addr) {
876 lock();
877 incrementq(counter_addr);
878 }
879
880 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
881 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
882
883 if (reachable(counter_addr)) {
884 atomic_incq(as_Address(counter_addr));
885 } else {
886 lea(rscratch, counter_addr);
887 atomic_incq(Address(rscratch, 0));
888 }
889 }
890
891 // Writes to stack successive pages until offset reached to check for
892 // stack overflow + shadow pages. This clobbers tmp.
893 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
894 movptr(tmp, rsp);
895 // Bang stack for total size given plus shadow page size.
896 // Bang one page at a time because large size can bang beyond yellow and
897 // red zones.
898 Label loop;
899 bind(loop);
900 movl(Address(tmp, (-(int)os::vm_page_size())), size );
901 subptr(tmp, (int)os::vm_page_size());
902 subl(size, (int)os::vm_page_size());
903 jcc(Assembler::greater, loop);
904
905 // Bang down shadow pages too.
906 // At this point, (tmp-0) is the last address touched, so don't
907 // touch it again. (It was touched as (tmp-pagesize) but then tmp
908 // was post-decremented.) Skip this address by starting at i=1, and
909 // touch a few more pages below. N.B. It is important to touch all
910 // the way down including all pages in the shadow zone.
911 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
912 // this could be any sized move but this is can be a debugging crumb
913 // so the bigger the better.
914 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
915 }
916 }
917
918 void MacroAssembler::reserved_stack_check() {
919 // testing if reserved zone needs to be enabled
920 Label no_reserved_zone_enabling;
921
922 cmpptr(rsp, Address(r15_thread, JavaThread::reserved_stack_activation_offset()));
923 jcc(Assembler::below, no_reserved_zone_enabling);
924
925 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), r15_thread);
926 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
927 should_not_reach_here();
928
929 bind(no_reserved_zone_enabling);
930 }
931
932 void MacroAssembler::c2bool(Register x) {
933 // implements x == 0 ? 0 : 1
934 // note: must only look at least-significant byte of x
935 // since C-style booleans are stored in one byte
936 // only! (was bug)
937 andl(x, 0xFF);
938 setb(Assembler::notZero, x);
939 }
940
941 // Wouldn't need if AddressLiteral version had new name
942 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
943 Assembler::call(L, rtype);
944 }
945
946 void MacroAssembler::call(Register entry) {
947 Assembler::call(entry);
948 }
949
950 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
951 assert(rscratch != noreg || always_reachable(entry), "missing");
952
953 if (reachable(entry)) {
954 Assembler::call_literal(entry.target(), entry.rspec());
955 } else {
956 lea(rscratch, entry);
957 Assembler::call(rscratch);
958 }
959 }
960
961 void MacroAssembler::ic_call(address entry, jint method_index) {
962 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
963 // Needs full 64-bit immediate for later patching.
964 Assembler::mov64(rax, (int64_t)Universe::non_oop_word());
965 call(AddressLiteral(entry, rh));
966 }
967
968 int MacroAssembler::ic_check_size() {
969 return UseCompactObjectHeaders ? 17 : 14;
970 }
971
972 int MacroAssembler::ic_check(int end_alignment) {
973 Register receiver = j_rarg0;
974 Register data = rax;
975 Register temp = rscratch1;
976
977 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
978 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
979 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
980 // before the inline cache check here, and not after
981 align(end_alignment, offset() + ic_check_size());
982
983 int uep_offset = offset();
984
985 if (UseCompactObjectHeaders) {
986 load_narrow_klass_compact(temp, receiver);
987 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
988 } else if (UseCompressedClassPointers) {
989 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
990 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
991 } else {
992 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
993 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
994 }
995
996 // if inline cache check fails, then jump to runtime routine
997 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
998 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
999
1000 return uep_offset;
1001 }
1002
1003 void MacroAssembler::emit_static_call_stub() {
1004 // Static stub relocation also tags the Method* in the code-stream.
1005 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1006 // This is recognized as unresolved by relocs/nativeinst/ic code.
1007 jump(RuntimeAddress(pc()));
1008 }
1009
1010 // Implementation of call_VM versions
1011
1012 void MacroAssembler::call_VM(Register oop_result,
1013 address entry_point,
1014 bool check_exceptions) {
1015 Label C, E;
1016 call(C, relocInfo::none);
1017 jmp(E);
1018
1019 bind(C);
1020 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1021 ret(0);
1022
1023 bind(E);
1024 }
1025
1026 void MacroAssembler::call_VM(Register oop_result,
1027 address entry_point,
1028 Register arg_1,
1029 bool check_exceptions) {
1030 Label C, E;
1031 call(C, relocInfo::none);
1032 jmp(E);
1033
1034 bind(C);
1035 pass_arg1(this, arg_1);
1036 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1037 ret(0);
1038
1039 bind(E);
1040 }
1041
1042 void MacroAssembler::call_VM(Register oop_result,
1043 address entry_point,
1044 Register arg_1,
1045 Register arg_2,
1046 bool check_exceptions) {
1047 Label C, E;
1048 call(C, relocInfo::none);
1049 jmp(E);
1050
1051 bind(C);
1052
1053 assert_different_registers(arg_1, c_rarg2);
1054
1055 pass_arg2(this, arg_2);
1056 pass_arg1(this, arg_1);
1057 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1058 ret(0);
1059
1060 bind(E);
1061 }
1062
1063 void MacroAssembler::call_VM(Register oop_result,
1064 address entry_point,
1065 Register arg_1,
1066 Register arg_2,
1067 Register arg_3,
1068 bool check_exceptions) {
1069 Label C, E;
1070 call(C, relocInfo::none);
1071 jmp(E);
1072
1073 bind(C);
1074
1075 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1076 assert_different_registers(arg_2, c_rarg3);
1077 pass_arg3(this, arg_3);
1078 pass_arg2(this, arg_2);
1079 pass_arg1(this, arg_1);
1080 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1081 ret(0);
1082
1083 bind(E);
1084 }
1085
1086 void MacroAssembler::call_VM(Register oop_result,
1087 Register last_java_sp,
1088 address entry_point,
1089 int number_of_arguments,
1090 bool check_exceptions) {
1091 call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1092 }
1093
1094 void MacroAssembler::call_VM(Register oop_result,
1095 Register last_java_sp,
1096 address entry_point,
1097 Register arg_1,
1098 bool check_exceptions) {
1099 pass_arg1(this, arg_1);
1100 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1101 }
1102
1103 void MacroAssembler::call_VM(Register oop_result,
1104 Register last_java_sp,
1105 address entry_point,
1106 Register arg_1,
1107 Register arg_2,
1108 bool check_exceptions) {
1109
1110 assert_different_registers(arg_1, c_rarg2);
1111 pass_arg2(this, arg_2);
1112 pass_arg1(this, arg_1);
1113 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1114 }
1115
1116 void MacroAssembler::call_VM(Register oop_result,
1117 Register last_java_sp,
1118 address entry_point,
1119 Register arg_1,
1120 Register arg_2,
1121 Register arg_3,
1122 bool check_exceptions) {
1123 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1124 assert_different_registers(arg_2, c_rarg3);
1125 pass_arg3(this, arg_3);
1126 pass_arg2(this, arg_2);
1127 pass_arg1(this, arg_1);
1128 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1129 }
1130
1131 void MacroAssembler::super_call_VM(Register oop_result,
1132 Register last_java_sp,
1133 address entry_point,
1134 int number_of_arguments,
1135 bool check_exceptions) {
1136 MacroAssembler::call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1137 }
1138
1139 void MacroAssembler::super_call_VM(Register oop_result,
1140 Register last_java_sp,
1141 address entry_point,
1142 Register arg_1,
1143 bool check_exceptions) {
1144 pass_arg1(this, arg_1);
1145 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1146 }
1147
1148 void MacroAssembler::super_call_VM(Register oop_result,
1149 Register last_java_sp,
1150 address entry_point,
1151 Register arg_1,
1152 Register arg_2,
1153 bool check_exceptions) {
1154
1155 assert_different_registers(arg_1, c_rarg2);
1156 pass_arg2(this, arg_2);
1157 pass_arg1(this, arg_1);
1158 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1159 }
1160
1161 void MacroAssembler::super_call_VM(Register oop_result,
1162 Register last_java_sp,
1163 address entry_point,
1164 Register arg_1,
1165 Register arg_2,
1166 Register arg_3,
1167 bool check_exceptions) {
1168 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1169 assert_different_registers(arg_2, c_rarg3);
1170 pass_arg3(this, arg_3);
1171 pass_arg2(this, arg_2);
1172 pass_arg1(this, arg_1);
1173 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1174 }
1175
1176 void MacroAssembler::call_VM_base(Register oop_result,
1177 Register last_java_sp,
1178 address entry_point,
1179 int number_of_arguments,
1180 bool check_exceptions) {
1181 Register java_thread = r15_thread;
1182
1183 // determine last_java_sp register
1184 if (!last_java_sp->is_valid()) {
1185 last_java_sp = rsp;
1186 }
1187 // debugging support
1188 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1189 #ifdef ASSERT
1190 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1191 // r12 is the heapbase.
1192 if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
1193 #endif // ASSERT
1194
1195 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1196 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1197
1198 // push java thread (becomes first argument of C function)
1199
1200 mov(c_rarg0, r15_thread);
1201
1202 // set last Java frame before call
1203 assert(last_java_sp != rbp, "can't use ebp/rbp");
1204
1205 // Only interpreter should have to set fp
1206 set_last_Java_frame(last_java_sp, rbp, nullptr, rscratch1);
1207
1208 // do the call, remove parameters
1209 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1210
1211 #ifdef ASSERT
1212 // Check that thread register is not clobbered.
1213 guarantee(java_thread != rax, "change this code");
1214 push(rax);
1215 { Label L;
1216 get_thread_slow(rax);
1217 cmpptr(java_thread, rax);
1218 jcc(Assembler::equal, L);
1219 STOP("MacroAssembler::call_VM_base: java_thread not callee saved?");
1220 bind(L);
1221 }
1222 pop(rax);
1223 #endif
1224
1225 // reset last Java frame
1226 // Only interpreter should have to clear fp
1227 reset_last_Java_frame(true);
1228
1229 // C++ interp handles this in the interpreter
1230 check_and_handle_popframe();
1231 check_and_handle_earlyret();
1232
1233 if (check_exceptions) {
1234 // check for pending exceptions (java_thread is set upon return)
1235 cmpptr(Address(r15_thread, Thread::pending_exception_offset()), NULL_WORD);
1236 // This used to conditionally jump to forward_exception however it is
1237 // possible if we relocate that the branch will not reach. So we must jump
1238 // around so we can always reach
1239
1240 Label ok;
1241 jcc(Assembler::equal, ok);
1242 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1243 bind(ok);
1244 }
1245
1246 // get oop result if there is one and reset the value in the thread
1247 if (oop_result->is_valid()) {
1248 get_vm_result_oop(oop_result);
1249 }
1250 }
1251
1252 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1253 // Calculate the value for last_Java_sp somewhat subtle.
1254 // call_VM does an intermediate call which places a return address on
1255 // the stack just under the stack pointer as the user finished with it.
1256 // This allows use to retrieve last_Java_pc from last_Java_sp[-1].
1257
1258 // We've pushed one address, correct last_Java_sp
1259 lea(rax, Address(rsp, wordSize));
1260
1261 call_VM_base(oop_result, rax, entry_point, number_of_arguments, check_exceptions);
1262 }
1263
1264 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1265 void MacroAssembler::call_VM_leaf0(address entry_point) {
1266 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1267 }
1268
1269 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1270 call_VM_leaf_base(entry_point, number_of_arguments);
1271 }
1272
1273 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1274 pass_arg0(this, arg_0);
1275 call_VM_leaf(entry_point, 1);
1276 }
1277
1278 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1279
1280 assert_different_registers(arg_0, c_rarg1);
1281 pass_arg1(this, arg_1);
1282 pass_arg0(this, arg_0);
1283 call_VM_leaf(entry_point, 2);
1284 }
1285
1286 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1287 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1288 assert_different_registers(arg_1, c_rarg2);
1289 pass_arg2(this, arg_2);
1290 pass_arg1(this, arg_1);
1291 pass_arg0(this, arg_0);
1292 call_VM_leaf(entry_point, 3);
1293 }
1294
1295 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1296 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1297 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1298 assert_different_registers(arg_2, c_rarg3);
1299 pass_arg3(this, arg_3);
1300 pass_arg2(this, arg_2);
1301 pass_arg1(this, arg_1);
1302 pass_arg0(this, arg_0);
1303 call_VM_leaf(entry_point, 3);
1304 }
1305
1306 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1307 pass_arg0(this, arg_0);
1308 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1309 }
1310
1311 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1312 assert_different_registers(arg_0, c_rarg1);
1313 pass_arg1(this, arg_1);
1314 pass_arg0(this, arg_0);
1315 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1316 }
1317
1318 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1319 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1320 assert_different_registers(arg_1, c_rarg2);
1321 pass_arg2(this, arg_2);
1322 pass_arg1(this, arg_1);
1323 pass_arg0(this, arg_0);
1324 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1325 }
1326
1327 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1328 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1329 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1330 assert_different_registers(arg_2, c_rarg3);
1331 pass_arg3(this, arg_3);
1332 pass_arg2(this, arg_2);
1333 pass_arg1(this, arg_1);
1334 pass_arg0(this, arg_0);
1335 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1336 }
1337
1338 void MacroAssembler::get_vm_result_oop(Register oop_result) {
1339 movptr(oop_result, Address(r15_thread, JavaThread::vm_result_oop_offset()));
1340 movptr(Address(r15_thread, JavaThread::vm_result_oop_offset()), NULL_WORD);
1341 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1342 }
1343
1344 void MacroAssembler::get_vm_result_metadata(Register metadata_result) {
1345 movptr(metadata_result, Address(r15_thread, JavaThread::vm_result_metadata_offset()));
1346 movptr(Address(r15_thread, JavaThread::vm_result_metadata_offset()), NULL_WORD);
1347 }
1348
1349 void MacroAssembler::check_and_handle_earlyret() {
1350 }
1351
1352 void MacroAssembler::check_and_handle_popframe() {
1353 }
1354
1355 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1356 assert(rscratch != noreg || always_reachable(src1), "missing");
1357
1358 if (reachable(src1)) {
1359 cmpl(as_Address(src1), imm);
1360 } else {
1361 lea(rscratch, src1);
1362 cmpl(Address(rscratch, 0), imm);
1363 }
1364 }
1365
1366 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1367 assert(!src2.is_lval(), "use cmpptr");
1368 assert(rscratch != noreg || always_reachable(src2), "missing");
1369
1370 if (reachable(src2)) {
1371 cmpl(src1, as_Address(src2));
1372 } else {
1373 lea(rscratch, src2);
1374 cmpl(src1, Address(rscratch, 0));
1375 }
1376 }
1377
1378 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1379 Assembler::cmpl(src1, imm);
1380 }
1381
1382 void MacroAssembler::cmp32(Register src1, Address src2) {
1383 Assembler::cmpl(src1, src2);
1384 }
1385
1386 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1387 ucomisd(opr1, opr2);
1388
1389 Label L;
1390 if (unordered_is_less) {
1391 movl(dst, -1);
1392 jcc(Assembler::parity, L);
1393 jcc(Assembler::below , L);
1394 movl(dst, 0);
1395 jcc(Assembler::equal , L);
1396 increment(dst);
1397 } else { // unordered is greater
1398 movl(dst, 1);
1399 jcc(Assembler::parity, L);
1400 jcc(Assembler::above , L);
1401 movl(dst, 0);
1402 jcc(Assembler::equal , L);
1403 decrementl(dst);
1404 }
1405 bind(L);
1406 }
1407
1408 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1409 ucomiss(opr1, opr2);
1410
1411 Label L;
1412 if (unordered_is_less) {
1413 movl(dst, -1);
1414 jcc(Assembler::parity, L);
1415 jcc(Assembler::below , L);
1416 movl(dst, 0);
1417 jcc(Assembler::equal , L);
1418 increment(dst);
1419 } else { // unordered is greater
1420 movl(dst, 1);
1421 jcc(Assembler::parity, L);
1422 jcc(Assembler::above , L);
1423 movl(dst, 0);
1424 jcc(Assembler::equal , L);
1425 decrementl(dst);
1426 }
1427 bind(L);
1428 }
1429
1430
1431 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1432 assert(rscratch != noreg || always_reachable(src1), "missing");
1433
1434 if (reachable(src1)) {
1435 cmpb(as_Address(src1), imm);
1436 } else {
1437 lea(rscratch, src1);
1438 cmpb(Address(rscratch, 0), imm);
1439 }
1440 }
1441
1442 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1443 assert(rscratch != noreg || always_reachable(src2), "missing");
1444
1445 if (src2.is_lval()) {
1446 movptr(rscratch, src2);
1447 Assembler::cmpq(src1, rscratch);
1448 } else if (reachable(src2)) {
1449 cmpq(src1, as_Address(src2));
1450 } else {
1451 lea(rscratch, src2);
1452 Assembler::cmpq(src1, Address(rscratch, 0));
1453 }
1454 }
1455
1456 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1457 assert(src2.is_lval(), "not a mem-mem compare");
1458 // moves src2's literal address
1459 movptr(rscratch, src2);
1460 Assembler::cmpq(src1, rscratch);
1461 }
1462
1463 void MacroAssembler::cmpoop(Register src1, Register src2) {
1464 cmpptr(src1, src2);
1465 }
1466
1467 void MacroAssembler::cmpoop(Register src1, Address src2) {
1468 cmpptr(src1, src2);
1469 }
1470
1471 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1472 movoop(rscratch, src2);
1473 cmpptr(src1, rscratch);
1474 }
1475
1476 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1477 assert(rscratch != noreg || always_reachable(adr), "missing");
1478
1479 if (reachable(adr)) {
1480 lock();
1481 cmpxchgptr(reg, as_Address(adr));
1482 } else {
1483 lea(rscratch, adr);
1484 lock();
1485 cmpxchgptr(reg, Address(rscratch, 0));
1486 }
1487 }
1488
1489 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1490 cmpxchgq(reg, adr);
1491 }
1492
1493 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1494 assert(rscratch != noreg || always_reachable(src), "missing");
1495
1496 if (reachable(src)) {
1497 Assembler::comisd(dst, as_Address(src));
1498 } else {
1499 lea(rscratch, src);
1500 Assembler::comisd(dst, Address(rscratch, 0));
1501 }
1502 }
1503
1504 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1505 assert(rscratch != noreg || always_reachable(src), "missing");
1506
1507 if (reachable(src)) {
1508 Assembler::comiss(dst, as_Address(src));
1509 } else {
1510 lea(rscratch, src);
1511 Assembler::comiss(dst, Address(rscratch, 0));
1512 }
1513 }
1514
1515
1516 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1517 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1518
1519 Condition negated_cond = negate_condition(cond);
1520 Label L;
1521 jcc(negated_cond, L);
1522 pushf(); // Preserve flags
1523 atomic_incl(counter_addr, rscratch);
1524 popf();
1525 bind(L);
1526 }
1527
1528 int MacroAssembler::corrected_idivl(Register reg) {
1529 // Full implementation of Java idiv and irem; checks for
1530 // special case as described in JVM spec., p.243 & p.271.
1531 // The function returns the (pc) offset of the idivl
1532 // instruction - may be needed for implicit exceptions.
1533 //
1534 // normal case special case
1535 //
1536 // input : rax,: dividend min_int
1537 // reg: divisor (may not be rax,/rdx) -1
1538 //
1539 // output: rax,: quotient (= rax, idiv reg) min_int
1540 // rdx: remainder (= rax, irem reg) 0
1541 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1542 const int min_int = 0x80000000;
1543 Label normal_case, special_case;
1544
1545 // check for special case
1546 cmpl(rax, min_int);
1547 jcc(Assembler::notEqual, normal_case);
1548 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1549 cmpl(reg, -1);
1550 jcc(Assembler::equal, special_case);
1551
1552 // handle normal case
1553 bind(normal_case);
1554 cdql();
1555 int idivl_offset = offset();
1556 idivl(reg);
1557
1558 // normal and special case exit
1559 bind(special_case);
1560
1561 return idivl_offset;
1562 }
1563
1564
1565
1566 void MacroAssembler::decrementl(Register reg, int value) {
1567 if (value == min_jint) {subl(reg, value) ; return; }
1568 if (value < 0) { incrementl(reg, -value); return; }
1569 if (value == 0) { ; return; }
1570 if (value == 1 && UseIncDec) { decl(reg) ; return; }
1571 /* else */ { subl(reg, value) ; return; }
1572 }
1573
1574 void MacroAssembler::decrementl(Address dst, int value) {
1575 if (value == min_jint) {subl(dst, value) ; return; }
1576 if (value < 0) { incrementl(dst, -value); return; }
1577 if (value == 0) { ; return; }
1578 if (value == 1 && UseIncDec) { decl(dst) ; return; }
1579 /* else */ { subl(dst, value) ; return; }
1580 }
1581
1582 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1583 assert(shift_value > 0, "illegal shift value");
1584 Label _is_positive;
1585 testl (reg, reg);
1586 jcc (Assembler::positive, _is_positive);
1587 int offset = (1 << shift_value) - 1 ;
1588
1589 if (offset == 1) {
1590 incrementl(reg);
1591 } else {
1592 addl(reg, offset);
1593 }
1594
1595 bind (_is_positive);
1596 sarl(reg, shift_value);
1597 }
1598
1599 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1600 assert(rscratch != noreg || always_reachable(src), "missing");
1601
1602 if (reachable(src)) {
1603 Assembler::divsd(dst, as_Address(src));
1604 } else {
1605 lea(rscratch, src);
1606 Assembler::divsd(dst, Address(rscratch, 0));
1607 }
1608 }
1609
1610 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1611 assert(rscratch != noreg || always_reachable(src), "missing");
1612
1613 if (reachable(src)) {
1614 Assembler::divss(dst, as_Address(src));
1615 } else {
1616 lea(rscratch, src);
1617 Assembler::divss(dst, Address(rscratch, 0));
1618 }
1619 }
1620
1621 void MacroAssembler::enter() {
1622 push(rbp);
1623 mov(rbp, rsp);
1624 }
1625
1626 void MacroAssembler::post_call_nop() {
1627 if (!Continuations::enabled()) {
1628 return;
1629 }
1630 InstructionMark im(this);
1631 relocate(post_call_nop_Relocation::spec());
1632 InlineSkippedInstructionsCounter skipCounter(this);
1633 emit_int8((uint8_t)0x0f);
1634 emit_int8((uint8_t)0x1f);
1635 emit_int8((uint8_t)0x84);
1636 emit_int8((uint8_t)0x00);
1637 emit_int32(0x00);
1638 }
1639
1640 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1641 assert(rscratch != noreg || always_reachable(src), "missing");
1642 if (reachable(src)) {
1643 Assembler::mulpd(dst, as_Address(src));
1644 } else {
1645 lea(rscratch, src);
1646 Assembler::mulpd(dst, Address(rscratch, 0));
1647 }
1648 }
1649
1650 // dst = c = a * b + c
1651 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1652 Assembler::vfmadd231sd(c, a, b);
1653 if (dst != c) {
1654 movdbl(dst, c);
1655 }
1656 }
1657
1658 // dst = c = a * b + c
1659 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1660 Assembler::vfmadd231ss(c, a, b);
1661 if (dst != c) {
1662 movflt(dst, c);
1663 }
1664 }
1665
1666 // dst = c = a * b + c
1667 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1668 Assembler::vfmadd231pd(c, a, b, vector_len);
1669 if (dst != c) {
1670 vmovdqu(dst, c);
1671 }
1672 }
1673
1674 // dst = c = a * b + c
1675 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1676 Assembler::vfmadd231ps(c, a, b, vector_len);
1677 if (dst != c) {
1678 vmovdqu(dst, c);
1679 }
1680 }
1681
1682 // dst = c = a * b + c
1683 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1684 Assembler::vfmadd231pd(c, a, b, vector_len);
1685 if (dst != c) {
1686 vmovdqu(dst, c);
1687 }
1688 }
1689
1690 // dst = c = a * b + c
1691 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1692 Assembler::vfmadd231ps(c, a, b, vector_len);
1693 if (dst != c) {
1694 vmovdqu(dst, c);
1695 }
1696 }
1697
1698 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
1699 assert(rscratch != noreg || always_reachable(dst), "missing");
1700
1701 if (reachable(dst)) {
1702 incrementl(as_Address(dst));
1703 } else {
1704 lea(rscratch, dst);
1705 incrementl(Address(rscratch, 0));
1706 }
1707 }
1708
1709 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
1710 incrementl(as_Address(dst, rscratch));
1711 }
1712
1713 void MacroAssembler::incrementl(Register reg, int value) {
1714 if (value == min_jint) {addl(reg, value) ; return; }
1715 if (value < 0) { decrementl(reg, -value); return; }
1716 if (value == 0) { ; return; }
1717 if (value == 1 && UseIncDec) { incl(reg) ; return; }
1718 /* else */ { addl(reg, value) ; return; }
1719 }
1720
1721 void MacroAssembler::incrementl(Address dst, int value) {
1722 if (value == min_jint) {addl(dst, value) ; return; }
1723 if (value < 0) { decrementl(dst, -value); return; }
1724 if (value == 0) { ; return; }
1725 if (value == 1 && UseIncDec) { incl(dst) ; return; }
1726 /* else */ { addl(dst, value) ; return; }
1727 }
1728
1729 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
1730 assert(rscratch != noreg || always_reachable(dst), "missing");
1731 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
1732 if (reachable(dst)) {
1733 jmp_literal(dst.target(), dst.rspec());
1734 } else {
1735 lea(rscratch, dst);
1736 jmp(rscratch);
1737 }
1738 }
1739
1740 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
1741 assert(rscratch != noreg || always_reachable(dst), "missing");
1742 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
1743 if (reachable(dst)) {
1744 InstructionMark im(this);
1745 relocate(dst.reloc());
1746 const int short_size = 2;
1747 const int long_size = 6;
1748 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
1749 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
1750 // 0111 tttn #8-bit disp
1751 emit_int8(0x70 | cc);
1752 emit_int8((offs - short_size) & 0xFF);
1753 } else {
1754 // 0000 1111 1000 tttn #32-bit disp
1755 emit_int8(0x0F);
1756 emit_int8((unsigned char)(0x80 | cc));
1757 emit_int32(offs - long_size);
1758 }
1759 } else {
1760 #ifdef ASSERT
1761 warning("reversing conditional branch");
1762 #endif /* ASSERT */
1763 Label skip;
1764 jccb(reverse[cc], skip);
1765 lea(rscratch, dst);
1766 Assembler::jmp(rscratch);
1767 bind(skip);
1768 }
1769 }
1770
1771 void MacroAssembler::cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch) {
1772 ExternalAddress mxcsr_std(StubRoutines::x86::addr_mxcsr_std());
1773 assert(rscratch != noreg || always_reachable(mxcsr_std), "missing");
1774
1775 stmxcsr(mxcsr_save);
1776 movl(tmp, mxcsr_save);
1777 if (EnableX86ECoreOpts) {
1778 // The mxcsr_std has status bits set for performance on ECore
1779 orl(tmp, 0x003f);
1780 } else {
1781 // Mask out status bits (only check control and mask bits)
1782 andl(tmp, 0xFFC0);
1783 }
1784 cmp32(tmp, mxcsr_std, rscratch);
1785 }
1786
1787 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
1788 assert(rscratch != noreg || always_reachable(src), "missing");
1789
1790 if (reachable(src)) {
1791 Assembler::ldmxcsr(as_Address(src));
1792 } else {
1793 lea(rscratch, src);
1794 Assembler::ldmxcsr(Address(rscratch, 0));
1795 }
1796 }
1797
1798 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1799 int off = offset();
1800 movsbl(dst, src); // movsxb
1801 return off;
1802 }
1803
1804 // Note: load_signed_short used to be called load_signed_word.
1805 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
1806 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
1807 // The term "word" in HotSpot means a 32- or 64-bit machine word.
1808 int MacroAssembler::load_signed_short(Register dst, Address src) {
1809 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
1810 // version but this is what 64bit has always done. This seems to imply
1811 // that users are only using 32bits worth.
1812 int off = offset();
1813 movswl(dst, src); // movsxw
1814 return off;
1815 }
1816
1817 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1818 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1819 // and "3.9 Partial Register Penalties", p. 22).
1820 int off = offset();
1821 movzbl(dst, src); // movzxb
1822 return off;
1823 }
1824
1825 // Note: load_unsigned_short used to be called load_unsigned_word.
1826 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1827 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1828 // and "3.9 Partial Register Penalties", p. 22).
1829 int off = offset();
1830 movzwl(dst, src); // movzxw
1831 return off;
1832 }
1833
1834 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1835 switch (size_in_bytes) {
1836 case 8: movq(dst, src); break;
1837 case 4: movl(dst, src); break;
1838 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1839 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1840 default: ShouldNotReachHere();
1841 }
1842 }
1843
1844 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1845 switch (size_in_bytes) {
1846 case 8: movq(dst, src); break;
1847 case 4: movl(dst, src); break;
1848 case 2: movw(dst, src); break;
1849 case 1: movb(dst, src); break;
1850 default: ShouldNotReachHere();
1851 }
1852 }
1853
1854 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
1855 assert(rscratch != noreg || always_reachable(dst), "missing");
1856
1857 if (reachable(dst)) {
1858 movl(as_Address(dst), src);
1859 } else {
1860 lea(rscratch, dst);
1861 movl(Address(rscratch, 0), src);
1862 }
1863 }
1864
1865 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
1866 if (reachable(src)) {
1867 movl(dst, as_Address(src));
1868 } else {
1869 lea(dst, src);
1870 movl(dst, Address(dst, 0));
1871 }
1872 }
1873
1874 // C++ bool manipulation
1875
1876 void MacroAssembler::movbool(Register dst, Address src) {
1877 if(sizeof(bool) == 1)
1878 movb(dst, src);
1879 else if(sizeof(bool) == 2)
1880 movw(dst, src);
1881 else if(sizeof(bool) == 4)
1882 movl(dst, src);
1883 else
1884 // unsupported
1885 ShouldNotReachHere();
1886 }
1887
1888 void MacroAssembler::movbool(Address dst, bool boolconst) {
1889 if(sizeof(bool) == 1)
1890 movb(dst, (int) boolconst);
1891 else if(sizeof(bool) == 2)
1892 movw(dst, (int) boolconst);
1893 else if(sizeof(bool) == 4)
1894 movl(dst, (int) boolconst);
1895 else
1896 // unsupported
1897 ShouldNotReachHere();
1898 }
1899
1900 void MacroAssembler::movbool(Address dst, Register src) {
1901 if(sizeof(bool) == 1)
1902 movb(dst, src);
1903 else if(sizeof(bool) == 2)
1904 movw(dst, src);
1905 else if(sizeof(bool) == 4)
1906 movl(dst, src);
1907 else
1908 // unsupported
1909 ShouldNotReachHere();
1910 }
1911
1912 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1913 assert(rscratch != noreg || always_reachable(src), "missing");
1914
1915 if (reachable(src)) {
1916 movdl(dst, as_Address(src));
1917 } else {
1918 lea(rscratch, src);
1919 movdl(dst, Address(rscratch, 0));
1920 }
1921 }
1922
1923 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
1924 assert(rscratch != noreg || always_reachable(src), "missing");
1925
1926 if (reachable(src)) {
1927 movq(dst, as_Address(src));
1928 } else {
1929 lea(rscratch, src);
1930 movq(dst, Address(rscratch, 0));
1931 }
1932 }
1933
1934 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1935 assert(rscratch != noreg || always_reachable(src), "missing");
1936
1937 if (reachable(src)) {
1938 if (UseXmmLoadAndClearUpper) {
1939 movsd (dst, as_Address(src));
1940 } else {
1941 movlpd(dst, as_Address(src));
1942 }
1943 } else {
1944 lea(rscratch, src);
1945 if (UseXmmLoadAndClearUpper) {
1946 movsd (dst, Address(rscratch, 0));
1947 } else {
1948 movlpd(dst, Address(rscratch, 0));
1949 }
1950 }
1951 }
1952
1953 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
1954 assert(rscratch != noreg || always_reachable(src), "missing");
1955
1956 if (reachable(src)) {
1957 movss(dst, as_Address(src));
1958 } else {
1959 lea(rscratch, src);
1960 movss(dst, Address(rscratch, 0));
1961 }
1962 }
1963
1964 void MacroAssembler::mov64(Register dst, int64_t imm64) {
1965 if (is_uimm32(imm64)) {
1966 movl(dst, checked_cast<uint32_t>(imm64));
1967 } else if (is_simm32(imm64)) {
1968 movq(dst, checked_cast<int32_t>(imm64));
1969 } else {
1970 Assembler::mov64(dst, imm64);
1971 }
1972 }
1973
1974 void MacroAssembler::mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format) {
1975 Assembler::mov64(dst, imm64, rtype, format);
1976 }
1977
1978 void MacroAssembler::movptr(Register dst, Register src) {
1979 movq(dst, src);
1980 }
1981
1982 void MacroAssembler::movptr(Register dst, Address src) {
1983 movq(dst, src);
1984 }
1985
1986 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
1987 void MacroAssembler::movptr(Register dst, intptr_t src) {
1988 mov64(dst, src);
1989 }
1990
1991 void MacroAssembler::movptr(Address dst, Register src) {
1992 movq(dst, src);
1993 }
1994
1995 void MacroAssembler::movptr(Address dst, int32_t src) {
1996 movslq(dst, src);
1997 }
1998
1999 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2000 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2001 Assembler::movdqu(dst, src);
2002 }
2003
2004 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2005 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2006 Assembler::movdqu(dst, src);
2007 }
2008
2009 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2010 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2011 Assembler::movdqu(dst, src);
2012 }
2013
2014 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2015 assert(rscratch != noreg || always_reachable(src), "missing");
2016
2017 if (reachable(src)) {
2018 movdqu(dst, as_Address(src));
2019 } else {
2020 lea(rscratch, src);
2021 movdqu(dst, Address(rscratch, 0));
2022 }
2023 }
2024
2025 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2026 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2027 Assembler::vmovdqu(dst, src);
2028 }
2029
2030 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2031 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2032 Assembler::vmovdqu(dst, src);
2033 }
2034
2035 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2036 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2037 Assembler::vmovdqu(dst, src);
2038 }
2039
2040 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2041 assert(rscratch != noreg || always_reachable(src), "missing");
2042
2043 if (reachable(src)) {
2044 vmovdqu(dst, as_Address(src));
2045 }
2046 else {
2047 lea(rscratch, src);
2048 vmovdqu(dst, Address(rscratch, 0));
2049 }
2050 }
2051
2052 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2053 assert(rscratch != noreg || always_reachable(src), "missing");
2054
2055 if (vector_len == AVX_512bit) {
2056 evmovdquq(dst, src, AVX_512bit, rscratch);
2057 } else if (vector_len == AVX_256bit) {
2058 vmovdqu(dst, src, rscratch);
2059 } else {
2060 movdqu(dst, src, rscratch);
2061 }
2062 }
2063
2064 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2065 if (vector_len == AVX_512bit) {
2066 evmovdquq(dst, src, AVX_512bit);
2067 } else if (vector_len == AVX_256bit) {
2068 vmovdqu(dst, src);
2069 } else {
2070 movdqu(dst, src);
2071 }
2072 }
2073
2074 void MacroAssembler::vmovdqu(Address dst, XMMRegister src, int vector_len) {
2075 if (vector_len == AVX_512bit) {
2076 evmovdquq(dst, src, AVX_512bit);
2077 } else if (vector_len == AVX_256bit) {
2078 vmovdqu(dst, src);
2079 } else {
2080 movdqu(dst, src);
2081 }
2082 }
2083
2084 void MacroAssembler::vmovdqu(XMMRegister dst, Address src, int vector_len) {
2085 if (vector_len == AVX_512bit) {
2086 evmovdquq(dst, src, AVX_512bit);
2087 } else if (vector_len == AVX_256bit) {
2088 vmovdqu(dst, src);
2089 } else {
2090 movdqu(dst, src);
2091 }
2092 }
2093
2094 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2095 assert(rscratch != noreg || always_reachable(src), "missing");
2096
2097 if (reachable(src)) {
2098 vmovdqa(dst, as_Address(src));
2099 }
2100 else {
2101 lea(rscratch, src);
2102 vmovdqa(dst, Address(rscratch, 0));
2103 }
2104 }
2105
2106 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2107 assert(rscratch != noreg || always_reachable(src), "missing");
2108
2109 if (vector_len == AVX_512bit) {
2110 evmovdqaq(dst, src, AVX_512bit, rscratch);
2111 } else if (vector_len == AVX_256bit) {
2112 vmovdqa(dst, src, rscratch);
2113 } else {
2114 movdqa(dst, src, rscratch);
2115 }
2116 }
2117
2118 void MacroAssembler::kmov(KRegister dst, Address src) {
2119 if (VM_Version::supports_avx512bw()) {
2120 kmovql(dst, src);
2121 } else {
2122 assert(VM_Version::supports_evex(), "");
2123 kmovwl(dst, src);
2124 }
2125 }
2126
2127 void MacroAssembler::kmov(Address dst, KRegister src) {
2128 if (VM_Version::supports_avx512bw()) {
2129 kmovql(dst, src);
2130 } else {
2131 assert(VM_Version::supports_evex(), "");
2132 kmovwl(dst, src);
2133 }
2134 }
2135
2136 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2137 if (VM_Version::supports_avx512bw()) {
2138 kmovql(dst, src);
2139 } else {
2140 assert(VM_Version::supports_evex(), "");
2141 kmovwl(dst, src);
2142 }
2143 }
2144
2145 void MacroAssembler::kmov(Register dst, KRegister src) {
2146 if (VM_Version::supports_avx512bw()) {
2147 kmovql(dst, src);
2148 } else {
2149 assert(VM_Version::supports_evex(), "");
2150 kmovwl(dst, src);
2151 }
2152 }
2153
2154 void MacroAssembler::kmov(KRegister dst, Register src) {
2155 if (VM_Version::supports_avx512bw()) {
2156 kmovql(dst, src);
2157 } else {
2158 assert(VM_Version::supports_evex(), "");
2159 kmovwl(dst, src);
2160 }
2161 }
2162
2163 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2164 assert(rscratch != noreg || always_reachable(src), "missing");
2165
2166 if (reachable(src)) {
2167 kmovql(dst, as_Address(src));
2168 } else {
2169 lea(rscratch, src);
2170 kmovql(dst, Address(rscratch, 0));
2171 }
2172 }
2173
2174 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2175 assert(rscratch != noreg || always_reachable(src), "missing");
2176
2177 if (reachable(src)) {
2178 kmovwl(dst, as_Address(src));
2179 } else {
2180 lea(rscratch, src);
2181 kmovwl(dst, Address(rscratch, 0));
2182 }
2183 }
2184
2185 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2186 int vector_len, Register rscratch) {
2187 assert(rscratch != noreg || always_reachable(src), "missing");
2188
2189 if (reachable(src)) {
2190 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2191 } else {
2192 lea(rscratch, src);
2193 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2194 }
2195 }
2196
2197 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2198 int vector_len, Register rscratch) {
2199 assert(rscratch != noreg || always_reachable(src), "missing");
2200
2201 if (reachable(src)) {
2202 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2203 } else {
2204 lea(rscratch, src);
2205 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2206 }
2207 }
2208
2209 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2210 assert(rscratch != noreg || always_reachable(src), "missing");
2211
2212 if (reachable(src)) {
2213 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2214 } else {
2215 lea(rscratch, src);
2216 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2217 }
2218 }
2219
2220 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2221 assert(rscratch != noreg || always_reachable(src), "missing");
2222
2223 if (reachable(src)) {
2224 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2225 } else {
2226 lea(rscratch, src);
2227 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2228 }
2229 }
2230
2231 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2232 assert(rscratch != noreg || always_reachable(src), "missing");
2233
2234 if (reachable(src)) {
2235 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2236 } else {
2237 lea(rscratch, src);
2238 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2239 }
2240 }
2241
2242 void MacroAssembler::evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2243 assert(rscratch != noreg || always_reachable(src), "missing");
2244
2245 if (reachable(src)) {
2246 Assembler::evmovdqaq(dst, mask, as_Address(src), merge, vector_len);
2247 } else {
2248 lea(rscratch, src);
2249 Assembler::evmovdqaq(dst, mask, Address(rscratch, 0), merge, vector_len);
2250 }
2251 }
2252
2253 void MacroAssembler::evmovdqaq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2254 assert(rscratch != noreg || always_reachable(src), "missing");
2255
2256 if (reachable(src)) {
2257 Assembler::evmovdqaq(dst, as_Address(src), vector_len);
2258 } else {
2259 lea(rscratch, src);
2260 Assembler::evmovdqaq(dst, Address(rscratch, 0), vector_len);
2261 }
2262 }
2263
2264 void MacroAssembler::movapd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2265 assert(rscratch != noreg || always_reachable(src), "missing");
2266
2267 if (reachable(src)) {
2268 Assembler::movapd(dst, as_Address(src));
2269 } else {
2270 lea(rscratch, src);
2271 Assembler::movapd(dst, Address(rscratch, 0));
2272 }
2273 }
2274
2275 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2276 assert(rscratch != noreg || always_reachable(src), "missing");
2277
2278 if (reachable(src)) {
2279 Assembler::movdqa(dst, as_Address(src));
2280 } else {
2281 lea(rscratch, src);
2282 Assembler::movdqa(dst, Address(rscratch, 0));
2283 }
2284 }
2285
2286 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2287 assert(rscratch != noreg || always_reachable(src), "missing");
2288
2289 if (reachable(src)) {
2290 Assembler::movsd(dst, as_Address(src));
2291 } else {
2292 lea(rscratch, src);
2293 Assembler::movsd(dst, Address(rscratch, 0));
2294 }
2295 }
2296
2297 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2298 assert(rscratch != noreg || always_reachable(src), "missing");
2299
2300 if (reachable(src)) {
2301 Assembler::movss(dst, as_Address(src));
2302 } else {
2303 lea(rscratch, src);
2304 Assembler::movss(dst, Address(rscratch, 0));
2305 }
2306 }
2307
2308 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2309 assert(rscratch != noreg || always_reachable(src), "missing");
2310
2311 if (reachable(src)) {
2312 Assembler::movddup(dst, as_Address(src));
2313 } else {
2314 lea(rscratch, src);
2315 Assembler::movddup(dst, Address(rscratch, 0));
2316 }
2317 }
2318
2319 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2320 assert(rscratch != noreg || always_reachable(src), "missing");
2321
2322 if (reachable(src)) {
2323 Assembler::vmovddup(dst, as_Address(src), vector_len);
2324 } else {
2325 lea(rscratch, src);
2326 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2327 }
2328 }
2329
2330 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2331 assert(rscratch != noreg || always_reachable(src), "missing");
2332
2333 if (reachable(src)) {
2334 Assembler::mulsd(dst, as_Address(src));
2335 } else {
2336 lea(rscratch, src);
2337 Assembler::mulsd(dst, Address(rscratch, 0));
2338 }
2339 }
2340
2341 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2342 assert(rscratch != noreg || always_reachable(src), "missing");
2343
2344 if (reachable(src)) {
2345 Assembler::mulss(dst, as_Address(src));
2346 } else {
2347 lea(rscratch, src);
2348 Assembler::mulss(dst, Address(rscratch, 0));
2349 }
2350 }
2351
2352 void MacroAssembler::null_check(Register reg, int offset) {
2353 if (needs_explicit_null_check(offset)) {
2354 // provoke OS null exception if reg is null by
2355 // accessing M[reg] w/o changing any (non-CC) registers
2356 // NOTE: cmpl is plenty here to provoke a segv
2357 cmpptr(rax, Address(reg, 0));
2358 // Note: should probably use testl(rax, Address(reg, 0));
2359 // may be shorter code (however, this version of
2360 // testl needs to be implemented first)
2361 } else {
2362 // nothing to do, (later) access of M[reg + offset]
2363 // will provoke OS null exception if reg is null
2364 }
2365 }
2366
2367 void MacroAssembler::os_breakpoint() {
2368 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2369 // (e.g., MSVC can't call ps() otherwise)
2370 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2371 }
2372
2373 void MacroAssembler::unimplemented(const char* what) {
2374 const char* buf = nullptr;
2375 {
2376 ResourceMark rm;
2377 stringStream ss;
2378 ss.print("unimplemented: %s", what);
2379 buf = code_string(ss.as_string());
2380 }
2381 stop(buf);
2382 }
2383
2384 #define XSTATE_BV 0x200
2385
2386 void MacroAssembler::pop_CPU_state() {
2387 pop_FPU_state();
2388 pop_IU_state();
2389 }
2390
2391 void MacroAssembler::pop_FPU_state() {
2392 fxrstor(Address(rsp, 0));
2393 addptr(rsp, FPUStateSizeInWords * wordSize);
2394 }
2395
2396 void MacroAssembler::pop_IU_state() {
2397 popa();
2398 addq(rsp, 8);
2399 popf();
2400 }
2401
2402 // Save Integer and Float state
2403 // Warning: Stack must be 16 byte aligned (64bit)
2404 void MacroAssembler::push_CPU_state() {
2405 push_IU_state();
2406 push_FPU_state();
2407 }
2408
2409 void MacroAssembler::push_FPU_state() {
2410 subptr(rsp, FPUStateSizeInWords * wordSize);
2411 fxsave(Address(rsp, 0));
2412 }
2413
2414 void MacroAssembler::push_IU_state() {
2415 // Push flags first because pusha kills them
2416 pushf();
2417 // Make sure rsp stays 16-byte aligned
2418 subq(rsp, 8);
2419 pusha();
2420 }
2421
2422 void MacroAssembler::push_cont_fastpath() {
2423 if (!Continuations::enabled()) return;
2424
2425 Label L_done;
2426 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2427 jccb(Assembler::belowEqual, L_done);
2428 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), rsp);
2429 bind(L_done);
2430 }
2431
2432 void MacroAssembler::pop_cont_fastpath() {
2433 if (!Continuations::enabled()) return;
2434
2435 Label L_done;
2436 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2437 jccb(Assembler::below, L_done);
2438 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), 0);
2439 bind(L_done);
2440 }
2441
2442 #ifdef ASSERT
2443 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
2444 Label no_cont;
2445 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
2446 testl(cont, cont);
2447 jcc(Assembler::zero, no_cont);
2448 stop(name);
2449 bind(no_cont);
2450 }
2451 #endif
2452
2453 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { // determine java_thread register
2454 // we must set sp to zero to clear frame
2455 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2456 // must clear fp, so that compiled frames are not confused; it is
2457 // possible that we need it only for debugging
2458 if (clear_fp) {
2459 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2460 }
2461 // Always clear the pc because it could have been set by make_walkable()
2462 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2463 vzeroupper();
2464 }
2465
2466 void MacroAssembler::round_to(Register reg, int modulus) {
2467 addptr(reg, modulus - 1);
2468 andptr(reg, -modulus);
2469 }
2470
2471 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod) {
2472 if (at_return) {
2473 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2474 // we may safely use rsp instead to perform the stack watermark check.
2475 cmpptr(in_nmethod ? rsp : rbp, Address(r15_thread, JavaThread::polling_word_offset()));
2476 jcc(Assembler::above, slow_path);
2477 return;
2478 }
2479 testb(Address(r15_thread, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2480 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2481 }
2482
2483 // Calls to C land
2484 //
2485 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2486 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2487 // has to be reset to 0. This is required to allow proper stack traversal.
2488 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2489 Register last_java_fp,
2490 address last_java_pc,
2491 Register rscratch) {
2492 vzeroupper();
2493 // determine last_java_sp register
2494 if (!last_java_sp->is_valid()) {
2495 last_java_sp = rsp;
2496 }
2497 // last_java_fp is optional
2498 if (last_java_fp->is_valid()) {
2499 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2500 }
2501 // last_java_pc is optional
2502 if (last_java_pc != nullptr) {
2503 Address java_pc(r15_thread,
2504 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
2505 lea(java_pc, InternalAddress(last_java_pc), rscratch);
2506 }
2507 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2508 }
2509
2510 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2511 Register last_java_fp,
2512 Label &L,
2513 Register scratch) {
2514 lea(scratch, L);
2515 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
2516 set_last_Java_frame(last_java_sp, last_java_fp, nullptr, scratch);
2517 }
2518
2519 void MacroAssembler::shlptr(Register dst, int imm8) {
2520 shlq(dst, imm8);
2521 }
2522
2523 void MacroAssembler::shrptr(Register dst, int imm8) {
2524 shrq(dst, imm8);
2525 }
2526
2527 void MacroAssembler::sign_extend_byte(Register reg) {
2528 movsbl(reg, reg); // movsxb
2529 }
2530
2531 void MacroAssembler::sign_extend_short(Register reg) {
2532 movswl(reg, reg); // movsxw
2533 }
2534
2535 void MacroAssembler::testl(Address dst, int32_t imm32) {
2536 if (imm32 >= 0 && is8bit(imm32)) {
2537 testb(dst, imm32);
2538 } else {
2539 Assembler::testl(dst, imm32);
2540 }
2541 }
2542
2543 void MacroAssembler::testl(Register dst, int32_t imm32) {
2544 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
2545 testb(dst, imm32);
2546 } else {
2547 Assembler::testl(dst, imm32);
2548 }
2549 }
2550
2551 void MacroAssembler::testl(Register dst, AddressLiteral src) {
2552 assert(always_reachable(src), "Address should be reachable");
2553 testl(dst, as_Address(src));
2554 }
2555
2556 void MacroAssembler::testq(Address dst, int32_t imm32) {
2557 if (imm32 >= 0) {
2558 testl(dst, imm32);
2559 } else {
2560 Assembler::testq(dst, imm32);
2561 }
2562 }
2563
2564 void MacroAssembler::testq(Register dst, int32_t imm32) {
2565 if (imm32 >= 0) {
2566 testl(dst, imm32);
2567 } else {
2568 Assembler::testq(dst, imm32);
2569 }
2570 }
2571
2572 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
2573 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2574 Assembler::pcmpeqb(dst, src);
2575 }
2576
2577 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
2578 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2579 Assembler::pcmpeqw(dst, src);
2580 }
2581
2582 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2583 assert((dst->encoding() < 16),"XMM register should be 0-15");
2584 Assembler::pcmpestri(dst, src, imm8);
2585 }
2586
2587 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2588 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2589 Assembler::pcmpestri(dst, src, imm8);
2590 }
2591
2592 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2593 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2594 Assembler::pmovzxbw(dst, src);
2595 }
2596
2597 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
2598 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2599 Assembler::pmovzxbw(dst, src);
2600 }
2601
2602 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
2603 assert((src->encoding() < 16),"XMM register should be 0-15");
2604 Assembler::pmovmskb(dst, src);
2605 }
2606
2607 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
2608 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2609 Assembler::ptest(dst, src);
2610 }
2611
2612 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2613 assert(rscratch != noreg || always_reachable(src), "missing");
2614
2615 if (reachable(src)) {
2616 Assembler::sqrtss(dst, as_Address(src));
2617 } else {
2618 lea(rscratch, src);
2619 Assembler::sqrtss(dst, Address(rscratch, 0));
2620 }
2621 }
2622
2623 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2624 assert(rscratch != noreg || always_reachable(src), "missing");
2625
2626 if (reachable(src)) {
2627 Assembler::subsd(dst, as_Address(src));
2628 } else {
2629 lea(rscratch, src);
2630 Assembler::subsd(dst, Address(rscratch, 0));
2631 }
2632 }
2633
2634 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
2635 assert(rscratch != noreg || always_reachable(src), "missing");
2636
2637 if (reachable(src)) {
2638 Assembler::roundsd(dst, as_Address(src), rmode);
2639 } else {
2640 lea(rscratch, src);
2641 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
2642 }
2643 }
2644
2645 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2646 assert(rscratch != noreg || always_reachable(src), "missing");
2647
2648 if (reachable(src)) {
2649 Assembler::subss(dst, as_Address(src));
2650 } else {
2651 lea(rscratch, src);
2652 Assembler::subss(dst, Address(rscratch, 0));
2653 }
2654 }
2655
2656 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2657 assert(rscratch != noreg || always_reachable(src), "missing");
2658
2659 if (reachable(src)) {
2660 Assembler::ucomisd(dst, as_Address(src));
2661 } else {
2662 lea(rscratch, src);
2663 Assembler::ucomisd(dst, Address(rscratch, 0));
2664 }
2665 }
2666
2667 void MacroAssembler::vucomxsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2668 assert(rscratch != noreg || always_reachable(src), "missing");
2669
2670 if (reachable(src)) {
2671 Assembler::vucomxsd(dst, as_Address(src));
2672 } else {
2673 lea(rscratch, src);
2674 Assembler::vucomxsd(dst, Address(rscratch, 0));
2675 }
2676 }
2677
2678 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2679 assert(rscratch != noreg || always_reachable(src), "missing");
2680
2681 if (reachable(src)) {
2682 Assembler::ucomiss(dst, as_Address(src));
2683 } else {
2684 lea(rscratch, src);
2685 Assembler::ucomiss(dst, Address(rscratch, 0));
2686 }
2687 }
2688
2689 void MacroAssembler::vucomxss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2690 assert(rscratch != noreg || always_reachable(src), "missing");
2691
2692 if (reachable(src)) {
2693 Assembler::vucomxss(dst, as_Address(src));
2694 } else {
2695 lea(rscratch, src);
2696 Assembler::vucomxss(dst, Address(rscratch, 0));
2697 }
2698 }
2699
2700 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2701 assert(rscratch != noreg || always_reachable(src), "missing");
2702
2703 // Used in sign-bit flipping with aligned address.
2704 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2705
2706 if (UseAVX > 2 &&
2707 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2708 (dst->encoding() >= 16)) {
2709 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2710 } else if (reachable(src)) {
2711 Assembler::xorpd(dst, as_Address(src));
2712 } else {
2713 lea(rscratch, src);
2714 Assembler::xorpd(dst, Address(rscratch, 0));
2715 }
2716 }
2717
2718 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
2719 if (UseAVX > 2 &&
2720 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2721 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2722 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2723 } else {
2724 Assembler::xorpd(dst, src);
2725 }
2726 }
2727
2728 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
2729 if (UseAVX > 2 &&
2730 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2731 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2732 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2733 } else {
2734 Assembler::xorps(dst, src);
2735 }
2736 }
2737
2738 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
2739 assert(rscratch != noreg || always_reachable(src), "missing");
2740
2741 // Used in sign-bit flipping with aligned address.
2742 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2743
2744 if (UseAVX > 2 &&
2745 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2746 (dst->encoding() >= 16)) {
2747 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2748 } else if (reachable(src)) {
2749 Assembler::xorps(dst, as_Address(src));
2750 } else {
2751 lea(rscratch, src);
2752 Assembler::xorps(dst, Address(rscratch, 0));
2753 }
2754 }
2755
2756 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
2757 assert(rscratch != noreg || always_reachable(src), "missing");
2758
2759 // Used in sign-bit flipping with aligned address.
2760 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
2761 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
2762 if (reachable(src)) {
2763 Assembler::pshufb(dst, as_Address(src));
2764 } else {
2765 lea(rscratch, src);
2766 Assembler::pshufb(dst, Address(rscratch, 0));
2767 }
2768 }
2769
2770 // AVX 3-operands instructions
2771
2772 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2773 assert(rscratch != noreg || always_reachable(src), "missing");
2774
2775 if (reachable(src)) {
2776 vaddsd(dst, nds, as_Address(src));
2777 } else {
2778 lea(rscratch, src);
2779 vaddsd(dst, nds, Address(rscratch, 0));
2780 }
2781 }
2782
2783 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2784 assert(rscratch != noreg || always_reachable(src), "missing");
2785
2786 if (reachable(src)) {
2787 vaddss(dst, nds, as_Address(src));
2788 } else {
2789 lea(rscratch, src);
2790 vaddss(dst, nds, Address(rscratch, 0));
2791 }
2792 }
2793
2794 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2795 assert(UseAVX > 0, "requires some form of AVX");
2796 assert(rscratch != noreg || always_reachable(src), "missing");
2797
2798 if (reachable(src)) {
2799 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
2800 } else {
2801 lea(rscratch, src);
2802 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
2803 }
2804 }
2805
2806 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2807 assert(UseAVX > 0, "requires some form of AVX");
2808 assert(rscratch != noreg || always_reachable(src), "missing");
2809
2810 if (reachable(src)) {
2811 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
2812 } else {
2813 lea(rscratch, src);
2814 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
2815 }
2816 }
2817
2818 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2819 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2820 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2821
2822 vandps(dst, nds, negate_field, vector_len, rscratch);
2823 }
2824
2825 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2826 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2827 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2828
2829 vandpd(dst, nds, negate_field, vector_len, rscratch);
2830 }
2831
2832 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2833 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2834 Assembler::vpaddb(dst, nds, src, vector_len);
2835 }
2836
2837 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2838 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2839 Assembler::vpaddb(dst, nds, src, vector_len);
2840 }
2841
2842 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2843 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2844 Assembler::vpaddw(dst, nds, src, vector_len);
2845 }
2846
2847 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2848 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2849 Assembler::vpaddw(dst, nds, src, vector_len);
2850 }
2851
2852 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2853 assert(rscratch != noreg || always_reachable(src), "missing");
2854
2855 if (reachable(src)) {
2856 Assembler::vpand(dst, nds, as_Address(src), vector_len);
2857 } else {
2858 lea(rscratch, src);
2859 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
2860 }
2861 }
2862
2863 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2864 assert(rscratch != noreg || always_reachable(src), "missing");
2865
2866 if (reachable(src)) {
2867 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
2868 } else {
2869 lea(rscratch, src);
2870 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
2871 }
2872 }
2873
2874 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2875 assert(rscratch != noreg || always_reachable(src), "missing");
2876
2877 if (reachable(src)) {
2878 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
2879 } else {
2880 lea(rscratch, src);
2881 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
2882 }
2883 }
2884
2885 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2886 assert(rscratch != noreg || always_reachable(src), "missing");
2887
2888 if (reachable(src)) {
2889 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
2890 } else {
2891 lea(rscratch, src);
2892 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
2893 }
2894 }
2895
2896 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2897 assert(rscratch != noreg || always_reachable(src), "missing");
2898
2899 if (reachable(src)) {
2900 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
2901 } else {
2902 lea(rscratch, src);
2903 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
2904 }
2905 }
2906
2907 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2908 assert(rscratch != noreg || always_reachable(src), "missing");
2909
2910 if (reachable(src)) {
2911 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
2912 } else {
2913 lea(rscratch, src);
2914 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
2915 }
2916 }
2917
2918 // Vector float blend
2919 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
2920 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
2921 // WARN: Allow dst == (src1|src2), mask == scratch
2922 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
2923 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
2924 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
2925 bool dst_available = dst != mask && (dst != src1 || dst != src2);
2926 if (blend_emulation && scratch_available && dst_available) {
2927 if (compute_mask) {
2928 vpsrad(scratch, mask, 32, vector_len);
2929 mask = scratch;
2930 }
2931 if (dst == src1) {
2932 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
2933 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
2934 } else {
2935 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
2936 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
2937 }
2938 vpor(dst, dst, scratch, vector_len);
2939 } else {
2940 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
2941 }
2942 }
2943
2944 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
2945 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
2946 // WARN: Allow dst == (src1|src2), mask == scratch
2947 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
2948 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
2949 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
2950 bool dst_available = dst != mask && (dst != src1 || dst != src2);
2951 if (blend_emulation && scratch_available && dst_available) {
2952 if (compute_mask) {
2953 vpxor(scratch, scratch, scratch, vector_len);
2954 vpcmpgtq(scratch, scratch, mask, vector_len);
2955 mask = scratch;
2956 }
2957 if (dst == src1) {
2958 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
2959 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
2960 } else {
2961 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
2962 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
2963 }
2964 vpor(dst, dst, scratch, vector_len);
2965 } else {
2966 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
2967 }
2968 }
2969
2970 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2971 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2972 Assembler::vpcmpeqb(dst, nds, src, vector_len);
2973 }
2974
2975 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
2976 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2977 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
2978 }
2979
2980 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2981 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2982 Assembler::vpcmpeqw(dst, nds, src, vector_len);
2983 }
2984
2985 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2986 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2987 Assembler::vpcmpeqw(dst, nds, src, vector_len);
2988 }
2989
2990 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2991 assert(rscratch != noreg || always_reachable(src), "missing");
2992
2993 if (reachable(src)) {
2994 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
2995 } else {
2996 lea(rscratch, src);
2997 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
2998 }
2999 }
3000
3001 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3002 int comparison, bool is_signed, int vector_len, Register rscratch) {
3003 assert(rscratch != noreg || always_reachable(src), "missing");
3004
3005 if (reachable(src)) {
3006 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3007 } else {
3008 lea(rscratch, src);
3009 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3010 }
3011 }
3012
3013 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3014 int comparison, bool is_signed, int vector_len, Register rscratch) {
3015 assert(rscratch != noreg || always_reachable(src), "missing");
3016
3017 if (reachable(src)) {
3018 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3019 } else {
3020 lea(rscratch, src);
3021 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3022 }
3023 }
3024
3025 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3026 int comparison, bool is_signed, int vector_len, Register rscratch) {
3027 assert(rscratch != noreg || always_reachable(src), "missing");
3028
3029 if (reachable(src)) {
3030 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3031 } else {
3032 lea(rscratch, src);
3033 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3034 }
3035 }
3036
3037 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3038 int comparison, bool is_signed, int vector_len, Register rscratch) {
3039 assert(rscratch != noreg || always_reachable(src), "missing");
3040
3041 if (reachable(src)) {
3042 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3043 } else {
3044 lea(rscratch, src);
3045 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3046 }
3047 }
3048
3049 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3050 if (width == Assembler::Q) {
3051 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3052 } else {
3053 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3054 }
3055 }
3056
3057 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3058 int eq_cond_enc = 0x29;
3059 int gt_cond_enc = 0x37;
3060 if (width != Assembler::Q) {
3061 eq_cond_enc = 0x74 + width;
3062 gt_cond_enc = 0x64 + width;
3063 }
3064 switch (cond) {
3065 case eq:
3066 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3067 break;
3068 case neq:
3069 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3070 vallones(xtmp, vector_len);
3071 vpxor(dst, xtmp, dst, vector_len);
3072 break;
3073 case le:
3074 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3075 vallones(xtmp, vector_len);
3076 vpxor(dst, xtmp, dst, vector_len);
3077 break;
3078 case nlt:
3079 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3080 vallones(xtmp, vector_len);
3081 vpxor(dst, xtmp, dst, vector_len);
3082 break;
3083 case lt:
3084 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3085 break;
3086 case nle:
3087 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3088 break;
3089 default:
3090 assert(false, "Should not reach here");
3091 }
3092 }
3093
3094 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3095 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3096 Assembler::vpmovzxbw(dst, src, vector_len);
3097 }
3098
3099 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3100 assert((src->encoding() < 16),"XMM register should be 0-15");
3101 Assembler::vpmovmskb(dst, src, vector_len);
3102 }
3103
3104 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3105 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3106 Assembler::vpmullw(dst, nds, src, vector_len);
3107 }
3108
3109 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3110 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3111 Assembler::vpmullw(dst, nds, src, vector_len);
3112 }
3113
3114 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3115 assert((UseAVX > 0), "AVX support is needed");
3116 assert(rscratch != noreg || always_reachable(src), "missing");
3117
3118 if (reachable(src)) {
3119 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3120 } else {
3121 lea(rscratch, src);
3122 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3123 }
3124 }
3125
3126 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3127 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3128 Assembler::vpsubb(dst, nds, src, vector_len);
3129 }
3130
3131 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3132 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3133 Assembler::vpsubb(dst, nds, src, vector_len);
3134 }
3135
3136 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3137 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3138 Assembler::vpsubw(dst, nds, src, vector_len);
3139 }
3140
3141 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3142 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3143 Assembler::vpsubw(dst, nds, src, vector_len);
3144 }
3145
3146 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3147 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3148 Assembler::vpsraw(dst, nds, shift, vector_len);
3149 }
3150
3151 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3152 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3153 Assembler::vpsraw(dst, nds, shift, vector_len);
3154 }
3155
3156 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3157 assert(UseAVX > 2,"");
3158 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3159 vector_len = 2;
3160 }
3161 Assembler::evpsraq(dst, nds, shift, vector_len);
3162 }
3163
3164 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3165 assert(UseAVX > 2,"");
3166 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3167 vector_len = 2;
3168 }
3169 Assembler::evpsraq(dst, nds, shift, vector_len);
3170 }
3171
3172 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3173 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3174 Assembler::vpsrlw(dst, nds, shift, vector_len);
3175 }
3176
3177 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3178 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3179 Assembler::vpsrlw(dst, nds, shift, vector_len);
3180 }
3181
3182 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3183 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3184 Assembler::vpsllw(dst, nds, shift, vector_len);
3185 }
3186
3187 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3188 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3189 Assembler::vpsllw(dst, nds, shift, vector_len);
3190 }
3191
3192 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3193 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3194 Assembler::vptest(dst, src);
3195 }
3196
3197 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3198 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3199 Assembler::punpcklbw(dst, src);
3200 }
3201
3202 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3203 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3204 Assembler::pshufd(dst, src, mode);
3205 }
3206
3207 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3208 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3209 Assembler::pshuflw(dst, src, mode);
3210 }
3211
3212 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3213 assert(rscratch != noreg || always_reachable(src), "missing");
3214
3215 if (reachable(src)) {
3216 vandpd(dst, nds, as_Address(src), vector_len);
3217 } else {
3218 lea(rscratch, src);
3219 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3220 }
3221 }
3222
3223 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3224 assert(rscratch != noreg || always_reachable(src), "missing");
3225
3226 if (reachable(src)) {
3227 vandps(dst, nds, as_Address(src), vector_len);
3228 } else {
3229 lea(rscratch, src);
3230 vandps(dst, nds, Address(rscratch, 0), vector_len);
3231 }
3232 }
3233
3234 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3235 bool merge, int vector_len, Register rscratch) {
3236 assert(rscratch != noreg || always_reachable(src), "missing");
3237
3238 if (reachable(src)) {
3239 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3240 } else {
3241 lea(rscratch, src);
3242 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3243 }
3244 }
3245
3246 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3247 assert(rscratch != noreg || always_reachable(src), "missing");
3248
3249 if (reachable(src)) {
3250 vdivsd(dst, nds, as_Address(src));
3251 } else {
3252 lea(rscratch, src);
3253 vdivsd(dst, nds, Address(rscratch, 0));
3254 }
3255 }
3256
3257 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3258 assert(rscratch != noreg || always_reachable(src), "missing");
3259
3260 if (reachable(src)) {
3261 vdivss(dst, nds, as_Address(src));
3262 } else {
3263 lea(rscratch, src);
3264 vdivss(dst, nds, Address(rscratch, 0));
3265 }
3266 }
3267
3268 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3269 assert(rscratch != noreg || always_reachable(src), "missing");
3270
3271 if (reachable(src)) {
3272 vmulsd(dst, nds, as_Address(src));
3273 } else {
3274 lea(rscratch, src);
3275 vmulsd(dst, nds, Address(rscratch, 0));
3276 }
3277 }
3278
3279 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3280 assert(rscratch != noreg || always_reachable(src), "missing");
3281
3282 if (reachable(src)) {
3283 vmulss(dst, nds, as_Address(src));
3284 } else {
3285 lea(rscratch, src);
3286 vmulss(dst, nds, Address(rscratch, 0));
3287 }
3288 }
3289
3290 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3291 assert(rscratch != noreg || always_reachable(src), "missing");
3292
3293 if (reachable(src)) {
3294 vsubsd(dst, nds, as_Address(src));
3295 } else {
3296 lea(rscratch, src);
3297 vsubsd(dst, nds, Address(rscratch, 0));
3298 }
3299 }
3300
3301 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3302 assert(rscratch != noreg || always_reachable(src), "missing");
3303
3304 if (reachable(src)) {
3305 vsubss(dst, nds, as_Address(src));
3306 } else {
3307 lea(rscratch, src);
3308 vsubss(dst, nds, Address(rscratch, 0));
3309 }
3310 }
3311
3312 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3313 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3314 assert(rscratch != noreg || always_reachable(src), "missing");
3315
3316 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3317 }
3318
3319 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3320 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3321 assert(rscratch != noreg || always_reachable(src), "missing");
3322
3323 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3324 }
3325
3326 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3327 assert(rscratch != noreg || always_reachable(src), "missing");
3328
3329 if (reachable(src)) {
3330 vxorpd(dst, nds, as_Address(src), vector_len);
3331 } else {
3332 lea(rscratch, src);
3333 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3334 }
3335 }
3336
3337 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3338 assert(rscratch != noreg || always_reachable(src), "missing");
3339
3340 if (reachable(src)) {
3341 vxorps(dst, nds, as_Address(src), vector_len);
3342 } else {
3343 lea(rscratch, src);
3344 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3345 }
3346 }
3347
3348 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3349 assert(rscratch != noreg || always_reachable(src), "missing");
3350
3351 if (UseAVX > 1 || (vector_len < 1)) {
3352 if (reachable(src)) {
3353 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3354 } else {
3355 lea(rscratch, src);
3356 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3357 }
3358 } else {
3359 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3360 }
3361 }
3362
3363 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3364 assert(rscratch != noreg || always_reachable(src), "missing");
3365
3366 if (reachable(src)) {
3367 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3368 } else {
3369 lea(rscratch, src);
3370 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3371 }
3372 }
3373
3374 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3375 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3376 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3377 // The inverted mask is sign-extended
3378 andptr(possibly_non_local, inverted_mask);
3379 }
3380
3381 void MacroAssembler::resolve_jobject(Register value,
3382 Register tmp) {
3383 Register thread = r15_thread;
3384 assert_different_registers(value, thread, tmp);
3385 Label done, tagged, weak_tagged;
3386 testptr(value, value);
3387 jcc(Assembler::zero, done); // Use null as-is.
3388 testptr(value, JNIHandles::tag_mask); // Test for tag.
3389 jcc(Assembler::notZero, tagged);
3390
3391 // Resolve local handle
3392 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp);
3393 verify_oop(value);
3394 jmp(done);
3395
3396 bind(tagged);
3397 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
3398 jcc(Assembler::notZero, weak_tagged);
3399
3400 // Resolve global handle
3401 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3402 verify_oop(value);
3403 jmp(done);
3404
3405 bind(weak_tagged);
3406 // Resolve jweak.
3407 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3408 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp);
3409 verify_oop(value);
3410
3411 bind(done);
3412 }
3413
3414 void MacroAssembler::resolve_global_jobject(Register value,
3415 Register tmp) {
3416 Register thread = r15_thread;
3417 assert_different_registers(value, thread, tmp);
3418 Label done;
3419
3420 testptr(value, value);
3421 jcc(Assembler::zero, done); // Use null as-is.
3422
3423 #ifdef ASSERT
3424 {
3425 Label valid_global_tag;
3426 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
3427 jcc(Assembler::notZero, valid_global_tag);
3428 stop("non global jobject using resolve_global_jobject");
3429 bind(valid_global_tag);
3430 }
3431 #endif
3432
3433 // Resolve global handle
3434 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3435 verify_oop(value);
3436
3437 bind(done);
3438 }
3439
3440 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3441 subq(dst, imm32);
3442 }
3443
3444 // Force generation of a 4 byte immediate value even if it fits into 8bit
3445 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3446 subq_imm32(dst, imm32);
3447 }
3448
3449 void MacroAssembler::subptr(Register dst, Register src) {
3450 subq(dst, src);
3451 }
3452
3453 // C++ bool manipulation
3454 void MacroAssembler::testbool(Register dst) {
3455 if(sizeof(bool) == 1)
3456 testb(dst, 0xff);
3457 else if(sizeof(bool) == 2) {
3458 // testw implementation needed for two byte bools
3459 ShouldNotReachHere();
3460 } else if(sizeof(bool) == 4)
3461 testl(dst, dst);
3462 else
3463 // unsupported
3464 ShouldNotReachHere();
3465 }
3466
3467 void MacroAssembler::testptr(Register dst, Register src) {
3468 testq(dst, src);
3469 }
3470
3471 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3472 void MacroAssembler::tlab_allocate(Register obj,
3473 Register var_size_in_bytes,
3474 int con_size_in_bytes,
3475 Register t1,
3476 Register t2,
3477 Label& slow_case) {
3478 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3479 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3480 }
3481
3482 RegSet MacroAssembler::call_clobbered_gp_registers() {
3483 RegSet regs;
3484 regs += RegSet::of(rax, rcx, rdx);
3485 #ifndef _WINDOWS
3486 regs += RegSet::of(rsi, rdi);
3487 #endif
3488 regs += RegSet::range(r8, r11);
3489 if (UseAPX) {
3490 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
3491 }
3492 return regs;
3493 }
3494
3495 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
3496 int num_xmm_registers = XMMRegister::available_xmm_registers();
3497 #if defined(_WINDOWS)
3498 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
3499 if (num_xmm_registers > 16) {
3500 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
3501 }
3502 return result;
3503 #else
3504 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
3505 #endif
3506 }
3507
3508 // C1 only ever uses the first double/float of the XMM register.
3509 static int xmm_save_size() { return sizeof(double); }
3510
3511 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3512 masm->movdbl(Address(rsp, offset), reg);
3513 }
3514
3515 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3516 masm->movdbl(reg, Address(rsp, offset));
3517 }
3518
3519 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
3520 bool save_fpu, int& gp_area_size, int& xmm_area_size) {
3521
3522 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
3523 StackAlignmentInBytes);
3524 xmm_area_size = save_fpu ? xmm_registers.size() * xmm_save_size() : 0;
3525
3526 return gp_area_size + xmm_area_size;
3527 }
3528
3529 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
3530 block_comment("push_call_clobbered_registers start");
3531 // Regular registers
3532 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
3533
3534 int gp_area_size;
3535 int xmm_area_size;
3536 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
3537 gp_area_size, xmm_area_size);
3538 subptr(rsp, total_save_size);
3539
3540 push_set(gp_registers_to_push, 0);
3541
3542 if (save_fpu) {
3543 push_set(call_clobbered_xmm_registers(), gp_area_size);
3544 }
3545
3546 block_comment("push_call_clobbered_registers end");
3547 }
3548
3549 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
3550 block_comment("pop_call_clobbered_registers start");
3551
3552 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
3553
3554 int gp_area_size;
3555 int xmm_area_size;
3556 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
3557 gp_area_size, xmm_area_size);
3558
3559 if (restore_fpu) {
3560 pop_set(call_clobbered_xmm_registers(), gp_area_size);
3561 }
3562
3563 pop_set(gp_registers_to_pop, 0);
3564
3565 addptr(rsp, total_save_size);
3566
3567 vzeroupper();
3568
3569 block_comment("pop_call_clobbered_registers end");
3570 }
3571
3572 void MacroAssembler::push_set(XMMRegSet set, int offset) {
3573 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
3574 int spill_offset = offset;
3575
3576 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
3577 save_xmm_register(this, spill_offset, *it);
3578 spill_offset += xmm_save_size();
3579 }
3580 }
3581
3582 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
3583 int restore_size = set.size() * xmm_save_size();
3584 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
3585
3586 int restore_offset = offset + restore_size - xmm_save_size();
3587
3588 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
3589 restore_xmm_register(this, restore_offset, *it);
3590 restore_offset -= xmm_save_size();
3591 }
3592 }
3593
3594 void MacroAssembler::push_set(RegSet set, int offset) {
3595 int spill_offset;
3596 if (offset == -1) {
3597 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3598 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
3599 subptr(rsp, aligned_size);
3600 spill_offset = 0;
3601 } else {
3602 spill_offset = offset;
3603 }
3604
3605 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
3606 movptr(Address(rsp, spill_offset), *it);
3607 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3608 }
3609 }
3610
3611 void MacroAssembler::pop_set(RegSet set, int offset) {
3612
3613 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3614 int restore_size = set.size() * gp_reg_size;
3615 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
3616
3617 int restore_offset;
3618 if (offset == -1) {
3619 restore_offset = restore_size - gp_reg_size;
3620 } else {
3621 restore_offset = offset + restore_size - gp_reg_size;
3622 }
3623 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
3624 movptr(*it, Address(rsp, restore_offset));
3625 restore_offset -= gp_reg_size;
3626 }
3627
3628 if (offset == -1) {
3629 addptr(rsp, aligned_size);
3630 }
3631 }
3632
3633 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3634 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3635 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3636 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3637 Label done;
3638
3639 testptr(length_in_bytes, length_in_bytes);
3640 jcc(Assembler::zero, done);
3641
3642 // initialize topmost word, divide index by 2, check if odd and test if zero
3643 // note: for the remaining code to work, index must be a multiple of BytesPerWord
3644 #ifdef ASSERT
3645 {
3646 Label L;
3647 testptr(length_in_bytes, BytesPerWord - 1);
3648 jcc(Assembler::zero, L);
3649 stop("length must be a multiple of BytesPerWord");
3650 bind(L);
3651 }
3652 #endif
3653 Register index = length_in_bytes;
3654 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
3655 if (UseIncDec) {
3656 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
3657 } else {
3658 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
3659 shrptr(index, 1);
3660 }
3661
3662 // initialize remaining object fields: index is a multiple of 2 now
3663 {
3664 Label loop;
3665 bind(loop);
3666 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3667 decrement(index);
3668 jcc(Assembler::notZero, loop);
3669 }
3670
3671 bind(done);
3672 }
3673
3674 // Look up the method for a megamorphic invokeinterface call.
3675 // The target method is determined by <intf_klass, itable_index>.
3676 // The receiver klass is in recv_klass.
3677 // On success, the result will be in method_result, and execution falls through.
3678 // On failure, execution transfers to the given label.
3679 void MacroAssembler::lookup_interface_method(Register recv_klass,
3680 Register intf_klass,
3681 RegisterOrConstant itable_index,
3682 Register method_result,
3683 Register scan_temp,
3684 Label& L_no_such_interface,
3685 bool return_method) {
3686 assert_different_registers(recv_klass, intf_klass, scan_temp);
3687 assert_different_registers(method_result, intf_klass, scan_temp);
3688 assert(recv_klass != method_result || !return_method,
3689 "recv_klass can be destroyed when method isn't needed");
3690
3691 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3692 "caller must use same register for non-constant itable index as for method");
3693
3694 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3695 int vtable_base = in_bytes(Klass::vtable_start_offset());
3696 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3697 int scan_step = itableOffsetEntry::size() * wordSize;
3698 int vte_size = vtableEntry::size_in_bytes();
3699 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3700 assert(vte_size == wordSize, "else adjust times_vte_scale");
3701
3702 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3703
3704 // Could store the aligned, prescaled offset in the klass.
3705 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3706
3707 if (return_method) {
3708 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3709 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3710 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3711 }
3712
3713 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
3714 // if (scan->interface() == intf) {
3715 // result = (klass + scan->offset() + itable_index);
3716 // }
3717 // }
3718 Label search, found_method;
3719
3720 for (int peel = 1; peel >= 0; peel--) {
3721 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
3722 cmpptr(intf_klass, method_result);
3723
3724 if (peel) {
3725 jccb(Assembler::equal, found_method);
3726 } else {
3727 jccb(Assembler::notEqual, search);
3728 // (invert the test to fall through to found_method...)
3729 }
3730
3731 if (!peel) break;
3732
3733 bind(search);
3734
3735 // Check that the previous entry is non-null. A null entry means that
3736 // the receiver class doesn't implement the interface, and wasn't the
3737 // same as when the caller was compiled.
3738 testptr(method_result, method_result);
3739 jcc(Assembler::zero, L_no_such_interface);
3740 addptr(scan_temp, scan_step);
3741 }
3742
3743 bind(found_method);
3744
3745 if (return_method) {
3746 // Got a hit.
3747 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
3748 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
3749 }
3750 }
3751
3752 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
3753 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
3754 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
3755 // The target method is determined by <holder_klass, itable_index>.
3756 // The receiver klass is in recv_klass.
3757 // On success, the result will be in method_result, and execution falls through.
3758 // On failure, execution transfers to the given label.
3759 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
3760 Register holder_klass,
3761 Register resolved_klass,
3762 Register method_result,
3763 Register scan_temp,
3764 Register temp_reg2,
3765 Register receiver,
3766 int itable_index,
3767 Label& L_no_such_interface) {
3768 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
3769 Register temp_itbl_klass = method_result;
3770 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
3771
3772 int vtable_base = in_bytes(Klass::vtable_start_offset());
3773 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3774 int scan_step = itableOffsetEntry::size() * wordSize;
3775 int vte_size = vtableEntry::size_in_bytes();
3776 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
3777 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
3778 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3779 assert(vte_size == wordSize, "adjust times_vte_scale");
3780
3781 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
3782
3783 // temp_itbl_klass = recv_klass.itable[0]
3784 // scan_temp = &recv_klass.itable[0] + step
3785 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3786 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
3787 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
3788 xorptr(temp_reg, temp_reg);
3789
3790 // Initial checks:
3791 // - if (holder_klass != resolved_klass), go to "scan for resolved"
3792 // - if (itable[0] == 0), no such interface
3793 // - if (itable[0] == holder_klass), shortcut to "holder found"
3794 cmpptr(holder_klass, resolved_klass);
3795 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
3796 testptr(temp_itbl_klass, temp_itbl_klass);
3797 jccb(Assembler::zero, L_no_such_interface);
3798 cmpptr(holder_klass, temp_itbl_klass);
3799 jccb(Assembler::equal, L_holder_found);
3800
3801 // Loop: Look for holder_klass record in itable
3802 // do {
3803 // tmp = itable[index];
3804 // index += step;
3805 // if (tmp == holder_klass) {
3806 // goto L_holder_found; // Found!
3807 // }
3808 // } while (tmp != 0);
3809 // goto L_no_such_interface // Not found.
3810 Label L_scan_holder;
3811 bind(L_scan_holder);
3812 movptr(temp_itbl_klass, Address(scan_temp, 0));
3813 addptr(scan_temp, scan_step);
3814 cmpptr(holder_klass, temp_itbl_klass);
3815 jccb(Assembler::equal, L_holder_found);
3816 testptr(temp_itbl_klass, temp_itbl_klass);
3817 jccb(Assembler::notZero, L_scan_holder);
3818
3819 jmpb(L_no_such_interface);
3820
3821 // Loop: Look for resolved_class record in itable
3822 // do {
3823 // tmp = itable[index];
3824 // index += step;
3825 // if (tmp == holder_klass) {
3826 // // Also check if we have met a holder klass
3827 // holder_tmp = itable[index-step-ioffset];
3828 // }
3829 // if (tmp == resolved_klass) {
3830 // goto L_resolved_found; // Found!
3831 // }
3832 // } while (tmp != 0);
3833 // goto L_no_such_interface // Not found.
3834 //
3835 Label L_loop_scan_resolved;
3836 bind(L_loop_scan_resolved);
3837 movptr(temp_itbl_klass, Address(scan_temp, 0));
3838 addptr(scan_temp, scan_step);
3839 bind(L_loop_scan_resolved_entry);
3840 cmpptr(holder_klass, temp_itbl_klass);
3841 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
3842 cmpptr(resolved_klass, temp_itbl_klass);
3843 jccb(Assembler::equal, L_resolved_found);
3844 testptr(temp_itbl_klass, temp_itbl_klass);
3845 jccb(Assembler::notZero, L_loop_scan_resolved);
3846
3847 jmpb(L_no_such_interface);
3848
3849 Label L_ready;
3850
3851 // See if we already have a holder klass. If not, go and scan for it.
3852 bind(L_resolved_found);
3853 testptr(temp_reg, temp_reg);
3854 jccb(Assembler::zero, L_scan_holder);
3855 jmpb(L_ready);
3856
3857 bind(L_holder_found);
3858 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
3859
3860 // Finally, temp_reg contains holder_klass vtable offset
3861 bind(L_ready);
3862 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3863 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
3864 load_klass(scan_temp, receiver, noreg);
3865 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
3866 } else {
3867 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
3868 }
3869 }
3870
3871
3872 // virtual method calling
3873 void MacroAssembler::lookup_virtual_method(Register recv_klass,
3874 RegisterOrConstant vtable_index,
3875 Register method_result) {
3876 const ByteSize base = Klass::vtable_start_offset();
3877 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
3878 Address vtable_entry_addr(recv_klass,
3879 vtable_index, Address::times_ptr,
3880 base + vtableEntry::method_offset());
3881 movptr(method_result, vtable_entry_addr);
3882 }
3883
3884
3885 void MacroAssembler::check_klass_subtype(Register sub_klass,
3886 Register super_klass,
3887 Register temp_reg,
3888 Label& L_success) {
3889 Label L_failure;
3890 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
3891 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
3892 bind(L_failure);
3893 }
3894
3895
3896 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
3897 Register super_klass,
3898 Register temp_reg,
3899 Label* L_success,
3900 Label* L_failure,
3901 Label* L_slow_path,
3902 RegisterOrConstant super_check_offset) {
3903 assert_different_registers(sub_klass, super_klass, temp_reg);
3904 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
3905 if (super_check_offset.is_register()) {
3906 assert_different_registers(sub_klass, super_klass,
3907 super_check_offset.as_register());
3908 } else if (must_load_sco) {
3909 assert(temp_reg != noreg, "supply either a temp or a register offset");
3910 }
3911
3912 Label L_fallthrough;
3913 int label_nulls = 0;
3914 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
3915 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
3916 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
3917 assert(label_nulls <= 1, "at most one null in the batch");
3918
3919 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3920 int sco_offset = in_bytes(Klass::super_check_offset_offset());
3921 Address super_check_offset_addr(super_klass, sco_offset);
3922
3923 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
3924 // range of a jccb. If this routine grows larger, reconsider at
3925 // least some of these.
3926 #define local_jcc(assembler_cond, label) \
3927 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
3928 else jcc( assembler_cond, label) /*omit semi*/
3929
3930 // Hacked jmp, which may only be used just before L_fallthrough.
3931 #define final_jmp(label) \
3932 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
3933 else jmp(label) /*omit semi*/
3934
3935 // If the pointers are equal, we are done (e.g., String[] elements).
3936 // This self-check enables sharing of secondary supertype arrays among
3937 // non-primary types such as array-of-interface. Otherwise, each such
3938 // type would need its own customized SSA.
3939 // We move this check to the front of the fast path because many
3940 // type checks are in fact trivially successful in this manner,
3941 // so we get a nicely predicted branch right at the start of the check.
3942 cmpptr(sub_klass, super_klass);
3943 local_jcc(Assembler::equal, *L_success);
3944
3945 // Check the supertype display:
3946 if (must_load_sco) {
3947 // Positive movl does right thing on LP64.
3948 movl(temp_reg, super_check_offset_addr);
3949 super_check_offset = RegisterOrConstant(temp_reg);
3950 }
3951 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
3952 cmpptr(super_klass, super_check_addr); // load displayed supertype
3953
3954 // This check has worked decisively for primary supers.
3955 // Secondary supers are sought in the super_cache ('super_cache_addr').
3956 // (Secondary supers are interfaces and very deeply nested subtypes.)
3957 // This works in the same check above because of a tricky aliasing
3958 // between the super_cache and the primary super display elements.
3959 // (The 'super_check_addr' can address either, as the case requires.)
3960 // Note that the cache is updated below if it does not help us find
3961 // what we need immediately.
3962 // So if it was a primary super, we can just fail immediately.
3963 // Otherwise, it's the slow path for us (no success at this point).
3964
3965 if (super_check_offset.is_register()) {
3966 local_jcc(Assembler::equal, *L_success);
3967 cmpl(super_check_offset.as_register(), sc_offset);
3968 if (L_failure == &L_fallthrough) {
3969 local_jcc(Assembler::equal, *L_slow_path);
3970 } else {
3971 local_jcc(Assembler::notEqual, *L_failure);
3972 final_jmp(*L_slow_path);
3973 }
3974 } else if (super_check_offset.as_constant() == sc_offset) {
3975 // Need a slow path; fast failure is impossible.
3976 if (L_slow_path == &L_fallthrough) {
3977 local_jcc(Assembler::equal, *L_success);
3978 } else {
3979 local_jcc(Assembler::notEqual, *L_slow_path);
3980 final_jmp(*L_success);
3981 }
3982 } else {
3983 // No slow path; it's a fast decision.
3984 if (L_failure == &L_fallthrough) {
3985 local_jcc(Assembler::equal, *L_success);
3986 } else {
3987 local_jcc(Assembler::notEqual, *L_failure);
3988 final_jmp(*L_success);
3989 }
3990 }
3991
3992 bind(L_fallthrough);
3993
3994 #undef local_jcc
3995 #undef final_jmp
3996 }
3997
3998
3999 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4000 Register super_klass,
4001 Register temp_reg,
4002 Register temp2_reg,
4003 Label* L_success,
4004 Label* L_failure,
4005 bool set_cond_codes) {
4006 assert_different_registers(sub_klass, super_klass, temp_reg);
4007 if (temp2_reg != noreg)
4008 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4009 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4010
4011 Label L_fallthrough;
4012 int label_nulls = 0;
4013 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4014 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4015 assert(label_nulls <= 1, "at most one null in the batch");
4016
4017 // a couple of useful fields in sub_klass:
4018 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4019 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4020 Address secondary_supers_addr(sub_klass, ss_offset);
4021 Address super_cache_addr( sub_klass, sc_offset);
4022
4023 // Do a linear scan of the secondary super-klass chain.
4024 // This code is rarely used, so simplicity is a virtue here.
4025 // The repne_scan instruction uses fixed registers, which we must spill.
4026 // Don't worry too much about pre-existing connections with the input regs.
4027
4028 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4029 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4030
4031 // Get super_klass value into rax (even if it was in rdi or rcx).
4032 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4033 if (super_klass != rax) {
4034 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4035 mov(rax, super_klass);
4036 }
4037 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4038 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4039
4040 #ifndef PRODUCT
4041 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4042 ExternalAddress pst_counter_addr((address) pst_counter);
4043 lea(rcx, pst_counter_addr);
4044 incrementl(Address(rcx, 0));
4045 #endif //PRODUCT
4046
4047 // We will consult the secondary-super array.
4048 movptr(rdi, secondary_supers_addr);
4049 // Load the array length. (Positive movl does right thing on LP64.)
4050 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4051 // Skip to start of data.
4052 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4053
4054 // Scan RCX words at [RDI] for an occurrence of RAX.
4055 // Set NZ/Z based on last compare.
4056 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4057 // not change flags (only scas instruction which is repeated sets flags).
4058 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4059
4060 testptr(rax,rax); // Set Z = 0
4061 repne_scan();
4062
4063 // Unspill the temp. registers:
4064 if (pushed_rdi) pop(rdi);
4065 if (pushed_rcx) pop(rcx);
4066 if (pushed_rax) pop(rax);
4067
4068 if (set_cond_codes) {
4069 // Special hack for the AD files: rdi is guaranteed non-zero.
4070 assert(!pushed_rdi, "rdi must be left non-null");
4071 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4072 }
4073
4074 if (L_failure == &L_fallthrough)
4075 jccb(Assembler::notEqual, *L_failure);
4076 else jcc(Assembler::notEqual, *L_failure);
4077
4078 // Success. Cache the super we found and proceed in triumph.
4079 movptr(super_cache_addr, super_klass);
4080
4081 if (L_success != &L_fallthrough) {
4082 jmp(*L_success);
4083 }
4084
4085 #undef IS_A_TEMP
4086
4087 bind(L_fallthrough);
4088 }
4089
4090 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4091 Register super_klass,
4092 Register temp_reg,
4093 Register temp2_reg,
4094 Label* L_success,
4095 Label* L_failure,
4096 bool set_cond_codes) {
4097 assert(set_cond_codes == false, "must be false on 64-bit x86");
4098 check_klass_subtype_slow_path
4099 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4100 L_success, L_failure);
4101 }
4102
4103 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4104 Register super_klass,
4105 Register temp_reg,
4106 Register temp2_reg,
4107 Register temp3_reg,
4108 Register temp4_reg,
4109 Label* L_success,
4110 Label* L_failure) {
4111 if (UseSecondarySupersTable) {
4112 check_klass_subtype_slow_path_table
4113 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4114 L_success, L_failure);
4115 } else {
4116 check_klass_subtype_slow_path_linear
4117 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4118 }
4119 }
4120
4121 Register MacroAssembler::allocate_if_noreg(Register r,
4122 RegSetIterator<Register> &available_regs,
4123 RegSet ®s_to_push) {
4124 if (!r->is_valid()) {
4125 r = *available_regs++;
4126 regs_to_push += r;
4127 }
4128 return r;
4129 }
4130
4131 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4132 Register super_klass,
4133 Register temp_reg,
4134 Register temp2_reg,
4135 Register temp3_reg,
4136 Register result_reg,
4137 Label* L_success,
4138 Label* L_failure) {
4139 // NB! Callers may assume that, when temp2_reg is a valid register,
4140 // this code sets it to a nonzero value.
4141 bool temp2_reg_was_valid = temp2_reg->is_valid();
4142
4143 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4144
4145 Label L_fallthrough;
4146 int label_nulls = 0;
4147 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4148 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4149 assert(label_nulls <= 1, "at most one null in the batch");
4150
4151 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4152
4153 RegSetIterator<Register> available_regs
4154 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4155
4156 RegSet pushed_regs;
4157
4158 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4159 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4160 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4161 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4162 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4163
4164 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4165
4166 {
4167
4168 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4169 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4170 subptr(rsp, aligned_size);
4171 push_set(pushed_regs, 0);
4172
4173 lookup_secondary_supers_table_var(sub_klass,
4174 super_klass,
4175 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4176 cmpq(result_reg, 0);
4177
4178 // Unspill the temp. registers:
4179 pop_set(pushed_regs, 0);
4180 // Increment SP but do not clobber flags.
4181 lea(rsp, Address(rsp, aligned_size));
4182 }
4183
4184 if (temp2_reg_was_valid) {
4185 movq(temp2_reg, 1);
4186 }
4187
4188 jcc(Assembler::notEqual, *L_failure);
4189
4190 if (L_success != &L_fallthrough) {
4191 jmp(*L_success);
4192 }
4193
4194 bind(L_fallthrough);
4195 }
4196
4197 // population_count variant for running without the POPCNT
4198 // instruction, which was introduced with SSE4.2 in 2008.
4199 void MacroAssembler::population_count(Register dst, Register src,
4200 Register scratch1, Register scratch2) {
4201 assert_different_registers(src, scratch1, scratch2);
4202 if (UsePopCountInstruction) {
4203 Assembler::popcntq(dst, src);
4204 } else {
4205 assert_different_registers(src, scratch1, scratch2);
4206 assert_different_registers(dst, scratch1, scratch2);
4207 Label loop, done;
4208
4209 mov(scratch1, src);
4210 // dst = 0;
4211 // while(scratch1 != 0) {
4212 // dst++;
4213 // scratch1 &= (scratch1 - 1);
4214 // }
4215 xorl(dst, dst);
4216 testq(scratch1, scratch1);
4217 jccb(Assembler::equal, done);
4218 {
4219 bind(loop);
4220 incq(dst);
4221 movq(scratch2, scratch1);
4222 decq(scratch2);
4223 andq(scratch1, scratch2);
4224 jccb(Assembler::notEqual, loop);
4225 }
4226 bind(done);
4227 }
4228 #ifdef ASSERT
4229 mov64(scratch1, 0xCafeBabeDeadBeef);
4230 movq(scratch2, scratch1);
4231 #endif
4232 }
4233
4234 // Ensure that the inline code and the stub are using the same registers.
4235 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4236 do { \
4237 assert(r_super_klass == rax, "mismatch"); \
4238 assert(r_array_base == rbx, "mismatch"); \
4239 assert(r_array_length == rcx, "mismatch"); \
4240 assert(r_array_index == rdx, "mismatch"); \
4241 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4242 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4243 assert(result == rdi || result == noreg, "mismatch"); \
4244 } while(0)
4245
4246 // Versions of salq and rorq that don't need count to be in rcx
4247
4248 void MacroAssembler::salq(Register dest, Register count) {
4249 if (count == rcx) {
4250 Assembler::salq(dest);
4251 } else {
4252 assert_different_registers(rcx, dest);
4253 xchgq(rcx, count);
4254 Assembler::salq(dest);
4255 xchgq(rcx, count);
4256 }
4257 }
4258
4259 void MacroAssembler::rorq(Register dest, Register count) {
4260 if (count == rcx) {
4261 Assembler::rorq(dest);
4262 } else {
4263 assert_different_registers(rcx, dest);
4264 xchgq(rcx, count);
4265 Assembler::rorq(dest);
4266 xchgq(rcx, count);
4267 }
4268 }
4269
4270 // Return true: we succeeded in generating this code
4271 //
4272 // At runtime, return 0 in result if r_super_klass is a superclass of
4273 // r_sub_klass, otherwise return nonzero. Use this if you know the
4274 // super_klass_slot of the class you're looking for. This is always
4275 // the case for instanceof and checkcast.
4276 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4277 Register r_super_klass,
4278 Register temp1,
4279 Register temp2,
4280 Register temp3,
4281 Register temp4,
4282 Register result,
4283 u1 super_klass_slot) {
4284 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4285
4286 Label L_fallthrough, L_success, L_failure;
4287
4288 BLOCK_COMMENT("lookup_secondary_supers_table {");
4289
4290 const Register
4291 r_array_index = temp1,
4292 r_array_length = temp2,
4293 r_array_base = temp3,
4294 r_bitmap = temp4;
4295
4296 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4297
4298 xorq(result, result); // = 0
4299
4300 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4301 movq(r_array_index, r_bitmap);
4302
4303 // First check the bitmap to see if super_klass might be present. If
4304 // the bit is zero, we are certain that super_klass is not one of
4305 // the secondary supers.
4306 u1 bit = super_klass_slot;
4307 {
4308 // NB: If the count in a x86 shift instruction is 0, the flags are
4309 // not affected, so we do a testq instead.
4310 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4311 if (shift_count != 0) {
4312 salq(r_array_index, shift_count);
4313 } else {
4314 testq(r_array_index, r_array_index);
4315 }
4316 }
4317 // We test the MSB of r_array_index, i.e. its sign bit
4318 jcc(Assembler::positive, L_failure);
4319
4320 // Get the first array index that can contain super_klass into r_array_index.
4321 if (bit != 0) {
4322 population_count(r_array_index, r_array_index, temp2, temp3);
4323 } else {
4324 movl(r_array_index, 1);
4325 }
4326 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4327
4328 // We will consult the secondary-super array.
4329 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4330
4331 // We're asserting that the first word in an Array<Klass*> is the
4332 // length, and the second word is the first word of the data. If
4333 // that ever changes, r_array_base will have to be adjusted here.
4334 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4335 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4336
4337 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4338 jccb(Assembler::equal, L_success);
4339
4340 // Is there another entry to check? Consult the bitmap.
4341 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
4342 jccb(Assembler::carryClear, L_failure);
4343
4344 // Linear probe. Rotate the bitmap so that the next bit to test is
4345 // in Bit 1.
4346 if (bit != 0) {
4347 rorq(r_bitmap, bit);
4348 }
4349
4350 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4351 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4352 // Kills: r_array_length.
4353 // Returns: result.
4354 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
4355 // Result (0/1) is in rdi
4356 jmpb(L_fallthrough);
4357
4358 bind(L_failure);
4359 incq(result); // 0 => 1
4360
4361 bind(L_success);
4362 // result = 0;
4363
4364 bind(L_fallthrough);
4365 BLOCK_COMMENT("} lookup_secondary_supers_table");
4366
4367 if (VerifySecondarySupers) {
4368 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4369 temp1, temp2, temp3);
4370 }
4371 }
4372
4373 // At runtime, return 0 in result if r_super_klass is a superclass of
4374 // r_sub_klass, otherwise return nonzero. Use this version of
4375 // lookup_secondary_supers_table() if you don't know ahead of time
4376 // which superclass will be searched for. Used by interpreter and
4377 // runtime stubs. It is larger and has somewhat greater latency than
4378 // the version above, which takes a constant super_klass_slot.
4379 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
4380 Register r_super_klass,
4381 Register temp1,
4382 Register temp2,
4383 Register temp3,
4384 Register temp4,
4385 Register result) {
4386 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4387 assert_different_registers(r_sub_klass, r_super_klass, rcx);
4388 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
4389
4390 Label L_fallthrough, L_success, L_failure;
4391
4392 BLOCK_COMMENT("lookup_secondary_supers_table {");
4393
4394 RegSetIterator<Register> available_regs = (temps - rcx).begin();
4395
4396 // FIXME. Once we are sure that all paths reaching this point really
4397 // do pass rcx as one of our temps we can get rid of the following
4398 // workaround.
4399 assert(temps.contains(rcx), "fix this code");
4400
4401 // We prefer to have our shift count in rcx. If rcx is one of our
4402 // temps, use it for slot. If not, pick any of our temps.
4403 Register slot;
4404 if (!temps.contains(rcx)) {
4405 slot = *available_regs++;
4406 } else {
4407 slot = rcx;
4408 }
4409
4410 const Register r_array_index = *available_regs++;
4411 const Register r_bitmap = *available_regs++;
4412
4413 // The logic above guarantees this property, but we state it here.
4414 assert_different_registers(r_array_index, r_bitmap, rcx);
4415
4416 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4417 movq(r_array_index, r_bitmap);
4418
4419 // First check the bitmap to see if super_klass might be present. If
4420 // the bit is zero, we are certain that super_klass is not one of
4421 // the secondary supers.
4422 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4423 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
4424 salq(r_array_index, slot);
4425
4426 testq(r_array_index, r_array_index);
4427 // We test the MSB of r_array_index, i.e. its sign bit
4428 jcc(Assembler::positive, L_failure);
4429
4430 const Register r_array_base = *available_regs++;
4431
4432 // Get the first array index that can contain super_klass into r_array_index.
4433 // Note: Clobbers r_array_base and slot.
4434 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
4435
4436 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4437
4438 // We will consult the secondary-super array.
4439 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4440
4441 // We're asserting that the first word in an Array<Klass*> is the
4442 // length, and the second word is the first word of the data. If
4443 // that ever changes, r_array_base will have to be adjusted here.
4444 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4445 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4446
4447 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4448 jccb(Assembler::equal, L_success);
4449
4450 // Restore slot to its true value
4451 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4452
4453 // Linear probe. Rotate the bitmap so that the next bit to test is
4454 // in Bit 1.
4455 rorq(r_bitmap, slot);
4456
4457 // Is there another entry to check? Consult the bitmap.
4458 btq(r_bitmap, 1);
4459 jccb(Assembler::carryClear, L_failure);
4460
4461 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4462 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4463 // Kills: r_array_length.
4464 // Returns: result.
4465 lookup_secondary_supers_table_slow_path(r_super_klass,
4466 r_array_base,
4467 r_array_index,
4468 r_bitmap,
4469 /*temp1*/result,
4470 /*temp2*/slot,
4471 &L_success,
4472 nullptr);
4473
4474 bind(L_failure);
4475 movq(result, 1);
4476 jmpb(L_fallthrough);
4477
4478 bind(L_success);
4479 xorq(result, result); // = 0
4480
4481 bind(L_fallthrough);
4482 BLOCK_COMMENT("} lookup_secondary_supers_table");
4483
4484 if (VerifySecondarySupers) {
4485 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4486 temp1, temp2, temp3);
4487 }
4488 }
4489
4490 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
4491 Label* L_success, Label* L_failure) {
4492 Label L_loop, L_fallthrough;
4493 {
4494 int label_nulls = 0;
4495 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4496 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4497 assert(label_nulls <= 1, "at most one null in the batch");
4498 }
4499 bind(L_loop);
4500 cmpq(value, Address(addr, count, Address::times_8));
4501 jcc(Assembler::equal, *L_success);
4502 addl(count, 1);
4503 cmpl(count, limit);
4504 jcc(Assembler::less, L_loop);
4505
4506 if (&L_fallthrough != L_failure) {
4507 jmp(*L_failure);
4508 }
4509 bind(L_fallthrough);
4510 }
4511
4512 // Called by code generated by check_klass_subtype_slow_path
4513 // above. This is called when there is a collision in the hashed
4514 // lookup in the secondary supers array.
4515 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
4516 Register r_array_base,
4517 Register r_array_index,
4518 Register r_bitmap,
4519 Register temp1,
4520 Register temp2,
4521 Label* L_success,
4522 Label* L_failure) {
4523 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
4524
4525 const Register
4526 r_array_length = temp1,
4527 r_sub_klass = noreg,
4528 result = noreg;
4529
4530 Label L_fallthrough;
4531 int label_nulls = 0;
4532 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4533 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4534 assert(label_nulls <= 1, "at most one null in the batch");
4535
4536 // Load the array length.
4537 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4538 // And adjust the array base to point to the data.
4539 // NB! Effectively increments current slot index by 1.
4540 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
4541 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4542
4543 // Linear probe
4544 Label L_huge;
4545
4546 // The bitmap is full to bursting.
4547 // Implicit invariant: BITMAP_FULL implies (length > 0)
4548 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
4549 jcc(Assembler::greater, L_huge);
4550
4551 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
4552 // current slot (at secondary_supers[r_array_index]) has not yet
4553 // been inspected, and r_array_index may be out of bounds if we
4554 // wrapped around the end of the array.
4555
4556 { // This is conventional linear probing, but instead of terminating
4557 // when a null entry is found in the table, we maintain a bitmap
4558 // in which a 0 indicates missing entries.
4559 // The check above guarantees there are 0s in the bitmap, so the loop
4560 // eventually terminates.
4561
4562 xorl(temp2, temp2); // = 0;
4563
4564 Label L_again;
4565 bind(L_again);
4566
4567 // Check for array wraparound.
4568 cmpl(r_array_index, r_array_length);
4569 cmovl(Assembler::greaterEqual, r_array_index, temp2);
4570
4571 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4572 jcc(Assembler::equal, *L_success);
4573
4574 // If the next bit in bitmap is zero, we're done.
4575 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
4576 jcc(Assembler::carryClear, *L_failure);
4577
4578 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
4579 addl(r_array_index, 1);
4580
4581 jmp(L_again);
4582 }
4583
4584 { // Degenerate case: more than 64 secondary supers.
4585 // FIXME: We could do something smarter here, maybe a vectorized
4586 // comparison or a binary search, but is that worth any added
4587 // complexity?
4588 bind(L_huge);
4589 xorl(r_array_index, r_array_index); // = 0
4590 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
4591 L_success,
4592 (&L_fallthrough != L_failure ? L_failure : nullptr));
4593
4594 bind(L_fallthrough);
4595 }
4596 }
4597
4598 struct VerifyHelperArguments {
4599 Klass* _super;
4600 Klass* _sub;
4601 intptr_t _linear_result;
4602 intptr_t _table_result;
4603 };
4604
4605 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
4606 Klass::on_secondary_supers_verification_failure(args->_super,
4607 args->_sub,
4608 args->_linear_result,
4609 args->_table_result,
4610 msg);
4611 }
4612
4613 // Make sure that the hashed lookup and a linear scan agree.
4614 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
4615 Register r_super_klass,
4616 Register result,
4617 Register temp1,
4618 Register temp2,
4619 Register temp3) {
4620 const Register
4621 r_array_index = temp1,
4622 r_array_length = temp2,
4623 r_array_base = temp3,
4624 r_bitmap = noreg;
4625
4626 BLOCK_COMMENT("verify_secondary_supers_table {");
4627
4628 Label L_success, L_failure, L_check, L_done;
4629
4630 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4631 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4632 // And adjust the array base to point to the data.
4633 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4634
4635 testl(r_array_length, r_array_length); // array_length == 0?
4636 jcc(Assembler::zero, L_failure);
4637
4638 movl(r_array_index, 0);
4639 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
4640 // fall through to L_failure
4641
4642 const Register linear_result = r_array_index; // reuse temp1
4643
4644 bind(L_failure); // not present
4645 movl(linear_result, 1);
4646 jmp(L_check);
4647
4648 bind(L_success); // present
4649 movl(linear_result, 0);
4650
4651 bind(L_check);
4652 cmpl(linear_result, result);
4653 jcc(Assembler::equal, L_done);
4654
4655 { // To avoid calling convention issues, build a record on the stack
4656 // and pass the pointer to that instead.
4657 push(result);
4658 push(linear_result);
4659 push(r_sub_klass);
4660 push(r_super_klass);
4661 movptr(c_rarg1, rsp);
4662 movptr(c_rarg0, (uintptr_t) "mismatch");
4663 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
4664 should_not_reach_here();
4665 }
4666 bind(L_done);
4667
4668 BLOCK_COMMENT("} verify_secondary_supers_table");
4669 }
4670
4671 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
4672
4673 void MacroAssembler::clinit_barrier(Register klass, Label* L_fast_path, Label* L_slow_path) {
4674 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
4675
4676 Label L_fallthrough;
4677 if (L_fast_path == nullptr) {
4678 L_fast_path = &L_fallthrough;
4679 } else if (L_slow_path == nullptr) {
4680 L_slow_path = &L_fallthrough;
4681 }
4682
4683 // Fast path check: class is fully initialized.
4684 // init_state needs acquire, but x86 is TSO, and so we are already good.
4685 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4686 jcc(Assembler::equal, *L_fast_path);
4687
4688 // Fast path check: current thread is initializer thread
4689 cmpptr(r15_thread, Address(klass, InstanceKlass::init_thread_offset()));
4690 if (L_slow_path == &L_fallthrough) {
4691 jcc(Assembler::equal, *L_fast_path);
4692 bind(*L_slow_path);
4693 } else if (L_fast_path == &L_fallthrough) {
4694 jcc(Assembler::notEqual, *L_slow_path);
4695 bind(*L_fast_path);
4696 } else {
4697 Unimplemented();
4698 }
4699 }
4700
4701 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4702 if (VM_Version::supports_cmov()) {
4703 cmovl(cc, dst, src);
4704 } else {
4705 Label L;
4706 jccb(negate_condition(cc), L);
4707 movl(dst, src);
4708 bind(L);
4709 }
4710 }
4711
4712 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4713 if (VM_Version::supports_cmov()) {
4714 cmovl(cc, dst, src);
4715 } else {
4716 Label L;
4717 jccb(negate_condition(cc), L);
4718 movl(dst, src);
4719 bind(L);
4720 }
4721 }
4722
4723 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
4724 if (!VerifyOops) return;
4725
4726 BLOCK_COMMENT("verify_oop {");
4727 push(rscratch1);
4728 push(rax); // save rax
4729 push(reg); // pass register argument
4730
4731 // Pass register number to verify_oop_subroutine
4732 const char* b = nullptr;
4733 {
4734 ResourceMark rm;
4735 stringStream ss;
4736 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
4737 b = code_string(ss.as_string());
4738 }
4739 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
4740 pushptr(buffer.addr(), rscratch1);
4741
4742 // call indirectly to solve generation ordering problem
4743 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4744 call(rax);
4745 // Caller pops the arguments (oop, message) and restores rax, r10
4746 BLOCK_COMMENT("} verify_oop");
4747 }
4748
4749 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
4750 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
4751 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
4752 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
4753 vpternlogd(dst, 0xFF, dst, dst, vector_len);
4754 } else if (VM_Version::supports_avx()) {
4755 vpcmpeqd(dst, dst, dst, vector_len);
4756 } else {
4757 pcmpeqd(dst, dst);
4758 }
4759 }
4760
4761 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4762 int extra_slot_offset) {
4763 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4764 int stackElementSize = Interpreter::stackElementSize;
4765 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4766 #ifdef ASSERT
4767 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4768 assert(offset1 - offset == stackElementSize, "correct arithmetic");
4769 #endif
4770 Register scale_reg = noreg;
4771 Address::ScaleFactor scale_factor = Address::no_scale;
4772 if (arg_slot.is_constant()) {
4773 offset += arg_slot.as_constant() * stackElementSize;
4774 } else {
4775 scale_reg = arg_slot.as_register();
4776 scale_factor = Address::times(stackElementSize);
4777 }
4778 offset += wordSize; // return PC is on stack
4779 return Address(rsp, scale_reg, scale_factor, offset);
4780 }
4781
4782 // Handle the receiver type profile update given the "recv" klass.
4783 //
4784 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
4785 // If there are no matching or claimable receiver entries in RD, updates
4786 // the polymorphic counter.
4787 //
4788 // This code expected to run by either the interpreter or JIT-ed code, without
4789 // extra synchronization. For safety, receiver cells are claimed atomically, which
4790 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
4791 // counter updates are not atomic.
4792 //
4793 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
4794 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
4795 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
4796 int poly_count_offset = in_bytes(CounterData::count_offset());
4797 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
4798 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
4799
4800 // Adjust for MDP offsets. Slots are pointer-sized, so is the global offset.
4801 assert(is_aligned(mdp_offset, BytesPerWord), "sanity");
4802 base_receiver_offset += mdp_offset;
4803 end_receiver_offset += mdp_offset;
4804 poly_count_offset += mdp_offset;
4805
4806 // Scale down to optimize encoding. Slots are pointer-sized.
4807 assert(is_aligned(base_receiver_offset, BytesPerWord), "sanity");
4808 assert(is_aligned(end_receiver_offset, BytesPerWord), "sanity");
4809 assert(is_aligned(poly_count_offset, BytesPerWord), "sanity");
4810 assert(is_aligned(receiver_step, BytesPerWord), "sanity");
4811 assert(is_aligned(receiver_to_count_step, BytesPerWord), "sanity");
4812 base_receiver_offset >>= LogBytesPerWord;
4813 end_receiver_offset >>= LogBytesPerWord;
4814 poly_count_offset >>= LogBytesPerWord;
4815 receiver_step >>= LogBytesPerWord;
4816 receiver_to_count_step >>= LogBytesPerWord;
4817
4818 #ifdef ASSERT
4819 // We are about to walk the MDO slots without asking for offsets.
4820 // Check that our math hits all the right spots.
4821 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
4822 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
4823 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
4824 int offset = base_receiver_offset + receiver_step*c;
4825 int count_offset = offset + receiver_to_count_step;
4826 assert((offset << LogBytesPerWord) == real_recv_offset, "receiver slot math");
4827 assert((count_offset << LogBytesPerWord) == real_count_offset, "receiver count math");
4828 }
4829 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
4830 assert(poly_count_offset << LogBytesPerWord == real_poly_count_offset, "poly counter math");
4831 #endif
4832
4833 // Corner case: no profile table. Increment poly counter and exit.
4834 if (ReceiverTypeData::row_limit() == 0) {
4835 addptr(Address(mdp, poly_count_offset, Address::times_ptr), DataLayout::counter_increment);
4836 return;
4837 }
4838
4839 Register offset = rscratch1;
4840
4841 Label L_loop_search_receiver, L_loop_search_empty;
4842 Label L_restart, L_found_recv, L_found_empty, L_polymorphic, L_count_update;
4843
4844 // The code here recognizes three major cases:
4845 // A. Fastest: receiver found in the table
4846 // B. Fast: no receiver in the table, and the table is full
4847 // C. Slow: no receiver in the table, free slots in the table
4848 //
4849 // The case A performance is most important, as perfectly-behaved code would end up
4850 // there, especially with larger TypeProfileWidth. The case B performance is
4851 // important as well, this is where bulk of code would land for normally megamorphic
4852 // cases. The case C performance is not essential, its job is to deal with installation
4853 // races, we optimize for code density instead. Case C needs to make sure that receiver
4854 // rows are only claimed once. This makes sure we never overwrite a row for another
4855 // receiver and never duplicate the receivers in the list, making profile type-accurate.
4856 //
4857 // It is very tempting to handle these cases in a single loop, and claim the first slot
4858 // without checking the rest of the table. But, profiling code should tolerate free slots
4859 // in the table, as class unloading can clear them. After such cleanup, the receiver
4860 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
4861 // to complete, before trying to install new slots. Splitting the code in several tight
4862 // loops also helpfully optimizes for cases A and B.
4863 //
4864 // This code is effectively:
4865 //
4866 // restart:
4867 // // Fastest: receiver is already installed
4868 // for (i = 0; i < receiver_count(); i++) {
4869 // if (receiver(i) == recv) goto found_recv(i);
4870 // }
4871 //
4872 // // Fast: no receiver, but profile is full
4873 // for (i = 0; i < receiver_count(); i++) {
4874 // if (receiver(i) == null) goto found_null(i);
4875 // }
4876 // goto polymorphic
4877 //
4878 // // Slow: try to install receiver
4879 // found_null(i):
4880 // CAS(&receiver(i), null, recv);
4881 // goto restart
4882 //
4883 // polymorphic:
4884 // count++;
4885 // return
4886 //
4887 // found_recv(i):
4888 // *receiver_count(i)++
4889 //
4890
4891 bind(L_restart);
4892
4893 // Fastest: receiver is already installed
4894 movptr(offset, base_receiver_offset);
4895 bind(L_loop_search_receiver);
4896 cmpptr(recv, Address(mdp, offset, Address::times_ptr));
4897 jccb(Assembler::equal, L_found_recv);
4898 addptr(offset, receiver_step);
4899 cmpptr(offset, end_receiver_offset);
4900 jccb(Assembler::notEqual, L_loop_search_receiver);
4901
4902 // Fast: no receiver, but profile is full
4903 movptr(offset, base_receiver_offset);
4904 bind(L_loop_search_empty);
4905 cmpptr(Address(mdp, offset, Address::times_ptr), NULL_WORD);
4906 jccb(Assembler::equal, L_found_empty);
4907 addptr(offset, receiver_step);
4908 cmpptr(offset, end_receiver_offset);
4909 jccb(Assembler::notEqual, L_loop_search_empty);
4910 jmpb(L_polymorphic);
4911
4912 // Slow: try to install receiver
4913 bind(L_found_empty);
4914
4915 // Atomically swing receiver slot: null -> recv.
4916 //
4917 // The update code uses CAS, which wants RAX register specifically, *and* it needs
4918 // other important registers untouched, as they form the address. Therefore, we need
4919 // to shift any important registers from RAX into some other spare register. If we
4920 // have a spare register, we are forced to save it on stack here.
4921
4922 Register spare_reg = noreg;
4923 Register shifted_mdp = mdp;
4924 Register shifted_recv = recv;
4925 if (recv == rax || mdp == rax) {
4926 spare_reg = (recv != rbx && mdp != rbx) ? rbx :
4927 (recv != rcx && mdp != rcx) ? rcx :
4928 rdx;
4929 assert_different_registers(mdp, recv, offset, spare_reg);
4930
4931 push(spare_reg);
4932 if (recv == rax) {
4933 movptr(spare_reg, recv);
4934 shifted_recv = spare_reg;
4935 } else {
4936 assert(mdp == rax, "Remaining case");
4937 movptr(spare_reg, mdp);
4938 shifted_mdp = spare_reg;
4939 }
4940 } else {
4941 push(rax);
4942 }
4943
4944 // None of the important registers are in RAX after this shuffle.
4945 assert_different_registers(rax, shifted_mdp, shifted_recv, offset);
4946
4947 xorptr(rax, rax);
4948 cmpxchgptr(shifted_recv, Address(shifted_mdp, offset, Address::times_ptr));
4949
4950 // Unshift registers.
4951 if (recv == rax || mdp == rax) {
4952 movptr(rax, spare_reg);
4953 pop(spare_reg);
4954 } else {
4955 pop(rax);
4956 }
4957
4958 // CAS success means the slot now has the receiver we want. CAS failure means
4959 // something had claimed the slot concurrently: it can be the same receiver we want,
4960 // or something else. Since this is a slow path, we can optimize for code density,
4961 // and just restart the search from the beginning.
4962 jmpb(L_restart);
4963
4964 // Counter updates:
4965
4966 // Increment polymorphic counter instead of receiver slot.
4967 bind(L_polymorphic);
4968 movptr(offset, poly_count_offset);
4969 jmpb(L_count_update);
4970
4971 // Found a receiver, convert its slot offset to corresponding count offset.
4972 bind(L_found_recv);
4973 addptr(offset, receiver_to_count_step);
4974
4975 bind(L_count_update);
4976 addptr(Address(mdp, offset, Address::times_ptr), DataLayout::counter_increment);
4977 }
4978
4979 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
4980 if (!VerifyOops) return;
4981
4982 push(rscratch1);
4983 push(rax); // save rax,
4984 // addr may contain rsp so we will have to adjust it based on the push
4985 // we just did (and on 64 bit we do two pushes)
4986 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4987 // stores rax into addr which is backwards of what was intended.
4988 if (addr.uses(rsp)) {
4989 lea(rax, addr);
4990 pushptr(Address(rax, 2 * BytesPerWord));
4991 } else {
4992 pushptr(addr);
4993 }
4994
4995 // Pass register number to verify_oop_subroutine
4996 const char* b = nullptr;
4997 {
4998 ResourceMark rm;
4999 stringStream ss;
5000 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5001 b = code_string(ss.as_string());
5002 }
5003 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5004 pushptr(buffer.addr(), rscratch1);
5005
5006 // call indirectly to solve generation ordering problem
5007 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5008 call(rax);
5009 // Caller pops the arguments (addr, message) and restores rax, r10.
5010 }
5011
5012 void MacroAssembler::verify_tlab() {
5013 #ifdef ASSERT
5014 if (UseTLAB && VerifyOops) {
5015 Label next, ok;
5016 Register t1 = rsi;
5017
5018 push(t1);
5019
5020 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5021 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_start_offset())));
5022 jcc(Assembler::aboveEqual, next);
5023 STOP("assert(top >= start)");
5024 should_not_reach_here();
5025
5026 bind(next);
5027 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_end_offset())));
5028 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5029 jcc(Assembler::aboveEqual, ok);
5030 STOP("assert(top <= end)");
5031 should_not_reach_here();
5032
5033 bind(ok);
5034 pop(t1);
5035 }
5036 #endif
5037 }
5038
5039 class ControlWord {
5040 public:
5041 int32_t _value;
5042
5043 int rounding_control() const { return (_value >> 10) & 3 ; }
5044 int precision_control() const { return (_value >> 8) & 3 ; }
5045 bool precision() const { return ((_value >> 5) & 1) != 0; }
5046 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5047 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5048 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5049 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5050 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5051
5052 void print() const {
5053 // rounding control
5054 const char* rc;
5055 switch (rounding_control()) {
5056 case 0: rc = "round near"; break;
5057 case 1: rc = "round down"; break;
5058 case 2: rc = "round up "; break;
5059 case 3: rc = "chop "; break;
5060 default:
5061 rc = nullptr; // silence compiler warnings
5062 fatal("Unknown rounding control: %d", rounding_control());
5063 };
5064 // precision control
5065 const char* pc;
5066 switch (precision_control()) {
5067 case 0: pc = "24 bits "; break;
5068 case 1: pc = "reserved"; break;
5069 case 2: pc = "53 bits "; break;
5070 case 3: pc = "64 bits "; break;
5071 default:
5072 pc = nullptr; // silence compiler warnings
5073 fatal("Unknown precision control: %d", precision_control());
5074 };
5075 // flags
5076 char f[9];
5077 f[0] = ' ';
5078 f[1] = ' ';
5079 f[2] = (precision ()) ? 'P' : 'p';
5080 f[3] = (underflow ()) ? 'U' : 'u';
5081 f[4] = (overflow ()) ? 'O' : 'o';
5082 f[5] = (zero_divide ()) ? 'Z' : 'z';
5083 f[6] = (denormalized()) ? 'D' : 'd';
5084 f[7] = (invalid ()) ? 'I' : 'i';
5085 f[8] = '\x0';
5086 // output
5087 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5088 }
5089
5090 };
5091
5092 class StatusWord {
5093 public:
5094 int32_t _value;
5095
5096 bool busy() const { return ((_value >> 15) & 1) != 0; }
5097 bool C3() const { return ((_value >> 14) & 1) != 0; }
5098 bool C2() const { return ((_value >> 10) & 1) != 0; }
5099 bool C1() const { return ((_value >> 9) & 1) != 0; }
5100 bool C0() const { return ((_value >> 8) & 1) != 0; }
5101 int top() const { return (_value >> 11) & 7 ; }
5102 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5103 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5104 bool precision() const { return ((_value >> 5) & 1) != 0; }
5105 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5106 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5107 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5108 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5109 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5110
5111 void print() const {
5112 // condition codes
5113 char c[5];
5114 c[0] = (C3()) ? '3' : '-';
5115 c[1] = (C2()) ? '2' : '-';
5116 c[2] = (C1()) ? '1' : '-';
5117 c[3] = (C0()) ? '0' : '-';
5118 c[4] = '\x0';
5119 // flags
5120 char f[9];
5121 f[0] = (error_status()) ? 'E' : '-';
5122 f[1] = (stack_fault ()) ? 'S' : '-';
5123 f[2] = (precision ()) ? 'P' : '-';
5124 f[3] = (underflow ()) ? 'U' : '-';
5125 f[4] = (overflow ()) ? 'O' : '-';
5126 f[5] = (zero_divide ()) ? 'Z' : '-';
5127 f[6] = (denormalized()) ? 'D' : '-';
5128 f[7] = (invalid ()) ? 'I' : '-';
5129 f[8] = '\x0';
5130 // output
5131 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5132 }
5133
5134 };
5135
5136 class TagWord {
5137 public:
5138 int32_t _value;
5139
5140 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5141
5142 void print() const {
5143 printf("%04x", _value & 0xFFFF);
5144 }
5145
5146 };
5147
5148 class FPU_Register {
5149 public:
5150 int32_t _m0;
5151 int32_t _m1;
5152 int16_t _ex;
5153
5154 bool is_indefinite() const {
5155 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5156 }
5157
5158 void print() const {
5159 char sign = (_ex < 0) ? '-' : '+';
5160 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5161 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5162 };
5163
5164 };
5165
5166 class FPU_State {
5167 public:
5168 enum {
5169 register_size = 10,
5170 number_of_registers = 8,
5171 register_mask = 7
5172 };
5173
5174 ControlWord _control_word;
5175 StatusWord _status_word;
5176 TagWord _tag_word;
5177 int32_t _error_offset;
5178 int32_t _error_selector;
5179 int32_t _data_offset;
5180 int32_t _data_selector;
5181 int8_t _register[register_size * number_of_registers];
5182
5183 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5184 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5185
5186 const char* tag_as_string(int tag) const {
5187 switch (tag) {
5188 case 0: return "valid";
5189 case 1: return "zero";
5190 case 2: return "special";
5191 case 3: return "empty";
5192 }
5193 ShouldNotReachHere();
5194 return nullptr;
5195 }
5196
5197 void print() const {
5198 // print computation registers
5199 { int t = _status_word.top();
5200 for (int i = 0; i < number_of_registers; i++) {
5201 int j = (i - t) & register_mask;
5202 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5203 st(j)->print();
5204 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5205 }
5206 }
5207 printf("\n");
5208 // print control registers
5209 printf("ctrl = "); _control_word.print(); printf("\n");
5210 printf("stat = "); _status_word .print(); printf("\n");
5211 printf("tags = "); _tag_word .print(); printf("\n");
5212 }
5213
5214 };
5215
5216 class Flag_Register {
5217 public:
5218 int32_t _value;
5219
5220 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5221 bool direction() const { return ((_value >> 10) & 1) != 0; }
5222 bool sign() const { return ((_value >> 7) & 1) != 0; }
5223 bool zero() const { return ((_value >> 6) & 1) != 0; }
5224 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5225 bool parity() const { return ((_value >> 2) & 1) != 0; }
5226 bool carry() const { return ((_value >> 0) & 1) != 0; }
5227
5228 void print() const {
5229 // flags
5230 char f[8];
5231 f[0] = (overflow ()) ? 'O' : '-';
5232 f[1] = (direction ()) ? 'D' : '-';
5233 f[2] = (sign ()) ? 'S' : '-';
5234 f[3] = (zero ()) ? 'Z' : '-';
5235 f[4] = (auxiliary_carry()) ? 'A' : '-';
5236 f[5] = (parity ()) ? 'P' : '-';
5237 f[6] = (carry ()) ? 'C' : '-';
5238 f[7] = '\x0';
5239 // output
5240 printf("%08x flags = %s", _value, f);
5241 }
5242
5243 };
5244
5245 class IU_Register {
5246 public:
5247 int32_t _value;
5248
5249 void print() const {
5250 printf("%08x %11d", _value, _value);
5251 }
5252
5253 };
5254
5255 class IU_State {
5256 public:
5257 Flag_Register _eflags;
5258 IU_Register _rdi;
5259 IU_Register _rsi;
5260 IU_Register _rbp;
5261 IU_Register _rsp;
5262 IU_Register _rbx;
5263 IU_Register _rdx;
5264 IU_Register _rcx;
5265 IU_Register _rax;
5266
5267 void print() const {
5268 // computation registers
5269 printf("rax, = "); _rax.print(); printf("\n");
5270 printf("rbx, = "); _rbx.print(); printf("\n");
5271 printf("rcx = "); _rcx.print(); printf("\n");
5272 printf("rdx = "); _rdx.print(); printf("\n");
5273 printf("rdi = "); _rdi.print(); printf("\n");
5274 printf("rsi = "); _rsi.print(); printf("\n");
5275 printf("rbp, = "); _rbp.print(); printf("\n");
5276 printf("rsp = "); _rsp.print(); printf("\n");
5277 printf("\n");
5278 // control registers
5279 printf("flgs = "); _eflags.print(); printf("\n");
5280 }
5281 };
5282
5283
5284 class CPU_State {
5285 public:
5286 FPU_State _fpu_state;
5287 IU_State _iu_state;
5288
5289 void print() const {
5290 printf("--------------------------------------------------\n");
5291 _iu_state .print();
5292 printf("\n");
5293 _fpu_state.print();
5294 printf("--------------------------------------------------\n");
5295 }
5296
5297 };
5298
5299
5300 static void _print_CPU_state(CPU_State* state) {
5301 state->print();
5302 };
5303
5304
5305 void MacroAssembler::print_CPU_state() {
5306 push_CPU_state();
5307 push(rsp); // pass CPU state
5308 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5309 addptr(rsp, wordSize); // discard argument
5310 pop_CPU_state();
5311 }
5312
5313 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5314 // Either restore the MXCSR register after returning from the JNI Call
5315 // or verify that it wasn't changed (with -Xcheck:jni flag).
5316 if (VM_Version::supports_sse()) {
5317 if (RestoreMXCSROnJNICalls) {
5318 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5319 } else if (CheckJNICalls) {
5320 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5321 }
5322 }
5323 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5324 vzeroupper();
5325 }
5326
5327 // ((OopHandle)result).resolve();
5328 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5329 assert_different_registers(result, tmp);
5330
5331 // Only 64 bit platforms support GCs that require a tmp register
5332 // Only IN_HEAP loads require a thread_tmp register
5333 // OopHandle::resolve is an indirection like jobject.
5334 access_load_at(T_OBJECT, IN_NATIVE,
5335 result, Address(result, 0), tmp);
5336 }
5337
5338 // ((WeakHandle)result).resolve();
5339 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5340 assert_different_registers(rresult, rtmp);
5341 Label resolved;
5342
5343 // A null weak handle resolves to null.
5344 cmpptr(rresult, 0);
5345 jcc(Assembler::equal, resolved);
5346
5347 // Only 64 bit platforms support GCs that require a tmp register
5348 // Only IN_HEAP loads require a thread_tmp register
5349 // WeakHandle::resolve is an indirection like jweak.
5350 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5351 rresult, Address(rresult, 0), rtmp);
5352 bind(resolved);
5353 }
5354
5355 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5356 // get mirror
5357 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5358 load_method_holder(mirror, method);
5359 movptr(mirror, Address(mirror, mirror_offset));
5360 resolve_oop_handle(mirror, tmp);
5361 }
5362
5363 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5364 load_method_holder(rresult, rmethod);
5365 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5366 }
5367
5368 void MacroAssembler::load_method_holder(Register holder, Register method) {
5369 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5370 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5371 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5372 }
5373
5374 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5375 assert(UseCompactObjectHeaders, "expect compact object headers");
5376 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5377 shrq(dst, markWord::klass_shift);
5378 }
5379
5380 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5381 assert_different_registers(src, tmp);
5382 assert_different_registers(dst, tmp);
5383
5384 if (UseCompactObjectHeaders) {
5385 load_narrow_klass_compact(dst, src);
5386 decode_klass_not_null(dst, tmp);
5387 } else if (UseCompressedClassPointers) {
5388 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5389 decode_klass_not_null(dst, tmp);
5390 } else {
5391 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5392 }
5393 }
5394
5395 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5396 assert(!UseCompactObjectHeaders, "not with compact headers");
5397 assert_different_registers(src, tmp);
5398 assert_different_registers(dst, tmp);
5399 if (UseCompressedClassPointers) {
5400 encode_klass_not_null(src, tmp);
5401 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5402 } else {
5403 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5404 }
5405 }
5406
5407 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
5408 if (UseCompactObjectHeaders) {
5409 assert(tmp != noreg, "need tmp");
5410 assert_different_registers(klass, obj, tmp);
5411 load_narrow_klass_compact(tmp, obj);
5412 cmpl(klass, tmp);
5413 } else if (UseCompressedClassPointers) {
5414 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5415 } else {
5416 cmpptr(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5417 }
5418 }
5419
5420 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5421 if (UseCompactObjectHeaders) {
5422 assert(tmp2 != noreg, "need tmp2");
5423 assert_different_registers(obj1, obj2, tmp1, tmp2);
5424 load_narrow_klass_compact(tmp1, obj1);
5425 load_narrow_klass_compact(tmp2, obj2);
5426 cmpl(tmp1, tmp2);
5427 } else if (UseCompressedClassPointers) {
5428 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5429 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5430 } else {
5431 movptr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5432 cmpptr(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5433 }
5434 }
5435
5436 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5437 Register tmp1) {
5438 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5439 decorators = AccessInternal::decorator_fixup(decorators, type);
5440 bool as_raw = (decorators & AS_RAW) != 0;
5441 if (as_raw) {
5442 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1);
5443 } else {
5444 bs->load_at(this, decorators, type, dst, src, tmp1);
5445 }
5446 }
5447
5448 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5449 Register tmp1, Register tmp2, Register tmp3) {
5450 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5451 decorators = AccessInternal::decorator_fixup(decorators, type);
5452 bool as_raw = (decorators & AS_RAW) != 0;
5453 if (as_raw) {
5454 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5455 } else {
5456 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5457 }
5458 }
5459
5460 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5461 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1);
5462 }
5463
5464 // Doesn't do verification, generates fixed size code
5465 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5466 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1);
5467 }
5468
5469 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5470 Register tmp2, Register tmp3, DecoratorSet decorators) {
5471 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5472 }
5473
5474 // Used for storing nulls.
5475 void MacroAssembler::store_heap_oop_null(Address dst) {
5476 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5477 }
5478
5479 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5480 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
5481 if (UseCompressedClassPointers) {
5482 // Store to klass gap in destination
5483 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5484 }
5485 }
5486
5487 #ifdef ASSERT
5488 void MacroAssembler::verify_heapbase(const char* msg) {
5489 assert (UseCompressedOops, "should be compressed");
5490 assert (Universe::heap() != nullptr, "java heap should be initialized");
5491 if (CheckCompressedOops) {
5492 Label ok;
5493 ExternalAddress src2(CompressedOops::base_addr());
5494 const bool is_src2_reachable = reachable(src2);
5495 if (!is_src2_reachable) {
5496 push(rscratch1); // cmpptr trashes rscratch1
5497 }
5498 cmpptr(r12_heapbase, src2, rscratch1);
5499 jcc(Assembler::equal, ok);
5500 STOP(msg);
5501 bind(ok);
5502 if (!is_src2_reachable) {
5503 pop(rscratch1);
5504 }
5505 }
5506 }
5507 #endif
5508
5509 // Algorithm must match oop.inline.hpp encode_heap_oop.
5510 void MacroAssembler::encode_heap_oop(Register r) {
5511 #ifdef ASSERT
5512 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5513 #endif
5514 verify_oop_msg(r, "broken oop in encode_heap_oop");
5515 if (CompressedOops::base() == nullptr) {
5516 if (CompressedOops::shift() != 0) {
5517 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5518 shrq(r, LogMinObjAlignmentInBytes);
5519 }
5520 return;
5521 }
5522 testq(r, r);
5523 cmovq(Assembler::equal, r, r12_heapbase);
5524 subq(r, r12_heapbase);
5525 shrq(r, LogMinObjAlignmentInBytes);
5526 }
5527
5528 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5529 #ifdef ASSERT
5530 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5531 if (CheckCompressedOops) {
5532 Label ok;
5533 testq(r, r);
5534 jcc(Assembler::notEqual, ok);
5535 STOP("null oop passed to encode_heap_oop_not_null");
5536 bind(ok);
5537 }
5538 #endif
5539 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5540 if (CompressedOops::base() != nullptr) {
5541 subq(r, r12_heapbase);
5542 }
5543 if (CompressedOops::shift() != 0) {
5544 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5545 shrq(r, LogMinObjAlignmentInBytes);
5546 }
5547 }
5548
5549 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5550 #ifdef ASSERT
5551 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5552 if (CheckCompressedOops) {
5553 Label ok;
5554 testq(src, src);
5555 jcc(Assembler::notEqual, ok);
5556 STOP("null oop passed to encode_heap_oop_not_null2");
5557 bind(ok);
5558 }
5559 #endif
5560 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5561 if (dst != src) {
5562 movq(dst, src);
5563 }
5564 if (CompressedOops::base() != nullptr) {
5565 subq(dst, r12_heapbase);
5566 }
5567 if (CompressedOops::shift() != 0) {
5568 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5569 shrq(dst, LogMinObjAlignmentInBytes);
5570 }
5571 }
5572
5573 void MacroAssembler::decode_heap_oop(Register r) {
5574 #ifdef ASSERT
5575 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5576 #endif
5577 if (CompressedOops::base() == nullptr) {
5578 if (CompressedOops::shift() != 0) {
5579 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5580 shlq(r, LogMinObjAlignmentInBytes);
5581 }
5582 } else {
5583 Label done;
5584 shlq(r, LogMinObjAlignmentInBytes);
5585 jccb(Assembler::equal, done);
5586 addq(r, r12_heapbase);
5587 bind(done);
5588 }
5589 verify_oop_msg(r, "broken oop in decode_heap_oop");
5590 }
5591
5592 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5593 // Note: it will change flags
5594 assert (UseCompressedOops, "should only be used for compressed headers");
5595 assert (Universe::heap() != nullptr, "java heap should be initialized");
5596 // Cannot assert, unverified entry point counts instructions (see .ad file)
5597 // vtableStubs also counts instructions in pd_code_size_limit.
5598 // Also do not verify_oop as this is called by verify_oop.
5599 if (CompressedOops::shift() != 0) {
5600 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5601 shlq(r, LogMinObjAlignmentInBytes);
5602 if (CompressedOops::base() != nullptr) {
5603 addq(r, r12_heapbase);
5604 }
5605 } else {
5606 assert (CompressedOops::base() == nullptr, "sanity");
5607 }
5608 }
5609
5610 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5611 // Note: it will change flags
5612 assert (UseCompressedOops, "should only be used for compressed headers");
5613 assert (Universe::heap() != nullptr, "java heap should be initialized");
5614 // Cannot assert, unverified entry point counts instructions (see .ad file)
5615 // vtableStubs also counts instructions in pd_code_size_limit.
5616 // Also do not verify_oop as this is called by verify_oop.
5617 if (CompressedOops::shift() != 0) {
5618 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5619 if (LogMinObjAlignmentInBytes == Address::times_8) {
5620 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5621 } else {
5622 if (dst != src) {
5623 movq(dst, src);
5624 }
5625 shlq(dst, LogMinObjAlignmentInBytes);
5626 if (CompressedOops::base() != nullptr) {
5627 addq(dst, r12_heapbase);
5628 }
5629 }
5630 } else {
5631 assert (CompressedOops::base() == nullptr, "sanity");
5632 if (dst != src) {
5633 movq(dst, src);
5634 }
5635 }
5636 }
5637
5638 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
5639 BLOCK_COMMENT("encode_klass_not_null {");
5640 assert_different_registers(r, tmp);
5641 if (CompressedKlassPointers::base() != nullptr) {
5642 if (AOTCodeCache::is_on_for_dump()) {
5643 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5644 } else {
5645 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5646 }
5647 subq(r, tmp);
5648 }
5649 if (CompressedKlassPointers::shift() != 0) {
5650 shrq(r, CompressedKlassPointers::shift());
5651 }
5652 BLOCK_COMMENT("} encode_klass_not_null");
5653 }
5654
5655 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
5656 BLOCK_COMMENT("encode_and_move_klass_not_null {");
5657 assert_different_registers(src, dst);
5658 if (CompressedKlassPointers::base() != nullptr) {
5659 if (AOTCodeCache::is_on_for_dump()) {
5660 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5661 negq(dst);
5662 } else {
5663 movptr(dst, -(intptr_t)CompressedKlassPointers::base());
5664 }
5665 addq(dst, src);
5666 } else {
5667 movptr(dst, src);
5668 }
5669 if (CompressedKlassPointers::shift() != 0) {
5670 shrq(dst, CompressedKlassPointers::shift());
5671 }
5672 BLOCK_COMMENT("} encode_and_move_klass_not_null");
5673 }
5674
5675 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
5676 BLOCK_COMMENT("decode_klass_not_null {");
5677 assert_different_registers(r, tmp);
5678 // Note: it will change flags
5679 assert(UseCompressedClassPointers, "should only be used for compressed headers");
5680 // Cannot assert, unverified entry point counts instructions (see .ad file)
5681 // vtableStubs also counts instructions in pd_code_size_limit.
5682 // Also do not verify_oop as this is called by verify_oop.
5683 if (CompressedKlassPointers::shift() != 0) {
5684 shlq(r, CompressedKlassPointers::shift());
5685 }
5686 if (CompressedKlassPointers::base() != nullptr) {
5687 if (AOTCodeCache::is_on_for_dump()) {
5688 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5689 } else {
5690 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5691 }
5692 addq(r, tmp);
5693 }
5694 BLOCK_COMMENT("} decode_klass_not_null");
5695 }
5696
5697 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
5698 BLOCK_COMMENT("decode_and_move_klass_not_null {");
5699 assert_different_registers(src, dst);
5700 // Note: it will change flags
5701 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5702 // Cannot assert, unverified entry point counts instructions (see .ad file)
5703 // vtableStubs also counts instructions in pd_code_size_limit.
5704 // Also do not verify_oop as this is called by verify_oop.
5705
5706 if (CompressedKlassPointers::base() == nullptr &&
5707 CompressedKlassPointers::shift() == 0) {
5708 // The best case scenario is that there is no base or shift. Then it is already
5709 // a pointer that needs nothing but a register rename.
5710 movptr(dst, src);
5711 } else {
5712 if (CompressedKlassPointers::shift() <= Address::times_8) {
5713 if (CompressedKlassPointers::base() != nullptr) {
5714 if (AOTCodeCache::is_on_for_dump()) {
5715 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5716 } else {
5717 movptr(dst, (intptr_t)CompressedKlassPointers::base());
5718 }
5719 } else {
5720 xorq(dst, dst);
5721 }
5722 if (CompressedKlassPointers::shift() != 0) {
5723 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
5724 leaq(dst, Address(dst, src, Address::times_8, 0));
5725 } else {
5726 addq(dst, src);
5727 }
5728 } else {
5729 if (CompressedKlassPointers::base() != nullptr) {
5730 if (AOTCodeCache::is_on_for_dump()) {
5731 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5732 shrq(dst, CompressedKlassPointers::shift());
5733 } else {
5734 const intptr_t base_right_shifted =
5735 (intptr_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5736 movptr(dst, base_right_shifted);
5737 }
5738 } else {
5739 xorq(dst, dst);
5740 }
5741 addq(dst, src);
5742 shlq(dst, CompressedKlassPointers::shift());
5743 }
5744 }
5745 BLOCK_COMMENT("} decode_and_move_klass_not_null");
5746 }
5747
5748 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5749 assert (UseCompressedOops, "should only be used for compressed headers");
5750 assert (Universe::heap() != nullptr, "java heap should be initialized");
5751 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5752 int oop_index = oop_recorder()->find_index(obj);
5753 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5754 mov_narrow_oop(dst, oop_index, rspec);
5755 }
5756
5757 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5758 assert (UseCompressedOops, "should only be used for compressed headers");
5759 assert (Universe::heap() != nullptr, "java heap should be initialized");
5760 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5761 int oop_index = oop_recorder()->find_index(obj);
5762 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5763 mov_narrow_oop(dst, oop_index, rspec);
5764 }
5765
5766 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5767 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5768 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5769 int klass_index = oop_recorder()->find_index(k);
5770 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5771 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5772 }
5773
5774 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5775 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5776 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5777 int klass_index = oop_recorder()->find_index(k);
5778 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5779 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5780 }
5781
5782 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5783 assert (UseCompressedOops, "should only be used for compressed headers");
5784 assert (Universe::heap() != nullptr, "java heap should be initialized");
5785 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5786 int oop_index = oop_recorder()->find_index(obj);
5787 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5788 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5789 }
5790
5791 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5792 assert (UseCompressedOops, "should only be used for compressed headers");
5793 assert (Universe::heap() != nullptr, "java heap should be initialized");
5794 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5795 int oop_index = oop_recorder()->find_index(obj);
5796 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5797 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5798 }
5799
5800 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5801 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5802 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5803 int klass_index = oop_recorder()->find_index(k);
5804 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5805 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5806 }
5807
5808 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5809 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5810 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5811 int klass_index = oop_recorder()->find_index(k);
5812 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5813 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5814 }
5815
5816 void MacroAssembler::reinit_heapbase() {
5817 if (UseCompressedOops) {
5818 if (Universe::heap() != nullptr) { // GC was initialized
5819 if (CompressedOops::base() == nullptr) {
5820 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5821 } else if (AOTCodeCache::is_on_for_dump()) {
5822 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
5823 } else {
5824 mov64(r12_heapbase, (int64_t)CompressedOops::base());
5825 }
5826 } else {
5827 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
5828 }
5829 }
5830 }
5831
5832 #if COMPILER2_OR_JVMCI
5833
5834 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
5835 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5836 // cnt - number of qwords (8-byte words).
5837 // base - start address, qword aligned.
5838 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5839 bool use64byteVector = (MaxVectorSize == 64) && (CopyAVX3Threshold == 0);
5840 if (use64byteVector) {
5841 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
5842 } else if (MaxVectorSize >= 32) {
5843 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5844 } else {
5845 pxor(xtmp, xtmp);
5846 }
5847 jmp(L_zero_64_bytes);
5848
5849 BIND(L_loop);
5850 if (MaxVectorSize >= 32) {
5851 fill64(base, 0, xtmp, use64byteVector);
5852 } else {
5853 movdqu(Address(base, 0), xtmp);
5854 movdqu(Address(base, 16), xtmp);
5855 movdqu(Address(base, 32), xtmp);
5856 movdqu(Address(base, 48), xtmp);
5857 }
5858 addptr(base, 64);
5859
5860 BIND(L_zero_64_bytes);
5861 subptr(cnt, 8);
5862 jccb(Assembler::greaterEqual, L_loop);
5863
5864 // Copy trailing 64 bytes
5865 if (use64byteVector) {
5866 addptr(cnt, 8);
5867 jccb(Assembler::equal, L_end);
5868 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
5869 jmp(L_end);
5870 } else {
5871 addptr(cnt, 4);
5872 jccb(Assembler::less, L_tail);
5873 if (MaxVectorSize >= 32) {
5874 vmovdqu(Address(base, 0), xtmp);
5875 } else {
5876 movdqu(Address(base, 0), xtmp);
5877 movdqu(Address(base, 16), xtmp);
5878 }
5879 }
5880 addptr(base, 32);
5881 subptr(cnt, 4);
5882
5883 BIND(L_tail);
5884 addptr(cnt, 4);
5885 jccb(Assembler::lessEqual, L_end);
5886 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
5887 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
5888 } else {
5889 decrement(cnt);
5890
5891 BIND(L_sloop);
5892 movq(Address(base, 0), xtmp);
5893 addptr(base, 8);
5894 decrement(cnt);
5895 jccb(Assembler::greaterEqual, L_sloop);
5896 }
5897 BIND(L_end);
5898 }
5899
5900 // Clearing constant sized memory using YMM/ZMM registers.
5901 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5902 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
5903 bool use64byteVector = (MaxVectorSize > 32) && (CopyAVX3Threshold == 0);
5904
5905 int vector64_count = (cnt & (~0x7)) >> 3;
5906 cnt = cnt & 0x7;
5907 const int fill64_per_loop = 4;
5908 const int max_unrolled_fill64 = 8;
5909
5910 // 64 byte initialization loop.
5911 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
5912 int start64 = 0;
5913 if (vector64_count > max_unrolled_fill64) {
5914 Label LOOP;
5915 Register index = rtmp;
5916
5917 start64 = vector64_count - (vector64_count % fill64_per_loop);
5918
5919 movl(index, 0);
5920 BIND(LOOP);
5921 for (int i = 0; i < fill64_per_loop; i++) {
5922 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
5923 }
5924 addl(index, fill64_per_loop * 64);
5925 cmpl(index, start64 * 64);
5926 jccb(Assembler::less, LOOP);
5927 }
5928 for (int i = start64; i < vector64_count; i++) {
5929 fill64(base, i * 64, xtmp, use64byteVector);
5930 }
5931
5932 // Clear remaining 64 byte tail.
5933 int disp = vector64_count * 64;
5934 if (cnt) {
5935 switch (cnt) {
5936 case 1:
5937 movq(Address(base, disp), xtmp);
5938 break;
5939 case 2:
5940 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
5941 break;
5942 case 3:
5943 movl(rtmp, 0x7);
5944 kmovwl(mask, rtmp);
5945 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
5946 break;
5947 case 4:
5948 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
5949 break;
5950 case 5:
5951 if (use64byteVector) {
5952 movl(rtmp, 0x1F);
5953 kmovwl(mask, rtmp);
5954 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
5955 } else {
5956 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
5957 movq(Address(base, disp + 32), xtmp);
5958 }
5959 break;
5960 case 6:
5961 if (use64byteVector) {
5962 movl(rtmp, 0x3F);
5963 kmovwl(mask, rtmp);
5964 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
5965 } else {
5966 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
5967 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
5968 }
5969 break;
5970 case 7:
5971 if (use64byteVector) {
5972 movl(rtmp, 0x7F);
5973 kmovwl(mask, rtmp);
5974 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
5975 } else {
5976 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
5977 movl(rtmp, 0x7);
5978 kmovwl(mask, rtmp);
5979 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
5980 }
5981 break;
5982 default:
5983 fatal("Unexpected length : %d\n",cnt);
5984 break;
5985 }
5986 }
5987 }
5988
5989 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
5990 bool is_large, KRegister mask) {
5991 // cnt - number of qwords (8-byte words).
5992 // base - start address, qword aligned.
5993 // is_large - if optimizers know cnt is larger than InitArrayShortSize
5994 assert(base==rdi, "base register must be edi for rep stos");
5995 assert(tmp==rax, "tmp register must be eax for rep stos");
5996 assert(cnt==rcx, "cnt register must be ecx for rep stos");
5997 assert(InitArrayShortSize % BytesPerLong == 0,
5998 "InitArrayShortSize should be the multiple of BytesPerLong");
5999
6000 Label DONE;
6001 if (!is_large || !UseXMMForObjInit) {
6002 xorptr(tmp, tmp);
6003 }
6004
6005 if (!is_large) {
6006 Label LOOP, LONG;
6007 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6008 jccb(Assembler::greater, LONG);
6009
6010 decrement(cnt);
6011 jccb(Assembler::negative, DONE); // Zero length
6012
6013 // Use individual pointer-sized stores for small counts:
6014 BIND(LOOP);
6015 movptr(Address(base, cnt, Address::times_ptr), tmp);
6016 decrement(cnt);
6017 jccb(Assembler::greaterEqual, LOOP);
6018 jmpb(DONE);
6019
6020 BIND(LONG);
6021 }
6022
6023 // Use longer rep-prefixed ops for non-small counts:
6024 if (UseFastStosb) {
6025 shlptr(cnt, 3); // convert to number of bytes
6026 rep_stosb();
6027 } else if (UseXMMForObjInit) {
6028 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
6029 } else {
6030 rep_stos();
6031 }
6032
6033 BIND(DONE);
6034 }
6035
6036 #endif //COMPILER2_OR_JVMCI
6037
6038
6039 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6040 Register to, Register value, Register count,
6041 Register rtmp, XMMRegister xtmp) {
6042 ShortBranchVerifier sbv(this);
6043 assert_different_registers(to, value, count, rtmp);
6044 Label L_exit;
6045 Label L_fill_2_bytes, L_fill_4_bytes;
6046
6047 #if defined(COMPILER2)
6048 if(MaxVectorSize >=32 &&
6049 VM_Version::supports_avx512vlbw() &&
6050 VM_Version::supports_bmi2()) {
6051 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6052 return;
6053 }
6054 #endif
6055
6056 int shift = -1;
6057 switch (t) {
6058 case T_BYTE:
6059 shift = 2;
6060 break;
6061 case T_SHORT:
6062 shift = 1;
6063 break;
6064 case T_INT:
6065 shift = 0;
6066 break;
6067 default: ShouldNotReachHere();
6068 }
6069
6070 if (t == T_BYTE) {
6071 andl(value, 0xff);
6072 movl(rtmp, value);
6073 shll(rtmp, 8);
6074 orl(value, rtmp);
6075 }
6076 if (t == T_SHORT) {
6077 andl(value, 0xffff);
6078 }
6079 if (t == T_BYTE || t == T_SHORT) {
6080 movl(rtmp, value);
6081 shll(rtmp, 16);
6082 orl(value, rtmp);
6083 }
6084
6085 cmpptr(count, 8 << shift); // Short arrays (< 32 bytes) fill by element
6086 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6087 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6088 Label L_skip_align2;
6089 // align source address at 4 bytes address boundary
6090 if (t == T_BYTE) {
6091 Label L_skip_align1;
6092 // One byte misalignment happens only for byte arrays
6093 testptr(to, 1);
6094 jccb(Assembler::zero, L_skip_align1);
6095 movb(Address(to, 0), value);
6096 increment(to);
6097 decrement(count);
6098 BIND(L_skip_align1);
6099 }
6100 // Two bytes misalignment happens only for byte and short (char) arrays
6101 testptr(to, 2);
6102 jccb(Assembler::zero, L_skip_align2);
6103 movw(Address(to, 0), value);
6104 addptr(to, 2);
6105 subptr(count, 1<<(shift-1));
6106 BIND(L_skip_align2);
6107 }
6108 {
6109 Label L_fill_32_bytes;
6110 if (!UseUnalignedLoadStores) {
6111 // align to 8 bytes, we know we are 4 byte aligned to start
6112 testptr(to, 4);
6113 jccb(Assembler::zero, L_fill_32_bytes);
6114 movl(Address(to, 0), value);
6115 addptr(to, 4);
6116 subptr(count, 1<<shift);
6117 }
6118 BIND(L_fill_32_bytes);
6119 {
6120 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6121 movdl(xtmp, value);
6122 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6123 Label L_check_fill_32_bytes;
6124 if (UseAVX > 2) {
6125 // Fill 64-byte chunks
6126 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6127
6128 // If number of bytes to fill < CopyAVX3Threshold, perform fill using AVX2
6129 cmpptr(count, CopyAVX3Threshold);
6130 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6131
6132 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6133
6134 subptr(count, 16 << shift);
6135 jcc(Assembler::less, L_check_fill_32_bytes);
6136 align(16);
6137
6138 BIND(L_fill_64_bytes_loop_avx3);
6139 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6140 addptr(to, 64);
6141 subptr(count, 16 << shift);
6142 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6143 jmpb(L_check_fill_32_bytes);
6144
6145 BIND(L_check_fill_64_bytes_avx2);
6146 }
6147 // Fill 64-byte chunks
6148 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6149
6150 subptr(count, 16 << shift);
6151 jcc(Assembler::less, L_check_fill_32_bytes);
6152
6153 // align data for 64-byte chunks
6154 Label L_fill_64_bytes_loop, L_align_64_bytes_loop;
6155 if (EnableX86ECoreOpts) {
6156 // align 'big' arrays to cache lines to minimize split_stores
6157 cmpptr(count, 96 << shift);
6158 jcc(Assembler::below, L_fill_64_bytes_loop);
6159
6160 // Find the bytes needed for alignment
6161 movptr(rtmp, to);
6162 andptr(rtmp, 0x1c);
6163 jcc(Assembler::zero, L_fill_64_bytes_loop);
6164 negptr(rtmp); // number of bytes to fill 32-rtmp. it filled by 2 mov by 32
6165 addptr(rtmp, 32);
6166 shrptr(rtmp, 2 - shift);// get number of elements from bytes
6167 subptr(count, rtmp); // adjust count by number of elements
6168
6169 align(16);
6170 BIND(L_align_64_bytes_loop);
6171 movdl(Address(to, 0), xtmp);
6172 addptr(to, 4);
6173 subptr(rtmp, 1 << shift);
6174 jcc(Assembler::greater, L_align_64_bytes_loop);
6175 }
6176
6177 align(16);
6178 BIND(L_fill_64_bytes_loop);
6179 vmovdqu(Address(to, 0), xtmp);
6180 vmovdqu(Address(to, 32), xtmp);
6181 addptr(to, 64);
6182 subptr(count, 16 << shift);
6183 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6184
6185 align(16);
6186 BIND(L_check_fill_32_bytes);
6187 addptr(count, 8 << shift);
6188 jccb(Assembler::less, L_check_fill_8_bytes);
6189 vmovdqu(Address(to, 0), xtmp);
6190 addptr(to, 32);
6191 subptr(count, 8 << shift);
6192
6193 BIND(L_check_fill_8_bytes);
6194 // clean upper bits of YMM registers
6195 movdl(xtmp, value);
6196 pshufd(xtmp, xtmp, 0);
6197 } else {
6198 // Fill 32-byte chunks
6199 pshufd(xtmp, xtmp, 0);
6200
6201 subptr(count, 8 << shift);
6202 jcc(Assembler::less, L_check_fill_8_bytes);
6203 align(16);
6204
6205 BIND(L_fill_32_bytes_loop);
6206
6207 if (UseUnalignedLoadStores) {
6208 movdqu(Address(to, 0), xtmp);
6209 movdqu(Address(to, 16), xtmp);
6210 } else {
6211 movq(Address(to, 0), xtmp);
6212 movq(Address(to, 8), xtmp);
6213 movq(Address(to, 16), xtmp);
6214 movq(Address(to, 24), xtmp);
6215 }
6216
6217 addptr(to, 32);
6218 subptr(count, 8 << shift);
6219 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6220
6221 BIND(L_check_fill_8_bytes);
6222 }
6223 addptr(count, 8 << shift);
6224 jccb(Assembler::zero, L_exit);
6225 jmpb(L_fill_8_bytes);
6226
6227 //
6228 // length is too short, just fill qwords
6229 //
6230 align(16);
6231 BIND(L_fill_8_bytes_loop);
6232 movq(Address(to, 0), xtmp);
6233 addptr(to, 8);
6234 BIND(L_fill_8_bytes);
6235 subptr(count, 1 << (shift + 1));
6236 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6237 }
6238 }
6239
6240 Label L_fill_4_bytes_loop;
6241 testl(count, 1 << shift);
6242 jccb(Assembler::zero, L_fill_2_bytes);
6243
6244 align(16);
6245 BIND(L_fill_4_bytes_loop);
6246 movl(Address(to, 0), value);
6247 addptr(to, 4);
6248
6249 BIND(L_fill_4_bytes);
6250 subptr(count, 1 << shift);
6251 jccb(Assembler::greaterEqual, L_fill_4_bytes_loop);
6252
6253 if (t == T_BYTE || t == T_SHORT) {
6254 Label L_fill_byte;
6255 BIND(L_fill_2_bytes);
6256 // fill trailing 2 bytes
6257 testl(count, 1<<(shift-1));
6258 jccb(Assembler::zero, L_fill_byte);
6259 movw(Address(to, 0), value);
6260 if (t == T_BYTE) {
6261 addptr(to, 2);
6262 BIND(L_fill_byte);
6263 // fill trailing byte
6264 testl(count, 1);
6265 jccb(Assembler::zero, L_exit);
6266 movb(Address(to, 0), value);
6267 } else {
6268 BIND(L_fill_byte);
6269 }
6270 } else {
6271 BIND(L_fill_2_bytes);
6272 }
6273 BIND(L_exit);
6274 }
6275
6276 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6277 switch(type) {
6278 case T_BYTE:
6279 case T_BOOLEAN:
6280 evpbroadcastb(dst, src, vector_len);
6281 break;
6282 case T_SHORT:
6283 case T_CHAR:
6284 evpbroadcastw(dst, src, vector_len);
6285 break;
6286 case T_INT:
6287 case T_FLOAT:
6288 evpbroadcastd(dst, src, vector_len);
6289 break;
6290 case T_LONG:
6291 case T_DOUBLE:
6292 evpbroadcastq(dst, src, vector_len);
6293 break;
6294 default:
6295 fatal("Unhandled type : %s", type2name(type));
6296 break;
6297 }
6298 }
6299
6300 // Encode given char[]/byte[] to byte[] in ISO_8859_1 or ASCII
6301 //
6302 // @IntrinsicCandidate
6303 // int sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(
6304 // char[] sa, int sp, byte[] da, int dp, int len) {
6305 // int i = 0;
6306 // for (; i < len; i++) {
6307 // char c = sa[sp++];
6308 // if (c > '\u00FF')
6309 // break;
6310 // da[dp++] = (byte) c;
6311 // }
6312 // return i;
6313 // }
6314 //
6315 // @IntrinsicCandidate
6316 // int java.lang.StringCoding.encodeISOArray0(
6317 // byte[] sa, int sp, byte[] da, int dp, int len) {
6318 // int i = 0;
6319 // for (; i < len; i++) {
6320 // char c = StringUTF16.getChar(sa, sp++);
6321 // if (c > '\u00FF')
6322 // break;
6323 // da[dp++] = (byte) c;
6324 // }
6325 // return i;
6326 // }
6327 //
6328 // @IntrinsicCandidate
6329 // int java.lang.StringCoding.encodeAsciiArray0(
6330 // char[] sa, int sp, byte[] da, int dp, int len) {
6331 // int i = 0;
6332 // for (; i < len; i++) {
6333 // char c = sa[sp++];
6334 // if (c >= '\u0080')
6335 // break;
6336 // da[dp++] = (byte) c;
6337 // }
6338 // return i;
6339 // }
6340 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6341 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6342 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6343 Register tmp5, Register result, bool ascii) {
6344
6345 // rsi: src
6346 // rdi: dst
6347 // rdx: len
6348 // rcx: tmp5
6349 // rax: result
6350 ShortBranchVerifier sbv(this);
6351 assert_different_registers(src, dst, len, tmp5, result);
6352 Label L_done, L_copy_1_char, L_copy_1_char_exit;
6353
6354 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
6355 int short_mask = ascii ? 0xff80 : 0xff00;
6356
6357 // set result
6358 xorl(result, result);
6359 // check for zero length
6360 testl(len, len);
6361 jcc(Assembler::zero, L_done);
6362
6363 movl(result, len);
6364
6365 // Setup pointers
6366 lea(src, Address(src, len, Address::times_2)); // char[]
6367 lea(dst, Address(dst, len, Address::times_1)); // byte[]
6368 negptr(len);
6369
6370 if (UseSSE42Intrinsics || UseAVX >= 2) {
6371 Label L_copy_8_chars, L_copy_8_chars_exit;
6372 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
6373
6374 if (UseAVX >= 2) {
6375 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
6376 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6377 movdl(tmp1Reg, tmp5);
6378 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
6379 jmp(L_chars_32_check);
6380
6381 bind(L_copy_32_chars);
6382 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
6383 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
6384 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6385 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6386 jccb(Assembler::notZero, L_copy_32_chars_exit);
6387 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6388 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
6389 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
6390
6391 bind(L_chars_32_check);
6392 addptr(len, 32);
6393 jcc(Assembler::lessEqual, L_copy_32_chars);
6394
6395 bind(L_copy_32_chars_exit);
6396 subptr(len, 16);
6397 jccb(Assembler::greater, L_copy_16_chars_exit);
6398
6399 } else if (UseSSE42Intrinsics) {
6400 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6401 movdl(tmp1Reg, tmp5);
6402 pshufd(tmp1Reg, tmp1Reg, 0);
6403 jmpb(L_chars_16_check);
6404 }
6405
6406 bind(L_copy_16_chars);
6407 if (UseAVX >= 2) {
6408 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
6409 vptest(tmp2Reg, tmp1Reg);
6410 jcc(Assembler::notZero, L_copy_16_chars_exit);
6411 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
6412 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
6413 } else {
6414 if (UseAVX > 0) {
6415 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6416 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6417 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
6418 } else {
6419 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6420 por(tmp2Reg, tmp3Reg);
6421 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6422 por(tmp2Reg, tmp4Reg);
6423 }
6424 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6425 jccb(Assembler::notZero, L_copy_16_chars_exit);
6426 packuswb(tmp3Reg, tmp4Reg);
6427 }
6428 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
6429
6430 bind(L_chars_16_check);
6431 addptr(len, 16);
6432 jcc(Assembler::lessEqual, L_copy_16_chars);
6433
6434 bind(L_copy_16_chars_exit);
6435 if (UseAVX >= 2) {
6436 // clean upper bits of YMM registers
6437 vpxor(tmp2Reg, tmp2Reg);
6438 vpxor(tmp3Reg, tmp3Reg);
6439 vpxor(tmp4Reg, tmp4Reg);
6440 movdl(tmp1Reg, tmp5);
6441 pshufd(tmp1Reg, tmp1Reg, 0);
6442 }
6443 subptr(len, 8);
6444 jccb(Assembler::greater, L_copy_8_chars_exit);
6445
6446 bind(L_copy_8_chars);
6447 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
6448 ptest(tmp3Reg, tmp1Reg);
6449 jccb(Assembler::notZero, L_copy_8_chars_exit);
6450 packuswb(tmp3Reg, tmp1Reg);
6451 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
6452 addptr(len, 8);
6453 jccb(Assembler::lessEqual, L_copy_8_chars);
6454
6455 bind(L_copy_8_chars_exit);
6456 subptr(len, 8);
6457 jccb(Assembler::zero, L_done);
6458 }
6459
6460 bind(L_copy_1_char);
6461 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
6462 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
6463 jccb(Assembler::notZero, L_copy_1_char_exit);
6464 movb(Address(dst, len, Address::times_1, 0), tmp5);
6465 addptr(len, 1);
6466 jccb(Assembler::less, L_copy_1_char);
6467
6468 bind(L_copy_1_char_exit);
6469 addptr(result, len); // len is negative count of not processed elements
6470
6471 bind(L_done);
6472 }
6473
6474 /**
6475 * Helper for multiply_to_len().
6476 */
6477 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
6478 addq(dest_lo, src1);
6479 adcq(dest_hi, 0);
6480 addq(dest_lo, src2);
6481 adcq(dest_hi, 0);
6482 }
6483
6484 /**
6485 * Multiply 64 bit by 64 bit first loop.
6486 */
6487 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
6488 Register y, Register y_idx, Register z,
6489 Register carry, Register product,
6490 Register idx, Register kdx) {
6491 //
6492 // jlong carry, x[], y[], z[];
6493 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6494 // huge_128 product = y[idx] * x[xstart] + carry;
6495 // z[kdx] = (jlong)product;
6496 // carry = (jlong)(product >>> 64);
6497 // }
6498 // z[xstart] = carry;
6499 //
6500
6501 Label L_first_loop, L_first_loop_exit;
6502 Label L_one_x, L_one_y, L_multiply;
6503
6504 decrementl(xstart);
6505 jcc(Assembler::negative, L_one_x);
6506
6507 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
6508 rorq(x_xstart, 32); // convert big-endian to little-endian
6509
6510 bind(L_first_loop);
6511 decrementl(idx);
6512 jcc(Assembler::negative, L_first_loop_exit);
6513 decrementl(idx);
6514 jcc(Assembler::negative, L_one_y);
6515 movq(y_idx, Address(y, idx, Address::times_4, 0));
6516 rorq(y_idx, 32); // convert big-endian to little-endian
6517 bind(L_multiply);
6518 movq(product, x_xstart);
6519 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
6520 addq(product, carry);
6521 adcq(rdx, 0);
6522 subl(kdx, 2);
6523 movl(Address(z, kdx, Address::times_4, 4), product);
6524 shrq(product, 32);
6525 movl(Address(z, kdx, Address::times_4, 0), product);
6526 movq(carry, rdx);
6527 jmp(L_first_loop);
6528
6529 bind(L_one_y);
6530 movl(y_idx, Address(y, 0));
6531 jmp(L_multiply);
6532
6533 bind(L_one_x);
6534 movl(x_xstart, Address(x, 0));
6535 jmp(L_first_loop);
6536
6537 bind(L_first_loop_exit);
6538 }
6539
6540 /**
6541 * Multiply 64 bit by 64 bit and add 128 bit.
6542 */
6543 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
6544 Register yz_idx, Register idx,
6545 Register carry, Register product, int offset) {
6546 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
6547 // z[kdx] = (jlong)product;
6548
6549 movq(yz_idx, Address(y, idx, Address::times_4, offset));
6550 rorq(yz_idx, 32); // convert big-endian to little-endian
6551 movq(product, x_xstart);
6552 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
6553 movq(yz_idx, Address(z, idx, Address::times_4, offset));
6554 rorq(yz_idx, 32); // convert big-endian to little-endian
6555
6556 add2_with_carry(rdx, product, carry, yz_idx);
6557
6558 movl(Address(z, idx, Address::times_4, offset+4), product);
6559 shrq(product, 32);
6560 movl(Address(z, idx, Address::times_4, offset), product);
6561
6562 }
6563
6564 /**
6565 * Multiply 128 bit by 128 bit. Unrolled inner loop.
6566 */
6567 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
6568 Register yz_idx, Register idx, Register jdx,
6569 Register carry, Register product,
6570 Register carry2) {
6571 // jlong carry, x[], y[], z[];
6572 // int kdx = ystart+1;
6573 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6574 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
6575 // z[kdx+idx+1] = (jlong)product;
6576 // jlong carry2 = (jlong)(product >>> 64);
6577 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
6578 // z[kdx+idx] = (jlong)product;
6579 // carry = (jlong)(product >>> 64);
6580 // }
6581 // idx += 2;
6582 // if (idx > 0) {
6583 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
6584 // z[kdx+idx] = (jlong)product;
6585 // carry = (jlong)(product >>> 64);
6586 // }
6587 //
6588
6589 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6590
6591 movl(jdx, idx);
6592 andl(jdx, 0xFFFFFFFC);
6593 shrl(jdx, 2);
6594
6595 bind(L_third_loop);
6596 subl(jdx, 1);
6597 jcc(Assembler::negative, L_third_loop_exit);
6598 subl(idx, 4);
6599
6600 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
6601 movq(carry2, rdx);
6602
6603 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
6604 movq(carry, rdx);
6605 jmp(L_third_loop);
6606
6607 bind (L_third_loop_exit);
6608
6609 andl (idx, 0x3);
6610 jcc(Assembler::zero, L_post_third_loop_done);
6611
6612 Label L_check_1;
6613 subl(idx, 2);
6614 jcc(Assembler::negative, L_check_1);
6615
6616 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
6617 movq(carry, rdx);
6618
6619 bind (L_check_1);
6620 addl (idx, 0x2);
6621 andl (idx, 0x1);
6622 subl(idx, 1);
6623 jcc(Assembler::negative, L_post_third_loop_done);
6624
6625 movl(yz_idx, Address(y, idx, Address::times_4, 0));
6626 movq(product, x_xstart);
6627 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
6628 movl(yz_idx, Address(z, idx, Address::times_4, 0));
6629
6630 add2_with_carry(rdx, product, yz_idx, carry);
6631
6632 movl(Address(z, idx, Address::times_4, 0), product);
6633 shrq(product, 32);
6634
6635 shlq(rdx, 32);
6636 orq(product, rdx);
6637 movq(carry, product);
6638
6639 bind(L_post_third_loop_done);
6640 }
6641
6642 /**
6643 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
6644 *
6645 */
6646 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
6647 Register carry, Register carry2,
6648 Register idx, Register jdx,
6649 Register yz_idx1, Register yz_idx2,
6650 Register tmp, Register tmp3, Register tmp4) {
6651 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
6652
6653 // jlong carry, x[], y[], z[];
6654 // int kdx = ystart+1;
6655 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6656 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
6657 // jlong carry2 = (jlong)(tmp3 >>> 64);
6658 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
6659 // carry = (jlong)(tmp4 >>> 64);
6660 // z[kdx+idx+1] = (jlong)tmp3;
6661 // z[kdx+idx] = (jlong)tmp4;
6662 // }
6663 // idx += 2;
6664 // if (idx > 0) {
6665 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
6666 // z[kdx+idx] = (jlong)yz_idx1;
6667 // carry = (jlong)(yz_idx1 >>> 64);
6668 // }
6669 //
6670
6671 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6672
6673 movl(jdx, idx);
6674 andl(jdx, 0xFFFFFFFC);
6675 shrl(jdx, 2);
6676
6677 bind(L_third_loop);
6678 subl(jdx, 1);
6679 jcc(Assembler::negative, L_third_loop_exit);
6680 subl(idx, 4);
6681
6682 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
6683 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
6684 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
6685 rorxq(yz_idx2, yz_idx2, 32);
6686
6687 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
6688 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
6689
6690 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
6691 rorxq(yz_idx1, yz_idx1, 32);
6692 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
6693 rorxq(yz_idx2, yz_idx2, 32);
6694
6695 if (VM_Version::supports_adx()) {
6696 adcxq(tmp3, carry);
6697 adoxq(tmp3, yz_idx1);
6698
6699 adcxq(tmp4, tmp);
6700 adoxq(tmp4, yz_idx2);
6701
6702 movl(carry, 0); // does not affect flags
6703 adcxq(carry2, carry);
6704 adoxq(carry2, carry);
6705 } else {
6706 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
6707 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
6708 }
6709 movq(carry, carry2);
6710
6711 movl(Address(z, idx, Address::times_4, 12), tmp3);
6712 shrq(tmp3, 32);
6713 movl(Address(z, idx, Address::times_4, 8), tmp3);
6714
6715 movl(Address(z, idx, Address::times_4, 4), tmp4);
6716 shrq(tmp4, 32);
6717 movl(Address(z, idx, Address::times_4, 0), tmp4);
6718
6719 jmp(L_third_loop);
6720
6721 bind (L_third_loop_exit);
6722
6723 andl (idx, 0x3);
6724 jcc(Assembler::zero, L_post_third_loop_done);
6725
6726 Label L_check_1;
6727 subl(idx, 2);
6728 jcc(Assembler::negative, L_check_1);
6729
6730 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
6731 rorxq(yz_idx1, yz_idx1, 32);
6732 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
6733 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
6734 rorxq(yz_idx2, yz_idx2, 32);
6735
6736 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
6737
6738 movl(Address(z, idx, Address::times_4, 4), tmp3);
6739 shrq(tmp3, 32);
6740 movl(Address(z, idx, Address::times_4, 0), tmp3);
6741 movq(carry, tmp4);
6742
6743 bind (L_check_1);
6744 addl (idx, 0x2);
6745 andl (idx, 0x1);
6746 subl(idx, 1);
6747 jcc(Assembler::negative, L_post_third_loop_done);
6748 movl(tmp4, Address(y, idx, Address::times_4, 0));
6749 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
6750 movl(tmp4, Address(z, idx, Address::times_4, 0));
6751
6752 add2_with_carry(carry2, tmp3, tmp4, carry);
6753
6754 movl(Address(z, idx, Address::times_4, 0), tmp3);
6755 shrq(tmp3, 32);
6756
6757 shlq(carry2, 32);
6758 orq(tmp3, carry2);
6759 movq(carry, tmp3);
6760
6761 bind(L_post_third_loop_done);
6762 }
6763
6764 /**
6765 * Code for BigInteger::multiplyToLen() intrinsic.
6766 *
6767 * rdi: x
6768 * rax: xlen
6769 * rsi: y
6770 * rcx: ylen
6771 * r8: z
6772 * r11: tmp0
6773 * r12: tmp1
6774 * r13: tmp2
6775 * r14: tmp3
6776 * r15: tmp4
6777 * rbx: tmp5
6778 *
6779 */
6780 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
6781 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
6782 ShortBranchVerifier sbv(this);
6783 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
6784
6785 push(tmp0);
6786 push(tmp1);
6787 push(tmp2);
6788 push(tmp3);
6789 push(tmp4);
6790 push(tmp5);
6791
6792 push(xlen);
6793
6794 const Register idx = tmp1;
6795 const Register kdx = tmp2;
6796 const Register xstart = tmp3;
6797
6798 const Register y_idx = tmp4;
6799 const Register carry = tmp5;
6800 const Register product = xlen;
6801 const Register x_xstart = tmp0;
6802
6803 // First Loop.
6804 //
6805 // final static long LONG_MASK = 0xffffffffL;
6806 // int xstart = xlen - 1;
6807 // int ystart = ylen - 1;
6808 // long carry = 0;
6809 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6810 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
6811 // z[kdx] = (int)product;
6812 // carry = product >>> 32;
6813 // }
6814 // z[xstart] = (int)carry;
6815 //
6816
6817 movl(idx, ylen); // idx = ylen;
6818 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
6819 xorq(carry, carry); // carry = 0;
6820
6821 Label L_done;
6822
6823 movl(xstart, xlen);
6824 decrementl(xstart);
6825 jcc(Assembler::negative, L_done);
6826
6827 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
6828
6829 Label L_second_loop;
6830 testl(kdx, kdx);
6831 jcc(Assembler::zero, L_second_loop);
6832
6833 Label L_carry;
6834 subl(kdx, 1);
6835 jcc(Assembler::zero, L_carry);
6836
6837 movl(Address(z, kdx, Address::times_4, 0), carry);
6838 shrq(carry, 32);
6839 subl(kdx, 1);
6840
6841 bind(L_carry);
6842 movl(Address(z, kdx, Address::times_4, 0), carry);
6843
6844 // Second and third (nested) loops.
6845 //
6846 // for (int i = xstart-1; i >= 0; i--) { // Second loop
6847 // carry = 0;
6848 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
6849 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
6850 // (z[k] & LONG_MASK) + carry;
6851 // z[k] = (int)product;
6852 // carry = product >>> 32;
6853 // }
6854 // z[i] = (int)carry;
6855 // }
6856 //
6857 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
6858
6859 const Register jdx = tmp1;
6860
6861 bind(L_second_loop);
6862 xorl(carry, carry); // carry = 0;
6863 movl(jdx, ylen); // j = ystart+1
6864
6865 subl(xstart, 1); // i = xstart-1;
6866 jcc(Assembler::negative, L_done);
6867
6868 push (z);
6869
6870 Label L_last_x;
6871 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
6872 subl(xstart, 1); // i = xstart-1;
6873 jcc(Assembler::negative, L_last_x);
6874
6875 if (UseBMI2Instructions) {
6876 movq(rdx, Address(x, xstart, Address::times_4, 0));
6877 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
6878 } else {
6879 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
6880 rorq(x_xstart, 32); // convert big-endian to little-endian
6881 }
6882
6883 Label L_third_loop_prologue;
6884 bind(L_third_loop_prologue);
6885
6886 push (x);
6887 push (xstart);
6888 push (ylen);
6889
6890
6891 if (UseBMI2Instructions) {
6892 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
6893 } else { // !UseBMI2Instructions
6894 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
6895 }
6896
6897 pop(ylen);
6898 pop(xlen);
6899 pop(x);
6900 pop(z);
6901
6902 movl(tmp3, xlen);
6903 addl(tmp3, 1);
6904 movl(Address(z, tmp3, Address::times_4, 0), carry);
6905 subl(tmp3, 1);
6906 jccb(Assembler::negative, L_done);
6907
6908 shrq(carry, 32);
6909 movl(Address(z, tmp3, Address::times_4, 0), carry);
6910 jmp(L_second_loop);
6911
6912 // Next infrequent code is moved outside loops.
6913 bind(L_last_x);
6914 if (UseBMI2Instructions) {
6915 movl(rdx, Address(x, 0));
6916 } else {
6917 movl(x_xstart, Address(x, 0));
6918 }
6919 jmp(L_third_loop_prologue);
6920
6921 bind(L_done);
6922
6923 pop(xlen);
6924
6925 pop(tmp5);
6926 pop(tmp4);
6927 pop(tmp3);
6928 pop(tmp2);
6929 pop(tmp1);
6930 pop(tmp0);
6931 }
6932
6933 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
6934 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
6935 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
6936 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
6937 Label VECTOR8_TAIL, VECTOR4_TAIL;
6938 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
6939 Label SAME_TILL_END, DONE;
6940 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
6941
6942 //scale is in rcx in both Win64 and Unix
6943 ShortBranchVerifier sbv(this);
6944
6945 shlq(length);
6946 xorq(result, result);
6947
6948 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
6949 VM_Version::supports_avx512vlbw()) {
6950 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
6951
6952 cmpq(length, 64);
6953 jcc(Assembler::less, VECTOR32_TAIL);
6954
6955 movq(tmp1, length);
6956 andq(tmp1, 0x3F); // tail count
6957 andq(length, ~(0x3F)); //vector count
6958
6959 bind(VECTOR64_LOOP);
6960 // AVX512 code to compare 64 byte vectors.
6961 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
6962 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
6963 kortestql(k7, k7);
6964 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
6965 addq(result, 64);
6966 subq(length, 64);
6967 jccb(Assembler::notZero, VECTOR64_LOOP);
6968
6969 //bind(VECTOR64_TAIL);
6970 testq(tmp1, tmp1);
6971 jcc(Assembler::zero, SAME_TILL_END);
6972
6973 //bind(VECTOR64_TAIL);
6974 // AVX512 code to compare up to 63 byte vectors.
6975 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
6976 shlxq(tmp2, tmp2, tmp1);
6977 notq(tmp2);
6978 kmovql(k3, tmp2);
6979
6980 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
6981 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
6982
6983 ktestql(k7, k3);
6984 jcc(Assembler::below, SAME_TILL_END); // not mismatch
6985
6986 bind(VECTOR64_NOT_EQUAL);
6987 kmovql(tmp1, k7);
6988 notq(tmp1);
6989 tzcntq(tmp1, tmp1);
6990 addq(result, tmp1);
6991 shrq(result);
6992 jmp(DONE);
6993 bind(VECTOR32_TAIL);
6994 }
6995
6996 cmpq(length, 8);
6997 jcc(Assembler::equal, VECTOR8_LOOP);
6998 jcc(Assembler::less, VECTOR4_TAIL);
6999
7000 if (UseAVX >= 2) {
7001 Label VECTOR16_TAIL, VECTOR32_LOOP;
7002
7003 cmpq(length, 16);
7004 jcc(Assembler::equal, VECTOR16_LOOP);
7005 jcc(Assembler::less, VECTOR8_LOOP);
7006
7007 cmpq(length, 32);
7008 jccb(Assembler::less, VECTOR16_TAIL);
7009
7010 subq(length, 32);
7011 bind(VECTOR32_LOOP);
7012 vmovdqu(rymm0, Address(obja, result));
7013 vmovdqu(rymm1, Address(objb, result));
7014 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7015 vptest(rymm2, rymm2);
7016 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7017 addq(result, 32);
7018 subq(length, 32);
7019 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7020 addq(length, 32);
7021 jcc(Assembler::equal, SAME_TILL_END);
7022 //falling through if less than 32 bytes left //close the branch here.
7023
7024 bind(VECTOR16_TAIL);
7025 cmpq(length, 16);
7026 jccb(Assembler::less, VECTOR8_TAIL);
7027 bind(VECTOR16_LOOP);
7028 movdqu(rymm0, Address(obja, result));
7029 movdqu(rymm1, Address(objb, result));
7030 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7031 ptest(rymm2, rymm2);
7032 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7033 addq(result, 16);
7034 subq(length, 16);
7035 jcc(Assembler::equal, SAME_TILL_END);
7036 //falling through if less than 16 bytes left
7037 } else {//regular intrinsics
7038
7039 cmpq(length, 16);
7040 jccb(Assembler::less, VECTOR8_TAIL);
7041
7042 subq(length, 16);
7043 bind(VECTOR16_LOOP);
7044 movdqu(rymm0, Address(obja, result));
7045 movdqu(rymm1, Address(objb, result));
7046 pxor(rymm0, rymm1);
7047 ptest(rymm0, rymm0);
7048 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7049 addq(result, 16);
7050 subq(length, 16);
7051 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7052 addq(length, 16);
7053 jcc(Assembler::equal, SAME_TILL_END);
7054 //falling through if less than 16 bytes left
7055 }
7056
7057 bind(VECTOR8_TAIL);
7058 cmpq(length, 8);
7059 jccb(Assembler::less, VECTOR4_TAIL);
7060 bind(VECTOR8_LOOP);
7061 movq(tmp1, Address(obja, result));
7062 movq(tmp2, Address(objb, result));
7063 xorq(tmp1, tmp2);
7064 testq(tmp1, tmp1);
7065 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7066 addq(result, 8);
7067 subq(length, 8);
7068 jcc(Assembler::equal, SAME_TILL_END);
7069 //falling through if less than 8 bytes left
7070
7071 bind(VECTOR4_TAIL);
7072 cmpq(length, 4);
7073 jccb(Assembler::less, BYTES_TAIL);
7074 bind(VECTOR4_LOOP);
7075 movl(tmp1, Address(obja, result));
7076 xorl(tmp1, Address(objb, result));
7077 testl(tmp1, tmp1);
7078 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7079 addq(result, 4);
7080 subq(length, 4);
7081 jcc(Assembler::equal, SAME_TILL_END);
7082 //falling through if less than 4 bytes left
7083
7084 bind(BYTES_TAIL);
7085 bind(BYTES_LOOP);
7086 load_unsigned_byte(tmp1, Address(obja, result));
7087 load_unsigned_byte(tmp2, Address(objb, result));
7088 xorl(tmp1, tmp2);
7089 testl(tmp1, tmp1);
7090 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7091 decq(length);
7092 jcc(Assembler::zero, SAME_TILL_END);
7093 incq(result);
7094 load_unsigned_byte(tmp1, Address(obja, result));
7095 load_unsigned_byte(tmp2, Address(objb, result));
7096 xorl(tmp1, tmp2);
7097 testl(tmp1, tmp1);
7098 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7099 decq(length);
7100 jcc(Assembler::zero, SAME_TILL_END);
7101 incq(result);
7102 load_unsigned_byte(tmp1, Address(obja, result));
7103 load_unsigned_byte(tmp2, Address(objb, result));
7104 xorl(tmp1, tmp2);
7105 testl(tmp1, tmp1);
7106 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7107 jmp(SAME_TILL_END);
7108
7109 if (UseAVX >= 2) {
7110 bind(VECTOR32_NOT_EQUAL);
7111 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7112 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7113 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7114 vpmovmskb(tmp1, rymm0);
7115 bsfq(tmp1, tmp1);
7116 addq(result, tmp1);
7117 shrq(result);
7118 jmp(DONE);
7119 }
7120
7121 bind(VECTOR16_NOT_EQUAL);
7122 if (UseAVX >= 2) {
7123 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7124 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7125 pxor(rymm0, rymm2);
7126 } else {
7127 pcmpeqb(rymm2, rymm2);
7128 pxor(rymm0, rymm1);
7129 pcmpeqb(rymm0, rymm1);
7130 pxor(rymm0, rymm2);
7131 }
7132 pmovmskb(tmp1, rymm0);
7133 bsfq(tmp1, tmp1);
7134 addq(result, tmp1);
7135 shrq(result);
7136 jmpb(DONE);
7137
7138 bind(VECTOR8_NOT_EQUAL);
7139 bind(VECTOR4_NOT_EQUAL);
7140 bsfq(tmp1, tmp1);
7141 shrq(tmp1, 3);
7142 addq(result, tmp1);
7143 bind(BYTES_NOT_EQUAL);
7144 shrq(result);
7145 jmpb(DONE);
7146
7147 bind(SAME_TILL_END);
7148 mov64(result, -1);
7149
7150 bind(DONE);
7151 }
7152
7153 //Helper functions for square_to_len()
7154
7155 /**
7156 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7157 * Preserves x and z and modifies rest of the registers.
7158 */
7159 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7160 // Perform square and right shift by 1
7161 // Handle odd xlen case first, then for even xlen do the following
7162 // jlong carry = 0;
7163 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7164 // huge_128 product = x[j:j+1] * x[j:j+1];
7165 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7166 // z[i+2:i+3] = (jlong)(product >>> 1);
7167 // carry = (jlong)product;
7168 // }
7169
7170 xorq(tmp5, tmp5); // carry
7171 xorq(rdxReg, rdxReg);
7172 xorl(tmp1, tmp1); // index for x
7173 xorl(tmp4, tmp4); // index for z
7174
7175 Label L_first_loop, L_first_loop_exit;
7176
7177 testl(xlen, 1);
7178 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7179
7180 // Square and right shift by 1 the odd element using 32 bit multiply
7181 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7182 imulq(raxReg, raxReg);
7183 shrq(raxReg, 1);
7184 adcq(tmp5, 0);
7185 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7186 incrementl(tmp1);
7187 addl(tmp4, 2);
7188
7189 // Square and right shift by 1 the rest using 64 bit multiply
7190 bind(L_first_loop);
7191 cmpptr(tmp1, xlen);
7192 jccb(Assembler::equal, L_first_loop_exit);
7193
7194 // Square
7195 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7196 rorq(raxReg, 32); // convert big-endian to little-endian
7197 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7198
7199 // Right shift by 1 and save carry
7200 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7201 rcrq(rdxReg, 1);
7202 rcrq(raxReg, 1);
7203 adcq(tmp5, 0);
7204
7205 // Store result in z
7206 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7207 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7208
7209 // Update indices for x and z
7210 addl(tmp1, 2);
7211 addl(tmp4, 4);
7212 jmp(L_first_loop);
7213
7214 bind(L_first_loop_exit);
7215 }
7216
7217
7218 /**
7219 * Perform the following multiply add operation using BMI2 instructions
7220 * carry:sum = sum + op1*op2 + carry
7221 * op2 should be in rdx
7222 * op2 is preserved, all other registers are modified
7223 */
7224 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7225 // assert op2 is rdx
7226 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7227 addq(sum, carry);
7228 adcq(tmp2, 0);
7229 addq(sum, op1);
7230 adcq(tmp2, 0);
7231 movq(carry, tmp2);
7232 }
7233
7234 /**
7235 * Perform the following multiply add operation:
7236 * carry:sum = sum + op1*op2 + carry
7237 * Preserves op1, op2 and modifies rest of registers
7238 */
7239 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7240 // rdx:rax = op1 * op2
7241 movq(raxReg, op2);
7242 mulq(op1);
7243
7244 // rdx:rax = sum + carry + rdx:rax
7245 addq(sum, carry);
7246 adcq(rdxReg, 0);
7247 addq(sum, raxReg);
7248 adcq(rdxReg, 0);
7249
7250 // carry:sum = rdx:sum
7251 movq(carry, rdxReg);
7252 }
7253
7254 /**
7255 * Add 64 bit long carry into z[] with carry propagation.
7256 * Preserves z and carry register values and modifies rest of registers.
7257 *
7258 */
7259 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7260 Label L_fourth_loop, L_fourth_loop_exit;
7261
7262 movl(tmp1, 1);
7263 subl(zlen, 2);
7264 addq(Address(z, zlen, Address::times_4, 0), carry);
7265
7266 bind(L_fourth_loop);
7267 jccb(Assembler::carryClear, L_fourth_loop_exit);
7268 subl(zlen, 2);
7269 jccb(Assembler::negative, L_fourth_loop_exit);
7270 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7271 jmp(L_fourth_loop);
7272 bind(L_fourth_loop_exit);
7273 }
7274
7275 /**
7276 * Shift z[] left by 1 bit.
7277 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7278 *
7279 */
7280 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7281
7282 Label L_fifth_loop, L_fifth_loop_exit;
7283
7284 // Fifth loop
7285 // Perform primitiveLeftShift(z, zlen, 1)
7286
7287 const Register prev_carry = tmp1;
7288 const Register new_carry = tmp4;
7289 const Register value = tmp2;
7290 const Register zidx = tmp3;
7291
7292 // int zidx, carry;
7293 // long value;
7294 // carry = 0;
7295 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7296 // (carry:value) = (z[i] << 1) | carry ;
7297 // z[i] = value;
7298 // }
7299
7300 movl(zidx, zlen);
7301 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7302
7303 bind(L_fifth_loop);
7304 decl(zidx); // Use decl to preserve carry flag
7305 decl(zidx);
7306 jccb(Assembler::negative, L_fifth_loop_exit);
7307
7308 if (UseBMI2Instructions) {
7309 movq(value, Address(z, zidx, Address::times_4, 0));
7310 rclq(value, 1);
7311 rorxq(value, value, 32);
7312 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7313 }
7314 else {
7315 // clear new_carry
7316 xorl(new_carry, new_carry);
7317
7318 // Shift z[i] by 1, or in previous carry and save new carry
7319 movq(value, Address(z, zidx, Address::times_4, 0));
7320 shlq(value, 1);
7321 adcl(new_carry, 0);
7322
7323 orq(value, prev_carry);
7324 rorq(value, 0x20);
7325 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7326
7327 // Set previous carry = new carry
7328 movl(prev_carry, new_carry);
7329 }
7330 jmp(L_fifth_loop);
7331
7332 bind(L_fifth_loop_exit);
7333 }
7334
7335
7336 /**
7337 * Code for BigInteger::squareToLen() intrinsic
7338 *
7339 * rdi: x
7340 * rsi: len
7341 * r8: z
7342 * rcx: zlen
7343 * r12: tmp1
7344 * r13: tmp2
7345 * r14: tmp3
7346 * r15: tmp4
7347 * rbx: tmp5
7348 *
7349 */
7350 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7351
7352 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
7353 push(tmp1);
7354 push(tmp2);
7355 push(tmp3);
7356 push(tmp4);
7357 push(tmp5);
7358
7359 // First loop
7360 // Store the squares, right shifted one bit (i.e., divided by 2).
7361 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7362
7363 // Add in off-diagonal sums.
7364 //
7365 // Second, third (nested) and fourth loops.
7366 // zlen +=2;
7367 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7368 // carry = 0;
7369 // long op2 = x[xidx:xidx+1];
7370 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7371 // k -= 2;
7372 // long op1 = x[j:j+1];
7373 // long sum = z[k:k+1];
7374 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7375 // z[k:k+1] = sum;
7376 // }
7377 // add_one_64(z, k, carry, tmp_regs);
7378 // }
7379
7380 const Register carry = tmp5;
7381 const Register sum = tmp3;
7382 const Register op1 = tmp4;
7383 Register op2 = tmp2;
7384
7385 push(zlen);
7386 push(len);
7387 addl(zlen,2);
7388 bind(L_second_loop);
7389 xorq(carry, carry);
7390 subl(zlen, 4);
7391 subl(len, 2);
7392 push(zlen);
7393 push(len);
7394 cmpl(len, 0);
7395 jccb(Assembler::lessEqual, L_second_loop_exit);
7396
7397 // Multiply an array by one 64 bit long.
7398 if (UseBMI2Instructions) {
7399 op2 = rdxReg;
7400 movq(op2, Address(x, len, Address::times_4, 0));
7401 rorxq(op2, op2, 32);
7402 }
7403 else {
7404 movq(op2, Address(x, len, Address::times_4, 0));
7405 rorq(op2, 32);
7406 }
7407
7408 bind(L_third_loop);
7409 decrementl(len);
7410 jccb(Assembler::negative, L_third_loop_exit);
7411 decrementl(len);
7412 jccb(Assembler::negative, L_last_x);
7413
7414 movq(op1, Address(x, len, Address::times_4, 0));
7415 rorq(op1, 32);
7416
7417 bind(L_multiply);
7418 subl(zlen, 2);
7419 movq(sum, Address(z, zlen, Address::times_4, 0));
7420
7421 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
7422 if (UseBMI2Instructions) {
7423 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
7424 }
7425 else {
7426 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7427 }
7428
7429 movq(Address(z, zlen, Address::times_4, 0), sum);
7430
7431 jmp(L_third_loop);
7432 bind(L_third_loop_exit);
7433
7434 // Fourth loop
7435 // Add 64 bit long carry into z with carry propagation.
7436 // Uses offsetted zlen.
7437 add_one_64(z, zlen, carry, tmp1);
7438
7439 pop(len);
7440 pop(zlen);
7441 jmp(L_second_loop);
7442
7443 // Next infrequent code is moved outside loops.
7444 bind(L_last_x);
7445 movl(op1, Address(x, 0));
7446 jmp(L_multiply);
7447
7448 bind(L_second_loop_exit);
7449 pop(len);
7450 pop(zlen);
7451 pop(len);
7452 pop(zlen);
7453
7454 // Fifth loop
7455 // Shift z left 1 bit.
7456 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
7457
7458 // z[zlen-1] |= x[len-1] & 1;
7459 movl(tmp3, Address(x, len, Address::times_4, -4));
7460 andl(tmp3, 1);
7461 orl(Address(z, zlen, Address::times_4, -4), tmp3);
7462
7463 pop(tmp5);
7464 pop(tmp4);
7465 pop(tmp3);
7466 pop(tmp2);
7467 pop(tmp1);
7468 }
7469
7470 /**
7471 * Helper function for mul_add()
7472 * Multiply the in[] by int k and add to out[] starting at offset offs using
7473 * 128 bit by 32 bit multiply and return the carry in tmp5.
7474 * Only quad int aligned length of in[] is operated on in this function.
7475 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
7476 * This function preserves out, in and k registers.
7477 * len and offset point to the appropriate index in "in" & "out" correspondingly
7478 * tmp5 has the carry.
7479 * other registers are temporary and are modified.
7480 *
7481 */
7482 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
7483 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
7484 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7485
7486 Label L_first_loop, L_first_loop_exit;
7487
7488 movl(tmp1, len);
7489 shrl(tmp1, 2);
7490
7491 bind(L_first_loop);
7492 subl(tmp1, 1);
7493 jccb(Assembler::negative, L_first_loop_exit);
7494
7495 subl(len, 4);
7496 subl(offset, 4);
7497
7498 Register op2 = tmp2;
7499 const Register sum = tmp3;
7500 const Register op1 = tmp4;
7501 const Register carry = tmp5;
7502
7503 if (UseBMI2Instructions) {
7504 op2 = rdxReg;
7505 }
7506
7507 movq(op1, Address(in, len, Address::times_4, 8));
7508 rorq(op1, 32);
7509 movq(sum, Address(out, offset, Address::times_4, 8));
7510 rorq(sum, 32);
7511 if (UseBMI2Instructions) {
7512 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7513 }
7514 else {
7515 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7516 }
7517 // Store back in big endian from little endian
7518 rorq(sum, 0x20);
7519 movq(Address(out, offset, Address::times_4, 8), sum);
7520
7521 movq(op1, Address(in, len, Address::times_4, 0));
7522 rorq(op1, 32);
7523 movq(sum, Address(out, offset, Address::times_4, 0));
7524 rorq(sum, 32);
7525 if (UseBMI2Instructions) {
7526 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7527 }
7528 else {
7529 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7530 }
7531 // Store back in big endian from little endian
7532 rorq(sum, 0x20);
7533 movq(Address(out, offset, Address::times_4, 0), sum);
7534
7535 jmp(L_first_loop);
7536 bind(L_first_loop_exit);
7537 }
7538
7539 /**
7540 * Code for BigInteger::mulAdd() intrinsic
7541 *
7542 * rdi: out
7543 * rsi: in
7544 * r11: offs (out.length - offset)
7545 * rcx: len
7546 * r8: k
7547 * r12: tmp1
7548 * r13: tmp2
7549 * r14: tmp3
7550 * r15: tmp4
7551 * rbx: tmp5
7552 * Multiply the in[] by word k and add to out[], return the carry in rax
7553 */
7554 void MacroAssembler::mul_add(Register out, Register in, Register offs,
7555 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
7556 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7557
7558 Label L_carry, L_last_in, L_done;
7559
7560 // carry = 0;
7561 // for (int j=len-1; j >= 0; j--) {
7562 // long product = (in[j] & LONG_MASK) * kLong +
7563 // (out[offs] & LONG_MASK) + carry;
7564 // out[offs--] = (int)product;
7565 // carry = product >>> 32;
7566 // }
7567 //
7568 push(tmp1);
7569 push(tmp2);
7570 push(tmp3);
7571 push(tmp4);
7572 push(tmp5);
7573
7574 Register op2 = tmp2;
7575 const Register sum = tmp3;
7576 const Register op1 = tmp4;
7577 const Register carry = tmp5;
7578
7579 if (UseBMI2Instructions) {
7580 op2 = rdxReg;
7581 movl(op2, k);
7582 }
7583 else {
7584 movl(op2, k);
7585 }
7586
7587 xorq(carry, carry);
7588
7589 //First loop
7590
7591 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
7592 //The carry is in tmp5
7593 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
7594
7595 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
7596 decrementl(len);
7597 jccb(Assembler::negative, L_carry);
7598 decrementl(len);
7599 jccb(Assembler::negative, L_last_in);
7600
7601 movq(op1, Address(in, len, Address::times_4, 0));
7602 rorq(op1, 32);
7603
7604 subl(offs, 2);
7605 movq(sum, Address(out, offs, Address::times_4, 0));
7606 rorq(sum, 32);
7607
7608 if (UseBMI2Instructions) {
7609 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7610 }
7611 else {
7612 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7613 }
7614
7615 // Store back in big endian from little endian
7616 rorq(sum, 0x20);
7617 movq(Address(out, offs, Address::times_4, 0), sum);
7618
7619 testl(len, len);
7620 jccb(Assembler::zero, L_carry);
7621
7622 //Multiply the last in[] entry, if any
7623 bind(L_last_in);
7624 movl(op1, Address(in, 0));
7625 movl(sum, Address(out, offs, Address::times_4, -4));
7626
7627 movl(raxReg, k);
7628 mull(op1); //tmp4 * eax -> edx:eax
7629 addl(sum, carry);
7630 adcl(rdxReg, 0);
7631 addl(sum, raxReg);
7632 adcl(rdxReg, 0);
7633 movl(carry, rdxReg);
7634
7635 movl(Address(out, offs, Address::times_4, -4), sum);
7636
7637 bind(L_carry);
7638 //return tmp5/carry as carry in rax
7639 movl(rax, carry);
7640
7641 bind(L_done);
7642 pop(tmp5);
7643 pop(tmp4);
7644 pop(tmp3);
7645 pop(tmp2);
7646 pop(tmp1);
7647 }
7648
7649 /**
7650 * Emits code to update CRC-32 with a byte value according to constants in table
7651 *
7652 * @param [in,out]crc Register containing the crc.
7653 * @param [in]val Register containing the byte to fold into the CRC.
7654 * @param [in]table Register containing the table of crc constants.
7655 *
7656 * uint32_t crc;
7657 * val = crc_table[(val ^ crc) & 0xFF];
7658 * crc = val ^ (crc >> 8);
7659 *
7660 */
7661 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
7662 xorl(val, crc);
7663 andl(val, 0xFF);
7664 shrl(crc, 8); // unsigned shift
7665 xorl(crc, Address(table, val, Address::times_4, 0));
7666 }
7667
7668 /**
7669 * Fold 128-bit data chunk
7670 */
7671 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
7672 if (UseAVX > 0) {
7673 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
7674 vpclmulldq(xcrc, xK, xcrc); // [63:0]
7675 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
7676 pxor(xcrc, xtmp);
7677 } else {
7678 movdqa(xtmp, xcrc);
7679 pclmulhdq(xtmp, xK); // [123:64]
7680 pclmulldq(xcrc, xK); // [63:0]
7681 pxor(xcrc, xtmp);
7682 movdqu(xtmp, Address(buf, offset));
7683 pxor(xcrc, xtmp);
7684 }
7685 }
7686
7687 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
7688 if (UseAVX > 0) {
7689 vpclmulhdq(xtmp, xK, xcrc);
7690 vpclmulldq(xcrc, xK, xcrc);
7691 pxor(xcrc, xbuf);
7692 pxor(xcrc, xtmp);
7693 } else {
7694 movdqa(xtmp, xcrc);
7695 pclmulhdq(xtmp, xK);
7696 pclmulldq(xcrc, xK);
7697 pxor(xcrc, xbuf);
7698 pxor(xcrc, xtmp);
7699 }
7700 }
7701
7702 /**
7703 * 8-bit folds to compute 32-bit CRC
7704 *
7705 * uint64_t xcrc;
7706 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
7707 */
7708 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
7709 movdl(tmp, xcrc);
7710 andl(tmp, 0xFF);
7711 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
7712 psrldq(xcrc, 1); // unsigned shift one byte
7713 pxor(xcrc, xtmp);
7714 }
7715
7716 /**
7717 * uint32_t crc;
7718 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
7719 */
7720 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
7721 movl(tmp, crc);
7722 andl(tmp, 0xFF);
7723 shrl(crc, 8);
7724 xorl(crc, Address(table, tmp, Address::times_4, 0));
7725 }
7726
7727 /**
7728 * @param crc register containing existing CRC (32-bit)
7729 * @param buf register pointing to input byte buffer (byte*)
7730 * @param len register containing number of bytes
7731 * @param table register that will contain address of CRC table
7732 * @param tmp scratch register
7733 */
7734 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
7735 assert_different_registers(crc, buf, len, table, tmp, rax);
7736
7737 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7738 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7739
7740 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
7741 // context for the registers used, where all instructions below are using 128-bit mode
7742 // On EVEX without VL and BW, these instructions will all be AVX.
7743 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
7744 notl(crc); // ~crc
7745 cmpl(len, 16);
7746 jcc(Assembler::less, L_tail);
7747
7748 // Align buffer to 16 bytes
7749 movl(tmp, buf);
7750 andl(tmp, 0xF);
7751 jccb(Assembler::zero, L_aligned);
7752 subl(tmp, 16);
7753 addl(len, tmp);
7754
7755 align(4);
7756 BIND(L_align_loop);
7757 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7758 update_byte_crc32(crc, rax, table);
7759 increment(buf);
7760 incrementl(tmp);
7761 jccb(Assembler::less, L_align_loop);
7762
7763 BIND(L_aligned);
7764 movl(tmp, len); // save
7765 shrl(len, 4);
7766 jcc(Assembler::zero, L_tail_restore);
7767
7768 // Fold crc into first bytes of vector
7769 movdqa(xmm1, Address(buf, 0));
7770 movdl(rax, xmm1);
7771 xorl(crc, rax);
7772 if (VM_Version::supports_sse4_1()) {
7773 pinsrd(xmm1, crc, 0);
7774 } else {
7775 pinsrw(xmm1, crc, 0);
7776 shrl(crc, 16);
7777 pinsrw(xmm1, crc, 1);
7778 }
7779 addptr(buf, 16);
7780 subl(len, 4); // len > 0
7781 jcc(Assembler::less, L_fold_tail);
7782
7783 movdqa(xmm2, Address(buf, 0));
7784 movdqa(xmm3, Address(buf, 16));
7785 movdqa(xmm4, Address(buf, 32));
7786 addptr(buf, 48);
7787 subl(len, 3);
7788 jcc(Assembler::lessEqual, L_fold_512b);
7789
7790 // Fold total 512 bits of polynomial on each iteration,
7791 // 128 bits per each of 4 parallel streams.
7792 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
7793
7794 align32();
7795 BIND(L_fold_512b_loop);
7796 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
7797 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
7798 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
7799 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
7800 addptr(buf, 64);
7801 subl(len, 4);
7802 jcc(Assembler::greater, L_fold_512b_loop);
7803
7804 // Fold 512 bits to 128 bits.
7805 BIND(L_fold_512b);
7806 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
7807 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
7808 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
7809 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
7810
7811 // Fold the rest of 128 bits data chunks
7812 BIND(L_fold_tail);
7813 addl(len, 3);
7814 jccb(Assembler::lessEqual, L_fold_128b);
7815 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
7816
7817 BIND(L_fold_tail_loop);
7818 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
7819 addptr(buf, 16);
7820 decrementl(len);
7821 jccb(Assembler::greater, L_fold_tail_loop);
7822
7823 // Fold 128 bits in xmm1 down into 32 bits in crc register.
7824 BIND(L_fold_128b);
7825 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
7826 if (UseAVX > 0) {
7827 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
7828 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
7829 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
7830 } else {
7831 movdqa(xmm2, xmm0);
7832 pclmulqdq(xmm2, xmm1, 0x1);
7833 movdqa(xmm3, xmm0);
7834 pand(xmm3, xmm2);
7835 pclmulqdq(xmm0, xmm3, 0x1);
7836 }
7837 psrldq(xmm1, 8);
7838 psrldq(xmm2, 4);
7839 pxor(xmm0, xmm1);
7840 pxor(xmm0, xmm2);
7841
7842 // 8 8-bit folds to compute 32-bit CRC.
7843 for (int j = 0; j < 4; j++) {
7844 fold_8bit_crc32(xmm0, table, xmm1, rax);
7845 }
7846 movdl(crc, xmm0); // mov 32 bits to general register
7847 for (int j = 0; j < 4; j++) {
7848 fold_8bit_crc32(crc, table, rax);
7849 }
7850
7851 BIND(L_tail_restore);
7852 movl(len, tmp); // restore
7853 BIND(L_tail);
7854 andl(len, 0xf);
7855 jccb(Assembler::zero, L_exit);
7856
7857 // Fold the rest of bytes
7858 align(4);
7859 BIND(L_tail_loop);
7860 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7861 update_byte_crc32(crc, rax, table);
7862 increment(buf);
7863 decrementl(len);
7864 jccb(Assembler::greater, L_tail_loop);
7865
7866 BIND(L_exit);
7867 notl(crc); // ~c
7868 }
7869
7870 // Helper function for AVX 512 CRC32
7871 // Fold 512-bit data chunks
7872 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
7873 Register pos, int offset) {
7874 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
7875 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
7876 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
7877 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
7878 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
7879 }
7880
7881 // Helper function for AVX 512 CRC32
7882 // Compute CRC32 for < 256B buffers
7883 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
7884 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
7885 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
7886
7887 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
7888 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
7889 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
7890
7891 // check if there is enough buffer to be able to fold 16B at a time
7892 cmpl(len, 32);
7893 jcc(Assembler::less, L_less_than_32);
7894
7895 // if there is, load the constants
7896 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
7897 movdl(xmm0, crc); // get the initial crc value
7898 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7899 pxor(xmm7, xmm0);
7900
7901 // update the buffer pointer
7902 addl(pos, 16);
7903 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
7904 subl(len, 32);
7905 jmp(L_16B_reduction_loop);
7906
7907 bind(L_less_than_32);
7908 //mov initial crc to the return value. this is necessary for zero - length buffers.
7909 movl(rax, crc);
7910 testl(len, len);
7911 jcc(Assembler::equal, L_cleanup);
7912
7913 movdl(xmm0, crc); //get the initial crc value
7914
7915 cmpl(len, 16);
7916 jcc(Assembler::equal, L_exact_16_left);
7917 jcc(Assembler::less, L_less_than_16_left);
7918
7919 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7920 pxor(xmm7, xmm0); //xor the initial crc value
7921 addl(pos, 16);
7922 subl(len, 16);
7923 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
7924 jmp(L_get_last_two_xmms);
7925
7926 bind(L_less_than_16_left);
7927 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
7928 pxor(xmm1, xmm1);
7929 movptr(tmp1, rsp);
7930 movdqu(Address(tmp1, 0 * 16), xmm1);
7931
7932 cmpl(len, 4);
7933 jcc(Assembler::less, L_only_less_than_4);
7934
7935 //backup the counter value
7936 movl(tmp2, len);
7937 cmpl(len, 8);
7938 jcc(Assembler::less, L_less_than_8_left);
7939
7940 //load 8 Bytes
7941 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
7942 movq(Address(tmp1, 0 * 16), rax);
7943 addptr(tmp1, 8);
7944 subl(len, 8);
7945 addl(pos, 8);
7946
7947 bind(L_less_than_8_left);
7948 cmpl(len, 4);
7949 jcc(Assembler::less, L_less_than_4_left);
7950
7951 //load 4 Bytes
7952 movl(rax, Address(buf, pos, Address::times_1, 0));
7953 movl(Address(tmp1, 0 * 16), rax);
7954 addptr(tmp1, 4);
7955 subl(len, 4);
7956 addl(pos, 4);
7957
7958 bind(L_less_than_4_left);
7959 cmpl(len, 2);
7960 jcc(Assembler::less, L_less_than_2_left);
7961
7962 // load 2 Bytes
7963 movw(rax, Address(buf, pos, Address::times_1, 0));
7964 movl(Address(tmp1, 0 * 16), rax);
7965 addptr(tmp1, 2);
7966 subl(len, 2);
7967 addl(pos, 2);
7968
7969 bind(L_less_than_2_left);
7970 cmpl(len, 1);
7971 jcc(Assembler::less, L_zero_left);
7972
7973 // load 1 Byte
7974 movb(rax, Address(buf, pos, Address::times_1, 0));
7975 movb(Address(tmp1, 0 * 16), rax);
7976
7977 bind(L_zero_left);
7978 movdqu(xmm7, Address(rsp, 0));
7979 pxor(xmm7, xmm0); //xor the initial crc value
7980
7981 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
7982 movdqu(xmm0, Address(rax, tmp2));
7983 pshufb(xmm7, xmm0);
7984 jmp(L_128_done);
7985
7986 bind(L_exact_16_left);
7987 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
7988 pxor(xmm7, xmm0); //xor the initial crc value
7989 jmp(L_128_done);
7990
7991 bind(L_only_less_than_4);
7992 cmpl(len, 3);
7993 jcc(Assembler::less, L_only_less_than_3);
7994
7995 // load 3 Bytes
7996 movb(rax, Address(buf, pos, Address::times_1, 0));
7997 movb(Address(tmp1, 0), rax);
7998
7999 movb(rax, Address(buf, pos, Address::times_1, 1));
8000 movb(Address(tmp1, 1), rax);
8001
8002 movb(rax, Address(buf, pos, Address::times_1, 2));
8003 movb(Address(tmp1, 2), rax);
8004
8005 movdqu(xmm7, Address(rsp, 0));
8006 pxor(xmm7, xmm0); //xor the initial crc value
8007
8008 pslldq(xmm7, 0x5);
8009 jmp(L_barrett);
8010 bind(L_only_less_than_3);
8011 cmpl(len, 2);
8012 jcc(Assembler::less, L_only_less_than_2);
8013
8014 // load 2 Bytes
8015 movb(rax, Address(buf, pos, Address::times_1, 0));
8016 movb(Address(tmp1, 0), rax);
8017
8018 movb(rax, Address(buf, pos, Address::times_1, 1));
8019 movb(Address(tmp1, 1), rax);
8020
8021 movdqu(xmm7, Address(rsp, 0));
8022 pxor(xmm7, xmm0); //xor the initial crc value
8023
8024 pslldq(xmm7, 0x6);
8025 jmp(L_barrett);
8026
8027 bind(L_only_less_than_2);
8028 //load 1 Byte
8029 movb(rax, Address(buf, pos, Address::times_1, 0));
8030 movb(Address(tmp1, 0), rax);
8031
8032 movdqu(xmm7, Address(rsp, 0));
8033 pxor(xmm7, xmm0); //xor the initial crc value
8034
8035 pslldq(xmm7, 0x7);
8036 }
8037
8038 /**
8039 * Compute CRC32 using AVX512 instructions
8040 * param crc register containing existing CRC (32-bit)
8041 * param buf register pointing to input byte buffer (byte*)
8042 * param len register containing number of bytes
8043 * param table address of crc or crc32c table
8044 * param tmp1 scratch register
8045 * param tmp2 scratch register
8046 * return rax result register
8047 *
8048 * This routine is identical for crc32c with the exception of the precomputed constant
8049 * table which will be passed as the table argument. The calculation steps are
8050 * the same for both variants.
8051 */
8052 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8053 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8054
8055 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8056 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8057 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8058 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8059 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8060
8061 const Register pos = r12;
8062 push(r12);
8063 subptr(rsp, 16 * 2 + 8);
8064
8065 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8066 // context for the registers used, where all instructions below are using 128-bit mode
8067 // On EVEX without VL and BW, these instructions will all be AVX.
8068 movl(pos, 0);
8069
8070 // check if smaller than 256B
8071 cmpl(len, 256);
8072 jcc(Assembler::less, L_less_than_256);
8073
8074 // load the initial crc value
8075 movdl(xmm10, crc);
8076
8077 // receive the initial 64B data, xor the initial crc value
8078 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8079 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8080 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8081 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8082
8083 subl(len, 256);
8084 cmpl(len, 256);
8085 jcc(Assembler::less, L_fold_128_B_loop);
8086
8087 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8088 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8089 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8090 subl(len, 256);
8091
8092 bind(L_fold_256_B_loop);
8093 addl(pos, 256);
8094 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8095 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8096 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8097 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8098
8099 subl(len, 256);
8100 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8101
8102 // Fold 256 into 128
8103 addl(pos, 256);
8104 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8105 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8106 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8107
8108 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8109 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8110 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8111
8112 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8113 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8114
8115 addl(len, 128);
8116 jmp(L_fold_128_B_register);
8117
8118 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8119 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8120
8121 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8122 bind(L_fold_128_B_loop);
8123 addl(pos, 128);
8124 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8125 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8126
8127 subl(len, 128);
8128 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8129
8130 addl(pos, 128);
8131
8132 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8133 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8134 bind(L_fold_128_B_register);
8135 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8136 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8137 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8138 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8139 // save last that has no multiplicand
8140 vextracti64x2(xmm7, xmm4, 3);
8141
8142 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8143 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8144 // Needed later in reduction loop
8145 movdqu(xmm10, Address(table, 1 * 16));
8146 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8147 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8148
8149 // Swap 1,0,3,2 - 01 00 11 10
8150 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8151 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8152 vextracti128(xmm5, xmm8, 1);
8153 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8154
8155 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8156 // instead of a cmp instruction, we use the negative flag with the jl instruction
8157 addl(len, 128 - 16);
8158 jcc(Assembler::less, L_final_reduction_for_128);
8159
8160 bind(L_16B_reduction_loop);
8161 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8162 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8163 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8164 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8165 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8166 addl(pos, 16);
8167 subl(len, 16);
8168 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8169
8170 bind(L_final_reduction_for_128);
8171 addl(len, 16);
8172 jcc(Assembler::equal, L_128_done);
8173
8174 bind(L_get_last_two_xmms);
8175 movdqu(xmm2, xmm7);
8176 addl(pos, len);
8177 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8178 subl(pos, len);
8179
8180 // get rid of the extra data that was loaded before
8181 // load the shift constant
8182 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8183 movdqu(xmm0, Address(rax, len));
8184 addl(rax, len);
8185
8186 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8187 //Change mask to 512
8188 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8189 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8190
8191 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8192 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8193 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8194 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8195 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8196
8197 bind(L_128_done);
8198 // compute crc of a 128-bit value
8199 movdqu(xmm10, Address(table, 3 * 16));
8200 movdqu(xmm0, xmm7);
8201
8202 // 64b fold
8203 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8204 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8205 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8206
8207 // 32b fold
8208 movdqu(xmm0, xmm7);
8209 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8210 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8211 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8212 jmp(L_barrett);
8213
8214 bind(L_less_than_256);
8215 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8216
8217 //barrett reduction
8218 bind(L_barrett);
8219 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8220 movdqu(xmm1, xmm7);
8221 movdqu(xmm2, xmm7);
8222 movdqu(xmm10, Address(table, 4 * 16));
8223
8224 pclmulqdq(xmm7, xmm10, 0x0);
8225 pxor(xmm7, xmm2);
8226 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8227 movdqu(xmm2, xmm7);
8228 pclmulqdq(xmm7, xmm10, 0x10);
8229 pxor(xmm7, xmm2);
8230 pxor(xmm7, xmm1);
8231 pextrd(crc, xmm7, 2);
8232
8233 bind(L_cleanup);
8234 addptr(rsp, 16 * 2 + 8);
8235 pop(r12);
8236 }
8237
8238 // S. Gueron / Information Processing Letters 112 (2012) 184
8239 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8240 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8241 // Output: the 64-bit carry-less product of B * CONST
8242 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8243 Register tmp1, Register tmp2, Register tmp3) {
8244 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8245 if (n > 0) {
8246 addq(tmp3, n * 256 * 8);
8247 }
8248 // Q1 = TABLEExt[n][B & 0xFF];
8249 movl(tmp1, in);
8250 andl(tmp1, 0x000000FF);
8251 shll(tmp1, 3);
8252 addq(tmp1, tmp3);
8253 movq(tmp1, Address(tmp1, 0));
8254
8255 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8256 movl(tmp2, in);
8257 shrl(tmp2, 8);
8258 andl(tmp2, 0x000000FF);
8259 shll(tmp2, 3);
8260 addq(tmp2, tmp3);
8261 movq(tmp2, Address(tmp2, 0));
8262
8263 shlq(tmp2, 8);
8264 xorq(tmp1, tmp2);
8265
8266 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8267 movl(tmp2, in);
8268 shrl(tmp2, 16);
8269 andl(tmp2, 0x000000FF);
8270 shll(tmp2, 3);
8271 addq(tmp2, tmp3);
8272 movq(tmp2, Address(tmp2, 0));
8273
8274 shlq(tmp2, 16);
8275 xorq(tmp1, tmp2);
8276
8277 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8278 shrl(in, 24);
8279 andl(in, 0x000000FF);
8280 shll(in, 3);
8281 addq(in, tmp3);
8282 movq(in, Address(in, 0));
8283
8284 shlq(in, 24);
8285 xorq(in, tmp1);
8286 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8287 }
8288
8289 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8290 Register in_out,
8291 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8292 XMMRegister w_xtmp2,
8293 Register tmp1,
8294 Register n_tmp2, Register n_tmp3) {
8295 if (is_pclmulqdq_supported) {
8296 movdl(w_xtmp1, in_out); // modified blindly
8297
8298 movl(tmp1, const_or_pre_comp_const_index);
8299 movdl(w_xtmp2, tmp1);
8300 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8301
8302 movdq(in_out, w_xtmp1);
8303 } else {
8304 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8305 }
8306 }
8307
8308 // Recombination Alternative 2: No bit-reflections
8309 // T1 = (CRC_A * U1) << 1
8310 // T2 = (CRC_B * U2) << 1
8311 // C1 = T1 >> 32
8312 // C2 = T2 >> 32
8313 // T1 = T1 & 0xFFFFFFFF
8314 // T2 = T2 & 0xFFFFFFFF
8315 // T1 = CRC32(0, T1)
8316 // T2 = CRC32(0, T2)
8317 // C1 = C1 ^ T1
8318 // C2 = C2 ^ T2
8319 // CRC = C1 ^ C2 ^ CRC_C
8320 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8321 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8322 Register tmp1, Register tmp2,
8323 Register n_tmp3) {
8324 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8325 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8326 shlq(in_out, 1);
8327 movl(tmp1, in_out);
8328 shrq(in_out, 32);
8329 xorl(tmp2, tmp2);
8330 crc32(tmp2, tmp1, 4);
8331 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8332 shlq(in1, 1);
8333 movl(tmp1, in1);
8334 shrq(in1, 32);
8335 xorl(tmp2, tmp2);
8336 crc32(tmp2, tmp1, 4);
8337 xorl(in1, tmp2);
8338 xorl(in_out, in1);
8339 xorl(in_out, in2);
8340 }
8341
8342 // Set N to predefined value
8343 // Subtract from a length of a buffer
8344 // execute in a loop:
8345 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8346 // for i = 1 to N do
8347 // CRC_A = CRC32(CRC_A, A[i])
8348 // CRC_B = CRC32(CRC_B, B[i])
8349 // CRC_C = CRC32(CRC_C, C[i])
8350 // end for
8351 // Recombine
8352 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8353 Register in_out1, Register in_out2, Register in_out3,
8354 Register tmp1, Register tmp2, Register tmp3,
8355 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8356 Register tmp4, Register tmp5,
8357 Register n_tmp6) {
8358 Label L_processPartitions;
8359 Label L_processPartition;
8360 Label L_exit;
8361
8362 bind(L_processPartitions);
8363 cmpl(in_out1, 3 * size);
8364 jcc(Assembler::less, L_exit);
8365 xorl(tmp1, tmp1);
8366 xorl(tmp2, tmp2);
8367 movq(tmp3, in_out2);
8368 addq(tmp3, size);
8369
8370 bind(L_processPartition);
8371 crc32(in_out3, Address(in_out2, 0), 8);
8372 crc32(tmp1, Address(in_out2, size), 8);
8373 crc32(tmp2, Address(in_out2, size * 2), 8);
8374 addq(in_out2, 8);
8375 cmpq(in_out2, tmp3);
8376 jcc(Assembler::less, L_processPartition);
8377 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8378 w_xtmp1, w_xtmp2, w_xtmp3,
8379 tmp4, tmp5,
8380 n_tmp6);
8381 addq(in_out2, 2 * size);
8382 subl(in_out1, 3 * size);
8383 jmp(L_processPartitions);
8384
8385 bind(L_exit);
8386 }
8387
8388 // Algorithm 2: Pipelined usage of the CRC32 instruction.
8389 // Input: A buffer I of L bytes.
8390 // Output: the CRC32C value of the buffer.
8391 // Notations:
8392 // Write L = 24N + r, with N = floor (L/24).
8393 // r = L mod 24 (0 <= r < 24).
8394 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
8395 // N quadwords, and R consists of r bytes.
8396 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
8397 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
8398 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
8399 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
8400 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
8401 Register tmp1, Register tmp2, Register tmp3,
8402 Register tmp4, Register tmp5, Register tmp6,
8403 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8404 bool is_pclmulqdq_supported) {
8405 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
8406 Label L_wordByWord;
8407 Label L_byteByByteProlog;
8408 Label L_byteByByte;
8409 Label L_exit;
8410
8411 if (is_pclmulqdq_supported ) {
8412 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
8413 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
8414
8415 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
8416 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
8417
8418 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
8419 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
8420 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
8421 } else {
8422 const_or_pre_comp_const_index[0] = 1;
8423 const_or_pre_comp_const_index[1] = 0;
8424
8425 const_or_pre_comp_const_index[2] = 3;
8426 const_or_pre_comp_const_index[3] = 2;
8427
8428 const_or_pre_comp_const_index[4] = 5;
8429 const_or_pre_comp_const_index[5] = 4;
8430 }
8431 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
8432 in2, in1, in_out,
8433 tmp1, tmp2, tmp3,
8434 w_xtmp1, w_xtmp2, w_xtmp3,
8435 tmp4, tmp5,
8436 tmp6);
8437 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
8438 in2, in1, in_out,
8439 tmp1, tmp2, tmp3,
8440 w_xtmp1, w_xtmp2, w_xtmp3,
8441 tmp4, tmp5,
8442 tmp6);
8443 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
8444 in2, in1, in_out,
8445 tmp1, tmp2, tmp3,
8446 w_xtmp1, w_xtmp2, w_xtmp3,
8447 tmp4, tmp5,
8448 tmp6);
8449 movl(tmp1, in2);
8450 andl(tmp1, 0x00000007);
8451 negl(tmp1);
8452 addl(tmp1, in2);
8453 addq(tmp1, in1);
8454
8455 cmpq(in1, tmp1);
8456 jccb(Assembler::greaterEqual, L_byteByByteProlog);
8457 align(16);
8458 BIND(L_wordByWord);
8459 crc32(in_out, Address(in1, 0), 8);
8460 addq(in1, 8);
8461 cmpq(in1, tmp1);
8462 jcc(Assembler::less, L_wordByWord);
8463
8464 BIND(L_byteByByteProlog);
8465 andl(in2, 0x00000007);
8466 movl(tmp2, 1);
8467
8468 cmpl(tmp2, in2);
8469 jccb(Assembler::greater, L_exit);
8470 BIND(L_byteByByte);
8471 crc32(in_out, Address(in1, 0), 1);
8472 incq(in1);
8473 incl(tmp2);
8474 cmpl(tmp2, in2);
8475 jcc(Assembler::lessEqual, L_byteByByte);
8476
8477 BIND(L_exit);
8478 }
8479 #undef BIND
8480 #undef BLOCK_COMMENT
8481
8482 // Compress char[] array to byte[].
8483 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
8484 // Return the array length if every element in array can be encoded,
8485 // otherwise, the index of first non-latin1 (> 0xff) character.
8486 // @IntrinsicCandidate
8487 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
8488 // for (int i = 0; i < len; i++) {
8489 // char c = src[srcOff];
8490 // if (c > 0xff) {
8491 // return i; // return index of non-latin1 char
8492 // }
8493 // dst[dstOff] = (byte)c;
8494 // srcOff++;
8495 // dstOff++;
8496 // }
8497 // return len;
8498 // }
8499 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
8500 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8501 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8502 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
8503 Label copy_chars_loop, done, reset_sp, copy_tail;
8504
8505 // rsi: src
8506 // rdi: dst
8507 // rdx: len
8508 // rcx: tmp5
8509 // rax: result
8510
8511 // rsi holds start addr of source char[] to be compressed
8512 // rdi holds start addr of destination byte[]
8513 // rdx holds length
8514
8515 assert(len != result, "");
8516
8517 // save length for return
8518 movl(result, len);
8519
8520 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
8521 VM_Version::supports_avx512vlbw() &&
8522 VM_Version::supports_bmi2()) {
8523
8524 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
8525
8526 // alignment
8527 Label post_alignment;
8528
8529 // if length of the string is less than 32, handle it the old fashioned way
8530 testl(len, -32);
8531 jcc(Assembler::zero, below_threshold);
8532
8533 // First check whether a character is compressible ( <= 0xFF).
8534 // Create mask to test for Unicode chars inside zmm vector
8535 movl(tmp5, 0x00FF);
8536 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
8537
8538 testl(len, -64);
8539 jccb(Assembler::zero, post_alignment);
8540
8541 movl(tmp5, dst);
8542 andl(tmp5, (32 - 1));
8543 negl(tmp5);
8544 andl(tmp5, (32 - 1));
8545
8546 // bail out when there is nothing to be done
8547 testl(tmp5, 0xFFFFFFFF);
8548 jccb(Assembler::zero, post_alignment);
8549
8550 // ~(~0 << len), where len is the # of remaining elements to process
8551 movl(len, 0xFFFFFFFF);
8552 shlxl(len, len, tmp5);
8553 notl(len);
8554 kmovdl(mask2, len);
8555 movl(len, result);
8556
8557 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
8558 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
8559 ktestd(mask1, mask2);
8560 jcc(Assembler::carryClear, copy_tail);
8561
8562 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
8563
8564 addptr(src, tmp5);
8565 addptr(src, tmp5);
8566 addptr(dst, tmp5);
8567 subl(len, tmp5);
8568
8569 bind(post_alignment);
8570 // end of alignment
8571
8572 movl(tmp5, len);
8573 andl(tmp5, (32 - 1)); // tail count (in chars)
8574 andl(len, ~(32 - 1)); // vector count (in chars)
8575 jccb(Assembler::zero, copy_loop_tail);
8576
8577 lea(src, Address(src, len, Address::times_2));
8578 lea(dst, Address(dst, len, Address::times_1));
8579 negptr(len);
8580
8581 bind(copy_32_loop);
8582 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
8583 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
8584 kortestdl(mask1, mask1);
8585 jccb(Assembler::carryClear, reset_for_copy_tail);
8586
8587 // All elements in current processed chunk are valid candidates for
8588 // compression. Write a truncated byte elements to the memory.
8589 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
8590 addptr(len, 32);
8591 jccb(Assembler::notZero, copy_32_loop);
8592
8593 bind(copy_loop_tail);
8594 // bail out when there is nothing to be done
8595 testl(tmp5, 0xFFFFFFFF);
8596 jcc(Assembler::zero, done);
8597
8598 movl(len, tmp5);
8599
8600 // ~(~0 << len), where len is the # of remaining elements to process
8601 movl(tmp5, 0xFFFFFFFF);
8602 shlxl(tmp5, tmp5, len);
8603 notl(tmp5);
8604
8605 kmovdl(mask2, tmp5);
8606
8607 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
8608 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
8609 ktestd(mask1, mask2);
8610 jcc(Assembler::carryClear, copy_tail);
8611
8612 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
8613 jmp(done);
8614
8615 bind(reset_for_copy_tail);
8616 lea(src, Address(src, tmp5, Address::times_2));
8617 lea(dst, Address(dst, tmp5, Address::times_1));
8618 subptr(len, tmp5);
8619 jmp(copy_chars_loop);
8620
8621 bind(below_threshold);
8622 }
8623
8624 if (UseSSE42Intrinsics) {
8625 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
8626
8627 // vectored compression
8628 testl(len, 0xfffffff8);
8629 jcc(Assembler::zero, copy_tail);
8630
8631 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
8632 movdl(tmp1Reg, tmp5);
8633 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
8634
8635 andl(len, 0xfffffff0);
8636 jccb(Assembler::zero, copy_16);
8637
8638 // compress 16 chars per iter
8639 pxor(tmp4Reg, tmp4Reg);
8640
8641 lea(src, Address(src, len, Address::times_2));
8642 lea(dst, Address(dst, len, Address::times_1));
8643 negptr(len);
8644
8645 bind(copy_32_loop);
8646 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
8647 por(tmp4Reg, tmp2Reg);
8648 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
8649 por(tmp4Reg, tmp3Reg);
8650 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
8651 jccb(Assembler::notZero, reset_for_copy_tail);
8652 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
8653 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
8654 addptr(len, 16);
8655 jccb(Assembler::notZero, copy_32_loop);
8656
8657 // compress next vector of 8 chars (if any)
8658 bind(copy_16);
8659 // len = 0
8660 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
8661 jccb(Assembler::zero, copy_tail_sse);
8662
8663 pxor(tmp3Reg, tmp3Reg);
8664
8665 movdqu(tmp2Reg, Address(src, 0));
8666 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8667 jccb(Assembler::notZero, reset_for_copy_tail);
8668 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
8669 movq(Address(dst, 0), tmp2Reg);
8670 addptr(src, 16);
8671 addptr(dst, 8);
8672 jmpb(copy_tail_sse);
8673
8674 bind(reset_for_copy_tail);
8675 movl(tmp5, result);
8676 andl(tmp5, 0x0000000f);
8677 lea(src, Address(src, tmp5, Address::times_2));
8678 lea(dst, Address(dst, tmp5, Address::times_1));
8679 subptr(len, tmp5);
8680 jmpb(copy_chars_loop);
8681
8682 bind(copy_tail_sse);
8683 movl(len, result);
8684 andl(len, 0x00000007); // tail count (in chars)
8685 }
8686 // compress 1 char per iter
8687 bind(copy_tail);
8688 testl(len, len);
8689 jccb(Assembler::zero, done);
8690 lea(src, Address(src, len, Address::times_2));
8691 lea(dst, Address(dst, len, Address::times_1));
8692 negptr(len);
8693
8694 bind(copy_chars_loop);
8695 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
8696 testl(tmp5, 0xff00); // check if Unicode char
8697 jccb(Assembler::notZero, reset_sp);
8698 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
8699 increment(len);
8700 jccb(Assembler::notZero, copy_chars_loop);
8701
8702 // add len then return (len will be zero if compress succeeded, otherwise negative)
8703 bind(reset_sp);
8704 addl(result, len);
8705
8706 bind(done);
8707 }
8708
8709 // Inflate byte[] array to char[].
8710 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
8711 // @IntrinsicCandidate
8712 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
8713 // for (int i = 0; i < len; i++) {
8714 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
8715 // }
8716 // }
8717 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
8718 XMMRegister tmp1, Register tmp2, KRegister mask) {
8719 Label copy_chars_loop, done, below_threshold, avx3_threshold;
8720 // rsi: src
8721 // rdi: dst
8722 // rdx: len
8723 // rcx: tmp2
8724
8725 // rsi holds start addr of source byte[] to be inflated
8726 // rdi holds start addr of destination char[]
8727 // rdx holds length
8728 assert_different_registers(src, dst, len, tmp2);
8729 movl(tmp2, len);
8730 if ((UseAVX > 2) && // AVX512
8731 VM_Version::supports_avx512vlbw() &&
8732 VM_Version::supports_bmi2()) {
8733
8734 Label copy_32_loop, copy_tail;
8735 Register tmp3_aliased = len;
8736
8737 // if length of the string is less than 16, handle it in an old fashioned way
8738 testl(len, -16);
8739 jcc(Assembler::zero, below_threshold);
8740
8741 testl(len, -1 * AVX3Threshold);
8742 jcc(Assembler::zero, avx3_threshold);
8743
8744 // In order to use only one arithmetic operation for the main loop we use
8745 // this pre-calculation
8746 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
8747 andl(len, -32); // vector count
8748 jccb(Assembler::zero, copy_tail);
8749
8750 lea(src, Address(src, len, Address::times_1));
8751 lea(dst, Address(dst, len, Address::times_2));
8752 negptr(len);
8753
8754
8755 // inflate 32 chars per iter
8756 bind(copy_32_loop);
8757 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
8758 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
8759 addptr(len, 32);
8760 jcc(Assembler::notZero, copy_32_loop);
8761
8762 bind(copy_tail);
8763 // bail out when there is nothing to be done
8764 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
8765 jcc(Assembler::zero, done);
8766
8767 // ~(~0 << length), where length is the # of remaining elements to process
8768 movl(tmp3_aliased, -1);
8769 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
8770 notl(tmp3_aliased);
8771 kmovdl(mask, tmp3_aliased);
8772 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
8773 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
8774
8775 jmp(done);
8776 bind(avx3_threshold);
8777 }
8778 if (UseSSE42Intrinsics) {
8779 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
8780
8781 if (UseAVX > 1) {
8782 andl(tmp2, (16 - 1));
8783 andl(len, -16);
8784 jccb(Assembler::zero, copy_new_tail);
8785 } else {
8786 andl(tmp2, 0x00000007); // tail count (in chars)
8787 andl(len, 0xfffffff8); // vector count (in chars)
8788 jccb(Assembler::zero, copy_tail);
8789 }
8790
8791 // vectored inflation
8792 lea(src, Address(src, len, Address::times_1));
8793 lea(dst, Address(dst, len, Address::times_2));
8794 negptr(len);
8795
8796 if (UseAVX > 1) {
8797 bind(copy_16_loop);
8798 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
8799 vmovdqu(Address(dst, len, Address::times_2), tmp1);
8800 addptr(len, 16);
8801 jcc(Assembler::notZero, copy_16_loop);
8802
8803 bind(below_threshold);
8804 bind(copy_new_tail);
8805 movl(len, tmp2);
8806 andl(tmp2, 0x00000007);
8807 andl(len, 0xFFFFFFF8);
8808 jccb(Assembler::zero, copy_tail);
8809
8810 pmovzxbw(tmp1, Address(src, 0));
8811 movdqu(Address(dst, 0), tmp1);
8812 addptr(src, 8);
8813 addptr(dst, 2 * 8);
8814
8815 jmp(copy_tail, true);
8816 }
8817
8818 // inflate 8 chars per iter
8819 bind(copy_8_loop);
8820 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
8821 movdqu(Address(dst, len, Address::times_2), tmp1);
8822 addptr(len, 8);
8823 jcc(Assembler::notZero, copy_8_loop);
8824
8825 bind(copy_tail);
8826 movl(len, tmp2);
8827
8828 cmpl(len, 4);
8829 jccb(Assembler::less, copy_bytes);
8830
8831 movdl(tmp1, Address(src, 0)); // load 4 byte chars
8832 pmovzxbw(tmp1, tmp1);
8833 movq(Address(dst, 0), tmp1);
8834 subptr(len, 4);
8835 addptr(src, 4);
8836 addptr(dst, 8);
8837
8838 bind(copy_bytes);
8839 } else {
8840 bind(below_threshold);
8841 }
8842
8843 testl(len, len);
8844 jccb(Assembler::zero, done);
8845 lea(src, Address(src, len, Address::times_1));
8846 lea(dst, Address(dst, len, Address::times_2));
8847 negptr(len);
8848
8849 // inflate 1 char per iter
8850 bind(copy_chars_loop);
8851 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
8852 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
8853 increment(len);
8854 jcc(Assembler::notZero, copy_chars_loop);
8855
8856 bind(done);
8857 }
8858
8859 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
8860 switch(type) {
8861 case T_BYTE:
8862 case T_BOOLEAN:
8863 evmovdqub(dst, kmask, src, merge, vector_len);
8864 break;
8865 case T_CHAR:
8866 case T_SHORT:
8867 evmovdquw(dst, kmask, src, merge, vector_len);
8868 break;
8869 case T_INT:
8870 case T_FLOAT:
8871 evmovdqul(dst, kmask, src, merge, vector_len);
8872 break;
8873 case T_LONG:
8874 case T_DOUBLE:
8875 evmovdquq(dst, kmask, src, merge, vector_len);
8876 break;
8877 default:
8878 fatal("Unexpected type argument %s", type2name(type));
8879 break;
8880 }
8881 }
8882
8883
8884 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
8885 switch(type) {
8886 case T_BYTE:
8887 case T_BOOLEAN:
8888 evmovdqub(dst, kmask, src, merge, vector_len);
8889 break;
8890 case T_CHAR:
8891 case T_SHORT:
8892 evmovdquw(dst, kmask, src, merge, vector_len);
8893 break;
8894 case T_INT:
8895 case T_FLOAT:
8896 evmovdqul(dst, kmask, src, merge, vector_len);
8897 break;
8898 case T_LONG:
8899 case T_DOUBLE:
8900 evmovdquq(dst, kmask, src, merge, vector_len);
8901 break;
8902 default:
8903 fatal("Unexpected type argument %s", type2name(type));
8904 break;
8905 }
8906 }
8907
8908 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
8909 switch(type) {
8910 case T_BYTE:
8911 case T_BOOLEAN:
8912 evmovdqub(dst, kmask, src, merge, vector_len);
8913 break;
8914 case T_CHAR:
8915 case T_SHORT:
8916 evmovdquw(dst, kmask, src, merge, vector_len);
8917 break;
8918 case T_INT:
8919 case T_FLOAT:
8920 evmovdqul(dst, kmask, src, merge, vector_len);
8921 break;
8922 case T_LONG:
8923 case T_DOUBLE:
8924 evmovdquq(dst, kmask, src, merge, vector_len);
8925 break;
8926 default:
8927 fatal("Unexpected type argument %s", type2name(type));
8928 break;
8929 }
8930 }
8931
8932 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
8933 switch(masklen) {
8934 case 2:
8935 knotbl(dst, src);
8936 movl(rtmp, 3);
8937 kmovbl(ktmp, rtmp);
8938 kandbl(dst, ktmp, dst);
8939 break;
8940 case 4:
8941 knotbl(dst, src);
8942 movl(rtmp, 15);
8943 kmovbl(ktmp, rtmp);
8944 kandbl(dst, ktmp, dst);
8945 break;
8946 case 8:
8947 knotbl(dst, src);
8948 break;
8949 case 16:
8950 knotwl(dst, src);
8951 break;
8952 case 32:
8953 knotdl(dst, src);
8954 break;
8955 case 64:
8956 knotql(dst, src);
8957 break;
8958 default:
8959 fatal("Unexpected vector length %d", masklen);
8960 break;
8961 }
8962 }
8963
8964 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8965 switch(type) {
8966 case T_BOOLEAN:
8967 case T_BYTE:
8968 kandbl(dst, src1, src2);
8969 break;
8970 case T_CHAR:
8971 case T_SHORT:
8972 kandwl(dst, src1, src2);
8973 break;
8974 case T_INT:
8975 case T_FLOAT:
8976 kanddl(dst, src1, src2);
8977 break;
8978 case T_LONG:
8979 case T_DOUBLE:
8980 kandql(dst, src1, src2);
8981 break;
8982 default:
8983 fatal("Unexpected type argument %s", type2name(type));
8984 break;
8985 }
8986 }
8987
8988 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8989 switch(type) {
8990 case T_BOOLEAN:
8991 case T_BYTE:
8992 korbl(dst, src1, src2);
8993 break;
8994 case T_CHAR:
8995 case T_SHORT:
8996 korwl(dst, src1, src2);
8997 break;
8998 case T_INT:
8999 case T_FLOAT:
9000 kordl(dst, src1, src2);
9001 break;
9002 case T_LONG:
9003 case T_DOUBLE:
9004 korql(dst, src1, src2);
9005 break;
9006 default:
9007 fatal("Unexpected type argument %s", type2name(type));
9008 break;
9009 }
9010 }
9011
9012 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9013 switch(type) {
9014 case T_BOOLEAN:
9015 case T_BYTE:
9016 kxorbl(dst, src1, src2);
9017 break;
9018 case T_CHAR:
9019 case T_SHORT:
9020 kxorwl(dst, src1, src2);
9021 break;
9022 case T_INT:
9023 case T_FLOAT:
9024 kxordl(dst, src1, src2);
9025 break;
9026 case T_LONG:
9027 case T_DOUBLE:
9028 kxorql(dst, src1, src2);
9029 break;
9030 default:
9031 fatal("Unexpected type argument %s", type2name(type));
9032 break;
9033 }
9034 }
9035
9036 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9037 switch(type) {
9038 case T_BOOLEAN:
9039 case T_BYTE:
9040 evpermb(dst, mask, nds, src, merge, vector_len); break;
9041 case T_CHAR:
9042 case T_SHORT:
9043 evpermw(dst, mask, nds, src, merge, vector_len); break;
9044 case T_INT:
9045 case T_FLOAT:
9046 evpermd(dst, mask, nds, src, merge, vector_len); break;
9047 case T_LONG:
9048 case T_DOUBLE:
9049 evpermq(dst, mask, nds, src, merge, vector_len); break;
9050 default:
9051 fatal("Unexpected type argument %s", type2name(type)); break;
9052 }
9053 }
9054
9055 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9056 switch(type) {
9057 case T_BOOLEAN:
9058 case T_BYTE:
9059 evpermb(dst, mask, nds, src, merge, vector_len); break;
9060 case T_CHAR:
9061 case T_SHORT:
9062 evpermw(dst, mask, nds, src, merge, vector_len); break;
9063 case T_INT:
9064 case T_FLOAT:
9065 evpermd(dst, mask, nds, src, merge, vector_len); break;
9066 case T_LONG:
9067 case T_DOUBLE:
9068 evpermq(dst, mask, nds, src, merge, vector_len); break;
9069 default:
9070 fatal("Unexpected type argument %s", type2name(type)); break;
9071 }
9072 }
9073
9074 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9075 switch(type) {
9076 case T_BYTE:
9077 evpminub(dst, mask, nds, src, merge, vector_len); break;
9078 case T_SHORT:
9079 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9080 case T_INT:
9081 evpminud(dst, mask, nds, src, merge, vector_len); break;
9082 case T_LONG:
9083 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9084 default:
9085 fatal("Unexpected type argument %s", type2name(type)); break;
9086 }
9087 }
9088
9089 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9090 switch(type) {
9091 case T_BYTE:
9092 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9093 case T_SHORT:
9094 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9095 case T_INT:
9096 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9097 case T_LONG:
9098 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9099 default:
9100 fatal("Unexpected type argument %s", type2name(type)); break;
9101 }
9102 }
9103
9104 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9105 switch(type) {
9106 case T_BYTE:
9107 evpminub(dst, mask, nds, src, merge, vector_len); break;
9108 case T_SHORT:
9109 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9110 case T_INT:
9111 evpminud(dst, mask, nds, src, merge, vector_len); break;
9112 case T_LONG:
9113 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9114 default:
9115 fatal("Unexpected type argument %s", type2name(type)); break;
9116 }
9117 }
9118
9119 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9120 switch(type) {
9121 case T_BYTE:
9122 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9123 case T_SHORT:
9124 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9125 case T_INT:
9126 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9127 case T_LONG:
9128 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9129 default:
9130 fatal("Unexpected type argument %s", type2name(type)); break;
9131 }
9132 }
9133
9134 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9135 switch(type) {
9136 case T_BYTE:
9137 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9138 case T_SHORT:
9139 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9140 case T_INT:
9141 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9142 case T_LONG:
9143 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9144 case T_FLOAT:
9145 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9146 case T_DOUBLE:
9147 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9148 default:
9149 fatal("Unexpected type argument %s", type2name(type)); break;
9150 }
9151 }
9152
9153 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9154 switch(type) {
9155 case T_BYTE:
9156 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9157 case T_SHORT:
9158 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9159 case T_INT:
9160 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9161 case T_LONG:
9162 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9163 case T_FLOAT:
9164 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9165 case T_DOUBLE:
9166 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9167 default:
9168 fatal("Unexpected type argument %s", type2name(type)); break;
9169 }
9170 }
9171
9172 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9173 switch(type) {
9174 case T_BYTE:
9175 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9176 case T_SHORT:
9177 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9178 case T_INT:
9179 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9180 case T_LONG:
9181 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9182 case T_FLOAT:
9183 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9184 case T_DOUBLE:
9185 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9186 default:
9187 fatal("Unexpected type argument %s", type2name(type)); break;
9188 }
9189 }
9190
9191 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9192 switch(type) {
9193 case T_BYTE:
9194 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9195 case T_SHORT:
9196 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9197 case T_INT:
9198 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9199 case T_LONG:
9200 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9201 case T_FLOAT:
9202 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9203 case T_DOUBLE:
9204 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9205 default:
9206 fatal("Unexpected type argument %s", type2name(type)); break;
9207 }
9208 }
9209
9210 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9211 switch(type) {
9212 case T_INT:
9213 evpxord(dst, mask, nds, src, merge, vector_len); break;
9214 case T_LONG:
9215 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9216 default:
9217 fatal("Unexpected type argument %s", type2name(type)); break;
9218 }
9219 }
9220
9221 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9222 switch(type) {
9223 case T_INT:
9224 evpxord(dst, mask, nds, src, merge, vector_len); break;
9225 case T_LONG:
9226 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9227 default:
9228 fatal("Unexpected type argument %s", type2name(type)); break;
9229 }
9230 }
9231
9232 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9233 switch(type) {
9234 case T_INT:
9235 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9236 case T_LONG:
9237 evporq(dst, mask, nds, src, merge, vector_len); break;
9238 default:
9239 fatal("Unexpected type argument %s", type2name(type)); break;
9240 }
9241 }
9242
9243 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9244 switch(type) {
9245 case T_INT:
9246 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9247 case T_LONG:
9248 evporq(dst, mask, nds, src, merge, vector_len); break;
9249 default:
9250 fatal("Unexpected type argument %s", type2name(type)); break;
9251 }
9252 }
9253
9254 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9255 switch(type) {
9256 case T_INT:
9257 evpandd(dst, mask, nds, src, merge, vector_len); break;
9258 case T_LONG:
9259 evpandq(dst, mask, nds, src, merge, vector_len); break;
9260 default:
9261 fatal("Unexpected type argument %s", type2name(type)); break;
9262 }
9263 }
9264
9265 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9266 switch(type) {
9267 case T_INT:
9268 evpandd(dst, mask, nds, src, merge, vector_len); break;
9269 case T_LONG:
9270 evpandq(dst, mask, nds, src, merge, vector_len); break;
9271 default:
9272 fatal("Unexpected type argument %s", type2name(type)); break;
9273 }
9274 }
9275
9276 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
9277 switch(masklen) {
9278 case 8:
9279 kortestbl(src1, src2);
9280 break;
9281 case 16:
9282 kortestwl(src1, src2);
9283 break;
9284 case 32:
9285 kortestdl(src1, src2);
9286 break;
9287 case 64:
9288 kortestql(src1, src2);
9289 break;
9290 default:
9291 fatal("Unexpected mask length %d", masklen);
9292 break;
9293 }
9294 }
9295
9296
9297 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
9298 switch(masklen) {
9299 case 8:
9300 ktestbl(src1, src2);
9301 break;
9302 case 16:
9303 ktestwl(src1, src2);
9304 break;
9305 case 32:
9306 ktestdl(src1, src2);
9307 break;
9308 case 64:
9309 ktestql(src1, src2);
9310 break;
9311 default:
9312 fatal("Unexpected mask length %d", masklen);
9313 break;
9314 }
9315 }
9316
9317 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9318 switch(type) {
9319 case T_INT:
9320 evprold(dst, mask, src, shift, merge, vlen_enc); break;
9321 case T_LONG:
9322 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
9323 default:
9324 fatal("Unexpected type argument %s", type2name(type)); break;
9325 break;
9326 }
9327 }
9328
9329 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9330 switch(type) {
9331 case T_INT:
9332 evprord(dst, mask, src, shift, merge, vlen_enc); break;
9333 case T_LONG:
9334 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
9335 default:
9336 fatal("Unexpected type argument %s", type2name(type)); break;
9337 }
9338 }
9339
9340 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
9341 switch(type) {
9342 case T_INT:
9343 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
9344 case T_LONG:
9345 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
9346 default:
9347 fatal("Unexpected type argument %s", type2name(type)); break;
9348 }
9349 }
9350
9351 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
9352 switch(type) {
9353 case T_INT:
9354 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
9355 case T_LONG:
9356 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
9357 default:
9358 fatal("Unexpected type argument %s", type2name(type)); break;
9359 }
9360 }
9361
9362 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9363 assert(rscratch != noreg || always_reachable(src), "missing");
9364
9365 if (reachable(src)) {
9366 evpandq(dst, nds, as_Address(src), vector_len);
9367 } else {
9368 lea(rscratch, src);
9369 evpandq(dst, nds, Address(rscratch, 0), vector_len);
9370 }
9371 }
9372
9373 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
9374 assert(rscratch != noreg || always_reachable(src), "missing");
9375
9376 if (reachable(src)) {
9377 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
9378 } else {
9379 lea(rscratch, src);
9380 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
9381 }
9382 }
9383
9384 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9385 assert(rscratch != noreg || always_reachable(src), "missing");
9386
9387 if (reachable(src)) {
9388 evporq(dst, nds, as_Address(src), vector_len);
9389 } else {
9390 lea(rscratch, src);
9391 evporq(dst, nds, Address(rscratch, 0), vector_len);
9392 }
9393 }
9394
9395 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9396 assert(rscratch != noreg || always_reachable(src), "missing");
9397
9398 if (reachable(src)) {
9399 vpshufb(dst, nds, as_Address(src), vector_len);
9400 } else {
9401 lea(rscratch, src);
9402 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
9403 }
9404 }
9405
9406 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9407 assert(rscratch != noreg || always_reachable(src), "missing");
9408
9409 if (reachable(src)) {
9410 Assembler::vpor(dst, nds, as_Address(src), vector_len);
9411 } else {
9412 lea(rscratch, src);
9413 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
9414 }
9415 }
9416
9417 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
9418 assert(rscratch != noreg || always_reachable(src3), "missing");
9419
9420 if (reachable(src3)) {
9421 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
9422 } else {
9423 lea(rscratch, src3);
9424 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
9425 }
9426 }
9427
9428 #if COMPILER2_OR_JVMCI
9429
9430 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
9431 Register length, Register temp, int vec_enc) {
9432 // Computing mask for predicated vector store.
9433 movptr(temp, -1);
9434 bzhiq(temp, temp, length);
9435 kmov(mask, temp);
9436 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
9437 }
9438
9439 // Set memory operation for length "less than" 64 bytes.
9440 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
9441 XMMRegister xmm, KRegister mask, Register length,
9442 Register temp, bool use64byteVector) {
9443 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9444 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
9445 if (!use64byteVector) {
9446 fill32(dst, disp, xmm);
9447 subptr(length, 32 >> shift);
9448 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
9449 } else {
9450 assert(MaxVectorSize == 64, "vector length != 64");
9451 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
9452 }
9453 }
9454
9455
9456 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
9457 XMMRegister xmm, KRegister mask, Register length,
9458 Register temp) {
9459 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9460 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
9461 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
9462 }
9463
9464
9465 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
9466 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9467 vmovdqu(dst, xmm);
9468 }
9469
9470 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
9471 fill32(Address(dst, disp), xmm);
9472 }
9473
9474 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
9475 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9476 if (!use64byteVector) {
9477 fill32(dst, xmm);
9478 fill32(dst.plus_disp(32), xmm);
9479 } else {
9480 evmovdquq(dst, xmm, Assembler::AVX_512bit);
9481 }
9482 }
9483
9484 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
9485 fill64(Address(dst, disp), xmm, use64byteVector);
9486 }
9487
9488 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
9489 Register count, Register rtmp, XMMRegister xtmp) {
9490 Label L_exit;
9491 Label L_fill_start;
9492 Label L_fill_64_bytes;
9493 Label L_fill_96_bytes;
9494 Label L_fill_128_bytes;
9495 Label L_fill_128_bytes_loop;
9496 Label L_fill_128_loop_header;
9497 Label L_fill_128_bytes_loop_header;
9498 Label L_fill_128_bytes_loop_pre_header;
9499 Label L_fill_zmm_sequence;
9500
9501 int shift = -1;
9502 switch(type) {
9503 case T_BYTE: shift = 0;
9504 break;
9505 case T_SHORT: shift = 1;
9506 break;
9507 case T_INT: shift = 2;
9508 break;
9509 /* Uncomment when LONG fill stubs are supported.
9510 case T_LONG: shift = 3;
9511 break;
9512 */
9513 default:
9514 fatal("Unhandled type: %s\n", type2name(type));
9515 }
9516
9517 if ((CopyAVX3Threshold != 0) || (MaxVectorSize == 32)) {
9518
9519 if (MaxVectorSize == 64) {
9520 cmpq(count, CopyAVX3Threshold >> shift);
9521 jcc(Assembler::greater, L_fill_zmm_sequence);
9522 }
9523
9524 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
9525
9526 bind(L_fill_start);
9527
9528 cmpq(count, 32 >> shift);
9529 jccb(Assembler::greater, L_fill_64_bytes);
9530 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
9531 jmp(L_exit);
9532
9533 bind(L_fill_64_bytes);
9534 cmpq(count, 64 >> shift);
9535 jccb(Assembler::greater, L_fill_96_bytes);
9536 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
9537 jmp(L_exit);
9538
9539 bind(L_fill_96_bytes);
9540 cmpq(count, 96 >> shift);
9541 jccb(Assembler::greater, L_fill_128_bytes);
9542 fill64(to, 0, xtmp);
9543 subq(count, 64 >> shift);
9544 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
9545 jmp(L_exit);
9546
9547 bind(L_fill_128_bytes);
9548 cmpq(count, 128 >> shift);
9549 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
9550 fill64(to, 0, xtmp);
9551 fill32(to, 64, xtmp);
9552 subq(count, 96 >> shift);
9553 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
9554 jmp(L_exit);
9555
9556 bind(L_fill_128_bytes_loop_pre_header);
9557 {
9558 mov(rtmp, to);
9559 andq(rtmp, 31);
9560 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
9561 negq(rtmp);
9562 addq(rtmp, 32);
9563 mov64(r8, -1L);
9564 bzhiq(r8, r8, rtmp);
9565 kmovql(k2, r8);
9566 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
9567 addq(to, rtmp);
9568 shrq(rtmp, shift);
9569 subq(count, rtmp);
9570 }
9571
9572 cmpq(count, 128 >> shift);
9573 jcc(Assembler::less, L_fill_start);
9574
9575 bind(L_fill_128_bytes_loop_header);
9576 subq(count, 128 >> shift);
9577
9578 align32();
9579 bind(L_fill_128_bytes_loop);
9580 fill64(to, 0, xtmp);
9581 fill64(to, 64, xtmp);
9582 addq(to, 128);
9583 subq(count, 128 >> shift);
9584 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
9585
9586 addq(count, 128 >> shift);
9587 jcc(Assembler::zero, L_exit);
9588 jmp(L_fill_start);
9589 }
9590
9591 if (MaxVectorSize == 64) {
9592 // Sequence using 64 byte ZMM register.
9593 Label L_fill_128_bytes_zmm;
9594 Label L_fill_192_bytes_zmm;
9595 Label L_fill_192_bytes_loop_zmm;
9596 Label L_fill_192_bytes_loop_header_zmm;
9597 Label L_fill_192_bytes_loop_pre_header_zmm;
9598 Label L_fill_start_zmm_sequence;
9599
9600 bind(L_fill_zmm_sequence);
9601 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
9602
9603 bind(L_fill_start_zmm_sequence);
9604 cmpq(count, 64 >> shift);
9605 jccb(Assembler::greater, L_fill_128_bytes_zmm);
9606 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
9607 jmp(L_exit);
9608
9609 bind(L_fill_128_bytes_zmm);
9610 cmpq(count, 128 >> shift);
9611 jccb(Assembler::greater, L_fill_192_bytes_zmm);
9612 fill64(to, 0, xtmp, true);
9613 subq(count, 64 >> shift);
9614 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
9615 jmp(L_exit);
9616
9617 bind(L_fill_192_bytes_zmm);
9618 cmpq(count, 192 >> shift);
9619 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
9620 fill64(to, 0, xtmp, true);
9621 fill64(to, 64, xtmp, true);
9622 subq(count, 128 >> shift);
9623 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
9624 jmp(L_exit);
9625
9626 bind(L_fill_192_bytes_loop_pre_header_zmm);
9627 {
9628 movq(rtmp, to);
9629 andq(rtmp, 63);
9630 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
9631 negq(rtmp);
9632 addq(rtmp, 64);
9633 mov64(r8, -1L);
9634 bzhiq(r8, r8, rtmp);
9635 kmovql(k2, r8);
9636 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
9637 addq(to, rtmp);
9638 shrq(rtmp, shift);
9639 subq(count, rtmp);
9640 }
9641
9642 cmpq(count, 192 >> shift);
9643 jcc(Assembler::less, L_fill_start_zmm_sequence);
9644
9645 bind(L_fill_192_bytes_loop_header_zmm);
9646 subq(count, 192 >> shift);
9647
9648 align32();
9649 bind(L_fill_192_bytes_loop_zmm);
9650 fill64(to, 0, xtmp, true);
9651 fill64(to, 64, xtmp, true);
9652 fill64(to, 128, xtmp, true);
9653 addq(to, 192);
9654 subq(count, 192 >> shift);
9655 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
9656
9657 addq(count, 192 >> shift);
9658 jcc(Assembler::zero, L_exit);
9659 jmp(L_fill_start_zmm_sequence);
9660 }
9661 bind(L_exit);
9662 }
9663 #endif //COMPILER2_OR_JVMCI
9664
9665
9666 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
9667 Label done;
9668 cvttss2sil(dst, src);
9669 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
9670 cmpl(dst, 0x80000000); // float_sign_flip
9671 jccb(Assembler::notEqual, done);
9672 subptr(rsp, 8);
9673 movflt(Address(rsp, 0), src);
9674 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9675 pop(dst);
9676 bind(done);
9677 }
9678
9679 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
9680 Label done;
9681 cvttsd2sil(dst, src);
9682 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
9683 cmpl(dst, 0x80000000); // float_sign_flip
9684 jccb(Assembler::notEqual, done);
9685 subptr(rsp, 8);
9686 movdbl(Address(rsp, 0), src);
9687 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
9688 pop(dst);
9689 bind(done);
9690 }
9691
9692 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
9693 Label done;
9694 cvttss2siq(dst, src);
9695 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9696 jccb(Assembler::notEqual, done);
9697 subptr(rsp, 8);
9698 movflt(Address(rsp, 0), src);
9699 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
9700 pop(dst);
9701 bind(done);
9702 }
9703
9704 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
9705 // Following code is line by line assembly translation rounding algorithm.
9706 // Please refer to java.lang.Math.round(float) algorithm for details.
9707 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
9708 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
9709 const int32_t FloatConsts_EXP_BIAS = 127;
9710 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
9711 const int32_t MINUS_32 = 0xFFFFFFE0;
9712 Label L_special_case, L_block1, L_exit;
9713 movl(rtmp, FloatConsts_EXP_BIT_MASK);
9714 movdl(dst, src);
9715 andl(dst, rtmp);
9716 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
9717 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
9718 subl(rtmp, dst);
9719 movl(rcx, rtmp);
9720 movl(dst, MINUS_32);
9721 testl(rtmp, dst);
9722 jccb(Assembler::notEqual, L_special_case);
9723 movdl(dst, src);
9724 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
9725 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
9726 movdl(rtmp, src);
9727 testl(rtmp, rtmp);
9728 jccb(Assembler::greaterEqual, L_block1);
9729 negl(dst);
9730 bind(L_block1);
9731 sarl(dst);
9732 addl(dst, 0x1);
9733 sarl(dst, 0x1);
9734 jmp(L_exit);
9735 bind(L_special_case);
9736 convert_f2i(dst, src);
9737 bind(L_exit);
9738 }
9739
9740 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
9741 // Following code is line by line assembly translation rounding algorithm.
9742 // Please refer to java.lang.Math.round(double) algorithm for details.
9743 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
9744 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
9745 const int64_t DoubleConsts_EXP_BIAS = 1023;
9746 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
9747 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
9748 Label L_special_case, L_block1, L_exit;
9749 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
9750 movq(dst, src);
9751 andq(dst, rtmp);
9752 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
9753 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
9754 subq(rtmp, dst);
9755 movq(rcx, rtmp);
9756 mov64(dst, MINUS_64);
9757 testq(rtmp, dst);
9758 jccb(Assembler::notEqual, L_special_case);
9759 movq(dst, src);
9760 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
9761 andq(dst, rtmp);
9762 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
9763 orq(dst, rtmp);
9764 movq(rtmp, src);
9765 testq(rtmp, rtmp);
9766 jccb(Assembler::greaterEqual, L_block1);
9767 negq(dst);
9768 bind(L_block1);
9769 sarq(dst);
9770 addq(dst, 0x1);
9771 sarq(dst, 0x1);
9772 jmp(L_exit);
9773 bind(L_special_case);
9774 convert_d2l(dst, src);
9775 bind(L_exit);
9776 }
9777
9778 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
9779 Label done;
9780 cvttsd2siq(dst, src);
9781 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9782 jccb(Assembler::notEqual, done);
9783 subptr(rsp, 8);
9784 movdbl(Address(rsp, 0), src);
9785 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
9786 pop(dst);
9787 bind(done);
9788 }
9789
9790 void MacroAssembler::cache_wb(Address line)
9791 {
9792 // 64 bit cpus always support clflush
9793 assert(VM_Version::supports_clflush(), "clflush should be available");
9794 bool optimized = VM_Version::supports_clflushopt();
9795 bool no_evict = VM_Version::supports_clwb();
9796
9797 // prefer clwb (writeback without evict) otherwise
9798 // prefer clflushopt (potentially parallel writeback with evict)
9799 // otherwise fallback on clflush (serial writeback with evict)
9800
9801 if (optimized) {
9802 if (no_evict) {
9803 clwb(line);
9804 } else {
9805 clflushopt(line);
9806 }
9807 } else {
9808 // no need for fence when using CLFLUSH
9809 clflush(line);
9810 }
9811 }
9812
9813 void MacroAssembler::cache_wbsync(bool is_pre)
9814 {
9815 assert(VM_Version::supports_clflush(), "clflush should be available");
9816 bool optimized = VM_Version::supports_clflushopt();
9817 bool no_evict = VM_Version::supports_clwb();
9818
9819 // pick the correct implementation
9820
9821 if (!is_pre && (optimized || no_evict)) {
9822 // need an sfence for post flush when using clflushopt or clwb
9823 // otherwise no no need for any synchroniaztion
9824
9825 sfence();
9826 }
9827 }
9828
9829 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
9830 switch (cond) {
9831 // Note some conditions are synonyms for others
9832 case Assembler::zero: return Assembler::notZero;
9833 case Assembler::notZero: return Assembler::zero;
9834 case Assembler::less: return Assembler::greaterEqual;
9835 case Assembler::lessEqual: return Assembler::greater;
9836 case Assembler::greater: return Assembler::lessEqual;
9837 case Assembler::greaterEqual: return Assembler::less;
9838 case Assembler::below: return Assembler::aboveEqual;
9839 case Assembler::belowEqual: return Assembler::above;
9840 case Assembler::above: return Assembler::belowEqual;
9841 case Assembler::aboveEqual: return Assembler::below;
9842 case Assembler::overflow: return Assembler::noOverflow;
9843 case Assembler::noOverflow: return Assembler::overflow;
9844 case Assembler::negative: return Assembler::positive;
9845 case Assembler::positive: return Assembler::negative;
9846 case Assembler::parity: return Assembler::noParity;
9847 case Assembler::noParity: return Assembler::parity;
9848 }
9849 ShouldNotReachHere(); return Assembler::overflow;
9850 }
9851
9852 // This is simply a call to Thread::current()
9853 void MacroAssembler::get_thread_slow(Register thread) {
9854 if (thread != rax) {
9855 push(rax);
9856 }
9857 push(rdi);
9858 push(rsi);
9859 push(rdx);
9860 push(rcx);
9861 push(r8);
9862 push(r9);
9863 push(r10);
9864 push(r11);
9865
9866 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
9867
9868 pop(r11);
9869 pop(r10);
9870 pop(r9);
9871 pop(r8);
9872 pop(rcx);
9873 pop(rdx);
9874 pop(rsi);
9875 pop(rdi);
9876 if (thread != rax) {
9877 mov(thread, rax);
9878 pop(rax);
9879 }
9880 }
9881
9882 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
9883 Label L_stack_ok;
9884 if (bias == 0) {
9885 testptr(sp, 2 * wordSize - 1);
9886 } else {
9887 // lea(tmp, Address(rsp, bias);
9888 mov(tmp, sp);
9889 addptr(tmp, bias);
9890 testptr(tmp, 2 * wordSize - 1);
9891 }
9892 jcc(Assembler::equal, L_stack_ok);
9893 block_comment(msg);
9894 stop(msg);
9895 bind(L_stack_ok);
9896 }
9897
9898 // Implements fast-locking.
9899 //
9900 // obj: the object to be locked
9901 // reg_rax: rax
9902 // thread: the thread which attempts to lock obj
9903 // tmp: a temporary register
9904 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register reg_rax, Register tmp, Label& slow) {
9905 Register thread = r15_thread;
9906
9907 assert(reg_rax == rax, "");
9908 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
9909
9910 Label push;
9911 const Register top = tmp;
9912
9913 // Preload the markWord. It is important that this is the first
9914 // instruction emitted as it is part of C1's null check semantics.
9915 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
9916
9917 if (UseObjectMonitorTable) {
9918 // Clear cache in case fast locking succeeds or we need to take the slow-path.
9919 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
9920 }
9921
9922 if (DiagnoseSyncOnValueBasedClasses != 0) {
9923 load_klass(tmp, obj, rscratch1);
9924 testb(Address(tmp, Klass::misc_flags_offset()), KlassFlags::_misc_is_value_based_class);
9925 jcc(Assembler::notZero, slow);
9926 }
9927
9928 // Load top.
9929 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
9930
9931 // Check if the lock-stack is full.
9932 cmpl(top, LockStack::end_offset());
9933 jcc(Assembler::greaterEqual, slow);
9934
9935 // Check for recursion.
9936 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
9937 jcc(Assembler::equal, push);
9938
9939 // Check header for monitor (0b10).
9940 testptr(reg_rax, markWord::monitor_value);
9941 jcc(Assembler::notZero, slow);
9942
9943 // Try to lock. Transition lock bits 0b01 => 0b00
9944 movptr(tmp, reg_rax);
9945 andptr(tmp, ~(int32_t)markWord::unlocked_value);
9946 orptr(reg_rax, markWord::unlocked_value);
9947 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
9948 jcc(Assembler::notEqual, slow);
9949
9950 // Restore top, CAS clobbers register.
9951 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
9952
9953 bind(push);
9954 // After successful lock, push object on lock-stack.
9955 movptr(Address(thread, top), obj);
9956 incrementl(top, oopSize);
9957 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
9958 }
9959
9960 // Implements fast-unlocking.
9961 //
9962 // obj: the object to be unlocked
9963 // reg_rax: rax
9964 // thread: the thread
9965 // tmp: a temporary register
9966 void MacroAssembler::fast_unlock(Register obj, Register reg_rax, Register tmp, Label& slow) {
9967 Register thread = r15_thread;
9968
9969 assert(reg_rax == rax, "");
9970 assert_different_registers(obj, reg_rax, thread, tmp);
9971
9972 Label unlocked, push_and_slow;
9973 const Register top = tmp;
9974
9975 // Check if obj is top of lock-stack.
9976 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
9977 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
9978 jcc(Assembler::notEqual, slow);
9979
9980 // Pop lock-stack.
9981 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
9982 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
9983
9984 // Check if recursive.
9985 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
9986 jcc(Assembler::equal, unlocked);
9987
9988 // Not recursive. Check header for monitor (0b10).
9989 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
9990 testptr(reg_rax, markWord::monitor_value);
9991 jcc(Assembler::notZero, push_and_slow);
9992
9993 #ifdef ASSERT
9994 // Check header not unlocked (0b01).
9995 Label not_unlocked;
9996 testptr(reg_rax, markWord::unlocked_value);
9997 jcc(Assembler::zero, not_unlocked);
9998 stop("fast_unlock already unlocked");
9999 bind(not_unlocked);
10000 #endif
10001
10002 // Try to unlock. Transition lock bits 0b00 => 0b01
10003 movptr(tmp, reg_rax);
10004 orptr(tmp, markWord::unlocked_value);
10005 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10006 jcc(Assembler::equal, unlocked);
10007
10008 bind(push_and_slow);
10009 // Restore lock-stack and handle the unlock in runtime.
10010 #ifdef ASSERT
10011 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10012 movptr(Address(thread, top), obj);
10013 #endif
10014 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10015 jmp(slow);
10016
10017 bind(unlocked);
10018 }
10019
10020 // Saves legacy GPRs state on stack.
10021 void MacroAssembler::save_legacy_gprs() {
10022 subq(rsp, 16 * wordSize);
10023 movq(Address(rsp, 15 * wordSize), rax);
10024 movq(Address(rsp, 14 * wordSize), rcx);
10025 movq(Address(rsp, 13 * wordSize), rdx);
10026 movq(Address(rsp, 12 * wordSize), rbx);
10027 movq(Address(rsp, 10 * wordSize), rbp);
10028 movq(Address(rsp, 9 * wordSize), rsi);
10029 movq(Address(rsp, 8 * wordSize), rdi);
10030 movq(Address(rsp, 7 * wordSize), r8);
10031 movq(Address(rsp, 6 * wordSize), r9);
10032 movq(Address(rsp, 5 * wordSize), r10);
10033 movq(Address(rsp, 4 * wordSize), r11);
10034 movq(Address(rsp, 3 * wordSize), r12);
10035 movq(Address(rsp, 2 * wordSize), r13);
10036 movq(Address(rsp, wordSize), r14);
10037 movq(Address(rsp, 0), r15);
10038 }
10039
10040 // Resotres back legacy GPRs state from stack.
10041 void MacroAssembler::restore_legacy_gprs() {
10042 movq(r15, Address(rsp, 0));
10043 movq(r14, Address(rsp, wordSize));
10044 movq(r13, Address(rsp, 2 * wordSize));
10045 movq(r12, Address(rsp, 3 * wordSize));
10046 movq(r11, Address(rsp, 4 * wordSize));
10047 movq(r10, Address(rsp, 5 * wordSize));
10048 movq(r9, Address(rsp, 6 * wordSize));
10049 movq(r8, Address(rsp, 7 * wordSize));
10050 movq(rdi, Address(rsp, 8 * wordSize));
10051 movq(rsi, Address(rsp, 9 * wordSize));
10052 movq(rbp, Address(rsp, 10 * wordSize));
10053 movq(rbx, Address(rsp, 12 * wordSize));
10054 movq(rdx, Address(rsp, 13 * wordSize));
10055 movq(rcx, Address(rsp, 14 * wordSize));
10056 movq(rax, Address(rsp, 15 * wordSize));
10057 addq(rsp, 16 * wordSize);
10058 }
10059
10060 void MacroAssembler::load_aotrc_address(Register reg, address a) {
10061 #if INCLUDE_CDS
10062 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
10063 if (AOTCodeCache::is_on_for_dump()) {
10064 // all aotrc field addresses should be registered in the AOTCodeCache address table
10065 lea(reg, ExternalAddress(a));
10066 } else {
10067 mov64(reg, (uint64_t)a);
10068 }
10069 #else
10070 ShouldNotReachHere();
10071 #endif
10072 }
10073
10074 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10075 if (VM_Version::supports_apx_f()) {
10076 esetzucc(comparison, dst);
10077 } else {
10078 setb(comparison, dst);
10079 movzbl(dst, dst);
10080 }
10081 }