1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "code/SCCache.hpp"
29 #include "code/compiledIC.hpp"
30 #include "compiler/compiler_globals.hpp"
31 #include "compiler/disassembler.hpp"
32 #include "crc32c.h"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/collectedHeap.inline.hpp"
36 #include "gc/shared/tlab_globals.hpp"
37 #include "interpreter/bytecodeHistogram.hpp"
38 #include "interpreter/interpreter.hpp"
39 #include "interpreter/interpreterRuntime.hpp"
40 #include "jvm.h"
41 #include "memory/resourceArea.hpp"
42 #include "memory/universe.hpp"
43 #include "oops/accessDecorators.hpp"
44 #include "oops/compressedKlass.inline.hpp"
45 #include "oops/compressedOops.inline.hpp"
46 #include "oops/klass.inline.hpp"
47 #include "prims/methodHandles.hpp"
48 #include "runtime/continuation.hpp"
49 #include "runtime/interfaceSupport.inline.hpp"
50 #include "runtime/javaThread.hpp"
51 #include "runtime/jniHandles.hpp"
52 #include "runtime/objectMonitor.hpp"
53 #include "runtime/os.hpp"
54 #include "runtime/safepoint.hpp"
55 #include "runtime/safepointMechanism.hpp"
56 #include "runtime/sharedRuntime.hpp"
57 #include "runtime/stubRoutines.hpp"
58 #include "utilities/checkedCast.hpp"
59 #include "utilities/macros.hpp"
60
61 #ifdef PRODUCT
62 #define BLOCK_COMMENT(str) /* nothing */
63 #define STOP(error) stop(error)
64 #else
65 #define BLOCK_COMMENT(str) block_comment(str)
66 #define STOP(error) block_comment(error); stop(error)
67 #endif
68
69 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
70
71 #ifdef ASSERT
72 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
73 #endif
74
75 static const Assembler::Condition reverse[] = {
76 Assembler::noOverflow /* overflow = 0x0 */ ,
77 Assembler::overflow /* noOverflow = 0x1 */ ,
78 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
79 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
80 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
81 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
82 Assembler::above /* belowEqual = 0x6 */ ,
83 Assembler::belowEqual /* above = 0x7 */ ,
84 Assembler::positive /* negative = 0x8 */ ,
85 Assembler::negative /* positive = 0x9 */ ,
86 Assembler::noParity /* parity = 0xa */ ,
87 Assembler::parity /* noParity = 0xb */ ,
88 Assembler::greaterEqual /* less = 0xc */ ,
89 Assembler::less /* greaterEqual = 0xd */ ,
90 Assembler::greater /* lessEqual = 0xe */ ,
91 Assembler::lessEqual /* greater = 0xf, */
92
93 };
94
95
96 // Implementation of MacroAssembler
97
98 // First all the versions that have distinct versions depending on 32/64 bit
99 // Unless the difference is trivial (1 line or so).
100
101 #ifndef _LP64
102
103 // 32bit versions
104
105 Address MacroAssembler::as_Address(AddressLiteral adr) {
106 return Address(adr.target(), adr.rspec());
107 }
108
109 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
110 assert(rscratch == noreg, "");
111 return Address::make_array(adr);
112 }
113
114 void MacroAssembler::call_VM_leaf_base(address entry_point,
115 int number_of_arguments) {
116 call(RuntimeAddress(entry_point));
117 increment(rsp, number_of_arguments * wordSize);
118 }
119
120 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
121 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
122 }
123
124
125 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
126 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
127 }
128
129 void MacroAssembler::cmpoop(Address src1, jobject obj) {
130 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
131 }
132
133 void MacroAssembler::cmpoop(Register src1, jobject obj, Register rscratch) {
134 assert(rscratch == noreg, "redundant");
135 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
136 }
137
138 void MacroAssembler::extend_sign(Register hi, Register lo) {
139 // According to Intel Doc. AP-526, "Integer Divide", p.18.
140 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
141 cdql();
142 } else {
143 movl(hi, lo);
144 sarl(hi, 31);
145 }
146 }
147
148 void MacroAssembler::jC2(Register tmp, Label& L) {
149 // set parity bit if FPU flag C2 is set (via rax)
150 save_rax(tmp);
151 fwait(); fnstsw_ax();
152 sahf();
153 restore_rax(tmp);
154 // branch
155 jcc(Assembler::parity, L);
156 }
157
158 void MacroAssembler::jnC2(Register tmp, Label& L) {
159 // set parity bit if FPU flag C2 is set (via rax)
160 save_rax(tmp);
161 fwait(); fnstsw_ax();
162 sahf();
163 restore_rax(tmp);
164 // branch
165 jcc(Assembler::noParity, L);
166 }
167
168 // 32bit can do a case table jump in one instruction but we no longer allow the base
169 // to be installed in the Address class
170 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
171 assert(rscratch == noreg, "not needed");
172 jmp(as_Address(entry, noreg));
173 }
174
175 // Note: y_lo will be destroyed
176 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
177 // Long compare for Java (semantics as described in JVM spec.)
178 Label high, low, done;
179
180 cmpl(x_hi, y_hi);
181 jcc(Assembler::less, low);
182 jcc(Assembler::greater, high);
183 // x_hi is the return register
184 xorl(x_hi, x_hi);
185 cmpl(x_lo, y_lo);
186 jcc(Assembler::below, low);
187 jcc(Assembler::equal, done);
188
189 bind(high);
190 xorl(x_hi, x_hi);
191 increment(x_hi);
192 jmp(done);
193
194 bind(low);
195 xorl(x_hi, x_hi);
196 decrementl(x_hi);
197
198 bind(done);
199 }
200
201 void MacroAssembler::lea(Register dst, AddressLiteral src) {
202 mov_literal32(dst, (int32_t)src.target(), src.rspec());
203 }
204
205 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
206 assert(rscratch == noreg, "not needed");
207
208 // leal(dst, as_Address(adr));
209 // see note in movl as to why we must use a move
210 mov_literal32(dst, (int32_t)adr.target(), adr.rspec());
211 }
212
213 void MacroAssembler::leave() {
214 mov(rsp, rbp);
215 pop(rbp);
216 }
217
218 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
219 // Multiplication of two Java long values stored on the stack
220 // as illustrated below. Result is in rdx:rax.
221 //
222 // rsp ---> [ ?? ] \ \
223 // .... | y_rsp_offset |
224 // [ y_lo ] / (in bytes) | x_rsp_offset
225 // [ y_hi ] | (in bytes)
226 // .... |
227 // [ x_lo ] /
228 // [ x_hi ]
229 // ....
230 //
231 // Basic idea: lo(result) = lo(x_lo * y_lo)
232 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
233 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
234 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
235 Label quick;
236 // load x_hi, y_hi and check if quick
237 // multiplication is possible
238 movl(rbx, x_hi);
239 movl(rcx, y_hi);
240 movl(rax, rbx);
241 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
242 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
243 // do full multiplication
244 // 1st step
245 mull(y_lo); // x_hi * y_lo
246 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
247 // 2nd step
248 movl(rax, x_lo);
249 mull(rcx); // x_lo * y_hi
250 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
251 // 3rd step
252 bind(quick); // note: rbx, = 0 if quick multiply!
253 movl(rax, x_lo);
254 mull(y_lo); // x_lo * y_lo
255 addl(rdx, rbx); // correct hi(x_lo * y_lo)
256 }
257
258 void MacroAssembler::lneg(Register hi, Register lo) {
259 negl(lo);
260 adcl(hi, 0);
261 negl(hi);
262 }
263
264 void MacroAssembler::lshl(Register hi, Register lo) {
265 // Java shift left long support (semantics as described in JVM spec., p.305)
266 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
267 // shift value is in rcx !
268 assert(hi != rcx, "must not use rcx");
269 assert(lo != rcx, "must not use rcx");
270 const Register s = rcx; // shift count
271 const int n = BitsPerWord;
272 Label L;
273 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
274 cmpl(s, n); // if (s < n)
275 jcc(Assembler::less, L); // else (s >= n)
276 movl(hi, lo); // x := x << n
277 xorl(lo, lo);
278 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
279 bind(L); // s (mod n) < n
280 shldl(hi, lo); // x := x << s
281 shll(lo);
282 }
283
284
285 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
286 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
287 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
288 assert(hi != rcx, "must not use rcx");
289 assert(lo != rcx, "must not use rcx");
290 const Register s = rcx; // shift count
291 const int n = BitsPerWord;
292 Label L;
293 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
294 cmpl(s, n); // if (s < n)
295 jcc(Assembler::less, L); // else (s >= n)
296 movl(lo, hi); // x := x >> n
297 if (sign_extension) sarl(hi, 31);
298 else xorl(hi, hi);
299 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
300 bind(L); // s (mod n) < n
301 shrdl(lo, hi); // x := x >> s
302 if (sign_extension) sarl(hi);
303 else shrl(hi);
304 }
305
306 void MacroAssembler::movoop(Register dst, jobject obj) {
307 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
308 }
309
310 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
311 assert(rscratch == noreg, "redundant");
312 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
313 }
314
315 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
316 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
317 }
318
319 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
320 assert(rscratch == noreg, "redundant");
321 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
322 }
323
324 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
325 if (src.is_lval()) {
326 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
327 } else {
328 movl(dst, as_Address(src));
329 }
330 }
331
332 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
333 assert(rscratch == noreg, "redundant");
334 movl(as_Address(dst, noreg), src);
335 }
336
337 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
338 movl(dst, as_Address(src, noreg));
339 }
340
341 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
342 assert(rscratch == noreg, "redundant");
343 movl(dst, src);
344 }
345
346 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
347 assert(rscratch == noreg, "redundant");
348 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
349 }
350
351 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
352 assert(rscratch == noreg, "redundant");
353 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
354 }
355
356 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
357 assert(rscratch == noreg, "redundant");
358 if (src.is_lval()) {
359 push_literal32((int32_t)src.target(), src.rspec());
360 } else {
361 pushl(as_Address(src));
362 }
363 }
364
365 static void pass_arg0(MacroAssembler* masm, Register arg) {
366 masm->push(arg);
367 }
368
369 static void pass_arg1(MacroAssembler* masm, Register arg) {
370 masm->push(arg);
371 }
372
373 static void pass_arg2(MacroAssembler* masm, Register arg) {
374 masm->push(arg);
375 }
376
377 static void pass_arg3(MacroAssembler* masm, Register arg) {
378 masm->push(arg);
379 }
380
381 #ifndef PRODUCT
382 extern "C" void findpc(intptr_t x);
383 #endif
384
385 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
386 // In order to get locks to work, we need to fake a in_VM state
387 JavaThread* thread = JavaThread::current();
388 JavaThreadState saved_state = thread->thread_state();
389 thread->set_thread_state(_thread_in_vm);
390 if (ShowMessageBoxOnError) {
391 JavaThread* thread = JavaThread::current();
392 JavaThreadState saved_state = thread->thread_state();
393 thread->set_thread_state(_thread_in_vm);
394 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
395 ttyLocker ttyl;
396 BytecodeCounter::print();
397 }
398 // To see where a verify_oop failed, get $ebx+40/X for this frame.
399 // This is the value of eip which points to where verify_oop will return.
400 if (os::message_box(msg, "Execution stopped, print registers?")) {
401 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
402 BREAKPOINT;
403 }
404 }
405 fatal("DEBUG MESSAGE: %s", msg);
406 }
407
408 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
409 ttyLocker ttyl;
410 DebuggingContext debugging{};
411 tty->print_cr("eip = 0x%08x", eip);
412 #ifndef PRODUCT
413 if ((WizardMode || Verbose) && PrintMiscellaneous) {
414 tty->cr();
415 findpc(eip);
416 tty->cr();
417 }
418 #endif
419 #define PRINT_REG(rax) \
420 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
421 PRINT_REG(rax);
422 PRINT_REG(rbx);
423 PRINT_REG(rcx);
424 PRINT_REG(rdx);
425 PRINT_REG(rdi);
426 PRINT_REG(rsi);
427 PRINT_REG(rbp);
428 PRINT_REG(rsp);
429 #undef PRINT_REG
430 // Print some words near top of staack.
431 int* dump_sp = (int*) rsp;
432 for (int col1 = 0; col1 < 8; col1++) {
433 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
434 os::print_location(tty, *dump_sp++);
435 }
436 for (int row = 0; row < 16; row++) {
437 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
438 for (int col = 0; col < 8; col++) {
439 tty->print(" 0x%08x", *dump_sp++);
440 }
441 tty->cr();
442 }
443 // Print some instructions around pc:
444 Disassembler::decode((address)eip-64, (address)eip);
445 tty->print_cr("--------");
446 Disassembler::decode((address)eip, (address)eip+32);
447 }
448
449 void MacroAssembler::stop(const char* msg) {
450 // push address of message
451 ExternalAddress message((address)msg);
452 pushptr(message.addr(), noreg);
453 { Label L; call(L, relocInfo::none); bind(L); } // push eip
454 pusha(); // push registers
455 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
456 hlt();
457 }
458
459 void MacroAssembler::warn(const char* msg) {
460 push_CPU_state();
461
462 // push address of message
463 ExternalAddress message((address)msg);
464 pushptr(message.addr(), noreg);
465
466 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
467 addl(rsp, wordSize); // discard argument
468 pop_CPU_state();
469 }
470
471 void MacroAssembler::print_state() {
472 { Label L; call(L, relocInfo::none); bind(L); } // push eip
473 pusha(); // push registers
474
475 push_CPU_state();
476 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
477 pop_CPU_state();
478
479 popa();
480 addl(rsp, wordSize);
481 }
482
483 #else // _LP64
484
485 // 64 bit versions
486
487 Address MacroAssembler::as_Address(AddressLiteral adr) {
488 // amd64 always does this as a pc-rel
489 // we can be absolute or disp based on the instruction type
490 // jmp/call are displacements others are absolute
491 assert(!adr.is_lval(), "must be rval");
492 assert(reachable(adr), "must be");
493 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
494
495 }
496
497 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
498 AddressLiteral base = adr.base();
499 lea(rscratch, base);
500 Address index = adr.index();
501 assert(index._disp == 0, "must not have disp"); // maybe it can?
502 Address array(rscratch, index._index, index._scale, index._disp);
503 return array;
504 }
505
506 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
507 Label L, E;
508
509 #ifdef _WIN64
510 // Windows always allocates space for it's register args
511 assert(num_args <= 4, "only register arguments supported");
512 subq(rsp, frame::arg_reg_save_area_bytes);
513 #endif
514
515 // Align stack if necessary
516 testl(rsp, 15);
517 jcc(Assembler::zero, L);
518
519 subq(rsp, 8);
520 call(RuntimeAddress(entry_point));
521 addq(rsp, 8);
522 jmp(E);
523
524 bind(L);
525 call(RuntimeAddress(entry_point));
526
527 bind(E);
528
529 #ifdef _WIN64
530 // restore stack pointer
531 addq(rsp, frame::arg_reg_save_area_bytes);
532 #endif
533 }
534
535 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
536 assert(!src2.is_lval(), "should use cmpptr");
537 assert(rscratch != noreg || always_reachable(src2), "missing");
538
539 if (reachable(src2)) {
540 cmpq(src1, as_Address(src2));
541 } else {
542 lea(rscratch, src2);
543 Assembler::cmpq(src1, Address(rscratch, 0));
544 }
545 }
546
547 int MacroAssembler::corrected_idivq(Register reg) {
548 // Full implementation of Java ldiv and lrem; checks for special
549 // case as described in JVM spec., p.243 & p.271. The function
550 // returns the (pc) offset of the idivl instruction - may be needed
551 // for implicit exceptions.
552 //
553 // normal case special case
554 //
555 // input : rax: dividend min_long
556 // reg: divisor (may not be eax/edx) -1
557 //
558 // output: rax: quotient (= rax idiv reg) min_long
559 // rdx: remainder (= rax irem reg) 0
560 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
561 static const int64_t min_long = 0x8000000000000000;
562 Label normal_case, special_case;
563
564 // check for special case
565 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
566 jcc(Assembler::notEqual, normal_case);
567 xorl(rdx, rdx); // prepare rdx for possible special case (where
568 // remainder = 0)
569 cmpq(reg, -1);
570 jcc(Assembler::equal, special_case);
571
572 // handle normal case
573 bind(normal_case);
574 cdqq();
575 int idivq_offset = offset();
576 idivq(reg);
577
578 // normal and special case exit
579 bind(special_case);
580
581 return idivq_offset;
582 }
583
584 void MacroAssembler::decrementq(Register reg, int value) {
585 if (value == min_jint) { subq(reg, value); return; }
586 if (value < 0) { incrementq(reg, -value); return; }
587 if (value == 0) { ; return; }
588 if (value == 1 && UseIncDec) { decq(reg) ; return; }
589 /* else */ { subq(reg, value) ; return; }
590 }
591
592 void MacroAssembler::decrementq(Address dst, int value) {
593 if (value == min_jint) { subq(dst, value); return; }
594 if (value < 0) { incrementq(dst, -value); return; }
595 if (value == 0) { ; return; }
596 if (value == 1 && UseIncDec) { decq(dst) ; return; }
597 /* else */ { subq(dst, value) ; return; }
598 }
599
600 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
601 assert(rscratch != noreg || always_reachable(dst), "missing");
602
603 if (reachable(dst)) {
604 incrementq(as_Address(dst));
605 } else {
606 lea(rscratch, dst);
607 incrementq(Address(rscratch, 0));
608 }
609 }
610
611 void MacroAssembler::incrementq(Register reg, int value) {
612 if (value == min_jint) { addq(reg, value); return; }
613 if (value < 0) { decrementq(reg, -value); return; }
614 if (value == 0) { ; return; }
615 if (value == 1 && UseIncDec) { incq(reg) ; return; }
616 /* else */ { addq(reg, value) ; return; }
617 }
618
619 void MacroAssembler::incrementq(Address dst, int value) {
620 if (value == min_jint) { addq(dst, value); return; }
621 if (value < 0) { decrementq(dst, -value); return; }
622 if (value == 0) { ; return; }
623 if (value == 1 && UseIncDec) { incq(dst) ; return; }
624 /* else */ { addq(dst, value) ; return; }
625 }
626
627 // 32bit can do a case table jump in one instruction but we no longer allow the base
628 // to be installed in the Address class
629 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
630 lea(rscratch, entry.base());
631 Address dispatch = entry.index();
632 assert(dispatch._base == noreg, "must be");
633 dispatch._base = rscratch;
634 jmp(dispatch);
635 }
636
637 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
638 ShouldNotReachHere(); // 64bit doesn't use two regs
639 cmpq(x_lo, y_lo);
640 }
641
642 void MacroAssembler::lea(Register dst, AddressLiteral src) {
643 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
644 }
645
646 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
647 lea(rscratch, adr);
648 movptr(dst, rscratch);
649 }
650
651 void MacroAssembler::leave() {
652 // %%% is this really better? Why not on 32bit too?
653 emit_int8((unsigned char)0xC9); // LEAVE
654 }
655
656 void MacroAssembler::lneg(Register hi, Register lo) {
657 ShouldNotReachHere(); // 64bit doesn't use two regs
658 negq(lo);
659 }
660
661 void MacroAssembler::movoop(Register dst, jobject obj) {
662 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
663 }
664
665 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
666 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
667 movq(dst, rscratch);
668 }
669
670 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
671 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
672 }
673
674 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
675 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
676 movq(dst, rscratch);
677 }
678
679 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
680 if (src.is_lval()) {
681 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
682 } else {
683 if (reachable(src)) {
684 movq(dst, as_Address(src));
685 } else {
686 lea(dst, src);
687 movq(dst, Address(dst, 0));
688 }
689 }
690 }
691
692 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
693 movq(as_Address(dst, rscratch), src);
694 }
695
696 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
697 movq(dst, as_Address(src, dst /*rscratch*/));
698 }
699
700 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
701 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
702 if (is_simm32(src)) {
703 movptr(dst, checked_cast<int32_t>(src));
704 } else {
705 mov64(rscratch, src);
706 movq(dst, rscratch);
707 }
708 }
709
710 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
711 movoop(rscratch, obj);
712 push(rscratch);
713 }
714
715 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
716 mov_metadata(rscratch, obj);
717 push(rscratch);
718 }
719
720 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
721 lea(rscratch, src);
722 if (src.is_lval()) {
723 push(rscratch);
724 } else {
725 pushq(Address(rscratch, 0));
726 }
727 }
728
729 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
730 reset_last_Java_frame(r15_thread, clear_fp);
731 }
732
733 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
734 Register last_java_fp,
735 address last_java_pc,
736 Register rscratch) {
737 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, last_java_pc, rscratch);
738 }
739
740 static void pass_arg0(MacroAssembler* masm, Register arg) {
741 if (c_rarg0 != arg ) {
742 masm->mov(c_rarg0, arg);
743 }
744 }
745
746 static void pass_arg1(MacroAssembler* masm, Register arg) {
747 if (c_rarg1 != arg ) {
748 masm->mov(c_rarg1, arg);
749 }
750 }
751
752 static void pass_arg2(MacroAssembler* masm, Register arg) {
753 if (c_rarg2 != arg ) {
754 masm->mov(c_rarg2, arg);
755 }
756 }
757
758 static void pass_arg3(MacroAssembler* masm, Register arg) {
759 if (c_rarg3 != arg ) {
760 masm->mov(c_rarg3, arg);
761 }
762 }
763
764 void MacroAssembler::stop(const char* msg) {
765 if (ShowMessageBoxOnError) {
766 address rip = pc();
767 pusha(); // get regs on stack
768 lea(c_rarg1, InternalAddress(rip));
769 movq(c_rarg2, rsp); // pass pointer to regs array
770 }
771 lea(c_rarg0, ExternalAddress((address) msg));
772 andq(rsp, -16); // align stack as required by ABI
773 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
774 hlt();
775 SCCache::add_C_string(msg);
776 }
777
778 void MacroAssembler::warn(const char* msg) {
779 push(rbp);
780 movq(rbp, rsp);
781 andq(rsp, -16); // align stack as required by push_CPU_state and call
782 push_CPU_state(); // keeps alignment at 16 bytes
783
784 lea(c_rarg0, ExternalAddress((address) msg));
785 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
786
787 pop_CPU_state();
788 mov(rsp, rbp);
789 pop(rbp);
790 }
791
792 void MacroAssembler::print_state() {
793 address rip = pc();
794 pusha(); // get regs on stack
795 push(rbp);
796 movq(rbp, rsp);
797 andq(rsp, -16); // align stack as required by push_CPU_state and call
798 push_CPU_state(); // keeps alignment at 16 bytes
799
800 lea(c_rarg0, InternalAddress(rip));
801 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
802 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
803
804 pop_CPU_state();
805 mov(rsp, rbp);
806 pop(rbp);
807 popa();
808 }
809
810 #ifndef PRODUCT
811 extern "C" void findpc(intptr_t x);
812 #endif
813
814 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
815 // In order to get locks to work, we need to fake a in_VM state
816 if (ShowMessageBoxOnError) {
817 JavaThread* thread = JavaThread::current();
818 JavaThreadState saved_state = thread->thread_state();
819 thread->set_thread_state(_thread_in_vm);
820 #ifndef PRODUCT
821 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
822 ttyLocker ttyl;
823 BytecodeCounter::print();
824 }
825 #endif
826 // To see where a verify_oop failed, get $ebx+40/X for this frame.
827 // XXX correct this offset for amd64
828 // This is the value of eip which points to where verify_oop will return.
829 if (os::message_box(msg, "Execution stopped, print registers?")) {
830 print_state64(pc, regs);
831 BREAKPOINT;
832 }
833 }
834 fatal("DEBUG MESSAGE: %s", msg);
835 }
836
837 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
838 ttyLocker ttyl;
839 DebuggingContext debugging{};
840 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
841 #ifndef PRODUCT
842 tty->cr();
843 findpc(pc);
844 tty->cr();
845 #endif
846 #define PRINT_REG(rax, value) \
847 { tty->print("%s = ", #rax); os::print_location(tty, value); }
848 PRINT_REG(rax, regs[15]);
849 PRINT_REG(rbx, regs[12]);
850 PRINT_REG(rcx, regs[14]);
851 PRINT_REG(rdx, regs[13]);
852 PRINT_REG(rdi, regs[8]);
853 PRINT_REG(rsi, regs[9]);
854 PRINT_REG(rbp, regs[10]);
855 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
856 PRINT_REG(rsp, (intptr_t)(®s[16]));
857 PRINT_REG(r8 , regs[7]);
858 PRINT_REG(r9 , regs[6]);
859 PRINT_REG(r10, regs[5]);
860 PRINT_REG(r11, regs[4]);
861 PRINT_REG(r12, regs[3]);
862 PRINT_REG(r13, regs[2]);
863 PRINT_REG(r14, regs[1]);
864 PRINT_REG(r15, regs[0]);
865 #undef PRINT_REG
866 // Print some words near the top of the stack.
867 int64_t* rsp = ®s[16];
868 int64_t* dump_sp = rsp;
869 for (int col1 = 0; col1 < 8; col1++) {
870 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
871 os::print_location(tty, *dump_sp++);
872 }
873 for (int row = 0; row < 25; row++) {
874 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
875 for (int col = 0; col < 4; col++) {
876 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
877 }
878 tty->cr();
879 }
880 // Print some instructions around pc:
881 Disassembler::decode((address)pc-64, (address)pc);
882 tty->print_cr("--------");
883 Disassembler::decode((address)pc, (address)pc+32);
884 }
885
886 // The java_calling_convention describes stack locations as ideal slots on
887 // a frame with no abi restrictions. Since we must observe abi restrictions
888 // (like the placement of the register window) the slots must be biased by
889 // the following value.
890 static int reg2offset_in(VMReg r) {
891 // Account for saved rbp and return address
892 // This should really be in_preserve_stack_slots
893 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
894 }
895
896 static int reg2offset_out(VMReg r) {
897 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
898 }
899
900 // A long move
901 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
902
903 // The calling conventions assures us that each VMregpair is either
904 // all really one physical register or adjacent stack slots.
905
906 if (src.is_single_phys_reg() ) {
907 if (dst.is_single_phys_reg()) {
908 if (dst.first() != src.first()) {
909 mov(dst.first()->as_Register(), src.first()->as_Register());
910 }
911 } else {
912 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
913 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
914 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
915 }
916 } else if (dst.is_single_phys_reg()) {
917 assert(src.is_single_reg(), "not a stack pair");
918 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
919 } else {
920 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
921 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
922 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
923 }
924 }
925
926 // A double move
927 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
928
929 // The calling conventions assures us that each VMregpair is either
930 // all really one physical register or adjacent stack slots.
931
932 if (src.is_single_phys_reg() ) {
933 if (dst.is_single_phys_reg()) {
934 // In theory these overlap but the ordering is such that this is likely a nop
935 if ( src.first() != dst.first()) {
936 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
937 }
938 } else {
939 assert(dst.is_single_reg(), "not a stack pair");
940 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
941 }
942 } else if (dst.is_single_phys_reg()) {
943 assert(src.is_single_reg(), "not a stack pair");
944 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
945 } else {
946 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
947 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
948 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
949 }
950 }
951
952
953 // A float arg may have to do float reg int reg conversion
954 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
955 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
956
957 // The calling conventions assures us that each VMregpair is either
958 // all really one physical register or adjacent stack slots.
959
960 if (src.first()->is_stack()) {
961 if (dst.first()->is_stack()) {
962 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
963 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
964 } else {
965 // stack to reg
966 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
967 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
968 }
969 } else if (dst.first()->is_stack()) {
970 // reg to stack
971 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
972 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
973 } else {
974 // reg to reg
975 // In theory these overlap but the ordering is such that this is likely a nop
976 if ( src.first() != dst.first()) {
977 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
978 }
979 }
980 }
981
982 // On 64 bit we will store integer like items to the stack as
983 // 64 bits items (x86_32/64 abi) even though java would only store
984 // 32bits for a parameter. On 32bit it will simply be 32 bits
985 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
986 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
987 if (src.first()->is_stack()) {
988 if (dst.first()->is_stack()) {
989 // stack to stack
990 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
991 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
992 } else {
993 // stack to reg
994 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
995 }
996 } else if (dst.first()->is_stack()) {
997 // reg to stack
998 // Do we really have to sign extend???
999 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1000 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
1001 } else {
1002 // Do we really have to sign extend???
1003 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1004 if (dst.first() != src.first()) {
1005 movq(dst.first()->as_Register(), src.first()->as_Register());
1006 }
1007 }
1008 }
1009
1010 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1011 if (src.first()->is_stack()) {
1012 if (dst.first()->is_stack()) {
1013 // stack to stack
1014 movq(rax, Address(rbp, reg2offset_in(src.first())));
1015 movq(Address(rsp, reg2offset_out(dst.first())), rax);
1016 } else {
1017 // stack to reg
1018 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1019 }
1020 } else if (dst.first()->is_stack()) {
1021 // reg to stack
1022 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1023 } else {
1024 if (dst.first() != src.first()) {
1025 movq(dst.first()->as_Register(), src.first()->as_Register());
1026 }
1027 }
1028 }
1029
1030 // An oop arg. Must pass a handle not the oop itself
1031 void MacroAssembler::object_move(OopMap* map,
1032 int oop_handle_offset,
1033 int framesize_in_slots,
1034 VMRegPair src,
1035 VMRegPair dst,
1036 bool is_receiver,
1037 int* receiver_offset) {
1038
1039 // must pass a handle. First figure out the location we use as a handle
1040
1041 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1042
1043 // See if oop is null if it is we need no handle
1044
1045 if (src.first()->is_stack()) {
1046
1047 // Oop is already on the stack as an argument
1048 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1049 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1050 if (is_receiver) {
1051 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1052 }
1053
1054 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
1055 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1056 // conditionally move a null
1057 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1058 } else {
1059
1060 // Oop is in a register we must store it to the space we reserve
1061 // on the stack for oop_handles and pass a handle if oop is non-null
1062
1063 const Register rOop = src.first()->as_Register();
1064 int oop_slot;
1065 if (rOop == j_rarg0)
1066 oop_slot = 0;
1067 else if (rOop == j_rarg1)
1068 oop_slot = 1;
1069 else if (rOop == j_rarg2)
1070 oop_slot = 2;
1071 else if (rOop == j_rarg3)
1072 oop_slot = 3;
1073 else if (rOop == j_rarg4)
1074 oop_slot = 4;
1075 else {
1076 assert(rOop == j_rarg5, "wrong register");
1077 oop_slot = 5;
1078 }
1079
1080 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1081 int offset = oop_slot*VMRegImpl::stack_slot_size;
1082
1083 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1084 // Store oop in handle area, may be null
1085 movptr(Address(rsp, offset), rOop);
1086 if (is_receiver) {
1087 *receiver_offset = offset;
1088 }
1089
1090 cmpptr(rOop, NULL_WORD);
1091 lea(rHandle, Address(rsp, offset));
1092 // conditionally move a null from the handle area where it was just stored
1093 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1094 }
1095
1096 // If arg is on the stack then place it otherwise it is already in correct reg.
1097 if (dst.first()->is_stack()) {
1098 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1099 }
1100 }
1101
1102 #endif // _LP64
1103
1104 // Now versions that are common to 32/64 bit
1105
1106 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1107 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1108 }
1109
1110 void MacroAssembler::addptr(Register dst, Register src) {
1111 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1112 }
1113
1114 void MacroAssembler::addptr(Address dst, Register src) {
1115 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1116 }
1117
1118 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1119 assert(rscratch != noreg || always_reachable(src), "missing");
1120
1121 if (reachable(src)) {
1122 Assembler::addsd(dst, as_Address(src));
1123 } else {
1124 lea(rscratch, src);
1125 Assembler::addsd(dst, Address(rscratch, 0));
1126 }
1127 }
1128
1129 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1130 assert(rscratch != noreg || always_reachable(src), "missing");
1131
1132 if (reachable(src)) {
1133 addss(dst, as_Address(src));
1134 } else {
1135 lea(rscratch, src);
1136 addss(dst, Address(rscratch, 0));
1137 }
1138 }
1139
1140 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1141 assert(rscratch != noreg || always_reachable(src), "missing");
1142
1143 if (reachable(src)) {
1144 Assembler::addpd(dst, as_Address(src));
1145 } else {
1146 lea(rscratch, src);
1147 Assembler::addpd(dst, Address(rscratch, 0));
1148 }
1149 }
1150
1151 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
1152 // Stub code is generated once and never copied.
1153 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1154 void MacroAssembler::align64() {
1155 align(64, (uint)(uintptr_t)pc());
1156 }
1157
1158 void MacroAssembler::align32() {
1159 align(32, (uint)(uintptr_t)pc());
1160 }
1161
1162 void MacroAssembler::align(uint modulus) {
1163 // 8273459: Ensure alignment is possible with current segment alignment
1164 assert(modulus <= (uintx)CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1165 align(modulus, offset());
1166 }
1167
1168 void MacroAssembler::align(uint modulus, uint target) {
1169 if (target % modulus != 0) {
1170 nop(modulus - (target % modulus));
1171 }
1172 }
1173
1174 void MacroAssembler::push_f(XMMRegister r) {
1175 subptr(rsp, wordSize);
1176 movflt(Address(rsp, 0), r);
1177 }
1178
1179 void MacroAssembler::pop_f(XMMRegister r) {
1180 movflt(r, Address(rsp, 0));
1181 addptr(rsp, wordSize);
1182 }
1183
1184 void MacroAssembler::push_d(XMMRegister r) {
1185 subptr(rsp, 2 * wordSize);
1186 movdbl(Address(rsp, 0), r);
1187 }
1188
1189 void MacroAssembler::pop_d(XMMRegister r) {
1190 movdbl(r, Address(rsp, 0));
1191 addptr(rsp, 2 * Interpreter::stackElementSize);
1192 }
1193
1194 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1195 // Used in sign-masking with aligned address.
1196 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1197 assert(rscratch != noreg || always_reachable(src), "missing");
1198
1199 if (UseAVX > 2 &&
1200 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
1201 (dst->encoding() >= 16)) {
1202 vpand(dst, dst, src, AVX_512bit, rscratch);
1203 } else if (reachable(src)) {
1204 Assembler::andpd(dst, as_Address(src));
1205 } else {
1206 lea(rscratch, src);
1207 Assembler::andpd(dst, Address(rscratch, 0));
1208 }
1209 }
1210
1211 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
1212 // Used in sign-masking with aligned address.
1213 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1214 assert(rscratch != noreg || always_reachable(src), "missing");
1215
1216 if (reachable(src)) {
1217 Assembler::andps(dst, as_Address(src));
1218 } else {
1219 lea(rscratch, src);
1220 Assembler::andps(dst, Address(rscratch, 0));
1221 }
1222 }
1223
1224 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1225 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1226 }
1227
1228 #ifdef _LP64
1229 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
1230 assert(rscratch != noreg || always_reachable(src), "missing");
1231
1232 if (reachable(src)) {
1233 andq(dst, as_Address(src));
1234 } else {
1235 lea(rscratch, src);
1236 andq(dst, Address(rscratch, 0));
1237 }
1238 }
1239 #endif
1240
1241 void MacroAssembler::atomic_incl(Address counter_addr) {
1242 lock();
1243 incrementl(counter_addr);
1244 }
1245
1246 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
1247 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1248
1249 if (reachable(counter_addr)) {
1250 atomic_incl(as_Address(counter_addr));
1251 } else {
1252 lea(rscratch, counter_addr);
1253 atomic_incl(Address(rscratch, 0));
1254 }
1255 }
1256
1257 #ifdef _LP64
1258 void MacroAssembler::atomic_incq(Address counter_addr) {
1259 lock();
1260 incrementq(counter_addr);
1261 }
1262
1263 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
1264 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1265
1266 if (reachable(counter_addr)) {
1267 atomic_incq(as_Address(counter_addr));
1268 } else {
1269 lea(rscratch, counter_addr);
1270 atomic_incq(Address(rscratch, 0));
1271 }
1272 }
1273 #endif
1274
1275 // Writes to stack successive pages until offset reached to check for
1276 // stack overflow + shadow pages. This clobbers tmp.
1277 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1278 movptr(tmp, rsp);
1279 // Bang stack for total size given plus shadow page size.
1280 // Bang one page at a time because large size can bang beyond yellow and
1281 // red zones.
1282 Label loop;
1283 bind(loop);
1284 movl(Address(tmp, (-(int)os::vm_page_size())), size );
1285 subptr(tmp, (int)os::vm_page_size());
1286 subl(size, (int)os::vm_page_size());
1287 jcc(Assembler::greater, loop);
1288
1289 // Bang down shadow pages too.
1290 // At this point, (tmp-0) is the last address touched, so don't
1291 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1292 // was post-decremented.) Skip this address by starting at i=1, and
1293 // touch a few more pages below. N.B. It is important to touch all
1294 // the way down including all pages in the shadow zone.
1295 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
1296 // this could be any sized move but this is can be a debugging crumb
1297 // so the bigger the better.
1298 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
1299 }
1300 }
1301
1302 void MacroAssembler::reserved_stack_check() {
1303 // testing if reserved zone needs to be enabled
1304 Label no_reserved_zone_enabling;
1305 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1306 NOT_LP64(get_thread(rsi);)
1307
1308 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1309 jcc(Assembler::below, no_reserved_zone_enabling);
1310
1311 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1312 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
1313 should_not_reach_here();
1314
1315 bind(no_reserved_zone_enabling);
1316 }
1317
1318 void MacroAssembler::c2bool(Register x) {
1319 // implements x == 0 ? 0 : 1
1320 // note: must only look at least-significant byte of x
1321 // since C-style booleans are stored in one byte
1322 // only! (was bug)
1323 andl(x, 0xFF);
1324 setb(Assembler::notZero, x);
1325 }
1326
1327 // Wouldn't need if AddressLiteral version had new name
1328 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1329 Assembler::call(L, rtype);
1330 }
1331
1332 void MacroAssembler::call(Register entry) {
1333 Assembler::call(entry);
1334 }
1335
1336 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
1337 assert(rscratch != noreg || always_reachable(entry), "missing");
1338
1339 if (reachable(entry)) {
1340 Assembler::call_literal(entry.target(), entry.rspec());
1341 } else {
1342 lea(rscratch, entry);
1343 Assembler::call(rscratch);
1344 }
1345 }
1346
1347 void MacroAssembler::ic_call(address entry, jint method_index) {
1348 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1349 #ifdef _LP64
1350 // Needs full 64-bit immediate for later patching.
1351 mov64(rax, (int64_t)Universe::non_oop_word());
1352 #else
1353 movptr(rax, (intptr_t)Universe::non_oop_word());
1354 #endif
1355 call(AddressLiteral(entry, rh));
1356 }
1357
1358 int MacroAssembler::ic_check_size() {
1359 return
1360 LP64_ONLY(UseCompactObjectHeaders ? 17 : 14) NOT_LP64(12);
1361 }
1362
1363 int MacroAssembler::ic_check(int end_alignment) {
1364 Register receiver = LP64_ONLY(j_rarg0) NOT_LP64(rcx);
1365 Register data = rax;
1366 Register temp = LP64_ONLY(rscratch1) NOT_LP64(rbx);
1367
1368 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1369 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1370 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1371 // before the inline cache check here, and not after
1372 align(end_alignment, offset() + ic_check_size());
1373
1374 int uep_offset = offset();
1375
1376 #ifdef _LP64
1377 if (UseCompactObjectHeaders) {
1378 load_narrow_klass_compact(temp, receiver);
1379 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1380 } else
1381 #endif
1382 if (UseCompressedClassPointers) {
1383 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1384 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1385 } else {
1386 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1387 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
1388 }
1389
1390 // if inline cache check fails, then jump to runtime routine
1391 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1392 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
1393
1394 return uep_offset;
1395 }
1396
1397 void MacroAssembler::emit_static_call_stub() {
1398 // Static stub relocation also tags the Method* in the code-stream.
1399 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1400 // This is recognized as unresolved by relocs/nativeinst/ic code.
1401 jump(RuntimeAddress(pc()));
1402 }
1403
1404 // Implementation of call_VM versions
1405
1406 void MacroAssembler::call_VM(Register oop_result,
1407 address entry_point,
1408 bool check_exceptions) {
1409 Label C, E;
1410 call(C, relocInfo::none);
1411 jmp(E);
1412
1413 bind(C);
1414 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1415 ret(0);
1416
1417 bind(E);
1418 }
1419
1420 void MacroAssembler::call_VM(Register oop_result,
1421 address entry_point,
1422 Register arg_1,
1423 bool check_exceptions) {
1424 Label C, E;
1425 call(C, relocInfo::none);
1426 jmp(E);
1427
1428 bind(C);
1429 pass_arg1(this, arg_1);
1430 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1431 ret(0);
1432
1433 bind(E);
1434 }
1435
1436 void MacroAssembler::call_VM(Register oop_result,
1437 address entry_point,
1438 Register arg_1,
1439 Register arg_2,
1440 bool check_exceptions) {
1441 Label C, E;
1442 call(C, relocInfo::none);
1443 jmp(E);
1444
1445 bind(C);
1446
1447 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1448
1449 pass_arg2(this, arg_2);
1450 pass_arg1(this, arg_1);
1451 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1452 ret(0);
1453
1454 bind(E);
1455 }
1456
1457 void MacroAssembler::call_VM(Register oop_result,
1458 address entry_point,
1459 Register arg_1,
1460 Register arg_2,
1461 Register arg_3,
1462 bool check_exceptions) {
1463 Label C, E;
1464 call(C, relocInfo::none);
1465 jmp(E);
1466
1467 bind(C);
1468
1469 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1470 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1471 pass_arg3(this, arg_3);
1472 pass_arg2(this, arg_2);
1473 pass_arg1(this, arg_1);
1474 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1475 ret(0);
1476
1477 bind(E);
1478 }
1479
1480 void MacroAssembler::call_VM(Register oop_result,
1481 Register last_java_sp,
1482 address entry_point,
1483 int number_of_arguments,
1484 bool check_exceptions) {
1485 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1486 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1487 }
1488
1489 void MacroAssembler::call_VM(Register oop_result,
1490 Register last_java_sp,
1491 address entry_point,
1492 Register arg_1,
1493 bool check_exceptions) {
1494 pass_arg1(this, arg_1);
1495 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1496 }
1497
1498 void MacroAssembler::call_VM(Register oop_result,
1499 Register last_java_sp,
1500 address entry_point,
1501 Register arg_1,
1502 Register arg_2,
1503 bool check_exceptions) {
1504
1505 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1506 pass_arg2(this, arg_2);
1507 pass_arg1(this, arg_1);
1508 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1509 }
1510
1511 void MacroAssembler::call_VM(Register oop_result,
1512 Register last_java_sp,
1513 address entry_point,
1514 Register arg_1,
1515 Register arg_2,
1516 Register arg_3,
1517 bool check_exceptions) {
1518 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1519 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1520 pass_arg3(this, arg_3);
1521 pass_arg2(this, arg_2);
1522 pass_arg1(this, arg_1);
1523 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1524 }
1525
1526 void MacroAssembler::super_call_VM(Register oop_result,
1527 Register last_java_sp,
1528 address entry_point,
1529 int number_of_arguments,
1530 bool check_exceptions) {
1531 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1532 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1533 }
1534
1535 void MacroAssembler::super_call_VM(Register oop_result,
1536 Register last_java_sp,
1537 address entry_point,
1538 Register arg_1,
1539 bool check_exceptions) {
1540 pass_arg1(this, arg_1);
1541 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1542 }
1543
1544 void MacroAssembler::super_call_VM(Register oop_result,
1545 Register last_java_sp,
1546 address entry_point,
1547 Register arg_1,
1548 Register arg_2,
1549 bool check_exceptions) {
1550
1551 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1552 pass_arg2(this, arg_2);
1553 pass_arg1(this, arg_1);
1554 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1555 }
1556
1557 void MacroAssembler::super_call_VM(Register oop_result,
1558 Register last_java_sp,
1559 address entry_point,
1560 Register arg_1,
1561 Register arg_2,
1562 Register arg_3,
1563 bool check_exceptions) {
1564 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1565 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1566 pass_arg3(this, arg_3);
1567 pass_arg2(this, arg_2);
1568 pass_arg1(this, arg_1);
1569 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1570 }
1571
1572 void MacroAssembler::call_VM_base(Register oop_result,
1573 Register java_thread,
1574 Register last_java_sp,
1575 address entry_point,
1576 int number_of_arguments,
1577 bool check_exceptions) {
1578 // determine java_thread register
1579 if (!java_thread->is_valid()) {
1580 #ifdef _LP64
1581 java_thread = r15_thread;
1582 #else
1583 java_thread = rdi;
1584 get_thread(java_thread);
1585 #endif // LP64
1586 }
1587 // determine last_java_sp register
1588 if (!last_java_sp->is_valid()) {
1589 last_java_sp = rsp;
1590 }
1591 // debugging support
1592 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1593 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1594 #ifdef ASSERT
1595 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1596 // r12 is the heapbase.
1597 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1598 #endif // ASSERT
1599
1600 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1601 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1602
1603 // push java thread (becomes first argument of C function)
1604
1605 NOT_LP64(push(java_thread); number_of_arguments++);
1606 LP64_ONLY(mov(c_rarg0, r15_thread));
1607
1608 // set last Java frame before call
1609 assert(last_java_sp != rbp, "can't use ebp/rbp");
1610
1611 // Only interpreter should have to set fp
1612 set_last_Java_frame(java_thread, last_java_sp, rbp, nullptr, rscratch1);
1613
1614 // do the call, remove parameters
1615 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1616
1617 // restore the thread (cannot use the pushed argument since arguments
1618 // may be overwritten by C code generated by an optimizing compiler);
1619 // however can use the register value directly if it is callee saved.
1620 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1621 // rdi & rsi (also r15) are callee saved -> nothing to do
1622 #ifdef ASSERT
1623 guarantee(java_thread != rax, "change this code");
1624 push(rax);
1625 { Label L;
1626 get_thread(rax);
1627 cmpptr(java_thread, rax);
1628 jcc(Assembler::equal, L);
1629 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1630 bind(L);
1631 }
1632 pop(rax);
1633 #endif
1634 } else {
1635 get_thread(java_thread);
1636 }
1637 // reset last Java frame
1638 // Only interpreter should have to clear fp
1639 reset_last_Java_frame(java_thread, true);
1640
1641 // C++ interp handles this in the interpreter
1642 check_and_handle_popframe(java_thread);
1643 check_and_handle_earlyret(java_thread);
1644
1645 if (check_exceptions) {
1646 // check for pending exceptions (java_thread is set upon return)
1647 cmpptr(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
1648 #ifndef _LP64
1649 jump_cc(Assembler::notEqual,
1650 RuntimeAddress(StubRoutines::forward_exception_entry()));
1651 #else
1652 // This used to conditionally jump to forward_exception however it is
1653 // possible if we relocate that the branch will not reach. So we must jump
1654 // around so we can always reach
1655
1656 Label ok;
1657 jcc(Assembler::equal, ok);
1658 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1659 bind(ok);
1660 #endif // LP64
1661 }
1662
1663 // get oop result if there is one and reset the value in the thread
1664 if (oop_result->is_valid()) {
1665 get_vm_result(oop_result, java_thread);
1666 }
1667 }
1668
1669 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1670
1671 // Calculate the value for last_Java_sp
1672 // somewhat subtle. call_VM does an intermediate call
1673 // which places a return address on the stack just under the
1674 // stack pointer as the user finished with it. This allows
1675 // use to retrieve last_Java_pc from last_Java_sp[-1].
1676 // On 32bit we then have to push additional args on the stack to accomplish
1677 // the actual requested call. On 64bit call_VM only can use register args
1678 // so the only extra space is the return address that call_VM created.
1679 // This hopefully explains the calculations here.
1680
1681 #ifdef _LP64
1682 // We've pushed one address, correct last_Java_sp
1683 lea(rax, Address(rsp, wordSize));
1684 #else
1685 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1686 #endif // LP64
1687
1688 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1689
1690 }
1691
1692 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1693 void MacroAssembler::call_VM_leaf0(address entry_point) {
1694 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1695 }
1696
1697 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1698 call_VM_leaf_base(entry_point, number_of_arguments);
1699 }
1700
1701 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1702 pass_arg0(this, arg_0);
1703 call_VM_leaf(entry_point, 1);
1704 }
1705
1706 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1707
1708 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1709 pass_arg1(this, arg_1);
1710 pass_arg0(this, arg_0);
1711 call_VM_leaf(entry_point, 2);
1712 }
1713
1714 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1715 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1716 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1717 pass_arg2(this, arg_2);
1718 pass_arg1(this, arg_1);
1719 pass_arg0(this, arg_0);
1720 call_VM_leaf(entry_point, 3);
1721 }
1722
1723 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1724 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1725 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1726 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1727 pass_arg3(this, arg_3);
1728 pass_arg2(this, arg_2);
1729 pass_arg1(this, arg_1);
1730 pass_arg0(this, arg_0);
1731 call_VM_leaf(entry_point, 3);
1732 }
1733
1734 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1735 pass_arg0(this, arg_0);
1736 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1737 }
1738
1739 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1740 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1741 pass_arg1(this, arg_1);
1742 pass_arg0(this, arg_0);
1743 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1744 }
1745
1746 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1747 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1748 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1749 pass_arg2(this, arg_2);
1750 pass_arg1(this, arg_1);
1751 pass_arg0(this, arg_0);
1752 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1753 }
1754
1755 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1756 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1757 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1758 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1759 pass_arg3(this, arg_3);
1760 pass_arg2(this, arg_2);
1761 pass_arg1(this, arg_1);
1762 pass_arg0(this, arg_0);
1763 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1764 }
1765
1766 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1767 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1768 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1769 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1770 }
1771
1772 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1773 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1774 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1775 }
1776
1777 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1778 }
1779
1780 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1781 }
1782
1783 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1784 assert(rscratch != noreg || always_reachable(src1), "missing");
1785
1786 if (reachable(src1)) {
1787 cmpl(as_Address(src1), imm);
1788 } else {
1789 lea(rscratch, src1);
1790 cmpl(Address(rscratch, 0), imm);
1791 }
1792 }
1793
1794 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1795 assert(!src2.is_lval(), "use cmpptr");
1796 assert(rscratch != noreg || always_reachable(src2), "missing");
1797
1798 if (reachable(src2)) {
1799 cmpl(src1, as_Address(src2));
1800 } else {
1801 lea(rscratch, src2);
1802 cmpl(src1, Address(rscratch, 0));
1803 }
1804 }
1805
1806 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1807 Assembler::cmpl(src1, imm);
1808 }
1809
1810 void MacroAssembler::cmp32(Register src1, Address src2) {
1811 Assembler::cmpl(src1, src2);
1812 }
1813
1814 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1815 ucomisd(opr1, opr2);
1816
1817 Label L;
1818 if (unordered_is_less) {
1819 movl(dst, -1);
1820 jcc(Assembler::parity, L);
1821 jcc(Assembler::below , L);
1822 movl(dst, 0);
1823 jcc(Assembler::equal , L);
1824 increment(dst);
1825 } else { // unordered is greater
1826 movl(dst, 1);
1827 jcc(Assembler::parity, L);
1828 jcc(Assembler::above , L);
1829 movl(dst, 0);
1830 jcc(Assembler::equal , L);
1831 decrementl(dst);
1832 }
1833 bind(L);
1834 }
1835
1836 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1837 ucomiss(opr1, opr2);
1838
1839 Label L;
1840 if (unordered_is_less) {
1841 movl(dst, -1);
1842 jcc(Assembler::parity, L);
1843 jcc(Assembler::below , L);
1844 movl(dst, 0);
1845 jcc(Assembler::equal , L);
1846 increment(dst);
1847 } else { // unordered is greater
1848 movl(dst, 1);
1849 jcc(Assembler::parity, L);
1850 jcc(Assembler::above , L);
1851 movl(dst, 0);
1852 jcc(Assembler::equal , L);
1853 decrementl(dst);
1854 }
1855 bind(L);
1856 }
1857
1858
1859 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1860 assert(rscratch != noreg || always_reachable(src1), "missing");
1861
1862 if (reachable(src1)) {
1863 cmpb(as_Address(src1), imm);
1864 } else {
1865 lea(rscratch, src1);
1866 cmpb(Address(rscratch, 0), imm);
1867 }
1868 }
1869
1870 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1871 #ifdef _LP64
1872 assert(rscratch != noreg || always_reachable(src2), "missing");
1873
1874 if (src2.is_lval()) {
1875 movptr(rscratch, src2);
1876 Assembler::cmpq(src1, rscratch);
1877 } else if (reachable(src2)) {
1878 cmpq(src1, as_Address(src2));
1879 } else {
1880 lea(rscratch, src2);
1881 Assembler::cmpq(src1, Address(rscratch, 0));
1882 }
1883 #else
1884 assert(rscratch == noreg, "not needed");
1885 if (src2.is_lval()) {
1886 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1887 } else {
1888 cmpl(src1, as_Address(src2));
1889 }
1890 #endif // _LP64
1891 }
1892
1893 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1894 assert(src2.is_lval(), "not a mem-mem compare");
1895 #ifdef _LP64
1896 // moves src2's literal address
1897 movptr(rscratch, src2);
1898 Assembler::cmpq(src1, rscratch);
1899 #else
1900 assert(rscratch == noreg, "not needed");
1901 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1902 #endif // _LP64
1903 }
1904
1905 void MacroAssembler::cmpoop(Register src1, Register src2) {
1906 cmpptr(src1, src2);
1907 }
1908
1909 void MacroAssembler::cmpoop(Register src1, Address src2) {
1910 cmpptr(src1, src2);
1911 }
1912
1913 #ifdef _LP64
1914 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1915 movoop(rscratch, src2);
1916 cmpptr(src1, rscratch);
1917 }
1918 #endif
1919
1920 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1921 assert(rscratch != noreg || always_reachable(adr), "missing");
1922
1923 if (reachable(adr)) {
1924 lock();
1925 cmpxchgptr(reg, as_Address(adr));
1926 } else {
1927 lea(rscratch, adr);
1928 lock();
1929 cmpxchgptr(reg, Address(rscratch, 0));
1930 }
1931 }
1932
1933 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1934 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1935 }
1936
1937 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1938 assert(rscratch != noreg || always_reachable(src), "missing");
1939
1940 if (reachable(src)) {
1941 Assembler::comisd(dst, as_Address(src));
1942 } else {
1943 lea(rscratch, src);
1944 Assembler::comisd(dst, Address(rscratch, 0));
1945 }
1946 }
1947
1948 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1949 assert(rscratch != noreg || always_reachable(src), "missing");
1950
1951 if (reachable(src)) {
1952 Assembler::comiss(dst, as_Address(src));
1953 } else {
1954 lea(rscratch, src);
1955 Assembler::comiss(dst, Address(rscratch, 0));
1956 }
1957 }
1958
1959
1960 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1961 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1962
1963 Condition negated_cond = negate_condition(cond);
1964 Label L;
1965 jcc(negated_cond, L);
1966 pushf(); // Preserve flags
1967 atomic_incl(counter_addr, rscratch);
1968 popf();
1969 bind(L);
1970 }
1971
1972 int MacroAssembler::corrected_idivl(Register reg) {
1973 // Full implementation of Java idiv and irem; checks for
1974 // special case as described in JVM spec., p.243 & p.271.
1975 // The function returns the (pc) offset of the idivl
1976 // instruction - may be needed for implicit exceptions.
1977 //
1978 // normal case special case
1979 //
1980 // input : rax,: dividend min_int
1981 // reg: divisor (may not be rax,/rdx) -1
1982 //
1983 // output: rax,: quotient (= rax, idiv reg) min_int
1984 // rdx: remainder (= rax, irem reg) 0
1985 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1986 const int min_int = 0x80000000;
1987 Label normal_case, special_case;
1988
1989 // check for special case
1990 cmpl(rax, min_int);
1991 jcc(Assembler::notEqual, normal_case);
1992 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1993 cmpl(reg, -1);
1994 jcc(Assembler::equal, special_case);
1995
1996 // handle normal case
1997 bind(normal_case);
1998 cdql();
1999 int idivl_offset = offset();
2000 idivl(reg);
2001
2002 // normal and special case exit
2003 bind(special_case);
2004
2005 return idivl_offset;
2006 }
2007
2008
2009
2010 void MacroAssembler::decrementl(Register reg, int value) {
2011 if (value == min_jint) {subl(reg, value) ; return; }
2012 if (value < 0) { incrementl(reg, -value); return; }
2013 if (value == 0) { ; return; }
2014 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2015 /* else */ { subl(reg, value) ; return; }
2016 }
2017
2018 void MacroAssembler::decrementl(Address dst, int value) {
2019 if (value == min_jint) {subl(dst, value) ; return; }
2020 if (value < 0) { incrementl(dst, -value); return; }
2021 if (value == 0) { ; return; }
2022 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2023 /* else */ { subl(dst, value) ; return; }
2024 }
2025
2026 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2027 assert(shift_value > 0, "illegal shift value");
2028 Label _is_positive;
2029 testl (reg, reg);
2030 jcc (Assembler::positive, _is_positive);
2031 int offset = (1 << shift_value) - 1 ;
2032
2033 if (offset == 1) {
2034 incrementl(reg);
2035 } else {
2036 addl(reg, offset);
2037 }
2038
2039 bind (_is_positive);
2040 sarl(reg, shift_value);
2041 }
2042
2043 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2044 assert(rscratch != noreg || always_reachable(src), "missing");
2045
2046 if (reachable(src)) {
2047 Assembler::divsd(dst, as_Address(src));
2048 } else {
2049 lea(rscratch, src);
2050 Assembler::divsd(dst, Address(rscratch, 0));
2051 }
2052 }
2053
2054 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2055 assert(rscratch != noreg || always_reachable(src), "missing");
2056
2057 if (reachable(src)) {
2058 Assembler::divss(dst, as_Address(src));
2059 } else {
2060 lea(rscratch, src);
2061 Assembler::divss(dst, Address(rscratch, 0));
2062 }
2063 }
2064
2065 void MacroAssembler::enter() {
2066 push(rbp);
2067 mov(rbp, rsp);
2068 }
2069
2070 void MacroAssembler::post_call_nop() {
2071 if (!Continuations::enabled()) {
2072 return;
2073 }
2074 InstructionMark im(this);
2075 relocate(post_call_nop_Relocation::spec());
2076 InlineSkippedInstructionsCounter skipCounter(this);
2077 emit_int8((uint8_t)0x0f);
2078 emit_int8((uint8_t)0x1f);
2079 emit_int8((uint8_t)0x84);
2080 emit_int8((uint8_t)0x00);
2081 emit_int32(0x00);
2082 }
2083
2084 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2085 void MacroAssembler::fat_nop() {
2086 if (UseAddressNop) {
2087 addr_nop_5();
2088 } else {
2089 emit_int8((uint8_t)0x26); // es:
2090 emit_int8((uint8_t)0x2e); // cs:
2091 emit_int8((uint8_t)0x64); // fs:
2092 emit_int8((uint8_t)0x65); // gs:
2093 emit_int8((uint8_t)0x90);
2094 }
2095 }
2096
2097 #ifndef _LP64
2098 void MacroAssembler::fcmp(Register tmp) {
2099 fcmp(tmp, 1, true, true);
2100 }
2101
2102 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2103 assert(!pop_right || pop_left, "usage error");
2104 if (VM_Version::supports_cmov()) {
2105 assert(tmp == noreg, "unneeded temp");
2106 if (pop_left) {
2107 fucomip(index);
2108 } else {
2109 fucomi(index);
2110 }
2111 if (pop_right) {
2112 fpop();
2113 }
2114 } else {
2115 assert(tmp != noreg, "need temp");
2116 if (pop_left) {
2117 if (pop_right) {
2118 fcompp();
2119 } else {
2120 fcomp(index);
2121 }
2122 } else {
2123 fcom(index);
2124 }
2125 // convert FPU condition into eflags condition via rax,
2126 save_rax(tmp);
2127 fwait(); fnstsw_ax();
2128 sahf();
2129 restore_rax(tmp);
2130 }
2131 // condition codes set as follows:
2132 //
2133 // CF (corresponds to C0) if x < y
2134 // PF (corresponds to C2) if unordered
2135 // ZF (corresponds to C3) if x = y
2136 }
2137
2138 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2139 fcmp2int(dst, unordered_is_less, 1, true, true);
2140 }
2141
2142 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2143 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2144 Label L;
2145 if (unordered_is_less) {
2146 movl(dst, -1);
2147 jcc(Assembler::parity, L);
2148 jcc(Assembler::below , L);
2149 movl(dst, 0);
2150 jcc(Assembler::equal , L);
2151 increment(dst);
2152 } else { // unordered is greater
2153 movl(dst, 1);
2154 jcc(Assembler::parity, L);
2155 jcc(Assembler::above , L);
2156 movl(dst, 0);
2157 jcc(Assembler::equal , L);
2158 decrementl(dst);
2159 }
2160 bind(L);
2161 }
2162
2163 void MacroAssembler::fld_d(AddressLiteral src) {
2164 fld_d(as_Address(src));
2165 }
2166
2167 void MacroAssembler::fld_s(AddressLiteral src) {
2168 fld_s(as_Address(src));
2169 }
2170
2171 void MacroAssembler::fldcw(AddressLiteral src) {
2172 fldcw(as_Address(src));
2173 }
2174
2175 void MacroAssembler::fpop() {
2176 ffree();
2177 fincstp();
2178 }
2179
2180 void MacroAssembler::fremr(Register tmp) {
2181 save_rax(tmp);
2182 { Label L;
2183 bind(L);
2184 fprem();
2185 fwait(); fnstsw_ax();
2186 sahf();
2187 jcc(Assembler::parity, L);
2188 }
2189 restore_rax(tmp);
2190 // Result is in ST0.
2191 // Note: fxch & fpop to get rid of ST1
2192 // (otherwise FPU stack could overflow eventually)
2193 fxch(1);
2194 fpop();
2195 }
2196
2197 void MacroAssembler::empty_FPU_stack() {
2198 if (VM_Version::supports_mmx()) {
2199 emms();
2200 } else {
2201 for (int i = 8; i-- > 0; ) ffree(i);
2202 }
2203 }
2204 #endif // !LP64
2205
2206 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2207 assert(rscratch != noreg || always_reachable(src), "missing");
2208 if (reachable(src)) {
2209 Assembler::mulpd(dst, as_Address(src));
2210 } else {
2211 lea(rscratch, src);
2212 Assembler::mulpd(dst, Address(rscratch, 0));
2213 }
2214 }
2215
2216 void MacroAssembler::load_float(Address src) {
2217 #ifdef _LP64
2218 movflt(xmm0, src);
2219 #else
2220 if (UseSSE >= 1) {
2221 movflt(xmm0, src);
2222 } else {
2223 fld_s(src);
2224 }
2225 #endif // LP64
2226 }
2227
2228 void MacroAssembler::store_float(Address dst) {
2229 #ifdef _LP64
2230 movflt(dst, xmm0);
2231 #else
2232 if (UseSSE >= 1) {
2233 movflt(dst, xmm0);
2234 } else {
2235 fstp_s(dst);
2236 }
2237 #endif // LP64
2238 }
2239
2240 void MacroAssembler::load_double(Address src) {
2241 #ifdef _LP64
2242 movdbl(xmm0, src);
2243 #else
2244 if (UseSSE >= 2) {
2245 movdbl(xmm0, src);
2246 } else {
2247 fld_d(src);
2248 }
2249 #endif // LP64
2250 }
2251
2252 void MacroAssembler::store_double(Address dst) {
2253 #ifdef _LP64
2254 movdbl(dst, xmm0);
2255 #else
2256 if (UseSSE >= 2) {
2257 movdbl(dst, xmm0);
2258 } else {
2259 fstp_d(dst);
2260 }
2261 #endif // LP64
2262 }
2263
2264 // dst = c = a * b + c
2265 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2266 Assembler::vfmadd231sd(c, a, b);
2267 if (dst != c) {
2268 movdbl(dst, c);
2269 }
2270 }
2271
2272 // dst = c = a * b + c
2273 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2274 Assembler::vfmadd231ss(c, a, b);
2275 if (dst != c) {
2276 movflt(dst, c);
2277 }
2278 }
2279
2280 // dst = c = a * b + c
2281 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2282 Assembler::vfmadd231pd(c, a, b, vector_len);
2283 if (dst != c) {
2284 vmovdqu(dst, c);
2285 }
2286 }
2287
2288 // dst = c = a * b + c
2289 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2290 Assembler::vfmadd231ps(c, a, b, vector_len);
2291 if (dst != c) {
2292 vmovdqu(dst, c);
2293 }
2294 }
2295
2296 // dst = c = a * b + c
2297 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2298 Assembler::vfmadd231pd(c, a, b, vector_len);
2299 if (dst != c) {
2300 vmovdqu(dst, c);
2301 }
2302 }
2303
2304 // dst = c = a * b + c
2305 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2306 Assembler::vfmadd231ps(c, a, b, vector_len);
2307 if (dst != c) {
2308 vmovdqu(dst, c);
2309 }
2310 }
2311
2312 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
2313 assert(rscratch != noreg || always_reachable(dst), "missing");
2314
2315 if (reachable(dst)) {
2316 incrementl(as_Address(dst));
2317 } else {
2318 lea(rscratch, dst);
2319 incrementl(Address(rscratch, 0));
2320 }
2321 }
2322
2323 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
2324 incrementl(as_Address(dst, rscratch));
2325 }
2326
2327 void MacroAssembler::incrementl(Register reg, int value) {
2328 if (value == min_jint) {addl(reg, value) ; return; }
2329 if (value < 0) { decrementl(reg, -value); return; }
2330 if (value == 0) { ; return; }
2331 if (value == 1 && UseIncDec) { incl(reg) ; return; }
2332 /* else */ { addl(reg, value) ; return; }
2333 }
2334
2335 void MacroAssembler::incrementl(Address dst, int value) {
2336 if (value == min_jint) {addl(dst, value) ; return; }
2337 if (value < 0) { decrementl(dst, -value); return; }
2338 if (value == 0) { ; return; }
2339 if (value == 1 && UseIncDec) { incl(dst) ; return; }
2340 /* else */ { addl(dst, value) ; return; }
2341 }
2342
2343 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
2344 assert(rscratch != noreg || always_reachable(dst), "missing");
2345 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
2346 if (reachable(dst)) {
2347 jmp_literal(dst.target(), dst.rspec());
2348 } else {
2349 lea(rscratch, dst);
2350 jmp(rscratch);
2351 }
2352 }
2353
2354 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
2355 assert(rscratch != noreg || always_reachable(dst), "missing");
2356 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
2357 if (reachable(dst)) {
2358 InstructionMark im(this);
2359 relocate(dst.reloc());
2360 const int short_size = 2;
2361 const int long_size = 6;
2362 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2363 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2364 // 0111 tttn #8-bit disp
2365 emit_int8(0x70 | cc);
2366 emit_int8((offs - short_size) & 0xFF);
2367 } else {
2368 // 0000 1111 1000 tttn #32-bit disp
2369 emit_int8(0x0F);
2370 emit_int8((unsigned char)(0x80 | cc));
2371 emit_int32(offs - long_size);
2372 }
2373 } else {
2374 #ifdef ASSERT
2375 warning("reversing conditional branch");
2376 #endif /* ASSERT */
2377 Label skip;
2378 jccb(reverse[cc], skip);
2379 lea(rscratch, dst);
2380 Assembler::jmp(rscratch);
2381 bind(skip);
2382 }
2383 }
2384
2385 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
2386 assert(rscratch != noreg || always_reachable(src), "missing");
2387
2388 if (reachable(src)) {
2389 Assembler::ldmxcsr(as_Address(src));
2390 } else {
2391 lea(rscratch, src);
2392 Assembler::ldmxcsr(Address(rscratch, 0));
2393 }
2394 }
2395
2396 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2397 int off;
2398 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2399 off = offset();
2400 movsbl(dst, src); // movsxb
2401 } else {
2402 off = load_unsigned_byte(dst, src);
2403 shll(dst, 24);
2404 sarl(dst, 24);
2405 }
2406 return off;
2407 }
2408
2409 // Note: load_signed_short used to be called load_signed_word.
2410 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2411 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2412 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2413 int MacroAssembler::load_signed_short(Register dst, Address src) {
2414 int off;
2415 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2416 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2417 // version but this is what 64bit has always done. This seems to imply
2418 // that users are only using 32bits worth.
2419 off = offset();
2420 movswl(dst, src); // movsxw
2421 } else {
2422 off = load_unsigned_short(dst, src);
2423 shll(dst, 16);
2424 sarl(dst, 16);
2425 }
2426 return off;
2427 }
2428
2429 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2430 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2431 // and "3.9 Partial Register Penalties", p. 22).
2432 int off;
2433 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2434 off = offset();
2435 movzbl(dst, src); // movzxb
2436 } else {
2437 xorl(dst, dst);
2438 off = offset();
2439 movb(dst, src);
2440 }
2441 return off;
2442 }
2443
2444 // Note: load_unsigned_short used to be called load_unsigned_word.
2445 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2446 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2447 // and "3.9 Partial Register Penalties", p. 22).
2448 int off;
2449 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2450 off = offset();
2451 movzwl(dst, src); // movzxw
2452 } else {
2453 xorl(dst, dst);
2454 off = offset();
2455 movw(dst, src);
2456 }
2457 return off;
2458 }
2459
2460 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2461 switch (size_in_bytes) {
2462 #ifndef _LP64
2463 case 8:
2464 assert(dst2 != noreg, "second dest register required");
2465 movl(dst, src);
2466 movl(dst2, src.plus_disp(BytesPerInt));
2467 break;
2468 #else
2469 case 8: movq(dst, src); break;
2470 #endif
2471 case 4: movl(dst, src); break;
2472 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2473 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2474 default: ShouldNotReachHere();
2475 }
2476 }
2477
2478 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2479 switch (size_in_bytes) {
2480 #ifndef _LP64
2481 case 8:
2482 assert(src2 != noreg, "second source register required");
2483 movl(dst, src);
2484 movl(dst.plus_disp(BytesPerInt), src2);
2485 break;
2486 #else
2487 case 8: movq(dst, src); break;
2488 #endif
2489 case 4: movl(dst, src); break;
2490 case 2: movw(dst, src); break;
2491 case 1: movb(dst, src); break;
2492 default: ShouldNotReachHere();
2493 }
2494 }
2495
2496 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
2497 assert(rscratch != noreg || always_reachable(dst), "missing");
2498
2499 if (reachable(dst)) {
2500 movl(as_Address(dst), src);
2501 } else {
2502 lea(rscratch, dst);
2503 movl(Address(rscratch, 0), src);
2504 }
2505 }
2506
2507 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2508 if (reachable(src)) {
2509 movl(dst, as_Address(src));
2510 } else {
2511 lea(dst, src);
2512 movl(dst, Address(dst, 0));
2513 }
2514 }
2515
2516 // C++ bool manipulation
2517
2518 void MacroAssembler::movbool(Register dst, Address src) {
2519 if(sizeof(bool) == 1)
2520 movb(dst, src);
2521 else if(sizeof(bool) == 2)
2522 movw(dst, src);
2523 else if(sizeof(bool) == 4)
2524 movl(dst, src);
2525 else
2526 // unsupported
2527 ShouldNotReachHere();
2528 }
2529
2530 void MacroAssembler::movbool(Address dst, bool boolconst) {
2531 if(sizeof(bool) == 1)
2532 movb(dst, (int) boolconst);
2533 else if(sizeof(bool) == 2)
2534 movw(dst, (int) boolconst);
2535 else if(sizeof(bool) == 4)
2536 movl(dst, (int) boolconst);
2537 else
2538 // unsupported
2539 ShouldNotReachHere();
2540 }
2541
2542 void MacroAssembler::movbool(Address dst, Register src) {
2543 if(sizeof(bool) == 1)
2544 movb(dst, src);
2545 else if(sizeof(bool) == 2)
2546 movw(dst, src);
2547 else if(sizeof(bool) == 4)
2548 movl(dst, src);
2549 else
2550 // unsupported
2551 ShouldNotReachHere();
2552 }
2553
2554 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2555 assert(rscratch != noreg || always_reachable(src), "missing");
2556
2557 if (reachable(src)) {
2558 movdl(dst, as_Address(src));
2559 } else {
2560 lea(rscratch, src);
2561 movdl(dst, Address(rscratch, 0));
2562 }
2563 }
2564
2565 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
2566 assert(rscratch != noreg || always_reachable(src), "missing");
2567
2568 if (reachable(src)) {
2569 movq(dst, as_Address(src));
2570 } else {
2571 lea(rscratch, src);
2572 movq(dst, Address(rscratch, 0));
2573 }
2574 }
2575
2576 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2577 assert(rscratch != noreg || always_reachable(src), "missing");
2578
2579 if (reachable(src)) {
2580 if (UseXmmLoadAndClearUpper) {
2581 movsd (dst, as_Address(src));
2582 } else {
2583 movlpd(dst, as_Address(src));
2584 }
2585 } else {
2586 lea(rscratch, src);
2587 if (UseXmmLoadAndClearUpper) {
2588 movsd (dst, Address(rscratch, 0));
2589 } else {
2590 movlpd(dst, Address(rscratch, 0));
2591 }
2592 }
2593 }
2594
2595 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
2596 assert(rscratch != noreg || always_reachable(src), "missing");
2597
2598 if (reachable(src)) {
2599 movss(dst, as_Address(src));
2600 } else {
2601 lea(rscratch, src);
2602 movss(dst, Address(rscratch, 0));
2603 }
2604 }
2605
2606 void MacroAssembler::movptr(Register dst, Register src) {
2607 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2608 }
2609
2610 void MacroAssembler::movptr(Register dst, Address src) {
2611 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2612 }
2613
2614 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2615 void MacroAssembler::movptr(Register dst, intptr_t src) {
2616 #ifdef _LP64
2617 if (is_uimm32(src)) {
2618 movl(dst, checked_cast<uint32_t>(src));
2619 } else if (is_simm32(src)) {
2620 movq(dst, checked_cast<int32_t>(src));
2621 } else {
2622 mov64(dst, src);
2623 }
2624 #else
2625 movl(dst, src);
2626 #endif
2627 }
2628
2629 void MacroAssembler::movptr(Address dst, Register src) {
2630 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2631 }
2632
2633 void MacroAssembler::movptr(Address dst, int32_t src) {
2634 LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src));
2635 }
2636
2637 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2638 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2639 Assembler::movdqu(dst, src);
2640 }
2641
2642 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2643 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2644 Assembler::movdqu(dst, src);
2645 }
2646
2647 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2648 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2649 Assembler::movdqu(dst, src);
2650 }
2651
2652 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2653 assert(rscratch != noreg || always_reachable(src), "missing");
2654
2655 if (reachable(src)) {
2656 movdqu(dst, as_Address(src));
2657 } else {
2658 lea(rscratch, src);
2659 movdqu(dst, Address(rscratch, 0));
2660 }
2661 }
2662
2663 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2664 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2665 Assembler::vmovdqu(dst, src);
2666 }
2667
2668 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2669 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2670 Assembler::vmovdqu(dst, src);
2671 }
2672
2673 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2674 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2675 Assembler::vmovdqu(dst, src);
2676 }
2677
2678 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2679 assert(rscratch != noreg || always_reachable(src), "missing");
2680
2681 if (reachable(src)) {
2682 vmovdqu(dst, as_Address(src));
2683 }
2684 else {
2685 lea(rscratch, src);
2686 vmovdqu(dst, Address(rscratch, 0));
2687 }
2688 }
2689
2690 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2691 assert(rscratch != noreg || always_reachable(src), "missing");
2692
2693 if (vector_len == AVX_512bit) {
2694 evmovdquq(dst, src, AVX_512bit, rscratch);
2695 } else if (vector_len == AVX_256bit) {
2696 vmovdqu(dst, src, rscratch);
2697 } else {
2698 movdqu(dst, src, rscratch);
2699 }
2700 }
2701
2702 void MacroAssembler::kmov(KRegister dst, Address src) {
2703 if (VM_Version::supports_avx512bw()) {
2704 kmovql(dst, src);
2705 } else {
2706 assert(VM_Version::supports_evex(), "");
2707 kmovwl(dst, src);
2708 }
2709 }
2710
2711 void MacroAssembler::kmov(Address dst, KRegister src) {
2712 if (VM_Version::supports_avx512bw()) {
2713 kmovql(dst, src);
2714 } else {
2715 assert(VM_Version::supports_evex(), "");
2716 kmovwl(dst, src);
2717 }
2718 }
2719
2720 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2721 if (VM_Version::supports_avx512bw()) {
2722 kmovql(dst, src);
2723 } else {
2724 assert(VM_Version::supports_evex(), "");
2725 kmovwl(dst, src);
2726 }
2727 }
2728
2729 void MacroAssembler::kmov(Register dst, KRegister src) {
2730 if (VM_Version::supports_avx512bw()) {
2731 kmovql(dst, src);
2732 } else {
2733 assert(VM_Version::supports_evex(), "");
2734 kmovwl(dst, src);
2735 }
2736 }
2737
2738 void MacroAssembler::kmov(KRegister dst, Register src) {
2739 if (VM_Version::supports_avx512bw()) {
2740 kmovql(dst, src);
2741 } else {
2742 assert(VM_Version::supports_evex(), "");
2743 kmovwl(dst, src);
2744 }
2745 }
2746
2747 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2748 assert(rscratch != noreg || always_reachable(src), "missing");
2749
2750 if (reachable(src)) {
2751 kmovql(dst, as_Address(src));
2752 } else {
2753 lea(rscratch, src);
2754 kmovql(dst, Address(rscratch, 0));
2755 }
2756 }
2757
2758 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2759 assert(rscratch != noreg || always_reachable(src), "missing");
2760
2761 if (reachable(src)) {
2762 kmovwl(dst, as_Address(src));
2763 } else {
2764 lea(rscratch, src);
2765 kmovwl(dst, Address(rscratch, 0));
2766 }
2767 }
2768
2769 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2770 int vector_len, Register rscratch) {
2771 assert(rscratch != noreg || always_reachable(src), "missing");
2772
2773 if (reachable(src)) {
2774 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2775 } else {
2776 lea(rscratch, src);
2777 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2778 }
2779 }
2780
2781 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2782 int vector_len, Register rscratch) {
2783 assert(rscratch != noreg || always_reachable(src), "missing");
2784
2785 if (reachable(src)) {
2786 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2787 } else {
2788 lea(rscratch, src);
2789 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2790 }
2791 }
2792
2793 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2794 assert(rscratch != noreg || always_reachable(src), "missing");
2795
2796 if (reachable(src)) {
2797 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2798 } else {
2799 lea(rscratch, src);
2800 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2801 }
2802 }
2803
2804 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2805 assert(rscratch != noreg || always_reachable(src), "missing");
2806
2807 if (reachable(src)) {
2808 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2809 } else {
2810 lea(rscratch, src);
2811 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2812 }
2813 }
2814
2815 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2816 assert(rscratch != noreg || always_reachable(src), "missing");
2817
2818 if (reachable(src)) {
2819 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2820 } else {
2821 lea(rscratch, src);
2822 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2823 }
2824 }
2825
2826 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2827 assert(rscratch != noreg || always_reachable(src), "missing");
2828
2829 if (reachable(src)) {
2830 Assembler::movdqa(dst, as_Address(src));
2831 } else {
2832 lea(rscratch, src);
2833 Assembler::movdqa(dst, Address(rscratch, 0));
2834 }
2835 }
2836
2837 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2838 assert(rscratch != noreg || always_reachable(src), "missing");
2839
2840 if (reachable(src)) {
2841 Assembler::movsd(dst, as_Address(src));
2842 } else {
2843 lea(rscratch, src);
2844 Assembler::movsd(dst, Address(rscratch, 0));
2845 }
2846 }
2847
2848 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2849 assert(rscratch != noreg || always_reachable(src), "missing");
2850
2851 if (reachable(src)) {
2852 Assembler::movss(dst, as_Address(src));
2853 } else {
2854 lea(rscratch, src);
2855 Assembler::movss(dst, Address(rscratch, 0));
2856 }
2857 }
2858
2859 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2860 assert(rscratch != noreg || always_reachable(src), "missing");
2861
2862 if (reachable(src)) {
2863 Assembler::movddup(dst, as_Address(src));
2864 } else {
2865 lea(rscratch, src);
2866 Assembler::movddup(dst, Address(rscratch, 0));
2867 }
2868 }
2869
2870 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2871 assert(rscratch != noreg || always_reachable(src), "missing");
2872
2873 if (reachable(src)) {
2874 Assembler::vmovddup(dst, as_Address(src), vector_len);
2875 } else {
2876 lea(rscratch, src);
2877 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2878 }
2879 }
2880
2881 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2882 assert(rscratch != noreg || always_reachable(src), "missing");
2883
2884 if (reachable(src)) {
2885 Assembler::mulsd(dst, as_Address(src));
2886 } else {
2887 lea(rscratch, src);
2888 Assembler::mulsd(dst, Address(rscratch, 0));
2889 }
2890 }
2891
2892 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2893 assert(rscratch != noreg || always_reachable(src), "missing");
2894
2895 if (reachable(src)) {
2896 Assembler::mulss(dst, as_Address(src));
2897 } else {
2898 lea(rscratch, src);
2899 Assembler::mulss(dst, Address(rscratch, 0));
2900 }
2901 }
2902
2903 void MacroAssembler::null_check(Register reg, int offset) {
2904 if (needs_explicit_null_check(offset)) {
2905 // provoke OS null exception if reg is null by
2906 // accessing M[reg] w/o changing any (non-CC) registers
2907 // NOTE: cmpl is plenty here to provoke a segv
2908 cmpptr(rax, Address(reg, 0));
2909 // Note: should probably use testl(rax, Address(reg, 0));
2910 // may be shorter code (however, this version of
2911 // testl needs to be implemented first)
2912 } else {
2913 // nothing to do, (later) access of M[reg + offset]
2914 // will provoke OS null exception if reg is null
2915 }
2916 }
2917
2918 void MacroAssembler::os_breakpoint() {
2919 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2920 // (e.g., MSVC can't call ps() otherwise)
2921 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2922 }
2923
2924 void MacroAssembler::unimplemented(const char* what) {
2925 const char* buf = nullptr;
2926 {
2927 ResourceMark rm;
2928 stringStream ss;
2929 ss.print("unimplemented: %s", what);
2930 buf = code_string(ss.as_string());
2931 }
2932 stop(buf);
2933 }
2934
2935 #ifdef _LP64
2936 #define XSTATE_BV 0x200
2937 #endif
2938
2939 void MacroAssembler::pop_CPU_state() {
2940 pop_FPU_state();
2941 pop_IU_state();
2942 }
2943
2944 void MacroAssembler::pop_FPU_state() {
2945 #ifndef _LP64
2946 frstor(Address(rsp, 0));
2947 #else
2948 fxrstor(Address(rsp, 0));
2949 #endif
2950 addptr(rsp, FPUStateSizeInWords * wordSize);
2951 }
2952
2953 void MacroAssembler::pop_IU_state() {
2954 popa();
2955 LP64_ONLY(addq(rsp, 8));
2956 popf();
2957 }
2958
2959 // Save Integer and Float state
2960 // Warning: Stack must be 16 byte aligned (64bit)
2961 void MacroAssembler::push_CPU_state() {
2962 push_IU_state();
2963 push_FPU_state();
2964 }
2965
2966 void MacroAssembler::push_FPU_state() {
2967 subptr(rsp, FPUStateSizeInWords * wordSize);
2968 #ifndef _LP64
2969 fnsave(Address(rsp, 0));
2970 fwait();
2971 #else
2972 fxsave(Address(rsp, 0));
2973 #endif // LP64
2974 }
2975
2976 void MacroAssembler::push_IU_state() {
2977 // Push flags first because pusha kills them
2978 pushf();
2979 // Make sure rsp stays 16-byte aligned
2980 LP64_ONLY(subq(rsp, 8));
2981 pusha();
2982 }
2983
2984 void MacroAssembler::push_cont_fastpath() {
2985 if (!Continuations::enabled()) return;
2986
2987 #ifndef _LP64
2988 Register rthread = rax;
2989 Register rrealsp = rbx;
2990 push(rthread);
2991 push(rrealsp);
2992
2993 get_thread(rthread);
2994
2995 // The code below wants the original RSP.
2996 // Move it back after the pushes above.
2997 movptr(rrealsp, rsp);
2998 addptr(rrealsp, 2*wordSize);
2999 #else
3000 Register rthread = r15_thread;
3001 Register rrealsp = rsp;
3002 #endif
3003
3004 Label done;
3005 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3006 jccb(Assembler::belowEqual, done);
3007 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), rrealsp);
3008 bind(done);
3009
3010 #ifndef _LP64
3011 pop(rrealsp);
3012 pop(rthread);
3013 #endif
3014 }
3015
3016 void MacroAssembler::pop_cont_fastpath() {
3017 if (!Continuations::enabled()) return;
3018
3019 #ifndef _LP64
3020 Register rthread = rax;
3021 Register rrealsp = rbx;
3022 push(rthread);
3023 push(rrealsp);
3024
3025 get_thread(rthread);
3026
3027 // The code below wants the original RSP.
3028 // Move it back after the pushes above.
3029 movptr(rrealsp, rsp);
3030 addptr(rrealsp, 2*wordSize);
3031 #else
3032 Register rthread = r15_thread;
3033 Register rrealsp = rsp;
3034 #endif
3035
3036 Label done;
3037 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3038 jccb(Assembler::below, done);
3039 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), 0);
3040 bind(done);
3041
3042 #ifndef _LP64
3043 pop(rrealsp);
3044 pop(rthread);
3045 #endif
3046 }
3047
3048 void MacroAssembler::inc_held_monitor_count() {
3049 #ifdef _LP64
3050 incrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3051 #endif
3052 }
3053
3054 void MacroAssembler::dec_held_monitor_count() {
3055 #ifdef _LP64
3056 decrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3057 #endif
3058 }
3059
3060 #ifdef ASSERT
3061 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
3062 #ifdef _LP64
3063 Label no_cont;
3064 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
3065 testl(cont, cont);
3066 jcc(Assembler::zero, no_cont);
3067 stop(name);
3068 bind(no_cont);
3069 #else
3070 Unimplemented();
3071 #endif
3072 }
3073 #endif
3074
3075 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3076 if (!java_thread->is_valid()) {
3077 java_thread = rdi;
3078 get_thread(java_thread);
3079 }
3080 // we must set sp to zero to clear frame
3081 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3082 // must clear fp, so that compiled frames are not confused; it is
3083 // possible that we need it only for debugging
3084 if (clear_fp) {
3085 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3086 }
3087 // Always clear the pc because it could have been set by make_walkable()
3088 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3089 vzeroupper();
3090 }
3091
3092 void MacroAssembler::restore_rax(Register tmp) {
3093 if (tmp == noreg) pop(rax);
3094 else if (tmp != rax) mov(rax, tmp);
3095 }
3096
3097 void MacroAssembler::round_to(Register reg, int modulus) {
3098 addptr(reg, modulus - 1);
3099 andptr(reg, -modulus);
3100 }
3101
3102 void MacroAssembler::save_rax(Register tmp) {
3103 if (tmp == noreg) push(rax);
3104 else if (tmp != rax) mov(tmp, rax);
3105 }
3106
3107 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
3108 if (at_return) {
3109 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
3110 // we may safely use rsp instead to perform the stack watermark check.
3111 cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
3112 jcc(Assembler::above, slow_path);
3113 return;
3114 }
3115 testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
3116 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3117 }
3118
3119 // Calls to C land
3120 //
3121 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3122 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3123 // has to be reset to 0. This is required to allow proper stack traversal.
3124 void MacroAssembler::set_last_Java_frame(Register java_thread,
3125 Register last_java_sp,
3126 Register last_java_fp,
3127 address last_java_pc,
3128 Register rscratch) {
3129 vzeroupper();
3130 // determine java_thread register
3131 if (!java_thread->is_valid()) {
3132 java_thread = rdi;
3133 get_thread(java_thread);
3134 }
3135 // determine last_java_sp register
3136 if (!last_java_sp->is_valid()) {
3137 last_java_sp = rsp;
3138 }
3139 // last_java_fp is optional
3140 if (last_java_fp->is_valid()) {
3141 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3142 }
3143 // last_java_pc is optional
3144 if (last_java_pc != nullptr) {
3145 Address java_pc(java_thread,
3146 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
3147 lea(java_pc, InternalAddress(last_java_pc), rscratch);
3148 }
3149 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3150 }
3151
3152 #ifdef _LP64
3153 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
3154 Register last_java_fp,
3155 Label &L,
3156 Register scratch) {
3157 lea(scratch, L);
3158 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
3159 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, nullptr, scratch);
3160 }
3161 #endif
3162
3163 void MacroAssembler::shlptr(Register dst, int imm8) {
3164 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3165 }
3166
3167 void MacroAssembler::shrptr(Register dst, int imm8) {
3168 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3169 }
3170
3171 void MacroAssembler::sign_extend_byte(Register reg) {
3172 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3173 movsbl(reg, reg); // movsxb
3174 } else {
3175 shll(reg, 24);
3176 sarl(reg, 24);
3177 }
3178 }
3179
3180 void MacroAssembler::sign_extend_short(Register reg) {
3181 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3182 movswl(reg, reg); // movsxw
3183 } else {
3184 shll(reg, 16);
3185 sarl(reg, 16);
3186 }
3187 }
3188
3189 void MacroAssembler::testl(Address dst, int32_t imm32) {
3190 if (imm32 >= 0 && is8bit(imm32)) {
3191 testb(dst, imm32);
3192 } else {
3193 Assembler::testl(dst, imm32);
3194 }
3195 }
3196
3197 void MacroAssembler::testl(Register dst, int32_t imm32) {
3198 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
3199 testb(dst, imm32);
3200 } else {
3201 Assembler::testl(dst, imm32);
3202 }
3203 }
3204
3205 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3206 assert(always_reachable(src), "Address should be reachable");
3207 testl(dst, as_Address(src));
3208 }
3209
3210 #ifdef _LP64
3211
3212 void MacroAssembler::testq(Address dst, int32_t imm32) {
3213 if (imm32 >= 0) {
3214 testl(dst, imm32);
3215 } else {
3216 Assembler::testq(dst, imm32);
3217 }
3218 }
3219
3220 void MacroAssembler::testq(Register dst, int32_t imm32) {
3221 if (imm32 >= 0) {
3222 testl(dst, imm32);
3223 } else {
3224 Assembler::testq(dst, imm32);
3225 }
3226 }
3227
3228 #endif
3229
3230 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3231 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3232 Assembler::pcmpeqb(dst, src);
3233 }
3234
3235 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3236 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3237 Assembler::pcmpeqw(dst, src);
3238 }
3239
3240 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3241 assert((dst->encoding() < 16),"XMM register should be 0-15");
3242 Assembler::pcmpestri(dst, src, imm8);
3243 }
3244
3245 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3246 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3247 Assembler::pcmpestri(dst, src, imm8);
3248 }
3249
3250 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3251 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3252 Assembler::pmovzxbw(dst, src);
3253 }
3254
3255 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3256 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3257 Assembler::pmovzxbw(dst, src);
3258 }
3259
3260 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3261 assert((src->encoding() < 16),"XMM register should be 0-15");
3262 Assembler::pmovmskb(dst, src);
3263 }
3264
3265 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3266 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3267 Assembler::ptest(dst, src);
3268 }
3269
3270 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3271 assert(rscratch != noreg || always_reachable(src), "missing");
3272
3273 if (reachable(src)) {
3274 Assembler::sqrtss(dst, as_Address(src));
3275 } else {
3276 lea(rscratch, src);
3277 Assembler::sqrtss(dst, Address(rscratch, 0));
3278 }
3279 }
3280
3281 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3282 assert(rscratch != noreg || always_reachable(src), "missing");
3283
3284 if (reachable(src)) {
3285 Assembler::subsd(dst, as_Address(src));
3286 } else {
3287 lea(rscratch, src);
3288 Assembler::subsd(dst, Address(rscratch, 0));
3289 }
3290 }
3291
3292 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
3293 assert(rscratch != noreg || always_reachable(src), "missing");
3294
3295 if (reachable(src)) {
3296 Assembler::roundsd(dst, as_Address(src), rmode);
3297 } else {
3298 lea(rscratch, src);
3299 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
3300 }
3301 }
3302
3303 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3304 assert(rscratch != noreg || always_reachable(src), "missing");
3305
3306 if (reachable(src)) {
3307 Assembler::subss(dst, as_Address(src));
3308 } else {
3309 lea(rscratch, src);
3310 Assembler::subss(dst, Address(rscratch, 0));
3311 }
3312 }
3313
3314 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3315 assert(rscratch != noreg || always_reachable(src), "missing");
3316
3317 if (reachable(src)) {
3318 Assembler::ucomisd(dst, as_Address(src));
3319 } else {
3320 lea(rscratch, src);
3321 Assembler::ucomisd(dst, Address(rscratch, 0));
3322 }
3323 }
3324
3325 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3326 assert(rscratch != noreg || always_reachable(src), "missing");
3327
3328 if (reachable(src)) {
3329 Assembler::ucomiss(dst, as_Address(src));
3330 } else {
3331 lea(rscratch, src);
3332 Assembler::ucomiss(dst, Address(rscratch, 0));
3333 }
3334 }
3335
3336 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3337 assert(rscratch != noreg || always_reachable(src), "missing");
3338
3339 // Used in sign-bit flipping with aligned address.
3340 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3341
3342 if (UseAVX > 2 &&
3343 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3344 (dst->encoding() >= 16)) {
3345 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
3346 } else if (reachable(src)) {
3347 Assembler::xorpd(dst, as_Address(src));
3348 } else {
3349 lea(rscratch, src);
3350 Assembler::xorpd(dst, Address(rscratch, 0));
3351 }
3352 }
3353
3354 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3355 if (UseAVX > 2 &&
3356 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3357 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
3358 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3359 } else {
3360 Assembler::xorpd(dst, src);
3361 }
3362 }
3363
3364 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3365 if (UseAVX > 2 &&
3366 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3367 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
3368 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3369 } else {
3370 Assembler::xorps(dst, src);
3371 }
3372 }
3373
3374 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
3375 assert(rscratch != noreg || always_reachable(src), "missing");
3376
3377 // Used in sign-bit flipping with aligned address.
3378 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3379
3380 if (UseAVX > 2 &&
3381 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3382 (dst->encoding() >= 16)) {
3383 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
3384 } else if (reachable(src)) {
3385 Assembler::xorps(dst, as_Address(src));
3386 } else {
3387 lea(rscratch, src);
3388 Assembler::xorps(dst, Address(rscratch, 0));
3389 }
3390 }
3391
3392 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
3393 assert(rscratch != noreg || always_reachable(src), "missing");
3394
3395 // Used in sign-bit flipping with aligned address.
3396 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3397 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3398 if (reachable(src)) {
3399 Assembler::pshufb(dst, as_Address(src));
3400 } else {
3401 lea(rscratch, src);
3402 Assembler::pshufb(dst, Address(rscratch, 0));
3403 }
3404 }
3405
3406 // AVX 3-operands instructions
3407
3408 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3409 assert(rscratch != noreg || always_reachable(src), "missing");
3410
3411 if (reachable(src)) {
3412 vaddsd(dst, nds, as_Address(src));
3413 } else {
3414 lea(rscratch, src);
3415 vaddsd(dst, nds, Address(rscratch, 0));
3416 }
3417 }
3418
3419 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3420 assert(rscratch != noreg || always_reachable(src), "missing");
3421
3422 if (reachable(src)) {
3423 vaddss(dst, nds, as_Address(src));
3424 } else {
3425 lea(rscratch, src);
3426 vaddss(dst, nds, Address(rscratch, 0));
3427 }
3428 }
3429
3430 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3431 assert(UseAVX > 0, "requires some form of AVX");
3432 assert(rscratch != noreg || always_reachable(src), "missing");
3433
3434 if (reachable(src)) {
3435 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3436 } else {
3437 lea(rscratch, src);
3438 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3439 }
3440 }
3441
3442 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3443 assert(UseAVX > 0, "requires some form of AVX");
3444 assert(rscratch != noreg || always_reachable(src), "missing");
3445
3446 if (reachable(src)) {
3447 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3448 } else {
3449 lea(rscratch, src);
3450 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3451 }
3452 }
3453
3454 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3455 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3456 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3457
3458 vandps(dst, nds, negate_field, vector_len, rscratch);
3459 }
3460
3461 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3462 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3463 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3464
3465 vandpd(dst, nds, negate_field, vector_len, rscratch);
3466 }
3467
3468 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3469 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3470 Assembler::vpaddb(dst, nds, src, vector_len);
3471 }
3472
3473 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3474 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3475 Assembler::vpaddb(dst, nds, src, vector_len);
3476 }
3477
3478 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3479 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3480 Assembler::vpaddw(dst, nds, src, vector_len);
3481 }
3482
3483 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3484 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3485 Assembler::vpaddw(dst, nds, src, vector_len);
3486 }
3487
3488 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3489 assert(rscratch != noreg || always_reachable(src), "missing");
3490
3491 if (reachable(src)) {
3492 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3493 } else {
3494 lea(rscratch, src);
3495 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
3496 }
3497 }
3498
3499 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3500 assert(rscratch != noreg || always_reachable(src), "missing");
3501
3502 if (reachable(src)) {
3503 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
3504 } else {
3505 lea(rscratch, src);
3506 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
3507 }
3508 }
3509
3510 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3511 assert(rscratch != noreg || always_reachable(src), "missing");
3512
3513 if (reachable(src)) {
3514 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
3515 } else {
3516 lea(rscratch, src);
3517 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
3518 }
3519 }
3520
3521 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3522 assert(rscratch != noreg || always_reachable(src), "missing");
3523
3524 if (reachable(src)) {
3525 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3526 } else {
3527 lea(rscratch, src);
3528 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3529 }
3530 }
3531
3532 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3533 assert(rscratch != noreg || always_reachable(src), "missing");
3534
3535 if (reachable(src)) {
3536 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3537 } else {
3538 lea(rscratch, src);
3539 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3540 }
3541 }
3542
3543 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3544 assert(rscratch != noreg || always_reachable(src), "missing");
3545
3546 if (reachable(src)) {
3547 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3548 } else {
3549 lea(rscratch, src);
3550 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3551 }
3552 }
3553
3554 // Vector float blend
3555 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3556 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3557 // WARN: Allow dst == (src1|src2), mask == scratch
3558 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3559 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3560 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3561 if (blend_emulation && scratch_available && dst_available) {
3562 if (compute_mask) {
3563 vpsrad(scratch, mask, 32, vector_len);
3564 mask = scratch;
3565 }
3566 if (dst == src1) {
3567 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3568 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3569 } else {
3570 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3571 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3572 }
3573 vpor(dst, dst, scratch, vector_len);
3574 } else {
3575 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3576 }
3577 }
3578
3579 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3580 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3581 // WARN: Allow dst == (src1|src2), mask == scratch
3582 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3583 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3584 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3585 if (blend_emulation && scratch_available && dst_available) {
3586 if (compute_mask) {
3587 vpxor(scratch, scratch, scratch, vector_len);
3588 vpcmpgtq(scratch, scratch, mask, vector_len);
3589 mask = scratch;
3590 }
3591 if (dst == src1) {
3592 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3593 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3594 } else {
3595 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3596 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3597 }
3598 vpor(dst, dst, scratch, vector_len);
3599 } else {
3600 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3601 }
3602 }
3603
3604 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3605 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3606 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3607 }
3608
3609 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3610 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3611 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3612 }
3613
3614 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3615 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3616 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3617 }
3618
3619 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3620 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3621 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3622 }
3623
3624 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3625 assert(rscratch != noreg || always_reachable(src), "missing");
3626
3627 if (reachable(src)) {
3628 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3629 } else {
3630 lea(rscratch, src);
3631 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3632 }
3633 }
3634
3635 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3636 int comparison, bool is_signed, int vector_len, Register rscratch) {
3637 assert(rscratch != noreg || always_reachable(src), "missing");
3638
3639 if (reachable(src)) {
3640 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3641 } else {
3642 lea(rscratch, src);
3643 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3644 }
3645 }
3646
3647 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3648 int comparison, bool is_signed, int vector_len, Register rscratch) {
3649 assert(rscratch != noreg || always_reachable(src), "missing");
3650
3651 if (reachable(src)) {
3652 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3653 } else {
3654 lea(rscratch, src);
3655 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3656 }
3657 }
3658
3659 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3660 int comparison, bool is_signed, int vector_len, Register rscratch) {
3661 assert(rscratch != noreg || always_reachable(src), "missing");
3662
3663 if (reachable(src)) {
3664 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3665 } else {
3666 lea(rscratch, src);
3667 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3668 }
3669 }
3670
3671 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3672 int comparison, bool is_signed, int vector_len, Register rscratch) {
3673 assert(rscratch != noreg || always_reachable(src), "missing");
3674
3675 if (reachable(src)) {
3676 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3677 } else {
3678 lea(rscratch, src);
3679 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3680 }
3681 }
3682
3683 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3684 if (width == Assembler::Q) {
3685 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3686 } else {
3687 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3688 }
3689 }
3690
3691 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3692 int eq_cond_enc = 0x29;
3693 int gt_cond_enc = 0x37;
3694 if (width != Assembler::Q) {
3695 eq_cond_enc = 0x74 + width;
3696 gt_cond_enc = 0x64 + width;
3697 }
3698 switch (cond) {
3699 case eq:
3700 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3701 break;
3702 case neq:
3703 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3704 vallones(xtmp, vector_len);
3705 vpxor(dst, xtmp, dst, vector_len);
3706 break;
3707 case le:
3708 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3709 vallones(xtmp, vector_len);
3710 vpxor(dst, xtmp, dst, vector_len);
3711 break;
3712 case nlt:
3713 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3714 vallones(xtmp, vector_len);
3715 vpxor(dst, xtmp, dst, vector_len);
3716 break;
3717 case lt:
3718 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3719 break;
3720 case nle:
3721 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3722 break;
3723 default:
3724 assert(false, "Should not reach here");
3725 }
3726 }
3727
3728 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3729 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3730 Assembler::vpmovzxbw(dst, src, vector_len);
3731 }
3732
3733 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3734 assert((src->encoding() < 16),"XMM register should be 0-15");
3735 Assembler::vpmovmskb(dst, src, vector_len);
3736 }
3737
3738 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3739 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3740 Assembler::vpmullw(dst, nds, src, vector_len);
3741 }
3742
3743 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3744 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3745 Assembler::vpmullw(dst, nds, src, vector_len);
3746 }
3747
3748 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3749 assert((UseAVX > 0), "AVX support is needed");
3750 assert(rscratch != noreg || always_reachable(src), "missing");
3751
3752 if (reachable(src)) {
3753 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3754 } else {
3755 lea(rscratch, src);
3756 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3757 }
3758 }
3759
3760 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3761 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3762 Assembler::vpsubb(dst, nds, src, vector_len);
3763 }
3764
3765 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3766 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3767 Assembler::vpsubb(dst, nds, src, vector_len);
3768 }
3769
3770 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3771 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3772 Assembler::vpsubw(dst, nds, src, vector_len);
3773 }
3774
3775 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3776 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3777 Assembler::vpsubw(dst, nds, src, vector_len);
3778 }
3779
3780 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3781 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3782 Assembler::vpsraw(dst, nds, shift, vector_len);
3783 }
3784
3785 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3786 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3787 Assembler::vpsraw(dst, nds, shift, vector_len);
3788 }
3789
3790 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3791 assert(UseAVX > 2,"");
3792 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3793 vector_len = 2;
3794 }
3795 Assembler::evpsraq(dst, nds, shift, vector_len);
3796 }
3797
3798 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3799 assert(UseAVX > 2,"");
3800 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3801 vector_len = 2;
3802 }
3803 Assembler::evpsraq(dst, nds, shift, vector_len);
3804 }
3805
3806 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3807 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3808 Assembler::vpsrlw(dst, nds, shift, vector_len);
3809 }
3810
3811 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3812 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3813 Assembler::vpsrlw(dst, nds, shift, vector_len);
3814 }
3815
3816 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3817 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3818 Assembler::vpsllw(dst, nds, shift, vector_len);
3819 }
3820
3821 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3822 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3823 Assembler::vpsllw(dst, nds, shift, vector_len);
3824 }
3825
3826 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3827 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3828 Assembler::vptest(dst, src);
3829 }
3830
3831 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3832 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3833 Assembler::punpcklbw(dst, src);
3834 }
3835
3836 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3837 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3838 Assembler::pshufd(dst, src, mode);
3839 }
3840
3841 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3842 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3843 Assembler::pshuflw(dst, src, mode);
3844 }
3845
3846 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3847 assert(rscratch != noreg || always_reachable(src), "missing");
3848
3849 if (reachable(src)) {
3850 vandpd(dst, nds, as_Address(src), vector_len);
3851 } else {
3852 lea(rscratch, src);
3853 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3854 }
3855 }
3856
3857 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3858 assert(rscratch != noreg || always_reachable(src), "missing");
3859
3860 if (reachable(src)) {
3861 vandps(dst, nds, as_Address(src), vector_len);
3862 } else {
3863 lea(rscratch, src);
3864 vandps(dst, nds, Address(rscratch, 0), vector_len);
3865 }
3866 }
3867
3868 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3869 bool merge, int vector_len, Register rscratch) {
3870 assert(rscratch != noreg || always_reachable(src), "missing");
3871
3872 if (reachable(src)) {
3873 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3874 } else {
3875 lea(rscratch, src);
3876 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3877 }
3878 }
3879
3880 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3881 assert(rscratch != noreg || always_reachable(src), "missing");
3882
3883 if (reachable(src)) {
3884 vdivsd(dst, nds, as_Address(src));
3885 } else {
3886 lea(rscratch, src);
3887 vdivsd(dst, nds, Address(rscratch, 0));
3888 }
3889 }
3890
3891 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3892 assert(rscratch != noreg || always_reachable(src), "missing");
3893
3894 if (reachable(src)) {
3895 vdivss(dst, nds, as_Address(src));
3896 } else {
3897 lea(rscratch, src);
3898 vdivss(dst, nds, Address(rscratch, 0));
3899 }
3900 }
3901
3902 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3903 assert(rscratch != noreg || always_reachable(src), "missing");
3904
3905 if (reachable(src)) {
3906 vmulsd(dst, nds, as_Address(src));
3907 } else {
3908 lea(rscratch, src);
3909 vmulsd(dst, nds, Address(rscratch, 0));
3910 }
3911 }
3912
3913 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3914 assert(rscratch != noreg || always_reachable(src), "missing");
3915
3916 if (reachable(src)) {
3917 vmulss(dst, nds, as_Address(src));
3918 } else {
3919 lea(rscratch, src);
3920 vmulss(dst, nds, Address(rscratch, 0));
3921 }
3922 }
3923
3924 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3925 assert(rscratch != noreg || always_reachable(src), "missing");
3926
3927 if (reachable(src)) {
3928 vsubsd(dst, nds, as_Address(src));
3929 } else {
3930 lea(rscratch, src);
3931 vsubsd(dst, nds, Address(rscratch, 0));
3932 }
3933 }
3934
3935 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3936 assert(rscratch != noreg || always_reachable(src), "missing");
3937
3938 if (reachable(src)) {
3939 vsubss(dst, nds, as_Address(src));
3940 } else {
3941 lea(rscratch, src);
3942 vsubss(dst, nds, Address(rscratch, 0));
3943 }
3944 }
3945
3946 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3947 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3948 assert(rscratch != noreg || always_reachable(src), "missing");
3949
3950 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3951 }
3952
3953 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3954 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3955 assert(rscratch != noreg || always_reachable(src), "missing");
3956
3957 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3958 }
3959
3960 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3961 assert(rscratch != noreg || always_reachable(src), "missing");
3962
3963 if (reachable(src)) {
3964 vxorpd(dst, nds, as_Address(src), vector_len);
3965 } else {
3966 lea(rscratch, src);
3967 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3968 }
3969 }
3970
3971 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3972 assert(rscratch != noreg || always_reachable(src), "missing");
3973
3974 if (reachable(src)) {
3975 vxorps(dst, nds, as_Address(src), vector_len);
3976 } else {
3977 lea(rscratch, src);
3978 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3979 }
3980 }
3981
3982 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3983 assert(rscratch != noreg || always_reachable(src), "missing");
3984
3985 if (UseAVX > 1 || (vector_len < 1)) {
3986 if (reachable(src)) {
3987 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3988 } else {
3989 lea(rscratch, src);
3990 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3991 }
3992 } else {
3993 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3994 }
3995 }
3996
3997 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3998 assert(rscratch != noreg || always_reachable(src), "missing");
3999
4000 if (reachable(src)) {
4001 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
4002 } else {
4003 lea(rscratch, src);
4004 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
4005 }
4006 }
4007
4008 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
4009 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
4010 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
4011 // The inverted mask is sign-extended
4012 andptr(possibly_non_local, inverted_mask);
4013 }
4014
4015 void MacroAssembler::resolve_jobject(Register value,
4016 Register thread,
4017 Register tmp) {
4018 assert_different_registers(value, thread, tmp);
4019 Label done, tagged, weak_tagged;
4020 testptr(value, value);
4021 jcc(Assembler::zero, done); // Use null as-is.
4022 testptr(value, JNIHandles::tag_mask); // Test for tag.
4023 jcc(Assembler::notZero, tagged);
4024
4025 // Resolve local handle
4026 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp, thread);
4027 verify_oop(value);
4028 jmp(done);
4029
4030 bind(tagged);
4031 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
4032 jcc(Assembler::notZero, weak_tagged);
4033
4034 // Resolve global handle
4035 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4036 verify_oop(value);
4037 jmp(done);
4038
4039 bind(weak_tagged);
4040 // Resolve jweak.
4041 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4042 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp, thread);
4043 verify_oop(value);
4044
4045 bind(done);
4046 }
4047
4048 void MacroAssembler::resolve_global_jobject(Register value,
4049 Register thread,
4050 Register tmp) {
4051 assert_different_registers(value, thread, tmp);
4052 Label done;
4053
4054 testptr(value, value);
4055 jcc(Assembler::zero, done); // Use null as-is.
4056
4057 #ifdef ASSERT
4058 {
4059 Label valid_global_tag;
4060 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
4061 jcc(Assembler::notZero, valid_global_tag);
4062 stop("non global jobject using resolve_global_jobject");
4063 bind(valid_global_tag);
4064 }
4065 #endif
4066
4067 // Resolve global handle
4068 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4069 verify_oop(value);
4070
4071 bind(done);
4072 }
4073
4074 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4075 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4076 }
4077
4078 // Force generation of a 4 byte immediate value even if it fits into 8bit
4079 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4080 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4081 }
4082
4083 void MacroAssembler::subptr(Register dst, Register src) {
4084 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4085 }
4086
4087 // C++ bool manipulation
4088 void MacroAssembler::testbool(Register dst) {
4089 if(sizeof(bool) == 1)
4090 testb(dst, 0xff);
4091 else if(sizeof(bool) == 2) {
4092 // testw implementation needed for two byte bools
4093 ShouldNotReachHere();
4094 } else if(sizeof(bool) == 4)
4095 testl(dst, dst);
4096 else
4097 // unsupported
4098 ShouldNotReachHere();
4099 }
4100
4101 void MacroAssembler::testptr(Register dst, Register src) {
4102 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4103 }
4104
4105 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4106 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4107 Register var_size_in_bytes,
4108 int con_size_in_bytes,
4109 Register t1,
4110 Register t2,
4111 Label& slow_case) {
4112 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4113 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4114 }
4115
4116 RegSet MacroAssembler::call_clobbered_gp_registers() {
4117 RegSet regs;
4118 #ifdef _LP64
4119 regs += RegSet::of(rax, rcx, rdx);
4120 #ifndef _WINDOWS
4121 regs += RegSet::of(rsi, rdi);
4122 #endif
4123 regs += RegSet::range(r8, r11);
4124 #else
4125 regs += RegSet::of(rax, rcx, rdx);
4126 #endif
4127 #ifdef _LP64
4128 if (UseAPX) {
4129 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
4130 }
4131 #endif
4132 return regs;
4133 }
4134
4135 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
4136 int num_xmm_registers = XMMRegister::available_xmm_registers();
4137 #if defined(_WINDOWS)
4138 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
4139 if (num_xmm_registers > 16) {
4140 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
4141 }
4142 return result;
4143 #else
4144 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
4145 #endif
4146 }
4147
4148 static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor
4149
4150 #ifndef _LP64
4151 static bool use_x87_registers() { return UseSSE < 2; }
4152 #endif
4153 static bool use_xmm_registers() { return UseSSE >= 1; }
4154
4155 // C1 only ever uses the first double/float of the XMM register.
4156 static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); }
4157
4158 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4159 if (UseSSE == 1) {
4160 masm->movflt(Address(rsp, offset), reg);
4161 } else {
4162 masm->movdbl(Address(rsp, offset), reg);
4163 }
4164 }
4165
4166 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4167 if (UseSSE == 1) {
4168 masm->movflt(reg, Address(rsp, offset));
4169 } else {
4170 masm->movdbl(reg, Address(rsp, offset));
4171 }
4172 }
4173
4174 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
4175 bool save_fpu, int& gp_area_size,
4176 int& fp_area_size, int& xmm_area_size) {
4177
4178 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
4179 StackAlignmentInBytes);
4180 #ifdef _LP64
4181 fp_area_size = 0;
4182 #else
4183 fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0;
4184 #endif
4185 xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0;
4186
4187 return gp_area_size + fp_area_size + xmm_area_size;
4188 }
4189
4190 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
4191 block_comment("push_call_clobbered_registers start");
4192 // Regular registers
4193 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
4194
4195 int gp_area_size;
4196 int fp_area_size;
4197 int xmm_area_size;
4198 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
4199 gp_area_size, fp_area_size, xmm_area_size);
4200 subptr(rsp, total_save_size);
4201
4202 push_set(gp_registers_to_push, 0);
4203
4204 #ifndef _LP64
4205 if (save_fpu && use_x87_registers()) {
4206 fnsave(Address(rsp, gp_area_size));
4207 fwait();
4208 }
4209 #endif
4210 if (save_fpu && use_xmm_registers()) {
4211 push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4212 }
4213
4214 block_comment("push_call_clobbered_registers end");
4215 }
4216
4217 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
4218 block_comment("pop_call_clobbered_registers start");
4219
4220 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
4221
4222 int gp_area_size;
4223 int fp_area_size;
4224 int xmm_area_size;
4225 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
4226 gp_area_size, fp_area_size, xmm_area_size);
4227
4228 if (restore_fpu && use_xmm_registers()) {
4229 pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4230 }
4231 #ifndef _LP64
4232 if (restore_fpu && use_x87_registers()) {
4233 frstor(Address(rsp, gp_area_size));
4234 }
4235 #endif
4236
4237 pop_set(gp_registers_to_pop, 0);
4238
4239 addptr(rsp, total_save_size);
4240
4241 vzeroupper();
4242
4243 block_comment("pop_call_clobbered_registers end");
4244 }
4245
4246 void MacroAssembler::push_set(XMMRegSet set, int offset) {
4247 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
4248 int spill_offset = offset;
4249
4250 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
4251 save_xmm_register(this, spill_offset, *it);
4252 spill_offset += xmm_save_size();
4253 }
4254 }
4255
4256 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
4257 int restore_size = set.size() * xmm_save_size();
4258 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
4259
4260 int restore_offset = offset + restore_size - xmm_save_size();
4261
4262 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
4263 restore_xmm_register(this, restore_offset, *it);
4264 restore_offset -= xmm_save_size();
4265 }
4266 }
4267
4268 void MacroAssembler::push_set(RegSet set, int offset) {
4269 int spill_offset;
4270 if (offset == -1) {
4271 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4272 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4273 subptr(rsp, aligned_size);
4274 spill_offset = 0;
4275 } else {
4276 spill_offset = offset;
4277 }
4278
4279 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
4280 movptr(Address(rsp, spill_offset), *it);
4281 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4282 }
4283 }
4284
4285 void MacroAssembler::pop_set(RegSet set, int offset) {
4286
4287 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4288 int restore_size = set.size() * gp_reg_size;
4289 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
4290
4291 int restore_offset;
4292 if (offset == -1) {
4293 restore_offset = restore_size - gp_reg_size;
4294 } else {
4295 restore_offset = offset + restore_size - gp_reg_size;
4296 }
4297 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
4298 movptr(*it, Address(rsp, restore_offset));
4299 restore_offset -= gp_reg_size;
4300 }
4301
4302 if (offset == -1) {
4303 addptr(rsp, aligned_size);
4304 }
4305 }
4306
4307 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4308 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4309 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4310 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4311 Label done;
4312
4313 testptr(length_in_bytes, length_in_bytes);
4314 jcc(Assembler::zero, done);
4315
4316 // initialize topmost word, divide index by 2, check if odd and test if zero
4317 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4318 #ifdef ASSERT
4319 {
4320 Label L;
4321 testptr(length_in_bytes, BytesPerWord - 1);
4322 jcc(Assembler::zero, L);
4323 stop("length must be a multiple of BytesPerWord");
4324 bind(L);
4325 }
4326 #endif
4327 Register index = length_in_bytes;
4328 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4329 if (UseIncDec) {
4330 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4331 } else {
4332 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4333 shrptr(index, 1);
4334 }
4335 #ifndef _LP64
4336 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4337 {
4338 Label even;
4339 // note: if index was a multiple of 8, then it cannot
4340 // be 0 now otherwise it must have been 0 before
4341 // => if it is even, we don't need to check for 0 again
4342 jcc(Assembler::carryClear, even);
4343 // clear topmost word (no jump would be needed if conditional assignment worked here)
4344 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4345 // index could be 0 now, must check again
4346 jcc(Assembler::zero, done);
4347 bind(even);
4348 }
4349 #endif // !_LP64
4350 // initialize remaining object fields: index is a multiple of 2 now
4351 {
4352 Label loop;
4353 bind(loop);
4354 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4355 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4356 decrement(index);
4357 jcc(Assembler::notZero, loop);
4358 }
4359
4360 bind(done);
4361 }
4362
4363 // Look up the method for a megamorphic invokeinterface call.
4364 // The target method is determined by <intf_klass, itable_index>.
4365 // The receiver klass is in recv_klass.
4366 // On success, the result will be in method_result, and execution falls through.
4367 // On failure, execution transfers to the given label.
4368 void MacroAssembler::lookup_interface_method(Register recv_klass,
4369 Register intf_klass,
4370 RegisterOrConstant itable_index,
4371 Register method_result,
4372 Register scan_temp,
4373 Label& L_no_such_interface,
4374 bool return_method) {
4375 assert_different_registers(recv_klass, intf_klass, scan_temp);
4376 assert_different_registers(method_result, intf_klass, scan_temp);
4377 assert(recv_klass != method_result || !return_method,
4378 "recv_klass can be destroyed when method isn't needed");
4379
4380 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4381 "caller must use same register for non-constant itable index as for method");
4382
4383 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4384 int vtable_base = in_bytes(Klass::vtable_start_offset());
4385 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4386 int scan_step = itableOffsetEntry::size() * wordSize;
4387 int vte_size = vtableEntry::size_in_bytes();
4388 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4389 assert(vte_size == wordSize, "else adjust times_vte_scale");
4390
4391 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4392
4393 // Could store the aligned, prescaled offset in the klass.
4394 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4395
4396 if (return_method) {
4397 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4398 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4399 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4400 }
4401
4402 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
4403 // if (scan->interface() == intf) {
4404 // result = (klass + scan->offset() + itable_index);
4405 // }
4406 // }
4407 Label search, found_method;
4408
4409 for (int peel = 1; peel >= 0; peel--) {
4410 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
4411 cmpptr(intf_klass, method_result);
4412
4413 if (peel) {
4414 jccb(Assembler::equal, found_method);
4415 } else {
4416 jccb(Assembler::notEqual, search);
4417 // (invert the test to fall through to found_method...)
4418 }
4419
4420 if (!peel) break;
4421
4422 bind(search);
4423
4424 // Check that the previous entry is non-null. A null entry means that
4425 // the receiver class doesn't implement the interface, and wasn't the
4426 // same as when the caller was compiled.
4427 testptr(method_result, method_result);
4428 jcc(Assembler::zero, L_no_such_interface);
4429 addptr(scan_temp, scan_step);
4430 }
4431
4432 bind(found_method);
4433
4434 if (return_method) {
4435 // Got a hit.
4436 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
4437 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4438 }
4439 }
4440
4441 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
4442 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
4443 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
4444 // The target method is determined by <holder_klass, itable_index>.
4445 // The receiver klass is in recv_klass.
4446 // On success, the result will be in method_result, and execution falls through.
4447 // On failure, execution transfers to the given label.
4448 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
4449 Register holder_klass,
4450 Register resolved_klass,
4451 Register method_result,
4452 Register scan_temp,
4453 Register temp_reg2,
4454 Register receiver,
4455 int itable_index,
4456 Label& L_no_such_interface) {
4457 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
4458 Register temp_itbl_klass = method_result;
4459 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
4460
4461 int vtable_base = in_bytes(Klass::vtable_start_offset());
4462 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4463 int scan_step = itableOffsetEntry::size() * wordSize;
4464 int vte_size = vtableEntry::size_in_bytes();
4465 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
4466 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
4467 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4468 assert(vte_size == wordSize, "adjust times_vte_scale");
4469
4470 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
4471
4472 // temp_itbl_klass = recv_klass.itable[0]
4473 // scan_temp = &recv_klass.itable[0] + step
4474 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4475 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
4476 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
4477 xorptr(temp_reg, temp_reg);
4478
4479 // Initial checks:
4480 // - if (holder_klass != resolved_klass), go to "scan for resolved"
4481 // - if (itable[0] == 0), no such interface
4482 // - if (itable[0] == holder_klass), shortcut to "holder found"
4483 cmpptr(holder_klass, resolved_klass);
4484 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
4485 testptr(temp_itbl_klass, temp_itbl_klass);
4486 jccb(Assembler::zero, L_no_such_interface);
4487 cmpptr(holder_klass, temp_itbl_klass);
4488 jccb(Assembler::equal, L_holder_found);
4489
4490 // Loop: Look for holder_klass record in itable
4491 // do {
4492 // tmp = itable[index];
4493 // index += step;
4494 // if (tmp == holder_klass) {
4495 // goto L_holder_found; // Found!
4496 // }
4497 // } while (tmp != 0);
4498 // goto L_no_such_interface // Not found.
4499 Label L_scan_holder;
4500 bind(L_scan_holder);
4501 movptr(temp_itbl_klass, Address(scan_temp, 0));
4502 addptr(scan_temp, scan_step);
4503 cmpptr(holder_klass, temp_itbl_klass);
4504 jccb(Assembler::equal, L_holder_found);
4505 testptr(temp_itbl_klass, temp_itbl_klass);
4506 jccb(Assembler::notZero, L_scan_holder);
4507
4508 jmpb(L_no_such_interface);
4509
4510 // Loop: Look for resolved_class record in itable
4511 // do {
4512 // tmp = itable[index];
4513 // index += step;
4514 // if (tmp == holder_klass) {
4515 // // Also check if we have met a holder klass
4516 // holder_tmp = itable[index-step-ioffset];
4517 // }
4518 // if (tmp == resolved_klass) {
4519 // goto L_resolved_found; // Found!
4520 // }
4521 // } while (tmp != 0);
4522 // goto L_no_such_interface // Not found.
4523 //
4524 Label L_loop_scan_resolved;
4525 bind(L_loop_scan_resolved);
4526 movptr(temp_itbl_klass, Address(scan_temp, 0));
4527 addptr(scan_temp, scan_step);
4528 bind(L_loop_scan_resolved_entry);
4529 cmpptr(holder_klass, temp_itbl_klass);
4530 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4531 cmpptr(resolved_klass, temp_itbl_klass);
4532 jccb(Assembler::equal, L_resolved_found);
4533 testptr(temp_itbl_klass, temp_itbl_klass);
4534 jccb(Assembler::notZero, L_loop_scan_resolved);
4535
4536 jmpb(L_no_such_interface);
4537
4538 Label L_ready;
4539
4540 // See if we already have a holder klass. If not, go and scan for it.
4541 bind(L_resolved_found);
4542 testptr(temp_reg, temp_reg);
4543 jccb(Assembler::zero, L_scan_holder);
4544 jmpb(L_ready);
4545
4546 bind(L_holder_found);
4547 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4548
4549 // Finally, temp_reg contains holder_klass vtable offset
4550 bind(L_ready);
4551 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4552 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4553 load_klass(scan_temp, receiver, noreg);
4554 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4555 } else {
4556 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4557 }
4558 }
4559
4560
4561 // virtual method calling
4562 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4563 RegisterOrConstant vtable_index,
4564 Register method_result) {
4565 const ByteSize base = Klass::vtable_start_offset();
4566 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4567 Address vtable_entry_addr(recv_klass,
4568 vtable_index, Address::times_ptr,
4569 base + vtableEntry::method_offset());
4570 movptr(method_result, vtable_entry_addr);
4571 }
4572
4573
4574 void MacroAssembler::check_klass_subtype(Register sub_klass,
4575 Register super_klass,
4576 Register temp_reg,
4577 Label& L_success) {
4578 Label L_failure;
4579 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4580 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4581 bind(L_failure);
4582 }
4583
4584
4585 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4586 Register super_klass,
4587 Register temp_reg,
4588 Label* L_success,
4589 Label* L_failure,
4590 Label* L_slow_path,
4591 RegisterOrConstant super_check_offset) {
4592 assert_different_registers(sub_klass, super_klass, temp_reg);
4593 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4594 if (super_check_offset.is_register()) {
4595 assert_different_registers(sub_klass, super_klass,
4596 super_check_offset.as_register());
4597 } else if (must_load_sco) {
4598 assert(temp_reg != noreg, "supply either a temp or a register offset");
4599 }
4600
4601 Label L_fallthrough;
4602 int label_nulls = 0;
4603 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4604 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4605 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4606 assert(label_nulls <= 1, "at most one null in the batch");
4607
4608 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4609 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4610 Address super_check_offset_addr(super_klass, sco_offset);
4611
4612 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4613 // range of a jccb. If this routine grows larger, reconsider at
4614 // least some of these.
4615 #define local_jcc(assembler_cond, label) \
4616 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4617 else jcc( assembler_cond, label) /*omit semi*/
4618
4619 // Hacked jmp, which may only be used just before L_fallthrough.
4620 #define final_jmp(label) \
4621 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4622 else jmp(label) /*omit semi*/
4623
4624 // If the pointers are equal, we are done (e.g., String[] elements).
4625 // This self-check enables sharing of secondary supertype arrays among
4626 // non-primary types such as array-of-interface. Otherwise, each such
4627 // type would need its own customized SSA.
4628 // We move this check to the front of the fast path because many
4629 // type checks are in fact trivially successful in this manner,
4630 // so we get a nicely predicted branch right at the start of the check.
4631 cmpptr(sub_klass, super_klass);
4632 local_jcc(Assembler::equal, *L_success);
4633
4634 // Check the supertype display:
4635 if (must_load_sco) {
4636 // Positive movl does right thing on LP64.
4637 movl(temp_reg, super_check_offset_addr);
4638 super_check_offset = RegisterOrConstant(temp_reg);
4639 }
4640 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4641 cmpptr(super_klass, super_check_addr); // load displayed supertype
4642
4643 // This check has worked decisively for primary supers.
4644 // Secondary supers are sought in the super_cache ('super_cache_addr').
4645 // (Secondary supers are interfaces and very deeply nested subtypes.)
4646 // This works in the same check above because of a tricky aliasing
4647 // between the super_cache and the primary super display elements.
4648 // (The 'super_check_addr' can address either, as the case requires.)
4649 // Note that the cache is updated below if it does not help us find
4650 // what we need immediately.
4651 // So if it was a primary super, we can just fail immediately.
4652 // Otherwise, it's the slow path for us (no success at this point).
4653
4654 if (super_check_offset.is_register()) {
4655 local_jcc(Assembler::equal, *L_success);
4656 cmpl(super_check_offset.as_register(), sc_offset);
4657 if (L_failure == &L_fallthrough) {
4658 local_jcc(Assembler::equal, *L_slow_path);
4659 } else {
4660 local_jcc(Assembler::notEqual, *L_failure);
4661 final_jmp(*L_slow_path);
4662 }
4663 } else if (super_check_offset.as_constant() == sc_offset) {
4664 // Need a slow path; fast failure is impossible.
4665 if (L_slow_path == &L_fallthrough) {
4666 local_jcc(Assembler::equal, *L_success);
4667 } else {
4668 local_jcc(Assembler::notEqual, *L_slow_path);
4669 final_jmp(*L_success);
4670 }
4671 } else {
4672 // No slow path; it's a fast decision.
4673 if (L_failure == &L_fallthrough) {
4674 local_jcc(Assembler::equal, *L_success);
4675 } else {
4676 local_jcc(Assembler::notEqual, *L_failure);
4677 final_jmp(*L_success);
4678 }
4679 }
4680
4681 bind(L_fallthrough);
4682
4683 #undef local_jcc
4684 #undef final_jmp
4685 }
4686
4687
4688 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4689 Register super_klass,
4690 Register temp_reg,
4691 Register temp2_reg,
4692 Label* L_success,
4693 Label* L_failure,
4694 bool set_cond_codes) {
4695 assert_different_registers(sub_klass, super_klass, temp_reg);
4696 if (temp2_reg != noreg)
4697 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4698 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4699
4700 Label L_fallthrough;
4701 int label_nulls = 0;
4702 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4703 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4704 assert(label_nulls <= 1, "at most one null in the batch");
4705
4706 // a couple of useful fields in sub_klass:
4707 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4708 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4709 Address secondary_supers_addr(sub_klass, ss_offset);
4710 Address super_cache_addr( sub_klass, sc_offset);
4711
4712 // Do a linear scan of the secondary super-klass chain.
4713 // This code is rarely used, so simplicity is a virtue here.
4714 // The repne_scan instruction uses fixed registers, which we must spill.
4715 // Don't worry too much about pre-existing connections with the input regs.
4716
4717 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4718 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4719
4720 // Get super_klass value into rax (even if it was in rdi or rcx).
4721 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4722 if (super_klass != rax) {
4723 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4724 mov(rax, super_klass);
4725 }
4726 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4727 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4728
4729 #ifndef PRODUCT
4730 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4731 ExternalAddress pst_counter_addr((address) pst_counter);
4732 NOT_LP64( incrementl(pst_counter_addr) );
4733 LP64_ONLY( lea(rcx, pst_counter_addr) );
4734 LP64_ONLY( incrementl(Address(rcx, 0)) );
4735 #endif //PRODUCT
4736
4737 // We will consult the secondary-super array.
4738 movptr(rdi, secondary_supers_addr);
4739 // Load the array length. (Positive movl does right thing on LP64.)
4740 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4741 // Skip to start of data.
4742 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4743
4744 // Scan RCX words at [RDI] for an occurrence of RAX.
4745 // Set NZ/Z based on last compare.
4746 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4747 // not change flags (only scas instruction which is repeated sets flags).
4748 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4749
4750 testptr(rax,rax); // Set Z = 0
4751 repne_scan();
4752
4753 // Unspill the temp. registers:
4754 if (pushed_rdi) pop(rdi);
4755 if (pushed_rcx) pop(rcx);
4756 if (pushed_rax) pop(rax);
4757
4758 if (set_cond_codes) {
4759 // Special hack for the AD files: rdi is guaranteed non-zero.
4760 assert(!pushed_rdi, "rdi must be left non-null");
4761 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4762 }
4763
4764 if (L_failure == &L_fallthrough)
4765 jccb(Assembler::notEqual, *L_failure);
4766 else jcc(Assembler::notEqual, *L_failure);
4767
4768 // Success. Cache the super we found and proceed in triumph.
4769 movptr(super_cache_addr, super_klass);
4770
4771 if (L_success != &L_fallthrough) {
4772 jmp(*L_success);
4773 }
4774
4775 #undef IS_A_TEMP
4776
4777 bind(L_fallthrough);
4778 }
4779
4780 #ifndef _LP64
4781
4782 // 32-bit x86 only: always use the linear search.
4783 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4784 Register super_klass,
4785 Register temp_reg,
4786 Register temp2_reg,
4787 Label* L_success,
4788 Label* L_failure,
4789 bool set_cond_codes) {
4790 check_klass_subtype_slow_path_linear
4791 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
4792 }
4793
4794 #else // _LP64
4795
4796 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4797 Register super_klass,
4798 Register temp_reg,
4799 Register temp2_reg,
4800 Label* L_success,
4801 Label* L_failure,
4802 bool set_cond_codes) {
4803 assert(set_cond_codes == false, "must be false on 64-bit x86");
4804 check_klass_subtype_slow_path
4805 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4806 L_success, L_failure);
4807 }
4808
4809 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4810 Register super_klass,
4811 Register temp_reg,
4812 Register temp2_reg,
4813 Register temp3_reg,
4814 Register temp4_reg,
4815 Label* L_success,
4816 Label* L_failure) {
4817 if (UseSecondarySupersTable) {
4818 check_klass_subtype_slow_path_table
4819 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4820 L_success, L_failure);
4821 } else {
4822 check_klass_subtype_slow_path_linear
4823 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4824 }
4825 }
4826
4827 Register MacroAssembler::allocate_if_noreg(Register r,
4828 RegSetIterator<Register> &available_regs,
4829 RegSet ®s_to_push) {
4830 if (!r->is_valid()) {
4831 r = *available_regs++;
4832 regs_to_push += r;
4833 }
4834 return r;
4835 }
4836
4837 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4838 Register super_klass,
4839 Register temp_reg,
4840 Register temp2_reg,
4841 Register temp3_reg,
4842 Register result_reg,
4843 Label* L_success,
4844 Label* L_failure) {
4845 // NB! Callers may assume that, when temp2_reg is a valid register,
4846 // this code sets it to a nonzero value.
4847 bool temp2_reg_was_valid = temp2_reg->is_valid();
4848
4849 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4850
4851 Label L_fallthrough;
4852 int label_nulls = 0;
4853 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4854 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4855 assert(label_nulls <= 1, "at most one null in the batch");
4856
4857 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4858
4859 RegSetIterator<Register> available_regs
4860 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4861
4862 RegSet pushed_regs;
4863
4864 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4865 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4866 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4867 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4868 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4869
4870 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4871
4872 {
4873
4874 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4875 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4876 subptr(rsp, aligned_size);
4877 push_set(pushed_regs, 0);
4878
4879 lookup_secondary_supers_table_var(sub_klass,
4880 super_klass,
4881 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4882 cmpq(result_reg, 0);
4883
4884 // Unspill the temp. registers:
4885 pop_set(pushed_regs, 0);
4886 // Increment SP but do not clobber flags.
4887 lea(rsp, Address(rsp, aligned_size));
4888 }
4889
4890 if (temp2_reg_was_valid) {
4891 movq(temp2_reg, 1);
4892 }
4893
4894 jcc(Assembler::notEqual, *L_failure);
4895
4896 if (L_success != &L_fallthrough) {
4897 jmp(*L_success);
4898 }
4899
4900 bind(L_fallthrough);
4901 }
4902
4903 // population_count variant for running without the POPCNT
4904 // instruction, which was introduced with SSE4.2 in 2008.
4905 void MacroAssembler::population_count(Register dst, Register src,
4906 Register scratch1, Register scratch2) {
4907 assert_different_registers(src, scratch1, scratch2);
4908 if (UsePopCountInstruction) {
4909 Assembler::popcntq(dst, src);
4910 } else {
4911 assert_different_registers(src, scratch1, scratch2);
4912 assert_different_registers(dst, scratch1, scratch2);
4913 Label loop, done;
4914
4915 mov(scratch1, src);
4916 // dst = 0;
4917 // while(scratch1 != 0) {
4918 // dst++;
4919 // scratch1 &= (scratch1 - 1);
4920 // }
4921 xorl(dst, dst);
4922 testq(scratch1, scratch1);
4923 jccb(Assembler::equal, done);
4924 {
4925 bind(loop);
4926 incq(dst);
4927 movq(scratch2, scratch1);
4928 decq(scratch2);
4929 andq(scratch1, scratch2);
4930 jccb(Assembler::notEqual, loop);
4931 }
4932 bind(done);
4933 }
4934 #ifdef ASSERT
4935 mov64(scratch1, 0xCafeBabeDeadBeef);
4936 movq(scratch2, scratch1);
4937 #endif
4938 }
4939
4940 // Ensure that the inline code and the stub are using the same registers.
4941 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4942 do { \
4943 assert(r_super_klass == rax, "mismatch"); \
4944 assert(r_array_base == rbx, "mismatch"); \
4945 assert(r_array_length == rcx, "mismatch"); \
4946 assert(r_array_index == rdx, "mismatch"); \
4947 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4948 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4949 assert(result == rdi || result == noreg, "mismatch"); \
4950 } while(0)
4951
4952 // Versions of salq and rorq that don't need count to be in rcx
4953
4954 void MacroAssembler::salq(Register dest, Register count) {
4955 if (count == rcx) {
4956 Assembler::salq(dest);
4957 } else {
4958 assert_different_registers(rcx, dest);
4959 xchgq(rcx, count);
4960 Assembler::salq(dest);
4961 xchgq(rcx, count);
4962 }
4963 }
4964
4965 void MacroAssembler::rorq(Register dest, Register count) {
4966 if (count == rcx) {
4967 Assembler::rorq(dest);
4968 } else {
4969 assert_different_registers(rcx, dest);
4970 xchgq(rcx, count);
4971 Assembler::rorq(dest);
4972 xchgq(rcx, count);
4973 }
4974 }
4975
4976 // Return true: we succeeded in generating this code
4977 //
4978 // At runtime, return 0 in result if r_super_klass is a superclass of
4979 // r_sub_klass, otherwise return nonzero. Use this if you know the
4980 // super_klass_slot of the class you're looking for. This is always
4981 // the case for instanceof and checkcast.
4982 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4983 Register r_super_klass,
4984 Register temp1,
4985 Register temp2,
4986 Register temp3,
4987 Register temp4,
4988 Register result,
4989 u1 super_klass_slot) {
4990 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4991
4992 Label L_fallthrough, L_success, L_failure;
4993
4994 BLOCK_COMMENT("lookup_secondary_supers_table {");
4995
4996 const Register
4997 r_array_index = temp1,
4998 r_array_length = temp2,
4999 r_array_base = temp3,
5000 r_bitmap = temp4;
5001
5002 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
5003
5004 xorq(result, result); // = 0
5005
5006 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
5007 movq(r_array_index, r_bitmap);
5008
5009 // First check the bitmap to see if super_klass might be present. If
5010 // the bit is zero, we are certain that super_klass is not one of
5011 // the secondary supers.
5012 u1 bit = super_klass_slot;
5013 {
5014 // NB: If the count in a x86 shift instruction is 0, the flags are
5015 // not affected, so we do a testq instead.
5016 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
5017 if (shift_count != 0) {
5018 salq(r_array_index, shift_count);
5019 } else {
5020 testq(r_array_index, r_array_index);
5021 }
5022 }
5023 // We test the MSB of r_array_index, i.e. its sign bit
5024 jcc(Assembler::positive, L_failure);
5025
5026 // Get the first array index that can contain super_klass into r_array_index.
5027 if (bit != 0) {
5028 population_count(r_array_index, r_array_index, temp2, temp3);
5029 } else {
5030 movl(r_array_index, 1);
5031 }
5032 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5033
5034 // We will consult the secondary-super array.
5035 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5036
5037 // We're asserting that the first word in an Array<Klass*> is the
5038 // length, and the second word is the first word of the data. If
5039 // that ever changes, r_array_base will have to be adjusted here.
5040 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5041 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5042
5043 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5044 jccb(Assembler::equal, L_success);
5045
5046 // Is there another entry to check? Consult the bitmap.
5047 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
5048 jccb(Assembler::carryClear, L_failure);
5049
5050 // Linear probe. Rotate the bitmap so that the next bit to test is
5051 // in Bit 1.
5052 if (bit != 0) {
5053 rorq(r_bitmap, bit);
5054 }
5055
5056 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5057 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5058 // Kills: r_array_length.
5059 // Returns: result.
5060 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
5061 // Result (0/1) is in rdi
5062 jmpb(L_fallthrough);
5063
5064 bind(L_failure);
5065 incq(result); // 0 => 1
5066
5067 bind(L_success);
5068 // result = 0;
5069
5070 bind(L_fallthrough);
5071 BLOCK_COMMENT("} lookup_secondary_supers_table");
5072
5073 if (VerifySecondarySupers) {
5074 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5075 temp1, temp2, temp3);
5076 }
5077 }
5078
5079 // At runtime, return 0 in result if r_super_klass is a superclass of
5080 // r_sub_klass, otherwise return nonzero. Use this version of
5081 // lookup_secondary_supers_table() if you don't know ahead of time
5082 // which superclass will be searched for. Used by interpreter and
5083 // runtime stubs. It is larger and has somewhat greater latency than
5084 // the version above, which takes a constant super_klass_slot.
5085 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
5086 Register r_super_klass,
5087 Register temp1,
5088 Register temp2,
5089 Register temp3,
5090 Register temp4,
5091 Register result) {
5092 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
5093 assert_different_registers(r_sub_klass, r_super_klass, rcx);
5094 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
5095
5096 Label L_fallthrough, L_success, L_failure;
5097
5098 BLOCK_COMMENT("lookup_secondary_supers_table {");
5099
5100 RegSetIterator<Register> available_regs = (temps - rcx).begin();
5101
5102 // FIXME. Once we are sure that all paths reaching this point really
5103 // do pass rcx as one of our temps we can get rid of the following
5104 // workaround.
5105 assert(temps.contains(rcx), "fix this code");
5106
5107 // We prefer to have our shift count in rcx. If rcx is one of our
5108 // temps, use it for slot. If not, pick any of our temps.
5109 Register slot;
5110 if (!temps.contains(rcx)) {
5111 slot = *available_regs++;
5112 } else {
5113 slot = rcx;
5114 }
5115
5116 const Register r_array_index = *available_regs++;
5117 const Register r_bitmap = *available_regs++;
5118
5119 // The logic above guarantees this property, but we state it here.
5120 assert_different_registers(r_array_index, r_bitmap, rcx);
5121
5122 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
5123 movq(r_array_index, r_bitmap);
5124
5125 // First check the bitmap to see if super_klass might be present. If
5126 // the bit is zero, we are certain that super_klass is not one of
5127 // the secondary supers.
5128 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
5129 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
5130 salq(r_array_index, slot);
5131
5132 testq(r_array_index, r_array_index);
5133 // We test the MSB of r_array_index, i.e. its sign bit
5134 jcc(Assembler::positive, L_failure);
5135
5136 const Register r_array_base = *available_regs++;
5137
5138 // Get the first array index that can contain super_klass into r_array_index.
5139 // Note: Clobbers r_array_base and slot.
5140 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
5141
5142 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5143
5144 // We will consult the secondary-super array.
5145 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5146
5147 // We're asserting that the first word in an Array<Klass*> is the
5148 // length, and the second word is the first word of the data. If
5149 // that ever changes, r_array_base will have to be adjusted here.
5150 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5151 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5152
5153 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5154 jccb(Assembler::equal, L_success);
5155
5156 // Restore slot to its true value
5157 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
5158
5159 // Linear probe. Rotate the bitmap so that the next bit to test is
5160 // in Bit 1.
5161 rorq(r_bitmap, slot);
5162
5163 // Is there another entry to check? Consult the bitmap.
5164 btq(r_bitmap, 1);
5165 jccb(Assembler::carryClear, L_failure);
5166
5167 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5168 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5169 // Kills: r_array_length.
5170 // Returns: result.
5171 lookup_secondary_supers_table_slow_path(r_super_klass,
5172 r_array_base,
5173 r_array_index,
5174 r_bitmap,
5175 /*temp1*/result,
5176 /*temp2*/slot,
5177 &L_success,
5178 nullptr);
5179
5180 bind(L_failure);
5181 movq(result, 1);
5182 jmpb(L_fallthrough);
5183
5184 bind(L_success);
5185 xorq(result, result); // = 0
5186
5187 bind(L_fallthrough);
5188 BLOCK_COMMENT("} lookup_secondary_supers_table");
5189
5190 if (VerifySecondarySupers) {
5191 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5192 temp1, temp2, temp3);
5193 }
5194 }
5195
5196 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
5197 Label* L_success, Label* L_failure) {
5198 Label L_loop, L_fallthrough;
5199 {
5200 int label_nulls = 0;
5201 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5202 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5203 assert(label_nulls <= 1, "at most one null in the batch");
5204 }
5205 bind(L_loop);
5206 cmpq(value, Address(addr, count, Address::times_8));
5207 jcc(Assembler::equal, *L_success);
5208 addl(count, 1);
5209 cmpl(count, limit);
5210 jcc(Assembler::less, L_loop);
5211
5212 if (&L_fallthrough != L_failure) {
5213 jmp(*L_failure);
5214 }
5215 bind(L_fallthrough);
5216 }
5217
5218 // Called by code generated by check_klass_subtype_slow_path
5219 // above. This is called when there is a collision in the hashed
5220 // lookup in the secondary supers array.
5221 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
5222 Register r_array_base,
5223 Register r_array_index,
5224 Register r_bitmap,
5225 Register temp1,
5226 Register temp2,
5227 Label* L_success,
5228 Label* L_failure) {
5229 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
5230
5231 const Register
5232 r_array_length = temp1,
5233 r_sub_klass = noreg,
5234 result = noreg;
5235
5236 Label L_fallthrough;
5237 int label_nulls = 0;
5238 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5239 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5240 assert(label_nulls <= 1, "at most one null in the batch");
5241
5242 // Load the array length.
5243 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5244 // And adjust the array base to point to the data.
5245 // NB! Effectively increments current slot index by 1.
5246 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
5247 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5248
5249 // Linear probe
5250 Label L_huge;
5251
5252 // The bitmap is full to bursting.
5253 // Implicit invariant: BITMAP_FULL implies (length > 0)
5254 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
5255 jcc(Assembler::greater, L_huge);
5256
5257 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
5258 // current slot (at secondary_supers[r_array_index]) has not yet
5259 // been inspected, and r_array_index may be out of bounds if we
5260 // wrapped around the end of the array.
5261
5262 { // This is conventional linear probing, but instead of terminating
5263 // when a null entry is found in the table, we maintain a bitmap
5264 // in which a 0 indicates missing entries.
5265 // The check above guarantees there are 0s in the bitmap, so the loop
5266 // eventually terminates.
5267
5268 xorl(temp2, temp2); // = 0;
5269
5270 Label L_again;
5271 bind(L_again);
5272
5273 // Check for array wraparound.
5274 cmpl(r_array_index, r_array_length);
5275 cmovl(Assembler::greaterEqual, r_array_index, temp2);
5276
5277 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5278 jcc(Assembler::equal, *L_success);
5279
5280 // If the next bit in bitmap is zero, we're done.
5281 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
5282 jcc(Assembler::carryClear, *L_failure);
5283
5284 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
5285 addl(r_array_index, 1);
5286
5287 jmp(L_again);
5288 }
5289
5290 { // Degenerate case: more than 64 secondary supers.
5291 // FIXME: We could do something smarter here, maybe a vectorized
5292 // comparison or a binary search, but is that worth any added
5293 // complexity?
5294 bind(L_huge);
5295 xorl(r_array_index, r_array_index); // = 0
5296 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
5297 L_success,
5298 (&L_fallthrough != L_failure ? L_failure : nullptr));
5299
5300 bind(L_fallthrough);
5301 }
5302 }
5303
5304 struct VerifyHelperArguments {
5305 Klass* _super;
5306 Klass* _sub;
5307 intptr_t _linear_result;
5308 intptr_t _table_result;
5309 };
5310
5311 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
5312 Klass::on_secondary_supers_verification_failure(args->_super,
5313 args->_sub,
5314 args->_linear_result,
5315 args->_table_result,
5316 msg);
5317 }
5318
5319 // Make sure that the hashed lookup and a linear scan agree.
5320 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
5321 Register r_super_klass,
5322 Register result,
5323 Register temp1,
5324 Register temp2,
5325 Register temp3) {
5326 const Register
5327 r_array_index = temp1,
5328 r_array_length = temp2,
5329 r_array_base = temp3,
5330 r_bitmap = noreg;
5331
5332 BLOCK_COMMENT("verify_secondary_supers_table {");
5333
5334 Label L_success, L_failure, L_check, L_done;
5335
5336 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5337 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5338 // And adjust the array base to point to the data.
5339 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5340
5341 testl(r_array_length, r_array_length); // array_length == 0?
5342 jcc(Assembler::zero, L_failure);
5343
5344 movl(r_array_index, 0);
5345 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
5346 // fall through to L_failure
5347
5348 const Register linear_result = r_array_index; // reuse temp1
5349
5350 bind(L_failure); // not present
5351 movl(linear_result, 1);
5352 jmp(L_check);
5353
5354 bind(L_success); // present
5355 movl(linear_result, 0);
5356
5357 bind(L_check);
5358 cmpl(linear_result, result);
5359 jcc(Assembler::equal, L_done);
5360
5361 { // To avoid calling convention issues, build a record on the stack
5362 // and pass the pointer to that instead.
5363 push(result);
5364 push(linear_result);
5365 push(r_sub_klass);
5366 push(r_super_klass);
5367 movptr(c_rarg1, rsp);
5368 movptr(c_rarg0, (uintptr_t) "mismatch");
5369 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
5370 should_not_reach_here();
5371 }
5372 bind(L_done);
5373
5374 BLOCK_COMMENT("} verify_secondary_supers_table");
5375 }
5376
5377 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
5378
5379 #endif // LP64
5380
5381 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
5382 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
5383
5384 Label L_fallthrough;
5385 if (L_fast_path == nullptr) {
5386 L_fast_path = &L_fallthrough;
5387 } else if (L_slow_path == nullptr) {
5388 L_slow_path = &L_fallthrough;
5389 }
5390
5391 // Fast path check: class is fully initialized.
5392 // init_state needs acquire, but x86 is TSO, and so we are already good.
5393 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
5394 jcc(Assembler::equal, *L_fast_path);
5395
5396 // Fast path check: current thread is initializer thread
5397 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
5398 if (L_slow_path == &L_fallthrough) {
5399 jcc(Assembler::equal, *L_fast_path);
5400 bind(*L_slow_path);
5401 } else if (L_fast_path == &L_fallthrough) {
5402 jcc(Assembler::notEqual, *L_slow_path);
5403 bind(*L_fast_path);
5404 } else {
5405 Unimplemented();
5406 }
5407 }
5408
5409 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5410 if (VM_Version::supports_cmov()) {
5411 cmovl(cc, dst, src);
5412 } else {
5413 Label L;
5414 jccb(negate_condition(cc), L);
5415 movl(dst, src);
5416 bind(L);
5417 }
5418 }
5419
5420 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5421 if (VM_Version::supports_cmov()) {
5422 cmovl(cc, dst, src);
5423 } else {
5424 Label L;
5425 jccb(negate_condition(cc), L);
5426 movl(dst, src);
5427 bind(L);
5428 }
5429 }
5430
5431 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
5432 if (!VerifyOops) return;
5433
5434 BLOCK_COMMENT("verify_oop {");
5435 #ifdef _LP64
5436 push(rscratch1);
5437 #endif
5438 push(rax); // save rax
5439 push(reg); // pass register argument
5440
5441 // Pass register number to verify_oop_subroutine
5442 const char* b = nullptr;
5443 {
5444 ResourceMark rm;
5445 stringStream ss;
5446 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5447 b = code_string(ss.as_string());
5448 }
5449 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5450 pushptr(buffer.addr(), rscratch1);
5451
5452 // call indirectly to solve generation ordering problem
5453 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5454 call(rax);
5455 // Caller pops the arguments (oop, message) and restores rax, r10
5456 BLOCK_COMMENT("} verify_oop");
5457 }
5458
5459 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
5460 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
5461 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
5462 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
5463 vpternlogd(dst, 0xFF, dst, dst, vector_len);
5464 } else if (VM_Version::supports_avx()) {
5465 vpcmpeqd(dst, dst, dst, vector_len);
5466 } else {
5467 pcmpeqd(dst, dst);
5468 }
5469 }
5470
5471 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5472 int extra_slot_offset) {
5473 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5474 int stackElementSize = Interpreter::stackElementSize;
5475 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5476 #ifdef ASSERT
5477 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5478 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5479 #endif
5480 Register scale_reg = noreg;
5481 Address::ScaleFactor scale_factor = Address::no_scale;
5482 if (arg_slot.is_constant()) {
5483 offset += arg_slot.as_constant() * stackElementSize;
5484 } else {
5485 scale_reg = arg_slot.as_register();
5486 scale_factor = Address::times(stackElementSize);
5487 }
5488 offset += wordSize; // return PC is on stack
5489 return Address(rsp, scale_reg, scale_factor, offset);
5490 }
5491
5492 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5493 if (!VerifyOops) return;
5494
5495 #ifdef _LP64
5496 push(rscratch1);
5497 #endif
5498 push(rax); // save rax,
5499 // addr may contain rsp so we will have to adjust it based on the push
5500 // we just did (and on 64 bit we do two pushes)
5501 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5502 // stores rax into addr which is backwards of what was intended.
5503 if (addr.uses(rsp)) {
5504 lea(rax, addr);
5505 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5506 } else {
5507 pushptr(addr);
5508 }
5509
5510 // Pass register number to verify_oop_subroutine
5511 const char* b = nullptr;
5512 {
5513 ResourceMark rm;
5514 stringStream ss;
5515 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5516 b = code_string(ss.as_string());
5517 }
5518 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5519 pushptr(buffer.addr(), rscratch1);
5520
5521 // call indirectly to solve generation ordering problem
5522 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5523 call(rax);
5524 // Caller pops the arguments (addr, message) and restores rax, r10.
5525 }
5526
5527 void MacroAssembler::verify_tlab() {
5528 #ifdef ASSERT
5529 if (UseTLAB && VerifyOops) {
5530 Label next, ok;
5531 Register t1 = rsi;
5532 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5533
5534 push(t1);
5535 NOT_LP64(push(thread_reg));
5536 NOT_LP64(get_thread(thread_reg));
5537
5538 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5539 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5540 jcc(Assembler::aboveEqual, next);
5541 STOP("assert(top >= start)");
5542 should_not_reach_here();
5543
5544 bind(next);
5545 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5546 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5547 jcc(Assembler::aboveEqual, ok);
5548 STOP("assert(top <= end)");
5549 should_not_reach_here();
5550
5551 bind(ok);
5552 NOT_LP64(pop(thread_reg));
5553 pop(t1);
5554 }
5555 #endif
5556 }
5557
5558 class ControlWord {
5559 public:
5560 int32_t _value;
5561
5562 int rounding_control() const { return (_value >> 10) & 3 ; }
5563 int precision_control() const { return (_value >> 8) & 3 ; }
5564 bool precision() const { return ((_value >> 5) & 1) != 0; }
5565 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5566 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5567 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5568 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5569 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5570
5571 void print() const {
5572 // rounding control
5573 const char* rc;
5574 switch (rounding_control()) {
5575 case 0: rc = "round near"; break;
5576 case 1: rc = "round down"; break;
5577 case 2: rc = "round up "; break;
5578 case 3: rc = "chop "; break;
5579 default:
5580 rc = nullptr; // silence compiler warnings
5581 fatal("Unknown rounding control: %d", rounding_control());
5582 };
5583 // precision control
5584 const char* pc;
5585 switch (precision_control()) {
5586 case 0: pc = "24 bits "; break;
5587 case 1: pc = "reserved"; break;
5588 case 2: pc = "53 bits "; break;
5589 case 3: pc = "64 bits "; break;
5590 default:
5591 pc = nullptr; // silence compiler warnings
5592 fatal("Unknown precision control: %d", precision_control());
5593 };
5594 // flags
5595 char f[9];
5596 f[0] = ' ';
5597 f[1] = ' ';
5598 f[2] = (precision ()) ? 'P' : 'p';
5599 f[3] = (underflow ()) ? 'U' : 'u';
5600 f[4] = (overflow ()) ? 'O' : 'o';
5601 f[5] = (zero_divide ()) ? 'Z' : 'z';
5602 f[6] = (denormalized()) ? 'D' : 'd';
5603 f[7] = (invalid ()) ? 'I' : 'i';
5604 f[8] = '\x0';
5605 // output
5606 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5607 }
5608
5609 };
5610
5611 class StatusWord {
5612 public:
5613 int32_t _value;
5614
5615 bool busy() const { return ((_value >> 15) & 1) != 0; }
5616 bool C3() const { return ((_value >> 14) & 1) != 0; }
5617 bool C2() const { return ((_value >> 10) & 1) != 0; }
5618 bool C1() const { return ((_value >> 9) & 1) != 0; }
5619 bool C0() const { return ((_value >> 8) & 1) != 0; }
5620 int top() const { return (_value >> 11) & 7 ; }
5621 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5622 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5623 bool precision() const { return ((_value >> 5) & 1) != 0; }
5624 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5625 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5626 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5627 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5628 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5629
5630 void print() const {
5631 // condition codes
5632 char c[5];
5633 c[0] = (C3()) ? '3' : '-';
5634 c[1] = (C2()) ? '2' : '-';
5635 c[2] = (C1()) ? '1' : '-';
5636 c[3] = (C0()) ? '0' : '-';
5637 c[4] = '\x0';
5638 // flags
5639 char f[9];
5640 f[0] = (error_status()) ? 'E' : '-';
5641 f[1] = (stack_fault ()) ? 'S' : '-';
5642 f[2] = (precision ()) ? 'P' : '-';
5643 f[3] = (underflow ()) ? 'U' : '-';
5644 f[4] = (overflow ()) ? 'O' : '-';
5645 f[5] = (zero_divide ()) ? 'Z' : '-';
5646 f[6] = (denormalized()) ? 'D' : '-';
5647 f[7] = (invalid ()) ? 'I' : '-';
5648 f[8] = '\x0';
5649 // output
5650 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5651 }
5652
5653 };
5654
5655 class TagWord {
5656 public:
5657 int32_t _value;
5658
5659 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5660
5661 void print() const {
5662 printf("%04x", _value & 0xFFFF);
5663 }
5664
5665 };
5666
5667 class FPU_Register {
5668 public:
5669 int32_t _m0;
5670 int32_t _m1;
5671 int16_t _ex;
5672
5673 bool is_indefinite() const {
5674 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5675 }
5676
5677 void print() const {
5678 char sign = (_ex < 0) ? '-' : '+';
5679 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5680 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5681 };
5682
5683 };
5684
5685 class FPU_State {
5686 public:
5687 enum {
5688 register_size = 10,
5689 number_of_registers = 8,
5690 register_mask = 7
5691 };
5692
5693 ControlWord _control_word;
5694 StatusWord _status_word;
5695 TagWord _tag_word;
5696 int32_t _error_offset;
5697 int32_t _error_selector;
5698 int32_t _data_offset;
5699 int32_t _data_selector;
5700 int8_t _register[register_size * number_of_registers];
5701
5702 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5703 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5704
5705 const char* tag_as_string(int tag) const {
5706 switch (tag) {
5707 case 0: return "valid";
5708 case 1: return "zero";
5709 case 2: return "special";
5710 case 3: return "empty";
5711 }
5712 ShouldNotReachHere();
5713 return nullptr;
5714 }
5715
5716 void print() const {
5717 // print computation registers
5718 { int t = _status_word.top();
5719 for (int i = 0; i < number_of_registers; i++) {
5720 int j = (i - t) & register_mask;
5721 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5722 st(j)->print();
5723 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5724 }
5725 }
5726 printf("\n");
5727 // print control registers
5728 printf("ctrl = "); _control_word.print(); printf("\n");
5729 printf("stat = "); _status_word .print(); printf("\n");
5730 printf("tags = "); _tag_word .print(); printf("\n");
5731 }
5732
5733 };
5734
5735 class Flag_Register {
5736 public:
5737 int32_t _value;
5738
5739 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5740 bool direction() const { return ((_value >> 10) & 1) != 0; }
5741 bool sign() const { return ((_value >> 7) & 1) != 0; }
5742 bool zero() const { return ((_value >> 6) & 1) != 0; }
5743 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5744 bool parity() const { return ((_value >> 2) & 1) != 0; }
5745 bool carry() const { return ((_value >> 0) & 1) != 0; }
5746
5747 void print() const {
5748 // flags
5749 char f[8];
5750 f[0] = (overflow ()) ? 'O' : '-';
5751 f[1] = (direction ()) ? 'D' : '-';
5752 f[2] = (sign ()) ? 'S' : '-';
5753 f[3] = (zero ()) ? 'Z' : '-';
5754 f[4] = (auxiliary_carry()) ? 'A' : '-';
5755 f[5] = (parity ()) ? 'P' : '-';
5756 f[6] = (carry ()) ? 'C' : '-';
5757 f[7] = '\x0';
5758 // output
5759 printf("%08x flags = %s", _value, f);
5760 }
5761
5762 };
5763
5764 class IU_Register {
5765 public:
5766 int32_t _value;
5767
5768 void print() const {
5769 printf("%08x %11d", _value, _value);
5770 }
5771
5772 };
5773
5774 class IU_State {
5775 public:
5776 Flag_Register _eflags;
5777 IU_Register _rdi;
5778 IU_Register _rsi;
5779 IU_Register _rbp;
5780 IU_Register _rsp;
5781 IU_Register _rbx;
5782 IU_Register _rdx;
5783 IU_Register _rcx;
5784 IU_Register _rax;
5785
5786 void print() const {
5787 // computation registers
5788 printf("rax, = "); _rax.print(); printf("\n");
5789 printf("rbx, = "); _rbx.print(); printf("\n");
5790 printf("rcx = "); _rcx.print(); printf("\n");
5791 printf("rdx = "); _rdx.print(); printf("\n");
5792 printf("rdi = "); _rdi.print(); printf("\n");
5793 printf("rsi = "); _rsi.print(); printf("\n");
5794 printf("rbp, = "); _rbp.print(); printf("\n");
5795 printf("rsp = "); _rsp.print(); printf("\n");
5796 printf("\n");
5797 // control registers
5798 printf("flgs = "); _eflags.print(); printf("\n");
5799 }
5800 };
5801
5802
5803 class CPU_State {
5804 public:
5805 FPU_State _fpu_state;
5806 IU_State _iu_state;
5807
5808 void print() const {
5809 printf("--------------------------------------------------\n");
5810 _iu_state .print();
5811 printf("\n");
5812 _fpu_state.print();
5813 printf("--------------------------------------------------\n");
5814 }
5815
5816 };
5817
5818
5819 static void _print_CPU_state(CPU_State* state) {
5820 state->print();
5821 };
5822
5823
5824 void MacroAssembler::print_CPU_state() {
5825 push_CPU_state();
5826 push(rsp); // pass CPU state
5827 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5828 addptr(rsp, wordSize); // discard argument
5829 pop_CPU_state();
5830 }
5831
5832
5833 #ifndef _LP64
5834 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5835 static int counter = 0;
5836 FPU_State* fs = &state->_fpu_state;
5837 counter++;
5838 // For leaf calls, only verify that the top few elements remain empty.
5839 // We only need 1 empty at the top for C2 code.
5840 if( stack_depth < 0 ) {
5841 if( fs->tag_for_st(7) != 3 ) {
5842 printf("FPR7 not empty\n");
5843 state->print();
5844 assert(false, "error");
5845 return false;
5846 }
5847 return true; // All other stack states do not matter
5848 }
5849
5850 assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
5851 "bad FPU control word");
5852
5853 // compute stack depth
5854 int i = 0;
5855 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5856 int d = i;
5857 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5858 // verify findings
5859 if (i != FPU_State::number_of_registers) {
5860 // stack not contiguous
5861 printf("%s: stack not contiguous at ST%d\n", s, i);
5862 state->print();
5863 assert(false, "error");
5864 return false;
5865 }
5866 // check if computed stack depth corresponds to expected stack depth
5867 if (stack_depth < 0) {
5868 // expected stack depth is -stack_depth or less
5869 if (d > -stack_depth) {
5870 // too many elements on the stack
5871 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5872 state->print();
5873 assert(false, "error");
5874 return false;
5875 }
5876 } else {
5877 // expected stack depth is stack_depth
5878 if (d != stack_depth) {
5879 // wrong stack depth
5880 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5881 state->print();
5882 assert(false, "error");
5883 return false;
5884 }
5885 }
5886 // everything is cool
5887 return true;
5888 }
5889
5890 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5891 if (!VerifyFPU) return;
5892 push_CPU_state();
5893 push(rsp); // pass CPU state
5894 ExternalAddress msg((address) s);
5895 // pass message string s
5896 pushptr(msg.addr(), noreg);
5897 push(stack_depth); // pass stack depth
5898 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5899 addptr(rsp, 3 * wordSize); // discard arguments
5900 // check for error
5901 { Label L;
5902 testl(rax, rax);
5903 jcc(Assembler::notZero, L);
5904 int3(); // break if error condition
5905 bind(L);
5906 }
5907 pop_CPU_state();
5908 }
5909 #endif // _LP64
5910
5911 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5912 // Either restore the MXCSR register after returning from the JNI Call
5913 // or verify that it wasn't changed (with -Xcheck:jni flag).
5914 if (VM_Version::supports_sse()) {
5915 if (RestoreMXCSROnJNICalls) {
5916 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5917 } else if (CheckJNICalls) {
5918 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5919 }
5920 }
5921 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5922 vzeroupper();
5923
5924 #ifndef _LP64
5925 // Either restore the x87 floating pointer control word after returning
5926 // from the JNI call or verify that it wasn't changed.
5927 if (CheckJNICalls) {
5928 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5929 }
5930 #endif // _LP64
5931 }
5932
5933 // ((OopHandle)result).resolve();
5934 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5935 assert_different_registers(result, tmp);
5936
5937 // Only 64 bit platforms support GCs that require a tmp register
5938 // Only IN_HEAP loads require a thread_tmp register
5939 // OopHandle::resolve is an indirection like jobject.
5940 access_load_at(T_OBJECT, IN_NATIVE,
5941 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5942 }
5943
5944 // ((WeakHandle)result).resolve();
5945 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5946 assert_different_registers(rresult, rtmp);
5947 Label resolved;
5948
5949 // A null weak handle resolves to null.
5950 cmpptr(rresult, 0);
5951 jcc(Assembler::equal, resolved);
5952
5953 // Only 64 bit platforms support GCs that require a tmp register
5954 // Only IN_HEAP loads require a thread_tmp register
5955 // WeakHandle::resolve is an indirection like jweak.
5956 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5957 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
5958 bind(resolved);
5959 }
5960
5961 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5962 // get mirror
5963 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5964 load_method_holder(mirror, method);
5965 movptr(mirror, Address(mirror, mirror_offset));
5966 resolve_oop_handle(mirror, tmp);
5967 }
5968
5969 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5970 load_method_holder(rresult, rmethod);
5971 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5972 }
5973
5974 void MacroAssembler::load_method_holder(Register holder, Register method) {
5975 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5976 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5977 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5978 }
5979
5980 #ifdef _LP64
5981 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5982 assert(UseCompactObjectHeaders, "expect compact object headers");
5983 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5984 shrq(dst, markWord::klass_shift);
5985 }
5986 #endif
5987
5988 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5989 assert_different_registers(src, tmp);
5990 assert_different_registers(dst, tmp);
5991 #ifdef _LP64
5992 if (UseCompactObjectHeaders) {
5993 load_narrow_klass_compact(dst, src);
5994 decode_klass_not_null(dst, tmp);
5995 } else if (UseCompressedClassPointers) {
5996 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5997 decode_klass_not_null(dst, tmp);
5998 } else
5999 #endif
6000 {
6001 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6002 }
6003 }
6004
6005 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
6006 assert(!UseCompactObjectHeaders, "not with compact headers");
6007 assert_different_registers(src, tmp);
6008 assert_different_registers(dst, tmp);
6009 #ifdef _LP64
6010 if (UseCompressedClassPointers) {
6011 encode_klass_not_null(src, tmp);
6012 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6013 } else
6014 #endif
6015 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6016 }
6017
6018 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
6019 #ifdef _LP64
6020 if (UseCompactObjectHeaders) {
6021 assert(tmp != noreg, "need tmp");
6022 assert_different_registers(klass, obj, tmp);
6023 load_narrow_klass_compact(tmp, obj);
6024 cmpl(klass, tmp);
6025 } else if (UseCompressedClassPointers) {
6026 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
6027 } else
6028 #endif
6029 {
6030 cmpptr(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
6031 }
6032 }
6033
6034 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
6035 #ifdef _LP64
6036 if (UseCompactObjectHeaders) {
6037 assert(tmp2 != noreg, "need tmp2");
6038 assert_different_registers(obj1, obj2, tmp1, tmp2);
6039 load_narrow_klass_compact(tmp1, obj1);
6040 load_narrow_klass_compact(tmp2, obj2);
6041 cmpl(tmp1, tmp2);
6042 } else if (UseCompressedClassPointers) {
6043 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
6044 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
6045 } else
6046 #endif
6047 {
6048 movptr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
6049 cmpptr(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
6050 }
6051 }
6052
6053 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
6054 Register tmp1, Register thread_tmp) {
6055 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6056 decorators = AccessInternal::decorator_fixup(decorators, type);
6057 bool as_raw = (decorators & AS_RAW) != 0;
6058 if (as_raw) {
6059 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6060 } else {
6061 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6062 }
6063 }
6064
6065 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
6066 Register tmp1, Register tmp2, Register tmp3) {
6067 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6068 decorators = AccessInternal::decorator_fixup(decorators, type);
6069 bool as_raw = (decorators & AS_RAW) != 0;
6070 if (as_raw) {
6071 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6072 } else {
6073 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6074 }
6075 }
6076
6077 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
6078 Register thread_tmp, DecoratorSet decorators) {
6079 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
6080 }
6081
6082 // Doesn't do verification, generates fixed size code
6083 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
6084 Register thread_tmp, DecoratorSet decorators) {
6085 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
6086 }
6087
6088 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
6089 Register tmp2, Register tmp3, DecoratorSet decorators) {
6090 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
6091 }
6092
6093 // Used for storing nulls.
6094 void MacroAssembler::store_heap_oop_null(Address dst) {
6095 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
6096 }
6097
6098 #ifdef _LP64
6099 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6100 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
6101 if (UseCompressedClassPointers) {
6102 // Store to klass gap in destination
6103 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6104 }
6105 }
6106
6107 #ifdef ASSERT
6108 void MacroAssembler::verify_heapbase(const char* msg) {
6109 assert (UseCompressedOops, "should be compressed");
6110 assert (Universe::heap() != nullptr, "java heap should be initialized");
6111 if (CheckCompressedOops) {
6112 Label ok;
6113 ExternalAddress src2(CompressedOops::base_addr());
6114 const bool is_src2_reachable = reachable(src2);
6115 if (!is_src2_reachable) {
6116 push(rscratch1); // cmpptr trashes rscratch1
6117 }
6118 cmpptr(r12_heapbase, src2, rscratch1);
6119 jcc(Assembler::equal, ok);
6120 STOP(msg);
6121 bind(ok);
6122 if (!is_src2_reachable) {
6123 pop(rscratch1);
6124 }
6125 }
6126 }
6127 #endif
6128
6129 // Algorithm must match oop.inline.hpp encode_heap_oop.
6130 void MacroAssembler::encode_heap_oop(Register r) {
6131 #ifdef ASSERT
6132 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6133 #endif
6134 verify_oop_msg(r, "broken oop in encode_heap_oop");
6135 if (CompressedOops::base() == nullptr) {
6136 if (CompressedOops::shift() != 0) {
6137 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6138 shrq(r, LogMinObjAlignmentInBytes);
6139 }
6140 return;
6141 }
6142 testq(r, r);
6143 cmovq(Assembler::equal, r, r12_heapbase);
6144 subq(r, r12_heapbase);
6145 shrq(r, LogMinObjAlignmentInBytes);
6146 }
6147
6148 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6149 #ifdef ASSERT
6150 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6151 if (CheckCompressedOops) {
6152 Label ok;
6153 testq(r, r);
6154 jcc(Assembler::notEqual, ok);
6155 STOP("null oop passed to encode_heap_oop_not_null");
6156 bind(ok);
6157 }
6158 #endif
6159 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
6160 if (CompressedOops::base() != nullptr) {
6161 subq(r, r12_heapbase);
6162 }
6163 if (CompressedOops::shift() != 0) {
6164 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6165 shrq(r, LogMinObjAlignmentInBytes);
6166 }
6167 }
6168
6169 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6170 #ifdef ASSERT
6171 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6172 if (CheckCompressedOops) {
6173 Label ok;
6174 testq(src, src);
6175 jcc(Assembler::notEqual, ok);
6176 STOP("null oop passed to encode_heap_oop_not_null2");
6177 bind(ok);
6178 }
6179 #endif
6180 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
6181 if (dst != src) {
6182 movq(dst, src);
6183 }
6184 if (CompressedOops::base() != nullptr) {
6185 subq(dst, r12_heapbase);
6186 }
6187 if (CompressedOops::shift() != 0) {
6188 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6189 shrq(dst, LogMinObjAlignmentInBytes);
6190 }
6191 }
6192
6193 void MacroAssembler::decode_heap_oop(Register r) {
6194 #ifdef ASSERT
6195 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6196 #endif
6197 if (CompressedOops::base() == nullptr) {
6198 if (CompressedOops::shift() != 0) {
6199 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6200 shlq(r, LogMinObjAlignmentInBytes);
6201 }
6202 } else {
6203 Label done;
6204 shlq(r, LogMinObjAlignmentInBytes);
6205 jccb(Assembler::equal, done);
6206 addq(r, r12_heapbase);
6207 bind(done);
6208 }
6209 verify_oop_msg(r, "broken oop in decode_heap_oop");
6210 }
6211
6212 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6213 // Note: it will change flags
6214 assert (UseCompressedOops, "should only be used for compressed headers");
6215 assert (Universe::heap() != nullptr, "java heap should be initialized");
6216 // Cannot assert, unverified entry point counts instructions (see .ad file)
6217 // vtableStubs also counts instructions in pd_code_size_limit.
6218 // Also do not verify_oop as this is called by verify_oop.
6219 if (CompressedOops::shift() != 0) {
6220 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6221 shlq(r, LogMinObjAlignmentInBytes);
6222 if (CompressedOops::base() != nullptr) {
6223 addq(r, r12_heapbase);
6224 }
6225 } else {
6226 assert (CompressedOops::base() == nullptr, "sanity");
6227 }
6228 }
6229
6230 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6231 // Note: it will change flags
6232 assert (UseCompressedOops, "should only be used for compressed headers");
6233 assert (Universe::heap() != nullptr, "java heap should be initialized");
6234 // Cannot assert, unverified entry point counts instructions (see .ad file)
6235 // vtableStubs also counts instructions in pd_code_size_limit.
6236 // Also do not verify_oop as this is called by verify_oop.
6237 if (CompressedOops::shift() != 0) {
6238 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6239 if (LogMinObjAlignmentInBytes == Address::times_8) {
6240 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6241 } else {
6242 if (dst != src) {
6243 movq(dst, src);
6244 }
6245 shlq(dst, LogMinObjAlignmentInBytes);
6246 if (CompressedOops::base() != nullptr) {
6247 addq(dst, r12_heapbase);
6248 }
6249 }
6250 } else {
6251 assert (CompressedOops::base() == nullptr, "sanity");
6252 if (dst != src) {
6253 movq(dst, src);
6254 }
6255 }
6256 }
6257
6258 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
6259 assert_different_registers(r, tmp);
6260 if (CompressedKlassPointers::base() != nullptr) {
6261 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6262 subq(r, tmp);
6263 }
6264 if (CompressedKlassPointers::shift() != 0) {
6265 shrq(r, CompressedKlassPointers::shift());
6266 }
6267 }
6268
6269 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
6270 assert_different_registers(src, dst);
6271 if (CompressedKlassPointers::base() != nullptr) {
6272 mov64(dst, -(int64_t)CompressedKlassPointers::base());
6273 addq(dst, src);
6274 } else {
6275 movptr(dst, src);
6276 }
6277 if (CompressedKlassPointers::shift() != 0) {
6278 shrq(dst, CompressedKlassPointers::shift());
6279 }
6280 }
6281
6282 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
6283 assert_different_registers(r, tmp);
6284 // Note: it will change flags
6285 assert(UseCompressedClassPointers, "should only be used for compressed headers");
6286 // Cannot assert, unverified entry point counts instructions (see .ad file)
6287 // vtableStubs also counts instructions in pd_code_size_limit.
6288 // Also do not verify_oop as this is called by verify_oop.
6289 if (CompressedKlassPointers::shift() != 0) {
6290 shlq(r, CompressedKlassPointers::shift());
6291 }
6292 if (CompressedKlassPointers::base() != nullptr) {
6293 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6294 addq(r, tmp);
6295 }
6296 }
6297
6298 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
6299 assert_different_registers(src, dst);
6300 // Note: it will change flags
6301 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6302 // Cannot assert, unverified entry point counts instructions (see .ad file)
6303 // vtableStubs also counts instructions in pd_code_size_limit.
6304 // Also do not verify_oop as this is called by verify_oop.
6305
6306 if (CompressedKlassPointers::base() == nullptr &&
6307 CompressedKlassPointers::shift() == 0) {
6308 // The best case scenario is that there is no base or shift. Then it is already
6309 // a pointer that needs nothing but a register rename.
6310 movl(dst, src);
6311 } else {
6312 if (CompressedKlassPointers::shift() <= Address::times_8) {
6313 if (CompressedKlassPointers::base() != nullptr) {
6314 mov64(dst, (int64_t)CompressedKlassPointers::base());
6315 } else {
6316 xorq(dst, dst);
6317 }
6318 if (CompressedKlassPointers::shift() != 0) {
6319 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
6320 leaq(dst, Address(dst, src, Address::times_8, 0));
6321 } else {
6322 addq(dst, src);
6323 }
6324 } else {
6325 if (CompressedKlassPointers::base() != nullptr) {
6326 const uint64_t base_right_shifted =
6327 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
6328 mov64(dst, base_right_shifted);
6329 } else {
6330 xorq(dst, dst);
6331 }
6332 addq(dst, src);
6333 shlq(dst, CompressedKlassPointers::shift());
6334 }
6335 }
6336 }
6337
6338 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6339 assert (UseCompressedOops, "should only be used for compressed headers");
6340 assert (Universe::heap() != nullptr, "java heap should be initialized");
6341 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6342 int oop_index = oop_recorder()->find_index(obj);
6343 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6344 mov_narrow_oop(dst, oop_index, rspec);
6345 }
6346
6347 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6348 assert (UseCompressedOops, "should only be used for compressed headers");
6349 assert (Universe::heap() != nullptr, "java heap should be initialized");
6350 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6351 int oop_index = oop_recorder()->find_index(obj);
6352 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6353 mov_narrow_oop(dst, oop_index, rspec);
6354 }
6355
6356 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6357 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6358 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6359 int klass_index = oop_recorder()->find_index(k);
6360 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6361 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6362 }
6363
6364 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6365 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6366 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6367 int klass_index = oop_recorder()->find_index(k);
6368 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6369 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6370 }
6371
6372 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6373 assert (UseCompressedOops, "should only be used for compressed headers");
6374 assert (Universe::heap() != nullptr, "java heap should be initialized");
6375 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6376 int oop_index = oop_recorder()->find_index(obj);
6377 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6378 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6379 }
6380
6381 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6382 assert (UseCompressedOops, "should only be used for compressed headers");
6383 assert (Universe::heap() != nullptr, "java heap should be initialized");
6384 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6385 int oop_index = oop_recorder()->find_index(obj);
6386 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6387 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6388 }
6389
6390 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6391 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6392 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6393 int klass_index = oop_recorder()->find_index(k);
6394 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6395 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6396 }
6397
6398 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6399 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6400 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6401 int klass_index = oop_recorder()->find_index(k);
6402 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6403 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6404 }
6405
6406 void MacroAssembler::reinit_heapbase() {
6407 if (UseCompressedOops) {
6408 if (Universe::heap() != nullptr) {
6409 if (CompressedOops::base() == nullptr) {
6410 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6411 } else {
6412 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6413 }
6414 } else {
6415 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6416 }
6417 }
6418 }
6419
6420 #endif // _LP64
6421
6422 #if COMPILER2_OR_JVMCI
6423
6424 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6425 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6426 // cnt - number of qwords (8-byte words).
6427 // base - start address, qword aligned.
6428 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6429 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
6430 if (use64byteVector) {
6431 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
6432 } else if (MaxVectorSize >= 32) {
6433 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
6434 } else {
6435 pxor(xtmp, xtmp);
6436 }
6437 jmp(L_zero_64_bytes);
6438
6439 BIND(L_loop);
6440 if (MaxVectorSize >= 32) {
6441 fill64(base, 0, xtmp, use64byteVector);
6442 } else {
6443 movdqu(Address(base, 0), xtmp);
6444 movdqu(Address(base, 16), xtmp);
6445 movdqu(Address(base, 32), xtmp);
6446 movdqu(Address(base, 48), xtmp);
6447 }
6448 addptr(base, 64);
6449
6450 BIND(L_zero_64_bytes);
6451 subptr(cnt, 8);
6452 jccb(Assembler::greaterEqual, L_loop);
6453
6454 // Copy trailing 64 bytes
6455 if (use64byteVector) {
6456 addptr(cnt, 8);
6457 jccb(Assembler::equal, L_end);
6458 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
6459 jmp(L_end);
6460 } else {
6461 addptr(cnt, 4);
6462 jccb(Assembler::less, L_tail);
6463 if (MaxVectorSize >= 32) {
6464 vmovdqu(Address(base, 0), xtmp);
6465 } else {
6466 movdqu(Address(base, 0), xtmp);
6467 movdqu(Address(base, 16), xtmp);
6468 }
6469 }
6470 addptr(base, 32);
6471 subptr(cnt, 4);
6472
6473 BIND(L_tail);
6474 addptr(cnt, 4);
6475 jccb(Assembler::lessEqual, L_end);
6476 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6477 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
6478 } else {
6479 decrement(cnt);
6480
6481 BIND(L_sloop);
6482 movq(Address(base, 0), xtmp);
6483 addptr(base, 8);
6484 decrement(cnt);
6485 jccb(Assembler::greaterEqual, L_sloop);
6486 }
6487 BIND(L_end);
6488 }
6489
6490 // Clearing constant sized memory using YMM/ZMM registers.
6491 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6492 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6493 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
6494
6495 int vector64_count = (cnt & (~0x7)) >> 3;
6496 cnt = cnt & 0x7;
6497 const int fill64_per_loop = 4;
6498 const int max_unrolled_fill64 = 8;
6499
6500 // 64 byte initialization loop.
6501 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6502 int start64 = 0;
6503 if (vector64_count > max_unrolled_fill64) {
6504 Label LOOP;
6505 Register index = rtmp;
6506
6507 start64 = vector64_count - (vector64_count % fill64_per_loop);
6508
6509 movl(index, 0);
6510 BIND(LOOP);
6511 for (int i = 0; i < fill64_per_loop; i++) {
6512 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6513 }
6514 addl(index, fill64_per_loop * 64);
6515 cmpl(index, start64 * 64);
6516 jccb(Assembler::less, LOOP);
6517 }
6518 for (int i = start64; i < vector64_count; i++) {
6519 fill64(base, i * 64, xtmp, use64byteVector);
6520 }
6521
6522 // Clear remaining 64 byte tail.
6523 int disp = vector64_count * 64;
6524 if (cnt) {
6525 switch (cnt) {
6526 case 1:
6527 movq(Address(base, disp), xtmp);
6528 break;
6529 case 2:
6530 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6531 break;
6532 case 3:
6533 movl(rtmp, 0x7);
6534 kmovwl(mask, rtmp);
6535 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6536 break;
6537 case 4:
6538 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6539 break;
6540 case 5:
6541 if (use64byteVector) {
6542 movl(rtmp, 0x1F);
6543 kmovwl(mask, rtmp);
6544 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6545 } else {
6546 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6547 movq(Address(base, disp + 32), xtmp);
6548 }
6549 break;
6550 case 6:
6551 if (use64byteVector) {
6552 movl(rtmp, 0x3F);
6553 kmovwl(mask, rtmp);
6554 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6555 } else {
6556 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6557 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6558 }
6559 break;
6560 case 7:
6561 if (use64byteVector) {
6562 movl(rtmp, 0x7F);
6563 kmovwl(mask, rtmp);
6564 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6565 } else {
6566 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6567 movl(rtmp, 0x7);
6568 kmovwl(mask, rtmp);
6569 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6570 }
6571 break;
6572 default:
6573 fatal("Unexpected length : %d\n",cnt);
6574 break;
6575 }
6576 }
6577 }
6578
6579 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
6580 bool is_large, KRegister mask) {
6581 // cnt - number of qwords (8-byte words).
6582 // base - start address, qword aligned.
6583 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6584 assert(base==rdi, "base register must be edi for rep stos");
6585 assert(tmp==rax, "tmp register must be eax for rep stos");
6586 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6587 assert(InitArrayShortSize % BytesPerLong == 0,
6588 "InitArrayShortSize should be the multiple of BytesPerLong");
6589
6590 Label DONE;
6591 if (!is_large || !UseXMMForObjInit) {
6592 xorptr(tmp, tmp);
6593 }
6594
6595 if (!is_large) {
6596 Label LOOP, LONG;
6597 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6598 jccb(Assembler::greater, LONG);
6599
6600 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6601
6602 decrement(cnt);
6603 jccb(Assembler::negative, DONE); // Zero length
6604
6605 // Use individual pointer-sized stores for small counts:
6606 BIND(LOOP);
6607 movptr(Address(base, cnt, Address::times_ptr), tmp);
6608 decrement(cnt);
6609 jccb(Assembler::greaterEqual, LOOP);
6610 jmpb(DONE);
6611
6612 BIND(LONG);
6613 }
6614
6615 // Use longer rep-prefixed ops for non-small counts:
6616 if (UseFastStosb) {
6617 shlptr(cnt, 3); // convert to number of bytes
6618 rep_stosb();
6619 } else if (UseXMMForObjInit) {
6620 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
6621 } else {
6622 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6623 rep_stos();
6624 }
6625
6626 BIND(DONE);
6627 }
6628
6629 #endif //COMPILER2_OR_JVMCI
6630
6631
6632 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6633 Register to, Register value, Register count,
6634 Register rtmp, XMMRegister xtmp) {
6635 ShortBranchVerifier sbv(this);
6636 assert_different_registers(to, value, count, rtmp);
6637 Label L_exit;
6638 Label L_fill_2_bytes, L_fill_4_bytes;
6639
6640 #if defined(COMPILER2) && defined(_LP64)
6641 if(MaxVectorSize >=32 &&
6642 VM_Version::supports_avx512vlbw() &&
6643 VM_Version::supports_bmi2()) {
6644 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6645 return;
6646 }
6647 #endif
6648
6649 int shift = -1;
6650 switch (t) {
6651 case T_BYTE:
6652 shift = 2;
6653 break;
6654 case T_SHORT:
6655 shift = 1;
6656 break;
6657 case T_INT:
6658 shift = 0;
6659 break;
6660 default: ShouldNotReachHere();
6661 }
6662
6663 if (t == T_BYTE) {
6664 andl(value, 0xff);
6665 movl(rtmp, value);
6666 shll(rtmp, 8);
6667 orl(value, rtmp);
6668 }
6669 if (t == T_SHORT) {
6670 andl(value, 0xffff);
6671 }
6672 if (t == T_BYTE || t == T_SHORT) {
6673 movl(rtmp, value);
6674 shll(rtmp, 16);
6675 orl(value, rtmp);
6676 }
6677
6678 cmpptr(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
6679 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6680 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6681 Label L_skip_align2;
6682 // align source address at 4 bytes address boundary
6683 if (t == T_BYTE) {
6684 Label L_skip_align1;
6685 // One byte misalignment happens only for byte arrays
6686 testptr(to, 1);
6687 jccb(Assembler::zero, L_skip_align1);
6688 movb(Address(to, 0), value);
6689 increment(to);
6690 decrement(count);
6691 BIND(L_skip_align1);
6692 }
6693 // Two bytes misalignment happens only for byte and short (char) arrays
6694 testptr(to, 2);
6695 jccb(Assembler::zero, L_skip_align2);
6696 movw(Address(to, 0), value);
6697 addptr(to, 2);
6698 subptr(count, 1<<(shift-1));
6699 BIND(L_skip_align2);
6700 }
6701 if (UseSSE < 2) {
6702 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6703 // Fill 32-byte chunks
6704 subptr(count, 8 << shift);
6705 jcc(Assembler::less, L_check_fill_8_bytes);
6706 align(16);
6707
6708 BIND(L_fill_32_bytes_loop);
6709
6710 for (int i = 0; i < 32; i += 4) {
6711 movl(Address(to, i), value);
6712 }
6713
6714 addptr(to, 32);
6715 subptr(count, 8 << shift);
6716 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6717 BIND(L_check_fill_8_bytes);
6718 addptr(count, 8 << shift);
6719 jccb(Assembler::zero, L_exit);
6720 jmpb(L_fill_8_bytes);
6721
6722 //
6723 // length is too short, just fill qwords
6724 //
6725 BIND(L_fill_8_bytes_loop);
6726 movl(Address(to, 0), value);
6727 movl(Address(to, 4), value);
6728 addptr(to, 8);
6729 BIND(L_fill_8_bytes);
6730 subptr(count, 1 << (shift + 1));
6731 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6732 // fall through to fill 4 bytes
6733 } else {
6734 Label L_fill_32_bytes;
6735 if (!UseUnalignedLoadStores) {
6736 // align to 8 bytes, we know we are 4 byte aligned to start
6737 testptr(to, 4);
6738 jccb(Assembler::zero, L_fill_32_bytes);
6739 movl(Address(to, 0), value);
6740 addptr(to, 4);
6741 subptr(count, 1<<shift);
6742 }
6743 BIND(L_fill_32_bytes);
6744 {
6745 assert( UseSSE >= 2, "supported cpu only" );
6746 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6747 movdl(xtmp, value);
6748 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6749 Label L_check_fill_32_bytes;
6750 if (UseAVX > 2) {
6751 // Fill 64-byte chunks
6752 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6753
6754 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
6755 cmpptr(count, VM_Version::avx3_threshold());
6756 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6757
6758 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6759
6760 subptr(count, 16 << shift);
6761 jccb(Assembler::less, L_check_fill_32_bytes);
6762 align(16);
6763
6764 BIND(L_fill_64_bytes_loop_avx3);
6765 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6766 addptr(to, 64);
6767 subptr(count, 16 << shift);
6768 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6769 jmpb(L_check_fill_32_bytes);
6770
6771 BIND(L_check_fill_64_bytes_avx2);
6772 }
6773 // Fill 64-byte chunks
6774 Label L_fill_64_bytes_loop;
6775 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6776
6777 subptr(count, 16 << shift);
6778 jcc(Assembler::less, L_check_fill_32_bytes);
6779 align(16);
6780
6781 BIND(L_fill_64_bytes_loop);
6782 vmovdqu(Address(to, 0), xtmp);
6783 vmovdqu(Address(to, 32), xtmp);
6784 addptr(to, 64);
6785 subptr(count, 16 << shift);
6786 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6787
6788 BIND(L_check_fill_32_bytes);
6789 addptr(count, 8 << shift);
6790 jccb(Assembler::less, L_check_fill_8_bytes);
6791 vmovdqu(Address(to, 0), xtmp);
6792 addptr(to, 32);
6793 subptr(count, 8 << shift);
6794
6795 BIND(L_check_fill_8_bytes);
6796 // clean upper bits of YMM registers
6797 movdl(xtmp, value);
6798 pshufd(xtmp, xtmp, 0);
6799 } else {
6800 // Fill 32-byte chunks
6801 pshufd(xtmp, xtmp, 0);
6802
6803 subptr(count, 8 << shift);
6804 jcc(Assembler::less, L_check_fill_8_bytes);
6805 align(16);
6806
6807 BIND(L_fill_32_bytes_loop);
6808
6809 if (UseUnalignedLoadStores) {
6810 movdqu(Address(to, 0), xtmp);
6811 movdqu(Address(to, 16), xtmp);
6812 } else {
6813 movq(Address(to, 0), xtmp);
6814 movq(Address(to, 8), xtmp);
6815 movq(Address(to, 16), xtmp);
6816 movq(Address(to, 24), xtmp);
6817 }
6818
6819 addptr(to, 32);
6820 subptr(count, 8 << shift);
6821 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6822
6823 BIND(L_check_fill_8_bytes);
6824 }
6825 addptr(count, 8 << shift);
6826 jccb(Assembler::zero, L_exit);
6827 jmpb(L_fill_8_bytes);
6828
6829 //
6830 // length is too short, just fill qwords
6831 //
6832 BIND(L_fill_8_bytes_loop);
6833 movq(Address(to, 0), xtmp);
6834 addptr(to, 8);
6835 BIND(L_fill_8_bytes);
6836 subptr(count, 1 << (shift + 1));
6837 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6838 }
6839 }
6840 // fill trailing 4 bytes
6841 BIND(L_fill_4_bytes);
6842 testl(count, 1<<shift);
6843 jccb(Assembler::zero, L_fill_2_bytes);
6844 movl(Address(to, 0), value);
6845 if (t == T_BYTE || t == T_SHORT) {
6846 Label L_fill_byte;
6847 addptr(to, 4);
6848 BIND(L_fill_2_bytes);
6849 // fill trailing 2 bytes
6850 testl(count, 1<<(shift-1));
6851 jccb(Assembler::zero, L_fill_byte);
6852 movw(Address(to, 0), value);
6853 if (t == T_BYTE) {
6854 addptr(to, 2);
6855 BIND(L_fill_byte);
6856 // fill trailing byte
6857 testl(count, 1);
6858 jccb(Assembler::zero, L_exit);
6859 movb(Address(to, 0), value);
6860 } else {
6861 BIND(L_fill_byte);
6862 }
6863 } else {
6864 BIND(L_fill_2_bytes);
6865 }
6866 BIND(L_exit);
6867 }
6868
6869 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6870 switch(type) {
6871 case T_BYTE:
6872 case T_BOOLEAN:
6873 evpbroadcastb(dst, src, vector_len);
6874 break;
6875 case T_SHORT:
6876 case T_CHAR:
6877 evpbroadcastw(dst, src, vector_len);
6878 break;
6879 case T_INT:
6880 case T_FLOAT:
6881 evpbroadcastd(dst, src, vector_len);
6882 break;
6883 case T_LONG:
6884 case T_DOUBLE:
6885 evpbroadcastq(dst, src, vector_len);
6886 break;
6887 default:
6888 fatal("Unhandled type : %s", type2name(type));
6889 break;
6890 }
6891 }
6892
6893 // encode char[] to byte[] in ISO_8859_1 or ASCII
6894 //@IntrinsicCandidate
6895 //private static int implEncodeISOArray(byte[] sa, int sp,
6896 //byte[] da, int dp, int len) {
6897 // int i = 0;
6898 // for (; i < len; i++) {
6899 // char c = StringUTF16.getChar(sa, sp++);
6900 // if (c > '\u00FF')
6901 // break;
6902 // da[dp++] = (byte)c;
6903 // }
6904 // return i;
6905 //}
6906 //
6907 //@IntrinsicCandidate
6908 //private static int implEncodeAsciiArray(char[] sa, int sp,
6909 // byte[] da, int dp, int len) {
6910 // int i = 0;
6911 // for (; i < len; i++) {
6912 // char c = sa[sp++];
6913 // if (c >= '\u0080')
6914 // break;
6915 // da[dp++] = (byte)c;
6916 // }
6917 // return i;
6918 //}
6919 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6920 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6921 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6922 Register tmp5, Register result, bool ascii) {
6923
6924 // rsi: src
6925 // rdi: dst
6926 // rdx: len
6927 // rcx: tmp5
6928 // rax: result
6929 ShortBranchVerifier sbv(this);
6930 assert_different_registers(src, dst, len, tmp5, result);
6931 Label L_done, L_copy_1_char, L_copy_1_char_exit;
6932
6933 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
6934 int short_mask = ascii ? 0xff80 : 0xff00;
6935
6936 // set result
6937 xorl(result, result);
6938 // check for zero length
6939 testl(len, len);
6940 jcc(Assembler::zero, L_done);
6941
6942 movl(result, len);
6943
6944 // Setup pointers
6945 lea(src, Address(src, len, Address::times_2)); // char[]
6946 lea(dst, Address(dst, len, Address::times_1)); // byte[]
6947 negptr(len);
6948
6949 if (UseSSE42Intrinsics || UseAVX >= 2) {
6950 Label L_copy_8_chars, L_copy_8_chars_exit;
6951 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
6952
6953 if (UseAVX >= 2) {
6954 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
6955 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6956 movdl(tmp1Reg, tmp5);
6957 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
6958 jmp(L_chars_32_check);
6959
6960 bind(L_copy_32_chars);
6961 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
6962 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
6963 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6964 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6965 jccb(Assembler::notZero, L_copy_32_chars_exit);
6966 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6967 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
6968 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
6969
6970 bind(L_chars_32_check);
6971 addptr(len, 32);
6972 jcc(Assembler::lessEqual, L_copy_32_chars);
6973
6974 bind(L_copy_32_chars_exit);
6975 subptr(len, 16);
6976 jccb(Assembler::greater, L_copy_16_chars_exit);
6977
6978 } else if (UseSSE42Intrinsics) {
6979 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6980 movdl(tmp1Reg, tmp5);
6981 pshufd(tmp1Reg, tmp1Reg, 0);
6982 jmpb(L_chars_16_check);
6983 }
6984
6985 bind(L_copy_16_chars);
6986 if (UseAVX >= 2) {
6987 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
6988 vptest(tmp2Reg, tmp1Reg);
6989 jcc(Assembler::notZero, L_copy_16_chars_exit);
6990 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
6991 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
6992 } else {
6993 if (UseAVX > 0) {
6994 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6995 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6996 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
6997 } else {
6998 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6999 por(tmp2Reg, tmp3Reg);
7000 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7001 por(tmp2Reg, tmp4Reg);
7002 }
7003 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7004 jccb(Assembler::notZero, L_copy_16_chars_exit);
7005 packuswb(tmp3Reg, tmp4Reg);
7006 }
7007 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7008
7009 bind(L_chars_16_check);
7010 addptr(len, 16);
7011 jcc(Assembler::lessEqual, L_copy_16_chars);
7012
7013 bind(L_copy_16_chars_exit);
7014 if (UseAVX >= 2) {
7015 // clean upper bits of YMM registers
7016 vpxor(tmp2Reg, tmp2Reg);
7017 vpxor(tmp3Reg, tmp3Reg);
7018 vpxor(tmp4Reg, tmp4Reg);
7019 movdl(tmp1Reg, tmp5);
7020 pshufd(tmp1Reg, tmp1Reg, 0);
7021 }
7022 subptr(len, 8);
7023 jccb(Assembler::greater, L_copy_8_chars_exit);
7024
7025 bind(L_copy_8_chars);
7026 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7027 ptest(tmp3Reg, tmp1Reg);
7028 jccb(Assembler::notZero, L_copy_8_chars_exit);
7029 packuswb(tmp3Reg, tmp1Reg);
7030 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7031 addptr(len, 8);
7032 jccb(Assembler::lessEqual, L_copy_8_chars);
7033
7034 bind(L_copy_8_chars_exit);
7035 subptr(len, 8);
7036 jccb(Assembler::zero, L_done);
7037 }
7038
7039 bind(L_copy_1_char);
7040 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7041 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
7042 jccb(Assembler::notZero, L_copy_1_char_exit);
7043 movb(Address(dst, len, Address::times_1, 0), tmp5);
7044 addptr(len, 1);
7045 jccb(Assembler::less, L_copy_1_char);
7046
7047 bind(L_copy_1_char_exit);
7048 addptr(result, len); // len is negative count of not processed elements
7049
7050 bind(L_done);
7051 }
7052
7053 #ifdef _LP64
7054 /**
7055 * Helper for multiply_to_len().
7056 */
7057 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7058 addq(dest_lo, src1);
7059 adcq(dest_hi, 0);
7060 addq(dest_lo, src2);
7061 adcq(dest_hi, 0);
7062 }
7063
7064 /**
7065 * Multiply 64 bit by 64 bit first loop.
7066 */
7067 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7068 Register y, Register y_idx, Register z,
7069 Register carry, Register product,
7070 Register idx, Register kdx) {
7071 //
7072 // jlong carry, x[], y[], z[];
7073 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7074 // huge_128 product = y[idx] * x[xstart] + carry;
7075 // z[kdx] = (jlong)product;
7076 // carry = (jlong)(product >>> 64);
7077 // }
7078 // z[xstart] = carry;
7079 //
7080
7081 Label L_first_loop, L_first_loop_exit;
7082 Label L_one_x, L_one_y, L_multiply;
7083
7084 decrementl(xstart);
7085 jcc(Assembler::negative, L_one_x);
7086
7087 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7088 rorq(x_xstart, 32); // convert big-endian to little-endian
7089
7090 bind(L_first_loop);
7091 decrementl(idx);
7092 jcc(Assembler::negative, L_first_loop_exit);
7093 decrementl(idx);
7094 jcc(Assembler::negative, L_one_y);
7095 movq(y_idx, Address(y, idx, Address::times_4, 0));
7096 rorq(y_idx, 32); // convert big-endian to little-endian
7097 bind(L_multiply);
7098 movq(product, x_xstart);
7099 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7100 addq(product, carry);
7101 adcq(rdx, 0);
7102 subl(kdx, 2);
7103 movl(Address(z, kdx, Address::times_4, 4), product);
7104 shrq(product, 32);
7105 movl(Address(z, kdx, Address::times_4, 0), product);
7106 movq(carry, rdx);
7107 jmp(L_first_loop);
7108
7109 bind(L_one_y);
7110 movl(y_idx, Address(y, 0));
7111 jmp(L_multiply);
7112
7113 bind(L_one_x);
7114 movl(x_xstart, Address(x, 0));
7115 jmp(L_first_loop);
7116
7117 bind(L_first_loop_exit);
7118 }
7119
7120 /**
7121 * Multiply 64 bit by 64 bit and add 128 bit.
7122 */
7123 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7124 Register yz_idx, Register idx,
7125 Register carry, Register product, int offset) {
7126 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7127 // z[kdx] = (jlong)product;
7128
7129 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7130 rorq(yz_idx, 32); // convert big-endian to little-endian
7131 movq(product, x_xstart);
7132 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7133 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7134 rorq(yz_idx, 32); // convert big-endian to little-endian
7135
7136 add2_with_carry(rdx, product, carry, yz_idx);
7137
7138 movl(Address(z, idx, Address::times_4, offset+4), product);
7139 shrq(product, 32);
7140 movl(Address(z, idx, Address::times_4, offset), product);
7141
7142 }
7143
7144 /**
7145 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7146 */
7147 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7148 Register yz_idx, Register idx, Register jdx,
7149 Register carry, Register product,
7150 Register carry2) {
7151 // jlong carry, x[], y[], z[];
7152 // int kdx = ystart+1;
7153 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7154 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7155 // z[kdx+idx+1] = (jlong)product;
7156 // jlong carry2 = (jlong)(product >>> 64);
7157 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7158 // z[kdx+idx] = (jlong)product;
7159 // carry = (jlong)(product >>> 64);
7160 // }
7161 // idx += 2;
7162 // if (idx > 0) {
7163 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7164 // z[kdx+idx] = (jlong)product;
7165 // carry = (jlong)(product >>> 64);
7166 // }
7167 //
7168
7169 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7170
7171 movl(jdx, idx);
7172 andl(jdx, 0xFFFFFFFC);
7173 shrl(jdx, 2);
7174
7175 bind(L_third_loop);
7176 subl(jdx, 1);
7177 jcc(Assembler::negative, L_third_loop_exit);
7178 subl(idx, 4);
7179
7180 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7181 movq(carry2, rdx);
7182
7183 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7184 movq(carry, rdx);
7185 jmp(L_third_loop);
7186
7187 bind (L_third_loop_exit);
7188
7189 andl (idx, 0x3);
7190 jcc(Assembler::zero, L_post_third_loop_done);
7191
7192 Label L_check_1;
7193 subl(idx, 2);
7194 jcc(Assembler::negative, L_check_1);
7195
7196 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7197 movq(carry, rdx);
7198
7199 bind (L_check_1);
7200 addl (idx, 0x2);
7201 andl (idx, 0x1);
7202 subl(idx, 1);
7203 jcc(Assembler::negative, L_post_third_loop_done);
7204
7205 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7206 movq(product, x_xstart);
7207 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7208 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7209
7210 add2_with_carry(rdx, product, yz_idx, carry);
7211
7212 movl(Address(z, idx, Address::times_4, 0), product);
7213 shrq(product, 32);
7214
7215 shlq(rdx, 32);
7216 orq(product, rdx);
7217 movq(carry, product);
7218
7219 bind(L_post_third_loop_done);
7220 }
7221
7222 /**
7223 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7224 *
7225 */
7226 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7227 Register carry, Register carry2,
7228 Register idx, Register jdx,
7229 Register yz_idx1, Register yz_idx2,
7230 Register tmp, Register tmp3, Register tmp4) {
7231 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7232
7233 // jlong carry, x[], y[], z[];
7234 // int kdx = ystart+1;
7235 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7236 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7237 // jlong carry2 = (jlong)(tmp3 >>> 64);
7238 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7239 // carry = (jlong)(tmp4 >>> 64);
7240 // z[kdx+idx+1] = (jlong)tmp3;
7241 // z[kdx+idx] = (jlong)tmp4;
7242 // }
7243 // idx += 2;
7244 // if (idx > 0) {
7245 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7246 // z[kdx+idx] = (jlong)yz_idx1;
7247 // carry = (jlong)(yz_idx1 >>> 64);
7248 // }
7249 //
7250
7251 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7252
7253 movl(jdx, idx);
7254 andl(jdx, 0xFFFFFFFC);
7255 shrl(jdx, 2);
7256
7257 bind(L_third_loop);
7258 subl(jdx, 1);
7259 jcc(Assembler::negative, L_third_loop_exit);
7260 subl(idx, 4);
7261
7262 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7263 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7264 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7265 rorxq(yz_idx2, yz_idx2, 32);
7266
7267 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7268 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7269
7270 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7271 rorxq(yz_idx1, yz_idx1, 32);
7272 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7273 rorxq(yz_idx2, yz_idx2, 32);
7274
7275 if (VM_Version::supports_adx()) {
7276 adcxq(tmp3, carry);
7277 adoxq(tmp3, yz_idx1);
7278
7279 adcxq(tmp4, tmp);
7280 adoxq(tmp4, yz_idx2);
7281
7282 movl(carry, 0); // does not affect flags
7283 adcxq(carry2, carry);
7284 adoxq(carry2, carry);
7285 } else {
7286 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7287 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7288 }
7289 movq(carry, carry2);
7290
7291 movl(Address(z, idx, Address::times_4, 12), tmp3);
7292 shrq(tmp3, 32);
7293 movl(Address(z, idx, Address::times_4, 8), tmp3);
7294
7295 movl(Address(z, idx, Address::times_4, 4), tmp4);
7296 shrq(tmp4, 32);
7297 movl(Address(z, idx, Address::times_4, 0), tmp4);
7298
7299 jmp(L_third_loop);
7300
7301 bind (L_third_loop_exit);
7302
7303 andl (idx, 0x3);
7304 jcc(Assembler::zero, L_post_third_loop_done);
7305
7306 Label L_check_1;
7307 subl(idx, 2);
7308 jcc(Assembler::negative, L_check_1);
7309
7310 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7311 rorxq(yz_idx1, yz_idx1, 32);
7312 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7313 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7314 rorxq(yz_idx2, yz_idx2, 32);
7315
7316 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7317
7318 movl(Address(z, idx, Address::times_4, 4), tmp3);
7319 shrq(tmp3, 32);
7320 movl(Address(z, idx, Address::times_4, 0), tmp3);
7321 movq(carry, tmp4);
7322
7323 bind (L_check_1);
7324 addl (idx, 0x2);
7325 andl (idx, 0x1);
7326 subl(idx, 1);
7327 jcc(Assembler::negative, L_post_third_loop_done);
7328 movl(tmp4, Address(y, idx, Address::times_4, 0));
7329 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7330 movl(tmp4, Address(z, idx, Address::times_4, 0));
7331
7332 add2_with_carry(carry2, tmp3, tmp4, carry);
7333
7334 movl(Address(z, idx, Address::times_4, 0), tmp3);
7335 shrq(tmp3, 32);
7336
7337 shlq(carry2, 32);
7338 orq(tmp3, carry2);
7339 movq(carry, tmp3);
7340
7341 bind(L_post_third_loop_done);
7342 }
7343
7344 /**
7345 * Code for BigInteger::multiplyToLen() intrinsic.
7346 *
7347 * rdi: x
7348 * rax: xlen
7349 * rsi: y
7350 * rcx: ylen
7351 * r8: z
7352 * r11: tmp0
7353 * r12: tmp1
7354 * r13: tmp2
7355 * r14: tmp3
7356 * r15: tmp4
7357 * rbx: tmp5
7358 *
7359 */
7360 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7361 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7362 ShortBranchVerifier sbv(this);
7363 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7364
7365 push(tmp0);
7366 push(tmp1);
7367 push(tmp2);
7368 push(tmp3);
7369 push(tmp4);
7370 push(tmp5);
7371
7372 push(xlen);
7373
7374 const Register idx = tmp1;
7375 const Register kdx = tmp2;
7376 const Register xstart = tmp3;
7377
7378 const Register y_idx = tmp4;
7379 const Register carry = tmp5;
7380 const Register product = xlen;
7381 const Register x_xstart = tmp0;
7382
7383 // First Loop.
7384 //
7385 // final static long LONG_MASK = 0xffffffffL;
7386 // int xstart = xlen - 1;
7387 // int ystart = ylen - 1;
7388 // long carry = 0;
7389 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7390 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7391 // z[kdx] = (int)product;
7392 // carry = product >>> 32;
7393 // }
7394 // z[xstart] = (int)carry;
7395 //
7396
7397 movl(idx, ylen); // idx = ylen;
7398 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7399 xorq(carry, carry); // carry = 0;
7400
7401 Label L_done;
7402
7403 movl(xstart, xlen);
7404 decrementl(xstart);
7405 jcc(Assembler::negative, L_done);
7406
7407 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7408
7409 Label L_second_loop;
7410 testl(kdx, kdx);
7411 jcc(Assembler::zero, L_second_loop);
7412
7413 Label L_carry;
7414 subl(kdx, 1);
7415 jcc(Assembler::zero, L_carry);
7416
7417 movl(Address(z, kdx, Address::times_4, 0), carry);
7418 shrq(carry, 32);
7419 subl(kdx, 1);
7420
7421 bind(L_carry);
7422 movl(Address(z, kdx, Address::times_4, 0), carry);
7423
7424 // Second and third (nested) loops.
7425 //
7426 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7427 // carry = 0;
7428 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7429 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7430 // (z[k] & LONG_MASK) + carry;
7431 // z[k] = (int)product;
7432 // carry = product >>> 32;
7433 // }
7434 // z[i] = (int)carry;
7435 // }
7436 //
7437 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7438
7439 const Register jdx = tmp1;
7440
7441 bind(L_second_loop);
7442 xorl(carry, carry); // carry = 0;
7443 movl(jdx, ylen); // j = ystart+1
7444
7445 subl(xstart, 1); // i = xstart-1;
7446 jcc(Assembler::negative, L_done);
7447
7448 push (z);
7449
7450 Label L_last_x;
7451 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7452 subl(xstart, 1); // i = xstart-1;
7453 jcc(Assembler::negative, L_last_x);
7454
7455 if (UseBMI2Instructions) {
7456 movq(rdx, Address(x, xstart, Address::times_4, 0));
7457 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7458 } else {
7459 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7460 rorq(x_xstart, 32); // convert big-endian to little-endian
7461 }
7462
7463 Label L_third_loop_prologue;
7464 bind(L_third_loop_prologue);
7465
7466 push (x);
7467 push (xstart);
7468 push (ylen);
7469
7470
7471 if (UseBMI2Instructions) {
7472 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7473 } else { // !UseBMI2Instructions
7474 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7475 }
7476
7477 pop(ylen);
7478 pop(xlen);
7479 pop(x);
7480 pop(z);
7481
7482 movl(tmp3, xlen);
7483 addl(tmp3, 1);
7484 movl(Address(z, tmp3, Address::times_4, 0), carry);
7485 subl(tmp3, 1);
7486 jccb(Assembler::negative, L_done);
7487
7488 shrq(carry, 32);
7489 movl(Address(z, tmp3, Address::times_4, 0), carry);
7490 jmp(L_second_loop);
7491
7492 // Next infrequent code is moved outside loops.
7493 bind(L_last_x);
7494 if (UseBMI2Instructions) {
7495 movl(rdx, Address(x, 0));
7496 } else {
7497 movl(x_xstart, Address(x, 0));
7498 }
7499 jmp(L_third_loop_prologue);
7500
7501 bind(L_done);
7502
7503 pop(xlen);
7504
7505 pop(tmp5);
7506 pop(tmp4);
7507 pop(tmp3);
7508 pop(tmp2);
7509 pop(tmp1);
7510 pop(tmp0);
7511 }
7512
7513 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7514 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7515 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7516 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7517 Label VECTOR8_TAIL, VECTOR4_TAIL;
7518 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7519 Label SAME_TILL_END, DONE;
7520 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7521
7522 //scale is in rcx in both Win64 and Unix
7523 ShortBranchVerifier sbv(this);
7524
7525 shlq(length);
7526 xorq(result, result);
7527
7528 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7529 VM_Version::supports_avx512vlbw()) {
7530 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7531
7532 cmpq(length, 64);
7533 jcc(Assembler::less, VECTOR32_TAIL);
7534
7535 movq(tmp1, length);
7536 andq(tmp1, 0x3F); // tail count
7537 andq(length, ~(0x3F)); //vector count
7538
7539 bind(VECTOR64_LOOP);
7540 // AVX512 code to compare 64 byte vectors.
7541 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7542 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7543 kortestql(k7, k7);
7544 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7545 addq(result, 64);
7546 subq(length, 64);
7547 jccb(Assembler::notZero, VECTOR64_LOOP);
7548
7549 //bind(VECTOR64_TAIL);
7550 testq(tmp1, tmp1);
7551 jcc(Assembler::zero, SAME_TILL_END);
7552
7553 //bind(VECTOR64_TAIL);
7554 // AVX512 code to compare up to 63 byte vectors.
7555 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7556 shlxq(tmp2, tmp2, tmp1);
7557 notq(tmp2);
7558 kmovql(k3, tmp2);
7559
7560 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7561 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7562
7563 ktestql(k7, k3);
7564 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7565
7566 bind(VECTOR64_NOT_EQUAL);
7567 kmovql(tmp1, k7);
7568 notq(tmp1);
7569 tzcntq(tmp1, tmp1);
7570 addq(result, tmp1);
7571 shrq(result);
7572 jmp(DONE);
7573 bind(VECTOR32_TAIL);
7574 }
7575
7576 cmpq(length, 8);
7577 jcc(Assembler::equal, VECTOR8_LOOP);
7578 jcc(Assembler::less, VECTOR4_TAIL);
7579
7580 if (UseAVX >= 2) {
7581 Label VECTOR16_TAIL, VECTOR32_LOOP;
7582
7583 cmpq(length, 16);
7584 jcc(Assembler::equal, VECTOR16_LOOP);
7585 jcc(Assembler::less, VECTOR8_LOOP);
7586
7587 cmpq(length, 32);
7588 jccb(Assembler::less, VECTOR16_TAIL);
7589
7590 subq(length, 32);
7591 bind(VECTOR32_LOOP);
7592 vmovdqu(rymm0, Address(obja, result));
7593 vmovdqu(rymm1, Address(objb, result));
7594 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7595 vptest(rymm2, rymm2);
7596 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7597 addq(result, 32);
7598 subq(length, 32);
7599 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7600 addq(length, 32);
7601 jcc(Assembler::equal, SAME_TILL_END);
7602 //falling through if less than 32 bytes left //close the branch here.
7603
7604 bind(VECTOR16_TAIL);
7605 cmpq(length, 16);
7606 jccb(Assembler::less, VECTOR8_TAIL);
7607 bind(VECTOR16_LOOP);
7608 movdqu(rymm0, Address(obja, result));
7609 movdqu(rymm1, Address(objb, result));
7610 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7611 ptest(rymm2, rymm2);
7612 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7613 addq(result, 16);
7614 subq(length, 16);
7615 jcc(Assembler::equal, SAME_TILL_END);
7616 //falling through if less than 16 bytes left
7617 } else {//regular intrinsics
7618
7619 cmpq(length, 16);
7620 jccb(Assembler::less, VECTOR8_TAIL);
7621
7622 subq(length, 16);
7623 bind(VECTOR16_LOOP);
7624 movdqu(rymm0, Address(obja, result));
7625 movdqu(rymm1, Address(objb, result));
7626 pxor(rymm0, rymm1);
7627 ptest(rymm0, rymm0);
7628 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7629 addq(result, 16);
7630 subq(length, 16);
7631 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7632 addq(length, 16);
7633 jcc(Assembler::equal, SAME_TILL_END);
7634 //falling through if less than 16 bytes left
7635 }
7636
7637 bind(VECTOR8_TAIL);
7638 cmpq(length, 8);
7639 jccb(Assembler::less, VECTOR4_TAIL);
7640 bind(VECTOR8_LOOP);
7641 movq(tmp1, Address(obja, result));
7642 movq(tmp2, Address(objb, result));
7643 xorq(tmp1, tmp2);
7644 testq(tmp1, tmp1);
7645 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7646 addq(result, 8);
7647 subq(length, 8);
7648 jcc(Assembler::equal, SAME_TILL_END);
7649 //falling through if less than 8 bytes left
7650
7651 bind(VECTOR4_TAIL);
7652 cmpq(length, 4);
7653 jccb(Assembler::less, BYTES_TAIL);
7654 bind(VECTOR4_LOOP);
7655 movl(tmp1, Address(obja, result));
7656 xorl(tmp1, Address(objb, result));
7657 testl(tmp1, tmp1);
7658 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7659 addq(result, 4);
7660 subq(length, 4);
7661 jcc(Assembler::equal, SAME_TILL_END);
7662 //falling through if less than 4 bytes left
7663
7664 bind(BYTES_TAIL);
7665 bind(BYTES_LOOP);
7666 load_unsigned_byte(tmp1, Address(obja, result));
7667 load_unsigned_byte(tmp2, Address(objb, result));
7668 xorl(tmp1, tmp2);
7669 testl(tmp1, tmp1);
7670 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7671 decq(length);
7672 jcc(Assembler::zero, SAME_TILL_END);
7673 incq(result);
7674 load_unsigned_byte(tmp1, Address(obja, result));
7675 load_unsigned_byte(tmp2, Address(objb, result));
7676 xorl(tmp1, tmp2);
7677 testl(tmp1, tmp1);
7678 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7679 decq(length);
7680 jcc(Assembler::zero, SAME_TILL_END);
7681 incq(result);
7682 load_unsigned_byte(tmp1, Address(obja, result));
7683 load_unsigned_byte(tmp2, Address(objb, result));
7684 xorl(tmp1, tmp2);
7685 testl(tmp1, tmp1);
7686 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7687 jmp(SAME_TILL_END);
7688
7689 if (UseAVX >= 2) {
7690 bind(VECTOR32_NOT_EQUAL);
7691 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7692 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7693 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7694 vpmovmskb(tmp1, rymm0);
7695 bsfq(tmp1, tmp1);
7696 addq(result, tmp1);
7697 shrq(result);
7698 jmp(DONE);
7699 }
7700
7701 bind(VECTOR16_NOT_EQUAL);
7702 if (UseAVX >= 2) {
7703 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7704 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7705 pxor(rymm0, rymm2);
7706 } else {
7707 pcmpeqb(rymm2, rymm2);
7708 pxor(rymm0, rymm1);
7709 pcmpeqb(rymm0, rymm1);
7710 pxor(rymm0, rymm2);
7711 }
7712 pmovmskb(tmp1, rymm0);
7713 bsfq(tmp1, tmp1);
7714 addq(result, tmp1);
7715 shrq(result);
7716 jmpb(DONE);
7717
7718 bind(VECTOR8_NOT_EQUAL);
7719 bind(VECTOR4_NOT_EQUAL);
7720 bsfq(tmp1, tmp1);
7721 shrq(tmp1, 3);
7722 addq(result, tmp1);
7723 bind(BYTES_NOT_EQUAL);
7724 shrq(result);
7725 jmpb(DONE);
7726
7727 bind(SAME_TILL_END);
7728 mov64(result, -1);
7729
7730 bind(DONE);
7731 }
7732
7733 //Helper functions for square_to_len()
7734
7735 /**
7736 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7737 * Preserves x and z and modifies rest of the registers.
7738 */
7739 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7740 // Perform square and right shift by 1
7741 // Handle odd xlen case first, then for even xlen do the following
7742 // jlong carry = 0;
7743 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7744 // huge_128 product = x[j:j+1] * x[j:j+1];
7745 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7746 // z[i+2:i+3] = (jlong)(product >>> 1);
7747 // carry = (jlong)product;
7748 // }
7749
7750 xorq(tmp5, tmp5); // carry
7751 xorq(rdxReg, rdxReg);
7752 xorl(tmp1, tmp1); // index for x
7753 xorl(tmp4, tmp4); // index for z
7754
7755 Label L_first_loop, L_first_loop_exit;
7756
7757 testl(xlen, 1);
7758 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7759
7760 // Square and right shift by 1 the odd element using 32 bit multiply
7761 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7762 imulq(raxReg, raxReg);
7763 shrq(raxReg, 1);
7764 adcq(tmp5, 0);
7765 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7766 incrementl(tmp1);
7767 addl(tmp4, 2);
7768
7769 // Square and right shift by 1 the rest using 64 bit multiply
7770 bind(L_first_loop);
7771 cmpptr(tmp1, xlen);
7772 jccb(Assembler::equal, L_first_loop_exit);
7773
7774 // Square
7775 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7776 rorq(raxReg, 32); // convert big-endian to little-endian
7777 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7778
7779 // Right shift by 1 and save carry
7780 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7781 rcrq(rdxReg, 1);
7782 rcrq(raxReg, 1);
7783 adcq(tmp5, 0);
7784
7785 // Store result in z
7786 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7787 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7788
7789 // Update indices for x and z
7790 addl(tmp1, 2);
7791 addl(tmp4, 4);
7792 jmp(L_first_loop);
7793
7794 bind(L_first_loop_exit);
7795 }
7796
7797
7798 /**
7799 * Perform the following multiply add operation using BMI2 instructions
7800 * carry:sum = sum + op1*op2 + carry
7801 * op2 should be in rdx
7802 * op2 is preserved, all other registers are modified
7803 */
7804 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7805 // assert op2 is rdx
7806 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7807 addq(sum, carry);
7808 adcq(tmp2, 0);
7809 addq(sum, op1);
7810 adcq(tmp2, 0);
7811 movq(carry, tmp2);
7812 }
7813
7814 /**
7815 * Perform the following multiply add operation:
7816 * carry:sum = sum + op1*op2 + carry
7817 * Preserves op1, op2 and modifies rest of registers
7818 */
7819 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7820 // rdx:rax = op1 * op2
7821 movq(raxReg, op2);
7822 mulq(op1);
7823
7824 // rdx:rax = sum + carry + rdx:rax
7825 addq(sum, carry);
7826 adcq(rdxReg, 0);
7827 addq(sum, raxReg);
7828 adcq(rdxReg, 0);
7829
7830 // carry:sum = rdx:sum
7831 movq(carry, rdxReg);
7832 }
7833
7834 /**
7835 * Add 64 bit long carry into z[] with carry propagation.
7836 * Preserves z and carry register values and modifies rest of registers.
7837 *
7838 */
7839 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7840 Label L_fourth_loop, L_fourth_loop_exit;
7841
7842 movl(tmp1, 1);
7843 subl(zlen, 2);
7844 addq(Address(z, zlen, Address::times_4, 0), carry);
7845
7846 bind(L_fourth_loop);
7847 jccb(Assembler::carryClear, L_fourth_loop_exit);
7848 subl(zlen, 2);
7849 jccb(Assembler::negative, L_fourth_loop_exit);
7850 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7851 jmp(L_fourth_loop);
7852 bind(L_fourth_loop_exit);
7853 }
7854
7855 /**
7856 * Shift z[] left by 1 bit.
7857 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7858 *
7859 */
7860 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7861
7862 Label L_fifth_loop, L_fifth_loop_exit;
7863
7864 // Fifth loop
7865 // Perform primitiveLeftShift(z, zlen, 1)
7866
7867 const Register prev_carry = tmp1;
7868 const Register new_carry = tmp4;
7869 const Register value = tmp2;
7870 const Register zidx = tmp3;
7871
7872 // int zidx, carry;
7873 // long value;
7874 // carry = 0;
7875 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7876 // (carry:value) = (z[i] << 1) | carry ;
7877 // z[i] = value;
7878 // }
7879
7880 movl(zidx, zlen);
7881 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7882
7883 bind(L_fifth_loop);
7884 decl(zidx); // Use decl to preserve carry flag
7885 decl(zidx);
7886 jccb(Assembler::negative, L_fifth_loop_exit);
7887
7888 if (UseBMI2Instructions) {
7889 movq(value, Address(z, zidx, Address::times_4, 0));
7890 rclq(value, 1);
7891 rorxq(value, value, 32);
7892 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7893 }
7894 else {
7895 // clear new_carry
7896 xorl(new_carry, new_carry);
7897
7898 // Shift z[i] by 1, or in previous carry and save new carry
7899 movq(value, Address(z, zidx, Address::times_4, 0));
7900 shlq(value, 1);
7901 adcl(new_carry, 0);
7902
7903 orq(value, prev_carry);
7904 rorq(value, 0x20);
7905 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7906
7907 // Set previous carry = new carry
7908 movl(prev_carry, new_carry);
7909 }
7910 jmp(L_fifth_loop);
7911
7912 bind(L_fifth_loop_exit);
7913 }
7914
7915
7916 /**
7917 * Code for BigInteger::squareToLen() intrinsic
7918 *
7919 * rdi: x
7920 * rsi: len
7921 * r8: z
7922 * rcx: zlen
7923 * r12: tmp1
7924 * r13: tmp2
7925 * r14: tmp3
7926 * r15: tmp4
7927 * rbx: tmp5
7928 *
7929 */
7930 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7931
7932 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
7933 push(tmp1);
7934 push(tmp2);
7935 push(tmp3);
7936 push(tmp4);
7937 push(tmp5);
7938
7939 // First loop
7940 // Store the squares, right shifted one bit (i.e., divided by 2).
7941 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7942
7943 // Add in off-diagonal sums.
7944 //
7945 // Second, third (nested) and fourth loops.
7946 // zlen +=2;
7947 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7948 // carry = 0;
7949 // long op2 = x[xidx:xidx+1];
7950 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7951 // k -= 2;
7952 // long op1 = x[j:j+1];
7953 // long sum = z[k:k+1];
7954 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7955 // z[k:k+1] = sum;
7956 // }
7957 // add_one_64(z, k, carry, tmp_regs);
7958 // }
7959
7960 const Register carry = tmp5;
7961 const Register sum = tmp3;
7962 const Register op1 = tmp4;
7963 Register op2 = tmp2;
7964
7965 push(zlen);
7966 push(len);
7967 addl(zlen,2);
7968 bind(L_second_loop);
7969 xorq(carry, carry);
7970 subl(zlen, 4);
7971 subl(len, 2);
7972 push(zlen);
7973 push(len);
7974 cmpl(len, 0);
7975 jccb(Assembler::lessEqual, L_second_loop_exit);
7976
7977 // Multiply an array by one 64 bit long.
7978 if (UseBMI2Instructions) {
7979 op2 = rdxReg;
7980 movq(op2, Address(x, len, Address::times_4, 0));
7981 rorxq(op2, op2, 32);
7982 }
7983 else {
7984 movq(op2, Address(x, len, Address::times_4, 0));
7985 rorq(op2, 32);
7986 }
7987
7988 bind(L_third_loop);
7989 decrementl(len);
7990 jccb(Assembler::negative, L_third_loop_exit);
7991 decrementl(len);
7992 jccb(Assembler::negative, L_last_x);
7993
7994 movq(op1, Address(x, len, Address::times_4, 0));
7995 rorq(op1, 32);
7996
7997 bind(L_multiply);
7998 subl(zlen, 2);
7999 movq(sum, Address(z, zlen, Address::times_4, 0));
8000
8001 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8002 if (UseBMI2Instructions) {
8003 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8004 }
8005 else {
8006 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8007 }
8008
8009 movq(Address(z, zlen, Address::times_4, 0), sum);
8010
8011 jmp(L_third_loop);
8012 bind(L_third_loop_exit);
8013
8014 // Fourth loop
8015 // Add 64 bit long carry into z with carry propagation.
8016 // Uses offsetted zlen.
8017 add_one_64(z, zlen, carry, tmp1);
8018
8019 pop(len);
8020 pop(zlen);
8021 jmp(L_second_loop);
8022
8023 // Next infrequent code is moved outside loops.
8024 bind(L_last_x);
8025 movl(op1, Address(x, 0));
8026 jmp(L_multiply);
8027
8028 bind(L_second_loop_exit);
8029 pop(len);
8030 pop(zlen);
8031 pop(len);
8032 pop(zlen);
8033
8034 // Fifth loop
8035 // Shift z left 1 bit.
8036 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8037
8038 // z[zlen-1] |= x[len-1] & 1;
8039 movl(tmp3, Address(x, len, Address::times_4, -4));
8040 andl(tmp3, 1);
8041 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8042
8043 pop(tmp5);
8044 pop(tmp4);
8045 pop(tmp3);
8046 pop(tmp2);
8047 pop(tmp1);
8048 }
8049
8050 /**
8051 * Helper function for mul_add()
8052 * Multiply the in[] by int k and add to out[] starting at offset offs using
8053 * 128 bit by 32 bit multiply and return the carry in tmp5.
8054 * Only quad int aligned length of in[] is operated on in this function.
8055 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8056 * This function preserves out, in and k registers.
8057 * len and offset point to the appropriate index in "in" & "out" correspondingly
8058 * tmp5 has the carry.
8059 * other registers are temporary and are modified.
8060 *
8061 */
8062 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8063 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8064 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8065
8066 Label L_first_loop, L_first_loop_exit;
8067
8068 movl(tmp1, len);
8069 shrl(tmp1, 2);
8070
8071 bind(L_first_loop);
8072 subl(tmp1, 1);
8073 jccb(Assembler::negative, L_first_loop_exit);
8074
8075 subl(len, 4);
8076 subl(offset, 4);
8077
8078 Register op2 = tmp2;
8079 const Register sum = tmp3;
8080 const Register op1 = tmp4;
8081 const Register carry = tmp5;
8082
8083 if (UseBMI2Instructions) {
8084 op2 = rdxReg;
8085 }
8086
8087 movq(op1, Address(in, len, Address::times_4, 8));
8088 rorq(op1, 32);
8089 movq(sum, Address(out, offset, Address::times_4, 8));
8090 rorq(sum, 32);
8091 if (UseBMI2Instructions) {
8092 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8093 }
8094 else {
8095 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8096 }
8097 // Store back in big endian from little endian
8098 rorq(sum, 0x20);
8099 movq(Address(out, offset, Address::times_4, 8), sum);
8100
8101 movq(op1, Address(in, len, Address::times_4, 0));
8102 rorq(op1, 32);
8103 movq(sum, Address(out, offset, Address::times_4, 0));
8104 rorq(sum, 32);
8105 if (UseBMI2Instructions) {
8106 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8107 }
8108 else {
8109 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8110 }
8111 // Store back in big endian from little endian
8112 rorq(sum, 0x20);
8113 movq(Address(out, offset, Address::times_4, 0), sum);
8114
8115 jmp(L_first_loop);
8116 bind(L_first_loop_exit);
8117 }
8118
8119 /**
8120 * Code for BigInteger::mulAdd() intrinsic
8121 *
8122 * rdi: out
8123 * rsi: in
8124 * r11: offs (out.length - offset)
8125 * rcx: len
8126 * r8: k
8127 * r12: tmp1
8128 * r13: tmp2
8129 * r14: tmp3
8130 * r15: tmp4
8131 * rbx: tmp5
8132 * Multiply the in[] by word k and add to out[], return the carry in rax
8133 */
8134 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8135 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8136 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8137
8138 Label L_carry, L_last_in, L_done;
8139
8140 // carry = 0;
8141 // for (int j=len-1; j >= 0; j--) {
8142 // long product = (in[j] & LONG_MASK) * kLong +
8143 // (out[offs] & LONG_MASK) + carry;
8144 // out[offs--] = (int)product;
8145 // carry = product >>> 32;
8146 // }
8147 //
8148 push(tmp1);
8149 push(tmp2);
8150 push(tmp3);
8151 push(tmp4);
8152 push(tmp5);
8153
8154 Register op2 = tmp2;
8155 const Register sum = tmp3;
8156 const Register op1 = tmp4;
8157 const Register carry = tmp5;
8158
8159 if (UseBMI2Instructions) {
8160 op2 = rdxReg;
8161 movl(op2, k);
8162 }
8163 else {
8164 movl(op2, k);
8165 }
8166
8167 xorq(carry, carry);
8168
8169 //First loop
8170
8171 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8172 //The carry is in tmp5
8173 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8174
8175 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8176 decrementl(len);
8177 jccb(Assembler::negative, L_carry);
8178 decrementl(len);
8179 jccb(Assembler::negative, L_last_in);
8180
8181 movq(op1, Address(in, len, Address::times_4, 0));
8182 rorq(op1, 32);
8183
8184 subl(offs, 2);
8185 movq(sum, Address(out, offs, Address::times_4, 0));
8186 rorq(sum, 32);
8187
8188 if (UseBMI2Instructions) {
8189 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8190 }
8191 else {
8192 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8193 }
8194
8195 // Store back in big endian from little endian
8196 rorq(sum, 0x20);
8197 movq(Address(out, offs, Address::times_4, 0), sum);
8198
8199 testl(len, len);
8200 jccb(Assembler::zero, L_carry);
8201
8202 //Multiply the last in[] entry, if any
8203 bind(L_last_in);
8204 movl(op1, Address(in, 0));
8205 movl(sum, Address(out, offs, Address::times_4, -4));
8206
8207 movl(raxReg, k);
8208 mull(op1); //tmp4 * eax -> edx:eax
8209 addl(sum, carry);
8210 adcl(rdxReg, 0);
8211 addl(sum, raxReg);
8212 adcl(rdxReg, 0);
8213 movl(carry, rdxReg);
8214
8215 movl(Address(out, offs, Address::times_4, -4), sum);
8216
8217 bind(L_carry);
8218 //return tmp5/carry as carry in rax
8219 movl(rax, carry);
8220
8221 bind(L_done);
8222 pop(tmp5);
8223 pop(tmp4);
8224 pop(tmp3);
8225 pop(tmp2);
8226 pop(tmp1);
8227 }
8228 #endif
8229
8230 /**
8231 * Emits code to update CRC-32 with a byte value according to constants in table
8232 *
8233 * @param [in,out]crc Register containing the crc.
8234 * @param [in]val Register containing the byte to fold into the CRC.
8235 * @param [in]table Register containing the table of crc constants.
8236 *
8237 * uint32_t crc;
8238 * val = crc_table[(val ^ crc) & 0xFF];
8239 * crc = val ^ (crc >> 8);
8240 *
8241 */
8242 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8243 xorl(val, crc);
8244 andl(val, 0xFF);
8245 shrl(crc, 8); // unsigned shift
8246 xorl(crc, Address(table, val, Address::times_4, 0));
8247 }
8248
8249 /**
8250 * Fold 128-bit data chunk
8251 */
8252 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8253 if (UseAVX > 0) {
8254 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8255 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8256 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8257 pxor(xcrc, xtmp);
8258 } else {
8259 movdqa(xtmp, xcrc);
8260 pclmulhdq(xtmp, xK); // [123:64]
8261 pclmulldq(xcrc, xK); // [63:0]
8262 pxor(xcrc, xtmp);
8263 movdqu(xtmp, Address(buf, offset));
8264 pxor(xcrc, xtmp);
8265 }
8266 }
8267
8268 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8269 if (UseAVX > 0) {
8270 vpclmulhdq(xtmp, xK, xcrc);
8271 vpclmulldq(xcrc, xK, xcrc);
8272 pxor(xcrc, xbuf);
8273 pxor(xcrc, xtmp);
8274 } else {
8275 movdqa(xtmp, xcrc);
8276 pclmulhdq(xtmp, xK);
8277 pclmulldq(xcrc, xK);
8278 pxor(xcrc, xbuf);
8279 pxor(xcrc, xtmp);
8280 }
8281 }
8282
8283 /**
8284 * 8-bit folds to compute 32-bit CRC
8285 *
8286 * uint64_t xcrc;
8287 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8288 */
8289 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8290 movdl(tmp, xcrc);
8291 andl(tmp, 0xFF);
8292 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8293 psrldq(xcrc, 1); // unsigned shift one byte
8294 pxor(xcrc, xtmp);
8295 }
8296
8297 /**
8298 * uint32_t crc;
8299 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8300 */
8301 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8302 movl(tmp, crc);
8303 andl(tmp, 0xFF);
8304 shrl(crc, 8);
8305 xorl(crc, Address(table, tmp, Address::times_4, 0));
8306 }
8307
8308 /**
8309 * @param crc register containing existing CRC (32-bit)
8310 * @param buf register pointing to input byte buffer (byte*)
8311 * @param len register containing number of bytes
8312 * @param table register that will contain address of CRC table
8313 * @param tmp scratch register
8314 */
8315 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8316 assert_different_registers(crc, buf, len, table, tmp, rax);
8317
8318 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8319 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8320
8321 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8322 // context for the registers used, where all instructions below are using 128-bit mode
8323 // On EVEX without VL and BW, these instructions will all be AVX.
8324 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8325 notl(crc); // ~crc
8326 cmpl(len, 16);
8327 jcc(Assembler::less, L_tail);
8328
8329 // Align buffer to 16 bytes
8330 movl(tmp, buf);
8331 andl(tmp, 0xF);
8332 jccb(Assembler::zero, L_aligned);
8333 subl(tmp, 16);
8334 addl(len, tmp);
8335
8336 align(4);
8337 BIND(L_align_loop);
8338 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8339 update_byte_crc32(crc, rax, table);
8340 increment(buf);
8341 incrementl(tmp);
8342 jccb(Assembler::less, L_align_loop);
8343
8344 BIND(L_aligned);
8345 movl(tmp, len); // save
8346 shrl(len, 4);
8347 jcc(Assembler::zero, L_tail_restore);
8348
8349 // Fold crc into first bytes of vector
8350 movdqa(xmm1, Address(buf, 0));
8351 movdl(rax, xmm1);
8352 xorl(crc, rax);
8353 if (VM_Version::supports_sse4_1()) {
8354 pinsrd(xmm1, crc, 0);
8355 } else {
8356 pinsrw(xmm1, crc, 0);
8357 shrl(crc, 16);
8358 pinsrw(xmm1, crc, 1);
8359 }
8360 addptr(buf, 16);
8361 subl(len, 4); // len > 0
8362 jcc(Assembler::less, L_fold_tail);
8363
8364 movdqa(xmm2, Address(buf, 0));
8365 movdqa(xmm3, Address(buf, 16));
8366 movdqa(xmm4, Address(buf, 32));
8367 addptr(buf, 48);
8368 subl(len, 3);
8369 jcc(Assembler::lessEqual, L_fold_512b);
8370
8371 // Fold total 512 bits of polynomial on each iteration,
8372 // 128 bits per each of 4 parallel streams.
8373 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8374
8375 align32();
8376 BIND(L_fold_512b_loop);
8377 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8378 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8379 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8380 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8381 addptr(buf, 64);
8382 subl(len, 4);
8383 jcc(Assembler::greater, L_fold_512b_loop);
8384
8385 // Fold 512 bits to 128 bits.
8386 BIND(L_fold_512b);
8387 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8388 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8389 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8390 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8391
8392 // Fold the rest of 128 bits data chunks
8393 BIND(L_fold_tail);
8394 addl(len, 3);
8395 jccb(Assembler::lessEqual, L_fold_128b);
8396 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8397
8398 BIND(L_fold_tail_loop);
8399 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8400 addptr(buf, 16);
8401 decrementl(len);
8402 jccb(Assembler::greater, L_fold_tail_loop);
8403
8404 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8405 BIND(L_fold_128b);
8406 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8407 if (UseAVX > 0) {
8408 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8409 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8410 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8411 } else {
8412 movdqa(xmm2, xmm0);
8413 pclmulqdq(xmm2, xmm1, 0x1);
8414 movdqa(xmm3, xmm0);
8415 pand(xmm3, xmm2);
8416 pclmulqdq(xmm0, xmm3, 0x1);
8417 }
8418 psrldq(xmm1, 8);
8419 psrldq(xmm2, 4);
8420 pxor(xmm0, xmm1);
8421 pxor(xmm0, xmm2);
8422
8423 // 8 8-bit folds to compute 32-bit CRC.
8424 for (int j = 0; j < 4; j++) {
8425 fold_8bit_crc32(xmm0, table, xmm1, rax);
8426 }
8427 movdl(crc, xmm0); // mov 32 bits to general register
8428 for (int j = 0; j < 4; j++) {
8429 fold_8bit_crc32(crc, table, rax);
8430 }
8431
8432 BIND(L_tail_restore);
8433 movl(len, tmp); // restore
8434 BIND(L_tail);
8435 andl(len, 0xf);
8436 jccb(Assembler::zero, L_exit);
8437
8438 // Fold the rest of bytes
8439 align(4);
8440 BIND(L_tail_loop);
8441 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8442 update_byte_crc32(crc, rax, table);
8443 increment(buf);
8444 decrementl(len);
8445 jccb(Assembler::greater, L_tail_loop);
8446
8447 BIND(L_exit);
8448 notl(crc); // ~c
8449 }
8450
8451 #ifdef _LP64
8452 // Helper function for AVX 512 CRC32
8453 // Fold 512-bit data chunks
8454 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8455 Register pos, int offset) {
8456 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8457 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8458 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8459 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8460 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8461 }
8462
8463 // Helper function for AVX 512 CRC32
8464 // Compute CRC32 for < 256B buffers
8465 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8466 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8467 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8468
8469 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8470 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8471 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8472
8473 // check if there is enough buffer to be able to fold 16B at a time
8474 cmpl(len, 32);
8475 jcc(Assembler::less, L_less_than_32);
8476
8477 // if there is, load the constants
8478 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8479 movdl(xmm0, crc); // get the initial crc value
8480 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8481 pxor(xmm7, xmm0);
8482
8483 // update the buffer pointer
8484 addl(pos, 16);
8485 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8486 subl(len, 32);
8487 jmp(L_16B_reduction_loop);
8488
8489 bind(L_less_than_32);
8490 //mov initial crc to the return value. this is necessary for zero - length buffers.
8491 movl(rax, crc);
8492 testl(len, len);
8493 jcc(Assembler::equal, L_cleanup);
8494
8495 movdl(xmm0, crc); //get the initial crc value
8496
8497 cmpl(len, 16);
8498 jcc(Assembler::equal, L_exact_16_left);
8499 jcc(Assembler::less, L_less_than_16_left);
8500
8501 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8502 pxor(xmm7, xmm0); //xor the initial crc value
8503 addl(pos, 16);
8504 subl(len, 16);
8505 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8506 jmp(L_get_last_two_xmms);
8507
8508 bind(L_less_than_16_left);
8509 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8510 pxor(xmm1, xmm1);
8511 movptr(tmp1, rsp);
8512 movdqu(Address(tmp1, 0 * 16), xmm1);
8513
8514 cmpl(len, 4);
8515 jcc(Assembler::less, L_only_less_than_4);
8516
8517 //backup the counter value
8518 movl(tmp2, len);
8519 cmpl(len, 8);
8520 jcc(Assembler::less, L_less_than_8_left);
8521
8522 //load 8 Bytes
8523 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8524 movq(Address(tmp1, 0 * 16), rax);
8525 addptr(tmp1, 8);
8526 subl(len, 8);
8527 addl(pos, 8);
8528
8529 bind(L_less_than_8_left);
8530 cmpl(len, 4);
8531 jcc(Assembler::less, L_less_than_4_left);
8532
8533 //load 4 Bytes
8534 movl(rax, Address(buf, pos, Address::times_1, 0));
8535 movl(Address(tmp1, 0 * 16), rax);
8536 addptr(tmp1, 4);
8537 subl(len, 4);
8538 addl(pos, 4);
8539
8540 bind(L_less_than_4_left);
8541 cmpl(len, 2);
8542 jcc(Assembler::less, L_less_than_2_left);
8543
8544 // load 2 Bytes
8545 movw(rax, Address(buf, pos, Address::times_1, 0));
8546 movl(Address(tmp1, 0 * 16), rax);
8547 addptr(tmp1, 2);
8548 subl(len, 2);
8549 addl(pos, 2);
8550
8551 bind(L_less_than_2_left);
8552 cmpl(len, 1);
8553 jcc(Assembler::less, L_zero_left);
8554
8555 // load 1 Byte
8556 movb(rax, Address(buf, pos, Address::times_1, 0));
8557 movb(Address(tmp1, 0 * 16), rax);
8558
8559 bind(L_zero_left);
8560 movdqu(xmm7, Address(rsp, 0));
8561 pxor(xmm7, xmm0); //xor the initial crc value
8562
8563 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8564 movdqu(xmm0, Address(rax, tmp2));
8565 pshufb(xmm7, xmm0);
8566 jmp(L_128_done);
8567
8568 bind(L_exact_16_left);
8569 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8570 pxor(xmm7, xmm0); //xor the initial crc value
8571 jmp(L_128_done);
8572
8573 bind(L_only_less_than_4);
8574 cmpl(len, 3);
8575 jcc(Assembler::less, L_only_less_than_3);
8576
8577 // load 3 Bytes
8578 movb(rax, Address(buf, pos, Address::times_1, 0));
8579 movb(Address(tmp1, 0), rax);
8580
8581 movb(rax, Address(buf, pos, Address::times_1, 1));
8582 movb(Address(tmp1, 1), rax);
8583
8584 movb(rax, Address(buf, pos, Address::times_1, 2));
8585 movb(Address(tmp1, 2), rax);
8586
8587 movdqu(xmm7, Address(rsp, 0));
8588 pxor(xmm7, xmm0); //xor the initial crc value
8589
8590 pslldq(xmm7, 0x5);
8591 jmp(L_barrett);
8592 bind(L_only_less_than_3);
8593 cmpl(len, 2);
8594 jcc(Assembler::less, L_only_less_than_2);
8595
8596 // load 2 Bytes
8597 movb(rax, Address(buf, pos, Address::times_1, 0));
8598 movb(Address(tmp1, 0), rax);
8599
8600 movb(rax, Address(buf, pos, Address::times_1, 1));
8601 movb(Address(tmp1, 1), rax);
8602
8603 movdqu(xmm7, Address(rsp, 0));
8604 pxor(xmm7, xmm0); //xor the initial crc value
8605
8606 pslldq(xmm7, 0x6);
8607 jmp(L_barrett);
8608
8609 bind(L_only_less_than_2);
8610 //load 1 Byte
8611 movb(rax, Address(buf, pos, Address::times_1, 0));
8612 movb(Address(tmp1, 0), rax);
8613
8614 movdqu(xmm7, Address(rsp, 0));
8615 pxor(xmm7, xmm0); //xor the initial crc value
8616
8617 pslldq(xmm7, 0x7);
8618 }
8619
8620 /**
8621 * Compute CRC32 using AVX512 instructions
8622 * param crc register containing existing CRC (32-bit)
8623 * param buf register pointing to input byte buffer (byte*)
8624 * param len register containing number of bytes
8625 * param table address of crc or crc32c table
8626 * param tmp1 scratch register
8627 * param tmp2 scratch register
8628 * return rax result register
8629 *
8630 * This routine is identical for crc32c with the exception of the precomputed constant
8631 * table which will be passed as the table argument. The calculation steps are
8632 * the same for both variants.
8633 */
8634 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8635 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8636
8637 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8638 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8639 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8640 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8641 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8642
8643 const Register pos = r12;
8644 push(r12);
8645 subptr(rsp, 16 * 2 + 8);
8646
8647 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8648 // context for the registers used, where all instructions below are using 128-bit mode
8649 // On EVEX without VL and BW, these instructions will all be AVX.
8650 movl(pos, 0);
8651
8652 // check if smaller than 256B
8653 cmpl(len, 256);
8654 jcc(Assembler::less, L_less_than_256);
8655
8656 // load the initial crc value
8657 movdl(xmm10, crc);
8658
8659 // receive the initial 64B data, xor the initial crc value
8660 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8661 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8662 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8663 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8664
8665 subl(len, 256);
8666 cmpl(len, 256);
8667 jcc(Assembler::less, L_fold_128_B_loop);
8668
8669 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8670 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8671 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8672 subl(len, 256);
8673
8674 bind(L_fold_256_B_loop);
8675 addl(pos, 256);
8676 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8677 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8678 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8679 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8680
8681 subl(len, 256);
8682 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8683
8684 // Fold 256 into 128
8685 addl(pos, 256);
8686 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8687 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8688 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8689
8690 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8691 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8692 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8693
8694 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8695 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8696
8697 addl(len, 128);
8698 jmp(L_fold_128_B_register);
8699
8700 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8701 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8702
8703 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8704 bind(L_fold_128_B_loop);
8705 addl(pos, 128);
8706 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8707 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8708
8709 subl(len, 128);
8710 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8711
8712 addl(pos, 128);
8713
8714 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8715 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8716 bind(L_fold_128_B_register);
8717 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8718 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8719 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8720 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8721 // save last that has no multiplicand
8722 vextracti64x2(xmm7, xmm4, 3);
8723
8724 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8725 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8726 // Needed later in reduction loop
8727 movdqu(xmm10, Address(table, 1 * 16));
8728 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8729 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8730
8731 // Swap 1,0,3,2 - 01 00 11 10
8732 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8733 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8734 vextracti128(xmm5, xmm8, 1);
8735 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8736
8737 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8738 // instead of a cmp instruction, we use the negative flag with the jl instruction
8739 addl(len, 128 - 16);
8740 jcc(Assembler::less, L_final_reduction_for_128);
8741
8742 bind(L_16B_reduction_loop);
8743 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8744 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8745 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8746 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8747 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8748 addl(pos, 16);
8749 subl(len, 16);
8750 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8751
8752 bind(L_final_reduction_for_128);
8753 addl(len, 16);
8754 jcc(Assembler::equal, L_128_done);
8755
8756 bind(L_get_last_two_xmms);
8757 movdqu(xmm2, xmm7);
8758 addl(pos, len);
8759 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8760 subl(pos, len);
8761
8762 // get rid of the extra data that was loaded before
8763 // load the shift constant
8764 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8765 movdqu(xmm0, Address(rax, len));
8766 addl(rax, len);
8767
8768 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8769 //Change mask to 512
8770 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8771 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8772
8773 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8774 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8775 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8776 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8777 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8778
8779 bind(L_128_done);
8780 // compute crc of a 128-bit value
8781 movdqu(xmm10, Address(table, 3 * 16));
8782 movdqu(xmm0, xmm7);
8783
8784 // 64b fold
8785 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8786 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8787 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8788
8789 // 32b fold
8790 movdqu(xmm0, xmm7);
8791 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8792 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8793 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8794 jmp(L_barrett);
8795
8796 bind(L_less_than_256);
8797 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8798
8799 //barrett reduction
8800 bind(L_barrett);
8801 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8802 movdqu(xmm1, xmm7);
8803 movdqu(xmm2, xmm7);
8804 movdqu(xmm10, Address(table, 4 * 16));
8805
8806 pclmulqdq(xmm7, xmm10, 0x0);
8807 pxor(xmm7, xmm2);
8808 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8809 movdqu(xmm2, xmm7);
8810 pclmulqdq(xmm7, xmm10, 0x10);
8811 pxor(xmm7, xmm2);
8812 pxor(xmm7, xmm1);
8813 pextrd(crc, xmm7, 2);
8814
8815 bind(L_cleanup);
8816 addptr(rsp, 16 * 2 + 8);
8817 pop(r12);
8818 }
8819
8820 // S. Gueron / Information Processing Letters 112 (2012) 184
8821 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8822 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8823 // Output: the 64-bit carry-less product of B * CONST
8824 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8825 Register tmp1, Register tmp2, Register tmp3) {
8826 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8827 if (n > 0) {
8828 addq(tmp3, n * 256 * 8);
8829 }
8830 // Q1 = TABLEExt[n][B & 0xFF];
8831 movl(tmp1, in);
8832 andl(tmp1, 0x000000FF);
8833 shll(tmp1, 3);
8834 addq(tmp1, tmp3);
8835 movq(tmp1, Address(tmp1, 0));
8836
8837 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8838 movl(tmp2, in);
8839 shrl(tmp2, 8);
8840 andl(tmp2, 0x000000FF);
8841 shll(tmp2, 3);
8842 addq(tmp2, tmp3);
8843 movq(tmp2, Address(tmp2, 0));
8844
8845 shlq(tmp2, 8);
8846 xorq(tmp1, tmp2);
8847
8848 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8849 movl(tmp2, in);
8850 shrl(tmp2, 16);
8851 andl(tmp2, 0x000000FF);
8852 shll(tmp2, 3);
8853 addq(tmp2, tmp3);
8854 movq(tmp2, Address(tmp2, 0));
8855
8856 shlq(tmp2, 16);
8857 xorq(tmp1, tmp2);
8858
8859 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8860 shrl(in, 24);
8861 andl(in, 0x000000FF);
8862 shll(in, 3);
8863 addq(in, tmp3);
8864 movq(in, Address(in, 0));
8865
8866 shlq(in, 24);
8867 xorq(in, tmp1);
8868 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8869 }
8870
8871 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8872 Register in_out,
8873 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8874 XMMRegister w_xtmp2,
8875 Register tmp1,
8876 Register n_tmp2, Register n_tmp3) {
8877 if (is_pclmulqdq_supported) {
8878 movdl(w_xtmp1, in_out); // modified blindly
8879
8880 movl(tmp1, const_or_pre_comp_const_index);
8881 movdl(w_xtmp2, tmp1);
8882 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8883
8884 movdq(in_out, w_xtmp1);
8885 } else {
8886 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8887 }
8888 }
8889
8890 // Recombination Alternative 2: No bit-reflections
8891 // T1 = (CRC_A * U1) << 1
8892 // T2 = (CRC_B * U2) << 1
8893 // C1 = T1 >> 32
8894 // C2 = T2 >> 32
8895 // T1 = T1 & 0xFFFFFFFF
8896 // T2 = T2 & 0xFFFFFFFF
8897 // T1 = CRC32(0, T1)
8898 // T2 = CRC32(0, T2)
8899 // C1 = C1 ^ T1
8900 // C2 = C2 ^ T2
8901 // CRC = C1 ^ C2 ^ CRC_C
8902 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8903 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8904 Register tmp1, Register tmp2,
8905 Register n_tmp3) {
8906 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8907 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8908 shlq(in_out, 1);
8909 movl(tmp1, in_out);
8910 shrq(in_out, 32);
8911 xorl(tmp2, tmp2);
8912 crc32(tmp2, tmp1, 4);
8913 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8914 shlq(in1, 1);
8915 movl(tmp1, in1);
8916 shrq(in1, 32);
8917 xorl(tmp2, tmp2);
8918 crc32(tmp2, tmp1, 4);
8919 xorl(in1, tmp2);
8920 xorl(in_out, in1);
8921 xorl(in_out, in2);
8922 }
8923
8924 // Set N to predefined value
8925 // Subtract from a length of a buffer
8926 // execute in a loop:
8927 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8928 // for i = 1 to N do
8929 // CRC_A = CRC32(CRC_A, A[i])
8930 // CRC_B = CRC32(CRC_B, B[i])
8931 // CRC_C = CRC32(CRC_C, C[i])
8932 // end for
8933 // Recombine
8934 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8935 Register in_out1, Register in_out2, Register in_out3,
8936 Register tmp1, Register tmp2, Register tmp3,
8937 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8938 Register tmp4, Register tmp5,
8939 Register n_tmp6) {
8940 Label L_processPartitions;
8941 Label L_processPartition;
8942 Label L_exit;
8943
8944 bind(L_processPartitions);
8945 cmpl(in_out1, 3 * size);
8946 jcc(Assembler::less, L_exit);
8947 xorl(tmp1, tmp1);
8948 xorl(tmp2, tmp2);
8949 movq(tmp3, in_out2);
8950 addq(tmp3, size);
8951
8952 bind(L_processPartition);
8953 crc32(in_out3, Address(in_out2, 0), 8);
8954 crc32(tmp1, Address(in_out2, size), 8);
8955 crc32(tmp2, Address(in_out2, size * 2), 8);
8956 addq(in_out2, 8);
8957 cmpq(in_out2, tmp3);
8958 jcc(Assembler::less, L_processPartition);
8959 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8960 w_xtmp1, w_xtmp2, w_xtmp3,
8961 tmp4, tmp5,
8962 n_tmp6);
8963 addq(in_out2, 2 * size);
8964 subl(in_out1, 3 * size);
8965 jmp(L_processPartitions);
8966
8967 bind(L_exit);
8968 }
8969 #else
8970 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
8971 Register tmp1, Register tmp2, Register tmp3,
8972 XMMRegister xtmp1, XMMRegister xtmp2) {
8973 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8974 if (n > 0) {
8975 addl(tmp3, n * 256 * 8);
8976 }
8977 // Q1 = TABLEExt[n][B & 0xFF];
8978 movl(tmp1, in_out);
8979 andl(tmp1, 0x000000FF);
8980 shll(tmp1, 3);
8981 addl(tmp1, tmp3);
8982 movq(xtmp1, Address(tmp1, 0));
8983
8984 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8985 movl(tmp2, in_out);
8986 shrl(tmp2, 8);
8987 andl(tmp2, 0x000000FF);
8988 shll(tmp2, 3);
8989 addl(tmp2, tmp3);
8990 movq(xtmp2, Address(tmp2, 0));
8991
8992 psllq(xtmp2, 8);
8993 pxor(xtmp1, xtmp2);
8994
8995 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8996 movl(tmp2, in_out);
8997 shrl(tmp2, 16);
8998 andl(tmp2, 0x000000FF);
8999 shll(tmp2, 3);
9000 addl(tmp2, tmp3);
9001 movq(xtmp2, Address(tmp2, 0));
9002
9003 psllq(xtmp2, 16);
9004 pxor(xtmp1, xtmp2);
9005
9006 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9007 shrl(in_out, 24);
9008 andl(in_out, 0x000000FF);
9009 shll(in_out, 3);
9010 addl(in_out, tmp3);
9011 movq(xtmp2, Address(in_out, 0));
9012
9013 psllq(xtmp2, 24);
9014 pxor(xtmp1, xtmp2); // Result in CXMM
9015 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9016 }
9017
9018 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9019 Register in_out,
9020 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9021 XMMRegister w_xtmp2,
9022 Register tmp1,
9023 Register n_tmp2, Register n_tmp3) {
9024 if (is_pclmulqdq_supported) {
9025 movdl(w_xtmp1, in_out);
9026
9027 movl(tmp1, const_or_pre_comp_const_index);
9028 movdl(w_xtmp2, tmp1);
9029 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9030 // Keep result in XMM since GPR is 32 bit in length
9031 } else {
9032 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
9033 }
9034 }
9035
9036 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9037 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9038 Register tmp1, Register tmp2,
9039 Register n_tmp3) {
9040 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9041 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9042
9043 psllq(w_xtmp1, 1);
9044 movdl(tmp1, w_xtmp1);
9045 psrlq(w_xtmp1, 32);
9046 movdl(in_out, w_xtmp1);
9047
9048 xorl(tmp2, tmp2);
9049 crc32(tmp2, tmp1, 4);
9050 xorl(in_out, tmp2);
9051
9052 psllq(w_xtmp2, 1);
9053 movdl(tmp1, w_xtmp2);
9054 psrlq(w_xtmp2, 32);
9055 movdl(in1, w_xtmp2);
9056
9057 xorl(tmp2, tmp2);
9058 crc32(tmp2, tmp1, 4);
9059 xorl(in1, tmp2);
9060 xorl(in_out, in1);
9061 xorl(in_out, in2);
9062 }
9063
9064 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9065 Register in_out1, Register in_out2, Register in_out3,
9066 Register tmp1, Register tmp2, Register tmp3,
9067 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9068 Register tmp4, Register tmp5,
9069 Register n_tmp6) {
9070 Label L_processPartitions;
9071 Label L_processPartition;
9072 Label L_exit;
9073
9074 bind(L_processPartitions);
9075 cmpl(in_out1, 3 * size);
9076 jcc(Assembler::less, L_exit);
9077 xorl(tmp1, tmp1);
9078 xorl(tmp2, tmp2);
9079 movl(tmp3, in_out2);
9080 addl(tmp3, size);
9081
9082 bind(L_processPartition);
9083 crc32(in_out3, Address(in_out2, 0), 4);
9084 crc32(tmp1, Address(in_out2, size), 4);
9085 crc32(tmp2, Address(in_out2, size*2), 4);
9086 crc32(in_out3, Address(in_out2, 0+4), 4);
9087 crc32(tmp1, Address(in_out2, size+4), 4);
9088 crc32(tmp2, Address(in_out2, size*2+4), 4);
9089 addl(in_out2, 8);
9090 cmpl(in_out2, tmp3);
9091 jcc(Assembler::less, L_processPartition);
9092
9093 push(tmp3);
9094 push(in_out1);
9095 push(in_out2);
9096 tmp4 = tmp3;
9097 tmp5 = in_out1;
9098 n_tmp6 = in_out2;
9099
9100 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9101 w_xtmp1, w_xtmp2, w_xtmp3,
9102 tmp4, tmp5,
9103 n_tmp6);
9104
9105 pop(in_out2);
9106 pop(in_out1);
9107 pop(tmp3);
9108
9109 addl(in_out2, 2 * size);
9110 subl(in_out1, 3 * size);
9111 jmp(L_processPartitions);
9112
9113 bind(L_exit);
9114 }
9115 #endif //LP64
9116
9117 #ifdef _LP64
9118 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9119 // Input: A buffer I of L bytes.
9120 // Output: the CRC32C value of the buffer.
9121 // Notations:
9122 // Write L = 24N + r, with N = floor (L/24).
9123 // r = L mod 24 (0 <= r < 24).
9124 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9125 // N quadwords, and R consists of r bytes.
9126 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9127 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9128 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9129 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9130 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9131 Register tmp1, Register tmp2, Register tmp3,
9132 Register tmp4, Register tmp5, Register tmp6,
9133 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9134 bool is_pclmulqdq_supported) {
9135 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9136 Label L_wordByWord;
9137 Label L_byteByByteProlog;
9138 Label L_byteByByte;
9139 Label L_exit;
9140
9141 if (is_pclmulqdq_supported ) {
9142 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9143 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
9144
9145 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9146 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9147
9148 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9149 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9150 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9151 } else {
9152 const_or_pre_comp_const_index[0] = 1;
9153 const_or_pre_comp_const_index[1] = 0;
9154
9155 const_or_pre_comp_const_index[2] = 3;
9156 const_or_pre_comp_const_index[3] = 2;
9157
9158 const_or_pre_comp_const_index[4] = 5;
9159 const_or_pre_comp_const_index[5] = 4;
9160 }
9161 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9162 in2, in1, in_out,
9163 tmp1, tmp2, tmp3,
9164 w_xtmp1, w_xtmp2, w_xtmp3,
9165 tmp4, tmp5,
9166 tmp6);
9167 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9168 in2, in1, in_out,
9169 tmp1, tmp2, tmp3,
9170 w_xtmp1, w_xtmp2, w_xtmp3,
9171 tmp4, tmp5,
9172 tmp6);
9173 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9174 in2, in1, in_out,
9175 tmp1, tmp2, tmp3,
9176 w_xtmp1, w_xtmp2, w_xtmp3,
9177 tmp4, tmp5,
9178 tmp6);
9179 movl(tmp1, in2);
9180 andl(tmp1, 0x00000007);
9181 negl(tmp1);
9182 addl(tmp1, in2);
9183 addq(tmp1, in1);
9184
9185 cmpq(in1, tmp1);
9186 jccb(Assembler::greaterEqual, L_byteByByteProlog);
9187 align(16);
9188 BIND(L_wordByWord);
9189 crc32(in_out, Address(in1, 0), 8);
9190 addq(in1, 8);
9191 cmpq(in1, tmp1);
9192 jcc(Assembler::less, L_wordByWord);
9193
9194 BIND(L_byteByByteProlog);
9195 andl(in2, 0x00000007);
9196 movl(tmp2, 1);
9197
9198 cmpl(tmp2, in2);
9199 jccb(Assembler::greater, L_exit);
9200 BIND(L_byteByByte);
9201 crc32(in_out, Address(in1, 0), 1);
9202 incq(in1);
9203 incl(tmp2);
9204 cmpl(tmp2, in2);
9205 jcc(Assembler::lessEqual, L_byteByByte);
9206
9207 BIND(L_exit);
9208 }
9209 #else
9210 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9211 Register tmp1, Register tmp2, Register tmp3,
9212 Register tmp4, Register tmp5, Register tmp6,
9213 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9214 bool is_pclmulqdq_supported) {
9215 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9216 Label L_wordByWord;
9217 Label L_byteByByteProlog;
9218 Label L_byteByByte;
9219 Label L_exit;
9220
9221 if (is_pclmulqdq_supported) {
9222 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9223 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
9224
9225 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9226 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9227
9228 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9229 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9230 } else {
9231 const_or_pre_comp_const_index[0] = 1;
9232 const_or_pre_comp_const_index[1] = 0;
9233
9234 const_or_pre_comp_const_index[2] = 3;
9235 const_or_pre_comp_const_index[3] = 2;
9236
9237 const_or_pre_comp_const_index[4] = 5;
9238 const_or_pre_comp_const_index[5] = 4;
9239 }
9240 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9241 in2, in1, in_out,
9242 tmp1, tmp2, tmp3,
9243 w_xtmp1, w_xtmp2, w_xtmp3,
9244 tmp4, tmp5,
9245 tmp6);
9246 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9247 in2, in1, in_out,
9248 tmp1, tmp2, tmp3,
9249 w_xtmp1, w_xtmp2, w_xtmp3,
9250 tmp4, tmp5,
9251 tmp6);
9252 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9253 in2, in1, in_out,
9254 tmp1, tmp2, tmp3,
9255 w_xtmp1, w_xtmp2, w_xtmp3,
9256 tmp4, tmp5,
9257 tmp6);
9258 movl(tmp1, in2);
9259 andl(tmp1, 0x00000007);
9260 negl(tmp1);
9261 addl(tmp1, in2);
9262 addl(tmp1, in1);
9263
9264 BIND(L_wordByWord);
9265 cmpl(in1, tmp1);
9266 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9267 crc32(in_out, Address(in1,0), 4);
9268 addl(in1, 4);
9269 jmp(L_wordByWord);
9270
9271 BIND(L_byteByByteProlog);
9272 andl(in2, 0x00000007);
9273 movl(tmp2, 1);
9274
9275 BIND(L_byteByByte);
9276 cmpl(tmp2, in2);
9277 jccb(Assembler::greater, L_exit);
9278 movb(tmp1, Address(in1, 0));
9279 crc32(in_out, tmp1, 1);
9280 incl(in1);
9281 incl(tmp2);
9282 jmp(L_byteByByte);
9283
9284 BIND(L_exit);
9285 }
9286 #endif // LP64
9287 #undef BIND
9288 #undef BLOCK_COMMENT
9289
9290 // Compress char[] array to byte[].
9291 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
9292 // Return the array length if every element in array can be encoded,
9293 // otherwise, the index of first non-latin1 (> 0xff) character.
9294 // @IntrinsicCandidate
9295 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9296 // for (int i = 0; i < len; i++) {
9297 // char c = src[srcOff];
9298 // if (c > 0xff) {
9299 // return i; // return index of non-latin1 char
9300 // }
9301 // dst[dstOff] = (byte)c;
9302 // srcOff++;
9303 // dstOff++;
9304 // }
9305 // return len;
9306 // }
9307 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9308 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9309 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9310 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9311 Label copy_chars_loop, done, reset_sp, copy_tail;
9312
9313 // rsi: src
9314 // rdi: dst
9315 // rdx: len
9316 // rcx: tmp5
9317 // rax: result
9318
9319 // rsi holds start addr of source char[] to be compressed
9320 // rdi holds start addr of destination byte[]
9321 // rdx holds length
9322
9323 assert(len != result, "");
9324
9325 // save length for return
9326 movl(result, len);
9327
9328 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9329 VM_Version::supports_avx512vlbw() &&
9330 VM_Version::supports_bmi2()) {
9331
9332 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9333
9334 // alignment
9335 Label post_alignment;
9336
9337 // if length of the string is less than 32, handle it the old fashioned way
9338 testl(len, -32);
9339 jcc(Assembler::zero, below_threshold);
9340
9341 // First check whether a character is compressible ( <= 0xFF).
9342 // Create mask to test for Unicode chars inside zmm vector
9343 movl(tmp5, 0x00FF);
9344 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9345
9346 testl(len, -64);
9347 jccb(Assembler::zero, post_alignment);
9348
9349 movl(tmp5, dst);
9350 andl(tmp5, (32 - 1));
9351 negl(tmp5);
9352 andl(tmp5, (32 - 1));
9353
9354 // bail out when there is nothing to be done
9355 testl(tmp5, 0xFFFFFFFF);
9356 jccb(Assembler::zero, post_alignment);
9357
9358 // ~(~0 << len), where len is the # of remaining elements to process
9359 movl(len, 0xFFFFFFFF);
9360 shlxl(len, len, tmp5);
9361 notl(len);
9362 kmovdl(mask2, len);
9363 movl(len, result);
9364
9365 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9366 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9367 ktestd(mask1, mask2);
9368 jcc(Assembler::carryClear, copy_tail);
9369
9370 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9371
9372 addptr(src, tmp5);
9373 addptr(src, tmp5);
9374 addptr(dst, tmp5);
9375 subl(len, tmp5);
9376
9377 bind(post_alignment);
9378 // end of alignment
9379
9380 movl(tmp5, len);
9381 andl(tmp5, (32 - 1)); // tail count (in chars)
9382 andl(len, ~(32 - 1)); // vector count (in chars)
9383 jccb(Assembler::zero, copy_loop_tail);
9384
9385 lea(src, Address(src, len, Address::times_2));
9386 lea(dst, Address(dst, len, Address::times_1));
9387 negptr(len);
9388
9389 bind(copy_32_loop);
9390 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9391 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9392 kortestdl(mask1, mask1);
9393 jccb(Assembler::carryClear, reset_for_copy_tail);
9394
9395 // All elements in current processed chunk are valid candidates for
9396 // compression. Write a truncated byte elements to the memory.
9397 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9398 addptr(len, 32);
9399 jccb(Assembler::notZero, copy_32_loop);
9400
9401 bind(copy_loop_tail);
9402 // bail out when there is nothing to be done
9403 testl(tmp5, 0xFFFFFFFF);
9404 jcc(Assembler::zero, done);
9405
9406 movl(len, tmp5);
9407
9408 // ~(~0 << len), where len is the # of remaining elements to process
9409 movl(tmp5, 0xFFFFFFFF);
9410 shlxl(tmp5, tmp5, len);
9411 notl(tmp5);
9412
9413 kmovdl(mask2, tmp5);
9414
9415 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9416 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9417 ktestd(mask1, mask2);
9418 jcc(Assembler::carryClear, copy_tail);
9419
9420 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9421 jmp(done);
9422
9423 bind(reset_for_copy_tail);
9424 lea(src, Address(src, tmp5, Address::times_2));
9425 lea(dst, Address(dst, tmp5, Address::times_1));
9426 subptr(len, tmp5);
9427 jmp(copy_chars_loop);
9428
9429 bind(below_threshold);
9430 }
9431
9432 if (UseSSE42Intrinsics) {
9433 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9434
9435 // vectored compression
9436 testl(len, 0xfffffff8);
9437 jcc(Assembler::zero, copy_tail);
9438
9439 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9440 movdl(tmp1Reg, tmp5);
9441 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9442
9443 andl(len, 0xfffffff0);
9444 jccb(Assembler::zero, copy_16);
9445
9446 // compress 16 chars per iter
9447 pxor(tmp4Reg, tmp4Reg);
9448
9449 lea(src, Address(src, len, Address::times_2));
9450 lea(dst, Address(dst, len, Address::times_1));
9451 negptr(len);
9452
9453 bind(copy_32_loop);
9454 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9455 por(tmp4Reg, tmp2Reg);
9456 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9457 por(tmp4Reg, tmp3Reg);
9458 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9459 jccb(Assembler::notZero, reset_for_copy_tail);
9460 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9461 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9462 addptr(len, 16);
9463 jccb(Assembler::notZero, copy_32_loop);
9464
9465 // compress next vector of 8 chars (if any)
9466 bind(copy_16);
9467 // len = 0
9468 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9469 jccb(Assembler::zero, copy_tail_sse);
9470
9471 pxor(tmp3Reg, tmp3Reg);
9472
9473 movdqu(tmp2Reg, Address(src, 0));
9474 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9475 jccb(Assembler::notZero, reset_for_copy_tail);
9476 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9477 movq(Address(dst, 0), tmp2Reg);
9478 addptr(src, 16);
9479 addptr(dst, 8);
9480 jmpb(copy_tail_sse);
9481
9482 bind(reset_for_copy_tail);
9483 movl(tmp5, result);
9484 andl(tmp5, 0x0000000f);
9485 lea(src, Address(src, tmp5, Address::times_2));
9486 lea(dst, Address(dst, tmp5, Address::times_1));
9487 subptr(len, tmp5);
9488 jmpb(copy_chars_loop);
9489
9490 bind(copy_tail_sse);
9491 movl(len, result);
9492 andl(len, 0x00000007); // tail count (in chars)
9493 }
9494 // compress 1 char per iter
9495 bind(copy_tail);
9496 testl(len, len);
9497 jccb(Assembler::zero, done);
9498 lea(src, Address(src, len, Address::times_2));
9499 lea(dst, Address(dst, len, Address::times_1));
9500 negptr(len);
9501
9502 bind(copy_chars_loop);
9503 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9504 testl(tmp5, 0xff00); // check if Unicode char
9505 jccb(Assembler::notZero, reset_sp);
9506 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9507 increment(len);
9508 jccb(Assembler::notZero, copy_chars_loop);
9509
9510 // add len then return (len will be zero if compress succeeded, otherwise negative)
9511 bind(reset_sp);
9512 addl(result, len);
9513
9514 bind(done);
9515 }
9516
9517 // Inflate byte[] array to char[].
9518 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9519 // @IntrinsicCandidate
9520 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9521 // for (int i = 0; i < len; i++) {
9522 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9523 // }
9524 // }
9525 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9526 XMMRegister tmp1, Register tmp2, KRegister mask) {
9527 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9528 // rsi: src
9529 // rdi: dst
9530 // rdx: len
9531 // rcx: tmp2
9532
9533 // rsi holds start addr of source byte[] to be inflated
9534 // rdi holds start addr of destination char[]
9535 // rdx holds length
9536 assert_different_registers(src, dst, len, tmp2);
9537 movl(tmp2, len);
9538 if ((UseAVX > 2) && // AVX512
9539 VM_Version::supports_avx512vlbw() &&
9540 VM_Version::supports_bmi2()) {
9541
9542 Label copy_32_loop, copy_tail;
9543 Register tmp3_aliased = len;
9544
9545 // if length of the string is less than 16, handle it in an old fashioned way
9546 testl(len, -16);
9547 jcc(Assembler::zero, below_threshold);
9548
9549 testl(len, -1 * AVX3Threshold);
9550 jcc(Assembler::zero, avx3_threshold);
9551
9552 // In order to use only one arithmetic operation for the main loop we use
9553 // this pre-calculation
9554 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9555 andl(len, -32); // vector count
9556 jccb(Assembler::zero, copy_tail);
9557
9558 lea(src, Address(src, len, Address::times_1));
9559 lea(dst, Address(dst, len, Address::times_2));
9560 negptr(len);
9561
9562
9563 // inflate 32 chars per iter
9564 bind(copy_32_loop);
9565 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9566 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9567 addptr(len, 32);
9568 jcc(Assembler::notZero, copy_32_loop);
9569
9570 bind(copy_tail);
9571 // bail out when there is nothing to be done
9572 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9573 jcc(Assembler::zero, done);
9574
9575 // ~(~0 << length), where length is the # of remaining elements to process
9576 movl(tmp3_aliased, -1);
9577 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9578 notl(tmp3_aliased);
9579 kmovdl(mask, tmp3_aliased);
9580 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9581 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9582
9583 jmp(done);
9584 bind(avx3_threshold);
9585 }
9586 if (UseSSE42Intrinsics) {
9587 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9588
9589 if (UseAVX > 1) {
9590 andl(tmp2, (16 - 1));
9591 andl(len, -16);
9592 jccb(Assembler::zero, copy_new_tail);
9593 } else {
9594 andl(tmp2, 0x00000007); // tail count (in chars)
9595 andl(len, 0xfffffff8); // vector count (in chars)
9596 jccb(Assembler::zero, copy_tail);
9597 }
9598
9599 // vectored inflation
9600 lea(src, Address(src, len, Address::times_1));
9601 lea(dst, Address(dst, len, Address::times_2));
9602 negptr(len);
9603
9604 if (UseAVX > 1) {
9605 bind(copy_16_loop);
9606 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9607 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9608 addptr(len, 16);
9609 jcc(Assembler::notZero, copy_16_loop);
9610
9611 bind(below_threshold);
9612 bind(copy_new_tail);
9613 movl(len, tmp2);
9614 andl(tmp2, 0x00000007);
9615 andl(len, 0xFFFFFFF8);
9616 jccb(Assembler::zero, copy_tail);
9617
9618 pmovzxbw(tmp1, Address(src, 0));
9619 movdqu(Address(dst, 0), tmp1);
9620 addptr(src, 8);
9621 addptr(dst, 2 * 8);
9622
9623 jmp(copy_tail, true);
9624 }
9625
9626 // inflate 8 chars per iter
9627 bind(copy_8_loop);
9628 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9629 movdqu(Address(dst, len, Address::times_2), tmp1);
9630 addptr(len, 8);
9631 jcc(Assembler::notZero, copy_8_loop);
9632
9633 bind(copy_tail);
9634 movl(len, tmp2);
9635
9636 cmpl(len, 4);
9637 jccb(Assembler::less, copy_bytes);
9638
9639 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9640 pmovzxbw(tmp1, tmp1);
9641 movq(Address(dst, 0), tmp1);
9642 subptr(len, 4);
9643 addptr(src, 4);
9644 addptr(dst, 8);
9645
9646 bind(copy_bytes);
9647 } else {
9648 bind(below_threshold);
9649 }
9650
9651 testl(len, len);
9652 jccb(Assembler::zero, done);
9653 lea(src, Address(src, len, Address::times_1));
9654 lea(dst, Address(dst, len, Address::times_2));
9655 negptr(len);
9656
9657 // inflate 1 char per iter
9658 bind(copy_chars_loop);
9659 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9660 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9661 increment(len);
9662 jcc(Assembler::notZero, copy_chars_loop);
9663
9664 bind(done);
9665 }
9666
9667 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
9668 switch(type) {
9669 case T_BYTE:
9670 case T_BOOLEAN:
9671 evmovdqub(dst, kmask, src, merge, vector_len);
9672 break;
9673 case T_CHAR:
9674 case T_SHORT:
9675 evmovdquw(dst, kmask, src, merge, vector_len);
9676 break;
9677 case T_INT:
9678 case T_FLOAT:
9679 evmovdqul(dst, kmask, src, merge, vector_len);
9680 break;
9681 case T_LONG:
9682 case T_DOUBLE:
9683 evmovdquq(dst, kmask, src, merge, vector_len);
9684 break;
9685 default:
9686 fatal("Unexpected type argument %s", type2name(type));
9687 break;
9688 }
9689 }
9690
9691
9692 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9693 switch(type) {
9694 case T_BYTE:
9695 case T_BOOLEAN:
9696 evmovdqub(dst, kmask, src, merge, vector_len);
9697 break;
9698 case T_CHAR:
9699 case T_SHORT:
9700 evmovdquw(dst, kmask, src, merge, vector_len);
9701 break;
9702 case T_INT:
9703 case T_FLOAT:
9704 evmovdqul(dst, kmask, src, merge, vector_len);
9705 break;
9706 case T_LONG:
9707 case T_DOUBLE:
9708 evmovdquq(dst, kmask, src, merge, vector_len);
9709 break;
9710 default:
9711 fatal("Unexpected type argument %s", type2name(type));
9712 break;
9713 }
9714 }
9715
9716 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9717 switch(type) {
9718 case T_BYTE:
9719 case T_BOOLEAN:
9720 evmovdqub(dst, kmask, src, merge, vector_len);
9721 break;
9722 case T_CHAR:
9723 case T_SHORT:
9724 evmovdquw(dst, kmask, src, merge, vector_len);
9725 break;
9726 case T_INT:
9727 case T_FLOAT:
9728 evmovdqul(dst, kmask, src, merge, vector_len);
9729 break;
9730 case T_LONG:
9731 case T_DOUBLE:
9732 evmovdquq(dst, kmask, src, merge, vector_len);
9733 break;
9734 default:
9735 fatal("Unexpected type argument %s", type2name(type));
9736 break;
9737 }
9738 }
9739
9740 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9741 switch(masklen) {
9742 case 2:
9743 knotbl(dst, src);
9744 movl(rtmp, 3);
9745 kmovbl(ktmp, rtmp);
9746 kandbl(dst, ktmp, dst);
9747 break;
9748 case 4:
9749 knotbl(dst, src);
9750 movl(rtmp, 15);
9751 kmovbl(ktmp, rtmp);
9752 kandbl(dst, ktmp, dst);
9753 break;
9754 case 8:
9755 knotbl(dst, src);
9756 break;
9757 case 16:
9758 knotwl(dst, src);
9759 break;
9760 case 32:
9761 knotdl(dst, src);
9762 break;
9763 case 64:
9764 knotql(dst, src);
9765 break;
9766 default:
9767 fatal("Unexpected vector length %d", masklen);
9768 break;
9769 }
9770 }
9771
9772 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9773 switch(type) {
9774 case T_BOOLEAN:
9775 case T_BYTE:
9776 kandbl(dst, src1, src2);
9777 break;
9778 case T_CHAR:
9779 case T_SHORT:
9780 kandwl(dst, src1, src2);
9781 break;
9782 case T_INT:
9783 case T_FLOAT:
9784 kanddl(dst, src1, src2);
9785 break;
9786 case T_LONG:
9787 case T_DOUBLE:
9788 kandql(dst, src1, src2);
9789 break;
9790 default:
9791 fatal("Unexpected type argument %s", type2name(type));
9792 break;
9793 }
9794 }
9795
9796 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9797 switch(type) {
9798 case T_BOOLEAN:
9799 case T_BYTE:
9800 korbl(dst, src1, src2);
9801 break;
9802 case T_CHAR:
9803 case T_SHORT:
9804 korwl(dst, src1, src2);
9805 break;
9806 case T_INT:
9807 case T_FLOAT:
9808 kordl(dst, src1, src2);
9809 break;
9810 case T_LONG:
9811 case T_DOUBLE:
9812 korql(dst, src1, src2);
9813 break;
9814 default:
9815 fatal("Unexpected type argument %s", type2name(type));
9816 break;
9817 }
9818 }
9819
9820 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9821 switch(type) {
9822 case T_BOOLEAN:
9823 case T_BYTE:
9824 kxorbl(dst, src1, src2);
9825 break;
9826 case T_CHAR:
9827 case T_SHORT:
9828 kxorwl(dst, src1, src2);
9829 break;
9830 case T_INT:
9831 case T_FLOAT:
9832 kxordl(dst, src1, src2);
9833 break;
9834 case T_LONG:
9835 case T_DOUBLE:
9836 kxorql(dst, src1, src2);
9837 break;
9838 default:
9839 fatal("Unexpected type argument %s", type2name(type));
9840 break;
9841 }
9842 }
9843
9844 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9845 switch(type) {
9846 case T_BOOLEAN:
9847 case T_BYTE:
9848 evpermb(dst, mask, nds, src, merge, vector_len); break;
9849 case T_CHAR:
9850 case T_SHORT:
9851 evpermw(dst, mask, nds, src, merge, vector_len); break;
9852 case T_INT:
9853 case T_FLOAT:
9854 evpermd(dst, mask, nds, src, merge, vector_len); break;
9855 case T_LONG:
9856 case T_DOUBLE:
9857 evpermq(dst, mask, nds, src, merge, vector_len); break;
9858 default:
9859 fatal("Unexpected type argument %s", type2name(type)); break;
9860 }
9861 }
9862
9863 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9864 switch(type) {
9865 case T_BOOLEAN:
9866 case T_BYTE:
9867 evpermb(dst, mask, nds, src, merge, vector_len); break;
9868 case T_CHAR:
9869 case T_SHORT:
9870 evpermw(dst, mask, nds, src, merge, vector_len); break;
9871 case T_INT:
9872 case T_FLOAT:
9873 evpermd(dst, mask, nds, src, merge, vector_len); break;
9874 case T_LONG:
9875 case T_DOUBLE:
9876 evpermq(dst, mask, nds, src, merge, vector_len); break;
9877 default:
9878 fatal("Unexpected type argument %s", type2name(type)); break;
9879 }
9880 }
9881
9882 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9883 switch(type) {
9884 case T_BYTE:
9885 evpminub(dst, mask, nds, src, merge, vector_len); break;
9886 case T_SHORT:
9887 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9888 case T_INT:
9889 evpminud(dst, mask, nds, src, merge, vector_len); break;
9890 case T_LONG:
9891 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9892 default:
9893 fatal("Unexpected type argument %s", type2name(type)); break;
9894 }
9895 }
9896
9897 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9898 switch(type) {
9899 case T_BYTE:
9900 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9901 case T_SHORT:
9902 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9903 case T_INT:
9904 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9905 case T_LONG:
9906 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9907 default:
9908 fatal("Unexpected type argument %s", type2name(type)); break;
9909 }
9910 }
9911
9912 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9913 switch(type) {
9914 case T_BYTE:
9915 evpminub(dst, mask, nds, src, merge, vector_len); break;
9916 case T_SHORT:
9917 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9918 case T_INT:
9919 evpminud(dst, mask, nds, src, merge, vector_len); break;
9920 case T_LONG:
9921 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9922 default:
9923 fatal("Unexpected type argument %s", type2name(type)); break;
9924 }
9925 }
9926
9927 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9928 switch(type) {
9929 case T_BYTE:
9930 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9931 case T_SHORT:
9932 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9933 case T_INT:
9934 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9935 case T_LONG:
9936 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9937 default:
9938 fatal("Unexpected type argument %s", type2name(type)); break;
9939 }
9940 }
9941
9942 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9943 switch(type) {
9944 case T_BYTE:
9945 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9946 case T_SHORT:
9947 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9948 case T_INT:
9949 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9950 case T_LONG:
9951 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9952 default:
9953 fatal("Unexpected type argument %s", type2name(type)); break;
9954 }
9955 }
9956
9957 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9958 switch(type) {
9959 case T_BYTE:
9960 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9961 case T_SHORT:
9962 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9963 case T_INT:
9964 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9965 case T_LONG:
9966 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9967 default:
9968 fatal("Unexpected type argument %s", type2name(type)); break;
9969 }
9970 }
9971
9972 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9973 switch(type) {
9974 case T_BYTE:
9975 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9976 case T_SHORT:
9977 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9978 case T_INT:
9979 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9980 case T_LONG:
9981 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9982 default:
9983 fatal("Unexpected type argument %s", type2name(type)); break;
9984 }
9985 }
9986
9987 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9988 switch(type) {
9989 case T_BYTE:
9990 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9991 case T_SHORT:
9992 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9993 case T_INT:
9994 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9995 case T_LONG:
9996 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9997 default:
9998 fatal("Unexpected type argument %s", type2name(type)); break;
9999 }
10000 }
10001
10002 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10003 switch(type) {
10004 case T_INT:
10005 evpxord(dst, mask, nds, src, merge, vector_len); break;
10006 case T_LONG:
10007 evpxorq(dst, mask, nds, src, merge, vector_len); break;
10008 default:
10009 fatal("Unexpected type argument %s", type2name(type)); break;
10010 }
10011 }
10012
10013 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10014 switch(type) {
10015 case T_INT:
10016 evpxord(dst, mask, nds, src, merge, vector_len); break;
10017 case T_LONG:
10018 evpxorq(dst, mask, nds, src, merge, vector_len); break;
10019 default:
10020 fatal("Unexpected type argument %s", type2name(type)); break;
10021 }
10022 }
10023
10024 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10025 switch(type) {
10026 case T_INT:
10027 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10028 case T_LONG:
10029 evporq(dst, mask, nds, src, merge, vector_len); break;
10030 default:
10031 fatal("Unexpected type argument %s", type2name(type)); break;
10032 }
10033 }
10034
10035 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10036 switch(type) {
10037 case T_INT:
10038 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10039 case T_LONG:
10040 evporq(dst, mask, nds, src, merge, vector_len); break;
10041 default:
10042 fatal("Unexpected type argument %s", type2name(type)); break;
10043 }
10044 }
10045
10046 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10047 switch(type) {
10048 case T_INT:
10049 evpandd(dst, mask, nds, src, merge, vector_len); break;
10050 case T_LONG:
10051 evpandq(dst, mask, nds, src, merge, vector_len); break;
10052 default:
10053 fatal("Unexpected type argument %s", type2name(type)); break;
10054 }
10055 }
10056
10057 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10058 switch(type) {
10059 case T_INT:
10060 evpandd(dst, mask, nds, src, merge, vector_len); break;
10061 case T_LONG:
10062 evpandq(dst, mask, nds, src, merge, vector_len); break;
10063 default:
10064 fatal("Unexpected type argument %s", type2name(type)); break;
10065 }
10066 }
10067
10068 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
10069 switch(masklen) {
10070 case 8:
10071 kortestbl(src1, src2);
10072 break;
10073 case 16:
10074 kortestwl(src1, src2);
10075 break;
10076 case 32:
10077 kortestdl(src1, src2);
10078 break;
10079 case 64:
10080 kortestql(src1, src2);
10081 break;
10082 default:
10083 fatal("Unexpected mask length %d", masklen);
10084 break;
10085 }
10086 }
10087
10088
10089 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
10090 switch(masklen) {
10091 case 8:
10092 ktestbl(src1, src2);
10093 break;
10094 case 16:
10095 ktestwl(src1, src2);
10096 break;
10097 case 32:
10098 ktestdl(src1, src2);
10099 break;
10100 case 64:
10101 ktestql(src1, src2);
10102 break;
10103 default:
10104 fatal("Unexpected mask length %d", masklen);
10105 break;
10106 }
10107 }
10108
10109 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10110 switch(type) {
10111 case T_INT:
10112 evprold(dst, mask, src, shift, merge, vlen_enc); break;
10113 case T_LONG:
10114 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
10115 default:
10116 fatal("Unexpected type argument %s", type2name(type)); break;
10117 break;
10118 }
10119 }
10120
10121 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10122 switch(type) {
10123 case T_INT:
10124 evprord(dst, mask, src, shift, merge, vlen_enc); break;
10125 case T_LONG:
10126 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
10127 default:
10128 fatal("Unexpected type argument %s", type2name(type)); break;
10129 }
10130 }
10131
10132 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10133 switch(type) {
10134 case T_INT:
10135 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
10136 case T_LONG:
10137 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
10138 default:
10139 fatal("Unexpected type argument %s", type2name(type)); break;
10140 }
10141 }
10142
10143 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10144 switch(type) {
10145 case T_INT:
10146 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
10147 case T_LONG:
10148 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
10149 default:
10150 fatal("Unexpected type argument %s", type2name(type)); break;
10151 }
10152 }
10153
10154 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10155 assert(rscratch != noreg || always_reachable(src), "missing");
10156
10157 if (reachable(src)) {
10158 evpandq(dst, nds, as_Address(src), vector_len);
10159 } else {
10160 lea(rscratch, src);
10161 evpandq(dst, nds, Address(rscratch, 0), vector_len);
10162 }
10163 }
10164
10165 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
10166 assert(rscratch != noreg || always_reachable(src), "missing");
10167
10168 if (reachable(src)) {
10169 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
10170 } else {
10171 lea(rscratch, src);
10172 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
10173 }
10174 }
10175
10176 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10177 assert(rscratch != noreg || always_reachable(src), "missing");
10178
10179 if (reachable(src)) {
10180 evporq(dst, nds, as_Address(src), vector_len);
10181 } else {
10182 lea(rscratch, src);
10183 evporq(dst, nds, Address(rscratch, 0), vector_len);
10184 }
10185 }
10186
10187 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10188 assert(rscratch != noreg || always_reachable(src), "missing");
10189
10190 if (reachable(src)) {
10191 vpshufb(dst, nds, as_Address(src), vector_len);
10192 } else {
10193 lea(rscratch, src);
10194 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
10195 }
10196 }
10197
10198 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10199 assert(rscratch != noreg || always_reachable(src), "missing");
10200
10201 if (reachable(src)) {
10202 Assembler::vpor(dst, nds, as_Address(src), vector_len);
10203 } else {
10204 lea(rscratch, src);
10205 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
10206 }
10207 }
10208
10209 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
10210 assert(rscratch != noreg || always_reachable(src3), "missing");
10211
10212 if (reachable(src3)) {
10213 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
10214 } else {
10215 lea(rscratch, src3);
10216 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
10217 }
10218 }
10219
10220 #if COMPILER2_OR_JVMCI
10221
10222 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
10223 Register length, Register temp, int vec_enc) {
10224 // Computing mask for predicated vector store.
10225 movptr(temp, -1);
10226 bzhiq(temp, temp, length);
10227 kmov(mask, temp);
10228 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
10229 }
10230
10231 // Set memory operation for length "less than" 64 bytes.
10232 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
10233 XMMRegister xmm, KRegister mask, Register length,
10234 Register temp, bool use64byteVector) {
10235 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10236 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10237 if (!use64byteVector) {
10238 fill32(dst, disp, xmm);
10239 subptr(length, 32 >> shift);
10240 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
10241 } else {
10242 assert(MaxVectorSize == 64, "vector length != 64");
10243 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
10244 }
10245 }
10246
10247
10248 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
10249 XMMRegister xmm, KRegister mask, Register length,
10250 Register temp) {
10251 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10252 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10253 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
10254 }
10255
10256
10257 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
10258 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10259 vmovdqu(dst, xmm);
10260 }
10261
10262 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
10263 fill32(Address(dst, disp), xmm);
10264 }
10265
10266 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
10267 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10268 if (!use64byteVector) {
10269 fill32(dst, xmm);
10270 fill32(dst.plus_disp(32), xmm);
10271 } else {
10272 evmovdquq(dst, xmm, Assembler::AVX_512bit);
10273 }
10274 }
10275
10276 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
10277 fill64(Address(dst, disp), xmm, use64byteVector);
10278 }
10279
10280 #ifdef _LP64
10281 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
10282 Register count, Register rtmp, XMMRegister xtmp) {
10283 Label L_exit;
10284 Label L_fill_start;
10285 Label L_fill_64_bytes;
10286 Label L_fill_96_bytes;
10287 Label L_fill_128_bytes;
10288 Label L_fill_128_bytes_loop;
10289 Label L_fill_128_loop_header;
10290 Label L_fill_128_bytes_loop_header;
10291 Label L_fill_128_bytes_loop_pre_header;
10292 Label L_fill_zmm_sequence;
10293
10294 int shift = -1;
10295 int avx3threshold = VM_Version::avx3_threshold();
10296 switch(type) {
10297 case T_BYTE: shift = 0;
10298 break;
10299 case T_SHORT: shift = 1;
10300 break;
10301 case T_INT: shift = 2;
10302 break;
10303 /* Uncomment when LONG fill stubs are supported.
10304 case T_LONG: shift = 3;
10305 break;
10306 */
10307 default:
10308 fatal("Unhandled type: %s\n", type2name(type));
10309 }
10310
10311 if ((avx3threshold != 0) || (MaxVectorSize == 32)) {
10312
10313 if (MaxVectorSize == 64) {
10314 cmpq(count, avx3threshold >> shift);
10315 jcc(Assembler::greater, L_fill_zmm_sequence);
10316 }
10317
10318 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
10319
10320 bind(L_fill_start);
10321
10322 cmpq(count, 32 >> shift);
10323 jccb(Assembler::greater, L_fill_64_bytes);
10324 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
10325 jmp(L_exit);
10326
10327 bind(L_fill_64_bytes);
10328 cmpq(count, 64 >> shift);
10329 jccb(Assembler::greater, L_fill_96_bytes);
10330 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10331 jmp(L_exit);
10332
10333 bind(L_fill_96_bytes);
10334 cmpq(count, 96 >> shift);
10335 jccb(Assembler::greater, L_fill_128_bytes);
10336 fill64(to, 0, xtmp);
10337 subq(count, 64 >> shift);
10338 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10339 jmp(L_exit);
10340
10341 bind(L_fill_128_bytes);
10342 cmpq(count, 128 >> shift);
10343 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10344 fill64(to, 0, xtmp);
10345 fill32(to, 64, xtmp);
10346 subq(count, 96 >> shift);
10347 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10348 jmp(L_exit);
10349
10350 bind(L_fill_128_bytes_loop_pre_header);
10351 {
10352 mov(rtmp, to);
10353 andq(rtmp, 31);
10354 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10355 negq(rtmp);
10356 addq(rtmp, 32);
10357 mov64(r8, -1L);
10358 bzhiq(r8, r8, rtmp);
10359 kmovql(k2, r8);
10360 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10361 addq(to, rtmp);
10362 shrq(rtmp, shift);
10363 subq(count, rtmp);
10364 }
10365
10366 cmpq(count, 128 >> shift);
10367 jcc(Assembler::less, L_fill_start);
10368
10369 bind(L_fill_128_bytes_loop_header);
10370 subq(count, 128 >> shift);
10371
10372 align32();
10373 bind(L_fill_128_bytes_loop);
10374 fill64(to, 0, xtmp);
10375 fill64(to, 64, xtmp);
10376 addq(to, 128);
10377 subq(count, 128 >> shift);
10378 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10379
10380 addq(count, 128 >> shift);
10381 jcc(Assembler::zero, L_exit);
10382 jmp(L_fill_start);
10383 }
10384
10385 if (MaxVectorSize == 64) {
10386 // Sequence using 64 byte ZMM register.
10387 Label L_fill_128_bytes_zmm;
10388 Label L_fill_192_bytes_zmm;
10389 Label L_fill_192_bytes_loop_zmm;
10390 Label L_fill_192_bytes_loop_header_zmm;
10391 Label L_fill_192_bytes_loop_pre_header_zmm;
10392 Label L_fill_start_zmm_sequence;
10393
10394 bind(L_fill_zmm_sequence);
10395 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10396
10397 bind(L_fill_start_zmm_sequence);
10398 cmpq(count, 64 >> shift);
10399 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10400 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10401 jmp(L_exit);
10402
10403 bind(L_fill_128_bytes_zmm);
10404 cmpq(count, 128 >> shift);
10405 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10406 fill64(to, 0, xtmp, true);
10407 subq(count, 64 >> shift);
10408 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10409 jmp(L_exit);
10410
10411 bind(L_fill_192_bytes_zmm);
10412 cmpq(count, 192 >> shift);
10413 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10414 fill64(to, 0, xtmp, true);
10415 fill64(to, 64, xtmp, true);
10416 subq(count, 128 >> shift);
10417 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10418 jmp(L_exit);
10419
10420 bind(L_fill_192_bytes_loop_pre_header_zmm);
10421 {
10422 movq(rtmp, to);
10423 andq(rtmp, 63);
10424 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10425 negq(rtmp);
10426 addq(rtmp, 64);
10427 mov64(r8, -1L);
10428 bzhiq(r8, r8, rtmp);
10429 kmovql(k2, r8);
10430 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10431 addq(to, rtmp);
10432 shrq(rtmp, shift);
10433 subq(count, rtmp);
10434 }
10435
10436 cmpq(count, 192 >> shift);
10437 jcc(Assembler::less, L_fill_start_zmm_sequence);
10438
10439 bind(L_fill_192_bytes_loop_header_zmm);
10440 subq(count, 192 >> shift);
10441
10442 align32();
10443 bind(L_fill_192_bytes_loop_zmm);
10444 fill64(to, 0, xtmp, true);
10445 fill64(to, 64, xtmp, true);
10446 fill64(to, 128, xtmp, true);
10447 addq(to, 192);
10448 subq(count, 192 >> shift);
10449 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10450
10451 addq(count, 192 >> shift);
10452 jcc(Assembler::zero, L_exit);
10453 jmp(L_fill_start_zmm_sequence);
10454 }
10455 bind(L_exit);
10456 }
10457 #endif
10458 #endif //COMPILER2_OR_JVMCI
10459
10460
10461 #ifdef _LP64
10462 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10463 Label done;
10464 cvttss2sil(dst, src);
10465 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10466 cmpl(dst, 0x80000000); // float_sign_flip
10467 jccb(Assembler::notEqual, done);
10468 subptr(rsp, 8);
10469 movflt(Address(rsp, 0), src);
10470 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10471 pop(dst);
10472 bind(done);
10473 }
10474
10475 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10476 Label done;
10477 cvttsd2sil(dst, src);
10478 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10479 cmpl(dst, 0x80000000); // float_sign_flip
10480 jccb(Assembler::notEqual, done);
10481 subptr(rsp, 8);
10482 movdbl(Address(rsp, 0), src);
10483 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10484 pop(dst);
10485 bind(done);
10486 }
10487
10488 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10489 Label done;
10490 cvttss2siq(dst, src);
10491 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10492 jccb(Assembler::notEqual, done);
10493 subptr(rsp, 8);
10494 movflt(Address(rsp, 0), src);
10495 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10496 pop(dst);
10497 bind(done);
10498 }
10499
10500 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10501 // Following code is line by line assembly translation rounding algorithm.
10502 // Please refer to java.lang.Math.round(float) algorithm for details.
10503 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10504 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10505 const int32_t FloatConsts_EXP_BIAS = 127;
10506 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10507 const int32_t MINUS_32 = 0xFFFFFFE0;
10508 Label L_special_case, L_block1, L_exit;
10509 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10510 movdl(dst, src);
10511 andl(dst, rtmp);
10512 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10513 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10514 subl(rtmp, dst);
10515 movl(rcx, rtmp);
10516 movl(dst, MINUS_32);
10517 testl(rtmp, dst);
10518 jccb(Assembler::notEqual, L_special_case);
10519 movdl(dst, src);
10520 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10521 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10522 movdl(rtmp, src);
10523 testl(rtmp, rtmp);
10524 jccb(Assembler::greaterEqual, L_block1);
10525 negl(dst);
10526 bind(L_block1);
10527 sarl(dst);
10528 addl(dst, 0x1);
10529 sarl(dst, 0x1);
10530 jmp(L_exit);
10531 bind(L_special_case);
10532 convert_f2i(dst, src);
10533 bind(L_exit);
10534 }
10535
10536 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10537 // Following code is line by line assembly translation rounding algorithm.
10538 // Please refer to java.lang.Math.round(double) algorithm for details.
10539 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10540 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10541 const int64_t DoubleConsts_EXP_BIAS = 1023;
10542 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10543 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10544 Label L_special_case, L_block1, L_exit;
10545 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10546 movq(dst, src);
10547 andq(dst, rtmp);
10548 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10549 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10550 subq(rtmp, dst);
10551 movq(rcx, rtmp);
10552 mov64(dst, MINUS_64);
10553 testq(rtmp, dst);
10554 jccb(Assembler::notEqual, L_special_case);
10555 movq(dst, src);
10556 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10557 andq(dst, rtmp);
10558 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10559 orq(dst, rtmp);
10560 movq(rtmp, src);
10561 testq(rtmp, rtmp);
10562 jccb(Assembler::greaterEqual, L_block1);
10563 negq(dst);
10564 bind(L_block1);
10565 sarq(dst);
10566 addq(dst, 0x1);
10567 sarq(dst, 0x1);
10568 jmp(L_exit);
10569 bind(L_special_case);
10570 convert_d2l(dst, src);
10571 bind(L_exit);
10572 }
10573
10574 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10575 Label done;
10576 cvttsd2siq(dst, src);
10577 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10578 jccb(Assembler::notEqual, done);
10579 subptr(rsp, 8);
10580 movdbl(Address(rsp, 0), src);
10581 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10582 pop(dst);
10583 bind(done);
10584 }
10585
10586 void MacroAssembler::cache_wb(Address line)
10587 {
10588 // 64 bit cpus always support clflush
10589 assert(VM_Version::supports_clflush(), "clflush should be available");
10590 bool optimized = VM_Version::supports_clflushopt();
10591 bool no_evict = VM_Version::supports_clwb();
10592
10593 // prefer clwb (writeback without evict) otherwise
10594 // prefer clflushopt (potentially parallel writeback with evict)
10595 // otherwise fallback on clflush (serial writeback with evict)
10596
10597 if (optimized) {
10598 if (no_evict) {
10599 clwb(line);
10600 } else {
10601 clflushopt(line);
10602 }
10603 } else {
10604 // no need for fence when using CLFLUSH
10605 clflush(line);
10606 }
10607 }
10608
10609 void MacroAssembler::cache_wbsync(bool is_pre)
10610 {
10611 assert(VM_Version::supports_clflush(), "clflush should be available");
10612 bool optimized = VM_Version::supports_clflushopt();
10613 bool no_evict = VM_Version::supports_clwb();
10614
10615 // pick the correct implementation
10616
10617 if (!is_pre && (optimized || no_evict)) {
10618 // need an sfence for post flush when using clflushopt or clwb
10619 // otherwise no no need for any synchroniaztion
10620
10621 sfence();
10622 }
10623 }
10624
10625 #endif // _LP64
10626
10627 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10628 switch (cond) {
10629 // Note some conditions are synonyms for others
10630 case Assembler::zero: return Assembler::notZero;
10631 case Assembler::notZero: return Assembler::zero;
10632 case Assembler::less: return Assembler::greaterEqual;
10633 case Assembler::lessEqual: return Assembler::greater;
10634 case Assembler::greater: return Assembler::lessEqual;
10635 case Assembler::greaterEqual: return Assembler::less;
10636 case Assembler::below: return Assembler::aboveEqual;
10637 case Assembler::belowEqual: return Assembler::above;
10638 case Assembler::above: return Assembler::belowEqual;
10639 case Assembler::aboveEqual: return Assembler::below;
10640 case Assembler::overflow: return Assembler::noOverflow;
10641 case Assembler::noOverflow: return Assembler::overflow;
10642 case Assembler::negative: return Assembler::positive;
10643 case Assembler::positive: return Assembler::negative;
10644 case Assembler::parity: return Assembler::noParity;
10645 case Assembler::noParity: return Assembler::parity;
10646 }
10647 ShouldNotReachHere(); return Assembler::overflow;
10648 }
10649
10650 // This is simply a call to Thread::current()
10651 void MacroAssembler::get_thread(Register thread) {
10652 if (thread != rax) {
10653 push(rax);
10654 }
10655 LP64_ONLY(push(rdi);)
10656 LP64_ONLY(push(rsi);)
10657 push(rdx);
10658 push(rcx);
10659 #ifdef _LP64
10660 push(r8);
10661 push(r9);
10662 push(r10);
10663 push(r11);
10664 #endif
10665
10666 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10667
10668 #ifdef _LP64
10669 pop(r11);
10670 pop(r10);
10671 pop(r9);
10672 pop(r8);
10673 #endif
10674 pop(rcx);
10675 pop(rdx);
10676 LP64_ONLY(pop(rsi);)
10677 LP64_ONLY(pop(rdi);)
10678 if (thread != rax) {
10679 mov(thread, rax);
10680 pop(rax);
10681 }
10682 }
10683
10684 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10685 Label L_stack_ok;
10686 if (bias == 0) {
10687 testptr(sp, 2 * wordSize - 1);
10688 } else {
10689 // lea(tmp, Address(rsp, bias);
10690 mov(tmp, sp);
10691 addptr(tmp, bias);
10692 testptr(tmp, 2 * wordSize - 1);
10693 }
10694 jcc(Assembler::equal, L_stack_ok);
10695 block_comment(msg);
10696 stop(msg);
10697 bind(L_stack_ok);
10698 }
10699
10700 // Implements lightweight-locking.
10701 //
10702 // obj: the object to be locked
10703 // reg_rax: rax
10704 // thread: the thread which attempts to lock obj
10705 // tmp: a temporary register
10706 void MacroAssembler::lightweight_lock(Register basic_lock, Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10707 assert(reg_rax == rax, "");
10708 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10709
10710 Label push;
10711 const Register top = tmp;
10712
10713 // Preload the markWord. It is important that this is the first
10714 // instruction emitted as it is part of C1's null check semantics.
10715 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10716
10717 if (UseObjectMonitorTable) {
10718 // Clear cache in case fast locking succeeds.
10719 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10720 }
10721
10722 // Load top.
10723 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10724
10725 // Check if the lock-stack is full.
10726 cmpl(top, LockStack::end_offset());
10727 jcc(Assembler::greaterEqual, slow);
10728
10729 // Check for recursion.
10730 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10731 jcc(Assembler::equal, push);
10732
10733 // Check header for monitor (0b10).
10734 testptr(reg_rax, markWord::monitor_value);
10735 jcc(Assembler::notZero, slow);
10736
10737 // Try to lock. Transition lock bits 0b01 => 0b00
10738 movptr(tmp, reg_rax);
10739 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10740 orptr(reg_rax, markWord::unlocked_value);
10741 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10742 jcc(Assembler::notEqual, slow);
10743
10744 // Restore top, CAS clobbers register.
10745 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10746
10747 bind(push);
10748 // After successful lock, push object on lock-stack.
10749 movptr(Address(thread, top), obj);
10750 incrementl(top, oopSize);
10751 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10752 }
10753
10754 // Implements lightweight-unlocking.
10755 //
10756 // obj: the object to be unlocked
10757 // reg_rax: rax
10758 // thread: the thread
10759 // tmp: a temporary register
10760 void MacroAssembler::lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10761 assert(reg_rax == rax, "");
10762 assert_different_registers(obj, reg_rax, thread, tmp);
10763
10764 Label unlocked, push_and_slow;
10765 const Register top = tmp;
10766
10767 // Check if obj is top of lock-stack.
10768 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10769 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10770 jcc(Assembler::notEqual, slow);
10771
10772 // Pop lock-stack.
10773 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10774 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10775
10776 // Check if recursive.
10777 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10778 jcc(Assembler::equal, unlocked);
10779
10780 // Not recursive. Check header for monitor (0b10).
10781 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10782 testptr(reg_rax, markWord::monitor_value);
10783 jcc(Assembler::notZero, push_and_slow);
10784
10785 #ifdef ASSERT
10786 // Check header not unlocked (0b01).
10787 Label not_unlocked;
10788 testptr(reg_rax, markWord::unlocked_value);
10789 jcc(Assembler::zero, not_unlocked);
10790 stop("lightweight_unlock already unlocked");
10791 bind(not_unlocked);
10792 #endif
10793
10794 // Try to unlock. Transition lock bits 0b00 => 0b01
10795 movptr(tmp, reg_rax);
10796 orptr(tmp, markWord::unlocked_value);
10797 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10798 jcc(Assembler::equal, unlocked);
10799
10800 bind(push_and_slow);
10801 // Restore lock-stack and handle the unlock in runtime.
10802 #ifdef ASSERT
10803 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10804 movptr(Address(thread, top), obj);
10805 #endif
10806 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10807 jmp(slow);
10808
10809 bind(unlocked);
10810 }
10811
10812 #ifdef _LP64
10813 // Saves legacy GPRs state on stack.
10814 void MacroAssembler::save_legacy_gprs() {
10815 subq(rsp, 16 * wordSize);
10816 movq(Address(rsp, 15 * wordSize), rax);
10817 movq(Address(rsp, 14 * wordSize), rcx);
10818 movq(Address(rsp, 13 * wordSize), rdx);
10819 movq(Address(rsp, 12 * wordSize), rbx);
10820 movq(Address(rsp, 10 * wordSize), rbp);
10821 movq(Address(rsp, 9 * wordSize), rsi);
10822 movq(Address(rsp, 8 * wordSize), rdi);
10823 movq(Address(rsp, 7 * wordSize), r8);
10824 movq(Address(rsp, 6 * wordSize), r9);
10825 movq(Address(rsp, 5 * wordSize), r10);
10826 movq(Address(rsp, 4 * wordSize), r11);
10827 movq(Address(rsp, 3 * wordSize), r12);
10828 movq(Address(rsp, 2 * wordSize), r13);
10829 movq(Address(rsp, wordSize), r14);
10830 movq(Address(rsp, 0), r15);
10831 }
10832
10833 // Resotres back legacy GPRs state from stack.
10834 void MacroAssembler::restore_legacy_gprs() {
10835 movq(r15, Address(rsp, 0));
10836 movq(r14, Address(rsp, wordSize));
10837 movq(r13, Address(rsp, 2 * wordSize));
10838 movq(r12, Address(rsp, 3 * wordSize));
10839 movq(r11, Address(rsp, 4 * wordSize));
10840 movq(r10, Address(rsp, 5 * wordSize));
10841 movq(r9, Address(rsp, 6 * wordSize));
10842 movq(r8, Address(rsp, 7 * wordSize));
10843 movq(rdi, Address(rsp, 8 * wordSize));
10844 movq(rsi, Address(rsp, 9 * wordSize));
10845 movq(rbp, Address(rsp, 10 * wordSize));
10846 movq(rbx, Address(rsp, 12 * wordSize));
10847 movq(rdx, Address(rsp, 13 * wordSize));
10848 movq(rcx, Address(rsp, 14 * wordSize));
10849 movq(rax, Address(rsp, 15 * wordSize));
10850 addq(rsp, 16 * wordSize);
10851 }
10852
10853 void MacroAssembler::load_aotrc_address(Register reg, address a) {
10854 #if INCLUDE_CDS
10855 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
10856 if (SCCache::is_on_for_write()) {
10857 // all aotrc field addresses should be registered in the SCC address table
10858 lea(reg, ExternalAddress(a));
10859 } else {
10860 mov64(reg, (uint64_t)a);
10861 }
10862 #else
10863 ShouldNotReachHere();
10864 #endif
10865 }
10866
10867 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10868 if (VM_Version::supports_apx_f()) {
10869 esetzucc(comparison, dst);
10870 } else {
10871 setb(comparison, dst);
10872 movzbl(dst, dst);
10873 }
10874 }
10875
10876 #endif