1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_VERSION_X86_HPP
26 #define CPU_X86_VM_VERSION_X86_HPP
27
28 #include "runtime/abstract_vm_version.hpp"
29 #include "utilities/debug.hpp"
30 #include "utilities/macros.hpp"
31 #include "utilities/sizes.hpp"
32
33 class VM_Version : public Abstract_VM_Version {
34 friend class VMStructs;
35 friend class JVMCIVMStructs;
36
37 public:
38 // cpuid result register layouts. These are all unions of a uint32_t
39 // (in case anyone wants access to the register as a whole) and a bitfield.
40
41 union StdCpuid1Eax {
42 uint32_t value;
43 struct {
44 uint32_t stepping : 4,
45 model : 4,
46 family : 4,
47 proc_type : 2,
48 : 2,
49 ext_model : 4,
50 ext_family : 8,
51 : 4;
52 } bits;
53 };
54
55 union StdCpuid1Ebx { // example, unused
56 uint32_t value;
57 struct {
58 uint32_t brand_id : 8,
59 clflush_size : 8,
60 threads_per_cpu : 8,
61 apic_id : 8;
62 } bits;
63 };
64
65 union StdCpuid1Ecx {
66 uint32_t value;
67 struct {
68 uint32_t sse3 : 1,
69 clmul : 1,
70 : 1,
71 monitor : 1,
72 : 1,
73 vmx : 1,
74 : 1,
75 est : 1,
76 : 1,
77 ssse3 : 1,
78 cid : 1,
79 : 1,
80 fma : 1,
81 cmpxchg16: 1,
82 : 4,
83 dca : 1,
84 sse4_1 : 1,
85 sse4_2 : 1,
86 : 2,
87 popcnt : 1,
88 : 1,
89 aes : 1,
90 : 1,
91 osxsave : 1,
92 avx : 1,
93 f16c : 1,
94 : 1,
95 hv : 1;
96 } bits;
97 };
98
99 union StdCpuid1Edx {
100 uint32_t value;
101 struct {
102 uint32_t : 4,
103 tsc : 1,
104 : 3,
105 cmpxchg8 : 1,
106 : 6,
107 cmov : 1,
108 : 3,
109 clflush : 1,
110 : 3,
111 mmx : 1,
112 fxsr : 1,
113 sse : 1,
114 sse2 : 1,
115 : 1,
116 ht : 1,
117 : 3;
118 } bits;
119 };
120
121 union DcpCpuid4Eax {
122 uint32_t value;
123 struct {
124 uint32_t cache_type : 5,
125 : 21,
126 cores_per_cpu : 6;
127 } bits;
128 };
129
130 union DcpCpuid4Ebx {
131 uint32_t value;
132 struct {
133 uint32_t L1_line_size : 12,
134 partitions : 10,
135 associativity : 10;
136 } bits;
137 };
138
139 union TplCpuidBEbx {
140 uint32_t value;
141 struct {
142 uint32_t logical_cpus : 16,
143 : 16;
144 } bits;
145 };
146
147 union ExtCpuid1Ecx {
148 uint32_t value;
149 struct {
150 uint32_t LahfSahf : 1,
151 CmpLegacy : 1,
152 : 3,
153 lzcnt : 1,
154 sse4a : 1,
155 misalignsse : 1,
156 prefetchw : 1,
157 : 23;
158 } bits;
159 };
160
161 union ExtCpuid1Edx {
162 uint32_t value;
163 struct {
164 uint32_t : 22,
165 mmx_amd : 1,
166 mmx : 1,
167 fxsr : 1,
168 fxsr_opt : 1,
169 pdpe1gb : 1,
170 rdtscp : 1,
171 : 1,
172 long_mode : 1,
173 tdnow2 : 1,
174 tdnow : 1;
175 } bits;
176 };
177
178 union ExtCpuid5Ex {
179 uint32_t value;
180 struct {
181 uint32_t L1_line_size : 8,
182 L1_tag_lines : 8,
183 L1_assoc : 8,
184 L1_size : 8;
185 } bits;
186 };
187
188 union ExtCpuid7Edx {
189 uint32_t value;
190 struct {
191 uint32_t : 8,
192 tsc_invariance : 1,
193 : 23;
194 } bits;
195 };
196
197 union ExtCpuid8Ecx {
198 uint32_t value;
199 struct {
200 uint32_t cores_per_cpu : 8,
201 : 24;
202 } bits;
203 };
204
205 union SefCpuid7Eax {
206 uint32_t value;
207 };
208
209 union SefCpuid7Ebx {
210 uint32_t value;
211 struct {
212 uint32_t fsgsbase : 1,
213 : 2,
214 bmi1 : 1,
215 : 1,
216 avx2 : 1,
217 : 2,
218 bmi2 : 1,
219 erms : 1,
220 : 1,
221 rtm : 1,
222 : 4,
223 avx512f : 1,
224 avx512dq : 1,
225 : 1,
226 adx : 1,
227 : 1,
228 avx512ifma : 1,
229 : 1,
230 clflushopt : 1,
231 clwb : 1,
232 : 1,
233 avx512pf : 1,
234 avx512er : 1,
235 avx512cd : 1,
236 sha : 1,
237 avx512bw : 1,
238 avx512vl : 1;
239 } bits;
240 };
241
242 union SefCpuid7Ecx {
243 uint32_t value;
244 struct {
245 uint32_t prefetchwt1 : 1,
246 avx512_vbmi : 1,
247 umip : 1,
248 pku : 1,
249 ospke : 1,
250 : 1,
251 avx512_vbmi2 : 1,
252 cet_ss : 1,
253 gfni : 1,
254 vaes : 1,
255 avx512_vpclmulqdq : 1,
256 avx512_vnni : 1,
257 avx512_bitalg : 1,
258 : 1,
259 avx512_vpopcntdq : 1,
260 : 1,
261 : 1,
262 mawau : 5,
263 rdpid : 1,
264 : 9;
265 } bits;
266 };
267
268 union SefCpuid7Edx {
269 uint32_t value;
270 struct {
271 uint32_t : 2,
272 avx512_4vnniw : 1,
273 avx512_4fmaps : 1,
274 fast_short_rep_mov : 1,
275 : 9,
276 serialize : 1,
277 : 5,
278 cet_ibt : 1,
279 : 2,
280 avx512_fp16 : 1,
281 : 8;
282 } bits;
283 };
284
285 union SefCpuid7SubLeaf1Eax {
286 uint32_t value;
287 struct {
288 uint32_t sha512 : 1,
289 : 22,
290 avx_ifma : 1,
291 : 8;
292 } bits;
293 };
294
295 union SefCpuid7SubLeaf1Edx {
296 uint32_t value;
297 struct {
298 uint32_t : 19,
299 avx10 : 1,
300 : 1,
301 apx_f : 1,
302 : 10;
303 } bits;
304 };
305
306 union StdCpuid24MainLeafEax {
307 uint32_t value;
308 struct {
309 uint32_t sub_leaves_cnt : 31;
310 } bits;
311 };
312
313 union StdCpuid24MainLeafEbx {
314 uint32_t value;
315 struct {
316 uint32_t avx10_converged_isa_version : 8,
317 : 8,
318 : 2,
319 avx10_vlen_512 : 1,
320 : 13;
321 } bits;
322 };
323
324 union ExtCpuid1EEbx {
325 uint32_t value;
326 struct {
327 uint32_t : 8,
328 threads_per_core : 8,
329 : 16;
330 } bits;
331 };
332
333 union XemXcr0Eax {
334 uint32_t value;
335 struct {
336 uint32_t x87 : 1,
337 sse : 1,
338 ymm : 1,
339 bndregs : 1,
340 bndcsr : 1,
341 opmask : 1,
342 zmm512 : 1,
343 zmm32 : 1,
344 : 11,
345 apx_f : 1,
346 : 12;
347 } bits;
348 };
349
350 protected:
351 static int _cpu;
352 static int _model;
353 static int _stepping;
354
355 static bool _has_intel_jcc_erratum;
356
357 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
358 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
359 static address _cpuinfo_segv_addr_apx; // address of instruction which causes APX specific SEGV
360 static address _cpuinfo_cont_addr_apx; // address of instruction after the one which causes APX specific SEGV
361
362 /*
363 * Update following files when declaring new flags:
364 * test/lib-test/jdk/test/whitebox/CPUInfoTest.java
365 * src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/amd64/AMD64.java
366 */
367 enum Feature_Flag {
368 #define CPU_FEATURE_FLAGS(decl) \
369 decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \
370 decl(CMOV, "cmov", 1) \
371 decl(FXSR, "fxsr", 2) \
372 decl(HT, "ht", 3) \
373 \
374 decl(MMX, "mmx", 4) \
375 decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
376 /* may not necessarily support other 3dnow instructions */ \
377 decl(SSE, "sse", 6) \
378 decl(SSE2, "sse2", 7) \
379 \
380 decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
381 decl(SSSE3, "ssse3", 9 ) \
382 decl(SSE4A, "sse4a", 10) \
383 decl(SSE4_1, "sse4.1", 11) \
384 \
385 decl(SSE4_2, "sse4.2", 12) \
386 decl(POPCNT, "popcnt", 13) \
387 decl(LZCNT, "lzcnt", 14) \
388 decl(TSC, "tsc", 15) \
389 \
390 decl(TSCINV_BIT, "tscinvbit", 16) \
391 decl(TSCINV, "tscinv", 17) \
392 decl(AVX, "avx", 18) \
393 decl(AVX2, "avx2", 19) \
394 \
395 decl(AES, "aes", 20) \
396 decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \
397 decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \
398 decl(BMI1, "bmi1", 23) \
399 \
400 decl(BMI2, "bmi2", 24) \
401 decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \
402 decl(ADX, "adx", 26) \
403 decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \
404 \
405 decl(AVX512DQ, "avx512dq", 28) \
406 decl(AVX512PF, "avx512pf", 29) \
407 decl(AVX512ER, "avx512er", 30) \
408 decl(AVX512CD, "avx512cd", 31) \
409 \
410 decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \
411 decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \
412 decl(SHA, "sha", 34) /* SHA instructions */ \
413 decl(FMA, "fma", 35) /* FMA instructions */ \
414 \
415 decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \
416 decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \
417 decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \
418 decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \
419 \
420 decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \
421 decl(FLUSH, "clflush", 41) /* flush instruction */ \
422 decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \
423 decl(CLWB, "clwb", 43) /* clwb instruction */ \
424 \
425 decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \
426 decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \
427 decl(HV, "hv", 46) /* Hypervisor instructions */ \
428 decl(SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \
429 decl(RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \
430 decl(RDPID, "rdpid", 49) /* RDPID instruction */ \
431 decl(FSRM, "fsrm", 50) /* Fast Short REP MOV */ \
432 decl(GFNI, "gfni", 51) /* Vector GFNI instructions */ \
433 decl(AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\
434 decl(F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \
435 decl(PKU, "pku", 54) /* Protection keys for user-mode pages */ \
436 decl(OSPKE, "ospke", 55) /* OS enables protection keys */ \
437 decl(CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \
438 decl(CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \
439 decl(AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/ \
440 decl(AVX_IFMA, "avx_ifma", 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \
441 decl(APX_F, "apx_f", 60) /* Intel Advanced Performance Extensions*/ \
442 decl(SHA512, "sha512", 61) /* SHA512 instructions*/ \
443 decl(AVX512_FP16, "avx512_fp16", 62) /* AVX512 FP16 ISA support*/ \
444 decl(AVX10_1, "avx10_1", 63) /* AVX10 512 bit vector ISA Version 1 support*/ \
445 decl(AVX10_2, "avx10_2", 64) /* AVX10 512 bit vector ISA Version 2 support*/
446
447 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit),
448 CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
449 #undef DECLARE_CPU_FEATURE_FLAG
450 MAX_CPU_FEATURES
451 };
452
453 class VM_Features {
454 friend class VMStructs;
455 friend class JVMCIVMStructs;
456
457 private:
458 uint64_t _features_bitmap[(MAX_CPU_FEATURES / BitsPerLong) + 1];
459
460 STATIC_ASSERT(sizeof(_features_bitmap) * BitsPerByte >= MAX_CPU_FEATURES);
461
462 // Number of 8-byte elements in _bitmap.
463 constexpr static int features_bitmap_element_count() {
464 return sizeof(_features_bitmap) / sizeof(uint64_t);
465 }
466
467 constexpr static int features_bitmap_element_shift_count() {
468 return LogBitsPerLong;
469 }
470
471 constexpr static uint64_t features_bitmap_element_mask() {
472 return (1ULL << features_bitmap_element_shift_count()) - 1;
473 }
474
475 static int index(Feature_Flag feature) {
476 int idx = feature >> features_bitmap_element_shift_count();
477 assert(idx < features_bitmap_element_count(), "Features array index out of bounds");
478 return idx;
479 }
480
481 static uint64_t bit_mask(Feature_Flag feature) {
482 return (1ULL << (feature & features_bitmap_element_mask()));
483 }
484
485 static int _features_bitmap_size; // for JVMCI purposes
486 public:
487 VM_Features() {
488 for (int i = 0; i < features_bitmap_element_count(); i++) {
489 _features_bitmap[i] = 0;
490 }
491 }
492
493 void set_feature(Feature_Flag feature) {
494 int idx = index(feature);
495 _features_bitmap[idx] |= bit_mask(feature);
496 }
497
498 void clear_feature(VM_Version::Feature_Flag feature) {
499 int idx = index(feature);
500 _features_bitmap[idx] &= ~bit_mask(feature);
501 }
502
503 bool supports_feature(VM_Version::Feature_Flag feature) {
504 int idx = index(feature);
505 return (_features_bitmap[idx] & bit_mask(feature)) != 0;
506 }
507 };
508
509 // CPU feature flags vector, can be affected by VM settings.
510 static VM_Features _features;
511
512 // Original CPU feature flags vector, not affected by VM settings.
513 static VM_Features _cpu_features;
514
515 static const char* _features_names[];
516
517 static void clear_cpu_features() {
518 _features = VM_Features();
519 _cpu_features = VM_Features();
520 }
521
522 enum Extended_Family {
523 // AMD
524 CPU_FAMILY_AMD_11H = 0x11,
525 CPU_FAMILY_AMD_17H = 0x17, /* Zen1 & Zen2 */
526 CPU_FAMILY_AMD_19H = 0x19, /* Zen3 & Zen4 */
527 // ZX
528 CPU_FAMILY_ZX_CORE_F6 = 6,
529 CPU_FAMILY_ZX_CORE_F7 = 7,
530 // Intel
531 CPU_FAMILY_INTEL_CORE = 6,
532 CPU_MODEL_NEHALEM = 0x1e,
533 CPU_MODEL_NEHALEM_EP = 0x1a,
534 CPU_MODEL_NEHALEM_EX = 0x2e,
535 CPU_MODEL_WESTMERE = 0x25,
536 CPU_MODEL_WESTMERE_EP = 0x2c,
537 CPU_MODEL_WESTMERE_EX = 0x2f,
538 CPU_MODEL_SANDYBRIDGE = 0x2a,
539 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
540 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
541 CPU_MODEL_HASWELL_E3 = 0x3c,
542 CPU_MODEL_HASWELL_E7 = 0x3f,
543 CPU_MODEL_BROADWELL = 0x3d,
544 CPU_MODEL_SKYLAKE = 0x55
545 };
546
547 // cpuid information block. All info derived from executing cpuid with
548 // various function numbers is stored here. Intel and AMD info is
549 // merged in this block: accessor methods disentangle it.
550 //
551 // The info block is laid out in subblocks of 4 dwords corresponding to
552 // eax, ebx, ecx and edx, whether or not they contain anything useful.
553 class CpuidInfo {
554 public:
555 // cpuid function 0
556 uint32_t std_max_function;
557 uint32_t std_vendor_name_0;
558 uint32_t std_vendor_name_1;
559 uint32_t std_vendor_name_2;
560
561 // cpuid function 1
562 StdCpuid1Eax std_cpuid1_eax;
563 StdCpuid1Ebx std_cpuid1_ebx;
564 StdCpuid1Ecx std_cpuid1_ecx;
565 StdCpuid1Edx std_cpuid1_edx;
566
567 // cpuid function 4 (deterministic cache parameters)
568 DcpCpuid4Eax dcp_cpuid4_eax;
569 DcpCpuid4Ebx dcp_cpuid4_ebx;
570 uint32_t dcp_cpuid4_ecx; // unused currently
571 uint32_t dcp_cpuid4_edx; // unused currently
572
573 // cpuid function 7 (structured extended features enumeration leaf)
574 // eax = 7, ecx = 0
575 SefCpuid7Eax sef_cpuid7_eax;
576 SefCpuid7Ebx sef_cpuid7_ebx;
577 SefCpuid7Ecx sef_cpuid7_ecx;
578 SefCpuid7Edx sef_cpuid7_edx;
579
580 // cpuid function 7 (structured extended features enumeration sub-leaf 1)
581 // eax = 7, ecx = 1
582 SefCpuid7SubLeaf1Eax sefsl1_cpuid7_eax;
583 SefCpuid7SubLeaf1Edx sefsl1_cpuid7_edx;
584
585 // cpuid function 24 converged vector ISA main leaf
586 // eax = 24, ecx = 0
587 StdCpuid24MainLeafEax std_cpuid24_eax;
588 StdCpuid24MainLeafEbx std_cpuid24_ebx;
589
590 // cpuid function 0xB (processor topology)
591 // ecx = 0
592 uint32_t tpl_cpuidB0_eax;
593 TplCpuidBEbx tpl_cpuidB0_ebx;
594 uint32_t tpl_cpuidB0_ecx; // unused currently
595 uint32_t tpl_cpuidB0_edx; // unused currently
596
597 // ecx = 1
598 uint32_t tpl_cpuidB1_eax;
599 TplCpuidBEbx tpl_cpuidB1_ebx;
600 uint32_t tpl_cpuidB1_ecx; // unused currently
601 uint32_t tpl_cpuidB1_edx; // unused currently
602
603 // ecx = 2
604 uint32_t tpl_cpuidB2_eax;
605 TplCpuidBEbx tpl_cpuidB2_ebx;
606 uint32_t tpl_cpuidB2_ecx; // unused currently
607 uint32_t tpl_cpuidB2_edx; // unused currently
608
609 // cpuid function 0x80000000 // example, unused
610 uint32_t ext_max_function;
611 uint32_t ext_vendor_name_0;
612 uint32_t ext_vendor_name_1;
613 uint32_t ext_vendor_name_2;
614
615 // cpuid function 0x80000001
616 uint32_t ext_cpuid1_eax; // reserved
617 uint32_t ext_cpuid1_ebx; // reserved
618 ExtCpuid1Ecx ext_cpuid1_ecx;
619 ExtCpuid1Edx ext_cpuid1_edx;
620
621 // cpuid functions 0x80000002 thru 0x80000004: example, unused
622 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
623 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
624 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
625
626 // cpuid function 0x80000005 // AMD L1, Intel reserved
627 uint32_t ext_cpuid5_eax; // unused currently
628 uint32_t ext_cpuid5_ebx; // reserved
629 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
630 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
631
632 // cpuid function 0x80000007
633 uint32_t ext_cpuid7_eax; // reserved
634 uint32_t ext_cpuid7_ebx; // reserved
635 uint32_t ext_cpuid7_ecx; // reserved
636 ExtCpuid7Edx ext_cpuid7_edx; // tscinv
637
638 // cpuid function 0x80000008
639 uint32_t ext_cpuid8_eax; // unused currently
640 uint32_t ext_cpuid8_ebx; // reserved
641 ExtCpuid8Ecx ext_cpuid8_ecx;
642 uint32_t ext_cpuid8_edx; // reserved
643
644 // cpuid function 0x8000001E // AMD 17h
645 uint32_t ext_cpuid1E_eax;
646 ExtCpuid1EEbx ext_cpuid1E_ebx; // threads per core (AMD17h)
647 uint32_t ext_cpuid1E_ecx;
648 uint32_t ext_cpuid1E_edx; // unused currently
649
650 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
651 XemXcr0Eax xem_xcr0_eax;
652 uint32_t xem_xcr0_edx; // reserved
653
654 // Space to save ymm registers after signal handle
655 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15
656
657 // Space to save zmm registers after signal handle
658 int zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31
659
660 // Space to save apx registers after signal handle
661 jlong apx_save[2]; // Save r16 and r31
662
663 VM_Features feature_flags() const;
664
665 // Asserts
666 void assert_is_initialized() const {
667 assert(std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
668 }
669
670 // Extractors
671 uint32_t extended_cpu_family() const {
672 uint32_t result = std_cpuid1_eax.bits.family;
673 result += std_cpuid1_eax.bits.ext_family;
674 return result;
675 }
676
677 uint32_t extended_cpu_model() const {
678 uint32_t result = std_cpuid1_eax.bits.model;
679 result |= std_cpuid1_eax.bits.ext_model << 4;
680 return result;
681 }
682
683 uint32_t cpu_stepping() const {
684 uint32_t result = std_cpuid1_eax.bits.stepping;
685 return result;
686 }
687 };
688
689 private:
690 // The actual cpuid info block
691 static CpuidInfo _cpuid_info;
692
693 // Extractors and predicates
694 static uint logical_processor_count() {
695 uint result = threads_per_core();
696 return result;
697 }
698
699 static bool compute_has_intel_jcc_erratum();
700
701 static bool os_supports_avx_vectors();
702 static bool os_supports_apx_egprs();
703 static void get_processor_features();
704
705 public:
706 // Offsets for cpuid asm stub
707 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
708 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
709 static ByteSize std_cpuid24_offset() { return byte_offset_of(CpuidInfo, std_cpuid24_eax); }
710 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
711 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
712 static ByteSize sefsl1_cpuid7_offset() { return byte_offset_of(CpuidInfo, sefsl1_cpuid7_eax); }
713 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
714 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
715 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
716 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
717 static ByteSize ext_cpuid1E_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1E_eax); }
718 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
719 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
720 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
721 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
722 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
723 static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
724 static ByteSize apx_save_offset() { return byte_offset_of(CpuidInfo, apx_save); }
725
726 // The value used to check ymm register after signal handle
727 static int ymm_test_value() { return 0xCAFEBABE; }
728 static jlong egpr_test_value() { return 0xCAFEBABECAFEBABELL; }
729
730 static void get_cpu_info_wrapper();
731 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
732 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
733 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
734 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; }
735
736 static void set_cpuinfo_segv_addr_apx(address pc) { _cpuinfo_segv_addr_apx = pc; }
737 static bool is_cpuinfo_segv_addr_apx(address pc) { return _cpuinfo_segv_addr_apx == pc; }
738 static void set_cpuinfo_cont_addr_apx(address pc) { _cpuinfo_cont_addr_apx = pc; }
739 static address cpuinfo_cont_addr_apx() { return _cpuinfo_cont_addr_apx; }
740
741 static void clear_apx_test_state();
742
743 static void clean_cpuFeatures() {
744 VM_Version::clear_cpu_features();
745 }
746 static void set_avx_cpuFeatures() {
747 _features.set_feature(CPU_SSE);
748 _features.set_feature(CPU_SSE2);
749 _features.set_feature(CPU_AVX);
750 _features.set_feature(CPU_VZEROUPPER);
751 }
752 static void set_evex_cpuFeatures() {
753 _features.set_feature(CPU_AVX10_1);
754 _features.set_feature(CPU_AVX512F);
755 _features.set_feature(CPU_SSE);
756 _features.set_feature(CPU_SSE2);
757 _features.set_feature(CPU_VZEROUPPER);
758 }
759 static void set_apx_cpuFeatures() { _features.set_feature(CPU_APX_F); }
760 static void set_bmi_cpuFeatures() {
761 _features.set_feature(CPU_BMI1);
762 _features.set_feature(CPU_BMI2);
763 _features.set_feature(CPU_LZCNT);
764 _features.set_feature(CPU_POPCNT);
765 }
766
767 // Initialization
768 static void initialize();
769
770 // Override Abstract_VM_Version implementation
771 static void print_platform_virtualization_info(outputStream*);
772
773 //
774 // Processor family:
775 // 3 - 386
776 // 4 - 486
777 // 5 - Pentium
778 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
779 // Pentium M, Core Solo, Core Duo, Core2 Duo
780 // family 6 model: 9, 13, 14, 15
781 // 0x0f - Pentium 4, Opteron
782 //
783 // Note: The cpu family should be used to select between
784 // instruction sequences which are valid on all Intel
785 // processors. Use the feature test functions below to
786 // determine whether a particular instruction is supported.
787 //
788 static void assert_is_initialized() { _cpuid_info.assert_is_initialized(); }
789 static uint32_t extended_cpu_family() { return _cpuid_info.extended_cpu_family(); }
790 static uint32_t extended_cpu_model() { return _cpuid_info.extended_cpu_model(); }
791 static uint32_t cpu_stepping() { return _cpuid_info.cpu_stepping(); }
792 static int cpu_family() { return _cpu;}
793 static bool is_P6() { return cpu_family() >= 6; }
794 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
795 static bool is_hygon() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH'
796 static bool is_amd_family() { return is_amd() || is_hygon(); }
797 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
798 static bool is_zx() { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS '
799 static bool is_atom_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton
800 static bool is_knights_family() { return UseKNLSetting || ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x57) || (extended_cpu_model() == 0x85))); } // Xeon Phi 3200/5200/7200 and Future Xeon Phi
801
802 static bool supports_processor_topology() {
803 return (_cpuid_info.std_max_function >= 0xB) &&
804 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
805 // Some cpus have max cpuid >= 0xB but do not support processor topology.
806 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
807 }
808
809 static uint cores_per_cpu();
810 static uint threads_per_core();
811 static uint L1_line_size();
812
813 static uint prefetch_data_size() {
814 return L1_line_size();
815 }
816
817 //
818 // Feature identification which can be affected by VM settings
819 //
820 static bool supports_cmov() { return _features.supports_feature(CPU_CMOV); }
821 static bool supports_fxsr() { return _features.supports_feature(CPU_FXSR); }
822 static bool supports_ht() { return _features.supports_feature(CPU_HT); }
823 static bool supports_mmx() { return _features.supports_feature(CPU_MMX); }
824 static bool supports_sse() { return _features.supports_feature(CPU_SSE); }
825 static bool supports_sse2() { return _features.supports_feature(CPU_SSE2); }
826 static bool supports_sse3() { return _features.supports_feature(CPU_SSE3); }
827 static bool supports_ssse3() { return _features.supports_feature(CPU_SSSE3); }
828 static bool supports_sse4_1() { return _features.supports_feature(CPU_SSE4_1); }
829 static bool supports_sse4_2() { return _features.supports_feature(CPU_SSE4_2); }
830 static bool supports_popcnt() { return _features.supports_feature(CPU_POPCNT); }
831 static bool supports_avx() { return _features.supports_feature(CPU_AVX); }
832 static bool supports_avx2() { return _features.supports_feature(CPU_AVX2); }
833 static bool supports_tsc() { return _features.supports_feature(CPU_TSC); }
834 static bool supports_rdtscp() { return _features.supports_feature(CPU_RDTSCP); }
835 static bool supports_rdpid() { return _features.supports_feature(CPU_RDPID); }
836 static bool supports_aes() { return _features.supports_feature(CPU_AES); }
837 static bool supports_erms() { return _features.supports_feature(CPU_ERMS); }
838 static bool supports_fsrm() { return _features.supports_feature(CPU_FSRM); }
839 static bool supports_clmul() { return _features.supports_feature(CPU_CLMUL); }
840 static bool supports_rtm() { return _features.supports_feature(CPU_RTM); }
841 static bool supports_bmi1() { return _features.supports_feature(CPU_BMI1); }
842 static bool supports_bmi2() { return _features.supports_feature(CPU_BMI2); }
843 static bool supports_adx() { return _features.supports_feature(CPU_ADX); }
844 static bool supports_evex() { return _features.supports_feature(CPU_AVX512F); }
845 static bool supports_avx512dq() { return _features.supports_feature(CPU_AVX512DQ); }
846 static bool supports_avx512ifma() { return _features.supports_feature(CPU_AVX512_IFMA); }
847 static bool supports_avxifma() { return _features.supports_feature(CPU_AVX_IFMA); }
848 static bool supports_avx512pf() { return _features.supports_feature(CPU_AVX512PF); }
849 static bool supports_avx512er() { return _features.supports_feature(CPU_AVX512ER); }
850 static bool supports_avx512cd() { return _features.supports_feature(CPU_AVX512CD); }
851 static bool supports_avx512bw() { return _features.supports_feature(CPU_AVX512BW); }
852 static bool supports_avx512vl() { return _features.supports_feature(CPU_AVX512VL); }
853 static bool supports_avx512vlbw() { return (supports_evex() && supports_avx512bw() && supports_avx512vl()); }
854 static bool supports_avx512bwdq() { return (supports_evex() && supports_avx512bw() && supports_avx512dq()); }
855 static bool supports_avx512vldq() { return (supports_evex() && supports_avx512dq() && supports_avx512vl()); }
856 static bool supports_avx512vlbwdq() { return (supports_evex() && supports_avx512vl() &&
857 supports_avx512bw() && supports_avx512dq()); }
858 static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); }
859 static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); }
860 static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); }
861 static bool supports_apx_f() { return _features.supports_feature(CPU_APX_F); }
862 static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
863 static bool supports_sha() { return _features.supports_feature(CPU_SHA); }
864 static bool supports_fma() { return _features.supports_feature(CPU_FMA) && supports_avx(); }
865 static bool supports_vzeroupper() { return _features.supports_feature(CPU_VZEROUPPER); }
866 static bool supports_avx512_vpopcntdq() { return _features.supports_feature(CPU_AVX512_VPOPCNTDQ); }
867 static bool supports_avx512_vpclmulqdq() { return _features.supports_feature(CPU_AVX512_VPCLMULQDQ); }
868 static bool supports_avx512_vaes() { return _features.supports_feature(CPU_AVX512_VAES); }
869 static bool supports_gfni() { return _features.supports_feature(CPU_GFNI); }
870 static bool supports_avx512_vnni() { return _features.supports_feature(CPU_AVX512_VNNI); }
871 static bool supports_avx512_bitalg() { return _features.supports_feature(CPU_AVX512_BITALG); }
872 static bool supports_avx512_vbmi() { return _features.supports_feature(CPU_AVX512_VBMI); }
873 static bool supports_avx512_vbmi2() { return _features.supports_feature(CPU_AVX512_VBMI2); }
874 static bool supports_avx512_fp16() { return _features.supports_feature(CPU_AVX512_FP16); }
875 static bool supports_hv() { return _features.supports_feature(CPU_HV); }
876 static bool supports_serialize() { return _features.supports_feature(CPU_SERIALIZE); }
877 static bool supports_f16c() { return _features.supports_feature(CPU_F16C); }
878 static bool supports_pku() { return _features.supports_feature(CPU_PKU); }
879 static bool supports_ospke() { return _features.supports_feature(CPU_OSPKE); }
880 static bool supports_cet_ss() { return _features.supports_feature(CPU_CET_SS); }
881 static bool supports_cet_ibt() { return _features.supports_feature(CPU_CET_IBT); }
882 static bool supports_sha512() { return _features.supports_feature(CPU_SHA512); }
883
884 // Intel® AVX10 introduces a versioned approach for enumeration that is monotonically increasing, inclusive,
885 // and supporting all vector lengths. Feature set supported by an AVX10 vector ISA version is also supported
886 // by all the versions above it.
887 static bool supports_avx10_1() { return _features.supports_feature(CPU_AVX10_1);}
888 static bool supports_avx10_2() { return _features.supports_feature(CPU_AVX10_2);}
889
890 //
891 // Feature identification not affected by VM flags
892 //
893 static bool cpu_supports_evex() { return _cpu_features.supports_feature(CPU_AVX512F); }
894
895 static bool supports_avx512_simd_sort() {
896 if (supports_avx512dq()) {
897 // Disable AVX512 version of SIMD Sort on AMD Zen4 Processors.
898 if (is_amd() && cpu_family() == CPU_FAMILY_AMD_19H) {
899 return false;
900 }
901 return true;
902 }
903 return false;
904 }
905
906 // Intel features
907 static bool is_intel_family_core() { return is_intel() &&
908 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
909
910 static bool is_intel_skylake() { return is_intel_family_core() &&
911 extended_cpu_model() == CPU_MODEL_SKYLAKE; }
912
913 #ifdef COMPILER2
914 // Determine if it's running on Cascade Lake using default options.
915 static bool is_default_intel_cascade_lake();
916 #endif
917
918 static bool is_intel_cascade_lake();
919
920 static int avx3_threshold();
921
922 static bool is_intel_tsc_synched_at_init();
923
924 static void insert_features_names(VM_Version::VM_Features features, char* buf, size_t buflen);
925
926 // This checks if the JVM is potentially affected by an erratum on Intel CPUs (SKX102)
927 // that causes unpredictable behaviour when jcc crosses 64 byte boundaries. Its microcode
928 // mitigation causes regressions when jumps or fused conditional branches cross or end at
929 // 32 byte boundaries.
930 static bool has_intel_jcc_erratum() { return _has_intel_jcc_erratum; }
931
932 // AMD features
933 static bool supports_3dnow_prefetch() { return _features.supports_feature(CPU_3DNOW_PREFETCH); }
934 static bool supports_lzcnt() { return _features.supports_feature(CPU_LZCNT); }
935 static bool supports_sse4a() { return _features.supports_feature(CPU_SSE4A); }
936
937 static bool is_amd_Barcelona() { return is_amd() &&
938 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
939
940 // Intel and AMD newer cores support fast timestamps well
941 static bool supports_tscinv_bit() {
942 return _features.supports_feature(CPU_TSCINV_BIT);
943 }
944 static bool supports_tscinv() {
945 return _features.supports_feature(CPU_TSCINV);
946 }
947
948 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
949 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 &&
950 supports_sse3() && _model != 0x1C; }
951
952 static bool supports_compare_and_exchange() { return true; }
953
954 static int allocate_prefetch_distance(bool use_watermark_prefetch);
955
956 // SSE2 and later processors implement a 'pause' instruction
957 // that can be used for efficient implementation of
958 // the intrinsic for java.lang.Thread.onSpinWait()
959 static bool supports_on_spin_wait() { return supports_sse2(); }
960
961 // x86_64 supports fast class initialization checks
962 static bool supports_fast_class_init_checks() {
963 return true;
964 }
965
966 // x86_64 supports secondary supers table
967 constexpr static bool supports_secondary_supers_table() {
968 return true;
969 }
970
971 constexpr static bool supports_stack_watermark_barrier() {
972 return true;
973 }
974
975 constexpr static bool supports_recursive_lightweight_locking() {
976 return true;
977 }
978
979 // For AVX CPUs only. f16c support is disabled if UseAVX == 0.
980 static bool supports_float16() {
981 return supports_f16c() || supports_avx512vl() || supports_avx512_fp16();
982 }
983
984 // Check intrinsic support
985 static bool is_intrinsic_supported(vmIntrinsicID id);
986
987 // there are several insns to force cache line sync to memory which
988 // we can use to ensure mapped non-volatile memory is up to date with
989 // pending in-cache changes.
990 //
991 // 64 bit cpus always support clflush which writes back and evicts
992 // on 32 bit cpus support is recorded via a feature flag
993 //
994 // clflushopt is optional and acts like clflush except it does
995 // not synchronize with other memory ops. it needs a preceding
996 // and trailing StoreStore fence
997 //
998 // clwb is an optional intel-specific instruction which
999 // writes back without evicting the line. it also does not
1000 // synchronize with other memory ops. so, it needs preceding
1001 // and trailing StoreStore fences.
1002
1003 static bool supports_clflush(); // Can't inline due to header file conflict
1004
1005 // Note: CPU_FLUSHOPT and CPU_CLWB bits should always be zero for 32-bit
1006 static bool supports_clflushopt() { return (_features.supports_feature(CPU_FLUSHOPT)); }
1007 static bool supports_clwb() { return (_features.supports_feature(CPU_CLWB)); }
1008
1009 // Old CPUs perform lea on AGU which causes additional latency transferring the
1010 // value from/to ALU for other operations
1011 static bool supports_fast_2op_lea() {
1012 return (is_intel() && supports_avx()) || // Sandy Bridge and above
1013 (is_amd() && supports_avx()); // Jaguar and Bulldozer and above
1014 }
1015
1016 // Pre Icelake Intels suffer inefficiency regarding 3-operand lea, which contains
1017 // all of base register, index register and displacement immediate, with 3 latency.
1018 // Note that when the address contains no displacement but the base register is
1019 // rbp or r13, the machine code must contain a zero displacement immediate,
1020 // effectively transform a 2-operand lea into a 3-operand lea. This can be
1021 // replaced by add-add or lea-add
1022 static bool supports_fast_3op_lea() {
1023 return supports_fast_2op_lea() &&
1024 ((is_intel() && supports_clwb() && !is_intel_skylake()) || // Icelake and above
1025 is_amd());
1026 }
1027
1028 #ifdef __APPLE__
1029 // Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64)
1030 static bool is_cpu_emulated();
1031 #endif
1032
1033 // support functions for virtualization detection
1034 private:
1035 static void check_virtualizations();
1036
1037 static const char* cpu_family_description(void);
1038 static const char* cpu_model_description(void);
1039 static const char* cpu_brand(void);
1040 static const char* cpu_brand_string(void);
1041
1042 static int cpu_type_description(char* const buf, size_t buf_len);
1043 static int cpu_detailed_description(char* const buf, size_t buf_len);
1044 static int cpu_extended_brand_string(char* const buf, size_t buf_len);
1045
1046 static bool cpu_is_em64t(void);
1047 static bool is_netburst(void);
1048
1049 // Returns bytes written excluding termninating null byte.
1050 static size_t cpu_write_support_string(char* const buf, size_t buf_len);
1051 static void resolve_cpu_information_details(void);
1052 static int64_t max_qualified_cpu_freq_from_brand_string(void);
1053
1054 public:
1055 // Offsets for cpuid asm stub brand string
1056 static ByteSize proc_name_0_offset() { return byte_offset_of(CpuidInfo, proc_name_0); }
1057 static ByteSize proc_name_1_offset() { return byte_offset_of(CpuidInfo, proc_name_1); }
1058 static ByteSize proc_name_2_offset() { return byte_offset_of(CpuidInfo, proc_name_2); }
1059 static ByteSize proc_name_3_offset() { return byte_offset_of(CpuidInfo, proc_name_3); }
1060 static ByteSize proc_name_4_offset() { return byte_offset_of(CpuidInfo, proc_name_4); }
1061 static ByteSize proc_name_5_offset() { return byte_offset_of(CpuidInfo, proc_name_5); }
1062 static ByteSize proc_name_6_offset() { return byte_offset_of(CpuidInfo, proc_name_6); }
1063 static ByteSize proc_name_7_offset() { return byte_offset_of(CpuidInfo, proc_name_7); }
1064 static ByteSize proc_name_8_offset() { return byte_offset_of(CpuidInfo, proc_name_8); }
1065 static ByteSize proc_name_9_offset() { return byte_offset_of(CpuidInfo, proc_name_9); }
1066 static ByteSize proc_name_10_offset() { return byte_offset_of(CpuidInfo, proc_name_10); }
1067 static ByteSize proc_name_11_offset() { return byte_offset_of(CpuidInfo, proc_name_11); }
1068
1069 static int64_t maximum_qualified_cpu_frequency(void);
1070
1071 static bool supports_tscinv_ext(void);
1072
1073 static void initialize_tsc();
1074 static void initialize_cpu_information(void);
1075 };
1076
1077 #endif // CPU_X86_VM_VERSION_X86_HPP