1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_VERSION_X86_HPP
26 #define CPU_X86_VM_VERSION_X86_HPP
27
28 #include "runtime/abstract_vm_version.hpp"
29 #include "utilities/debug.hpp"
30 #include "utilities/macros.hpp"
31 #include "utilities/sizes.hpp"
32
33 class stringStream;
34
35 class VM_Version : public Abstract_VM_Version {
36 friend class VMStructs;
37 friend class JVMCIVMStructs;
38
39 public:
40 // cpuid result register layouts. These are all unions of a uint32_t
41 // (in case anyone wants access to the register as a whole) and a bitfield.
42
43 union StdCpuid1Eax {
44 uint32_t value;
45 struct {
46 uint32_t stepping : 4,
47 model : 4,
48 family : 4,
49 proc_type : 2,
50 : 2,
51 ext_model : 4,
52 ext_family : 8,
53 : 4;
54 } bits;
55 };
56
57 union StdCpuid1Ebx { // example, unused
58 uint32_t value;
59 struct {
60 uint32_t brand_id : 8,
61 clflush_size : 8,
62 threads_per_cpu : 8,
63 apic_id : 8;
64 } bits;
65 };
66
67 union StdCpuid1Ecx {
68 uint32_t value;
69 struct {
70 uint32_t sse3 : 1,
71 clmul : 1,
72 : 1,
73 monitor : 1,
74 : 1,
75 vmx : 1,
76 : 1,
77 est : 1,
78 : 1,
79 ssse3 : 1,
80 cid : 1,
81 : 1,
82 fma : 1,
83 cmpxchg16: 1,
84 : 4,
85 dca : 1,
86 sse4_1 : 1,
87 sse4_2 : 1,
88 : 2,
89 popcnt : 1,
90 : 1,
91 aes : 1,
92 : 1,
93 osxsave : 1,
94 avx : 1,
95 f16c : 1,
96 : 1,
97 hv : 1;
98 } bits;
99 };
100
101 union StdCpuid1Edx {
102 uint32_t value;
103 struct {
104 uint32_t : 4,
105 tsc : 1,
106 : 3,
107 cmpxchg8 : 1,
108 : 6,
109 cmov : 1,
110 : 3,
111 clflush : 1,
112 : 3,
113 mmx : 1,
114 fxsr : 1,
115 sse : 1,
116 sse2 : 1,
117 : 1,
118 ht : 1,
119 : 3;
120 } bits;
121 };
122
123 union DcpCpuid4Eax {
124 uint32_t value;
125 struct {
126 uint32_t cache_type : 5,
127 : 21,
128 cores_per_cpu : 6;
129 } bits;
130 };
131
132 union DcpCpuid4Ebx {
133 uint32_t value;
134 struct {
135 uint32_t L1_line_size : 12,
136 partitions : 10,
137 associativity : 10;
138 } bits;
139 };
140
141 union TplCpuidBEbx {
142 uint32_t value;
143 struct {
144 uint32_t logical_cpus : 16,
145 : 16;
146 } bits;
147 };
148
149 union ExtCpuid1Ecx {
150 uint32_t value;
151 struct {
152 uint32_t LahfSahf : 1,
153 CmpLegacy : 1,
154 : 3,
155 lzcnt : 1,
156 sse4a : 1,
157 misalignsse : 1,
158 prefetchw : 1,
159 : 23;
160 } bits;
161 };
162
163 union ExtCpuid1Edx {
164 uint32_t value;
165 struct {
166 uint32_t : 22,
167 mmx_amd : 1,
168 mmx : 1,
169 fxsr : 1,
170 fxsr_opt : 1,
171 pdpe1gb : 1,
172 rdtscp : 1,
173 : 1,
174 long_mode : 1,
175 tdnow2 : 1,
176 tdnow : 1;
177 } bits;
178 };
179
180 union ExtCpuid5Ex {
181 uint32_t value;
182 struct {
183 uint32_t L1_line_size : 8,
184 L1_tag_lines : 8,
185 L1_assoc : 8,
186 L1_size : 8;
187 } bits;
188 };
189
190 union ExtCpuid7Edx {
191 uint32_t value;
192 struct {
193 uint32_t : 8,
194 tsc_invariance : 1,
195 : 23;
196 } bits;
197 };
198
199 union ExtCpuid8Ecx {
200 uint32_t value;
201 struct {
202 uint32_t threads_per_cpu : 8,
203 : 24;
204 } bits;
205 };
206
207 union SefCpuid7Eax {
208 uint32_t value;
209 };
210
211 union SefCpuid7Ebx {
212 uint32_t value;
213 struct {
214 uint32_t fsgsbase : 1,
215 : 2,
216 bmi1 : 1,
217 : 1,
218 avx2 : 1,
219 : 2,
220 bmi2 : 1,
221 erms : 1,
222 : 1,
223 rtm : 1,
224 : 4,
225 avx512f : 1,
226 avx512dq : 1,
227 : 1,
228 adx : 1,
229 : 1,
230 avx512ifma : 1,
231 : 1,
232 clflushopt : 1,
233 clwb : 1,
234 : 1,
235 avx512pf : 1,
236 avx512er : 1,
237 avx512cd : 1,
238 sha : 1,
239 avx512bw : 1,
240 avx512vl : 1;
241 } bits;
242 };
243
244 union SefCpuid7Ecx {
245 uint32_t value;
246 struct {
247 uint32_t prefetchwt1 : 1,
248 avx512_vbmi : 1,
249 umip : 1,
250 pku : 1,
251 ospke : 1,
252 : 1,
253 avx512_vbmi2 : 1,
254 cet_ss : 1,
255 gfni : 1,
256 vaes : 1,
257 avx512_vpclmulqdq : 1,
258 avx512_vnni : 1,
259 avx512_bitalg : 1,
260 : 1,
261 avx512_vpopcntdq : 1,
262 : 1,
263 : 1,
264 mawau : 5,
265 rdpid : 1,
266 : 9;
267 } bits;
268 };
269
270 union SefCpuid7Edx {
271 uint32_t value;
272 struct {
273 uint32_t : 2,
274 avx512_4vnniw : 1,
275 avx512_4fmaps : 1,
276 fast_short_rep_mov : 1,
277 : 9,
278 serialize : 1,
279 hybrid: 1,
280 : 4,
281 cet_ibt : 1,
282 : 2,
283 avx512_fp16 : 1,
284 : 8;
285 } bits;
286 };
287
288 union SefCpuid7SubLeaf1Eax {
289 uint32_t value;
290 struct {
291 uint32_t sha512 : 1,
292 : 22,
293 avx_ifma : 1,
294 : 8;
295 } bits;
296 };
297
298 union SefCpuid7SubLeaf1Edx {
299 uint32_t value;
300 struct {
301 uint32_t : 19,
302 avx10 : 1,
303 : 1,
304 apx_f : 1,
305 : 10;
306 } bits;
307 };
308
309 union StdCpuid24MainLeafEax {
310 uint32_t value;
311 struct {
312 uint32_t sub_leaves_cnt : 31;
313 } bits;
314 };
315
316 union StdCpuid24MainLeafEbx {
317 uint32_t value;
318 struct {
319 uint32_t avx10_converged_isa_version : 8,
320 : 8,
321 : 2,
322 avx10_vlen_512 : 1,
323 : 13;
324 } bits;
325 };
326
327 union ExtCpuid1EEbx {
328 uint32_t value;
329 struct {
330 uint32_t : 8,
331 threads_per_core : 8,
332 : 16;
333 } bits;
334 };
335
336 union XemXcr0Eax {
337 uint32_t value;
338 struct {
339 uint32_t x87 : 1,
340 sse : 1,
341 ymm : 1,
342 bndregs : 1,
343 bndcsr : 1,
344 opmask : 1,
345 zmm512 : 1,
346 zmm32 : 1,
347 : 11,
348 apx_f : 1,
349 : 12;
350 } bits;
351 };
352
353 protected:
354 static int _cpu;
355 static int _model;
356 static int _stepping;
357
358 static bool _has_intel_jcc_erratum;
359
360 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
361 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
362 static address _cpuinfo_segv_addr_apx; // address of instruction which causes APX specific SEGV
363 static address _cpuinfo_cont_addr_apx; // address of instruction after the one which causes APX specific SEGV
364
365 /*
366 * Update following files when declaring new flags:
367 * test/lib-test/jdk/test/whitebox/CPUInfoTest.java
368 * src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/amd64/AMD64.java
369 */
370 enum Feature_Flag {
371 #define CPU_FEATURE_FLAGS(decl) \
372 decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \
373 decl(CMOV, "cmov", 1) \
374 decl(FXSR, "fxsr", 2) \
375 decl(HT, "ht", 3) \
376 \
377 decl(MMX, "mmx", 4) \
378 decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
379 /* may not necessarily support other 3dnow instructions */ \
380 decl(SSE, "sse", 6) \
381 decl(SSE2, "sse2", 7) \
382 \
383 decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
384 decl(SSSE3, "ssse3", 9 ) \
385 decl(SSE4A, "sse4a", 10) \
386 decl(SSE4_1, "sse4.1", 11) \
387 \
388 decl(SSE4_2, "sse4.2", 12) \
389 decl(POPCNT, "popcnt", 13) \
390 decl(LZCNT, "lzcnt", 14) \
391 decl(TSC, "tsc", 15) \
392 \
393 decl(TSCINV_BIT, "tscinvbit", 16) \
394 decl(TSCINV, "tscinv", 17) \
395 decl(AVX, "avx", 18) \
396 decl(AVX2, "avx2", 19) \
397 \
398 decl(AES, "aes", 20) \
399 decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \
400 decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \
401 decl(BMI1, "bmi1", 23) \
402 \
403 decl(BMI2, "bmi2", 24) \
404 decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \
405 decl(ADX, "adx", 26) \
406 decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \
407 \
408 decl(AVX512DQ, "avx512dq", 28) \
409 decl(AVX512PF, "avx512pf", 29) \
410 decl(AVX512ER, "avx512er", 30) \
411 decl(AVX512CD, "avx512cd", 31) \
412 \
413 decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \
414 decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \
415 decl(SHA, "sha", 34) /* SHA instructions */ \
416 decl(FMA, "fma", 35) /* FMA instructions */ \
417 \
418 decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \
419 decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \
420 decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \
421 decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \
422 \
423 decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \
424 decl(FLUSH, "clflush", 41) /* flush instruction */ \
425 decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \
426 decl(CLWB, "clwb", 43) /* clwb instruction */ \
427 \
428 decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \
429 decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \
430 decl(HV, "hv", 46) /* Hypervisor instructions */ \
431 decl(SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \
432 decl(RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \
433 decl(RDPID, "rdpid", 49) /* RDPID instruction */ \
434 decl(FSRM, "fsrm", 50) /* Fast Short REP MOV */ \
435 decl(GFNI, "gfni", 51) /* Vector GFNI instructions */ \
436 decl(AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\
437 decl(F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \
438 decl(PKU, "pku", 54) /* Protection keys for user-mode pages */ \
439 decl(OSPKE, "ospke", 55) /* OS enables protection keys */ \
440 decl(CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \
441 decl(CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \
442 decl(AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/ \
443 decl(AVX_IFMA, "avx_ifma", 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \
444 decl(APX_F, "apx_f", 60) /* Intel Advanced Performance Extensions*/ \
445 decl(SHA512, "sha512", 61) /* SHA512 instructions*/ \
446 decl(AVX512_FP16, "avx512_fp16", 62) /* AVX512 FP16 ISA support*/ \
447 decl(AVX10_1, "avx10_1", 63) /* AVX10 512 bit vector ISA Version 1 support*/ \
448 decl(AVX10_2, "avx10_2", 64) /* AVX10 512 bit vector ISA Version 2 support*/ \
449 decl(HYBRID, "hybrid", 65) /* Hybrid architecture */
450
451 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit),
452 CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
453 #undef DECLARE_CPU_FEATURE_FLAG
454 MAX_CPU_FEATURES
455 };
456
457 class VM_Features {
458 friend class VMStructs;
459 friend class JVMCIVMStructs;
460
461 private:
462 uint64_t _features_bitmap[(MAX_CPU_FEATURES / BitsPerLong) + 1];
463
464 STATIC_ASSERT(sizeof(_features_bitmap) * BitsPerByte >= MAX_CPU_FEATURES);
465
466 // Number of 8-byte elements in _bitmap.
467 constexpr static int features_bitmap_element_count() {
468 return sizeof(_features_bitmap) / sizeof(uint64_t);
469 }
470
471 constexpr static int features_bitmap_element_shift_count() {
472 return LogBitsPerLong;
473 }
474
475 constexpr static uint64_t features_bitmap_element_mask() {
476 return (1ULL << features_bitmap_element_shift_count()) - 1;
477 }
478
479 static int index(Feature_Flag feature) {
480 int idx = feature >> features_bitmap_element_shift_count();
481 assert(idx < features_bitmap_element_count(), "Features array index out of bounds");
482 return idx;
483 }
484
485 static uint64_t bit_mask(Feature_Flag feature) {
486 return (1ULL << (feature & features_bitmap_element_mask()));
487 }
488
489 static int _features_bitmap_size; // for JVMCI purposes
490 public:
491 VM_Features() {
492 for (int i = 0; i < features_bitmap_element_count(); i++) {
493 _features_bitmap[i] = 0;
494 }
495 }
496
497 void set_feature(Feature_Flag feature) {
498 int idx = index(feature);
499 _features_bitmap[idx] |= bit_mask(feature);
500 }
501
502 void clear_feature(VM_Version::Feature_Flag feature) {
503 int idx = index(feature);
504 _features_bitmap[idx] &= ~bit_mask(feature);
505 }
506
507 bool supports_feature(VM_Version::Feature_Flag feature) {
508 int idx = index(feature);
509 return (_features_bitmap[idx] & bit_mask(feature)) != 0;
510 }
511 };
512
513 // CPU feature flags vector, can be affected by VM settings.
514 static VM_Features _features;
515
516 // Original CPU feature flags vector, not affected by VM settings.
517 static VM_Features _cpu_features;
518
519 static const char* _features_names[];
520
521 static void clear_cpu_features() {
522 _features = VM_Features();
523 _cpu_features = VM_Features();
524 }
525
526 enum Extended_Family {
527 // AMD
528 CPU_FAMILY_AMD_11H = 0x11,
529 CPU_FAMILY_AMD_17H = 0x17, /* Zen1 & Zen2 */
530 CPU_FAMILY_AMD_19H = 0x19, /* Zen3 & Zen4 */
531 // ZX
532 CPU_FAMILY_ZX_CORE_F6 = 6,
533 CPU_FAMILY_ZX_CORE_F7 = 7,
534 // Intel
535 CPU_FAMILY_INTEL_CORE = 6,
536 CPU_MODEL_NEHALEM = 0x1e,
537 CPU_MODEL_NEHALEM_EP = 0x1a,
538 CPU_MODEL_NEHALEM_EX = 0x2e,
539 CPU_MODEL_WESTMERE = 0x25,
540 CPU_MODEL_WESTMERE_EP = 0x2c,
541 CPU_MODEL_WESTMERE_EX = 0x2f,
542 CPU_MODEL_SANDYBRIDGE = 0x2a,
543 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
544 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
545 CPU_MODEL_HASWELL_E3 = 0x3c,
546 CPU_MODEL_HASWELL_E7 = 0x3f,
547 CPU_MODEL_BROADWELL = 0x3d,
548 CPU_MODEL_SKYLAKE = 0x55
549 };
550
551 // cpuid information block. All info derived from executing cpuid with
552 // various function numbers is stored here. Intel and AMD info is
553 // merged in this block: accessor methods disentangle it.
554 //
555 // The info block is laid out in subblocks of 4 dwords corresponding to
556 // eax, ebx, ecx and edx, whether or not they contain anything useful.
557 class CpuidInfo {
558 public:
559 // cpuid function 0
560 uint32_t std_max_function;
561 uint32_t std_vendor_name_0;
562 uint32_t std_vendor_name_1;
563 uint32_t std_vendor_name_2;
564
565 // cpuid function 1
566 StdCpuid1Eax std_cpuid1_eax;
567 StdCpuid1Ebx std_cpuid1_ebx;
568 StdCpuid1Ecx std_cpuid1_ecx;
569 StdCpuid1Edx std_cpuid1_edx;
570
571 // cpuid function 4 (deterministic cache parameters)
572 DcpCpuid4Eax dcp_cpuid4_eax;
573 DcpCpuid4Ebx dcp_cpuid4_ebx;
574 uint32_t dcp_cpuid4_ecx; // unused currently
575 uint32_t dcp_cpuid4_edx; // unused currently
576
577 // cpuid function 7 (structured extended features enumeration leaf)
578 // eax = 7, ecx = 0
579 SefCpuid7Eax sef_cpuid7_eax;
580 SefCpuid7Ebx sef_cpuid7_ebx;
581 SefCpuid7Ecx sef_cpuid7_ecx;
582 SefCpuid7Edx sef_cpuid7_edx;
583
584 // cpuid function 7 (structured extended features enumeration sub-leaf 1)
585 // eax = 7, ecx = 1
586 SefCpuid7SubLeaf1Eax sefsl1_cpuid7_eax;
587 SefCpuid7SubLeaf1Edx sefsl1_cpuid7_edx;
588
589 // cpuid function 24 converged vector ISA main leaf
590 // eax = 24, ecx = 0
591 StdCpuid24MainLeafEax std_cpuid24_eax;
592 StdCpuid24MainLeafEbx std_cpuid24_ebx;
593
594 // cpuid function 0xB (processor topology)
595 // ecx = 0
596 uint32_t tpl_cpuidB0_eax;
597 TplCpuidBEbx tpl_cpuidB0_ebx;
598 uint32_t tpl_cpuidB0_ecx; // unused currently
599 uint32_t tpl_cpuidB0_edx; // unused currently
600
601 // ecx = 1
602 uint32_t tpl_cpuidB1_eax;
603 TplCpuidBEbx tpl_cpuidB1_ebx;
604 uint32_t tpl_cpuidB1_ecx; // unused currently
605 uint32_t tpl_cpuidB1_edx; // unused currently
606
607 // ecx = 2
608 uint32_t tpl_cpuidB2_eax;
609 TplCpuidBEbx tpl_cpuidB2_ebx;
610 uint32_t tpl_cpuidB2_ecx; // unused currently
611 uint32_t tpl_cpuidB2_edx; // unused currently
612
613 // cpuid function 0x80000000 // example, unused
614 uint32_t ext_max_function;
615 uint32_t ext_vendor_name_0;
616 uint32_t ext_vendor_name_1;
617 uint32_t ext_vendor_name_2;
618
619 // cpuid function 0x80000001
620 uint32_t ext_cpuid1_eax; // reserved
621 uint32_t ext_cpuid1_ebx; // reserved
622 ExtCpuid1Ecx ext_cpuid1_ecx;
623 ExtCpuid1Edx ext_cpuid1_edx;
624
625 // cpuid functions 0x80000002 thru 0x80000004: example, unused
626 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
627 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
628 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
629
630 // cpuid function 0x80000005 // AMD L1, Intel reserved
631 uint32_t ext_cpuid5_eax; // unused currently
632 uint32_t ext_cpuid5_ebx; // reserved
633 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
634 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
635
636 // cpuid function 0x80000007
637 uint32_t ext_cpuid7_eax; // reserved
638 uint32_t ext_cpuid7_ebx; // reserved
639 uint32_t ext_cpuid7_ecx; // reserved
640 ExtCpuid7Edx ext_cpuid7_edx; // tscinv
641
642 // cpuid function 0x80000008
643 uint32_t ext_cpuid8_eax; // unused currently
644 uint32_t ext_cpuid8_ebx; // reserved
645 ExtCpuid8Ecx ext_cpuid8_ecx;
646 uint32_t ext_cpuid8_edx; // reserved
647
648 // cpuid function 0x8000001E // AMD 17h
649 uint32_t ext_cpuid1E_eax;
650 ExtCpuid1EEbx ext_cpuid1E_ebx; // threads per core (AMD17h)
651 uint32_t ext_cpuid1E_ecx;
652 uint32_t ext_cpuid1E_edx; // unused currently
653
654 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
655 XemXcr0Eax xem_xcr0_eax;
656 uint32_t xem_xcr0_edx; // reserved
657
658 // Space to save ymm registers after signal handle
659 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15
660
661 // Space to save zmm registers after signal handle
662 int zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31
663
664 // Space to save apx registers after signal handle
665 jlong apx_save[2]; // Save r16 and r31
666
667 VM_Features feature_flags() const;
668
669 // Asserts
670 void assert_is_initialized() const {
671 assert(std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
672 }
673
674 // Extractors
675 uint32_t extended_cpu_family() const {
676 uint32_t result = std_cpuid1_eax.bits.family;
677 result += std_cpuid1_eax.bits.ext_family;
678 return result;
679 }
680
681 uint32_t extended_cpu_model() const {
682 uint32_t result = std_cpuid1_eax.bits.model;
683 result |= std_cpuid1_eax.bits.ext_model << 4;
684 return result;
685 }
686
687 uint32_t cpu_stepping() const {
688 uint32_t result = std_cpuid1_eax.bits.stepping;
689 return result;
690 }
691 };
692
693 private:
694 // The actual cpuid info block
695 static CpuidInfo _cpuid_info;
696
697 // Extractors and predicates
698 static uint logical_processor_count() {
699 uint result = threads_per_core();
700 return result;
701 }
702
703 static bool compute_has_intel_jcc_erratum();
704
705 static bool os_supports_avx_vectors();
706 static bool os_supports_apx_egprs();
707 static void get_processor_features();
708
709 public:
710 // Offsets for cpuid asm stub
711 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
712 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
713 static ByteSize std_cpuid24_offset() { return byte_offset_of(CpuidInfo, std_cpuid24_eax); }
714 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
715 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
716 static ByteSize sefsl1_cpuid7_offset() { return byte_offset_of(CpuidInfo, sefsl1_cpuid7_eax); }
717 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
718 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
719 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
720 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
721 static ByteSize ext_cpuid1E_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1E_eax); }
722 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
723 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
724 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
725 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
726 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
727 static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
728 static ByteSize apx_save_offset() { return byte_offset_of(CpuidInfo, apx_save); }
729
730 // The value used to check ymm register after signal handle
731 static int ymm_test_value() { return 0xCAFEBABE; }
732 static jlong egpr_test_value() { return 0xCAFEBABECAFEBABELL; }
733
734 static void get_cpu_info_wrapper();
735 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
736 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
737 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
738 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; }
739
740 static void set_cpuinfo_segv_addr_apx(address pc) { _cpuinfo_segv_addr_apx = pc; }
741 static bool is_cpuinfo_segv_addr_apx(address pc) { return _cpuinfo_segv_addr_apx == pc; }
742 static void set_cpuinfo_cont_addr_apx(address pc) { _cpuinfo_cont_addr_apx = pc; }
743 static address cpuinfo_cont_addr_apx() { return _cpuinfo_cont_addr_apx; }
744
745 static void clear_apx_test_state();
746
747 static void clean_cpuFeatures() {
748 VM_Version::clear_cpu_features();
749 }
750 static void set_avx_cpuFeatures() {
751 _features.set_feature(CPU_SSE);
752 _features.set_feature(CPU_SSE2);
753 _features.set_feature(CPU_AVX);
754 _features.set_feature(CPU_VZEROUPPER);
755 }
756 static void set_evex_cpuFeatures() {
757 _features.set_feature(CPU_AVX10_1);
758 _features.set_feature(CPU_AVX512F);
759 _features.set_feature(CPU_SSE);
760 _features.set_feature(CPU_SSE2);
761 _features.set_feature(CPU_VZEROUPPER);
762 }
763 static void set_apx_cpuFeatures() { _features.set_feature(CPU_APX_F); }
764 static void set_bmi_cpuFeatures() {
765 _features.set_feature(CPU_BMI1);
766 _features.set_feature(CPU_BMI2);
767 _features.set_feature(CPU_LZCNT);
768 _features.set_feature(CPU_POPCNT);
769 }
770
771 // Initialization
772 static void initialize();
773
774 // Override Abstract_VM_Version implementation
775 static void print_platform_virtualization_info(outputStream*);
776
777 //
778 // Processor family:
779 // 3 - 386
780 // 4 - 486
781 // 5 - Pentium
782 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
783 // Pentium M, Core Solo, Core Duo, Core2 Duo
784 // family 6 model: 9, 13, 14, 15
785 // 0x0f - Pentium 4, Opteron
786 //
787 // Note: The cpu family should be used to select between
788 // instruction sequences which are valid on all Intel
789 // processors. Use the feature test functions below to
790 // determine whether a particular instruction is supported.
791 //
792 static void assert_is_initialized() { _cpuid_info.assert_is_initialized(); }
793 static uint32_t extended_cpu_family() { return _cpuid_info.extended_cpu_family(); }
794 static uint32_t extended_cpu_model() { return _cpuid_info.extended_cpu_model(); }
795 static uint32_t cpu_stepping() { return _cpuid_info.cpu_stepping(); }
796 static int cpu_family() { return _cpu;}
797 static bool is_P6() { return cpu_family() >= 6; }
798 static bool is_intel_server_family() { return cpu_family() == 6 || cpu_family() == 19; }
799 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
800 static bool is_hygon() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH'
801 static bool is_amd_family() { return is_amd() || is_hygon(); }
802 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
803 static bool is_zx() { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS '
804 static bool is_atom_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton
805 static bool is_knights_family() { return UseKNLSetting || ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x57) || (extended_cpu_model() == 0x85))); } // Xeon Phi 3200/5200/7200 and Future Xeon Phi
806
807 static bool supports_processor_topology() {
808 return (_cpuid_info.std_max_function >= 0xB) &&
809 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
810 // Some cpus have max cpuid >= 0xB but do not support processor topology.
811 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
812 }
813
814 static uint cores_per_cpu();
815 static uint threads_per_core();
816 static uint L1_line_size();
817
818 static uint prefetch_data_size() {
819 return L1_line_size();
820 }
821
822 //
823 // Feature identification which can be affected by VM settings
824 //
825 static bool supports_cmov() { return _features.supports_feature(CPU_CMOV); }
826 static bool supports_fxsr() { return _features.supports_feature(CPU_FXSR); }
827 static bool supports_ht() { return _features.supports_feature(CPU_HT); }
828 static bool supports_mmx() { return _features.supports_feature(CPU_MMX); }
829 static bool supports_sse() { return _features.supports_feature(CPU_SSE); }
830 static bool supports_sse2() { return _features.supports_feature(CPU_SSE2); }
831 static bool supports_sse3() { return _features.supports_feature(CPU_SSE3); }
832 static bool supports_ssse3() { return _features.supports_feature(CPU_SSSE3); }
833 static bool supports_sse4_1() { return _features.supports_feature(CPU_SSE4_1); }
834 static bool supports_sse4_2() { return _features.supports_feature(CPU_SSE4_2); }
835 static bool supports_popcnt() { return _features.supports_feature(CPU_POPCNT); }
836 static bool supports_avx() { return _features.supports_feature(CPU_AVX); }
837 static bool supports_avx2() { return _features.supports_feature(CPU_AVX2); }
838 static bool supports_tsc() { return _features.supports_feature(CPU_TSC); }
839 static bool supports_rdtscp() { return _features.supports_feature(CPU_RDTSCP); }
840 static bool supports_rdpid() { return _features.supports_feature(CPU_RDPID); }
841 static bool supports_aes() { return _features.supports_feature(CPU_AES); }
842 static bool supports_erms() { return _features.supports_feature(CPU_ERMS); }
843 static bool supports_fsrm() { return _features.supports_feature(CPU_FSRM); }
844 static bool supports_clmul() { return _features.supports_feature(CPU_CLMUL); }
845 static bool supports_rtm() { return _features.supports_feature(CPU_RTM); }
846 static bool supports_bmi1() { return _features.supports_feature(CPU_BMI1); }
847 static bool supports_bmi2() { return _features.supports_feature(CPU_BMI2); }
848 static bool supports_adx() { return _features.supports_feature(CPU_ADX); }
849 static bool supports_evex() { return _features.supports_feature(CPU_AVX512F); }
850 static bool supports_avx512dq() { return _features.supports_feature(CPU_AVX512DQ); }
851 static bool supports_avx512ifma() { return _features.supports_feature(CPU_AVX512_IFMA); }
852 static bool supports_avxifma() { return _features.supports_feature(CPU_AVX_IFMA); }
853 static bool supports_avx512pf() { return _features.supports_feature(CPU_AVX512PF); }
854 static bool supports_avx512er() { return _features.supports_feature(CPU_AVX512ER); }
855 static bool supports_avx512cd() { return _features.supports_feature(CPU_AVX512CD); }
856 static bool supports_avx512bw() { return _features.supports_feature(CPU_AVX512BW); }
857 static bool supports_avx512vl() { return _features.supports_feature(CPU_AVX512VL); }
858 static bool supports_avx512vlbw() { return (supports_evex() && supports_avx512bw() && supports_avx512vl()); }
859 static bool supports_avx512bwdq() { return (supports_evex() && supports_avx512bw() && supports_avx512dq()); }
860 static bool supports_avx512vldq() { return (supports_evex() && supports_avx512dq() && supports_avx512vl()); }
861 static bool supports_avx512vlbwdq() { return (supports_evex() && supports_avx512vl() &&
862 supports_avx512bw() && supports_avx512dq()); }
863 static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); }
864 static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); }
865 static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); }
866 static bool supports_apx_f() { return _features.supports_feature(CPU_APX_F); }
867 static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
868 static bool supports_sha() { return _features.supports_feature(CPU_SHA); }
869 static bool supports_fma() { return _features.supports_feature(CPU_FMA) && supports_avx(); }
870 static bool supports_vzeroupper() { return _features.supports_feature(CPU_VZEROUPPER); }
871 static bool supports_avx512_vpopcntdq() { return _features.supports_feature(CPU_AVX512_VPOPCNTDQ); }
872 static bool supports_avx512_vpclmulqdq() { return _features.supports_feature(CPU_AVX512_VPCLMULQDQ); }
873 static bool supports_avx512_vaes() { return _features.supports_feature(CPU_AVX512_VAES); }
874 static bool supports_gfni() { return _features.supports_feature(CPU_GFNI); }
875 static bool supports_avx512_vnni() { return _features.supports_feature(CPU_AVX512_VNNI); }
876 static bool supports_avx512_bitalg() { return _features.supports_feature(CPU_AVX512_BITALG); }
877 static bool supports_avx512_vbmi() { return _features.supports_feature(CPU_AVX512_VBMI); }
878 static bool supports_avx512_vbmi2() { return _features.supports_feature(CPU_AVX512_VBMI2); }
879 static bool supports_avx512_fp16() { return _features.supports_feature(CPU_AVX512_FP16); }
880 static bool supports_hv() { return _features.supports_feature(CPU_HV); }
881 static bool supports_serialize() { return _features.supports_feature(CPU_SERIALIZE); }
882 static bool supports_hybrid() { return _features.supports_feature(CPU_HYBRID); }
883 static bool supports_f16c() { return _features.supports_feature(CPU_F16C); }
884 static bool supports_pku() { return _features.supports_feature(CPU_PKU); }
885 static bool supports_ospke() { return _features.supports_feature(CPU_OSPKE); }
886 static bool supports_cet_ss() { return _features.supports_feature(CPU_CET_SS); }
887 static bool supports_cet_ibt() { return _features.supports_feature(CPU_CET_IBT); }
888 static bool supports_sha512() { return _features.supports_feature(CPU_SHA512); }
889
890 // Intel® AVX10 introduces a versioned approach for enumeration that is monotonically increasing, inclusive,
891 // and supporting all vector lengths. Feature set supported by an AVX10 vector ISA version is also supported
892 // by all the versions above it.
893 static bool supports_avx10_1() { return _features.supports_feature(CPU_AVX10_1);}
894 static bool supports_avx10_2() { return _features.supports_feature(CPU_AVX10_2);}
895
896 //
897 // Feature identification not affected by VM flags
898 //
899 static bool cpu_supports_evex() { return _cpu_features.supports_feature(CPU_AVX512F); }
900
901 static bool supports_avx512_simd_sort() {
902 if (supports_avx512dq()) {
903 // Disable AVX512 version of SIMD Sort on AMD Zen4 Processors.
904 if (is_amd() && cpu_family() == CPU_FAMILY_AMD_19H) {
905 return false;
906 }
907 return true;
908 }
909 return false;
910 }
911
912 // Intel features
913 static bool is_intel_family_core() { return is_intel() &&
914 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
915
916 static bool is_intel_skylake() { return is_intel_family_core() &&
917 extended_cpu_model() == CPU_MODEL_SKYLAKE; }
918
919 #ifdef COMPILER2
920 // Determine if it's running on Cascade Lake using default options.
921 static bool is_default_intel_cascade_lake();
922 #endif
923
924 static bool is_intel_cascade_lake();
925
926 static int avx3_threshold();
927
928 static bool is_intel_tsc_synched_at_init();
929
930 static void insert_features_names(VM_Version::VM_Features features, stringStream& ss);
931
932 // This checks if the JVM is potentially affected by an erratum on Intel CPUs (SKX102)
933 // that causes unpredictable behaviour when jcc crosses 64 byte boundaries. Its microcode
934 // mitigation causes regressions when jumps or fused conditional branches cross or end at
935 // 32 byte boundaries.
936 static bool has_intel_jcc_erratum() { return _has_intel_jcc_erratum; }
937
938 // AMD features
939 static bool supports_3dnow_prefetch() { return _features.supports_feature(CPU_3DNOW_PREFETCH); }
940 static bool supports_lzcnt() { return _features.supports_feature(CPU_LZCNT); }
941 static bool supports_sse4a() { return _features.supports_feature(CPU_SSE4A); }
942
943 static bool is_amd_Barcelona() { return is_amd() &&
944 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
945
946 // Intel and AMD newer cores support fast timestamps well
947 static bool supports_tscinv_bit() {
948 return _features.supports_feature(CPU_TSCINV_BIT);
949 }
950 static bool supports_tscinv() {
951 return _features.supports_feature(CPU_TSCINV);
952 }
953
954 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
955 static bool has_fast_idiv() { return is_intel() && is_intel_server_family() &&
956 supports_sse3() && _model != 0x1C; }
957
958 static bool supports_compare_and_exchange() { return true; }
959
960 static int allocate_prefetch_distance(bool use_watermark_prefetch);
961
962 // SSE2 and later processors implement a 'pause' instruction
963 // that can be used for efficient implementation of
964 // the intrinsic for java.lang.Thread.onSpinWait()
965 static bool supports_on_spin_wait() { return supports_sse2(); }
966
967 // x86_64 supports fast class initialization checks
968 static bool supports_fast_class_init_checks() {
969 return true;
970 }
971
972 // x86_64 supports secondary supers table
973 constexpr static bool supports_secondary_supers_table() {
974 return true;
975 }
976
977 constexpr static bool supports_stack_watermark_barrier() {
978 return true;
979 }
980
981 constexpr static bool supports_recursive_lightweight_locking() {
982 return true;
983 }
984
985 // For AVX CPUs only. f16c support is disabled if UseAVX == 0.
986 static bool supports_float16() {
987 return supports_f16c() || supports_avx512vl() || supports_avx512_fp16();
988 }
989
990 // Check intrinsic support
991 static bool is_intrinsic_supported(vmIntrinsicID id);
992
993 // there are several insns to force cache line sync to memory which
994 // we can use to ensure mapped non-volatile memory is up to date with
995 // pending in-cache changes.
996 //
997 // 64 bit cpus always support clflush which writes back and evicts
998 // on 32 bit cpus support is recorded via a feature flag
999 //
1000 // clflushopt is optional and acts like clflush except it does
1001 // not synchronize with other memory ops. it needs a preceding
1002 // and trailing StoreStore fence
1003 //
1004 // clwb is an optional intel-specific instruction which
1005 // writes back without evicting the line. it also does not
1006 // synchronize with other memory ops. so, it needs preceding
1007 // and trailing StoreStore fences.
1008
1009 static bool supports_clflush(); // Can't inline due to header file conflict
1010
1011 // Note: CPU_FLUSHOPT and CPU_CLWB bits should always be zero for 32-bit
1012 static bool supports_clflushopt() { return (_features.supports_feature(CPU_FLUSHOPT)); }
1013 static bool supports_clwb() { return (_features.supports_feature(CPU_CLWB)); }
1014
1015 // Old CPUs perform lea on AGU which causes additional latency transferring the
1016 // value from/to ALU for other operations
1017 static bool supports_fast_2op_lea() {
1018 return (is_intel() && supports_avx()) || // Sandy Bridge and above
1019 (is_amd() && supports_avx()); // Jaguar and Bulldozer and above
1020 }
1021
1022 // Pre Icelake Intels suffer inefficiency regarding 3-operand lea, which contains
1023 // all of base register, index register and displacement immediate, with 3 latency.
1024 // Note that when the address contains no displacement but the base register is
1025 // rbp or r13, the machine code must contain a zero displacement immediate,
1026 // effectively transform a 2-operand lea into a 3-operand lea. This can be
1027 // replaced by add-add or lea-add
1028 static bool supports_fast_3op_lea() {
1029 return supports_fast_2op_lea() &&
1030 ((is_intel() && supports_clwb() && !is_intel_skylake()) || // Icelake and above
1031 is_amd());
1032 }
1033
1034 #ifdef __APPLE__
1035 // Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64)
1036 static bool is_cpu_emulated();
1037 #endif
1038
1039 // support functions for virtualization detection
1040 private:
1041 static void check_virtualizations();
1042
1043 static const char* cpu_family_description(void);
1044 static const char* cpu_model_description(void);
1045 static const char* cpu_brand(void);
1046 static const char* cpu_brand_string(void);
1047
1048 static int cpu_type_description(char* const buf, size_t buf_len);
1049 static int cpu_detailed_description(char* const buf, size_t buf_len);
1050 static int cpu_extended_brand_string(char* const buf, size_t buf_len);
1051
1052 static bool cpu_is_em64t(void);
1053 static bool is_netburst(void);
1054
1055 // Returns bytes written excluding termninating null byte.
1056 static size_t cpu_write_support_string(char* const buf, size_t buf_len);
1057 static void resolve_cpu_information_details(void);
1058 static int64_t max_qualified_cpu_freq_from_brand_string(void);
1059
1060 public:
1061 // Offsets for cpuid asm stub brand string
1062 static ByteSize proc_name_0_offset() { return byte_offset_of(CpuidInfo, proc_name_0); }
1063 static ByteSize proc_name_1_offset() { return byte_offset_of(CpuidInfo, proc_name_1); }
1064 static ByteSize proc_name_2_offset() { return byte_offset_of(CpuidInfo, proc_name_2); }
1065 static ByteSize proc_name_3_offset() { return byte_offset_of(CpuidInfo, proc_name_3); }
1066 static ByteSize proc_name_4_offset() { return byte_offset_of(CpuidInfo, proc_name_4); }
1067 static ByteSize proc_name_5_offset() { return byte_offset_of(CpuidInfo, proc_name_5); }
1068 static ByteSize proc_name_6_offset() { return byte_offset_of(CpuidInfo, proc_name_6); }
1069 static ByteSize proc_name_7_offset() { return byte_offset_of(CpuidInfo, proc_name_7); }
1070 static ByteSize proc_name_8_offset() { return byte_offset_of(CpuidInfo, proc_name_8); }
1071 static ByteSize proc_name_9_offset() { return byte_offset_of(CpuidInfo, proc_name_9); }
1072 static ByteSize proc_name_10_offset() { return byte_offset_of(CpuidInfo, proc_name_10); }
1073 static ByteSize proc_name_11_offset() { return byte_offset_of(CpuidInfo, proc_name_11); }
1074
1075 static int64_t maximum_qualified_cpu_frequency(void);
1076
1077 static bool supports_tscinv_ext(void);
1078
1079 static void initialize_tsc();
1080 static void initialize_cpu_information(void);
1081 };
1082
1083 #endif // CPU_X86_VM_VERSION_X86_HPP