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#include "runtime/abstract_vm_version.hpp"
#include "utilities/debug.hpp"
#include "utilities/macros.hpp"
#include "utilities/sizes.hpp"
+ class stringStream;
+
class VM_Version : public Abstract_VM_Version {
friend class VMStructs;
friend class JVMCIVMStructs;
public:
* test/lib-test/jdk/test/whitebox/CPUInfoTest.java
* src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/amd64/AMD64.java
*/
enum Feature_Flag {
#define CPU_FEATURE_FLAGS(decl) \
! decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \
! decl(CMOV, "cmov", 1) \
! decl(FXSR, "fxsr", 2) \
! decl(HT, "ht", 3) \
\
! decl(MMX, "mmx", 4) \
! decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
/* may not necessarily support other 3dnow instructions */ \
! decl(SSE, "sse", 6) \
! decl(SSE2, "sse2", 7) \
\
! decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
! decl(SSSE3, "ssse3", 9 ) \
! decl(SSE4A, "sse4a", 10) \
! decl(SSE4_1, "sse4.1", 11) \
\
! decl(SSE4_2, "sse4.2", 12) \
! decl(POPCNT, "popcnt", 13) \
! decl(LZCNT, "lzcnt", 14) \
! decl(TSC, "tsc", 15) \
\
! decl(TSCINV_BIT, "tscinvbit", 16) \
! decl(TSCINV, "tscinv", 17) \
! decl(AVX, "avx", 18) \
! decl(AVX2, "avx2", 19) \
\
! decl(AES, "aes", 20) \
! decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \
! decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \
! decl(BMI1, "bmi1", 23) \
\
! decl(BMI2, "bmi2", 24) \
! decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \
! decl(ADX, "adx", 26) \
! decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \
\
! decl(AVX512DQ, "avx512dq", 28) \
! decl(AVX512PF, "avx512pf", 29) \
! decl(AVX512ER, "avx512er", 30) \
! decl(AVX512CD, "avx512cd", 31) \
\
! decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \
! decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \
! decl(SHA, "sha", 34) /* SHA instructions */ \
! decl(FMA, "fma", 35) /* FMA instructions */ \
\
! decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \
! decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \
! decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \
! decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \
\
! decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \
! decl(FLUSH, "clflush", 41) /* flush instruction */ \
! decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \
! decl(CLWB, "clwb", 43) /* clwb instruction */ \
\
! decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \
! decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \
! decl(HV, "hv", 46) /* Hypervisor instructions */ \
! decl(SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \
! decl(RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \
! decl(RDPID, "rdpid", 49) /* RDPID instruction */ \
! decl(FSRM, "fsrm", 50) /* Fast Short REP MOV */ \
! decl(GFNI, "gfni", 51) /* Vector GFNI instructions */ \
! decl(AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\
! decl(F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \
! decl(PKU, "pku", 54) /* Protection keys for user-mode pages */ \
! decl(OSPKE, "ospke", 55) /* OS enables protection keys */ \
! decl(CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \
! decl(CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \
! decl(AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/ \
! decl(AVX_IFMA, "avx_ifma", 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \
! decl(APX_F, "apx_f", 60) /* Intel Advanced Performance Extensions*/ \
! decl(SHA512, "sha512", 61) /* SHA512 instructions*/ \
! decl(AVX512_FP16, "avx512_fp16", 62) /* AVX512 FP16 ISA support*/ \
! decl(AVX10_1, "avx10_1", 63) /* AVX10 512 bit vector ISA Version 1 support*/ \
! decl(AVX10_2, "avx10_2", 64) /* AVX10 512 bit vector ISA Version 2 support*/
#define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit),
CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
#undef DECLARE_CPU_FEATURE_FLAG
MAX_CPU_FEATURES
* test/lib-test/jdk/test/whitebox/CPUInfoTest.java
* src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/amd64/AMD64.java
*/
enum Feature_Flag {
#define CPU_FEATURE_FLAGS(decl) \
! decl(CX8, cx8, 0) /* next bits are from cpuid 1 (EDX) */ \
! decl(CMOV, cmov, 1) \
! decl(FXSR, fxsr, 2) \
! decl(HT, ht, 3) \
\
! decl(MMX, mmx, 4) \
! decl(3DNOW_PREFETCH, 3dnowpref, 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
/* may not necessarily support other 3dnow instructions */ \
! decl(SSE, sse, 6) \
! decl(SSE2, sse2, 7) \
\
! decl(SSE3, sse3, 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
! decl(SSSE3, ssse3, 9 ) \
! decl(SSE4A, sse4a, 10) \
! decl(SSE4_1, sse4.1, 11) \
\
! decl(SSE4_2, sse4.2, 12) \
! decl(POPCNT, popcnt, 13) \
! decl(LZCNT, lzcnt, 14) \
! decl(TSC, tsc, 15) \
\
! decl(TSCINV_BIT, tscinvbit, 16) \
! decl(TSCINV, tscinv, 17) \
! decl(AVX, avx, 18) \
! decl(AVX2, avx2, 19) \
\
! decl(AES, aes, 20) \
! decl(ERMS, erms, 21) /* enhanced 'rep movsb/stosb' instructions */ \
! decl(CLMUL, clmul, 22) /* carryless multiply for CRC */ \
! decl(BMI1, bmi1, 23) \
\
! decl(BMI2, bmi2, 24) \
! decl(RTM, rtm, 25) /* Restricted Transactional Memory instructions */ \
! decl(ADX, adx, 26) \
! decl(AVX512F, avx512f, 27) /* AVX 512bit foundation instructions */ \
\
! decl(AVX512DQ, avx512dq, 28) \
! decl(AVX512PF, avx512pf, 29) \
! decl(AVX512ER, avx512er, 30) \
! decl(AVX512CD, avx512cd, 31) \
\
! decl(AVX512BW, avx512bw, 32) /* Byte and word vector instructions */ \
! decl(AVX512VL, avx512vl, 33) /* EVEX instructions with smaller vector length */ \
! decl(SHA, sha, 34) /* SHA instructions */ \
! decl(FMA, fma, 35) /* FMA instructions */ \
\
! decl(VZEROUPPER, vzeroupper, 36) /* Vzeroupper instruction */ \
! decl(AVX512_VPOPCNTDQ, avx512_vpopcntdq, 37) /* Vector popcount */ \
! decl(AVX512_VPCLMULQDQ, avx512_vpclmulqdq, 38) /* Vector carryless multiplication */ \
! decl(AVX512_VAES, avx512_vaes, 39) /* Vector AES instruction */ \
\
! decl(AVX512_VNNI, avx512_vnni, 40) /* Vector Neural Network Instructions */ \
! decl(FLUSH, clflush, 41) /* flush instruction */ \
! decl(FLUSHOPT, clflushopt, 42) /* flusopth instruction */ \
! decl(CLWB, clwb, 43) /* clwb instruction */ \
\
! decl(AVX512_VBMI2, avx512_vbmi2, 44) /* VBMI2 shift left double instructions */ \
! decl(AVX512_VBMI, avx512_vbmi, 45) /* Vector BMI instructions */ \
! decl(HV, hv, 46) /* Hypervisor instructions */ \
! decl(SERIALIZE, serialize, 47) /* CPU SERIALIZE */ \
! decl(RDTSCP, rdtscp, 48) /* RDTSCP instruction */ \
! decl(RDPID, rdpid, 49) /* RDPID instruction */ \
! decl(FSRM, fsrm, 50) /* Fast Short REP MOV */ \
! decl(GFNI, gfni, 51) /* Vector GFNI instructions */ \
! decl(AVX512_BITALG, avx512_bitalg, 52) /* Vector sub-word popcount and bit gather instructions */\
! decl(F16C, f16c, 53) /* Half-precision and single precision FP conversion instructions*/ \
! decl(PKU, pku, 54) /* Protection keys for user-mode pages */ \
! decl(OSPKE, ospke, 55) /* OS enables protection keys */ \
! decl(CET_IBT, cet_ibt, 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \
! decl(CET_SS, cet_ss, 57) /* Control Flow Enforcement - Shadow Stack */ \
! decl(AVX512_IFMA, avx512_ifma, 58) /* Integer Vector FMA instructions*/ \
! decl(AVX_IFMA, avx_ifma, 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \
! decl(APX_F, apx_f, 60) /* Intel Advanced Performance Extensions*/ \
! decl(SHA512, sha512, 61) /* SHA512 instructions*/ \
! decl(AVX512_FP16, avx512_fp16, 62) /* AVX512 FP16 ISA support*/ \
! decl(AVX10_1, avx10_1, 63) /* AVX10 512 bit vector ISA Version 1 support*/ \
! decl(AVX10_2, avx10_2, 64) /* AVX10 512 bit vector ISA Version 2 support*/
#define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit),
CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
#undef DECLARE_CPU_FEATURE_FLAG
MAX_CPU_FEATURES
static uint64_t bit_mask(Feature_Flag feature) {
return (1ULL << (feature & features_bitmap_element_mask()));
}
static int _features_bitmap_size; // for JVMCI purposes
+
public:
VM_Features() {
for (int i = 0; i < features_bitmap_element_count(); i++) {
_features_bitmap[i] = 0;
}
bool supports_feature(VM_Version::Feature_Flag feature) {
int idx = index(feature);
return (_features_bitmap[idx] & bit_mask(feature)) != 0;
}
+
+ bool supports_features(VM_Features* features_to_test) {
+ for (int i = 0; i < features_bitmap_element_count(); i++) {
+ if ((_features_bitmap[i] & features_to_test->_features_bitmap[i]) != features_to_test->_features_bitmap[i]) {
+ return false;
+ }
+ }
+ return true;
+ }
};
// CPU feature flags vector, can be affected by VM settings.
static VM_Features _features;
static int avx3_threshold();
static bool is_intel_tsc_synched_at_init();
! static void insert_features_names(VM_Version::VM_Features features, char* buf, size_t buflen);
// This checks if the JVM is potentially affected by an erratum on Intel CPUs (SKX102)
// that causes unpredictable behaviour when jcc crosses 64 byte boundaries. Its microcode
// mitigation causes regressions when jumps or fused conditional branches cross or end at
// 32 byte boundaries.
static int avx3_threshold();
static bool is_intel_tsc_synched_at_init();
! static void insert_features_names(VM_Version::VM_Features features, stringStream& ss);
// This checks if the JVM is potentially affected by an erratum on Intel CPUs (SKX102)
// that causes unpredictable behaviour when jcc crosses 64 byte boundaries. Its microcode
// mitigation causes regressions when jumps or fused conditional branches cross or end at
// 32 byte boundaries.
static bool supports_tscinv_ext(void);
static void initialize_tsc();
static void initialize_cpu_information(void);
+
+ static void get_cpu_features_name(void* features_buffer, stringStream& ss);
+ static void get_missing_features_name(void* features_buffer, stringStream& ss);
+
+ // Returns number of bytes required to store cpu features representation
+ static int cpu_features_size();
+
+ // Stores cpu features representation in the provided buffer. This representation is arch dependent.
+ // Size of the buffer must be same as returned by cpu_features_size()
+ static void store_cpu_features(void* buf);
+
+ static bool supports_features(void* features_to_test);
};
#endif // CPU_X86_VM_VERSION_X86_HPP
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