1 //
2 // Copyright (c) 2003, 2025, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // architecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131 reg_def R16 (SOC, SOC, Op_RegI, 16, r16->as_VMReg());
132 reg_def R16_H(SOC, SOC, Op_RegI, 16, r16->as_VMReg()->next());
133
134 reg_def R17 (SOC, SOC, Op_RegI, 17, r17->as_VMReg());
135 reg_def R17_H(SOC, SOC, Op_RegI, 17, r17->as_VMReg()->next());
136
137 reg_def R18 (SOC, SOC, Op_RegI, 18, r18->as_VMReg());
138 reg_def R18_H(SOC, SOC, Op_RegI, 18, r18->as_VMReg()->next());
139
140 reg_def R19 (SOC, SOC, Op_RegI, 19, r19->as_VMReg());
141 reg_def R19_H(SOC, SOC, Op_RegI, 19, r19->as_VMReg()->next());
142
143 reg_def R20 (SOC, SOC, Op_RegI, 20, r20->as_VMReg());
144 reg_def R20_H(SOC, SOC, Op_RegI, 20, r20->as_VMReg()->next());
145
146 reg_def R21 (SOC, SOC, Op_RegI, 21, r21->as_VMReg());
147 reg_def R21_H(SOC, SOC, Op_RegI, 21, r21->as_VMReg()->next());
148
149 reg_def R22 (SOC, SOC, Op_RegI, 22, r22->as_VMReg());
150 reg_def R22_H(SOC, SOC, Op_RegI, 22, r22->as_VMReg()->next());
151
152 reg_def R23 (SOC, SOC, Op_RegI, 23, r23->as_VMReg());
153 reg_def R23_H(SOC, SOC, Op_RegI, 23, r23->as_VMReg()->next());
154
155 reg_def R24 (SOC, SOC, Op_RegI, 24, r24->as_VMReg());
156 reg_def R24_H(SOC, SOC, Op_RegI, 24, r24->as_VMReg()->next());
157
158 reg_def R25 (SOC, SOC, Op_RegI, 25, r25->as_VMReg());
159 reg_def R25_H(SOC, SOC, Op_RegI, 25, r25->as_VMReg()->next());
160
161 reg_def R26 (SOC, SOC, Op_RegI, 26, r26->as_VMReg());
162 reg_def R26_H(SOC, SOC, Op_RegI, 26, r26->as_VMReg()->next());
163
164 reg_def R27 (SOC, SOC, Op_RegI, 27, r27->as_VMReg());
165 reg_def R27_H(SOC, SOC, Op_RegI, 27, r27->as_VMReg()->next());
166
167 reg_def R28 (SOC, SOC, Op_RegI, 28, r28->as_VMReg());
168 reg_def R28_H(SOC, SOC, Op_RegI, 28, r28->as_VMReg()->next());
169
170 reg_def R29 (SOC, SOC, Op_RegI, 29, r29->as_VMReg());
171 reg_def R29_H(SOC, SOC, Op_RegI, 29, r29->as_VMReg()->next());
172
173 reg_def R30 (SOC, SOC, Op_RegI, 30, r30->as_VMReg());
174 reg_def R30_H(SOC, SOC, Op_RegI, 30, r30->as_VMReg()->next());
175
176 reg_def R31 (SOC, SOC, Op_RegI, 31, r31->as_VMReg());
177 reg_def R31_H(SOC, SOC, Op_RegI, 31, r31->as_VMReg()->next());
178
179 // Floating Point Registers
180
181 // Specify priority of register selection within phases of register
182 // allocation. Highest priority is first. A useful heuristic is to
183 // give registers a low priority when they are required by machine
184 // instructions, like EAX and EDX on I486, and choose no-save registers
185 // before save-on-call, & save-on-call before save-on-entry. Registers
186 // which participate in fixed calling sequences should come last.
187 // Registers which are used as pairs must fall on an even boundary.
188
189 alloc_class chunk0(R10, R10_H,
190 R11, R11_H,
191 R8, R8_H,
192 R9, R9_H,
193 R12, R12_H,
194 RCX, RCX_H,
195 RBX, RBX_H,
196 RDI, RDI_H,
197 RDX, RDX_H,
198 RSI, RSI_H,
199 RAX, RAX_H,
200 RBP, RBP_H,
201 R13, R13_H,
202 R14, R14_H,
203 R15, R15_H,
204 R16, R16_H,
205 R17, R17_H,
206 R18, R18_H,
207 R19, R19_H,
208 R20, R20_H,
209 R21, R21_H,
210 R22, R22_H,
211 R23, R23_H,
212 R24, R24_H,
213 R25, R25_H,
214 R26, R26_H,
215 R27, R27_H,
216 R28, R28_H,
217 R29, R29_H,
218 R30, R30_H,
219 R31, R31_H,
220 RSP, RSP_H);
221
222
223 //----------Architecture Description Register Classes--------------------------
224 // Several register classes are automatically defined based upon information in
225 // this architecture description.
226 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
227 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
228 //
229
230 // Empty register class.
231 reg_class no_reg();
232
233 // Class for all pointer/long registers including APX extended GPRs.
234 reg_class all_reg(RAX, RAX_H,
235 RDX, RDX_H,
236 RBP, RBP_H,
237 RDI, RDI_H,
238 RSI, RSI_H,
239 RCX, RCX_H,
240 RBX, RBX_H,
241 RSP, RSP_H,
242 R8, R8_H,
243 R9, R9_H,
244 R10, R10_H,
245 R11, R11_H,
246 R12, R12_H,
247 R13, R13_H,
248 R14, R14_H,
249 R15, R15_H,
250 R16, R16_H,
251 R17, R17_H,
252 R18, R18_H,
253 R19, R19_H,
254 R20, R20_H,
255 R21, R21_H,
256 R22, R22_H,
257 R23, R23_H,
258 R24, R24_H,
259 R25, R25_H,
260 R26, R26_H,
261 R27, R27_H,
262 R28, R28_H,
263 R29, R29_H,
264 R30, R30_H,
265 R31, R31_H);
266
267 // Class for all int registers including APX extended GPRs.
268 reg_class all_int_reg(RAX
269 RDX,
270 RBP,
271 RDI,
272 RSI,
273 RCX,
274 RBX,
275 R8,
276 R9,
277 R10,
278 R11,
279 R12,
280 R13,
281 R14,
282 R16,
283 R17,
284 R18,
285 R19,
286 R20,
287 R21,
288 R22,
289 R23,
290 R24,
291 R25,
292 R26,
293 R27,
294 R28,
295 R29,
296 R30,
297 R31);
298
299 // Class for all pointer registers
300 reg_class any_reg %{
301 return _ANY_REG_mask;
302 %}
303
304 // Class for all pointer registers (excluding RSP)
305 reg_class ptr_reg %{
306 return _PTR_REG_mask;
307 %}
308
309 // Class for all pointer registers (excluding RSP and RBP)
310 reg_class ptr_reg_no_rbp %{
311 return _PTR_REG_NO_RBP_mask;
312 %}
313
314 // Class for all pointer registers (excluding RAX and RSP)
315 reg_class ptr_no_rax_reg %{
316 return _PTR_NO_RAX_REG_mask;
317 %}
318
319 // Class for all pointer registers (excluding RAX, RBX, and RSP)
320 reg_class ptr_no_rax_rbx_reg %{
321 return _PTR_NO_RAX_RBX_REG_mask;
322 %}
323
324 // Class for all long registers (excluding RSP)
325 reg_class long_reg %{
326 return _LONG_REG_mask;
327 %}
328
329 // Class for all long registers (excluding RAX, RDX and RSP)
330 reg_class long_no_rax_rdx_reg %{
331 return _LONG_NO_RAX_RDX_REG_mask;
332 %}
333
334 // Class for all long registers (excluding RCX and RSP)
335 reg_class long_no_rcx_reg %{
336 return _LONG_NO_RCX_REG_mask;
337 %}
338
339 // Class for all long registers (excluding RBP and R13)
340 reg_class long_no_rbp_r13_reg %{
341 return _LONG_NO_RBP_R13_REG_mask;
342 %}
343
344 // Class for all int registers (excluding RSP)
345 reg_class int_reg %{
346 return _INT_REG_mask;
347 %}
348
349 // Class for all int registers (excluding RAX, RDX, and RSP)
350 reg_class int_no_rax_rdx_reg %{
351 return _INT_NO_RAX_RDX_REG_mask;
352 %}
353
354 // Class for all int registers (excluding RCX and RSP)
355 reg_class int_no_rcx_reg %{
356 return _INT_NO_RCX_REG_mask;
357 %}
358
359 // Class for all int registers (excluding RBP and R13)
360 reg_class int_no_rbp_r13_reg %{
361 return _INT_NO_RBP_R13_REG_mask;
362 %}
363
364 // Singleton class for RAX pointer register
365 reg_class ptr_rax_reg(RAX, RAX_H);
366
367 // Singleton class for RBX pointer register
368 reg_class ptr_rbx_reg(RBX, RBX_H);
369
370 // Singleton class for RSI pointer register
371 reg_class ptr_rsi_reg(RSI, RSI_H);
372
373 // Singleton class for RBP pointer register
374 reg_class ptr_rbp_reg(RBP, RBP_H);
375
376 // Singleton class for RDI pointer register
377 reg_class ptr_rdi_reg(RDI, RDI_H);
378
379 // Singleton class for stack pointer
380 reg_class ptr_rsp_reg(RSP, RSP_H);
381
382 // Singleton class for TLS pointer
383 reg_class ptr_r15_reg(R15, R15_H);
384
385 // Singleton class for RAX long register
386 reg_class long_rax_reg(RAX, RAX_H);
387
388 // Singleton class for RCX long register
389 reg_class long_rcx_reg(RCX, RCX_H);
390
391 // Singleton class for RDX long register
392 reg_class long_rdx_reg(RDX, RDX_H);
393
394 // Singleton class for R11 long register
395 reg_class long_r11_reg(R11, R11_H);
396
397 // Singleton class for RAX int register
398 reg_class int_rax_reg(RAX);
399
400 // Singleton class for RBX int register
401 reg_class int_rbx_reg(RBX);
402
403 // Singleton class for RCX int register
404 reg_class int_rcx_reg(RCX);
405
406 // Singleton class for RDX int register
407 reg_class int_rdx_reg(RDX);
408
409 // Singleton class for RDI int register
410 reg_class int_rdi_reg(RDI);
411
412 // Singleton class for instruction pointer
413 // reg_class ip_reg(RIP);
414
415 %}
416
417 //----------SOURCE BLOCK-------------------------------------------------------
418 // This is a block of C++ code which provides values, functions, and
419 // definitions necessary in the rest of the architecture description
420
421 source_hpp %{
422
423 #include "peephole_x86_64.hpp"
424
425 %}
426
427 // Register masks
428 source_hpp %{
429
430 extern RegMask _ANY_REG_mask;
431 extern RegMask _PTR_REG_mask;
432 extern RegMask _PTR_REG_NO_RBP_mask;
433 extern RegMask _PTR_NO_RAX_REG_mask;
434 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
435 extern RegMask _LONG_REG_mask;
436 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
437 extern RegMask _LONG_NO_RCX_REG_mask;
438 extern RegMask _LONG_NO_RBP_R13_REG_mask;
439 extern RegMask _INT_REG_mask;
440 extern RegMask _INT_NO_RAX_RDX_REG_mask;
441 extern RegMask _INT_NO_RCX_REG_mask;
442 extern RegMask _INT_NO_RBP_R13_REG_mask;
443 extern RegMask _FLOAT_REG_mask;
444
445 extern RegMask _STACK_OR_PTR_REG_mask;
446 extern RegMask _STACK_OR_LONG_REG_mask;
447 extern RegMask _STACK_OR_INT_REG_mask;
448
449 inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
450 inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; }
451 inline const RegMask& STACK_OR_INT_REG_mask() { return _STACK_OR_INT_REG_mask; }
452
453 %}
454
455 source %{
456 #define RELOC_IMM64 Assembler::imm_operand
457 #define RELOC_DISP32 Assembler::disp32_operand
458
459 #define __ masm->
460
461 RegMask _ANY_REG_mask;
462 RegMask _PTR_REG_mask;
463 RegMask _PTR_REG_NO_RBP_mask;
464 RegMask _PTR_NO_RAX_REG_mask;
465 RegMask _PTR_NO_RAX_RBX_REG_mask;
466 RegMask _LONG_REG_mask;
467 RegMask _LONG_NO_RAX_RDX_REG_mask;
468 RegMask _LONG_NO_RCX_REG_mask;
469 RegMask _LONG_NO_RBP_R13_REG_mask;
470 RegMask _INT_REG_mask;
471 RegMask _INT_NO_RAX_RDX_REG_mask;
472 RegMask _INT_NO_RCX_REG_mask;
473 RegMask _INT_NO_RBP_R13_REG_mask;
474 RegMask _FLOAT_REG_mask;
475 RegMask _STACK_OR_PTR_REG_mask;
476 RegMask _STACK_OR_LONG_REG_mask;
477 RegMask _STACK_OR_INT_REG_mask;
478
479 static bool need_r12_heapbase() {
480 return UseCompressedOops;
481 }
482
483 void reg_mask_init() {
484 constexpr Register egprs[] = {r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30, r31};
485
486 // _ALL_REG_mask is generated by adlc from the all_reg register class below.
487 // We derive a number of subsets from it.
488 _ANY_REG_mask = _ALL_REG_mask;
489
490 if (PreserveFramePointer) {
491 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
492 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
493 }
494 if (need_r12_heapbase()) {
495 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
496 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
497 }
498
499 _PTR_REG_mask = _ANY_REG_mask;
500 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
501 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
502 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
503 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
504 if (!UseAPX) {
505 for (uint i = 0; i < sizeof(egprs)/sizeof(Register); i++) {
506 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(egprs[i]->as_VMReg()));
507 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(egprs[i]->as_VMReg()->next()));
508 }
509 }
510
511 _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
512 _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
513
514 _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
515 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
516 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
517
518 _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
519 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
520 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
521
522 _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
523 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
524 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
525
526
527 _LONG_REG_mask = _PTR_REG_mask;
528 _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
529 _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
530
531 _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
532 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
533 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
534 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
535 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
536
537 _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
538 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
539 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
540
541 _LONG_NO_RBP_R13_REG_mask = _LONG_REG_mask;
542 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
543 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
544 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()));
545 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()->next()));
546
547 _INT_REG_mask = _ALL_INT_REG_mask;
548 if (!UseAPX) {
549 for (uint i = 0; i < sizeof(egprs)/sizeof(Register); i++) {
550 _INT_REG_mask.Remove(OptoReg::as_OptoReg(egprs[i]->as_VMReg()));
551 }
552 }
553
554 if (PreserveFramePointer) {
555 _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
556 }
557 if (need_r12_heapbase()) {
558 _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
559 }
560
561 _STACK_OR_INT_REG_mask = _INT_REG_mask;
562 _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
563
564 _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
565 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
566 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
567
568 _INT_NO_RCX_REG_mask = _INT_REG_mask;
569 _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
570
571 _INT_NO_RBP_R13_REG_mask = _INT_REG_mask;
572 _INT_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
573 _INT_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()));
574
575 // _FLOAT_REG_LEGACY_mask/_FLOAT_REG_EVEX_mask is generated by adlc
576 // from the float_reg_legacy/float_reg_evex register class.
577 _FLOAT_REG_mask = VM_Version::supports_evex() ? _FLOAT_REG_EVEX_mask : _FLOAT_REG_LEGACY_mask;
578 }
579
580 static bool generate_vzeroupper(Compile* C) {
581 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
582 }
583
584 static int clear_avx_size() {
585 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
586 }
587
588 // !!!!! Special hack to get all types of calls to specify the byte offset
589 // from the start of the call to the point where the return address
590 // will point.
591 int MachCallStaticJavaNode::ret_addr_offset()
592 {
593 int offset = 5; // 5 bytes from start of call to where return address points
594 offset += clear_avx_size();
595 return offset;
596 }
597
598 int MachCallDynamicJavaNode::ret_addr_offset()
599 {
600 int offset = 15; // 15 bytes from start of call to where return address points
601 offset += clear_avx_size();
602 return offset;
603 }
604
605 int MachCallRuntimeNode::ret_addr_offset() {
606 int offset = 13; // movq r10,#addr; callq (r10)
607 if (this->ideal_Opcode() != Op_CallLeafVector) {
608 offset += clear_avx_size();
609 }
610 return offset;
611 }
612 //
613 // Compute padding required for nodes which need alignment
614 //
615
616 // The address of the call instruction needs to be 4-byte aligned to
617 // ensure that it does not span a cache line so that it can be patched.
618 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
619 {
620 current_offset += clear_avx_size(); // skip vzeroupper
621 current_offset += 1; // skip call opcode byte
622 return align_up(current_offset, alignment_required()) - current_offset;
623 }
624
625 // The address of the call instruction needs to be 4-byte aligned to
626 // ensure that it does not span a cache line so that it can be patched.
627 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
628 {
629 current_offset += clear_avx_size(); // skip vzeroupper
630 current_offset += 11; // skip movq instruction + call opcode byte
631 return align_up(current_offset, alignment_required()) - current_offset;
632 }
633
634 // This could be in MacroAssembler but it's fairly C2 specific
635 static void emit_cmpfp_fixup(MacroAssembler* masm) {
636 Label exit;
637 __ jccb(Assembler::noParity, exit);
638 __ pushf();
639 //
640 // comiss/ucomiss instructions set ZF,PF,CF flags and
641 // zero OF,AF,SF for NaN values.
642 // Fixup flags by zeroing ZF,PF so that compare of NaN
643 // values returns 'less than' result (CF is set).
644 // Leave the rest of flags unchanged.
645 //
646 // 7 6 5 4 3 2 1 0
647 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
648 // 0 0 1 0 1 0 1 1 (0x2B)
649 //
650 __ andq(Address(rsp, 0), 0xffffff2b);
651 __ popf();
652 __ bind(exit);
653 }
654
655 static void emit_cmpfp3(MacroAssembler* masm, Register dst) {
656 Label done;
657 __ movl(dst, -1);
658 __ jcc(Assembler::parity, done);
659 __ jcc(Assembler::below, done);
660 __ setcc(Assembler::notEqual, dst);
661 __ bind(done);
662 }
663
664 // Math.min() # Math.max()
665 // --------------------------
666 // ucomis[s/d] #
667 // ja -> b # a
668 // jp -> NaN # NaN
669 // jb -> a # b
670 // je #
671 // |-jz -> a | b # a & b
672 // | -> a #
673 static void emit_fp_min_max(MacroAssembler* masm, XMMRegister dst,
674 XMMRegister a, XMMRegister b,
675 XMMRegister xmmt, Register rt,
676 bool min, bool single) {
677
678 Label nan, zero, below, above, done;
679
680 if (single)
681 __ ucomiss(a, b);
682 else
683 __ ucomisd(a, b);
684
685 if (dst->encoding() != (min ? b : a)->encoding())
686 __ jccb(Assembler::above, above); // CF=0 & ZF=0
687 else
688 __ jccb(Assembler::above, done);
689
690 __ jccb(Assembler::parity, nan); // PF=1
691 __ jccb(Assembler::below, below); // CF=1
692
693 // equal
694 __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
695 if (single) {
696 __ ucomiss(a, xmmt);
697 __ jccb(Assembler::equal, zero);
698
699 __ movflt(dst, a);
700 __ jmp(done);
701 }
702 else {
703 __ ucomisd(a, xmmt);
704 __ jccb(Assembler::equal, zero);
705
706 __ movdbl(dst, a);
707 __ jmp(done);
708 }
709
710 __ bind(zero);
711 if (min)
712 __ vpor(dst, a, b, Assembler::AVX_128bit);
713 else
714 __ vpand(dst, a, b, Assembler::AVX_128bit);
715
716 __ jmp(done);
717
718 __ bind(above);
719 if (single)
720 __ movflt(dst, min ? b : a);
721 else
722 __ movdbl(dst, min ? b : a);
723
724 __ jmp(done);
725
726 __ bind(nan);
727 if (single) {
728 __ movl(rt, 0x7fc00000); // Float.NaN
729 __ movdl(dst, rt);
730 }
731 else {
732 __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
733 __ movdq(dst, rt);
734 }
735 __ jmp(done);
736
737 __ bind(below);
738 if (single)
739 __ movflt(dst, min ? a : b);
740 else
741 __ movdbl(dst, min ? a : b);
742
743 __ bind(done);
744 }
745
746 //=============================================================================
747 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
748
749 int ConstantTable::calculate_table_base_offset() const {
750 return 0; // absolute addressing, no offset
751 }
752
753 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
754 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
755 ShouldNotReachHere();
756 }
757
758 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
759 // Empty encoding
760 }
761
762 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
763 return 0;
764 }
765
766 #ifndef PRODUCT
767 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
768 st->print("# MachConstantBaseNode (empty encoding)");
769 }
770 #endif
771
772
773 //=============================================================================
774 #ifndef PRODUCT
775 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
776 Compile* C = ra_->C;
777
778 int framesize = C->output()->frame_size_in_bytes();
779 int bangsize = C->output()->bang_size_in_bytes();
780 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
781 // Remove wordSize for return addr which is already pushed.
782 framesize -= wordSize;
783
784 if (C->output()->need_stack_bang(bangsize)) {
785 framesize -= wordSize;
786 st->print("# stack bang (%d bytes)", bangsize);
787 st->print("\n\t");
788 st->print("pushq rbp\t# Save rbp");
789 if (PreserveFramePointer) {
790 st->print("\n\t");
791 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
792 }
793 if (framesize) {
794 st->print("\n\t");
795 st->print("subq rsp, #%d\t# Create frame",framesize);
796 }
797 } else {
798 st->print("subq rsp, #%d\t# Create frame",framesize);
799 st->print("\n\t");
800 framesize -= wordSize;
801 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
802 if (PreserveFramePointer) {
803 st->print("\n\t");
804 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
805 if (framesize > 0) {
806 st->print("\n\t");
807 st->print("addq rbp, #%d", framesize);
808 }
809 }
810 }
811
812 if (VerifyStackAtCalls) {
813 st->print("\n\t");
814 framesize -= wordSize;
815 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
816 #ifdef ASSERT
817 st->print("\n\t");
818 st->print("# stack alignment check");
819 #endif
820 }
821 if (C->stub_function() != nullptr) {
822 st->print("\n\t");
823 st->print("cmpl [r15_thread + #disarmed_guard_value_offset], #disarmed_guard_value\t");
824 st->print("\n\t");
825 st->print("je fast_entry\t");
826 st->print("\n\t");
827 st->print("call #nmethod_entry_barrier_stub\t");
828 st->print("\n\tfast_entry:");
829 }
830 st->cr();
831 }
832 #endif
833
834 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
835 Compile* C = ra_->C;
836
837 int framesize = C->output()->frame_size_in_bytes();
838 int bangsize = C->output()->bang_size_in_bytes();
839
840 if (C->clinit_barrier_on_entry()) {
841 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
842 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
843
844 Label L_skip_barrier;
845 Register klass = rscratch1;
846
847 __ mov_metadata(klass, C->method()->holder()->constant_encoding());
848 __ clinit_barrier(klass, &L_skip_barrier /*L_fast_path*/);
849
850 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
851
852 __ bind(L_skip_barrier);
853 }
854
855 __ verified_entry(framesize, C->output()->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != nullptr);
856
857 C->output()->set_frame_complete(__ offset());
858
859 if (C->has_mach_constant_base_node()) {
860 // NOTE: We set the table base offset here because users might be
861 // emitted before MachConstantBaseNode.
862 ConstantTable& constant_table = C->output()->constant_table();
863 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
864 }
865 }
866
867 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
868 {
869 return MachNode::size(ra_); // too many variables; just compute it
870 // the hard way
871 }
872
873 int MachPrologNode::reloc() const
874 {
875 return 0; // a large enough number
876 }
877
878 //=============================================================================
879 #ifndef PRODUCT
880 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
881 {
882 Compile* C = ra_->C;
883 if (generate_vzeroupper(C)) {
884 st->print("vzeroupper");
885 st->cr(); st->print("\t");
886 }
887
888 int framesize = C->output()->frame_size_in_bytes();
889 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
890 // Remove word for return adr already pushed
891 // and RBP
892 framesize -= 2*wordSize;
893
894 if (framesize) {
895 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
896 st->print("\t");
897 }
898
899 st->print_cr("popq rbp");
900 if (do_polling() && C->is_method_compilation()) {
901 st->print("\t");
902 st->print_cr("cmpq rsp, poll_offset[r15_thread] \n\t"
903 "ja #safepoint_stub\t"
904 "# Safepoint: poll for GC");
905 }
906 }
907 #endif
908
909 void MachEpilogNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
910 {
911 Compile* C = ra_->C;
912
913 if (generate_vzeroupper(C)) {
914 // Clear upper bits of YMM registers when current compiled code uses
915 // wide vectors to avoid AVX <-> SSE transition penalty during call.
916 __ vzeroupper();
917 }
918
919 int framesize = C->output()->frame_size_in_bytes();
920 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
921 // Remove word for return adr already pushed
922 // and RBP
923 framesize -= 2*wordSize;
924
925 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
926
927 if (framesize) {
928 __ addq(rsp, framesize);
929 }
930
931 __ popq(rbp);
932
933 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
934 __ reserved_stack_check();
935 }
936
937 if (do_polling() && C->is_method_compilation()) {
938 Label dummy_label;
939 Label* code_stub = &dummy_label;
940 if (!C->output()->in_scratch_emit_size()) {
941 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
942 C->output()->add_stub(stub);
943 code_stub = &stub->entry();
944 }
945 __ relocate(relocInfo::poll_return_type);
946 __ safepoint_poll(*code_stub, true /* at_return */, true /* in_nmethod */);
947 }
948 }
949
950 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
951 {
952 return MachNode::size(ra_); // too many variables; just compute it
953 // the hard way
954 }
955
956 int MachEpilogNode::reloc() const
957 {
958 return 2; // a large enough number
959 }
960
961 const Pipeline* MachEpilogNode::pipeline() const
962 {
963 return MachNode::pipeline_class();
964 }
965
966 //=============================================================================
967
968 enum RC {
969 rc_bad,
970 rc_int,
971 rc_kreg,
972 rc_float,
973 rc_stack
974 };
975
976 static enum RC rc_class(OptoReg::Name reg)
977 {
978 if( !OptoReg::is_valid(reg) ) return rc_bad;
979
980 if (OptoReg::is_stack(reg)) return rc_stack;
981
982 VMReg r = OptoReg::as_VMReg(reg);
983
984 if (r->is_Register()) return rc_int;
985
986 if (r->is_KRegister()) return rc_kreg;
987
988 assert(r->is_XMMRegister(), "must be");
989 return rc_float;
990 }
991
992 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
993 static void vec_mov_helper(C2_MacroAssembler *masm, int src_lo, int dst_lo,
994 int src_hi, int dst_hi, uint ireg, outputStream* st);
995
996 void vec_spill_helper(C2_MacroAssembler *masm, bool is_load,
997 int stack_offset, int reg, uint ireg, outputStream* st);
998
999 static void vec_stack_to_stack_helper(C2_MacroAssembler *masm, int src_offset,
1000 int dst_offset, uint ireg, outputStream* st) {
1001 if (masm) {
1002 switch (ireg) {
1003 case Op_VecS:
1004 __ movq(Address(rsp, -8), rax);
1005 __ movl(rax, Address(rsp, src_offset));
1006 __ movl(Address(rsp, dst_offset), rax);
1007 __ movq(rax, Address(rsp, -8));
1008 break;
1009 case Op_VecD:
1010 __ pushq(Address(rsp, src_offset));
1011 __ popq (Address(rsp, dst_offset));
1012 break;
1013 case Op_VecX:
1014 __ pushq(Address(rsp, src_offset));
1015 __ popq (Address(rsp, dst_offset));
1016 __ pushq(Address(rsp, src_offset+8));
1017 __ popq (Address(rsp, dst_offset+8));
1018 break;
1019 case Op_VecY:
1020 __ vmovdqu(Address(rsp, -32), xmm0);
1021 __ vmovdqu(xmm0, Address(rsp, src_offset));
1022 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1023 __ vmovdqu(xmm0, Address(rsp, -32));
1024 break;
1025 case Op_VecZ:
1026 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1027 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1028 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1029 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1030 break;
1031 default:
1032 ShouldNotReachHere();
1033 }
1034 #ifndef PRODUCT
1035 } else {
1036 switch (ireg) {
1037 case Op_VecS:
1038 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1039 "movl rax, [rsp + #%d]\n\t"
1040 "movl [rsp + #%d], rax\n\t"
1041 "movq rax, [rsp - #8]",
1042 src_offset, dst_offset);
1043 break;
1044 case Op_VecD:
1045 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1046 "popq [rsp + #%d]",
1047 src_offset, dst_offset);
1048 break;
1049 case Op_VecX:
1050 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1051 "popq [rsp + #%d]\n\t"
1052 "pushq [rsp + #%d]\n\t"
1053 "popq [rsp + #%d]",
1054 src_offset, dst_offset, src_offset+8, dst_offset+8);
1055 break;
1056 case Op_VecY:
1057 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1058 "vmovdqu xmm0, [rsp + #%d]\n\t"
1059 "vmovdqu [rsp + #%d], xmm0\n\t"
1060 "vmovdqu xmm0, [rsp - #32]",
1061 src_offset, dst_offset);
1062 break;
1063 case Op_VecZ:
1064 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1065 "vmovdqu xmm0, [rsp + #%d]\n\t"
1066 "vmovdqu [rsp + #%d], xmm0\n\t"
1067 "vmovdqu xmm0, [rsp - #64]",
1068 src_offset, dst_offset);
1069 break;
1070 default:
1071 ShouldNotReachHere();
1072 }
1073 #endif
1074 }
1075 }
1076
1077 uint MachSpillCopyNode::implementation(C2_MacroAssembler* masm,
1078 PhaseRegAlloc* ra_,
1079 bool do_size,
1080 outputStream* st) const {
1081 assert(masm != nullptr || st != nullptr, "sanity");
1082 // Get registers to move
1083 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1084 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1085 OptoReg::Name dst_second = ra_->get_reg_second(this);
1086 OptoReg::Name dst_first = ra_->get_reg_first(this);
1087
1088 enum RC src_second_rc = rc_class(src_second);
1089 enum RC src_first_rc = rc_class(src_first);
1090 enum RC dst_second_rc = rc_class(dst_second);
1091 enum RC dst_first_rc = rc_class(dst_first);
1092
1093 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1094 "must move at least 1 register" );
1095
1096 if (src_first == dst_first && src_second == dst_second) {
1097 // Self copy, no move
1098 return 0;
1099 }
1100 if (bottom_type()->isa_vect() != nullptr && bottom_type()->isa_vectmask() == nullptr) {
1101 uint ireg = ideal_reg();
1102 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1103 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1104 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1105 // mem -> mem
1106 int src_offset = ra_->reg2offset(src_first);
1107 int dst_offset = ra_->reg2offset(dst_first);
1108 vec_stack_to_stack_helper(masm, src_offset, dst_offset, ireg, st);
1109 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1110 vec_mov_helper(masm, src_first, dst_first, src_second, dst_second, ireg, st);
1111 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1112 int stack_offset = ra_->reg2offset(dst_first);
1113 vec_spill_helper(masm, false, stack_offset, src_first, ireg, st);
1114 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1115 int stack_offset = ra_->reg2offset(src_first);
1116 vec_spill_helper(masm, true, stack_offset, dst_first, ireg, st);
1117 } else {
1118 ShouldNotReachHere();
1119 }
1120 return 0;
1121 }
1122 if (src_first_rc == rc_stack) {
1123 // mem ->
1124 if (dst_first_rc == rc_stack) {
1125 // mem -> mem
1126 assert(src_second != dst_first, "overlap");
1127 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1128 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1129 // 64-bit
1130 int src_offset = ra_->reg2offset(src_first);
1131 int dst_offset = ra_->reg2offset(dst_first);
1132 if (masm) {
1133 __ pushq(Address(rsp, src_offset));
1134 __ popq (Address(rsp, dst_offset));
1135 #ifndef PRODUCT
1136 } else {
1137 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1138 "popq [rsp + #%d]",
1139 src_offset, dst_offset);
1140 #endif
1141 }
1142 } else {
1143 // 32-bit
1144 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1145 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1146 // No pushl/popl, so:
1147 int src_offset = ra_->reg2offset(src_first);
1148 int dst_offset = ra_->reg2offset(dst_first);
1149 if (masm) {
1150 __ movq(Address(rsp, -8), rax);
1151 __ movl(rax, Address(rsp, src_offset));
1152 __ movl(Address(rsp, dst_offset), rax);
1153 __ movq(rax, Address(rsp, -8));
1154 #ifndef PRODUCT
1155 } else {
1156 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1157 "movl rax, [rsp + #%d]\n\t"
1158 "movl [rsp + #%d], rax\n\t"
1159 "movq rax, [rsp - #8]",
1160 src_offset, dst_offset);
1161 #endif
1162 }
1163 }
1164 return 0;
1165 } else if (dst_first_rc == rc_int) {
1166 // mem -> gpr
1167 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1168 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1169 // 64-bit
1170 int offset = ra_->reg2offset(src_first);
1171 if (masm) {
1172 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1173 #ifndef PRODUCT
1174 } else {
1175 st->print("movq %s, [rsp + #%d]\t# spill",
1176 Matcher::regName[dst_first],
1177 offset);
1178 #endif
1179 }
1180 } else {
1181 // 32-bit
1182 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1183 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1184 int offset = ra_->reg2offset(src_first);
1185 if (masm) {
1186 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1187 #ifndef PRODUCT
1188 } else {
1189 st->print("movl %s, [rsp + #%d]\t# spill",
1190 Matcher::regName[dst_first],
1191 offset);
1192 #endif
1193 }
1194 }
1195 return 0;
1196 } else if (dst_first_rc == rc_float) {
1197 // mem-> xmm
1198 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1199 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1200 // 64-bit
1201 int offset = ra_->reg2offset(src_first);
1202 if (masm) {
1203 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1204 #ifndef PRODUCT
1205 } else {
1206 st->print("%s %s, [rsp + #%d]\t# spill",
1207 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1208 Matcher::regName[dst_first],
1209 offset);
1210 #endif
1211 }
1212 } else {
1213 // 32-bit
1214 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1215 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1216 int offset = ra_->reg2offset(src_first);
1217 if (masm) {
1218 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1219 #ifndef PRODUCT
1220 } else {
1221 st->print("movss %s, [rsp + #%d]\t# spill",
1222 Matcher::regName[dst_first],
1223 offset);
1224 #endif
1225 }
1226 }
1227 return 0;
1228 } else if (dst_first_rc == rc_kreg) {
1229 // mem -> kreg
1230 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1231 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1232 // 64-bit
1233 int offset = ra_->reg2offset(src_first);
1234 if (masm) {
1235 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1236 #ifndef PRODUCT
1237 } else {
1238 st->print("kmovq %s, [rsp + #%d]\t# spill",
1239 Matcher::regName[dst_first],
1240 offset);
1241 #endif
1242 }
1243 }
1244 return 0;
1245 }
1246 } else if (src_first_rc == rc_int) {
1247 // gpr ->
1248 if (dst_first_rc == rc_stack) {
1249 // gpr -> mem
1250 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1251 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1252 // 64-bit
1253 int offset = ra_->reg2offset(dst_first);
1254 if (masm) {
1255 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1256 #ifndef PRODUCT
1257 } else {
1258 st->print("movq [rsp + #%d], %s\t# spill",
1259 offset,
1260 Matcher::regName[src_first]);
1261 #endif
1262 }
1263 } else {
1264 // 32-bit
1265 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1266 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1267 int offset = ra_->reg2offset(dst_first);
1268 if (masm) {
1269 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1270 #ifndef PRODUCT
1271 } else {
1272 st->print("movl [rsp + #%d], %s\t# spill",
1273 offset,
1274 Matcher::regName[src_first]);
1275 #endif
1276 }
1277 }
1278 return 0;
1279 } else if (dst_first_rc == rc_int) {
1280 // gpr -> gpr
1281 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1282 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1283 // 64-bit
1284 if (masm) {
1285 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1286 as_Register(Matcher::_regEncode[src_first]));
1287 #ifndef PRODUCT
1288 } else {
1289 st->print("movq %s, %s\t# spill",
1290 Matcher::regName[dst_first],
1291 Matcher::regName[src_first]);
1292 #endif
1293 }
1294 return 0;
1295 } else {
1296 // 32-bit
1297 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1298 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1299 if (masm) {
1300 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1301 as_Register(Matcher::_regEncode[src_first]));
1302 #ifndef PRODUCT
1303 } else {
1304 st->print("movl %s, %s\t# spill",
1305 Matcher::regName[dst_first],
1306 Matcher::regName[src_first]);
1307 #endif
1308 }
1309 return 0;
1310 }
1311 } else if (dst_first_rc == rc_float) {
1312 // gpr -> xmm
1313 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1314 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1315 // 64-bit
1316 if (masm) {
1317 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1318 #ifndef PRODUCT
1319 } else {
1320 st->print("movdq %s, %s\t# spill",
1321 Matcher::regName[dst_first],
1322 Matcher::regName[src_first]);
1323 #endif
1324 }
1325 } else {
1326 // 32-bit
1327 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1328 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1329 if (masm) {
1330 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1331 #ifndef PRODUCT
1332 } else {
1333 st->print("movdl %s, %s\t# spill",
1334 Matcher::regName[dst_first],
1335 Matcher::regName[src_first]);
1336 #endif
1337 }
1338 }
1339 return 0;
1340 } else if (dst_first_rc == rc_kreg) {
1341 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1342 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1343 // 64-bit
1344 if (masm) {
1345 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1346 #ifndef PRODUCT
1347 } else {
1348 st->print("kmovq %s, %s\t# spill",
1349 Matcher::regName[dst_first],
1350 Matcher::regName[src_first]);
1351 #endif
1352 }
1353 }
1354 Unimplemented();
1355 return 0;
1356 }
1357 } else if (src_first_rc == rc_float) {
1358 // xmm ->
1359 if (dst_first_rc == rc_stack) {
1360 // xmm -> mem
1361 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1362 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1363 // 64-bit
1364 int offset = ra_->reg2offset(dst_first);
1365 if (masm) {
1366 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1367 #ifndef PRODUCT
1368 } else {
1369 st->print("movsd [rsp + #%d], %s\t# spill",
1370 offset,
1371 Matcher::regName[src_first]);
1372 #endif
1373 }
1374 } else {
1375 // 32-bit
1376 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1377 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1378 int offset = ra_->reg2offset(dst_first);
1379 if (masm) {
1380 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1381 #ifndef PRODUCT
1382 } else {
1383 st->print("movss [rsp + #%d], %s\t# spill",
1384 offset,
1385 Matcher::regName[src_first]);
1386 #endif
1387 }
1388 }
1389 return 0;
1390 } else if (dst_first_rc == rc_int) {
1391 // xmm -> gpr
1392 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1393 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1394 // 64-bit
1395 if (masm) {
1396 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1397 #ifndef PRODUCT
1398 } else {
1399 st->print("movdq %s, %s\t# spill",
1400 Matcher::regName[dst_first],
1401 Matcher::regName[src_first]);
1402 #endif
1403 }
1404 } else {
1405 // 32-bit
1406 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1407 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1408 if (masm) {
1409 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1410 #ifndef PRODUCT
1411 } else {
1412 st->print("movdl %s, %s\t# spill",
1413 Matcher::regName[dst_first],
1414 Matcher::regName[src_first]);
1415 #endif
1416 }
1417 }
1418 return 0;
1419 } else if (dst_first_rc == rc_float) {
1420 // xmm -> xmm
1421 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1422 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1423 // 64-bit
1424 if (masm) {
1425 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1426 #ifndef PRODUCT
1427 } else {
1428 st->print("%s %s, %s\t# spill",
1429 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1430 Matcher::regName[dst_first],
1431 Matcher::regName[src_first]);
1432 #endif
1433 }
1434 } else {
1435 // 32-bit
1436 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1437 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1438 if (masm) {
1439 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1440 #ifndef PRODUCT
1441 } else {
1442 st->print("%s %s, %s\t# spill",
1443 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1444 Matcher::regName[dst_first],
1445 Matcher::regName[src_first]);
1446 #endif
1447 }
1448 }
1449 return 0;
1450 } else if (dst_first_rc == rc_kreg) {
1451 assert(false, "Illegal spilling");
1452 return 0;
1453 }
1454 } else if (src_first_rc == rc_kreg) {
1455 if (dst_first_rc == rc_stack) {
1456 // mem -> kreg
1457 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1458 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1459 // 64-bit
1460 int offset = ra_->reg2offset(dst_first);
1461 if (masm) {
1462 __ kmov(Address(rsp, offset), as_KRegister(Matcher::_regEncode[src_first]));
1463 #ifndef PRODUCT
1464 } else {
1465 st->print("kmovq [rsp + #%d] , %s\t# spill",
1466 offset,
1467 Matcher::regName[src_first]);
1468 #endif
1469 }
1470 }
1471 return 0;
1472 } else if (dst_first_rc == rc_int) {
1473 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1474 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1475 // 64-bit
1476 if (masm) {
1477 __ kmov(as_Register(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
1478 #ifndef PRODUCT
1479 } else {
1480 st->print("kmovq %s, %s\t# spill",
1481 Matcher::regName[dst_first],
1482 Matcher::regName[src_first]);
1483 #endif
1484 }
1485 }
1486 Unimplemented();
1487 return 0;
1488 } else if (dst_first_rc == rc_kreg) {
1489 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1490 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1491 // 64-bit
1492 if (masm) {
1493 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
1494 #ifndef PRODUCT
1495 } else {
1496 st->print("kmovq %s, %s\t# spill",
1497 Matcher::regName[dst_first],
1498 Matcher::regName[src_first]);
1499 #endif
1500 }
1501 }
1502 return 0;
1503 } else if (dst_first_rc == rc_float) {
1504 assert(false, "Illegal spill");
1505 return 0;
1506 }
1507 }
1508
1509 assert(0," foo ");
1510 Unimplemented();
1511 return 0;
1512 }
1513
1514 #ifndef PRODUCT
1515 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1516 implementation(nullptr, ra_, false, st);
1517 }
1518 #endif
1519
1520 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1521 implementation(masm, ra_, false, nullptr);
1522 }
1523
1524 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1525 return MachNode::size(ra_);
1526 }
1527
1528 //=============================================================================
1529 #ifndef PRODUCT
1530 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1531 {
1532 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1533 int reg = ra_->get_reg_first(this);
1534 st->print("leaq %s, [rsp + #%d]\t# box lock",
1535 Matcher::regName[reg], offset);
1536 }
1537 #endif
1538
1539 void BoxLockNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1540 {
1541 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1542 int reg = ra_->get_encode(this);
1543
1544 __ lea(as_Register(reg), Address(rsp, offset));
1545 }
1546
1547 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1548 {
1549 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1550 if (ra_->get_encode(this) > 15) {
1551 return (offset < 0x80) ? 6 : 9; // REX2
1552 } else {
1553 return (offset < 0x80) ? 5 : 8; // REX
1554 }
1555 }
1556
1557 //=============================================================================
1558 #ifndef PRODUCT
1559 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1560 {
1561 if (UseCompressedClassPointers) {
1562 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1563 st->print_cr("\tcmpl rscratch1, [rax + CompiledICData::speculated_klass_offset()]\t # Inline cache check");
1564 } else {
1565 st->print_cr("movq rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1566 st->print_cr("\tcmpq rscratch1, [rax + CompiledICData::speculated_klass_offset()]\t # Inline cache check");
1567 }
1568 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1569 }
1570 #endif
1571
1572 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1573 {
1574 __ ic_check(InteriorEntryAlignment);
1575 }
1576
1577 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1578 {
1579 return MachNode::size(ra_); // too many variables; just compute it
1580 // the hard way
1581 }
1582
1583
1584 //=============================================================================
1585
1586 bool Matcher::supports_vector_calling_convention(void) {
1587 if (EnableVectorSupport && UseVectorStubs) {
1588 return true;
1589 }
1590 return false;
1591 }
1592
1593 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1594 assert(EnableVectorSupport && UseVectorStubs, "sanity");
1595 int lo = XMM0_num;
1596 int hi = XMM0b_num;
1597 if (ideal_reg == Op_VecX) hi = XMM0d_num;
1598 else if (ideal_reg == Op_VecY) hi = XMM0h_num;
1599 else if (ideal_reg == Op_VecZ) hi = XMM0p_num;
1600 return OptoRegPair(hi, lo);
1601 }
1602
1603 // Is this branch offset short enough that a short branch can be used?
1604 //
1605 // NOTE: If the platform does not provide any short branch variants, then
1606 // this method should return false for offset 0.
1607 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1608 // The passed offset is relative to address of the branch.
1609 // On 86 a branch displacement is calculated relative to address
1610 // of a next instruction.
1611 offset -= br_size;
1612
1613 // the short version of jmpConUCF2 contains multiple branches,
1614 // making the reach slightly less
1615 if (rule == jmpConUCF2_rule)
1616 return (-126 <= offset && offset <= 125);
1617 return (-128 <= offset && offset <= 127);
1618 }
1619
1620 // Return whether or not this register is ever used as an argument.
1621 // This function is used on startup to build the trampoline stubs in
1622 // generateOptoStub. Registers not mentioned will be killed by the VM
1623 // call in the trampoline, and arguments in those registers not be
1624 // available to the callee.
1625 bool Matcher::can_be_java_arg(int reg)
1626 {
1627 return
1628 reg == RDI_num || reg == RDI_H_num ||
1629 reg == RSI_num || reg == RSI_H_num ||
1630 reg == RDX_num || reg == RDX_H_num ||
1631 reg == RCX_num || reg == RCX_H_num ||
1632 reg == R8_num || reg == R8_H_num ||
1633 reg == R9_num || reg == R9_H_num ||
1634 reg == R12_num || reg == R12_H_num ||
1635 reg == XMM0_num || reg == XMM0b_num ||
1636 reg == XMM1_num || reg == XMM1b_num ||
1637 reg == XMM2_num || reg == XMM2b_num ||
1638 reg == XMM3_num || reg == XMM3b_num ||
1639 reg == XMM4_num || reg == XMM4b_num ||
1640 reg == XMM5_num || reg == XMM5b_num ||
1641 reg == XMM6_num || reg == XMM6b_num ||
1642 reg == XMM7_num || reg == XMM7b_num;
1643 }
1644
1645 bool Matcher::is_spillable_arg(int reg)
1646 {
1647 return can_be_java_arg(reg);
1648 }
1649
1650 uint Matcher::int_pressure_limit()
1651 {
1652 return (INTPRESSURE == -1) ? _INT_REG_mask.Size() : INTPRESSURE;
1653 }
1654
1655 uint Matcher::float_pressure_limit()
1656 {
1657 // After experiment around with different values, the following default threshold
1658 // works best for LCM's register pressure scheduling on x64.
1659 uint dec_count = VM_Version::supports_evex() ? 4 : 2;
1660 uint default_float_pressure_threshold = _FLOAT_REG_mask.Size() - dec_count;
1661 return (FLOATPRESSURE == -1) ? default_float_pressure_threshold : FLOATPRESSURE;
1662 }
1663
1664 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1665 // In 64 bit mode a code which use multiply when
1666 // devisor is constant is faster than hardware
1667 // DIV instruction (it uses MulHiL).
1668 return false;
1669 }
1670
1671 // Register for DIVI projection of divmodI
1672 RegMask Matcher::divI_proj_mask() {
1673 return INT_RAX_REG_mask();
1674 }
1675
1676 // Register for MODI projection of divmodI
1677 RegMask Matcher::modI_proj_mask() {
1678 return INT_RDX_REG_mask();
1679 }
1680
1681 // Register for DIVL projection of divmodL
1682 RegMask Matcher::divL_proj_mask() {
1683 return LONG_RAX_REG_mask();
1684 }
1685
1686 // Register for MODL projection of divmodL
1687 RegMask Matcher::modL_proj_mask() {
1688 return LONG_RDX_REG_mask();
1689 }
1690
1691 // Register for saving SP into on method handle invokes. Not used on x86_64.
1692 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1693 return NO_REG_mask();
1694 }
1695
1696 %}
1697
1698 //----------ENCODING BLOCK-----------------------------------------------------
1699 // This block specifies the encoding classes used by the compiler to
1700 // output byte streams. Encoding classes are parameterized macros
1701 // used by Machine Instruction Nodes in order to generate the bit
1702 // encoding of the instruction. Operands specify their base encoding
1703 // interface with the interface keyword. There are currently
1704 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1705 // COND_INTER. REG_INTER causes an operand to generate a function
1706 // which returns its register number when queried. CONST_INTER causes
1707 // an operand to generate a function which returns the value of the
1708 // constant when queried. MEMORY_INTER causes an operand to generate
1709 // four functions which return the Base Register, the Index Register,
1710 // the Scale Value, and the Offset Value of the operand when queried.
1711 // COND_INTER causes an operand to generate six functions which return
1712 // the encoding code (ie - encoding bits for the instruction)
1713 // associated with each basic boolean condition for a conditional
1714 // instruction.
1715 //
1716 // Instructions specify two basic values for encoding. Again, a
1717 // function is available to check if the constant displacement is an
1718 // oop. They use the ins_encode keyword to specify their encoding
1719 // classes (which must be a sequence of enc_class names, and their
1720 // parameters, specified in the encoding block), and they use the
1721 // opcode keyword to specify, in order, their primary, secondary, and
1722 // tertiary opcode. Only the opcode sections which a particular
1723 // instruction needs for encoding need to be specified.
1724 encode %{
1725 enc_class cdql_enc(no_rax_rdx_RegI div)
1726 %{
1727 // Full implementation of Java idiv and irem; checks for
1728 // special case as described in JVM spec., p.243 & p.271.
1729 //
1730 // normal case special case
1731 //
1732 // input : rax: dividend min_int
1733 // reg: divisor -1
1734 //
1735 // output: rax: quotient (= rax idiv reg) min_int
1736 // rdx: remainder (= rax irem reg) 0
1737 //
1738 // Code sequnce:
1739 //
1740 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1741 // 5: 75 07/08 jne e <normal>
1742 // 7: 33 d2 xor %edx,%edx
1743 // [div >= 8 -> offset + 1]
1744 // [REX_B]
1745 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1746 // c: 74 03/04 je 11 <done>
1747 // 000000000000000e <normal>:
1748 // e: 99 cltd
1749 // [div >= 8 -> offset + 1]
1750 // [REX_B]
1751 // f: f7 f9 idiv $div
1752 // 0000000000000011 <done>:
1753 Label normal;
1754 Label done;
1755
1756 // cmp $0x80000000,%eax
1757 __ cmpl(as_Register(RAX_enc), 0x80000000);
1758
1759 // jne e <normal>
1760 __ jccb(Assembler::notEqual, normal);
1761
1762 // xor %edx,%edx
1763 __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
1764
1765 // cmp $0xffffffffffffffff,%ecx
1766 __ cmpl($div$$Register, -1);
1767
1768 // je 11 <done>
1769 __ jccb(Assembler::equal, done);
1770
1771 // <normal>
1772 // cltd
1773 __ bind(normal);
1774 __ cdql();
1775
1776 // idivl
1777 // <done>
1778 __ idivl($div$$Register);
1779 __ bind(done);
1780 %}
1781
1782 enc_class cdqq_enc(no_rax_rdx_RegL div)
1783 %{
1784 // Full implementation of Java ldiv and lrem; checks for
1785 // special case as described in JVM spec., p.243 & p.271.
1786 //
1787 // normal case special case
1788 //
1789 // input : rax: dividend min_long
1790 // reg: divisor -1
1791 //
1792 // output: rax: quotient (= rax idiv reg) min_long
1793 // rdx: remainder (= rax irem reg) 0
1794 //
1795 // Code sequnce:
1796 //
1797 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1798 // 7: 00 00 80
1799 // a: 48 39 d0 cmp %rdx,%rax
1800 // d: 75 08 jne 17 <normal>
1801 // f: 33 d2 xor %edx,%edx
1802 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1803 // 15: 74 05 je 1c <done>
1804 // 0000000000000017 <normal>:
1805 // 17: 48 99 cqto
1806 // 19: 48 f7 f9 idiv $div
1807 // 000000000000001c <done>:
1808 Label normal;
1809 Label done;
1810
1811 // mov $0x8000000000000000,%rdx
1812 __ mov64(as_Register(RDX_enc), 0x8000000000000000);
1813
1814 // cmp %rdx,%rax
1815 __ cmpq(as_Register(RAX_enc), as_Register(RDX_enc));
1816
1817 // jne 17 <normal>
1818 __ jccb(Assembler::notEqual, normal);
1819
1820 // xor %edx,%edx
1821 __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
1822
1823 // cmp $0xffffffffffffffff,$div
1824 __ cmpq($div$$Register, -1);
1825
1826 // je 1e <done>
1827 __ jccb(Assembler::equal, done);
1828
1829 // <normal>
1830 // cqto
1831 __ bind(normal);
1832 __ cdqq();
1833
1834 // idivq (note: must be emitted by the user of this rule)
1835 // <done>
1836 __ idivq($div$$Register);
1837 __ bind(done);
1838 %}
1839
1840 enc_class clear_avx %{
1841 debug_only(int off0 = __ offset());
1842 if (generate_vzeroupper(Compile::current())) {
1843 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
1844 // Clear upper bits of YMM registers when current compiled code uses
1845 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1846 __ vzeroupper();
1847 }
1848 debug_only(int off1 = __ offset());
1849 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
1850 %}
1851
1852 enc_class Java_To_Runtime(method meth) %{
1853 // No relocation needed
1854 __ mov64(r10, (int64_t) $meth$$method);
1855 __ call(r10);
1856 __ post_call_nop();
1857 %}
1858
1859 enc_class Java_Static_Call(method meth)
1860 %{
1861 // JAVA STATIC CALL
1862 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
1863 // determine who we intended to call.
1864 if (!_method) {
1865 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, $meth$$method)));
1866 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
1867 // The NOP here is purely to ensure that eliding a call to
1868 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
1869 __ addr_nop_5();
1870 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
1871 } else {
1872 int method_index = resolved_method_index(masm);
1873 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
1874 : static_call_Relocation::spec(method_index);
1875 address mark = __ pc();
1876 int call_offset = __ offset();
1877 __ call(AddressLiteral(CAST_FROM_FN_PTR(address, $meth$$method), rspec));
1878 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
1879 // Calls of the same statically bound method can share
1880 // a stub to the interpreter.
1881 __ code()->shared_stub_to_interp_for(_method, call_offset);
1882 } else {
1883 // Emit stubs for static call.
1884 address stub = CompiledDirectCall::emit_to_interp_stub(masm, mark);
1885 __ clear_inst_mark();
1886 if (stub == nullptr) {
1887 ciEnv::current()->record_failure("CodeCache is full");
1888 return;
1889 }
1890 }
1891 }
1892 __ post_call_nop();
1893 %}
1894
1895 enc_class Java_Dynamic_Call(method meth) %{
1896 __ ic_call((address)$meth$$method, resolved_method_index(masm));
1897 __ post_call_nop();
1898 %}
1899
1900 %}
1901
1902
1903
1904 //----------FRAME--------------------------------------------------------------
1905 // Definition of frame structure and management information.
1906 //
1907 // S T A C K L A Y O U T Allocators stack-slot number
1908 // | (to get allocators register number
1909 // G Owned by | | v add OptoReg::stack0())
1910 // r CALLER | |
1911 // o | +--------+ pad to even-align allocators stack-slot
1912 // w V | pad0 | numbers; owned by CALLER
1913 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
1914 // h ^ | in | 5
1915 // | | args | 4 Holes in incoming args owned by SELF
1916 // | | | | 3
1917 // | | +--------+
1918 // V | | old out| Empty on Intel, window on Sparc
1919 // | old |preserve| Must be even aligned.
1920 // | SP-+--------+----> Matcher::_old_SP, even aligned
1921 // | | in | 3 area for Intel ret address
1922 // Owned by |preserve| Empty on Sparc.
1923 // SELF +--------+
1924 // | | pad2 | 2 pad to align old SP
1925 // | +--------+ 1
1926 // | | locks | 0
1927 // | +--------+----> OptoReg::stack0(), even aligned
1928 // | | pad1 | 11 pad to align new SP
1929 // | +--------+
1930 // | | | 10
1931 // | | spills | 9 spills
1932 // V | | 8 (pad0 slot for callee)
1933 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
1934 // ^ | out | 7
1935 // | | args | 6 Holes in outgoing args owned by CALLEE
1936 // Owned by +--------+
1937 // CALLEE | new out| 6 Empty on Intel, window on Sparc
1938 // | new |preserve| Must be even-aligned.
1939 // | SP-+--------+----> Matcher::_new_SP, even aligned
1940 // | | |
1941 //
1942 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
1943 // known from SELF's arguments and the Java calling convention.
1944 // Region 6-7 is determined per call site.
1945 // Note 2: If the calling convention leaves holes in the incoming argument
1946 // area, those holes are owned by SELF. Holes in the outgoing area
1947 // are owned by the CALLEE. Holes should not be necessary in the
1948 // incoming area, as the Java calling convention is completely under
1949 // the control of the AD file. Doubles can be sorted and packed to
1950 // avoid holes. Holes in the outgoing arguments may be necessary for
1951 // varargs C calling conventions.
1952 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
1953 // even aligned with pad0 as needed.
1954 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
1955 // region 6-11 is even aligned; it may be padded out more so that
1956 // the region from SP to FP meets the minimum stack alignment.
1957 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
1958 // alignment. Region 11, pad1, may be dynamically extended so that
1959 // SP meets the minimum alignment.
1960
1961 frame
1962 %{
1963 // These three registers define part of the calling convention
1964 // between compiled code and the interpreter.
1965 inline_cache_reg(RAX); // Inline Cache Register
1966
1967 // Optional: name the operand used by cisc-spilling to access
1968 // [stack_pointer + offset]
1969 cisc_spilling_operand_name(indOffset32);
1970
1971 // Number of stack slots consumed by locking an object
1972 sync_stack_slots(2);
1973
1974 // Compiled code's Frame Pointer
1975 frame_pointer(RSP);
1976
1977 // Interpreter stores its frame pointer in a register which is
1978 // stored to the stack by I2CAdaptors.
1979 // I2CAdaptors convert from interpreted java to compiled java.
1980 interpreter_frame_pointer(RBP);
1981
1982 // Stack alignment requirement
1983 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
1984
1985 // Number of outgoing stack slots killed above the out_preserve_stack_slots
1986 // for calls to C. Supports the var-args backing area for register parms.
1987 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
1988
1989 // The after-PROLOG location of the return address. Location of
1990 // return address specifies a type (REG or STACK) and a number
1991 // representing the register number (i.e. - use a register name) or
1992 // stack slot.
1993 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
1994 // Otherwise, it is above the locks and verification slot and alignment word
1995 return_addr(STACK - 2 +
1996 align_up((Compile::current()->in_preserve_stack_slots() +
1997 Compile::current()->fixed_slots()),
1998 stack_alignment_in_slots()));
1999
2000 // Location of compiled Java return values. Same as C for now.
2001 return_value
2002 %{
2003 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2004 "only return normal values");
2005
2006 static const int lo[Op_RegL + 1] = {
2007 0,
2008 0,
2009 RAX_num, // Op_RegN
2010 RAX_num, // Op_RegI
2011 RAX_num, // Op_RegP
2012 XMM0_num, // Op_RegF
2013 XMM0_num, // Op_RegD
2014 RAX_num // Op_RegL
2015 };
2016 static const int hi[Op_RegL + 1] = {
2017 0,
2018 0,
2019 OptoReg::Bad, // Op_RegN
2020 OptoReg::Bad, // Op_RegI
2021 RAX_H_num, // Op_RegP
2022 OptoReg::Bad, // Op_RegF
2023 XMM0b_num, // Op_RegD
2024 RAX_H_num // Op_RegL
2025 };
2026 // Excluded flags and vector registers.
2027 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 8, "missing type");
2028 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2029 %}
2030 %}
2031
2032 //----------ATTRIBUTES---------------------------------------------------------
2033 //----------Operand Attributes-------------------------------------------------
2034 op_attrib op_cost(0); // Required cost attribute
2035
2036 //----------Instruction Attributes---------------------------------------------
2037 ins_attrib ins_cost(100); // Required cost attribute
2038 ins_attrib ins_size(8); // Required size attribute (in bits)
2039 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2040 // a non-matching short branch variant
2041 // of some long branch?
2042 ins_attrib ins_alignment(1); // Required alignment attribute (must
2043 // be a power of 2) specifies the
2044 // alignment that some part of the
2045 // instruction (not necessarily the
2046 // start) requires. If > 1, a
2047 // compute_padding() function must be
2048 // provided for the instruction
2049
2050 //----------OPERANDS-----------------------------------------------------------
2051 // Operand definitions must precede instruction definitions for correct parsing
2052 // in the ADLC because operands constitute user defined types which are used in
2053 // instruction definitions.
2054
2055 //----------Simple Operands----------------------------------------------------
2056 // Immediate Operands
2057 // Integer Immediate
2058 operand immI()
2059 %{
2060 match(ConI);
2061
2062 op_cost(10);
2063 format %{ %}
2064 interface(CONST_INTER);
2065 %}
2066
2067 // Constant for test vs zero
2068 operand immI_0()
2069 %{
2070 predicate(n->get_int() == 0);
2071 match(ConI);
2072
2073 op_cost(0);
2074 format %{ %}
2075 interface(CONST_INTER);
2076 %}
2077
2078 // Constant for increment
2079 operand immI_1()
2080 %{
2081 predicate(n->get_int() == 1);
2082 match(ConI);
2083
2084 op_cost(0);
2085 format %{ %}
2086 interface(CONST_INTER);
2087 %}
2088
2089 // Constant for decrement
2090 operand immI_M1()
2091 %{
2092 predicate(n->get_int() == -1);
2093 match(ConI);
2094
2095 op_cost(0);
2096 format %{ %}
2097 interface(CONST_INTER);
2098 %}
2099
2100 operand immI_2()
2101 %{
2102 predicate(n->get_int() == 2);
2103 match(ConI);
2104
2105 op_cost(0);
2106 format %{ %}
2107 interface(CONST_INTER);
2108 %}
2109
2110 operand immI_4()
2111 %{
2112 predicate(n->get_int() == 4);
2113 match(ConI);
2114
2115 op_cost(0);
2116 format %{ %}
2117 interface(CONST_INTER);
2118 %}
2119
2120 operand immI_8()
2121 %{
2122 predicate(n->get_int() == 8);
2123 match(ConI);
2124
2125 op_cost(0);
2126 format %{ %}
2127 interface(CONST_INTER);
2128 %}
2129
2130 // Valid scale values for addressing modes
2131 operand immI2()
2132 %{
2133 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2134 match(ConI);
2135
2136 format %{ %}
2137 interface(CONST_INTER);
2138 %}
2139
2140 operand immU7()
2141 %{
2142 predicate((0 <= n->get_int()) && (n->get_int() <= 0x7F));
2143 match(ConI);
2144
2145 op_cost(5);
2146 format %{ %}
2147 interface(CONST_INTER);
2148 %}
2149
2150 operand immI8()
2151 %{
2152 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2153 match(ConI);
2154
2155 op_cost(5);
2156 format %{ %}
2157 interface(CONST_INTER);
2158 %}
2159
2160 operand immU8()
2161 %{
2162 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2163 match(ConI);
2164
2165 op_cost(5);
2166 format %{ %}
2167 interface(CONST_INTER);
2168 %}
2169
2170 operand immI16()
2171 %{
2172 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2173 match(ConI);
2174
2175 op_cost(10);
2176 format %{ %}
2177 interface(CONST_INTER);
2178 %}
2179
2180 // Int Immediate non-negative
2181 operand immU31()
2182 %{
2183 predicate(n->get_int() >= 0);
2184 match(ConI);
2185
2186 op_cost(0);
2187 format %{ %}
2188 interface(CONST_INTER);
2189 %}
2190
2191 // Pointer Immediate
2192 operand immP()
2193 %{
2194 match(ConP);
2195
2196 op_cost(10);
2197 format %{ %}
2198 interface(CONST_INTER);
2199 %}
2200
2201 // Null Pointer Immediate
2202 operand immP0()
2203 %{
2204 predicate(n->get_ptr() == 0);
2205 match(ConP);
2206
2207 op_cost(5);
2208 format %{ %}
2209 interface(CONST_INTER);
2210 %}
2211
2212 // Pointer Immediate
2213 operand immN() %{
2214 match(ConN);
2215
2216 op_cost(10);
2217 format %{ %}
2218 interface(CONST_INTER);
2219 %}
2220
2221 operand immNKlass() %{
2222 match(ConNKlass);
2223
2224 op_cost(10);
2225 format %{ %}
2226 interface(CONST_INTER);
2227 %}
2228
2229 // Null Pointer Immediate
2230 operand immN0() %{
2231 predicate(n->get_narrowcon() == 0);
2232 match(ConN);
2233
2234 op_cost(5);
2235 format %{ %}
2236 interface(CONST_INTER);
2237 %}
2238
2239 operand immP31()
2240 %{
2241 predicate(n->as_Type()->type()->reloc() == relocInfo::none
2242 && (n->get_ptr() >> 31) == 0);
2243 match(ConP);
2244
2245 op_cost(5);
2246 format %{ %}
2247 interface(CONST_INTER);
2248 %}
2249
2250
2251 // Long Immediate
2252 operand immL()
2253 %{
2254 match(ConL);
2255
2256 op_cost(20);
2257 format %{ %}
2258 interface(CONST_INTER);
2259 %}
2260
2261 // Long Immediate 8-bit
2262 operand immL8()
2263 %{
2264 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
2265 match(ConL);
2266
2267 op_cost(5);
2268 format %{ %}
2269 interface(CONST_INTER);
2270 %}
2271
2272 // Long Immediate 32-bit unsigned
2273 operand immUL32()
2274 %{
2275 predicate(n->get_long() == (unsigned int) (n->get_long()));
2276 match(ConL);
2277
2278 op_cost(10);
2279 format %{ %}
2280 interface(CONST_INTER);
2281 %}
2282
2283 // Long Immediate 32-bit signed
2284 operand immL32()
2285 %{
2286 predicate(n->get_long() == (int) (n->get_long()));
2287 match(ConL);
2288
2289 op_cost(15);
2290 format %{ %}
2291 interface(CONST_INTER);
2292 %}
2293
2294 operand immL_Pow2()
2295 %{
2296 predicate(is_power_of_2((julong)n->get_long()));
2297 match(ConL);
2298
2299 op_cost(15);
2300 format %{ %}
2301 interface(CONST_INTER);
2302 %}
2303
2304 operand immL_NotPow2()
2305 %{
2306 predicate(is_power_of_2((julong)~n->get_long()));
2307 match(ConL);
2308
2309 op_cost(15);
2310 format %{ %}
2311 interface(CONST_INTER);
2312 %}
2313
2314 // Long Immediate zero
2315 operand immL0()
2316 %{
2317 predicate(n->get_long() == 0L);
2318 match(ConL);
2319
2320 op_cost(10);
2321 format %{ %}
2322 interface(CONST_INTER);
2323 %}
2324
2325 // Constant for increment
2326 operand immL1()
2327 %{
2328 predicate(n->get_long() == 1);
2329 match(ConL);
2330
2331 format %{ %}
2332 interface(CONST_INTER);
2333 %}
2334
2335 // Constant for decrement
2336 operand immL_M1()
2337 %{
2338 predicate(n->get_long() == -1);
2339 match(ConL);
2340
2341 format %{ %}
2342 interface(CONST_INTER);
2343 %}
2344
2345 // Long Immediate: low 32-bit mask
2346 operand immL_32bits()
2347 %{
2348 predicate(n->get_long() == 0xFFFFFFFFL);
2349 match(ConL);
2350 op_cost(20);
2351
2352 format %{ %}
2353 interface(CONST_INTER);
2354 %}
2355
2356 // Int Immediate: 2^n-1, positive
2357 operand immI_Pow2M1()
2358 %{
2359 predicate((n->get_int() > 0)
2360 && is_power_of_2((juint)n->get_int() + 1));
2361 match(ConI);
2362
2363 op_cost(20);
2364 format %{ %}
2365 interface(CONST_INTER);
2366 %}
2367
2368 // Float Immediate zero
2369 operand immF0()
2370 %{
2371 predicate(jint_cast(n->getf()) == 0);
2372 match(ConF);
2373
2374 op_cost(5);
2375 format %{ %}
2376 interface(CONST_INTER);
2377 %}
2378
2379 // Float Immediate
2380 operand immF()
2381 %{
2382 match(ConF);
2383
2384 op_cost(15);
2385 format %{ %}
2386 interface(CONST_INTER);
2387 %}
2388
2389 // Half Float Immediate
2390 operand immH()
2391 %{
2392 match(ConH);
2393
2394 op_cost(15);
2395 format %{ %}
2396 interface(CONST_INTER);
2397 %}
2398
2399 // Double Immediate zero
2400 operand immD0()
2401 %{
2402 predicate(jlong_cast(n->getd()) == 0);
2403 match(ConD);
2404
2405 op_cost(5);
2406 format %{ %}
2407 interface(CONST_INTER);
2408 %}
2409
2410 // Double Immediate
2411 operand immD()
2412 %{
2413 match(ConD);
2414
2415 op_cost(15);
2416 format %{ %}
2417 interface(CONST_INTER);
2418 %}
2419
2420 // Immediates for special shifts (sign extend)
2421
2422 // Constants for increment
2423 operand immI_16()
2424 %{
2425 predicate(n->get_int() == 16);
2426 match(ConI);
2427
2428 format %{ %}
2429 interface(CONST_INTER);
2430 %}
2431
2432 operand immI_24()
2433 %{
2434 predicate(n->get_int() == 24);
2435 match(ConI);
2436
2437 format %{ %}
2438 interface(CONST_INTER);
2439 %}
2440
2441 // Constant for byte-wide masking
2442 operand immI_255()
2443 %{
2444 predicate(n->get_int() == 255);
2445 match(ConI);
2446
2447 format %{ %}
2448 interface(CONST_INTER);
2449 %}
2450
2451 // Constant for short-wide masking
2452 operand immI_65535()
2453 %{
2454 predicate(n->get_int() == 65535);
2455 match(ConI);
2456
2457 format %{ %}
2458 interface(CONST_INTER);
2459 %}
2460
2461 // Constant for byte-wide masking
2462 operand immL_255()
2463 %{
2464 predicate(n->get_long() == 255);
2465 match(ConL);
2466
2467 format %{ %}
2468 interface(CONST_INTER);
2469 %}
2470
2471 // Constant for short-wide masking
2472 operand immL_65535()
2473 %{
2474 predicate(n->get_long() == 65535);
2475 match(ConL);
2476
2477 format %{ %}
2478 interface(CONST_INTER);
2479 %}
2480
2481 operand kReg()
2482 %{
2483 constraint(ALLOC_IN_RC(vectmask_reg));
2484 match(RegVectMask);
2485 format %{%}
2486 interface(REG_INTER);
2487 %}
2488
2489 // Register Operands
2490 // Integer Register
2491 operand rRegI()
2492 %{
2493 constraint(ALLOC_IN_RC(int_reg));
2494 match(RegI);
2495
2496 match(rax_RegI);
2497 match(rbx_RegI);
2498 match(rcx_RegI);
2499 match(rdx_RegI);
2500 match(rdi_RegI);
2501
2502 format %{ %}
2503 interface(REG_INTER);
2504 %}
2505
2506 // Special Registers
2507 operand rax_RegI()
2508 %{
2509 constraint(ALLOC_IN_RC(int_rax_reg));
2510 match(RegI);
2511 match(rRegI);
2512
2513 format %{ "RAX" %}
2514 interface(REG_INTER);
2515 %}
2516
2517 // Special Registers
2518 operand rbx_RegI()
2519 %{
2520 constraint(ALLOC_IN_RC(int_rbx_reg));
2521 match(RegI);
2522 match(rRegI);
2523
2524 format %{ "RBX" %}
2525 interface(REG_INTER);
2526 %}
2527
2528 operand rcx_RegI()
2529 %{
2530 constraint(ALLOC_IN_RC(int_rcx_reg));
2531 match(RegI);
2532 match(rRegI);
2533
2534 format %{ "RCX" %}
2535 interface(REG_INTER);
2536 %}
2537
2538 operand rdx_RegI()
2539 %{
2540 constraint(ALLOC_IN_RC(int_rdx_reg));
2541 match(RegI);
2542 match(rRegI);
2543
2544 format %{ "RDX" %}
2545 interface(REG_INTER);
2546 %}
2547
2548 operand rdi_RegI()
2549 %{
2550 constraint(ALLOC_IN_RC(int_rdi_reg));
2551 match(RegI);
2552 match(rRegI);
2553
2554 format %{ "RDI" %}
2555 interface(REG_INTER);
2556 %}
2557
2558 operand no_rax_rdx_RegI()
2559 %{
2560 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
2561 match(RegI);
2562 match(rbx_RegI);
2563 match(rcx_RegI);
2564 match(rdi_RegI);
2565
2566 format %{ %}
2567 interface(REG_INTER);
2568 %}
2569
2570 operand no_rbp_r13_RegI()
2571 %{
2572 constraint(ALLOC_IN_RC(int_no_rbp_r13_reg));
2573 match(RegI);
2574 match(rRegI);
2575 match(rax_RegI);
2576 match(rbx_RegI);
2577 match(rcx_RegI);
2578 match(rdx_RegI);
2579 match(rdi_RegI);
2580
2581 format %{ %}
2582 interface(REG_INTER);
2583 %}
2584
2585 // Pointer Register
2586 operand any_RegP()
2587 %{
2588 constraint(ALLOC_IN_RC(any_reg));
2589 match(RegP);
2590 match(rax_RegP);
2591 match(rbx_RegP);
2592 match(rdi_RegP);
2593 match(rsi_RegP);
2594 match(rbp_RegP);
2595 match(r15_RegP);
2596 match(rRegP);
2597
2598 format %{ %}
2599 interface(REG_INTER);
2600 %}
2601
2602 operand rRegP()
2603 %{
2604 constraint(ALLOC_IN_RC(ptr_reg));
2605 match(RegP);
2606 match(rax_RegP);
2607 match(rbx_RegP);
2608 match(rdi_RegP);
2609 match(rsi_RegP);
2610 match(rbp_RegP); // See Q&A below about
2611 match(r15_RegP); // r15_RegP and rbp_RegP.
2612
2613 format %{ %}
2614 interface(REG_INTER);
2615 %}
2616
2617 operand rRegN() %{
2618 constraint(ALLOC_IN_RC(int_reg));
2619 match(RegN);
2620
2621 format %{ %}
2622 interface(REG_INTER);
2623 %}
2624
2625 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
2626 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
2627 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
2628 // The output of an instruction is controlled by the allocator, which respects
2629 // register class masks, not match rules. Unless an instruction mentions
2630 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
2631 // by the allocator as an input.
2632 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
2633 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
2634 // result, RBP is not included in the output of the instruction either.
2635
2636 // This operand is not allowed to use RBP even if
2637 // RBP is not used to hold the frame pointer.
2638 operand no_rbp_RegP()
2639 %{
2640 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
2641 match(RegP);
2642 match(rbx_RegP);
2643 match(rsi_RegP);
2644 match(rdi_RegP);
2645
2646 format %{ %}
2647 interface(REG_INTER);
2648 %}
2649
2650 // Special Registers
2651 // Return a pointer value
2652 operand rax_RegP()
2653 %{
2654 constraint(ALLOC_IN_RC(ptr_rax_reg));
2655 match(RegP);
2656 match(rRegP);
2657
2658 format %{ %}
2659 interface(REG_INTER);
2660 %}
2661
2662 // Special Registers
2663 // Return a compressed pointer value
2664 operand rax_RegN()
2665 %{
2666 constraint(ALLOC_IN_RC(int_rax_reg));
2667 match(RegN);
2668 match(rRegN);
2669
2670 format %{ %}
2671 interface(REG_INTER);
2672 %}
2673
2674 // Used in AtomicAdd
2675 operand rbx_RegP()
2676 %{
2677 constraint(ALLOC_IN_RC(ptr_rbx_reg));
2678 match(RegP);
2679 match(rRegP);
2680
2681 format %{ %}
2682 interface(REG_INTER);
2683 %}
2684
2685 operand rsi_RegP()
2686 %{
2687 constraint(ALLOC_IN_RC(ptr_rsi_reg));
2688 match(RegP);
2689 match(rRegP);
2690
2691 format %{ %}
2692 interface(REG_INTER);
2693 %}
2694
2695 operand rbp_RegP()
2696 %{
2697 constraint(ALLOC_IN_RC(ptr_rbp_reg));
2698 match(RegP);
2699 match(rRegP);
2700
2701 format %{ %}
2702 interface(REG_INTER);
2703 %}
2704
2705 // Used in rep stosq
2706 operand rdi_RegP()
2707 %{
2708 constraint(ALLOC_IN_RC(ptr_rdi_reg));
2709 match(RegP);
2710 match(rRegP);
2711
2712 format %{ %}
2713 interface(REG_INTER);
2714 %}
2715
2716 operand r15_RegP()
2717 %{
2718 constraint(ALLOC_IN_RC(ptr_r15_reg));
2719 match(RegP);
2720 match(rRegP);
2721
2722 format %{ %}
2723 interface(REG_INTER);
2724 %}
2725
2726 operand rRegL()
2727 %{
2728 constraint(ALLOC_IN_RC(long_reg));
2729 match(RegL);
2730 match(rax_RegL);
2731 match(rdx_RegL);
2732
2733 format %{ %}
2734 interface(REG_INTER);
2735 %}
2736
2737 // Special Registers
2738 operand no_rax_rdx_RegL()
2739 %{
2740 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
2741 match(RegL);
2742 match(rRegL);
2743
2744 format %{ %}
2745 interface(REG_INTER);
2746 %}
2747
2748 operand rax_RegL()
2749 %{
2750 constraint(ALLOC_IN_RC(long_rax_reg));
2751 match(RegL);
2752 match(rRegL);
2753
2754 format %{ "RAX" %}
2755 interface(REG_INTER);
2756 %}
2757
2758 operand rcx_RegL()
2759 %{
2760 constraint(ALLOC_IN_RC(long_rcx_reg));
2761 match(RegL);
2762 match(rRegL);
2763
2764 format %{ %}
2765 interface(REG_INTER);
2766 %}
2767
2768 operand rdx_RegL()
2769 %{
2770 constraint(ALLOC_IN_RC(long_rdx_reg));
2771 match(RegL);
2772 match(rRegL);
2773
2774 format %{ %}
2775 interface(REG_INTER);
2776 %}
2777
2778 operand r11_RegL()
2779 %{
2780 constraint(ALLOC_IN_RC(long_r11_reg));
2781 match(RegL);
2782 match(rRegL);
2783
2784 format %{ %}
2785 interface(REG_INTER);
2786 %}
2787
2788 operand no_rbp_r13_RegL()
2789 %{
2790 constraint(ALLOC_IN_RC(long_no_rbp_r13_reg));
2791 match(RegL);
2792 match(rRegL);
2793 match(rax_RegL);
2794 match(rcx_RegL);
2795 match(rdx_RegL);
2796
2797 format %{ %}
2798 interface(REG_INTER);
2799 %}
2800
2801 // Flags register, used as output of compare instructions
2802 operand rFlagsReg()
2803 %{
2804 constraint(ALLOC_IN_RC(int_flags));
2805 match(RegFlags);
2806
2807 format %{ "RFLAGS" %}
2808 interface(REG_INTER);
2809 %}
2810
2811 // Flags register, used as output of FLOATING POINT compare instructions
2812 operand rFlagsRegU()
2813 %{
2814 constraint(ALLOC_IN_RC(int_flags));
2815 match(RegFlags);
2816
2817 format %{ "RFLAGS_U" %}
2818 interface(REG_INTER);
2819 %}
2820
2821 operand rFlagsRegUCF() %{
2822 constraint(ALLOC_IN_RC(int_flags));
2823 match(RegFlags);
2824 predicate(false);
2825
2826 format %{ "RFLAGS_U_CF" %}
2827 interface(REG_INTER);
2828 %}
2829
2830 // Float register operands
2831 operand regF() %{
2832 constraint(ALLOC_IN_RC(float_reg));
2833 match(RegF);
2834
2835 format %{ %}
2836 interface(REG_INTER);
2837 %}
2838
2839 // Float register operands
2840 operand legRegF() %{
2841 constraint(ALLOC_IN_RC(float_reg_legacy));
2842 match(RegF);
2843
2844 format %{ %}
2845 interface(REG_INTER);
2846 %}
2847
2848 // Float register operands
2849 operand vlRegF() %{
2850 constraint(ALLOC_IN_RC(float_reg_vl));
2851 match(RegF);
2852
2853 format %{ %}
2854 interface(REG_INTER);
2855 %}
2856
2857 // Double register operands
2858 operand regD() %{
2859 constraint(ALLOC_IN_RC(double_reg));
2860 match(RegD);
2861
2862 format %{ %}
2863 interface(REG_INTER);
2864 %}
2865
2866 // Double register operands
2867 operand legRegD() %{
2868 constraint(ALLOC_IN_RC(double_reg_legacy));
2869 match(RegD);
2870
2871 format %{ %}
2872 interface(REG_INTER);
2873 %}
2874
2875 // Double register operands
2876 operand vlRegD() %{
2877 constraint(ALLOC_IN_RC(double_reg_vl));
2878 match(RegD);
2879
2880 format %{ %}
2881 interface(REG_INTER);
2882 %}
2883
2884 //----------Memory Operands----------------------------------------------------
2885 // Direct Memory Operand
2886 // operand direct(immP addr)
2887 // %{
2888 // match(addr);
2889
2890 // format %{ "[$addr]" %}
2891 // interface(MEMORY_INTER) %{
2892 // base(0xFFFFFFFF);
2893 // index(0x4);
2894 // scale(0x0);
2895 // disp($addr);
2896 // %}
2897 // %}
2898
2899 // Indirect Memory Operand
2900 operand indirect(any_RegP reg)
2901 %{
2902 constraint(ALLOC_IN_RC(ptr_reg));
2903 match(reg);
2904
2905 format %{ "[$reg]" %}
2906 interface(MEMORY_INTER) %{
2907 base($reg);
2908 index(0x4);
2909 scale(0x0);
2910 disp(0x0);
2911 %}
2912 %}
2913
2914 // Indirect Memory Plus Short Offset Operand
2915 operand indOffset8(any_RegP reg, immL8 off)
2916 %{
2917 constraint(ALLOC_IN_RC(ptr_reg));
2918 match(AddP reg off);
2919
2920 format %{ "[$reg + $off (8-bit)]" %}
2921 interface(MEMORY_INTER) %{
2922 base($reg);
2923 index(0x4);
2924 scale(0x0);
2925 disp($off);
2926 %}
2927 %}
2928
2929 // Indirect Memory Plus Long Offset Operand
2930 operand indOffset32(any_RegP reg, immL32 off)
2931 %{
2932 constraint(ALLOC_IN_RC(ptr_reg));
2933 match(AddP reg off);
2934
2935 format %{ "[$reg + $off (32-bit)]" %}
2936 interface(MEMORY_INTER) %{
2937 base($reg);
2938 index(0x4);
2939 scale(0x0);
2940 disp($off);
2941 %}
2942 %}
2943
2944 // Indirect Memory Plus Index Register Plus Offset Operand
2945 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
2946 %{
2947 constraint(ALLOC_IN_RC(ptr_reg));
2948 match(AddP (AddP reg lreg) off);
2949
2950 op_cost(10);
2951 format %{"[$reg + $off + $lreg]" %}
2952 interface(MEMORY_INTER) %{
2953 base($reg);
2954 index($lreg);
2955 scale(0x0);
2956 disp($off);
2957 %}
2958 %}
2959
2960 // Indirect Memory Plus Index Register Plus Offset Operand
2961 operand indIndex(any_RegP reg, rRegL lreg)
2962 %{
2963 constraint(ALLOC_IN_RC(ptr_reg));
2964 match(AddP reg lreg);
2965
2966 op_cost(10);
2967 format %{"[$reg + $lreg]" %}
2968 interface(MEMORY_INTER) %{
2969 base($reg);
2970 index($lreg);
2971 scale(0x0);
2972 disp(0x0);
2973 %}
2974 %}
2975
2976 // Indirect Memory Times Scale Plus Index Register
2977 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
2978 %{
2979 constraint(ALLOC_IN_RC(ptr_reg));
2980 match(AddP reg (LShiftL lreg scale));
2981
2982 op_cost(10);
2983 format %{"[$reg + $lreg << $scale]" %}
2984 interface(MEMORY_INTER) %{
2985 base($reg);
2986 index($lreg);
2987 scale($scale);
2988 disp(0x0);
2989 %}
2990 %}
2991
2992 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
2993 %{
2994 constraint(ALLOC_IN_RC(ptr_reg));
2995 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
2996 match(AddP reg (LShiftL (ConvI2L idx) scale));
2997
2998 op_cost(10);
2999 format %{"[$reg + pos $idx << $scale]" %}
3000 interface(MEMORY_INTER) %{
3001 base($reg);
3002 index($idx);
3003 scale($scale);
3004 disp(0x0);
3005 %}
3006 %}
3007
3008 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3009 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3010 %{
3011 constraint(ALLOC_IN_RC(ptr_reg));
3012 match(AddP (AddP reg (LShiftL lreg scale)) off);
3013
3014 op_cost(10);
3015 format %{"[$reg + $off + $lreg << $scale]" %}
3016 interface(MEMORY_INTER) %{
3017 base($reg);
3018 index($lreg);
3019 scale($scale);
3020 disp($off);
3021 %}
3022 %}
3023
3024 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3025 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3026 %{
3027 constraint(ALLOC_IN_RC(ptr_reg));
3028 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3029 match(AddP (AddP reg (ConvI2L idx)) off);
3030
3031 op_cost(10);
3032 format %{"[$reg + $off + $idx]" %}
3033 interface(MEMORY_INTER) %{
3034 base($reg);
3035 index($idx);
3036 scale(0x0);
3037 disp($off);
3038 %}
3039 %}
3040
3041 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3042 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3043 %{
3044 constraint(ALLOC_IN_RC(ptr_reg));
3045 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3046 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3047
3048 op_cost(10);
3049 format %{"[$reg + $off + $idx << $scale]" %}
3050 interface(MEMORY_INTER) %{
3051 base($reg);
3052 index($idx);
3053 scale($scale);
3054 disp($off);
3055 %}
3056 %}
3057
3058 // Indirect Narrow Oop Plus Offset Operand
3059 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3060 // we can't free r12 even with CompressedOops::base() == nullptr.
3061 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3062 predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
3063 constraint(ALLOC_IN_RC(ptr_reg));
3064 match(AddP (DecodeN reg) off);
3065
3066 op_cost(10);
3067 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3068 interface(MEMORY_INTER) %{
3069 base(0xc); // R12
3070 index($reg);
3071 scale(0x3);
3072 disp($off);
3073 %}
3074 %}
3075
3076 // Indirect Memory Operand
3077 operand indirectNarrow(rRegN reg)
3078 %{
3079 predicate(CompressedOops::shift() == 0);
3080 constraint(ALLOC_IN_RC(ptr_reg));
3081 match(DecodeN reg);
3082
3083 format %{ "[$reg]" %}
3084 interface(MEMORY_INTER) %{
3085 base($reg);
3086 index(0x4);
3087 scale(0x0);
3088 disp(0x0);
3089 %}
3090 %}
3091
3092 // Indirect Memory Plus Short Offset Operand
3093 operand indOffset8Narrow(rRegN reg, immL8 off)
3094 %{
3095 predicate(CompressedOops::shift() == 0);
3096 constraint(ALLOC_IN_RC(ptr_reg));
3097 match(AddP (DecodeN reg) off);
3098
3099 format %{ "[$reg + $off (8-bit)]" %}
3100 interface(MEMORY_INTER) %{
3101 base($reg);
3102 index(0x4);
3103 scale(0x0);
3104 disp($off);
3105 %}
3106 %}
3107
3108 // Indirect Memory Plus Long Offset Operand
3109 operand indOffset32Narrow(rRegN reg, immL32 off)
3110 %{
3111 predicate(CompressedOops::shift() == 0);
3112 constraint(ALLOC_IN_RC(ptr_reg));
3113 match(AddP (DecodeN reg) off);
3114
3115 format %{ "[$reg + $off (32-bit)]" %}
3116 interface(MEMORY_INTER) %{
3117 base($reg);
3118 index(0x4);
3119 scale(0x0);
3120 disp($off);
3121 %}
3122 %}
3123
3124 // Indirect Memory Plus Index Register Plus Offset Operand
3125 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3126 %{
3127 predicate(CompressedOops::shift() == 0);
3128 constraint(ALLOC_IN_RC(ptr_reg));
3129 match(AddP (AddP (DecodeN reg) lreg) off);
3130
3131 op_cost(10);
3132 format %{"[$reg + $off + $lreg]" %}
3133 interface(MEMORY_INTER) %{
3134 base($reg);
3135 index($lreg);
3136 scale(0x0);
3137 disp($off);
3138 %}
3139 %}
3140
3141 // Indirect Memory Plus Index Register Plus Offset Operand
3142 operand indIndexNarrow(rRegN reg, rRegL lreg)
3143 %{
3144 predicate(CompressedOops::shift() == 0);
3145 constraint(ALLOC_IN_RC(ptr_reg));
3146 match(AddP (DecodeN reg) lreg);
3147
3148 op_cost(10);
3149 format %{"[$reg + $lreg]" %}
3150 interface(MEMORY_INTER) %{
3151 base($reg);
3152 index($lreg);
3153 scale(0x0);
3154 disp(0x0);
3155 %}
3156 %}
3157
3158 // Indirect Memory Times Scale Plus Index Register
3159 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3160 %{
3161 predicate(CompressedOops::shift() == 0);
3162 constraint(ALLOC_IN_RC(ptr_reg));
3163 match(AddP (DecodeN reg) (LShiftL lreg scale));
3164
3165 op_cost(10);
3166 format %{"[$reg + $lreg << $scale]" %}
3167 interface(MEMORY_INTER) %{
3168 base($reg);
3169 index($lreg);
3170 scale($scale);
3171 disp(0x0);
3172 %}
3173 %}
3174
3175 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3176 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3177 %{
3178 predicate(CompressedOops::shift() == 0);
3179 constraint(ALLOC_IN_RC(ptr_reg));
3180 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3181
3182 op_cost(10);
3183 format %{"[$reg + $off + $lreg << $scale]" %}
3184 interface(MEMORY_INTER) %{
3185 base($reg);
3186 index($lreg);
3187 scale($scale);
3188 disp($off);
3189 %}
3190 %}
3191
3192 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
3193 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
3194 %{
3195 constraint(ALLOC_IN_RC(ptr_reg));
3196 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3197 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
3198
3199 op_cost(10);
3200 format %{"[$reg + $off + $idx]" %}
3201 interface(MEMORY_INTER) %{
3202 base($reg);
3203 index($idx);
3204 scale(0x0);
3205 disp($off);
3206 %}
3207 %}
3208
3209 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3210 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3211 %{
3212 constraint(ALLOC_IN_RC(ptr_reg));
3213 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3214 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
3215
3216 op_cost(10);
3217 format %{"[$reg + $off + $idx << $scale]" %}
3218 interface(MEMORY_INTER) %{
3219 base($reg);
3220 index($idx);
3221 scale($scale);
3222 disp($off);
3223 %}
3224 %}
3225
3226 //----------Special Memory Operands--------------------------------------------
3227 // Stack Slot Operand - This operand is used for loading and storing temporary
3228 // values on the stack where a match requires a value to
3229 // flow through memory.
3230 operand stackSlotP(sRegP reg)
3231 %{
3232 constraint(ALLOC_IN_RC(stack_slots));
3233 // No match rule because this operand is only generated in matching
3234
3235 format %{ "[$reg]" %}
3236 interface(MEMORY_INTER) %{
3237 base(0x4); // RSP
3238 index(0x4); // No Index
3239 scale(0x0); // No Scale
3240 disp($reg); // Stack Offset
3241 %}
3242 %}
3243
3244 operand stackSlotI(sRegI reg)
3245 %{
3246 constraint(ALLOC_IN_RC(stack_slots));
3247 // No match rule because this operand is only generated in matching
3248
3249 format %{ "[$reg]" %}
3250 interface(MEMORY_INTER) %{
3251 base(0x4); // RSP
3252 index(0x4); // No Index
3253 scale(0x0); // No Scale
3254 disp($reg); // Stack Offset
3255 %}
3256 %}
3257
3258 operand stackSlotF(sRegF reg)
3259 %{
3260 constraint(ALLOC_IN_RC(stack_slots));
3261 // No match rule because this operand is only generated in matching
3262
3263 format %{ "[$reg]" %}
3264 interface(MEMORY_INTER) %{
3265 base(0x4); // RSP
3266 index(0x4); // No Index
3267 scale(0x0); // No Scale
3268 disp($reg); // Stack Offset
3269 %}
3270 %}
3271
3272 operand stackSlotD(sRegD reg)
3273 %{
3274 constraint(ALLOC_IN_RC(stack_slots));
3275 // No match rule because this operand is only generated in matching
3276
3277 format %{ "[$reg]" %}
3278 interface(MEMORY_INTER) %{
3279 base(0x4); // RSP
3280 index(0x4); // No Index
3281 scale(0x0); // No Scale
3282 disp($reg); // Stack Offset
3283 %}
3284 %}
3285 operand stackSlotL(sRegL reg)
3286 %{
3287 constraint(ALLOC_IN_RC(stack_slots));
3288 // No match rule because this operand is only generated in matching
3289
3290 format %{ "[$reg]" %}
3291 interface(MEMORY_INTER) %{
3292 base(0x4); // RSP
3293 index(0x4); // No Index
3294 scale(0x0); // No Scale
3295 disp($reg); // Stack Offset
3296 %}
3297 %}
3298
3299 //----------Conditional Branch Operands----------------------------------------
3300 // Comparison Op - This is the operation of the comparison, and is limited to
3301 // the following set of codes:
3302 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3303 //
3304 // Other attributes of the comparison, such as unsignedness, are specified
3305 // by the comparison instruction that sets a condition code flags register.
3306 // That result is represented by a flags operand whose subtype is appropriate
3307 // to the unsignedness (etc.) of the comparison.
3308 //
3309 // Later, the instruction which matches both the Comparison Op (a Bool) and
3310 // the flags (produced by the Cmp) specifies the coding of the comparison op
3311 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3312
3313 // Comparison Code
3314 operand cmpOp()
3315 %{
3316 match(Bool);
3317
3318 format %{ "" %}
3319 interface(COND_INTER) %{
3320 equal(0x4, "e");
3321 not_equal(0x5, "ne");
3322 less(0xC, "l");
3323 greater_equal(0xD, "ge");
3324 less_equal(0xE, "le");
3325 greater(0xF, "g");
3326 overflow(0x0, "o");
3327 no_overflow(0x1, "no");
3328 %}
3329 %}
3330
3331 // Comparison Code, unsigned compare. Used by FP also, with
3332 // C2 (unordered) turned into GT or LT already. The other bits
3333 // C0 and C3 are turned into Carry & Zero flags.
3334 operand cmpOpU()
3335 %{
3336 match(Bool);
3337
3338 format %{ "" %}
3339 interface(COND_INTER) %{
3340 equal(0x4, "e");
3341 not_equal(0x5, "ne");
3342 less(0x2, "b");
3343 greater_equal(0x3, "ae");
3344 less_equal(0x6, "be");
3345 greater(0x7, "a");
3346 overflow(0x0, "o");
3347 no_overflow(0x1, "no");
3348 %}
3349 %}
3350
3351
3352 // Floating comparisons that don't require any fixup for the unordered case,
3353 // If both inputs of the comparison are the same, ZF is always set so we
3354 // don't need to use cmpOpUCF2 for eq/ne
3355 operand cmpOpUCF() %{
3356 match(Bool);
3357 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3358 n->as_Bool()->_test._test == BoolTest::ge ||
3359 n->as_Bool()->_test._test == BoolTest::le ||
3360 n->as_Bool()->_test._test == BoolTest::gt ||
3361 n->in(1)->in(1) == n->in(1)->in(2));
3362 format %{ "" %}
3363 interface(COND_INTER) %{
3364 equal(0xb, "np");
3365 not_equal(0xa, "p");
3366 less(0x2, "b");
3367 greater_equal(0x3, "ae");
3368 less_equal(0x6, "be");
3369 greater(0x7, "a");
3370 overflow(0x0, "o");
3371 no_overflow(0x1, "no");
3372 %}
3373 %}
3374
3375
3376 // Floating comparisons that can be fixed up with extra conditional jumps
3377 operand cmpOpUCF2() %{
3378 match(Bool);
3379 predicate((n->as_Bool()->_test._test == BoolTest::ne ||
3380 n->as_Bool()->_test._test == BoolTest::eq) &&
3381 n->in(1)->in(1) != n->in(1)->in(2));
3382 format %{ "" %}
3383 interface(COND_INTER) %{
3384 equal(0x4, "e");
3385 not_equal(0x5, "ne");
3386 less(0x2, "b");
3387 greater_equal(0x3, "ae");
3388 less_equal(0x6, "be");
3389 greater(0x7, "a");
3390 overflow(0x0, "o");
3391 no_overflow(0x1, "no");
3392 %}
3393 %}
3394
3395 //----------OPERAND CLASSES----------------------------------------------------
3396 // Operand Classes are groups of operands that are used as to simplify
3397 // instruction definitions by not requiring the AD writer to specify separate
3398 // instructions for every form of operand when the instruction accepts
3399 // multiple operand types with the same basic encoding and format. The classic
3400 // case of this is memory operands.
3401
3402 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
3403 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
3404 indCompressedOopOffset,
3405 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
3406 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
3407 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
3408
3409 //----------PIPELINE-----------------------------------------------------------
3410 // Rules which define the behavior of the target architectures pipeline.
3411 pipeline %{
3412
3413 //----------ATTRIBUTES---------------------------------------------------------
3414 attributes %{
3415 variable_size_instructions; // Fixed size instructions
3416 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
3417 instruction_unit_size = 1; // An instruction is 1 bytes long
3418 instruction_fetch_unit_size = 16; // The processor fetches one line
3419 instruction_fetch_units = 1; // of 16 bytes
3420
3421 // List of nop instructions
3422 nops( MachNop );
3423 %}
3424
3425 //----------RESOURCES----------------------------------------------------------
3426 // Resources are the functional units available to the machine
3427
3428 // Generic P2/P3 pipeline
3429 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
3430 // 3 instructions decoded per cycle.
3431 // 2 load/store ops per cycle, 1 branch, 1 FPU,
3432 // 3 ALU op, only ALU0 handles mul instructions.
3433 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
3434 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
3435 BR, FPU,
3436 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
3437
3438 //----------PIPELINE DESCRIPTION-----------------------------------------------
3439 // Pipeline Description specifies the stages in the machine's pipeline
3440
3441 // Generic P2/P3 pipeline
3442 pipe_desc(S0, S1, S2, S3, S4, S5);
3443
3444 //----------PIPELINE CLASSES---------------------------------------------------
3445 // Pipeline Classes describe the stages in which input and output are
3446 // referenced by the hardware pipeline.
3447
3448 // Naming convention: ialu or fpu
3449 // Then: _reg
3450 // Then: _reg if there is a 2nd register
3451 // Then: _long if it's a pair of instructions implementing a long
3452 // Then: _fat if it requires the big decoder
3453 // Or: _mem if it requires the big decoder and a memory unit.
3454
3455 // Integer ALU reg operation
3456 pipe_class ialu_reg(rRegI dst)
3457 %{
3458 single_instruction;
3459 dst : S4(write);
3460 dst : S3(read);
3461 DECODE : S0; // any decoder
3462 ALU : S3; // any alu
3463 %}
3464
3465 // Long ALU reg operation
3466 pipe_class ialu_reg_long(rRegL dst)
3467 %{
3468 instruction_count(2);
3469 dst : S4(write);
3470 dst : S3(read);
3471 DECODE : S0(2); // any 2 decoders
3472 ALU : S3(2); // both alus
3473 %}
3474
3475 // Integer ALU reg operation using big decoder
3476 pipe_class ialu_reg_fat(rRegI dst)
3477 %{
3478 single_instruction;
3479 dst : S4(write);
3480 dst : S3(read);
3481 D0 : S0; // big decoder only
3482 ALU : S3; // any alu
3483 %}
3484
3485 // Integer ALU reg-reg operation
3486 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
3487 %{
3488 single_instruction;
3489 dst : S4(write);
3490 src : S3(read);
3491 DECODE : S0; // any decoder
3492 ALU : S3; // any alu
3493 %}
3494
3495 // Integer ALU reg-reg operation
3496 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
3497 %{
3498 single_instruction;
3499 dst : S4(write);
3500 src : S3(read);
3501 D0 : S0; // big decoder only
3502 ALU : S3; // any alu
3503 %}
3504
3505 // Integer ALU reg-mem operation
3506 pipe_class ialu_reg_mem(rRegI dst, memory mem)
3507 %{
3508 single_instruction;
3509 dst : S5(write);
3510 mem : S3(read);
3511 D0 : S0; // big decoder only
3512 ALU : S4; // any alu
3513 MEM : S3; // any mem
3514 %}
3515
3516 // Integer mem operation (prefetch)
3517 pipe_class ialu_mem(memory mem)
3518 %{
3519 single_instruction;
3520 mem : S3(read);
3521 D0 : S0; // big decoder only
3522 MEM : S3; // any mem
3523 %}
3524
3525 // Integer Store to Memory
3526 pipe_class ialu_mem_reg(memory mem, rRegI src)
3527 %{
3528 single_instruction;
3529 mem : S3(read);
3530 src : S5(read);
3531 D0 : S0; // big decoder only
3532 ALU : S4; // any alu
3533 MEM : S3;
3534 %}
3535
3536 // // Long Store to Memory
3537 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
3538 // %{
3539 // instruction_count(2);
3540 // mem : S3(read);
3541 // src : S5(read);
3542 // D0 : S0(2); // big decoder only; twice
3543 // ALU : S4(2); // any 2 alus
3544 // MEM : S3(2); // Both mems
3545 // %}
3546
3547 // Integer Store to Memory
3548 pipe_class ialu_mem_imm(memory mem)
3549 %{
3550 single_instruction;
3551 mem : S3(read);
3552 D0 : S0; // big decoder only
3553 ALU : S4; // any alu
3554 MEM : S3;
3555 %}
3556
3557 // Integer ALU0 reg-reg operation
3558 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
3559 %{
3560 single_instruction;
3561 dst : S4(write);
3562 src : S3(read);
3563 D0 : S0; // Big decoder only
3564 ALU0 : S3; // only alu0
3565 %}
3566
3567 // Integer ALU0 reg-mem operation
3568 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
3569 %{
3570 single_instruction;
3571 dst : S5(write);
3572 mem : S3(read);
3573 D0 : S0; // big decoder only
3574 ALU0 : S4; // ALU0 only
3575 MEM : S3; // any mem
3576 %}
3577
3578 // Integer ALU reg-reg operation
3579 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
3580 %{
3581 single_instruction;
3582 cr : S4(write);
3583 src1 : S3(read);
3584 src2 : S3(read);
3585 DECODE : S0; // any decoder
3586 ALU : S3; // any alu
3587 %}
3588
3589 // Integer ALU reg-imm operation
3590 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
3591 %{
3592 single_instruction;
3593 cr : S4(write);
3594 src1 : S3(read);
3595 DECODE : S0; // any decoder
3596 ALU : S3; // any alu
3597 %}
3598
3599 // Integer ALU reg-mem operation
3600 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
3601 %{
3602 single_instruction;
3603 cr : S4(write);
3604 src1 : S3(read);
3605 src2 : S3(read);
3606 D0 : S0; // big decoder only
3607 ALU : S4; // any alu
3608 MEM : S3;
3609 %}
3610
3611 // Conditional move reg-reg
3612 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
3613 %{
3614 instruction_count(4);
3615 y : S4(read);
3616 q : S3(read);
3617 p : S3(read);
3618 DECODE : S0(4); // any decoder
3619 %}
3620
3621 // Conditional move reg-reg
3622 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
3623 %{
3624 single_instruction;
3625 dst : S4(write);
3626 src : S3(read);
3627 cr : S3(read);
3628 DECODE : S0; // any decoder
3629 %}
3630
3631 // Conditional move reg-mem
3632 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
3633 %{
3634 single_instruction;
3635 dst : S4(write);
3636 src : S3(read);
3637 cr : S3(read);
3638 DECODE : S0; // any decoder
3639 MEM : S3;
3640 %}
3641
3642 // Conditional move reg-reg long
3643 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
3644 %{
3645 single_instruction;
3646 dst : S4(write);
3647 src : S3(read);
3648 cr : S3(read);
3649 DECODE : S0(2); // any 2 decoders
3650 %}
3651
3652 // Float reg-reg operation
3653 pipe_class fpu_reg(regD dst)
3654 %{
3655 instruction_count(2);
3656 dst : S3(read);
3657 DECODE : S0(2); // any 2 decoders
3658 FPU : S3;
3659 %}
3660
3661 // Float reg-reg operation
3662 pipe_class fpu_reg_reg(regD dst, regD src)
3663 %{
3664 instruction_count(2);
3665 dst : S4(write);
3666 src : S3(read);
3667 DECODE : S0(2); // any 2 decoders
3668 FPU : S3;
3669 %}
3670
3671 // Float reg-reg operation
3672 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
3673 %{
3674 instruction_count(3);
3675 dst : S4(write);
3676 src1 : S3(read);
3677 src2 : S3(read);
3678 DECODE : S0(3); // any 3 decoders
3679 FPU : S3(2);
3680 %}
3681
3682 // Float reg-reg operation
3683 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
3684 %{
3685 instruction_count(4);
3686 dst : S4(write);
3687 src1 : S3(read);
3688 src2 : S3(read);
3689 src3 : S3(read);
3690 DECODE : S0(4); // any 3 decoders
3691 FPU : S3(2);
3692 %}
3693
3694 // Float reg-reg operation
3695 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
3696 %{
3697 instruction_count(4);
3698 dst : S4(write);
3699 src1 : S3(read);
3700 src2 : S3(read);
3701 src3 : S3(read);
3702 DECODE : S1(3); // any 3 decoders
3703 D0 : S0; // Big decoder only
3704 FPU : S3(2);
3705 MEM : S3;
3706 %}
3707
3708 // Float reg-mem operation
3709 pipe_class fpu_reg_mem(regD dst, memory mem)
3710 %{
3711 instruction_count(2);
3712 dst : S5(write);
3713 mem : S3(read);
3714 D0 : S0; // big decoder only
3715 DECODE : S1; // any decoder for FPU POP
3716 FPU : S4;
3717 MEM : S3; // any mem
3718 %}
3719
3720 // Float reg-mem operation
3721 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
3722 %{
3723 instruction_count(3);
3724 dst : S5(write);
3725 src1 : S3(read);
3726 mem : S3(read);
3727 D0 : S0; // big decoder only
3728 DECODE : S1(2); // any decoder for FPU POP
3729 FPU : S4;
3730 MEM : S3; // any mem
3731 %}
3732
3733 // Float mem-reg operation
3734 pipe_class fpu_mem_reg(memory mem, regD src)
3735 %{
3736 instruction_count(2);
3737 src : S5(read);
3738 mem : S3(read);
3739 DECODE : S0; // any decoder for FPU PUSH
3740 D0 : S1; // big decoder only
3741 FPU : S4;
3742 MEM : S3; // any mem
3743 %}
3744
3745 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
3746 %{
3747 instruction_count(3);
3748 src1 : S3(read);
3749 src2 : S3(read);
3750 mem : S3(read);
3751 DECODE : S0(2); // any decoder for FPU PUSH
3752 D0 : S1; // big decoder only
3753 FPU : S4;
3754 MEM : S3; // any mem
3755 %}
3756
3757 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
3758 %{
3759 instruction_count(3);
3760 src1 : S3(read);
3761 src2 : S3(read);
3762 mem : S4(read);
3763 DECODE : S0; // any decoder for FPU PUSH
3764 D0 : S0(2); // big decoder only
3765 FPU : S4;
3766 MEM : S3(2); // any mem
3767 %}
3768
3769 pipe_class fpu_mem_mem(memory dst, memory src1)
3770 %{
3771 instruction_count(2);
3772 src1 : S3(read);
3773 dst : S4(read);
3774 D0 : S0(2); // big decoder only
3775 MEM : S3(2); // any mem
3776 %}
3777
3778 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
3779 %{
3780 instruction_count(3);
3781 src1 : S3(read);
3782 src2 : S3(read);
3783 dst : S4(read);
3784 D0 : S0(3); // big decoder only
3785 FPU : S4;
3786 MEM : S3(3); // any mem
3787 %}
3788
3789 pipe_class fpu_mem_reg_con(memory mem, regD src1)
3790 %{
3791 instruction_count(3);
3792 src1 : S4(read);
3793 mem : S4(read);
3794 DECODE : S0; // any decoder for FPU PUSH
3795 D0 : S0(2); // big decoder only
3796 FPU : S4;
3797 MEM : S3(2); // any mem
3798 %}
3799
3800 // Float load constant
3801 pipe_class fpu_reg_con(regD dst)
3802 %{
3803 instruction_count(2);
3804 dst : S5(write);
3805 D0 : S0; // big decoder only for the load
3806 DECODE : S1; // any decoder for FPU POP
3807 FPU : S4;
3808 MEM : S3; // any mem
3809 %}
3810
3811 // Float load constant
3812 pipe_class fpu_reg_reg_con(regD dst, regD src)
3813 %{
3814 instruction_count(3);
3815 dst : S5(write);
3816 src : S3(read);
3817 D0 : S0; // big decoder only for the load
3818 DECODE : S1(2); // any decoder for FPU POP
3819 FPU : S4;
3820 MEM : S3; // any mem
3821 %}
3822
3823 // UnConditional branch
3824 pipe_class pipe_jmp(label labl)
3825 %{
3826 single_instruction;
3827 BR : S3;
3828 %}
3829
3830 // Conditional branch
3831 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
3832 %{
3833 single_instruction;
3834 cr : S1(read);
3835 BR : S3;
3836 %}
3837
3838 // Allocation idiom
3839 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
3840 %{
3841 instruction_count(1); force_serialization;
3842 fixed_latency(6);
3843 heap_ptr : S3(read);
3844 DECODE : S0(3);
3845 D0 : S2;
3846 MEM : S3;
3847 ALU : S3(2);
3848 dst : S5(write);
3849 BR : S5;
3850 %}
3851
3852 // Generic big/slow expanded idiom
3853 pipe_class pipe_slow()
3854 %{
3855 instruction_count(10); multiple_bundles; force_serialization;
3856 fixed_latency(100);
3857 D0 : S0(2);
3858 MEM : S3(2);
3859 %}
3860
3861 // The real do-nothing guy
3862 pipe_class empty()
3863 %{
3864 instruction_count(0);
3865 %}
3866
3867 // Define the class for the Nop node
3868 define
3869 %{
3870 MachNop = empty;
3871 %}
3872
3873 %}
3874
3875 //----------INSTRUCTIONS-------------------------------------------------------
3876 //
3877 // match -- States which machine-independent subtree may be replaced
3878 // by this instruction.
3879 // ins_cost -- The estimated cost of this instruction is used by instruction
3880 // selection to identify a minimum cost tree of machine
3881 // instructions that matches a tree of machine-independent
3882 // instructions.
3883 // format -- A string providing the disassembly for this instruction.
3884 // The value of an instruction's operand may be inserted
3885 // by referring to it with a '$' prefix.
3886 // opcode -- Three instruction opcodes may be provided. These are referred
3887 // to within an encode class as $primary, $secondary, and $tertiary
3888 // rrspectively. The primary opcode is commonly used to
3889 // indicate the type of machine instruction, while secondary
3890 // and tertiary are often used for prefix options or addressing
3891 // modes.
3892 // ins_encode -- A list of encode classes with parameters. The encode class
3893 // name must have been defined in an 'enc_class' specification
3894 // in the encode section of the architecture description.
3895
3896 // Dummy reg-to-reg vector moves. Removed during post-selection cleanup.
3897 // Load Float
3898 instruct MoveF2VL(vlRegF dst, regF src) %{
3899 match(Set dst src);
3900 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
3901 ins_encode %{
3902 ShouldNotReachHere();
3903 %}
3904 ins_pipe( fpu_reg_reg );
3905 %}
3906
3907 // Load Float
3908 instruct MoveF2LEG(legRegF dst, regF src) %{
3909 match(Set dst src);
3910 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
3911 ins_encode %{
3912 ShouldNotReachHere();
3913 %}
3914 ins_pipe( fpu_reg_reg );
3915 %}
3916
3917 // Load Float
3918 instruct MoveVL2F(regF dst, vlRegF src) %{
3919 match(Set dst src);
3920 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
3921 ins_encode %{
3922 ShouldNotReachHere();
3923 %}
3924 ins_pipe( fpu_reg_reg );
3925 %}
3926
3927 // Load Float
3928 instruct MoveLEG2F(regF dst, legRegF src) %{
3929 match(Set dst src);
3930 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
3931 ins_encode %{
3932 ShouldNotReachHere();
3933 %}
3934 ins_pipe( fpu_reg_reg );
3935 %}
3936
3937 // Load Double
3938 instruct MoveD2VL(vlRegD dst, regD src) %{
3939 match(Set dst src);
3940 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
3941 ins_encode %{
3942 ShouldNotReachHere();
3943 %}
3944 ins_pipe( fpu_reg_reg );
3945 %}
3946
3947 // Load Double
3948 instruct MoveD2LEG(legRegD dst, regD src) %{
3949 match(Set dst src);
3950 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
3951 ins_encode %{
3952 ShouldNotReachHere();
3953 %}
3954 ins_pipe( fpu_reg_reg );
3955 %}
3956
3957 // Load Double
3958 instruct MoveVL2D(regD dst, vlRegD src) %{
3959 match(Set dst src);
3960 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
3961 ins_encode %{
3962 ShouldNotReachHere();
3963 %}
3964 ins_pipe( fpu_reg_reg );
3965 %}
3966
3967 // Load Double
3968 instruct MoveLEG2D(regD dst, legRegD src) %{
3969 match(Set dst src);
3970 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
3971 ins_encode %{
3972 ShouldNotReachHere();
3973 %}
3974 ins_pipe( fpu_reg_reg );
3975 %}
3976
3977 //----------Load/Store/Move Instructions---------------------------------------
3978 //----------Load Instructions--------------------------------------------------
3979
3980 // Load Byte (8 bit signed)
3981 instruct loadB(rRegI dst, memory mem)
3982 %{
3983 match(Set dst (LoadB mem));
3984
3985 ins_cost(125);
3986 format %{ "movsbl $dst, $mem\t# byte" %}
3987
3988 ins_encode %{
3989 __ movsbl($dst$$Register, $mem$$Address);
3990 %}
3991
3992 ins_pipe(ialu_reg_mem);
3993 %}
3994
3995 // Load Byte (8 bit signed) into Long Register
3996 instruct loadB2L(rRegL dst, memory mem)
3997 %{
3998 match(Set dst (ConvI2L (LoadB mem)));
3999
4000 ins_cost(125);
4001 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4002
4003 ins_encode %{
4004 __ movsbq($dst$$Register, $mem$$Address);
4005 %}
4006
4007 ins_pipe(ialu_reg_mem);
4008 %}
4009
4010 // Load Unsigned Byte (8 bit UNsigned)
4011 instruct loadUB(rRegI dst, memory mem)
4012 %{
4013 match(Set dst (LoadUB mem));
4014
4015 ins_cost(125);
4016 format %{ "movzbl $dst, $mem\t# ubyte" %}
4017
4018 ins_encode %{
4019 __ movzbl($dst$$Register, $mem$$Address);
4020 %}
4021
4022 ins_pipe(ialu_reg_mem);
4023 %}
4024
4025 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4026 instruct loadUB2L(rRegL dst, memory mem)
4027 %{
4028 match(Set dst (ConvI2L (LoadUB mem)));
4029
4030 ins_cost(125);
4031 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4032
4033 ins_encode %{
4034 __ movzbq($dst$$Register, $mem$$Address);
4035 %}
4036
4037 ins_pipe(ialu_reg_mem);
4038 %}
4039
4040 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4041 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4042 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4043 effect(KILL cr);
4044
4045 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4046 "andl $dst, right_n_bits($mask, 8)" %}
4047 ins_encode %{
4048 Register Rdst = $dst$$Register;
4049 __ movzbq(Rdst, $mem$$Address);
4050 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4051 %}
4052 ins_pipe(ialu_reg_mem);
4053 %}
4054
4055 // Load Short (16 bit signed)
4056 instruct loadS(rRegI dst, memory mem)
4057 %{
4058 match(Set dst (LoadS mem));
4059
4060 ins_cost(125);
4061 format %{ "movswl $dst, $mem\t# short" %}
4062
4063 ins_encode %{
4064 __ movswl($dst$$Register, $mem$$Address);
4065 %}
4066
4067 ins_pipe(ialu_reg_mem);
4068 %}
4069
4070 // Load Short (16 bit signed) to Byte (8 bit signed)
4071 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4072 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4073
4074 ins_cost(125);
4075 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4076 ins_encode %{
4077 __ movsbl($dst$$Register, $mem$$Address);
4078 %}
4079 ins_pipe(ialu_reg_mem);
4080 %}
4081
4082 // Load Short (16 bit signed) into Long Register
4083 instruct loadS2L(rRegL dst, memory mem)
4084 %{
4085 match(Set dst (ConvI2L (LoadS mem)));
4086
4087 ins_cost(125);
4088 format %{ "movswq $dst, $mem\t# short -> long" %}
4089
4090 ins_encode %{
4091 __ movswq($dst$$Register, $mem$$Address);
4092 %}
4093
4094 ins_pipe(ialu_reg_mem);
4095 %}
4096
4097 // Load Unsigned Short/Char (16 bit UNsigned)
4098 instruct loadUS(rRegI dst, memory mem)
4099 %{
4100 match(Set dst (LoadUS mem));
4101
4102 ins_cost(125);
4103 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4104
4105 ins_encode %{
4106 __ movzwl($dst$$Register, $mem$$Address);
4107 %}
4108
4109 ins_pipe(ialu_reg_mem);
4110 %}
4111
4112 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4113 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4114 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4115
4116 ins_cost(125);
4117 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4118 ins_encode %{
4119 __ movsbl($dst$$Register, $mem$$Address);
4120 %}
4121 ins_pipe(ialu_reg_mem);
4122 %}
4123
4124 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4125 instruct loadUS2L(rRegL dst, memory mem)
4126 %{
4127 match(Set dst (ConvI2L (LoadUS mem)));
4128
4129 ins_cost(125);
4130 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4131
4132 ins_encode %{
4133 __ movzwq($dst$$Register, $mem$$Address);
4134 %}
4135
4136 ins_pipe(ialu_reg_mem);
4137 %}
4138
4139 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4140 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4141 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4142
4143 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4144 ins_encode %{
4145 __ movzbq($dst$$Register, $mem$$Address);
4146 %}
4147 ins_pipe(ialu_reg_mem);
4148 %}
4149
4150 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4151 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4152 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4153 effect(KILL cr);
4154
4155 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4156 "andl $dst, right_n_bits($mask, 16)" %}
4157 ins_encode %{
4158 Register Rdst = $dst$$Register;
4159 __ movzwq(Rdst, $mem$$Address);
4160 __ andl(Rdst, $mask$$constant & right_n_bits(16));
4161 %}
4162 ins_pipe(ialu_reg_mem);
4163 %}
4164
4165 // Load Integer
4166 instruct loadI(rRegI dst, memory mem)
4167 %{
4168 match(Set dst (LoadI mem));
4169
4170 ins_cost(125);
4171 format %{ "movl $dst, $mem\t# int" %}
4172
4173 ins_encode %{
4174 __ movl($dst$$Register, $mem$$Address);
4175 %}
4176
4177 ins_pipe(ialu_reg_mem);
4178 %}
4179
4180 // Load Integer (32 bit signed) to Byte (8 bit signed)
4181 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4182 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4183
4184 ins_cost(125);
4185 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4186 ins_encode %{
4187 __ movsbl($dst$$Register, $mem$$Address);
4188 %}
4189 ins_pipe(ialu_reg_mem);
4190 %}
4191
4192 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4193 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4194 match(Set dst (AndI (LoadI mem) mask));
4195
4196 ins_cost(125);
4197 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4198 ins_encode %{
4199 __ movzbl($dst$$Register, $mem$$Address);
4200 %}
4201 ins_pipe(ialu_reg_mem);
4202 %}
4203
4204 // Load Integer (32 bit signed) to Short (16 bit signed)
4205 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4206 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4207
4208 ins_cost(125);
4209 format %{ "movswl $dst, $mem\t# int -> short" %}
4210 ins_encode %{
4211 __ movswl($dst$$Register, $mem$$Address);
4212 %}
4213 ins_pipe(ialu_reg_mem);
4214 %}
4215
4216 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4217 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4218 match(Set dst (AndI (LoadI mem) mask));
4219
4220 ins_cost(125);
4221 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4222 ins_encode %{
4223 __ movzwl($dst$$Register, $mem$$Address);
4224 %}
4225 ins_pipe(ialu_reg_mem);
4226 %}
4227
4228 // Load Integer into Long Register
4229 instruct loadI2L(rRegL dst, memory mem)
4230 %{
4231 match(Set dst (ConvI2L (LoadI mem)));
4232
4233 ins_cost(125);
4234 format %{ "movslq $dst, $mem\t# int -> long" %}
4235
4236 ins_encode %{
4237 __ movslq($dst$$Register, $mem$$Address);
4238 %}
4239
4240 ins_pipe(ialu_reg_mem);
4241 %}
4242
4243 // Load Integer with mask 0xFF into Long Register
4244 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4245 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4246
4247 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
4248 ins_encode %{
4249 __ movzbq($dst$$Register, $mem$$Address);
4250 %}
4251 ins_pipe(ialu_reg_mem);
4252 %}
4253
4254 // Load Integer with mask 0xFFFF into Long Register
4255 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
4256 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4257
4258 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
4259 ins_encode %{
4260 __ movzwq($dst$$Register, $mem$$Address);
4261 %}
4262 ins_pipe(ialu_reg_mem);
4263 %}
4264
4265 // Load Integer with a 31-bit mask into Long Register
4266 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
4267 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4268 effect(KILL cr);
4269
4270 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
4271 "andl $dst, $mask" %}
4272 ins_encode %{
4273 Register Rdst = $dst$$Register;
4274 __ movl(Rdst, $mem$$Address);
4275 __ andl(Rdst, $mask$$constant);
4276 %}
4277 ins_pipe(ialu_reg_mem);
4278 %}
4279
4280 // Load Unsigned Integer into Long Register
4281 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
4282 %{
4283 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4284
4285 ins_cost(125);
4286 format %{ "movl $dst, $mem\t# uint -> long" %}
4287
4288 ins_encode %{
4289 __ movl($dst$$Register, $mem$$Address);
4290 %}
4291
4292 ins_pipe(ialu_reg_mem);
4293 %}
4294
4295 // Load Long
4296 instruct loadL(rRegL dst, memory mem)
4297 %{
4298 match(Set dst (LoadL mem));
4299
4300 ins_cost(125);
4301 format %{ "movq $dst, $mem\t# long" %}
4302
4303 ins_encode %{
4304 __ movq($dst$$Register, $mem$$Address);
4305 %}
4306
4307 ins_pipe(ialu_reg_mem); // XXX
4308 %}
4309
4310 // Load Range
4311 instruct loadRange(rRegI dst, memory mem)
4312 %{
4313 match(Set dst (LoadRange mem));
4314
4315 ins_cost(125); // XXX
4316 format %{ "movl $dst, $mem\t# range" %}
4317 ins_encode %{
4318 __ movl($dst$$Register, $mem$$Address);
4319 %}
4320 ins_pipe(ialu_reg_mem);
4321 %}
4322
4323 // Load Pointer
4324 instruct loadP(rRegP dst, memory mem)
4325 %{
4326 match(Set dst (LoadP mem));
4327 predicate(n->as_Load()->barrier_data() == 0);
4328
4329 ins_cost(125); // XXX
4330 format %{ "movq $dst, $mem\t# ptr" %}
4331 ins_encode %{
4332 __ movq($dst$$Register, $mem$$Address);
4333 %}
4334 ins_pipe(ialu_reg_mem); // XXX
4335 %}
4336
4337 // Load Compressed Pointer
4338 instruct loadN(rRegN dst, memory mem)
4339 %{
4340 predicate(n->as_Load()->barrier_data() == 0);
4341 match(Set dst (LoadN mem));
4342
4343 ins_cost(125); // XXX
4344 format %{ "movl $dst, $mem\t# compressed ptr" %}
4345 ins_encode %{
4346 __ movl($dst$$Register, $mem$$Address);
4347 %}
4348 ins_pipe(ialu_reg_mem); // XXX
4349 %}
4350
4351
4352 // Load Klass Pointer
4353 instruct loadKlass(rRegP dst, memory mem)
4354 %{
4355 match(Set dst (LoadKlass mem));
4356
4357 ins_cost(125); // XXX
4358 format %{ "movq $dst, $mem\t# class" %}
4359 ins_encode %{
4360 __ movq($dst$$Register, $mem$$Address);
4361 %}
4362 ins_pipe(ialu_reg_mem); // XXX
4363 %}
4364
4365 // Load narrow Klass Pointer
4366 instruct loadNKlass(rRegN dst, memory mem)
4367 %{
4368 predicate(!UseCompactObjectHeaders);
4369 match(Set dst (LoadNKlass mem));
4370
4371 ins_cost(125); // XXX
4372 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
4373 ins_encode %{
4374 __ movl($dst$$Register, $mem$$Address);
4375 %}
4376 ins_pipe(ialu_reg_mem); // XXX
4377 %}
4378
4379 instruct loadNKlassCompactHeaders(rRegN dst, memory mem, rFlagsReg cr)
4380 %{
4381 predicate(UseCompactObjectHeaders);
4382 match(Set dst (LoadNKlass mem));
4383 effect(KILL cr);
4384 ins_cost(125);
4385 format %{
4386 "movl $dst, $mem\t# compressed klass ptr, shifted\n\t"
4387 "shrl $dst, markWord::klass_shift_at_offset"
4388 %}
4389 ins_encode %{
4390 if (UseAPX) {
4391 __ eshrl($dst$$Register, $mem$$Address, markWord::klass_shift_at_offset, false);
4392 }
4393 else {
4394 __ movl($dst$$Register, $mem$$Address);
4395 __ shrl($dst$$Register, markWord::klass_shift_at_offset);
4396 }
4397 %}
4398 ins_pipe(ialu_reg_mem);
4399 %}
4400
4401 // Load Float
4402 instruct loadF(regF dst, memory mem)
4403 %{
4404 match(Set dst (LoadF mem));
4405
4406 ins_cost(145); // XXX
4407 format %{ "movss $dst, $mem\t# float" %}
4408 ins_encode %{
4409 __ movflt($dst$$XMMRegister, $mem$$Address);
4410 %}
4411 ins_pipe(pipe_slow); // XXX
4412 %}
4413
4414 // Load Double
4415 instruct loadD_partial(regD dst, memory mem)
4416 %{
4417 predicate(!UseXmmLoadAndClearUpper);
4418 match(Set dst (LoadD mem));
4419
4420 ins_cost(145); // XXX
4421 format %{ "movlpd $dst, $mem\t# double" %}
4422 ins_encode %{
4423 __ movdbl($dst$$XMMRegister, $mem$$Address);
4424 %}
4425 ins_pipe(pipe_slow); // XXX
4426 %}
4427
4428 instruct loadD(regD dst, memory mem)
4429 %{
4430 predicate(UseXmmLoadAndClearUpper);
4431 match(Set dst (LoadD mem));
4432
4433 ins_cost(145); // XXX
4434 format %{ "movsd $dst, $mem\t# double" %}
4435 ins_encode %{
4436 __ movdbl($dst$$XMMRegister, $mem$$Address);
4437 %}
4438 ins_pipe(pipe_slow); // XXX
4439 %}
4440
4441 // max = java.lang.Math.max(float a, float b)
4442 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
4443 predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
4444 match(Set dst (MaxF a b));
4445 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4446 format %{ "maxF $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
4447 ins_encode %{
4448 __ vminmax_fp(Op_MaxV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4449 %}
4450 ins_pipe( pipe_slow );
4451 %}
4452
4453 instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xtmp, rRegI rtmp, rFlagsReg cr) %{
4454 predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
4455 match(Set dst (MaxF a b));
4456 effect(USE a, USE b, TEMP xtmp, TEMP rtmp, KILL cr);
4457
4458 format %{ "maxF_reduction $dst, $a, $b \t!using $xtmp and $rtmp as TEMP" %}
4459 ins_encode %{
4460 emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xtmp$$XMMRegister, $rtmp$$Register,
4461 false /*min*/, true /*single*/);
4462 %}
4463 ins_pipe( pipe_slow );
4464 %}
4465
4466 // max = java.lang.Math.max(double a, double b)
4467 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
4468 predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
4469 match(Set dst (MaxD a b));
4470 effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
4471 format %{ "maxD $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
4472 ins_encode %{
4473 __ vminmax_fp(Op_MaxV, T_DOUBLE, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4474 %}
4475 ins_pipe( pipe_slow );
4476 %}
4477
4478 instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xtmp, rRegL rtmp, rFlagsReg cr) %{
4479 predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
4480 match(Set dst (MaxD a b));
4481 effect(USE a, USE b, TEMP xtmp, TEMP rtmp, KILL cr);
4482
4483 format %{ "maxD_reduction $dst, $a, $b \t! using $xtmp and $rtmp as TEMP" %}
4484 ins_encode %{
4485 emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xtmp$$XMMRegister, $rtmp$$Register,
4486 false /*min*/, false /*single*/);
4487 %}
4488 ins_pipe( pipe_slow );
4489 %}
4490
4491 // min = java.lang.Math.min(float a, float b)
4492 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
4493 predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
4494 match(Set dst (MinF a b));
4495 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4496 format %{ "minF $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
4497 ins_encode %{
4498 __ vminmax_fp(Op_MinV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4499 %}
4500 ins_pipe( pipe_slow );
4501 %}
4502
4503 instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xtmp, rRegI rtmp, rFlagsReg cr) %{
4504 predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
4505 match(Set dst (MinF a b));
4506 effect(USE a, USE b, TEMP xtmp, TEMP rtmp, KILL cr);
4507
4508 format %{ "minF_reduction $dst, $a, $b \t! using $xtmp and $rtmp as TEMP" %}
4509 ins_encode %{
4510 emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xtmp$$XMMRegister, $rtmp$$Register,
4511 true /*min*/, true /*single*/);
4512 %}
4513 ins_pipe( pipe_slow );
4514 %}
4515
4516 // min = java.lang.Math.min(double a, double b)
4517 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
4518 predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
4519 match(Set dst (MinD a b));
4520 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4521 format %{ "minD $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
4522 ins_encode %{
4523 __ vminmax_fp(Op_MinV, T_DOUBLE, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4524 %}
4525 ins_pipe( pipe_slow );
4526 %}
4527
4528 instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xtmp, rRegL rtmp, rFlagsReg cr) %{
4529 predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
4530 match(Set dst (MinD a b));
4531 effect(USE a, USE b, TEMP xtmp, TEMP rtmp, KILL cr);
4532
4533 format %{ "maxD_reduction $dst, $a, $b \t! using $xtmp and $rtmp as TEMP" %}
4534 ins_encode %{
4535 emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xtmp$$XMMRegister, $rtmp$$Register,
4536 true /*min*/, false /*single*/);
4537 %}
4538 ins_pipe( pipe_slow );
4539 %}
4540
4541 // Load Effective Address
4542 instruct leaP8(rRegP dst, indOffset8 mem)
4543 %{
4544 match(Set dst mem);
4545
4546 ins_cost(110); // XXX
4547 format %{ "leaq $dst, $mem\t# ptr 8" %}
4548 ins_encode %{
4549 __ leaq($dst$$Register, $mem$$Address);
4550 %}
4551 ins_pipe(ialu_reg_reg_fat);
4552 %}
4553
4554 instruct leaP32(rRegP dst, indOffset32 mem)
4555 %{
4556 match(Set dst mem);
4557
4558 ins_cost(110);
4559 format %{ "leaq $dst, $mem\t# ptr 32" %}
4560 ins_encode %{
4561 __ leaq($dst$$Register, $mem$$Address);
4562 %}
4563 ins_pipe(ialu_reg_reg_fat);
4564 %}
4565
4566 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
4567 %{
4568 match(Set dst mem);
4569
4570 ins_cost(110);
4571 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
4572 ins_encode %{
4573 __ leaq($dst$$Register, $mem$$Address);
4574 %}
4575 ins_pipe(ialu_reg_reg_fat);
4576 %}
4577
4578 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
4579 %{
4580 match(Set dst mem);
4581
4582 ins_cost(110);
4583 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
4584 ins_encode %{
4585 __ leaq($dst$$Register, $mem$$Address);
4586 %}
4587 ins_pipe(ialu_reg_reg_fat);
4588 %}
4589
4590 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
4591 %{
4592 match(Set dst mem);
4593
4594 ins_cost(110);
4595 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
4596 ins_encode %{
4597 __ leaq($dst$$Register, $mem$$Address);
4598 %}
4599 ins_pipe(ialu_reg_reg_fat);
4600 %}
4601
4602 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
4603 %{
4604 match(Set dst mem);
4605
4606 ins_cost(110);
4607 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
4608 ins_encode %{
4609 __ leaq($dst$$Register, $mem$$Address);
4610 %}
4611 ins_pipe(ialu_reg_reg_fat);
4612 %}
4613
4614 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
4615 %{
4616 match(Set dst mem);
4617
4618 ins_cost(110);
4619 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
4620 ins_encode %{
4621 __ leaq($dst$$Register, $mem$$Address);
4622 %}
4623 ins_pipe(ialu_reg_reg_fat);
4624 %}
4625
4626 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
4627 %{
4628 match(Set dst mem);
4629
4630 ins_cost(110);
4631 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
4632 ins_encode %{
4633 __ leaq($dst$$Register, $mem$$Address);
4634 %}
4635 ins_pipe(ialu_reg_reg_fat);
4636 %}
4637
4638 // Load Effective Address which uses Narrow (32-bits) oop
4639 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
4640 %{
4641 predicate(UseCompressedOops && (CompressedOops::shift() != 0));
4642 match(Set dst mem);
4643
4644 ins_cost(110);
4645 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
4646 ins_encode %{
4647 __ leaq($dst$$Register, $mem$$Address);
4648 %}
4649 ins_pipe(ialu_reg_reg_fat);
4650 %}
4651
4652 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
4653 %{
4654 predicate(CompressedOops::shift() == 0);
4655 match(Set dst mem);
4656
4657 ins_cost(110); // XXX
4658 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
4659 ins_encode %{
4660 __ leaq($dst$$Register, $mem$$Address);
4661 %}
4662 ins_pipe(ialu_reg_reg_fat);
4663 %}
4664
4665 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
4666 %{
4667 predicate(CompressedOops::shift() == 0);
4668 match(Set dst mem);
4669
4670 ins_cost(110);
4671 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
4672 ins_encode %{
4673 __ leaq($dst$$Register, $mem$$Address);
4674 %}
4675 ins_pipe(ialu_reg_reg_fat);
4676 %}
4677
4678 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
4679 %{
4680 predicate(CompressedOops::shift() == 0);
4681 match(Set dst mem);
4682
4683 ins_cost(110);
4684 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
4685 ins_encode %{
4686 __ leaq($dst$$Register, $mem$$Address);
4687 %}
4688 ins_pipe(ialu_reg_reg_fat);
4689 %}
4690
4691 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
4692 %{
4693 predicate(CompressedOops::shift() == 0);
4694 match(Set dst mem);
4695
4696 ins_cost(110);
4697 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
4698 ins_encode %{
4699 __ leaq($dst$$Register, $mem$$Address);
4700 %}
4701 ins_pipe(ialu_reg_reg_fat);
4702 %}
4703
4704 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
4705 %{
4706 predicate(CompressedOops::shift() == 0);
4707 match(Set dst mem);
4708
4709 ins_cost(110);
4710 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
4711 ins_encode %{
4712 __ leaq($dst$$Register, $mem$$Address);
4713 %}
4714 ins_pipe(ialu_reg_reg_fat);
4715 %}
4716
4717 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
4718 %{
4719 predicate(CompressedOops::shift() == 0);
4720 match(Set dst mem);
4721
4722 ins_cost(110);
4723 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
4724 ins_encode %{
4725 __ leaq($dst$$Register, $mem$$Address);
4726 %}
4727 ins_pipe(ialu_reg_reg_fat);
4728 %}
4729
4730 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
4731 %{
4732 predicate(CompressedOops::shift() == 0);
4733 match(Set dst mem);
4734
4735 ins_cost(110);
4736 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
4737 ins_encode %{
4738 __ leaq($dst$$Register, $mem$$Address);
4739 %}
4740 ins_pipe(ialu_reg_reg_fat);
4741 %}
4742
4743 instruct loadConI(rRegI dst, immI src)
4744 %{
4745 match(Set dst src);
4746
4747 format %{ "movl $dst, $src\t# int" %}
4748 ins_encode %{
4749 __ movl($dst$$Register, $src$$constant);
4750 %}
4751 ins_pipe(ialu_reg_fat); // XXX
4752 %}
4753
4754 instruct loadConI0(rRegI dst, immI_0 src, rFlagsReg cr)
4755 %{
4756 match(Set dst src);
4757 effect(KILL cr);
4758
4759 ins_cost(50);
4760 format %{ "xorl $dst, $dst\t# int" %}
4761 ins_encode %{
4762 __ xorl($dst$$Register, $dst$$Register);
4763 %}
4764 ins_pipe(ialu_reg);
4765 %}
4766
4767 instruct loadConL(rRegL dst, immL src)
4768 %{
4769 match(Set dst src);
4770
4771 ins_cost(150);
4772 format %{ "movq $dst, $src\t# long" %}
4773 ins_encode %{
4774 __ mov64($dst$$Register, $src$$constant);
4775 %}
4776 ins_pipe(ialu_reg);
4777 %}
4778
4779 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
4780 %{
4781 match(Set dst src);
4782 effect(KILL cr);
4783
4784 ins_cost(50);
4785 format %{ "xorl $dst, $dst\t# long" %}
4786 ins_encode %{
4787 __ xorl($dst$$Register, $dst$$Register);
4788 %}
4789 ins_pipe(ialu_reg); // XXX
4790 %}
4791
4792 instruct loadConUL32(rRegL dst, immUL32 src)
4793 %{
4794 match(Set dst src);
4795
4796 ins_cost(60);
4797 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
4798 ins_encode %{
4799 __ movl($dst$$Register, $src$$constant);
4800 %}
4801 ins_pipe(ialu_reg);
4802 %}
4803
4804 instruct loadConL32(rRegL dst, immL32 src)
4805 %{
4806 match(Set dst src);
4807
4808 ins_cost(70);
4809 format %{ "movq $dst, $src\t# long (32-bit)" %}
4810 ins_encode %{
4811 __ movq($dst$$Register, $src$$constant);
4812 %}
4813 ins_pipe(ialu_reg);
4814 %}
4815
4816 instruct loadConP(rRegP dst, immP con) %{
4817 match(Set dst con);
4818
4819 format %{ "movq $dst, $con\t# ptr" %}
4820 ins_encode %{
4821 __ mov64($dst$$Register, $con$$constant, $con->constant_reloc(), RELOC_IMM64);
4822 %}
4823 ins_pipe(ialu_reg_fat); // XXX
4824 %}
4825
4826 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
4827 %{
4828 match(Set dst src);
4829 effect(KILL cr);
4830
4831 ins_cost(50);
4832 format %{ "xorl $dst, $dst\t# ptr" %}
4833 ins_encode %{
4834 __ xorl($dst$$Register, $dst$$Register);
4835 %}
4836 ins_pipe(ialu_reg);
4837 %}
4838
4839 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
4840 %{
4841 match(Set dst src);
4842 effect(KILL cr);
4843
4844 ins_cost(60);
4845 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
4846 ins_encode %{
4847 __ movl($dst$$Register, $src$$constant);
4848 %}
4849 ins_pipe(ialu_reg);
4850 %}
4851
4852 instruct loadConF(regF dst, immF con) %{
4853 match(Set dst con);
4854 ins_cost(125);
4855 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
4856 ins_encode %{
4857 __ movflt($dst$$XMMRegister, $constantaddress($con));
4858 %}
4859 ins_pipe(pipe_slow);
4860 %}
4861
4862 instruct loadConH(regF dst, immH con) %{
4863 match(Set dst con);
4864 ins_cost(125);
4865 format %{ "movss $dst, [$constantaddress]\t# load from constant table: halffloat=$con" %}
4866 ins_encode %{
4867 __ movflt($dst$$XMMRegister, $constantaddress($con));
4868 %}
4869 ins_pipe(pipe_slow);
4870 %}
4871
4872 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
4873 match(Set dst src);
4874 effect(KILL cr);
4875 format %{ "xorq $dst, $src\t# compressed null pointer" %}
4876 ins_encode %{
4877 __ xorq($dst$$Register, $dst$$Register);
4878 %}
4879 ins_pipe(ialu_reg);
4880 %}
4881
4882 instruct loadConN(rRegN dst, immN src) %{
4883 match(Set dst src);
4884
4885 ins_cost(125);
4886 format %{ "movl $dst, $src\t# compressed ptr" %}
4887 ins_encode %{
4888 address con = (address)$src$$constant;
4889 if (con == nullptr) {
4890 ShouldNotReachHere();
4891 } else {
4892 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
4893 }
4894 %}
4895 ins_pipe(ialu_reg_fat); // XXX
4896 %}
4897
4898 instruct loadConNKlass(rRegN dst, immNKlass src) %{
4899 match(Set dst src);
4900
4901 ins_cost(125);
4902 format %{ "movl $dst, $src\t# compressed klass ptr" %}
4903 ins_encode %{
4904 address con = (address)$src$$constant;
4905 if (con == nullptr) {
4906 ShouldNotReachHere();
4907 } else {
4908 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
4909 }
4910 %}
4911 ins_pipe(ialu_reg_fat); // XXX
4912 %}
4913
4914 instruct loadConF0(regF dst, immF0 src)
4915 %{
4916 match(Set dst src);
4917 ins_cost(100);
4918
4919 format %{ "xorps $dst, $dst\t# float 0.0" %}
4920 ins_encode %{
4921 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
4922 %}
4923 ins_pipe(pipe_slow);
4924 %}
4925
4926 // Use the same format since predicate() can not be used here.
4927 instruct loadConD(regD dst, immD con) %{
4928 match(Set dst con);
4929 ins_cost(125);
4930 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
4931 ins_encode %{
4932 __ movdbl($dst$$XMMRegister, $constantaddress($con));
4933 %}
4934 ins_pipe(pipe_slow);
4935 %}
4936
4937 instruct loadConD0(regD dst, immD0 src)
4938 %{
4939 match(Set dst src);
4940 ins_cost(100);
4941
4942 format %{ "xorpd $dst, $dst\t# double 0.0" %}
4943 ins_encode %{
4944 __ xorpd($dst$$XMMRegister, $dst$$XMMRegister);
4945 %}
4946 ins_pipe(pipe_slow);
4947 %}
4948
4949 instruct loadSSI(rRegI dst, stackSlotI src)
4950 %{
4951 match(Set dst src);
4952
4953 ins_cost(125);
4954 format %{ "movl $dst, $src\t# int stk" %}
4955 ins_encode %{
4956 __ movl($dst$$Register, $src$$Address);
4957 %}
4958 ins_pipe(ialu_reg_mem);
4959 %}
4960
4961 instruct loadSSL(rRegL dst, stackSlotL src)
4962 %{
4963 match(Set dst src);
4964
4965 ins_cost(125);
4966 format %{ "movq $dst, $src\t# long stk" %}
4967 ins_encode %{
4968 __ movq($dst$$Register, $src$$Address);
4969 %}
4970 ins_pipe(ialu_reg_mem);
4971 %}
4972
4973 instruct loadSSP(rRegP dst, stackSlotP src)
4974 %{
4975 match(Set dst src);
4976
4977 ins_cost(125);
4978 format %{ "movq $dst, $src\t# ptr stk" %}
4979 ins_encode %{
4980 __ movq($dst$$Register, $src$$Address);
4981 %}
4982 ins_pipe(ialu_reg_mem);
4983 %}
4984
4985 instruct loadSSF(regF dst, stackSlotF src)
4986 %{
4987 match(Set dst src);
4988
4989 ins_cost(125);
4990 format %{ "movss $dst, $src\t# float stk" %}
4991 ins_encode %{
4992 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
4993 %}
4994 ins_pipe(pipe_slow); // XXX
4995 %}
4996
4997 // Use the same format since predicate() can not be used here.
4998 instruct loadSSD(regD dst, stackSlotD src)
4999 %{
5000 match(Set dst src);
5001
5002 ins_cost(125);
5003 format %{ "movsd $dst, $src\t# double stk" %}
5004 ins_encode %{
5005 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5006 %}
5007 ins_pipe(pipe_slow); // XXX
5008 %}
5009
5010 // Prefetch instructions for allocation.
5011 // Must be safe to execute with invalid address (cannot fault).
5012
5013 instruct prefetchAlloc( memory mem ) %{
5014 predicate(AllocatePrefetchInstr==3);
5015 match(PrefetchAllocation mem);
5016 ins_cost(125);
5017
5018 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5019 ins_encode %{
5020 __ prefetchw($mem$$Address);
5021 %}
5022 ins_pipe(ialu_mem);
5023 %}
5024
5025 instruct prefetchAllocNTA( memory mem ) %{
5026 predicate(AllocatePrefetchInstr==0);
5027 match(PrefetchAllocation mem);
5028 ins_cost(125);
5029
5030 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5031 ins_encode %{
5032 __ prefetchnta($mem$$Address);
5033 %}
5034 ins_pipe(ialu_mem);
5035 %}
5036
5037 instruct prefetchAllocT0( memory mem ) %{
5038 predicate(AllocatePrefetchInstr==1);
5039 match(PrefetchAllocation mem);
5040 ins_cost(125);
5041
5042 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5043 ins_encode %{
5044 __ prefetcht0($mem$$Address);
5045 %}
5046 ins_pipe(ialu_mem);
5047 %}
5048
5049 instruct prefetchAllocT2( memory mem ) %{
5050 predicate(AllocatePrefetchInstr==2);
5051 match(PrefetchAllocation mem);
5052 ins_cost(125);
5053
5054 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5055 ins_encode %{
5056 __ prefetcht2($mem$$Address);
5057 %}
5058 ins_pipe(ialu_mem);
5059 %}
5060
5061 //----------Store Instructions-------------------------------------------------
5062
5063 // Store Byte
5064 instruct storeB(memory mem, rRegI src)
5065 %{
5066 match(Set mem (StoreB mem src));
5067
5068 ins_cost(125); // XXX
5069 format %{ "movb $mem, $src\t# byte" %}
5070 ins_encode %{
5071 __ movb($mem$$Address, $src$$Register);
5072 %}
5073 ins_pipe(ialu_mem_reg);
5074 %}
5075
5076 // Store Char/Short
5077 instruct storeC(memory mem, rRegI src)
5078 %{
5079 match(Set mem (StoreC mem src));
5080
5081 ins_cost(125); // XXX
5082 format %{ "movw $mem, $src\t# char/short" %}
5083 ins_encode %{
5084 __ movw($mem$$Address, $src$$Register);
5085 %}
5086 ins_pipe(ialu_mem_reg);
5087 %}
5088
5089 // Store Integer
5090 instruct storeI(memory mem, rRegI src)
5091 %{
5092 match(Set mem (StoreI mem src));
5093
5094 ins_cost(125); // XXX
5095 format %{ "movl $mem, $src\t# int" %}
5096 ins_encode %{
5097 __ movl($mem$$Address, $src$$Register);
5098 %}
5099 ins_pipe(ialu_mem_reg);
5100 %}
5101
5102 // Store Long
5103 instruct storeL(memory mem, rRegL src)
5104 %{
5105 match(Set mem (StoreL mem src));
5106
5107 ins_cost(125); // XXX
5108 format %{ "movq $mem, $src\t# long" %}
5109 ins_encode %{
5110 __ movq($mem$$Address, $src$$Register);
5111 %}
5112 ins_pipe(ialu_mem_reg); // XXX
5113 %}
5114
5115 // Store Pointer
5116 instruct storeP(memory mem, any_RegP src)
5117 %{
5118 predicate(n->as_Store()->barrier_data() == 0);
5119 match(Set mem (StoreP mem src));
5120
5121 ins_cost(125); // XXX
5122 format %{ "movq $mem, $src\t# ptr" %}
5123 ins_encode %{
5124 __ movq($mem$$Address, $src$$Register);
5125 %}
5126 ins_pipe(ialu_mem_reg);
5127 %}
5128
5129 instruct storeImmP0(memory mem, immP0 zero)
5130 %{
5131 predicate(UseCompressedOops && (CompressedOops::base() == nullptr) && n->as_Store()->barrier_data() == 0);
5132 match(Set mem (StoreP mem zero));
5133
5134 ins_cost(125); // XXX
5135 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5136 ins_encode %{
5137 __ movq($mem$$Address, r12);
5138 %}
5139 ins_pipe(ialu_mem_reg);
5140 %}
5141
5142 // Store Null Pointer, mark word, or other simple pointer constant.
5143 instruct storeImmP(memory mem, immP31 src)
5144 %{
5145 predicate(n->as_Store()->barrier_data() == 0);
5146 match(Set mem (StoreP mem src));
5147
5148 ins_cost(150); // XXX
5149 format %{ "movq $mem, $src\t# ptr" %}
5150 ins_encode %{
5151 __ movq($mem$$Address, $src$$constant);
5152 %}
5153 ins_pipe(ialu_mem_imm);
5154 %}
5155
5156 // Store Compressed Pointer
5157 instruct storeN(memory mem, rRegN src)
5158 %{
5159 predicate(n->as_Store()->barrier_data() == 0);
5160 match(Set mem (StoreN mem src));
5161
5162 ins_cost(125); // XXX
5163 format %{ "movl $mem, $src\t# compressed ptr" %}
5164 ins_encode %{
5165 __ movl($mem$$Address, $src$$Register);
5166 %}
5167 ins_pipe(ialu_mem_reg);
5168 %}
5169
5170 instruct storeNKlass(memory mem, rRegN src)
5171 %{
5172 match(Set mem (StoreNKlass mem src));
5173
5174 ins_cost(125); // XXX
5175 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5176 ins_encode %{
5177 __ movl($mem$$Address, $src$$Register);
5178 %}
5179 ins_pipe(ialu_mem_reg);
5180 %}
5181
5182 instruct storeImmN0(memory mem, immN0 zero)
5183 %{
5184 predicate(CompressedOops::base() == nullptr && n->as_Store()->barrier_data() == 0);
5185 match(Set mem (StoreN mem zero));
5186
5187 ins_cost(125); // XXX
5188 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5189 ins_encode %{
5190 __ movl($mem$$Address, r12);
5191 %}
5192 ins_pipe(ialu_mem_reg);
5193 %}
5194
5195 instruct storeImmN(memory mem, immN src)
5196 %{
5197 predicate(n->as_Store()->barrier_data() == 0);
5198 match(Set mem (StoreN mem src));
5199
5200 ins_cost(150); // XXX
5201 format %{ "movl $mem, $src\t# compressed ptr" %}
5202 ins_encode %{
5203 address con = (address)$src$$constant;
5204 if (con == nullptr) {
5205 __ movl($mem$$Address, 0);
5206 } else {
5207 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5208 }
5209 %}
5210 ins_pipe(ialu_mem_imm);
5211 %}
5212
5213 instruct storeImmNKlass(memory mem, immNKlass src)
5214 %{
5215 match(Set mem (StoreNKlass mem src));
5216
5217 ins_cost(150); // XXX
5218 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5219 ins_encode %{
5220 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5221 %}
5222 ins_pipe(ialu_mem_imm);
5223 %}
5224
5225 // Store Integer Immediate
5226 instruct storeImmI0(memory mem, immI_0 zero)
5227 %{
5228 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5229 match(Set mem (StoreI mem zero));
5230
5231 ins_cost(125); // XXX
5232 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5233 ins_encode %{
5234 __ movl($mem$$Address, r12);
5235 %}
5236 ins_pipe(ialu_mem_reg);
5237 %}
5238
5239 instruct storeImmI(memory mem, immI src)
5240 %{
5241 match(Set mem (StoreI mem src));
5242
5243 ins_cost(150);
5244 format %{ "movl $mem, $src\t# int" %}
5245 ins_encode %{
5246 __ movl($mem$$Address, $src$$constant);
5247 %}
5248 ins_pipe(ialu_mem_imm);
5249 %}
5250
5251 // Store Long Immediate
5252 instruct storeImmL0(memory mem, immL0 zero)
5253 %{
5254 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5255 match(Set mem (StoreL mem zero));
5256
5257 ins_cost(125); // XXX
5258 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5259 ins_encode %{
5260 __ movq($mem$$Address, r12);
5261 %}
5262 ins_pipe(ialu_mem_reg);
5263 %}
5264
5265 instruct storeImmL(memory mem, immL32 src)
5266 %{
5267 match(Set mem (StoreL mem src));
5268
5269 ins_cost(150);
5270 format %{ "movq $mem, $src\t# long" %}
5271 ins_encode %{
5272 __ movq($mem$$Address, $src$$constant);
5273 %}
5274 ins_pipe(ialu_mem_imm);
5275 %}
5276
5277 // Store Short/Char Immediate
5278 instruct storeImmC0(memory mem, immI_0 zero)
5279 %{
5280 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5281 match(Set mem (StoreC mem zero));
5282
5283 ins_cost(125); // XXX
5284 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5285 ins_encode %{
5286 __ movw($mem$$Address, r12);
5287 %}
5288 ins_pipe(ialu_mem_reg);
5289 %}
5290
5291 instruct storeImmI16(memory mem, immI16 src)
5292 %{
5293 predicate(UseStoreImmI16);
5294 match(Set mem (StoreC mem src));
5295
5296 ins_cost(150);
5297 format %{ "movw $mem, $src\t# short/char" %}
5298 ins_encode %{
5299 __ movw($mem$$Address, $src$$constant);
5300 %}
5301 ins_pipe(ialu_mem_imm);
5302 %}
5303
5304 // Store Byte Immediate
5305 instruct storeImmB0(memory mem, immI_0 zero)
5306 %{
5307 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5308 match(Set mem (StoreB mem zero));
5309
5310 ins_cost(125); // XXX
5311 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5312 ins_encode %{
5313 __ movb($mem$$Address, r12);
5314 %}
5315 ins_pipe(ialu_mem_reg);
5316 %}
5317
5318 instruct storeImmB(memory mem, immI8 src)
5319 %{
5320 match(Set mem (StoreB mem src));
5321
5322 ins_cost(150); // XXX
5323 format %{ "movb $mem, $src\t# byte" %}
5324 ins_encode %{
5325 __ movb($mem$$Address, $src$$constant);
5326 %}
5327 ins_pipe(ialu_mem_imm);
5328 %}
5329
5330 // Store Float
5331 instruct storeF(memory mem, regF src)
5332 %{
5333 match(Set mem (StoreF mem src));
5334
5335 ins_cost(95); // XXX
5336 format %{ "movss $mem, $src\t# float" %}
5337 ins_encode %{
5338 __ movflt($mem$$Address, $src$$XMMRegister);
5339 %}
5340 ins_pipe(pipe_slow); // XXX
5341 %}
5342
5343 // Store immediate Float value (it is faster than store from XMM register)
5344 instruct storeF0(memory mem, immF0 zero)
5345 %{
5346 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5347 match(Set mem (StoreF mem zero));
5348
5349 ins_cost(25); // XXX
5350 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5351 ins_encode %{
5352 __ movl($mem$$Address, r12);
5353 %}
5354 ins_pipe(ialu_mem_reg);
5355 %}
5356
5357 instruct storeF_imm(memory mem, immF src)
5358 %{
5359 match(Set mem (StoreF mem src));
5360
5361 ins_cost(50);
5362 format %{ "movl $mem, $src\t# float" %}
5363 ins_encode %{
5364 __ movl($mem$$Address, jint_cast($src$$constant));
5365 %}
5366 ins_pipe(ialu_mem_imm);
5367 %}
5368
5369 // Store Double
5370 instruct storeD(memory mem, regD src)
5371 %{
5372 match(Set mem (StoreD mem src));
5373
5374 ins_cost(95); // XXX
5375 format %{ "movsd $mem, $src\t# double" %}
5376 ins_encode %{
5377 __ movdbl($mem$$Address, $src$$XMMRegister);
5378 %}
5379 ins_pipe(pipe_slow); // XXX
5380 %}
5381
5382 // Store immediate double 0.0 (it is faster than store from XMM register)
5383 instruct storeD0_imm(memory mem, immD0 src)
5384 %{
5385 predicate(!UseCompressedOops || (CompressedOops::base() != nullptr));
5386 match(Set mem (StoreD mem src));
5387
5388 ins_cost(50);
5389 format %{ "movq $mem, $src\t# double 0." %}
5390 ins_encode %{
5391 __ movq($mem$$Address, $src$$constant);
5392 %}
5393 ins_pipe(ialu_mem_imm);
5394 %}
5395
5396 instruct storeD0(memory mem, immD0 zero)
5397 %{
5398 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5399 match(Set mem (StoreD mem zero));
5400
5401 ins_cost(25); // XXX
5402 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
5403 ins_encode %{
5404 __ movq($mem$$Address, r12);
5405 %}
5406 ins_pipe(ialu_mem_reg);
5407 %}
5408
5409 instruct storeSSI(stackSlotI dst, rRegI src)
5410 %{
5411 match(Set dst src);
5412
5413 ins_cost(100);
5414 format %{ "movl $dst, $src\t# int stk" %}
5415 ins_encode %{
5416 __ movl($dst$$Address, $src$$Register);
5417 %}
5418 ins_pipe( ialu_mem_reg );
5419 %}
5420
5421 instruct storeSSL(stackSlotL dst, rRegL src)
5422 %{
5423 match(Set dst src);
5424
5425 ins_cost(100);
5426 format %{ "movq $dst, $src\t# long stk" %}
5427 ins_encode %{
5428 __ movq($dst$$Address, $src$$Register);
5429 %}
5430 ins_pipe(ialu_mem_reg);
5431 %}
5432
5433 instruct storeSSP(stackSlotP dst, rRegP src)
5434 %{
5435 match(Set dst src);
5436
5437 ins_cost(100);
5438 format %{ "movq $dst, $src\t# ptr stk" %}
5439 ins_encode %{
5440 __ movq($dst$$Address, $src$$Register);
5441 %}
5442 ins_pipe(ialu_mem_reg);
5443 %}
5444
5445 instruct storeSSF(stackSlotF dst, regF src)
5446 %{
5447 match(Set dst src);
5448
5449 ins_cost(95); // XXX
5450 format %{ "movss $dst, $src\t# float stk" %}
5451 ins_encode %{
5452 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
5453 %}
5454 ins_pipe(pipe_slow); // XXX
5455 %}
5456
5457 instruct storeSSD(stackSlotD dst, regD src)
5458 %{
5459 match(Set dst src);
5460
5461 ins_cost(95); // XXX
5462 format %{ "movsd $dst, $src\t# double stk" %}
5463 ins_encode %{
5464 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
5465 %}
5466 ins_pipe(pipe_slow); // XXX
5467 %}
5468
5469 instruct cacheWB(indirect addr)
5470 %{
5471 predicate(VM_Version::supports_data_cache_line_flush());
5472 match(CacheWB addr);
5473
5474 ins_cost(100);
5475 format %{"cache wb $addr" %}
5476 ins_encode %{
5477 assert($addr->index_position() < 0, "should be");
5478 assert($addr$$disp == 0, "should be");
5479 __ cache_wb(Address($addr$$base$$Register, 0));
5480 %}
5481 ins_pipe(pipe_slow); // XXX
5482 %}
5483
5484 instruct cacheWBPreSync()
5485 %{
5486 predicate(VM_Version::supports_data_cache_line_flush());
5487 match(CacheWBPreSync);
5488
5489 ins_cost(100);
5490 format %{"cache wb presync" %}
5491 ins_encode %{
5492 __ cache_wbsync(true);
5493 %}
5494 ins_pipe(pipe_slow); // XXX
5495 %}
5496
5497 instruct cacheWBPostSync()
5498 %{
5499 predicate(VM_Version::supports_data_cache_line_flush());
5500 match(CacheWBPostSync);
5501
5502 ins_cost(100);
5503 format %{"cache wb postsync" %}
5504 ins_encode %{
5505 __ cache_wbsync(false);
5506 %}
5507 ins_pipe(pipe_slow); // XXX
5508 %}
5509
5510 //----------BSWAP Instructions-------------------------------------------------
5511 instruct bytes_reverse_int(rRegI dst) %{
5512 match(Set dst (ReverseBytesI dst));
5513
5514 format %{ "bswapl $dst" %}
5515 ins_encode %{
5516 __ bswapl($dst$$Register);
5517 %}
5518 ins_pipe( ialu_reg );
5519 %}
5520
5521 instruct bytes_reverse_long(rRegL dst) %{
5522 match(Set dst (ReverseBytesL dst));
5523
5524 format %{ "bswapq $dst" %}
5525 ins_encode %{
5526 __ bswapq($dst$$Register);
5527 %}
5528 ins_pipe( ialu_reg);
5529 %}
5530
5531 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
5532 match(Set dst (ReverseBytesUS dst));
5533 effect(KILL cr);
5534
5535 format %{ "bswapl $dst\n\t"
5536 "shrl $dst,16\n\t" %}
5537 ins_encode %{
5538 __ bswapl($dst$$Register);
5539 __ shrl($dst$$Register, 16);
5540 %}
5541 ins_pipe( ialu_reg );
5542 %}
5543
5544 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
5545 match(Set dst (ReverseBytesS dst));
5546 effect(KILL cr);
5547
5548 format %{ "bswapl $dst\n\t"
5549 "sar $dst,16\n\t" %}
5550 ins_encode %{
5551 __ bswapl($dst$$Register);
5552 __ sarl($dst$$Register, 16);
5553 %}
5554 ins_pipe( ialu_reg );
5555 %}
5556
5557 //---------- Zeros Count Instructions ------------------------------------------
5558
5559 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
5560 predicate(UseCountLeadingZerosInstruction);
5561 match(Set dst (CountLeadingZerosI src));
5562 effect(KILL cr);
5563
5564 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
5565 ins_encode %{
5566 __ lzcntl($dst$$Register, $src$$Register);
5567 %}
5568 ins_pipe(ialu_reg);
5569 %}
5570
5571 instruct countLeadingZerosI_mem(rRegI dst, memory src, rFlagsReg cr) %{
5572 predicate(UseCountLeadingZerosInstruction);
5573 match(Set dst (CountLeadingZerosI (LoadI src)));
5574 effect(KILL cr);
5575 ins_cost(175);
5576 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
5577 ins_encode %{
5578 __ lzcntl($dst$$Register, $src$$Address);
5579 %}
5580 ins_pipe(ialu_reg_mem);
5581 %}
5582
5583 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
5584 predicate(!UseCountLeadingZerosInstruction);
5585 match(Set dst (CountLeadingZerosI src));
5586 effect(KILL cr);
5587
5588 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
5589 "jnz skip\n\t"
5590 "movl $dst, -1\n"
5591 "skip:\n\t"
5592 "negl $dst\n\t"
5593 "addl $dst, 31" %}
5594 ins_encode %{
5595 Register Rdst = $dst$$Register;
5596 Register Rsrc = $src$$Register;
5597 Label skip;
5598 __ bsrl(Rdst, Rsrc);
5599 __ jccb(Assembler::notZero, skip);
5600 __ movl(Rdst, -1);
5601 __ bind(skip);
5602 __ negl(Rdst);
5603 __ addl(Rdst, BitsPerInt - 1);
5604 %}
5605 ins_pipe(ialu_reg);
5606 %}
5607
5608 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
5609 predicate(UseCountLeadingZerosInstruction);
5610 match(Set dst (CountLeadingZerosL src));
5611 effect(KILL cr);
5612
5613 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
5614 ins_encode %{
5615 __ lzcntq($dst$$Register, $src$$Register);
5616 %}
5617 ins_pipe(ialu_reg);
5618 %}
5619
5620 instruct countLeadingZerosL_mem(rRegI dst, memory src, rFlagsReg cr) %{
5621 predicate(UseCountLeadingZerosInstruction);
5622 match(Set dst (CountLeadingZerosL (LoadL src)));
5623 effect(KILL cr);
5624 ins_cost(175);
5625 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
5626 ins_encode %{
5627 __ lzcntq($dst$$Register, $src$$Address);
5628 %}
5629 ins_pipe(ialu_reg_mem);
5630 %}
5631
5632 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
5633 predicate(!UseCountLeadingZerosInstruction);
5634 match(Set dst (CountLeadingZerosL src));
5635 effect(KILL cr);
5636
5637 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
5638 "jnz skip\n\t"
5639 "movl $dst, -1\n"
5640 "skip:\n\t"
5641 "negl $dst\n\t"
5642 "addl $dst, 63" %}
5643 ins_encode %{
5644 Register Rdst = $dst$$Register;
5645 Register Rsrc = $src$$Register;
5646 Label skip;
5647 __ bsrq(Rdst, Rsrc);
5648 __ jccb(Assembler::notZero, skip);
5649 __ movl(Rdst, -1);
5650 __ bind(skip);
5651 __ negl(Rdst);
5652 __ addl(Rdst, BitsPerLong - 1);
5653 %}
5654 ins_pipe(ialu_reg);
5655 %}
5656
5657 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
5658 predicate(UseCountTrailingZerosInstruction);
5659 match(Set dst (CountTrailingZerosI src));
5660 effect(KILL cr);
5661
5662 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
5663 ins_encode %{
5664 __ tzcntl($dst$$Register, $src$$Register);
5665 %}
5666 ins_pipe(ialu_reg);
5667 %}
5668
5669 instruct countTrailingZerosI_mem(rRegI dst, memory src, rFlagsReg cr) %{
5670 predicate(UseCountTrailingZerosInstruction);
5671 match(Set dst (CountTrailingZerosI (LoadI src)));
5672 effect(KILL cr);
5673 ins_cost(175);
5674 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
5675 ins_encode %{
5676 __ tzcntl($dst$$Register, $src$$Address);
5677 %}
5678 ins_pipe(ialu_reg_mem);
5679 %}
5680
5681 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
5682 predicate(!UseCountTrailingZerosInstruction);
5683 match(Set dst (CountTrailingZerosI src));
5684 effect(KILL cr);
5685
5686 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
5687 "jnz done\n\t"
5688 "movl $dst, 32\n"
5689 "done:" %}
5690 ins_encode %{
5691 Register Rdst = $dst$$Register;
5692 Label done;
5693 __ bsfl(Rdst, $src$$Register);
5694 __ jccb(Assembler::notZero, done);
5695 __ movl(Rdst, BitsPerInt);
5696 __ bind(done);
5697 %}
5698 ins_pipe(ialu_reg);
5699 %}
5700
5701 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
5702 predicate(UseCountTrailingZerosInstruction);
5703 match(Set dst (CountTrailingZerosL src));
5704 effect(KILL cr);
5705
5706 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
5707 ins_encode %{
5708 __ tzcntq($dst$$Register, $src$$Register);
5709 %}
5710 ins_pipe(ialu_reg);
5711 %}
5712
5713 instruct countTrailingZerosL_mem(rRegI dst, memory src, rFlagsReg cr) %{
5714 predicate(UseCountTrailingZerosInstruction);
5715 match(Set dst (CountTrailingZerosL (LoadL src)));
5716 effect(KILL cr);
5717 ins_cost(175);
5718 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
5719 ins_encode %{
5720 __ tzcntq($dst$$Register, $src$$Address);
5721 %}
5722 ins_pipe(ialu_reg_mem);
5723 %}
5724
5725 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
5726 predicate(!UseCountTrailingZerosInstruction);
5727 match(Set dst (CountTrailingZerosL src));
5728 effect(KILL cr);
5729
5730 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
5731 "jnz done\n\t"
5732 "movl $dst, 64\n"
5733 "done:" %}
5734 ins_encode %{
5735 Register Rdst = $dst$$Register;
5736 Label done;
5737 __ bsfq(Rdst, $src$$Register);
5738 __ jccb(Assembler::notZero, done);
5739 __ movl(Rdst, BitsPerLong);
5740 __ bind(done);
5741 %}
5742 ins_pipe(ialu_reg);
5743 %}
5744
5745 //--------------- Reverse Operation Instructions ----------------
5746 instruct bytes_reversebit_int(rRegI dst, rRegI src, rRegI rtmp, rFlagsReg cr) %{
5747 predicate(!VM_Version::supports_gfni());
5748 match(Set dst (ReverseI src));
5749 effect(TEMP dst, TEMP rtmp, KILL cr);
5750 format %{ "reverse_int $dst $src\t! using $rtmp as TEMP" %}
5751 ins_encode %{
5752 __ reverseI($dst$$Register, $src$$Register, xnoreg, xnoreg, $rtmp$$Register);
5753 %}
5754 ins_pipe( ialu_reg );
5755 %}
5756
5757 instruct bytes_reversebit_int_gfni(rRegI dst, rRegI src, vlRegF xtmp1, vlRegF xtmp2, rRegL rtmp, rFlagsReg cr) %{
5758 predicate(VM_Version::supports_gfni());
5759 match(Set dst (ReverseI src));
5760 effect(TEMP dst, TEMP xtmp1, TEMP xtmp2, TEMP rtmp, KILL cr);
5761 format %{ "reverse_int $dst $src\t! using $rtmp, $xtmp1 and $xtmp2 as TEMP" %}
5762 ins_encode %{
5763 __ reverseI($dst$$Register, $src$$Register, $xtmp1$$XMMRegister, $xtmp2$$XMMRegister, $rtmp$$Register);
5764 %}
5765 ins_pipe( ialu_reg );
5766 %}
5767
5768 instruct bytes_reversebit_long(rRegL dst, rRegL src, rRegL rtmp1, rRegL rtmp2, rFlagsReg cr) %{
5769 predicate(!VM_Version::supports_gfni());
5770 match(Set dst (ReverseL src));
5771 effect(TEMP dst, TEMP rtmp1, TEMP rtmp2, KILL cr);
5772 format %{ "reverse_long $dst $src\t! using $rtmp1 and $rtmp2 as TEMP" %}
5773 ins_encode %{
5774 __ reverseL($dst$$Register, $src$$Register, xnoreg, xnoreg, $rtmp1$$Register, $rtmp2$$Register);
5775 %}
5776 ins_pipe( ialu_reg );
5777 %}
5778
5779 instruct bytes_reversebit_long_gfni(rRegL dst, rRegL src, vlRegD xtmp1, vlRegD xtmp2, rRegL rtmp, rFlagsReg cr) %{
5780 predicate(VM_Version::supports_gfni());
5781 match(Set dst (ReverseL src));
5782 effect(TEMP dst, TEMP xtmp1, TEMP xtmp2, TEMP rtmp, KILL cr);
5783 format %{ "reverse_long $dst $src\t! using $rtmp, $xtmp1 and $xtmp2 as TEMP" %}
5784 ins_encode %{
5785 __ reverseL($dst$$Register, $src$$Register, $xtmp1$$XMMRegister, $xtmp2$$XMMRegister, $rtmp$$Register, noreg);
5786 %}
5787 ins_pipe( ialu_reg );
5788 %}
5789
5790 //---------- Population Count Instructions -------------------------------------
5791
5792 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
5793 predicate(UsePopCountInstruction);
5794 match(Set dst (PopCountI src));
5795 effect(KILL cr);
5796
5797 format %{ "popcnt $dst, $src" %}
5798 ins_encode %{
5799 __ popcntl($dst$$Register, $src$$Register);
5800 %}
5801 ins_pipe(ialu_reg);
5802 %}
5803
5804 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
5805 predicate(UsePopCountInstruction);
5806 match(Set dst (PopCountI (LoadI mem)));
5807 effect(KILL cr);
5808
5809 format %{ "popcnt $dst, $mem" %}
5810 ins_encode %{
5811 __ popcntl($dst$$Register, $mem$$Address);
5812 %}
5813 ins_pipe(ialu_reg);
5814 %}
5815
5816 // Note: Long.bitCount(long) returns an int.
5817 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
5818 predicate(UsePopCountInstruction);
5819 match(Set dst (PopCountL src));
5820 effect(KILL cr);
5821
5822 format %{ "popcnt $dst, $src" %}
5823 ins_encode %{
5824 __ popcntq($dst$$Register, $src$$Register);
5825 %}
5826 ins_pipe(ialu_reg);
5827 %}
5828
5829 // Note: Long.bitCount(long) returns an int.
5830 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
5831 predicate(UsePopCountInstruction);
5832 match(Set dst (PopCountL (LoadL mem)));
5833 effect(KILL cr);
5834
5835 format %{ "popcnt $dst, $mem" %}
5836 ins_encode %{
5837 __ popcntq($dst$$Register, $mem$$Address);
5838 %}
5839 ins_pipe(ialu_reg);
5840 %}
5841
5842
5843 //----------MemBar Instructions-----------------------------------------------
5844 // Memory barrier flavors
5845
5846 instruct membar_acquire()
5847 %{
5848 match(MemBarAcquire);
5849 match(LoadFence);
5850 ins_cost(0);
5851
5852 size(0);
5853 format %{ "MEMBAR-acquire ! (empty encoding)" %}
5854 ins_encode();
5855 ins_pipe(empty);
5856 %}
5857
5858 instruct membar_acquire_lock()
5859 %{
5860 match(MemBarAcquireLock);
5861 ins_cost(0);
5862
5863 size(0);
5864 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
5865 ins_encode();
5866 ins_pipe(empty);
5867 %}
5868
5869 instruct membar_release()
5870 %{
5871 match(MemBarRelease);
5872 match(StoreFence);
5873 ins_cost(0);
5874
5875 size(0);
5876 format %{ "MEMBAR-release ! (empty encoding)" %}
5877 ins_encode();
5878 ins_pipe(empty);
5879 %}
5880
5881 instruct membar_release_lock()
5882 %{
5883 match(MemBarReleaseLock);
5884 ins_cost(0);
5885
5886 size(0);
5887 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
5888 ins_encode();
5889 ins_pipe(empty);
5890 %}
5891
5892 instruct membar_volatile(rFlagsReg cr) %{
5893 match(MemBarVolatile);
5894 effect(KILL cr);
5895 ins_cost(400);
5896
5897 format %{
5898 $$template
5899 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
5900 %}
5901 ins_encode %{
5902 __ membar(Assembler::StoreLoad);
5903 %}
5904 ins_pipe(pipe_slow);
5905 %}
5906
5907 instruct unnecessary_membar_volatile()
5908 %{
5909 match(MemBarVolatile);
5910 predicate(Matcher::post_store_load_barrier(n));
5911 ins_cost(0);
5912
5913 size(0);
5914 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
5915 ins_encode();
5916 ins_pipe(empty);
5917 %}
5918
5919 instruct membar_storestore() %{
5920 match(MemBarStoreStore);
5921 match(StoreStoreFence);
5922 ins_cost(0);
5923
5924 size(0);
5925 format %{ "MEMBAR-storestore (empty encoding)" %}
5926 ins_encode( );
5927 ins_pipe(empty);
5928 %}
5929
5930 //----------Move Instructions--------------------------------------------------
5931
5932 instruct castX2P(rRegP dst, rRegL src)
5933 %{
5934 match(Set dst (CastX2P src));
5935
5936 format %{ "movq $dst, $src\t# long->ptr" %}
5937 ins_encode %{
5938 if ($dst$$reg != $src$$reg) {
5939 __ movptr($dst$$Register, $src$$Register);
5940 }
5941 %}
5942 ins_pipe(ialu_reg_reg); // XXX
5943 %}
5944
5945 instruct castP2X(rRegL dst, rRegP src)
5946 %{
5947 match(Set dst (CastP2X src));
5948
5949 format %{ "movq $dst, $src\t# ptr -> long" %}
5950 ins_encode %{
5951 if ($dst$$reg != $src$$reg) {
5952 __ movptr($dst$$Register, $src$$Register);
5953 }
5954 %}
5955 ins_pipe(ialu_reg_reg); // XXX
5956 %}
5957
5958 // Convert oop into int for vectors alignment masking
5959 instruct convP2I(rRegI dst, rRegP src)
5960 %{
5961 match(Set dst (ConvL2I (CastP2X src)));
5962
5963 format %{ "movl $dst, $src\t# ptr -> int" %}
5964 ins_encode %{
5965 __ movl($dst$$Register, $src$$Register);
5966 %}
5967 ins_pipe(ialu_reg_reg); // XXX
5968 %}
5969
5970 // Convert compressed oop into int for vectors alignment masking
5971 // in case of 32bit oops (heap < 4Gb).
5972 instruct convN2I(rRegI dst, rRegN src)
5973 %{
5974 predicate(CompressedOops::shift() == 0);
5975 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
5976
5977 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
5978 ins_encode %{
5979 __ movl($dst$$Register, $src$$Register);
5980 %}
5981 ins_pipe(ialu_reg_reg); // XXX
5982 %}
5983
5984 // Convert oop pointer into compressed form
5985 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
5986 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
5987 match(Set dst (EncodeP src));
5988 effect(KILL cr);
5989 format %{ "encode_heap_oop $dst,$src" %}
5990 ins_encode %{
5991 Register s = $src$$Register;
5992 Register d = $dst$$Register;
5993 if (s != d) {
5994 __ movq(d, s);
5995 }
5996 __ encode_heap_oop(d);
5997 %}
5998 ins_pipe(ialu_reg_long);
5999 %}
6000
6001 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6002 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6003 match(Set dst (EncodeP src));
6004 effect(KILL cr);
6005 format %{ "encode_heap_oop_not_null $dst,$src" %}
6006 ins_encode %{
6007 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6008 %}
6009 ins_pipe(ialu_reg_long);
6010 %}
6011
6012 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6013 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6014 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6015 match(Set dst (DecodeN src));
6016 effect(KILL cr);
6017 format %{ "decode_heap_oop $dst,$src" %}
6018 ins_encode %{
6019 Register s = $src$$Register;
6020 Register d = $dst$$Register;
6021 if (s != d) {
6022 __ movq(d, s);
6023 }
6024 __ decode_heap_oop(d);
6025 %}
6026 ins_pipe(ialu_reg_long);
6027 %}
6028
6029 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6030 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6031 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6032 match(Set dst (DecodeN src));
6033 effect(KILL cr);
6034 format %{ "decode_heap_oop_not_null $dst,$src" %}
6035 ins_encode %{
6036 Register s = $src$$Register;
6037 Register d = $dst$$Register;
6038 if (s != d) {
6039 __ decode_heap_oop_not_null(d, s);
6040 } else {
6041 __ decode_heap_oop_not_null(d);
6042 }
6043 %}
6044 ins_pipe(ialu_reg_long);
6045 %}
6046
6047 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6048 match(Set dst (EncodePKlass src));
6049 effect(TEMP dst, KILL cr);
6050 format %{ "encode_and_move_klass_not_null $dst,$src" %}
6051 ins_encode %{
6052 __ encode_and_move_klass_not_null($dst$$Register, $src$$Register);
6053 %}
6054 ins_pipe(ialu_reg_long);
6055 %}
6056
6057 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6058 match(Set dst (DecodeNKlass src));
6059 effect(TEMP dst, KILL cr);
6060 format %{ "decode_and_move_klass_not_null $dst,$src" %}
6061 ins_encode %{
6062 __ decode_and_move_klass_not_null($dst$$Register, $src$$Register);
6063 %}
6064 ins_pipe(ialu_reg_long);
6065 %}
6066
6067 //----------Conditional Move---------------------------------------------------
6068 // Jump
6069 // dummy instruction for generating temp registers
6070 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6071 match(Jump (LShiftL switch_val shift));
6072 ins_cost(350);
6073 predicate(false);
6074 effect(TEMP dest);
6075
6076 format %{ "leaq $dest, [$constantaddress]\n\t"
6077 "jmp [$dest + $switch_val << $shift]\n\t" %}
6078 ins_encode %{
6079 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6080 // to do that and the compiler is using that register as one it can allocate.
6081 // So we build it all by hand.
6082 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6083 // ArrayAddress dispatch(table, index);
6084 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6085 __ lea($dest$$Register, $constantaddress);
6086 __ jmp(dispatch);
6087 %}
6088 ins_pipe(pipe_jmp);
6089 %}
6090
6091 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6092 match(Jump (AddL (LShiftL switch_val shift) offset));
6093 ins_cost(350);
6094 effect(TEMP dest);
6095
6096 format %{ "leaq $dest, [$constantaddress]\n\t"
6097 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6098 ins_encode %{
6099 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6100 // to do that and the compiler is using that register as one it can allocate.
6101 // So we build it all by hand.
6102 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6103 // ArrayAddress dispatch(table, index);
6104 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6105 __ lea($dest$$Register, $constantaddress);
6106 __ jmp(dispatch);
6107 %}
6108 ins_pipe(pipe_jmp);
6109 %}
6110
6111 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6112 match(Jump switch_val);
6113 ins_cost(350);
6114 effect(TEMP dest);
6115
6116 format %{ "leaq $dest, [$constantaddress]\n\t"
6117 "jmp [$dest + $switch_val]\n\t" %}
6118 ins_encode %{
6119 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6120 // to do that and the compiler is using that register as one it can allocate.
6121 // So we build it all by hand.
6122 // Address index(noreg, switch_reg, Address::times_1);
6123 // ArrayAddress dispatch(table, index);
6124 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6125 __ lea($dest$$Register, $constantaddress);
6126 __ jmp(dispatch);
6127 %}
6128 ins_pipe(pipe_jmp);
6129 %}
6130
6131 // Conditional move
6132 instruct cmovI_imm_01(rRegI dst, immI_1 src, rFlagsReg cr, cmpOp cop)
6133 %{
6134 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
6135 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6136
6137 ins_cost(100); // XXX
6138 format %{ "setbn$cop $dst\t# signed, int" %}
6139 ins_encode %{
6140 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6141 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6142 %}
6143 ins_pipe(ialu_reg);
6144 %}
6145
6146 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6147 %{
6148 predicate(!UseAPX);
6149 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6150
6151 ins_cost(200); // XXX
6152 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6153 ins_encode %{
6154 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6155 %}
6156 ins_pipe(pipe_cmov_reg);
6157 %}
6158
6159 instruct cmovI_reg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr, cmpOp cop)
6160 %{
6161 predicate(UseAPX);
6162 match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
6163
6164 ins_cost(200);
6165 format %{ "ecmovl$cop $dst, $src1, $src2\t# signed, int ndd" %}
6166 ins_encode %{
6167 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6168 %}
6169 ins_pipe(pipe_cmov_reg);
6170 %}
6171
6172 instruct cmovI_imm_01U(rRegI dst, immI_1 src, rFlagsRegU cr, cmpOpU cop)
6173 %{
6174 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
6175 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6176
6177 ins_cost(100); // XXX
6178 format %{ "setbn$cop $dst\t# unsigned, int" %}
6179 ins_encode %{
6180 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6181 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6182 %}
6183 ins_pipe(ialu_reg);
6184 %}
6185
6186 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6187 predicate(!UseAPX);
6188 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6189
6190 ins_cost(200); // XXX
6191 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6192 ins_encode %{
6193 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6194 %}
6195 ins_pipe(pipe_cmov_reg);
6196 %}
6197
6198 instruct cmovI_regU_ndd(rRegI dst, cmpOpU cop, rFlagsRegU cr, rRegI src1, rRegI src2) %{
6199 predicate(UseAPX);
6200 match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
6201
6202 ins_cost(200);
6203 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %}
6204 ins_encode %{
6205 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6206 %}
6207 ins_pipe(pipe_cmov_reg);
6208 %}
6209
6210 instruct cmovI_imm_01UCF(rRegI dst, immI_1 src, rFlagsRegUCF cr, cmpOpUCF cop)
6211 %{
6212 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
6213 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6214
6215 ins_cost(100); // XXX
6216 format %{ "setbn$cop $dst\t# unsigned, int" %}
6217 ins_encode %{
6218 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6219 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6220 %}
6221 ins_pipe(ialu_reg);
6222 %}
6223
6224 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6225 predicate(!UseAPX);
6226 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6227 ins_cost(200);
6228 expand %{
6229 cmovI_regU(cop, cr, dst, src);
6230 %}
6231 %}
6232
6233 instruct cmovI_regUCF_ndd(rRegI dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegI src1, rRegI src2) %{
6234 predicate(UseAPX);
6235 match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
6236 ins_cost(200);
6237 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %}
6238 ins_encode %{
6239 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6240 %}
6241 ins_pipe(pipe_cmov_reg);
6242 %}
6243
6244 instruct cmovI_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6245 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6246 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6247
6248 ins_cost(200); // XXX
6249 format %{ "cmovpl $dst, $src\n\t"
6250 "cmovnel $dst, $src" %}
6251 ins_encode %{
6252 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6253 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6254 %}
6255 ins_pipe(pipe_cmov_reg);
6256 %}
6257
6258 instruct cmovI_regUCF2_ne_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src1, rRegI src2) %{
6259 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6260 match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
6261
6262 ins_cost(200);
6263 format %{ "ecmovpl $dst, $src1, $src2\n\t"
6264 "ecmovnel $dst, $src1, $src2" %}
6265 ins_encode %{
6266 __ ecmovl(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6267 __ ecmovl(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6268 %}
6269 ins_pipe(pipe_cmov_reg);
6270 %}
6271
6272 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6273 // inputs of the CMove
6274 instruct cmovI_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6275 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6276 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6277
6278 ins_cost(200); // XXX
6279 format %{ "cmovpl $dst, $src\n\t"
6280 "cmovnel $dst, $src" %}
6281 ins_encode %{
6282 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6283 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6284 %}
6285 ins_pipe(pipe_cmov_reg);
6286 %}
6287
6288 // We need this special handling for only eq / neq comparison since NaN == NaN is false,
6289 // and parity flag bit is set if any of the operand is a NaN.
6290 instruct cmovI_regUCF2_eq_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src1, rRegI src2) %{
6291 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6292 match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
6293
6294 ins_cost(200);
6295 format %{ "ecmovpl $dst, $src1, $src2\n\t"
6296 "ecmovnel $dst, $src1, $src2" %}
6297 ins_encode %{
6298 __ ecmovl(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6299 __ ecmovl(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6300 %}
6301 ins_pipe(pipe_cmov_reg);
6302 %}
6303
6304 // Conditional move
6305 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6306 predicate(!UseAPX);
6307 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6308
6309 ins_cost(250); // XXX
6310 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6311 ins_encode %{
6312 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6313 %}
6314 ins_pipe(pipe_cmov_mem);
6315 %}
6316
6317 // Conditional move
6318 instruct cmovI_rReg_rReg_mem_ndd(rRegI dst, cmpOp cop, rFlagsReg cr, rRegI src1, memory src2)
6319 %{
6320 predicate(UseAPX);
6321 match(Set dst (CMoveI (Binary cop cr) (Binary src1 (LoadI src2))));
6322
6323 ins_cost(250);
6324 format %{ "ecmovl$cop $dst, $src1, $src2\t# signed, int ndd" %}
6325 ins_encode %{
6326 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6327 %}
6328 ins_pipe(pipe_cmov_mem);
6329 %}
6330
6331 // Conditional move
6332 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6333 %{
6334 predicate(!UseAPX);
6335 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6336
6337 ins_cost(250); // XXX
6338 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6339 ins_encode %{
6340 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6341 %}
6342 ins_pipe(pipe_cmov_mem);
6343 %}
6344
6345 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6346 predicate(!UseAPX);
6347 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6348 ins_cost(250);
6349 expand %{
6350 cmovI_memU(cop, cr, dst, src);
6351 %}
6352 %}
6353
6354 instruct cmovI_rReg_rReg_memU_ndd(rRegI dst, cmpOpU cop, rFlagsRegU cr, rRegI src1, memory src2)
6355 %{
6356 predicate(UseAPX);
6357 match(Set dst (CMoveI (Binary cop cr) (Binary src1 (LoadI src2))));
6358
6359 ins_cost(250);
6360 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %}
6361 ins_encode %{
6362 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6363 %}
6364 ins_pipe(pipe_cmov_mem);
6365 %}
6366
6367 instruct cmovI_rReg_rReg_memUCF_ndd(rRegI dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegI src1, memory src2)
6368 %{
6369 predicate(UseAPX);
6370 match(Set dst (CMoveI (Binary cop cr) (Binary src1 (LoadI src2))));
6371 ins_cost(250);
6372 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %}
6373 ins_encode %{
6374 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6375 %}
6376 ins_pipe(pipe_cmov_mem);
6377 %}
6378
6379 // Conditional move
6380 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6381 %{
6382 predicate(!UseAPX);
6383 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6384
6385 ins_cost(200); // XXX
6386 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6387 ins_encode %{
6388 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6389 %}
6390 ins_pipe(pipe_cmov_reg);
6391 %}
6392
6393 // Conditional move ndd
6394 instruct cmovN_reg_ndd(rRegN dst, rRegN src1, rRegN src2, rFlagsReg cr, cmpOp cop)
6395 %{
6396 predicate(UseAPX);
6397 match(Set dst (CMoveN (Binary cop cr) (Binary src1 src2)));
6398
6399 ins_cost(200);
6400 format %{ "ecmovl$cop $dst, $src1, $src2\t# signed, compressed ptr ndd" %}
6401 ins_encode %{
6402 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6403 %}
6404 ins_pipe(pipe_cmov_reg);
6405 %}
6406
6407 // Conditional move
6408 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6409 %{
6410 predicate(!UseAPX);
6411 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6412
6413 ins_cost(200); // XXX
6414 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6415 ins_encode %{
6416 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6417 %}
6418 ins_pipe(pipe_cmov_reg);
6419 %}
6420
6421 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6422 predicate(!UseAPX);
6423 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6424 ins_cost(200);
6425 expand %{
6426 cmovN_regU(cop, cr, dst, src);
6427 %}
6428 %}
6429
6430 // Conditional move ndd
6431 instruct cmovN_regU_ndd(rRegN dst, cmpOpU cop, rFlagsRegU cr, rRegN src1, rRegN src2)
6432 %{
6433 predicate(UseAPX);
6434 match(Set dst (CMoveN (Binary cop cr) (Binary src1 src2)));
6435
6436 ins_cost(200);
6437 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, compressed ptr ndd" %}
6438 ins_encode %{
6439 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6440 %}
6441 ins_pipe(pipe_cmov_reg);
6442 %}
6443
6444 instruct cmovN_regUCF_ndd(rRegN dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegN src1, rRegN src2) %{
6445 predicate(UseAPX);
6446 match(Set dst (CMoveN (Binary cop cr) (Binary src1 src2)));
6447 ins_cost(200);
6448 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, compressed ptr ndd" %}
6449 ins_encode %{
6450 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6451 %}
6452 ins_pipe(pipe_cmov_reg);
6453 %}
6454
6455 instruct cmovN_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6456 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6457 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6458
6459 ins_cost(200); // XXX
6460 format %{ "cmovpl $dst, $src\n\t"
6461 "cmovnel $dst, $src" %}
6462 ins_encode %{
6463 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6464 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6465 %}
6466 ins_pipe(pipe_cmov_reg);
6467 %}
6468
6469 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6470 // inputs of the CMove
6471 instruct cmovN_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6472 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6473 match(Set dst (CMoveN (Binary cop cr) (Binary src dst)));
6474
6475 ins_cost(200); // XXX
6476 format %{ "cmovpl $dst, $src\n\t"
6477 "cmovnel $dst, $src" %}
6478 ins_encode %{
6479 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6480 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6481 %}
6482 ins_pipe(pipe_cmov_reg);
6483 %}
6484
6485 // Conditional move
6486 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6487 %{
6488 predicate(!UseAPX);
6489 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6490
6491 ins_cost(200); // XXX
6492 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6493 ins_encode %{
6494 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6495 %}
6496 ins_pipe(pipe_cmov_reg); // XXX
6497 %}
6498
6499 // Conditional move ndd
6500 instruct cmovP_reg_ndd(rRegP dst, rRegP src1, rRegP src2, rFlagsReg cr, cmpOp cop)
6501 %{
6502 predicate(UseAPX);
6503 match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
6504
6505 ins_cost(200);
6506 format %{ "ecmovq$cop $dst, $src1, $src2\t# signed, ptr ndd" %}
6507 ins_encode %{
6508 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6509 %}
6510 ins_pipe(pipe_cmov_reg);
6511 %}
6512
6513 // Conditional move
6514 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6515 %{
6516 predicate(!UseAPX);
6517 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6518
6519 ins_cost(200); // XXX
6520 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6521 ins_encode %{
6522 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6523 %}
6524 ins_pipe(pipe_cmov_reg); // XXX
6525 %}
6526
6527 // Conditional move ndd
6528 instruct cmovP_regU_ndd(rRegP dst, cmpOpU cop, rFlagsRegU cr, rRegP src1, rRegP src2)
6529 %{
6530 predicate(UseAPX);
6531 match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
6532
6533 ins_cost(200);
6534 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, ptr ndd" %}
6535 ins_encode %{
6536 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6537 %}
6538 ins_pipe(pipe_cmov_reg);
6539 %}
6540
6541 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6542 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6543 ins_cost(200);
6544 expand %{
6545 cmovP_regU(cop, cr, dst, src);
6546 %}
6547 %}
6548
6549 instruct cmovP_regUCF_ndd(rRegP dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegP src1, rRegP src2) %{
6550 match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
6551 ins_cost(200);
6552 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, ptr ndd" %}
6553 ins_encode %{
6554 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6555 %}
6556 ins_pipe(pipe_cmov_reg);
6557 %}
6558
6559 instruct cmovP_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6560 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6561 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6562
6563 ins_cost(200); // XXX
6564 format %{ "cmovpq $dst, $src\n\t"
6565 "cmovneq $dst, $src" %}
6566 ins_encode %{
6567 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6568 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6569 %}
6570 ins_pipe(pipe_cmov_reg);
6571 %}
6572
6573 instruct cmovP_regUCF2_ne_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src1, rRegP src2) %{
6574 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6575 match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
6576
6577 ins_cost(200);
6578 format %{ "ecmovpq $dst, $src1, $src2\n\t"
6579 "ecmovneq $dst, $src1, $src2" %}
6580 ins_encode %{
6581 __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6582 __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6583 %}
6584 ins_pipe(pipe_cmov_reg);
6585 %}
6586
6587 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6588 // inputs of the CMove
6589 instruct cmovP_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6590 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6591 match(Set dst (CMoveP (Binary cop cr) (Binary src dst)));
6592
6593 ins_cost(200); // XXX
6594 format %{ "cmovpq $dst, $src\n\t"
6595 "cmovneq $dst, $src" %}
6596 ins_encode %{
6597 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6598 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6599 %}
6600 ins_pipe(pipe_cmov_reg);
6601 %}
6602
6603 instruct cmovP_regUCF2_eq_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src1, rRegP src2) %{
6604 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6605 match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
6606
6607 ins_cost(200);
6608 format %{ "ecmovpq $dst, $src1, $src2\n\t"
6609 "ecmovneq $dst, $src1, $src2" %}
6610 ins_encode %{
6611 __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6612 __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6613 %}
6614 ins_pipe(pipe_cmov_reg);
6615 %}
6616
6617 instruct cmovL_imm_01(rRegL dst, immL1 src, rFlagsReg cr, cmpOp cop)
6618 %{
6619 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
6620 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6621
6622 ins_cost(100); // XXX
6623 format %{ "setbn$cop $dst\t# signed, long" %}
6624 ins_encode %{
6625 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6626 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6627 %}
6628 ins_pipe(ialu_reg);
6629 %}
6630
6631 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6632 %{
6633 predicate(!UseAPX);
6634 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6635
6636 ins_cost(200); // XXX
6637 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6638 ins_encode %{
6639 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6640 %}
6641 ins_pipe(pipe_cmov_reg); // XXX
6642 %}
6643
6644 instruct cmovL_reg_ndd(rRegL dst, cmpOp cop, rFlagsReg cr, rRegL src1, rRegL src2)
6645 %{
6646 predicate(UseAPX);
6647 match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
6648
6649 ins_cost(200);
6650 format %{ "ecmovq$cop $dst, $src1, $src2\t# signed, long ndd" %}
6651 ins_encode %{
6652 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6653 %}
6654 ins_pipe(pipe_cmov_reg);
6655 %}
6656
6657 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6658 %{
6659 predicate(!UseAPX);
6660 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6661
6662 ins_cost(200); // XXX
6663 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6664 ins_encode %{
6665 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6666 %}
6667 ins_pipe(pipe_cmov_mem); // XXX
6668 %}
6669
6670 instruct cmovL_rReg_rReg_mem_ndd(rRegL dst, cmpOp cop, rFlagsReg cr, rRegL src1, memory src2)
6671 %{
6672 predicate(UseAPX);
6673 match(Set dst (CMoveL (Binary cop cr) (Binary src1 (LoadL src2))));
6674
6675 ins_cost(200);
6676 format %{ "ecmovq$cop $dst, $src1, $src2\t# signed, long ndd" %}
6677 ins_encode %{
6678 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6679 %}
6680 ins_pipe(pipe_cmov_mem);
6681 %}
6682
6683 instruct cmovL_imm_01U(rRegL dst, immL1 src, rFlagsRegU cr, cmpOpU cop)
6684 %{
6685 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
6686 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6687
6688 ins_cost(100); // XXX
6689 format %{ "setbn$cop $dst\t# unsigned, long" %}
6690 ins_encode %{
6691 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6692 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6693 %}
6694 ins_pipe(ialu_reg);
6695 %}
6696
6697 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6698 %{
6699 predicate(!UseAPX);
6700 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6701
6702 ins_cost(200); // XXX
6703 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6704 ins_encode %{
6705 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6706 %}
6707 ins_pipe(pipe_cmov_reg); // XXX
6708 %}
6709
6710 instruct cmovL_regU_ndd(rRegL dst, cmpOpU cop, rFlagsRegU cr, rRegL src1, rRegL src2)
6711 %{
6712 predicate(UseAPX);
6713 match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
6714
6715 ins_cost(200);
6716 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %}
6717 ins_encode %{
6718 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6719 %}
6720 ins_pipe(pipe_cmov_reg);
6721 %}
6722
6723 instruct cmovL_imm_01UCF(rRegL dst, immL1 src, rFlagsRegUCF cr, cmpOpUCF cop)
6724 %{
6725 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
6726 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6727
6728 ins_cost(100); // XXX
6729 format %{ "setbn$cop $dst\t# unsigned, long" %}
6730 ins_encode %{
6731 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6732 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6733 %}
6734 ins_pipe(ialu_reg);
6735 %}
6736
6737 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6738 predicate(!UseAPX);
6739 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6740 ins_cost(200);
6741 expand %{
6742 cmovL_regU(cop, cr, dst, src);
6743 %}
6744 %}
6745
6746 instruct cmovL_regUCF_ndd(rRegL dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegL src1, rRegL src2)
6747 %{
6748 predicate(UseAPX);
6749 match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
6750 ins_cost(200);
6751 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %}
6752 ins_encode %{
6753 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6754 %}
6755 ins_pipe(pipe_cmov_reg);
6756 %}
6757
6758 instruct cmovL_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6759 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6760 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6761
6762 ins_cost(200); // XXX
6763 format %{ "cmovpq $dst, $src\n\t"
6764 "cmovneq $dst, $src" %}
6765 ins_encode %{
6766 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6767 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6768 %}
6769 ins_pipe(pipe_cmov_reg);
6770 %}
6771
6772 instruct cmovL_regUCF2_ne_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src1, rRegL src2) %{
6773 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6774 match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
6775
6776 ins_cost(200);
6777 format %{ "ecmovpq $dst, $src1, $src2\n\t"
6778 "ecmovneq $dst, $src1, $src2" %}
6779 ins_encode %{
6780 __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6781 __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6782 %}
6783 ins_pipe(pipe_cmov_reg);
6784 %}
6785
6786 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6787 // inputs of the CMove
6788 instruct cmovL_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6789 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6790 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6791
6792 ins_cost(200); // XXX
6793 format %{ "cmovpq $dst, $src\n\t"
6794 "cmovneq $dst, $src" %}
6795 ins_encode %{
6796 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6797 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6798 %}
6799 ins_pipe(pipe_cmov_reg);
6800 %}
6801
6802 instruct cmovL_regUCF2_eq_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src1, rRegL src2) %{
6803 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6804 match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
6805
6806 ins_cost(200);
6807 format %{ "ecmovpq $dst, $src1, $src2\n\t"
6808 "ecmovneq $dst, $src1, $src2" %}
6809 ins_encode %{
6810 __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6811 __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6812 %}
6813 ins_pipe(pipe_cmov_reg);
6814 %}
6815
6816 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6817 %{
6818 predicate(!UseAPX);
6819 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6820
6821 ins_cost(200); // XXX
6822 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6823 ins_encode %{
6824 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6825 %}
6826 ins_pipe(pipe_cmov_mem); // XXX
6827 %}
6828
6829 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6830 predicate(!UseAPX);
6831 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6832 ins_cost(200);
6833 expand %{
6834 cmovL_memU(cop, cr, dst, src);
6835 %}
6836 %}
6837
6838 instruct cmovL_rReg_rReg_memU_ndd(rRegL dst, cmpOpU cop, rFlagsRegU cr, rRegL src1, memory src2)
6839 %{
6840 predicate(UseAPX);
6841 match(Set dst (CMoveL (Binary cop cr) (Binary src1 (LoadL src2))));
6842
6843 ins_cost(200);
6844 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %}
6845 ins_encode %{
6846 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6847 %}
6848 ins_pipe(pipe_cmov_mem);
6849 %}
6850
6851 instruct cmovL_rReg_rReg_memUCF_ndd(rRegL dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegL src1, memory src2)
6852 %{
6853 predicate(UseAPX);
6854 match(Set dst (CMoveL (Binary cop cr) (Binary src1 (LoadL src2))));
6855 ins_cost(200);
6856 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %}
6857 ins_encode %{
6858 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6859 %}
6860 ins_pipe(pipe_cmov_mem);
6861 %}
6862
6863 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6864 %{
6865 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6866
6867 ins_cost(200); // XXX
6868 format %{ "jn$cop skip\t# signed cmove float\n\t"
6869 "movss $dst, $src\n"
6870 "skip:" %}
6871 ins_encode %{
6872 Label Lskip;
6873 // Invert sense of branch from sense of CMOV
6874 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6875 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6876 __ bind(Lskip);
6877 %}
6878 ins_pipe(pipe_slow);
6879 %}
6880
6881 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6882 %{
6883 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6884
6885 ins_cost(200); // XXX
6886 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6887 "movss $dst, $src\n"
6888 "skip:" %}
6889 ins_encode %{
6890 Label Lskip;
6891 // Invert sense of branch from sense of CMOV
6892 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6893 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6894 __ bind(Lskip);
6895 %}
6896 ins_pipe(pipe_slow);
6897 %}
6898
6899 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6900 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6901 ins_cost(200);
6902 expand %{
6903 cmovF_regU(cop, cr, dst, src);
6904 %}
6905 %}
6906
6907 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6908 %{
6909 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6910
6911 ins_cost(200); // XXX
6912 format %{ "jn$cop skip\t# signed cmove double\n\t"
6913 "movsd $dst, $src\n"
6914 "skip:" %}
6915 ins_encode %{
6916 Label Lskip;
6917 // Invert sense of branch from sense of CMOV
6918 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6919 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6920 __ bind(Lskip);
6921 %}
6922 ins_pipe(pipe_slow);
6923 %}
6924
6925 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6926 %{
6927 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6928
6929 ins_cost(200); // XXX
6930 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6931 "movsd $dst, $src\n"
6932 "skip:" %}
6933 ins_encode %{
6934 Label Lskip;
6935 // Invert sense of branch from sense of CMOV
6936 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6937 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6938 __ bind(Lskip);
6939 %}
6940 ins_pipe(pipe_slow);
6941 %}
6942
6943 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6944 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6945 ins_cost(200);
6946 expand %{
6947 cmovD_regU(cop, cr, dst, src);
6948 %}
6949 %}
6950
6951 //----------Arithmetic Instructions--------------------------------------------
6952 //----------Addition Instructions----------------------------------------------
6953
6954 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6955 %{
6956 predicate(!UseAPX);
6957 match(Set dst (AddI dst src));
6958 effect(KILL cr);
6959 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6960 format %{ "addl $dst, $src\t# int" %}
6961 ins_encode %{
6962 __ addl($dst$$Register, $src$$Register);
6963 %}
6964 ins_pipe(ialu_reg_reg);
6965 %}
6966
6967 instruct addI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
6968 %{
6969 predicate(UseAPX);
6970 match(Set dst (AddI src1 src2));
6971 effect(KILL cr);
6972 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6973
6974 format %{ "eaddl $dst, $src1, $src2\t# int ndd" %}
6975 ins_encode %{
6976 __ eaddl($dst$$Register, $src1$$Register, $src2$$Register, false);
6977 %}
6978 ins_pipe(ialu_reg_reg);
6979 %}
6980
6981 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6982 %{
6983 predicate(!UseAPX);
6984 match(Set dst (AddI dst src));
6985 effect(KILL cr);
6986 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6987
6988 format %{ "addl $dst, $src\t# int" %}
6989 ins_encode %{
6990 __ addl($dst$$Register, $src$$constant);
6991 %}
6992 ins_pipe( ialu_reg );
6993 %}
6994
6995 instruct addI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
6996 %{
6997 predicate(UseAPX);
6998 match(Set dst (AddI src1 src2));
6999 effect(KILL cr);
7000 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7001
7002 format %{ "eaddl $dst, $src1, $src2\t# int ndd" %}
7003 ins_encode %{
7004 __ eaddl($dst$$Register, $src1$$Register, $src2$$constant, false);
7005 %}
7006 ins_pipe( ialu_reg );
7007 %}
7008
7009 instruct addI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
7010 %{
7011 predicate(UseAPX);
7012 match(Set dst (AddI (LoadI src1) src2));
7013 effect(KILL cr);
7014 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7015
7016 format %{ "eaddl $dst, $src1, $src2\t# int ndd" %}
7017 ins_encode %{
7018 __ eaddl($dst$$Register, $src1$$Address, $src2$$constant, false);
7019 %}
7020 ins_pipe( ialu_reg );
7021 %}
7022
7023 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7024 %{
7025 predicate(!UseAPX);
7026 match(Set dst (AddI dst (LoadI src)));
7027 effect(KILL cr);
7028 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7029
7030 ins_cost(150); // XXX
7031 format %{ "addl $dst, $src\t# int" %}
7032 ins_encode %{
7033 __ addl($dst$$Register, $src$$Address);
7034 %}
7035 ins_pipe(ialu_reg_mem);
7036 %}
7037
7038 instruct addI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr)
7039 %{
7040 predicate(UseAPX);
7041 match(Set dst (AddI (LoadI src1) src2));
7042 effect(KILL cr);
7043 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7044
7045 ins_cost(150);
7046 format %{ "eaddl $dst, $src1, $src2\t# int ndd" %}
7047 ins_encode %{
7048 __ eaddl($dst$$Register, $src1$$Address, $src2$$Register, false);
7049 %}
7050 ins_pipe(ialu_reg_mem);
7051 %}
7052
7053 instruct addI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
7054 %{
7055 predicate(UseAPX);
7056 match(Set dst (AddI src1 (LoadI src2)));
7057 effect(KILL cr);
7058 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7059
7060 ins_cost(150);
7061 format %{ "eaddl $dst, $src1, $src2\t# int ndd" %}
7062 ins_encode %{
7063 __ eaddl($dst$$Register, $src1$$Register, $src2$$Address, false);
7064 %}
7065 ins_pipe(ialu_reg_mem);
7066 %}
7067
7068 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7069 %{
7070 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7071 effect(KILL cr);
7072 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7073
7074 ins_cost(150); // XXX
7075 format %{ "addl $dst, $src\t# int" %}
7076 ins_encode %{
7077 __ addl($dst$$Address, $src$$Register);
7078 %}
7079 ins_pipe(ialu_mem_reg);
7080 %}
7081
7082 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7083 %{
7084 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7085 effect(KILL cr);
7086 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7087
7088
7089 ins_cost(125); // XXX
7090 format %{ "addl $dst, $src\t# int" %}
7091 ins_encode %{
7092 __ addl($dst$$Address, $src$$constant);
7093 %}
7094 ins_pipe(ialu_mem_imm);
7095 %}
7096
7097 instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
7098 %{
7099 predicate(!UseAPX && UseIncDec);
7100 match(Set dst (AddI dst src));
7101 effect(KILL cr);
7102
7103 format %{ "incl $dst\t# int" %}
7104 ins_encode %{
7105 __ incrementl($dst$$Register);
7106 %}
7107 ins_pipe(ialu_reg);
7108 %}
7109
7110 instruct incI_rReg_ndd(rRegI dst, rRegI src, immI_1 val, rFlagsReg cr)
7111 %{
7112 predicate(UseAPX && UseIncDec);
7113 match(Set dst (AddI src val));
7114 effect(KILL cr);
7115
7116 format %{ "eincl $dst, $src\t# int ndd" %}
7117 ins_encode %{
7118 __ eincl($dst$$Register, $src$$Register, false);
7119 %}
7120 ins_pipe(ialu_reg);
7121 %}
7122
7123 instruct incI_rReg_mem_ndd(rRegI dst, memory src, immI_1 val, rFlagsReg cr)
7124 %{
7125 predicate(UseAPX && UseIncDec);
7126 match(Set dst (AddI (LoadI src) val));
7127 effect(KILL cr);
7128
7129 format %{ "eincl $dst, $src\t# int ndd" %}
7130 ins_encode %{
7131 __ eincl($dst$$Register, $src$$Address, false);
7132 %}
7133 ins_pipe(ialu_reg);
7134 %}
7135
7136 instruct incI_mem(memory dst, immI_1 src, rFlagsReg cr)
7137 %{
7138 predicate(UseIncDec);
7139 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7140 effect(KILL cr);
7141
7142 ins_cost(125); // XXX
7143 format %{ "incl $dst\t# int" %}
7144 ins_encode %{
7145 __ incrementl($dst$$Address);
7146 %}
7147 ins_pipe(ialu_mem_imm);
7148 %}
7149
7150 // XXX why does that use AddI
7151 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7152 %{
7153 predicate(!UseAPX && UseIncDec);
7154 match(Set dst (AddI dst src));
7155 effect(KILL cr);
7156
7157 format %{ "decl $dst\t# int" %}
7158 ins_encode %{
7159 __ decrementl($dst$$Register);
7160 %}
7161 ins_pipe(ialu_reg);
7162 %}
7163
7164 instruct decI_rReg_ndd(rRegI dst, rRegI src, immI_M1 val, rFlagsReg cr)
7165 %{
7166 predicate(UseAPX && UseIncDec);
7167 match(Set dst (AddI src val));
7168 effect(KILL cr);
7169
7170 format %{ "edecl $dst, $src\t# int ndd" %}
7171 ins_encode %{
7172 __ edecl($dst$$Register, $src$$Register, false);
7173 %}
7174 ins_pipe(ialu_reg);
7175 %}
7176
7177 instruct decI_rReg_mem_ndd(rRegI dst, memory src, immI_M1 val, rFlagsReg cr)
7178 %{
7179 predicate(UseAPX && UseIncDec);
7180 match(Set dst (AddI (LoadI src) val));
7181 effect(KILL cr);
7182
7183 format %{ "edecl $dst, $src\t# int ndd" %}
7184 ins_encode %{
7185 __ edecl($dst$$Register, $src$$Address, false);
7186 %}
7187 ins_pipe(ialu_reg);
7188 %}
7189
7190 // XXX why does that use AddI
7191 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7192 %{
7193 predicate(UseIncDec);
7194 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7195 effect(KILL cr);
7196
7197 ins_cost(125); // XXX
7198 format %{ "decl $dst\t# int" %}
7199 ins_encode %{
7200 __ decrementl($dst$$Address);
7201 %}
7202 ins_pipe(ialu_mem_imm);
7203 %}
7204
7205 instruct leaI_rReg_immI2_immI(rRegI dst, rRegI index, immI2 scale, immI disp)
7206 %{
7207 predicate(VM_Version::supports_fast_2op_lea());
7208 match(Set dst (AddI (LShiftI index scale) disp));
7209
7210 format %{ "leal $dst, [$index << $scale + $disp]\t# int" %}
7211 ins_encode %{
7212 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7213 __ leal($dst$$Register, Address(noreg, $index$$Register, scale, $disp$$constant));
7214 %}
7215 ins_pipe(ialu_reg_reg);
7216 %}
7217
7218 instruct leaI_rReg_rReg_immI(rRegI dst, rRegI base, rRegI index, immI disp)
7219 %{
7220 predicate(VM_Version::supports_fast_3op_lea());
7221 match(Set dst (AddI (AddI base index) disp));
7222
7223 format %{ "leal $dst, [$base + $index + $disp]\t# int" %}
7224 ins_encode %{
7225 __ leal($dst$$Register, Address($base$$Register, $index$$Register, Address::times_1, $disp$$constant));
7226 %}
7227 ins_pipe(ialu_reg_reg);
7228 %}
7229
7230 instruct leaI_rReg_rReg_immI2(rRegI dst, no_rbp_r13_RegI base, rRegI index, immI2 scale)
7231 %{
7232 predicate(VM_Version::supports_fast_2op_lea());
7233 match(Set dst (AddI base (LShiftI index scale)));
7234
7235 format %{ "leal $dst, [$base + $index << $scale]\t# int" %}
7236 ins_encode %{
7237 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7238 __ leal($dst$$Register, Address($base$$Register, $index$$Register, scale));
7239 %}
7240 ins_pipe(ialu_reg_reg);
7241 %}
7242
7243 instruct leaI_rReg_rReg_immI2_immI(rRegI dst, rRegI base, rRegI index, immI2 scale, immI disp)
7244 %{
7245 predicate(VM_Version::supports_fast_3op_lea());
7246 match(Set dst (AddI (AddI base (LShiftI index scale)) disp));
7247
7248 format %{ "leal $dst, [$base + $index << $scale + $disp]\t# int" %}
7249 ins_encode %{
7250 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7251 __ leal($dst$$Register, Address($base$$Register, $index$$Register, scale, $disp$$constant));
7252 %}
7253 ins_pipe(ialu_reg_reg);
7254 %}
7255
7256 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7257 %{
7258 predicate(!UseAPX);
7259 match(Set dst (AddL dst src));
7260 effect(KILL cr);
7261 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7262
7263 format %{ "addq $dst, $src\t# long" %}
7264 ins_encode %{
7265 __ addq($dst$$Register, $src$$Register);
7266 %}
7267 ins_pipe(ialu_reg_reg);
7268 %}
7269
7270 instruct addL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
7271 %{
7272 predicate(UseAPX);
7273 match(Set dst (AddL src1 src2));
7274 effect(KILL cr);
7275 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7276
7277 format %{ "eaddq $dst, $src1, $src2\t# long ndd" %}
7278 ins_encode %{
7279 __ eaddq($dst$$Register, $src1$$Register, $src2$$Register, false);
7280 %}
7281 ins_pipe(ialu_reg_reg);
7282 %}
7283
7284 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7285 %{
7286 predicate(!UseAPX);
7287 match(Set dst (AddL dst src));
7288 effect(KILL cr);
7289 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7290
7291 format %{ "addq $dst, $src\t# long" %}
7292 ins_encode %{
7293 __ addq($dst$$Register, $src$$constant);
7294 %}
7295 ins_pipe( ialu_reg );
7296 %}
7297
7298 instruct addL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
7299 %{
7300 predicate(UseAPX);
7301 match(Set dst (AddL src1 src2));
7302 effect(KILL cr);
7303 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7304
7305 format %{ "eaddq $dst, $src1, $src2\t# long ndd" %}
7306 ins_encode %{
7307 __ eaddq($dst$$Register, $src1$$Register, $src2$$constant, false);
7308 %}
7309 ins_pipe( ialu_reg );
7310 %}
7311
7312 instruct addL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
7313 %{
7314 predicate(UseAPX);
7315 match(Set dst (AddL (LoadL src1) src2));
7316 effect(KILL cr);
7317 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7318
7319 format %{ "eaddq $dst, $src1, $src2\t# long ndd" %}
7320 ins_encode %{
7321 __ eaddq($dst$$Register, $src1$$Address, $src2$$constant, false);
7322 %}
7323 ins_pipe( ialu_reg );
7324 %}
7325
7326 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7327 %{
7328 predicate(!UseAPX);
7329 match(Set dst (AddL dst (LoadL src)));
7330 effect(KILL cr);
7331 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7332
7333 ins_cost(150); // XXX
7334 format %{ "addq $dst, $src\t# long" %}
7335 ins_encode %{
7336 __ addq($dst$$Register, $src$$Address);
7337 %}
7338 ins_pipe(ialu_reg_mem);
7339 %}
7340
7341 instruct addL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
7342 %{
7343 predicate(UseAPX);
7344 match(Set dst (AddL src1 (LoadL src2)));
7345 effect(KILL cr);
7346 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7347
7348 ins_cost(150);
7349 format %{ "eaddq $dst, $src1, $src2\t# long ndd" %}
7350 ins_encode %{
7351 __ eaddq($dst$$Register, $src1$$Register, $src2$$Address, false);
7352 %}
7353 ins_pipe(ialu_reg_mem);
7354 %}
7355
7356 instruct addL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
7357 %{
7358 predicate(UseAPX);
7359 match(Set dst (AddL (LoadL src1) src2));
7360 effect(KILL cr);
7361 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7362
7363 ins_cost(150);
7364 format %{ "eaddq $dst, $src1, $src2\t# long ndd" %}
7365 ins_encode %{
7366 __ eaddq($dst$$Register, $src1$$Address, $src2$$Register, false);
7367 %}
7368 ins_pipe(ialu_reg_mem);
7369 %}
7370
7371 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7372 %{
7373 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7374 effect(KILL cr);
7375 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7376
7377 ins_cost(150); // XXX
7378 format %{ "addq $dst, $src\t# long" %}
7379 ins_encode %{
7380 __ addq($dst$$Address, $src$$Register);
7381 %}
7382 ins_pipe(ialu_mem_reg);
7383 %}
7384
7385 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7386 %{
7387 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7388 effect(KILL cr);
7389 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7390
7391 ins_cost(125); // XXX
7392 format %{ "addq $dst, $src\t# long" %}
7393 ins_encode %{
7394 __ addq($dst$$Address, $src$$constant);
7395 %}
7396 ins_pipe(ialu_mem_imm);
7397 %}
7398
7399 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7400 %{
7401 predicate(!UseAPX && UseIncDec);
7402 match(Set dst (AddL dst src));
7403 effect(KILL cr);
7404
7405 format %{ "incq $dst\t# long" %}
7406 ins_encode %{
7407 __ incrementq($dst$$Register);
7408 %}
7409 ins_pipe(ialu_reg);
7410 %}
7411
7412 instruct incL_rReg_ndd(rRegI dst, rRegI src, immL1 val, rFlagsReg cr)
7413 %{
7414 predicate(UseAPX && UseIncDec);
7415 match(Set dst (AddL src val));
7416 effect(KILL cr);
7417
7418 format %{ "eincq $dst, $src\t# long ndd" %}
7419 ins_encode %{
7420 __ eincq($dst$$Register, $src$$Register, false);
7421 %}
7422 ins_pipe(ialu_reg);
7423 %}
7424
7425 instruct incL_rReg_mem_ndd(rRegI dst, memory src, immL1 val, rFlagsReg cr)
7426 %{
7427 predicate(UseAPX && UseIncDec);
7428 match(Set dst (AddL (LoadL src) val));
7429 effect(KILL cr);
7430
7431 format %{ "eincq $dst, $src\t# long ndd" %}
7432 ins_encode %{
7433 __ eincq($dst$$Register, $src$$Address, false);
7434 %}
7435 ins_pipe(ialu_reg);
7436 %}
7437
7438 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7439 %{
7440 predicate(UseIncDec);
7441 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7442 effect(KILL cr);
7443
7444 ins_cost(125); // XXX
7445 format %{ "incq $dst\t# long" %}
7446 ins_encode %{
7447 __ incrementq($dst$$Address);
7448 %}
7449 ins_pipe(ialu_mem_imm);
7450 %}
7451
7452 // XXX why does that use AddL
7453 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7454 %{
7455 predicate(!UseAPX && UseIncDec);
7456 match(Set dst (AddL dst src));
7457 effect(KILL cr);
7458
7459 format %{ "decq $dst\t# long" %}
7460 ins_encode %{
7461 __ decrementq($dst$$Register);
7462 %}
7463 ins_pipe(ialu_reg);
7464 %}
7465
7466 instruct decL_rReg_ndd(rRegL dst, rRegL src, immL_M1 val, rFlagsReg cr)
7467 %{
7468 predicate(UseAPX && UseIncDec);
7469 match(Set dst (AddL src val));
7470 effect(KILL cr);
7471
7472 format %{ "edecq $dst, $src\t# long ndd" %}
7473 ins_encode %{
7474 __ edecq($dst$$Register, $src$$Register, false);
7475 %}
7476 ins_pipe(ialu_reg);
7477 %}
7478
7479 instruct decL_rReg_mem_ndd(rRegL dst, memory src, immL_M1 val, rFlagsReg cr)
7480 %{
7481 predicate(UseAPX && UseIncDec);
7482 match(Set dst (AddL (LoadL src) val));
7483 effect(KILL cr);
7484
7485 format %{ "edecq $dst, $src\t# long ndd" %}
7486 ins_encode %{
7487 __ edecq($dst$$Register, $src$$Address, false);
7488 %}
7489 ins_pipe(ialu_reg);
7490 %}
7491
7492 // XXX why does that use AddL
7493 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7494 %{
7495 predicate(UseIncDec);
7496 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7497 effect(KILL cr);
7498
7499 ins_cost(125); // XXX
7500 format %{ "decq $dst\t# long" %}
7501 ins_encode %{
7502 __ decrementq($dst$$Address);
7503 %}
7504 ins_pipe(ialu_mem_imm);
7505 %}
7506
7507 instruct leaL_rReg_immI2_immL32(rRegL dst, rRegL index, immI2 scale, immL32 disp)
7508 %{
7509 predicate(VM_Version::supports_fast_2op_lea());
7510 match(Set dst (AddL (LShiftL index scale) disp));
7511
7512 format %{ "leaq $dst, [$index << $scale + $disp]\t# long" %}
7513 ins_encode %{
7514 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7515 __ leaq($dst$$Register, Address(noreg, $index$$Register, scale, $disp$$constant));
7516 %}
7517 ins_pipe(ialu_reg_reg);
7518 %}
7519
7520 instruct leaL_rReg_rReg_immL32(rRegL dst, rRegL base, rRegL index, immL32 disp)
7521 %{
7522 predicate(VM_Version::supports_fast_3op_lea());
7523 match(Set dst (AddL (AddL base index) disp));
7524
7525 format %{ "leaq $dst, [$base + $index + $disp]\t# long" %}
7526 ins_encode %{
7527 __ leaq($dst$$Register, Address($base$$Register, $index$$Register, Address::times_1, $disp$$constant));
7528 %}
7529 ins_pipe(ialu_reg_reg);
7530 %}
7531
7532 instruct leaL_rReg_rReg_immI2(rRegL dst, no_rbp_r13_RegL base, rRegL index, immI2 scale)
7533 %{
7534 predicate(VM_Version::supports_fast_2op_lea());
7535 match(Set dst (AddL base (LShiftL index scale)));
7536
7537 format %{ "leaq $dst, [$base + $index << $scale]\t# long" %}
7538 ins_encode %{
7539 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7540 __ leaq($dst$$Register, Address($base$$Register, $index$$Register, scale));
7541 %}
7542 ins_pipe(ialu_reg_reg);
7543 %}
7544
7545 instruct leaL_rReg_rReg_immI2_immL32(rRegL dst, rRegL base, rRegL index, immI2 scale, immL32 disp)
7546 %{
7547 predicate(VM_Version::supports_fast_3op_lea());
7548 match(Set dst (AddL (AddL base (LShiftL index scale)) disp));
7549
7550 format %{ "leaq $dst, [$base + $index << $scale + $disp]\t# long" %}
7551 ins_encode %{
7552 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7553 __ leaq($dst$$Register, Address($base$$Register, $index$$Register, scale, $disp$$constant));
7554 %}
7555 ins_pipe(ialu_reg_reg);
7556 %}
7557
7558 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7559 %{
7560 match(Set dst (AddP dst src));
7561 effect(KILL cr);
7562 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7563
7564 format %{ "addq $dst, $src\t# ptr" %}
7565 ins_encode %{
7566 __ addq($dst$$Register, $src$$Register);
7567 %}
7568 ins_pipe(ialu_reg_reg);
7569 %}
7570
7571 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7572 %{
7573 match(Set dst (AddP dst src));
7574 effect(KILL cr);
7575 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7576
7577 format %{ "addq $dst, $src\t# ptr" %}
7578 ins_encode %{
7579 __ addq($dst$$Register, $src$$constant);
7580 %}
7581 ins_pipe( ialu_reg );
7582 %}
7583
7584 // XXX addP mem ops ????
7585
7586 instruct checkCastPP(rRegP dst)
7587 %{
7588 match(Set dst (CheckCastPP dst));
7589
7590 size(0);
7591 format %{ "# checkcastPP of $dst" %}
7592 ins_encode(/* empty encoding */);
7593 ins_pipe(empty);
7594 %}
7595
7596 instruct castPP(rRegP dst)
7597 %{
7598 match(Set dst (CastPP dst));
7599
7600 size(0);
7601 format %{ "# castPP of $dst" %}
7602 ins_encode(/* empty encoding */);
7603 ins_pipe(empty);
7604 %}
7605
7606 instruct castII(rRegI dst)
7607 %{
7608 match(Set dst (CastII dst));
7609
7610 size(0);
7611 format %{ "# castII of $dst" %}
7612 ins_encode(/* empty encoding */);
7613 ins_cost(0);
7614 ins_pipe(empty);
7615 %}
7616
7617 instruct castLL(rRegL dst)
7618 %{
7619 match(Set dst (CastLL dst));
7620
7621 size(0);
7622 format %{ "# castLL of $dst" %}
7623 ins_encode(/* empty encoding */);
7624 ins_cost(0);
7625 ins_pipe(empty);
7626 %}
7627
7628 instruct castFF(regF dst)
7629 %{
7630 match(Set dst (CastFF dst));
7631
7632 size(0);
7633 format %{ "# castFF of $dst" %}
7634 ins_encode(/* empty encoding */);
7635 ins_cost(0);
7636 ins_pipe(empty);
7637 %}
7638
7639 instruct castHH(regF dst)
7640 %{
7641 match(Set dst (CastHH dst));
7642
7643 size(0);
7644 format %{ "# castHH of $dst" %}
7645 ins_encode(/* empty encoding */);
7646 ins_cost(0);
7647 ins_pipe(empty);
7648 %}
7649
7650 instruct castDD(regD dst)
7651 %{
7652 match(Set dst (CastDD dst));
7653
7654 size(0);
7655 format %{ "# castDD of $dst" %}
7656 ins_encode(/* empty encoding */);
7657 ins_cost(0);
7658 ins_pipe(empty);
7659 %}
7660
7661 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7662 instruct compareAndSwapP(rRegI res,
7663 memory mem_ptr,
7664 rax_RegP oldval, rRegP newval,
7665 rFlagsReg cr)
7666 %{
7667 predicate(n->as_LoadStore()->barrier_data() == 0);
7668 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7669 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7670 effect(KILL cr, KILL oldval);
7671
7672 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7673 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7674 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7675 ins_encode %{
7676 __ lock();
7677 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7678 __ setcc(Assembler::equal, $res$$Register);
7679 %}
7680 ins_pipe( pipe_cmpxchg );
7681 %}
7682
7683 instruct compareAndSwapL(rRegI res,
7684 memory mem_ptr,
7685 rax_RegL oldval, rRegL newval,
7686 rFlagsReg cr)
7687 %{
7688 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7689 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7690 effect(KILL cr, KILL oldval);
7691
7692 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7693 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7694 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7695 ins_encode %{
7696 __ lock();
7697 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7698 __ setcc(Assembler::equal, $res$$Register);
7699 %}
7700 ins_pipe( pipe_cmpxchg );
7701 %}
7702
7703 instruct compareAndSwapI(rRegI res,
7704 memory mem_ptr,
7705 rax_RegI oldval, rRegI newval,
7706 rFlagsReg cr)
7707 %{
7708 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7709 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7710 effect(KILL cr, KILL oldval);
7711
7712 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7713 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7714 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7715 ins_encode %{
7716 __ lock();
7717 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7718 __ setcc(Assembler::equal, $res$$Register);
7719 %}
7720 ins_pipe( pipe_cmpxchg );
7721 %}
7722
7723 instruct compareAndSwapB(rRegI res,
7724 memory mem_ptr,
7725 rax_RegI oldval, rRegI newval,
7726 rFlagsReg cr)
7727 %{
7728 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7729 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7730 effect(KILL cr, KILL oldval);
7731
7732 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7733 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7734 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7735 ins_encode %{
7736 __ lock();
7737 __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
7738 __ setcc(Assembler::equal, $res$$Register);
7739 %}
7740 ins_pipe( pipe_cmpxchg );
7741 %}
7742
7743 instruct compareAndSwapS(rRegI res,
7744 memory mem_ptr,
7745 rax_RegI oldval, rRegI newval,
7746 rFlagsReg cr)
7747 %{
7748 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7749 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7750 effect(KILL cr, KILL oldval);
7751
7752 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7753 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7754 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7755 ins_encode %{
7756 __ lock();
7757 __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
7758 __ setcc(Assembler::equal, $res$$Register);
7759 %}
7760 ins_pipe( pipe_cmpxchg );
7761 %}
7762
7763 instruct compareAndSwapN(rRegI res,
7764 memory mem_ptr,
7765 rax_RegN oldval, rRegN newval,
7766 rFlagsReg cr) %{
7767 predicate(n->as_LoadStore()->barrier_data() == 0);
7768 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7769 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7770 effect(KILL cr, KILL oldval);
7771
7772 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7773 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7774 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7775 ins_encode %{
7776 __ lock();
7777 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7778 __ setcc(Assembler::equal, $res$$Register);
7779 %}
7780 ins_pipe( pipe_cmpxchg );
7781 %}
7782
7783 instruct compareAndExchangeB(
7784 memory mem_ptr,
7785 rax_RegI oldval, rRegI newval,
7786 rFlagsReg cr)
7787 %{
7788 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7789 effect(KILL cr);
7790
7791 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7792 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7793 ins_encode %{
7794 __ lock();
7795 __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
7796 %}
7797 ins_pipe( pipe_cmpxchg );
7798 %}
7799
7800 instruct compareAndExchangeS(
7801 memory mem_ptr,
7802 rax_RegI oldval, rRegI newval,
7803 rFlagsReg cr)
7804 %{
7805 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7806 effect(KILL cr);
7807
7808 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7809 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7810 ins_encode %{
7811 __ lock();
7812 __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
7813 %}
7814 ins_pipe( pipe_cmpxchg );
7815 %}
7816
7817 instruct compareAndExchangeI(
7818 memory mem_ptr,
7819 rax_RegI oldval, rRegI newval,
7820 rFlagsReg cr)
7821 %{
7822 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7823 effect(KILL cr);
7824
7825 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7826 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7827 ins_encode %{
7828 __ lock();
7829 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7830 %}
7831 ins_pipe( pipe_cmpxchg );
7832 %}
7833
7834 instruct compareAndExchangeL(
7835 memory mem_ptr,
7836 rax_RegL oldval, rRegL newval,
7837 rFlagsReg cr)
7838 %{
7839 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7840 effect(KILL cr);
7841
7842 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7843 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7844 ins_encode %{
7845 __ lock();
7846 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7847 %}
7848 ins_pipe( pipe_cmpxchg );
7849 %}
7850
7851 instruct compareAndExchangeN(
7852 memory mem_ptr,
7853 rax_RegN oldval, rRegN newval,
7854 rFlagsReg cr) %{
7855 predicate(n->as_LoadStore()->barrier_data() == 0);
7856 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7857 effect(KILL cr);
7858
7859 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7860 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7861 ins_encode %{
7862 __ lock();
7863 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7864 %}
7865 ins_pipe( pipe_cmpxchg );
7866 %}
7867
7868 instruct compareAndExchangeP(
7869 memory mem_ptr,
7870 rax_RegP oldval, rRegP newval,
7871 rFlagsReg cr)
7872 %{
7873 predicate(n->as_LoadStore()->barrier_data() == 0);
7874 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7875 effect(KILL cr);
7876
7877 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7878 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7879 ins_encode %{
7880 __ lock();
7881 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7882 %}
7883 ins_pipe( pipe_cmpxchg );
7884 %}
7885
7886 instruct xaddB_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
7887 predicate(n->as_LoadStore()->result_not_used());
7888 match(Set dummy (GetAndAddB mem add));
7889 effect(KILL cr);
7890 format %{ "addb_lock $mem, $add" %}
7891 ins_encode %{
7892 __ lock();
7893 __ addb($mem$$Address, $add$$Register);
7894 %}
7895 ins_pipe(pipe_cmpxchg);
7896 %}
7897
7898 instruct xaddB_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7899 predicate(n->as_LoadStore()->result_not_used());
7900 match(Set dummy (GetAndAddB mem add));
7901 effect(KILL cr);
7902 format %{ "addb_lock $mem, $add" %}
7903 ins_encode %{
7904 __ lock();
7905 __ addb($mem$$Address, $add$$constant);
7906 %}
7907 ins_pipe(pipe_cmpxchg);
7908 %}
7909
7910 instruct xaddB(memory mem, rRegI newval, rFlagsReg cr) %{
7911 predicate(!n->as_LoadStore()->result_not_used());
7912 match(Set newval (GetAndAddB mem newval));
7913 effect(KILL cr);
7914 format %{ "xaddb_lock $mem, $newval" %}
7915 ins_encode %{
7916 __ lock();
7917 __ xaddb($mem$$Address, $newval$$Register);
7918 %}
7919 ins_pipe(pipe_cmpxchg);
7920 %}
7921
7922 instruct xaddS_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
7923 predicate(n->as_LoadStore()->result_not_used());
7924 match(Set dummy (GetAndAddS mem add));
7925 effect(KILL cr);
7926 format %{ "addw_lock $mem, $add" %}
7927 ins_encode %{
7928 __ lock();
7929 __ addw($mem$$Address, $add$$Register);
7930 %}
7931 ins_pipe(pipe_cmpxchg);
7932 %}
7933
7934 instruct xaddS_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7935 predicate(UseStoreImmI16 && n->as_LoadStore()->result_not_used());
7936 match(Set dummy (GetAndAddS mem add));
7937 effect(KILL cr);
7938 format %{ "addw_lock $mem, $add" %}
7939 ins_encode %{
7940 __ lock();
7941 __ addw($mem$$Address, $add$$constant);
7942 %}
7943 ins_pipe(pipe_cmpxchg);
7944 %}
7945
7946 instruct xaddS(memory mem, rRegI newval, rFlagsReg cr) %{
7947 predicate(!n->as_LoadStore()->result_not_used());
7948 match(Set newval (GetAndAddS mem newval));
7949 effect(KILL cr);
7950 format %{ "xaddw_lock $mem, $newval" %}
7951 ins_encode %{
7952 __ lock();
7953 __ xaddw($mem$$Address, $newval$$Register);
7954 %}
7955 ins_pipe(pipe_cmpxchg);
7956 %}
7957
7958 instruct xaddI_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
7959 predicate(n->as_LoadStore()->result_not_used());
7960 match(Set dummy (GetAndAddI mem add));
7961 effect(KILL cr);
7962 format %{ "addl_lock $mem, $add" %}
7963 ins_encode %{
7964 __ lock();
7965 __ addl($mem$$Address, $add$$Register);
7966 %}
7967 ins_pipe(pipe_cmpxchg);
7968 %}
7969
7970 instruct xaddI_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7971 predicate(n->as_LoadStore()->result_not_used());
7972 match(Set dummy (GetAndAddI mem add));
7973 effect(KILL cr);
7974 format %{ "addl_lock $mem, $add" %}
7975 ins_encode %{
7976 __ lock();
7977 __ addl($mem$$Address, $add$$constant);
7978 %}
7979 ins_pipe(pipe_cmpxchg);
7980 %}
7981
7982 instruct xaddI(memory mem, rRegI newval, rFlagsReg cr) %{
7983 predicate(!n->as_LoadStore()->result_not_used());
7984 match(Set newval (GetAndAddI mem newval));
7985 effect(KILL cr);
7986 format %{ "xaddl_lock $mem, $newval" %}
7987 ins_encode %{
7988 __ lock();
7989 __ xaddl($mem$$Address, $newval$$Register);
7990 %}
7991 ins_pipe(pipe_cmpxchg);
7992 %}
7993
7994 instruct xaddL_reg_no_res(memory mem, Universe dummy, rRegL add, rFlagsReg cr) %{
7995 predicate(n->as_LoadStore()->result_not_used());
7996 match(Set dummy (GetAndAddL mem add));
7997 effect(KILL cr);
7998 format %{ "addq_lock $mem, $add" %}
7999 ins_encode %{
8000 __ lock();
8001 __ addq($mem$$Address, $add$$Register);
8002 %}
8003 ins_pipe(pipe_cmpxchg);
8004 %}
8005
8006 instruct xaddL_imm_no_res(memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
8007 predicate(n->as_LoadStore()->result_not_used());
8008 match(Set dummy (GetAndAddL mem add));
8009 effect(KILL cr);
8010 format %{ "addq_lock $mem, $add" %}
8011 ins_encode %{
8012 __ lock();
8013 __ addq($mem$$Address, $add$$constant);
8014 %}
8015 ins_pipe(pipe_cmpxchg);
8016 %}
8017
8018 instruct xaddL(memory mem, rRegL newval, rFlagsReg cr) %{
8019 predicate(!n->as_LoadStore()->result_not_used());
8020 match(Set newval (GetAndAddL mem newval));
8021 effect(KILL cr);
8022 format %{ "xaddq_lock $mem, $newval" %}
8023 ins_encode %{
8024 __ lock();
8025 __ xaddq($mem$$Address, $newval$$Register);
8026 %}
8027 ins_pipe(pipe_cmpxchg);
8028 %}
8029
8030 instruct xchgB( memory mem, rRegI newval) %{
8031 match(Set newval (GetAndSetB mem newval));
8032 format %{ "XCHGB $newval,[$mem]" %}
8033 ins_encode %{
8034 __ xchgb($newval$$Register, $mem$$Address);
8035 %}
8036 ins_pipe( pipe_cmpxchg );
8037 %}
8038
8039 instruct xchgS( memory mem, rRegI newval) %{
8040 match(Set newval (GetAndSetS mem newval));
8041 format %{ "XCHGW $newval,[$mem]" %}
8042 ins_encode %{
8043 __ xchgw($newval$$Register, $mem$$Address);
8044 %}
8045 ins_pipe( pipe_cmpxchg );
8046 %}
8047
8048 instruct xchgI( memory mem, rRegI newval) %{
8049 match(Set newval (GetAndSetI mem newval));
8050 format %{ "XCHGL $newval,[$mem]" %}
8051 ins_encode %{
8052 __ xchgl($newval$$Register, $mem$$Address);
8053 %}
8054 ins_pipe( pipe_cmpxchg );
8055 %}
8056
8057 instruct xchgL( memory mem, rRegL newval) %{
8058 match(Set newval (GetAndSetL mem newval));
8059 format %{ "XCHGL $newval,[$mem]" %}
8060 ins_encode %{
8061 __ xchgq($newval$$Register, $mem$$Address);
8062 %}
8063 ins_pipe( pipe_cmpxchg );
8064 %}
8065
8066 instruct xchgP( memory mem, rRegP newval) %{
8067 match(Set newval (GetAndSetP mem newval));
8068 predicate(n->as_LoadStore()->barrier_data() == 0);
8069 format %{ "XCHGQ $newval,[$mem]" %}
8070 ins_encode %{
8071 __ xchgq($newval$$Register, $mem$$Address);
8072 %}
8073 ins_pipe( pipe_cmpxchg );
8074 %}
8075
8076 instruct xchgN( memory mem, rRegN newval) %{
8077 predicate(n->as_LoadStore()->barrier_data() == 0);
8078 match(Set newval (GetAndSetN mem newval));
8079 format %{ "XCHGL $newval,$mem]" %}
8080 ins_encode %{
8081 __ xchgl($newval$$Register, $mem$$Address);
8082 %}
8083 ins_pipe( pipe_cmpxchg );
8084 %}
8085
8086 //----------Abs Instructions-------------------------------------------
8087
8088 // Integer Absolute Instructions
8089 instruct absI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8090 %{
8091 match(Set dst (AbsI src));
8092 effect(TEMP dst, KILL cr);
8093 format %{ "xorl $dst, $dst\t# abs int\n\t"
8094 "subl $dst, $src\n\t"
8095 "cmovll $dst, $src" %}
8096 ins_encode %{
8097 __ xorl($dst$$Register, $dst$$Register);
8098 __ subl($dst$$Register, $src$$Register);
8099 __ cmovl(Assembler::less, $dst$$Register, $src$$Register);
8100 %}
8101
8102 ins_pipe(ialu_reg_reg);
8103 %}
8104
8105 // Long Absolute Instructions
8106 instruct absL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8107 %{
8108 match(Set dst (AbsL src));
8109 effect(TEMP dst, KILL cr);
8110 format %{ "xorl $dst, $dst\t# abs long\n\t"
8111 "subq $dst, $src\n\t"
8112 "cmovlq $dst, $src" %}
8113 ins_encode %{
8114 __ xorl($dst$$Register, $dst$$Register);
8115 __ subq($dst$$Register, $src$$Register);
8116 __ cmovq(Assembler::less, $dst$$Register, $src$$Register);
8117 %}
8118
8119 ins_pipe(ialu_reg_reg);
8120 %}
8121
8122 //----------Subtraction Instructions-------------------------------------------
8123
8124 // Integer Subtraction Instructions
8125 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8126 %{
8127 predicate(!UseAPX);
8128 match(Set dst (SubI dst src));
8129 effect(KILL cr);
8130 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8131
8132 format %{ "subl $dst, $src\t# int" %}
8133 ins_encode %{
8134 __ subl($dst$$Register, $src$$Register);
8135 %}
8136 ins_pipe(ialu_reg_reg);
8137 %}
8138
8139 instruct subI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
8140 %{
8141 predicate(UseAPX);
8142 match(Set dst (SubI src1 src2));
8143 effect(KILL cr);
8144 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8145
8146 format %{ "esubl $dst, $src1, $src2\t# int ndd" %}
8147 ins_encode %{
8148 __ esubl($dst$$Register, $src1$$Register, $src2$$Register, false);
8149 %}
8150 ins_pipe(ialu_reg_reg);
8151 %}
8152
8153 instruct subI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
8154 %{
8155 predicate(UseAPX);
8156 match(Set dst (SubI src1 src2));
8157 effect(KILL cr);
8158 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8159
8160 format %{ "esubl $dst, $src1, $src2\t# int ndd" %}
8161 ins_encode %{
8162 __ esubl($dst$$Register, $src1$$Register, $src2$$constant, false);
8163 %}
8164 ins_pipe(ialu_reg_reg);
8165 %}
8166
8167 instruct subI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
8168 %{
8169 predicate(UseAPX);
8170 match(Set dst (SubI (LoadI src1) src2));
8171 effect(KILL cr);
8172 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8173
8174 format %{ "esubl $dst, $src1, $src2\t# int ndd" %}
8175 ins_encode %{
8176 __ esubl($dst$$Register, $src1$$Address, $src2$$constant, false);
8177 %}
8178 ins_pipe(ialu_reg_reg);
8179 %}
8180
8181 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8182 %{
8183 predicate(!UseAPX);
8184 match(Set dst (SubI dst (LoadI src)));
8185 effect(KILL cr);
8186 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8187
8188 ins_cost(150);
8189 format %{ "subl $dst, $src\t# int" %}
8190 ins_encode %{
8191 __ subl($dst$$Register, $src$$Address);
8192 %}
8193 ins_pipe(ialu_reg_mem);
8194 %}
8195
8196 instruct subI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
8197 %{
8198 predicate(UseAPX);
8199 match(Set dst (SubI src1 (LoadI src2)));
8200 effect(KILL cr);
8201 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8202
8203 ins_cost(150);
8204 format %{ "esubl $dst, $src1, $src2\t# int ndd" %}
8205 ins_encode %{
8206 __ esubl($dst$$Register, $src1$$Register, $src2$$Address, false);
8207 %}
8208 ins_pipe(ialu_reg_mem);
8209 %}
8210
8211 instruct subI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr)
8212 %{
8213 predicate(UseAPX);
8214 match(Set dst (SubI (LoadI src1) src2));
8215 effect(KILL cr);
8216 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8217
8218 ins_cost(150);
8219 format %{ "esubl $dst, $src1, $src2\t# int ndd" %}
8220 ins_encode %{
8221 __ esubl($dst$$Register, $src1$$Address, $src2$$Register, false);
8222 %}
8223 ins_pipe(ialu_reg_mem);
8224 %}
8225
8226 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8227 %{
8228 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8229 effect(KILL cr);
8230 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8231
8232 ins_cost(150);
8233 format %{ "subl $dst, $src\t# int" %}
8234 ins_encode %{
8235 __ subl($dst$$Address, $src$$Register);
8236 %}
8237 ins_pipe(ialu_mem_reg);
8238 %}
8239
8240 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8241 %{
8242 predicate(!UseAPX);
8243 match(Set dst (SubL dst src));
8244 effect(KILL cr);
8245 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8246
8247 format %{ "subq $dst, $src\t# long" %}
8248 ins_encode %{
8249 __ subq($dst$$Register, $src$$Register);
8250 %}
8251 ins_pipe(ialu_reg_reg);
8252 %}
8253
8254 instruct subL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
8255 %{
8256 predicate(UseAPX);
8257 match(Set dst (SubL src1 src2));
8258 effect(KILL cr);
8259 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8260
8261 format %{ "esubq $dst, $src1, $src2\t# long ndd" %}
8262 ins_encode %{
8263 __ esubq($dst$$Register, $src1$$Register, $src2$$Register, false);
8264 %}
8265 ins_pipe(ialu_reg_reg);
8266 %}
8267
8268 instruct subL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
8269 %{
8270 predicate(UseAPX);
8271 match(Set dst (SubL src1 src2));
8272 effect(KILL cr);
8273 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8274
8275 format %{ "esubq $dst, $src1, $src2\t# long ndd" %}
8276 ins_encode %{
8277 __ esubq($dst$$Register, $src1$$Register, $src2$$constant, false);
8278 %}
8279 ins_pipe(ialu_reg_reg);
8280 %}
8281
8282 instruct subL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
8283 %{
8284 predicate(UseAPX);
8285 match(Set dst (SubL (LoadL src1) src2));
8286 effect(KILL cr);
8287 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8288
8289 format %{ "esubq $dst, $src1, $src2\t# long ndd" %}
8290 ins_encode %{
8291 __ esubq($dst$$Register, $src1$$Address, $src2$$constant, false);
8292 %}
8293 ins_pipe(ialu_reg_reg);
8294 %}
8295
8296 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8297 %{
8298 predicate(!UseAPX);
8299 match(Set dst (SubL dst (LoadL src)));
8300 effect(KILL cr);
8301 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8302
8303 ins_cost(150);
8304 format %{ "subq $dst, $src\t# long" %}
8305 ins_encode %{
8306 __ subq($dst$$Register, $src$$Address);
8307 %}
8308 ins_pipe(ialu_reg_mem);
8309 %}
8310
8311 instruct subL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
8312 %{
8313 predicate(UseAPX);
8314 match(Set dst (SubL src1 (LoadL src2)));
8315 effect(KILL cr);
8316 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8317
8318 ins_cost(150);
8319 format %{ "esubq $dst, $src1, $src2\t# long ndd" %}
8320 ins_encode %{
8321 __ esubq($dst$$Register, $src1$$Register, $src2$$Address, false);
8322 %}
8323 ins_pipe(ialu_reg_mem);
8324 %}
8325
8326 instruct subL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
8327 %{
8328 predicate(UseAPX);
8329 match(Set dst (SubL (LoadL src1) src2));
8330 effect(KILL cr);
8331 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8332
8333 ins_cost(150);
8334 format %{ "esubq $dst, $src1, $src2\t# long ndd" %}
8335 ins_encode %{
8336 __ esubq($dst$$Register, $src1$$Address, $src2$$Register, false);
8337 %}
8338 ins_pipe(ialu_reg_mem);
8339 %}
8340
8341 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8342 %{
8343 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8344 effect(KILL cr);
8345 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8346
8347 ins_cost(150);
8348 format %{ "subq $dst, $src\t# long" %}
8349 ins_encode %{
8350 __ subq($dst$$Address, $src$$Register);
8351 %}
8352 ins_pipe(ialu_mem_reg);
8353 %}
8354
8355 // Subtract from a pointer
8356 // XXX hmpf???
8357 instruct subP_rReg(rRegP dst, rRegI src, immI_0 zero, rFlagsReg cr)
8358 %{
8359 match(Set dst (AddP dst (SubI zero src)));
8360 effect(KILL cr);
8361
8362 format %{ "subq $dst, $src\t# ptr - int" %}
8363 ins_encode %{
8364 __ subq($dst$$Register, $src$$Register);
8365 %}
8366 ins_pipe(ialu_reg_reg);
8367 %}
8368
8369 instruct negI_rReg(rRegI dst, immI_0 zero, rFlagsReg cr)
8370 %{
8371 predicate(!UseAPX);
8372 match(Set dst (SubI zero dst));
8373 effect(KILL cr);
8374 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8375
8376 format %{ "negl $dst\t# int" %}
8377 ins_encode %{
8378 __ negl($dst$$Register);
8379 %}
8380 ins_pipe(ialu_reg);
8381 %}
8382
8383 instruct negI_rReg_ndd(rRegI dst, rRegI src, immI_0 zero, rFlagsReg cr)
8384 %{
8385 predicate(UseAPX);
8386 match(Set dst (SubI zero src));
8387 effect(KILL cr);
8388 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8389
8390 format %{ "enegl $dst, $src\t# int ndd" %}
8391 ins_encode %{
8392 __ enegl($dst$$Register, $src$$Register, false);
8393 %}
8394 ins_pipe(ialu_reg);
8395 %}
8396
8397 instruct negI_rReg_2(rRegI dst, rFlagsReg cr)
8398 %{
8399 predicate(!UseAPX);
8400 match(Set dst (NegI dst));
8401 effect(KILL cr);
8402 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8403
8404 format %{ "negl $dst\t# int" %}
8405 ins_encode %{
8406 __ negl($dst$$Register);
8407 %}
8408 ins_pipe(ialu_reg);
8409 %}
8410
8411 instruct negI_rReg_2_ndd(rRegI dst, rRegI src, rFlagsReg cr)
8412 %{
8413 predicate(UseAPX);
8414 match(Set dst (NegI src));
8415 effect(KILL cr);
8416 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8417
8418 format %{ "enegl $dst, $src\t# int ndd" %}
8419 ins_encode %{
8420 __ enegl($dst$$Register, $src$$Register, false);
8421 %}
8422 ins_pipe(ialu_reg);
8423 %}
8424
8425 instruct negI_mem(memory dst, immI_0 zero, rFlagsReg cr)
8426 %{
8427 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8428 effect(KILL cr);
8429 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8430
8431 format %{ "negl $dst\t# int" %}
8432 ins_encode %{
8433 __ negl($dst$$Address);
8434 %}
8435 ins_pipe(ialu_reg);
8436 %}
8437
8438 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8439 %{
8440 predicate(!UseAPX);
8441 match(Set dst (SubL zero dst));
8442 effect(KILL cr);
8443 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8444
8445 format %{ "negq $dst\t# long" %}
8446 ins_encode %{
8447 __ negq($dst$$Register);
8448 %}
8449 ins_pipe(ialu_reg);
8450 %}
8451
8452 instruct negL_rReg_ndd(rRegL dst, rRegL src, immL0 zero, rFlagsReg cr)
8453 %{
8454 predicate(UseAPX);
8455 match(Set dst (SubL zero src));
8456 effect(KILL cr);
8457 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8458
8459 format %{ "enegq $dst, $src\t# long ndd" %}
8460 ins_encode %{
8461 __ enegq($dst$$Register, $src$$Register, false);
8462 %}
8463 ins_pipe(ialu_reg);
8464 %}
8465
8466 instruct negL_rReg_2(rRegL dst, rFlagsReg cr)
8467 %{
8468 predicate(!UseAPX);
8469 match(Set dst (NegL dst));
8470 effect(KILL cr);
8471 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8472
8473 format %{ "negq $dst\t# int" %}
8474 ins_encode %{
8475 __ negq($dst$$Register);
8476 %}
8477 ins_pipe(ialu_reg);
8478 %}
8479
8480 instruct negL_rReg_2_ndd(rRegL dst, rRegL src, rFlagsReg cr)
8481 %{
8482 predicate(UseAPX);
8483 match(Set dst (NegL src));
8484 effect(KILL cr);
8485 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8486
8487 format %{ "enegq $dst, $src\t# long ndd" %}
8488 ins_encode %{
8489 __ enegq($dst$$Register, $src$$Register, false);
8490 %}
8491 ins_pipe(ialu_reg);
8492 %}
8493
8494 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8495 %{
8496 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8497 effect(KILL cr);
8498 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8499
8500 format %{ "negq $dst\t# long" %}
8501 ins_encode %{
8502 __ negq($dst$$Address);
8503 %}
8504 ins_pipe(ialu_reg);
8505 %}
8506
8507 //----------Multiplication/Division Instructions-------------------------------
8508 // Integer Multiplication Instructions
8509 // Multiply Register
8510
8511 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8512 %{
8513 predicate(!UseAPX);
8514 match(Set dst (MulI dst src));
8515 effect(KILL cr);
8516
8517 ins_cost(300);
8518 format %{ "imull $dst, $src\t# int" %}
8519 ins_encode %{
8520 __ imull($dst$$Register, $src$$Register);
8521 %}
8522 ins_pipe(ialu_reg_reg_alu0);
8523 %}
8524
8525 instruct mulI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
8526 %{
8527 predicate(UseAPX);
8528 match(Set dst (MulI src1 src2));
8529 effect(KILL cr);
8530
8531 ins_cost(300);
8532 format %{ "eimull $dst, $src1, $src2\t# int ndd" %}
8533 ins_encode %{
8534 __ eimull($dst$$Register, $src1$$Register, $src2$$Register, false);
8535 %}
8536 ins_pipe(ialu_reg_reg_alu0);
8537 %}
8538
8539 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8540 %{
8541 predicate(!UseAPX);
8542 match(Set dst (MulI src imm));
8543 effect(KILL cr);
8544
8545 ins_cost(300);
8546 format %{ "imull $dst, $src, $imm\t# int" %}
8547 ins_encode %{
8548 __ imull($dst$$Register, $src$$Register, $imm$$constant);
8549 %}
8550 ins_pipe(ialu_reg_reg_alu0);
8551 %}
8552
8553 instruct mulI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
8554 %{
8555 predicate(UseAPX);
8556 match(Set dst (MulI src1 src2));
8557 effect(KILL cr);
8558
8559 ins_cost(300);
8560 format %{ "eimull $dst, $src1, $src2\t# int ndd" %}
8561 ins_encode %{
8562 __ eimull($dst$$Register, $src1$$Register, $src2$$constant, false);
8563 %}
8564 ins_pipe(ialu_reg_reg_alu0);
8565 %}
8566
8567 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8568 %{
8569 predicate(!UseAPX);
8570 match(Set dst (MulI dst (LoadI src)));
8571 effect(KILL cr);
8572
8573 ins_cost(350);
8574 format %{ "imull $dst, $src\t# int" %}
8575 ins_encode %{
8576 __ imull($dst$$Register, $src$$Address);
8577 %}
8578 ins_pipe(ialu_reg_mem_alu0);
8579 %}
8580
8581 instruct mulI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
8582 %{
8583 predicate(UseAPX);
8584 match(Set dst (MulI src1 (LoadI src2)));
8585 effect(KILL cr);
8586
8587 ins_cost(350);
8588 format %{ "eimull $dst, $src1, $src2\t# int ndd" %}
8589 ins_encode %{
8590 __ eimull($dst$$Register, $src1$$Register, $src2$$Address, false);
8591 %}
8592 ins_pipe(ialu_reg_mem_alu0);
8593 %}
8594
8595 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8596 %{
8597 predicate(!UseAPX);
8598 match(Set dst (MulI (LoadI src) imm));
8599 effect(KILL cr);
8600
8601 ins_cost(300);
8602 format %{ "imull $dst, $src, $imm\t# int" %}
8603 ins_encode %{
8604 __ imull($dst$$Register, $src$$Address, $imm$$constant);
8605 %}
8606 ins_pipe(ialu_reg_mem_alu0);
8607 %}
8608
8609 instruct mulI_rReg_mem_imm(rRegI dst, memory src1, immI src2, rFlagsReg cr)
8610 %{
8611 predicate(UseAPX);
8612 match(Set dst (MulI (LoadI src1) src2));
8613 effect(KILL cr);
8614
8615 ins_cost(300);
8616 format %{ "eimull $dst, $src1, $src2\t# int ndd" %}
8617 ins_encode %{
8618 __ eimull($dst$$Register, $src1$$Address, $src2$$constant, false);
8619 %}
8620 ins_pipe(ialu_reg_mem_alu0);
8621 %}
8622
8623 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
8624 %{
8625 match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
8626 effect(KILL cr, KILL src2);
8627
8628 expand %{ mulI_rReg(dst, src1, cr);
8629 mulI_rReg(src2, src3, cr);
8630 addI_rReg(dst, src2, cr); %}
8631 %}
8632
8633 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8634 %{
8635 predicate(!UseAPX);
8636 match(Set dst (MulL dst src));
8637 effect(KILL cr);
8638
8639 ins_cost(300);
8640 format %{ "imulq $dst, $src\t# long" %}
8641 ins_encode %{
8642 __ imulq($dst$$Register, $src$$Register);
8643 %}
8644 ins_pipe(ialu_reg_reg_alu0);
8645 %}
8646
8647 instruct mulL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
8648 %{
8649 predicate(UseAPX);
8650 match(Set dst (MulL src1 src2));
8651 effect(KILL cr);
8652
8653 ins_cost(300);
8654 format %{ "eimulq $dst, $src1, $src2\t# long ndd" %}
8655 ins_encode %{
8656 __ eimulq($dst$$Register, $src1$$Register, $src2$$Register, false);
8657 %}
8658 ins_pipe(ialu_reg_reg_alu0);
8659 %}
8660
8661 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8662 %{
8663 predicate(!UseAPX);
8664 match(Set dst (MulL src imm));
8665 effect(KILL cr);
8666
8667 ins_cost(300);
8668 format %{ "imulq $dst, $src, $imm\t# long" %}
8669 ins_encode %{
8670 __ imulq($dst$$Register, $src$$Register, $imm$$constant);
8671 %}
8672 ins_pipe(ialu_reg_reg_alu0);
8673 %}
8674
8675 instruct mulL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
8676 %{
8677 predicate(UseAPX);
8678 match(Set dst (MulL src1 src2));
8679 effect(KILL cr);
8680
8681 ins_cost(300);
8682 format %{ "eimulq $dst, $src1, $src2\t# long ndd" %}
8683 ins_encode %{
8684 __ eimulq($dst$$Register, $src1$$Register, $src2$$constant, false);
8685 %}
8686 ins_pipe(ialu_reg_reg_alu0);
8687 %}
8688
8689 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8690 %{
8691 predicate(!UseAPX);
8692 match(Set dst (MulL dst (LoadL src)));
8693 effect(KILL cr);
8694
8695 ins_cost(350);
8696 format %{ "imulq $dst, $src\t# long" %}
8697 ins_encode %{
8698 __ imulq($dst$$Register, $src$$Address);
8699 %}
8700 ins_pipe(ialu_reg_mem_alu0);
8701 %}
8702
8703 instruct mulL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
8704 %{
8705 predicate(UseAPX);
8706 match(Set dst (MulL src1 (LoadL src2)));
8707 effect(KILL cr);
8708
8709 ins_cost(350);
8710 format %{ "eimulq $dst, $src1, $src2 \t# long" %}
8711 ins_encode %{
8712 __ eimulq($dst$$Register, $src1$$Register, $src2$$Address, false);
8713 %}
8714 ins_pipe(ialu_reg_mem_alu0);
8715 %}
8716
8717 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8718 %{
8719 predicate(!UseAPX);
8720 match(Set dst (MulL (LoadL src) imm));
8721 effect(KILL cr);
8722
8723 ins_cost(300);
8724 format %{ "imulq $dst, $src, $imm\t# long" %}
8725 ins_encode %{
8726 __ imulq($dst$$Register, $src$$Address, $imm$$constant);
8727 %}
8728 ins_pipe(ialu_reg_mem_alu0);
8729 %}
8730
8731 instruct mulL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
8732 %{
8733 predicate(UseAPX);
8734 match(Set dst (MulL (LoadL src1) src2));
8735 effect(KILL cr);
8736
8737 ins_cost(300);
8738 format %{ "eimulq $dst, $src1, $src2\t# long ndd" %}
8739 ins_encode %{
8740 __ eimulq($dst$$Register, $src1$$Address, $src2$$constant, false);
8741 %}
8742 ins_pipe(ialu_reg_mem_alu0);
8743 %}
8744
8745 instruct mulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr)
8746 %{
8747 match(Set dst (MulHiL src rax));
8748 effect(USE_KILL rax, KILL cr);
8749
8750 ins_cost(300);
8751 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8752 ins_encode %{
8753 __ imulq($src$$Register);
8754 %}
8755 ins_pipe(ialu_reg_reg_alu0);
8756 %}
8757
8758 instruct umulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr)
8759 %{
8760 match(Set dst (UMulHiL src rax));
8761 effect(USE_KILL rax, KILL cr);
8762
8763 ins_cost(300);
8764 format %{ "mulq RDX:RAX, RAX, $src\t# umulhi" %}
8765 ins_encode %{
8766 __ mulq($src$$Register);
8767 %}
8768 ins_pipe(ialu_reg_reg_alu0);
8769 %}
8770
8771 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8772 rFlagsReg cr)
8773 %{
8774 match(Set rax (DivI rax div));
8775 effect(KILL rdx, KILL cr);
8776
8777 ins_cost(30*100+10*100); // XXX
8778 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8779 "jne,s normal\n\t"
8780 "xorl rdx, rdx\n\t"
8781 "cmpl $div, -1\n\t"
8782 "je,s done\n"
8783 "normal: cdql\n\t"
8784 "idivl $div\n"
8785 "done:" %}
8786 ins_encode(cdql_enc(div));
8787 ins_pipe(ialu_reg_reg_alu0);
8788 %}
8789
8790 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8791 rFlagsReg cr)
8792 %{
8793 match(Set rax (DivL rax div));
8794 effect(KILL rdx, KILL cr);
8795
8796 ins_cost(30*100+10*100); // XXX
8797 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8798 "cmpq rax, rdx\n\t"
8799 "jne,s normal\n\t"
8800 "xorl rdx, rdx\n\t"
8801 "cmpq $div, -1\n\t"
8802 "je,s done\n"
8803 "normal: cdqq\n\t"
8804 "idivq $div\n"
8805 "done:" %}
8806 ins_encode(cdqq_enc(div));
8807 ins_pipe(ialu_reg_reg_alu0);
8808 %}
8809
8810 instruct udivI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, rFlagsReg cr)
8811 %{
8812 match(Set rax (UDivI rax div));
8813 effect(KILL rdx, KILL cr);
8814
8815 ins_cost(300);
8816 format %{ "udivl $rax,$rax,$div\t# UDivI\n" %}
8817 ins_encode %{
8818 __ udivI($rax$$Register, $div$$Register, $rdx$$Register);
8819 %}
8820 ins_pipe(ialu_reg_reg_alu0);
8821 %}
8822
8823 instruct udivL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, rFlagsReg cr)
8824 %{
8825 match(Set rax (UDivL rax div));
8826 effect(KILL rdx, KILL cr);
8827
8828 ins_cost(300);
8829 format %{ "udivq $rax,$rax,$div\t# UDivL\n" %}
8830 ins_encode %{
8831 __ udivL($rax$$Register, $div$$Register, $rdx$$Register);
8832 %}
8833 ins_pipe(ialu_reg_reg_alu0);
8834 %}
8835
8836 // Integer DIVMOD with Register, both quotient and mod results
8837 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8838 rFlagsReg cr)
8839 %{
8840 match(DivModI rax div);
8841 effect(KILL cr);
8842
8843 ins_cost(30*100+10*100); // XXX
8844 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8845 "jne,s normal\n\t"
8846 "xorl rdx, rdx\n\t"
8847 "cmpl $div, -1\n\t"
8848 "je,s done\n"
8849 "normal: cdql\n\t"
8850 "idivl $div\n"
8851 "done:" %}
8852 ins_encode(cdql_enc(div));
8853 ins_pipe(pipe_slow);
8854 %}
8855
8856 // Long DIVMOD with Register, both quotient and mod results
8857 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8858 rFlagsReg cr)
8859 %{
8860 match(DivModL rax div);
8861 effect(KILL cr);
8862
8863 ins_cost(30*100+10*100); // XXX
8864 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8865 "cmpq rax, rdx\n\t"
8866 "jne,s normal\n\t"
8867 "xorl rdx, rdx\n\t"
8868 "cmpq $div, -1\n\t"
8869 "je,s done\n"
8870 "normal: cdqq\n\t"
8871 "idivq $div\n"
8872 "done:" %}
8873 ins_encode(cdqq_enc(div));
8874 ins_pipe(pipe_slow);
8875 %}
8876
8877 // Unsigned integer DIVMOD with Register, both quotient and mod results
8878 instruct udivModI_rReg_divmod(rax_RegI rax, no_rax_rdx_RegI tmp, rdx_RegI rdx,
8879 no_rax_rdx_RegI div, rFlagsReg cr)
8880 %{
8881 match(UDivModI rax div);
8882 effect(TEMP tmp, KILL cr);
8883
8884 ins_cost(300);
8885 format %{ "udivl $rax,$rax,$div\t# begin UDivModI\n\t"
8886 "umodl $rdx,$rax,$div\t! using $tmp as TEMP # end UDivModI\n"
8887 %}
8888 ins_encode %{
8889 __ udivmodI($rax$$Register, $div$$Register, $rdx$$Register, $tmp$$Register);
8890 %}
8891 ins_pipe(pipe_slow);
8892 %}
8893
8894 // Unsigned long DIVMOD with Register, both quotient and mod results
8895 instruct udivModL_rReg_divmod(rax_RegL rax, no_rax_rdx_RegL tmp, rdx_RegL rdx,
8896 no_rax_rdx_RegL div, rFlagsReg cr)
8897 %{
8898 match(UDivModL rax div);
8899 effect(TEMP tmp, KILL cr);
8900
8901 ins_cost(300);
8902 format %{ "udivq $rax,$rax,$div\t# begin UDivModL\n\t"
8903 "umodq $rdx,$rax,$div\t! using $tmp as TEMP # end UDivModL\n"
8904 %}
8905 ins_encode %{
8906 __ udivmodL($rax$$Register, $div$$Register, $rdx$$Register, $tmp$$Register);
8907 %}
8908 ins_pipe(pipe_slow);
8909 %}
8910
8911 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8912 rFlagsReg cr)
8913 %{
8914 match(Set rdx (ModI rax div));
8915 effect(KILL rax, KILL cr);
8916
8917 ins_cost(300); // XXX
8918 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8919 "jne,s normal\n\t"
8920 "xorl rdx, rdx\n\t"
8921 "cmpl $div, -1\n\t"
8922 "je,s done\n"
8923 "normal: cdql\n\t"
8924 "idivl $div\n"
8925 "done:" %}
8926 ins_encode(cdql_enc(div));
8927 ins_pipe(ialu_reg_reg_alu0);
8928 %}
8929
8930 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8931 rFlagsReg cr)
8932 %{
8933 match(Set rdx (ModL rax div));
8934 effect(KILL rax, KILL cr);
8935
8936 ins_cost(300); // XXX
8937 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8938 "cmpq rax, rdx\n\t"
8939 "jne,s normal\n\t"
8940 "xorl rdx, rdx\n\t"
8941 "cmpq $div, -1\n\t"
8942 "je,s done\n"
8943 "normal: cdqq\n\t"
8944 "idivq $div\n"
8945 "done:" %}
8946 ins_encode(cdqq_enc(div));
8947 ins_pipe(ialu_reg_reg_alu0);
8948 %}
8949
8950 instruct umodI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, rFlagsReg cr)
8951 %{
8952 match(Set rdx (UModI rax div));
8953 effect(KILL rax, KILL cr);
8954
8955 ins_cost(300);
8956 format %{ "umodl $rdx,$rax,$div\t# UModI\n" %}
8957 ins_encode %{
8958 __ umodI($rax$$Register, $div$$Register, $rdx$$Register);
8959 %}
8960 ins_pipe(ialu_reg_reg_alu0);
8961 %}
8962
8963 instruct umodL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, rFlagsReg cr)
8964 %{
8965 match(Set rdx (UModL rax div));
8966 effect(KILL rax, KILL cr);
8967
8968 ins_cost(300);
8969 format %{ "umodq $rdx,$rax,$div\t# UModL\n" %}
8970 ins_encode %{
8971 __ umodL($rax$$Register, $div$$Register, $rdx$$Register);
8972 %}
8973 ins_pipe(ialu_reg_reg_alu0);
8974 %}
8975
8976 // Integer Shift Instructions
8977 // Shift Left by one, two, three
8978 instruct salI_rReg_immI2(rRegI dst, immI2 shift, rFlagsReg cr)
8979 %{
8980 predicate(!UseAPX);
8981 match(Set dst (LShiftI dst shift));
8982 effect(KILL cr);
8983
8984 format %{ "sall $dst, $shift" %}
8985 ins_encode %{
8986 __ sall($dst$$Register, $shift$$constant);
8987 %}
8988 ins_pipe(ialu_reg);
8989 %}
8990
8991 // Shift Left by one, two, three
8992 instruct salI_rReg_immI2_ndd(rRegI dst, rRegI src, immI2 shift, rFlagsReg cr)
8993 %{
8994 predicate(UseAPX);
8995 match(Set dst (LShiftI src shift));
8996 effect(KILL cr);
8997
8998 format %{ "esall $dst, $src, $shift\t# int(ndd)" %}
8999 ins_encode %{
9000 __ esall($dst$$Register, $src$$Register, $shift$$constant, false);
9001 %}
9002 ins_pipe(ialu_reg);
9003 %}
9004
9005 // Shift Left by 8-bit immediate
9006 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
9007 %{
9008 predicate(!UseAPX);
9009 match(Set dst (LShiftI dst shift));
9010 effect(KILL cr);
9011
9012 format %{ "sall $dst, $shift" %}
9013 ins_encode %{
9014 __ sall($dst$$Register, $shift$$constant);
9015 %}
9016 ins_pipe(ialu_reg);
9017 %}
9018
9019 // Shift Left by 8-bit immediate
9020 instruct salI_rReg_imm_ndd(rRegI dst, rRegI src, immI8 shift, rFlagsReg cr)
9021 %{
9022 predicate(UseAPX);
9023 match(Set dst (LShiftI src shift));
9024 effect(KILL cr);
9025
9026 format %{ "esall $dst, $src, $shift\t# int (ndd)" %}
9027 ins_encode %{
9028 __ esall($dst$$Register, $src$$Register, $shift$$constant, false);
9029 %}
9030 ins_pipe(ialu_reg);
9031 %}
9032
9033 instruct salI_rReg_mem_imm_ndd(rRegI dst, memory src, immI8 shift, rFlagsReg cr)
9034 %{
9035 predicate(UseAPX);
9036 match(Set dst (LShiftI (LoadI src) shift));
9037 effect(KILL cr);
9038
9039 format %{ "esall $dst, $src, $shift\t# int (ndd)" %}
9040 ins_encode %{
9041 __ esall($dst$$Register, $src$$Address, $shift$$constant, false);
9042 %}
9043 ins_pipe(ialu_reg);
9044 %}
9045
9046 // Shift Left by 8-bit immediate
9047 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9048 %{
9049 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
9050 effect(KILL cr);
9051
9052 format %{ "sall $dst, $shift" %}
9053 ins_encode %{
9054 __ sall($dst$$Address, $shift$$constant);
9055 %}
9056 ins_pipe(ialu_mem_imm);
9057 %}
9058
9059 // Shift Left by variable
9060 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9061 %{
9062 predicate(!VM_Version::supports_bmi2());
9063 match(Set dst (LShiftI dst shift));
9064 effect(KILL cr);
9065
9066 format %{ "sall $dst, $shift" %}
9067 ins_encode %{
9068 __ sall($dst$$Register);
9069 %}
9070 ins_pipe(ialu_reg_reg);
9071 %}
9072
9073 // Shift Left by variable
9074 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9075 %{
9076 predicate(!VM_Version::supports_bmi2());
9077 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
9078 effect(KILL cr);
9079
9080 format %{ "sall $dst, $shift" %}
9081 ins_encode %{
9082 __ sall($dst$$Address);
9083 %}
9084 ins_pipe(ialu_mem_reg);
9085 %}
9086
9087 instruct salI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
9088 %{
9089 predicate(VM_Version::supports_bmi2());
9090 match(Set dst (LShiftI src shift));
9091
9092 format %{ "shlxl $dst, $src, $shift" %}
9093 ins_encode %{
9094 __ shlxl($dst$$Register, $src$$Register, $shift$$Register);
9095 %}
9096 ins_pipe(ialu_reg_reg);
9097 %}
9098
9099 instruct salI_mem_rReg(rRegI dst, memory src, rRegI shift)
9100 %{
9101 predicate(VM_Version::supports_bmi2());
9102 match(Set dst (LShiftI (LoadI src) shift));
9103 ins_cost(175);
9104 format %{ "shlxl $dst, $src, $shift" %}
9105 ins_encode %{
9106 __ shlxl($dst$$Register, $src$$Address, $shift$$Register);
9107 %}
9108 ins_pipe(ialu_reg_mem);
9109 %}
9110
9111 // Arithmetic Shift Right by 8-bit immediate
9112 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
9113 %{
9114 predicate(!UseAPX);
9115 match(Set dst (RShiftI dst shift));
9116 effect(KILL cr);
9117
9118 format %{ "sarl $dst, $shift" %}
9119 ins_encode %{
9120 __ sarl($dst$$Register, $shift$$constant);
9121 %}
9122 ins_pipe(ialu_mem_imm);
9123 %}
9124
9125 // Arithmetic Shift Right by 8-bit immediate
9126 instruct sarI_rReg_imm_ndd(rRegI dst, rRegI src, immI8 shift, rFlagsReg cr)
9127 %{
9128 predicate(UseAPX);
9129 match(Set dst (RShiftI src shift));
9130 effect(KILL cr);
9131
9132 format %{ "esarl $dst, $src, $shift\t# int (ndd)" %}
9133 ins_encode %{
9134 __ esarl($dst$$Register, $src$$Register, $shift$$constant, false);
9135 %}
9136 ins_pipe(ialu_mem_imm);
9137 %}
9138
9139 instruct sarI_rReg_mem_imm_ndd(rRegI dst, memory src, immI8 shift, rFlagsReg cr)
9140 %{
9141 predicate(UseAPX);
9142 match(Set dst (RShiftI (LoadI src) shift));
9143 effect(KILL cr);
9144
9145 format %{ "esarl $dst, $src, $shift\t# int (ndd)" %}
9146 ins_encode %{
9147 __ esarl($dst$$Register, $src$$Address, $shift$$constant, false);
9148 %}
9149 ins_pipe(ialu_mem_imm);
9150 %}
9151
9152 // Arithmetic Shift Right by 8-bit immediate
9153 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9154 %{
9155 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9156 effect(KILL cr);
9157
9158 format %{ "sarl $dst, $shift" %}
9159 ins_encode %{
9160 __ sarl($dst$$Address, $shift$$constant);
9161 %}
9162 ins_pipe(ialu_mem_imm);
9163 %}
9164
9165 // Arithmetic Shift Right by variable
9166 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9167 %{
9168 predicate(!VM_Version::supports_bmi2());
9169 match(Set dst (RShiftI dst shift));
9170 effect(KILL cr);
9171
9172 format %{ "sarl $dst, $shift" %}
9173 ins_encode %{
9174 __ sarl($dst$$Register);
9175 %}
9176 ins_pipe(ialu_reg_reg);
9177 %}
9178
9179 // Arithmetic Shift Right by variable
9180 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9181 %{
9182 predicate(!VM_Version::supports_bmi2());
9183 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9184 effect(KILL cr);
9185
9186 format %{ "sarl $dst, $shift" %}
9187 ins_encode %{
9188 __ sarl($dst$$Address);
9189 %}
9190 ins_pipe(ialu_mem_reg);
9191 %}
9192
9193 instruct sarI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
9194 %{
9195 predicate(VM_Version::supports_bmi2());
9196 match(Set dst (RShiftI src shift));
9197
9198 format %{ "sarxl $dst, $src, $shift" %}
9199 ins_encode %{
9200 __ sarxl($dst$$Register, $src$$Register, $shift$$Register);
9201 %}
9202 ins_pipe(ialu_reg_reg);
9203 %}
9204
9205 instruct sarI_mem_rReg(rRegI dst, memory src, rRegI shift)
9206 %{
9207 predicate(VM_Version::supports_bmi2());
9208 match(Set dst (RShiftI (LoadI src) shift));
9209 ins_cost(175);
9210 format %{ "sarxl $dst, $src, $shift" %}
9211 ins_encode %{
9212 __ sarxl($dst$$Register, $src$$Address, $shift$$Register);
9213 %}
9214 ins_pipe(ialu_reg_mem);
9215 %}
9216
9217 // Logical Shift Right by 8-bit immediate
9218 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
9219 %{
9220 predicate(!UseAPX);
9221 match(Set dst (URShiftI dst shift));
9222 effect(KILL cr);
9223
9224 format %{ "shrl $dst, $shift" %}
9225 ins_encode %{
9226 __ shrl($dst$$Register, $shift$$constant);
9227 %}
9228 ins_pipe(ialu_reg);
9229 %}
9230
9231 // Logical Shift Right by 8-bit immediate
9232 instruct shrI_rReg_imm_ndd(rRegI dst, rRegI src, immI8 shift, rFlagsReg cr)
9233 %{
9234 predicate(UseAPX);
9235 match(Set dst (URShiftI src shift));
9236 effect(KILL cr);
9237
9238 format %{ "eshrl $dst, $src, $shift\t # int (ndd)" %}
9239 ins_encode %{
9240 __ eshrl($dst$$Register, $src$$Register, $shift$$constant, false);
9241 %}
9242 ins_pipe(ialu_reg);
9243 %}
9244
9245 instruct shrI_rReg_mem_imm_ndd(rRegI dst, memory src, immI8 shift, rFlagsReg cr)
9246 %{
9247 predicate(UseAPX);
9248 match(Set dst (URShiftI (LoadI src) shift));
9249 effect(KILL cr);
9250
9251 format %{ "eshrl $dst, $src, $shift\t # int (ndd)" %}
9252 ins_encode %{
9253 __ eshrl($dst$$Register, $src$$Address, $shift$$constant, false);
9254 %}
9255 ins_pipe(ialu_reg);
9256 %}
9257
9258 // Logical Shift Right by 8-bit immediate
9259 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9260 %{
9261 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
9262 effect(KILL cr);
9263
9264 format %{ "shrl $dst, $shift" %}
9265 ins_encode %{
9266 __ shrl($dst$$Address, $shift$$constant);
9267 %}
9268 ins_pipe(ialu_mem_imm);
9269 %}
9270
9271 // Logical Shift Right by variable
9272 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9273 %{
9274 predicate(!VM_Version::supports_bmi2());
9275 match(Set dst (URShiftI dst shift));
9276 effect(KILL cr);
9277
9278 format %{ "shrl $dst, $shift" %}
9279 ins_encode %{
9280 __ shrl($dst$$Register);
9281 %}
9282 ins_pipe(ialu_reg_reg);
9283 %}
9284
9285 // Logical Shift Right by variable
9286 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9287 %{
9288 predicate(!VM_Version::supports_bmi2());
9289 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
9290 effect(KILL cr);
9291
9292 format %{ "shrl $dst, $shift" %}
9293 ins_encode %{
9294 __ shrl($dst$$Address);
9295 %}
9296 ins_pipe(ialu_mem_reg);
9297 %}
9298
9299 instruct shrI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
9300 %{
9301 predicate(VM_Version::supports_bmi2());
9302 match(Set dst (URShiftI src shift));
9303
9304 format %{ "shrxl $dst, $src, $shift" %}
9305 ins_encode %{
9306 __ shrxl($dst$$Register, $src$$Register, $shift$$Register);
9307 %}
9308 ins_pipe(ialu_reg_reg);
9309 %}
9310
9311 instruct shrI_mem_rReg(rRegI dst, memory src, rRegI shift)
9312 %{
9313 predicate(VM_Version::supports_bmi2());
9314 match(Set dst (URShiftI (LoadI src) shift));
9315 ins_cost(175);
9316 format %{ "shrxl $dst, $src, $shift" %}
9317 ins_encode %{
9318 __ shrxl($dst$$Register, $src$$Address, $shift$$Register);
9319 %}
9320 ins_pipe(ialu_reg_mem);
9321 %}
9322
9323 // Long Shift Instructions
9324 // Shift Left by one, two, three
9325 instruct salL_rReg_immI2(rRegL dst, immI2 shift, rFlagsReg cr)
9326 %{
9327 predicate(!UseAPX);
9328 match(Set dst (LShiftL dst shift));
9329 effect(KILL cr);
9330
9331 format %{ "salq $dst, $shift" %}
9332 ins_encode %{
9333 __ salq($dst$$Register, $shift$$constant);
9334 %}
9335 ins_pipe(ialu_reg);
9336 %}
9337
9338 // Shift Left by one, two, three
9339 instruct salL_rReg_immI2_ndd(rRegL dst, rRegL src, immI2 shift, rFlagsReg cr)
9340 %{
9341 predicate(UseAPX);
9342 match(Set dst (LShiftL src shift));
9343 effect(KILL cr);
9344
9345 format %{ "esalq $dst, $src, $shift\t# long (ndd)" %}
9346 ins_encode %{
9347 __ esalq($dst$$Register, $src$$Register, $shift$$constant, false);
9348 %}
9349 ins_pipe(ialu_reg);
9350 %}
9351
9352 // Shift Left by 8-bit immediate
9353 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9354 %{
9355 predicate(!UseAPX);
9356 match(Set dst (LShiftL dst shift));
9357 effect(KILL cr);
9358
9359 format %{ "salq $dst, $shift" %}
9360 ins_encode %{
9361 __ salq($dst$$Register, $shift$$constant);
9362 %}
9363 ins_pipe(ialu_reg);
9364 %}
9365
9366 // Shift Left by 8-bit immediate
9367 instruct salL_rReg_imm_ndd(rRegL dst, rRegL src, immI8 shift, rFlagsReg cr)
9368 %{
9369 predicate(UseAPX);
9370 match(Set dst (LShiftL src shift));
9371 effect(KILL cr);
9372
9373 format %{ "esalq $dst, $src, $shift\t# long (ndd)" %}
9374 ins_encode %{
9375 __ esalq($dst$$Register, $src$$Register, $shift$$constant, false);
9376 %}
9377 ins_pipe(ialu_reg);
9378 %}
9379
9380 instruct salL_rReg_mem_imm_ndd(rRegL dst, memory src, immI8 shift, rFlagsReg cr)
9381 %{
9382 predicate(UseAPX);
9383 match(Set dst (LShiftL (LoadL src) shift));
9384 effect(KILL cr);
9385
9386 format %{ "esalq $dst, $src, $shift\t# long (ndd)" %}
9387 ins_encode %{
9388 __ esalq($dst$$Register, $src$$Address, $shift$$constant, false);
9389 %}
9390 ins_pipe(ialu_reg);
9391 %}
9392
9393 // Shift Left by 8-bit immediate
9394 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9395 %{
9396 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9397 effect(KILL cr);
9398
9399 format %{ "salq $dst, $shift" %}
9400 ins_encode %{
9401 __ salq($dst$$Address, $shift$$constant);
9402 %}
9403 ins_pipe(ialu_mem_imm);
9404 %}
9405
9406 // Shift Left by variable
9407 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9408 %{
9409 predicate(!VM_Version::supports_bmi2());
9410 match(Set dst (LShiftL dst shift));
9411 effect(KILL cr);
9412
9413 format %{ "salq $dst, $shift" %}
9414 ins_encode %{
9415 __ salq($dst$$Register);
9416 %}
9417 ins_pipe(ialu_reg_reg);
9418 %}
9419
9420 // Shift Left by variable
9421 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9422 %{
9423 predicate(!VM_Version::supports_bmi2());
9424 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9425 effect(KILL cr);
9426
9427 format %{ "salq $dst, $shift" %}
9428 ins_encode %{
9429 __ salq($dst$$Address);
9430 %}
9431 ins_pipe(ialu_mem_reg);
9432 %}
9433
9434 instruct salL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
9435 %{
9436 predicate(VM_Version::supports_bmi2());
9437 match(Set dst (LShiftL src shift));
9438
9439 format %{ "shlxq $dst, $src, $shift" %}
9440 ins_encode %{
9441 __ shlxq($dst$$Register, $src$$Register, $shift$$Register);
9442 %}
9443 ins_pipe(ialu_reg_reg);
9444 %}
9445
9446 instruct salL_mem_rReg(rRegL dst, memory src, rRegI shift)
9447 %{
9448 predicate(VM_Version::supports_bmi2());
9449 match(Set dst (LShiftL (LoadL src) shift));
9450 ins_cost(175);
9451 format %{ "shlxq $dst, $src, $shift" %}
9452 ins_encode %{
9453 __ shlxq($dst$$Register, $src$$Address, $shift$$Register);
9454 %}
9455 ins_pipe(ialu_reg_mem);
9456 %}
9457
9458 // Arithmetic Shift Right by 8-bit immediate
9459 instruct sarL_rReg_imm(rRegL dst, immI shift, rFlagsReg cr)
9460 %{
9461 predicate(!UseAPX);
9462 match(Set dst (RShiftL dst shift));
9463 effect(KILL cr);
9464
9465 format %{ "sarq $dst, $shift" %}
9466 ins_encode %{
9467 __ sarq($dst$$Register, (unsigned char)($shift$$constant & 0x3F));
9468 %}
9469 ins_pipe(ialu_mem_imm);
9470 %}
9471
9472 // Arithmetic Shift Right by 8-bit immediate
9473 instruct sarL_rReg_imm_ndd(rRegL dst, rRegL src, immI shift, rFlagsReg cr)
9474 %{
9475 predicate(UseAPX);
9476 match(Set dst (RShiftL src shift));
9477 effect(KILL cr);
9478
9479 format %{ "esarq $dst, $src, $shift\t# long (ndd)" %}
9480 ins_encode %{
9481 __ esarq($dst$$Register, $src$$Register, (unsigned char)($shift$$constant & 0x3F), false);
9482 %}
9483 ins_pipe(ialu_mem_imm);
9484 %}
9485
9486 instruct sarL_rReg_mem_imm_ndd(rRegL dst, memory src, immI shift, rFlagsReg cr)
9487 %{
9488 predicate(UseAPX);
9489 match(Set dst (RShiftL (LoadL src) shift));
9490 effect(KILL cr);
9491
9492 format %{ "esarq $dst, $src, $shift\t# long (ndd)" %}
9493 ins_encode %{
9494 __ esarq($dst$$Register, $src$$Address, (unsigned char)($shift$$constant & 0x3F), false);
9495 %}
9496 ins_pipe(ialu_mem_imm);
9497 %}
9498
9499 // Arithmetic Shift Right by 8-bit immediate
9500 instruct sarL_mem_imm(memory dst, immI shift, rFlagsReg cr)
9501 %{
9502 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9503 effect(KILL cr);
9504
9505 format %{ "sarq $dst, $shift" %}
9506 ins_encode %{
9507 __ sarq($dst$$Address, (unsigned char)($shift$$constant & 0x3F));
9508 %}
9509 ins_pipe(ialu_mem_imm);
9510 %}
9511
9512 // Arithmetic Shift Right by variable
9513 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9514 %{
9515 predicate(!VM_Version::supports_bmi2());
9516 match(Set dst (RShiftL dst shift));
9517 effect(KILL cr);
9518
9519 format %{ "sarq $dst, $shift" %}
9520 ins_encode %{
9521 __ sarq($dst$$Register);
9522 %}
9523 ins_pipe(ialu_reg_reg);
9524 %}
9525
9526 // Arithmetic Shift Right by variable
9527 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9528 %{
9529 predicate(!VM_Version::supports_bmi2());
9530 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9531 effect(KILL cr);
9532
9533 format %{ "sarq $dst, $shift" %}
9534 ins_encode %{
9535 __ sarq($dst$$Address);
9536 %}
9537 ins_pipe(ialu_mem_reg);
9538 %}
9539
9540 instruct sarL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
9541 %{
9542 predicate(VM_Version::supports_bmi2());
9543 match(Set dst (RShiftL src shift));
9544
9545 format %{ "sarxq $dst, $src, $shift" %}
9546 ins_encode %{
9547 __ sarxq($dst$$Register, $src$$Register, $shift$$Register);
9548 %}
9549 ins_pipe(ialu_reg_reg);
9550 %}
9551
9552 instruct sarL_mem_rReg(rRegL dst, memory src, rRegI shift)
9553 %{
9554 predicate(VM_Version::supports_bmi2());
9555 match(Set dst (RShiftL (LoadL src) shift));
9556 ins_cost(175);
9557 format %{ "sarxq $dst, $src, $shift" %}
9558 ins_encode %{
9559 __ sarxq($dst$$Register, $src$$Address, $shift$$Register);
9560 %}
9561 ins_pipe(ialu_reg_mem);
9562 %}
9563
9564 // Logical Shift Right by 8-bit immediate
9565 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9566 %{
9567 predicate(!UseAPX);
9568 match(Set dst (URShiftL dst shift));
9569 effect(KILL cr);
9570
9571 format %{ "shrq $dst, $shift" %}
9572 ins_encode %{
9573 __ shrq($dst$$Register, $shift$$constant);
9574 %}
9575 ins_pipe(ialu_reg);
9576 %}
9577
9578 // Logical Shift Right by 8-bit immediate
9579 instruct shrL_rReg_imm_ndd(rRegL dst, rRegL src, immI8 shift, rFlagsReg cr)
9580 %{
9581 predicate(UseAPX);
9582 match(Set dst (URShiftL src shift));
9583 effect(KILL cr);
9584
9585 format %{ "eshrq $dst, $src, $shift\t# long (ndd)" %}
9586 ins_encode %{
9587 __ eshrq($dst$$Register, $src$$Register, $shift$$constant, false);
9588 %}
9589 ins_pipe(ialu_reg);
9590 %}
9591
9592 instruct shrL_rReg_mem_imm_ndd(rRegL dst, memory src, immI8 shift, rFlagsReg cr)
9593 %{
9594 predicate(UseAPX);
9595 match(Set dst (URShiftL (LoadL src) shift));
9596 effect(KILL cr);
9597
9598 format %{ "eshrq $dst, $src, $shift\t# long (ndd)" %}
9599 ins_encode %{
9600 __ eshrq($dst$$Register, $src$$Address, $shift$$constant, false);
9601 %}
9602 ins_pipe(ialu_reg);
9603 %}
9604
9605 // Logical Shift Right by 8-bit immediate
9606 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9607 %{
9608 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9609 effect(KILL cr);
9610
9611 format %{ "shrq $dst, $shift" %}
9612 ins_encode %{
9613 __ shrq($dst$$Address, $shift$$constant);
9614 %}
9615 ins_pipe(ialu_mem_imm);
9616 %}
9617
9618 // Logical Shift Right by variable
9619 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9620 %{
9621 predicate(!VM_Version::supports_bmi2());
9622 match(Set dst (URShiftL dst shift));
9623 effect(KILL cr);
9624
9625 format %{ "shrq $dst, $shift" %}
9626 ins_encode %{
9627 __ shrq($dst$$Register);
9628 %}
9629 ins_pipe(ialu_reg_reg);
9630 %}
9631
9632 // Logical Shift Right by variable
9633 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9634 %{
9635 predicate(!VM_Version::supports_bmi2());
9636 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9637 effect(KILL cr);
9638
9639 format %{ "shrq $dst, $shift" %}
9640 ins_encode %{
9641 __ shrq($dst$$Address);
9642 %}
9643 ins_pipe(ialu_mem_reg);
9644 %}
9645
9646 instruct shrL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
9647 %{
9648 predicate(VM_Version::supports_bmi2());
9649 match(Set dst (URShiftL src shift));
9650
9651 format %{ "shrxq $dst, $src, $shift" %}
9652 ins_encode %{
9653 __ shrxq($dst$$Register, $src$$Register, $shift$$Register);
9654 %}
9655 ins_pipe(ialu_reg_reg);
9656 %}
9657
9658 instruct shrL_mem_rReg(rRegL dst, memory src, rRegI shift)
9659 %{
9660 predicate(VM_Version::supports_bmi2());
9661 match(Set dst (URShiftL (LoadL src) shift));
9662 ins_cost(175);
9663 format %{ "shrxq $dst, $src, $shift" %}
9664 ins_encode %{
9665 __ shrxq($dst$$Register, $src$$Address, $shift$$Register);
9666 %}
9667 ins_pipe(ialu_reg_mem);
9668 %}
9669
9670 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9671 // This idiom is used by the compiler for the i2b bytecode.
9672 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9673 %{
9674 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9675
9676 format %{ "movsbl $dst, $src\t# i2b" %}
9677 ins_encode %{
9678 __ movsbl($dst$$Register, $src$$Register);
9679 %}
9680 ins_pipe(ialu_reg_reg);
9681 %}
9682
9683 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9684 // This idiom is used by the compiler the i2s bytecode.
9685 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9686 %{
9687 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9688
9689 format %{ "movswl $dst, $src\t# i2s" %}
9690 ins_encode %{
9691 __ movswl($dst$$Register, $src$$Register);
9692 %}
9693 ins_pipe(ialu_reg_reg);
9694 %}
9695
9696 // ROL/ROR instructions
9697
9698 // Rotate left by constant.
9699 instruct rolI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
9700 %{
9701 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9702 match(Set dst (RotateLeft dst shift));
9703 effect(KILL cr);
9704 format %{ "roll $dst, $shift" %}
9705 ins_encode %{
9706 __ roll($dst$$Register, $shift$$constant);
9707 %}
9708 ins_pipe(ialu_reg);
9709 %}
9710
9711 instruct rolI_immI8(rRegI dst, rRegI src, immI8 shift)
9712 %{
9713 predicate(!UseAPX && VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9714 match(Set dst (RotateLeft src shift));
9715 format %{ "rolxl $dst, $src, $shift" %}
9716 ins_encode %{
9717 int shift = 32 - ($shift$$constant & 31);
9718 __ rorxl($dst$$Register, $src$$Register, shift);
9719 %}
9720 ins_pipe(ialu_reg_reg);
9721 %}
9722
9723 instruct rolI_mem_immI8(rRegI dst, memory src, immI8 shift)
9724 %{
9725 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9726 match(Set dst (RotateLeft (LoadI src) shift));
9727 ins_cost(175);
9728 format %{ "rolxl $dst, $src, $shift" %}
9729 ins_encode %{
9730 int shift = 32 - ($shift$$constant & 31);
9731 __ rorxl($dst$$Register, $src$$Address, shift);
9732 %}
9733 ins_pipe(ialu_reg_mem);
9734 %}
9735
9736 // Rotate Left by variable
9737 instruct rolI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9738 %{
9739 predicate(!UseAPX && n->bottom_type()->basic_type() == T_INT);
9740 match(Set dst (RotateLeft dst shift));
9741 effect(KILL cr);
9742 format %{ "roll $dst, $shift" %}
9743 ins_encode %{
9744 __ roll($dst$$Register);
9745 %}
9746 ins_pipe(ialu_reg_reg);
9747 %}
9748
9749 // Rotate Left by variable
9750 instruct rolI_rReg_Var_ndd(rRegI dst, rRegI src, rcx_RegI shift, rFlagsReg cr)
9751 %{
9752 predicate(UseAPX && n->bottom_type()->basic_type() == T_INT);
9753 match(Set dst (RotateLeft src shift));
9754 effect(KILL cr);
9755
9756 format %{ "eroll $dst, $src, $shift\t# rotate left (int ndd)" %}
9757 ins_encode %{
9758 __ eroll($dst$$Register, $src$$Register, false);
9759 %}
9760 ins_pipe(ialu_reg_reg);
9761 %}
9762
9763 // Rotate Right by constant.
9764 instruct rorI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
9765 %{
9766 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9767 match(Set dst (RotateRight dst shift));
9768 effect(KILL cr);
9769 format %{ "rorl $dst, $shift" %}
9770 ins_encode %{
9771 __ rorl($dst$$Register, $shift$$constant);
9772 %}
9773 ins_pipe(ialu_reg);
9774 %}
9775
9776 // Rotate Right by constant.
9777 instruct rorI_immI8(rRegI dst, rRegI src, immI8 shift)
9778 %{
9779 predicate(!UseAPX && VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9780 match(Set dst (RotateRight src shift));
9781 format %{ "rorxl $dst, $src, $shift" %}
9782 ins_encode %{
9783 __ rorxl($dst$$Register, $src$$Register, $shift$$constant);
9784 %}
9785 ins_pipe(ialu_reg_reg);
9786 %}
9787
9788 instruct rorI_mem_immI8(rRegI dst, memory src, immI8 shift)
9789 %{
9790 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9791 match(Set dst (RotateRight (LoadI src) shift));
9792 ins_cost(175);
9793 format %{ "rorxl $dst, $src, $shift" %}
9794 ins_encode %{
9795 __ rorxl($dst$$Register, $src$$Address, $shift$$constant);
9796 %}
9797 ins_pipe(ialu_reg_mem);
9798 %}
9799
9800 // Rotate Right by variable
9801 instruct rorI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9802 %{
9803 predicate(!UseAPX && n->bottom_type()->basic_type() == T_INT);
9804 match(Set dst (RotateRight dst shift));
9805 effect(KILL cr);
9806 format %{ "rorl $dst, $shift" %}
9807 ins_encode %{
9808 __ rorl($dst$$Register);
9809 %}
9810 ins_pipe(ialu_reg_reg);
9811 %}
9812
9813 // Rotate Right by variable
9814 instruct rorI_rReg_Var_ndd(rRegI dst, rRegI src, rcx_RegI shift, rFlagsReg cr)
9815 %{
9816 predicate(UseAPX && n->bottom_type()->basic_type() == T_INT);
9817 match(Set dst (RotateRight src shift));
9818 effect(KILL cr);
9819
9820 format %{ "erorl $dst, $src, $shift\t# rotate right(int ndd)" %}
9821 ins_encode %{
9822 __ erorl($dst$$Register, $src$$Register, false);
9823 %}
9824 ins_pipe(ialu_reg_reg);
9825 %}
9826
9827 // Rotate Left by constant.
9828 instruct rolL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr)
9829 %{
9830 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9831 match(Set dst (RotateLeft dst shift));
9832 effect(KILL cr);
9833 format %{ "rolq $dst, $shift" %}
9834 ins_encode %{
9835 __ rolq($dst$$Register, $shift$$constant);
9836 %}
9837 ins_pipe(ialu_reg);
9838 %}
9839
9840 instruct rolL_immI8(rRegL dst, rRegL src, immI8 shift)
9841 %{
9842 predicate(!UseAPX && VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9843 match(Set dst (RotateLeft src shift));
9844 format %{ "rolxq $dst, $src, $shift" %}
9845 ins_encode %{
9846 int shift = 64 - ($shift$$constant & 63);
9847 __ rorxq($dst$$Register, $src$$Register, shift);
9848 %}
9849 ins_pipe(ialu_reg_reg);
9850 %}
9851
9852 instruct rolL_mem_immI8(rRegL dst, memory src, immI8 shift)
9853 %{
9854 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9855 match(Set dst (RotateLeft (LoadL src) shift));
9856 ins_cost(175);
9857 format %{ "rolxq $dst, $src, $shift" %}
9858 ins_encode %{
9859 int shift = 64 - ($shift$$constant & 63);
9860 __ rorxq($dst$$Register, $src$$Address, shift);
9861 %}
9862 ins_pipe(ialu_reg_mem);
9863 %}
9864
9865 // Rotate Left by variable
9866 instruct rolL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9867 %{
9868 predicate(!UseAPX && n->bottom_type()->basic_type() == T_LONG);
9869 match(Set dst (RotateLeft dst shift));
9870 effect(KILL cr);
9871 format %{ "rolq $dst, $shift" %}
9872 ins_encode %{
9873 __ rolq($dst$$Register);
9874 %}
9875 ins_pipe(ialu_reg_reg);
9876 %}
9877
9878 // Rotate Left by variable
9879 instruct rolL_rReg_Var_ndd(rRegL dst, rRegL src, rcx_RegI shift, rFlagsReg cr)
9880 %{
9881 predicate(UseAPX && n->bottom_type()->basic_type() == T_LONG);
9882 match(Set dst (RotateLeft src shift));
9883 effect(KILL cr);
9884
9885 format %{ "erolq $dst, $src, $shift\t# rotate left(long ndd)" %}
9886 ins_encode %{
9887 __ erolq($dst$$Register, $src$$Register, false);
9888 %}
9889 ins_pipe(ialu_reg_reg);
9890 %}
9891
9892 // Rotate Right by constant.
9893 instruct rorL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr)
9894 %{
9895 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9896 match(Set dst (RotateRight dst shift));
9897 effect(KILL cr);
9898 format %{ "rorq $dst, $shift" %}
9899 ins_encode %{
9900 __ rorq($dst$$Register, $shift$$constant);
9901 %}
9902 ins_pipe(ialu_reg);
9903 %}
9904
9905 // Rotate Right by constant
9906 instruct rorL_immI8(rRegL dst, rRegL src, immI8 shift)
9907 %{
9908 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9909 match(Set dst (RotateRight src shift));
9910 format %{ "rorxq $dst, $src, $shift" %}
9911 ins_encode %{
9912 __ rorxq($dst$$Register, $src$$Register, $shift$$constant);
9913 %}
9914 ins_pipe(ialu_reg_reg);
9915 %}
9916
9917 instruct rorL_mem_immI8(rRegL dst, memory src, immI8 shift)
9918 %{
9919 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9920 match(Set dst (RotateRight (LoadL src) shift));
9921 ins_cost(175);
9922 format %{ "rorxq $dst, $src, $shift" %}
9923 ins_encode %{
9924 __ rorxq($dst$$Register, $src$$Address, $shift$$constant);
9925 %}
9926 ins_pipe(ialu_reg_mem);
9927 %}
9928
9929 // Rotate Right by variable
9930 instruct rorL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9931 %{
9932 predicate(!UseAPX && n->bottom_type()->basic_type() == T_LONG);
9933 match(Set dst (RotateRight dst shift));
9934 effect(KILL cr);
9935 format %{ "rorq $dst, $shift" %}
9936 ins_encode %{
9937 __ rorq($dst$$Register);
9938 %}
9939 ins_pipe(ialu_reg_reg);
9940 %}
9941
9942 // Rotate Right by variable
9943 instruct rorL_rReg_Var_ndd(rRegL dst, rRegL src, rcx_RegI shift, rFlagsReg cr)
9944 %{
9945 predicate(UseAPX && n->bottom_type()->basic_type() == T_LONG);
9946 match(Set dst (RotateRight src shift));
9947 effect(KILL cr);
9948
9949 format %{ "erorq $dst, $src, $shift\t# rotate right(long ndd)" %}
9950 ins_encode %{
9951 __ erorq($dst$$Register, $src$$Register, false);
9952 %}
9953 ins_pipe(ialu_reg_reg);
9954 %}
9955
9956 //----------------------------- CompressBits/ExpandBits ------------------------
9957
9958 instruct compressBitsL_reg(rRegL dst, rRegL src, rRegL mask) %{
9959 predicate(n->bottom_type()->isa_long());
9960 match(Set dst (CompressBits src mask));
9961 format %{ "pextq $dst, $src, $mask\t! parallel bit extract" %}
9962 ins_encode %{
9963 __ pextq($dst$$Register, $src$$Register, $mask$$Register);
9964 %}
9965 ins_pipe( pipe_slow );
9966 %}
9967
9968 instruct expandBitsL_reg(rRegL dst, rRegL src, rRegL mask) %{
9969 predicate(n->bottom_type()->isa_long());
9970 match(Set dst (ExpandBits src mask));
9971 format %{ "pdepq $dst, $src, $mask\t! parallel bit deposit" %}
9972 ins_encode %{
9973 __ pdepq($dst$$Register, $src$$Register, $mask$$Register);
9974 %}
9975 ins_pipe( pipe_slow );
9976 %}
9977
9978 instruct compressBitsL_mem(rRegL dst, rRegL src, memory mask) %{
9979 predicate(n->bottom_type()->isa_long());
9980 match(Set dst (CompressBits src (LoadL mask)));
9981 format %{ "pextq $dst, $src, $mask\t! parallel bit extract" %}
9982 ins_encode %{
9983 __ pextq($dst$$Register, $src$$Register, $mask$$Address);
9984 %}
9985 ins_pipe( pipe_slow );
9986 %}
9987
9988 instruct expandBitsL_mem(rRegL dst, rRegL src, memory mask) %{
9989 predicate(n->bottom_type()->isa_long());
9990 match(Set dst (ExpandBits src (LoadL mask)));
9991 format %{ "pdepq $dst, $src, $mask\t! parallel bit deposit" %}
9992 ins_encode %{
9993 __ pdepq($dst$$Register, $src$$Register, $mask$$Address);
9994 %}
9995 ins_pipe( pipe_slow );
9996 %}
9997
9998
9999 // Logical Instructions
10000
10001 // Integer Logical Instructions
10002
10003 // And Instructions
10004 // And Register with Register
10005 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
10006 %{
10007 predicate(!UseAPX);
10008 match(Set dst (AndI dst src));
10009 effect(KILL cr);
10010 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10011
10012 format %{ "andl $dst, $src\t# int" %}
10013 ins_encode %{
10014 __ andl($dst$$Register, $src$$Register);
10015 %}
10016 ins_pipe(ialu_reg_reg);
10017 %}
10018
10019 // And Register with Register using New Data Destination (NDD)
10020 instruct andI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
10021 %{
10022 predicate(UseAPX);
10023 match(Set dst (AndI src1 src2));
10024 effect(KILL cr);
10025 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10026
10027 format %{ "eandl $dst, $src1, $src2\t# int ndd" %}
10028 ins_encode %{
10029 __ eandl($dst$$Register, $src1$$Register, $src2$$Register, false);
10030
10031 %}
10032 ins_pipe(ialu_reg_reg);
10033 %}
10034
10035 // And Register with Immediate 255
10036 instruct andI_rReg_imm255(rRegI dst, rRegI src, immI_255 mask)
10037 %{
10038 match(Set dst (AndI src mask));
10039
10040 format %{ "movzbl $dst, $src\t# int & 0xFF" %}
10041 ins_encode %{
10042 __ movzbl($dst$$Register, $src$$Register);
10043 %}
10044 ins_pipe(ialu_reg);
10045 %}
10046
10047 // And Register with Immediate 255 and promote to long
10048 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
10049 %{
10050 match(Set dst (ConvI2L (AndI src mask)));
10051
10052 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
10053 ins_encode %{
10054 __ movzbl($dst$$Register, $src$$Register);
10055 %}
10056 ins_pipe(ialu_reg);
10057 %}
10058
10059 // And Register with Immediate 65535
10060 instruct andI_rReg_imm65535(rRegI dst, rRegI src, immI_65535 mask)
10061 %{
10062 match(Set dst (AndI src mask));
10063
10064 format %{ "movzwl $dst, $src\t# int & 0xFFFF" %}
10065 ins_encode %{
10066 __ movzwl($dst$$Register, $src$$Register);
10067 %}
10068 ins_pipe(ialu_reg);
10069 %}
10070
10071 // And Register with Immediate 65535 and promote to long
10072 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
10073 %{
10074 match(Set dst (ConvI2L (AndI src mask)));
10075
10076 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
10077 ins_encode %{
10078 __ movzwl($dst$$Register, $src$$Register);
10079 %}
10080 ins_pipe(ialu_reg);
10081 %}
10082
10083 // Can skip int2long conversions after AND with small bitmask
10084 instruct convI2LAndI_reg_immIbitmask(rRegL dst, rRegI src, immI_Pow2M1 mask, rRegI tmp, rFlagsReg cr)
10085 %{
10086 predicate(VM_Version::supports_bmi2());
10087 ins_cost(125);
10088 effect(TEMP tmp, KILL cr);
10089 match(Set dst (ConvI2L (AndI src mask)));
10090 format %{ "bzhiq $dst, $src, $mask \t# using $tmp as TEMP, int & immI_Pow2M1 -> long" %}
10091 ins_encode %{
10092 __ movl($tmp$$Register, exact_log2($mask$$constant + 1));
10093 __ bzhiq($dst$$Register, $src$$Register, $tmp$$Register);
10094 %}
10095 ins_pipe(ialu_reg_reg);
10096 %}
10097
10098 // And Register with Immediate
10099 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
10100 %{
10101 predicate(!UseAPX);
10102 match(Set dst (AndI dst src));
10103 effect(KILL cr);
10104 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10105
10106 format %{ "andl $dst, $src\t# int" %}
10107 ins_encode %{
10108 __ andl($dst$$Register, $src$$constant);
10109 %}
10110 ins_pipe(ialu_reg);
10111 %}
10112
10113 instruct andI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
10114 %{
10115 predicate(UseAPX);
10116 match(Set dst (AndI src1 src2));
10117 effect(KILL cr);
10118 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10119
10120 format %{ "eandl $dst, $src1, $src2\t# int ndd" %}
10121 ins_encode %{
10122 __ eandl($dst$$Register, $src1$$Register, $src2$$constant, false);
10123 %}
10124 ins_pipe(ialu_reg);
10125 %}
10126
10127 instruct andI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
10128 %{
10129 predicate(UseAPX);
10130 match(Set dst (AndI (LoadI src1) src2));
10131 effect(KILL cr);
10132 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10133
10134 format %{ "eandl $dst, $src1, $src2\t# int ndd" %}
10135 ins_encode %{
10136 __ eandl($dst$$Register, $src1$$Address, $src2$$constant, false);
10137 %}
10138 ins_pipe(ialu_reg);
10139 %}
10140
10141 // And Register with Memory
10142 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
10143 %{
10144 predicate(!UseAPX);
10145 match(Set dst (AndI dst (LoadI src)));
10146 effect(KILL cr);
10147 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10148
10149 ins_cost(150);
10150 format %{ "andl $dst, $src\t# int" %}
10151 ins_encode %{
10152 __ andl($dst$$Register, $src$$Address);
10153 %}
10154 ins_pipe(ialu_reg_mem);
10155 %}
10156
10157 instruct andI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
10158 %{
10159 predicate(UseAPX);
10160 match(Set dst (AndI src1 (LoadI src2)));
10161 effect(KILL cr);
10162 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10163
10164 ins_cost(150);
10165 format %{ "eandl $dst, $src1, $src2\t# int ndd" %}
10166 ins_encode %{
10167 __ eandl($dst$$Register, $src1$$Register, $src2$$Address, false);
10168 %}
10169 ins_pipe(ialu_reg_mem);
10170 %}
10171
10172 // And Memory with Register
10173 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10174 %{
10175 match(Set dst (StoreB dst (AndI (LoadB dst) src)));
10176 effect(KILL cr);
10177 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10178
10179 ins_cost(150);
10180 format %{ "andb $dst, $src\t# byte" %}
10181 ins_encode %{
10182 __ andb($dst$$Address, $src$$Register);
10183 %}
10184 ins_pipe(ialu_mem_reg);
10185 %}
10186
10187 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10188 %{
10189 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
10190 effect(KILL cr);
10191 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10192
10193 ins_cost(150);
10194 format %{ "andl $dst, $src\t# int" %}
10195 ins_encode %{
10196 __ andl($dst$$Address, $src$$Register);
10197 %}
10198 ins_pipe(ialu_mem_reg);
10199 %}
10200
10201 // And Memory with Immediate
10202 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
10203 %{
10204 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
10205 effect(KILL cr);
10206 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10207
10208 ins_cost(125);
10209 format %{ "andl $dst, $src\t# int" %}
10210 ins_encode %{
10211 __ andl($dst$$Address, $src$$constant);
10212 %}
10213 ins_pipe(ialu_mem_imm);
10214 %}
10215
10216 // BMI1 instructions
10217 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
10218 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
10219 predicate(UseBMI1Instructions);
10220 effect(KILL cr);
10221 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10222
10223 ins_cost(125);
10224 format %{ "andnl $dst, $src1, $src2" %}
10225
10226 ins_encode %{
10227 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
10228 %}
10229 ins_pipe(ialu_reg_mem);
10230 %}
10231
10232 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
10233 match(Set dst (AndI (XorI src1 minus_1) src2));
10234 predicate(UseBMI1Instructions);
10235 effect(KILL cr);
10236 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10237
10238 format %{ "andnl $dst, $src1, $src2" %}
10239
10240 ins_encode %{
10241 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
10242 %}
10243 ins_pipe(ialu_reg);
10244 %}
10245
10246 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, rFlagsReg cr) %{
10247 match(Set dst (AndI (SubI imm_zero src) src));
10248 predicate(UseBMI1Instructions);
10249 effect(KILL cr);
10250 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10251
10252 format %{ "blsil $dst, $src" %}
10253
10254 ins_encode %{
10255 __ blsil($dst$$Register, $src$$Register);
10256 %}
10257 ins_pipe(ialu_reg);
10258 %}
10259
10260 instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, rFlagsReg cr) %{
10261 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
10262 predicate(UseBMI1Instructions);
10263 effect(KILL cr);
10264 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10265
10266 ins_cost(125);
10267 format %{ "blsil $dst, $src" %}
10268
10269 ins_encode %{
10270 __ blsil($dst$$Register, $src$$Address);
10271 %}
10272 ins_pipe(ialu_reg_mem);
10273 %}
10274
10275 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
10276 %{
10277 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
10278 predicate(UseBMI1Instructions);
10279 effect(KILL cr);
10280 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
10281
10282 ins_cost(125);
10283 format %{ "blsmskl $dst, $src" %}
10284
10285 ins_encode %{
10286 __ blsmskl($dst$$Register, $src$$Address);
10287 %}
10288 ins_pipe(ialu_reg_mem);
10289 %}
10290
10291 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
10292 %{
10293 match(Set dst (XorI (AddI src minus_1) src));
10294 predicate(UseBMI1Instructions);
10295 effect(KILL cr);
10296 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
10297
10298 format %{ "blsmskl $dst, $src" %}
10299
10300 ins_encode %{
10301 __ blsmskl($dst$$Register, $src$$Register);
10302 %}
10303
10304 ins_pipe(ialu_reg);
10305 %}
10306
10307 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
10308 %{
10309 match(Set dst (AndI (AddI src minus_1) src) );
10310 predicate(UseBMI1Instructions);
10311 effect(KILL cr);
10312 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10313
10314 format %{ "blsrl $dst, $src" %}
10315
10316 ins_encode %{
10317 __ blsrl($dst$$Register, $src$$Register);
10318 %}
10319
10320 ins_pipe(ialu_reg_mem);
10321 %}
10322
10323 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
10324 %{
10325 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
10326 predicate(UseBMI1Instructions);
10327 effect(KILL cr);
10328 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10329
10330 ins_cost(125);
10331 format %{ "blsrl $dst, $src" %}
10332
10333 ins_encode %{
10334 __ blsrl($dst$$Register, $src$$Address);
10335 %}
10336
10337 ins_pipe(ialu_reg);
10338 %}
10339
10340 // Or Instructions
10341 // Or Register with Register
10342 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
10343 %{
10344 predicate(!UseAPX);
10345 match(Set dst (OrI dst src));
10346 effect(KILL cr);
10347 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10348
10349 format %{ "orl $dst, $src\t# int" %}
10350 ins_encode %{
10351 __ orl($dst$$Register, $src$$Register);
10352 %}
10353 ins_pipe(ialu_reg_reg);
10354 %}
10355
10356 // Or Register with Register using New Data Destination (NDD)
10357 instruct orI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
10358 %{
10359 predicate(UseAPX);
10360 match(Set dst (OrI src1 src2));
10361 effect(KILL cr);
10362 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10363
10364 format %{ "eorl $dst, $src1, $src2\t# int ndd" %}
10365 ins_encode %{
10366 __ eorl($dst$$Register, $src1$$Register, $src2$$Register, false);
10367 %}
10368 ins_pipe(ialu_reg_reg);
10369 %}
10370
10371 // Or Register with Immediate
10372 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
10373 %{
10374 predicate(!UseAPX);
10375 match(Set dst (OrI dst src));
10376 effect(KILL cr);
10377 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10378
10379 format %{ "orl $dst, $src\t# int" %}
10380 ins_encode %{
10381 __ orl($dst$$Register, $src$$constant);
10382 %}
10383 ins_pipe(ialu_reg);
10384 %}
10385
10386 instruct orI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
10387 %{
10388 predicate(UseAPX);
10389 match(Set dst (OrI src1 src2));
10390 effect(KILL cr);
10391 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10392
10393 format %{ "eorl $dst, $src1, $src2\t# int ndd" %}
10394 ins_encode %{
10395 __ eorl($dst$$Register, $src1$$Register, $src2$$constant, false);
10396 %}
10397 ins_pipe(ialu_reg);
10398 %}
10399
10400 instruct orI_rReg_imm_rReg_ndd(rRegI dst, immI src1, rRegI src2, rFlagsReg cr)
10401 %{
10402 predicate(UseAPX);
10403 match(Set dst (OrI src1 src2));
10404 effect(KILL cr);
10405 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10406
10407 format %{ "eorl $dst, $src2, $src1\t# int ndd" %}
10408 ins_encode %{
10409 __ eorl($dst$$Register, $src2$$Register, $src1$$constant, false);
10410 %}
10411 ins_pipe(ialu_reg);
10412 %}
10413
10414 instruct orI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
10415 %{
10416 predicate(UseAPX);
10417 match(Set dst (OrI (LoadI src1) src2));
10418 effect(KILL cr);
10419 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10420
10421 format %{ "eorl $dst, $src1, $src2\t# int ndd" %}
10422 ins_encode %{
10423 __ eorl($dst$$Register, $src1$$Address, $src2$$constant, false);
10424 %}
10425 ins_pipe(ialu_reg);
10426 %}
10427
10428 // Or Register with Memory
10429 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
10430 %{
10431 predicate(!UseAPX);
10432 match(Set dst (OrI dst (LoadI src)));
10433 effect(KILL cr);
10434 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10435
10436 ins_cost(150);
10437 format %{ "orl $dst, $src\t# int" %}
10438 ins_encode %{
10439 __ orl($dst$$Register, $src$$Address);
10440 %}
10441 ins_pipe(ialu_reg_mem);
10442 %}
10443
10444 instruct orI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
10445 %{
10446 predicate(UseAPX);
10447 match(Set dst (OrI src1 (LoadI src2)));
10448 effect(KILL cr);
10449 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10450
10451 ins_cost(150);
10452 format %{ "eorl $dst, $src1, $src2\t# int ndd" %}
10453 ins_encode %{
10454 __ eorl($dst$$Register, $src1$$Register, $src2$$Address, false);
10455 %}
10456 ins_pipe(ialu_reg_mem);
10457 %}
10458
10459 // Or Memory with Register
10460 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10461 %{
10462 match(Set dst (StoreB dst (OrI (LoadB dst) src)));
10463 effect(KILL cr);
10464 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10465
10466 ins_cost(150);
10467 format %{ "orb $dst, $src\t# byte" %}
10468 ins_encode %{
10469 __ orb($dst$$Address, $src$$Register);
10470 %}
10471 ins_pipe(ialu_mem_reg);
10472 %}
10473
10474 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10475 %{
10476 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
10477 effect(KILL cr);
10478 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10479
10480 ins_cost(150);
10481 format %{ "orl $dst, $src\t# int" %}
10482 ins_encode %{
10483 __ orl($dst$$Address, $src$$Register);
10484 %}
10485 ins_pipe(ialu_mem_reg);
10486 %}
10487
10488 // Or Memory with Immediate
10489 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
10490 %{
10491 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
10492 effect(KILL cr);
10493 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10494
10495 ins_cost(125);
10496 format %{ "orl $dst, $src\t# int" %}
10497 ins_encode %{
10498 __ orl($dst$$Address, $src$$constant);
10499 %}
10500 ins_pipe(ialu_mem_imm);
10501 %}
10502
10503 // Xor Instructions
10504 // Xor Register with Register
10505 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
10506 %{
10507 predicate(!UseAPX);
10508 match(Set dst (XorI dst src));
10509 effect(KILL cr);
10510 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10511
10512 format %{ "xorl $dst, $src\t# int" %}
10513 ins_encode %{
10514 __ xorl($dst$$Register, $src$$Register);
10515 %}
10516 ins_pipe(ialu_reg_reg);
10517 %}
10518
10519 // Xor Register with Register using New Data Destination (NDD)
10520 instruct xorI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
10521 %{
10522 predicate(UseAPX);
10523 match(Set dst (XorI src1 src2));
10524 effect(KILL cr);
10525 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10526
10527 format %{ "exorl $dst, $src1, $src2\t# int ndd" %}
10528 ins_encode %{
10529 __ exorl($dst$$Register, $src1$$Register, $src2$$Register, false);
10530 %}
10531 ins_pipe(ialu_reg_reg);
10532 %}
10533
10534 // Xor Register with Immediate -1
10535 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm)
10536 %{
10537 predicate(!UseAPX);
10538 match(Set dst (XorI dst imm));
10539
10540 format %{ "notl $dst" %}
10541 ins_encode %{
10542 __ notl($dst$$Register);
10543 %}
10544 ins_pipe(ialu_reg);
10545 %}
10546
10547 instruct xorI_rReg_im1_ndd(rRegI dst, rRegI src, immI_M1 imm)
10548 %{
10549 match(Set dst (XorI src imm));
10550 predicate(UseAPX);
10551
10552 format %{ "enotl $dst, $src" %}
10553 ins_encode %{
10554 __ enotl($dst$$Register, $src$$Register);
10555 %}
10556 ins_pipe(ialu_reg);
10557 %}
10558
10559 // Xor Register with Immediate
10560 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
10561 %{
10562 predicate(!UseAPX);
10563 match(Set dst (XorI dst src));
10564 effect(KILL cr);
10565 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10566
10567 format %{ "xorl $dst, $src\t# int" %}
10568 ins_encode %{
10569 __ xorl($dst$$Register, $src$$constant);
10570 %}
10571 ins_pipe(ialu_reg);
10572 %}
10573
10574 instruct xorI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
10575 %{
10576 predicate(UseAPX);
10577 match(Set dst (XorI src1 src2));
10578 effect(KILL cr);
10579 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10580
10581 format %{ "exorl $dst, $src1, $src2\t# int ndd" %}
10582 ins_encode %{
10583 __ exorl($dst$$Register, $src1$$Register, $src2$$constant, false);
10584 %}
10585 ins_pipe(ialu_reg);
10586 %}
10587
10588 // Xor Memory with Immediate
10589 instruct xorI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
10590 %{
10591 predicate(UseAPX);
10592 match(Set dst (XorI (LoadI src1) src2));
10593 effect(KILL cr);
10594 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10595
10596 format %{ "exorl $dst, $src1, $src2\t# int ndd" %}
10597 ins_encode %{
10598 __ exorl($dst$$Register, $src1$$Address, $src2$$constant, false);
10599 %}
10600 ins_pipe(ialu_reg);
10601 %}
10602
10603 // Xor Register with Memory
10604 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
10605 %{
10606 predicate(!UseAPX);
10607 match(Set dst (XorI dst (LoadI src)));
10608 effect(KILL cr);
10609 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10610
10611 ins_cost(150);
10612 format %{ "xorl $dst, $src\t# int" %}
10613 ins_encode %{
10614 __ xorl($dst$$Register, $src$$Address);
10615 %}
10616 ins_pipe(ialu_reg_mem);
10617 %}
10618
10619 instruct xorI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
10620 %{
10621 predicate(UseAPX);
10622 match(Set dst (XorI src1 (LoadI src2)));
10623 effect(KILL cr);
10624 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10625
10626 ins_cost(150);
10627 format %{ "exorl $dst, $src1, $src2\t# int ndd" %}
10628 ins_encode %{
10629 __ exorl($dst$$Register, $src1$$Register, $src2$$Address, false);
10630 %}
10631 ins_pipe(ialu_reg_mem);
10632 %}
10633
10634 instruct xorI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr)
10635 %{
10636 predicate(UseAPX);
10637 match(Set dst (XorI (LoadI src1) src2));
10638 effect(KILL cr);
10639 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10640
10641 ins_cost(150);
10642 format %{ "exorl $dst, $src1, $src2\t# int ndd" %}
10643 ins_encode %{
10644 __ exorl($dst$$Register, $src1$$Address, $src2$$Register, false);
10645 %}
10646 ins_pipe(ialu_reg_mem);
10647 %}
10648
10649 // Xor Memory with Register
10650 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10651 %{
10652 match(Set dst (StoreB dst (XorI (LoadB dst) src)));
10653 effect(KILL cr);
10654 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10655
10656 ins_cost(150);
10657 format %{ "xorb $dst, $src\t# byte" %}
10658 ins_encode %{
10659 __ xorb($dst$$Address, $src$$Register);
10660 %}
10661 ins_pipe(ialu_mem_reg);
10662 %}
10663
10664 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10665 %{
10666 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
10667 effect(KILL cr);
10668 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10669
10670 ins_cost(150);
10671 format %{ "xorl $dst, $src\t# int" %}
10672 ins_encode %{
10673 __ xorl($dst$$Address, $src$$Register);
10674 %}
10675 ins_pipe(ialu_mem_reg);
10676 %}
10677
10678 // Xor Memory with Immediate
10679 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
10680 %{
10681 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
10682 effect(KILL cr);
10683 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10684
10685 ins_cost(125);
10686 format %{ "xorl $dst, $src\t# int" %}
10687 ins_encode %{
10688 __ xorl($dst$$Address, $src$$constant);
10689 %}
10690 ins_pipe(ialu_mem_imm);
10691 %}
10692
10693
10694 // Long Logical Instructions
10695
10696 // And Instructions
10697 // And Register with Register
10698 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10699 %{
10700 predicate(!UseAPX);
10701 match(Set dst (AndL dst src));
10702 effect(KILL cr);
10703 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10704
10705 format %{ "andq $dst, $src\t# long" %}
10706 ins_encode %{
10707 __ andq($dst$$Register, $src$$Register);
10708 %}
10709 ins_pipe(ialu_reg_reg);
10710 %}
10711
10712 // And Register with Register using New Data Destination (NDD)
10713 instruct andL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
10714 %{
10715 predicate(UseAPX);
10716 match(Set dst (AndL src1 src2));
10717 effect(KILL cr);
10718 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10719
10720 format %{ "eandq $dst, $src1, $src2\t# long ndd" %}
10721 ins_encode %{
10722 __ eandq($dst$$Register, $src1$$Register, $src2$$Register, false);
10723
10724 %}
10725 ins_pipe(ialu_reg_reg);
10726 %}
10727
10728 // And Register with Immediate 255
10729 instruct andL_rReg_imm255(rRegL dst, rRegL src, immL_255 mask)
10730 %{
10731 match(Set dst (AndL src mask));
10732
10733 format %{ "movzbl $dst, $src\t# long & 0xFF" %}
10734 ins_encode %{
10735 // movzbl zeroes out the upper 32-bit and does not need REX.W
10736 __ movzbl($dst$$Register, $src$$Register);
10737 %}
10738 ins_pipe(ialu_reg);
10739 %}
10740
10741 // And Register with Immediate 65535
10742 instruct andL_rReg_imm65535(rRegL dst, rRegL src, immL_65535 mask)
10743 %{
10744 match(Set dst (AndL src mask));
10745
10746 format %{ "movzwl $dst, $src\t# long & 0xFFFF" %}
10747 ins_encode %{
10748 // movzwl zeroes out the upper 32-bit and does not need REX.W
10749 __ movzwl($dst$$Register, $src$$Register);
10750 %}
10751 ins_pipe(ialu_reg);
10752 %}
10753
10754 // And Register with Immediate
10755 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10756 %{
10757 predicate(!UseAPX);
10758 match(Set dst (AndL dst src));
10759 effect(KILL cr);
10760 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10761
10762 format %{ "andq $dst, $src\t# long" %}
10763 ins_encode %{
10764 __ andq($dst$$Register, $src$$constant);
10765 %}
10766 ins_pipe(ialu_reg);
10767 %}
10768
10769 instruct andL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
10770 %{
10771 predicate(UseAPX);
10772 match(Set dst (AndL src1 src2));
10773 effect(KILL cr);
10774 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10775
10776 format %{ "eandq $dst, $src1, $src2\t# long ndd" %}
10777 ins_encode %{
10778 __ eandq($dst$$Register, $src1$$Register, $src2$$constant, false);
10779 %}
10780 ins_pipe(ialu_reg);
10781 %}
10782
10783 instruct andL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
10784 %{
10785 predicate(UseAPX);
10786 match(Set dst (AndL (LoadL src1) src2));
10787 effect(KILL cr);
10788 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10789
10790 format %{ "eandq $dst, $src1, $src2\t# long ndd" %}
10791 ins_encode %{
10792 __ eandq($dst$$Register, $src1$$Address, $src2$$constant, false);
10793 %}
10794 ins_pipe(ialu_reg);
10795 %}
10796
10797 // And Register with Memory
10798 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10799 %{
10800 predicate(!UseAPX);
10801 match(Set dst (AndL dst (LoadL src)));
10802 effect(KILL cr);
10803 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10804
10805 ins_cost(150);
10806 format %{ "andq $dst, $src\t# long" %}
10807 ins_encode %{
10808 __ andq($dst$$Register, $src$$Address);
10809 %}
10810 ins_pipe(ialu_reg_mem);
10811 %}
10812
10813 instruct andL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
10814 %{
10815 predicate(UseAPX);
10816 match(Set dst (AndL src1 (LoadL src2)));
10817 effect(KILL cr);
10818 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10819
10820 ins_cost(150);
10821 format %{ "eandq $dst, $src1, $src2\t# long ndd" %}
10822 ins_encode %{
10823 __ eandq($dst$$Register, $src1$$Register, $src2$$Address, false);
10824 %}
10825 ins_pipe(ialu_reg_mem);
10826 %}
10827
10828 instruct andL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
10829 %{
10830 predicate(UseAPX);
10831 match(Set dst (AndL (LoadL src1) src2));
10832 effect(KILL cr);
10833 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10834
10835 ins_cost(150);
10836 format %{ "eandq $dst, $src1, $src2\t# long ndd" %}
10837 ins_encode %{
10838 __ eandq($dst$$Register, $src1$$Address, $src2$$Register, false);
10839 %}
10840 ins_pipe(ialu_reg_mem);
10841 %}
10842
10843 // And Memory with Register
10844 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10845 %{
10846 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
10847 effect(KILL cr);
10848 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10849
10850 ins_cost(150);
10851 format %{ "andq $dst, $src\t# long" %}
10852 ins_encode %{
10853 __ andq($dst$$Address, $src$$Register);
10854 %}
10855 ins_pipe(ialu_mem_reg);
10856 %}
10857
10858 // And Memory with Immediate
10859 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10860 %{
10861 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
10862 effect(KILL cr);
10863 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10864
10865 ins_cost(125);
10866 format %{ "andq $dst, $src\t# long" %}
10867 ins_encode %{
10868 __ andq($dst$$Address, $src$$constant);
10869 %}
10870 ins_pipe(ialu_mem_imm);
10871 %}
10872
10873 instruct btrL_mem_imm(memory dst, immL_NotPow2 con, rFlagsReg cr)
10874 %{
10875 // con should be a pure 64-bit immediate given that not(con) is a power of 2
10876 // because AND/OR works well enough for 8/32-bit values.
10877 predicate(log2i_graceful(~n->in(3)->in(2)->get_long()) > 30);
10878
10879 match(Set dst (StoreL dst (AndL (LoadL dst) con)));
10880 effect(KILL cr);
10881
10882 ins_cost(125);
10883 format %{ "btrq $dst, log2(not($con))\t# long" %}
10884 ins_encode %{
10885 __ btrq($dst$$Address, log2i_exact((julong)~$con$$constant));
10886 %}
10887 ins_pipe(ialu_mem_imm);
10888 %}
10889
10890 // BMI1 instructions
10891 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
10892 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
10893 predicate(UseBMI1Instructions);
10894 effect(KILL cr);
10895 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10896
10897 ins_cost(125);
10898 format %{ "andnq $dst, $src1, $src2" %}
10899
10900 ins_encode %{
10901 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
10902 %}
10903 ins_pipe(ialu_reg_mem);
10904 %}
10905
10906 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
10907 match(Set dst (AndL (XorL src1 minus_1) src2));
10908 predicate(UseBMI1Instructions);
10909 effect(KILL cr);
10910 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10911
10912 format %{ "andnq $dst, $src1, $src2" %}
10913
10914 ins_encode %{
10915 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
10916 %}
10917 ins_pipe(ialu_reg_mem);
10918 %}
10919
10920 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
10921 match(Set dst (AndL (SubL imm_zero src) src));
10922 predicate(UseBMI1Instructions);
10923 effect(KILL cr);
10924 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10925
10926 format %{ "blsiq $dst, $src" %}
10927
10928 ins_encode %{
10929 __ blsiq($dst$$Register, $src$$Register);
10930 %}
10931 ins_pipe(ialu_reg);
10932 %}
10933
10934 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
10935 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
10936 predicate(UseBMI1Instructions);
10937 effect(KILL cr);
10938 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10939
10940 ins_cost(125);
10941 format %{ "blsiq $dst, $src" %}
10942
10943 ins_encode %{
10944 __ blsiq($dst$$Register, $src$$Address);
10945 %}
10946 ins_pipe(ialu_reg_mem);
10947 %}
10948
10949 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
10950 %{
10951 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
10952 predicate(UseBMI1Instructions);
10953 effect(KILL cr);
10954 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
10955
10956 ins_cost(125);
10957 format %{ "blsmskq $dst, $src" %}
10958
10959 ins_encode %{
10960 __ blsmskq($dst$$Register, $src$$Address);
10961 %}
10962 ins_pipe(ialu_reg_mem);
10963 %}
10964
10965 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
10966 %{
10967 match(Set dst (XorL (AddL src minus_1) src));
10968 predicate(UseBMI1Instructions);
10969 effect(KILL cr);
10970 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
10971
10972 format %{ "blsmskq $dst, $src" %}
10973
10974 ins_encode %{
10975 __ blsmskq($dst$$Register, $src$$Register);
10976 %}
10977
10978 ins_pipe(ialu_reg);
10979 %}
10980
10981 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
10982 %{
10983 match(Set dst (AndL (AddL src minus_1) src) );
10984 predicate(UseBMI1Instructions);
10985 effect(KILL cr);
10986 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10987
10988 format %{ "blsrq $dst, $src" %}
10989
10990 ins_encode %{
10991 __ blsrq($dst$$Register, $src$$Register);
10992 %}
10993
10994 ins_pipe(ialu_reg);
10995 %}
10996
10997 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
10998 %{
10999 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
11000 predicate(UseBMI1Instructions);
11001 effect(KILL cr);
11002 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
11003
11004 ins_cost(125);
11005 format %{ "blsrq $dst, $src" %}
11006
11007 ins_encode %{
11008 __ blsrq($dst$$Register, $src$$Address);
11009 %}
11010
11011 ins_pipe(ialu_reg);
11012 %}
11013
11014 // Or Instructions
11015 // Or Register with Register
11016 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
11017 %{
11018 predicate(!UseAPX);
11019 match(Set dst (OrL dst src));
11020 effect(KILL cr);
11021 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11022
11023 format %{ "orq $dst, $src\t# long" %}
11024 ins_encode %{
11025 __ orq($dst$$Register, $src$$Register);
11026 %}
11027 ins_pipe(ialu_reg_reg);
11028 %}
11029
11030 // Or Register with Register using New Data Destination (NDD)
11031 instruct orL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
11032 %{
11033 predicate(UseAPX);
11034 match(Set dst (OrL src1 src2));
11035 effect(KILL cr);
11036 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11037
11038 format %{ "eorq $dst, $src1, $src2\t# long ndd" %}
11039 ins_encode %{
11040 __ eorq($dst$$Register, $src1$$Register, $src2$$Register, false);
11041
11042 %}
11043 ins_pipe(ialu_reg_reg);
11044 %}
11045
11046 // Use any_RegP to match R15 (TLS register) without spilling.
11047 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
11048 match(Set dst (OrL dst (CastP2X src)));
11049 effect(KILL cr);
11050 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11051
11052 format %{ "orq $dst, $src\t# long" %}
11053 ins_encode %{
11054 __ orq($dst$$Register, $src$$Register);
11055 %}
11056 ins_pipe(ialu_reg_reg);
11057 %}
11058
11059 instruct orL_rReg_castP2X_ndd(rRegL dst, any_RegP src1, any_RegP src2, rFlagsReg cr) %{
11060 match(Set dst (OrL src1 (CastP2X src2)));
11061 effect(KILL cr);
11062 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11063
11064 format %{ "eorq $dst, $src1, $src2\t# long ndd" %}
11065 ins_encode %{
11066 __ eorq($dst$$Register, $src1$$Register, $src2$$Register, false);
11067 %}
11068 ins_pipe(ialu_reg_reg);
11069 %}
11070
11071 // Or Register with Immediate
11072 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
11073 %{
11074 predicate(!UseAPX);
11075 match(Set dst (OrL dst src));
11076 effect(KILL cr);
11077 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11078
11079 format %{ "orq $dst, $src\t# long" %}
11080 ins_encode %{
11081 __ orq($dst$$Register, $src$$constant);
11082 %}
11083 ins_pipe(ialu_reg);
11084 %}
11085
11086 instruct orL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
11087 %{
11088 predicate(UseAPX);
11089 match(Set dst (OrL src1 src2));
11090 effect(KILL cr);
11091 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11092
11093 format %{ "eorq $dst, $src1, $src2\t# long ndd" %}
11094 ins_encode %{
11095 __ eorq($dst$$Register, $src1$$Register, $src2$$constant, false);
11096 %}
11097 ins_pipe(ialu_reg);
11098 %}
11099
11100 instruct orL_rReg_imm_rReg_ndd(rRegL dst, immL32 src1, rRegL src2, rFlagsReg cr)
11101 %{
11102 predicate(UseAPX);
11103 match(Set dst (OrL src1 src2));
11104 effect(KILL cr);
11105 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11106
11107 format %{ "eorq $dst, $src2, $src1\t# long ndd" %}
11108 ins_encode %{
11109 __ eorq($dst$$Register, $src2$$Register, $src1$$constant, false);
11110 %}
11111 ins_pipe(ialu_reg);
11112 %}
11113
11114 // Or Memory with Immediate
11115 instruct orL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
11116 %{
11117 predicate(UseAPX);
11118 match(Set dst (OrL (LoadL src1) src2));
11119 effect(KILL cr);
11120 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11121
11122 format %{ "eorq $dst, $src1, $src2\t# long ndd" %}
11123 ins_encode %{
11124 __ eorq($dst$$Register, $src1$$Address, $src2$$constant, false);
11125 %}
11126 ins_pipe(ialu_reg);
11127 %}
11128
11129 // Or Register with Memory
11130 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
11131 %{
11132 predicate(!UseAPX);
11133 match(Set dst (OrL dst (LoadL src)));
11134 effect(KILL cr);
11135 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11136
11137 ins_cost(150);
11138 format %{ "orq $dst, $src\t# long" %}
11139 ins_encode %{
11140 __ orq($dst$$Register, $src$$Address);
11141 %}
11142 ins_pipe(ialu_reg_mem);
11143 %}
11144
11145 instruct orL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
11146 %{
11147 predicate(UseAPX);
11148 match(Set dst (OrL src1 (LoadL src2)));
11149 effect(KILL cr);
11150 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11151
11152 ins_cost(150);
11153 format %{ "eorq $dst, $src1, $src2\t# long ndd" %}
11154 ins_encode %{
11155 __ eorq($dst$$Register, $src1$$Register, $src2$$Address, false);
11156 %}
11157 ins_pipe(ialu_reg_mem);
11158 %}
11159
11160 // Or Memory with Register
11161 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
11162 %{
11163 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
11164 effect(KILL cr);
11165 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11166
11167 ins_cost(150);
11168 format %{ "orq $dst, $src\t# long" %}
11169 ins_encode %{
11170 __ orq($dst$$Address, $src$$Register);
11171 %}
11172 ins_pipe(ialu_mem_reg);
11173 %}
11174
11175 // Or Memory with Immediate
11176 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
11177 %{
11178 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
11179 effect(KILL cr);
11180 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11181
11182 ins_cost(125);
11183 format %{ "orq $dst, $src\t# long" %}
11184 ins_encode %{
11185 __ orq($dst$$Address, $src$$constant);
11186 %}
11187 ins_pipe(ialu_mem_imm);
11188 %}
11189
11190 instruct btsL_mem_imm(memory dst, immL_Pow2 con, rFlagsReg cr)
11191 %{
11192 // con should be a pure 64-bit power of 2 immediate
11193 // because AND/OR works well enough for 8/32-bit values.
11194 predicate(log2i_graceful(n->in(3)->in(2)->get_long()) > 31);
11195
11196 match(Set dst (StoreL dst (OrL (LoadL dst) con)));
11197 effect(KILL cr);
11198
11199 ins_cost(125);
11200 format %{ "btsq $dst, log2($con)\t# long" %}
11201 ins_encode %{
11202 __ btsq($dst$$Address, log2i_exact((julong)$con$$constant));
11203 %}
11204 ins_pipe(ialu_mem_imm);
11205 %}
11206
11207 // Xor Instructions
11208 // Xor Register with Register
11209 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
11210 %{
11211 predicate(!UseAPX);
11212 match(Set dst (XorL dst src));
11213 effect(KILL cr);
11214 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11215
11216 format %{ "xorq $dst, $src\t# long" %}
11217 ins_encode %{
11218 __ xorq($dst$$Register, $src$$Register);
11219 %}
11220 ins_pipe(ialu_reg_reg);
11221 %}
11222
11223 // Xor Register with Register using New Data Destination (NDD)
11224 instruct xorL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
11225 %{
11226 predicate(UseAPX);
11227 match(Set dst (XorL src1 src2));
11228 effect(KILL cr);
11229 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11230
11231 format %{ "exorq $dst, $src1, $src2\t# long ndd" %}
11232 ins_encode %{
11233 __ exorq($dst$$Register, $src1$$Register, $src2$$Register, false);
11234 %}
11235 ins_pipe(ialu_reg_reg);
11236 %}
11237
11238 // Xor Register with Immediate -1
11239 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm)
11240 %{
11241 predicate(!UseAPX);
11242 match(Set dst (XorL dst imm));
11243
11244 format %{ "notq $dst" %}
11245 ins_encode %{
11246 __ notq($dst$$Register);
11247 %}
11248 ins_pipe(ialu_reg);
11249 %}
11250
11251 instruct xorL_rReg_im1_ndd(rRegL dst,rRegL src, immL_M1 imm)
11252 %{
11253 predicate(UseAPX);
11254 match(Set dst (XorL src imm));
11255
11256 format %{ "enotq $dst, $src" %}
11257 ins_encode %{
11258 __ enotq($dst$$Register, $src$$Register);
11259 %}
11260 ins_pipe(ialu_reg);
11261 %}
11262
11263 // Xor Register with Immediate
11264 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
11265 %{
11266 predicate(!UseAPX);
11267 match(Set dst (XorL dst src));
11268 effect(KILL cr);
11269 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11270
11271 format %{ "xorq $dst, $src\t# long" %}
11272 ins_encode %{
11273 __ xorq($dst$$Register, $src$$constant);
11274 %}
11275 ins_pipe(ialu_reg);
11276 %}
11277
11278 instruct xorL_rReg_rReg_imm(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
11279 %{
11280 predicate(UseAPX);
11281 match(Set dst (XorL src1 src2));
11282 effect(KILL cr);
11283 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11284
11285 format %{ "exorq $dst, $src1, $src2\t# long ndd" %}
11286 ins_encode %{
11287 __ exorq($dst$$Register, $src1$$Register, $src2$$constant, false);
11288 %}
11289 ins_pipe(ialu_reg);
11290 %}
11291
11292 // Xor Memory with Immediate
11293 instruct xorL_rReg_mem_imm(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
11294 %{
11295 predicate(UseAPX);
11296 match(Set dst (XorL (LoadL src1) src2));
11297 effect(KILL cr);
11298 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11299
11300 format %{ "exorq $dst, $src1, $src2\t# long ndd" %}
11301 ins_encode %{
11302 __ exorq($dst$$Register, $src1$$Address, $src2$$constant, false);
11303 %}
11304 ins_pipe(ialu_reg);
11305 %}
11306
11307 // Xor Register with Memory
11308 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
11309 %{
11310 predicate(!UseAPX);
11311 match(Set dst (XorL dst (LoadL src)));
11312 effect(KILL cr);
11313 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11314
11315 ins_cost(150);
11316 format %{ "xorq $dst, $src\t# long" %}
11317 ins_encode %{
11318 __ xorq($dst$$Register, $src$$Address);
11319 %}
11320 ins_pipe(ialu_reg_mem);
11321 %}
11322
11323 instruct xorL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
11324 %{
11325 predicate(UseAPX);
11326 match(Set dst (XorL src1 (LoadL src2)));
11327 effect(KILL cr);
11328 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11329
11330 ins_cost(150);
11331 format %{ "exorq $dst, $src1, $src2\t# long ndd" %}
11332 ins_encode %{
11333 __ exorq($dst$$Register, $src1$$Register, $src2$$Address, false);
11334 %}
11335 ins_pipe(ialu_reg_mem);
11336 %}
11337
11338 instruct xorL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
11339 %{
11340 predicate(UseAPX);
11341 match(Set dst (XorL (LoadL src1) src2));
11342 effect(KILL cr);
11343 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11344
11345 ins_cost(150);
11346 format %{ "exorq $dst, $src1, $src2\t# long ndd" %}
11347 ins_encode %{
11348 __ exorq($dst$$Register, $src1$$Address, $src1$$Register, false);
11349 %}
11350 ins_pipe(ialu_reg_mem);
11351 %}
11352
11353 // Xor Memory with Register
11354 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
11355 %{
11356 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
11357 effect(KILL cr);
11358 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11359
11360 ins_cost(150);
11361 format %{ "xorq $dst, $src\t# long" %}
11362 ins_encode %{
11363 __ xorq($dst$$Address, $src$$Register);
11364 %}
11365 ins_pipe(ialu_mem_reg);
11366 %}
11367
11368 // Xor Memory with Immediate
11369 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
11370 %{
11371 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
11372 effect(KILL cr);
11373 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11374
11375 ins_cost(125);
11376 format %{ "xorq $dst, $src\t# long" %}
11377 ins_encode %{
11378 __ xorq($dst$$Address, $src$$constant);
11379 %}
11380 ins_pipe(ialu_mem_imm);
11381 %}
11382
11383 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
11384 %{
11385 match(Set dst (CmpLTMask p q));
11386 effect(KILL cr);
11387
11388 ins_cost(400);
11389 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
11390 "setcc $dst \t# emits setlt + movzbl or setzul for APX"
11391 "negl $dst" %}
11392 ins_encode %{
11393 __ cmpl($p$$Register, $q$$Register);
11394 __ setcc(Assembler::less, $dst$$Register);
11395 __ negl($dst$$Register);
11396 %}
11397 ins_pipe(pipe_slow);
11398 %}
11399
11400 instruct cmpLTMask0(rRegI dst, immI_0 zero, rFlagsReg cr)
11401 %{
11402 match(Set dst (CmpLTMask dst zero));
11403 effect(KILL cr);
11404
11405 ins_cost(100);
11406 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
11407 ins_encode %{
11408 __ sarl($dst$$Register, 31);
11409 %}
11410 ins_pipe(ialu_reg);
11411 %}
11412
11413 /* Better to save a register than avoid a branch */
11414 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
11415 %{
11416 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
11417 effect(KILL cr);
11418 ins_cost(300);
11419 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
11420 "jge done\n\t"
11421 "addl $p,$y\n"
11422 "done: " %}
11423 ins_encode %{
11424 Register Rp = $p$$Register;
11425 Register Rq = $q$$Register;
11426 Register Ry = $y$$Register;
11427 Label done;
11428 __ subl(Rp, Rq);
11429 __ jccb(Assembler::greaterEqual, done);
11430 __ addl(Rp, Ry);
11431 __ bind(done);
11432 %}
11433 ins_pipe(pipe_cmplt);
11434 %}
11435
11436 /* Better to save a register than avoid a branch */
11437 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
11438 %{
11439 match(Set y (AndI (CmpLTMask p q) y));
11440 effect(KILL cr);
11441
11442 ins_cost(300);
11443
11444 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
11445 "jlt done\n\t"
11446 "xorl $y, $y\n"
11447 "done: " %}
11448 ins_encode %{
11449 Register Rp = $p$$Register;
11450 Register Rq = $q$$Register;
11451 Register Ry = $y$$Register;
11452 Label done;
11453 __ cmpl(Rp, Rq);
11454 __ jccb(Assembler::less, done);
11455 __ xorl(Ry, Ry);
11456 __ bind(done);
11457 %}
11458 ins_pipe(pipe_cmplt);
11459 %}
11460
11461
11462 //---------- FP Instructions------------------------------------------------
11463
11464 // Really expensive, avoid
11465 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
11466 %{
11467 match(Set cr (CmpF src1 src2));
11468
11469 ins_cost(500);
11470 format %{ "ucomiss $src1, $src2\n\t"
11471 "jnp,s exit\n\t"
11472 "pushfq\t# saw NaN, set CF\n\t"
11473 "andq [rsp], #0xffffff2b\n\t"
11474 "popfq\n"
11475 "exit:" %}
11476 ins_encode %{
11477 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
11478 emit_cmpfp_fixup(masm);
11479 %}
11480 ins_pipe(pipe_slow);
11481 %}
11482
11483 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
11484 match(Set cr (CmpF src1 src2));
11485
11486 ins_cost(100);
11487 format %{ "ucomiss $src1, $src2" %}
11488 ins_encode %{
11489 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
11490 %}
11491 ins_pipe(pipe_slow);
11492 %}
11493
11494 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
11495 match(Set cr (CmpF src1 (LoadF src2)));
11496
11497 ins_cost(100);
11498 format %{ "ucomiss $src1, $src2" %}
11499 ins_encode %{
11500 __ ucomiss($src1$$XMMRegister, $src2$$Address);
11501 %}
11502 ins_pipe(pipe_slow);
11503 %}
11504
11505 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
11506 match(Set cr (CmpF src con));
11507 ins_cost(100);
11508 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
11509 ins_encode %{
11510 __ ucomiss($src$$XMMRegister, $constantaddress($con));
11511 %}
11512 ins_pipe(pipe_slow);
11513 %}
11514
11515 // Really expensive, avoid
11516 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
11517 %{
11518 match(Set cr (CmpD src1 src2));
11519
11520 ins_cost(500);
11521 format %{ "ucomisd $src1, $src2\n\t"
11522 "jnp,s exit\n\t"
11523 "pushfq\t# saw NaN, set CF\n\t"
11524 "andq [rsp], #0xffffff2b\n\t"
11525 "popfq\n"
11526 "exit:" %}
11527 ins_encode %{
11528 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
11529 emit_cmpfp_fixup(masm);
11530 %}
11531 ins_pipe(pipe_slow);
11532 %}
11533
11534 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
11535 match(Set cr (CmpD src1 src2));
11536
11537 ins_cost(100);
11538 format %{ "ucomisd $src1, $src2 test" %}
11539 ins_encode %{
11540 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
11541 %}
11542 ins_pipe(pipe_slow);
11543 %}
11544
11545 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
11546 match(Set cr (CmpD src1 (LoadD src2)));
11547
11548 ins_cost(100);
11549 format %{ "ucomisd $src1, $src2" %}
11550 ins_encode %{
11551 __ ucomisd($src1$$XMMRegister, $src2$$Address);
11552 %}
11553 ins_pipe(pipe_slow);
11554 %}
11555
11556 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
11557 match(Set cr (CmpD src con));
11558 ins_cost(100);
11559 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
11560 ins_encode %{
11561 __ ucomisd($src$$XMMRegister, $constantaddress($con));
11562 %}
11563 ins_pipe(pipe_slow);
11564 %}
11565
11566 // Compare into -1,0,1
11567 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
11568 %{
11569 match(Set dst (CmpF3 src1 src2));
11570 effect(KILL cr);
11571
11572 ins_cost(275);
11573 format %{ "ucomiss $src1, $src2\n\t"
11574 "movl $dst, #-1\n\t"
11575 "jp,s done\n\t"
11576 "jb,s done\n\t"
11577 "setne $dst\n\t"
11578 "movzbl $dst, $dst\n"
11579 "done:" %}
11580 ins_encode %{
11581 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
11582 emit_cmpfp3(masm, $dst$$Register);
11583 %}
11584 ins_pipe(pipe_slow);
11585 %}
11586
11587 // Compare into -1,0,1
11588 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
11589 %{
11590 match(Set dst (CmpF3 src1 (LoadF src2)));
11591 effect(KILL cr);
11592
11593 ins_cost(275);
11594 format %{ "ucomiss $src1, $src2\n\t"
11595 "movl $dst, #-1\n\t"
11596 "jp,s done\n\t"
11597 "jb,s done\n\t"
11598 "setne $dst\n\t"
11599 "movzbl $dst, $dst\n"
11600 "done:" %}
11601 ins_encode %{
11602 __ ucomiss($src1$$XMMRegister, $src2$$Address);
11603 emit_cmpfp3(masm, $dst$$Register);
11604 %}
11605 ins_pipe(pipe_slow);
11606 %}
11607
11608 // Compare into -1,0,1
11609 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
11610 match(Set dst (CmpF3 src con));
11611 effect(KILL cr);
11612
11613 ins_cost(275);
11614 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
11615 "movl $dst, #-1\n\t"
11616 "jp,s done\n\t"
11617 "jb,s done\n\t"
11618 "setne $dst\n\t"
11619 "movzbl $dst, $dst\n"
11620 "done:" %}
11621 ins_encode %{
11622 __ ucomiss($src$$XMMRegister, $constantaddress($con));
11623 emit_cmpfp3(masm, $dst$$Register);
11624 %}
11625 ins_pipe(pipe_slow);
11626 %}
11627
11628 // Compare into -1,0,1
11629 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
11630 %{
11631 match(Set dst (CmpD3 src1 src2));
11632 effect(KILL cr);
11633
11634 ins_cost(275);
11635 format %{ "ucomisd $src1, $src2\n\t"
11636 "movl $dst, #-1\n\t"
11637 "jp,s done\n\t"
11638 "jb,s done\n\t"
11639 "setne $dst\n\t"
11640 "movzbl $dst, $dst\n"
11641 "done:" %}
11642 ins_encode %{
11643 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
11644 emit_cmpfp3(masm, $dst$$Register);
11645 %}
11646 ins_pipe(pipe_slow);
11647 %}
11648
11649 // Compare into -1,0,1
11650 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
11651 %{
11652 match(Set dst (CmpD3 src1 (LoadD src2)));
11653 effect(KILL cr);
11654
11655 ins_cost(275);
11656 format %{ "ucomisd $src1, $src2\n\t"
11657 "movl $dst, #-1\n\t"
11658 "jp,s done\n\t"
11659 "jb,s done\n\t"
11660 "setne $dst\n\t"
11661 "movzbl $dst, $dst\n"
11662 "done:" %}
11663 ins_encode %{
11664 __ ucomisd($src1$$XMMRegister, $src2$$Address);
11665 emit_cmpfp3(masm, $dst$$Register);
11666 %}
11667 ins_pipe(pipe_slow);
11668 %}
11669
11670 // Compare into -1,0,1
11671 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
11672 match(Set dst (CmpD3 src con));
11673 effect(KILL cr);
11674
11675 ins_cost(275);
11676 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
11677 "movl $dst, #-1\n\t"
11678 "jp,s done\n\t"
11679 "jb,s done\n\t"
11680 "setne $dst\n\t"
11681 "movzbl $dst, $dst\n"
11682 "done:" %}
11683 ins_encode %{
11684 __ ucomisd($src$$XMMRegister, $constantaddress($con));
11685 emit_cmpfp3(masm, $dst$$Register);
11686 %}
11687 ins_pipe(pipe_slow);
11688 %}
11689
11690 //----------Arithmetic Conversion Instructions---------------------------------
11691
11692 instruct convF2D_reg_reg(regD dst, regF src)
11693 %{
11694 match(Set dst (ConvF2D src));
11695
11696 format %{ "cvtss2sd $dst, $src" %}
11697 ins_encode %{
11698 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
11699 %}
11700 ins_pipe(pipe_slow); // XXX
11701 %}
11702
11703 instruct convF2D_reg_mem(regD dst, memory src)
11704 %{
11705 predicate(UseAVX == 0);
11706 match(Set dst (ConvF2D (LoadF src)));
11707
11708 format %{ "cvtss2sd $dst, $src" %}
11709 ins_encode %{
11710 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
11711 %}
11712 ins_pipe(pipe_slow); // XXX
11713 %}
11714
11715 instruct convD2F_reg_reg(regF dst, regD src)
11716 %{
11717 match(Set dst (ConvD2F src));
11718
11719 format %{ "cvtsd2ss $dst, $src" %}
11720 ins_encode %{
11721 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
11722 %}
11723 ins_pipe(pipe_slow); // XXX
11724 %}
11725
11726 instruct convD2F_reg_mem(regF dst, memory src)
11727 %{
11728 predicate(UseAVX == 0);
11729 match(Set dst (ConvD2F (LoadD src)));
11730
11731 format %{ "cvtsd2ss $dst, $src" %}
11732 ins_encode %{
11733 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
11734 %}
11735 ins_pipe(pipe_slow); // XXX
11736 %}
11737
11738 // XXX do mem variants
11739 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
11740 %{
11741 match(Set dst (ConvF2I src));
11742 effect(KILL cr);
11743 format %{ "convert_f2i $dst, $src" %}
11744 ins_encode %{
11745 __ convertF2I(T_INT, T_FLOAT, $dst$$Register, $src$$XMMRegister);
11746 %}
11747 ins_pipe(pipe_slow);
11748 %}
11749
11750 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
11751 %{
11752 match(Set dst (ConvF2L src));
11753 effect(KILL cr);
11754 format %{ "convert_f2l $dst, $src"%}
11755 ins_encode %{
11756 __ convertF2I(T_LONG, T_FLOAT, $dst$$Register, $src$$XMMRegister);
11757 %}
11758 ins_pipe(pipe_slow);
11759 %}
11760
11761 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
11762 %{
11763 match(Set dst (ConvD2I src));
11764 effect(KILL cr);
11765 format %{ "convert_d2i $dst, $src"%}
11766 ins_encode %{
11767 __ convertF2I(T_INT, T_DOUBLE, $dst$$Register, $src$$XMMRegister);
11768 %}
11769 ins_pipe(pipe_slow);
11770 %}
11771
11772 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
11773 %{
11774 match(Set dst (ConvD2L src));
11775 effect(KILL cr);
11776 format %{ "convert_d2l $dst, $src"%}
11777 ins_encode %{
11778 __ convertF2I(T_LONG, T_DOUBLE, $dst$$Register, $src$$XMMRegister);
11779 %}
11780 ins_pipe(pipe_slow);
11781 %}
11782
11783 instruct round_double_reg(rRegL dst, regD src, rRegL rtmp, rcx_RegL rcx, rFlagsReg cr)
11784 %{
11785 match(Set dst (RoundD src));
11786 effect(TEMP dst, TEMP rtmp, TEMP rcx, KILL cr);
11787 format %{ "round_double $dst,$src \t! using $rtmp and $rcx as TEMP"%}
11788 ins_encode %{
11789 __ round_double($dst$$Register, $src$$XMMRegister, $rtmp$$Register, $rcx$$Register);
11790 %}
11791 ins_pipe(pipe_slow);
11792 %}
11793
11794 instruct round_float_reg(rRegI dst, regF src, rRegL rtmp, rcx_RegL rcx, rFlagsReg cr)
11795 %{
11796 match(Set dst (RoundF src));
11797 effect(TEMP dst, TEMP rtmp, TEMP rcx, KILL cr);
11798 format %{ "round_float $dst,$src" %}
11799 ins_encode %{
11800 __ round_float($dst$$Register, $src$$XMMRegister, $rtmp$$Register, $rcx$$Register);
11801 %}
11802 ins_pipe(pipe_slow);
11803 %}
11804
11805 instruct convI2F_reg_reg(vlRegF dst, rRegI src)
11806 %{
11807 predicate(!UseXmmI2F);
11808 match(Set dst (ConvI2F src));
11809
11810 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
11811 ins_encode %{
11812 if (UseAVX > 0) {
11813 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11814 }
11815 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11816 %}
11817 ins_pipe(pipe_slow); // XXX
11818 %}
11819
11820 instruct convI2F_reg_mem(regF dst, memory src)
11821 %{
11822 predicate(UseAVX == 0);
11823 match(Set dst (ConvI2F (LoadI src)));
11824
11825 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
11826 ins_encode %{
11827 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
11828 %}
11829 ins_pipe(pipe_slow); // XXX
11830 %}
11831
11832 instruct convI2D_reg_reg(vlRegD dst, rRegI src)
11833 %{
11834 predicate(!UseXmmI2D);
11835 match(Set dst (ConvI2D src));
11836
11837 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
11838 ins_encode %{
11839 if (UseAVX > 0) {
11840 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11841 }
11842 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11843 %}
11844 ins_pipe(pipe_slow); // XXX
11845 %}
11846
11847 instruct convI2D_reg_mem(regD dst, memory src)
11848 %{
11849 predicate(UseAVX == 0);
11850 match(Set dst (ConvI2D (LoadI src)));
11851
11852 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
11853 ins_encode %{
11854 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
11855 %}
11856 ins_pipe(pipe_slow); // XXX
11857 %}
11858
11859 instruct convXI2F_reg(regF dst, rRegI src)
11860 %{
11861 predicate(UseXmmI2F);
11862 match(Set dst (ConvI2F src));
11863
11864 format %{ "movdl $dst, $src\n\t"
11865 "cvtdq2psl $dst, $dst\t# i2f" %}
11866 ins_encode %{
11867 __ movdl($dst$$XMMRegister, $src$$Register);
11868 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11869 %}
11870 ins_pipe(pipe_slow); // XXX
11871 %}
11872
11873 instruct convXI2D_reg(regD dst, rRegI src)
11874 %{
11875 predicate(UseXmmI2D);
11876 match(Set dst (ConvI2D src));
11877
11878 format %{ "movdl $dst, $src\n\t"
11879 "cvtdq2pdl $dst, $dst\t# i2d" %}
11880 ins_encode %{
11881 __ movdl($dst$$XMMRegister, $src$$Register);
11882 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11883 %}
11884 ins_pipe(pipe_slow); // XXX
11885 %}
11886
11887 instruct convL2F_reg_reg(vlRegF dst, rRegL src)
11888 %{
11889 match(Set dst (ConvL2F src));
11890
11891 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
11892 ins_encode %{
11893 if (UseAVX > 0) {
11894 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11895 }
11896 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
11897 %}
11898 ins_pipe(pipe_slow); // XXX
11899 %}
11900
11901 instruct convL2F_reg_mem(regF dst, memory src)
11902 %{
11903 predicate(UseAVX == 0);
11904 match(Set dst (ConvL2F (LoadL src)));
11905
11906 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
11907 ins_encode %{
11908 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
11909 %}
11910 ins_pipe(pipe_slow); // XXX
11911 %}
11912
11913 instruct convL2D_reg_reg(vlRegD dst, rRegL src)
11914 %{
11915 match(Set dst (ConvL2D src));
11916
11917 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
11918 ins_encode %{
11919 if (UseAVX > 0) {
11920 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11921 }
11922 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
11923 %}
11924 ins_pipe(pipe_slow); // XXX
11925 %}
11926
11927 instruct convL2D_reg_mem(regD dst, memory src)
11928 %{
11929 predicate(UseAVX == 0);
11930 match(Set dst (ConvL2D (LoadL src)));
11931
11932 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
11933 ins_encode %{
11934 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
11935 %}
11936 ins_pipe(pipe_slow); // XXX
11937 %}
11938
11939 instruct convI2L_reg_reg(rRegL dst, rRegI src)
11940 %{
11941 match(Set dst (ConvI2L src));
11942
11943 ins_cost(125);
11944 format %{ "movslq $dst, $src\t# i2l" %}
11945 ins_encode %{
11946 __ movslq($dst$$Register, $src$$Register);
11947 %}
11948 ins_pipe(ialu_reg_reg);
11949 %}
11950
11951 // Zero-extend convert int to long
11952 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
11953 %{
11954 match(Set dst (AndL (ConvI2L src) mask));
11955
11956 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
11957 ins_encode %{
11958 if ($dst$$reg != $src$$reg) {
11959 __ movl($dst$$Register, $src$$Register);
11960 }
11961 %}
11962 ins_pipe(ialu_reg_reg);
11963 %}
11964
11965 // Zero-extend convert int to long
11966 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
11967 %{
11968 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
11969
11970 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
11971 ins_encode %{
11972 __ movl($dst$$Register, $src$$Address);
11973 %}
11974 ins_pipe(ialu_reg_mem);
11975 %}
11976
11977 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
11978 %{
11979 match(Set dst (AndL src mask));
11980
11981 format %{ "movl $dst, $src\t# zero-extend long" %}
11982 ins_encode %{
11983 __ movl($dst$$Register, $src$$Register);
11984 %}
11985 ins_pipe(ialu_reg_reg);
11986 %}
11987
11988 instruct convL2I_reg_reg(rRegI dst, rRegL src)
11989 %{
11990 match(Set dst (ConvL2I src));
11991
11992 format %{ "movl $dst, $src\t# l2i" %}
11993 ins_encode %{
11994 __ movl($dst$$Register, $src$$Register);
11995 %}
11996 ins_pipe(ialu_reg_reg);
11997 %}
11998
11999
12000 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
12001 match(Set dst (MoveF2I src));
12002 effect(DEF dst, USE src);
12003
12004 ins_cost(125);
12005 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
12006 ins_encode %{
12007 __ movl($dst$$Register, Address(rsp, $src$$disp));
12008 %}
12009 ins_pipe(ialu_reg_mem);
12010 %}
12011
12012 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
12013 match(Set dst (MoveI2F src));
12014 effect(DEF dst, USE src);
12015
12016 ins_cost(125);
12017 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
12018 ins_encode %{
12019 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
12020 %}
12021 ins_pipe(pipe_slow);
12022 %}
12023
12024 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
12025 match(Set dst (MoveD2L src));
12026 effect(DEF dst, USE src);
12027
12028 ins_cost(125);
12029 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
12030 ins_encode %{
12031 __ movq($dst$$Register, Address(rsp, $src$$disp));
12032 %}
12033 ins_pipe(ialu_reg_mem);
12034 %}
12035
12036 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
12037 predicate(!UseXmmLoadAndClearUpper);
12038 match(Set dst (MoveL2D src));
12039 effect(DEF dst, USE src);
12040
12041 ins_cost(125);
12042 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
12043 ins_encode %{
12044 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
12045 %}
12046 ins_pipe(pipe_slow);
12047 %}
12048
12049 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
12050 predicate(UseXmmLoadAndClearUpper);
12051 match(Set dst (MoveL2D src));
12052 effect(DEF dst, USE src);
12053
12054 ins_cost(125);
12055 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
12056 ins_encode %{
12057 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
12058 %}
12059 ins_pipe(pipe_slow);
12060 %}
12061
12062
12063 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
12064 match(Set dst (MoveF2I src));
12065 effect(DEF dst, USE src);
12066
12067 ins_cost(95); // XXX
12068 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
12069 ins_encode %{
12070 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
12071 %}
12072 ins_pipe(pipe_slow);
12073 %}
12074
12075 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
12076 match(Set dst (MoveI2F src));
12077 effect(DEF dst, USE src);
12078
12079 ins_cost(100);
12080 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
12081 ins_encode %{
12082 __ movl(Address(rsp, $dst$$disp), $src$$Register);
12083 %}
12084 ins_pipe( ialu_mem_reg );
12085 %}
12086
12087 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
12088 match(Set dst (MoveD2L src));
12089 effect(DEF dst, USE src);
12090
12091 ins_cost(95); // XXX
12092 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
12093 ins_encode %{
12094 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
12095 %}
12096 ins_pipe(pipe_slow);
12097 %}
12098
12099 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
12100 match(Set dst (MoveL2D src));
12101 effect(DEF dst, USE src);
12102
12103 ins_cost(100);
12104 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
12105 ins_encode %{
12106 __ movq(Address(rsp, $dst$$disp), $src$$Register);
12107 %}
12108 ins_pipe(ialu_mem_reg);
12109 %}
12110
12111 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
12112 match(Set dst (MoveF2I src));
12113 effect(DEF dst, USE src);
12114 ins_cost(85);
12115 format %{ "movd $dst,$src\t# MoveF2I" %}
12116 ins_encode %{
12117 __ movdl($dst$$Register, $src$$XMMRegister);
12118 %}
12119 ins_pipe( pipe_slow );
12120 %}
12121
12122 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
12123 match(Set dst (MoveD2L src));
12124 effect(DEF dst, USE src);
12125 ins_cost(85);
12126 format %{ "movd $dst,$src\t# MoveD2L" %}
12127 ins_encode %{
12128 __ movdq($dst$$Register, $src$$XMMRegister);
12129 %}
12130 ins_pipe( pipe_slow );
12131 %}
12132
12133 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
12134 match(Set dst (MoveI2F src));
12135 effect(DEF dst, USE src);
12136 ins_cost(100);
12137 format %{ "movd $dst,$src\t# MoveI2F" %}
12138 ins_encode %{
12139 __ movdl($dst$$XMMRegister, $src$$Register);
12140 %}
12141 ins_pipe( pipe_slow );
12142 %}
12143
12144 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
12145 match(Set dst (MoveL2D src));
12146 effect(DEF dst, USE src);
12147 ins_cost(100);
12148 format %{ "movd $dst,$src\t# MoveL2D" %}
12149 ins_encode %{
12150 __ movdq($dst$$XMMRegister, $src$$Register);
12151 %}
12152 ins_pipe( pipe_slow );
12153 %}
12154
12155 // Fast clearing of an array
12156 // Small non-constant lenght ClearArray for non-AVX512 targets.
12157 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
12158 Universe dummy, rFlagsReg cr)
12159 %{
12160 predicate(!((ClearArrayNode*)n)->is_large() && (UseAVX <= 2));
12161 match(Set dummy (ClearArray cnt base));
12162 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
12163
12164 format %{ $$template
12165 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12166 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
12167 $$emit$$"jg LARGE\n\t"
12168 $$emit$$"dec rcx\n\t"
12169 $$emit$$"js DONE\t# Zero length\n\t"
12170 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
12171 $$emit$$"dec rcx\n\t"
12172 $$emit$$"jge LOOP\n\t"
12173 $$emit$$"jmp DONE\n\t"
12174 $$emit$$"# LARGE:\n\t"
12175 if (UseFastStosb) {
12176 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
12177 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
12178 } else if (UseXMMForObjInit) {
12179 $$emit$$"mov rdi,rax\n\t"
12180 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
12181 $$emit$$"jmpq L_zero_64_bytes\n\t"
12182 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
12183 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12184 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
12185 $$emit$$"add 0x40,rax\n\t"
12186 $$emit$$"# L_zero_64_bytes:\n\t"
12187 $$emit$$"sub 0x8,rcx\n\t"
12188 $$emit$$"jge L_loop\n\t"
12189 $$emit$$"add 0x4,rcx\n\t"
12190 $$emit$$"jl L_tail\n\t"
12191 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12192 $$emit$$"add 0x20,rax\n\t"
12193 $$emit$$"sub 0x4,rcx\n\t"
12194 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
12195 $$emit$$"add 0x4,rcx\n\t"
12196 $$emit$$"jle L_end\n\t"
12197 $$emit$$"dec rcx\n\t"
12198 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
12199 $$emit$$"vmovq xmm0,(rax)\n\t"
12200 $$emit$$"add 0x8,rax\n\t"
12201 $$emit$$"dec rcx\n\t"
12202 $$emit$$"jge L_sloop\n\t"
12203 $$emit$$"# L_end:\n\t"
12204 } else {
12205 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
12206 }
12207 $$emit$$"# DONE"
12208 %}
12209 ins_encode %{
12210 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
12211 $tmp$$XMMRegister, false, knoreg);
12212 %}
12213 ins_pipe(pipe_slow);
12214 %}
12215
12216 // Small non-constant length ClearArray for AVX512 targets.
12217 instruct rep_stos_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegI zero,
12218 Universe dummy, rFlagsReg cr)
12219 %{
12220 predicate(!((ClearArrayNode*)n)->is_large() && (UseAVX > 2));
12221 match(Set dummy (ClearArray cnt base));
12222 ins_cost(125);
12223 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, KILL zero, KILL cr);
12224
12225 format %{ $$template
12226 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12227 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
12228 $$emit$$"jg LARGE\n\t"
12229 $$emit$$"dec rcx\n\t"
12230 $$emit$$"js DONE\t# Zero length\n\t"
12231 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
12232 $$emit$$"dec rcx\n\t"
12233 $$emit$$"jge LOOP\n\t"
12234 $$emit$$"jmp DONE\n\t"
12235 $$emit$$"# LARGE:\n\t"
12236 if (UseFastStosb) {
12237 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
12238 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
12239 } else if (UseXMMForObjInit) {
12240 $$emit$$"mov rdi,rax\n\t"
12241 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
12242 $$emit$$"jmpq L_zero_64_bytes\n\t"
12243 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
12244 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12245 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
12246 $$emit$$"add 0x40,rax\n\t"
12247 $$emit$$"# L_zero_64_bytes:\n\t"
12248 $$emit$$"sub 0x8,rcx\n\t"
12249 $$emit$$"jge L_loop\n\t"
12250 $$emit$$"add 0x4,rcx\n\t"
12251 $$emit$$"jl L_tail\n\t"
12252 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12253 $$emit$$"add 0x20,rax\n\t"
12254 $$emit$$"sub 0x4,rcx\n\t"
12255 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
12256 $$emit$$"add 0x4,rcx\n\t"
12257 $$emit$$"jle L_end\n\t"
12258 $$emit$$"dec rcx\n\t"
12259 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
12260 $$emit$$"vmovq xmm0,(rax)\n\t"
12261 $$emit$$"add 0x8,rax\n\t"
12262 $$emit$$"dec rcx\n\t"
12263 $$emit$$"jge L_sloop\n\t"
12264 $$emit$$"# L_end:\n\t"
12265 } else {
12266 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
12267 }
12268 $$emit$$"# DONE"
12269 %}
12270 ins_encode %{
12271 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
12272 $tmp$$XMMRegister, false, $ktmp$$KRegister);
12273 %}
12274 ins_pipe(pipe_slow);
12275 %}
12276
12277 // Large non-constant length ClearArray for non-AVX512 targets.
12278 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
12279 Universe dummy, rFlagsReg cr)
12280 %{
12281 predicate((UseAVX <=2) && ((ClearArrayNode*)n)->is_large());
12282 match(Set dummy (ClearArray cnt base));
12283 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
12284
12285 format %{ $$template
12286 if (UseFastStosb) {
12287 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12288 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
12289 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
12290 } else if (UseXMMForObjInit) {
12291 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
12292 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
12293 $$emit$$"jmpq L_zero_64_bytes\n\t"
12294 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
12295 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12296 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
12297 $$emit$$"add 0x40,rax\n\t"
12298 $$emit$$"# L_zero_64_bytes:\n\t"
12299 $$emit$$"sub 0x8,rcx\n\t"
12300 $$emit$$"jge L_loop\n\t"
12301 $$emit$$"add 0x4,rcx\n\t"
12302 $$emit$$"jl L_tail\n\t"
12303 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12304 $$emit$$"add 0x20,rax\n\t"
12305 $$emit$$"sub 0x4,rcx\n\t"
12306 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
12307 $$emit$$"add 0x4,rcx\n\t"
12308 $$emit$$"jle L_end\n\t"
12309 $$emit$$"dec rcx\n\t"
12310 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
12311 $$emit$$"vmovq xmm0,(rax)\n\t"
12312 $$emit$$"add 0x8,rax\n\t"
12313 $$emit$$"dec rcx\n\t"
12314 $$emit$$"jge L_sloop\n\t"
12315 $$emit$$"# L_end:\n\t"
12316 } else {
12317 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12318 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
12319 }
12320 %}
12321 ins_encode %{
12322 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
12323 $tmp$$XMMRegister, true, knoreg);
12324 %}
12325 ins_pipe(pipe_slow);
12326 %}
12327
12328 // Large non-constant length ClearArray for AVX512 targets.
12329 instruct rep_stos_large_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegI zero,
12330 Universe dummy, rFlagsReg cr)
12331 %{
12332 predicate((UseAVX > 2) && ((ClearArrayNode*)n)->is_large());
12333 match(Set dummy (ClearArray cnt base));
12334 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, KILL zero, KILL cr);
12335
12336 format %{ $$template
12337 if (UseFastStosb) {
12338 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12339 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
12340 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
12341 } else if (UseXMMForObjInit) {
12342 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
12343 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
12344 $$emit$$"jmpq L_zero_64_bytes\n\t"
12345 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
12346 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12347 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
12348 $$emit$$"add 0x40,rax\n\t"
12349 $$emit$$"# L_zero_64_bytes:\n\t"
12350 $$emit$$"sub 0x8,rcx\n\t"
12351 $$emit$$"jge L_loop\n\t"
12352 $$emit$$"add 0x4,rcx\n\t"
12353 $$emit$$"jl L_tail\n\t"
12354 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12355 $$emit$$"add 0x20,rax\n\t"
12356 $$emit$$"sub 0x4,rcx\n\t"
12357 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
12358 $$emit$$"add 0x4,rcx\n\t"
12359 $$emit$$"jle L_end\n\t"
12360 $$emit$$"dec rcx\n\t"
12361 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
12362 $$emit$$"vmovq xmm0,(rax)\n\t"
12363 $$emit$$"add 0x8,rax\n\t"
12364 $$emit$$"dec rcx\n\t"
12365 $$emit$$"jge L_sloop\n\t"
12366 $$emit$$"# L_end:\n\t"
12367 } else {
12368 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12369 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
12370 }
12371 %}
12372 ins_encode %{
12373 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
12374 $tmp$$XMMRegister, true, $ktmp$$KRegister);
12375 %}
12376 ins_pipe(pipe_slow);
12377 %}
12378
12379 // Small constant length ClearArray for AVX512 targets.
12380 instruct rep_stos_im(immL cnt, rRegP base, regD tmp, rRegI zero, kReg ktmp, Universe dummy, rFlagsReg cr)
12381 %{
12382 predicate(!((ClearArrayNode*)n)->is_large() && (MaxVectorSize >= 32) && VM_Version::supports_avx512vl());
12383 match(Set dummy (ClearArray cnt base));
12384 ins_cost(100);
12385 effect(TEMP tmp, TEMP zero, TEMP ktmp, KILL cr);
12386 format %{ "clear_mem_imm $base , $cnt \n\t" %}
12387 ins_encode %{
12388 __ clear_mem($base$$Register, $cnt$$constant, $zero$$Register, $tmp$$XMMRegister, $ktmp$$KRegister);
12389 %}
12390 ins_pipe(pipe_slow);
12391 %}
12392
12393 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12394 rax_RegI result, legRegD tmp1, rFlagsReg cr)
12395 %{
12396 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
12397 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12398 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12399
12400 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12401 ins_encode %{
12402 __ string_compare($str1$$Register, $str2$$Register,
12403 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12404 $tmp1$$XMMRegister, StrIntrinsicNode::LL, knoreg);
12405 %}
12406 ins_pipe( pipe_slow );
12407 %}
12408
12409 instruct string_compareL_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12410 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
12411 %{
12412 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
12413 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12414 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12415
12416 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12417 ins_encode %{
12418 __ string_compare($str1$$Register, $str2$$Register,
12419 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12420 $tmp1$$XMMRegister, StrIntrinsicNode::LL, $ktmp$$KRegister);
12421 %}
12422 ins_pipe( pipe_slow );
12423 %}
12424
12425 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12426 rax_RegI result, legRegD tmp1, rFlagsReg cr)
12427 %{
12428 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
12429 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12430 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12431
12432 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12433 ins_encode %{
12434 __ string_compare($str1$$Register, $str2$$Register,
12435 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12436 $tmp1$$XMMRegister, StrIntrinsicNode::UU, knoreg);
12437 %}
12438 ins_pipe( pipe_slow );
12439 %}
12440
12441 instruct string_compareU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12442 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
12443 %{
12444 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
12445 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12446 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12447
12448 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12449 ins_encode %{
12450 __ string_compare($str1$$Register, $str2$$Register,
12451 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12452 $tmp1$$XMMRegister, StrIntrinsicNode::UU, $ktmp$$KRegister);
12453 %}
12454 ins_pipe( pipe_slow );
12455 %}
12456
12457 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12458 rax_RegI result, legRegD tmp1, rFlagsReg cr)
12459 %{
12460 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
12461 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12462 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12463
12464 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12465 ins_encode %{
12466 __ string_compare($str1$$Register, $str2$$Register,
12467 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12468 $tmp1$$XMMRegister, StrIntrinsicNode::LU, knoreg);
12469 %}
12470 ins_pipe( pipe_slow );
12471 %}
12472
12473 instruct string_compareLU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12474 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
12475 %{
12476 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
12477 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12478 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12479
12480 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12481 ins_encode %{
12482 __ string_compare($str1$$Register, $str2$$Register,
12483 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12484 $tmp1$$XMMRegister, StrIntrinsicNode::LU, $ktmp$$KRegister);
12485 %}
12486 ins_pipe( pipe_slow );
12487 %}
12488
12489 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
12490 rax_RegI result, legRegD tmp1, rFlagsReg cr)
12491 %{
12492 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
12493 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12494 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12495
12496 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12497 ins_encode %{
12498 __ string_compare($str2$$Register, $str1$$Register,
12499 $cnt2$$Register, $cnt1$$Register, $result$$Register,
12500 $tmp1$$XMMRegister, StrIntrinsicNode::UL, knoreg);
12501 %}
12502 ins_pipe( pipe_slow );
12503 %}
12504
12505 instruct string_compareUL_evex(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
12506 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
12507 %{
12508 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
12509 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12510 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12511
12512 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12513 ins_encode %{
12514 __ string_compare($str2$$Register, $str1$$Register,
12515 $cnt2$$Register, $cnt1$$Register, $result$$Register,
12516 $tmp1$$XMMRegister, StrIntrinsicNode::UL, $ktmp$$KRegister);
12517 %}
12518 ins_pipe( pipe_slow );
12519 %}
12520
12521 // fast search of substring with known size.
12522 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
12523 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
12524 %{
12525 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
12526 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12527 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12528
12529 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
12530 ins_encode %{
12531 int icnt2 = (int)$int_cnt2$$constant;
12532 if (icnt2 >= 16) {
12533 // IndexOf for constant substrings with size >= 16 elements
12534 // which don't need to be loaded through stack.
12535 __ string_indexofC8($str1$$Register, $str2$$Register,
12536 $cnt1$$Register, $cnt2$$Register,
12537 icnt2, $result$$Register,
12538 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
12539 } else {
12540 // Small strings are loaded through stack if they cross page boundary.
12541 __ string_indexof($str1$$Register, $str2$$Register,
12542 $cnt1$$Register, $cnt2$$Register,
12543 icnt2, $result$$Register,
12544 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
12545 }
12546 %}
12547 ins_pipe( pipe_slow );
12548 %}
12549
12550 // fast search of substring with known size.
12551 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
12552 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
12553 %{
12554 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
12555 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12556 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12557
12558 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
12559 ins_encode %{
12560 int icnt2 = (int)$int_cnt2$$constant;
12561 if (icnt2 >= 8) {
12562 // IndexOf for constant substrings with size >= 8 elements
12563 // which don't need to be loaded through stack.
12564 __ string_indexofC8($str1$$Register, $str2$$Register,
12565 $cnt1$$Register, $cnt2$$Register,
12566 icnt2, $result$$Register,
12567 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
12568 } else {
12569 // Small strings are loaded through stack if they cross page boundary.
12570 __ string_indexof($str1$$Register, $str2$$Register,
12571 $cnt1$$Register, $cnt2$$Register,
12572 icnt2, $result$$Register,
12573 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
12574 }
12575 %}
12576 ins_pipe( pipe_slow );
12577 %}
12578
12579 // fast search of substring with known size.
12580 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
12581 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
12582 %{
12583 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
12584 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12585 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12586
12587 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
12588 ins_encode %{
12589 int icnt2 = (int)$int_cnt2$$constant;
12590 if (icnt2 >= 8) {
12591 // IndexOf for constant substrings with size >= 8 elements
12592 // which don't need to be loaded through stack.
12593 __ string_indexofC8($str1$$Register, $str2$$Register,
12594 $cnt1$$Register, $cnt2$$Register,
12595 icnt2, $result$$Register,
12596 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
12597 } else {
12598 // Small strings are loaded through stack if they cross page boundary.
12599 __ string_indexof($str1$$Register, $str2$$Register,
12600 $cnt1$$Register, $cnt2$$Register,
12601 icnt2, $result$$Register,
12602 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
12603 }
12604 %}
12605 ins_pipe( pipe_slow );
12606 %}
12607
12608 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
12609 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
12610 %{
12611 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
12612 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12613 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12614
12615 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
12616 ins_encode %{
12617 __ string_indexof($str1$$Register, $str2$$Register,
12618 $cnt1$$Register, $cnt2$$Register,
12619 (-1), $result$$Register,
12620 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
12621 %}
12622 ins_pipe( pipe_slow );
12623 %}
12624
12625 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
12626 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
12627 %{
12628 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
12629 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12630 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12631
12632 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
12633 ins_encode %{
12634 __ string_indexof($str1$$Register, $str2$$Register,
12635 $cnt1$$Register, $cnt2$$Register,
12636 (-1), $result$$Register,
12637 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
12638 %}
12639 ins_pipe( pipe_slow );
12640 %}
12641
12642 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
12643 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
12644 %{
12645 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
12646 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12647 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12648
12649 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
12650 ins_encode %{
12651 __ string_indexof($str1$$Register, $str2$$Register,
12652 $cnt1$$Register, $cnt2$$Register,
12653 (-1), $result$$Register,
12654 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
12655 %}
12656 ins_pipe( pipe_slow );
12657 %}
12658
12659 instruct string_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
12660 rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
12661 %{
12662 predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
12663 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
12664 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
12665 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
12666 ins_encode %{
12667 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
12668 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
12669 %}
12670 ins_pipe( pipe_slow );
12671 %}
12672
12673 instruct stringL_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
12674 rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
12675 %{
12676 predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
12677 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
12678 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
12679 format %{ "StringLatin1 IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
12680 ins_encode %{
12681 __ stringL_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
12682 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
12683 %}
12684 ins_pipe( pipe_slow );
12685 %}
12686
12687 // fast string equals
12688 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
12689 legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr)
12690 %{
12691 predicate(!VM_Version::supports_avx512vlbw());
12692 match(Set result (StrEquals (Binary str1 str2) cnt));
12693 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12694
12695 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12696 ins_encode %{
12697 __ arrays_equals(false, $str1$$Register, $str2$$Register,
12698 $cnt$$Register, $result$$Register, $tmp3$$Register,
12699 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
12700 %}
12701 ins_pipe( pipe_slow );
12702 %}
12703
12704 instruct string_equals_evex(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
12705 legRegD tmp1, legRegD tmp2, kReg ktmp, rbx_RegI tmp3, rFlagsReg cr)
12706 %{
12707 predicate(VM_Version::supports_avx512vlbw());
12708 match(Set result (StrEquals (Binary str1 str2) cnt));
12709 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12710
12711 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12712 ins_encode %{
12713 __ arrays_equals(false, $str1$$Register, $str2$$Register,
12714 $cnt$$Register, $result$$Register, $tmp3$$Register,
12715 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
12716 %}
12717 ins_pipe( pipe_slow );
12718 %}
12719
12720 // fast array equals
12721 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
12722 legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
12723 %{
12724 predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
12725 match(Set result (AryEq ary1 ary2));
12726 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12727
12728 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12729 ins_encode %{
12730 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
12731 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12732 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
12733 %}
12734 ins_pipe( pipe_slow );
12735 %}
12736
12737 instruct array_equalsB_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
12738 legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
12739 %{
12740 predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
12741 match(Set result (AryEq ary1 ary2));
12742 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12743
12744 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12745 ins_encode %{
12746 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
12747 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12748 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
12749 %}
12750 ins_pipe( pipe_slow );
12751 %}
12752
12753 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
12754 legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
12755 %{
12756 predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
12757 match(Set result (AryEq ary1 ary2));
12758 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12759
12760 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12761 ins_encode %{
12762 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
12763 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12764 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, knoreg);
12765 %}
12766 ins_pipe( pipe_slow );
12767 %}
12768
12769 instruct array_equalsC_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
12770 legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
12771 %{
12772 predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
12773 match(Set result (AryEq ary1 ary2));
12774 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12775
12776 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12777 ins_encode %{
12778 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
12779 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12780 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, $ktmp$$KRegister);
12781 %}
12782 ins_pipe( pipe_slow );
12783 %}
12784
12785 instruct arrays_hashcode(rdi_RegP ary1, rdx_RegI cnt1, rbx_RegI result, immU8 basic_type,
12786 legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, legRegD tmp_vec4,
12787 legRegD tmp_vec5, legRegD tmp_vec6, legRegD tmp_vec7, legRegD tmp_vec8,
12788 legRegD tmp_vec9, legRegD tmp_vec10, legRegD tmp_vec11, legRegD tmp_vec12,
12789 legRegD tmp_vec13, rRegI tmp1, rRegI tmp2, rRegI tmp3, rFlagsReg cr)
12790 %{
12791 predicate(UseAVX >= 2);
12792 match(Set result (VectorizedHashCode (Binary ary1 cnt1) (Binary result basic_type)));
12793 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, TEMP tmp_vec4, TEMP tmp_vec5, TEMP tmp_vec6,
12794 TEMP tmp_vec7, TEMP tmp_vec8, TEMP tmp_vec9, TEMP tmp_vec10, TEMP tmp_vec11, TEMP tmp_vec12,
12795 TEMP tmp_vec13, TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL ary1, USE_KILL cnt1,
12796 USE basic_type, KILL cr);
12797
12798 format %{ "Array HashCode array[] $ary1,$cnt1,$result,$basic_type -> $result // KILL all" %}
12799 ins_encode %{
12800 __ arrays_hashcode($ary1$$Register, $cnt1$$Register, $result$$Register,
12801 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
12802 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister,
12803 $tmp_vec4$$XMMRegister, $tmp_vec5$$XMMRegister, $tmp_vec6$$XMMRegister,
12804 $tmp_vec7$$XMMRegister, $tmp_vec8$$XMMRegister, $tmp_vec9$$XMMRegister,
12805 $tmp_vec10$$XMMRegister, $tmp_vec11$$XMMRegister, $tmp_vec12$$XMMRegister,
12806 $tmp_vec13$$XMMRegister, (BasicType)$basic_type$$constant);
12807 %}
12808 ins_pipe( pipe_slow );
12809 %}
12810
12811 instruct count_positives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
12812 legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr,)
12813 %{
12814 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
12815 match(Set result (CountPositives ary1 len));
12816 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
12817
12818 format %{ "countPositives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12819 ins_encode %{
12820 __ count_positives($ary1$$Register, $len$$Register,
12821 $result$$Register, $tmp3$$Register,
12822 $tmp1$$XMMRegister, $tmp2$$XMMRegister, knoreg, knoreg);
12823 %}
12824 ins_pipe( pipe_slow );
12825 %}
12826
12827 instruct count_positives_evex(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
12828 legRegD tmp1, legRegD tmp2, kReg ktmp1, kReg ktmp2, rbx_RegI tmp3, rFlagsReg cr,)
12829 %{
12830 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
12831 match(Set result (CountPositives ary1 len));
12832 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp1, TEMP ktmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
12833
12834 format %{ "countPositives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12835 ins_encode %{
12836 __ count_positives($ary1$$Register, $len$$Register,
12837 $result$$Register, $tmp3$$Register,
12838 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $ktmp1$$KRegister, $ktmp2$$KRegister);
12839 %}
12840 ins_pipe( pipe_slow );
12841 %}
12842
12843 // fast char[] to byte[] compression
12844 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
12845 legRegD tmp4, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12846 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
12847 match(Set result (StrCompressedCopy src (Binary dst len)));
12848 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst,
12849 USE_KILL len, KILL tmp5, KILL cr);
12850
12851 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
12852 ins_encode %{
12853 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
12854 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12855 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
12856 knoreg, knoreg);
12857 %}
12858 ins_pipe( pipe_slow );
12859 %}
12860
12861 instruct string_compress_evex(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
12862 legRegD tmp4, kReg ktmp1, kReg ktmp2, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12863 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
12864 match(Set result (StrCompressedCopy src (Binary dst len)));
12865 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ktmp1, TEMP ktmp2, USE_KILL src, USE_KILL dst,
12866 USE_KILL len, KILL tmp5, KILL cr);
12867
12868 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
12869 ins_encode %{
12870 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
12871 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12872 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
12873 $ktmp1$$KRegister, $ktmp2$$KRegister);
12874 %}
12875 ins_pipe( pipe_slow );
12876 %}
12877 // fast byte[] to char[] inflation
12878 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12879 legRegD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
12880 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
12881 match(Set dummy (StrInflatedCopy src (Binary dst len)));
12882 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
12883
12884 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
12885 ins_encode %{
12886 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
12887 $tmp1$$XMMRegister, $tmp2$$Register, knoreg);
12888 %}
12889 ins_pipe( pipe_slow );
12890 %}
12891
12892 instruct string_inflate_evex(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12893 legRegD tmp1, kReg ktmp, rcx_RegI tmp2, rFlagsReg cr) %{
12894 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
12895 match(Set dummy (StrInflatedCopy src (Binary dst len)));
12896 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
12897
12898 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
12899 ins_encode %{
12900 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
12901 $tmp1$$XMMRegister, $tmp2$$Register, $ktmp$$KRegister);
12902 %}
12903 ins_pipe( pipe_slow );
12904 %}
12905
12906 // encode char[] to byte[] in ISO_8859_1
12907 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12908 legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
12909 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12910 predicate(!((EncodeISOArrayNode*)n)->is_ascii());
12911 match(Set result (EncodeISOArray src (Binary dst len)));
12912 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
12913
12914 format %{ "Encode iso array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
12915 ins_encode %{
12916 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
12917 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12918 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, false);
12919 %}
12920 ins_pipe( pipe_slow );
12921 %}
12922
12923 // encode char[] to byte[] in ASCII
12924 instruct encode_ascii_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12925 legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
12926 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12927 predicate(((EncodeISOArrayNode*)n)->is_ascii());
12928 match(Set result (EncodeISOArray src (Binary dst len)));
12929 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
12930
12931 format %{ "Encode ascii array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
12932 ins_encode %{
12933 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
12934 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12935 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, true);
12936 %}
12937 ins_pipe( pipe_slow );
12938 %}
12939
12940 //----------Overflow Math Instructions-----------------------------------------
12941
12942 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
12943 %{
12944 match(Set cr (OverflowAddI op1 op2));
12945 effect(DEF cr, USE_KILL op1, USE op2);
12946
12947 format %{ "addl $op1, $op2\t# overflow check int" %}
12948
12949 ins_encode %{
12950 __ addl($op1$$Register, $op2$$Register);
12951 %}
12952 ins_pipe(ialu_reg_reg);
12953 %}
12954
12955 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
12956 %{
12957 match(Set cr (OverflowAddI op1 op2));
12958 effect(DEF cr, USE_KILL op1, USE op2);
12959
12960 format %{ "addl $op1, $op2\t# overflow check int" %}
12961
12962 ins_encode %{
12963 __ addl($op1$$Register, $op2$$constant);
12964 %}
12965 ins_pipe(ialu_reg_reg);
12966 %}
12967
12968 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
12969 %{
12970 match(Set cr (OverflowAddL op1 op2));
12971 effect(DEF cr, USE_KILL op1, USE op2);
12972
12973 format %{ "addq $op1, $op2\t# overflow check long" %}
12974 ins_encode %{
12975 __ addq($op1$$Register, $op2$$Register);
12976 %}
12977 ins_pipe(ialu_reg_reg);
12978 %}
12979
12980 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
12981 %{
12982 match(Set cr (OverflowAddL op1 op2));
12983 effect(DEF cr, USE_KILL op1, USE op2);
12984
12985 format %{ "addq $op1, $op2\t# overflow check long" %}
12986 ins_encode %{
12987 __ addq($op1$$Register, $op2$$constant);
12988 %}
12989 ins_pipe(ialu_reg_reg);
12990 %}
12991
12992 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
12993 %{
12994 match(Set cr (OverflowSubI op1 op2));
12995
12996 format %{ "cmpl $op1, $op2\t# overflow check int" %}
12997 ins_encode %{
12998 __ cmpl($op1$$Register, $op2$$Register);
12999 %}
13000 ins_pipe(ialu_reg_reg);
13001 %}
13002
13003 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
13004 %{
13005 match(Set cr (OverflowSubI op1 op2));
13006
13007 format %{ "cmpl $op1, $op2\t# overflow check int" %}
13008 ins_encode %{
13009 __ cmpl($op1$$Register, $op2$$constant);
13010 %}
13011 ins_pipe(ialu_reg_reg);
13012 %}
13013
13014 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
13015 %{
13016 match(Set cr (OverflowSubL op1 op2));
13017
13018 format %{ "cmpq $op1, $op2\t# overflow check long" %}
13019 ins_encode %{
13020 __ cmpq($op1$$Register, $op2$$Register);
13021 %}
13022 ins_pipe(ialu_reg_reg);
13023 %}
13024
13025 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
13026 %{
13027 match(Set cr (OverflowSubL op1 op2));
13028
13029 format %{ "cmpq $op1, $op2\t# overflow check long" %}
13030 ins_encode %{
13031 __ cmpq($op1$$Register, $op2$$constant);
13032 %}
13033 ins_pipe(ialu_reg_reg);
13034 %}
13035
13036 instruct overflowNegI_rReg(rFlagsReg cr, immI_0 zero, rax_RegI op2)
13037 %{
13038 match(Set cr (OverflowSubI zero op2));
13039 effect(DEF cr, USE_KILL op2);
13040
13041 format %{ "negl $op2\t# overflow check int" %}
13042 ins_encode %{
13043 __ negl($op2$$Register);
13044 %}
13045 ins_pipe(ialu_reg_reg);
13046 %}
13047
13048 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
13049 %{
13050 match(Set cr (OverflowSubL zero op2));
13051 effect(DEF cr, USE_KILL op2);
13052
13053 format %{ "negq $op2\t# overflow check long" %}
13054 ins_encode %{
13055 __ negq($op2$$Register);
13056 %}
13057 ins_pipe(ialu_reg_reg);
13058 %}
13059
13060 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
13061 %{
13062 match(Set cr (OverflowMulI op1 op2));
13063 effect(DEF cr, USE_KILL op1, USE op2);
13064
13065 format %{ "imull $op1, $op2\t# overflow check int" %}
13066 ins_encode %{
13067 __ imull($op1$$Register, $op2$$Register);
13068 %}
13069 ins_pipe(ialu_reg_reg_alu0);
13070 %}
13071
13072 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
13073 %{
13074 match(Set cr (OverflowMulI op1 op2));
13075 effect(DEF cr, TEMP tmp, USE op1, USE op2);
13076
13077 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
13078 ins_encode %{
13079 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
13080 %}
13081 ins_pipe(ialu_reg_reg_alu0);
13082 %}
13083
13084 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
13085 %{
13086 match(Set cr (OverflowMulL op1 op2));
13087 effect(DEF cr, USE_KILL op1, USE op2);
13088
13089 format %{ "imulq $op1, $op2\t# overflow check long" %}
13090 ins_encode %{
13091 __ imulq($op1$$Register, $op2$$Register);
13092 %}
13093 ins_pipe(ialu_reg_reg_alu0);
13094 %}
13095
13096 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
13097 %{
13098 match(Set cr (OverflowMulL op1 op2));
13099 effect(DEF cr, TEMP tmp, USE op1, USE op2);
13100
13101 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
13102 ins_encode %{
13103 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
13104 %}
13105 ins_pipe(ialu_reg_reg_alu0);
13106 %}
13107
13108
13109 //----------Control Flow Instructions------------------------------------------
13110 // Signed compare Instructions
13111
13112 // XXX more variants!!
13113 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
13114 %{
13115 match(Set cr (CmpI op1 op2));
13116 effect(DEF cr, USE op1, USE op2);
13117
13118 format %{ "cmpl $op1, $op2" %}
13119 ins_encode %{
13120 __ cmpl($op1$$Register, $op2$$Register);
13121 %}
13122 ins_pipe(ialu_cr_reg_reg);
13123 %}
13124
13125 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
13126 %{
13127 match(Set cr (CmpI op1 op2));
13128
13129 format %{ "cmpl $op1, $op2" %}
13130 ins_encode %{
13131 __ cmpl($op1$$Register, $op2$$constant);
13132 %}
13133 ins_pipe(ialu_cr_reg_imm);
13134 %}
13135
13136 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
13137 %{
13138 match(Set cr (CmpI op1 (LoadI op2)));
13139
13140 ins_cost(500); // XXX
13141 format %{ "cmpl $op1, $op2" %}
13142 ins_encode %{
13143 __ cmpl($op1$$Register, $op2$$Address);
13144 %}
13145 ins_pipe(ialu_cr_reg_mem);
13146 %}
13147
13148 instruct testI_reg(rFlagsReg cr, rRegI src, immI_0 zero)
13149 %{
13150 match(Set cr (CmpI src zero));
13151
13152 format %{ "testl $src, $src" %}
13153 ins_encode %{
13154 __ testl($src$$Register, $src$$Register);
13155 %}
13156 ins_pipe(ialu_cr_reg_imm);
13157 %}
13158
13159 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI_0 zero)
13160 %{
13161 match(Set cr (CmpI (AndI src con) zero));
13162
13163 format %{ "testl $src, $con" %}
13164 ins_encode %{
13165 __ testl($src$$Register, $con$$constant);
13166 %}
13167 ins_pipe(ialu_cr_reg_imm);
13168 %}
13169
13170 instruct testI_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2, immI_0 zero)
13171 %{
13172 match(Set cr (CmpI (AndI src1 src2) zero));
13173
13174 format %{ "testl $src1, $src2" %}
13175 ins_encode %{
13176 __ testl($src1$$Register, $src2$$Register);
13177 %}
13178 ins_pipe(ialu_cr_reg_imm);
13179 %}
13180
13181 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI_0 zero)
13182 %{
13183 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
13184
13185 format %{ "testl $src, $mem" %}
13186 ins_encode %{
13187 __ testl($src$$Register, $mem$$Address);
13188 %}
13189 ins_pipe(ialu_cr_reg_mem);
13190 %}
13191
13192 // Unsigned compare Instructions; really, same as signed except they
13193 // produce an rFlagsRegU instead of rFlagsReg.
13194 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
13195 %{
13196 match(Set cr (CmpU op1 op2));
13197
13198 format %{ "cmpl $op1, $op2\t# unsigned" %}
13199 ins_encode %{
13200 __ cmpl($op1$$Register, $op2$$Register);
13201 %}
13202 ins_pipe(ialu_cr_reg_reg);
13203 %}
13204
13205 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
13206 %{
13207 match(Set cr (CmpU op1 op2));
13208
13209 format %{ "cmpl $op1, $op2\t# unsigned" %}
13210 ins_encode %{
13211 __ cmpl($op1$$Register, $op2$$constant);
13212 %}
13213 ins_pipe(ialu_cr_reg_imm);
13214 %}
13215
13216 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
13217 %{
13218 match(Set cr (CmpU op1 (LoadI op2)));
13219
13220 ins_cost(500); // XXX
13221 format %{ "cmpl $op1, $op2\t# unsigned" %}
13222 ins_encode %{
13223 __ cmpl($op1$$Register, $op2$$Address);
13224 %}
13225 ins_pipe(ialu_cr_reg_mem);
13226 %}
13227
13228 instruct testU_reg(rFlagsRegU cr, rRegI src, immI_0 zero)
13229 %{
13230 match(Set cr (CmpU src zero));
13231
13232 format %{ "testl $src, $src\t# unsigned" %}
13233 ins_encode %{
13234 __ testl($src$$Register, $src$$Register);
13235 %}
13236 ins_pipe(ialu_cr_reg_imm);
13237 %}
13238
13239 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
13240 %{
13241 match(Set cr (CmpP op1 op2));
13242
13243 format %{ "cmpq $op1, $op2\t# ptr" %}
13244 ins_encode %{
13245 __ cmpq($op1$$Register, $op2$$Register);
13246 %}
13247 ins_pipe(ialu_cr_reg_reg);
13248 %}
13249
13250 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
13251 %{
13252 match(Set cr (CmpP op1 (LoadP op2)));
13253 predicate(n->in(2)->as_Load()->barrier_data() == 0);
13254
13255 ins_cost(500); // XXX
13256 format %{ "cmpq $op1, $op2\t# ptr" %}
13257 ins_encode %{
13258 __ cmpq($op1$$Register, $op2$$Address);
13259 %}
13260 ins_pipe(ialu_cr_reg_mem);
13261 %}
13262
13263 // XXX this is generalized by compP_rReg_mem???
13264 // Compare raw pointer (used in out-of-heap check).
13265 // Only works because non-oop pointers must be raw pointers
13266 // and raw pointers have no anti-dependencies.
13267 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
13268 %{
13269 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none &&
13270 n->in(2)->as_Load()->barrier_data() == 0);
13271 match(Set cr (CmpP op1 (LoadP op2)));
13272
13273 format %{ "cmpq $op1, $op2\t# raw ptr" %}
13274 ins_encode %{
13275 __ cmpq($op1$$Register, $op2$$Address);
13276 %}
13277 ins_pipe(ialu_cr_reg_mem);
13278 %}
13279
13280 // This will generate a signed flags result. This should be OK since
13281 // any compare to a zero should be eq/neq.
13282 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
13283 %{
13284 match(Set cr (CmpP src zero));
13285
13286 format %{ "testq $src, $src\t# ptr" %}
13287 ins_encode %{
13288 __ testq($src$$Register, $src$$Register);
13289 %}
13290 ins_pipe(ialu_cr_reg_imm);
13291 %}
13292
13293 // This will generate a signed flags result. This should be OK since
13294 // any compare to a zero should be eq/neq.
13295 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
13296 %{
13297 predicate((!UseCompressedOops || (CompressedOops::base() != nullptr)) &&
13298 n->in(1)->as_Load()->barrier_data() == 0);
13299 match(Set cr (CmpP (LoadP op) zero));
13300
13301 ins_cost(500); // XXX
13302 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
13303 ins_encode %{
13304 __ testq($op$$Address, 0xFFFFFFFF);
13305 %}
13306 ins_pipe(ialu_cr_reg_imm);
13307 %}
13308
13309 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
13310 %{
13311 predicate(UseCompressedOops && (CompressedOops::base() == nullptr) &&
13312 n->in(1)->as_Load()->barrier_data() == 0);
13313 match(Set cr (CmpP (LoadP mem) zero));
13314
13315 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
13316 ins_encode %{
13317 __ cmpq(r12, $mem$$Address);
13318 %}
13319 ins_pipe(ialu_cr_reg_mem);
13320 %}
13321
13322 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
13323 %{
13324 match(Set cr (CmpN op1 op2));
13325
13326 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
13327 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
13328 ins_pipe(ialu_cr_reg_reg);
13329 %}
13330
13331 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
13332 %{
13333 predicate(n->in(2)->as_Load()->barrier_data() == 0);
13334 match(Set cr (CmpN src (LoadN mem)));
13335
13336 format %{ "cmpl $src, $mem\t# compressed ptr" %}
13337 ins_encode %{
13338 __ cmpl($src$$Register, $mem$$Address);
13339 %}
13340 ins_pipe(ialu_cr_reg_mem);
13341 %}
13342
13343 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
13344 match(Set cr (CmpN op1 op2));
13345
13346 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
13347 ins_encode %{
13348 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
13349 %}
13350 ins_pipe(ialu_cr_reg_imm);
13351 %}
13352
13353 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
13354 %{
13355 predicate(n->in(2)->as_Load()->barrier_data() == 0);
13356 match(Set cr (CmpN src (LoadN mem)));
13357
13358 format %{ "cmpl $mem, $src\t# compressed ptr" %}
13359 ins_encode %{
13360 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
13361 %}
13362 ins_pipe(ialu_cr_reg_mem);
13363 %}
13364
13365 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
13366 match(Set cr (CmpN op1 op2));
13367
13368 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
13369 ins_encode %{
13370 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
13371 %}
13372 ins_pipe(ialu_cr_reg_imm);
13373 %}
13374
13375 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
13376 %{
13377 predicate(!UseCompactObjectHeaders);
13378 match(Set cr (CmpN src (LoadNKlass mem)));
13379
13380 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
13381 ins_encode %{
13382 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
13383 %}
13384 ins_pipe(ialu_cr_reg_mem);
13385 %}
13386
13387 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
13388 match(Set cr (CmpN src zero));
13389
13390 format %{ "testl $src, $src\t# compressed ptr" %}
13391 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
13392 ins_pipe(ialu_cr_reg_imm);
13393 %}
13394
13395 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
13396 %{
13397 predicate(CompressedOops::base() != nullptr &&
13398 n->in(1)->as_Load()->barrier_data() == 0);
13399 match(Set cr (CmpN (LoadN mem) zero));
13400
13401 ins_cost(500); // XXX
13402 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
13403 ins_encode %{
13404 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
13405 %}
13406 ins_pipe(ialu_cr_reg_mem);
13407 %}
13408
13409 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
13410 %{
13411 predicate(CompressedOops::base() == nullptr &&
13412 n->in(1)->as_Load()->barrier_data() == 0);
13413 match(Set cr (CmpN (LoadN mem) zero));
13414
13415 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
13416 ins_encode %{
13417 __ cmpl(r12, $mem$$Address);
13418 %}
13419 ins_pipe(ialu_cr_reg_mem);
13420 %}
13421
13422 // Yanked all unsigned pointer compare operations.
13423 // Pointer compares are done with CmpP which is already unsigned.
13424
13425 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
13426 %{
13427 match(Set cr (CmpL op1 op2));
13428
13429 format %{ "cmpq $op1, $op2" %}
13430 ins_encode %{
13431 __ cmpq($op1$$Register, $op2$$Register);
13432 %}
13433 ins_pipe(ialu_cr_reg_reg);
13434 %}
13435
13436 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
13437 %{
13438 match(Set cr (CmpL op1 op2));
13439
13440 format %{ "cmpq $op1, $op2" %}
13441 ins_encode %{
13442 __ cmpq($op1$$Register, $op2$$constant);
13443 %}
13444 ins_pipe(ialu_cr_reg_imm);
13445 %}
13446
13447 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
13448 %{
13449 match(Set cr (CmpL op1 (LoadL op2)));
13450
13451 format %{ "cmpq $op1, $op2" %}
13452 ins_encode %{
13453 __ cmpq($op1$$Register, $op2$$Address);
13454 %}
13455 ins_pipe(ialu_cr_reg_mem);
13456 %}
13457
13458 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
13459 %{
13460 match(Set cr (CmpL src zero));
13461
13462 format %{ "testq $src, $src" %}
13463 ins_encode %{
13464 __ testq($src$$Register, $src$$Register);
13465 %}
13466 ins_pipe(ialu_cr_reg_imm);
13467 %}
13468
13469 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
13470 %{
13471 match(Set cr (CmpL (AndL src con) zero));
13472
13473 format %{ "testq $src, $con\t# long" %}
13474 ins_encode %{
13475 __ testq($src$$Register, $con$$constant);
13476 %}
13477 ins_pipe(ialu_cr_reg_imm);
13478 %}
13479
13480 instruct testL_reg_reg(rFlagsReg cr, rRegL src1, rRegL src2, immL0 zero)
13481 %{
13482 match(Set cr (CmpL (AndL src1 src2) zero));
13483
13484 format %{ "testq $src1, $src2\t# long" %}
13485 ins_encode %{
13486 __ testq($src1$$Register, $src2$$Register);
13487 %}
13488 ins_pipe(ialu_cr_reg_imm);
13489 %}
13490
13491 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
13492 %{
13493 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
13494
13495 format %{ "testq $src, $mem" %}
13496 ins_encode %{
13497 __ testq($src$$Register, $mem$$Address);
13498 %}
13499 ins_pipe(ialu_cr_reg_mem);
13500 %}
13501
13502 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
13503 %{
13504 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
13505
13506 format %{ "testq $src, $mem" %}
13507 ins_encode %{
13508 __ testq($src$$Register, $mem$$Address);
13509 %}
13510 ins_pipe(ialu_cr_reg_mem);
13511 %}
13512
13513 // Manifest a CmpU result in an integer register. Very painful.
13514 // This is the test to avoid.
13515 instruct cmpU3_reg_reg(rRegI dst, rRegI src1, rRegI src2, rFlagsReg flags)
13516 %{
13517 match(Set dst (CmpU3 src1 src2));
13518 effect(KILL flags);
13519
13520 ins_cost(275); // XXX
13521 format %{ "cmpl $src1, $src2\t# CmpL3\n\t"
13522 "movl $dst, -1\n\t"
13523 "jb,u done\n\t"
13524 "setcc $dst \t# emits setne + movzbl or setzune for APX"
13525 "done:" %}
13526 ins_encode %{
13527 Label done;
13528 __ cmpl($src1$$Register, $src2$$Register);
13529 __ movl($dst$$Register, -1);
13530 __ jccb(Assembler::below, done);
13531 __ setcc(Assembler::notZero, $dst$$Register);
13532 __ bind(done);
13533 %}
13534 ins_pipe(pipe_slow);
13535 %}
13536
13537 // Manifest a CmpL result in an integer register. Very painful.
13538 // This is the test to avoid.
13539 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
13540 %{
13541 match(Set dst (CmpL3 src1 src2));
13542 effect(KILL flags);
13543
13544 ins_cost(275); // XXX
13545 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
13546 "movl $dst, -1\n\t"
13547 "jl,s done\n\t"
13548 "setcc $dst \t# emits setne + movzbl or setzune for APX"
13549 "done:" %}
13550 ins_encode %{
13551 Label done;
13552 __ cmpq($src1$$Register, $src2$$Register);
13553 __ movl($dst$$Register, -1);
13554 __ jccb(Assembler::less, done);
13555 __ setcc(Assembler::notZero, $dst$$Register);
13556 __ bind(done);
13557 %}
13558 ins_pipe(pipe_slow);
13559 %}
13560
13561 // Manifest a CmpUL result in an integer register. Very painful.
13562 // This is the test to avoid.
13563 instruct cmpUL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
13564 %{
13565 match(Set dst (CmpUL3 src1 src2));
13566 effect(KILL flags);
13567
13568 ins_cost(275); // XXX
13569 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
13570 "movl $dst, -1\n\t"
13571 "jb,u done\n\t"
13572 "setcc $dst \t# emits setne + movzbl or setzune for APX"
13573 "done:" %}
13574 ins_encode %{
13575 Label done;
13576 __ cmpq($src1$$Register, $src2$$Register);
13577 __ movl($dst$$Register, -1);
13578 __ jccb(Assembler::below, done);
13579 __ setcc(Assembler::notZero, $dst$$Register);
13580 __ bind(done);
13581 %}
13582 ins_pipe(pipe_slow);
13583 %}
13584
13585 // Unsigned long compare Instructions; really, same as signed long except they
13586 // produce an rFlagsRegU instead of rFlagsReg.
13587 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
13588 %{
13589 match(Set cr (CmpUL op1 op2));
13590
13591 format %{ "cmpq $op1, $op2\t# unsigned" %}
13592 ins_encode %{
13593 __ cmpq($op1$$Register, $op2$$Register);
13594 %}
13595 ins_pipe(ialu_cr_reg_reg);
13596 %}
13597
13598 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
13599 %{
13600 match(Set cr (CmpUL op1 op2));
13601
13602 format %{ "cmpq $op1, $op2\t# unsigned" %}
13603 ins_encode %{
13604 __ cmpq($op1$$Register, $op2$$constant);
13605 %}
13606 ins_pipe(ialu_cr_reg_imm);
13607 %}
13608
13609 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
13610 %{
13611 match(Set cr (CmpUL op1 (LoadL op2)));
13612
13613 format %{ "cmpq $op1, $op2\t# unsigned" %}
13614 ins_encode %{
13615 __ cmpq($op1$$Register, $op2$$Address);
13616 %}
13617 ins_pipe(ialu_cr_reg_mem);
13618 %}
13619
13620 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
13621 %{
13622 match(Set cr (CmpUL src zero));
13623
13624 format %{ "testq $src, $src\t# unsigned" %}
13625 ins_encode %{
13626 __ testq($src$$Register, $src$$Register);
13627 %}
13628 ins_pipe(ialu_cr_reg_imm);
13629 %}
13630
13631 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
13632 %{
13633 match(Set cr (CmpI (LoadB mem) imm));
13634
13635 ins_cost(125);
13636 format %{ "cmpb $mem, $imm" %}
13637 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
13638 ins_pipe(ialu_cr_reg_mem);
13639 %}
13640
13641 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU7 imm, immI_0 zero)
13642 %{
13643 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
13644
13645 ins_cost(125);
13646 format %{ "testb $mem, $imm\t# ubyte" %}
13647 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
13648 ins_pipe(ialu_cr_reg_mem);
13649 %}
13650
13651 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI_0 zero)
13652 %{
13653 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
13654
13655 ins_cost(125);
13656 format %{ "testb $mem, $imm\t# byte" %}
13657 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
13658 ins_pipe(ialu_cr_reg_mem);
13659 %}
13660
13661 //----------Max and Min--------------------------------------------------------
13662 // Min Instructions
13663
13664 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
13665 %{
13666 predicate(!UseAPX);
13667 effect(USE_DEF dst, USE src, USE cr);
13668
13669 format %{ "cmovlgt $dst, $src\t# min" %}
13670 ins_encode %{
13671 __ cmovl(Assembler::greater, $dst$$Register, $src$$Register);
13672 %}
13673 ins_pipe(pipe_cmov_reg);
13674 %}
13675
13676 instruct cmovI_reg_g_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
13677 %{
13678 predicate(UseAPX);
13679 effect(DEF dst, USE src1, USE src2, USE cr);
13680
13681 format %{ "ecmovlgt $dst, $src1, $src2\t# min ndd" %}
13682 ins_encode %{
13683 __ ecmovl(Assembler::greater, $dst$$Register, $src1$$Register, $src2$$Register);
13684 %}
13685 ins_pipe(pipe_cmov_reg);
13686 %}
13687
13688 instruct minI_rReg(rRegI dst, rRegI src)
13689 %{
13690 predicate(!UseAPX);
13691 match(Set dst (MinI dst src));
13692
13693 ins_cost(200);
13694 expand %{
13695 rFlagsReg cr;
13696 compI_rReg(cr, dst, src);
13697 cmovI_reg_g(dst, src, cr);
13698 %}
13699 %}
13700
13701 instruct minI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2)
13702 %{
13703 predicate(UseAPX);
13704 match(Set dst (MinI src1 src2));
13705 effect(DEF dst, USE src1, USE src2);
13706
13707 ins_cost(200);
13708 expand %{
13709 rFlagsReg cr;
13710 compI_rReg(cr, src1, src2);
13711 cmovI_reg_g_ndd(dst, src1, src2, cr);
13712 %}
13713 %}
13714
13715 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
13716 %{
13717 predicate(!UseAPX);
13718 effect(USE_DEF dst, USE src, USE cr);
13719
13720 format %{ "cmovllt $dst, $src\t# max" %}
13721 ins_encode %{
13722 __ cmovl(Assembler::less, $dst$$Register, $src$$Register);
13723 %}
13724 ins_pipe(pipe_cmov_reg);
13725 %}
13726
13727 instruct cmovI_reg_l_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
13728 %{
13729 predicate(UseAPX);
13730 effect(DEF dst, USE src1, USE src2, USE cr);
13731
13732 format %{ "ecmovllt $dst, $src1, $src2\t# max ndd" %}
13733 ins_encode %{
13734 __ ecmovl(Assembler::less, $dst$$Register, $src1$$Register, $src2$$Register);
13735 %}
13736 ins_pipe(pipe_cmov_reg);
13737 %}
13738
13739 instruct maxI_rReg(rRegI dst, rRegI src)
13740 %{
13741 predicate(!UseAPX);
13742 match(Set dst (MaxI dst src));
13743
13744 ins_cost(200);
13745 expand %{
13746 rFlagsReg cr;
13747 compI_rReg(cr, dst, src);
13748 cmovI_reg_l(dst, src, cr);
13749 %}
13750 %}
13751
13752 instruct maxI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2)
13753 %{
13754 predicate(UseAPX);
13755 match(Set dst (MaxI src1 src2));
13756 effect(DEF dst, USE src1, USE src2);
13757
13758 ins_cost(200);
13759 expand %{
13760 rFlagsReg cr;
13761 compI_rReg(cr, src1, src2);
13762 cmovI_reg_l_ndd(dst, src1, src2, cr);
13763 %}
13764 %}
13765
13766 // ============================================================================
13767 // Branch Instructions
13768
13769 // Jump Direct - Label defines a relative address from JMP+1
13770 instruct jmpDir(label labl)
13771 %{
13772 match(Goto);
13773 effect(USE labl);
13774
13775 ins_cost(300);
13776 format %{ "jmp $labl" %}
13777 size(5);
13778 ins_encode %{
13779 Label* L = $labl$$label;
13780 __ jmp(*L, false); // Always long jump
13781 %}
13782 ins_pipe(pipe_jmp);
13783 %}
13784
13785 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13786 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
13787 %{
13788 match(If cop cr);
13789 effect(USE labl);
13790
13791 ins_cost(300);
13792 format %{ "j$cop $labl" %}
13793 size(6);
13794 ins_encode %{
13795 Label* L = $labl$$label;
13796 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13797 %}
13798 ins_pipe(pipe_jcc);
13799 %}
13800
13801 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13802 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
13803 %{
13804 match(CountedLoopEnd cop cr);
13805 effect(USE labl);
13806
13807 ins_cost(300);
13808 format %{ "j$cop $labl\t# loop end" %}
13809 size(6);
13810 ins_encode %{
13811 Label* L = $labl$$label;
13812 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13813 %}
13814 ins_pipe(pipe_jcc);
13815 %}
13816
13817 // Jump Direct Conditional - using unsigned comparison
13818 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
13819 match(If cop cmp);
13820 effect(USE labl);
13821
13822 ins_cost(300);
13823 format %{ "j$cop,u $labl" %}
13824 size(6);
13825 ins_encode %{
13826 Label* L = $labl$$label;
13827 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13828 %}
13829 ins_pipe(pipe_jcc);
13830 %}
13831
13832 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
13833 match(If cop cmp);
13834 effect(USE labl);
13835
13836 ins_cost(200);
13837 format %{ "j$cop,u $labl" %}
13838 size(6);
13839 ins_encode %{
13840 Label* L = $labl$$label;
13841 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13842 %}
13843 ins_pipe(pipe_jcc);
13844 %}
13845
13846 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
13847 match(If cop cmp);
13848 effect(USE labl);
13849
13850 ins_cost(200);
13851 format %{ $$template
13852 if ($cop$$cmpcode == Assembler::notEqual) {
13853 $$emit$$"jp,u $labl\n\t"
13854 $$emit$$"j$cop,u $labl"
13855 } else {
13856 $$emit$$"jp,u done\n\t"
13857 $$emit$$"j$cop,u $labl\n\t"
13858 $$emit$$"done:"
13859 }
13860 %}
13861 ins_encode %{
13862 Label* l = $labl$$label;
13863 if ($cop$$cmpcode == Assembler::notEqual) {
13864 __ jcc(Assembler::parity, *l, false);
13865 __ jcc(Assembler::notEqual, *l, false);
13866 } else if ($cop$$cmpcode == Assembler::equal) {
13867 Label done;
13868 __ jccb(Assembler::parity, done);
13869 __ jcc(Assembler::equal, *l, false);
13870 __ bind(done);
13871 } else {
13872 ShouldNotReachHere();
13873 }
13874 %}
13875 ins_pipe(pipe_jcc);
13876 %}
13877
13878 // ============================================================================
13879 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
13880 // superklass array for an instance of the superklass. Set a hidden
13881 // internal cache on a hit (cache is checked with exposed code in
13882 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
13883 // encoding ALSO sets flags.
13884
13885 instruct partialSubtypeCheck(rdi_RegP result,
13886 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
13887 rFlagsReg cr)
13888 %{
13889 match(Set result (PartialSubtypeCheck sub super));
13890 predicate(!UseSecondarySupersTable);
13891 effect(KILL rcx, KILL cr);
13892
13893 ins_cost(1100); // slightly larger than the next version
13894 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
13895 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
13896 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
13897 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
13898 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
13899 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
13900 "xorq $result, $result\t\t Hit: rdi zero\n\t"
13901 "miss:\t" %}
13902
13903 ins_encode %{
13904 Label miss;
13905 // NB: Callers may assume that, when $result is a valid register,
13906 // check_klass_subtype_slow_path_linear sets it to a nonzero
13907 // value.
13908 __ check_klass_subtype_slow_path_linear($sub$$Register, $super$$Register,
13909 $rcx$$Register, $result$$Register,
13910 nullptr, &miss,
13911 /*set_cond_codes:*/ true);
13912 __ xorptr($result$$Register, $result$$Register);
13913 __ bind(miss);
13914 %}
13915
13916 ins_pipe(pipe_slow);
13917 %}
13918
13919 // ============================================================================
13920 // Two versions of hashtable-based partialSubtypeCheck, both used when
13921 // we need to search for a super class in the secondary supers array.
13922 // The first is used when we don't know _a priori_ the class being
13923 // searched for. The second, far more common, is used when we do know:
13924 // this is used for instanceof, checkcast, and any case where C2 can
13925 // determine it by constant propagation.
13926
13927 instruct partialSubtypeCheckVarSuper(rsi_RegP sub, rax_RegP super, rdi_RegP result,
13928 rdx_RegL temp1, rcx_RegL temp2, rbx_RegP temp3, r11_RegL temp4,
13929 rFlagsReg cr)
13930 %{
13931 match(Set result (PartialSubtypeCheck sub super));
13932 predicate(UseSecondarySupersTable);
13933 effect(KILL cr, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
13934
13935 ins_cost(1000);
13936 format %{ "partialSubtypeCheck $result, $sub, $super" %}
13937
13938 ins_encode %{
13939 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $temp1$$Register, $temp2$$Register,
13940 $temp3$$Register, $temp4$$Register, $result$$Register);
13941 %}
13942
13943 ins_pipe(pipe_slow);
13944 %}
13945
13946 instruct partialSubtypeCheckConstSuper(rsi_RegP sub, rax_RegP super_reg, immP super_con, rdi_RegP result,
13947 rdx_RegL temp1, rcx_RegL temp2, rbx_RegP temp3, r11_RegL temp4,
13948 rFlagsReg cr)
13949 %{
13950 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
13951 predicate(UseSecondarySupersTable);
13952 effect(KILL cr, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
13953
13954 ins_cost(700); // smaller than the next version
13955 format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
13956
13957 ins_encode %{
13958 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
13959 if (InlineSecondarySupersTest) {
13960 __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $temp1$$Register, $temp2$$Register,
13961 $temp3$$Register, $temp4$$Register, $result$$Register,
13962 super_klass_slot);
13963 } else {
13964 __ call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
13965 }
13966 %}
13967
13968 ins_pipe(pipe_slow);
13969 %}
13970
13971 // ============================================================================
13972 // Branch Instructions -- short offset versions
13973 //
13974 // These instructions are used to replace jumps of a long offset (the default
13975 // match) with jumps of a shorter offset. These instructions are all tagged
13976 // with the ins_short_branch attribute, which causes the ADLC to suppress the
13977 // match rules in general matching. Instead, the ADLC generates a conversion
13978 // method in the MachNode which can be used to do in-place replacement of the
13979 // long variant with the shorter variant. The compiler will determine if a
13980 // branch can be taken by the is_short_branch_offset() predicate in the machine
13981 // specific code section of the file.
13982
13983 // Jump Direct - Label defines a relative address from JMP+1
13984 instruct jmpDir_short(label labl) %{
13985 match(Goto);
13986 effect(USE labl);
13987
13988 ins_cost(300);
13989 format %{ "jmp,s $labl" %}
13990 size(2);
13991 ins_encode %{
13992 Label* L = $labl$$label;
13993 __ jmpb(*L);
13994 %}
13995 ins_pipe(pipe_jmp);
13996 ins_short_branch(1);
13997 %}
13998
13999 // Jump Direct Conditional - Label defines a relative address from Jcc+1
14000 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
14001 match(If cop cr);
14002 effect(USE labl);
14003
14004 ins_cost(300);
14005 format %{ "j$cop,s $labl" %}
14006 size(2);
14007 ins_encode %{
14008 Label* L = $labl$$label;
14009 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
14010 %}
14011 ins_pipe(pipe_jcc);
14012 ins_short_branch(1);
14013 %}
14014
14015 // Jump Direct Conditional - Label defines a relative address from Jcc+1
14016 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
14017 match(CountedLoopEnd cop cr);
14018 effect(USE labl);
14019
14020 ins_cost(300);
14021 format %{ "j$cop,s $labl\t# loop end" %}
14022 size(2);
14023 ins_encode %{
14024 Label* L = $labl$$label;
14025 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
14026 %}
14027 ins_pipe(pipe_jcc);
14028 ins_short_branch(1);
14029 %}
14030
14031 // Jump Direct Conditional - using unsigned comparison
14032 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
14033 match(If cop cmp);
14034 effect(USE labl);
14035
14036 ins_cost(300);
14037 format %{ "j$cop,us $labl" %}
14038 size(2);
14039 ins_encode %{
14040 Label* L = $labl$$label;
14041 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
14042 %}
14043 ins_pipe(pipe_jcc);
14044 ins_short_branch(1);
14045 %}
14046
14047 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
14048 match(If cop cmp);
14049 effect(USE labl);
14050
14051 ins_cost(300);
14052 format %{ "j$cop,us $labl" %}
14053 size(2);
14054 ins_encode %{
14055 Label* L = $labl$$label;
14056 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
14057 %}
14058 ins_pipe(pipe_jcc);
14059 ins_short_branch(1);
14060 %}
14061
14062 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
14063 match(If cop cmp);
14064 effect(USE labl);
14065
14066 ins_cost(300);
14067 format %{ $$template
14068 if ($cop$$cmpcode == Assembler::notEqual) {
14069 $$emit$$"jp,u,s $labl\n\t"
14070 $$emit$$"j$cop,u,s $labl"
14071 } else {
14072 $$emit$$"jp,u,s done\n\t"
14073 $$emit$$"j$cop,u,s $labl\n\t"
14074 $$emit$$"done:"
14075 }
14076 %}
14077 size(4);
14078 ins_encode %{
14079 Label* l = $labl$$label;
14080 if ($cop$$cmpcode == Assembler::notEqual) {
14081 __ jccb(Assembler::parity, *l);
14082 __ jccb(Assembler::notEqual, *l);
14083 } else if ($cop$$cmpcode == Assembler::equal) {
14084 Label done;
14085 __ jccb(Assembler::parity, done);
14086 __ jccb(Assembler::equal, *l);
14087 __ bind(done);
14088 } else {
14089 ShouldNotReachHere();
14090 }
14091 %}
14092 ins_pipe(pipe_jcc);
14093 ins_short_branch(1);
14094 %}
14095
14096 // ============================================================================
14097 // inlined locking and unlocking
14098
14099 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
14100 predicate(LockingMode != LM_LIGHTWEIGHT);
14101 match(Set cr (FastLock object box));
14102 effect(TEMP tmp, TEMP scr, USE_KILL box);
14103 ins_cost(300);
14104 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
14105 ins_encode %{
14106 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
14107 $scr$$Register, noreg, noreg, r15_thread, nullptr);
14108 %}
14109 ins_pipe(pipe_slow);
14110 %}
14111
14112 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
14113 predicate(LockingMode != LM_LIGHTWEIGHT);
14114 match(Set cr (FastUnlock object box));
14115 effect(TEMP tmp, USE_KILL box);
14116 ins_cost(300);
14117 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
14118 ins_encode %{
14119 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register);
14120 %}
14121 ins_pipe(pipe_slow);
14122 %}
14123
14124 instruct cmpFastLockLightweight(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI rax_reg, rRegP tmp) %{
14125 predicate(LockingMode == LM_LIGHTWEIGHT);
14126 match(Set cr (FastLock object box));
14127 effect(TEMP rax_reg, TEMP tmp, USE_KILL box);
14128 ins_cost(300);
14129 format %{ "fastlock $object,$box\t! kills $box,$rax_reg,$tmp" %}
14130 ins_encode %{
14131 __ fast_lock_lightweight($object$$Register, $box$$Register, $rax_reg$$Register, $tmp$$Register, r15_thread);
14132 %}
14133 ins_pipe(pipe_slow);
14134 %}
14135
14136 instruct cmpFastUnlockLightweight(rFlagsReg cr, rRegP object, rax_RegP rax_reg, rRegP tmp) %{
14137 predicate(LockingMode == LM_LIGHTWEIGHT);
14138 match(Set cr (FastUnlock object rax_reg));
14139 effect(TEMP tmp, USE_KILL rax_reg);
14140 ins_cost(300);
14141 format %{ "fastunlock $object,$rax_reg\t! kills $rax_reg,$tmp" %}
14142 ins_encode %{
14143 __ fast_unlock_lightweight($object$$Register, $rax_reg$$Register, $tmp$$Register, r15_thread);
14144 %}
14145 ins_pipe(pipe_slow);
14146 %}
14147
14148
14149 // ============================================================================
14150 // Safepoint Instructions
14151 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
14152 %{
14153 match(SafePoint poll);
14154 effect(KILL cr, USE poll);
14155
14156 format %{ "testl rax, [$poll]\t"
14157 "# Safepoint: poll for GC" %}
14158 ins_cost(125);
14159 ins_encode %{
14160 __ relocate(relocInfo::poll_type);
14161 address pre_pc = __ pc();
14162 __ testl(rax, Address($poll$$Register, 0));
14163 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
14164 %}
14165 ins_pipe(ialu_reg_mem);
14166 %}
14167
14168 instruct mask_all_evexL(kReg dst, rRegL src) %{
14169 match(Set dst (MaskAll src));
14170 format %{ "mask_all_evexL $dst, $src \t! mask all operation" %}
14171 ins_encode %{
14172 int mask_len = Matcher::vector_length(this);
14173 __ vector_maskall_operation($dst$$KRegister, $src$$Register, mask_len);
14174 %}
14175 ins_pipe( pipe_slow );
14176 %}
14177
14178 instruct mask_all_evexI_GT32(kReg dst, rRegI src, rRegL tmp) %{
14179 predicate(Matcher::vector_length(n) > 32);
14180 match(Set dst (MaskAll src));
14181 effect(TEMP tmp);
14182 format %{ "mask_all_evexI_GT32 $dst, $src \t! using $tmp as TEMP" %}
14183 ins_encode %{
14184 int mask_len = Matcher::vector_length(this);
14185 __ movslq($tmp$$Register, $src$$Register);
14186 __ vector_maskall_operation($dst$$KRegister, $tmp$$Register, mask_len);
14187 %}
14188 ins_pipe( pipe_slow );
14189 %}
14190
14191 // ============================================================================
14192 // Procedure Call/Return Instructions
14193 // Call Java Static Instruction
14194 // Note: If this code changes, the corresponding ret_addr_offset() and
14195 // compute_padding() functions will have to be adjusted.
14196 instruct CallStaticJavaDirect(method meth) %{
14197 match(CallStaticJava);
14198 effect(USE meth);
14199
14200 ins_cost(300);
14201 format %{ "call,static " %}
14202 opcode(0xE8); /* E8 cd */
14203 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
14204 ins_pipe(pipe_slow);
14205 ins_alignment(4);
14206 %}
14207
14208 // Call Java Dynamic Instruction
14209 // Note: If this code changes, the corresponding ret_addr_offset() and
14210 // compute_padding() functions will have to be adjusted.
14211 instruct CallDynamicJavaDirect(method meth)
14212 %{
14213 match(CallDynamicJava);
14214 effect(USE meth);
14215
14216 ins_cost(300);
14217 format %{ "movq rax, #Universe::non_oop_word()\n\t"
14218 "call,dynamic " %}
14219 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
14220 ins_pipe(pipe_slow);
14221 ins_alignment(4);
14222 %}
14223
14224 // Call Runtime Instruction
14225 instruct CallRuntimeDirect(method meth)
14226 %{
14227 match(CallRuntime);
14228 effect(USE meth);
14229
14230 ins_cost(300);
14231 format %{ "call,runtime " %}
14232 ins_encode(clear_avx, Java_To_Runtime(meth));
14233 ins_pipe(pipe_slow);
14234 %}
14235
14236 // Call runtime without safepoint
14237 instruct CallLeafDirect(method meth)
14238 %{
14239 match(CallLeaf);
14240 effect(USE meth);
14241
14242 ins_cost(300);
14243 format %{ "call_leaf,runtime " %}
14244 ins_encode(clear_avx, Java_To_Runtime(meth));
14245 ins_pipe(pipe_slow);
14246 %}
14247
14248 // Call runtime without safepoint and with vector arguments
14249 instruct CallLeafDirectVector(method meth)
14250 %{
14251 match(CallLeafVector);
14252 effect(USE meth);
14253
14254 ins_cost(300);
14255 format %{ "call_leaf,vector " %}
14256 ins_encode(Java_To_Runtime(meth));
14257 ins_pipe(pipe_slow);
14258 %}
14259
14260 // Call runtime without safepoint
14261 instruct CallLeafNoFPDirect(method meth)
14262 %{
14263 match(CallLeafNoFP);
14264 effect(USE meth);
14265
14266 ins_cost(300);
14267 format %{ "call_leaf_nofp,runtime " %}
14268 ins_encode(clear_avx, Java_To_Runtime(meth));
14269 ins_pipe(pipe_slow);
14270 %}
14271
14272 // Return Instruction
14273 // Remove the return address & jump to it.
14274 // Notice: We always emit a nop after a ret to make sure there is room
14275 // for safepoint patching
14276 instruct Ret()
14277 %{
14278 match(Return);
14279
14280 format %{ "ret" %}
14281 ins_encode %{
14282 __ ret(0);
14283 %}
14284 ins_pipe(pipe_jmp);
14285 %}
14286
14287 // Tail Call; Jump from runtime stub to Java code.
14288 // Also known as an 'interprocedural jump'.
14289 // Target of jump will eventually return to caller.
14290 // TailJump below removes the return address.
14291 // Don't use rbp for 'jump_target' because a MachEpilogNode has already been
14292 // emitted just above the TailCall which has reset rbp to the caller state.
14293 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_ptr)
14294 %{
14295 match(TailCall jump_target method_ptr);
14296
14297 ins_cost(300);
14298 format %{ "jmp $jump_target\t# rbx holds method" %}
14299 ins_encode %{
14300 __ jmp($jump_target$$Register);
14301 %}
14302 ins_pipe(pipe_jmp);
14303 %}
14304
14305 // Tail Jump; remove the return address; jump to target.
14306 // TailCall above leaves the return address around.
14307 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
14308 %{
14309 match(TailJump jump_target ex_oop);
14310
14311 ins_cost(300);
14312 format %{ "popq rdx\t# pop return address\n\t"
14313 "jmp $jump_target" %}
14314 ins_encode %{
14315 __ popq(as_Register(RDX_enc));
14316 __ jmp($jump_target$$Register);
14317 %}
14318 ins_pipe(pipe_jmp);
14319 %}
14320
14321 // Forward exception.
14322 instruct ForwardExceptionjmp()
14323 %{
14324 match(ForwardException);
14325
14326 format %{ "jmp forward_exception_stub" %}
14327 ins_encode %{
14328 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()), noreg);
14329 %}
14330 ins_pipe(pipe_jmp);
14331 %}
14332
14333 // Create exception oop: created by stack-crawling runtime code.
14334 // Created exception is now available to this handler, and is setup
14335 // just prior to jumping to this handler. No code emitted.
14336 instruct CreateException(rax_RegP ex_oop)
14337 %{
14338 match(Set ex_oop (CreateEx));
14339
14340 size(0);
14341 // use the following format syntax
14342 format %{ "# exception oop is in rax; no code emitted" %}
14343 ins_encode();
14344 ins_pipe(empty);
14345 %}
14346
14347 // Rethrow exception:
14348 // The exception oop will come in the first argument position.
14349 // Then JUMP (not call) to the rethrow stub code.
14350 instruct RethrowException()
14351 %{
14352 match(Rethrow);
14353
14354 // use the following format syntax
14355 format %{ "jmp rethrow_stub" %}
14356 ins_encode %{
14357 __ jump(RuntimeAddress(OptoRuntime::rethrow_stub()), noreg);
14358 %}
14359 ins_pipe(pipe_jmp);
14360 %}
14361
14362 // ============================================================================
14363 // This name is KNOWN by the ADLC and cannot be changed.
14364 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
14365 // for this guy.
14366 instruct tlsLoadP(r15_RegP dst) %{
14367 match(Set dst (ThreadLocal));
14368 effect(DEF dst);
14369
14370 size(0);
14371 format %{ "# TLS is in R15" %}
14372 ins_encode( /*empty encoding*/ );
14373 ins_pipe(ialu_reg_reg);
14374 %}
14375
14376
14377 //----------PEEPHOLE RULES-----------------------------------------------------
14378 // These must follow all instruction definitions as they use the names
14379 // defined in the instructions definitions.
14380 //
14381 // peeppredicate ( rule_predicate );
14382 // // the predicate unless which the peephole rule will be ignored
14383 //
14384 // peepmatch ( root_instr_name [preceding_instruction]* );
14385 //
14386 // peepprocedure ( procedure_name );
14387 // // provide a procedure name to perform the optimization, the procedure should
14388 // // reside in the architecture dependent peephole file, the method has the
14389 // // signature of MachNode* (Block*, int, PhaseRegAlloc*, (MachNode*)(*)(), int...)
14390 // // with the arguments being the basic block, the current node index inside the
14391 // // block, the register allocator, the functions upon invoked return a new node
14392 // // defined in peepreplace, and the rules of the nodes appearing in the
14393 // // corresponding peepmatch, the function return true if successful, else
14394 // // return false
14395 //
14396 // peepconstraint %{
14397 // (instruction_number.operand_name relational_op instruction_number.operand_name
14398 // [, ...] );
14399 // // instruction numbers are zero-based using left to right order in peepmatch
14400 //
14401 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
14402 // // provide an instruction_number.operand_name for each operand that appears
14403 // // in the replacement instruction's match rule
14404 //
14405 // ---------VM FLAGS---------------------------------------------------------
14406 //
14407 // All peephole optimizations can be turned off using -XX:-OptoPeephole
14408 //
14409 // Each peephole rule is given an identifying number starting with zero and
14410 // increasing by one in the order seen by the parser. An individual peephole
14411 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
14412 // on the command-line.
14413 //
14414 // ---------CURRENT LIMITATIONS----------------------------------------------
14415 //
14416 // Only transformations inside a basic block (do we need more for peephole)
14417 //
14418 // ---------EXAMPLE----------------------------------------------------------
14419 //
14420 // // pertinent parts of existing instructions in architecture description
14421 // instruct movI(rRegI dst, rRegI src)
14422 // %{
14423 // match(Set dst (CopyI src));
14424 // %}
14425 //
14426 // instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
14427 // %{
14428 // match(Set dst (AddI dst src));
14429 // effect(KILL cr);
14430 // %}
14431 //
14432 // instruct leaI_rReg_immI(rRegI dst, immI_1 src)
14433 // %{
14434 // match(Set dst (AddI dst src));
14435 // %}
14436 //
14437 // 1. Simple replacement
14438 // - Only match adjacent instructions in same basic block
14439 // - Only equality constraints
14440 // - Only constraints between operands, not (0.dest_reg == RAX_enc)
14441 // - Only one replacement instruction
14442 //
14443 // // Change (inc mov) to lea
14444 // peephole %{
14445 // // lea should only be emitted when beneficial
14446 // peeppredicate( VM_Version::supports_fast_2op_lea() );
14447 // // increment preceded by register-register move
14448 // peepmatch ( incI_rReg movI );
14449 // // require that the destination register of the increment
14450 // // match the destination register of the move
14451 // peepconstraint ( 0.dst == 1.dst );
14452 // // construct a replacement instruction that sets
14453 // // the destination to ( move's source register + one )
14454 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
14455 // %}
14456 //
14457 // 2. Procedural replacement
14458 // - More flexible finding relevent nodes
14459 // - More flexible constraints
14460 // - More flexible transformations
14461 // - May utilise architecture-dependent API more effectively
14462 // - Currently only one replacement instruction due to adlc parsing capabilities
14463 //
14464 // // Change (inc mov) to lea
14465 // peephole %{
14466 // // lea should only be emitted when beneficial
14467 // peeppredicate( VM_Version::supports_fast_2op_lea() );
14468 // // the rule numbers of these nodes inside are passed into the function below
14469 // peepmatch ( incI_rReg movI );
14470 // // the method that takes the responsibility of transformation
14471 // peepprocedure ( inc_mov_to_lea );
14472 // // the replacement is a leaI_rReg_immI, a lambda upon invoked creating this
14473 // // node is passed into the function above
14474 // peepreplace ( leaI_rReg_immI() );
14475 // %}
14476
14477 // These instructions is not matched by the matcher but used by the peephole
14478 instruct leaI_rReg_rReg_peep(rRegI dst, rRegI src1, rRegI src2)
14479 %{
14480 predicate(false);
14481 match(Set dst (AddI src1 src2));
14482 format %{ "leal $dst, [$src1 + $src2]" %}
14483 ins_encode %{
14484 Register dst = $dst$$Register;
14485 Register src1 = $src1$$Register;
14486 Register src2 = $src2$$Register;
14487 if (src1 != rbp && src1 != r13) {
14488 __ leal(dst, Address(src1, src2, Address::times_1));
14489 } else {
14490 assert(src2 != rbp && src2 != r13, "");
14491 __ leal(dst, Address(src2, src1, Address::times_1));
14492 }
14493 %}
14494 ins_pipe(ialu_reg_reg);
14495 %}
14496
14497 instruct leaI_rReg_immI_peep(rRegI dst, rRegI src1, immI src2)
14498 %{
14499 predicate(false);
14500 match(Set dst (AddI src1 src2));
14501 format %{ "leal $dst, [$src1 + $src2]" %}
14502 ins_encode %{
14503 __ leal($dst$$Register, Address($src1$$Register, $src2$$constant));
14504 %}
14505 ins_pipe(ialu_reg_reg);
14506 %}
14507
14508 instruct leaI_rReg_immI2_peep(rRegI dst, rRegI src, immI2 shift)
14509 %{
14510 predicate(false);
14511 match(Set dst (LShiftI src shift));
14512 format %{ "leal $dst, [$src << $shift]" %}
14513 ins_encode %{
14514 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($shift$$constant);
14515 Register src = $src$$Register;
14516 if (scale == Address::times_2 && src != rbp && src != r13) {
14517 __ leal($dst$$Register, Address(src, src, Address::times_1));
14518 } else {
14519 __ leal($dst$$Register, Address(noreg, src, scale));
14520 }
14521 %}
14522 ins_pipe(ialu_reg_reg);
14523 %}
14524
14525 instruct leaL_rReg_rReg_peep(rRegL dst, rRegL src1, rRegL src2)
14526 %{
14527 predicate(false);
14528 match(Set dst (AddL src1 src2));
14529 format %{ "leaq $dst, [$src1 + $src2]" %}
14530 ins_encode %{
14531 Register dst = $dst$$Register;
14532 Register src1 = $src1$$Register;
14533 Register src2 = $src2$$Register;
14534 if (src1 != rbp && src1 != r13) {
14535 __ leaq(dst, Address(src1, src2, Address::times_1));
14536 } else {
14537 assert(src2 != rbp && src2 != r13, "");
14538 __ leaq(dst, Address(src2, src1, Address::times_1));
14539 }
14540 %}
14541 ins_pipe(ialu_reg_reg);
14542 %}
14543
14544 instruct leaL_rReg_immL32_peep(rRegL dst, rRegL src1, immL32 src2)
14545 %{
14546 predicate(false);
14547 match(Set dst (AddL src1 src2));
14548 format %{ "leaq $dst, [$src1 + $src2]" %}
14549 ins_encode %{
14550 __ leaq($dst$$Register, Address($src1$$Register, $src2$$constant));
14551 %}
14552 ins_pipe(ialu_reg_reg);
14553 %}
14554
14555 instruct leaL_rReg_immI2_peep(rRegL dst, rRegL src, immI2 shift)
14556 %{
14557 predicate(false);
14558 match(Set dst (LShiftL src shift));
14559 format %{ "leaq $dst, [$src << $shift]" %}
14560 ins_encode %{
14561 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($shift$$constant);
14562 Register src = $src$$Register;
14563 if (scale == Address::times_2 && src != rbp && src != r13) {
14564 __ leaq($dst$$Register, Address(src, src, Address::times_1));
14565 } else {
14566 __ leaq($dst$$Register, Address(noreg, src, scale));
14567 }
14568 %}
14569 ins_pipe(ialu_reg_reg);
14570 %}
14571
14572 // These peephole rules replace mov + I pairs (where I is one of {add, inc, dec,
14573 // sal}) with lea instructions. The {add, sal} rules are beneficial in
14574 // processors with at least partial ALU support for lea
14575 // (supports_fast_2op_lea()), whereas the {inc, dec} rules are only generally
14576 // beneficial for processors with full ALU support
14577 // (VM_Version::supports_fast_3op_lea()) and Intel Cascade Lake.
14578
14579 peephole
14580 %{
14581 peeppredicate(VM_Version::supports_fast_2op_lea());
14582 peepmatch (addI_rReg);
14583 peepprocedure (lea_coalesce_reg);
14584 peepreplace (leaI_rReg_rReg_peep());
14585 %}
14586
14587 peephole
14588 %{
14589 peeppredicate(VM_Version::supports_fast_2op_lea());
14590 peepmatch (addI_rReg_imm);
14591 peepprocedure (lea_coalesce_imm);
14592 peepreplace (leaI_rReg_immI_peep());
14593 %}
14594
14595 peephole
14596 %{
14597 peeppredicate(VM_Version::supports_fast_3op_lea() ||
14598 VM_Version::is_intel_cascade_lake());
14599 peepmatch (incI_rReg);
14600 peepprocedure (lea_coalesce_imm);
14601 peepreplace (leaI_rReg_immI_peep());
14602 %}
14603
14604 peephole
14605 %{
14606 peeppredicate(VM_Version::supports_fast_3op_lea() ||
14607 VM_Version::is_intel_cascade_lake());
14608 peepmatch (decI_rReg);
14609 peepprocedure (lea_coalesce_imm);
14610 peepreplace (leaI_rReg_immI_peep());
14611 %}
14612
14613 peephole
14614 %{
14615 peeppredicate(VM_Version::supports_fast_2op_lea());
14616 peepmatch (salI_rReg_immI2);
14617 peepprocedure (lea_coalesce_imm);
14618 peepreplace (leaI_rReg_immI2_peep());
14619 %}
14620
14621 peephole
14622 %{
14623 peeppredicate(VM_Version::supports_fast_2op_lea());
14624 peepmatch (addL_rReg);
14625 peepprocedure (lea_coalesce_reg);
14626 peepreplace (leaL_rReg_rReg_peep());
14627 %}
14628
14629 peephole
14630 %{
14631 peeppredicate(VM_Version::supports_fast_2op_lea());
14632 peepmatch (addL_rReg_imm);
14633 peepprocedure (lea_coalesce_imm);
14634 peepreplace (leaL_rReg_immL32_peep());
14635 %}
14636
14637 peephole
14638 %{
14639 peeppredicate(VM_Version::supports_fast_3op_lea() ||
14640 VM_Version::is_intel_cascade_lake());
14641 peepmatch (incL_rReg);
14642 peepprocedure (lea_coalesce_imm);
14643 peepreplace (leaL_rReg_immL32_peep());
14644 %}
14645
14646 peephole
14647 %{
14648 peeppredicate(VM_Version::supports_fast_3op_lea() ||
14649 VM_Version::is_intel_cascade_lake());
14650 peepmatch (decL_rReg);
14651 peepprocedure (lea_coalesce_imm);
14652 peepreplace (leaL_rReg_immL32_peep());
14653 %}
14654
14655 peephole
14656 %{
14657 peeppredicate(VM_Version::supports_fast_2op_lea());
14658 peepmatch (salL_rReg_immI2);
14659 peepprocedure (lea_coalesce_imm);
14660 peepreplace (leaL_rReg_immI2_peep());
14661 %}
14662
14663 // These peephole rules matches instructions which set flags and are followed by a testI/L_reg
14664 // The test instruction is redudanent in case the downstream instuctions (like JCC or CMOV) only use flags that are already set by the previous instruction
14665
14666 //int variant
14667 peephole
14668 %{
14669 peepmatch (testI_reg);
14670 peepprocedure (test_may_remove);
14671 %}
14672
14673 //long variant
14674 peephole
14675 %{
14676 peepmatch (testL_reg);
14677 peepprocedure (test_may_remove);
14678 %}
14679
14680
14681 //----------SMARTSPILL RULES---------------------------------------------------
14682 // These must follow all instruction definitions as they use the names
14683 // defined in the instructions definitions.