1 //
2 // Copyright (c) 2003, 2025, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // architecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131 reg_def R16 (SOC, SOC, Op_RegI, 16, r16->as_VMReg());
132 reg_def R16_H(SOC, SOC, Op_RegI, 16, r16->as_VMReg()->next());
133
134 reg_def R17 (SOC, SOC, Op_RegI, 17, r17->as_VMReg());
135 reg_def R17_H(SOC, SOC, Op_RegI, 17, r17->as_VMReg()->next());
136
137 reg_def R18 (SOC, SOC, Op_RegI, 18, r18->as_VMReg());
138 reg_def R18_H(SOC, SOC, Op_RegI, 18, r18->as_VMReg()->next());
139
140 reg_def R19 (SOC, SOC, Op_RegI, 19, r19->as_VMReg());
141 reg_def R19_H(SOC, SOC, Op_RegI, 19, r19->as_VMReg()->next());
142
143 reg_def R20 (SOC, SOC, Op_RegI, 20, r20->as_VMReg());
144 reg_def R20_H(SOC, SOC, Op_RegI, 20, r20->as_VMReg()->next());
145
146 reg_def R21 (SOC, SOC, Op_RegI, 21, r21->as_VMReg());
147 reg_def R21_H(SOC, SOC, Op_RegI, 21, r21->as_VMReg()->next());
148
149 reg_def R22 (SOC, SOC, Op_RegI, 22, r22->as_VMReg());
150 reg_def R22_H(SOC, SOC, Op_RegI, 22, r22->as_VMReg()->next());
151
152 reg_def R23 (SOC, SOC, Op_RegI, 23, r23->as_VMReg());
153 reg_def R23_H(SOC, SOC, Op_RegI, 23, r23->as_VMReg()->next());
154
155 reg_def R24 (SOC, SOC, Op_RegI, 24, r24->as_VMReg());
156 reg_def R24_H(SOC, SOC, Op_RegI, 24, r24->as_VMReg()->next());
157
158 reg_def R25 (SOC, SOC, Op_RegI, 25, r25->as_VMReg());
159 reg_def R25_H(SOC, SOC, Op_RegI, 25, r25->as_VMReg()->next());
160
161 reg_def R26 (SOC, SOC, Op_RegI, 26, r26->as_VMReg());
162 reg_def R26_H(SOC, SOC, Op_RegI, 26, r26->as_VMReg()->next());
163
164 reg_def R27 (SOC, SOC, Op_RegI, 27, r27->as_VMReg());
165 reg_def R27_H(SOC, SOC, Op_RegI, 27, r27->as_VMReg()->next());
166
167 reg_def R28 (SOC, SOC, Op_RegI, 28, r28->as_VMReg());
168 reg_def R28_H(SOC, SOC, Op_RegI, 28, r28->as_VMReg()->next());
169
170 reg_def R29 (SOC, SOC, Op_RegI, 29, r29->as_VMReg());
171 reg_def R29_H(SOC, SOC, Op_RegI, 29, r29->as_VMReg()->next());
172
173 reg_def R30 (SOC, SOC, Op_RegI, 30, r30->as_VMReg());
174 reg_def R30_H(SOC, SOC, Op_RegI, 30, r30->as_VMReg()->next());
175
176 reg_def R31 (SOC, SOC, Op_RegI, 31, r31->as_VMReg());
177 reg_def R31_H(SOC, SOC, Op_RegI, 31, r31->as_VMReg()->next());
178
179 // Floating Point Registers
180
181 // Specify priority of register selection within phases of register
182 // allocation. Highest priority is first. A useful heuristic is to
183 // give registers a low priority when they are required by machine
184 // instructions, like EAX and EDX on I486, and choose no-save registers
185 // before save-on-call, & save-on-call before save-on-entry. Registers
186 // which participate in fixed calling sequences should come last.
187 // Registers which are used as pairs must fall on an even boundary.
188
189 alloc_class chunk0(R10, R10_H,
190 R11, R11_H,
191 R8, R8_H,
192 R9, R9_H,
193 R12, R12_H,
194 RCX, RCX_H,
195 RBX, RBX_H,
196 RDI, RDI_H,
197 RDX, RDX_H,
198 RSI, RSI_H,
199 RAX, RAX_H,
200 RBP, RBP_H,
201 R13, R13_H,
202 R14, R14_H,
203 R15, R15_H,
204 R16, R16_H,
205 R17, R17_H,
206 R18, R18_H,
207 R19, R19_H,
208 R20, R20_H,
209 R21, R21_H,
210 R22, R22_H,
211 R23, R23_H,
212 R24, R24_H,
213 R25, R25_H,
214 R26, R26_H,
215 R27, R27_H,
216 R28, R28_H,
217 R29, R29_H,
218 R30, R30_H,
219 R31, R31_H,
220 RSP, RSP_H);
221
222
223 //----------Architecture Description Register Classes--------------------------
224 // Several register classes are automatically defined based upon information in
225 // this architecture description.
226 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
227 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
228 //
229
230 // Empty register class.
231 reg_class no_reg();
232
233 // Class for all pointer/long registers including APX extended GPRs.
234 reg_class all_reg(RAX, RAX_H,
235 RDX, RDX_H,
236 RBP, RBP_H,
237 RDI, RDI_H,
238 RSI, RSI_H,
239 RCX, RCX_H,
240 RBX, RBX_H,
241 RSP, RSP_H,
242 R8, R8_H,
243 R9, R9_H,
244 R10, R10_H,
245 R11, R11_H,
246 R12, R12_H,
247 R13, R13_H,
248 R14, R14_H,
249 R15, R15_H,
250 R16, R16_H,
251 R17, R17_H,
252 R18, R18_H,
253 R19, R19_H,
254 R20, R20_H,
255 R21, R21_H,
256 R22, R22_H,
257 R23, R23_H,
258 R24, R24_H,
259 R25, R25_H,
260 R26, R26_H,
261 R27, R27_H,
262 R28, R28_H,
263 R29, R29_H,
264 R30, R30_H,
265 R31, R31_H);
266
267 // Class for all int registers including APX extended GPRs.
268 reg_class all_int_reg(RAX
269 RDX,
270 RBP,
271 RDI,
272 RSI,
273 RCX,
274 RBX,
275 R8,
276 R9,
277 R10,
278 R11,
279 R12,
280 R13,
281 R14,
282 R16,
283 R17,
284 R18,
285 R19,
286 R20,
287 R21,
288 R22,
289 R23,
290 R24,
291 R25,
292 R26,
293 R27,
294 R28,
295 R29,
296 R30,
297 R31);
298
299 // Class for all pointer registers
300 reg_class any_reg %{
301 return _ANY_REG_mask;
302 %}
303
304 // Class for all pointer registers (excluding RSP)
305 reg_class ptr_reg %{
306 return _PTR_REG_mask;
307 %}
308
309 // Class for all pointer registers (excluding RSP and RBP)
310 reg_class ptr_reg_no_rbp %{
311 return _PTR_REG_NO_RBP_mask;
312 %}
313
314 // Class for all pointer registers (excluding RAX and RSP)
315 reg_class ptr_no_rax_reg %{
316 return _PTR_NO_RAX_REG_mask;
317 %}
318
319 // Class for all pointer registers (excluding RAX, RBX, and RSP)
320 reg_class ptr_no_rax_rbx_reg %{
321 return _PTR_NO_RAX_RBX_REG_mask;
322 %}
323
324 // Class for all long registers (excluding RSP)
325 reg_class long_reg %{
326 return _LONG_REG_mask;
327 %}
328
329 // Class for all long registers (excluding RAX, RDX and RSP)
330 reg_class long_no_rax_rdx_reg %{
331 return _LONG_NO_RAX_RDX_REG_mask;
332 %}
333
334 // Class for all long registers (excluding RCX and RSP)
335 reg_class long_no_rcx_reg %{
336 return _LONG_NO_RCX_REG_mask;
337 %}
338
339 // Class for all long registers (excluding RBP and R13)
340 reg_class long_no_rbp_r13_reg %{
341 return _LONG_NO_RBP_R13_REG_mask;
342 %}
343
344 // Class for all int registers (excluding RSP)
345 reg_class int_reg %{
346 return _INT_REG_mask;
347 %}
348
349 // Class for all int registers (excluding RAX, RDX, and RSP)
350 reg_class int_no_rax_rdx_reg %{
351 return _INT_NO_RAX_RDX_REG_mask;
352 %}
353
354 // Class for all int registers (excluding RCX and RSP)
355 reg_class int_no_rcx_reg %{
356 return _INT_NO_RCX_REG_mask;
357 %}
358
359 // Class for all int registers (excluding RBP and R13)
360 reg_class int_no_rbp_r13_reg %{
361 return _INT_NO_RBP_R13_REG_mask;
362 %}
363
364 // Singleton class for RAX pointer register
365 reg_class ptr_rax_reg(RAX, RAX_H);
366
367 // Singleton class for RBX pointer register
368 reg_class ptr_rbx_reg(RBX, RBX_H);
369
370 // Singleton class for RSI pointer register
371 reg_class ptr_rsi_reg(RSI, RSI_H);
372
373 // Singleton class for RBP pointer register
374 reg_class ptr_rbp_reg(RBP, RBP_H);
375
376 // Singleton class for RDI pointer register
377 reg_class ptr_rdi_reg(RDI, RDI_H);
378
379 // Singleton class for stack pointer
380 reg_class ptr_rsp_reg(RSP, RSP_H);
381
382 // Singleton class for TLS pointer
383 reg_class ptr_r15_reg(R15, R15_H);
384
385 // Singleton class for RAX long register
386 reg_class long_rax_reg(RAX, RAX_H);
387
388 // Singleton class for RCX long register
389 reg_class long_rcx_reg(RCX, RCX_H);
390
391 // Singleton class for RDX long register
392 reg_class long_rdx_reg(RDX, RDX_H);
393
394 // Singleton class for R11 long register
395 reg_class long_r11_reg(R11, R11_H);
396
397 // Singleton class for RAX int register
398 reg_class int_rax_reg(RAX);
399
400 // Singleton class for RBX int register
401 reg_class int_rbx_reg(RBX);
402
403 // Singleton class for RCX int register
404 reg_class int_rcx_reg(RCX);
405
406 // Singleton class for RDX int register
407 reg_class int_rdx_reg(RDX);
408
409 // Singleton class for RDI int register
410 reg_class int_rdi_reg(RDI);
411
412 // Singleton class for instruction pointer
413 // reg_class ip_reg(RIP);
414
415 %}
416
417 //----------SOURCE BLOCK-------------------------------------------------------
418 // This is a block of C++ code which provides values, functions, and
419 // definitions necessary in the rest of the architecture description
420
421 source_hpp %{
422
423 #include "peephole_x86_64.hpp"
424
425 bool castLL_is_imm32(const Node* n);
426
427 %}
428
429 source %{
430
431 bool castLL_is_imm32(const Node* n) {
432 assert(n->is_CastLL(), "must be a CastLL");
433 const TypeLong* t = n->bottom_type()->is_long();
434 return (t->_lo == min_jlong || Assembler::is_simm32(t->_lo)) && (t->_hi == max_jlong || Assembler::is_simm32(t->_hi));
435 }
436
437 %}
438
439 // Register masks
440 source_hpp %{
441 extern RegMask _ANY_REG_mask;
442 extern RegMask _PTR_REG_mask;
443 extern RegMask _PTR_REG_NO_RBP_mask;
444 extern RegMask _PTR_NO_RAX_REG_mask;
445 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
446 extern RegMask _LONG_REG_mask;
447 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
448 extern RegMask _LONG_NO_RCX_REG_mask;
449 extern RegMask _LONG_NO_RBP_R13_REG_mask;
450 extern RegMask _INT_REG_mask;
451 extern RegMask _INT_NO_RAX_RDX_REG_mask;
452 extern RegMask _INT_NO_RCX_REG_mask;
453 extern RegMask _INT_NO_RBP_R13_REG_mask;
454 extern RegMask _FLOAT_REG_mask;
455
456 extern RegMask _STACK_OR_PTR_REG_mask;
457 extern RegMask _STACK_OR_LONG_REG_mask;
458 extern RegMask _STACK_OR_INT_REG_mask;
459
460 inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
461 inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; }
462 inline const RegMask& STACK_OR_INT_REG_mask() { return _STACK_OR_INT_REG_mask; }
463
464 %}
465
466 source %{
467 #define RELOC_IMM64 Assembler::imm_operand
468 #define RELOC_DISP32 Assembler::disp32_operand
469
470 #define __ masm->
471
472 RegMask _ANY_REG_mask;
473 RegMask _PTR_REG_mask;
474 RegMask _PTR_REG_NO_RBP_mask;
475 RegMask _PTR_NO_RAX_REG_mask;
476 RegMask _PTR_NO_RAX_RBX_REG_mask;
477 RegMask _LONG_REG_mask;
478 RegMask _LONG_NO_RAX_RDX_REG_mask;
479 RegMask _LONG_NO_RCX_REG_mask;
480 RegMask _LONG_NO_RBP_R13_REG_mask;
481 RegMask _INT_REG_mask;
482 RegMask _INT_NO_RAX_RDX_REG_mask;
483 RegMask _INT_NO_RCX_REG_mask;
484 RegMask _INT_NO_RBP_R13_REG_mask;
485 RegMask _FLOAT_REG_mask;
486 RegMask _STACK_OR_PTR_REG_mask;
487 RegMask _STACK_OR_LONG_REG_mask;
488 RegMask _STACK_OR_INT_REG_mask;
489
490 static bool need_r12_heapbase() {
491 return UseCompressedOops;
492 }
493
494 void reg_mask_init() {
495 constexpr Register egprs[] = {r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30, r31};
496
497 // _ALL_REG_mask is generated by adlc from the all_reg register class below.
498 // We derive a number of subsets from it.
499 _ANY_REG_mask = _ALL_REG_mask;
500
501 if (PreserveFramePointer) {
502 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
503 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
504 }
505 if (need_r12_heapbase()) {
506 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
507 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
508 }
509
510 _PTR_REG_mask = _ANY_REG_mask;
511 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
512 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
513 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
514 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
515 if (!UseAPX) {
516 for (uint i = 0; i < sizeof(egprs)/sizeof(Register); i++) {
517 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(egprs[i]->as_VMReg()));
518 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(egprs[i]->as_VMReg()->next()));
519 }
520 }
521
522 _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
523 _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
524
525 _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
526 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
527 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
528
529 _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
530 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
531 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
532
533 _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
534 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
535 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
536
537
538 _LONG_REG_mask = _PTR_REG_mask;
539 _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
540 _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
541
542 _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
543 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
544 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
545 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
546 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
547
548 _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
549 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
550 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
551
552 _LONG_NO_RBP_R13_REG_mask = _LONG_REG_mask;
553 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
554 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
555 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()));
556 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()->next()));
557
558 _INT_REG_mask = _ALL_INT_REG_mask;
559 if (!UseAPX) {
560 for (uint i = 0; i < sizeof(egprs)/sizeof(Register); i++) {
561 _INT_REG_mask.Remove(OptoReg::as_OptoReg(egprs[i]->as_VMReg()));
562 }
563 }
564
565 if (PreserveFramePointer) {
566 _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
567 }
568 if (need_r12_heapbase()) {
569 _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
570 }
571
572 _STACK_OR_INT_REG_mask = _INT_REG_mask;
573 _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
574
575 _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
576 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
577 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
578
579 _INT_NO_RCX_REG_mask = _INT_REG_mask;
580 _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
581
582 _INT_NO_RBP_R13_REG_mask = _INT_REG_mask;
583 _INT_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
584 _INT_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()));
585
586 // _FLOAT_REG_LEGACY_mask/_FLOAT_REG_EVEX_mask is generated by adlc
587 // from the float_reg_legacy/float_reg_evex register class.
588 _FLOAT_REG_mask = VM_Version::supports_evex() ? _FLOAT_REG_EVEX_mask : _FLOAT_REG_LEGACY_mask;
589 }
590
591 static bool generate_vzeroupper(Compile* C) {
592 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
593 }
594
595 static int clear_avx_size() {
596 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
597 }
598
599 // !!!!! Special hack to get all types of calls to specify the byte offset
600 // from the start of the call to the point where the return address
601 // will point.
602 int MachCallStaticJavaNode::ret_addr_offset()
603 {
604 int offset = 5; // 5 bytes from start of call to where return address points
605 offset += clear_avx_size();
606 return offset;
607 }
608
609 int MachCallDynamicJavaNode::ret_addr_offset()
610 {
611 int offset = 15; // 15 bytes from start of call to where return address points
612 offset += clear_avx_size();
613 return offset;
614 }
615
616 int MachCallRuntimeNode::ret_addr_offset() {
617 int offset = 13; // movq r10,#addr; callq (r10)
618 if (this->ideal_Opcode() != Op_CallLeafVector) {
619 offset += clear_avx_size();
620 }
621 return offset;
622 }
623 //
624 // Compute padding required for nodes which need alignment
625 //
626
627 // The address of the call instruction needs to be 4-byte aligned to
628 // ensure that it does not span a cache line so that it can be patched.
629 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
630 {
631 current_offset += clear_avx_size(); // skip vzeroupper
632 current_offset += 1; // skip call opcode byte
633 return align_up(current_offset, alignment_required()) - current_offset;
634 }
635
636 // The address of the call instruction needs to be 4-byte aligned to
637 // ensure that it does not span a cache line so that it can be patched.
638 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
639 {
640 current_offset += clear_avx_size(); // skip vzeroupper
641 current_offset += 11; // skip movq instruction + call opcode byte
642 return align_up(current_offset, alignment_required()) - current_offset;
643 }
644
645 // This could be in MacroAssembler but it's fairly C2 specific
646 static void emit_cmpfp_fixup(MacroAssembler* masm) {
647 Label exit;
648 __ jccb(Assembler::noParity, exit);
649 __ pushf();
650 //
651 // comiss/ucomiss instructions set ZF,PF,CF flags and
652 // zero OF,AF,SF for NaN values.
653 // Fixup flags by zeroing ZF,PF so that compare of NaN
654 // values returns 'less than' result (CF is set).
655 // Leave the rest of flags unchanged.
656 //
657 // 7 6 5 4 3 2 1 0
658 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
659 // 0 0 1 0 1 0 1 1 (0x2B)
660 //
661 __ andq(Address(rsp, 0), 0xffffff2b);
662 __ popf();
663 __ bind(exit);
664 }
665
666 static void emit_cmpfp3(MacroAssembler* masm, Register dst) {
667 Label done;
668 __ movl(dst, -1);
669 __ jcc(Assembler::parity, done);
670 __ jcc(Assembler::below, done);
671 __ setcc(Assembler::notEqual, dst);
672 __ bind(done);
673 }
674
675 // Math.min() # Math.max()
676 // --------------------------
677 // ucomis[s/d] #
678 // ja -> b # a
679 // jp -> NaN # NaN
680 // jb -> a # b
681 // je #
682 // |-jz -> a | b # a & b
683 // | -> a #
684 static void emit_fp_min_max(MacroAssembler* masm, XMMRegister dst,
685 XMMRegister a, XMMRegister b,
686 XMMRegister xmmt, Register rt,
687 bool min, bool single) {
688
689 Label nan, zero, below, above, done;
690
691 if (single)
692 __ ucomiss(a, b);
693 else
694 __ ucomisd(a, b);
695
696 if (dst->encoding() != (min ? b : a)->encoding())
697 __ jccb(Assembler::above, above); // CF=0 & ZF=0
698 else
699 __ jccb(Assembler::above, done);
700
701 __ jccb(Assembler::parity, nan); // PF=1
702 __ jccb(Assembler::below, below); // CF=1
703
704 // equal
705 __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
706 if (single) {
707 __ ucomiss(a, xmmt);
708 __ jccb(Assembler::equal, zero);
709
710 __ movflt(dst, a);
711 __ jmp(done);
712 }
713 else {
714 __ ucomisd(a, xmmt);
715 __ jccb(Assembler::equal, zero);
716
717 __ movdbl(dst, a);
718 __ jmp(done);
719 }
720
721 __ bind(zero);
722 if (min)
723 __ vpor(dst, a, b, Assembler::AVX_128bit);
724 else
725 __ vpand(dst, a, b, Assembler::AVX_128bit);
726
727 __ jmp(done);
728
729 __ bind(above);
730 if (single)
731 __ movflt(dst, min ? b : a);
732 else
733 __ movdbl(dst, min ? b : a);
734
735 __ jmp(done);
736
737 __ bind(nan);
738 if (single) {
739 __ movl(rt, 0x7fc00000); // Float.NaN
740 __ movdl(dst, rt);
741 }
742 else {
743 __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
744 __ movdq(dst, rt);
745 }
746 __ jmp(done);
747
748 __ bind(below);
749 if (single)
750 __ movflt(dst, min ? a : b);
751 else
752 __ movdbl(dst, min ? a : b);
753
754 __ bind(done);
755 }
756
757 //=============================================================================
758 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
759
760 int ConstantTable::calculate_table_base_offset() const {
761 return 0; // absolute addressing, no offset
762 }
763
764 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
765 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
766 ShouldNotReachHere();
767 }
768
769 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
770 // Empty encoding
771 }
772
773 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
774 return 0;
775 }
776
777 #ifndef PRODUCT
778 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
779 st->print("# MachConstantBaseNode (empty encoding)");
780 }
781 #endif
782
783
784 //=============================================================================
785 #ifndef PRODUCT
786 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
787 Compile* C = ra_->C;
788
789 int framesize = C->output()->frame_size_in_bytes();
790 int bangsize = C->output()->bang_size_in_bytes();
791 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
792 // Remove wordSize for return addr which is already pushed.
793 framesize -= wordSize;
794
795 if (C->output()->need_stack_bang(bangsize)) {
796 framesize -= wordSize;
797 st->print("# stack bang (%d bytes)", bangsize);
798 st->print("\n\t");
799 st->print("pushq rbp\t# Save rbp");
800 if (PreserveFramePointer) {
801 st->print("\n\t");
802 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
803 }
804 if (framesize) {
805 st->print("\n\t");
806 st->print("subq rsp, #%d\t# Create frame",framesize);
807 }
808 } else {
809 st->print("subq rsp, #%d\t# Create frame",framesize);
810 st->print("\n\t");
811 framesize -= wordSize;
812 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
813 if (PreserveFramePointer) {
814 st->print("\n\t");
815 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
816 if (framesize > 0) {
817 st->print("\n\t");
818 st->print("addq rbp, #%d", framesize);
819 }
820 }
821 }
822
823 if (VerifyStackAtCalls) {
824 st->print("\n\t");
825 framesize -= wordSize;
826 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
827 #ifdef ASSERT
828 st->print("\n\t");
829 st->print("# stack alignment check");
830 #endif
831 }
832 if (C->stub_function() != nullptr) {
833 st->print("\n\t");
834 st->print("cmpl [r15_thread + #disarmed_guard_value_offset], #disarmed_guard_value\t");
835 st->print("\n\t");
836 st->print("je fast_entry\t");
837 st->print("\n\t");
838 st->print("call #nmethod_entry_barrier_stub\t");
839 st->print("\n\tfast_entry:");
840 }
841 st->cr();
842 }
843 #endif
844
845 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
846 Compile* C = ra_->C;
847
848 int framesize = C->output()->frame_size_in_bytes();
849 int bangsize = C->output()->bang_size_in_bytes();
850
851 if (C->clinit_barrier_on_entry()) {
852 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
853 assert(!C->method()->holder()->is_not_initialized() || C->do_clinit_barriers(), "initialization should have been started");
854
855 Label L_skip_barrier;
856 Register klass = rscratch1;
857
858 __ mov_metadata(klass, C->method()->holder()->constant_encoding());
859 __ clinit_barrier(klass, &L_skip_barrier /*L_fast_path*/);
860
861 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
862
863 __ bind(L_skip_barrier);
864 }
865
866 __ verified_entry(framesize, C->output()->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != nullptr);
867
868 C->output()->set_frame_complete(__ offset());
869
870 if (C->has_mach_constant_base_node()) {
871 // NOTE: We set the table base offset here because users might be
872 // emitted before MachConstantBaseNode.
873 ConstantTable& constant_table = C->output()->constant_table();
874 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
875 }
876 }
877
878 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
879 {
880 return MachNode::size(ra_); // too many variables; just compute it
881 // the hard way
882 }
883
884 int MachPrologNode::reloc() const
885 {
886 return 0; // a large enough number
887 }
888
889 //=============================================================================
890 #ifndef PRODUCT
891 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
892 {
893 Compile* C = ra_->C;
894 if (generate_vzeroupper(C)) {
895 st->print("vzeroupper");
896 st->cr(); st->print("\t");
897 }
898
899 int framesize = C->output()->frame_size_in_bytes();
900 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
901 // Remove word for return adr already pushed
902 // and RBP
903 framesize -= 2*wordSize;
904
905 if (framesize) {
906 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
907 st->print("\t");
908 }
909
910 st->print_cr("popq rbp");
911 if (do_polling() && C->is_method_compilation()) {
912 st->print("\t");
913 st->print_cr("cmpq rsp, poll_offset[r15_thread] \n\t"
914 "ja #safepoint_stub\t"
915 "# Safepoint: poll for GC");
916 }
917 }
918 #endif
919
920 void MachEpilogNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
921 {
922 Compile* C = ra_->C;
923
924 if (generate_vzeroupper(C)) {
925 // Clear upper bits of YMM registers when current compiled code uses
926 // wide vectors to avoid AVX <-> SSE transition penalty during call.
927 __ vzeroupper();
928 }
929
930 int framesize = C->output()->frame_size_in_bytes();
931 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
932 // Remove word for return adr already pushed
933 // and RBP
934 framesize -= 2*wordSize;
935
936 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
937
938 if (framesize) {
939 __ addq(rsp, framesize);
940 }
941
942 __ popq(rbp);
943
944 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
945 __ reserved_stack_check();
946 }
947
948 if (do_polling() && C->is_method_compilation()) {
949 Label dummy_label;
950 Label* code_stub = &dummy_label;
951 if (!C->output()->in_scratch_emit_size()) {
952 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
953 C->output()->add_stub(stub);
954 code_stub = &stub->entry();
955 }
956 __ relocate(relocInfo::poll_return_type);
957 __ safepoint_poll(*code_stub, true /* at_return */, true /* in_nmethod */);
958 }
959 }
960
961 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
962 {
963 return MachNode::size(ra_); // too many variables; just compute it
964 // the hard way
965 }
966
967 int MachEpilogNode::reloc() const
968 {
969 return 2; // a large enough number
970 }
971
972 const Pipeline* MachEpilogNode::pipeline() const
973 {
974 return MachNode::pipeline_class();
975 }
976
977 //=============================================================================
978
979 enum RC {
980 rc_bad,
981 rc_int,
982 rc_kreg,
983 rc_float,
984 rc_stack
985 };
986
987 static enum RC rc_class(OptoReg::Name reg)
988 {
989 if( !OptoReg::is_valid(reg) ) return rc_bad;
990
991 if (OptoReg::is_stack(reg)) return rc_stack;
992
993 VMReg r = OptoReg::as_VMReg(reg);
994
995 if (r->is_Register()) return rc_int;
996
997 if (r->is_KRegister()) return rc_kreg;
998
999 assert(r->is_XMMRegister(), "must be");
1000 return rc_float;
1001 }
1002
1003 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1004 static void vec_mov_helper(C2_MacroAssembler *masm, int src_lo, int dst_lo,
1005 int src_hi, int dst_hi, uint ireg, outputStream* st);
1006
1007 void vec_spill_helper(C2_MacroAssembler *masm, bool is_load,
1008 int stack_offset, int reg, uint ireg, outputStream* st);
1009
1010 static void vec_stack_to_stack_helper(C2_MacroAssembler *masm, int src_offset,
1011 int dst_offset, uint ireg, outputStream* st) {
1012 if (masm) {
1013 switch (ireg) {
1014 case Op_VecS:
1015 __ movq(Address(rsp, -8), rax);
1016 __ movl(rax, Address(rsp, src_offset));
1017 __ movl(Address(rsp, dst_offset), rax);
1018 __ movq(rax, Address(rsp, -8));
1019 break;
1020 case Op_VecD:
1021 __ pushq(Address(rsp, src_offset));
1022 __ popq (Address(rsp, dst_offset));
1023 break;
1024 case Op_VecX:
1025 __ pushq(Address(rsp, src_offset));
1026 __ popq (Address(rsp, dst_offset));
1027 __ pushq(Address(rsp, src_offset+8));
1028 __ popq (Address(rsp, dst_offset+8));
1029 break;
1030 case Op_VecY:
1031 __ vmovdqu(Address(rsp, -32), xmm0);
1032 __ vmovdqu(xmm0, Address(rsp, src_offset));
1033 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1034 __ vmovdqu(xmm0, Address(rsp, -32));
1035 break;
1036 case Op_VecZ:
1037 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1038 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1039 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1040 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1041 break;
1042 default:
1043 ShouldNotReachHere();
1044 }
1045 #ifndef PRODUCT
1046 } else {
1047 switch (ireg) {
1048 case Op_VecS:
1049 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1050 "movl rax, [rsp + #%d]\n\t"
1051 "movl [rsp + #%d], rax\n\t"
1052 "movq rax, [rsp - #8]",
1053 src_offset, dst_offset);
1054 break;
1055 case Op_VecD:
1056 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1057 "popq [rsp + #%d]",
1058 src_offset, dst_offset);
1059 break;
1060 case Op_VecX:
1061 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1062 "popq [rsp + #%d]\n\t"
1063 "pushq [rsp + #%d]\n\t"
1064 "popq [rsp + #%d]",
1065 src_offset, dst_offset, src_offset+8, dst_offset+8);
1066 break;
1067 case Op_VecY:
1068 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1069 "vmovdqu xmm0, [rsp + #%d]\n\t"
1070 "vmovdqu [rsp + #%d], xmm0\n\t"
1071 "vmovdqu xmm0, [rsp - #32]",
1072 src_offset, dst_offset);
1073 break;
1074 case Op_VecZ:
1075 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1076 "vmovdqu xmm0, [rsp + #%d]\n\t"
1077 "vmovdqu [rsp + #%d], xmm0\n\t"
1078 "vmovdqu xmm0, [rsp - #64]",
1079 src_offset, dst_offset);
1080 break;
1081 default:
1082 ShouldNotReachHere();
1083 }
1084 #endif
1085 }
1086 }
1087
1088 uint MachSpillCopyNode::implementation(C2_MacroAssembler* masm,
1089 PhaseRegAlloc* ra_,
1090 bool do_size,
1091 outputStream* st) const {
1092 assert(masm != nullptr || st != nullptr, "sanity");
1093 // Get registers to move
1094 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1095 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1096 OptoReg::Name dst_second = ra_->get_reg_second(this);
1097 OptoReg::Name dst_first = ra_->get_reg_first(this);
1098
1099 enum RC src_second_rc = rc_class(src_second);
1100 enum RC src_first_rc = rc_class(src_first);
1101 enum RC dst_second_rc = rc_class(dst_second);
1102 enum RC dst_first_rc = rc_class(dst_first);
1103
1104 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1105 "must move at least 1 register" );
1106
1107 if (src_first == dst_first && src_second == dst_second) {
1108 // Self copy, no move
1109 return 0;
1110 }
1111 if (bottom_type()->isa_vect() != nullptr && bottom_type()->isa_vectmask() == nullptr) {
1112 uint ireg = ideal_reg();
1113 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1114 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1115 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1116 // mem -> mem
1117 int src_offset = ra_->reg2offset(src_first);
1118 int dst_offset = ra_->reg2offset(dst_first);
1119 vec_stack_to_stack_helper(masm, src_offset, dst_offset, ireg, st);
1120 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1121 vec_mov_helper(masm, src_first, dst_first, src_second, dst_second, ireg, st);
1122 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1123 int stack_offset = ra_->reg2offset(dst_first);
1124 vec_spill_helper(masm, false, stack_offset, src_first, ireg, st);
1125 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1126 int stack_offset = ra_->reg2offset(src_first);
1127 vec_spill_helper(masm, true, stack_offset, dst_first, ireg, st);
1128 } else {
1129 ShouldNotReachHere();
1130 }
1131 return 0;
1132 }
1133 if (src_first_rc == rc_stack) {
1134 // mem ->
1135 if (dst_first_rc == rc_stack) {
1136 // mem -> mem
1137 assert(src_second != dst_first, "overlap");
1138 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1139 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1140 // 64-bit
1141 int src_offset = ra_->reg2offset(src_first);
1142 int dst_offset = ra_->reg2offset(dst_first);
1143 if (masm) {
1144 __ pushq(Address(rsp, src_offset));
1145 __ popq (Address(rsp, dst_offset));
1146 #ifndef PRODUCT
1147 } else {
1148 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1149 "popq [rsp + #%d]",
1150 src_offset, dst_offset);
1151 #endif
1152 }
1153 } else {
1154 // 32-bit
1155 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1156 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1157 // No pushl/popl, so:
1158 int src_offset = ra_->reg2offset(src_first);
1159 int dst_offset = ra_->reg2offset(dst_first);
1160 if (masm) {
1161 __ movq(Address(rsp, -8), rax);
1162 __ movl(rax, Address(rsp, src_offset));
1163 __ movl(Address(rsp, dst_offset), rax);
1164 __ movq(rax, Address(rsp, -8));
1165 #ifndef PRODUCT
1166 } else {
1167 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1168 "movl rax, [rsp + #%d]\n\t"
1169 "movl [rsp + #%d], rax\n\t"
1170 "movq rax, [rsp - #8]",
1171 src_offset, dst_offset);
1172 #endif
1173 }
1174 }
1175 return 0;
1176 } else if (dst_first_rc == rc_int) {
1177 // mem -> gpr
1178 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1179 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1180 // 64-bit
1181 int offset = ra_->reg2offset(src_first);
1182 if (masm) {
1183 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1184 #ifndef PRODUCT
1185 } else {
1186 st->print("movq %s, [rsp + #%d]\t# spill",
1187 Matcher::regName[dst_first],
1188 offset);
1189 #endif
1190 }
1191 } else {
1192 // 32-bit
1193 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1194 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1195 int offset = ra_->reg2offset(src_first);
1196 if (masm) {
1197 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1198 #ifndef PRODUCT
1199 } else {
1200 st->print("movl %s, [rsp + #%d]\t# spill",
1201 Matcher::regName[dst_first],
1202 offset);
1203 #endif
1204 }
1205 }
1206 return 0;
1207 } else if (dst_first_rc == rc_float) {
1208 // mem-> xmm
1209 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1210 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1211 // 64-bit
1212 int offset = ra_->reg2offset(src_first);
1213 if (masm) {
1214 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1215 #ifndef PRODUCT
1216 } else {
1217 st->print("%s %s, [rsp + #%d]\t# spill",
1218 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1219 Matcher::regName[dst_first],
1220 offset);
1221 #endif
1222 }
1223 } else {
1224 // 32-bit
1225 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1226 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1227 int offset = ra_->reg2offset(src_first);
1228 if (masm) {
1229 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1230 #ifndef PRODUCT
1231 } else {
1232 st->print("movss %s, [rsp + #%d]\t# spill",
1233 Matcher::regName[dst_first],
1234 offset);
1235 #endif
1236 }
1237 }
1238 return 0;
1239 } else if (dst_first_rc == rc_kreg) {
1240 // mem -> kreg
1241 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1242 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1243 // 64-bit
1244 int offset = ra_->reg2offset(src_first);
1245 if (masm) {
1246 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1247 #ifndef PRODUCT
1248 } else {
1249 st->print("kmovq %s, [rsp + #%d]\t# spill",
1250 Matcher::regName[dst_first],
1251 offset);
1252 #endif
1253 }
1254 }
1255 return 0;
1256 }
1257 } else if (src_first_rc == rc_int) {
1258 // gpr ->
1259 if (dst_first_rc == rc_stack) {
1260 // gpr -> mem
1261 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1262 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1263 // 64-bit
1264 int offset = ra_->reg2offset(dst_first);
1265 if (masm) {
1266 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1267 #ifndef PRODUCT
1268 } else {
1269 st->print("movq [rsp + #%d], %s\t# spill",
1270 offset,
1271 Matcher::regName[src_first]);
1272 #endif
1273 }
1274 } else {
1275 // 32-bit
1276 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1277 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1278 int offset = ra_->reg2offset(dst_first);
1279 if (masm) {
1280 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1281 #ifndef PRODUCT
1282 } else {
1283 st->print("movl [rsp + #%d], %s\t# spill",
1284 offset,
1285 Matcher::regName[src_first]);
1286 #endif
1287 }
1288 }
1289 return 0;
1290 } else if (dst_first_rc == rc_int) {
1291 // gpr -> gpr
1292 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1293 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1294 // 64-bit
1295 if (masm) {
1296 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1297 as_Register(Matcher::_regEncode[src_first]));
1298 #ifndef PRODUCT
1299 } else {
1300 st->print("movq %s, %s\t# spill",
1301 Matcher::regName[dst_first],
1302 Matcher::regName[src_first]);
1303 #endif
1304 }
1305 return 0;
1306 } else {
1307 // 32-bit
1308 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1309 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1310 if (masm) {
1311 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1312 as_Register(Matcher::_regEncode[src_first]));
1313 #ifndef PRODUCT
1314 } else {
1315 st->print("movl %s, %s\t# spill",
1316 Matcher::regName[dst_first],
1317 Matcher::regName[src_first]);
1318 #endif
1319 }
1320 return 0;
1321 }
1322 } else if (dst_first_rc == rc_float) {
1323 // gpr -> xmm
1324 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1325 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1326 // 64-bit
1327 if (masm) {
1328 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1329 #ifndef PRODUCT
1330 } else {
1331 st->print("movdq %s, %s\t# spill",
1332 Matcher::regName[dst_first],
1333 Matcher::regName[src_first]);
1334 #endif
1335 }
1336 } else {
1337 // 32-bit
1338 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1339 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1340 if (masm) {
1341 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1342 #ifndef PRODUCT
1343 } else {
1344 st->print("movdl %s, %s\t# spill",
1345 Matcher::regName[dst_first],
1346 Matcher::regName[src_first]);
1347 #endif
1348 }
1349 }
1350 return 0;
1351 } else if (dst_first_rc == rc_kreg) {
1352 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1353 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1354 // 64-bit
1355 if (masm) {
1356 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1357 #ifndef PRODUCT
1358 } else {
1359 st->print("kmovq %s, %s\t# spill",
1360 Matcher::regName[dst_first],
1361 Matcher::regName[src_first]);
1362 #endif
1363 }
1364 }
1365 Unimplemented();
1366 return 0;
1367 }
1368 } else if (src_first_rc == rc_float) {
1369 // xmm ->
1370 if (dst_first_rc == rc_stack) {
1371 // xmm -> mem
1372 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1373 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1374 // 64-bit
1375 int offset = ra_->reg2offset(dst_first);
1376 if (masm) {
1377 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1378 #ifndef PRODUCT
1379 } else {
1380 st->print("movsd [rsp + #%d], %s\t# spill",
1381 offset,
1382 Matcher::regName[src_first]);
1383 #endif
1384 }
1385 } else {
1386 // 32-bit
1387 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1388 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1389 int offset = ra_->reg2offset(dst_first);
1390 if (masm) {
1391 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1392 #ifndef PRODUCT
1393 } else {
1394 st->print("movss [rsp + #%d], %s\t# spill",
1395 offset,
1396 Matcher::regName[src_first]);
1397 #endif
1398 }
1399 }
1400 return 0;
1401 } else if (dst_first_rc == rc_int) {
1402 // xmm -> gpr
1403 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1404 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1405 // 64-bit
1406 if (masm) {
1407 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1408 #ifndef PRODUCT
1409 } else {
1410 st->print("movdq %s, %s\t# spill",
1411 Matcher::regName[dst_first],
1412 Matcher::regName[src_first]);
1413 #endif
1414 }
1415 } else {
1416 // 32-bit
1417 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1418 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1419 if (masm) {
1420 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1421 #ifndef PRODUCT
1422 } else {
1423 st->print("movdl %s, %s\t# spill",
1424 Matcher::regName[dst_first],
1425 Matcher::regName[src_first]);
1426 #endif
1427 }
1428 }
1429 return 0;
1430 } else if (dst_first_rc == rc_float) {
1431 // xmm -> xmm
1432 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1433 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1434 // 64-bit
1435 if (masm) {
1436 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1437 #ifndef PRODUCT
1438 } else {
1439 st->print("%s %s, %s\t# spill",
1440 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1441 Matcher::regName[dst_first],
1442 Matcher::regName[src_first]);
1443 #endif
1444 }
1445 } else {
1446 // 32-bit
1447 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1448 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1449 if (masm) {
1450 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1451 #ifndef PRODUCT
1452 } else {
1453 st->print("%s %s, %s\t# spill",
1454 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1455 Matcher::regName[dst_first],
1456 Matcher::regName[src_first]);
1457 #endif
1458 }
1459 }
1460 return 0;
1461 } else if (dst_first_rc == rc_kreg) {
1462 assert(false, "Illegal spilling");
1463 return 0;
1464 }
1465 } else if (src_first_rc == rc_kreg) {
1466 if (dst_first_rc == rc_stack) {
1467 // mem -> kreg
1468 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1469 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1470 // 64-bit
1471 int offset = ra_->reg2offset(dst_first);
1472 if (masm) {
1473 __ kmov(Address(rsp, offset), as_KRegister(Matcher::_regEncode[src_first]));
1474 #ifndef PRODUCT
1475 } else {
1476 st->print("kmovq [rsp + #%d] , %s\t# spill",
1477 offset,
1478 Matcher::regName[src_first]);
1479 #endif
1480 }
1481 }
1482 return 0;
1483 } else if (dst_first_rc == rc_int) {
1484 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1485 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1486 // 64-bit
1487 if (masm) {
1488 __ kmov(as_Register(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
1489 #ifndef PRODUCT
1490 } else {
1491 st->print("kmovq %s, %s\t# spill",
1492 Matcher::regName[dst_first],
1493 Matcher::regName[src_first]);
1494 #endif
1495 }
1496 }
1497 Unimplemented();
1498 return 0;
1499 } else if (dst_first_rc == rc_kreg) {
1500 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1501 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1502 // 64-bit
1503 if (masm) {
1504 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
1505 #ifndef PRODUCT
1506 } else {
1507 st->print("kmovq %s, %s\t# spill",
1508 Matcher::regName[dst_first],
1509 Matcher::regName[src_first]);
1510 #endif
1511 }
1512 }
1513 return 0;
1514 } else if (dst_first_rc == rc_float) {
1515 assert(false, "Illegal spill");
1516 return 0;
1517 }
1518 }
1519
1520 assert(0," foo ");
1521 Unimplemented();
1522 return 0;
1523 }
1524
1525 #ifndef PRODUCT
1526 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1527 implementation(nullptr, ra_, false, st);
1528 }
1529 #endif
1530
1531 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1532 implementation(masm, ra_, false, nullptr);
1533 }
1534
1535 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1536 return MachNode::size(ra_);
1537 }
1538
1539 //=============================================================================
1540 #ifndef PRODUCT
1541 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1542 {
1543 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1544 int reg = ra_->get_reg_first(this);
1545 st->print("leaq %s, [rsp + #%d]\t# box lock",
1546 Matcher::regName[reg], offset);
1547 }
1548 #endif
1549
1550 void BoxLockNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1551 {
1552 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1553 int reg = ra_->get_encode(this);
1554
1555 __ lea(as_Register(reg), Address(rsp, offset));
1556 }
1557
1558 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1559 {
1560 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1561 if (ra_->get_encode(this) > 15) {
1562 return (offset < 0x80) ? 6 : 9; // REX2
1563 } else {
1564 return (offset < 0x80) ? 5 : 8; // REX
1565 }
1566 }
1567
1568 //=============================================================================
1569 #ifndef PRODUCT
1570 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1571 {
1572 if (UseCompressedClassPointers) {
1573 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1574 st->print_cr("\tcmpl rscratch1, [rax + CompiledICData::speculated_klass_offset()]\t # Inline cache check");
1575 } else {
1576 st->print_cr("movq rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1577 st->print_cr("\tcmpq rscratch1, [rax + CompiledICData::speculated_klass_offset()]\t # Inline cache check");
1578 }
1579 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1580 }
1581 #endif
1582
1583 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1584 {
1585 __ ic_check(InteriorEntryAlignment);
1586 }
1587
1588 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1589 {
1590 return MachNode::size(ra_); // too many variables; just compute it
1591 // the hard way
1592 }
1593
1594
1595 //=============================================================================
1596
1597 bool Matcher::supports_vector_calling_convention(void) {
1598 return EnableVectorSupport;
1599 }
1600
1601 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1602 assert(EnableVectorSupport, "sanity");
1603 int lo = XMM0_num;
1604 int hi = XMM0b_num;
1605 if (ideal_reg == Op_VecX) hi = XMM0d_num;
1606 else if (ideal_reg == Op_VecY) hi = XMM0h_num;
1607 else if (ideal_reg == Op_VecZ) hi = XMM0p_num;
1608 return OptoRegPair(hi, lo);
1609 }
1610
1611 // Is this branch offset short enough that a short branch can be used?
1612 //
1613 // NOTE: If the platform does not provide any short branch variants, then
1614 // this method should return false for offset 0.
1615 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1616 // The passed offset is relative to address of the branch.
1617 // On 86 a branch displacement is calculated relative to address
1618 // of a next instruction.
1619 offset -= br_size;
1620
1621 // the short version of jmpConUCF2 contains multiple branches,
1622 // making the reach slightly less
1623 if (rule == jmpConUCF2_rule)
1624 return (-126 <= offset && offset <= 125);
1625 return (-128 <= offset && offset <= 127);
1626 }
1627
1628 // Return whether or not this register is ever used as an argument.
1629 // This function is used on startup to build the trampoline stubs in
1630 // generateOptoStub. Registers not mentioned will be killed by the VM
1631 // call in the trampoline, and arguments in those registers not be
1632 // available to the callee.
1633 bool Matcher::can_be_java_arg(int reg)
1634 {
1635 return
1636 reg == RDI_num || reg == RDI_H_num ||
1637 reg == RSI_num || reg == RSI_H_num ||
1638 reg == RDX_num || reg == RDX_H_num ||
1639 reg == RCX_num || reg == RCX_H_num ||
1640 reg == R8_num || reg == R8_H_num ||
1641 reg == R9_num || reg == R9_H_num ||
1642 reg == R12_num || reg == R12_H_num ||
1643 reg == XMM0_num || reg == XMM0b_num ||
1644 reg == XMM1_num || reg == XMM1b_num ||
1645 reg == XMM2_num || reg == XMM2b_num ||
1646 reg == XMM3_num || reg == XMM3b_num ||
1647 reg == XMM4_num || reg == XMM4b_num ||
1648 reg == XMM5_num || reg == XMM5b_num ||
1649 reg == XMM6_num || reg == XMM6b_num ||
1650 reg == XMM7_num || reg == XMM7b_num;
1651 }
1652
1653 bool Matcher::is_spillable_arg(int reg)
1654 {
1655 return can_be_java_arg(reg);
1656 }
1657
1658 uint Matcher::int_pressure_limit()
1659 {
1660 return (INTPRESSURE == -1) ? _INT_REG_mask.Size() : INTPRESSURE;
1661 }
1662
1663 uint Matcher::float_pressure_limit()
1664 {
1665 // After experiment around with different values, the following default threshold
1666 // works best for LCM's register pressure scheduling on x64.
1667 uint dec_count = VM_Version::supports_evex() ? 4 : 2;
1668 uint default_float_pressure_threshold = _FLOAT_REG_mask.Size() - dec_count;
1669 return (FLOATPRESSURE == -1) ? default_float_pressure_threshold : FLOATPRESSURE;
1670 }
1671
1672 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1673 // In 64 bit mode a code which use multiply when
1674 // devisor is constant is faster than hardware
1675 // DIV instruction (it uses MulHiL).
1676 return false;
1677 }
1678
1679 // Register for DIVI projection of divmodI
1680 RegMask Matcher::divI_proj_mask() {
1681 return INT_RAX_REG_mask();
1682 }
1683
1684 // Register for MODI projection of divmodI
1685 RegMask Matcher::modI_proj_mask() {
1686 return INT_RDX_REG_mask();
1687 }
1688
1689 // Register for DIVL projection of divmodL
1690 RegMask Matcher::divL_proj_mask() {
1691 return LONG_RAX_REG_mask();
1692 }
1693
1694 // Register for MODL projection of divmodL
1695 RegMask Matcher::modL_proj_mask() {
1696 return LONG_RDX_REG_mask();
1697 }
1698
1699 // Register for saving SP into on method handle invokes. Not used on x86_64.
1700 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1701 return NO_REG_mask();
1702 }
1703
1704 %}
1705
1706 //----------ENCODING BLOCK-----------------------------------------------------
1707 // This block specifies the encoding classes used by the compiler to
1708 // output byte streams. Encoding classes are parameterized macros
1709 // used by Machine Instruction Nodes in order to generate the bit
1710 // encoding of the instruction. Operands specify their base encoding
1711 // interface with the interface keyword. There are currently
1712 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1713 // COND_INTER. REG_INTER causes an operand to generate a function
1714 // which returns its register number when queried. CONST_INTER causes
1715 // an operand to generate a function which returns the value of the
1716 // constant when queried. MEMORY_INTER causes an operand to generate
1717 // four functions which return the Base Register, the Index Register,
1718 // the Scale Value, and the Offset Value of the operand when queried.
1719 // COND_INTER causes an operand to generate six functions which return
1720 // the encoding code (ie - encoding bits for the instruction)
1721 // associated with each basic boolean condition for a conditional
1722 // instruction.
1723 //
1724 // Instructions specify two basic values for encoding. Again, a
1725 // function is available to check if the constant displacement is an
1726 // oop. They use the ins_encode keyword to specify their encoding
1727 // classes (which must be a sequence of enc_class names, and their
1728 // parameters, specified in the encoding block), and they use the
1729 // opcode keyword to specify, in order, their primary, secondary, and
1730 // tertiary opcode. Only the opcode sections which a particular
1731 // instruction needs for encoding need to be specified.
1732 encode %{
1733 enc_class cdql_enc(no_rax_rdx_RegI div)
1734 %{
1735 // Full implementation of Java idiv and irem; checks for
1736 // special case as described in JVM spec., p.243 & p.271.
1737 //
1738 // normal case special case
1739 //
1740 // input : rax: dividend min_int
1741 // reg: divisor -1
1742 //
1743 // output: rax: quotient (= rax idiv reg) min_int
1744 // rdx: remainder (= rax irem reg) 0
1745 //
1746 // Code sequnce:
1747 //
1748 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1749 // 5: 75 07/08 jne e <normal>
1750 // 7: 33 d2 xor %edx,%edx
1751 // [div >= 8 -> offset + 1]
1752 // [REX_B]
1753 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1754 // c: 74 03/04 je 11 <done>
1755 // 000000000000000e <normal>:
1756 // e: 99 cltd
1757 // [div >= 8 -> offset + 1]
1758 // [REX_B]
1759 // f: f7 f9 idiv $div
1760 // 0000000000000011 <done>:
1761 Label normal;
1762 Label done;
1763
1764 // cmp $0x80000000,%eax
1765 __ cmpl(as_Register(RAX_enc), 0x80000000);
1766
1767 // jne e <normal>
1768 __ jccb(Assembler::notEqual, normal);
1769
1770 // xor %edx,%edx
1771 __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
1772
1773 // cmp $0xffffffffffffffff,%ecx
1774 __ cmpl($div$$Register, -1);
1775
1776 // je 11 <done>
1777 __ jccb(Assembler::equal, done);
1778
1779 // <normal>
1780 // cltd
1781 __ bind(normal);
1782 __ cdql();
1783
1784 // idivl
1785 // <done>
1786 __ idivl($div$$Register);
1787 __ bind(done);
1788 %}
1789
1790 enc_class cdqq_enc(no_rax_rdx_RegL div)
1791 %{
1792 // Full implementation of Java ldiv and lrem; checks for
1793 // special case as described in JVM spec., p.243 & p.271.
1794 //
1795 // normal case special case
1796 //
1797 // input : rax: dividend min_long
1798 // reg: divisor -1
1799 //
1800 // output: rax: quotient (= rax idiv reg) min_long
1801 // rdx: remainder (= rax irem reg) 0
1802 //
1803 // Code sequnce:
1804 //
1805 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1806 // 7: 00 00 80
1807 // a: 48 39 d0 cmp %rdx,%rax
1808 // d: 75 08 jne 17 <normal>
1809 // f: 33 d2 xor %edx,%edx
1810 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1811 // 15: 74 05 je 1c <done>
1812 // 0000000000000017 <normal>:
1813 // 17: 48 99 cqto
1814 // 19: 48 f7 f9 idiv $div
1815 // 000000000000001c <done>:
1816 Label normal;
1817 Label done;
1818
1819 // mov $0x8000000000000000,%rdx
1820 __ mov64(as_Register(RDX_enc), 0x8000000000000000);
1821
1822 // cmp %rdx,%rax
1823 __ cmpq(as_Register(RAX_enc), as_Register(RDX_enc));
1824
1825 // jne 17 <normal>
1826 __ jccb(Assembler::notEqual, normal);
1827
1828 // xor %edx,%edx
1829 __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
1830
1831 // cmp $0xffffffffffffffff,$div
1832 __ cmpq($div$$Register, -1);
1833
1834 // je 1e <done>
1835 __ jccb(Assembler::equal, done);
1836
1837 // <normal>
1838 // cqto
1839 __ bind(normal);
1840 __ cdqq();
1841
1842 // idivq (note: must be emitted by the user of this rule)
1843 // <done>
1844 __ idivq($div$$Register);
1845 __ bind(done);
1846 %}
1847
1848 enc_class clear_avx %{
1849 DEBUG_ONLY(int off0 = __ offset());
1850 if (generate_vzeroupper(Compile::current())) {
1851 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
1852 // Clear upper bits of YMM registers when current compiled code uses
1853 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1854 __ vzeroupper();
1855 }
1856 DEBUG_ONLY(int off1 = __ offset());
1857 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
1858 %}
1859
1860 enc_class Java_To_Runtime(method meth) %{
1861 // No relocation needed
1862 if (AOTCodeCache::is_on_for_dump()) {
1863 // Created runtime_call_type relocation when caching code
1864 __ lea(r10, RuntimeAddress((address)$meth$$method));
1865 } else {
1866 __ mov64(r10, (int64_t) $meth$$method);
1867 }
1868 __ call(r10);
1869 __ post_call_nop();
1870 %}
1871
1872 enc_class Java_Static_Call(method meth)
1873 %{
1874 // JAVA STATIC CALL
1875 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
1876 // determine who we intended to call.
1877 if (!_method) {
1878 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, $meth$$method)));
1879 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
1880 // The NOP here is purely to ensure that eliding a call to
1881 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
1882 __ addr_nop_5();
1883 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
1884 } else {
1885 int method_index = resolved_method_index(masm);
1886 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
1887 : static_call_Relocation::spec(method_index);
1888 address mark = __ pc();
1889 int call_offset = __ offset();
1890 __ call(AddressLiteral(CAST_FROM_FN_PTR(address, $meth$$method), rspec));
1891 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
1892 // Calls of the same statically bound method can share
1893 // a stub to the interpreter.
1894 __ code()->shared_stub_to_interp_for(_method, call_offset);
1895 } else {
1896 // Emit stubs for static call.
1897 address stub = CompiledDirectCall::emit_to_interp_stub(masm, mark);
1898 __ clear_inst_mark();
1899 if (stub == nullptr) {
1900 ciEnv::current()->record_failure("CodeCache is full");
1901 return;
1902 }
1903 }
1904 }
1905 __ post_call_nop();
1906 %}
1907
1908 enc_class Java_Dynamic_Call(method meth) %{
1909 __ ic_call((address)$meth$$method, resolved_method_index(masm));
1910 __ post_call_nop();
1911 %}
1912
1913 %}
1914
1915
1916
1917 //----------FRAME--------------------------------------------------------------
1918 // Definition of frame structure and management information.
1919 //
1920 // S T A C K L A Y O U T Allocators stack-slot number
1921 // | (to get allocators register number
1922 // G Owned by | | v add OptoReg::stack0())
1923 // r CALLER | |
1924 // o | +--------+ pad to even-align allocators stack-slot
1925 // w V | pad0 | numbers; owned by CALLER
1926 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
1927 // h ^ | in | 5
1928 // | | args | 4 Holes in incoming args owned by SELF
1929 // | | | | 3
1930 // | | +--------+
1931 // V | | old out| Empty on Intel, window on Sparc
1932 // | old |preserve| Must be even aligned.
1933 // | SP-+--------+----> Matcher::_old_SP, even aligned
1934 // | | in | 3 area for Intel ret address
1935 // Owned by |preserve| Empty on Sparc.
1936 // SELF +--------+
1937 // | | pad2 | 2 pad to align old SP
1938 // | +--------+ 1
1939 // | | locks | 0
1940 // | +--------+----> OptoReg::stack0(), even aligned
1941 // | | pad1 | 11 pad to align new SP
1942 // | +--------+
1943 // | | | 10
1944 // | | spills | 9 spills
1945 // V | | 8 (pad0 slot for callee)
1946 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
1947 // ^ | out | 7
1948 // | | args | 6 Holes in outgoing args owned by CALLEE
1949 // Owned by +--------+
1950 // CALLEE | new out| 6 Empty on Intel, window on Sparc
1951 // | new |preserve| Must be even-aligned.
1952 // | SP-+--------+----> Matcher::_new_SP, even aligned
1953 // | | |
1954 //
1955 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
1956 // known from SELF's arguments and the Java calling convention.
1957 // Region 6-7 is determined per call site.
1958 // Note 2: If the calling convention leaves holes in the incoming argument
1959 // area, those holes are owned by SELF. Holes in the outgoing area
1960 // are owned by the CALLEE. Holes should not be necessary in the
1961 // incoming area, as the Java calling convention is completely under
1962 // the control of the AD file. Doubles can be sorted and packed to
1963 // avoid holes. Holes in the outgoing arguments may be necessary for
1964 // varargs C calling conventions.
1965 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
1966 // even aligned with pad0 as needed.
1967 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
1968 // region 6-11 is even aligned; it may be padded out more so that
1969 // the region from SP to FP meets the minimum stack alignment.
1970 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
1971 // alignment. Region 11, pad1, may be dynamically extended so that
1972 // SP meets the minimum alignment.
1973
1974 frame
1975 %{
1976 // These three registers define part of the calling convention
1977 // between compiled code and the interpreter.
1978 inline_cache_reg(RAX); // Inline Cache Register
1979
1980 // Optional: name the operand used by cisc-spilling to access
1981 // [stack_pointer + offset]
1982 cisc_spilling_operand_name(indOffset32);
1983
1984 // Number of stack slots consumed by locking an object
1985 sync_stack_slots(2);
1986
1987 // Compiled code's Frame Pointer
1988 frame_pointer(RSP);
1989
1990 // Interpreter stores its frame pointer in a register which is
1991 // stored to the stack by I2CAdaptors.
1992 // I2CAdaptors convert from interpreted java to compiled java.
1993 interpreter_frame_pointer(RBP);
1994
1995 // Stack alignment requirement
1996 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
1997
1998 // Number of outgoing stack slots killed above the out_preserve_stack_slots
1999 // for calls to C. Supports the var-args backing area for register parms.
2000 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2001
2002 // The after-PROLOG location of the return address. Location of
2003 // return address specifies a type (REG or STACK) and a number
2004 // representing the register number (i.e. - use a register name) or
2005 // stack slot.
2006 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2007 // Otherwise, it is above the locks and verification slot and alignment word
2008 return_addr(STACK - 2 +
2009 align_up((Compile::current()->in_preserve_stack_slots() +
2010 Compile::current()->fixed_slots()),
2011 stack_alignment_in_slots()));
2012
2013 // Location of compiled Java return values. Same as C for now.
2014 return_value
2015 %{
2016 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2017 "only return normal values");
2018
2019 static const int lo[Op_RegL + 1] = {
2020 0,
2021 0,
2022 RAX_num, // Op_RegN
2023 RAX_num, // Op_RegI
2024 RAX_num, // Op_RegP
2025 XMM0_num, // Op_RegF
2026 XMM0_num, // Op_RegD
2027 RAX_num // Op_RegL
2028 };
2029 static const int hi[Op_RegL + 1] = {
2030 0,
2031 0,
2032 OptoReg::Bad, // Op_RegN
2033 OptoReg::Bad, // Op_RegI
2034 RAX_H_num, // Op_RegP
2035 OptoReg::Bad, // Op_RegF
2036 XMM0b_num, // Op_RegD
2037 RAX_H_num // Op_RegL
2038 };
2039 // Excluded flags and vector registers.
2040 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 8, "missing type");
2041 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2042 %}
2043 %}
2044
2045 //----------ATTRIBUTES---------------------------------------------------------
2046 //----------Operand Attributes-------------------------------------------------
2047 op_attrib op_cost(0); // Required cost attribute
2048
2049 //----------Instruction Attributes---------------------------------------------
2050 ins_attrib ins_cost(100); // Required cost attribute
2051 ins_attrib ins_size(8); // Required size attribute (in bits)
2052 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2053 // a non-matching short branch variant
2054 // of some long branch?
2055 ins_attrib ins_alignment(1); // Required alignment attribute (must
2056 // be a power of 2) specifies the
2057 // alignment that some part of the
2058 // instruction (not necessarily the
2059 // start) requires. If > 1, a
2060 // compute_padding() function must be
2061 // provided for the instruction
2062
2063 //----------OPERANDS-----------------------------------------------------------
2064 // Operand definitions must precede instruction definitions for correct parsing
2065 // in the ADLC because operands constitute user defined types which are used in
2066 // instruction definitions.
2067
2068 //----------Simple Operands----------------------------------------------------
2069 // Immediate Operands
2070 // Integer Immediate
2071 operand immI()
2072 %{
2073 match(ConI);
2074
2075 op_cost(10);
2076 format %{ %}
2077 interface(CONST_INTER);
2078 %}
2079
2080 // Constant for test vs zero
2081 operand immI_0()
2082 %{
2083 predicate(n->get_int() == 0);
2084 match(ConI);
2085
2086 op_cost(0);
2087 format %{ %}
2088 interface(CONST_INTER);
2089 %}
2090
2091 // Constant for increment
2092 operand immI_1()
2093 %{
2094 predicate(n->get_int() == 1);
2095 match(ConI);
2096
2097 op_cost(0);
2098 format %{ %}
2099 interface(CONST_INTER);
2100 %}
2101
2102 // Constant for decrement
2103 operand immI_M1()
2104 %{
2105 predicate(n->get_int() == -1);
2106 match(ConI);
2107
2108 op_cost(0);
2109 format %{ %}
2110 interface(CONST_INTER);
2111 %}
2112
2113 operand immI_2()
2114 %{
2115 predicate(n->get_int() == 2);
2116 match(ConI);
2117
2118 op_cost(0);
2119 format %{ %}
2120 interface(CONST_INTER);
2121 %}
2122
2123 operand immI_4()
2124 %{
2125 predicate(n->get_int() == 4);
2126 match(ConI);
2127
2128 op_cost(0);
2129 format %{ %}
2130 interface(CONST_INTER);
2131 %}
2132
2133 operand immI_8()
2134 %{
2135 predicate(n->get_int() == 8);
2136 match(ConI);
2137
2138 op_cost(0);
2139 format %{ %}
2140 interface(CONST_INTER);
2141 %}
2142
2143 // Valid scale values for addressing modes
2144 operand immI2()
2145 %{
2146 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2147 match(ConI);
2148
2149 format %{ %}
2150 interface(CONST_INTER);
2151 %}
2152
2153 operand immU7()
2154 %{
2155 predicate((0 <= n->get_int()) && (n->get_int() <= 0x7F));
2156 match(ConI);
2157
2158 op_cost(5);
2159 format %{ %}
2160 interface(CONST_INTER);
2161 %}
2162
2163 operand immI8()
2164 %{
2165 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2166 match(ConI);
2167
2168 op_cost(5);
2169 format %{ %}
2170 interface(CONST_INTER);
2171 %}
2172
2173 operand immU8()
2174 %{
2175 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2176 match(ConI);
2177
2178 op_cost(5);
2179 format %{ %}
2180 interface(CONST_INTER);
2181 %}
2182
2183 operand immI16()
2184 %{
2185 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2186 match(ConI);
2187
2188 op_cost(10);
2189 format %{ %}
2190 interface(CONST_INTER);
2191 %}
2192
2193 // Int Immediate non-negative
2194 operand immU31()
2195 %{
2196 predicate(n->get_int() >= 0);
2197 match(ConI);
2198
2199 op_cost(0);
2200 format %{ %}
2201 interface(CONST_INTER);
2202 %}
2203
2204 // Pointer Immediate
2205 operand immP()
2206 %{
2207 match(ConP);
2208
2209 op_cost(10);
2210 format %{ %}
2211 interface(CONST_INTER);
2212 %}
2213
2214 // Null Pointer Immediate
2215 operand immP0()
2216 %{
2217 predicate(n->get_ptr() == 0);
2218 match(ConP);
2219
2220 op_cost(5);
2221 format %{ %}
2222 interface(CONST_INTER);
2223 %}
2224
2225 // Pointer Immediate
2226 operand immN() %{
2227 match(ConN);
2228
2229 op_cost(10);
2230 format %{ %}
2231 interface(CONST_INTER);
2232 %}
2233
2234 operand immNKlass() %{
2235 match(ConNKlass);
2236
2237 op_cost(10);
2238 format %{ %}
2239 interface(CONST_INTER);
2240 %}
2241
2242 // Null Pointer Immediate
2243 operand immN0() %{
2244 predicate(n->get_narrowcon() == 0);
2245 match(ConN);
2246
2247 op_cost(5);
2248 format %{ %}
2249 interface(CONST_INTER);
2250 %}
2251
2252 operand immP31()
2253 %{
2254 predicate(n->as_Type()->type()->reloc() == relocInfo::none
2255 && (n->get_ptr() >> 31) == 0);
2256 match(ConP);
2257
2258 op_cost(5);
2259 format %{ %}
2260 interface(CONST_INTER);
2261 %}
2262
2263
2264 // Long Immediate
2265 operand immL()
2266 %{
2267 match(ConL);
2268
2269 op_cost(20);
2270 format %{ %}
2271 interface(CONST_INTER);
2272 %}
2273
2274 // Long Immediate 8-bit
2275 operand immL8()
2276 %{
2277 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
2278 match(ConL);
2279
2280 op_cost(5);
2281 format %{ %}
2282 interface(CONST_INTER);
2283 %}
2284
2285 // Long Immediate 32-bit unsigned
2286 operand immUL32()
2287 %{
2288 predicate(n->get_long() == (unsigned int) (n->get_long()));
2289 match(ConL);
2290
2291 op_cost(10);
2292 format %{ %}
2293 interface(CONST_INTER);
2294 %}
2295
2296 // Long Immediate 32-bit signed
2297 operand immL32()
2298 %{
2299 predicate(n->get_long() == (int) (n->get_long()));
2300 match(ConL);
2301
2302 op_cost(15);
2303 format %{ %}
2304 interface(CONST_INTER);
2305 %}
2306
2307 operand immL_Pow2()
2308 %{
2309 predicate(is_power_of_2((julong)n->get_long()));
2310 match(ConL);
2311
2312 op_cost(15);
2313 format %{ %}
2314 interface(CONST_INTER);
2315 %}
2316
2317 operand immL_NotPow2()
2318 %{
2319 predicate(is_power_of_2((julong)~n->get_long()));
2320 match(ConL);
2321
2322 op_cost(15);
2323 format %{ %}
2324 interface(CONST_INTER);
2325 %}
2326
2327 // Long Immediate zero
2328 operand immL0()
2329 %{
2330 predicate(n->get_long() == 0L);
2331 match(ConL);
2332
2333 op_cost(10);
2334 format %{ %}
2335 interface(CONST_INTER);
2336 %}
2337
2338 // Constant for increment
2339 operand immL1()
2340 %{
2341 predicate(n->get_long() == 1);
2342 match(ConL);
2343
2344 format %{ %}
2345 interface(CONST_INTER);
2346 %}
2347
2348 // Constant for decrement
2349 operand immL_M1()
2350 %{
2351 predicate(n->get_long() == -1);
2352 match(ConL);
2353
2354 format %{ %}
2355 interface(CONST_INTER);
2356 %}
2357
2358 // Long Immediate: low 32-bit mask
2359 operand immL_32bits()
2360 %{
2361 predicate(n->get_long() == 0xFFFFFFFFL);
2362 match(ConL);
2363 op_cost(20);
2364
2365 format %{ %}
2366 interface(CONST_INTER);
2367 %}
2368
2369 // Int Immediate: 2^n-1, positive
2370 operand immI_Pow2M1()
2371 %{
2372 predicate((n->get_int() > 0)
2373 && is_power_of_2((juint)n->get_int() + 1));
2374 match(ConI);
2375
2376 op_cost(20);
2377 format %{ %}
2378 interface(CONST_INTER);
2379 %}
2380
2381 // Float Immediate zero
2382 operand immF0()
2383 %{
2384 predicate(jint_cast(n->getf()) == 0);
2385 match(ConF);
2386
2387 op_cost(5);
2388 format %{ %}
2389 interface(CONST_INTER);
2390 %}
2391
2392 // Float Immediate
2393 operand immF()
2394 %{
2395 match(ConF);
2396
2397 op_cost(15);
2398 format %{ %}
2399 interface(CONST_INTER);
2400 %}
2401
2402 // Half Float Immediate
2403 operand immH()
2404 %{
2405 match(ConH);
2406
2407 op_cost(15);
2408 format %{ %}
2409 interface(CONST_INTER);
2410 %}
2411
2412 // Double Immediate zero
2413 operand immD0()
2414 %{
2415 predicate(jlong_cast(n->getd()) == 0);
2416 match(ConD);
2417
2418 op_cost(5);
2419 format %{ %}
2420 interface(CONST_INTER);
2421 %}
2422
2423 // Double Immediate
2424 operand immD()
2425 %{
2426 match(ConD);
2427
2428 op_cost(15);
2429 format %{ %}
2430 interface(CONST_INTER);
2431 %}
2432
2433 // Immediates for special shifts (sign extend)
2434
2435 // Constants for increment
2436 operand immI_16()
2437 %{
2438 predicate(n->get_int() == 16);
2439 match(ConI);
2440
2441 format %{ %}
2442 interface(CONST_INTER);
2443 %}
2444
2445 operand immI_24()
2446 %{
2447 predicate(n->get_int() == 24);
2448 match(ConI);
2449
2450 format %{ %}
2451 interface(CONST_INTER);
2452 %}
2453
2454 // Constant for byte-wide masking
2455 operand immI_255()
2456 %{
2457 predicate(n->get_int() == 255);
2458 match(ConI);
2459
2460 format %{ %}
2461 interface(CONST_INTER);
2462 %}
2463
2464 // Constant for short-wide masking
2465 operand immI_65535()
2466 %{
2467 predicate(n->get_int() == 65535);
2468 match(ConI);
2469
2470 format %{ %}
2471 interface(CONST_INTER);
2472 %}
2473
2474 // Constant for byte-wide masking
2475 operand immL_255()
2476 %{
2477 predicate(n->get_long() == 255);
2478 match(ConL);
2479
2480 format %{ %}
2481 interface(CONST_INTER);
2482 %}
2483
2484 // Constant for short-wide masking
2485 operand immL_65535()
2486 %{
2487 predicate(n->get_long() == 65535);
2488 match(ConL);
2489
2490 format %{ %}
2491 interface(CONST_INTER);
2492 %}
2493
2494 // AOT Runtime Constants Address
2495 operand immAOTRuntimeConstantsAddress()
2496 %{
2497 // Check if the address is in the range of AOT Runtime Constants
2498 predicate(AOTRuntimeConstants::contains((address)(n->get_ptr())));
2499 match(ConP);
2500
2501 op_cost(0);
2502 format %{ %}
2503 interface(CONST_INTER);
2504 %}
2505
2506 operand kReg()
2507 %{
2508 constraint(ALLOC_IN_RC(vectmask_reg));
2509 match(RegVectMask);
2510 format %{%}
2511 interface(REG_INTER);
2512 %}
2513
2514 // Register Operands
2515 // Integer Register
2516 operand rRegI()
2517 %{
2518 constraint(ALLOC_IN_RC(int_reg));
2519 match(RegI);
2520
2521 match(rax_RegI);
2522 match(rbx_RegI);
2523 match(rcx_RegI);
2524 match(rdx_RegI);
2525 match(rdi_RegI);
2526
2527 format %{ %}
2528 interface(REG_INTER);
2529 %}
2530
2531 // Special Registers
2532 operand rax_RegI()
2533 %{
2534 constraint(ALLOC_IN_RC(int_rax_reg));
2535 match(RegI);
2536 match(rRegI);
2537
2538 format %{ "RAX" %}
2539 interface(REG_INTER);
2540 %}
2541
2542 // Special Registers
2543 operand rbx_RegI()
2544 %{
2545 constraint(ALLOC_IN_RC(int_rbx_reg));
2546 match(RegI);
2547 match(rRegI);
2548
2549 format %{ "RBX" %}
2550 interface(REG_INTER);
2551 %}
2552
2553 operand rcx_RegI()
2554 %{
2555 constraint(ALLOC_IN_RC(int_rcx_reg));
2556 match(RegI);
2557 match(rRegI);
2558
2559 format %{ "RCX" %}
2560 interface(REG_INTER);
2561 %}
2562
2563 operand rdx_RegI()
2564 %{
2565 constraint(ALLOC_IN_RC(int_rdx_reg));
2566 match(RegI);
2567 match(rRegI);
2568
2569 format %{ "RDX" %}
2570 interface(REG_INTER);
2571 %}
2572
2573 operand rdi_RegI()
2574 %{
2575 constraint(ALLOC_IN_RC(int_rdi_reg));
2576 match(RegI);
2577 match(rRegI);
2578
2579 format %{ "RDI" %}
2580 interface(REG_INTER);
2581 %}
2582
2583 operand no_rax_rdx_RegI()
2584 %{
2585 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
2586 match(RegI);
2587 match(rbx_RegI);
2588 match(rcx_RegI);
2589 match(rdi_RegI);
2590
2591 format %{ %}
2592 interface(REG_INTER);
2593 %}
2594
2595 operand no_rbp_r13_RegI()
2596 %{
2597 constraint(ALLOC_IN_RC(int_no_rbp_r13_reg));
2598 match(RegI);
2599 match(rRegI);
2600 match(rax_RegI);
2601 match(rbx_RegI);
2602 match(rcx_RegI);
2603 match(rdx_RegI);
2604 match(rdi_RegI);
2605
2606 format %{ %}
2607 interface(REG_INTER);
2608 %}
2609
2610 // Pointer Register
2611 operand any_RegP()
2612 %{
2613 constraint(ALLOC_IN_RC(any_reg));
2614 match(RegP);
2615 match(rax_RegP);
2616 match(rbx_RegP);
2617 match(rdi_RegP);
2618 match(rsi_RegP);
2619 match(rbp_RegP);
2620 match(r15_RegP);
2621 match(rRegP);
2622
2623 format %{ %}
2624 interface(REG_INTER);
2625 %}
2626
2627 operand rRegP()
2628 %{
2629 constraint(ALLOC_IN_RC(ptr_reg));
2630 match(RegP);
2631 match(rax_RegP);
2632 match(rbx_RegP);
2633 match(rdi_RegP);
2634 match(rsi_RegP);
2635 match(rbp_RegP); // See Q&A below about
2636 match(r15_RegP); // r15_RegP and rbp_RegP.
2637
2638 format %{ %}
2639 interface(REG_INTER);
2640 %}
2641
2642 operand rRegN() %{
2643 constraint(ALLOC_IN_RC(int_reg));
2644 match(RegN);
2645
2646 format %{ %}
2647 interface(REG_INTER);
2648 %}
2649
2650 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
2651 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
2652 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
2653 // The output of an instruction is controlled by the allocator, which respects
2654 // register class masks, not match rules. Unless an instruction mentions
2655 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
2656 // by the allocator as an input.
2657 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
2658 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
2659 // result, RBP is not included in the output of the instruction either.
2660
2661 // This operand is not allowed to use RBP even if
2662 // RBP is not used to hold the frame pointer.
2663 operand no_rbp_RegP()
2664 %{
2665 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
2666 match(RegP);
2667 match(rbx_RegP);
2668 match(rsi_RegP);
2669 match(rdi_RegP);
2670
2671 format %{ %}
2672 interface(REG_INTER);
2673 %}
2674
2675 // Special Registers
2676 // Return a pointer value
2677 operand rax_RegP()
2678 %{
2679 constraint(ALLOC_IN_RC(ptr_rax_reg));
2680 match(RegP);
2681 match(rRegP);
2682
2683 format %{ %}
2684 interface(REG_INTER);
2685 %}
2686
2687 // Special Registers
2688 // Return a compressed pointer value
2689 operand rax_RegN()
2690 %{
2691 constraint(ALLOC_IN_RC(int_rax_reg));
2692 match(RegN);
2693 match(rRegN);
2694
2695 format %{ %}
2696 interface(REG_INTER);
2697 %}
2698
2699 // Used in AtomicAdd
2700 operand rbx_RegP()
2701 %{
2702 constraint(ALLOC_IN_RC(ptr_rbx_reg));
2703 match(RegP);
2704 match(rRegP);
2705
2706 format %{ %}
2707 interface(REG_INTER);
2708 %}
2709
2710 operand rsi_RegP()
2711 %{
2712 constraint(ALLOC_IN_RC(ptr_rsi_reg));
2713 match(RegP);
2714 match(rRegP);
2715
2716 format %{ %}
2717 interface(REG_INTER);
2718 %}
2719
2720 operand rbp_RegP()
2721 %{
2722 constraint(ALLOC_IN_RC(ptr_rbp_reg));
2723 match(RegP);
2724 match(rRegP);
2725
2726 format %{ %}
2727 interface(REG_INTER);
2728 %}
2729
2730 // Used in rep stosq
2731 operand rdi_RegP()
2732 %{
2733 constraint(ALLOC_IN_RC(ptr_rdi_reg));
2734 match(RegP);
2735 match(rRegP);
2736
2737 format %{ %}
2738 interface(REG_INTER);
2739 %}
2740
2741 operand r15_RegP()
2742 %{
2743 constraint(ALLOC_IN_RC(ptr_r15_reg));
2744 match(RegP);
2745 match(rRegP);
2746
2747 format %{ %}
2748 interface(REG_INTER);
2749 %}
2750
2751 operand rRegL()
2752 %{
2753 constraint(ALLOC_IN_RC(long_reg));
2754 match(RegL);
2755 match(rax_RegL);
2756 match(rdx_RegL);
2757
2758 format %{ %}
2759 interface(REG_INTER);
2760 %}
2761
2762 // Special Registers
2763 operand no_rax_rdx_RegL()
2764 %{
2765 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
2766 match(RegL);
2767 match(rRegL);
2768
2769 format %{ %}
2770 interface(REG_INTER);
2771 %}
2772
2773 operand rax_RegL()
2774 %{
2775 constraint(ALLOC_IN_RC(long_rax_reg));
2776 match(RegL);
2777 match(rRegL);
2778
2779 format %{ "RAX" %}
2780 interface(REG_INTER);
2781 %}
2782
2783 operand rcx_RegL()
2784 %{
2785 constraint(ALLOC_IN_RC(long_rcx_reg));
2786 match(RegL);
2787 match(rRegL);
2788
2789 format %{ %}
2790 interface(REG_INTER);
2791 %}
2792
2793 operand rdx_RegL()
2794 %{
2795 constraint(ALLOC_IN_RC(long_rdx_reg));
2796 match(RegL);
2797 match(rRegL);
2798
2799 format %{ %}
2800 interface(REG_INTER);
2801 %}
2802
2803 operand r11_RegL()
2804 %{
2805 constraint(ALLOC_IN_RC(long_r11_reg));
2806 match(RegL);
2807 match(rRegL);
2808
2809 format %{ %}
2810 interface(REG_INTER);
2811 %}
2812
2813 operand no_rbp_r13_RegL()
2814 %{
2815 constraint(ALLOC_IN_RC(long_no_rbp_r13_reg));
2816 match(RegL);
2817 match(rRegL);
2818 match(rax_RegL);
2819 match(rcx_RegL);
2820 match(rdx_RegL);
2821
2822 format %{ %}
2823 interface(REG_INTER);
2824 %}
2825
2826 // Flags register, used as output of compare instructions
2827 operand rFlagsReg()
2828 %{
2829 constraint(ALLOC_IN_RC(int_flags));
2830 match(RegFlags);
2831
2832 format %{ "RFLAGS" %}
2833 interface(REG_INTER);
2834 %}
2835
2836 // Flags register, used as output of FLOATING POINT compare instructions
2837 operand rFlagsRegU()
2838 %{
2839 constraint(ALLOC_IN_RC(int_flags));
2840 match(RegFlags);
2841
2842 format %{ "RFLAGS_U" %}
2843 interface(REG_INTER);
2844 %}
2845
2846 operand rFlagsRegUCF() %{
2847 constraint(ALLOC_IN_RC(int_flags));
2848 match(RegFlags);
2849 predicate(false);
2850
2851 format %{ "RFLAGS_U_CF" %}
2852 interface(REG_INTER);
2853 %}
2854
2855 // Float register operands
2856 operand regF() %{
2857 constraint(ALLOC_IN_RC(float_reg));
2858 match(RegF);
2859
2860 format %{ %}
2861 interface(REG_INTER);
2862 %}
2863
2864 // Float register operands
2865 operand legRegF() %{
2866 constraint(ALLOC_IN_RC(float_reg_legacy));
2867 match(RegF);
2868
2869 format %{ %}
2870 interface(REG_INTER);
2871 %}
2872
2873 // Float register operands
2874 operand vlRegF() %{
2875 constraint(ALLOC_IN_RC(float_reg_vl));
2876 match(RegF);
2877
2878 format %{ %}
2879 interface(REG_INTER);
2880 %}
2881
2882 // Double register operands
2883 operand regD() %{
2884 constraint(ALLOC_IN_RC(double_reg));
2885 match(RegD);
2886
2887 format %{ %}
2888 interface(REG_INTER);
2889 %}
2890
2891 // Double register operands
2892 operand legRegD() %{
2893 constraint(ALLOC_IN_RC(double_reg_legacy));
2894 match(RegD);
2895
2896 format %{ %}
2897 interface(REG_INTER);
2898 %}
2899
2900 // Double register operands
2901 operand vlRegD() %{
2902 constraint(ALLOC_IN_RC(double_reg_vl));
2903 match(RegD);
2904
2905 format %{ %}
2906 interface(REG_INTER);
2907 %}
2908
2909 //----------Memory Operands----------------------------------------------------
2910 // Direct Memory Operand
2911 // operand direct(immP addr)
2912 // %{
2913 // match(addr);
2914
2915 // format %{ "[$addr]" %}
2916 // interface(MEMORY_INTER) %{
2917 // base(0xFFFFFFFF);
2918 // index(0x4);
2919 // scale(0x0);
2920 // disp($addr);
2921 // %}
2922 // %}
2923
2924 // Indirect Memory Operand
2925 operand indirect(any_RegP reg)
2926 %{
2927 constraint(ALLOC_IN_RC(ptr_reg));
2928 match(reg);
2929
2930 format %{ "[$reg]" %}
2931 interface(MEMORY_INTER) %{
2932 base($reg);
2933 index(0x4);
2934 scale(0x0);
2935 disp(0x0);
2936 %}
2937 %}
2938
2939 // Indirect Memory Plus Short Offset Operand
2940 operand indOffset8(any_RegP reg, immL8 off)
2941 %{
2942 constraint(ALLOC_IN_RC(ptr_reg));
2943 match(AddP reg off);
2944
2945 format %{ "[$reg + $off (8-bit)]" %}
2946 interface(MEMORY_INTER) %{
2947 base($reg);
2948 index(0x4);
2949 scale(0x0);
2950 disp($off);
2951 %}
2952 %}
2953
2954 // Indirect Memory Plus Long Offset Operand
2955 operand indOffset32(any_RegP reg, immL32 off)
2956 %{
2957 constraint(ALLOC_IN_RC(ptr_reg));
2958 match(AddP reg off);
2959
2960 format %{ "[$reg + $off (32-bit)]" %}
2961 interface(MEMORY_INTER) %{
2962 base($reg);
2963 index(0x4);
2964 scale(0x0);
2965 disp($off);
2966 %}
2967 %}
2968
2969 // Indirect Memory Plus Index Register Plus Offset Operand
2970 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
2971 %{
2972 constraint(ALLOC_IN_RC(ptr_reg));
2973 match(AddP (AddP reg lreg) off);
2974
2975 op_cost(10);
2976 format %{"[$reg + $off + $lreg]" %}
2977 interface(MEMORY_INTER) %{
2978 base($reg);
2979 index($lreg);
2980 scale(0x0);
2981 disp($off);
2982 %}
2983 %}
2984
2985 // Indirect Memory Plus Index Register Plus Offset Operand
2986 operand indIndex(any_RegP reg, rRegL lreg)
2987 %{
2988 constraint(ALLOC_IN_RC(ptr_reg));
2989 match(AddP reg lreg);
2990
2991 op_cost(10);
2992 format %{"[$reg + $lreg]" %}
2993 interface(MEMORY_INTER) %{
2994 base($reg);
2995 index($lreg);
2996 scale(0x0);
2997 disp(0x0);
2998 %}
2999 %}
3000
3001 // Indirect Memory Times Scale Plus Index Register
3002 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3003 %{
3004 constraint(ALLOC_IN_RC(ptr_reg));
3005 match(AddP reg (LShiftL lreg scale));
3006
3007 op_cost(10);
3008 format %{"[$reg + $lreg << $scale]" %}
3009 interface(MEMORY_INTER) %{
3010 base($reg);
3011 index($lreg);
3012 scale($scale);
3013 disp(0x0);
3014 %}
3015 %}
3016
3017 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3018 %{
3019 constraint(ALLOC_IN_RC(ptr_reg));
3020 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3021 match(AddP reg (LShiftL (ConvI2L idx) scale));
3022
3023 op_cost(10);
3024 format %{"[$reg + pos $idx << $scale]" %}
3025 interface(MEMORY_INTER) %{
3026 base($reg);
3027 index($idx);
3028 scale($scale);
3029 disp(0x0);
3030 %}
3031 %}
3032
3033 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3034 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3035 %{
3036 constraint(ALLOC_IN_RC(ptr_reg));
3037 match(AddP (AddP reg (LShiftL lreg scale)) off);
3038
3039 op_cost(10);
3040 format %{"[$reg + $off + $lreg << $scale]" %}
3041 interface(MEMORY_INTER) %{
3042 base($reg);
3043 index($lreg);
3044 scale($scale);
3045 disp($off);
3046 %}
3047 %}
3048
3049 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3050 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3051 %{
3052 constraint(ALLOC_IN_RC(ptr_reg));
3053 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3054 match(AddP (AddP reg (ConvI2L idx)) off);
3055
3056 op_cost(10);
3057 format %{"[$reg + $off + $idx]" %}
3058 interface(MEMORY_INTER) %{
3059 base($reg);
3060 index($idx);
3061 scale(0x0);
3062 disp($off);
3063 %}
3064 %}
3065
3066 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3067 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3068 %{
3069 constraint(ALLOC_IN_RC(ptr_reg));
3070 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3071 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3072
3073 op_cost(10);
3074 format %{"[$reg + $off + $idx << $scale]" %}
3075 interface(MEMORY_INTER) %{
3076 base($reg);
3077 index($idx);
3078 scale($scale);
3079 disp($off);
3080 %}
3081 %}
3082
3083 // Indirect Narrow Oop Plus Offset Operand
3084 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3085 // we can't free r12 even with CompressedOops::base() == nullptr.
3086 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3087 predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
3088 constraint(ALLOC_IN_RC(ptr_reg));
3089 match(AddP (DecodeN reg) off);
3090
3091 op_cost(10);
3092 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3093 interface(MEMORY_INTER) %{
3094 base(0xc); // R12
3095 index($reg);
3096 scale(0x3);
3097 disp($off);
3098 %}
3099 %}
3100
3101 // Indirect Memory Operand
3102 operand indirectNarrow(rRegN reg)
3103 %{
3104 predicate(CompressedOops::shift() == 0);
3105 constraint(ALLOC_IN_RC(ptr_reg));
3106 match(DecodeN reg);
3107
3108 format %{ "[$reg]" %}
3109 interface(MEMORY_INTER) %{
3110 base($reg);
3111 index(0x4);
3112 scale(0x0);
3113 disp(0x0);
3114 %}
3115 %}
3116
3117 // Indirect Memory Plus Short Offset Operand
3118 operand indOffset8Narrow(rRegN reg, immL8 off)
3119 %{
3120 predicate(CompressedOops::shift() == 0);
3121 constraint(ALLOC_IN_RC(ptr_reg));
3122 match(AddP (DecodeN reg) off);
3123
3124 format %{ "[$reg + $off (8-bit)]" %}
3125 interface(MEMORY_INTER) %{
3126 base($reg);
3127 index(0x4);
3128 scale(0x0);
3129 disp($off);
3130 %}
3131 %}
3132
3133 // Indirect Memory Plus Long Offset Operand
3134 operand indOffset32Narrow(rRegN reg, immL32 off)
3135 %{
3136 predicate(CompressedOops::shift() == 0);
3137 constraint(ALLOC_IN_RC(ptr_reg));
3138 match(AddP (DecodeN reg) off);
3139
3140 format %{ "[$reg + $off (32-bit)]" %}
3141 interface(MEMORY_INTER) %{
3142 base($reg);
3143 index(0x4);
3144 scale(0x0);
3145 disp($off);
3146 %}
3147 %}
3148
3149 // Indirect Memory Plus Index Register Plus Offset Operand
3150 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3151 %{
3152 predicate(CompressedOops::shift() == 0);
3153 constraint(ALLOC_IN_RC(ptr_reg));
3154 match(AddP (AddP (DecodeN reg) lreg) off);
3155
3156 op_cost(10);
3157 format %{"[$reg + $off + $lreg]" %}
3158 interface(MEMORY_INTER) %{
3159 base($reg);
3160 index($lreg);
3161 scale(0x0);
3162 disp($off);
3163 %}
3164 %}
3165
3166 // Indirect Memory Plus Index Register Plus Offset Operand
3167 operand indIndexNarrow(rRegN reg, rRegL lreg)
3168 %{
3169 predicate(CompressedOops::shift() == 0);
3170 constraint(ALLOC_IN_RC(ptr_reg));
3171 match(AddP (DecodeN reg) lreg);
3172
3173 op_cost(10);
3174 format %{"[$reg + $lreg]" %}
3175 interface(MEMORY_INTER) %{
3176 base($reg);
3177 index($lreg);
3178 scale(0x0);
3179 disp(0x0);
3180 %}
3181 %}
3182
3183 // Indirect Memory Times Scale Plus Index Register
3184 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3185 %{
3186 predicate(CompressedOops::shift() == 0);
3187 constraint(ALLOC_IN_RC(ptr_reg));
3188 match(AddP (DecodeN reg) (LShiftL lreg scale));
3189
3190 op_cost(10);
3191 format %{"[$reg + $lreg << $scale]" %}
3192 interface(MEMORY_INTER) %{
3193 base($reg);
3194 index($lreg);
3195 scale($scale);
3196 disp(0x0);
3197 %}
3198 %}
3199
3200 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3201 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3202 %{
3203 predicate(CompressedOops::shift() == 0);
3204 constraint(ALLOC_IN_RC(ptr_reg));
3205 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3206
3207 op_cost(10);
3208 format %{"[$reg + $off + $lreg << $scale]" %}
3209 interface(MEMORY_INTER) %{
3210 base($reg);
3211 index($lreg);
3212 scale($scale);
3213 disp($off);
3214 %}
3215 %}
3216
3217 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
3218 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
3219 %{
3220 constraint(ALLOC_IN_RC(ptr_reg));
3221 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3222 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
3223
3224 op_cost(10);
3225 format %{"[$reg + $off + $idx]" %}
3226 interface(MEMORY_INTER) %{
3227 base($reg);
3228 index($idx);
3229 scale(0x0);
3230 disp($off);
3231 %}
3232 %}
3233
3234 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3235 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3236 %{
3237 constraint(ALLOC_IN_RC(ptr_reg));
3238 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3239 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
3240
3241 op_cost(10);
3242 format %{"[$reg + $off + $idx << $scale]" %}
3243 interface(MEMORY_INTER) %{
3244 base($reg);
3245 index($idx);
3246 scale($scale);
3247 disp($off);
3248 %}
3249 %}
3250
3251 //----------Special Memory Operands--------------------------------------------
3252 // Stack Slot Operand - This operand is used for loading and storing temporary
3253 // values on the stack where a match requires a value to
3254 // flow through memory.
3255 operand stackSlotP(sRegP reg)
3256 %{
3257 constraint(ALLOC_IN_RC(stack_slots));
3258 // No match rule because this operand is only generated in matching
3259
3260 format %{ "[$reg]" %}
3261 interface(MEMORY_INTER) %{
3262 base(0x4); // RSP
3263 index(0x4); // No Index
3264 scale(0x0); // No Scale
3265 disp($reg); // Stack Offset
3266 %}
3267 %}
3268
3269 operand stackSlotI(sRegI reg)
3270 %{
3271 constraint(ALLOC_IN_RC(stack_slots));
3272 // No match rule because this operand is only generated in matching
3273
3274 format %{ "[$reg]" %}
3275 interface(MEMORY_INTER) %{
3276 base(0x4); // RSP
3277 index(0x4); // No Index
3278 scale(0x0); // No Scale
3279 disp($reg); // Stack Offset
3280 %}
3281 %}
3282
3283 operand stackSlotF(sRegF reg)
3284 %{
3285 constraint(ALLOC_IN_RC(stack_slots));
3286 // No match rule because this operand is only generated in matching
3287
3288 format %{ "[$reg]" %}
3289 interface(MEMORY_INTER) %{
3290 base(0x4); // RSP
3291 index(0x4); // No Index
3292 scale(0x0); // No Scale
3293 disp($reg); // Stack Offset
3294 %}
3295 %}
3296
3297 operand stackSlotD(sRegD reg)
3298 %{
3299 constraint(ALLOC_IN_RC(stack_slots));
3300 // No match rule because this operand is only generated in matching
3301
3302 format %{ "[$reg]" %}
3303 interface(MEMORY_INTER) %{
3304 base(0x4); // RSP
3305 index(0x4); // No Index
3306 scale(0x0); // No Scale
3307 disp($reg); // Stack Offset
3308 %}
3309 %}
3310 operand stackSlotL(sRegL reg)
3311 %{
3312 constraint(ALLOC_IN_RC(stack_slots));
3313 // No match rule because this operand is only generated in matching
3314
3315 format %{ "[$reg]" %}
3316 interface(MEMORY_INTER) %{
3317 base(0x4); // RSP
3318 index(0x4); // No Index
3319 scale(0x0); // No Scale
3320 disp($reg); // Stack Offset
3321 %}
3322 %}
3323
3324 //----------Conditional Branch Operands----------------------------------------
3325 // Comparison Op - This is the operation of the comparison, and is limited to
3326 // the following set of codes:
3327 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3328 //
3329 // Other attributes of the comparison, such as unsignedness, are specified
3330 // by the comparison instruction that sets a condition code flags register.
3331 // That result is represented by a flags operand whose subtype is appropriate
3332 // to the unsignedness (etc.) of the comparison.
3333 //
3334 // Later, the instruction which matches both the Comparison Op (a Bool) and
3335 // the flags (produced by the Cmp) specifies the coding of the comparison op
3336 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3337
3338 // Comparison Code
3339 operand cmpOp()
3340 %{
3341 match(Bool);
3342
3343 format %{ "" %}
3344 interface(COND_INTER) %{
3345 equal(0x4, "e");
3346 not_equal(0x5, "ne");
3347 less(0xC, "l");
3348 greater_equal(0xD, "ge");
3349 less_equal(0xE, "le");
3350 greater(0xF, "g");
3351 overflow(0x0, "o");
3352 no_overflow(0x1, "no");
3353 %}
3354 %}
3355
3356 // Comparison Code, unsigned compare. Used by FP also, with
3357 // C2 (unordered) turned into GT or LT already. The other bits
3358 // C0 and C3 are turned into Carry & Zero flags.
3359 operand cmpOpU()
3360 %{
3361 match(Bool);
3362
3363 format %{ "" %}
3364 interface(COND_INTER) %{
3365 equal(0x4, "e");
3366 not_equal(0x5, "ne");
3367 less(0x2, "b");
3368 greater_equal(0x3, "ae");
3369 less_equal(0x6, "be");
3370 greater(0x7, "a");
3371 overflow(0x0, "o");
3372 no_overflow(0x1, "no");
3373 %}
3374 %}
3375
3376
3377 // Floating comparisons that don't require any fixup for the unordered case,
3378 // If both inputs of the comparison are the same, ZF is always set so we
3379 // don't need to use cmpOpUCF2 for eq/ne
3380 operand cmpOpUCF() %{
3381 match(Bool);
3382 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3383 n->as_Bool()->_test._test == BoolTest::ge ||
3384 n->as_Bool()->_test._test == BoolTest::le ||
3385 n->as_Bool()->_test._test == BoolTest::gt ||
3386 n->in(1)->in(1) == n->in(1)->in(2));
3387 format %{ "" %}
3388 interface(COND_INTER) %{
3389 equal(0xb, "np");
3390 not_equal(0xa, "p");
3391 less(0x2, "b");
3392 greater_equal(0x3, "ae");
3393 less_equal(0x6, "be");
3394 greater(0x7, "a");
3395 overflow(0x0, "o");
3396 no_overflow(0x1, "no");
3397 %}
3398 %}
3399
3400
3401 // Floating comparisons that can be fixed up with extra conditional jumps
3402 operand cmpOpUCF2() %{
3403 match(Bool);
3404 predicate((n->as_Bool()->_test._test == BoolTest::ne ||
3405 n->as_Bool()->_test._test == BoolTest::eq) &&
3406 n->in(1)->in(1) != n->in(1)->in(2));
3407 format %{ "" %}
3408 interface(COND_INTER) %{
3409 equal(0x4, "e");
3410 not_equal(0x5, "ne");
3411 less(0x2, "b");
3412 greater_equal(0x3, "ae");
3413 less_equal(0x6, "be");
3414 greater(0x7, "a");
3415 overflow(0x0, "o");
3416 no_overflow(0x1, "no");
3417 %}
3418 %}
3419
3420 //----------OPERAND CLASSES----------------------------------------------------
3421 // Operand Classes are groups of operands that are used as to simplify
3422 // instruction definitions by not requiring the AD writer to specify separate
3423 // instructions for every form of operand when the instruction accepts
3424 // multiple operand types with the same basic encoding and format. The classic
3425 // case of this is memory operands.
3426
3427 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
3428 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
3429 indCompressedOopOffset,
3430 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
3431 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
3432 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
3433
3434 //----------PIPELINE-----------------------------------------------------------
3435 // Rules which define the behavior of the target architectures pipeline.
3436 pipeline %{
3437
3438 //----------ATTRIBUTES---------------------------------------------------------
3439 attributes %{
3440 variable_size_instructions; // Fixed size instructions
3441 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
3442 instruction_unit_size = 1; // An instruction is 1 bytes long
3443 instruction_fetch_unit_size = 16; // The processor fetches one line
3444 instruction_fetch_units = 1; // of 16 bytes
3445
3446 // List of nop instructions
3447 nops( MachNop );
3448 %}
3449
3450 //----------RESOURCES----------------------------------------------------------
3451 // Resources are the functional units available to the machine
3452
3453 // Generic P2/P3 pipeline
3454 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
3455 // 3 instructions decoded per cycle.
3456 // 2 load/store ops per cycle, 1 branch, 1 FPU,
3457 // 3 ALU op, only ALU0 handles mul instructions.
3458 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
3459 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
3460 BR, FPU,
3461 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
3462
3463 //----------PIPELINE DESCRIPTION-----------------------------------------------
3464 // Pipeline Description specifies the stages in the machine's pipeline
3465
3466 // Generic P2/P3 pipeline
3467 pipe_desc(S0, S1, S2, S3, S4, S5);
3468
3469 //----------PIPELINE CLASSES---------------------------------------------------
3470 // Pipeline Classes describe the stages in which input and output are
3471 // referenced by the hardware pipeline.
3472
3473 // Naming convention: ialu or fpu
3474 // Then: _reg
3475 // Then: _reg if there is a 2nd register
3476 // Then: _long if it's a pair of instructions implementing a long
3477 // Then: _fat if it requires the big decoder
3478 // Or: _mem if it requires the big decoder and a memory unit.
3479
3480 // Integer ALU reg operation
3481 pipe_class ialu_reg(rRegI dst)
3482 %{
3483 single_instruction;
3484 dst : S4(write);
3485 dst : S3(read);
3486 DECODE : S0; // any decoder
3487 ALU : S3; // any alu
3488 %}
3489
3490 // Long ALU reg operation
3491 pipe_class ialu_reg_long(rRegL dst)
3492 %{
3493 instruction_count(2);
3494 dst : S4(write);
3495 dst : S3(read);
3496 DECODE : S0(2); // any 2 decoders
3497 ALU : S3(2); // both alus
3498 %}
3499
3500 // Integer ALU reg operation using big decoder
3501 pipe_class ialu_reg_fat(rRegI dst)
3502 %{
3503 single_instruction;
3504 dst : S4(write);
3505 dst : S3(read);
3506 D0 : S0; // big decoder only
3507 ALU : S3; // any alu
3508 %}
3509
3510 // Integer ALU reg-reg operation
3511 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
3512 %{
3513 single_instruction;
3514 dst : S4(write);
3515 src : S3(read);
3516 DECODE : S0; // any decoder
3517 ALU : S3; // any alu
3518 %}
3519
3520 // Integer ALU reg-reg operation
3521 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
3522 %{
3523 single_instruction;
3524 dst : S4(write);
3525 src : S3(read);
3526 D0 : S0; // big decoder only
3527 ALU : S3; // any alu
3528 %}
3529
3530 // Integer ALU reg-mem operation
3531 pipe_class ialu_reg_mem(rRegI dst, memory mem)
3532 %{
3533 single_instruction;
3534 dst : S5(write);
3535 mem : S3(read);
3536 D0 : S0; // big decoder only
3537 ALU : S4; // any alu
3538 MEM : S3; // any mem
3539 %}
3540
3541 // Integer mem operation (prefetch)
3542 pipe_class ialu_mem(memory mem)
3543 %{
3544 single_instruction;
3545 mem : S3(read);
3546 D0 : S0; // big decoder only
3547 MEM : S3; // any mem
3548 %}
3549
3550 // Integer Store to Memory
3551 pipe_class ialu_mem_reg(memory mem, rRegI src)
3552 %{
3553 single_instruction;
3554 mem : S3(read);
3555 src : S5(read);
3556 D0 : S0; // big decoder only
3557 ALU : S4; // any alu
3558 MEM : S3;
3559 %}
3560
3561 // // Long Store to Memory
3562 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
3563 // %{
3564 // instruction_count(2);
3565 // mem : S3(read);
3566 // src : S5(read);
3567 // D0 : S0(2); // big decoder only; twice
3568 // ALU : S4(2); // any 2 alus
3569 // MEM : S3(2); // Both mems
3570 // %}
3571
3572 // Integer Store to Memory
3573 pipe_class ialu_mem_imm(memory mem)
3574 %{
3575 single_instruction;
3576 mem : S3(read);
3577 D0 : S0; // big decoder only
3578 ALU : S4; // any alu
3579 MEM : S3;
3580 %}
3581
3582 // Integer ALU0 reg-reg operation
3583 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
3584 %{
3585 single_instruction;
3586 dst : S4(write);
3587 src : S3(read);
3588 D0 : S0; // Big decoder only
3589 ALU0 : S3; // only alu0
3590 %}
3591
3592 // Integer ALU0 reg-mem operation
3593 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
3594 %{
3595 single_instruction;
3596 dst : S5(write);
3597 mem : S3(read);
3598 D0 : S0; // big decoder only
3599 ALU0 : S4; // ALU0 only
3600 MEM : S3; // any mem
3601 %}
3602
3603 // Integer ALU reg-reg operation
3604 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
3605 %{
3606 single_instruction;
3607 cr : S4(write);
3608 src1 : S3(read);
3609 src2 : S3(read);
3610 DECODE : S0; // any decoder
3611 ALU : S3; // any alu
3612 %}
3613
3614 // Integer ALU reg-imm operation
3615 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
3616 %{
3617 single_instruction;
3618 cr : S4(write);
3619 src1 : S3(read);
3620 DECODE : S0; // any decoder
3621 ALU : S3; // any alu
3622 %}
3623
3624 // Integer ALU reg-mem operation
3625 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
3626 %{
3627 single_instruction;
3628 cr : S4(write);
3629 src1 : S3(read);
3630 src2 : S3(read);
3631 D0 : S0; // big decoder only
3632 ALU : S4; // any alu
3633 MEM : S3;
3634 %}
3635
3636 // Conditional move reg-reg
3637 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
3638 %{
3639 instruction_count(4);
3640 y : S4(read);
3641 q : S3(read);
3642 p : S3(read);
3643 DECODE : S0(4); // any decoder
3644 %}
3645
3646 // Conditional move reg-reg
3647 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
3648 %{
3649 single_instruction;
3650 dst : S4(write);
3651 src : S3(read);
3652 cr : S3(read);
3653 DECODE : S0; // any decoder
3654 %}
3655
3656 // Conditional move reg-mem
3657 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
3658 %{
3659 single_instruction;
3660 dst : S4(write);
3661 src : S3(read);
3662 cr : S3(read);
3663 DECODE : S0; // any decoder
3664 MEM : S3;
3665 %}
3666
3667 // Conditional move reg-reg long
3668 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
3669 %{
3670 single_instruction;
3671 dst : S4(write);
3672 src : S3(read);
3673 cr : S3(read);
3674 DECODE : S0(2); // any 2 decoders
3675 %}
3676
3677 // Float reg-reg operation
3678 pipe_class fpu_reg(regD dst)
3679 %{
3680 instruction_count(2);
3681 dst : S3(read);
3682 DECODE : S0(2); // any 2 decoders
3683 FPU : S3;
3684 %}
3685
3686 // Float reg-reg operation
3687 pipe_class fpu_reg_reg(regD dst, regD src)
3688 %{
3689 instruction_count(2);
3690 dst : S4(write);
3691 src : S3(read);
3692 DECODE : S0(2); // any 2 decoders
3693 FPU : S3;
3694 %}
3695
3696 // Float reg-reg operation
3697 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
3698 %{
3699 instruction_count(3);
3700 dst : S4(write);
3701 src1 : S3(read);
3702 src2 : S3(read);
3703 DECODE : S0(3); // any 3 decoders
3704 FPU : S3(2);
3705 %}
3706
3707 // Float reg-reg operation
3708 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
3709 %{
3710 instruction_count(4);
3711 dst : S4(write);
3712 src1 : S3(read);
3713 src2 : S3(read);
3714 src3 : S3(read);
3715 DECODE : S0(4); // any 3 decoders
3716 FPU : S3(2);
3717 %}
3718
3719 // Float reg-reg operation
3720 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
3721 %{
3722 instruction_count(4);
3723 dst : S4(write);
3724 src1 : S3(read);
3725 src2 : S3(read);
3726 src3 : S3(read);
3727 DECODE : S1(3); // any 3 decoders
3728 D0 : S0; // Big decoder only
3729 FPU : S3(2);
3730 MEM : S3;
3731 %}
3732
3733 // Float reg-mem operation
3734 pipe_class fpu_reg_mem(regD dst, memory mem)
3735 %{
3736 instruction_count(2);
3737 dst : S5(write);
3738 mem : S3(read);
3739 D0 : S0; // big decoder only
3740 DECODE : S1; // any decoder for FPU POP
3741 FPU : S4;
3742 MEM : S3; // any mem
3743 %}
3744
3745 // Float reg-mem operation
3746 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
3747 %{
3748 instruction_count(3);
3749 dst : S5(write);
3750 src1 : S3(read);
3751 mem : S3(read);
3752 D0 : S0; // big decoder only
3753 DECODE : S1(2); // any decoder for FPU POP
3754 FPU : S4;
3755 MEM : S3; // any mem
3756 %}
3757
3758 // Float mem-reg operation
3759 pipe_class fpu_mem_reg(memory mem, regD src)
3760 %{
3761 instruction_count(2);
3762 src : S5(read);
3763 mem : S3(read);
3764 DECODE : S0; // any decoder for FPU PUSH
3765 D0 : S1; // big decoder only
3766 FPU : S4;
3767 MEM : S3; // any mem
3768 %}
3769
3770 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
3771 %{
3772 instruction_count(3);
3773 src1 : S3(read);
3774 src2 : S3(read);
3775 mem : S3(read);
3776 DECODE : S0(2); // any decoder for FPU PUSH
3777 D0 : S1; // big decoder only
3778 FPU : S4;
3779 MEM : S3; // any mem
3780 %}
3781
3782 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
3783 %{
3784 instruction_count(3);
3785 src1 : S3(read);
3786 src2 : S3(read);
3787 mem : S4(read);
3788 DECODE : S0; // any decoder for FPU PUSH
3789 D0 : S0(2); // big decoder only
3790 FPU : S4;
3791 MEM : S3(2); // any mem
3792 %}
3793
3794 pipe_class fpu_mem_mem(memory dst, memory src1)
3795 %{
3796 instruction_count(2);
3797 src1 : S3(read);
3798 dst : S4(read);
3799 D0 : S0(2); // big decoder only
3800 MEM : S3(2); // any mem
3801 %}
3802
3803 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
3804 %{
3805 instruction_count(3);
3806 src1 : S3(read);
3807 src2 : S3(read);
3808 dst : S4(read);
3809 D0 : S0(3); // big decoder only
3810 FPU : S4;
3811 MEM : S3(3); // any mem
3812 %}
3813
3814 pipe_class fpu_mem_reg_con(memory mem, regD src1)
3815 %{
3816 instruction_count(3);
3817 src1 : S4(read);
3818 mem : S4(read);
3819 DECODE : S0; // any decoder for FPU PUSH
3820 D0 : S0(2); // big decoder only
3821 FPU : S4;
3822 MEM : S3(2); // any mem
3823 %}
3824
3825 // Float load constant
3826 pipe_class fpu_reg_con(regD dst)
3827 %{
3828 instruction_count(2);
3829 dst : S5(write);
3830 D0 : S0; // big decoder only for the load
3831 DECODE : S1; // any decoder for FPU POP
3832 FPU : S4;
3833 MEM : S3; // any mem
3834 %}
3835
3836 // Float load constant
3837 pipe_class fpu_reg_reg_con(regD dst, regD src)
3838 %{
3839 instruction_count(3);
3840 dst : S5(write);
3841 src : S3(read);
3842 D0 : S0; // big decoder only for the load
3843 DECODE : S1(2); // any decoder for FPU POP
3844 FPU : S4;
3845 MEM : S3; // any mem
3846 %}
3847
3848 // UnConditional branch
3849 pipe_class pipe_jmp(label labl)
3850 %{
3851 single_instruction;
3852 BR : S3;
3853 %}
3854
3855 // Conditional branch
3856 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
3857 %{
3858 single_instruction;
3859 cr : S1(read);
3860 BR : S3;
3861 %}
3862
3863 // Allocation idiom
3864 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
3865 %{
3866 instruction_count(1); force_serialization;
3867 fixed_latency(6);
3868 heap_ptr : S3(read);
3869 DECODE : S0(3);
3870 D0 : S2;
3871 MEM : S3;
3872 ALU : S3(2);
3873 dst : S5(write);
3874 BR : S5;
3875 %}
3876
3877 // Generic big/slow expanded idiom
3878 pipe_class pipe_slow()
3879 %{
3880 instruction_count(10); multiple_bundles; force_serialization;
3881 fixed_latency(100);
3882 D0 : S0(2);
3883 MEM : S3(2);
3884 %}
3885
3886 // The real do-nothing guy
3887 pipe_class empty()
3888 %{
3889 instruction_count(0);
3890 %}
3891
3892 // Define the class for the Nop node
3893 define
3894 %{
3895 MachNop = empty;
3896 %}
3897
3898 %}
3899
3900 //----------INSTRUCTIONS-------------------------------------------------------
3901 //
3902 // match -- States which machine-independent subtree may be replaced
3903 // by this instruction.
3904 // ins_cost -- The estimated cost of this instruction is used by instruction
3905 // selection to identify a minimum cost tree of machine
3906 // instructions that matches a tree of machine-independent
3907 // instructions.
3908 // format -- A string providing the disassembly for this instruction.
3909 // The value of an instruction's operand may be inserted
3910 // by referring to it with a '$' prefix.
3911 // opcode -- Three instruction opcodes may be provided. These are referred
3912 // to within an encode class as $primary, $secondary, and $tertiary
3913 // rrspectively. The primary opcode is commonly used to
3914 // indicate the type of machine instruction, while secondary
3915 // and tertiary are often used for prefix options or addressing
3916 // modes.
3917 // ins_encode -- A list of encode classes with parameters. The encode class
3918 // name must have been defined in an 'enc_class' specification
3919 // in the encode section of the architecture description.
3920
3921 // Dummy reg-to-reg vector moves. Removed during post-selection cleanup.
3922 // Load Float
3923 instruct MoveF2VL(vlRegF dst, regF src) %{
3924 match(Set dst src);
3925 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
3926 ins_encode %{
3927 ShouldNotReachHere();
3928 %}
3929 ins_pipe( fpu_reg_reg );
3930 %}
3931
3932 // Load Float
3933 instruct MoveF2LEG(legRegF dst, regF src) %{
3934 match(Set dst src);
3935 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
3936 ins_encode %{
3937 ShouldNotReachHere();
3938 %}
3939 ins_pipe( fpu_reg_reg );
3940 %}
3941
3942 // Load Float
3943 instruct MoveVL2F(regF dst, vlRegF src) %{
3944 match(Set dst src);
3945 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
3946 ins_encode %{
3947 ShouldNotReachHere();
3948 %}
3949 ins_pipe( fpu_reg_reg );
3950 %}
3951
3952 // Load Float
3953 instruct MoveLEG2F(regF dst, legRegF src) %{
3954 match(Set dst src);
3955 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
3956 ins_encode %{
3957 ShouldNotReachHere();
3958 %}
3959 ins_pipe( fpu_reg_reg );
3960 %}
3961
3962 // Load Double
3963 instruct MoveD2VL(vlRegD dst, regD src) %{
3964 match(Set dst src);
3965 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
3966 ins_encode %{
3967 ShouldNotReachHere();
3968 %}
3969 ins_pipe( fpu_reg_reg );
3970 %}
3971
3972 // Load Double
3973 instruct MoveD2LEG(legRegD dst, regD src) %{
3974 match(Set dst src);
3975 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
3976 ins_encode %{
3977 ShouldNotReachHere();
3978 %}
3979 ins_pipe( fpu_reg_reg );
3980 %}
3981
3982 // Load Double
3983 instruct MoveVL2D(regD dst, vlRegD src) %{
3984 match(Set dst src);
3985 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
3986 ins_encode %{
3987 ShouldNotReachHere();
3988 %}
3989 ins_pipe( fpu_reg_reg );
3990 %}
3991
3992 // Load Double
3993 instruct MoveLEG2D(regD dst, legRegD src) %{
3994 match(Set dst src);
3995 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
3996 ins_encode %{
3997 ShouldNotReachHere();
3998 %}
3999 ins_pipe( fpu_reg_reg );
4000 %}
4001
4002 //----------Load/Store/Move Instructions---------------------------------------
4003 //----------Load Instructions--------------------------------------------------
4004
4005 // Load Byte (8 bit signed)
4006 instruct loadB(rRegI dst, memory mem)
4007 %{
4008 match(Set dst (LoadB mem));
4009
4010 ins_cost(125);
4011 format %{ "movsbl $dst, $mem\t# byte" %}
4012
4013 ins_encode %{
4014 __ movsbl($dst$$Register, $mem$$Address);
4015 %}
4016
4017 ins_pipe(ialu_reg_mem);
4018 %}
4019
4020 // Load Byte (8 bit signed) into Long Register
4021 instruct loadB2L(rRegL dst, memory mem)
4022 %{
4023 match(Set dst (ConvI2L (LoadB mem)));
4024
4025 ins_cost(125);
4026 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4027
4028 ins_encode %{
4029 __ movsbq($dst$$Register, $mem$$Address);
4030 %}
4031
4032 ins_pipe(ialu_reg_mem);
4033 %}
4034
4035 // Load Unsigned Byte (8 bit UNsigned)
4036 instruct loadUB(rRegI dst, memory mem)
4037 %{
4038 match(Set dst (LoadUB mem));
4039
4040 ins_cost(125);
4041 format %{ "movzbl $dst, $mem\t# ubyte" %}
4042
4043 ins_encode %{
4044 __ movzbl($dst$$Register, $mem$$Address);
4045 %}
4046
4047 ins_pipe(ialu_reg_mem);
4048 %}
4049
4050 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4051 instruct loadUB2L(rRegL dst, memory mem)
4052 %{
4053 match(Set dst (ConvI2L (LoadUB mem)));
4054
4055 ins_cost(125);
4056 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4057
4058 ins_encode %{
4059 __ movzbq($dst$$Register, $mem$$Address);
4060 %}
4061
4062 ins_pipe(ialu_reg_mem);
4063 %}
4064
4065 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4066 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4067 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4068 effect(KILL cr);
4069
4070 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4071 "andl $dst, right_n_bits($mask, 8)" %}
4072 ins_encode %{
4073 Register Rdst = $dst$$Register;
4074 __ movzbq(Rdst, $mem$$Address);
4075 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4076 %}
4077 ins_pipe(ialu_reg_mem);
4078 %}
4079
4080 // Load Short (16 bit signed)
4081 instruct loadS(rRegI dst, memory mem)
4082 %{
4083 match(Set dst (LoadS mem));
4084
4085 ins_cost(125);
4086 format %{ "movswl $dst, $mem\t# short" %}
4087
4088 ins_encode %{
4089 __ movswl($dst$$Register, $mem$$Address);
4090 %}
4091
4092 ins_pipe(ialu_reg_mem);
4093 %}
4094
4095 // Load Short (16 bit signed) to Byte (8 bit signed)
4096 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4097 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4098
4099 ins_cost(125);
4100 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4101 ins_encode %{
4102 __ movsbl($dst$$Register, $mem$$Address);
4103 %}
4104 ins_pipe(ialu_reg_mem);
4105 %}
4106
4107 // Load Short (16 bit signed) into Long Register
4108 instruct loadS2L(rRegL dst, memory mem)
4109 %{
4110 match(Set dst (ConvI2L (LoadS mem)));
4111
4112 ins_cost(125);
4113 format %{ "movswq $dst, $mem\t# short -> long" %}
4114
4115 ins_encode %{
4116 __ movswq($dst$$Register, $mem$$Address);
4117 %}
4118
4119 ins_pipe(ialu_reg_mem);
4120 %}
4121
4122 // Load Unsigned Short/Char (16 bit UNsigned)
4123 instruct loadUS(rRegI dst, memory mem)
4124 %{
4125 match(Set dst (LoadUS mem));
4126
4127 ins_cost(125);
4128 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4129
4130 ins_encode %{
4131 __ movzwl($dst$$Register, $mem$$Address);
4132 %}
4133
4134 ins_pipe(ialu_reg_mem);
4135 %}
4136
4137 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4138 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4139 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4140
4141 ins_cost(125);
4142 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4143 ins_encode %{
4144 __ movsbl($dst$$Register, $mem$$Address);
4145 %}
4146 ins_pipe(ialu_reg_mem);
4147 %}
4148
4149 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4150 instruct loadUS2L(rRegL dst, memory mem)
4151 %{
4152 match(Set dst (ConvI2L (LoadUS mem)));
4153
4154 ins_cost(125);
4155 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4156
4157 ins_encode %{
4158 __ movzwq($dst$$Register, $mem$$Address);
4159 %}
4160
4161 ins_pipe(ialu_reg_mem);
4162 %}
4163
4164 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4165 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4166 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4167
4168 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4169 ins_encode %{
4170 __ movzbq($dst$$Register, $mem$$Address);
4171 %}
4172 ins_pipe(ialu_reg_mem);
4173 %}
4174
4175 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4176 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4177 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4178 effect(KILL cr);
4179
4180 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4181 "andl $dst, right_n_bits($mask, 16)" %}
4182 ins_encode %{
4183 Register Rdst = $dst$$Register;
4184 __ movzwq(Rdst, $mem$$Address);
4185 __ andl(Rdst, $mask$$constant & right_n_bits(16));
4186 %}
4187 ins_pipe(ialu_reg_mem);
4188 %}
4189
4190 // Load Integer
4191 instruct loadI(rRegI dst, memory mem)
4192 %{
4193 match(Set dst (LoadI mem));
4194
4195 ins_cost(125);
4196 format %{ "movl $dst, $mem\t# int" %}
4197
4198 ins_encode %{
4199 __ movl($dst$$Register, $mem$$Address);
4200 %}
4201
4202 ins_pipe(ialu_reg_mem);
4203 %}
4204
4205 // Load Integer (32 bit signed) to Byte (8 bit signed)
4206 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4207 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4208
4209 ins_cost(125);
4210 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4211 ins_encode %{
4212 __ movsbl($dst$$Register, $mem$$Address);
4213 %}
4214 ins_pipe(ialu_reg_mem);
4215 %}
4216
4217 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4218 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4219 match(Set dst (AndI (LoadI mem) mask));
4220
4221 ins_cost(125);
4222 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4223 ins_encode %{
4224 __ movzbl($dst$$Register, $mem$$Address);
4225 %}
4226 ins_pipe(ialu_reg_mem);
4227 %}
4228
4229 // Load Integer (32 bit signed) to Short (16 bit signed)
4230 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4231 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4232
4233 ins_cost(125);
4234 format %{ "movswl $dst, $mem\t# int -> short" %}
4235 ins_encode %{
4236 __ movswl($dst$$Register, $mem$$Address);
4237 %}
4238 ins_pipe(ialu_reg_mem);
4239 %}
4240
4241 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4242 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4243 match(Set dst (AndI (LoadI mem) mask));
4244
4245 ins_cost(125);
4246 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4247 ins_encode %{
4248 __ movzwl($dst$$Register, $mem$$Address);
4249 %}
4250 ins_pipe(ialu_reg_mem);
4251 %}
4252
4253 // Load Integer into Long Register
4254 instruct loadI2L(rRegL dst, memory mem)
4255 %{
4256 match(Set dst (ConvI2L (LoadI mem)));
4257
4258 ins_cost(125);
4259 format %{ "movslq $dst, $mem\t# int -> long" %}
4260
4261 ins_encode %{
4262 __ movslq($dst$$Register, $mem$$Address);
4263 %}
4264
4265 ins_pipe(ialu_reg_mem);
4266 %}
4267
4268 // Load Integer with mask 0xFF into Long Register
4269 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4270 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4271
4272 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
4273 ins_encode %{
4274 __ movzbq($dst$$Register, $mem$$Address);
4275 %}
4276 ins_pipe(ialu_reg_mem);
4277 %}
4278
4279 // Load Integer with mask 0xFFFF into Long Register
4280 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
4281 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4282
4283 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
4284 ins_encode %{
4285 __ movzwq($dst$$Register, $mem$$Address);
4286 %}
4287 ins_pipe(ialu_reg_mem);
4288 %}
4289
4290 // Load Integer with a 31-bit mask into Long Register
4291 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
4292 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4293 effect(KILL cr);
4294
4295 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
4296 "andl $dst, $mask" %}
4297 ins_encode %{
4298 Register Rdst = $dst$$Register;
4299 __ movl(Rdst, $mem$$Address);
4300 __ andl(Rdst, $mask$$constant);
4301 %}
4302 ins_pipe(ialu_reg_mem);
4303 %}
4304
4305 // Load Unsigned Integer into Long Register
4306 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
4307 %{
4308 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4309
4310 ins_cost(125);
4311 format %{ "movl $dst, $mem\t# uint -> long" %}
4312
4313 ins_encode %{
4314 __ movl($dst$$Register, $mem$$Address);
4315 %}
4316
4317 ins_pipe(ialu_reg_mem);
4318 %}
4319
4320 // Load Long
4321 instruct loadL(rRegL dst, memory mem)
4322 %{
4323 match(Set dst (LoadL mem));
4324
4325 ins_cost(125);
4326 format %{ "movq $dst, $mem\t# long" %}
4327
4328 ins_encode %{
4329 __ movq($dst$$Register, $mem$$Address);
4330 %}
4331
4332 ins_pipe(ialu_reg_mem); // XXX
4333 %}
4334
4335 // Load Range
4336 instruct loadRange(rRegI dst, memory mem)
4337 %{
4338 match(Set dst (LoadRange mem));
4339
4340 ins_cost(125); // XXX
4341 format %{ "movl $dst, $mem\t# range" %}
4342 ins_encode %{
4343 __ movl($dst$$Register, $mem$$Address);
4344 %}
4345 ins_pipe(ialu_reg_mem);
4346 %}
4347
4348 // Load Pointer
4349 instruct loadP(rRegP dst, memory mem)
4350 %{
4351 match(Set dst (LoadP mem));
4352 predicate(n->as_Load()->barrier_data() == 0);
4353
4354 ins_cost(125); // XXX
4355 format %{ "movq $dst, $mem\t# ptr" %}
4356 ins_encode %{
4357 __ movq($dst$$Register, $mem$$Address);
4358 %}
4359 ins_pipe(ialu_reg_mem); // XXX
4360 %}
4361
4362 // Load Compressed Pointer
4363 instruct loadN(rRegN dst, memory mem)
4364 %{
4365 predicate(n->as_Load()->barrier_data() == 0);
4366 match(Set dst (LoadN mem));
4367
4368 ins_cost(125); // XXX
4369 format %{ "movl $dst, $mem\t# compressed ptr" %}
4370 ins_encode %{
4371 __ movl($dst$$Register, $mem$$Address);
4372 %}
4373 ins_pipe(ialu_reg_mem); // XXX
4374 %}
4375
4376
4377 // Load Klass Pointer
4378 instruct loadKlass(rRegP dst, memory mem)
4379 %{
4380 match(Set dst (LoadKlass mem));
4381
4382 ins_cost(125); // XXX
4383 format %{ "movq $dst, $mem\t# class" %}
4384 ins_encode %{
4385 __ movq($dst$$Register, $mem$$Address);
4386 %}
4387 ins_pipe(ialu_reg_mem); // XXX
4388 %}
4389
4390 // Load narrow Klass Pointer
4391 instruct loadNKlass(rRegN dst, memory mem)
4392 %{
4393 predicate(!UseCompactObjectHeaders);
4394 match(Set dst (LoadNKlass mem));
4395
4396 ins_cost(125); // XXX
4397 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
4398 ins_encode %{
4399 __ movl($dst$$Register, $mem$$Address);
4400 %}
4401 ins_pipe(ialu_reg_mem); // XXX
4402 %}
4403
4404 instruct loadNKlassCompactHeaders(rRegN dst, memory mem, rFlagsReg cr)
4405 %{
4406 predicate(UseCompactObjectHeaders);
4407 match(Set dst (LoadNKlass mem));
4408 effect(KILL cr);
4409 ins_cost(125);
4410 format %{
4411 "movl $dst, $mem\t# compressed klass ptr, shifted\n\t"
4412 "shrl $dst, markWord::klass_shift_at_offset"
4413 %}
4414 ins_encode %{
4415 if (UseAPX) {
4416 __ eshrl($dst$$Register, $mem$$Address, markWord::klass_shift_at_offset, false);
4417 }
4418 else {
4419 __ movl($dst$$Register, $mem$$Address);
4420 __ shrl($dst$$Register, markWord::klass_shift_at_offset);
4421 }
4422 %}
4423 ins_pipe(ialu_reg_mem);
4424 %}
4425
4426 // Load Float
4427 instruct loadF(regF dst, memory mem)
4428 %{
4429 match(Set dst (LoadF mem));
4430
4431 ins_cost(145); // XXX
4432 format %{ "movss $dst, $mem\t# float" %}
4433 ins_encode %{
4434 __ movflt($dst$$XMMRegister, $mem$$Address);
4435 %}
4436 ins_pipe(pipe_slow); // XXX
4437 %}
4438
4439 // Load Double
4440 instruct loadD_partial(regD dst, memory mem)
4441 %{
4442 predicate(!UseXmmLoadAndClearUpper);
4443 match(Set dst (LoadD mem));
4444
4445 ins_cost(145); // XXX
4446 format %{ "movlpd $dst, $mem\t# double" %}
4447 ins_encode %{
4448 __ movdbl($dst$$XMMRegister, $mem$$Address);
4449 %}
4450 ins_pipe(pipe_slow); // XXX
4451 %}
4452
4453 instruct loadD(regD dst, memory mem)
4454 %{
4455 predicate(UseXmmLoadAndClearUpper);
4456 match(Set dst (LoadD mem));
4457
4458 ins_cost(145); // XXX
4459 format %{ "movsd $dst, $mem\t# double" %}
4460 ins_encode %{
4461 __ movdbl($dst$$XMMRegister, $mem$$Address);
4462 %}
4463 ins_pipe(pipe_slow); // XXX
4464 %}
4465
4466 instruct loadAOTRCAddress(rRegP dst, immAOTRuntimeConstantsAddress con)
4467 %{
4468 match(Set dst con);
4469
4470 format %{ "leaq $dst, $con\t# AOT Runtime Constants Address" %}
4471
4472 ins_encode %{
4473 __ load_aotrc_address($dst$$Register, (address)$con$$constant);
4474 %}
4475
4476 ins_pipe(ialu_reg_fat);
4477 %}
4478
4479 // max = java.lang.Math.max(float a, float b)
4480 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
4481 predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
4482 match(Set dst (MaxF a b));
4483 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4484 format %{ "maxF $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
4485 ins_encode %{
4486 __ vminmax_fp(Op_MaxV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4487 %}
4488 ins_pipe( pipe_slow );
4489 %}
4490
4491 instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xtmp, rRegI rtmp, rFlagsReg cr) %{
4492 predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
4493 match(Set dst (MaxF a b));
4494 effect(USE a, USE b, TEMP xtmp, TEMP rtmp, KILL cr);
4495
4496 format %{ "maxF_reduction $dst, $a, $b \t!using $xtmp and $rtmp as TEMP" %}
4497 ins_encode %{
4498 emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xtmp$$XMMRegister, $rtmp$$Register,
4499 false /*min*/, true /*single*/);
4500 %}
4501 ins_pipe( pipe_slow );
4502 %}
4503
4504 // max = java.lang.Math.max(double a, double b)
4505 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
4506 predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
4507 match(Set dst (MaxD a b));
4508 effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
4509 format %{ "maxD $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
4510 ins_encode %{
4511 __ vminmax_fp(Op_MaxV, T_DOUBLE, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4512 %}
4513 ins_pipe( pipe_slow );
4514 %}
4515
4516 instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xtmp, rRegL rtmp, rFlagsReg cr) %{
4517 predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
4518 match(Set dst (MaxD a b));
4519 effect(USE a, USE b, TEMP xtmp, TEMP rtmp, KILL cr);
4520
4521 format %{ "maxD_reduction $dst, $a, $b \t! using $xtmp and $rtmp as TEMP" %}
4522 ins_encode %{
4523 emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xtmp$$XMMRegister, $rtmp$$Register,
4524 false /*min*/, false /*single*/);
4525 %}
4526 ins_pipe( pipe_slow );
4527 %}
4528
4529 // min = java.lang.Math.min(float a, float b)
4530 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
4531 predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
4532 match(Set dst (MinF a b));
4533 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4534 format %{ "minF $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
4535 ins_encode %{
4536 __ vminmax_fp(Op_MinV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4537 %}
4538 ins_pipe( pipe_slow );
4539 %}
4540
4541 instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xtmp, rRegI rtmp, rFlagsReg cr) %{
4542 predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
4543 match(Set dst (MinF a b));
4544 effect(USE a, USE b, TEMP xtmp, TEMP rtmp, KILL cr);
4545
4546 format %{ "minF_reduction $dst, $a, $b \t! using $xtmp and $rtmp as TEMP" %}
4547 ins_encode %{
4548 emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xtmp$$XMMRegister, $rtmp$$Register,
4549 true /*min*/, true /*single*/);
4550 %}
4551 ins_pipe( pipe_slow );
4552 %}
4553
4554 // min = java.lang.Math.min(double a, double b)
4555 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
4556 predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
4557 match(Set dst (MinD a b));
4558 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4559 format %{ "minD $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
4560 ins_encode %{
4561 __ vminmax_fp(Op_MinV, T_DOUBLE, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4562 %}
4563 ins_pipe( pipe_slow );
4564 %}
4565
4566 instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xtmp, rRegL rtmp, rFlagsReg cr) %{
4567 predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
4568 match(Set dst (MinD a b));
4569 effect(USE a, USE b, TEMP xtmp, TEMP rtmp, KILL cr);
4570
4571 format %{ "maxD_reduction $dst, $a, $b \t! using $xtmp and $rtmp as TEMP" %}
4572 ins_encode %{
4573 emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xtmp$$XMMRegister, $rtmp$$Register,
4574 true /*min*/, false /*single*/);
4575 %}
4576 ins_pipe( pipe_slow );
4577 %}
4578
4579 // Load Effective Address
4580 instruct leaP8(rRegP dst, indOffset8 mem)
4581 %{
4582 match(Set dst mem);
4583
4584 ins_cost(110); // XXX
4585 format %{ "leaq $dst, $mem\t# ptr 8" %}
4586 ins_encode %{
4587 __ leaq($dst$$Register, $mem$$Address);
4588 %}
4589 ins_pipe(ialu_reg_reg_fat);
4590 %}
4591
4592 instruct leaP32(rRegP dst, indOffset32 mem)
4593 %{
4594 match(Set dst mem);
4595
4596 ins_cost(110);
4597 format %{ "leaq $dst, $mem\t# ptr 32" %}
4598 ins_encode %{
4599 __ leaq($dst$$Register, $mem$$Address);
4600 %}
4601 ins_pipe(ialu_reg_reg_fat);
4602 %}
4603
4604 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
4605 %{
4606 match(Set dst mem);
4607
4608 ins_cost(110);
4609 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
4610 ins_encode %{
4611 __ leaq($dst$$Register, $mem$$Address);
4612 %}
4613 ins_pipe(ialu_reg_reg_fat);
4614 %}
4615
4616 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
4617 %{
4618 match(Set dst mem);
4619
4620 ins_cost(110);
4621 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
4622 ins_encode %{
4623 __ leaq($dst$$Register, $mem$$Address);
4624 %}
4625 ins_pipe(ialu_reg_reg_fat);
4626 %}
4627
4628 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
4629 %{
4630 match(Set dst mem);
4631
4632 ins_cost(110);
4633 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
4634 ins_encode %{
4635 __ leaq($dst$$Register, $mem$$Address);
4636 %}
4637 ins_pipe(ialu_reg_reg_fat);
4638 %}
4639
4640 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
4641 %{
4642 match(Set dst mem);
4643
4644 ins_cost(110);
4645 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
4646 ins_encode %{
4647 __ leaq($dst$$Register, $mem$$Address);
4648 %}
4649 ins_pipe(ialu_reg_reg_fat);
4650 %}
4651
4652 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
4653 %{
4654 match(Set dst mem);
4655
4656 ins_cost(110);
4657 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
4658 ins_encode %{
4659 __ leaq($dst$$Register, $mem$$Address);
4660 %}
4661 ins_pipe(ialu_reg_reg_fat);
4662 %}
4663
4664 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
4665 %{
4666 match(Set dst mem);
4667
4668 ins_cost(110);
4669 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
4670 ins_encode %{
4671 __ leaq($dst$$Register, $mem$$Address);
4672 %}
4673 ins_pipe(ialu_reg_reg_fat);
4674 %}
4675
4676 // Load Effective Address which uses Narrow (32-bits) oop
4677 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
4678 %{
4679 predicate(UseCompressedOops && (CompressedOops::shift() != 0));
4680 match(Set dst mem);
4681
4682 ins_cost(110);
4683 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
4684 ins_encode %{
4685 __ leaq($dst$$Register, $mem$$Address);
4686 %}
4687 ins_pipe(ialu_reg_reg_fat);
4688 %}
4689
4690 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
4691 %{
4692 predicate(CompressedOops::shift() == 0);
4693 match(Set dst mem);
4694
4695 ins_cost(110); // XXX
4696 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
4697 ins_encode %{
4698 __ leaq($dst$$Register, $mem$$Address);
4699 %}
4700 ins_pipe(ialu_reg_reg_fat);
4701 %}
4702
4703 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
4704 %{
4705 predicate(CompressedOops::shift() == 0);
4706 match(Set dst mem);
4707
4708 ins_cost(110);
4709 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
4710 ins_encode %{
4711 __ leaq($dst$$Register, $mem$$Address);
4712 %}
4713 ins_pipe(ialu_reg_reg_fat);
4714 %}
4715
4716 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
4717 %{
4718 predicate(CompressedOops::shift() == 0);
4719 match(Set dst mem);
4720
4721 ins_cost(110);
4722 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
4723 ins_encode %{
4724 __ leaq($dst$$Register, $mem$$Address);
4725 %}
4726 ins_pipe(ialu_reg_reg_fat);
4727 %}
4728
4729 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
4730 %{
4731 predicate(CompressedOops::shift() == 0);
4732 match(Set dst mem);
4733
4734 ins_cost(110);
4735 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
4736 ins_encode %{
4737 __ leaq($dst$$Register, $mem$$Address);
4738 %}
4739 ins_pipe(ialu_reg_reg_fat);
4740 %}
4741
4742 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
4743 %{
4744 predicate(CompressedOops::shift() == 0);
4745 match(Set dst mem);
4746
4747 ins_cost(110);
4748 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
4749 ins_encode %{
4750 __ leaq($dst$$Register, $mem$$Address);
4751 %}
4752 ins_pipe(ialu_reg_reg_fat);
4753 %}
4754
4755 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
4756 %{
4757 predicate(CompressedOops::shift() == 0);
4758 match(Set dst mem);
4759
4760 ins_cost(110);
4761 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
4762 ins_encode %{
4763 __ leaq($dst$$Register, $mem$$Address);
4764 %}
4765 ins_pipe(ialu_reg_reg_fat);
4766 %}
4767
4768 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
4769 %{
4770 predicate(CompressedOops::shift() == 0);
4771 match(Set dst mem);
4772
4773 ins_cost(110);
4774 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
4775 ins_encode %{
4776 __ leaq($dst$$Register, $mem$$Address);
4777 %}
4778 ins_pipe(ialu_reg_reg_fat);
4779 %}
4780
4781 instruct loadConI(rRegI dst, immI src)
4782 %{
4783 match(Set dst src);
4784
4785 format %{ "movl $dst, $src\t# int" %}
4786 ins_encode %{
4787 __ movl($dst$$Register, $src$$constant);
4788 %}
4789 ins_pipe(ialu_reg_fat); // XXX
4790 %}
4791
4792 instruct loadConI0(rRegI dst, immI_0 src, rFlagsReg cr)
4793 %{
4794 match(Set dst src);
4795 effect(KILL cr);
4796
4797 ins_cost(50);
4798 format %{ "xorl $dst, $dst\t# int" %}
4799 ins_encode %{
4800 __ xorl($dst$$Register, $dst$$Register);
4801 %}
4802 ins_pipe(ialu_reg);
4803 %}
4804
4805 instruct loadConL(rRegL dst, immL src)
4806 %{
4807 match(Set dst src);
4808
4809 ins_cost(150);
4810 format %{ "movq $dst, $src\t# long" %}
4811 ins_encode %{
4812 __ mov64($dst$$Register, $src$$constant);
4813 %}
4814 ins_pipe(ialu_reg);
4815 %}
4816
4817 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
4818 %{
4819 match(Set dst src);
4820 effect(KILL cr);
4821
4822 ins_cost(50);
4823 format %{ "xorl $dst, $dst\t# long" %}
4824 ins_encode %{
4825 __ xorl($dst$$Register, $dst$$Register);
4826 %}
4827 ins_pipe(ialu_reg); // XXX
4828 %}
4829
4830 instruct loadConUL32(rRegL dst, immUL32 src)
4831 %{
4832 match(Set dst src);
4833
4834 ins_cost(60);
4835 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
4836 ins_encode %{
4837 __ movl($dst$$Register, $src$$constant);
4838 %}
4839 ins_pipe(ialu_reg);
4840 %}
4841
4842 instruct loadConL32(rRegL dst, immL32 src)
4843 %{
4844 match(Set dst src);
4845
4846 ins_cost(70);
4847 format %{ "movq $dst, $src\t# long (32-bit)" %}
4848 ins_encode %{
4849 __ movq($dst$$Register, $src$$constant);
4850 %}
4851 ins_pipe(ialu_reg);
4852 %}
4853
4854 instruct loadConP(rRegP dst, immP con) %{
4855 match(Set dst con);
4856
4857 format %{ "movq $dst, $con\t# ptr" %}
4858 ins_encode %{
4859 __ mov64($dst$$Register, $con$$constant, $con->constant_reloc(), RELOC_IMM64);
4860 %}
4861 ins_pipe(ialu_reg_fat); // XXX
4862 %}
4863
4864 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
4865 %{
4866 match(Set dst src);
4867 effect(KILL cr);
4868
4869 ins_cost(50);
4870 format %{ "xorl $dst, $dst\t# ptr" %}
4871 ins_encode %{
4872 __ xorl($dst$$Register, $dst$$Register);
4873 %}
4874 ins_pipe(ialu_reg);
4875 %}
4876
4877 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
4878 %{
4879 match(Set dst src);
4880 effect(KILL cr);
4881
4882 ins_cost(60);
4883 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
4884 ins_encode %{
4885 __ movl($dst$$Register, $src$$constant);
4886 %}
4887 ins_pipe(ialu_reg);
4888 %}
4889
4890 instruct loadConF(regF dst, immF con) %{
4891 match(Set dst con);
4892 ins_cost(125);
4893 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
4894 ins_encode %{
4895 __ movflt($dst$$XMMRegister, $constantaddress($con));
4896 %}
4897 ins_pipe(pipe_slow);
4898 %}
4899
4900 instruct loadConH(regF dst, immH con) %{
4901 match(Set dst con);
4902 ins_cost(125);
4903 format %{ "movss $dst, [$constantaddress]\t# load from constant table: halffloat=$con" %}
4904 ins_encode %{
4905 __ movflt($dst$$XMMRegister, $constantaddress($con));
4906 %}
4907 ins_pipe(pipe_slow);
4908 %}
4909
4910 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
4911 match(Set dst src);
4912 effect(KILL cr);
4913 format %{ "xorq $dst, $src\t# compressed null pointer" %}
4914 ins_encode %{
4915 __ xorq($dst$$Register, $dst$$Register);
4916 %}
4917 ins_pipe(ialu_reg);
4918 %}
4919
4920 instruct loadConN(rRegN dst, immN src) %{
4921 match(Set dst src);
4922
4923 ins_cost(125);
4924 format %{ "movl $dst, $src\t# compressed ptr" %}
4925 ins_encode %{
4926 address con = (address)$src$$constant;
4927 if (con == nullptr) {
4928 ShouldNotReachHere();
4929 } else {
4930 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
4931 }
4932 %}
4933 ins_pipe(ialu_reg_fat); // XXX
4934 %}
4935
4936 instruct loadConNKlass(rRegN dst, immNKlass src) %{
4937 match(Set dst src);
4938
4939 ins_cost(125);
4940 format %{ "movl $dst, $src\t# compressed klass ptr" %}
4941 ins_encode %{
4942 address con = (address)$src$$constant;
4943 if (con == nullptr) {
4944 ShouldNotReachHere();
4945 } else {
4946 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
4947 }
4948 %}
4949 ins_pipe(ialu_reg_fat); // XXX
4950 %}
4951
4952 instruct loadConF0(regF dst, immF0 src)
4953 %{
4954 match(Set dst src);
4955 ins_cost(100);
4956
4957 format %{ "xorps $dst, $dst\t# float 0.0" %}
4958 ins_encode %{
4959 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
4960 %}
4961 ins_pipe(pipe_slow);
4962 %}
4963
4964 // Use the same format since predicate() can not be used here.
4965 instruct loadConD(regD dst, immD con) %{
4966 match(Set dst con);
4967 ins_cost(125);
4968 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
4969 ins_encode %{
4970 __ movdbl($dst$$XMMRegister, $constantaddress($con));
4971 %}
4972 ins_pipe(pipe_slow);
4973 %}
4974
4975 instruct loadConD0(regD dst, immD0 src)
4976 %{
4977 match(Set dst src);
4978 ins_cost(100);
4979
4980 format %{ "xorpd $dst, $dst\t# double 0.0" %}
4981 ins_encode %{
4982 __ xorpd($dst$$XMMRegister, $dst$$XMMRegister);
4983 %}
4984 ins_pipe(pipe_slow);
4985 %}
4986
4987 instruct loadSSI(rRegI dst, stackSlotI src)
4988 %{
4989 match(Set dst src);
4990
4991 ins_cost(125);
4992 format %{ "movl $dst, $src\t# int stk" %}
4993 ins_encode %{
4994 __ movl($dst$$Register, $src$$Address);
4995 %}
4996 ins_pipe(ialu_reg_mem);
4997 %}
4998
4999 instruct loadSSL(rRegL dst, stackSlotL src)
5000 %{
5001 match(Set dst src);
5002
5003 ins_cost(125);
5004 format %{ "movq $dst, $src\t# long stk" %}
5005 ins_encode %{
5006 __ movq($dst$$Register, $src$$Address);
5007 %}
5008 ins_pipe(ialu_reg_mem);
5009 %}
5010
5011 instruct loadSSP(rRegP dst, stackSlotP src)
5012 %{
5013 match(Set dst src);
5014
5015 ins_cost(125);
5016 format %{ "movq $dst, $src\t# ptr stk" %}
5017 ins_encode %{
5018 __ movq($dst$$Register, $src$$Address);
5019 %}
5020 ins_pipe(ialu_reg_mem);
5021 %}
5022
5023 instruct loadSSF(regF dst, stackSlotF src)
5024 %{
5025 match(Set dst src);
5026
5027 ins_cost(125);
5028 format %{ "movss $dst, $src\t# float stk" %}
5029 ins_encode %{
5030 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5031 %}
5032 ins_pipe(pipe_slow); // XXX
5033 %}
5034
5035 // Use the same format since predicate() can not be used here.
5036 instruct loadSSD(regD dst, stackSlotD src)
5037 %{
5038 match(Set dst src);
5039
5040 ins_cost(125);
5041 format %{ "movsd $dst, $src\t# double stk" %}
5042 ins_encode %{
5043 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5044 %}
5045 ins_pipe(pipe_slow); // XXX
5046 %}
5047
5048 // Prefetch instructions for allocation.
5049 // Must be safe to execute with invalid address (cannot fault).
5050
5051 instruct prefetchAlloc( memory mem ) %{
5052 predicate(AllocatePrefetchInstr==3);
5053 match(PrefetchAllocation mem);
5054 ins_cost(125);
5055
5056 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5057 ins_encode %{
5058 __ prefetchw($mem$$Address);
5059 %}
5060 ins_pipe(ialu_mem);
5061 %}
5062
5063 instruct prefetchAllocNTA( memory mem ) %{
5064 predicate(AllocatePrefetchInstr==0);
5065 match(PrefetchAllocation mem);
5066 ins_cost(125);
5067
5068 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5069 ins_encode %{
5070 __ prefetchnta($mem$$Address);
5071 %}
5072 ins_pipe(ialu_mem);
5073 %}
5074
5075 instruct prefetchAllocT0( memory mem ) %{
5076 predicate(AllocatePrefetchInstr==1);
5077 match(PrefetchAllocation mem);
5078 ins_cost(125);
5079
5080 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5081 ins_encode %{
5082 __ prefetcht0($mem$$Address);
5083 %}
5084 ins_pipe(ialu_mem);
5085 %}
5086
5087 instruct prefetchAllocT2( memory mem ) %{
5088 predicate(AllocatePrefetchInstr==2);
5089 match(PrefetchAllocation mem);
5090 ins_cost(125);
5091
5092 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5093 ins_encode %{
5094 __ prefetcht2($mem$$Address);
5095 %}
5096 ins_pipe(ialu_mem);
5097 %}
5098
5099 //----------Store Instructions-------------------------------------------------
5100
5101 // Store Byte
5102 instruct storeB(memory mem, rRegI src)
5103 %{
5104 match(Set mem (StoreB mem src));
5105
5106 ins_cost(125); // XXX
5107 format %{ "movb $mem, $src\t# byte" %}
5108 ins_encode %{
5109 __ movb($mem$$Address, $src$$Register);
5110 %}
5111 ins_pipe(ialu_mem_reg);
5112 %}
5113
5114 // Store Char/Short
5115 instruct storeC(memory mem, rRegI src)
5116 %{
5117 match(Set mem (StoreC mem src));
5118
5119 ins_cost(125); // XXX
5120 format %{ "movw $mem, $src\t# char/short" %}
5121 ins_encode %{
5122 __ movw($mem$$Address, $src$$Register);
5123 %}
5124 ins_pipe(ialu_mem_reg);
5125 %}
5126
5127 // Store Integer
5128 instruct storeI(memory mem, rRegI src)
5129 %{
5130 match(Set mem (StoreI mem src));
5131
5132 ins_cost(125); // XXX
5133 format %{ "movl $mem, $src\t# int" %}
5134 ins_encode %{
5135 __ movl($mem$$Address, $src$$Register);
5136 %}
5137 ins_pipe(ialu_mem_reg);
5138 %}
5139
5140 // Store Long
5141 instruct storeL(memory mem, rRegL src)
5142 %{
5143 match(Set mem (StoreL mem src));
5144
5145 ins_cost(125); // XXX
5146 format %{ "movq $mem, $src\t# long" %}
5147 ins_encode %{
5148 __ movq($mem$$Address, $src$$Register);
5149 %}
5150 ins_pipe(ialu_mem_reg); // XXX
5151 %}
5152
5153 // Store Pointer
5154 instruct storeP(memory mem, any_RegP src)
5155 %{
5156 predicate(n->as_Store()->barrier_data() == 0);
5157 match(Set mem (StoreP mem src));
5158
5159 ins_cost(125); // XXX
5160 format %{ "movq $mem, $src\t# ptr" %}
5161 ins_encode %{
5162 __ movq($mem$$Address, $src$$Register);
5163 %}
5164 ins_pipe(ialu_mem_reg);
5165 %}
5166
5167 instruct storeImmP0(memory mem, immP0 zero)
5168 %{
5169 predicate(UseCompressedOops && (CompressedOops::base() == nullptr) && n->as_Store()->barrier_data() == 0);
5170 match(Set mem (StoreP mem zero));
5171
5172 ins_cost(125); // XXX
5173 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5174 ins_encode %{
5175 __ movq($mem$$Address, r12);
5176 %}
5177 ins_pipe(ialu_mem_reg);
5178 %}
5179
5180 // Store Null Pointer, mark word, or other simple pointer constant.
5181 instruct storeImmP(memory mem, immP31 src)
5182 %{
5183 predicate(n->as_Store()->barrier_data() == 0);
5184 match(Set mem (StoreP mem src));
5185
5186 ins_cost(150); // XXX
5187 format %{ "movq $mem, $src\t# ptr" %}
5188 ins_encode %{
5189 __ movq($mem$$Address, $src$$constant);
5190 %}
5191 ins_pipe(ialu_mem_imm);
5192 %}
5193
5194 // Store Compressed Pointer
5195 instruct storeN(memory mem, rRegN src)
5196 %{
5197 predicate(n->as_Store()->barrier_data() == 0);
5198 match(Set mem (StoreN mem src));
5199
5200 ins_cost(125); // XXX
5201 format %{ "movl $mem, $src\t# compressed ptr" %}
5202 ins_encode %{
5203 __ movl($mem$$Address, $src$$Register);
5204 %}
5205 ins_pipe(ialu_mem_reg);
5206 %}
5207
5208 instruct storeNKlass(memory mem, rRegN src)
5209 %{
5210 match(Set mem (StoreNKlass mem src));
5211
5212 ins_cost(125); // XXX
5213 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5214 ins_encode %{
5215 __ movl($mem$$Address, $src$$Register);
5216 %}
5217 ins_pipe(ialu_mem_reg);
5218 %}
5219
5220 instruct storeImmN0(memory mem, immN0 zero)
5221 %{
5222 predicate(CompressedOops::base() == nullptr && n->as_Store()->barrier_data() == 0);
5223 match(Set mem (StoreN mem zero));
5224
5225 ins_cost(125); // XXX
5226 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5227 ins_encode %{
5228 __ movl($mem$$Address, r12);
5229 %}
5230 ins_pipe(ialu_mem_reg);
5231 %}
5232
5233 instruct storeImmN(memory mem, immN src)
5234 %{
5235 predicate(n->as_Store()->barrier_data() == 0);
5236 match(Set mem (StoreN mem src));
5237
5238 ins_cost(150); // XXX
5239 format %{ "movl $mem, $src\t# compressed ptr" %}
5240 ins_encode %{
5241 address con = (address)$src$$constant;
5242 if (con == nullptr) {
5243 __ movl($mem$$Address, 0);
5244 } else {
5245 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5246 }
5247 %}
5248 ins_pipe(ialu_mem_imm);
5249 %}
5250
5251 instruct storeImmNKlass(memory mem, immNKlass src)
5252 %{
5253 match(Set mem (StoreNKlass mem src));
5254
5255 ins_cost(150); // XXX
5256 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5257 ins_encode %{
5258 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5259 %}
5260 ins_pipe(ialu_mem_imm);
5261 %}
5262
5263 // Store Integer Immediate
5264 instruct storeImmI0(memory mem, immI_0 zero)
5265 %{
5266 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5267 match(Set mem (StoreI mem zero));
5268
5269 ins_cost(125); // XXX
5270 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5271 ins_encode %{
5272 __ movl($mem$$Address, r12);
5273 %}
5274 ins_pipe(ialu_mem_reg);
5275 %}
5276
5277 instruct storeImmI(memory mem, immI src)
5278 %{
5279 match(Set mem (StoreI mem src));
5280
5281 ins_cost(150);
5282 format %{ "movl $mem, $src\t# int" %}
5283 ins_encode %{
5284 __ movl($mem$$Address, $src$$constant);
5285 %}
5286 ins_pipe(ialu_mem_imm);
5287 %}
5288
5289 // Store Long Immediate
5290 instruct storeImmL0(memory mem, immL0 zero)
5291 %{
5292 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5293 match(Set mem (StoreL mem zero));
5294
5295 ins_cost(125); // XXX
5296 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5297 ins_encode %{
5298 __ movq($mem$$Address, r12);
5299 %}
5300 ins_pipe(ialu_mem_reg);
5301 %}
5302
5303 instruct storeImmL(memory mem, immL32 src)
5304 %{
5305 match(Set mem (StoreL mem src));
5306
5307 ins_cost(150);
5308 format %{ "movq $mem, $src\t# long" %}
5309 ins_encode %{
5310 __ movq($mem$$Address, $src$$constant);
5311 %}
5312 ins_pipe(ialu_mem_imm);
5313 %}
5314
5315 // Store Short/Char Immediate
5316 instruct storeImmC0(memory mem, immI_0 zero)
5317 %{
5318 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5319 match(Set mem (StoreC mem zero));
5320
5321 ins_cost(125); // XXX
5322 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5323 ins_encode %{
5324 __ movw($mem$$Address, r12);
5325 %}
5326 ins_pipe(ialu_mem_reg);
5327 %}
5328
5329 instruct storeImmI16(memory mem, immI16 src)
5330 %{
5331 predicate(UseStoreImmI16);
5332 match(Set mem (StoreC mem src));
5333
5334 ins_cost(150);
5335 format %{ "movw $mem, $src\t# short/char" %}
5336 ins_encode %{
5337 __ movw($mem$$Address, $src$$constant);
5338 %}
5339 ins_pipe(ialu_mem_imm);
5340 %}
5341
5342 // Store Byte Immediate
5343 instruct storeImmB0(memory mem, immI_0 zero)
5344 %{
5345 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5346 match(Set mem (StoreB mem zero));
5347
5348 ins_cost(125); // XXX
5349 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5350 ins_encode %{
5351 __ movb($mem$$Address, r12);
5352 %}
5353 ins_pipe(ialu_mem_reg);
5354 %}
5355
5356 instruct storeImmB(memory mem, immI8 src)
5357 %{
5358 match(Set mem (StoreB mem src));
5359
5360 ins_cost(150); // XXX
5361 format %{ "movb $mem, $src\t# byte" %}
5362 ins_encode %{
5363 __ movb($mem$$Address, $src$$constant);
5364 %}
5365 ins_pipe(ialu_mem_imm);
5366 %}
5367
5368 // Store Float
5369 instruct storeF(memory mem, regF src)
5370 %{
5371 match(Set mem (StoreF mem src));
5372
5373 ins_cost(95); // XXX
5374 format %{ "movss $mem, $src\t# float" %}
5375 ins_encode %{
5376 __ movflt($mem$$Address, $src$$XMMRegister);
5377 %}
5378 ins_pipe(pipe_slow); // XXX
5379 %}
5380
5381 // Store immediate Float value (it is faster than store from XMM register)
5382 instruct storeF0(memory mem, immF0 zero)
5383 %{
5384 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5385 match(Set mem (StoreF mem zero));
5386
5387 ins_cost(25); // XXX
5388 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5389 ins_encode %{
5390 __ movl($mem$$Address, r12);
5391 %}
5392 ins_pipe(ialu_mem_reg);
5393 %}
5394
5395 instruct storeF_imm(memory mem, immF src)
5396 %{
5397 match(Set mem (StoreF mem src));
5398
5399 ins_cost(50);
5400 format %{ "movl $mem, $src\t# float" %}
5401 ins_encode %{
5402 __ movl($mem$$Address, jint_cast($src$$constant));
5403 %}
5404 ins_pipe(ialu_mem_imm);
5405 %}
5406
5407 // Store Double
5408 instruct storeD(memory mem, regD src)
5409 %{
5410 match(Set mem (StoreD mem src));
5411
5412 ins_cost(95); // XXX
5413 format %{ "movsd $mem, $src\t# double" %}
5414 ins_encode %{
5415 __ movdbl($mem$$Address, $src$$XMMRegister);
5416 %}
5417 ins_pipe(pipe_slow); // XXX
5418 %}
5419
5420 // Store immediate double 0.0 (it is faster than store from XMM register)
5421 instruct storeD0_imm(memory mem, immD0 src)
5422 %{
5423 predicate(!UseCompressedOops || (CompressedOops::base() != nullptr));
5424 match(Set mem (StoreD mem src));
5425
5426 ins_cost(50);
5427 format %{ "movq $mem, $src\t# double 0." %}
5428 ins_encode %{
5429 __ movq($mem$$Address, $src$$constant);
5430 %}
5431 ins_pipe(ialu_mem_imm);
5432 %}
5433
5434 instruct storeD0(memory mem, immD0 zero)
5435 %{
5436 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5437 match(Set mem (StoreD mem zero));
5438
5439 ins_cost(25); // XXX
5440 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
5441 ins_encode %{
5442 __ movq($mem$$Address, r12);
5443 %}
5444 ins_pipe(ialu_mem_reg);
5445 %}
5446
5447 instruct storeSSI(stackSlotI dst, rRegI src)
5448 %{
5449 match(Set dst src);
5450
5451 ins_cost(100);
5452 format %{ "movl $dst, $src\t# int stk" %}
5453 ins_encode %{
5454 __ movl($dst$$Address, $src$$Register);
5455 %}
5456 ins_pipe( ialu_mem_reg );
5457 %}
5458
5459 instruct storeSSL(stackSlotL dst, rRegL src)
5460 %{
5461 match(Set dst src);
5462
5463 ins_cost(100);
5464 format %{ "movq $dst, $src\t# long stk" %}
5465 ins_encode %{
5466 __ movq($dst$$Address, $src$$Register);
5467 %}
5468 ins_pipe(ialu_mem_reg);
5469 %}
5470
5471 instruct storeSSP(stackSlotP dst, rRegP src)
5472 %{
5473 match(Set dst src);
5474
5475 ins_cost(100);
5476 format %{ "movq $dst, $src\t# ptr stk" %}
5477 ins_encode %{
5478 __ movq($dst$$Address, $src$$Register);
5479 %}
5480 ins_pipe(ialu_mem_reg);
5481 %}
5482
5483 instruct storeSSF(stackSlotF dst, regF src)
5484 %{
5485 match(Set dst src);
5486
5487 ins_cost(95); // XXX
5488 format %{ "movss $dst, $src\t# float stk" %}
5489 ins_encode %{
5490 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
5491 %}
5492 ins_pipe(pipe_slow); // XXX
5493 %}
5494
5495 instruct storeSSD(stackSlotD dst, regD src)
5496 %{
5497 match(Set dst src);
5498
5499 ins_cost(95); // XXX
5500 format %{ "movsd $dst, $src\t# double stk" %}
5501 ins_encode %{
5502 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
5503 %}
5504 ins_pipe(pipe_slow); // XXX
5505 %}
5506
5507 instruct cacheWB(indirect addr)
5508 %{
5509 predicate(VM_Version::supports_data_cache_line_flush());
5510 match(CacheWB addr);
5511
5512 ins_cost(100);
5513 format %{"cache wb $addr" %}
5514 ins_encode %{
5515 assert($addr->index_position() < 0, "should be");
5516 assert($addr$$disp == 0, "should be");
5517 __ cache_wb(Address($addr$$base$$Register, 0));
5518 %}
5519 ins_pipe(pipe_slow); // XXX
5520 %}
5521
5522 instruct cacheWBPreSync()
5523 %{
5524 predicate(VM_Version::supports_data_cache_line_flush());
5525 match(CacheWBPreSync);
5526
5527 ins_cost(100);
5528 format %{"cache wb presync" %}
5529 ins_encode %{
5530 __ cache_wbsync(true);
5531 %}
5532 ins_pipe(pipe_slow); // XXX
5533 %}
5534
5535 instruct cacheWBPostSync()
5536 %{
5537 predicate(VM_Version::supports_data_cache_line_flush());
5538 match(CacheWBPostSync);
5539
5540 ins_cost(100);
5541 format %{"cache wb postsync" %}
5542 ins_encode %{
5543 __ cache_wbsync(false);
5544 %}
5545 ins_pipe(pipe_slow); // XXX
5546 %}
5547
5548 //----------BSWAP Instructions-------------------------------------------------
5549 instruct bytes_reverse_int(rRegI dst) %{
5550 match(Set dst (ReverseBytesI dst));
5551
5552 format %{ "bswapl $dst" %}
5553 ins_encode %{
5554 __ bswapl($dst$$Register);
5555 %}
5556 ins_pipe( ialu_reg );
5557 %}
5558
5559 instruct bytes_reverse_long(rRegL dst) %{
5560 match(Set dst (ReverseBytesL dst));
5561
5562 format %{ "bswapq $dst" %}
5563 ins_encode %{
5564 __ bswapq($dst$$Register);
5565 %}
5566 ins_pipe( ialu_reg);
5567 %}
5568
5569 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
5570 match(Set dst (ReverseBytesUS dst));
5571 effect(KILL cr);
5572
5573 format %{ "bswapl $dst\n\t"
5574 "shrl $dst,16\n\t" %}
5575 ins_encode %{
5576 __ bswapl($dst$$Register);
5577 __ shrl($dst$$Register, 16);
5578 %}
5579 ins_pipe( ialu_reg );
5580 %}
5581
5582 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
5583 match(Set dst (ReverseBytesS dst));
5584 effect(KILL cr);
5585
5586 format %{ "bswapl $dst\n\t"
5587 "sar $dst,16\n\t" %}
5588 ins_encode %{
5589 __ bswapl($dst$$Register);
5590 __ sarl($dst$$Register, 16);
5591 %}
5592 ins_pipe( ialu_reg );
5593 %}
5594
5595 //---------- Zeros Count Instructions ------------------------------------------
5596
5597 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
5598 predicate(UseCountLeadingZerosInstruction);
5599 match(Set dst (CountLeadingZerosI src));
5600 effect(KILL cr);
5601
5602 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
5603 ins_encode %{
5604 __ lzcntl($dst$$Register, $src$$Register);
5605 %}
5606 ins_pipe(ialu_reg);
5607 %}
5608
5609 instruct countLeadingZerosI_mem(rRegI dst, memory src, rFlagsReg cr) %{
5610 predicate(UseCountLeadingZerosInstruction);
5611 match(Set dst (CountLeadingZerosI (LoadI src)));
5612 effect(KILL cr);
5613 ins_cost(175);
5614 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
5615 ins_encode %{
5616 __ lzcntl($dst$$Register, $src$$Address);
5617 %}
5618 ins_pipe(ialu_reg_mem);
5619 %}
5620
5621 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
5622 predicate(!UseCountLeadingZerosInstruction);
5623 match(Set dst (CountLeadingZerosI src));
5624 effect(KILL cr);
5625
5626 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
5627 "jnz skip\n\t"
5628 "movl $dst, -1\n"
5629 "skip:\n\t"
5630 "negl $dst\n\t"
5631 "addl $dst, 31" %}
5632 ins_encode %{
5633 Register Rdst = $dst$$Register;
5634 Register Rsrc = $src$$Register;
5635 Label skip;
5636 __ bsrl(Rdst, Rsrc);
5637 __ jccb(Assembler::notZero, skip);
5638 __ movl(Rdst, -1);
5639 __ bind(skip);
5640 __ negl(Rdst);
5641 __ addl(Rdst, BitsPerInt - 1);
5642 %}
5643 ins_pipe(ialu_reg);
5644 %}
5645
5646 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
5647 predicate(UseCountLeadingZerosInstruction);
5648 match(Set dst (CountLeadingZerosL src));
5649 effect(KILL cr);
5650
5651 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
5652 ins_encode %{
5653 __ lzcntq($dst$$Register, $src$$Register);
5654 %}
5655 ins_pipe(ialu_reg);
5656 %}
5657
5658 instruct countLeadingZerosL_mem(rRegI dst, memory src, rFlagsReg cr) %{
5659 predicate(UseCountLeadingZerosInstruction);
5660 match(Set dst (CountLeadingZerosL (LoadL src)));
5661 effect(KILL cr);
5662 ins_cost(175);
5663 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
5664 ins_encode %{
5665 __ lzcntq($dst$$Register, $src$$Address);
5666 %}
5667 ins_pipe(ialu_reg_mem);
5668 %}
5669
5670 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
5671 predicate(!UseCountLeadingZerosInstruction);
5672 match(Set dst (CountLeadingZerosL src));
5673 effect(KILL cr);
5674
5675 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
5676 "jnz skip\n\t"
5677 "movl $dst, -1\n"
5678 "skip:\n\t"
5679 "negl $dst\n\t"
5680 "addl $dst, 63" %}
5681 ins_encode %{
5682 Register Rdst = $dst$$Register;
5683 Register Rsrc = $src$$Register;
5684 Label skip;
5685 __ bsrq(Rdst, Rsrc);
5686 __ jccb(Assembler::notZero, skip);
5687 __ movl(Rdst, -1);
5688 __ bind(skip);
5689 __ negl(Rdst);
5690 __ addl(Rdst, BitsPerLong - 1);
5691 %}
5692 ins_pipe(ialu_reg);
5693 %}
5694
5695 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
5696 predicate(UseCountTrailingZerosInstruction);
5697 match(Set dst (CountTrailingZerosI src));
5698 effect(KILL cr);
5699
5700 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
5701 ins_encode %{
5702 __ tzcntl($dst$$Register, $src$$Register);
5703 %}
5704 ins_pipe(ialu_reg);
5705 %}
5706
5707 instruct countTrailingZerosI_mem(rRegI dst, memory src, rFlagsReg cr) %{
5708 predicate(UseCountTrailingZerosInstruction);
5709 match(Set dst (CountTrailingZerosI (LoadI src)));
5710 effect(KILL cr);
5711 ins_cost(175);
5712 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
5713 ins_encode %{
5714 __ tzcntl($dst$$Register, $src$$Address);
5715 %}
5716 ins_pipe(ialu_reg_mem);
5717 %}
5718
5719 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
5720 predicate(!UseCountTrailingZerosInstruction);
5721 match(Set dst (CountTrailingZerosI src));
5722 effect(KILL cr);
5723
5724 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
5725 "jnz done\n\t"
5726 "movl $dst, 32\n"
5727 "done:" %}
5728 ins_encode %{
5729 Register Rdst = $dst$$Register;
5730 Label done;
5731 __ bsfl(Rdst, $src$$Register);
5732 __ jccb(Assembler::notZero, done);
5733 __ movl(Rdst, BitsPerInt);
5734 __ bind(done);
5735 %}
5736 ins_pipe(ialu_reg);
5737 %}
5738
5739 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
5740 predicate(UseCountTrailingZerosInstruction);
5741 match(Set dst (CountTrailingZerosL src));
5742 effect(KILL cr);
5743
5744 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
5745 ins_encode %{
5746 __ tzcntq($dst$$Register, $src$$Register);
5747 %}
5748 ins_pipe(ialu_reg);
5749 %}
5750
5751 instruct countTrailingZerosL_mem(rRegI dst, memory src, rFlagsReg cr) %{
5752 predicate(UseCountTrailingZerosInstruction);
5753 match(Set dst (CountTrailingZerosL (LoadL src)));
5754 effect(KILL cr);
5755 ins_cost(175);
5756 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
5757 ins_encode %{
5758 __ tzcntq($dst$$Register, $src$$Address);
5759 %}
5760 ins_pipe(ialu_reg_mem);
5761 %}
5762
5763 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
5764 predicate(!UseCountTrailingZerosInstruction);
5765 match(Set dst (CountTrailingZerosL src));
5766 effect(KILL cr);
5767
5768 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
5769 "jnz done\n\t"
5770 "movl $dst, 64\n"
5771 "done:" %}
5772 ins_encode %{
5773 Register Rdst = $dst$$Register;
5774 Label done;
5775 __ bsfq(Rdst, $src$$Register);
5776 __ jccb(Assembler::notZero, done);
5777 __ movl(Rdst, BitsPerLong);
5778 __ bind(done);
5779 %}
5780 ins_pipe(ialu_reg);
5781 %}
5782
5783 //--------------- Reverse Operation Instructions ----------------
5784 instruct bytes_reversebit_int(rRegI dst, rRegI src, rRegI rtmp, rFlagsReg cr) %{
5785 predicate(!VM_Version::supports_gfni());
5786 match(Set dst (ReverseI src));
5787 effect(TEMP dst, TEMP rtmp, KILL cr);
5788 format %{ "reverse_int $dst $src\t! using $rtmp as TEMP" %}
5789 ins_encode %{
5790 __ reverseI($dst$$Register, $src$$Register, xnoreg, xnoreg, $rtmp$$Register);
5791 %}
5792 ins_pipe( ialu_reg );
5793 %}
5794
5795 instruct bytes_reversebit_int_gfni(rRegI dst, rRegI src, vlRegF xtmp1, vlRegF xtmp2, rRegL rtmp, rFlagsReg cr) %{
5796 predicate(VM_Version::supports_gfni());
5797 match(Set dst (ReverseI src));
5798 effect(TEMP dst, TEMP xtmp1, TEMP xtmp2, TEMP rtmp, KILL cr);
5799 format %{ "reverse_int $dst $src\t! using $rtmp, $xtmp1 and $xtmp2 as TEMP" %}
5800 ins_encode %{
5801 __ reverseI($dst$$Register, $src$$Register, $xtmp1$$XMMRegister, $xtmp2$$XMMRegister, $rtmp$$Register);
5802 %}
5803 ins_pipe( ialu_reg );
5804 %}
5805
5806 instruct bytes_reversebit_long(rRegL dst, rRegL src, rRegL rtmp1, rRegL rtmp2, rFlagsReg cr) %{
5807 predicate(!VM_Version::supports_gfni());
5808 match(Set dst (ReverseL src));
5809 effect(TEMP dst, TEMP rtmp1, TEMP rtmp2, KILL cr);
5810 format %{ "reverse_long $dst $src\t! using $rtmp1 and $rtmp2 as TEMP" %}
5811 ins_encode %{
5812 __ reverseL($dst$$Register, $src$$Register, xnoreg, xnoreg, $rtmp1$$Register, $rtmp2$$Register);
5813 %}
5814 ins_pipe( ialu_reg );
5815 %}
5816
5817 instruct bytes_reversebit_long_gfni(rRegL dst, rRegL src, vlRegD xtmp1, vlRegD xtmp2, rRegL rtmp, rFlagsReg cr) %{
5818 predicate(VM_Version::supports_gfni());
5819 match(Set dst (ReverseL src));
5820 effect(TEMP dst, TEMP xtmp1, TEMP xtmp2, TEMP rtmp, KILL cr);
5821 format %{ "reverse_long $dst $src\t! using $rtmp, $xtmp1 and $xtmp2 as TEMP" %}
5822 ins_encode %{
5823 __ reverseL($dst$$Register, $src$$Register, $xtmp1$$XMMRegister, $xtmp2$$XMMRegister, $rtmp$$Register, noreg);
5824 %}
5825 ins_pipe( ialu_reg );
5826 %}
5827
5828 //---------- Population Count Instructions -------------------------------------
5829
5830 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
5831 predicate(UsePopCountInstruction);
5832 match(Set dst (PopCountI src));
5833 effect(KILL cr);
5834
5835 format %{ "popcnt $dst, $src" %}
5836 ins_encode %{
5837 __ popcntl($dst$$Register, $src$$Register);
5838 %}
5839 ins_pipe(ialu_reg);
5840 %}
5841
5842 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
5843 predicate(UsePopCountInstruction);
5844 match(Set dst (PopCountI (LoadI mem)));
5845 effect(KILL cr);
5846
5847 format %{ "popcnt $dst, $mem" %}
5848 ins_encode %{
5849 __ popcntl($dst$$Register, $mem$$Address);
5850 %}
5851 ins_pipe(ialu_reg);
5852 %}
5853
5854 // Note: Long.bitCount(long) returns an int.
5855 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
5856 predicate(UsePopCountInstruction);
5857 match(Set dst (PopCountL src));
5858 effect(KILL cr);
5859
5860 format %{ "popcnt $dst, $src" %}
5861 ins_encode %{
5862 __ popcntq($dst$$Register, $src$$Register);
5863 %}
5864 ins_pipe(ialu_reg);
5865 %}
5866
5867 // Note: Long.bitCount(long) returns an int.
5868 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
5869 predicate(UsePopCountInstruction);
5870 match(Set dst (PopCountL (LoadL mem)));
5871 effect(KILL cr);
5872
5873 format %{ "popcnt $dst, $mem" %}
5874 ins_encode %{
5875 __ popcntq($dst$$Register, $mem$$Address);
5876 %}
5877 ins_pipe(ialu_reg);
5878 %}
5879
5880
5881 //----------MemBar Instructions-----------------------------------------------
5882 // Memory barrier flavors
5883
5884 instruct membar_acquire()
5885 %{
5886 match(MemBarAcquire);
5887 match(LoadFence);
5888 ins_cost(0);
5889
5890 size(0);
5891 format %{ "MEMBAR-acquire ! (empty encoding)" %}
5892 ins_encode();
5893 ins_pipe(empty);
5894 %}
5895
5896 instruct membar_acquire_lock()
5897 %{
5898 match(MemBarAcquireLock);
5899 ins_cost(0);
5900
5901 size(0);
5902 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
5903 ins_encode();
5904 ins_pipe(empty);
5905 %}
5906
5907 instruct membar_release()
5908 %{
5909 match(MemBarRelease);
5910 match(StoreFence);
5911 ins_cost(0);
5912
5913 size(0);
5914 format %{ "MEMBAR-release ! (empty encoding)" %}
5915 ins_encode();
5916 ins_pipe(empty);
5917 %}
5918
5919 instruct membar_release_lock()
5920 %{
5921 match(MemBarReleaseLock);
5922 ins_cost(0);
5923
5924 size(0);
5925 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
5926 ins_encode();
5927 ins_pipe(empty);
5928 %}
5929
5930 instruct membar_volatile(rFlagsReg cr) %{
5931 match(MemBarVolatile);
5932 effect(KILL cr);
5933 ins_cost(400);
5934
5935 format %{
5936 $$template
5937 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
5938 %}
5939 ins_encode %{
5940 __ membar(Assembler::StoreLoad);
5941 %}
5942 ins_pipe(pipe_slow);
5943 %}
5944
5945 instruct unnecessary_membar_volatile()
5946 %{
5947 match(MemBarVolatile);
5948 predicate(Matcher::post_store_load_barrier(n));
5949 ins_cost(0);
5950
5951 size(0);
5952 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
5953 ins_encode();
5954 ins_pipe(empty);
5955 %}
5956
5957 instruct membar_storestore() %{
5958 match(MemBarStoreStore);
5959 match(StoreStoreFence);
5960 ins_cost(0);
5961
5962 size(0);
5963 format %{ "MEMBAR-storestore (empty encoding)" %}
5964 ins_encode( );
5965 ins_pipe(empty);
5966 %}
5967
5968 //----------Move Instructions--------------------------------------------------
5969
5970 instruct castX2P(rRegP dst, rRegL src)
5971 %{
5972 match(Set dst (CastX2P src));
5973
5974 format %{ "movq $dst, $src\t# long->ptr" %}
5975 ins_encode %{
5976 if ($dst$$reg != $src$$reg) {
5977 __ movptr($dst$$Register, $src$$Register);
5978 }
5979 %}
5980 ins_pipe(ialu_reg_reg); // XXX
5981 %}
5982
5983 instruct castP2X(rRegL dst, rRegP src)
5984 %{
5985 match(Set dst (CastP2X src));
5986
5987 format %{ "movq $dst, $src\t# ptr -> long" %}
5988 ins_encode %{
5989 if ($dst$$reg != $src$$reg) {
5990 __ movptr($dst$$Register, $src$$Register);
5991 }
5992 %}
5993 ins_pipe(ialu_reg_reg); // XXX
5994 %}
5995
5996 // Convert oop into int for vectors alignment masking
5997 instruct convP2I(rRegI dst, rRegP src)
5998 %{
5999 match(Set dst (ConvL2I (CastP2X src)));
6000
6001 format %{ "movl $dst, $src\t# ptr -> int" %}
6002 ins_encode %{
6003 __ movl($dst$$Register, $src$$Register);
6004 %}
6005 ins_pipe(ialu_reg_reg); // XXX
6006 %}
6007
6008 // Convert compressed oop into int for vectors alignment masking
6009 // in case of 32bit oops (heap < 4Gb).
6010 instruct convN2I(rRegI dst, rRegN src)
6011 %{
6012 predicate(CompressedOops::shift() == 0);
6013 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6014
6015 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6016 ins_encode %{
6017 __ movl($dst$$Register, $src$$Register);
6018 %}
6019 ins_pipe(ialu_reg_reg); // XXX
6020 %}
6021
6022 // Convert oop pointer into compressed form
6023 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6024 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6025 match(Set dst (EncodeP src));
6026 effect(KILL cr);
6027 format %{ "encode_heap_oop $dst,$src" %}
6028 ins_encode %{
6029 Register s = $src$$Register;
6030 Register d = $dst$$Register;
6031 if (s != d) {
6032 __ movq(d, s);
6033 }
6034 __ encode_heap_oop(d);
6035 %}
6036 ins_pipe(ialu_reg_long);
6037 %}
6038
6039 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6040 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6041 match(Set dst (EncodeP src));
6042 effect(KILL cr);
6043 format %{ "encode_heap_oop_not_null $dst,$src" %}
6044 ins_encode %{
6045 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6046 %}
6047 ins_pipe(ialu_reg_long);
6048 %}
6049
6050 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6051 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6052 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6053 match(Set dst (DecodeN src));
6054 effect(KILL cr);
6055 format %{ "decode_heap_oop $dst,$src" %}
6056 ins_encode %{
6057 Register s = $src$$Register;
6058 Register d = $dst$$Register;
6059 if (s != d) {
6060 __ movq(d, s);
6061 }
6062 __ decode_heap_oop(d);
6063 %}
6064 ins_pipe(ialu_reg_long);
6065 %}
6066
6067 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6068 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6069 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6070 match(Set dst (DecodeN src));
6071 effect(KILL cr);
6072 format %{ "decode_heap_oop_not_null $dst,$src" %}
6073 ins_encode %{
6074 Register s = $src$$Register;
6075 Register d = $dst$$Register;
6076 if (s != d) {
6077 __ decode_heap_oop_not_null(d, s);
6078 } else {
6079 __ decode_heap_oop_not_null(d);
6080 }
6081 %}
6082 ins_pipe(ialu_reg_long);
6083 %}
6084
6085 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6086 match(Set dst (EncodePKlass src));
6087 effect(TEMP dst, KILL cr);
6088 format %{ "encode_and_move_klass_not_null $dst,$src" %}
6089 ins_encode %{
6090 __ encode_and_move_klass_not_null($dst$$Register, $src$$Register);
6091 %}
6092 ins_pipe(ialu_reg_long);
6093 %}
6094
6095 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6096 match(Set dst (DecodeNKlass src));
6097 effect(TEMP dst, KILL cr);
6098 format %{ "decode_and_move_klass_not_null $dst,$src" %}
6099 ins_encode %{
6100 __ decode_and_move_klass_not_null($dst$$Register, $src$$Register);
6101 %}
6102 ins_pipe(ialu_reg_long);
6103 %}
6104
6105 //----------Conditional Move---------------------------------------------------
6106 // Jump
6107 // dummy instruction for generating temp registers
6108 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6109 match(Jump (LShiftL switch_val shift));
6110 ins_cost(350);
6111 predicate(false);
6112 effect(TEMP dest);
6113
6114 format %{ "leaq $dest, [$constantaddress]\n\t"
6115 "jmp [$dest + $switch_val << $shift]\n\t" %}
6116 ins_encode %{
6117 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6118 // to do that and the compiler is using that register as one it can allocate.
6119 // So we build it all by hand.
6120 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6121 // ArrayAddress dispatch(table, index);
6122 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6123 __ lea($dest$$Register, $constantaddress);
6124 __ jmp(dispatch);
6125 %}
6126 ins_pipe(pipe_jmp);
6127 %}
6128
6129 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6130 match(Jump (AddL (LShiftL switch_val shift) offset));
6131 ins_cost(350);
6132 effect(TEMP dest);
6133
6134 format %{ "leaq $dest, [$constantaddress]\n\t"
6135 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6136 ins_encode %{
6137 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6138 // to do that and the compiler is using that register as one it can allocate.
6139 // So we build it all by hand.
6140 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6141 // ArrayAddress dispatch(table, index);
6142 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6143 __ lea($dest$$Register, $constantaddress);
6144 __ jmp(dispatch);
6145 %}
6146 ins_pipe(pipe_jmp);
6147 %}
6148
6149 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6150 match(Jump switch_val);
6151 ins_cost(350);
6152 effect(TEMP dest);
6153
6154 format %{ "leaq $dest, [$constantaddress]\n\t"
6155 "jmp [$dest + $switch_val]\n\t" %}
6156 ins_encode %{
6157 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6158 // to do that and the compiler is using that register as one it can allocate.
6159 // So we build it all by hand.
6160 // Address index(noreg, switch_reg, Address::times_1);
6161 // ArrayAddress dispatch(table, index);
6162 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6163 __ lea($dest$$Register, $constantaddress);
6164 __ jmp(dispatch);
6165 %}
6166 ins_pipe(pipe_jmp);
6167 %}
6168
6169 // Conditional move
6170 instruct cmovI_imm_01(rRegI dst, immI_1 src, rFlagsReg cr, cmpOp cop)
6171 %{
6172 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
6173 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6174
6175 ins_cost(100); // XXX
6176 format %{ "setbn$cop $dst\t# signed, int" %}
6177 ins_encode %{
6178 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6179 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6180 %}
6181 ins_pipe(ialu_reg);
6182 %}
6183
6184 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6185 %{
6186 predicate(!UseAPX);
6187 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6188
6189 ins_cost(200); // XXX
6190 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6191 ins_encode %{
6192 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6193 %}
6194 ins_pipe(pipe_cmov_reg);
6195 %}
6196
6197 instruct cmovI_reg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr, cmpOp cop)
6198 %{
6199 predicate(UseAPX);
6200 match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
6201
6202 ins_cost(200);
6203 format %{ "ecmovl$cop $dst, $src1, $src2\t# signed, int ndd" %}
6204 ins_encode %{
6205 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6206 %}
6207 ins_pipe(pipe_cmov_reg);
6208 %}
6209
6210 instruct cmovI_imm_01U(rRegI dst, immI_1 src, rFlagsRegU cr, cmpOpU cop)
6211 %{
6212 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
6213 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6214
6215 ins_cost(100); // XXX
6216 format %{ "setbn$cop $dst\t# unsigned, int" %}
6217 ins_encode %{
6218 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6219 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6220 %}
6221 ins_pipe(ialu_reg);
6222 %}
6223
6224 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6225 predicate(!UseAPX);
6226 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6227
6228 ins_cost(200); // XXX
6229 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6230 ins_encode %{
6231 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6232 %}
6233 ins_pipe(pipe_cmov_reg);
6234 %}
6235
6236 instruct cmovI_regU_ndd(rRegI dst, cmpOpU cop, rFlagsRegU cr, rRegI src1, rRegI src2) %{
6237 predicate(UseAPX);
6238 match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
6239
6240 ins_cost(200);
6241 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %}
6242 ins_encode %{
6243 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6244 %}
6245 ins_pipe(pipe_cmov_reg);
6246 %}
6247
6248 instruct cmovI_imm_01UCF(rRegI dst, immI_1 src, rFlagsRegUCF cr, cmpOpUCF cop)
6249 %{
6250 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
6251 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6252
6253 ins_cost(100); // XXX
6254 format %{ "setbn$cop $dst\t# unsigned, int" %}
6255 ins_encode %{
6256 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6257 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6258 %}
6259 ins_pipe(ialu_reg);
6260 %}
6261
6262 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6263 predicate(!UseAPX);
6264 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6265 ins_cost(200);
6266 expand %{
6267 cmovI_regU(cop, cr, dst, src);
6268 %}
6269 %}
6270
6271 instruct cmovI_regUCF_ndd(rRegI dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegI src1, rRegI src2) %{
6272 predicate(UseAPX);
6273 match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
6274 ins_cost(200);
6275 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %}
6276 ins_encode %{
6277 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6278 %}
6279 ins_pipe(pipe_cmov_reg);
6280 %}
6281
6282 instruct cmovI_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6283 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6284 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6285
6286 ins_cost(200); // XXX
6287 format %{ "cmovpl $dst, $src\n\t"
6288 "cmovnel $dst, $src" %}
6289 ins_encode %{
6290 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6291 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6292 %}
6293 ins_pipe(pipe_cmov_reg);
6294 %}
6295
6296 instruct cmovI_regUCF2_ne_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src1, rRegI src2) %{
6297 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6298 match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
6299
6300 ins_cost(200);
6301 format %{ "ecmovpl $dst, $src1, $src2\n\t"
6302 "ecmovnel $dst, $src1, $src2" %}
6303 ins_encode %{
6304 __ ecmovl(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6305 __ ecmovl(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6306 %}
6307 ins_pipe(pipe_cmov_reg);
6308 %}
6309
6310 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6311 // inputs of the CMove
6312 instruct cmovI_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6313 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6314 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6315
6316 ins_cost(200); // XXX
6317 format %{ "cmovpl $dst, $src\n\t"
6318 "cmovnel $dst, $src" %}
6319 ins_encode %{
6320 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6321 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6322 %}
6323 ins_pipe(pipe_cmov_reg);
6324 %}
6325
6326 // We need this special handling for only eq / neq comparison since NaN == NaN is false,
6327 // and parity flag bit is set if any of the operand is a NaN.
6328 instruct cmovI_regUCF2_eq_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src1, rRegI src2) %{
6329 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6330 match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
6331
6332 ins_cost(200);
6333 format %{ "ecmovpl $dst, $src1, $src2\n\t"
6334 "ecmovnel $dst, $src1, $src2" %}
6335 ins_encode %{
6336 __ ecmovl(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6337 __ ecmovl(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6338 %}
6339 ins_pipe(pipe_cmov_reg);
6340 %}
6341
6342 // Conditional move
6343 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6344 predicate(!UseAPX);
6345 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6346
6347 ins_cost(250); // XXX
6348 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6349 ins_encode %{
6350 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6351 %}
6352 ins_pipe(pipe_cmov_mem);
6353 %}
6354
6355 // Conditional move
6356 instruct cmovI_rReg_rReg_mem_ndd(rRegI dst, cmpOp cop, rFlagsReg cr, rRegI src1, memory src2)
6357 %{
6358 predicate(UseAPX);
6359 match(Set dst (CMoveI (Binary cop cr) (Binary src1 (LoadI src2))));
6360
6361 ins_cost(250);
6362 format %{ "ecmovl$cop $dst, $src1, $src2\t# signed, int ndd" %}
6363 ins_encode %{
6364 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6365 %}
6366 ins_pipe(pipe_cmov_mem);
6367 %}
6368
6369 // Conditional move
6370 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6371 %{
6372 predicate(!UseAPX);
6373 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6374
6375 ins_cost(250); // XXX
6376 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6377 ins_encode %{
6378 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6379 %}
6380 ins_pipe(pipe_cmov_mem);
6381 %}
6382
6383 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6384 predicate(!UseAPX);
6385 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6386 ins_cost(250);
6387 expand %{
6388 cmovI_memU(cop, cr, dst, src);
6389 %}
6390 %}
6391
6392 instruct cmovI_rReg_rReg_memU_ndd(rRegI dst, cmpOpU cop, rFlagsRegU cr, rRegI src1, memory src2)
6393 %{
6394 predicate(UseAPX);
6395 match(Set dst (CMoveI (Binary cop cr) (Binary src1 (LoadI src2))));
6396
6397 ins_cost(250);
6398 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %}
6399 ins_encode %{
6400 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6401 %}
6402 ins_pipe(pipe_cmov_mem);
6403 %}
6404
6405 instruct cmovI_rReg_rReg_memUCF_ndd(rRegI dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegI src1, memory src2)
6406 %{
6407 predicate(UseAPX);
6408 match(Set dst (CMoveI (Binary cop cr) (Binary src1 (LoadI src2))));
6409 ins_cost(250);
6410 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %}
6411 ins_encode %{
6412 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6413 %}
6414 ins_pipe(pipe_cmov_mem);
6415 %}
6416
6417 // Conditional move
6418 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6419 %{
6420 predicate(!UseAPX);
6421 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6422
6423 ins_cost(200); // XXX
6424 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6425 ins_encode %{
6426 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6427 %}
6428 ins_pipe(pipe_cmov_reg);
6429 %}
6430
6431 // Conditional move ndd
6432 instruct cmovN_reg_ndd(rRegN dst, rRegN src1, rRegN src2, rFlagsReg cr, cmpOp cop)
6433 %{
6434 predicate(UseAPX);
6435 match(Set dst (CMoveN (Binary cop cr) (Binary src1 src2)));
6436
6437 ins_cost(200);
6438 format %{ "ecmovl$cop $dst, $src1, $src2\t# signed, compressed ptr ndd" %}
6439 ins_encode %{
6440 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6441 %}
6442 ins_pipe(pipe_cmov_reg);
6443 %}
6444
6445 // Conditional move
6446 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6447 %{
6448 predicate(!UseAPX);
6449 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6450
6451 ins_cost(200); // XXX
6452 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6453 ins_encode %{
6454 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6455 %}
6456 ins_pipe(pipe_cmov_reg);
6457 %}
6458
6459 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6460 predicate(!UseAPX);
6461 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6462 ins_cost(200);
6463 expand %{
6464 cmovN_regU(cop, cr, dst, src);
6465 %}
6466 %}
6467
6468 // Conditional move ndd
6469 instruct cmovN_regU_ndd(rRegN dst, cmpOpU cop, rFlagsRegU cr, rRegN src1, rRegN src2)
6470 %{
6471 predicate(UseAPX);
6472 match(Set dst (CMoveN (Binary cop cr) (Binary src1 src2)));
6473
6474 ins_cost(200);
6475 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, compressed ptr ndd" %}
6476 ins_encode %{
6477 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6478 %}
6479 ins_pipe(pipe_cmov_reg);
6480 %}
6481
6482 instruct cmovN_regUCF_ndd(rRegN dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegN src1, rRegN src2) %{
6483 predicate(UseAPX);
6484 match(Set dst (CMoveN (Binary cop cr) (Binary src1 src2)));
6485 ins_cost(200);
6486 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, compressed ptr ndd" %}
6487 ins_encode %{
6488 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6489 %}
6490 ins_pipe(pipe_cmov_reg);
6491 %}
6492
6493 instruct cmovN_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6494 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6495 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6496
6497 ins_cost(200); // XXX
6498 format %{ "cmovpl $dst, $src\n\t"
6499 "cmovnel $dst, $src" %}
6500 ins_encode %{
6501 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6502 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6503 %}
6504 ins_pipe(pipe_cmov_reg);
6505 %}
6506
6507 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6508 // inputs of the CMove
6509 instruct cmovN_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6510 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6511 match(Set dst (CMoveN (Binary cop cr) (Binary src dst)));
6512
6513 ins_cost(200); // XXX
6514 format %{ "cmovpl $dst, $src\n\t"
6515 "cmovnel $dst, $src" %}
6516 ins_encode %{
6517 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6518 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6519 %}
6520 ins_pipe(pipe_cmov_reg);
6521 %}
6522
6523 // Conditional move
6524 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6525 %{
6526 predicate(!UseAPX);
6527 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6528
6529 ins_cost(200); // XXX
6530 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6531 ins_encode %{
6532 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6533 %}
6534 ins_pipe(pipe_cmov_reg); // XXX
6535 %}
6536
6537 // Conditional move ndd
6538 instruct cmovP_reg_ndd(rRegP dst, rRegP src1, rRegP src2, rFlagsReg cr, cmpOp cop)
6539 %{
6540 predicate(UseAPX);
6541 match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
6542
6543 ins_cost(200);
6544 format %{ "ecmovq$cop $dst, $src1, $src2\t# signed, ptr ndd" %}
6545 ins_encode %{
6546 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6547 %}
6548 ins_pipe(pipe_cmov_reg);
6549 %}
6550
6551 // Conditional move
6552 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6553 %{
6554 predicate(!UseAPX);
6555 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6556
6557 ins_cost(200); // XXX
6558 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6559 ins_encode %{
6560 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6561 %}
6562 ins_pipe(pipe_cmov_reg); // XXX
6563 %}
6564
6565 // Conditional move ndd
6566 instruct cmovP_regU_ndd(rRegP dst, cmpOpU cop, rFlagsRegU cr, rRegP src1, rRegP src2)
6567 %{
6568 predicate(UseAPX);
6569 match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
6570
6571 ins_cost(200);
6572 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, ptr ndd" %}
6573 ins_encode %{
6574 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6575 %}
6576 ins_pipe(pipe_cmov_reg);
6577 %}
6578
6579 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6580 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6581 ins_cost(200);
6582 expand %{
6583 cmovP_regU(cop, cr, dst, src);
6584 %}
6585 %}
6586
6587 instruct cmovP_regUCF_ndd(rRegP dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegP src1, rRegP src2) %{
6588 match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
6589 ins_cost(200);
6590 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, ptr ndd" %}
6591 ins_encode %{
6592 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6593 %}
6594 ins_pipe(pipe_cmov_reg);
6595 %}
6596
6597 instruct cmovP_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6598 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6599 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6600
6601 ins_cost(200); // XXX
6602 format %{ "cmovpq $dst, $src\n\t"
6603 "cmovneq $dst, $src" %}
6604 ins_encode %{
6605 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6606 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6607 %}
6608 ins_pipe(pipe_cmov_reg);
6609 %}
6610
6611 instruct cmovP_regUCF2_ne_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src1, rRegP src2) %{
6612 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6613 match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
6614
6615 ins_cost(200);
6616 format %{ "ecmovpq $dst, $src1, $src2\n\t"
6617 "ecmovneq $dst, $src1, $src2" %}
6618 ins_encode %{
6619 __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6620 __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6621 %}
6622 ins_pipe(pipe_cmov_reg);
6623 %}
6624
6625 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6626 // inputs of the CMove
6627 instruct cmovP_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6628 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6629 match(Set dst (CMoveP (Binary cop cr) (Binary src dst)));
6630
6631 ins_cost(200); // XXX
6632 format %{ "cmovpq $dst, $src\n\t"
6633 "cmovneq $dst, $src" %}
6634 ins_encode %{
6635 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6636 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6637 %}
6638 ins_pipe(pipe_cmov_reg);
6639 %}
6640
6641 instruct cmovP_regUCF2_eq_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src1, rRegP src2) %{
6642 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6643 match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
6644
6645 ins_cost(200);
6646 format %{ "ecmovpq $dst, $src1, $src2\n\t"
6647 "ecmovneq $dst, $src1, $src2" %}
6648 ins_encode %{
6649 __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6650 __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6651 %}
6652 ins_pipe(pipe_cmov_reg);
6653 %}
6654
6655 instruct cmovL_imm_01(rRegL dst, immL1 src, rFlagsReg cr, cmpOp cop)
6656 %{
6657 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
6658 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6659
6660 ins_cost(100); // XXX
6661 format %{ "setbn$cop $dst\t# signed, long" %}
6662 ins_encode %{
6663 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6664 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6665 %}
6666 ins_pipe(ialu_reg);
6667 %}
6668
6669 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6670 %{
6671 predicate(!UseAPX);
6672 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6673
6674 ins_cost(200); // XXX
6675 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6676 ins_encode %{
6677 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6678 %}
6679 ins_pipe(pipe_cmov_reg); // XXX
6680 %}
6681
6682 instruct cmovL_reg_ndd(rRegL dst, cmpOp cop, rFlagsReg cr, rRegL src1, rRegL src2)
6683 %{
6684 predicate(UseAPX);
6685 match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
6686
6687 ins_cost(200);
6688 format %{ "ecmovq$cop $dst, $src1, $src2\t# signed, long ndd" %}
6689 ins_encode %{
6690 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6691 %}
6692 ins_pipe(pipe_cmov_reg);
6693 %}
6694
6695 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6696 %{
6697 predicate(!UseAPX);
6698 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6699
6700 ins_cost(200); // XXX
6701 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6702 ins_encode %{
6703 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6704 %}
6705 ins_pipe(pipe_cmov_mem); // XXX
6706 %}
6707
6708 instruct cmovL_rReg_rReg_mem_ndd(rRegL dst, cmpOp cop, rFlagsReg cr, rRegL src1, memory src2)
6709 %{
6710 predicate(UseAPX);
6711 match(Set dst (CMoveL (Binary cop cr) (Binary src1 (LoadL src2))));
6712
6713 ins_cost(200);
6714 format %{ "ecmovq$cop $dst, $src1, $src2\t# signed, long ndd" %}
6715 ins_encode %{
6716 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6717 %}
6718 ins_pipe(pipe_cmov_mem);
6719 %}
6720
6721 instruct cmovL_imm_01U(rRegL dst, immL1 src, rFlagsRegU cr, cmpOpU cop)
6722 %{
6723 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
6724 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6725
6726 ins_cost(100); // XXX
6727 format %{ "setbn$cop $dst\t# unsigned, long" %}
6728 ins_encode %{
6729 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6730 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6731 %}
6732 ins_pipe(ialu_reg);
6733 %}
6734
6735 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6736 %{
6737 predicate(!UseAPX);
6738 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6739
6740 ins_cost(200); // XXX
6741 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6742 ins_encode %{
6743 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6744 %}
6745 ins_pipe(pipe_cmov_reg); // XXX
6746 %}
6747
6748 instruct cmovL_regU_ndd(rRegL dst, cmpOpU cop, rFlagsRegU cr, rRegL src1, rRegL src2)
6749 %{
6750 predicate(UseAPX);
6751 match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
6752
6753 ins_cost(200);
6754 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %}
6755 ins_encode %{
6756 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6757 %}
6758 ins_pipe(pipe_cmov_reg);
6759 %}
6760
6761 instruct cmovL_imm_01UCF(rRegL dst, immL1 src, rFlagsRegUCF cr, cmpOpUCF cop)
6762 %{
6763 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
6764 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6765
6766 ins_cost(100); // XXX
6767 format %{ "setbn$cop $dst\t# unsigned, long" %}
6768 ins_encode %{
6769 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6770 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6771 %}
6772 ins_pipe(ialu_reg);
6773 %}
6774
6775 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6776 predicate(!UseAPX);
6777 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6778 ins_cost(200);
6779 expand %{
6780 cmovL_regU(cop, cr, dst, src);
6781 %}
6782 %}
6783
6784 instruct cmovL_regUCF_ndd(rRegL dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegL src1, rRegL src2)
6785 %{
6786 predicate(UseAPX);
6787 match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
6788 ins_cost(200);
6789 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %}
6790 ins_encode %{
6791 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6792 %}
6793 ins_pipe(pipe_cmov_reg);
6794 %}
6795
6796 instruct cmovL_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6797 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6798 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6799
6800 ins_cost(200); // XXX
6801 format %{ "cmovpq $dst, $src\n\t"
6802 "cmovneq $dst, $src" %}
6803 ins_encode %{
6804 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6805 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6806 %}
6807 ins_pipe(pipe_cmov_reg);
6808 %}
6809
6810 instruct cmovL_regUCF2_ne_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src1, rRegL src2) %{
6811 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6812 match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
6813
6814 ins_cost(200);
6815 format %{ "ecmovpq $dst, $src1, $src2\n\t"
6816 "ecmovneq $dst, $src1, $src2" %}
6817 ins_encode %{
6818 __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6819 __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6820 %}
6821 ins_pipe(pipe_cmov_reg);
6822 %}
6823
6824 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6825 // inputs of the CMove
6826 instruct cmovL_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6827 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6828 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6829
6830 ins_cost(200); // XXX
6831 format %{ "cmovpq $dst, $src\n\t"
6832 "cmovneq $dst, $src" %}
6833 ins_encode %{
6834 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6835 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6836 %}
6837 ins_pipe(pipe_cmov_reg);
6838 %}
6839
6840 instruct cmovL_regUCF2_eq_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src1, rRegL src2) %{
6841 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6842 match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
6843
6844 ins_cost(200);
6845 format %{ "ecmovpq $dst, $src1, $src2\n\t"
6846 "ecmovneq $dst, $src1, $src2" %}
6847 ins_encode %{
6848 __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6849 __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6850 %}
6851 ins_pipe(pipe_cmov_reg);
6852 %}
6853
6854 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6855 %{
6856 predicate(!UseAPX);
6857 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6858
6859 ins_cost(200); // XXX
6860 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6861 ins_encode %{
6862 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6863 %}
6864 ins_pipe(pipe_cmov_mem); // XXX
6865 %}
6866
6867 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6868 predicate(!UseAPX);
6869 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6870 ins_cost(200);
6871 expand %{
6872 cmovL_memU(cop, cr, dst, src);
6873 %}
6874 %}
6875
6876 instruct cmovL_rReg_rReg_memU_ndd(rRegL dst, cmpOpU cop, rFlagsRegU cr, rRegL src1, memory src2)
6877 %{
6878 predicate(UseAPX);
6879 match(Set dst (CMoveL (Binary cop cr) (Binary src1 (LoadL src2))));
6880
6881 ins_cost(200);
6882 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %}
6883 ins_encode %{
6884 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6885 %}
6886 ins_pipe(pipe_cmov_mem);
6887 %}
6888
6889 instruct cmovL_rReg_rReg_memUCF_ndd(rRegL dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegL src1, memory src2)
6890 %{
6891 predicate(UseAPX);
6892 match(Set dst (CMoveL (Binary cop cr) (Binary src1 (LoadL src2))));
6893 ins_cost(200);
6894 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %}
6895 ins_encode %{
6896 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6897 %}
6898 ins_pipe(pipe_cmov_mem);
6899 %}
6900
6901 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6902 %{
6903 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6904
6905 ins_cost(200); // XXX
6906 format %{ "jn$cop skip\t# signed cmove float\n\t"
6907 "movss $dst, $src\n"
6908 "skip:" %}
6909 ins_encode %{
6910 Label Lskip;
6911 // Invert sense of branch from sense of CMOV
6912 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6913 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6914 __ bind(Lskip);
6915 %}
6916 ins_pipe(pipe_slow);
6917 %}
6918
6919 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6920 %{
6921 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6922
6923 ins_cost(200); // XXX
6924 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6925 "movss $dst, $src\n"
6926 "skip:" %}
6927 ins_encode %{
6928 Label Lskip;
6929 // Invert sense of branch from sense of CMOV
6930 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6931 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6932 __ bind(Lskip);
6933 %}
6934 ins_pipe(pipe_slow);
6935 %}
6936
6937 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6938 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6939 ins_cost(200);
6940 expand %{
6941 cmovF_regU(cop, cr, dst, src);
6942 %}
6943 %}
6944
6945 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6946 %{
6947 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6948
6949 ins_cost(200); // XXX
6950 format %{ "jn$cop skip\t# signed cmove double\n\t"
6951 "movsd $dst, $src\n"
6952 "skip:" %}
6953 ins_encode %{
6954 Label Lskip;
6955 // Invert sense of branch from sense of CMOV
6956 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6957 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6958 __ bind(Lskip);
6959 %}
6960 ins_pipe(pipe_slow);
6961 %}
6962
6963 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6964 %{
6965 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6966
6967 ins_cost(200); // XXX
6968 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6969 "movsd $dst, $src\n"
6970 "skip:" %}
6971 ins_encode %{
6972 Label Lskip;
6973 // Invert sense of branch from sense of CMOV
6974 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6975 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6976 __ bind(Lskip);
6977 %}
6978 ins_pipe(pipe_slow);
6979 %}
6980
6981 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6982 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6983 ins_cost(200);
6984 expand %{
6985 cmovD_regU(cop, cr, dst, src);
6986 %}
6987 %}
6988
6989 //----------Arithmetic Instructions--------------------------------------------
6990 //----------Addition Instructions----------------------------------------------
6991
6992 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6993 %{
6994 predicate(!UseAPX);
6995 match(Set dst (AddI dst src));
6996 effect(KILL cr);
6997 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6998 format %{ "addl $dst, $src\t# int" %}
6999 ins_encode %{
7000 __ addl($dst$$Register, $src$$Register);
7001 %}
7002 ins_pipe(ialu_reg_reg);
7003 %}
7004
7005 instruct addI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
7006 %{
7007 predicate(UseAPX);
7008 match(Set dst (AddI src1 src2));
7009 effect(KILL cr);
7010 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7011
7012 format %{ "eaddl $dst, $src1, $src2\t# int ndd" %}
7013 ins_encode %{
7014 __ eaddl($dst$$Register, $src1$$Register, $src2$$Register, false);
7015 %}
7016 ins_pipe(ialu_reg_reg);
7017 %}
7018
7019 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7020 %{
7021 predicate(!UseAPX);
7022 match(Set dst (AddI dst src));
7023 effect(KILL cr);
7024 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7025
7026 format %{ "addl $dst, $src\t# int" %}
7027 ins_encode %{
7028 __ addl($dst$$Register, $src$$constant);
7029 %}
7030 ins_pipe( ialu_reg );
7031 %}
7032
7033 instruct addI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
7034 %{
7035 predicate(UseAPX);
7036 match(Set dst (AddI src1 src2));
7037 effect(KILL cr);
7038 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7039
7040 format %{ "eaddl $dst, $src1, $src2\t# int ndd" %}
7041 ins_encode %{
7042 __ eaddl($dst$$Register, $src1$$Register, $src2$$constant, false);
7043 %}
7044 ins_pipe( ialu_reg );
7045 %}
7046
7047 instruct addI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
7048 %{
7049 predicate(UseAPX);
7050 match(Set dst (AddI (LoadI src1) src2));
7051 effect(KILL cr);
7052 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7053
7054 format %{ "eaddl $dst, $src1, $src2\t# int ndd" %}
7055 ins_encode %{
7056 __ eaddl($dst$$Register, $src1$$Address, $src2$$constant, false);
7057 %}
7058 ins_pipe( ialu_reg );
7059 %}
7060
7061 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7062 %{
7063 predicate(!UseAPX);
7064 match(Set dst (AddI dst (LoadI src)));
7065 effect(KILL cr);
7066 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7067
7068 ins_cost(150); // XXX
7069 format %{ "addl $dst, $src\t# int" %}
7070 ins_encode %{
7071 __ addl($dst$$Register, $src$$Address);
7072 %}
7073 ins_pipe(ialu_reg_mem);
7074 %}
7075
7076 instruct addI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr)
7077 %{
7078 predicate(UseAPX);
7079 match(Set dst (AddI (LoadI src1) src2));
7080 effect(KILL cr);
7081 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7082
7083 ins_cost(150);
7084 format %{ "eaddl $dst, $src1, $src2\t# int ndd" %}
7085 ins_encode %{
7086 __ eaddl($dst$$Register, $src1$$Address, $src2$$Register, false);
7087 %}
7088 ins_pipe(ialu_reg_mem);
7089 %}
7090
7091 instruct addI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
7092 %{
7093 predicate(UseAPX);
7094 match(Set dst (AddI src1 (LoadI src2)));
7095 effect(KILL cr);
7096 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7097
7098 ins_cost(150);
7099 format %{ "eaddl $dst, $src1, $src2\t# int ndd" %}
7100 ins_encode %{
7101 __ eaddl($dst$$Register, $src1$$Register, $src2$$Address, false);
7102 %}
7103 ins_pipe(ialu_reg_mem);
7104 %}
7105
7106 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7107 %{
7108 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7109 effect(KILL cr);
7110 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7111
7112 ins_cost(150); // XXX
7113 format %{ "addl $dst, $src\t# int" %}
7114 ins_encode %{
7115 __ addl($dst$$Address, $src$$Register);
7116 %}
7117 ins_pipe(ialu_mem_reg);
7118 %}
7119
7120 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7121 %{
7122 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7123 effect(KILL cr);
7124 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7125
7126
7127 ins_cost(125); // XXX
7128 format %{ "addl $dst, $src\t# int" %}
7129 ins_encode %{
7130 __ addl($dst$$Address, $src$$constant);
7131 %}
7132 ins_pipe(ialu_mem_imm);
7133 %}
7134
7135 instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
7136 %{
7137 predicate(!UseAPX && UseIncDec);
7138 match(Set dst (AddI dst src));
7139 effect(KILL cr);
7140
7141 format %{ "incl $dst\t# int" %}
7142 ins_encode %{
7143 __ incrementl($dst$$Register);
7144 %}
7145 ins_pipe(ialu_reg);
7146 %}
7147
7148 instruct incI_rReg_ndd(rRegI dst, rRegI src, immI_1 val, rFlagsReg cr)
7149 %{
7150 predicate(UseAPX && UseIncDec);
7151 match(Set dst (AddI src val));
7152 effect(KILL cr);
7153
7154 format %{ "eincl $dst, $src\t# int ndd" %}
7155 ins_encode %{
7156 __ eincl($dst$$Register, $src$$Register, false);
7157 %}
7158 ins_pipe(ialu_reg);
7159 %}
7160
7161 instruct incI_rReg_mem_ndd(rRegI dst, memory src, immI_1 val, rFlagsReg cr)
7162 %{
7163 predicate(UseAPX && UseIncDec);
7164 match(Set dst (AddI (LoadI src) val));
7165 effect(KILL cr);
7166
7167 format %{ "eincl $dst, $src\t# int ndd" %}
7168 ins_encode %{
7169 __ eincl($dst$$Register, $src$$Address, false);
7170 %}
7171 ins_pipe(ialu_reg);
7172 %}
7173
7174 instruct incI_mem(memory dst, immI_1 src, rFlagsReg cr)
7175 %{
7176 predicate(UseIncDec);
7177 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7178 effect(KILL cr);
7179
7180 ins_cost(125); // XXX
7181 format %{ "incl $dst\t# int" %}
7182 ins_encode %{
7183 __ incrementl($dst$$Address);
7184 %}
7185 ins_pipe(ialu_mem_imm);
7186 %}
7187
7188 // XXX why does that use AddI
7189 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7190 %{
7191 predicate(!UseAPX && UseIncDec);
7192 match(Set dst (AddI dst src));
7193 effect(KILL cr);
7194
7195 format %{ "decl $dst\t# int" %}
7196 ins_encode %{
7197 __ decrementl($dst$$Register);
7198 %}
7199 ins_pipe(ialu_reg);
7200 %}
7201
7202 instruct decI_rReg_ndd(rRegI dst, rRegI src, immI_M1 val, rFlagsReg cr)
7203 %{
7204 predicate(UseAPX && UseIncDec);
7205 match(Set dst (AddI src val));
7206 effect(KILL cr);
7207
7208 format %{ "edecl $dst, $src\t# int ndd" %}
7209 ins_encode %{
7210 __ edecl($dst$$Register, $src$$Register, false);
7211 %}
7212 ins_pipe(ialu_reg);
7213 %}
7214
7215 instruct decI_rReg_mem_ndd(rRegI dst, memory src, immI_M1 val, rFlagsReg cr)
7216 %{
7217 predicate(UseAPX && UseIncDec);
7218 match(Set dst (AddI (LoadI src) val));
7219 effect(KILL cr);
7220
7221 format %{ "edecl $dst, $src\t# int ndd" %}
7222 ins_encode %{
7223 __ edecl($dst$$Register, $src$$Address, false);
7224 %}
7225 ins_pipe(ialu_reg);
7226 %}
7227
7228 // XXX why does that use AddI
7229 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7230 %{
7231 predicate(UseIncDec);
7232 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7233 effect(KILL cr);
7234
7235 ins_cost(125); // XXX
7236 format %{ "decl $dst\t# int" %}
7237 ins_encode %{
7238 __ decrementl($dst$$Address);
7239 %}
7240 ins_pipe(ialu_mem_imm);
7241 %}
7242
7243 instruct leaI_rReg_immI2_immI(rRegI dst, rRegI index, immI2 scale, immI disp)
7244 %{
7245 predicate(VM_Version::supports_fast_2op_lea());
7246 match(Set dst (AddI (LShiftI index scale) disp));
7247
7248 format %{ "leal $dst, [$index << $scale + $disp]\t# int" %}
7249 ins_encode %{
7250 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7251 __ leal($dst$$Register, Address(noreg, $index$$Register, scale, $disp$$constant));
7252 %}
7253 ins_pipe(ialu_reg_reg);
7254 %}
7255
7256 instruct leaI_rReg_rReg_immI(rRegI dst, rRegI base, rRegI index, immI disp)
7257 %{
7258 predicate(VM_Version::supports_fast_3op_lea());
7259 match(Set dst (AddI (AddI base index) disp));
7260
7261 format %{ "leal $dst, [$base + $index + $disp]\t# int" %}
7262 ins_encode %{
7263 __ leal($dst$$Register, Address($base$$Register, $index$$Register, Address::times_1, $disp$$constant));
7264 %}
7265 ins_pipe(ialu_reg_reg);
7266 %}
7267
7268 instruct leaI_rReg_rReg_immI2(rRegI dst, no_rbp_r13_RegI base, rRegI index, immI2 scale)
7269 %{
7270 predicate(VM_Version::supports_fast_2op_lea());
7271 match(Set dst (AddI base (LShiftI index scale)));
7272
7273 format %{ "leal $dst, [$base + $index << $scale]\t# int" %}
7274 ins_encode %{
7275 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7276 __ leal($dst$$Register, Address($base$$Register, $index$$Register, scale));
7277 %}
7278 ins_pipe(ialu_reg_reg);
7279 %}
7280
7281 instruct leaI_rReg_rReg_immI2_immI(rRegI dst, rRegI base, rRegI index, immI2 scale, immI disp)
7282 %{
7283 predicate(VM_Version::supports_fast_3op_lea());
7284 match(Set dst (AddI (AddI base (LShiftI index scale)) disp));
7285
7286 format %{ "leal $dst, [$base + $index << $scale + $disp]\t# int" %}
7287 ins_encode %{
7288 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7289 __ leal($dst$$Register, Address($base$$Register, $index$$Register, scale, $disp$$constant));
7290 %}
7291 ins_pipe(ialu_reg_reg);
7292 %}
7293
7294 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7295 %{
7296 predicate(!UseAPX);
7297 match(Set dst (AddL dst src));
7298 effect(KILL cr);
7299 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7300
7301 format %{ "addq $dst, $src\t# long" %}
7302 ins_encode %{
7303 __ addq($dst$$Register, $src$$Register);
7304 %}
7305 ins_pipe(ialu_reg_reg);
7306 %}
7307
7308 instruct addL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
7309 %{
7310 predicate(UseAPX);
7311 match(Set dst (AddL src1 src2));
7312 effect(KILL cr);
7313 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7314
7315 format %{ "eaddq $dst, $src1, $src2\t# long ndd" %}
7316 ins_encode %{
7317 __ eaddq($dst$$Register, $src1$$Register, $src2$$Register, false);
7318 %}
7319 ins_pipe(ialu_reg_reg);
7320 %}
7321
7322 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7323 %{
7324 predicate(!UseAPX);
7325 match(Set dst (AddL dst src));
7326 effect(KILL cr);
7327 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7328
7329 format %{ "addq $dst, $src\t# long" %}
7330 ins_encode %{
7331 __ addq($dst$$Register, $src$$constant);
7332 %}
7333 ins_pipe( ialu_reg );
7334 %}
7335
7336 instruct addL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
7337 %{
7338 predicate(UseAPX);
7339 match(Set dst (AddL src1 src2));
7340 effect(KILL cr);
7341 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7342
7343 format %{ "eaddq $dst, $src1, $src2\t# long ndd" %}
7344 ins_encode %{
7345 __ eaddq($dst$$Register, $src1$$Register, $src2$$constant, false);
7346 %}
7347 ins_pipe( ialu_reg );
7348 %}
7349
7350 instruct addL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
7351 %{
7352 predicate(UseAPX);
7353 match(Set dst (AddL (LoadL src1) src2));
7354 effect(KILL cr);
7355 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7356
7357 format %{ "eaddq $dst, $src1, $src2\t# long ndd" %}
7358 ins_encode %{
7359 __ eaddq($dst$$Register, $src1$$Address, $src2$$constant, false);
7360 %}
7361 ins_pipe( ialu_reg );
7362 %}
7363
7364 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7365 %{
7366 predicate(!UseAPX);
7367 match(Set dst (AddL dst (LoadL src)));
7368 effect(KILL cr);
7369 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7370
7371 ins_cost(150); // XXX
7372 format %{ "addq $dst, $src\t# long" %}
7373 ins_encode %{
7374 __ addq($dst$$Register, $src$$Address);
7375 %}
7376 ins_pipe(ialu_reg_mem);
7377 %}
7378
7379 instruct addL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
7380 %{
7381 predicate(UseAPX);
7382 match(Set dst (AddL src1 (LoadL src2)));
7383 effect(KILL cr);
7384 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7385
7386 ins_cost(150);
7387 format %{ "eaddq $dst, $src1, $src2\t# long ndd" %}
7388 ins_encode %{
7389 __ eaddq($dst$$Register, $src1$$Register, $src2$$Address, false);
7390 %}
7391 ins_pipe(ialu_reg_mem);
7392 %}
7393
7394 instruct addL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
7395 %{
7396 predicate(UseAPX);
7397 match(Set dst (AddL (LoadL src1) src2));
7398 effect(KILL cr);
7399 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7400
7401 ins_cost(150);
7402 format %{ "eaddq $dst, $src1, $src2\t# long ndd" %}
7403 ins_encode %{
7404 __ eaddq($dst$$Register, $src1$$Address, $src2$$Register, false);
7405 %}
7406 ins_pipe(ialu_reg_mem);
7407 %}
7408
7409 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7410 %{
7411 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7412 effect(KILL cr);
7413 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7414
7415 ins_cost(150); // XXX
7416 format %{ "addq $dst, $src\t# long" %}
7417 ins_encode %{
7418 __ addq($dst$$Address, $src$$Register);
7419 %}
7420 ins_pipe(ialu_mem_reg);
7421 %}
7422
7423 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7424 %{
7425 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7426 effect(KILL cr);
7427 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7428
7429 ins_cost(125); // XXX
7430 format %{ "addq $dst, $src\t# long" %}
7431 ins_encode %{
7432 __ addq($dst$$Address, $src$$constant);
7433 %}
7434 ins_pipe(ialu_mem_imm);
7435 %}
7436
7437 instruct incL_rReg(rRegL dst, immL1 src, rFlagsReg cr)
7438 %{
7439 predicate(!UseAPX && UseIncDec);
7440 match(Set dst (AddL dst src));
7441 effect(KILL cr);
7442
7443 format %{ "incq $dst\t# long" %}
7444 ins_encode %{
7445 __ incrementq($dst$$Register);
7446 %}
7447 ins_pipe(ialu_reg);
7448 %}
7449
7450 instruct incL_rReg_ndd(rRegL dst, rRegI src, immL1 val, rFlagsReg cr)
7451 %{
7452 predicate(UseAPX && UseIncDec);
7453 match(Set dst (AddL src val));
7454 effect(KILL cr);
7455
7456 format %{ "eincq $dst, $src\t# long ndd" %}
7457 ins_encode %{
7458 __ eincq($dst$$Register, $src$$Register, false);
7459 %}
7460 ins_pipe(ialu_reg);
7461 %}
7462
7463 instruct incL_rReg_mem_ndd(rRegL dst, memory src, immL1 val, rFlagsReg cr)
7464 %{
7465 predicate(UseAPX && UseIncDec);
7466 match(Set dst (AddL (LoadL src) val));
7467 effect(KILL cr);
7468
7469 format %{ "eincq $dst, $src\t# long ndd" %}
7470 ins_encode %{
7471 __ eincq($dst$$Register, $src$$Address, false);
7472 %}
7473 ins_pipe(ialu_reg);
7474 %}
7475
7476 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7477 %{
7478 predicate(UseIncDec);
7479 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7480 effect(KILL cr);
7481
7482 ins_cost(125); // XXX
7483 format %{ "incq $dst\t# long" %}
7484 ins_encode %{
7485 __ incrementq($dst$$Address);
7486 %}
7487 ins_pipe(ialu_mem_imm);
7488 %}
7489
7490 // XXX why does that use AddL
7491 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7492 %{
7493 predicate(!UseAPX && UseIncDec);
7494 match(Set dst (AddL dst src));
7495 effect(KILL cr);
7496
7497 format %{ "decq $dst\t# long" %}
7498 ins_encode %{
7499 __ decrementq($dst$$Register);
7500 %}
7501 ins_pipe(ialu_reg);
7502 %}
7503
7504 instruct decL_rReg_ndd(rRegL dst, rRegL src, immL_M1 val, rFlagsReg cr)
7505 %{
7506 predicate(UseAPX && UseIncDec);
7507 match(Set dst (AddL src val));
7508 effect(KILL cr);
7509
7510 format %{ "edecq $dst, $src\t# long ndd" %}
7511 ins_encode %{
7512 __ edecq($dst$$Register, $src$$Register, false);
7513 %}
7514 ins_pipe(ialu_reg);
7515 %}
7516
7517 instruct decL_rReg_mem_ndd(rRegL dst, memory src, immL_M1 val, rFlagsReg cr)
7518 %{
7519 predicate(UseAPX && UseIncDec);
7520 match(Set dst (AddL (LoadL src) val));
7521 effect(KILL cr);
7522
7523 format %{ "edecq $dst, $src\t# long ndd" %}
7524 ins_encode %{
7525 __ edecq($dst$$Register, $src$$Address, false);
7526 %}
7527 ins_pipe(ialu_reg);
7528 %}
7529
7530 // XXX why does that use AddL
7531 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7532 %{
7533 predicate(UseIncDec);
7534 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7535 effect(KILL cr);
7536
7537 ins_cost(125); // XXX
7538 format %{ "decq $dst\t# long" %}
7539 ins_encode %{
7540 __ decrementq($dst$$Address);
7541 %}
7542 ins_pipe(ialu_mem_imm);
7543 %}
7544
7545 instruct leaL_rReg_immI2_immL32(rRegL dst, rRegL index, immI2 scale, immL32 disp)
7546 %{
7547 predicate(VM_Version::supports_fast_2op_lea());
7548 match(Set dst (AddL (LShiftL index scale) disp));
7549
7550 format %{ "leaq $dst, [$index << $scale + $disp]\t# long" %}
7551 ins_encode %{
7552 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7553 __ leaq($dst$$Register, Address(noreg, $index$$Register, scale, $disp$$constant));
7554 %}
7555 ins_pipe(ialu_reg_reg);
7556 %}
7557
7558 instruct leaL_rReg_rReg_immL32(rRegL dst, rRegL base, rRegL index, immL32 disp)
7559 %{
7560 predicate(VM_Version::supports_fast_3op_lea());
7561 match(Set dst (AddL (AddL base index) disp));
7562
7563 format %{ "leaq $dst, [$base + $index + $disp]\t# long" %}
7564 ins_encode %{
7565 __ leaq($dst$$Register, Address($base$$Register, $index$$Register, Address::times_1, $disp$$constant));
7566 %}
7567 ins_pipe(ialu_reg_reg);
7568 %}
7569
7570 instruct leaL_rReg_rReg_immI2(rRegL dst, no_rbp_r13_RegL base, rRegL index, immI2 scale)
7571 %{
7572 predicate(VM_Version::supports_fast_2op_lea());
7573 match(Set dst (AddL base (LShiftL index scale)));
7574
7575 format %{ "leaq $dst, [$base + $index << $scale]\t# long" %}
7576 ins_encode %{
7577 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7578 __ leaq($dst$$Register, Address($base$$Register, $index$$Register, scale));
7579 %}
7580 ins_pipe(ialu_reg_reg);
7581 %}
7582
7583 instruct leaL_rReg_rReg_immI2_immL32(rRegL dst, rRegL base, rRegL index, immI2 scale, immL32 disp)
7584 %{
7585 predicate(VM_Version::supports_fast_3op_lea());
7586 match(Set dst (AddL (AddL base (LShiftL index scale)) disp));
7587
7588 format %{ "leaq $dst, [$base + $index << $scale + $disp]\t# long" %}
7589 ins_encode %{
7590 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7591 __ leaq($dst$$Register, Address($base$$Register, $index$$Register, scale, $disp$$constant));
7592 %}
7593 ins_pipe(ialu_reg_reg);
7594 %}
7595
7596 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7597 %{
7598 match(Set dst (AddP dst src));
7599 effect(KILL cr);
7600 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7601
7602 format %{ "addq $dst, $src\t# ptr" %}
7603 ins_encode %{
7604 __ addq($dst$$Register, $src$$Register);
7605 %}
7606 ins_pipe(ialu_reg_reg);
7607 %}
7608
7609 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7610 %{
7611 match(Set dst (AddP dst src));
7612 effect(KILL cr);
7613 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7614
7615 format %{ "addq $dst, $src\t# ptr" %}
7616 ins_encode %{
7617 __ addq($dst$$Register, $src$$constant);
7618 %}
7619 ins_pipe( ialu_reg );
7620 %}
7621
7622 // XXX addP mem ops ????
7623
7624 instruct checkCastPP(rRegP dst)
7625 %{
7626 match(Set dst (CheckCastPP dst));
7627
7628 size(0);
7629 format %{ "# checkcastPP of $dst" %}
7630 ins_encode(/* empty encoding */);
7631 ins_pipe(empty);
7632 %}
7633
7634 instruct castPP(rRegP dst)
7635 %{
7636 match(Set dst (CastPP dst));
7637
7638 size(0);
7639 format %{ "# castPP of $dst" %}
7640 ins_encode(/* empty encoding */);
7641 ins_pipe(empty);
7642 %}
7643
7644 instruct castII(rRegI dst)
7645 %{
7646 predicate(VerifyConstraintCasts == 0);
7647 match(Set dst (CastII dst));
7648
7649 size(0);
7650 format %{ "# castII of $dst" %}
7651 ins_encode(/* empty encoding */);
7652 ins_cost(0);
7653 ins_pipe(empty);
7654 %}
7655
7656 instruct castII_checked(rRegI dst, rFlagsReg cr)
7657 %{
7658 predicate(VerifyConstraintCasts > 0);
7659 match(Set dst (CastII dst));
7660
7661 effect(KILL cr);
7662 format %{ "# cast_checked_II $dst" %}
7663 ins_encode %{
7664 __ verify_int_in_range(_idx, bottom_type()->is_int(), $dst$$Register);
7665 %}
7666 ins_pipe(pipe_slow);
7667 %}
7668
7669 instruct castLL(rRegL dst)
7670 %{
7671 predicate(VerifyConstraintCasts == 0);
7672 match(Set dst (CastLL dst));
7673
7674 size(0);
7675 format %{ "# castLL of $dst" %}
7676 ins_encode(/* empty encoding */);
7677 ins_cost(0);
7678 ins_pipe(empty);
7679 %}
7680
7681 instruct castLL_checked_L32(rRegL dst, rFlagsReg cr)
7682 %{
7683 predicate(VerifyConstraintCasts > 0 && castLL_is_imm32(n));
7684 match(Set dst (CastLL dst));
7685
7686 effect(KILL cr);
7687 format %{ "# cast_checked_LL $dst" %}
7688 ins_encode %{
7689 __ verify_long_in_range(_idx, bottom_type()->is_long(), $dst$$Register, noreg);
7690 %}
7691 ins_pipe(pipe_slow);
7692 %}
7693
7694 instruct castLL_checked(rRegL dst, rRegL tmp, rFlagsReg cr)
7695 %{
7696 predicate(VerifyConstraintCasts > 0 && !castLL_is_imm32(n));
7697 match(Set dst (CastLL dst));
7698
7699 effect(KILL cr, TEMP tmp);
7700 format %{ "# cast_checked_LL $dst\tusing $tmp as TEMP" %}
7701 ins_encode %{
7702 __ verify_long_in_range(_idx, bottom_type()->is_long(), $dst$$Register, $tmp$$Register);
7703 %}
7704 ins_pipe(pipe_slow);
7705 %}
7706
7707 instruct castFF(regF dst)
7708 %{
7709 match(Set dst (CastFF dst));
7710
7711 size(0);
7712 format %{ "# castFF of $dst" %}
7713 ins_encode(/* empty encoding */);
7714 ins_cost(0);
7715 ins_pipe(empty);
7716 %}
7717
7718 instruct castHH(regF dst)
7719 %{
7720 match(Set dst (CastHH dst));
7721
7722 size(0);
7723 format %{ "# castHH of $dst" %}
7724 ins_encode(/* empty encoding */);
7725 ins_cost(0);
7726 ins_pipe(empty);
7727 %}
7728
7729 instruct castDD(regD dst)
7730 %{
7731 match(Set dst (CastDD dst));
7732
7733 size(0);
7734 format %{ "# castDD of $dst" %}
7735 ins_encode(/* empty encoding */);
7736 ins_cost(0);
7737 ins_pipe(empty);
7738 %}
7739
7740 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7741 instruct compareAndSwapP(rRegI res,
7742 memory mem_ptr,
7743 rax_RegP oldval, rRegP newval,
7744 rFlagsReg cr)
7745 %{
7746 predicate(n->as_LoadStore()->barrier_data() == 0);
7747 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7748 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7749 effect(KILL cr, KILL oldval);
7750
7751 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7752 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7753 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7754 ins_encode %{
7755 __ lock();
7756 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7757 __ setcc(Assembler::equal, $res$$Register);
7758 %}
7759 ins_pipe( pipe_cmpxchg );
7760 %}
7761
7762 instruct compareAndSwapL(rRegI res,
7763 memory mem_ptr,
7764 rax_RegL oldval, rRegL newval,
7765 rFlagsReg cr)
7766 %{
7767 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7768 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7769 effect(KILL cr, KILL oldval);
7770
7771 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7772 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7773 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7774 ins_encode %{
7775 __ lock();
7776 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7777 __ setcc(Assembler::equal, $res$$Register);
7778 %}
7779 ins_pipe( pipe_cmpxchg );
7780 %}
7781
7782 instruct compareAndSwapI(rRegI res,
7783 memory mem_ptr,
7784 rax_RegI oldval, rRegI newval,
7785 rFlagsReg cr)
7786 %{
7787 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7788 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7789 effect(KILL cr, KILL oldval);
7790
7791 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7792 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7793 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7794 ins_encode %{
7795 __ lock();
7796 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7797 __ setcc(Assembler::equal, $res$$Register);
7798 %}
7799 ins_pipe( pipe_cmpxchg );
7800 %}
7801
7802 instruct compareAndSwapB(rRegI res,
7803 memory mem_ptr,
7804 rax_RegI oldval, rRegI newval,
7805 rFlagsReg cr)
7806 %{
7807 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7808 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7809 effect(KILL cr, KILL oldval);
7810
7811 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7812 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7813 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7814 ins_encode %{
7815 __ lock();
7816 __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
7817 __ setcc(Assembler::equal, $res$$Register);
7818 %}
7819 ins_pipe( pipe_cmpxchg );
7820 %}
7821
7822 instruct compareAndSwapS(rRegI res,
7823 memory mem_ptr,
7824 rax_RegI oldval, rRegI newval,
7825 rFlagsReg cr)
7826 %{
7827 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7828 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7829 effect(KILL cr, KILL oldval);
7830
7831 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7832 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7833 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7834 ins_encode %{
7835 __ lock();
7836 __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
7837 __ setcc(Assembler::equal, $res$$Register);
7838 %}
7839 ins_pipe( pipe_cmpxchg );
7840 %}
7841
7842 instruct compareAndSwapN(rRegI res,
7843 memory mem_ptr,
7844 rax_RegN oldval, rRegN newval,
7845 rFlagsReg cr) %{
7846 predicate(n->as_LoadStore()->barrier_data() == 0);
7847 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7848 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7849 effect(KILL cr, KILL oldval);
7850
7851 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7852 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7853 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7854 ins_encode %{
7855 __ lock();
7856 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7857 __ setcc(Assembler::equal, $res$$Register);
7858 %}
7859 ins_pipe( pipe_cmpxchg );
7860 %}
7861
7862 instruct compareAndExchangeB(
7863 memory mem_ptr,
7864 rax_RegI oldval, rRegI newval,
7865 rFlagsReg cr)
7866 %{
7867 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7868 effect(KILL cr);
7869
7870 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7871 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7872 ins_encode %{
7873 __ lock();
7874 __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
7875 %}
7876 ins_pipe( pipe_cmpxchg );
7877 %}
7878
7879 instruct compareAndExchangeS(
7880 memory mem_ptr,
7881 rax_RegI oldval, rRegI newval,
7882 rFlagsReg cr)
7883 %{
7884 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7885 effect(KILL cr);
7886
7887 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7888 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7889 ins_encode %{
7890 __ lock();
7891 __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
7892 %}
7893 ins_pipe( pipe_cmpxchg );
7894 %}
7895
7896 instruct compareAndExchangeI(
7897 memory mem_ptr,
7898 rax_RegI oldval, rRegI newval,
7899 rFlagsReg cr)
7900 %{
7901 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7902 effect(KILL cr);
7903
7904 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7905 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7906 ins_encode %{
7907 __ lock();
7908 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7909 %}
7910 ins_pipe( pipe_cmpxchg );
7911 %}
7912
7913 instruct compareAndExchangeL(
7914 memory mem_ptr,
7915 rax_RegL oldval, rRegL newval,
7916 rFlagsReg cr)
7917 %{
7918 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7919 effect(KILL cr);
7920
7921 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7922 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7923 ins_encode %{
7924 __ lock();
7925 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7926 %}
7927 ins_pipe( pipe_cmpxchg );
7928 %}
7929
7930 instruct compareAndExchangeN(
7931 memory mem_ptr,
7932 rax_RegN oldval, rRegN newval,
7933 rFlagsReg cr) %{
7934 predicate(n->as_LoadStore()->barrier_data() == 0);
7935 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7936 effect(KILL cr);
7937
7938 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7939 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7940 ins_encode %{
7941 __ lock();
7942 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7943 %}
7944 ins_pipe( pipe_cmpxchg );
7945 %}
7946
7947 instruct compareAndExchangeP(
7948 memory mem_ptr,
7949 rax_RegP oldval, rRegP newval,
7950 rFlagsReg cr)
7951 %{
7952 predicate(n->as_LoadStore()->barrier_data() == 0);
7953 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7954 effect(KILL cr);
7955
7956 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7957 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7958 ins_encode %{
7959 __ lock();
7960 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7961 %}
7962 ins_pipe( pipe_cmpxchg );
7963 %}
7964
7965 instruct xaddB_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
7966 predicate(n->as_LoadStore()->result_not_used());
7967 match(Set dummy (GetAndAddB mem add));
7968 effect(KILL cr);
7969 format %{ "addb_lock $mem, $add" %}
7970 ins_encode %{
7971 __ lock();
7972 __ addb($mem$$Address, $add$$Register);
7973 %}
7974 ins_pipe(pipe_cmpxchg);
7975 %}
7976
7977 instruct xaddB_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7978 predicate(n->as_LoadStore()->result_not_used());
7979 match(Set dummy (GetAndAddB mem add));
7980 effect(KILL cr);
7981 format %{ "addb_lock $mem, $add" %}
7982 ins_encode %{
7983 __ lock();
7984 __ addb($mem$$Address, $add$$constant);
7985 %}
7986 ins_pipe(pipe_cmpxchg);
7987 %}
7988
7989 instruct xaddB(memory mem, rRegI newval, rFlagsReg cr) %{
7990 predicate(!n->as_LoadStore()->result_not_used());
7991 match(Set newval (GetAndAddB mem newval));
7992 effect(KILL cr);
7993 format %{ "xaddb_lock $mem, $newval" %}
7994 ins_encode %{
7995 __ lock();
7996 __ xaddb($mem$$Address, $newval$$Register);
7997 %}
7998 ins_pipe(pipe_cmpxchg);
7999 %}
8000
8001 instruct xaddS_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
8002 predicate(n->as_LoadStore()->result_not_used());
8003 match(Set dummy (GetAndAddS mem add));
8004 effect(KILL cr);
8005 format %{ "addw_lock $mem, $add" %}
8006 ins_encode %{
8007 __ lock();
8008 __ addw($mem$$Address, $add$$Register);
8009 %}
8010 ins_pipe(pipe_cmpxchg);
8011 %}
8012
8013 instruct xaddS_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8014 predicate(UseStoreImmI16 && n->as_LoadStore()->result_not_used());
8015 match(Set dummy (GetAndAddS mem add));
8016 effect(KILL cr);
8017 format %{ "addw_lock $mem, $add" %}
8018 ins_encode %{
8019 __ lock();
8020 __ addw($mem$$Address, $add$$constant);
8021 %}
8022 ins_pipe(pipe_cmpxchg);
8023 %}
8024
8025 instruct xaddS(memory mem, rRegI newval, rFlagsReg cr) %{
8026 predicate(!n->as_LoadStore()->result_not_used());
8027 match(Set newval (GetAndAddS mem newval));
8028 effect(KILL cr);
8029 format %{ "xaddw_lock $mem, $newval" %}
8030 ins_encode %{
8031 __ lock();
8032 __ xaddw($mem$$Address, $newval$$Register);
8033 %}
8034 ins_pipe(pipe_cmpxchg);
8035 %}
8036
8037 instruct xaddI_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
8038 predicate(n->as_LoadStore()->result_not_used());
8039 match(Set dummy (GetAndAddI mem add));
8040 effect(KILL cr);
8041 format %{ "addl_lock $mem, $add" %}
8042 ins_encode %{
8043 __ lock();
8044 __ addl($mem$$Address, $add$$Register);
8045 %}
8046 ins_pipe(pipe_cmpxchg);
8047 %}
8048
8049 instruct xaddI_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8050 predicate(n->as_LoadStore()->result_not_used());
8051 match(Set dummy (GetAndAddI mem add));
8052 effect(KILL cr);
8053 format %{ "addl_lock $mem, $add" %}
8054 ins_encode %{
8055 __ lock();
8056 __ addl($mem$$Address, $add$$constant);
8057 %}
8058 ins_pipe(pipe_cmpxchg);
8059 %}
8060
8061 instruct xaddI(memory mem, rRegI newval, rFlagsReg cr) %{
8062 predicate(!n->as_LoadStore()->result_not_used());
8063 match(Set newval (GetAndAddI mem newval));
8064 effect(KILL cr);
8065 format %{ "xaddl_lock $mem, $newval" %}
8066 ins_encode %{
8067 __ lock();
8068 __ xaddl($mem$$Address, $newval$$Register);
8069 %}
8070 ins_pipe(pipe_cmpxchg);
8071 %}
8072
8073 instruct xaddL_reg_no_res(memory mem, Universe dummy, rRegL add, rFlagsReg cr) %{
8074 predicate(n->as_LoadStore()->result_not_used());
8075 match(Set dummy (GetAndAddL mem add));
8076 effect(KILL cr);
8077 format %{ "addq_lock $mem, $add" %}
8078 ins_encode %{
8079 __ lock();
8080 __ addq($mem$$Address, $add$$Register);
8081 %}
8082 ins_pipe(pipe_cmpxchg);
8083 %}
8084
8085 instruct xaddL_imm_no_res(memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
8086 predicate(n->as_LoadStore()->result_not_used());
8087 match(Set dummy (GetAndAddL mem add));
8088 effect(KILL cr);
8089 format %{ "addq_lock $mem, $add" %}
8090 ins_encode %{
8091 __ lock();
8092 __ addq($mem$$Address, $add$$constant);
8093 %}
8094 ins_pipe(pipe_cmpxchg);
8095 %}
8096
8097 instruct xaddL(memory mem, rRegL newval, rFlagsReg cr) %{
8098 predicate(!n->as_LoadStore()->result_not_used());
8099 match(Set newval (GetAndAddL mem newval));
8100 effect(KILL cr);
8101 format %{ "xaddq_lock $mem, $newval" %}
8102 ins_encode %{
8103 __ lock();
8104 __ xaddq($mem$$Address, $newval$$Register);
8105 %}
8106 ins_pipe(pipe_cmpxchg);
8107 %}
8108
8109 instruct xchgB( memory mem, rRegI newval) %{
8110 match(Set newval (GetAndSetB mem newval));
8111 format %{ "XCHGB $newval,[$mem]" %}
8112 ins_encode %{
8113 __ xchgb($newval$$Register, $mem$$Address);
8114 %}
8115 ins_pipe( pipe_cmpxchg );
8116 %}
8117
8118 instruct xchgS( memory mem, rRegI newval) %{
8119 match(Set newval (GetAndSetS mem newval));
8120 format %{ "XCHGW $newval,[$mem]" %}
8121 ins_encode %{
8122 __ xchgw($newval$$Register, $mem$$Address);
8123 %}
8124 ins_pipe( pipe_cmpxchg );
8125 %}
8126
8127 instruct xchgI( memory mem, rRegI newval) %{
8128 match(Set newval (GetAndSetI mem newval));
8129 format %{ "XCHGL $newval,[$mem]" %}
8130 ins_encode %{
8131 __ xchgl($newval$$Register, $mem$$Address);
8132 %}
8133 ins_pipe( pipe_cmpxchg );
8134 %}
8135
8136 instruct xchgL( memory mem, rRegL newval) %{
8137 match(Set newval (GetAndSetL mem newval));
8138 format %{ "XCHGL $newval,[$mem]" %}
8139 ins_encode %{
8140 __ xchgq($newval$$Register, $mem$$Address);
8141 %}
8142 ins_pipe( pipe_cmpxchg );
8143 %}
8144
8145 instruct xchgP( memory mem, rRegP newval) %{
8146 match(Set newval (GetAndSetP mem newval));
8147 predicate(n->as_LoadStore()->barrier_data() == 0);
8148 format %{ "XCHGQ $newval,[$mem]" %}
8149 ins_encode %{
8150 __ xchgq($newval$$Register, $mem$$Address);
8151 %}
8152 ins_pipe( pipe_cmpxchg );
8153 %}
8154
8155 instruct xchgN( memory mem, rRegN newval) %{
8156 predicate(n->as_LoadStore()->barrier_data() == 0);
8157 match(Set newval (GetAndSetN mem newval));
8158 format %{ "XCHGL $newval,$mem]" %}
8159 ins_encode %{
8160 __ xchgl($newval$$Register, $mem$$Address);
8161 %}
8162 ins_pipe( pipe_cmpxchg );
8163 %}
8164
8165 //----------Abs Instructions-------------------------------------------
8166
8167 // Integer Absolute Instructions
8168 instruct absI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8169 %{
8170 match(Set dst (AbsI src));
8171 effect(TEMP dst, KILL cr);
8172 format %{ "xorl $dst, $dst\t# abs int\n\t"
8173 "subl $dst, $src\n\t"
8174 "cmovll $dst, $src" %}
8175 ins_encode %{
8176 __ xorl($dst$$Register, $dst$$Register);
8177 __ subl($dst$$Register, $src$$Register);
8178 __ cmovl(Assembler::less, $dst$$Register, $src$$Register);
8179 %}
8180
8181 ins_pipe(ialu_reg_reg);
8182 %}
8183
8184 // Long Absolute Instructions
8185 instruct absL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8186 %{
8187 match(Set dst (AbsL src));
8188 effect(TEMP dst, KILL cr);
8189 format %{ "xorl $dst, $dst\t# abs long\n\t"
8190 "subq $dst, $src\n\t"
8191 "cmovlq $dst, $src" %}
8192 ins_encode %{
8193 __ xorl($dst$$Register, $dst$$Register);
8194 __ subq($dst$$Register, $src$$Register);
8195 __ cmovq(Assembler::less, $dst$$Register, $src$$Register);
8196 %}
8197
8198 ins_pipe(ialu_reg_reg);
8199 %}
8200
8201 //----------Subtraction Instructions-------------------------------------------
8202
8203 // Integer Subtraction Instructions
8204 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8205 %{
8206 predicate(!UseAPX);
8207 match(Set dst (SubI dst src));
8208 effect(KILL cr);
8209 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8210
8211 format %{ "subl $dst, $src\t# int" %}
8212 ins_encode %{
8213 __ subl($dst$$Register, $src$$Register);
8214 %}
8215 ins_pipe(ialu_reg_reg);
8216 %}
8217
8218 instruct subI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
8219 %{
8220 predicate(UseAPX);
8221 match(Set dst (SubI src1 src2));
8222 effect(KILL cr);
8223 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8224
8225 format %{ "esubl $dst, $src1, $src2\t# int ndd" %}
8226 ins_encode %{
8227 __ esubl($dst$$Register, $src1$$Register, $src2$$Register, false);
8228 %}
8229 ins_pipe(ialu_reg_reg);
8230 %}
8231
8232 instruct subI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
8233 %{
8234 predicate(UseAPX);
8235 match(Set dst (SubI src1 src2));
8236 effect(KILL cr);
8237 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8238
8239 format %{ "esubl $dst, $src1, $src2\t# int ndd" %}
8240 ins_encode %{
8241 __ esubl($dst$$Register, $src1$$Register, $src2$$constant, false);
8242 %}
8243 ins_pipe(ialu_reg_reg);
8244 %}
8245
8246 instruct subI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
8247 %{
8248 predicate(UseAPX);
8249 match(Set dst (SubI (LoadI src1) src2));
8250 effect(KILL cr);
8251 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8252
8253 format %{ "esubl $dst, $src1, $src2\t# int ndd" %}
8254 ins_encode %{
8255 __ esubl($dst$$Register, $src1$$Address, $src2$$constant, false);
8256 %}
8257 ins_pipe(ialu_reg_reg);
8258 %}
8259
8260 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8261 %{
8262 predicate(!UseAPX);
8263 match(Set dst (SubI dst (LoadI src)));
8264 effect(KILL cr);
8265 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8266
8267 ins_cost(150);
8268 format %{ "subl $dst, $src\t# int" %}
8269 ins_encode %{
8270 __ subl($dst$$Register, $src$$Address);
8271 %}
8272 ins_pipe(ialu_reg_mem);
8273 %}
8274
8275 instruct subI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
8276 %{
8277 predicate(UseAPX);
8278 match(Set dst (SubI src1 (LoadI src2)));
8279 effect(KILL cr);
8280 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8281
8282 ins_cost(150);
8283 format %{ "esubl $dst, $src1, $src2\t# int ndd" %}
8284 ins_encode %{
8285 __ esubl($dst$$Register, $src1$$Register, $src2$$Address, false);
8286 %}
8287 ins_pipe(ialu_reg_mem);
8288 %}
8289
8290 instruct subI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr)
8291 %{
8292 predicate(UseAPX);
8293 match(Set dst (SubI (LoadI src1) src2));
8294 effect(KILL cr);
8295 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8296
8297 ins_cost(150);
8298 format %{ "esubl $dst, $src1, $src2\t# int ndd" %}
8299 ins_encode %{
8300 __ esubl($dst$$Register, $src1$$Address, $src2$$Register, false);
8301 %}
8302 ins_pipe(ialu_reg_mem);
8303 %}
8304
8305 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8306 %{
8307 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8308 effect(KILL cr);
8309 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8310
8311 ins_cost(150);
8312 format %{ "subl $dst, $src\t# int" %}
8313 ins_encode %{
8314 __ subl($dst$$Address, $src$$Register);
8315 %}
8316 ins_pipe(ialu_mem_reg);
8317 %}
8318
8319 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8320 %{
8321 predicate(!UseAPX);
8322 match(Set dst (SubL dst src));
8323 effect(KILL cr);
8324 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8325
8326 format %{ "subq $dst, $src\t# long" %}
8327 ins_encode %{
8328 __ subq($dst$$Register, $src$$Register);
8329 %}
8330 ins_pipe(ialu_reg_reg);
8331 %}
8332
8333 instruct subL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
8334 %{
8335 predicate(UseAPX);
8336 match(Set dst (SubL src1 src2));
8337 effect(KILL cr);
8338 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8339
8340 format %{ "esubq $dst, $src1, $src2\t# long ndd" %}
8341 ins_encode %{
8342 __ esubq($dst$$Register, $src1$$Register, $src2$$Register, false);
8343 %}
8344 ins_pipe(ialu_reg_reg);
8345 %}
8346
8347 instruct subL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
8348 %{
8349 predicate(UseAPX);
8350 match(Set dst (SubL src1 src2));
8351 effect(KILL cr);
8352 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8353
8354 format %{ "esubq $dst, $src1, $src2\t# long ndd" %}
8355 ins_encode %{
8356 __ esubq($dst$$Register, $src1$$Register, $src2$$constant, false);
8357 %}
8358 ins_pipe(ialu_reg_reg);
8359 %}
8360
8361 instruct subL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
8362 %{
8363 predicate(UseAPX);
8364 match(Set dst (SubL (LoadL src1) src2));
8365 effect(KILL cr);
8366 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8367
8368 format %{ "esubq $dst, $src1, $src2\t# long ndd" %}
8369 ins_encode %{
8370 __ esubq($dst$$Register, $src1$$Address, $src2$$constant, false);
8371 %}
8372 ins_pipe(ialu_reg_reg);
8373 %}
8374
8375 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8376 %{
8377 predicate(!UseAPX);
8378 match(Set dst (SubL dst (LoadL src)));
8379 effect(KILL cr);
8380 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8381
8382 ins_cost(150);
8383 format %{ "subq $dst, $src\t# long" %}
8384 ins_encode %{
8385 __ subq($dst$$Register, $src$$Address);
8386 %}
8387 ins_pipe(ialu_reg_mem);
8388 %}
8389
8390 instruct subL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
8391 %{
8392 predicate(UseAPX);
8393 match(Set dst (SubL src1 (LoadL src2)));
8394 effect(KILL cr);
8395 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8396
8397 ins_cost(150);
8398 format %{ "esubq $dst, $src1, $src2\t# long ndd" %}
8399 ins_encode %{
8400 __ esubq($dst$$Register, $src1$$Register, $src2$$Address, false);
8401 %}
8402 ins_pipe(ialu_reg_mem);
8403 %}
8404
8405 instruct subL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
8406 %{
8407 predicate(UseAPX);
8408 match(Set dst (SubL (LoadL src1) src2));
8409 effect(KILL cr);
8410 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8411
8412 ins_cost(150);
8413 format %{ "esubq $dst, $src1, $src2\t# long ndd" %}
8414 ins_encode %{
8415 __ esubq($dst$$Register, $src1$$Address, $src2$$Register, false);
8416 %}
8417 ins_pipe(ialu_reg_mem);
8418 %}
8419
8420 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8421 %{
8422 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8423 effect(KILL cr);
8424 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8425
8426 ins_cost(150);
8427 format %{ "subq $dst, $src\t# long" %}
8428 ins_encode %{
8429 __ subq($dst$$Address, $src$$Register);
8430 %}
8431 ins_pipe(ialu_mem_reg);
8432 %}
8433
8434 // Subtract from a pointer
8435 // XXX hmpf???
8436 instruct subP_rReg(rRegP dst, rRegI src, immI_0 zero, rFlagsReg cr)
8437 %{
8438 match(Set dst (AddP dst (SubI zero src)));
8439 effect(KILL cr);
8440
8441 format %{ "subq $dst, $src\t# ptr - int" %}
8442 ins_encode %{
8443 __ subq($dst$$Register, $src$$Register);
8444 %}
8445 ins_pipe(ialu_reg_reg);
8446 %}
8447
8448 instruct negI_rReg(rRegI dst, immI_0 zero, rFlagsReg cr)
8449 %{
8450 predicate(!UseAPX);
8451 match(Set dst (SubI zero dst));
8452 effect(KILL cr);
8453 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8454
8455 format %{ "negl $dst\t# int" %}
8456 ins_encode %{
8457 __ negl($dst$$Register);
8458 %}
8459 ins_pipe(ialu_reg);
8460 %}
8461
8462 instruct negI_rReg_ndd(rRegI dst, rRegI src, immI_0 zero, rFlagsReg cr)
8463 %{
8464 predicate(UseAPX);
8465 match(Set dst (SubI zero src));
8466 effect(KILL cr);
8467 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8468
8469 format %{ "enegl $dst, $src\t# int ndd" %}
8470 ins_encode %{
8471 __ enegl($dst$$Register, $src$$Register, false);
8472 %}
8473 ins_pipe(ialu_reg);
8474 %}
8475
8476 instruct negI_rReg_2(rRegI dst, rFlagsReg cr)
8477 %{
8478 predicate(!UseAPX);
8479 match(Set dst (NegI dst));
8480 effect(KILL cr);
8481 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8482
8483 format %{ "negl $dst\t# int" %}
8484 ins_encode %{
8485 __ negl($dst$$Register);
8486 %}
8487 ins_pipe(ialu_reg);
8488 %}
8489
8490 instruct negI_rReg_2_ndd(rRegI dst, rRegI src, rFlagsReg cr)
8491 %{
8492 predicate(UseAPX);
8493 match(Set dst (NegI src));
8494 effect(KILL cr);
8495 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8496
8497 format %{ "enegl $dst, $src\t# int ndd" %}
8498 ins_encode %{
8499 __ enegl($dst$$Register, $src$$Register, false);
8500 %}
8501 ins_pipe(ialu_reg);
8502 %}
8503
8504 instruct negI_mem(memory dst, immI_0 zero, rFlagsReg cr)
8505 %{
8506 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8507 effect(KILL cr);
8508 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8509
8510 format %{ "negl $dst\t# int" %}
8511 ins_encode %{
8512 __ negl($dst$$Address);
8513 %}
8514 ins_pipe(ialu_reg);
8515 %}
8516
8517 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8518 %{
8519 predicate(!UseAPX);
8520 match(Set dst (SubL zero dst));
8521 effect(KILL cr);
8522 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8523
8524 format %{ "negq $dst\t# long" %}
8525 ins_encode %{
8526 __ negq($dst$$Register);
8527 %}
8528 ins_pipe(ialu_reg);
8529 %}
8530
8531 instruct negL_rReg_ndd(rRegL dst, rRegL src, immL0 zero, rFlagsReg cr)
8532 %{
8533 predicate(UseAPX);
8534 match(Set dst (SubL zero src));
8535 effect(KILL cr);
8536 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8537
8538 format %{ "enegq $dst, $src\t# long ndd" %}
8539 ins_encode %{
8540 __ enegq($dst$$Register, $src$$Register, false);
8541 %}
8542 ins_pipe(ialu_reg);
8543 %}
8544
8545 instruct negL_rReg_2(rRegL dst, rFlagsReg cr)
8546 %{
8547 predicate(!UseAPX);
8548 match(Set dst (NegL dst));
8549 effect(KILL cr);
8550 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8551
8552 format %{ "negq $dst\t# int" %}
8553 ins_encode %{
8554 __ negq($dst$$Register);
8555 %}
8556 ins_pipe(ialu_reg);
8557 %}
8558
8559 instruct negL_rReg_2_ndd(rRegL dst, rRegL src, rFlagsReg cr)
8560 %{
8561 predicate(UseAPX);
8562 match(Set dst (NegL src));
8563 effect(KILL cr);
8564 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8565
8566 format %{ "enegq $dst, $src\t# long ndd" %}
8567 ins_encode %{
8568 __ enegq($dst$$Register, $src$$Register, false);
8569 %}
8570 ins_pipe(ialu_reg);
8571 %}
8572
8573 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8574 %{
8575 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8576 effect(KILL cr);
8577 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8578
8579 format %{ "negq $dst\t# long" %}
8580 ins_encode %{
8581 __ negq($dst$$Address);
8582 %}
8583 ins_pipe(ialu_reg);
8584 %}
8585
8586 //----------Multiplication/Division Instructions-------------------------------
8587 // Integer Multiplication Instructions
8588 // Multiply Register
8589
8590 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8591 %{
8592 predicate(!UseAPX);
8593 match(Set dst (MulI dst src));
8594 effect(KILL cr);
8595
8596 ins_cost(300);
8597 format %{ "imull $dst, $src\t# int" %}
8598 ins_encode %{
8599 __ imull($dst$$Register, $src$$Register);
8600 %}
8601 ins_pipe(ialu_reg_reg_alu0);
8602 %}
8603
8604 instruct mulI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
8605 %{
8606 predicate(UseAPX);
8607 match(Set dst (MulI src1 src2));
8608 effect(KILL cr);
8609
8610 ins_cost(300);
8611 format %{ "eimull $dst, $src1, $src2\t# int ndd" %}
8612 ins_encode %{
8613 __ eimull($dst$$Register, $src1$$Register, $src2$$Register, false);
8614 %}
8615 ins_pipe(ialu_reg_reg_alu0);
8616 %}
8617
8618 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8619 %{
8620 predicate(!UseAPX);
8621 match(Set dst (MulI src imm));
8622 effect(KILL cr);
8623
8624 ins_cost(300);
8625 format %{ "imull $dst, $src, $imm\t# int" %}
8626 ins_encode %{
8627 __ imull($dst$$Register, $src$$Register, $imm$$constant);
8628 %}
8629 ins_pipe(ialu_reg_reg_alu0);
8630 %}
8631
8632 instruct mulI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
8633 %{
8634 predicate(UseAPX);
8635 match(Set dst (MulI src1 src2));
8636 effect(KILL cr);
8637
8638 ins_cost(300);
8639 format %{ "eimull $dst, $src1, $src2\t# int ndd" %}
8640 ins_encode %{
8641 __ eimull($dst$$Register, $src1$$Register, $src2$$constant, false);
8642 %}
8643 ins_pipe(ialu_reg_reg_alu0);
8644 %}
8645
8646 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8647 %{
8648 predicate(!UseAPX);
8649 match(Set dst (MulI dst (LoadI src)));
8650 effect(KILL cr);
8651
8652 ins_cost(350);
8653 format %{ "imull $dst, $src\t# int" %}
8654 ins_encode %{
8655 __ imull($dst$$Register, $src$$Address);
8656 %}
8657 ins_pipe(ialu_reg_mem_alu0);
8658 %}
8659
8660 instruct mulI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
8661 %{
8662 predicate(UseAPX);
8663 match(Set dst (MulI src1 (LoadI src2)));
8664 effect(KILL cr);
8665
8666 ins_cost(350);
8667 format %{ "eimull $dst, $src1, $src2\t# int ndd" %}
8668 ins_encode %{
8669 __ eimull($dst$$Register, $src1$$Register, $src2$$Address, false);
8670 %}
8671 ins_pipe(ialu_reg_mem_alu0);
8672 %}
8673
8674 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8675 %{
8676 predicate(!UseAPX);
8677 match(Set dst (MulI (LoadI src) imm));
8678 effect(KILL cr);
8679
8680 ins_cost(300);
8681 format %{ "imull $dst, $src, $imm\t# int" %}
8682 ins_encode %{
8683 __ imull($dst$$Register, $src$$Address, $imm$$constant);
8684 %}
8685 ins_pipe(ialu_reg_mem_alu0);
8686 %}
8687
8688 instruct mulI_rReg_mem_imm(rRegI dst, memory src1, immI src2, rFlagsReg cr)
8689 %{
8690 predicate(UseAPX);
8691 match(Set dst (MulI (LoadI src1) src2));
8692 effect(KILL cr);
8693
8694 ins_cost(300);
8695 format %{ "eimull $dst, $src1, $src2\t# int ndd" %}
8696 ins_encode %{
8697 __ eimull($dst$$Register, $src1$$Address, $src2$$constant, false);
8698 %}
8699 ins_pipe(ialu_reg_mem_alu0);
8700 %}
8701
8702 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
8703 %{
8704 match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
8705 effect(KILL cr, KILL src2);
8706
8707 expand %{ mulI_rReg(dst, src1, cr);
8708 mulI_rReg(src2, src3, cr);
8709 addI_rReg(dst, src2, cr); %}
8710 %}
8711
8712 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8713 %{
8714 predicate(!UseAPX);
8715 match(Set dst (MulL dst src));
8716 effect(KILL cr);
8717
8718 ins_cost(300);
8719 format %{ "imulq $dst, $src\t# long" %}
8720 ins_encode %{
8721 __ imulq($dst$$Register, $src$$Register);
8722 %}
8723 ins_pipe(ialu_reg_reg_alu0);
8724 %}
8725
8726 instruct mulL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
8727 %{
8728 predicate(UseAPX);
8729 match(Set dst (MulL src1 src2));
8730 effect(KILL cr);
8731
8732 ins_cost(300);
8733 format %{ "eimulq $dst, $src1, $src2\t# long ndd" %}
8734 ins_encode %{
8735 __ eimulq($dst$$Register, $src1$$Register, $src2$$Register, false);
8736 %}
8737 ins_pipe(ialu_reg_reg_alu0);
8738 %}
8739
8740 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8741 %{
8742 predicate(!UseAPX);
8743 match(Set dst (MulL src imm));
8744 effect(KILL cr);
8745
8746 ins_cost(300);
8747 format %{ "imulq $dst, $src, $imm\t# long" %}
8748 ins_encode %{
8749 __ imulq($dst$$Register, $src$$Register, $imm$$constant);
8750 %}
8751 ins_pipe(ialu_reg_reg_alu0);
8752 %}
8753
8754 instruct mulL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
8755 %{
8756 predicate(UseAPX);
8757 match(Set dst (MulL src1 src2));
8758 effect(KILL cr);
8759
8760 ins_cost(300);
8761 format %{ "eimulq $dst, $src1, $src2\t# long ndd" %}
8762 ins_encode %{
8763 __ eimulq($dst$$Register, $src1$$Register, $src2$$constant, false);
8764 %}
8765 ins_pipe(ialu_reg_reg_alu0);
8766 %}
8767
8768 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8769 %{
8770 predicate(!UseAPX);
8771 match(Set dst (MulL dst (LoadL src)));
8772 effect(KILL cr);
8773
8774 ins_cost(350);
8775 format %{ "imulq $dst, $src\t# long" %}
8776 ins_encode %{
8777 __ imulq($dst$$Register, $src$$Address);
8778 %}
8779 ins_pipe(ialu_reg_mem_alu0);
8780 %}
8781
8782 instruct mulL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
8783 %{
8784 predicate(UseAPX);
8785 match(Set dst (MulL src1 (LoadL src2)));
8786 effect(KILL cr);
8787
8788 ins_cost(350);
8789 format %{ "eimulq $dst, $src1, $src2 \t# long" %}
8790 ins_encode %{
8791 __ eimulq($dst$$Register, $src1$$Register, $src2$$Address, false);
8792 %}
8793 ins_pipe(ialu_reg_mem_alu0);
8794 %}
8795
8796 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8797 %{
8798 predicate(!UseAPX);
8799 match(Set dst (MulL (LoadL src) imm));
8800 effect(KILL cr);
8801
8802 ins_cost(300);
8803 format %{ "imulq $dst, $src, $imm\t# long" %}
8804 ins_encode %{
8805 __ imulq($dst$$Register, $src$$Address, $imm$$constant);
8806 %}
8807 ins_pipe(ialu_reg_mem_alu0);
8808 %}
8809
8810 instruct mulL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
8811 %{
8812 predicate(UseAPX);
8813 match(Set dst (MulL (LoadL src1) src2));
8814 effect(KILL cr);
8815
8816 ins_cost(300);
8817 format %{ "eimulq $dst, $src1, $src2\t# long ndd" %}
8818 ins_encode %{
8819 __ eimulq($dst$$Register, $src1$$Address, $src2$$constant, false);
8820 %}
8821 ins_pipe(ialu_reg_mem_alu0);
8822 %}
8823
8824 instruct mulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr)
8825 %{
8826 match(Set dst (MulHiL src rax));
8827 effect(USE_KILL rax, KILL cr);
8828
8829 ins_cost(300);
8830 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8831 ins_encode %{
8832 __ imulq($src$$Register);
8833 %}
8834 ins_pipe(ialu_reg_reg_alu0);
8835 %}
8836
8837 instruct umulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr)
8838 %{
8839 match(Set dst (UMulHiL src rax));
8840 effect(USE_KILL rax, KILL cr);
8841
8842 ins_cost(300);
8843 format %{ "mulq RDX:RAX, RAX, $src\t# umulhi" %}
8844 ins_encode %{
8845 __ mulq($src$$Register);
8846 %}
8847 ins_pipe(ialu_reg_reg_alu0);
8848 %}
8849
8850 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8851 rFlagsReg cr)
8852 %{
8853 match(Set rax (DivI rax div));
8854 effect(KILL rdx, KILL cr);
8855
8856 ins_cost(30*100+10*100); // XXX
8857 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8858 "jne,s normal\n\t"
8859 "xorl rdx, rdx\n\t"
8860 "cmpl $div, -1\n\t"
8861 "je,s done\n"
8862 "normal: cdql\n\t"
8863 "idivl $div\n"
8864 "done:" %}
8865 ins_encode(cdql_enc(div));
8866 ins_pipe(ialu_reg_reg_alu0);
8867 %}
8868
8869 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8870 rFlagsReg cr)
8871 %{
8872 match(Set rax (DivL rax div));
8873 effect(KILL rdx, KILL cr);
8874
8875 ins_cost(30*100+10*100); // XXX
8876 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8877 "cmpq rax, rdx\n\t"
8878 "jne,s normal\n\t"
8879 "xorl rdx, rdx\n\t"
8880 "cmpq $div, -1\n\t"
8881 "je,s done\n"
8882 "normal: cdqq\n\t"
8883 "idivq $div\n"
8884 "done:" %}
8885 ins_encode(cdqq_enc(div));
8886 ins_pipe(ialu_reg_reg_alu0);
8887 %}
8888
8889 instruct udivI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, rFlagsReg cr)
8890 %{
8891 match(Set rax (UDivI rax div));
8892 effect(KILL rdx, KILL cr);
8893
8894 ins_cost(300);
8895 format %{ "udivl $rax,$rax,$div\t# UDivI\n" %}
8896 ins_encode %{
8897 __ udivI($rax$$Register, $div$$Register, $rdx$$Register);
8898 %}
8899 ins_pipe(ialu_reg_reg_alu0);
8900 %}
8901
8902 instruct udivL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, rFlagsReg cr)
8903 %{
8904 match(Set rax (UDivL rax div));
8905 effect(KILL rdx, KILL cr);
8906
8907 ins_cost(300);
8908 format %{ "udivq $rax,$rax,$div\t# UDivL\n" %}
8909 ins_encode %{
8910 __ udivL($rax$$Register, $div$$Register, $rdx$$Register);
8911 %}
8912 ins_pipe(ialu_reg_reg_alu0);
8913 %}
8914
8915 // Integer DIVMOD with Register, both quotient and mod results
8916 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8917 rFlagsReg cr)
8918 %{
8919 match(DivModI rax div);
8920 effect(KILL cr);
8921
8922 ins_cost(30*100+10*100); // XXX
8923 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8924 "jne,s normal\n\t"
8925 "xorl rdx, rdx\n\t"
8926 "cmpl $div, -1\n\t"
8927 "je,s done\n"
8928 "normal: cdql\n\t"
8929 "idivl $div\n"
8930 "done:" %}
8931 ins_encode(cdql_enc(div));
8932 ins_pipe(pipe_slow);
8933 %}
8934
8935 // Long DIVMOD with Register, both quotient and mod results
8936 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8937 rFlagsReg cr)
8938 %{
8939 match(DivModL rax div);
8940 effect(KILL cr);
8941
8942 ins_cost(30*100+10*100); // XXX
8943 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8944 "cmpq rax, rdx\n\t"
8945 "jne,s normal\n\t"
8946 "xorl rdx, rdx\n\t"
8947 "cmpq $div, -1\n\t"
8948 "je,s done\n"
8949 "normal: cdqq\n\t"
8950 "idivq $div\n"
8951 "done:" %}
8952 ins_encode(cdqq_enc(div));
8953 ins_pipe(pipe_slow);
8954 %}
8955
8956 // Unsigned integer DIVMOD with Register, both quotient and mod results
8957 instruct udivModI_rReg_divmod(rax_RegI rax, no_rax_rdx_RegI tmp, rdx_RegI rdx,
8958 no_rax_rdx_RegI div, rFlagsReg cr)
8959 %{
8960 match(UDivModI rax div);
8961 effect(TEMP tmp, KILL cr);
8962
8963 ins_cost(300);
8964 format %{ "udivl $rax,$rax,$div\t# begin UDivModI\n\t"
8965 "umodl $rdx,$rax,$div\t! using $tmp as TEMP # end UDivModI\n"
8966 %}
8967 ins_encode %{
8968 __ udivmodI($rax$$Register, $div$$Register, $rdx$$Register, $tmp$$Register);
8969 %}
8970 ins_pipe(pipe_slow);
8971 %}
8972
8973 // Unsigned long DIVMOD with Register, both quotient and mod results
8974 instruct udivModL_rReg_divmod(rax_RegL rax, no_rax_rdx_RegL tmp, rdx_RegL rdx,
8975 no_rax_rdx_RegL div, rFlagsReg cr)
8976 %{
8977 match(UDivModL rax div);
8978 effect(TEMP tmp, KILL cr);
8979
8980 ins_cost(300);
8981 format %{ "udivq $rax,$rax,$div\t# begin UDivModL\n\t"
8982 "umodq $rdx,$rax,$div\t! using $tmp as TEMP # end UDivModL\n"
8983 %}
8984 ins_encode %{
8985 __ udivmodL($rax$$Register, $div$$Register, $rdx$$Register, $tmp$$Register);
8986 %}
8987 ins_pipe(pipe_slow);
8988 %}
8989
8990 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8991 rFlagsReg cr)
8992 %{
8993 match(Set rdx (ModI rax div));
8994 effect(KILL rax, KILL cr);
8995
8996 ins_cost(300); // XXX
8997 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8998 "jne,s normal\n\t"
8999 "xorl rdx, rdx\n\t"
9000 "cmpl $div, -1\n\t"
9001 "je,s done\n"
9002 "normal: cdql\n\t"
9003 "idivl $div\n"
9004 "done:" %}
9005 ins_encode(cdql_enc(div));
9006 ins_pipe(ialu_reg_reg_alu0);
9007 %}
9008
9009 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
9010 rFlagsReg cr)
9011 %{
9012 match(Set rdx (ModL rax div));
9013 effect(KILL rax, KILL cr);
9014
9015 ins_cost(300); // XXX
9016 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
9017 "cmpq rax, rdx\n\t"
9018 "jne,s normal\n\t"
9019 "xorl rdx, rdx\n\t"
9020 "cmpq $div, -1\n\t"
9021 "je,s done\n"
9022 "normal: cdqq\n\t"
9023 "idivq $div\n"
9024 "done:" %}
9025 ins_encode(cdqq_enc(div));
9026 ins_pipe(ialu_reg_reg_alu0);
9027 %}
9028
9029 instruct umodI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, rFlagsReg cr)
9030 %{
9031 match(Set rdx (UModI rax div));
9032 effect(KILL rax, KILL cr);
9033
9034 ins_cost(300);
9035 format %{ "umodl $rdx,$rax,$div\t# UModI\n" %}
9036 ins_encode %{
9037 __ umodI($rax$$Register, $div$$Register, $rdx$$Register);
9038 %}
9039 ins_pipe(ialu_reg_reg_alu0);
9040 %}
9041
9042 instruct umodL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, rFlagsReg cr)
9043 %{
9044 match(Set rdx (UModL rax div));
9045 effect(KILL rax, KILL cr);
9046
9047 ins_cost(300);
9048 format %{ "umodq $rdx,$rax,$div\t# UModL\n" %}
9049 ins_encode %{
9050 __ umodL($rax$$Register, $div$$Register, $rdx$$Register);
9051 %}
9052 ins_pipe(ialu_reg_reg_alu0);
9053 %}
9054
9055 // Integer Shift Instructions
9056 // Shift Left by one, two, three
9057 instruct salI_rReg_immI2(rRegI dst, immI2 shift, rFlagsReg cr)
9058 %{
9059 predicate(!UseAPX);
9060 match(Set dst (LShiftI dst shift));
9061 effect(KILL cr);
9062
9063 format %{ "sall $dst, $shift" %}
9064 ins_encode %{
9065 __ sall($dst$$Register, $shift$$constant);
9066 %}
9067 ins_pipe(ialu_reg);
9068 %}
9069
9070 // Shift Left by one, two, three
9071 instruct salI_rReg_immI2_ndd(rRegI dst, rRegI src, immI2 shift, rFlagsReg cr)
9072 %{
9073 predicate(UseAPX);
9074 match(Set dst (LShiftI src shift));
9075 effect(KILL cr);
9076
9077 format %{ "esall $dst, $src, $shift\t# int(ndd)" %}
9078 ins_encode %{
9079 __ esall($dst$$Register, $src$$Register, $shift$$constant, false);
9080 %}
9081 ins_pipe(ialu_reg);
9082 %}
9083
9084 // Shift Left by 8-bit immediate
9085 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
9086 %{
9087 predicate(!UseAPX);
9088 match(Set dst (LShiftI dst shift));
9089 effect(KILL cr);
9090
9091 format %{ "sall $dst, $shift" %}
9092 ins_encode %{
9093 __ sall($dst$$Register, $shift$$constant);
9094 %}
9095 ins_pipe(ialu_reg);
9096 %}
9097
9098 // Shift Left by 8-bit immediate
9099 instruct salI_rReg_imm_ndd(rRegI dst, rRegI src, immI8 shift, rFlagsReg cr)
9100 %{
9101 predicate(UseAPX);
9102 match(Set dst (LShiftI src shift));
9103 effect(KILL cr);
9104
9105 format %{ "esall $dst, $src, $shift\t# int (ndd)" %}
9106 ins_encode %{
9107 __ esall($dst$$Register, $src$$Register, $shift$$constant, false);
9108 %}
9109 ins_pipe(ialu_reg);
9110 %}
9111
9112 instruct salI_rReg_mem_imm_ndd(rRegI dst, memory src, immI8 shift, rFlagsReg cr)
9113 %{
9114 predicate(UseAPX);
9115 match(Set dst (LShiftI (LoadI src) shift));
9116 effect(KILL cr);
9117
9118 format %{ "esall $dst, $src, $shift\t# int (ndd)" %}
9119 ins_encode %{
9120 __ esall($dst$$Register, $src$$Address, $shift$$constant, false);
9121 %}
9122 ins_pipe(ialu_reg);
9123 %}
9124
9125 // Shift Left by 8-bit immediate
9126 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9127 %{
9128 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
9129 effect(KILL cr);
9130
9131 format %{ "sall $dst, $shift" %}
9132 ins_encode %{
9133 __ sall($dst$$Address, $shift$$constant);
9134 %}
9135 ins_pipe(ialu_mem_imm);
9136 %}
9137
9138 // Shift Left by variable
9139 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9140 %{
9141 predicate(!VM_Version::supports_bmi2());
9142 match(Set dst (LShiftI dst shift));
9143 effect(KILL cr);
9144
9145 format %{ "sall $dst, $shift" %}
9146 ins_encode %{
9147 __ sall($dst$$Register);
9148 %}
9149 ins_pipe(ialu_reg_reg);
9150 %}
9151
9152 // Shift Left by variable
9153 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9154 %{
9155 predicate(!VM_Version::supports_bmi2());
9156 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
9157 effect(KILL cr);
9158
9159 format %{ "sall $dst, $shift" %}
9160 ins_encode %{
9161 __ sall($dst$$Address);
9162 %}
9163 ins_pipe(ialu_mem_reg);
9164 %}
9165
9166 instruct salI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
9167 %{
9168 predicate(VM_Version::supports_bmi2());
9169 match(Set dst (LShiftI src shift));
9170
9171 format %{ "shlxl $dst, $src, $shift" %}
9172 ins_encode %{
9173 __ shlxl($dst$$Register, $src$$Register, $shift$$Register);
9174 %}
9175 ins_pipe(ialu_reg_reg);
9176 %}
9177
9178 instruct salI_mem_rReg(rRegI dst, memory src, rRegI shift)
9179 %{
9180 predicate(VM_Version::supports_bmi2());
9181 match(Set dst (LShiftI (LoadI src) shift));
9182 ins_cost(175);
9183 format %{ "shlxl $dst, $src, $shift" %}
9184 ins_encode %{
9185 __ shlxl($dst$$Register, $src$$Address, $shift$$Register);
9186 %}
9187 ins_pipe(ialu_reg_mem);
9188 %}
9189
9190 // Arithmetic Shift Right by 8-bit immediate
9191 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
9192 %{
9193 predicate(!UseAPX);
9194 match(Set dst (RShiftI dst shift));
9195 effect(KILL cr);
9196
9197 format %{ "sarl $dst, $shift" %}
9198 ins_encode %{
9199 __ sarl($dst$$Register, $shift$$constant);
9200 %}
9201 ins_pipe(ialu_mem_imm);
9202 %}
9203
9204 // Arithmetic Shift Right by 8-bit immediate
9205 instruct sarI_rReg_imm_ndd(rRegI dst, rRegI src, immI8 shift, rFlagsReg cr)
9206 %{
9207 predicate(UseAPX);
9208 match(Set dst (RShiftI src shift));
9209 effect(KILL cr);
9210
9211 format %{ "esarl $dst, $src, $shift\t# int (ndd)" %}
9212 ins_encode %{
9213 __ esarl($dst$$Register, $src$$Register, $shift$$constant, false);
9214 %}
9215 ins_pipe(ialu_mem_imm);
9216 %}
9217
9218 instruct sarI_rReg_mem_imm_ndd(rRegI dst, memory src, immI8 shift, rFlagsReg cr)
9219 %{
9220 predicate(UseAPX);
9221 match(Set dst (RShiftI (LoadI src) shift));
9222 effect(KILL cr);
9223
9224 format %{ "esarl $dst, $src, $shift\t# int (ndd)" %}
9225 ins_encode %{
9226 __ esarl($dst$$Register, $src$$Address, $shift$$constant, false);
9227 %}
9228 ins_pipe(ialu_mem_imm);
9229 %}
9230
9231 // Arithmetic Shift Right by 8-bit immediate
9232 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9233 %{
9234 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9235 effect(KILL cr);
9236
9237 format %{ "sarl $dst, $shift" %}
9238 ins_encode %{
9239 __ sarl($dst$$Address, $shift$$constant);
9240 %}
9241 ins_pipe(ialu_mem_imm);
9242 %}
9243
9244 // Arithmetic Shift Right by variable
9245 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9246 %{
9247 predicate(!VM_Version::supports_bmi2());
9248 match(Set dst (RShiftI dst shift));
9249 effect(KILL cr);
9250
9251 format %{ "sarl $dst, $shift" %}
9252 ins_encode %{
9253 __ sarl($dst$$Register);
9254 %}
9255 ins_pipe(ialu_reg_reg);
9256 %}
9257
9258 // Arithmetic Shift Right by variable
9259 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9260 %{
9261 predicate(!VM_Version::supports_bmi2());
9262 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9263 effect(KILL cr);
9264
9265 format %{ "sarl $dst, $shift" %}
9266 ins_encode %{
9267 __ sarl($dst$$Address);
9268 %}
9269 ins_pipe(ialu_mem_reg);
9270 %}
9271
9272 instruct sarI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
9273 %{
9274 predicate(VM_Version::supports_bmi2());
9275 match(Set dst (RShiftI src shift));
9276
9277 format %{ "sarxl $dst, $src, $shift" %}
9278 ins_encode %{
9279 __ sarxl($dst$$Register, $src$$Register, $shift$$Register);
9280 %}
9281 ins_pipe(ialu_reg_reg);
9282 %}
9283
9284 instruct sarI_mem_rReg(rRegI dst, memory src, rRegI shift)
9285 %{
9286 predicate(VM_Version::supports_bmi2());
9287 match(Set dst (RShiftI (LoadI src) shift));
9288 ins_cost(175);
9289 format %{ "sarxl $dst, $src, $shift" %}
9290 ins_encode %{
9291 __ sarxl($dst$$Register, $src$$Address, $shift$$Register);
9292 %}
9293 ins_pipe(ialu_reg_mem);
9294 %}
9295
9296 // Logical Shift Right by 8-bit immediate
9297 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
9298 %{
9299 predicate(!UseAPX);
9300 match(Set dst (URShiftI dst shift));
9301 effect(KILL cr);
9302
9303 format %{ "shrl $dst, $shift" %}
9304 ins_encode %{
9305 __ shrl($dst$$Register, $shift$$constant);
9306 %}
9307 ins_pipe(ialu_reg);
9308 %}
9309
9310 // Logical Shift Right by 8-bit immediate
9311 instruct shrI_rReg_imm_ndd(rRegI dst, rRegI src, immI8 shift, rFlagsReg cr)
9312 %{
9313 predicate(UseAPX);
9314 match(Set dst (URShiftI src shift));
9315 effect(KILL cr);
9316
9317 format %{ "eshrl $dst, $src, $shift\t # int (ndd)" %}
9318 ins_encode %{
9319 __ eshrl($dst$$Register, $src$$Register, $shift$$constant, false);
9320 %}
9321 ins_pipe(ialu_reg);
9322 %}
9323
9324 instruct shrI_rReg_mem_imm_ndd(rRegI dst, memory src, immI8 shift, rFlagsReg cr)
9325 %{
9326 predicate(UseAPX);
9327 match(Set dst (URShiftI (LoadI src) shift));
9328 effect(KILL cr);
9329
9330 format %{ "eshrl $dst, $src, $shift\t # int (ndd)" %}
9331 ins_encode %{
9332 __ eshrl($dst$$Register, $src$$Address, $shift$$constant, false);
9333 %}
9334 ins_pipe(ialu_reg);
9335 %}
9336
9337 // Logical Shift Right by 8-bit immediate
9338 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9339 %{
9340 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
9341 effect(KILL cr);
9342
9343 format %{ "shrl $dst, $shift" %}
9344 ins_encode %{
9345 __ shrl($dst$$Address, $shift$$constant);
9346 %}
9347 ins_pipe(ialu_mem_imm);
9348 %}
9349
9350 // Logical Shift Right by variable
9351 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9352 %{
9353 predicate(!VM_Version::supports_bmi2());
9354 match(Set dst (URShiftI dst shift));
9355 effect(KILL cr);
9356
9357 format %{ "shrl $dst, $shift" %}
9358 ins_encode %{
9359 __ shrl($dst$$Register);
9360 %}
9361 ins_pipe(ialu_reg_reg);
9362 %}
9363
9364 // Logical Shift Right by variable
9365 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9366 %{
9367 predicate(!VM_Version::supports_bmi2());
9368 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
9369 effect(KILL cr);
9370
9371 format %{ "shrl $dst, $shift" %}
9372 ins_encode %{
9373 __ shrl($dst$$Address);
9374 %}
9375 ins_pipe(ialu_mem_reg);
9376 %}
9377
9378 instruct shrI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
9379 %{
9380 predicate(VM_Version::supports_bmi2());
9381 match(Set dst (URShiftI src shift));
9382
9383 format %{ "shrxl $dst, $src, $shift" %}
9384 ins_encode %{
9385 __ shrxl($dst$$Register, $src$$Register, $shift$$Register);
9386 %}
9387 ins_pipe(ialu_reg_reg);
9388 %}
9389
9390 instruct shrI_mem_rReg(rRegI dst, memory src, rRegI shift)
9391 %{
9392 predicate(VM_Version::supports_bmi2());
9393 match(Set dst (URShiftI (LoadI src) shift));
9394 ins_cost(175);
9395 format %{ "shrxl $dst, $src, $shift" %}
9396 ins_encode %{
9397 __ shrxl($dst$$Register, $src$$Address, $shift$$Register);
9398 %}
9399 ins_pipe(ialu_reg_mem);
9400 %}
9401
9402 // Long Shift Instructions
9403 // Shift Left by one, two, three
9404 instruct salL_rReg_immI2(rRegL dst, immI2 shift, rFlagsReg cr)
9405 %{
9406 predicate(!UseAPX);
9407 match(Set dst (LShiftL dst shift));
9408 effect(KILL cr);
9409
9410 format %{ "salq $dst, $shift" %}
9411 ins_encode %{
9412 __ salq($dst$$Register, $shift$$constant);
9413 %}
9414 ins_pipe(ialu_reg);
9415 %}
9416
9417 // Shift Left by one, two, three
9418 instruct salL_rReg_immI2_ndd(rRegL dst, rRegL src, immI2 shift, rFlagsReg cr)
9419 %{
9420 predicate(UseAPX);
9421 match(Set dst (LShiftL src shift));
9422 effect(KILL cr);
9423
9424 format %{ "esalq $dst, $src, $shift\t# long (ndd)" %}
9425 ins_encode %{
9426 __ esalq($dst$$Register, $src$$Register, $shift$$constant, false);
9427 %}
9428 ins_pipe(ialu_reg);
9429 %}
9430
9431 // Shift Left by 8-bit immediate
9432 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9433 %{
9434 predicate(!UseAPX);
9435 match(Set dst (LShiftL dst shift));
9436 effect(KILL cr);
9437
9438 format %{ "salq $dst, $shift" %}
9439 ins_encode %{
9440 __ salq($dst$$Register, $shift$$constant);
9441 %}
9442 ins_pipe(ialu_reg);
9443 %}
9444
9445 // Shift Left by 8-bit immediate
9446 instruct salL_rReg_imm_ndd(rRegL dst, rRegL src, immI8 shift, rFlagsReg cr)
9447 %{
9448 predicate(UseAPX);
9449 match(Set dst (LShiftL src shift));
9450 effect(KILL cr);
9451
9452 format %{ "esalq $dst, $src, $shift\t# long (ndd)" %}
9453 ins_encode %{
9454 __ esalq($dst$$Register, $src$$Register, $shift$$constant, false);
9455 %}
9456 ins_pipe(ialu_reg);
9457 %}
9458
9459 instruct salL_rReg_mem_imm_ndd(rRegL dst, memory src, immI8 shift, rFlagsReg cr)
9460 %{
9461 predicate(UseAPX);
9462 match(Set dst (LShiftL (LoadL src) shift));
9463 effect(KILL cr);
9464
9465 format %{ "esalq $dst, $src, $shift\t# long (ndd)" %}
9466 ins_encode %{
9467 __ esalq($dst$$Register, $src$$Address, $shift$$constant, false);
9468 %}
9469 ins_pipe(ialu_reg);
9470 %}
9471
9472 // Shift Left by 8-bit immediate
9473 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9474 %{
9475 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9476 effect(KILL cr);
9477
9478 format %{ "salq $dst, $shift" %}
9479 ins_encode %{
9480 __ salq($dst$$Address, $shift$$constant);
9481 %}
9482 ins_pipe(ialu_mem_imm);
9483 %}
9484
9485 // Shift Left by variable
9486 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9487 %{
9488 predicate(!VM_Version::supports_bmi2());
9489 match(Set dst (LShiftL dst shift));
9490 effect(KILL cr);
9491
9492 format %{ "salq $dst, $shift" %}
9493 ins_encode %{
9494 __ salq($dst$$Register);
9495 %}
9496 ins_pipe(ialu_reg_reg);
9497 %}
9498
9499 // Shift Left by variable
9500 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9501 %{
9502 predicate(!VM_Version::supports_bmi2());
9503 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9504 effect(KILL cr);
9505
9506 format %{ "salq $dst, $shift" %}
9507 ins_encode %{
9508 __ salq($dst$$Address);
9509 %}
9510 ins_pipe(ialu_mem_reg);
9511 %}
9512
9513 instruct salL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
9514 %{
9515 predicate(VM_Version::supports_bmi2());
9516 match(Set dst (LShiftL src shift));
9517
9518 format %{ "shlxq $dst, $src, $shift" %}
9519 ins_encode %{
9520 __ shlxq($dst$$Register, $src$$Register, $shift$$Register);
9521 %}
9522 ins_pipe(ialu_reg_reg);
9523 %}
9524
9525 instruct salL_mem_rReg(rRegL dst, memory src, rRegI shift)
9526 %{
9527 predicate(VM_Version::supports_bmi2());
9528 match(Set dst (LShiftL (LoadL src) shift));
9529 ins_cost(175);
9530 format %{ "shlxq $dst, $src, $shift" %}
9531 ins_encode %{
9532 __ shlxq($dst$$Register, $src$$Address, $shift$$Register);
9533 %}
9534 ins_pipe(ialu_reg_mem);
9535 %}
9536
9537 // Arithmetic Shift Right by 8-bit immediate
9538 instruct sarL_rReg_imm(rRegL dst, immI shift, rFlagsReg cr)
9539 %{
9540 predicate(!UseAPX);
9541 match(Set dst (RShiftL dst shift));
9542 effect(KILL cr);
9543
9544 format %{ "sarq $dst, $shift" %}
9545 ins_encode %{
9546 __ sarq($dst$$Register, (unsigned char)($shift$$constant & 0x3F));
9547 %}
9548 ins_pipe(ialu_mem_imm);
9549 %}
9550
9551 // Arithmetic Shift Right by 8-bit immediate
9552 instruct sarL_rReg_imm_ndd(rRegL dst, rRegL src, immI shift, rFlagsReg cr)
9553 %{
9554 predicate(UseAPX);
9555 match(Set dst (RShiftL src shift));
9556 effect(KILL cr);
9557
9558 format %{ "esarq $dst, $src, $shift\t# long (ndd)" %}
9559 ins_encode %{
9560 __ esarq($dst$$Register, $src$$Register, (unsigned char)($shift$$constant & 0x3F), false);
9561 %}
9562 ins_pipe(ialu_mem_imm);
9563 %}
9564
9565 instruct sarL_rReg_mem_imm_ndd(rRegL dst, memory src, immI shift, rFlagsReg cr)
9566 %{
9567 predicate(UseAPX);
9568 match(Set dst (RShiftL (LoadL src) shift));
9569 effect(KILL cr);
9570
9571 format %{ "esarq $dst, $src, $shift\t# long (ndd)" %}
9572 ins_encode %{
9573 __ esarq($dst$$Register, $src$$Address, (unsigned char)($shift$$constant & 0x3F), false);
9574 %}
9575 ins_pipe(ialu_mem_imm);
9576 %}
9577
9578 // Arithmetic Shift Right by 8-bit immediate
9579 instruct sarL_mem_imm(memory dst, immI shift, rFlagsReg cr)
9580 %{
9581 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9582 effect(KILL cr);
9583
9584 format %{ "sarq $dst, $shift" %}
9585 ins_encode %{
9586 __ sarq($dst$$Address, (unsigned char)($shift$$constant & 0x3F));
9587 %}
9588 ins_pipe(ialu_mem_imm);
9589 %}
9590
9591 // Arithmetic Shift Right by variable
9592 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9593 %{
9594 predicate(!VM_Version::supports_bmi2());
9595 match(Set dst (RShiftL dst shift));
9596 effect(KILL cr);
9597
9598 format %{ "sarq $dst, $shift" %}
9599 ins_encode %{
9600 __ sarq($dst$$Register);
9601 %}
9602 ins_pipe(ialu_reg_reg);
9603 %}
9604
9605 // Arithmetic Shift Right by variable
9606 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9607 %{
9608 predicate(!VM_Version::supports_bmi2());
9609 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9610 effect(KILL cr);
9611
9612 format %{ "sarq $dst, $shift" %}
9613 ins_encode %{
9614 __ sarq($dst$$Address);
9615 %}
9616 ins_pipe(ialu_mem_reg);
9617 %}
9618
9619 instruct sarL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
9620 %{
9621 predicate(VM_Version::supports_bmi2());
9622 match(Set dst (RShiftL src shift));
9623
9624 format %{ "sarxq $dst, $src, $shift" %}
9625 ins_encode %{
9626 __ sarxq($dst$$Register, $src$$Register, $shift$$Register);
9627 %}
9628 ins_pipe(ialu_reg_reg);
9629 %}
9630
9631 instruct sarL_mem_rReg(rRegL dst, memory src, rRegI shift)
9632 %{
9633 predicate(VM_Version::supports_bmi2());
9634 match(Set dst (RShiftL (LoadL src) shift));
9635 ins_cost(175);
9636 format %{ "sarxq $dst, $src, $shift" %}
9637 ins_encode %{
9638 __ sarxq($dst$$Register, $src$$Address, $shift$$Register);
9639 %}
9640 ins_pipe(ialu_reg_mem);
9641 %}
9642
9643 // Logical Shift Right by 8-bit immediate
9644 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9645 %{
9646 predicate(!UseAPX);
9647 match(Set dst (URShiftL dst shift));
9648 effect(KILL cr);
9649
9650 format %{ "shrq $dst, $shift" %}
9651 ins_encode %{
9652 __ shrq($dst$$Register, $shift$$constant);
9653 %}
9654 ins_pipe(ialu_reg);
9655 %}
9656
9657 // Logical Shift Right by 8-bit immediate
9658 instruct shrL_rReg_imm_ndd(rRegL dst, rRegL src, immI8 shift, rFlagsReg cr)
9659 %{
9660 predicate(UseAPX);
9661 match(Set dst (URShiftL src shift));
9662 effect(KILL cr);
9663
9664 format %{ "eshrq $dst, $src, $shift\t# long (ndd)" %}
9665 ins_encode %{
9666 __ eshrq($dst$$Register, $src$$Register, $shift$$constant, false);
9667 %}
9668 ins_pipe(ialu_reg);
9669 %}
9670
9671 instruct shrL_rReg_mem_imm_ndd(rRegL dst, memory src, immI8 shift, rFlagsReg cr)
9672 %{
9673 predicate(UseAPX);
9674 match(Set dst (URShiftL (LoadL src) shift));
9675 effect(KILL cr);
9676
9677 format %{ "eshrq $dst, $src, $shift\t# long (ndd)" %}
9678 ins_encode %{
9679 __ eshrq($dst$$Register, $src$$Address, $shift$$constant, false);
9680 %}
9681 ins_pipe(ialu_reg);
9682 %}
9683
9684 // Logical Shift Right by 8-bit immediate
9685 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9686 %{
9687 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9688 effect(KILL cr);
9689
9690 format %{ "shrq $dst, $shift" %}
9691 ins_encode %{
9692 __ shrq($dst$$Address, $shift$$constant);
9693 %}
9694 ins_pipe(ialu_mem_imm);
9695 %}
9696
9697 // Logical Shift Right by variable
9698 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9699 %{
9700 predicate(!VM_Version::supports_bmi2());
9701 match(Set dst (URShiftL dst shift));
9702 effect(KILL cr);
9703
9704 format %{ "shrq $dst, $shift" %}
9705 ins_encode %{
9706 __ shrq($dst$$Register);
9707 %}
9708 ins_pipe(ialu_reg_reg);
9709 %}
9710
9711 // Logical Shift Right by variable
9712 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9713 %{
9714 predicate(!VM_Version::supports_bmi2());
9715 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9716 effect(KILL cr);
9717
9718 format %{ "shrq $dst, $shift" %}
9719 ins_encode %{
9720 __ shrq($dst$$Address);
9721 %}
9722 ins_pipe(ialu_mem_reg);
9723 %}
9724
9725 instruct shrL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
9726 %{
9727 predicate(VM_Version::supports_bmi2());
9728 match(Set dst (URShiftL src shift));
9729
9730 format %{ "shrxq $dst, $src, $shift" %}
9731 ins_encode %{
9732 __ shrxq($dst$$Register, $src$$Register, $shift$$Register);
9733 %}
9734 ins_pipe(ialu_reg_reg);
9735 %}
9736
9737 instruct shrL_mem_rReg(rRegL dst, memory src, rRegI shift)
9738 %{
9739 predicate(VM_Version::supports_bmi2());
9740 match(Set dst (URShiftL (LoadL src) shift));
9741 ins_cost(175);
9742 format %{ "shrxq $dst, $src, $shift" %}
9743 ins_encode %{
9744 __ shrxq($dst$$Register, $src$$Address, $shift$$Register);
9745 %}
9746 ins_pipe(ialu_reg_mem);
9747 %}
9748
9749 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9750 // This idiom is used by the compiler for the i2b bytecode.
9751 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9752 %{
9753 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9754
9755 format %{ "movsbl $dst, $src\t# i2b" %}
9756 ins_encode %{
9757 __ movsbl($dst$$Register, $src$$Register);
9758 %}
9759 ins_pipe(ialu_reg_reg);
9760 %}
9761
9762 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9763 // This idiom is used by the compiler the i2s bytecode.
9764 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9765 %{
9766 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9767
9768 format %{ "movswl $dst, $src\t# i2s" %}
9769 ins_encode %{
9770 __ movswl($dst$$Register, $src$$Register);
9771 %}
9772 ins_pipe(ialu_reg_reg);
9773 %}
9774
9775 // ROL/ROR instructions
9776
9777 // Rotate left by constant.
9778 instruct rolI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
9779 %{
9780 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9781 match(Set dst (RotateLeft dst shift));
9782 effect(KILL cr);
9783 format %{ "roll $dst, $shift" %}
9784 ins_encode %{
9785 __ roll($dst$$Register, $shift$$constant);
9786 %}
9787 ins_pipe(ialu_reg);
9788 %}
9789
9790 instruct rolI_immI8(rRegI dst, rRegI src, immI8 shift)
9791 %{
9792 predicate(!UseAPX && VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9793 match(Set dst (RotateLeft src shift));
9794 format %{ "rolxl $dst, $src, $shift" %}
9795 ins_encode %{
9796 int shift = 32 - ($shift$$constant & 31);
9797 __ rorxl($dst$$Register, $src$$Register, shift);
9798 %}
9799 ins_pipe(ialu_reg_reg);
9800 %}
9801
9802 instruct rolI_mem_immI8(rRegI dst, memory src, immI8 shift)
9803 %{
9804 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9805 match(Set dst (RotateLeft (LoadI src) shift));
9806 ins_cost(175);
9807 format %{ "rolxl $dst, $src, $shift" %}
9808 ins_encode %{
9809 int shift = 32 - ($shift$$constant & 31);
9810 __ rorxl($dst$$Register, $src$$Address, shift);
9811 %}
9812 ins_pipe(ialu_reg_mem);
9813 %}
9814
9815 // Rotate Left by variable
9816 instruct rolI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9817 %{
9818 predicate(!UseAPX && n->bottom_type()->basic_type() == T_INT);
9819 match(Set dst (RotateLeft dst shift));
9820 effect(KILL cr);
9821 format %{ "roll $dst, $shift" %}
9822 ins_encode %{
9823 __ roll($dst$$Register);
9824 %}
9825 ins_pipe(ialu_reg_reg);
9826 %}
9827
9828 // Rotate Left by variable
9829 instruct rolI_rReg_Var_ndd(rRegI dst, rRegI src, rcx_RegI shift, rFlagsReg cr)
9830 %{
9831 predicate(UseAPX && n->bottom_type()->basic_type() == T_INT);
9832 match(Set dst (RotateLeft src shift));
9833 effect(KILL cr);
9834
9835 format %{ "eroll $dst, $src, $shift\t# rotate left (int ndd)" %}
9836 ins_encode %{
9837 __ eroll($dst$$Register, $src$$Register, false);
9838 %}
9839 ins_pipe(ialu_reg_reg);
9840 %}
9841
9842 // Rotate Right by constant.
9843 instruct rorI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
9844 %{
9845 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9846 match(Set dst (RotateRight dst shift));
9847 effect(KILL cr);
9848 format %{ "rorl $dst, $shift" %}
9849 ins_encode %{
9850 __ rorl($dst$$Register, $shift$$constant);
9851 %}
9852 ins_pipe(ialu_reg);
9853 %}
9854
9855 // Rotate Right by constant.
9856 instruct rorI_immI8(rRegI dst, rRegI src, immI8 shift)
9857 %{
9858 predicate(!UseAPX && VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9859 match(Set dst (RotateRight src shift));
9860 format %{ "rorxl $dst, $src, $shift" %}
9861 ins_encode %{
9862 __ rorxl($dst$$Register, $src$$Register, $shift$$constant);
9863 %}
9864 ins_pipe(ialu_reg_reg);
9865 %}
9866
9867 instruct rorI_mem_immI8(rRegI dst, memory src, immI8 shift)
9868 %{
9869 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9870 match(Set dst (RotateRight (LoadI src) shift));
9871 ins_cost(175);
9872 format %{ "rorxl $dst, $src, $shift" %}
9873 ins_encode %{
9874 __ rorxl($dst$$Register, $src$$Address, $shift$$constant);
9875 %}
9876 ins_pipe(ialu_reg_mem);
9877 %}
9878
9879 // Rotate Right by variable
9880 instruct rorI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9881 %{
9882 predicate(!UseAPX && n->bottom_type()->basic_type() == T_INT);
9883 match(Set dst (RotateRight dst shift));
9884 effect(KILL cr);
9885 format %{ "rorl $dst, $shift" %}
9886 ins_encode %{
9887 __ rorl($dst$$Register);
9888 %}
9889 ins_pipe(ialu_reg_reg);
9890 %}
9891
9892 // Rotate Right by variable
9893 instruct rorI_rReg_Var_ndd(rRegI dst, rRegI src, rcx_RegI shift, rFlagsReg cr)
9894 %{
9895 predicate(UseAPX && n->bottom_type()->basic_type() == T_INT);
9896 match(Set dst (RotateRight src shift));
9897 effect(KILL cr);
9898
9899 format %{ "erorl $dst, $src, $shift\t# rotate right(int ndd)" %}
9900 ins_encode %{
9901 __ erorl($dst$$Register, $src$$Register, false);
9902 %}
9903 ins_pipe(ialu_reg_reg);
9904 %}
9905
9906 // Rotate Left by constant.
9907 instruct rolL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr)
9908 %{
9909 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9910 match(Set dst (RotateLeft dst shift));
9911 effect(KILL cr);
9912 format %{ "rolq $dst, $shift" %}
9913 ins_encode %{
9914 __ rolq($dst$$Register, $shift$$constant);
9915 %}
9916 ins_pipe(ialu_reg);
9917 %}
9918
9919 instruct rolL_immI8(rRegL dst, rRegL src, immI8 shift)
9920 %{
9921 predicate(!UseAPX && VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9922 match(Set dst (RotateLeft src shift));
9923 format %{ "rolxq $dst, $src, $shift" %}
9924 ins_encode %{
9925 int shift = 64 - ($shift$$constant & 63);
9926 __ rorxq($dst$$Register, $src$$Register, shift);
9927 %}
9928 ins_pipe(ialu_reg_reg);
9929 %}
9930
9931 instruct rolL_mem_immI8(rRegL dst, memory src, immI8 shift)
9932 %{
9933 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9934 match(Set dst (RotateLeft (LoadL src) shift));
9935 ins_cost(175);
9936 format %{ "rolxq $dst, $src, $shift" %}
9937 ins_encode %{
9938 int shift = 64 - ($shift$$constant & 63);
9939 __ rorxq($dst$$Register, $src$$Address, shift);
9940 %}
9941 ins_pipe(ialu_reg_mem);
9942 %}
9943
9944 // Rotate Left by variable
9945 instruct rolL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9946 %{
9947 predicate(!UseAPX && n->bottom_type()->basic_type() == T_LONG);
9948 match(Set dst (RotateLeft dst shift));
9949 effect(KILL cr);
9950 format %{ "rolq $dst, $shift" %}
9951 ins_encode %{
9952 __ rolq($dst$$Register);
9953 %}
9954 ins_pipe(ialu_reg_reg);
9955 %}
9956
9957 // Rotate Left by variable
9958 instruct rolL_rReg_Var_ndd(rRegL dst, rRegL src, rcx_RegI shift, rFlagsReg cr)
9959 %{
9960 predicate(UseAPX && n->bottom_type()->basic_type() == T_LONG);
9961 match(Set dst (RotateLeft src shift));
9962 effect(KILL cr);
9963
9964 format %{ "erolq $dst, $src, $shift\t# rotate left(long ndd)" %}
9965 ins_encode %{
9966 __ erolq($dst$$Register, $src$$Register, false);
9967 %}
9968 ins_pipe(ialu_reg_reg);
9969 %}
9970
9971 // Rotate Right by constant.
9972 instruct rorL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr)
9973 %{
9974 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9975 match(Set dst (RotateRight dst shift));
9976 effect(KILL cr);
9977 format %{ "rorq $dst, $shift" %}
9978 ins_encode %{
9979 __ rorq($dst$$Register, $shift$$constant);
9980 %}
9981 ins_pipe(ialu_reg);
9982 %}
9983
9984 // Rotate Right by constant
9985 instruct rorL_immI8(rRegL dst, rRegL src, immI8 shift)
9986 %{
9987 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9988 match(Set dst (RotateRight src shift));
9989 format %{ "rorxq $dst, $src, $shift" %}
9990 ins_encode %{
9991 __ rorxq($dst$$Register, $src$$Register, $shift$$constant);
9992 %}
9993 ins_pipe(ialu_reg_reg);
9994 %}
9995
9996 instruct rorL_mem_immI8(rRegL dst, memory src, immI8 shift)
9997 %{
9998 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9999 match(Set dst (RotateRight (LoadL src) shift));
10000 ins_cost(175);
10001 format %{ "rorxq $dst, $src, $shift" %}
10002 ins_encode %{
10003 __ rorxq($dst$$Register, $src$$Address, $shift$$constant);
10004 %}
10005 ins_pipe(ialu_reg_mem);
10006 %}
10007
10008 // Rotate Right by variable
10009 instruct rorL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
10010 %{
10011 predicate(!UseAPX && n->bottom_type()->basic_type() == T_LONG);
10012 match(Set dst (RotateRight dst shift));
10013 effect(KILL cr);
10014 format %{ "rorq $dst, $shift" %}
10015 ins_encode %{
10016 __ rorq($dst$$Register);
10017 %}
10018 ins_pipe(ialu_reg_reg);
10019 %}
10020
10021 // Rotate Right by variable
10022 instruct rorL_rReg_Var_ndd(rRegL dst, rRegL src, rcx_RegI shift, rFlagsReg cr)
10023 %{
10024 predicate(UseAPX && n->bottom_type()->basic_type() == T_LONG);
10025 match(Set dst (RotateRight src shift));
10026 effect(KILL cr);
10027
10028 format %{ "erorq $dst, $src, $shift\t# rotate right(long ndd)" %}
10029 ins_encode %{
10030 __ erorq($dst$$Register, $src$$Register, false);
10031 %}
10032 ins_pipe(ialu_reg_reg);
10033 %}
10034
10035 //----------------------------- CompressBits/ExpandBits ------------------------
10036
10037 instruct compressBitsL_reg(rRegL dst, rRegL src, rRegL mask) %{
10038 predicate(n->bottom_type()->isa_long());
10039 match(Set dst (CompressBits src mask));
10040 format %{ "pextq $dst, $src, $mask\t! parallel bit extract" %}
10041 ins_encode %{
10042 __ pextq($dst$$Register, $src$$Register, $mask$$Register);
10043 %}
10044 ins_pipe( pipe_slow );
10045 %}
10046
10047 instruct expandBitsL_reg(rRegL dst, rRegL src, rRegL mask) %{
10048 predicate(n->bottom_type()->isa_long());
10049 match(Set dst (ExpandBits src mask));
10050 format %{ "pdepq $dst, $src, $mask\t! parallel bit deposit" %}
10051 ins_encode %{
10052 __ pdepq($dst$$Register, $src$$Register, $mask$$Register);
10053 %}
10054 ins_pipe( pipe_slow );
10055 %}
10056
10057 instruct compressBitsL_mem(rRegL dst, rRegL src, memory mask) %{
10058 predicate(n->bottom_type()->isa_long());
10059 match(Set dst (CompressBits src (LoadL mask)));
10060 format %{ "pextq $dst, $src, $mask\t! parallel bit extract" %}
10061 ins_encode %{
10062 __ pextq($dst$$Register, $src$$Register, $mask$$Address);
10063 %}
10064 ins_pipe( pipe_slow );
10065 %}
10066
10067 instruct expandBitsL_mem(rRegL dst, rRegL src, memory mask) %{
10068 predicate(n->bottom_type()->isa_long());
10069 match(Set dst (ExpandBits src (LoadL mask)));
10070 format %{ "pdepq $dst, $src, $mask\t! parallel bit deposit" %}
10071 ins_encode %{
10072 __ pdepq($dst$$Register, $src$$Register, $mask$$Address);
10073 %}
10074 ins_pipe( pipe_slow );
10075 %}
10076
10077
10078 // Logical Instructions
10079
10080 // Integer Logical Instructions
10081
10082 // And Instructions
10083 // And Register with Register
10084 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
10085 %{
10086 predicate(!UseAPX);
10087 match(Set dst (AndI dst src));
10088 effect(KILL cr);
10089 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10090
10091 format %{ "andl $dst, $src\t# int" %}
10092 ins_encode %{
10093 __ andl($dst$$Register, $src$$Register);
10094 %}
10095 ins_pipe(ialu_reg_reg);
10096 %}
10097
10098 // And Register with Register using New Data Destination (NDD)
10099 instruct andI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
10100 %{
10101 predicate(UseAPX);
10102 match(Set dst (AndI src1 src2));
10103 effect(KILL cr);
10104 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10105
10106 format %{ "eandl $dst, $src1, $src2\t# int ndd" %}
10107 ins_encode %{
10108 __ eandl($dst$$Register, $src1$$Register, $src2$$Register, false);
10109
10110 %}
10111 ins_pipe(ialu_reg_reg);
10112 %}
10113
10114 // And Register with Immediate 255
10115 instruct andI_rReg_imm255(rRegI dst, rRegI src, immI_255 mask)
10116 %{
10117 match(Set dst (AndI src mask));
10118
10119 format %{ "movzbl $dst, $src\t# int & 0xFF" %}
10120 ins_encode %{
10121 __ movzbl($dst$$Register, $src$$Register);
10122 %}
10123 ins_pipe(ialu_reg);
10124 %}
10125
10126 // And Register with Immediate 255 and promote to long
10127 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
10128 %{
10129 match(Set dst (ConvI2L (AndI src mask)));
10130
10131 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
10132 ins_encode %{
10133 __ movzbl($dst$$Register, $src$$Register);
10134 %}
10135 ins_pipe(ialu_reg);
10136 %}
10137
10138 // And Register with Immediate 65535
10139 instruct andI_rReg_imm65535(rRegI dst, rRegI src, immI_65535 mask)
10140 %{
10141 match(Set dst (AndI src mask));
10142
10143 format %{ "movzwl $dst, $src\t# int & 0xFFFF" %}
10144 ins_encode %{
10145 __ movzwl($dst$$Register, $src$$Register);
10146 %}
10147 ins_pipe(ialu_reg);
10148 %}
10149
10150 // And Register with Immediate 65535 and promote to long
10151 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
10152 %{
10153 match(Set dst (ConvI2L (AndI src mask)));
10154
10155 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
10156 ins_encode %{
10157 __ movzwl($dst$$Register, $src$$Register);
10158 %}
10159 ins_pipe(ialu_reg);
10160 %}
10161
10162 // Can skip int2long conversions after AND with small bitmask
10163 instruct convI2LAndI_reg_immIbitmask(rRegL dst, rRegI src, immI_Pow2M1 mask, rRegI tmp, rFlagsReg cr)
10164 %{
10165 predicate(VM_Version::supports_bmi2());
10166 ins_cost(125);
10167 effect(TEMP tmp, KILL cr);
10168 match(Set dst (ConvI2L (AndI src mask)));
10169 format %{ "bzhiq $dst, $src, $mask \t# using $tmp as TEMP, int & immI_Pow2M1 -> long" %}
10170 ins_encode %{
10171 __ movl($tmp$$Register, exact_log2($mask$$constant + 1));
10172 __ bzhiq($dst$$Register, $src$$Register, $tmp$$Register);
10173 %}
10174 ins_pipe(ialu_reg_reg);
10175 %}
10176
10177 // And Register with Immediate
10178 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
10179 %{
10180 predicate(!UseAPX);
10181 match(Set dst (AndI dst src));
10182 effect(KILL cr);
10183 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10184
10185 format %{ "andl $dst, $src\t# int" %}
10186 ins_encode %{
10187 __ andl($dst$$Register, $src$$constant);
10188 %}
10189 ins_pipe(ialu_reg);
10190 %}
10191
10192 instruct andI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
10193 %{
10194 predicate(UseAPX);
10195 match(Set dst (AndI src1 src2));
10196 effect(KILL cr);
10197 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10198
10199 format %{ "eandl $dst, $src1, $src2\t# int ndd" %}
10200 ins_encode %{
10201 __ eandl($dst$$Register, $src1$$Register, $src2$$constant, false);
10202 %}
10203 ins_pipe(ialu_reg);
10204 %}
10205
10206 instruct andI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
10207 %{
10208 predicate(UseAPX);
10209 match(Set dst (AndI (LoadI src1) src2));
10210 effect(KILL cr);
10211 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10212
10213 format %{ "eandl $dst, $src1, $src2\t# int ndd" %}
10214 ins_encode %{
10215 __ eandl($dst$$Register, $src1$$Address, $src2$$constant, false);
10216 %}
10217 ins_pipe(ialu_reg);
10218 %}
10219
10220 // And Register with Memory
10221 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
10222 %{
10223 predicate(!UseAPX);
10224 match(Set dst (AndI dst (LoadI src)));
10225 effect(KILL cr);
10226 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10227
10228 ins_cost(150);
10229 format %{ "andl $dst, $src\t# int" %}
10230 ins_encode %{
10231 __ andl($dst$$Register, $src$$Address);
10232 %}
10233 ins_pipe(ialu_reg_mem);
10234 %}
10235
10236 instruct andI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
10237 %{
10238 predicate(UseAPX);
10239 match(Set dst (AndI src1 (LoadI src2)));
10240 effect(KILL cr);
10241 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10242
10243 ins_cost(150);
10244 format %{ "eandl $dst, $src1, $src2\t# int ndd" %}
10245 ins_encode %{
10246 __ eandl($dst$$Register, $src1$$Register, $src2$$Address, false);
10247 %}
10248 ins_pipe(ialu_reg_mem);
10249 %}
10250
10251 // And Memory with Register
10252 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10253 %{
10254 match(Set dst (StoreB dst (AndI (LoadB dst) src)));
10255 effect(KILL cr);
10256 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10257
10258 ins_cost(150);
10259 format %{ "andb $dst, $src\t# byte" %}
10260 ins_encode %{
10261 __ andb($dst$$Address, $src$$Register);
10262 %}
10263 ins_pipe(ialu_mem_reg);
10264 %}
10265
10266 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10267 %{
10268 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
10269 effect(KILL cr);
10270 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10271
10272 ins_cost(150);
10273 format %{ "andl $dst, $src\t# int" %}
10274 ins_encode %{
10275 __ andl($dst$$Address, $src$$Register);
10276 %}
10277 ins_pipe(ialu_mem_reg);
10278 %}
10279
10280 // And Memory with Immediate
10281 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
10282 %{
10283 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
10284 effect(KILL cr);
10285 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10286
10287 ins_cost(125);
10288 format %{ "andl $dst, $src\t# int" %}
10289 ins_encode %{
10290 __ andl($dst$$Address, $src$$constant);
10291 %}
10292 ins_pipe(ialu_mem_imm);
10293 %}
10294
10295 // BMI1 instructions
10296 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
10297 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
10298 predicate(UseBMI1Instructions);
10299 effect(KILL cr);
10300 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10301
10302 ins_cost(125);
10303 format %{ "andnl $dst, $src1, $src2" %}
10304
10305 ins_encode %{
10306 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
10307 %}
10308 ins_pipe(ialu_reg_mem);
10309 %}
10310
10311 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
10312 match(Set dst (AndI (XorI src1 minus_1) src2));
10313 predicate(UseBMI1Instructions);
10314 effect(KILL cr);
10315 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10316
10317 format %{ "andnl $dst, $src1, $src2" %}
10318
10319 ins_encode %{
10320 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
10321 %}
10322 ins_pipe(ialu_reg);
10323 %}
10324
10325 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, rFlagsReg cr) %{
10326 match(Set dst (AndI (SubI imm_zero src) src));
10327 predicate(UseBMI1Instructions);
10328 effect(KILL cr);
10329 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10330
10331 format %{ "blsil $dst, $src" %}
10332
10333 ins_encode %{
10334 __ blsil($dst$$Register, $src$$Register);
10335 %}
10336 ins_pipe(ialu_reg);
10337 %}
10338
10339 instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, rFlagsReg cr) %{
10340 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
10341 predicate(UseBMI1Instructions);
10342 effect(KILL cr);
10343 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10344
10345 ins_cost(125);
10346 format %{ "blsil $dst, $src" %}
10347
10348 ins_encode %{
10349 __ blsil($dst$$Register, $src$$Address);
10350 %}
10351 ins_pipe(ialu_reg_mem);
10352 %}
10353
10354 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
10355 %{
10356 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
10357 predicate(UseBMI1Instructions);
10358 effect(KILL cr);
10359 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
10360
10361 ins_cost(125);
10362 format %{ "blsmskl $dst, $src" %}
10363
10364 ins_encode %{
10365 __ blsmskl($dst$$Register, $src$$Address);
10366 %}
10367 ins_pipe(ialu_reg_mem);
10368 %}
10369
10370 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
10371 %{
10372 match(Set dst (XorI (AddI src minus_1) src));
10373 predicate(UseBMI1Instructions);
10374 effect(KILL cr);
10375 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
10376
10377 format %{ "blsmskl $dst, $src" %}
10378
10379 ins_encode %{
10380 __ blsmskl($dst$$Register, $src$$Register);
10381 %}
10382
10383 ins_pipe(ialu_reg);
10384 %}
10385
10386 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
10387 %{
10388 match(Set dst (AndI (AddI src minus_1) src) );
10389 predicate(UseBMI1Instructions);
10390 effect(KILL cr);
10391 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10392
10393 format %{ "blsrl $dst, $src" %}
10394
10395 ins_encode %{
10396 __ blsrl($dst$$Register, $src$$Register);
10397 %}
10398
10399 ins_pipe(ialu_reg_mem);
10400 %}
10401
10402 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
10403 %{
10404 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
10405 predicate(UseBMI1Instructions);
10406 effect(KILL cr);
10407 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10408
10409 ins_cost(125);
10410 format %{ "blsrl $dst, $src" %}
10411
10412 ins_encode %{
10413 __ blsrl($dst$$Register, $src$$Address);
10414 %}
10415
10416 ins_pipe(ialu_reg);
10417 %}
10418
10419 // Or Instructions
10420 // Or Register with Register
10421 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
10422 %{
10423 predicate(!UseAPX);
10424 match(Set dst (OrI dst src));
10425 effect(KILL cr);
10426 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10427
10428 format %{ "orl $dst, $src\t# int" %}
10429 ins_encode %{
10430 __ orl($dst$$Register, $src$$Register);
10431 %}
10432 ins_pipe(ialu_reg_reg);
10433 %}
10434
10435 // Or Register with Register using New Data Destination (NDD)
10436 instruct orI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
10437 %{
10438 predicate(UseAPX);
10439 match(Set dst (OrI src1 src2));
10440 effect(KILL cr);
10441 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10442
10443 format %{ "eorl $dst, $src1, $src2\t# int ndd" %}
10444 ins_encode %{
10445 __ eorl($dst$$Register, $src1$$Register, $src2$$Register, false);
10446 %}
10447 ins_pipe(ialu_reg_reg);
10448 %}
10449
10450 // Or Register with Immediate
10451 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
10452 %{
10453 predicate(!UseAPX);
10454 match(Set dst (OrI dst src));
10455 effect(KILL cr);
10456 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10457
10458 format %{ "orl $dst, $src\t# int" %}
10459 ins_encode %{
10460 __ orl($dst$$Register, $src$$constant);
10461 %}
10462 ins_pipe(ialu_reg);
10463 %}
10464
10465 instruct orI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
10466 %{
10467 predicate(UseAPX);
10468 match(Set dst (OrI src1 src2));
10469 effect(KILL cr);
10470 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10471
10472 format %{ "eorl $dst, $src1, $src2\t# int ndd" %}
10473 ins_encode %{
10474 __ eorl($dst$$Register, $src1$$Register, $src2$$constant, false);
10475 %}
10476 ins_pipe(ialu_reg);
10477 %}
10478
10479 instruct orI_rReg_imm_rReg_ndd(rRegI dst, immI src1, rRegI src2, rFlagsReg cr)
10480 %{
10481 predicate(UseAPX);
10482 match(Set dst (OrI src1 src2));
10483 effect(KILL cr);
10484 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10485
10486 format %{ "eorl $dst, $src2, $src1\t# int ndd" %}
10487 ins_encode %{
10488 __ eorl($dst$$Register, $src2$$Register, $src1$$constant, false);
10489 %}
10490 ins_pipe(ialu_reg);
10491 %}
10492
10493 instruct orI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
10494 %{
10495 predicate(UseAPX);
10496 match(Set dst (OrI (LoadI src1) src2));
10497 effect(KILL cr);
10498 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10499
10500 format %{ "eorl $dst, $src1, $src2\t# int ndd" %}
10501 ins_encode %{
10502 __ eorl($dst$$Register, $src1$$Address, $src2$$constant, false);
10503 %}
10504 ins_pipe(ialu_reg);
10505 %}
10506
10507 // Or Register with Memory
10508 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
10509 %{
10510 predicate(!UseAPX);
10511 match(Set dst (OrI dst (LoadI src)));
10512 effect(KILL cr);
10513 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10514
10515 ins_cost(150);
10516 format %{ "orl $dst, $src\t# int" %}
10517 ins_encode %{
10518 __ orl($dst$$Register, $src$$Address);
10519 %}
10520 ins_pipe(ialu_reg_mem);
10521 %}
10522
10523 instruct orI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
10524 %{
10525 predicate(UseAPX);
10526 match(Set dst (OrI src1 (LoadI src2)));
10527 effect(KILL cr);
10528 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10529
10530 ins_cost(150);
10531 format %{ "eorl $dst, $src1, $src2\t# int ndd" %}
10532 ins_encode %{
10533 __ eorl($dst$$Register, $src1$$Register, $src2$$Address, false);
10534 %}
10535 ins_pipe(ialu_reg_mem);
10536 %}
10537
10538 // Or Memory with Register
10539 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10540 %{
10541 match(Set dst (StoreB dst (OrI (LoadB dst) src)));
10542 effect(KILL cr);
10543 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10544
10545 ins_cost(150);
10546 format %{ "orb $dst, $src\t# byte" %}
10547 ins_encode %{
10548 __ orb($dst$$Address, $src$$Register);
10549 %}
10550 ins_pipe(ialu_mem_reg);
10551 %}
10552
10553 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10554 %{
10555 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
10556 effect(KILL cr);
10557 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10558
10559 ins_cost(150);
10560 format %{ "orl $dst, $src\t# int" %}
10561 ins_encode %{
10562 __ orl($dst$$Address, $src$$Register);
10563 %}
10564 ins_pipe(ialu_mem_reg);
10565 %}
10566
10567 // Or Memory with Immediate
10568 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
10569 %{
10570 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
10571 effect(KILL cr);
10572 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10573
10574 ins_cost(125);
10575 format %{ "orl $dst, $src\t# int" %}
10576 ins_encode %{
10577 __ orl($dst$$Address, $src$$constant);
10578 %}
10579 ins_pipe(ialu_mem_imm);
10580 %}
10581
10582 // Xor Instructions
10583 // Xor Register with Register
10584 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
10585 %{
10586 predicate(!UseAPX);
10587 match(Set dst (XorI dst src));
10588 effect(KILL cr);
10589 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10590
10591 format %{ "xorl $dst, $src\t# int" %}
10592 ins_encode %{
10593 __ xorl($dst$$Register, $src$$Register);
10594 %}
10595 ins_pipe(ialu_reg_reg);
10596 %}
10597
10598 // Xor Register with Register using New Data Destination (NDD)
10599 instruct xorI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
10600 %{
10601 predicate(UseAPX);
10602 match(Set dst (XorI src1 src2));
10603 effect(KILL cr);
10604 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10605
10606 format %{ "exorl $dst, $src1, $src2\t# int ndd" %}
10607 ins_encode %{
10608 __ exorl($dst$$Register, $src1$$Register, $src2$$Register, false);
10609 %}
10610 ins_pipe(ialu_reg_reg);
10611 %}
10612
10613 // Xor Register with Immediate -1
10614 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm)
10615 %{
10616 predicate(!UseAPX);
10617 match(Set dst (XorI dst imm));
10618
10619 format %{ "notl $dst" %}
10620 ins_encode %{
10621 __ notl($dst$$Register);
10622 %}
10623 ins_pipe(ialu_reg);
10624 %}
10625
10626 instruct xorI_rReg_im1_ndd(rRegI dst, rRegI src, immI_M1 imm)
10627 %{
10628 match(Set dst (XorI src imm));
10629 predicate(UseAPX);
10630
10631 format %{ "enotl $dst, $src" %}
10632 ins_encode %{
10633 __ enotl($dst$$Register, $src$$Register);
10634 %}
10635 ins_pipe(ialu_reg);
10636 %}
10637
10638 // Xor Register with Immediate
10639 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
10640 %{
10641 predicate(!UseAPX);
10642 match(Set dst (XorI dst src));
10643 effect(KILL cr);
10644 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10645
10646 format %{ "xorl $dst, $src\t# int" %}
10647 ins_encode %{
10648 __ xorl($dst$$Register, $src$$constant);
10649 %}
10650 ins_pipe(ialu_reg);
10651 %}
10652
10653 instruct xorI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
10654 %{
10655 predicate(UseAPX);
10656 match(Set dst (XorI src1 src2));
10657 effect(KILL cr);
10658 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10659
10660 format %{ "exorl $dst, $src1, $src2\t# int ndd" %}
10661 ins_encode %{
10662 __ exorl($dst$$Register, $src1$$Register, $src2$$constant, false);
10663 %}
10664 ins_pipe(ialu_reg);
10665 %}
10666
10667 // Xor Memory with Immediate
10668 instruct xorI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
10669 %{
10670 predicate(UseAPX);
10671 match(Set dst (XorI (LoadI src1) src2));
10672 effect(KILL cr);
10673 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10674
10675 format %{ "exorl $dst, $src1, $src2\t# int ndd" %}
10676 ins_encode %{
10677 __ exorl($dst$$Register, $src1$$Address, $src2$$constant, false);
10678 %}
10679 ins_pipe(ialu_reg);
10680 %}
10681
10682 // Xor Register with Memory
10683 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
10684 %{
10685 predicate(!UseAPX);
10686 match(Set dst (XorI dst (LoadI src)));
10687 effect(KILL cr);
10688 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10689
10690 ins_cost(150);
10691 format %{ "xorl $dst, $src\t# int" %}
10692 ins_encode %{
10693 __ xorl($dst$$Register, $src$$Address);
10694 %}
10695 ins_pipe(ialu_reg_mem);
10696 %}
10697
10698 instruct xorI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
10699 %{
10700 predicate(UseAPX);
10701 match(Set dst (XorI src1 (LoadI src2)));
10702 effect(KILL cr);
10703 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10704
10705 ins_cost(150);
10706 format %{ "exorl $dst, $src1, $src2\t# int ndd" %}
10707 ins_encode %{
10708 __ exorl($dst$$Register, $src1$$Register, $src2$$Address, false);
10709 %}
10710 ins_pipe(ialu_reg_mem);
10711 %}
10712
10713 instruct xorI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr)
10714 %{
10715 predicate(UseAPX);
10716 match(Set dst (XorI (LoadI src1) src2));
10717 effect(KILL cr);
10718 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10719
10720 ins_cost(150);
10721 format %{ "exorl $dst, $src1, $src2\t# int ndd" %}
10722 ins_encode %{
10723 __ exorl($dst$$Register, $src1$$Address, $src2$$Register, false);
10724 %}
10725 ins_pipe(ialu_reg_mem);
10726 %}
10727
10728 // Xor Memory with Register
10729 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10730 %{
10731 match(Set dst (StoreB dst (XorI (LoadB dst) src)));
10732 effect(KILL cr);
10733 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10734
10735 ins_cost(150);
10736 format %{ "xorb $dst, $src\t# byte" %}
10737 ins_encode %{
10738 __ xorb($dst$$Address, $src$$Register);
10739 %}
10740 ins_pipe(ialu_mem_reg);
10741 %}
10742
10743 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10744 %{
10745 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
10746 effect(KILL cr);
10747 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10748
10749 ins_cost(150);
10750 format %{ "xorl $dst, $src\t# int" %}
10751 ins_encode %{
10752 __ xorl($dst$$Address, $src$$Register);
10753 %}
10754 ins_pipe(ialu_mem_reg);
10755 %}
10756
10757 // Xor Memory with Immediate
10758 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
10759 %{
10760 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
10761 effect(KILL cr);
10762 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10763
10764 ins_cost(125);
10765 format %{ "xorl $dst, $src\t# int" %}
10766 ins_encode %{
10767 __ xorl($dst$$Address, $src$$constant);
10768 %}
10769 ins_pipe(ialu_mem_imm);
10770 %}
10771
10772
10773 // Long Logical Instructions
10774
10775 // And Instructions
10776 // And Register with Register
10777 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10778 %{
10779 predicate(!UseAPX);
10780 match(Set dst (AndL dst src));
10781 effect(KILL cr);
10782 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10783
10784 format %{ "andq $dst, $src\t# long" %}
10785 ins_encode %{
10786 __ andq($dst$$Register, $src$$Register);
10787 %}
10788 ins_pipe(ialu_reg_reg);
10789 %}
10790
10791 // And Register with Register using New Data Destination (NDD)
10792 instruct andL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
10793 %{
10794 predicate(UseAPX);
10795 match(Set dst (AndL src1 src2));
10796 effect(KILL cr);
10797 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10798
10799 format %{ "eandq $dst, $src1, $src2\t# long ndd" %}
10800 ins_encode %{
10801 __ eandq($dst$$Register, $src1$$Register, $src2$$Register, false);
10802
10803 %}
10804 ins_pipe(ialu_reg_reg);
10805 %}
10806
10807 // And Register with Immediate 255
10808 instruct andL_rReg_imm255(rRegL dst, rRegL src, immL_255 mask)
10809 %{
10810 match(Set dst (AndL src mask));
10811
10812 format %{ "movzbl $dst, $src\t# long & 0xFF" %}
10813 ins_encode %{
10814 // movzbl zeroes out the upper 32-bit and does not need REX.W
10815 __ movzbl($dst$$Register, $src$$Register);
10816 %}
10817 ins_pipe(ialu_reg);
10818 %}
10819
10820 // And Register with Immediate 65535
10821 instruct andL_rReg_imm65535(rRegL dst, rRegL src, immL_65535 mask)
10822 %{
10823 match(Set dst (AndL src mask));
10824
10825 format %{ "movzwl $dst, $src\t# long & 0xFFFF" %}
10826 ins_encode %{
10827 // movzwl zeroes out the upper 32-bit and does not need REX.W
10828 __ movzwl($dst$$Register, $src$$Register);
10829 %}
10830 ins_pipe(ialu_reg);
10831 %}
10832
10833 // And Register with Immediate
10834 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10835 %{
10836 predicate(!UseAPX);
10837 match(Set dst (AndL dst src));
10838 effect(KILL cr);
10839 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10840
10841 format %{ "andq $dst, $src\t# long" %}
10842 ins_encode %{
10843 __ andq($dst$$Register, $src$$constant);
10844 %}
10845 ins_pipe(ialu_reg);
10846 %}
10847
10848 instruct andL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
10849 %{
10850 predicate(UseAPX);
10851 match(Set dst (AndL src1 src2));
10852 effect(KILL cr);
10853 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10854
10855 format %{ "eandq $dst, $src1, $src2\t# long ndd" %}
10856 ins_encode %{
10857 __ eandq($dst$$Register, $src1$$Register, $src2$$constant, false);
10858 %}
10859 ins_pipe(ialu_reg);
10860 %}
10861
10862 instruct andL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
10863 %{
10864 predicate(UseAPX);
10865 match(Set dst (AndL (LoadL src1) src2));
10866 effect(KILL cr);
10867 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10868
10869 format %{ "eandq $dst, $src1, $src2\t# long ndd" %}
10870 ins_encode %{
10871 __ eandq($dst$$Register, $src1$$Address, $src2$$constant, false);
10872 %}
10873 ins_pipe(ialu_reg);
10874 %}
10875
10876 // And Register with Memory
10877 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10878 %{
10879 predicate(!UseAPX);
10880 match(Set dst (AndL dst (LoadL src)));
10881 effect(KILL cr);
10882 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10883
10884 ins_cost(150);
10885 format %{ "andq $dst, $src\t# long" %}
10886 ins_encode %{
10887 __ andq($dst$$Register, $src$$Address);
10888 %}
10889 ins_pipe(ialu_reg_mem);
10890 %}
10891
10892 instruct andL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
10893 %{
10894 predicate(UseAPX);
10895 match(Set dst (AndL src1 (LoadL src2)));
10896 effect(KILL cr);
10897 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10898
10899 ins_cost(150);
10900 format %{ "eandq $dst, $src1, $src2\t# long ndd" %}
10901 ins_encode %{
10902 __ eandq($dst$$Register, $src1$$Register, $src2$$Address, false);
10903 %}
10904 ins_pipe(ialu_reg_mem);
10905 %}
10906
10907 instruct andL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
10908 %{
10909 predicate(UseAPX);
10910 match(Set dst (AndL (LoadL src1) src2));
10911 effect(KILL cr);
10912 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10913
10914 ins_cost(150);
10915 format %{ "eandq $dst, $src1, $src2\t# long ndd" %}
10916 ins_encode %{
10917 __ eandq($dst$$Register, $src1$$Address, $src2$$Register, false);
10918 %}
10919 ins_pipe(ialu_reg_mem);
10920 %}
10921
10922 // And Memory with Register
10923 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10924 %{
10925 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
10926 effect(KILL cr);
10927 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10928
10929 ins_cost(150);
10930 format %{ "andq $dst, $src\t# long" %}
10931 ins_encode %{
10932 __ andq($dst$$Address, $src$$Register);
10933 %}
10934 ins_pipe(ialu_mem_reg);
10935 %}
10936
10937 // And Memory with Immediate
10938 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10939 %{
10940 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
10941 effect(KILL cr);
10942 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10943
10944 ins_cost(125);
10945 format %{ "andq $dst, $src\t# long" %}
10946 ins_encode %{
10947 __ andq($dst$$Address, $src$$constant);
10948 %}
10949 ins_pipe(ialu_mem_imm);
10950 %}
10951
10952 instruct btrL_mem_imm(memory dst, immL_NotPow2 con, rFlagsReg cr)
10953 %{
10954 // con should be a pure 64-bit immediate given that not(con) is a power of 2
10955 // because AND/OR works well enough for 8/32-bit values.
10956 predicate(log2i_graceful(~n->in(3)->in(2)->get_long()) > 30);
10957
10958 match(Set dst (StoreL dst (AndL (LoadL dst) con)));
10959 effect(KILL cr);
10960
10961 ins_cost(125);
10962 format %{ "btrq $dst, log2(not($con))\t# long" %}
10963 ins_encode %{
10964 __ btrq($dst$$Address, log2i_exact((julong)~$con$$constant));
10965 %}
10966 ins_pipe(ialu_mem_imm);
10967 %}
10968
10969 // BMI1 instructions
10970 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
10971 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
10972 predicate(UseBMI1Instructions);
10973 effect(KILL cr);
10974 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10975
10976 ins_cost(125);
10977 format %{ "andnq $dst, $src1, $src2" %}
10978
10979 ins_encode %{
10980 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
10981 %}
10982 ins_pipe(ialu_reg_mem);
10983 %}
10984
10985 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
10986 match(Set dst (AndL (XorL src1 minus_1) src2));
10987 predicate(UseBMI1Instructions);
10988 effect(KILL cr);
10989 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10990
10991 format %{ "andnq $dst, $src1, $src2" %}
10992
10993 ins_encode %{
10994 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
10995 %}
10996 ins_pipe(ialu_reg_mem);
10997 %}
10998
10999 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
11000 match(Set dst (AndL (SubL imm_zero src) src));
11001 predicate(UseBMI1Instructions);
11002 effect(KILL cr);
11003 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
11004
11005 format %{ "blsiq $dst, $src" %}
11006
11007 ins_encode %{
11008 __ blsiq($dst$$Register, $src$$Register);
11009 %}
11010 ins_pipe(ialu_reg);
11011 %}
11012
11013 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
11014 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
11015 predicate(UseBMI1Instructions);
11016 effect(KILL cr);
11017 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
11018
11019 ins_cost(125);
11020 format %{ "blsiq $dst, $src" %}
11021
11022 ins_encode %{
11023 __ blsiq($dst$$Register, $src$$Address);
11024 %}
11025 ins_pipe(ialu_reg_mem);
11026 %}
11027
11028 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
11029 %{
11030 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
11031 predicate(UseBMI1Instructions);
11032 effect(KILL cr);
11033 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
11034
11035 ins_cost(125);
11036 format %{ "blsmskq $dst, $src" %}
11037
11038 ins_encode %{
11039 __ blsmskq($dst$$Register, $src$$Address);
11040 %}
11041 ins_pipe(ialu_reg_mem);
11042 %}
11043
11044 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
11045 %{
11046 match(Set dst (XorL (AddL src minus_1) src));
11047 predicate(UseBMI1Instructions);
11048 effect(KILL cr);
11049 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
11050
11051 format %{ "blsmskq $dst, $src" %}
11052
11053 ins_encode %{
11054 __ blsmskq($dst$$Register, $src$$Register);
11055 %}
11056
11057 ins_pipe(ialu_reg);
11058 %}
11059
11060 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
11061 %{
11062 match(Set dst (AndL (AddL src minus_1) src) );
11063 predicate(UseBMI1Instructions);
11064 effect(KILL cr);
11065 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
11066
11067 format %{ "blsrq $dst, $src" %}
11068
11069 ins_encode %{
11070 __ blsrq($dst$$Register, $src$$Register);
11071 %}
11072
11073 ins_pipe(ialu_reg);
11074 %}
11075
11076 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
11077 %{
11078 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
11079 predicate(UseBMI1Instructions);
11080 effect(KILL cr);
11081 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
11082
11083 ins_cost(125);
11084 format %{ "blsrq $dst, $src" %}
11085
11086 ins_encode %{
11087 __ blsrq($dst$$Register, $src$$Address);
11088 %}
11089
11090 ins_pipe(ialu_reg);
11091 %}
11092
11093 // Or Instructions
11094 // Or Register with Register
11095 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
11096 %{
11097 predicate(!UseAPX);
11098 match(Set dst (OrL dst src));
11099 effect(KILL cr);
11100 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11101
11102 format %{ "orq $dst, $src\t# long" %}
11103 ins_encode %{
11104 __ orq($dst$$Register, $src$$Register);
11105 %}
11106 ins_pipe(ialu_reg_reg);
11107 %}
11108
11109 // Or Register with Register using New Data Destination (NDD)
11110 instruct orL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
11111 %{
11112 predicate(UseAPX);
11113 match(Set dst (OrL src1 src2));
11114 effect(KILL cr);
11115 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11116
11117 format %{ "eorq $dst, $src1, $src2\t# long ndd" %}
11118 ins_encode %{
11119 __ eorq($dst$$Register, $src1$$Register, $src2$$Register, false);
11120
11121 %}
11122 ins_pipe(ialu_reg_reg);
11123 %}
11124
11125 // Use any_RegP to match R15 (TLS register) without spilling.
11126 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
11127 match(Set dst (OrL dst (CastP2X src)));
11128 effect(KILL cr);
11129 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11130
11131 format %{ "orq $dst, $src\t# long" %}
11132 ins_encode %{
11133 __ orq($dst$$Register, $src$$Register);
11134 %}
11135 ins_pipe(ialu_reg_reg);
11136 %}
11137
11138 instruct orL_rReg_castP2X_ndd(rRegL dst, any_RegP src1, any_RegP src2, rFlagsReg cr) %{
11139 match(Set dst (OrL src1 (CastP2X src2)));
11140 effect(KILL cr);
11141 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11142
11143 format %{ "eorq $dst, $src1, $src2\t# long ndd" %}
11144 ins_encode %{
11145 __ eorq($dst$$Register, $src1$$Register, $src2$$Register, false);
11146 %}
11147 ins_pipe(ialu_reg_reg);
11148 %}
11149
11150 // Or Register with Immediate
11151 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
11152 %{
11153 predicate(!UseAPX);
11154 match(Set dst (OrL dst src));
11155 effect(KILL cr);
11156 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11157
11158 format %{ "orq $dst, $src\t# long" %}
11159 ins_encode %{
11160 __ orq($dst$$Register, $src$$constant);
11161 %}
11162 ins_pipe(ialu_reg);
11163 %}
11164
11165 instruct orL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
11166 %{
11167 predicate(UseAPX);
11168 match(Set dst (OrL src1 src2));
11169 effect(KILL cr);
11170 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11171
11172 format %{ "eorq $dst, $src1, $src2\t# long ndd" %}
11173 ins_encode %{
11174 __ eorq($dst$$Register, $src1$$Register, $src2$$constant, false);
11175 %}
11176 ins_pipe(ialu_reg);
11177 %}
11178
11179 instruct orL_rReg_imm_rReg_ndd(rRegL dst, immL32 src1, rRegL src2, rFlagsReg cr)
11180 %{
11181 predicate(UseAPX);
11182 match(Set dst (OrL src1 src2));
11183 effect(KILL cr);
11184 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11185
11186 format %{ "eorq $dst, $src2, $src1\t# long ndd" %}
11187 ins_encode %{
11188 __ eorq($dst$$Register, $src2$$Register, $src1$$constant, false);
11189 %}
11190 ins_pipe(ialu_reg);
11191 %}
11192
11193 // Or Memory with Immediate
11194 instruct orL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
11195 %{
11196 predicate(UseAPX);
11197 match(Set dst (OrL (LoadL src1) src2));
11198 effect(KILL cr);
11199 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11200
11201 format %{ "eorq $dst, $src1, $src2\t# long ndd" %}
11202 ins_encode %{
11203 __ eorq($dst$$Register, $src1$$Address, $src2$$constant, false);
11204 %}
11205 ins_pipe(ialu_reg);
11206 %}
11207
11208 // Or Register with Memory
11209 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
11210 %{
11211 predicate(!UseAPX);
11212 match(Set dst (OrL dst (LoadL src)));
11213 effect(KILL cr);
11214 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11215
11216 ins_cost(150);
11217 format %{ "orq $dst, $src\t# long" %}
11218 ins_encode %{
11219 __ orq($dst$$Register, $src$$Address);
11220 %}
11221 ins_pipe(ialu_reg_mem);
11222 %}
11223
11224 instruct orL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
11225 %{
11226 predicate(UseAPX);
11227 match(Set dst (OrL src1 (LoadL src2)));
11228 effect(KILL cr);
11229 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11230
11231 ins_cost(150);
11232 format %{ "eorq $dst, $src1, $src2\t# long ndd" %}
11233 ins_encode %{
11234 __ eorq($dst$$Register, $src1$$Register, $src2$$Address, false);
11235 %}
11236 ins_pipe(ialu_reg_mem);
11237 %}
11238
11239 // Or Memory with Register
11240 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
11241 %{
11242 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
11243 effect(KILL cr);
11244 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11245
11246 ins_cost(150);
11247 format %{ "orq $dst, $src\t# long" %}
11248 ins_encode %{
11249 __ orq($dst$$Address, $src$$Register);
11250 %}
11251 ins_pipe(ialu_mem_reg);
11252 %}
11253
11254 // Or Memory with Immediate
11255 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
11256 %{
11257 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
11258 effect(KILL cr);
11259 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11260
11261 ins_cost(125);
11262 format %{ "orq $dst, $src\t# long" %}
11263 ins_encode %{
11264 __ orq($dst$$Address, $src$$constant);
11265 %}
11266 ins_pipe(ialu_mem_imm);
11267 %}
11268
11269 instruct btsL_mem_imm(memory dst, immL_Pow2 con, rFlagsReg cr)
11270 %{
11271 // con should be a pure 64-bit power of 2 immediate
11272 // because AND/OR works well enough for 8/32-bit values.
11273 predicate(log2i_graceful(n->in(3)->in(2)->get_long()) > 31);
11274
11275 match(Set dst (StoreL dst (OrL (LoadL dst) con)));
11276 effect(KILL cr);
11277
11278 ins_cost(125);
11279 format %{ "btsq $dst, log2($con)\t# long" %}
11280 ins_encode %{
11281 __ btsq($dst$$Address, log2i_exact((julong)$con$$constant));
11282 %}
11283 ins_pipe(ialu_mem_imm);
11284 %}
11285
11286 // Xor Instructions
11287 // Xor Register with Register
11288 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
11289 %{
11290 predicate(!UseAPX);
11291 match(Set dst (XorL dst src));
11292 effect(KILL cr);
11293 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11294
11295 format %{ "xorq $dst, $src\t# long" %}
11296 ins_encode %{
11297 __ xorq($dst$$Register, $src$$Register);
11298 %}
11299 ins_pipe(ialu_reg_reg);
11300 %}
11301
11302 // Xor Register with Register using New Data Destination (NDD)
11303 instruct xorL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
11304 %{
11305 predicate(UseAPX);
11306 match(Set dst (XorL src1 src2));
11307 effect(KILL cr);
11308 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11309
11310 format %{ "exorq $dst, $src1, $src2\t# long ndd" %}
11311 ins_encode %{
11312 __ exorq($dst$$Register, $src1$$Register, $src2$$Register, false);
11313 %}
11314 ins_pipe(ialu_reg_reg);
11315 %}
11316
11317 // Xor Register with Immediate -1
11318 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm)
11319 %{
11320 predicate(!UseAPX);
11321 match(Set dst (XorL dst imm));
11322
11323 format %{ "notq $dst" %}
11324 ins_encode %{
11325 __ notq($dst$$Register);
11326 %}
11327 ins_pipe(ialu_reg);
11328 %}
11329
11330 instruct xorL_rReg_im1_ndd(rRegL dst,rRegL src, immL_M1 imm)
11331 %{
11332 predicate(UseAPX);
11333 match(Set dst (XorL src imm));
11334
11335 format %{ "enotq $dst, $src" %}
11336 ins_encode %{
11337 __ enotq($dst$$Register, $src$$Register);
11338 %}
11339 ins_pipe(ialu_reg);
11340 %}
11341
11342 // Xor Register with Immediate
11343 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
11344 %{
11345 predicate(!UseAPX);
11346 match(Set dst (XorL dst src));
11347 effect(KILL cr);
11348 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11349
11350 format %{ "xorq $dst, $src\t# long" %}
11351 ins_encode %{
11352 __ xorq($dst$$Register, $src$$constant);
11353 %}
11354 ins_pipe(ialu_reg);
11355 %}
11356
11357 instruct xorL_rReg_rReg_imm(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
11358 %{
11359 predicate(UseAPX);
11360 match(Set dst (XorL src1 src2));
11361 effect(KILL cr);
11362 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11363
11364 format %{ "exorq $dst, $src1, $src2\t# long ndd" %}
11365 ins_encode %{
11366 __ exorq($dst$$Register, $src1$$Register, $src2$$constant, false);
11367 %}
11368 ins_pipe(ialu_reg);
11369 %}
11370
11371 // Xor Memory with Immediate
11372 instruct xorL_rReg_mem_imm(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
11373 %{
11374 predicate(UseAPX);
11375 match(Set dst (XorL (LoadL src1) src2));
11376 effect(KILL cr);
11377 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11378
11379 format %{ "exorq $dst, $src1, $src2\t# long ndd" %}
11380 ins_encode %{
11381 __ exorq($dst$$Register, $src1$$Address, $src2$$constant, false);
11382 %}
11383 ins_pipe(ialu_reg);
11384 %}
11385
11386 // Xor Register with Memory
11387 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
11388 %{
11389 predicate(!UseAPX);
11390 match(Set dst (XorL dst (LoadL src)));
11391 effect(KILL cr);
11392 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11393
11394 ins_cost(150);
11395 format %{ "xorq $dst, $src\t# long" %}
11396 ins_encode %{
11397 __ xorq($dst$$Register, $src$$Address);
11398 %}
11399 ins_pipe(ialu_reg_mem);
11400 %}
11401
11402 instruct xorL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
11403 %{
11404 predicate(UseAPX);
11405 match(Set dst (XorL src1 (LoadL src2)));
11406 effect(KILL cr);
11407 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11408
11409 ins_cost(150);
11410 format %{ "exorq $dst, $src1, $src2\t# long ndd" %}
11411 ins_encode %{
11412 __ exorq($dst$$Register, $src1$$Register, $src2$$Address, false);
11413 %}
11414 ins_pipe(ialu_reg_mem);
11415 %}
11416
11417 instruct xorL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
11418 %{
11419 predicate(UseAPX);
11420 match(Set dst (XorL (LoadL src1) src2));
11421 effect(KILL cr);
11422 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11423
11424 ins_cost(150);
11425 format %{ "exorq $dst, $src1, $src2\t# long ndd" %}
11426 ins_encode %{
11427 __ exorq($dst$$Register, $src1$$Address, $src2$$Register, false);
11428 %}
11429 ins_pipe(ialu_reg_mem);
11430 %}
11431
11432 // Xor Memory with Register
11433 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
11434 %{
11435 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
11436 effect(KILL cr);
11437 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11438
11439 ins_cost(150);
11440 format %{ "xorq $dst, $src\t# long" %}
11441 ins_encode %{
11442 __ xorq($dst$$Address, $src$$Register);
11443 %}
11444 ins_pipe(ialu_mem_reg);
11445 %}
11446
11447 // Xor Memory with Immediate
11448 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
11449 %{
11450 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
11451 effect(KILL cr);
11452 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11453
11454 ins_cost(125);
11455 format %{ "xorq $dst, $src\t# long" %}
11456 ins_encode %{
11457 __ xorq($dst$$Address, $src$$constant);
11458 %}
11459 ins_pipe(ialu_mem_imm);
11460 %}
11461
11462 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
11463 %{
11464 match(Set dst (CmpLTMask p q));
11465 effect(KILL cr);
11466
11467 ins_cost(400);
11468 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
11469 "setcc $dst \t# emits setlt + movzbl or setzul for APX"
11470 "negl $dst" %}
11471 ins_encode %{
11472 __ cmpl($p$$Register, $q$$Register);
11473 __ setcc(Assembler::less, $dst$$Register);
11474 __ negl($dst$$Register);
11475 %}
11476 ins_pipe(pipe_slow);
11477 %}
11478
11479 instruct cmpLTMask0(rRegI dst, immI_0 zero, rFlagsReg cr)
11480 %{
11481 match(Set dst (CmpLTMask dst zero));
11482 effect(KILL cr);
11483
11484 ins_cost(100);
11485 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
11486 ins_encode %{
11487 __ sarl($dst$$Register, 31);
11488 %}
11489 ins_pipe(ialu_reg);
11490 %}
11491
11492 /* Better to save a register than avoid a branch */
11493 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
11494 %{
11495 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
11496 effect(KILL cr);
11497 ins_cost(300);
11498 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
11499 "jge done\n\t"
11500 "addl $p,$y\n"
11501 "done: " %}
11502 ins_encode %{
11503 Register Rp = $p$$Register;
11504 Register Rq = $q$$Register;
11505 Register Ry = $y$$Register;
11506 Label done;
11507 __ subl(Rp, Rq);
11508 __ jccb(Assembler::greaterEqual, done);
11509 __ addl(Rp, Ry);
11510 __ bind(done);
11511 %}
11512 ins_pipe(pipe_cmplt);
11513 %}
11514
11515 /* Better to save a register than avoid a branch */
11516 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
11517 %{
11518 match(Set y (AndI (CmpLTMask p q) y));
11519 effect(KILL cr);
11520
11521 ins_cost(300);
11522
11523 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
11524 "jlt done\n\t"
11525 "xorl $y, $y\n"
11526 "done: " %}
11527 ins_encode %{
11528 Register Rp = $p$$Register;
11529 Register Rq = $q$$Register;
11530 Register Ry = $y$$Register;
11531 Label done;
11532 __ cmpl(Rp, Rq);
11533 __ jccb(Assembler::less, done);
11534 __ xorl(Ry, Ry);
11535 __ bind(done);
11536 %}
11537 ins_pipe(pipe_cmplt);
11538 %}
11539
11540
11541 //---------- FP Instructions------------------------------------------------
11542
11543 // Really expensive, avoid
11544 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
11545 %{
11546 match(Set cr (CmpF src1 src2));
11547
11548 ins_cost(500);
11549 format %{ "ucomiss $src1, $src2\n\t"
11550 "jnp,s exit\n\t"
11551 "pushfq\t# saw NaN, set CF\n\t"
11552 "andq [rsp], #0xffffff2b\n\t"
11553 "popfq\n"
11554 "exit:" %}
11555 ins_encode %{
11556 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
11557 emit_cmpfp_fixup(masm);
11558 %}
11559 ins_pipe(pipe_slow);
11560 %}
11561
11562 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
11563 match(Set cr (CmpF src1 src2));
11564
11565 ins_cost(100);
11566 format %{ "ucomiss $src1, $src2" %}
11567 ins_encode %{
11568 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
11569 %}
11570 ins_pipe(pipe_slow);
11571 %}
11572
11573 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
11574 match(Set cr (CmpF src1 (LoadF src2)));
11575
11576 ins_cost(100);
11577 format %{ "ucomiss $src1, $src2" %}
11578 ins_encode %{
11579 __ ucomiss($src1$$XMMRegister, $src2$$Address);
11580 %}
11581 ins_pipe(pipe_slow);
11582 %}
11583
11584 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
11585 match(Set cr (CmpF src con));
11586 ins_cost(100);
11587 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
11588 ins_encode %{
11589 __ ucomiss($src$$XMMRegister, $constantaddress($con));
11590 %}
11591 ins_pipe(pipe_slow);
11592 %}
11593
11594 // Really expensive, avoid
11595 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
11596 %{
11597 match(Set cr (CmpD src1 src2));
11598
11599 ins_cost(500);
11600 format %{ "ucomisd $src1, $src2\n\t"
11601 "jnp,s exit\n\t"
11602 "pushfq\t# saw NaN, set CF\n\t"
11603 "andq [rsp], #0xffffff2b\n\t"
11604 "popfq\n"
11605 "exit:" %}
11606 ins_encode %{
11607 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
11608 emit_cmpfp_fixup(masm);
11609 %}
11610 ins_pipe(pipe_slow);
11611 %}
11612
11613 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
11614 match(Set cr (CmpD src1 src2));
11615
11616 ins_cost(100);
11617 format %{ "ucomisd $src1, $src2 test" %}
11618 ins_encode %{
11619 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
11620 %}
11621 ins_pipe(pipe_slow);
11622 %}
11623
11624 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
11625 match(Set cr (CmpD src1 (LoadD src2)));
11626
11627 ins_cost(100);
11628 format %{ "ucomisd $src1, $src2" %}
11629 ins_encode %{
11630 __ ucomisd($src1$$XMMRegister, $src2$$Address);
11631 %}
11632 ins_pipe(pipe_slow);
11633 %}
11634
11635 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
11636 match(Set cr (CmpD src con));
11637 ins_cost(100);
11638 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
11639 ins_encode %{
11640 __ ucomisd($src$$XMMRegister, $constantaddress($con));
11641 %}
11642 ins_pipe(pipe_slow);
11643 %}
11644
11645 // Compare into -1,0,1
11646 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
11647 %{
11648 match(Set dst (CmpF3 src1 src2));
11649 effect(KILL cr);
11650
11651 ins_cost(275);
11652 format %{ "ucomiss $src1, $src2\n\t"
11653 "movl $dst, #-1\n\t"
11654 "jp,s done\n\t"
11655 "jb,s done\n\t"
11656 "setne $dst\n\t"
11657 "movzbl $dst, $dst\n"
11658 "done:" %}
11659 ins_encode %{
11660 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
11661 emit_cmpfp3(masm, $dst$$Register);
11662 %}
11663 ins_pipe(pipe_slow);
11664 %}
11665
11666 // Compare into -1,0,1
11667 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
11668 %{
11669 match(Set dst (CmpF3 src1 (LoadF src2)));
11670 effect(KILL cr);
11671
11672 ins_cost(275);
11673 format %{ "ucomiss $src1, $src2\n\t"
11674 "movl $dst, #-1\n\t"
11675 "jp,s done\n\t"
11676 "jb,s done\n\t"
11677 "setne $dst\n\t"
11678 "movzbl $dst, $dst\n"
11679 "done:" %}
11680 ins_encode %{
11681 __ ucomiss($src1$$XMMRegister, $src2$$Address);
11682 emit_cmpfp3(masm, $dst$$Register);
11683 %}
11684 ins_pipe(pipe_slow);
11685 %}
11686
11687 // Compare into -1,0,1
11688 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
11689 match(Set dst (CmpF3 src con));
11690 effect(KILL cr);
11691
11692 ins_cost(275);
11693 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
11694 "movl $dst, #-1\n\t"
11695 "jp,s done\n\t"
11696 "jb,s done\n\t"
11697 "setne $dst\n\t"
11698 "movzbl $dst, $dst\n"
11699 "done:" %}
11700 ins_encode %{
11701 __ ucomiss($src$$XMMRegister, $constantaddress($con));
11702 emit_cmpfp3(masm, $dst$$Register);
11703 %}
11704 ins_pipe(pipe_slow);
11705 %}
11706
11707 // Compare into -1,0,1
11708 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
11709 %{
11710 match(Set dst (CmpD3 src1 src2));
11711 effect(KILL cr);
11712
11713 ins_cost(275);
11714 format %{ "ucomisd $src1, $src2\n\t"
11715 "movl $dst, #-1\n\t"
11716 "jp,s done\n\t"
11717 "jb,s done\n\t"
11718 "setne $dst\n\t"
11719 "movzbl $dst, $dst\n"
11720 "done:" %}
11721 ins_encode %{
11722 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
11723 emit_cmpfp3(masm, $dst$$Register);
11724 %}
11725 ins_pipe(pipe_slow);
11726 %}
11727
11728 // Compare into -1,0,1
11729 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
11730 %{
11731 match(Set dst (CmpD3 src1 (LoadD src2)));
11732 effect(KILL cr);
11733
11734 ins_cost(275);
11735 format %{ "ucomisd $src1, $src2\n\t"
11736 "movl $dst, #-1\n\t"
11737 "jp,s done\n\t"
11738 "jb,s done\n\t"
11739 "setne $dst\n\t"
11740 "movzbl $dst, $dst\n"
11741 "done:" %}
11742 ins_encode %{
11743 __ ucomisd($src1$$XMMRegister, $src2$$Address);
11744 emit_cmpfp3(masm, $dst$$Register);
11745 %}
11746 ins_pipe(pipe_slow);
11747 %}
11748
11749 // Compare into -1,0,1
11750 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
11751 match(Set dst (CmpD3 src con));
11752 effect(KILL cr);
11753
11754 ins_cost(275);
11755 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
11756 "movl $dst, #-1\n\t"
11757 "jp,s done\n\t"
11758 "jb,s done\n\t"
11759 "setne $dst\n\t"
11760 "movzbl $dst, $dst\n"
11761 "done:" %}
11762 ins_encode %{
11763 __ ucomisd($src$$XMMRegister, $constantaddress($con));
11764 emit_cmpfp3(masm, $dst$$Register);
11765 %}
11766 ins_pipe(pipe_slow);
11767 %}
11768
11769 //----------Arithmetic Conversion Instructions---------------------------------
11770
11771 instruct convF2D_reg_reg(regD dst, regF src)
11772 %{
11773 match(Set dst (ConvF2D src));
11774
11775 format %{ "cvtss2sd $dst, $src" %}
11776 ins_encode %{
11777 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
11778 %}
11779 ins_pipe(pipe_slow); // XXX
11780 %}
11781
11782 instruct convF2D_reg_mem(regD dst, memory src)
11783 %{
11784 predicate(UseAVX == 0);
11785 match(Set dst (ConvF2D (LoadF src)));
11786
11787 format %{ "cvtss2sd $dst, $src" %}
11788 ins_encode %{
11789 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
11790 %}
11791 ins_pipe(pipe_slow); // XXX
11792 %}
11793
11794 instruct convD2F_reg_reg(regF dst, regD src)
11795 %{
11796 match(Set dst (ConvD2F src));
11797
11798 format %{ "cvtsd2ss $dst, $src" %}
11799 ins_encode %{
11800 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
11801 %}
11802 ins_pipe(pipe_slow); // XXX
11803 %}
11804
11805 instruct convD2F_reg_mem(regF dst, memory src)
11806 %{
11807 predicate(UseAVX == 0);
11808 match(Set dst (ConvD2F (LoadD src)));
11809
11810 format %{ "cvtsd2ss $dst, $src" %}
11811 ins_encode %{
11812 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
11813 %}
11814 ins_pipe(pipe_slow); // XXX
11815 %}
11816
11817 // XXX do mem variants
11818 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
11819 %{
11820 match(Set dst (ConvF2I src));
11821 effect(KILL cr);
11822 format %{ "convert_f2i $dst, $src" %}
11823 ins_encode %{
11824 __ convertF2I(T_INT, T_FLOAT, $dst$$Register, $src$$XMMRegister);
11825 %}
11826 ins_pipe(pipe_slow);
11827 %}
11828
11829 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
11830 %{
11831 match(Set dst (ConvF2L src));
11832 effect(KILL cr);
11833 format %{ "convert_f2l $dst, $src"%}
11834 ins_encode %{
11835 __ convertF2I(T_LONG, T_FLOAT, $dst$$Register, $src$$XMMRegister);
11836 %}
11837 ins_pipe(pipe_slow);
11838 %}
11839
11840 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
11841 %{
11842 match(Set dst (ConvD2I src));
11843 effect(KILL cr);
11844 format %{ "convert_d2i $dst, $src"%}
11845 ins_encode %{
11846 __ convertF2I(T_INT, T_DOUBLE, $dst$$Register, $src$$XMMRegister);
11847 %}
11848 ins_pipe(pipe_slow);
11849 %}
11850
11851 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
11852 %{
11853 match(Set dst (ConvD2L src));
11854 effect(KILL cr);
11855 format %{ "convert_d2l $dst, $src"%}
11856 ins_encode %{
11857 __ convertF2I(T_LONG, T_DOUBLE, $dst$$Register, $src$$XMMRegister);
11858 %}
11859 ins_pipe(pipe_slow);
11860 %}
11861
11862 instruct round_double_reg(rRegL dst, regD src, rRegL rtmp, rcx_RegL rcx, rFlagsReg cr)
11863 %{
11864 match(Set dst (RoundD src));
11865 effect(TEMP dst, TEMP rtmp, TEMP rcx, KILL cr);
11866 format %{ "round_double $dst,$src \t! using $rtmp and $rcx as TEMP"%}
11867 ins_encode %{
11868 __ round_double($dst$$Register, $src$$XMMRegister, $rtmp$$Register, $rcx$$Register);
11869 %}
11870 ins_pipe(pipe_slow);
11871 %}
11872
11873 instruct round_float_reg(rRegI dst, regF src, rRegL rtmp, rcx_RegL rcx, rFlagsReg cr)
11874 %{
11875 match(Set dst (RoundF src));
11876 effect(TEMP dst, TEMP rtmp, TEMP rcx, KILL cr);
11877 format %{ "round_float $dst,$src" %}
11878 ins_encode %{
11879 __ round_float($dst$$Register, $src$$XMMRegister, $rtmp$$Register, $rcx$$Register);
11880 %}
11881 ins_pipe(pipe_slow);
11882 %}
11883
11884 instruct convI2F_reg_reg(vlRegF dst, rRegI src)
11885 %{
11886 predicate(!UseXmmI2F);
11887 match(Set dst (ConvI2F src));
11888
11889 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
11890 ins_encode %{
11891 if (UseAVX > 0) {
11892 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11893 }
11894 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11895 %}
11896 ins_pipe(pipe_slow); // XXX
11897 %}
11898
11899 instruct convI2F_reg_mem(regF dst, memory src)
11900 %{
11901 predicate(UseAVX == 0);
11902 match(Set dst (ConvI2F (LoadI src)));
11903
11904 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
11905 ins_encode %{
11906 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
11907 %}
11908 ins_pipe(pipe_slow); // XXX
11909 %}
11910
11911 instruct convI2D_reg_reg(vlRegD dst, rRegI src)
11912 %{
11913 predicate(!UseXmmI2D);
11914 match(Set dst (ConvI2D src));
11915
11916 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
11917 ins_encode %{
11918 if (UseAVX > 0) {
11919 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11920 }
11921 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11922 %}
11923 ins_pipe(pipe_slow); // XXX
11924 %}
11925
11926 instruct convI2D_reg_mem(regD dst, memory src)
11927 %{
11928 predicate(UseAVX == 0);
11929 match(Set dst (ConvI2D (LoadI src)));
11930
11931 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
11932 ins_encode %{
11933 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
11934 %}
11935 ins_pipe(pipe_slow); // XXX
11936 %}
11937
11938 instruct convXI2F_reg(regF dst, rRegI src)
11939 %{
11940 predicate(UseXmmI2F);
11941 match(Set dst (ConvI2F src));
11942
11943 format %{ "movdl $dst, $src\n\t"
11944 "cvtdq2psl $dst, $dst\t# i2f" %}
11945 ins_encode %{
11946 __ movdl($dst$$XMMRegister, $src$$Register);
11947 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11948 %}
11949 ins_pipe(pipe_slow); // XXX
11950 %}
11951
11952 instruct convXI2D_reg(regD dst, rRegI src)
11953 %{
11954 predicate(UseXmmI2D);
11955 match(Set dst (ConvI2D src));
11956
11957 format %{ "movdl $dst, $src\n\t"
11958 "cvtdq2pdl $dst, $dst\t# i2d" %}
11959 ins_encode %{
11960 __ movdl($dst$$XMMRegister, $src$$Register);
11961 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11962 %}
11963 ins_pipe(pipe_slow); // XXX
11964 %}
11965
11966 instruct convL2F_reg_reg(vlRegF dst, rRegL src)
11967 %{
11968 match(Set dst (ConvL2F src));
11969
11970 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
11971 ins_encode %{
11972 if (UseAVX > 0) {
11973 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11974 }
11975 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
11976 %}
11977 ins_pipe(pipe_slow); // XXX
11978 %}
11979
11980 instruct convL2F_reg_mem(regF dst, memory src)
11981 %{
11982 predicate(UseAVX == 0);
11983 match(Set dst (ConvL2F (LoadL src)));
11984
11985 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
11986 ins_encode %{
11987 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
11988 %}
11989 ins_pipe(pipe_slow); // XXX
11990 %}
11991
11992 instruct convL2D_reg_reg(vlRegD dst, rRegL src)
11993 %{
11994 match(Set dst (ConvL2D src));
11995
11996 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
11997 ins_encode %{
11998 if (UseAVX > 0) {
11999 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
12000 }
12001 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
12002 %}
12003 ins_pipe(pipe_slow); // XXX
12004 %}
12005
12006 instruct convL2D_reg_mem(regD dst, memory src)
12007 %{
12008 predicate(UseAVX == 0);
12009 match(Set dst (ConvL2D (LoadL src)));
12010
12011 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
12012 ins_encode %{
12013 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
12014 %}
12015 ins_pipe(pipe_slow); // XXX
12016 %}
12017
12018 instruct convI2L_reg_reg(rRegL dst, rRegI src)
12019 %{
12020 match(Set dst (ConvI2L src));
12021
12022 ins_cost(125);
12023 format %{ "movslq $dst, $src\t# i2l" %}
12024 ins_encode %{
12025 __ movslq($dst$$Register, $src$$Register);
12026 %}
12027 ins_pipe(ialu_reg_reg);
12028 %}
12029
12030 // Zero-extend convert int to long
12031 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
12032 %{
12033 match(Set dst (AndL (ConvI2L src) mask));
12034
12035 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
12036 ins_encode %{
12037 if ($dst$$reg != $src$$reg) {
12038 __ movl($dst$$Register, $src$$Register);
12039 }
12040 %}
12041 ins_pipe(ialu_reg_reg);
12042 %}
12043
12044 // Zero-extend convert int to long
12045 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
12046 %{
12047 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
12048
12049 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
12050 ins_encode %{
12051 __ movl($dst$$Register, $src$$Address);
12052 %}
12053 ins_pipe(ialu_reg_mem);
12054 %}
12055
12056 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
12057 %{
12058 match(Set dst (AndL src mask));
12059
12060 format %{ "movl $dst, $src\t# zero-extend long" %}
12061 ins_encode %{
12062 __ movl($dst$$Register, $src$$Register);
12063 %}
12064 ins_pipe(ialu_reg_reg);
12065 %}
12066
12067 instruct convL2I_reg_reg(rRegI dst, rRegL src)
12068 %{
12069 match(Set dst (ConvL2I src));
12070
12071 format %{ "movl $dst, $src\t# l2i" %}
12072 ins_encode %{
12073 __ movl($dst$$Register, $src$$Register);
12074 %}
12075 ins_pipe(ialu_reg_reg);
12076 %}
12077
12078
12079 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
12080 match(Set dst (MoveF2I src));
12081 effect(DEF dst, USE src);
12082
12083 ins_cost(125);
12084 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
12085 ins_encode %{
12086 __ movl($dst$$Register, Address(rsp, $src$$disp));
12087 %}
12088 ins_pipe(ialu_reg_mem);
12089 %}
12090
12091 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
12092 match(Set dst (MoveI2F src));
12093 effect(DEF dst, USE src);
12094
12095 ins_cost(125);
12096 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
12097 ins_encode %{
12098 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
12099 %}
12100 ins_pipe(pipe_slow);
12101 %}
12102
12103 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
12104 match(Set dst (MoveD2L src));
12105 effect(DEF dst, USE src);
12106
12107 ins_cost(125);
12108 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
12109 ins_encode %{
12110 __ movq($dst$$Register, Address(rsp, $src$$disp));
12111 %}
12112 ins_pipe(ialu_reg_mem);
12113 %}
12114
12115 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
12116 predicate(!UseXmmLoadAndClearUpper);
12117 match(Set dst (MoveL2D src));
12118 effect(DEF dst, USE src);
12119
12120 ins_cost(125);
12121 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
12122 ins_encode %{
12123 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
12124 %}
12125 ins_pipe(pipe_slow);
12126 %}
12127
12128 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
12129 predicate(UseXmmLoadAndClearUpper);
12130 match(Set dst (MoveL2D src));
12131 effect(DEF dst, USE src);
12132
12133 ins_cost(125);
12134 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
12135 ins_encode %{
12136 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
12137 %}
12138 ins_pipe(pipe_slow);
12139 %}
12140
12141
12142 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
12143 match(Set dst (MoveF2I src));
12144 effect(DEF dst, USE src);
12145
12146 ins_cost(95); // XXX
12147 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
12148 ins_encode %{
12149 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
12150 %}
12151 ins_pipe(pipe_slow);
12152 %}
12153
12154 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
12155 match(Set dst (MoveI2F src));
12156 effect(DEF dst, USE src);
12157
12158 ins_cost(100);
12159 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
12160 ins_encode %{
12161 __ movl(Address(rsp, $dst$$disp), $src$$Register);
12162 %}
12163 ins_pipe( ialu_mem_reg );
12164 %}
12165
12166 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
12167 match(Set dst (MoveD2L src));
12168 effect(DEF dst, USE src);
12169
12170 ins_cost(95); // XXX
12171 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
12172 ins_encode %{
12173 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
12174 %}
12175 ins_pipe(pipe_slow);
12176 %}
12177
12178 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
12179 match(Set dst (MoveL2D src));
12180 effect(DEF dst, USE src);
12181
12182 ins_cost(100);
12183 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
12184 ins_encode %{
12185 __ movq(Address(rsp, $dst$$disp), $src$$Register);
12186 %}
12187 ins_pipe(ialu_mem_reg);
12188 %}
12189
12190 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
12191 match(Set dst (MoveF2I src));
12192 effect(DEF dst, USE src);
12193 ins_cost(85);
12194 format %{ "movd $dst,$src\t# MoveF2I" %}
12195 ins_encode %{
12196 __ movdl($dst$$Register, $src$$XMMRegister);
12197 %}
12198 ins_pipe( pipe_slow );
12199 %}
12200
12201 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
12202 match(Set dst (MoveD2L src));
12203 effect(DEF dst, USE src);
12204 ins_cost(85);
12205 format %{ "movd $dst,$src\t# MoveD2L" %}
12206 ins_encode %{
12207 __ movdq($dst$$Register, $src$$XMMRegister);
12208 %}
12209 ins_pipe( pipe_slow );
12210 %}
12211
12212 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
12213 match(Set dst (MoveI2F src));
12214 effect(DEF dst, USE src);
12215 ins_cost(100);
12216 format %{ "movd $dst,$src\t# MoveI2F" %}
12217 ins_encode %{
12218 __ movdl($dst$$XMMRegister, $src$$Register);
12219 %}
12220 ins_pipe( pipe_slow );
12221 %}
12222
12223 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
12224 match(Set dst (MoveL2D src));
12225 effect(DEF dst, USE src);
12226 ins_cost(100);
12227 format %{ "movd $dst,$src\t# MoveL2D" %}
12228 ins_encode %{
12229 __ movdq($dst$$XMMRegister, $src$$Register);
12230 %}
12231 ins_pipe( pipe_slow );
12232 %}
12233
12234 // Fast clearing of an array
12235 // Small non-constant lenght ClearArray for non-AVX512 targets.
12236 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
12237 Universe dummy, rFlagsReg cr)
12238 %{
12239 predicate(!((ClearArrayNode*)n)->is_large() && (UseAVX <= 2));
12240 match(Set dummy (ClearArray cnt base));
12241 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
12242
12243 format %{ $$template
12244 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12245 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
12246 $$emit$$"jg LARGE\n\t"
12247 $$emit$$"dec rcx\n\t"
12248 $$emit$$"js DONE\t# Zero length\n\t"
12249 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
12250 $$emit$$"dec rcx\n\t"
12251 $$emit$$"jge LOOP\n\t"
12252 $$emit$$"jmp DONE\n\t"
12253 $$emit$$"# LARGE:\n\t"
12254 if (UseFastStosb) {
12255 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
12256 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
12257 } else if (UseXMMForObjInit) {
12258 $$emit$$"mov rdi,rax\n\t"
12259 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
12260 $$emit$$"jmpq L_zero_64_bytes\n\t"
12261 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
12262 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12263 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
12264 $$emit$$"add 0x40,rax\n\t"
12265 $$emit$$"# L_zero_64_bytes:\n\t"
12266 $$emit$$"sub 0x8,rcx\n\t"
12267 $$emit$$"jge L_loop\n\t"
12268 $$emit$$"add 0x4,rcx\n\t"
12269 $$emit$$"jl L_tail\n\t"
12270 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12271 $$emit$$"add 0x20,rax\n\t"
12272 $$emit$$"sub 0x4,rcx\n\t"
12273 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
12274 $$emit$$"add 0x4,rcx\n\t"
12275 $$emit$$"jle L_end\n\t"
12276 $$emit$$"dec rcx\n\t"
12277 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
12278 $$emit$$"vmovq xmm0,(rax)\n\t"
12279 $$emit$$"add 0x8,rax\n\t"
12280 $$emit$$"dec rcx\n\t"
12281 $$emit$$"jge L_sloop\n\t"
12282 $$emit$$"# L_end:\n\t"
12283 } else {
12284 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
12285 }
12286 $$emit$$"# DONE"
12287 %}
12288 ins_encode %{
12289 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
12290 $tmp$$XMMRegister, false, knoreg);
12291 %}
12292 ins_pipe(pipe_slow);
12293 %}
12294
12295 // Small non-constant length ClearArray for AVX512 targets.
12296 instruct rep_stos_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegI zero,
12297 Universe dummy, rFlagsReg cr)
12298 %{
12299 predicate(!((ClearArrayNode*)n)->is_large() && (UseAVX > 2));
12300 match(Set dummy (ClearArray cnt base));
12301 ins_cost(125);
12302 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, KILL zero, KILL cr);
12303
12304 format %{ $$template
12305 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12306 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
12307 $$emit$$"jg LARGE\n\t"
12308 $$emit$$"dec rcx\n\t"
12309 $$emit$$"js DONE\t# Zero length\n\t"
12310 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
12311 $$emit$$"dec rcx\n\t"
12312 $$emit$$"jge LOOP\n\t"
12313 $$emit$$"jmp DONE\n\t"
12314 $$emit$$"# LARGE:\n\t"
12315 if (UseFastStosb) {
12316 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
12317 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
12318 } else if (UseXMMForObjInit) {
12319 $$emit$$"mov rdi,rax\n\t"
12320 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
12321 $$emit$$"jmpq L_zero_64_bytes\n\t"
12322 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
12323 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12324 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
12325 $$emit$$"add 0x40,rax\n\t"
12326 $$emit$$"# L_zero_64_bytes:\n\t"
12327 $$emit$$"sub 0x8,rcx\n\t"
12328 $$emit$$"jge L_loop\n\t"
12329 $$emit$$"add 0x4,rcx\n\t"
12330 $$emit$$"jl L_tail\n\t"
12331 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12332 $$emit$$"add 0x20,rax\n\t"
12333 $$emit$$"sub 0x4,rcx\n\t"
12334 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
12335 $$emit$$"add 0x4,rcx\n\t"
12336 $$emit$$"jle L_end\n\t"
12337 $$emit$$"dec rcx\n\t"
12338 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
12339 $$emit$$"vmovq xmm0,(rax)\n\t"
12340 $$emit$$"add 0x8,rax\n\t"
12341 $$emit$$"dec rcx\n\t"
12342 $$emit$$"jge L_sloop\n\t"
12343 $$emit$$"# L_end:\n\t"
12344 } else {
12345 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
12346 }
12347 $$emit$$"# DONE"
12348 %}
12349 ins_encode %{
12350 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
12351 $tmp$$XMMRegister, false, $ktmp$$KRegister);
12352 %}
12353 ins_pipe(pipe_slow);
12354 %}
12355
12356 // Large non-constant length ClearArray for non-AVX512 targets.
12357 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
12358 Universe dummy, rFlagsReg cr)
12359 %{
12360 predicate((UseAVX <=2) && ((ClearArrayNode*)n)->is_large());
12361 match(Set dummy (ClearArray cnt base));
12362 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
12363
12364 format %{ $$template
12365 if (UseFastStosb) {
12366 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12367 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
12368 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
12369 } else if (UseXMMForObjInit) {
12370 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
12371 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
12372 $$emit$$"jmpq L_zero_64_bytes\n\t"
12373 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
12374 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12375 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
12376 $$emit$$"add 0x40,rax\n\t"
12377 $$emit$$"# L_zero_64_bytes:\n\t"
12378 $$emit$$"sub 0x8,rcx\n\t"
12379 $$emit$$"jge L_loop\n\t"
12380 $$emit$$"add 0x4,rcx\n\t"
12381 $$emit$$"jl L_tail\n\t"
12382 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12383 $$emit$$"add 0x20,rax\n\t"
12384 $$emit$$"sub 0x4,rcx\n\t"
12385 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
12386 $$emit$$"add 0x4,rcx\n\t"
12387 $$emit$$"jle L_end\n\t"
12388 $$emit$$"dec rcx\n\t"
12389 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
12390 $$emit$$"vmovq xmm0,(rax)\n\t"
12391 $$emit$$"add 0x8,rax\n\t"
12392 $$emit$$"dec rcx\n\t"
12393 $$emit$$"jge L_sloop\n\t"
12394 $$emit$$"# L_end:\n\t"
12395 } else {
12396 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12397 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
12398 }
12399 %}
12400 ins_encode %{
12401 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
12402 $tmp$$XMMRegister, true, knoreg);
12403 %}
12404 ins_pipe(pipe_slow);
12405 %}
12406
12407 // Large non-constant length ClearArray for AVX512 targets.
12408 instruct rep_stos_large_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegI zero,
12409 Universe dummy, rFlagsReg cr)
12410 %{
12411 predicate((UseAVX > 2) && ((ClearArrayNode*)n)->is_large());
12412 match(Set dummy (ClearArray cnt base));
12413 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, KILL zero, KILL cr);
12414
12415 format %{ $$template
12416 if (UseFastStosb) {
12417 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12418 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
12419 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
12420 } else if (UseXMMForObjInit) {
12421 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
12422 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
12423 $$emit$$"jmpq L_zero_64_bytes\n\t"
12424 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
12425 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12426 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
12427 $$emit$$"add 0x40,rax\n\t"
12428 $$emit$$"# L_zero_64_bytes:\n\t"
12429 $$emit$$"sub 0x8,rcx\n\t"
12430 $$emit$$"jge L_loop\n\t"
12431 $$emit$$"add 0x4,rcx\n\t"
12432 $$emit$$"jl L_tail\n\t"
12433 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12434 $$emit$$"add 0x20,rax\n\t"
12435 $$emit$$"sub 0x4,rcx\n\t"
12436 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
12437 $$emit$$"add 0x4,rcx\n\t"
12438 $$emit$$"jle L_end\n\t"
12439 $$emit$$"dec rcx\n\t"
12440 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
12441 $$emit$$"vmovq xmm0,(rax)\n\t"
12442 $$emit$$"add 0x8,rax\n\t"
12443 $$emit$$"dec rcx\n\t"
12444 $$emit$$"jge L_sloop\n\t"
12445 $$emit$$"# L_end:\n\t"
12446 } else {
12447 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12448 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
12449 }
12450 %}
12451 ins_encode %{
12452 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
12453 $tmp$$XMMRegister, true, $ktmp$$KRegister);
12454 %}
12455 ins_pipe(pipe_slow);
12456 %}
12457
12458 // Small constant length ClearArray for AVX512 targets.
12459 instruct rep_stos_im(immL cnt, rRegP base, regD tmp, rRegI zero, kReg ktmp, Universe dummy, rFlagsReg cr)
12460 %{
12461 predicate(!((ClearArrayNode*)n)->is_large() && (MaxVectorSize >= 32) && VM_Version::supports_avx512vl());
12462 match(Set dummy (ClearArray cnt base));
12463 ins_cost(100);
12464 effect(TEMP tmp, TEMP zero, TEMP ktmp, KILL cr);
12465 format %{ "clear_mem_imm $base , $cnt \n\t" %}
12466 ins_encode %{
12467 __ clear_mem($base$$Register, $cnt$$constant, $zero$$Register, $tmp$$XMMRegister, $ktmp$$KRegister);
12468 %}
12469 ins_pipe(pipe_slow);
12470 %}
12471
12472 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12473 rax_RegI result, legRegD tmp1, rFlagsReg cr)
12474 %{
12475 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
12476 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12477 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12478
12479 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12480 ins_encode %{
12481 __ string_compare($str1$$Register, $str2$$Register,
12482 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12483 $tmp1$$XMMRegister, StrIntrinsicNode::LL, knoreg);
12484 %}
12485 ins_pipe( pipe_slow );
12486 %}
12487
12488 instruct string_compareL_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12489 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
12490 %{
12491 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
12492 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12493 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12494
12495 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12496 ins_encode %{
12497 __ string_compare($str1$$Register, $str2$$Register,
12498 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12499 $tmp1$$XMMRegister, StrIntrinsicNode::LL, $ktmp$$KRegister);
12500 %}
12501 ins_pipe( pipe_slow );
12502 %}
12503
12504 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12505 rax_RegI result, legRegD tmp1, rFlagsReg cr)
12506 %{
12507 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
12508 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12509 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12510
12511 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12512 ins_encode %{
12513 __ string_compare($str1$$Register, $str2$$Register,
12514 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12515 $tmp1$$XMMRegister, StrIntrinsicNode::UU, knoreg);
12516 %}
12517 ins_pipe( pipe_slow );
12518 %}
12519
12520 instruct string_compareU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12521 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
12522 %{
12523 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
12524 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12525 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12526
12527 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12528 ins_encode %{
12529 __ string_compare($str1$$Register, $str2$$Register,
12530 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12531 $tmp1$$XMMRegister, StrIntrinsicNode::UU, $ktmp$$KRegister);
12532 %}
12533 ins_pipe( pipe_slow );
12534 %}
12535
12536 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12537 rax_RegI result, legRegD tmp1, rFlagsReg cr)
12538 %{
12539 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
12540 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12541 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12542
12543 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12544 ins_encode %{
12545 __ string_compare($str1$$Register, $str2$$Register,
12546 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12547 $tmp1$$XMMRegister, StrIntrinsicNode::LU, knoreg);
12548 %}
12549 ins_pipe( pipe_slow );
12550 %}
12551
12552 instruct string_compareLU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12553 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
12554 %{
12555 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
12556 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12557 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12558
12559 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12560 ins_encode %{
12561 __ string_compare($str1$$Register, $str2$$Register,
12562 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12563 $tmp1$$XMMRegister, StrIntrinsicNode::LU, $ktmp$$KRegister);
12564 %}
12565 ins_pipe( pipe_slow );
12566 %}
12567
12568 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
12569 rax_RegI result, legRegD tmp1, rFlagsReg cr)
12570 %{
12571 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
12572 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12573 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12574
12575 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12576 ins_encode %{
12577 __ string_compare($str2$$Register, $str1$$Register,
12578 $cnt2$$Register, $cnt1$$Register, $result$$Register,
12579 $tmp1$$XMMRegister, StrIntrinsicNode::UL, knoreg);
12580 %}
12581 ins_pipe( pipe_slow );
12582 %}
12583
12584 instruct string_compareUL_evex(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
12585 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
12586 %{
12587 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
12588 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12589 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12590
12591 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12592 ins_encode %{
12593 __ string_compare($str2$$Register, $str1$$Register,
12594 $cnt2$$Register, $cnt1$$Register, $result$$Register,
12595 $tmp1$$XMMRegister, StrIntrinsicNode::UL, $ktmp$$KRegister);
12596 %}
12597 ins_pipe( pipe_slow );
12598 %}
12599
12600 // fast search of substring with known size.
12601 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
12602 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
12603 %{
12604 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
12605 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12606 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12607
12608 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
12609 ins_encode %{
12610 int icnt2 = (int)$int_cnt2$$constant;
12611 if (icnt2 >= 16) {
12612 // IndexOf for constant substrings with size >= 16 elements
12613 // which don't need to be loaded through stack.
12614 __ string_indexofC8($str1$$Register, $str2$$Register,
12615 $cnt1$$Register, $cnt2$$Register,
12616 icnt2, $result$$Register,
12617 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
12618 } else {
12619 // Small strings are loaded through stack if they cross page boundary.
12620 __ string_indexof($str1$$Register, $str2$$Register,
12621 $cnt1$$Register, $cnt2$$Register,
12622 icnt2, $result$$Register,
12623 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
12624 }
12625 %}
12626 ins_pipe( pipe_slow );
12627 %}
12628
12629 // fast search of substring with known size.
12630 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
12631 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
12632 %{
12633 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
12634 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12635 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12636
12637 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
12638 ins_encode %{
12639 int icnt2 = (int)$int_cnt2$$constant;
12640 if (icnt2 >= 8) {
12641 // IndexOf for constant substrings with size >= 8 elements
12642 // which don't need to be loaded through stack.
12643 __ string_indexofC8($str1$$Register, $str2$$Register,
12644 $cnt1$$Register, $cnt2$$Register,
12645 icnt2, $result$$Register,
12646 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
12647 } else {
12648 // Small strings are loaded through stack if they cross page boundary.
12649 __ string_indexof($str1$$Register, $str2$$Register,
12650 $cnt1$$Register, $cnt2$$Register,
12651 icnt2, $result$$Register,
12652 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
12653 }
12654 %}
12655 ins_pipe( pipe_slow );
12656 %}
12657
12658 // fast search of substring with known size.
12659 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
12660 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
12661 %{
12662 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
12663 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12664 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12665
12666 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
12667 ins_encode %{
12668 int icnt2 = (int)$int_cnt2$$constant;
12669 if (icnt2 >= 8) {
12670 // IndexOf for constant substrings with size >= 8 elements
12671 // which don't need to be loaded through stack.
12672 __ string_indexofC8($str1$$Register, $str2$$Register,
12673 $cnt1$$Register, $cnt2$$Register,
12674 icnt2, $result$$Register,
12675 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
12676 } else {
12677 // Small strings are loaded through stack if they cross page boundary.
12678 __ string_indexof($str1$$Register, $str2$$Register,
12679 $cnt1$$Register, $cnt2$$Register,
12680 icnt2, $result$$Register,
12681 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
12682 }
12683 %}
12684 ins_pipe( pipe_slow );
12685 %}
12686
12687 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
12688 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
12689 %{
12690 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
12691 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12692 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12693
12694 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
12695 ins_encode %{
12696 __ string_indexof($str1$$Register, $str2$$Register,
12697 $cnt1$$Register, $cnt2$$Register,
12698 (-1), $result$$Register,
12699 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
12700 %}
12701 ins_pipe( pipe_slow );
12702 %}
12703
12704 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
12705 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
12706 %{
12707 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
12708 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12709 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12710
12711 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
12712 ins_encode %{
12713 __ string_indexof($str1$$Register, $str2$$Register,
12714 $cnt1$$Register, $cnt2$$Register,
12715 (-1), $result$$Register,
12716 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
12717 %}
12718 ins_pipe( pipe_slow );
12719 %}
12720
12721 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
12722 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
12723 %{
12724 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
12725 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12726 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12727
12728 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
12729 ins_encode %{
12730 __ string_indexof($str1$$Register, $str2$$Register,
12731 $cnt1$$Register, $cnt2$$Register,
12732 (-1), $result$$Register,
12733 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
12734 %}
12735 ins_pipe( pipe_slow );
12736 %}
12737
12738 instruct string_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
12739 rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
12740 %{
12741 predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
12742 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
12743 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
12744 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
12745 ins_encode %{
12746 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
12747 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
12748 %}
12749 ins_pipe( pipe_slow );
12750 %}
12751
12752 instruct stringL_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
12753 rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
12754 %{
12755 predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
12756 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
12757 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
12758 format %{ "StringLatin1 IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
12759 ins_encode %{
12760 __ stringL_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
12761 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
12762 %}
12763 ins_pipe( pipe_slow );
12764 %}
12765
12766 // fast string equals
12767 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
12768 legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr)
12769 %{
12770 predicate(!VM_Version::supports_avx512vlbw());
12771 match(Set result (StrEquals (Binary str1 str2) cnt));
12772 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12773
12774 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12775 ins_encode %{
12776 __ arrays_equals(false, $str1$$Register, $str2$$Register,
12777 $cnt$$Register, $result$$Register, $tmp3$$Register,
12778 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
12779 %}
12780 ins_pipe( pipe_slow );
12781 %}
12782
12783 instruct string_equals_evex(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
12784 legRegD tmp1, legRegD tmp2, kReg ktmp, rbx_RegI tmp3, rFlagsReg cr)
12785 %{
12786 predicate(VM_Version::supports_avx512vlbw());
12787 match(Set result (StrEquals (Binary str1 str2) cnt));
12788 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12789
12790 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12791 ins_encode %{
12792 __ arrays_equals(false, $str1$$Register, $str2$$Register,
12793 $cnt$$Register, $result$$Register, $tmp3$$Register,
12794 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
12795 %}
12796 ins_pipe( pipe_slow );
12797 %}
12798
12799 // fast array equals
12800 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
12801 legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
12802 %{
12803 predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
12804 match(Set result (AryEq ary1 ary2));
12805 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12806
12807 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12808 ins_encode %{
12809 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
12810 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12811 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
12812 %}
12813 ins_pipe( pipe_slow );
12814 %}
12815
12816 instruct array_equalsB_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
12817 legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
12818 %{
12819 predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
12820 match(Set result (AryEq ary1 ary2));
12821 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12822
12823 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12824 ins_encode %{
12825 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
12826 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12827 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
12828 %}
12829 ins_pipe( pipe_slow );
12830 %}
12831
12832 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
12833 legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
12834 %{
12835 predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
12836 match(Set result (AryEq ary1 ary2));
12837 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12838
12839 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12840 ins_encode %{
12841 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
12842 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12843 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, knoreg);
12844 %}
12845 ins_pipe( pipe_slow );
12846 %}
12847
12848 instruct array_equalsC_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
12849 legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
12850 %{
12851 predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
12852 match(Set result (AryEq ary1 ary2));
12853 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12854
12855 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12856 ins_encode %{
12857 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
12858 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12859 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, $ktmp$$KRegister);
12860 %}
12861 ins_pipe( pipe_slow );
12862 %}
12863
12864 instruct arrays_hashcode(rdi_RegP ary1, rdx_RegI cnt1, rbx_RegI result, immU8 basic_type,
12865 legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, legRegD tmp_vec4,
12866 legRegD tmp_vec5, legRegD tmp_vec6, legRegD tmp_vec7, legRegD tmp_vec8,
12867 legRegD tmp_vec9, legRegD tmp_vec10, legRegD tmp_vec11, legRegD tmp_vec12,
12868 legRegD tmp_vec13, rRegI tmp1, rRegI tmp2, rRegI tmp3, rFlagsReg cr)
12869 %{
12870 predicate(UseAVX >= 2);
12871 match(Set result (VectorizedHashCode (Binary ary1 cnt1) (Binary result basic_type)));
12872 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, TEMP tmp_vec4, TEMP tmp_vec5, TEMP tmp_vec6,
12873 TEMP tmp_vec7, TEMP tmp_vec8, TEMP tmp_vec9, TEMP tmp_vec10, TEMP tmp_vec11, TEMP tmp_vec12,
12874 TEMP tmp_vec13, TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL ary1, USE_KILL cnt1,
12875 USE basic_type, KILL cr);
12876
12877 format %{ "Array HashCode array[] $ary1,$cnt1,$result,$basic_type -> $result // KILL all" %}
12878 ins_encode %{
12879 __ arrays_hashcode($ary1$$Register, $cnt1$$Register, $result$$Register,
12880 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
12881 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister,
12882 $tmp_vec4$$XMMRegister, $tmp_vec5$$XMMRegister, $tmp_vec6$$XMMRegister,
12883 $tmp_vec7$$XMMRegister, $tmp_vec8$$XMMRegister, $tmp_vec9$$XMMRegister,
12884 $tmp_vec10$$XMMRegister, $tmp_vec11$$XMMRegister, $tmp_vec12$$XMMRegister,
12885 $tmp_vec13$$XMMRegister, (BasicType)$basic_type$$constant);
12886 %}
12887 ins_pipe( pipe_slow );
12888 %}
12889
12890 instruct count_positives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
12891 legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr,)
12892 %{
12893 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
12894 match(Set result (CountPositives ary1 len));
12895 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
12896
12897 format %{ "countPositives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12898 ins_encode %{
12899 __ count_positives($ary1$$Register, $len$$Register,
12900 $result$$Register, $tmp3$$Register,
12901 $tmp1$$XMMRegister, $tmp2$$XMMRegister, knoreg, knoreg);
12902 %}
12903 ins_pipe( pipe_slow );
12904 %}
12905
12906 instruct count_positives_evex(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
12907 legRegD tmp1, legRegD tmp2, kReg ktmp1, kReg ktmp2, rbx_RegI tmp3, rFlagsReg cr,)
12908 %{
12909 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
12910 match(Set result (CountPositives ary1 len));
12911 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp1, TEMP ktmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
12912
12913 format %{ "countPositives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12914 ins_encode %{
12915 __ count_positives($ary1$$Register, $len$$Register,
12916 $result$$Register, $tmp3$$Register,
12917 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $ktmp1$$KRegister, $ktmp2$$KRegister);
12918 %}
12919 ins_pipe( pipe_slow );
12920 %}
12921
12922 // fast char[] to byte[] compression
12923 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
12924 legRegD tmp4, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12925 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
12926 match(Set result (StrCompressedCopy src (Binary dst len)));
12927 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst,
12928 USE_KILL len, KILL tmp5, KILL cr);
12929
12930 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
12931 ins_encode %{
12932 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
12933 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12934 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
12935 knoreg, knoreg);
12936 %}
12937 ins_pipe( pipe_slow );
12938 %}
12939
12940 instruct string_compress_evex(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
12941 legRegD tmp4, kReg ktmp1, kReg ktmp2, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12942 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
12943 match(Set result (StrCompressedCopy src (Binary dst len)));
12944 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ktmp1, TEMP ktmp2, USE_KILL src, USE_KILL dst,
12945 USE_KILL len, KILL tmp5, KILL cr);
12946
12947 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
12948 ins_encode %{
12949 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
12950 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12951 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
12952 $ktmp1$$KRegister, $ktmp2$$KRegister);
12953 %}
12954 ins_pipe( pipe_slow );
12955 %}
12956 // fast byte[] to char[] inflation
12957 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12958 legRegD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
12959 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
12960 match(Set dummy (StrInflatedCopy src (Binary dst len)));
12961 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
12962
12963 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
12964 ins_encode %{
12965 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
12966 $tmp1$$XMMRegister, $tmp2$$Register, knoreg);
12967 %}
12968 ins_pipe( pipe_slow );
12969 %}
12970
12971 instruct string_inflate_evex(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12972 legRegD tmp1, kReg ktmp, rcx_RegI tmp2, rFlagsReg cr) %{
12973 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
12974 match(Set dummy (StrInflatedCopy src (Binary dst len)));
12975 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
12976
12977 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
12978 ins_encode %{
12979 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
12980 $tmp1$$XMMRegister, $tmp2$$Register, $ktmp$$KRegister);
12981 %}
12982 ins_pipe( pipe_slow );
12983 %}
12984
12985 // encode char[] to byte[] in ISO_8859_1
12986 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12987 legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
12988 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12989 predicate(!((EncodeISOArrayNode*)n)->is_ascii());
12990 match(Set result (EncodeISOArray src (Binary dst len)));
12991 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
12992
12993 format %{ "Encode iso array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
12994 ins_encode %{
12995 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
12996 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12997 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, false);
12998 %}
12999 ins_pipe( pipe_slow );
13000 %}
13001
13002 // encode char[] to byte[] in ASCII
13003 instruct encode_ascii_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
13004 legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
13005 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
13006 predicate(((EncodeISOArrayNode*)n)->is_ascii());
13007 match(Set result (EncodeISOArray src (Binary dst len)));
13008 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
13009
13010 format %{ "Encode ascii array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
13011 ins_encode %{
13012 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
13013 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
13014 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, true);
13015 %}
13016 ins_pipe( pipe_slow );
13017 %}
13018
13019 //----------Overflow Math Instructions-----------------------------------------
13020
13021 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
13022 %{
13023 match(Set cr (OverflowAddI op1 op2));
13024 effect(DEF cr, USE_KILL op1, USE op2);
13025
13026 format %{ "addl $op1, $op2\t# overflow check int" %}
13027
13028 ins_encode %{
13029 __ addl($op1$$Register, $op2$$Register);
13030 %}
13031 ins_pipe(ialu_reg_reg);
13032 %}
13033
13034 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
13035 %{
13036 match(Set cr (OverflowAddI op1 op2));
13037 effect(DEF cr, USE_KILL op1, USE op2);
13038
13039 format %{ "addl $op1, $op2\t# overflow check int" %}
13040
13041 ins_encode %{
13042 __ addl($op1$$Register, $op2$$constant);
13043 %}
13044 ins_pipe(ialu_reg_reg);
13045 %}
13046
13047 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
13048 %{
13049 match(Set cr (OverflowAddL op1 op2));
13050 effect(DEF cr, USE_KILL op1, USE op2);
13051
13052 format %{ "addq $op1, $op2\t# overflow check long" %}
13053 ins_encode %{
13054 __ addq($op1$$Register, $op2$$Register);
13055 %}
13056 ins_pipe(ialu_reg_reg);
13057 %}
13058
13059 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
13060 %{
13061 match(Set cr (OverflowAddL op1 op2));
13062 effect(DEF cr, USE_KILL op1, USE op2);
13063
13064 format %{ "addq $op1, $op2\t# overflow check long" %}
13065 ins_encode %{
13066 __ addq($op1$$Register, $op2$$constant);
13067 %}
13068 ins_pipe(ialu_reg_reg);
13069 %}
13070
13071 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
13072 %{
13073 match(Set cr (OverflowSubI op1 op2));
13074
13075 format %{ "cmpl $op1, $op2\t# overflow check int" %}
13076 ins_encode %{
13077 __ cmpl($op1$$Register, $op2$$Register);
13078 %}
13079 ins_pipe(ialu_reg_reg);
13080 %}
13081
13082 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
13083 %{
13084 match(Set cr (OverflowSubI op1 op2));
13085
13086 format %{ "cmpl $op1, $op2\t# overflow check int" %}
13087 ins_encode %{
13088 __ cmpl($op1$$Register, $op2$$constant);
13089 %}
13090 ins_pipe(ialu_reg_reg);
13091 %}
13092
13093 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
13094 %{
13095 match(Set cr (OverflowSubL op1 op2));
13096
13097 format %{ "cmpq $op1, $op2\t# overflow check long" %}
13098 ins_encode %{
13099 __ cmpq($op1$$Register, $op2$$Register);
13100 %}
13101 ins_pipe(ialu_reg_reg);
13102 %}
13103
13104 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
13105 %{
13106 match(Set cr (OverflowSubL op1 op2));
13107
13108 format %{ "cmpq $op1, $op2\t# overflow check long" %}
13109 ins_encode %{
13110 __ cmpq($op1$$Register, $op2$$constant);
13111 %}
13112 ins_pipe(ialu_reg_reg);
13113 %}
13114
13115 instruct overflowNegI_rReg(rFlagsReg cr, immI_0 zero, rax_RegI op2)
13116 %{
13117 match(Set cr (OverflowSubI zero op2));
13118 effect(DEF cr, USE_KILL op2);
13119
13120 format %{ "negl $op2\t# overflow check int" %}
13121 ins_encode %{
13122 __ negl($op2$$Register);
13123 %}
13124 ins_pipe(ialu_reg_reg);
13125 %}
13126
13127 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
13128 %{
13129 match(Set cr (OverflowSubL zero op2));
13130 effect(DEF cr, USE_KILL op2);
13131
13132 format %{ "negq $op2\t# overflow check long" %}
13133 ins_encode %{
13134 __ negq($op2$$Register);
13135 %}
13136 ins_pipe(ialu_reg_reg);
13137 %}
13138
13139 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
13140 %{
13141 match(Set cr (OverflowMulI op1 op2));
13142 effect(DEF cr, USE_KILL op1, USE op2);
13143
13144 format %{ "imull $op1, $op2\t# overflow check int" %}
13145 ins_encode %{
13146 __ imull($op1$$Register, $op2$$Register);
13147 %}
13148 ins_pipe(ialu_reg_reg_alu0);
13149 %}
13150
13151 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
13152 %{
13153 match(Set cr (OverflowMulI op1 op2));
13154 effect(DEF cr, TEMP tmp, USE op1, USE op2);
13155
13156 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
13157 ins_encode %{
13158 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
13159 %}
13160 ins_pipe(ialu_reg_reg_alu0);
13161 %}
13162
13163 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
13164 %{
13165 match(Set cr (OverflowMulL op1 op2));
13166 effect(DEF cr, USE_KILL op1, USE op2);
13167
13168 format %{ "imulq $op1, $op2\t# overflow check long" %}
13169 ins_encode %{
13170 __ imulq($op1$$Register, $op2$$Register);
13171 %}
13172 ins_pipe(ialu_reg_reg_alu0);
13173 %}
13174
13175 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
13176 %{
13177 match(Set cr (OverflowMulL op1 op2));
13178 effect(DEF cr, TEMP tmp, USE op1, USE op2);
13179
13180 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
13181 ins_encode %{
13182 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
13183 %}
13184 ins_pipe(ialu_reg_reg_alu0);
13185 %}
13186
13187
13188 //----------Control Flow Instructions------------------------------------------
13189 // Signed compare Instructions
13190
13191 // XXX more variants!!
13192 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
13193 %{
13194 match(Set cr (CmpI op1 op2));
13195 effect(DEF cr, USE op1, USE op2);
13196
13197 format %{ "cmpl $op1, $op2" %}
13198 ins_encode %{
13199 __ cmpl($op1$$Register, $op2$$Register);
13200 %}
13201 ins_pipe(ialu_cr_reg_reg);
13202 %}
13203
13204 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
13205 %{
13206 match(Set cr (CmpI op1 op2));
13207
13208 format %{ "cmpl $op1, $op2" %}
13209 ins_encode %{
13210 __ cmpl($op1$$Register, $op2$$constant);
13211 %}
13212 ins_pipe(ialu_cr_reg_imm);
13213 %}
13214
13215 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
13216 %{
13217 match(Set cr (CmpI op1 (LoadI op2)));
13218
13219 ins_cost(500); // XXX
13220 format %{ "cmpl $op1, $op2" %}
13221 ins_encode %{
13222 __ cmpl($op1$$Register, $op2$$Address);
13223 %}
13224 ins_pipe(ialu_cr_reg_mem);
13225 %}
13226
13227 instruct testI_reg(rFlagsReg cr, rRegI src, immI_0 zero)
13228 %{
13229 match(Set cr (CmpI src zero));
13230
13231 format %{ "testl $src, $src" %}
13232 ins_encode %{
13233 __ testl($src$$Register, $src$$Register);
13234 %}
13235 ins_pipe(ialu_cr_reg_imm);
13236 %}
13237
13238 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI_0 zero)
13239 %{
13240 match(Set cr (CmpI (AndI src con) zero));
13241
13242 format %{ "testl $src, $con" %}
13243 ins_encode %{
13244 __ testl($src$$Register, $con$$constant);
13245 %}
13246 ins_pipe(ialu_cr_reg_imm);
13247 %}
13248
13249 instruct testI_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2, immI_0 zero)
13250 %{
13251 match(Set cr (CmpI (AndI src1 src2) zero));
13252
13253 format %{ "testl $src1, $src2" %}
13254 ins_encode %{
13255 __ testl($src1$$Register, $src2$$Register);
13256 %}
13257 ins_pipe(ialu_cr_reg_imm);
13258 %}
13259
13260 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI_0 zero)
13261 %{
13262 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
13263
13264 format %{ "testl $src, $mem" %}
13265 ins_encode %{
13266 __ testl($src$$Register, $mem$$Address);
13267 %}
13268 ins_pipe(ialu_cr_reg_mem);
13269 %}
13270
13271 // Unsigned compare Instructions; really, same as signed except they
13272 // produce an rFlagsRegU instead of rFlagsReg.
13273 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
13274 %{
13275 match(Set cr (CmpU op1 op2));
13276
13277 format %{ "cmpl $op1, $op2\t# unsigned" %}
13278 ins_encode %{
13279 __ cmpl($op1$$Register, $op2$$Register);
13280 %}
13281 ins_pipe(ialu_cr_reg_reg);
13282 %}
13283
13284 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
13285 %{
13286 match(Set cr (CmpU op1 op2));
13287
13288 format %{ "cmpl $op1, $op2\t# unsigned" %}
13289 ins_encode %{
13290 __ cmpl($op1$$Register, $op2$$constant);
13291 %}
13292 ins_pipe(ialu_cr_reg_imm);
13293 %}
13294
13295 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
13296 %{
13297 match(Set cr (CmpU op1 (LoadI op2)));
13298
13299 ins_cost(500); // XXX
13300 format %{ "cmpl $op1, $op2\t# unsigned" %}
13301 ins_encode %{
13302 __ cmpl($op1$$Register, $op2$$Address);
13303 %}
13304 ins_pipe(ialu_cr_reg_mem);
13305 %}
13306
13307 instruct testU_reg(rFlagsRegU cr, rRegI src, immI_0 zero)
13308 %{
13309 match(Set cr (CmpU src zero));
13310
13311 format %{ "testl $src, $src\t# unsigned" %}
13312 ins_encode %{
13313 __ testl($src$$Register, $src$$Register);
13314 %}
13315 ins_pipe(ialu_cr_reg_imm);
13316 %}
13317
13318 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
13319 %{
13320 match(Set cr (CmpP op1 op2));
13321
13322 format %{ "cmpq $op1, $op2\t# ptr" %}
13323 ins_encode %{
13324 __ cmpq($op1$$Register, $op2$$Register);
13325 %}
13326 ins_pipe(ialu_cr_reg_reg);
13327 %}
13328
13329 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
13330 %{
13331 match(Set cr (CmpP op1 (LoadP op2)));
13332 predicate(n->in(2)->as_Load()->barrier_data() == 0);
13333
13334 ins_cost(500); // XXX
13335 format %{ "cmpq $op1, $op2\t# ptr" %}
13336 ins_encode %{
13337 __ cmpq($op1$$Register, $op2$$Address);
13338 %}
13339 ins_pipe(ialu_cr_reg_mem);
13340 %}
13341
13342 // XXX this is generalized by compP_rReg_mem???
13343 // Compare raw pointer (used in out-of-heap check).
13344 // Only works because non-oop pointers must be raw pointers
13345 // and raw pointers have no anti-dependencies.
13346 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
13347 %{
13348 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none &&
13349 n->in(2)->as_Load()->barrier_data() == 0);
13350 match(Set cr (CmpP op1 (LoadP op2)));
13351
13352 format %{ "cmpq $op1, $op2\t# raw ptr" %}
13353 ins_encode %{
13354 __ cmpq($op1$$Register, $op2$$Address);
13355 %}
13356 ins_pipe(ialu_cr_reg_mem);
13357 %}
13358
13359 // This will generate a signed flags result. This should be OK since
13360 // any compare to a zero should be eq/neq.
13361 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
13362 %{
13363 match(Set cr (CmpP src zero));
13364
13365 format %{ "testq $src, $src\t# ptr" %}
13366 ins_encode %{
13367 __ testq($src$$Register, $src$$Register);
13368 %}
13369 ins_pipe(ialu_cr_reg_imm);
13370 %}
13371
13372 // This will generate a signed flags result. This should be OK since
13373 // any compare to a zero should be eq/neq.
13374 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
13375 %{
13376 predicate((!UseCompressedOops || (CompressedOops::base() != nullptr)) &&
13377 n->in(1)->as_Load()->barrier_data() == 0);
13378 match(Set cr (CmpP (LoadP op) zero));
13379
13380 ins_cost(500); // XXX
13381 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
13382 ins_encode %{
13383 __ testq($op$$Address, 0xFFFFFFFF);
13384 %}
13385 ins_pipe(ialu_cr_reg_imm);
13386 %}
13387
13388 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
13389 %{
13390 predicate(UseCompressedOops && (CompressedOops::base() == nullptr) &&
13391 n->in(1)->as_Load()->barrier_data() == 0);
13392 match(Set cr (CmpP (LoadP mem) zero));
13393
13394 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
13395 ins_encode %{
13396 __ cmpq(r12, $mem$$Address);
13397 %}
13398 ins_pipe(ialu_cr_reg_mem);
13399 %}
13400
13401 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
13402 %{
13403 match(Set cr (CmpN op1 op2));
13404
13405 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
13406 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
13407 ins_pipe(ialu_cr_reg_reg);
13408 %}
13409
13410 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
13411 %{
13412 predicate(n->in(2)->as_Load()->barrier_data() == 0);
13413 match(Set cr (CmpN src (LoadN mem)));
13414
13415 format %{ "cmpl $src, $mem\t# compressed ptr" %}
13416 ins_encode %{
13417 __ cmpl($src$$Register, $mem$$Address);
13418 %}
13419 ins_pipe(ialu_cr_reg_mem);
13420 %}
13421
13422 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
13423 match(Set cr (CmpN op1 op2));
13424
13425 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
13426 ins_encode %{
13427 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
13428 %}
13429 ins_pipe(ialu_cr_reg_imm);
13430 %}
13431
13432 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
13433 %{
13434 predicate(n->in(2)->as_Load()->barrier_data() == 0);
13435 match(Set cr (CmpN src (LoadN mem)));
13436
13437 format %{ "cmpl $mem, $src\t# compressed ptr" %}
13438 ins_encode %{
13439 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
13440 %}
13441 ins_pipe(ialu_cr_reg_mem);
13442 %}
13443
13444 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
13445 match(Set cr (CmpN op1 op2));
13446
13447 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
13448 ins_encode %{
13449 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
13450 %}
13451 ins_pipe(ialu_cr_reg_imm);
13452 %}
13453
13454 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
13455 %{
13456 predicate(!UseCompactObjectHeaders);
13457 match(Set cr (CmpN src (LoadNKlass mem)));
13458
13459 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
13460 ins_encode %{
13461 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
13462 %}
13463 ins_pipe(ialu_cr_reg_mem);
13464 %}
13465
13466 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
13467 match(Set cr (CmpN src zero));
13468
13469 format %{ "testl $src, $src\t# compressed ptr" %}
13470 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
13471 ins_pipe(ialu_cr_reg_imm);
13472 %}
13473
13474 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
13475 %{
13476 predicate(CompressedOops::base() != nullptr &&
13477 n->in(1)->as_Load()->barrier_data() == 0);
13478 match(Set cr (CmpN (LoadN mem) zero));
13479
13480 ins_cost(500); // XXX
13481 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
13482 ins_encode %{
13483 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
13484 %}
13485 ins_pipe(ialu_cr_reg_mem);
13486 %}
13487
13488 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
13489 %{
13490 predicate(CompressedOops::base() == nullptr &&
13491 n->in(1)->as_Load()->barrier_data() == 0);
13492 match(Set cr (CmpN (LoadN mem) zero));
13493
13494 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
13495 ins_encode %{
13496 __ cmpl(r12, $mem$$Address);
13497 %}
13498 ins_pipe(ialu_cr_reg_mem);
13499 %}
13500
13501 // Yanked all unsigned pointer compare operations.
13502 // Pointer compares are done with CmpP which is already unsigned.
13503
13504 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
13505 %{
13506 match(Set cr (CmpL op1 op2));
13507
13508 format %{ "cmpq $op1, $op2" %}
13509 ins_encode %{
13510 __ cmpq($op1$$Register, $op2$$Register);
13511 %}
13512 ins_pipe(ialu_cr_reg_reg);
13513 %}
13514
13515 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
13516 %{
13517 match(Set cr (CmpL op1 op2));
13518
13519 format %{ "cmpq $op1, $op2" %}
13520 ins_encode %{
13521 __ cmpq($op1$$Register, $op2$$constant);
13522 %}
13523 ins_pipe(ialu_cr_reg_imm);
13524 %}
13525
13526 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
13527 %{
13528 match(Set cr (CmpL op1 (LoadL op2)));
13529
13530 format %{ "cmpq $op1, $op2" %}
13531 ins_encode %{
13532 __ cmpq($op1$$Register, $op2$$Address);
13533 %}
13534 ins_pipe(ialu_cr_reg_mem);
13535 %}
13536
13537 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
13538 %{
13539 match(Set cr (CmpL src zero));
13540
13541 format %{ "testq $src, $src" %}
13542 ins_encode %{
13543 __ testq($src$$Register, $src$$Register);
13544 %}
13545 ins_pipe(ialu_cr_reg_imm);
13546 %}
13547
13548 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
13549 %{
13550 match(Set cr (CmpL (AndL src con) zero));
13551
13552 format %{ "testq $src, $con\t# long" %}
13553 ins_encode %{
13554 __ testq($src$$Register, $con$$constant);
13555 %}
13556 ins_pipe(ialu_cr_reg_imm);
13557 %}
13558
13559 instruct testL_reg_reg(rFlagsReg cr, rRegL src1, rRegL src2, immL0 zero)
13560 %{
13561 match(Set cr (CmpL (AndL src1 src2) zero));
13562
13563 format %{ "testq $src1, $src2\t# long" %}
13564 ins_encode %{
13565 __ testq($src1$$Register, $src2$$Register);
13566 %}
13567 ins_pipe(ialu_cr_reg_imm);
13568 %}
13569
13570 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
13571 %{
13572 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
13573
13574 format %{ "testq $src, $mem" %}
13575 ins_encode %{
13576 __ testq($src$$Register, $mem$$Address);
13577 %}
13578 ins_pipe(ialu_cr_reg_mem);
13579 %}
13580
13581 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
13582 %{
13583 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
13584
13585 format %{ "testq $src, $mem" %}
13586 ins_encode %{
13587 __ testq($src$$Register, $mem$$Address);
13588 %}
13589 ins_pipe(ialu_cr_reg_mem);
13590 %}
13591
13592 // Manifest a CmpU result in an integer register. Very painful.
13593 // This is the test to avoid.
13594 instruct cmpU3_reg_reg(rRegI dst, rRegI src1, rRegI src2, rFlagsReg flags)
13595 %{
13596 match(Set dst (CmpU3 src1 src2));
13597 effect(KILL flags);
13598
13599 ins_cost(275); // XXX
13600 format %{ "cmpl $src1, $src2\t# CmpL3\n\t"
13601 "movl $dst, -1\n\t"
13602 "jb,u done\n\t"
13603 "setcc $dst \t# emits setne + movzbl or setzune for APX"
13604 "done:" %}
13605 ins_encode %{
13606 Label done;
13607 __ cmpl($src1$$Register, $src2$$Register);
13608 __ movl($dst$$Register, -1);
13609 __ jccb(Assembler::below, done);
13610 __ setcc(Assembler::notZero, $dst$$Register);
13611 __ bind(done);
13612 %}
13613 ins_pipe(pipe_slow);
13614 %}
13615
13616 // Manifest a CmpL result in an integer register. Very painful.
13617 // This is the test to avoid.
13618 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
13619 %{
13620 match(Set dst (CmpL3 src1 src2));
13621 effect(KILL flags);
13622
13623 ins_cost(275); // XXX
13624 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
13625 "movl $dst, -1\n\t"
13626 "jl,s done\n\t"
13627 "setcc $dst \t# emits setne + movzbl or setzune for APX"
13628 "done:" %}
13629 ins_encode %{
13630 Label done;
13631 __ cmpq($src1$$Register, $src2$$Register);
13632 __ movl($dst$$Register, -1);
13633 __ jccb(Assembler::less, done);
13634 __ setcc(Assembler::notZero, $dst$$Register);
13635 __ bind(done);
13636 %}
13637 ins_pipe(pipe_slow);
13638 %}
13639
13640 // Manifest a CmpUL result in an integer register. Very painful.
13641 // This is the test to avoid.
13642 instruct cmpUL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
13643 %{
13644 match(Set dst (CmpUL3 src1 src2));
13645 effect(KILL flags);
13646
13647 ins_cost(275); // XXX
13648 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
13649 "movl $dst, -1\n\t"
13650 "jb,u done\n\t"
13651 "setcc $dst \t# emits setne + movzbl or setzune for APX"
13652 "done:" %}
13653 ins_encode %{
13654 Label done;
13655 __ cmpq($src1$$Register, $src2$$Register);
13656 __ movl($dst$$Register, -1);
13657 __ jccb(Assembler::below, done);
13658 __ setcc(Assembler::notZero, $dst$$Register);
13659 __ bind(done);
13660 %}
13661 ins_pipe(pipe_slow);
13662 %}
13663
13664 // Unsigned long compare Instructions; really, same as signed long except they
13665 // produce an rFlagsRegU instead of rFlagsReg.
13666 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
13667 %{
13668 match(Set cr (CmpUL op1 op2));
13669
13670 format %{ "cmpq $op1, $op2\t# unsigned" %}
13671 ins_encode %{
13672 __ cmpq($op1$$Register, $op2$$Register);
13673 %}
13674 ins_pipe(ialu_cr_reg_reg);
13675 %}
13676
13677 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
13678 %{
13679 match(Set cr (CmpUL op1 op2));
13680
13681 format %{ "cmpq $op1, $op2\t# unsigned" %}
13682 ins_encode %{
13683 __ cmpq($op1$$Register, $op2$$constant);
13684 %}
13685 ins_pipe(ialu_cr_reg_imm);
13686 %}
13687
13688 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
13689 %{
13690 match(Set cr (CmpUL op1 (LoadL op2)));
13691
13692 format %{ "cmpq $op1, $op2\t# unsigned" %}
13693 ins_encode %{
13694 __ cmpq($op1$$Register, $op2$$Address);
13695 %}
13696 ins_pipe(ialu_cr_reg_mem);
13697 %}
13698
13699 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
13700 %{
13701 match(Set cr (CmpUL src zero));
13702
13703 format %{ "testq $src, $src\t# unsigned" %}
13704 ins_encode %{
13705 __ testq($src$$Register, $src$$Register);
13706 %}
13707 ins_pipe(ialu_cr_reg_imm);
13708 %}
13709
13710 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
13711 %{
13712 match(Set cr (CmpI (LoadB mem) imm));
13713
13714 ins_cost(125);
13715 format %{ "cmpb $mem, $imm" %}
13716 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
13717 ins_pipe(ialu_cr_reg_mem);
13718 %}
13719
13720 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU7 imm, immI_0 zero)
13721 %{
13722 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
13723
13724 ins_cost(125);
13725 format %{ "testb $mem, $imm\t# ubyte" %}
13726 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
13727 ins_pipe(ialu_cr_reg_mem);
13728 %}
13729
13730 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI_0 zero)
13731 %{
13732 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
13733
13734 ins_cost(125);
13735 format %{ "testb $mem, $imm\t# byte" %}
13736 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
13737 ins_pipe(ialu_cr_reg_mem);
13738 %}
13739
13740 //----------Max and Min--------------------------------------------------------
13741 // Min Instructions
13742
13743 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
13744 %{
13745 predicate(!UseAPX);
13746 effect(USE_DEF dst, USE src, USE cr);
13747
13748 format %{ "cmovlgt $dst, $src\t# min" %}
13749 ins_encode %{
13750 __ cmovl(Assembler::greater, $dst$$Register, $src$$Register);
13751 %}
13752 ins_pipe(pipe_cmov_reg);
13753 %}
13754
13755 instruct cmovI_reg_g_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
13756 %{
13757 predicate(UseAPX);
13758 effect(DEF dst, USE src1, USE src2, USE cr);
13759
13760 format %{ "ecmovlgt $dst, $src1, $src2\t# min ndd" %}
13761 ins_encode %{
13762 __ ecmovl(Assembler::greater, $dst$$Register, $src1$$Register, $src2$$Register);
13763 %}
13764 ins_pipe(pipe_cmov_reg);
13765 %}
13766
13767 instruct minI_rReg(rRegI dst, rRegI src)
13768 %{
13769 predicate(!UseAPX);
13770 match(Set dst (MinI dst src));
13771
13772 ins_cost(200);
13773 expand %{
13774 rFlagsReg cr;
13775 compI_rReg(cr, dst, src);
13776 cmovI_reg_g(dst, src, cr);
13777 %}
13778 %}
13779
13780 instruct minI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2)
13781 %{
13782 predicate(UseAPX);
13783 match(Set dst (MinI src1 src2));
13784 effect(DEF dst, USE src1, USE src2);
13785
13786 ins_cost(200);
13787 expand %{
13788 rFlagsReg cr;
13789 compI_rReg(cr, src1, src2);
13790 cmovI_reg_g_ndd(dst, src1, src2, cr);
13791 %}
13792 %}
13793
13794 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
13795 %{
13796 predicate(!UseAPX);
13797 effect(USE_DEF dst, USE src, USE cr);
13798
13799 format %{ "cmovllt $dst, $src\t# max" %}
13800 ins_encode %{
13801 __ cmovl(Assembler::less, $dst$$Register, $src$$Register);
13802 %}
13803 ins_pipe(pipe_cmov_reg);
13804 %}
13805
13806 instruct cmovI_reg_l_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
13807 %{
13808 predicate(UseAPX);
13809 effect(DEF dst, USE src1, USE src2, USE cr);
13810
13811 format %{ "ecmovllt $dst, $src1, $src2\t# max ndd" %}
13812 ins_encode %{
13813 __ ecmovl(Assembler::less, $dst$$Register, $src1$$Register, $src2$$Register);
13814 %}
13815 ins_pipe(pipe_cmov_reg);
13816 %}
13817
13818 instruct maxI_rReg(rRegI dst, rRegI src)
13819 %{
13820 predicate(!UseAPX);
13821 match(Set dst (MaxI dst src));
13822
13823 ins_cost(200);
13824 expand %{
13825 rFlagsReg cr;
13826 compI_rReg(cr, dst, src);
13827 cmovI_reg_l(dst, src, cr);
13828 %}
13829 %}
13830
13831 instruct maxI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2)
13832 %{
13833 predicate(UseAPX);
13834 match(Set dst (MaxI src1 src2));
13835 effect(DEF dst, USE src1, USE src2);
13836
13837 ins_cost(200);
13838 expand %{
13839 rFlagsReg cr;
13840 compI_rReg(cr, src1, src2);
13841 cmovI_reg_l_ndd(dst, src1, src2, cr);
13842 %}
13843 %}
13844
13845 // ============================================================================
13846 // Branch Instructions
13847
13848 // Jump Direct - Label defines a relative address from JMP+1
13849 instruct jmpDir(label labl)
13850 %{
13851 match(Goto);
13852 effect(USE labl);
13853
13854 ins_cost(300);
13855 format %{ "jmp $labl" %}
13856 size(5);
13857 ins_encode %{
13858 Label* L = $labl$$label;
13859 __ jmp(*L, false); // Always long jump
13860 %}
13861 ins_pipe(pipe_jmp);
13862 %}
13863
13864 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13865 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
13866 %{
13867 match(If cop cr);
13868 effect(USE labl);
13869
13870 ins_cost(300);
13871 format %{ "j$cop $labl" %}
13872 size(6);
13873 ins_encode %{
13874 Label* L = $labl$$label;
13875 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13876 %}
13877 ins_pipe(pipe_jcc);
13878 %}
13879
13880 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13881 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
13882 %{
13883 match(CountedLoopEnd cop cr);
13884 effect(USE labl);
13885
13886 ins_cost(300);
13887 format %{ "j$cop $labl\t# loop end" %}
13888 size(6);
13889 ins_encode %{
13890 Label* L = $labl$$label;
13891 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13892 %}
13893 ins_pipe(pipe_jcc);
13894 %}
13895
13896 // Jump Direct Conditional - using unsigned comparison
13897 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
13898 match(If cop cmp);
13899 effect(USE labl);
13900
13901 ins_cost(300);
13902 format %{ "j$cop,u $labl" %}
13903 size(6);
13904 ins_encode %{
13905 Label* L = $labl$$label;
13906 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13907 %}
13908 ins_pipe(pipe_jcc);
13909 %}
13910
13911 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
13912 match(If cop cmp);
13913 effect(USE labl);
13914
13915 ins_cost(200);
13916 format %{ "j$cop,u $labl" %}
13917 size(6);
13918 ins_encode %{
13919 Label* L = $labl$$label;
13920 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13921 %}
13922 ins_pipe(pipe_jcc);
13923 %}
13924
13925 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
13926 match(If cop cmp);
13927 effect(USE labl);
13928
13929 ins_cost(200);
13930 format %{ $$template
13931 if ($cop$$cmpcode == Assembler::notEqual) {
13932 $$emit$$"jp,u $labl\n\t"
13933 $$emit$$"j$cop,u $labl"
13934 } else {
13935 $$emit$$"jp,u done\n\t"
13936 $$emit$$"j$cop,u $labl\n\t"
13937 $$emit$$"done:"
13938 }
13939 %}
13940 ins_encode %{
13941 Label* l = $labl$$label;
13942 if ($cop$$cmpcode == Assembler::notEqual) {
13943 __ jcc(Assembler::parity, *l, false);
13944 __ jcc(Assembler::notEqual, *l, false);
13945 } else if ($cop$$cmpcode == Assembler::equal) {
13946 Label done;
13947 __ jccb(Assembler::parity, done);
13948 __ jcc(Assembler::equal, *l, false);
13949 __ bind(done);
13950 } else {
13951 ShouldNotReachHere();
13952 }
13953 %}
13954 ins_pipe(pipe_jcc);
13955 %}
13956
13957 // ============================================================================
13958 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
13959 // superklass array for an instance of the superklass. Set a hidden
13960 // internal cache on a hit (cache is checked with exposed code in
13961 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
13962 // encoding ALSO sets flags.
13963
13964 instruct partialSubtypeCheck(rdi_RegP result,
13965 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
13966 rFlagsReg cr)
13967 %{
13968 match(Set result (PartialSubtypeCheck sub super));
13969 predicate(!UseSecondarySupersTable);
13970 effect(KILL rcx, KILL cr);
13971
13972 ins_cost(1100); // slightly larger than the next version
13973 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
13974 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
13975 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
13976 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
13977 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
13978 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
13979 "xorq $result, $result\t\t Hit: rdi zero\n\t"
13980 "miss:\t" %}
13981
13982 ins_encode %{
13983 Label miss;
13984 // NB: Callers may assume that, when $result is a valid register,
13985 // check_klass_subtype_slow_path_linear sets it to a nonzero
13986 // value.
13987 __ check_klass_subtype_slow_path_linear($sub$$Register, $super$$Register,
13988 $rcx$$Register, $result$$Register,
13989 nullptr, &miss,
13990 /*set_cond_codes:*/ true);
13991 __ xorptr($result$$Register, $result$$Register);
13992 __ bind(miss);
13993 %}
13994
13995 ins_pipe(pipe_slow);
13996 %}
13997
13998 // ============================================================================
13999 // Two versions of hashtable-based partialSubtypeCheck, both used when
14000 // we need to search for a super class in the secondary supers array.
14001 // The first is used when we don't know _a priori_ the class being
14002 // searched for. The second, far more common, is used when we do know:
14003 // this is used for instanceof, checkcast, and any case where C2 can
14004 // determine it by constant propagation.
14005
14006 instruct partialSubtypeCheckVarSuper(rsi_RegP sub, rax_RegP super, rdi_RegP result,
14007 rdx_RegL temp1, rcx_RegL temp2, rbx_RegP temp3, r11_RegL temp4,
14008 rFlagsReg cr)
14009 %{
14010 match(Set result (PartialSubtypeCheck sub super));
14011 predicate(UseSecondarySupersTable);
14012 effect(KILL cr, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
14013
14014 ins_cost(1000);
14015 format %{ "partialSubtypeCheck $result, $sub, $super" %}
14016
14017 ins_encode %{
14018 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $temp1$$Register, $temp2$$Register,
14019 $temp3$$Register, $temp4$$Register, $result$$Register);
14020 %}
14021
14022 ins_pipe(pipe_slow);
14023 %}
14024
14025 instruct partialSubtypeCheckConstSuper(rsi_RegP sub, rax_RegP super_reg, immP super_con, rdi_RegP result,
14026 rdx_RegL temp1, rcx_RegL temp2, rbx_RegP temp3, r11_RegL temp4,
14027 rFlagsReg cr)
14028 %{
14029 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
14030 predicate(UseSecondarySupersTable);
14031 effect(KILL cr, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
14032
14033 ins_cost(700); // smaller than the next version
14034 format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
14035
14036 ins_encode %{
14037 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
14038 if (InlineSecondarySupersTest) {
14039 __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $temp1$$Register, $temp2$$Register,
14040 $temp3$$Register, $temp4$$Register, $result$$Register,
14041 super_klass_slot);
14042 } else {
14043 __ call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
14044 }
14045 %}
14046
14047 ins_pipe(pipe_slow);
14048 %}
14049
14050 // ============================================================================
14051 // Branch Instructions -- short offset versions
14052 //
14053 // These instructions are used to replace jumps of a long offset (the default
14054 // match) with jumps of a shorter offset. These instructions are all tagged
14055 // with the ins_short_branch attribute, which causes the ADLC to suppress the
14056 // match rules in general matching. Instead, the ADLC generates a conversion
14057 // method in the MachNode which can be used to do in-place replacement of the
14058 // long variant with the shorter variant. The compiler will determine if a
14059 // branch can be taken by the is_short_branch_offset() predicate in the machine
14060 // specific code section of the file.
14061
14062 // Jump Direct - Label defines a relative address from JMP+1
14063 instruct jmpDir_short(label labl) %{
14064 match(Goto);
14065 effect(USE labl);
14066
14067 ins_cost(300);
14068 format %{ "jmp,s $labl" %}
14069 size(2);
14070 ins_encode %{
14071 Label* L = $labl$$label;
14072 __ jmpb(*L);
14073 %}
14074 ins_pipe(pipe_jmp);
14075 ins_short_branch(1);
14076 %}
14077
14078 // Jump Direct Conditional - Label defines a relative address from Jcc+1
14079 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
14080 match(If cop cr);
14081 effect(USE labl);
14082
14083 ins_cost(300);
14084 format %{ "j$cop,s $labl" %}
14085 size(2);
14086 ins_encode %{
14087 Label* L = $labl$$label;
14088 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
14089 %}
14090 ins_pipe(pipe_jcc);
14091 ins_short_branch(1);
14092 %}
14093
14094 // Jump Direct Conditional - Label defines a relative address from Jcc+1
14095 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
14096 match(CountedLoopEnd cop cr);
14097 effect(USE labl);
14098
14099 ins_cost(300);
14100 format %{ "j$cop,s $labl\t# loop end" %}
14101 size(2);
14102 ins_encode %{
14103 Label* L = $labl$$label;
14104 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
14105 %}
14106 ins_pipe(pipe_jcc);
14107 ins_short_branch(1);
14108 %}
14109
14110 // Jump Direct Conditional - using unsigned comparison
14111 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
14112 match(If cop cmp);
14113 effect(USE labl);
14114
14115 ins_cost(300);
14116 format %{ "j$cop,us $labl" %}
14117 size(2);
14118 ins_encode %{
14119 Label* L = $labl$$label;
14120 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
14121 %}
14122 ins_pipe(pipe_jcc);
14123 ins_short_branch(1);
14124 %}
14125
14126 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
14127 match(If cop cmp);
14128 effect(USE labl);
14129
14130 ins_cost(300);
14131 format %{ "j$cop,us $labl" %}
14132 size(2);
14133 ins_encode %{
14134 Label* L = $labl$$label;
14135 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
14136 %}
14137 ins_pipe(pipe_jcc);
14138 ins_short_branch(1);
14139 %}
14140
14141 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
14142 match(If cop cmp);
14143 effect(USE labl);
14144
14145 ins_cost(300);
14146 format %{ $$template
14147 if ($cop$$cmpcode == Assembler::notEqual) {
14148 $$emit$$"jp,u,s $labl\n\t"
14149 $$emit$$"j$cop,u,s $labl"
14150 } else {
14151 $$emit$$"jp,u,s done\n\t"
14152 $$emit$$"j$cop,u,s $labl\n\t"
14153 $$emit$$"done:"
14154 }
14155 %}
14156 size(4);
14157 ins_encode %{
14158 Label* l = $labl$$label;
14159 if ($cop$$cmpcode == Assembler::notEqual) {
14160 __ jccb(Assembler::parity, *l);
14161 __ jccb(Assembler::notEqual, *l);
14162 } else if ($cop$$cmpcode == Assembler::equal) {
14163 Label done;
14164 __ jccb(Assembler::parity, done);
14165 __ jccb(Assembler::equal, *l);
14166 __ bind(done);
14167 } else {
14168 ShouldNotReachHere();
14169 }
14170 %}
14171 ins_pipe(pipe_jcc);
14172 ins_short_branch(1);
14173 %}
14174
14175 // ============================================================================
14176 // inlined locking and unlocking
14177
14178 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
14179 predicate(LockingMode != LM_LIGHTWEIGHT);
14180 match(Set cr (FastLock object box));
14181 effect(TEMP tmp, TEMP scr, USE_KILL box);
14182 ins_cost(300);
14183 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
14184 ins_encode %{
14185 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
14186 $scr$$Register, noreg, noreg, r15_thread, nullptr);
14187 %}
14188 ins_pipe(pipe_slow);
14189 %}
14190
14191 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
14192 predicate(LockingMode != LM_LIGHTWEIGHT);
14193 match(Set cr (FastUnlock object box));
14194 effect(TEMP tmp, USE_KILL box);
14195 ins_cost(300);
14196 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
14197 ins_encode %{
14198 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register);
14199 %}
14200 ins_pipe(pipe_slow);
14201 %}
14202
14203 instruct cmpFastLockLightweight(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI rax_reg, rRegP tmp) %{
14204 predicate(LockingMode == LM_LIGHTWEIGHT);
14205 match(Set cr (FastLock object box));
14206 effect(TEMP rax_reg, TEMP tmp, USE_KILL box);
14207 ins_cost(300);
14208 format %{ "fastlock $object,$box\t! kills $box,$rax_reg,$tmp" %}
14209 ins_encode %{
14210 __ fast_lock_lightweight($object$$Register, $box$$Register, $rax_reg$$Register, $tmp$$Register, r15_thread);
14211 %}
14212 ins_pipe(pipe_slow);
14213 %}
14214
14215 instruct cmpFastUnlockLightweight(rFlagsReg cr, rRegP object, rax_RegP rax_reg, rRegP tmp) %{
14216 predicate(LockingMode == LM_LIGHTWEIGHT);
14217 match(Set cr (FastUnlock object rax_reg));
14218 effect(TEMP tmp, USE_KILL rax_reg);
14219 ins_cost(300);
14220 format %{ "fastunlock $object,$rax_reg\t! kills $rax_reg,$tmp" %}
14221 ins_encode %{
14222 __ fast_unlock_lightweight($object$$Register, $rax_reg$$Register, $tmp$$Register, r15_thread);
14223 %}
14224 ins_pipe(pipe_slow);
14225 %}
14226
14227
14228 // ============================================================================
14229 // Safepoint Instructions
14230 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
14231 %{
14232 match(SafePoint poll);
14233 effect(KILL cr, USE poll);
14234
14235 format %{ "testl rax, [$poll]\t"
14236 "# Safepoint: poll for GC" %}
14237 ins_cost(125);
14238 ins_encode %{
14239 __ relocate(relocInfo::poll_type);
14240 address pre_pc = __ pc();
14241 __ testl(rax, Address($poll$$Register, 0));
14242 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
14243 %}
14244 ins_pipe(ialu_reg_mem);
14245 %}
14246
14247 instruct mask_all_evexL(kReg dst, rRegL src) %{
14248 match(Set dst (MaskAll src));
14249 format %{ "mask_all_evexL $dst, $src \t! mask all operation" %}
14250 ins_encode %{
14251 int mask_len = Matcher::vector_length(this);
14252 __ vector_maskall_operation($dst$$KRegister, $src$$Register, mask_len);
14253 %}
14254 ins_pipe( pipe_slow );
14255 %}
14256
14257 instruct mask_all_evexI_GT32(kReg dst, rRegI src, rRegL tmp) %{
14258 predicate(Matcher::vector_length(n) > 32);
14259 match(Set dst (MaskAll src));
14260 effect(TEMP tmp);
14261 format %{ "mask_all_evexI_GT32 $dst, $src \t! using $tmp as TEMP" %}
14262 ins_encode %{
14263 int mask_len = Matcher::vector_length(this);
14264 __ movslq($tmp$$Register, $src$$Register);
14265 __ vector_maskall_operation($dst$$KRegister, $tmp$$Register, mask_len);
14266 %}
14267 ins_pipe( pipe_slow );
14268 %}
14269
14270 // ============================================================================
14271 // Procedure Call/Return Instructions
14272 // Call Java Static Instruction
14273 // Note: If this code changes, the corresponding ret_addr_offset() and
14274 // compute_padding() functions will have to be adjusted.
14275 instruct CallStaticJavaDirect(method meth) %{
14276 match(CallStaticJava);
14277 effect(USE meth);
14278
14279 ins_cost(300);
14280 format %{ "call,static " %}
14281 opcode(0xE8); /* E8 cd */
14282 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
14283 ins_pipe(pipe_slow);
14284 ins_alignment(4);
14285 %}
14286
14287 // Call Java Dynamic Instruction
14288 // Note: If this code changes, the corresponding ret_addr_offset() and
14289 // compute_padding() functions will have to be adjusted.
14290 instruct CallDynamicJavaDirect(method meth)
14291 %{
14292 match(CallDynamicJava);
14293 effect(USE meth);
14294
14295 ins_cost(300);
14296 format %{ "movq rax, #Universe::non_oop_word()\n\t"
14297 "call,dynamic " %}
14298 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
14299 ins_pipe(pipe_slow);
14300 ins_alignment(4);
14301 %}
14302
14303 // Call Runtime Instruction
14304 instruct CallRuntimeDirect(method meth)
14305 %{
14306 match(CallRuntime);
14307 effect(USE meth);
14308
14309 ins_cost(300);
14310 format %{ "call,runtime " %}
14311 ins_encode(clear_avx, Java_To_Runtime(meth));
14312 ins_pipe(pipe_slow);
14313 %}
14314
14315 // Call runtime without safepoint
14316 instruct CallLeafDirect(method meth)
14317 %{
14318 match(CallLeaf);
14319 effect(USE meth);
14320
14321 ins_cost(300);
14322 format %{ "call_leaf,runtime " %}
14323 ins_encode(clear_avx, Java_To_Runtime(meth));
14324 ins_pipe(pipe_slow);
14325 %}
14326
14327 // Call runtime without safepoint and with vector arguments
14328 instruct CallLeafDirectVector(method meth)
14329 %{
14330 match(CallLeafVector);
14331 effect(USE meth);
14332
14333 ins_cost(300);
14334 format %{ "call_leaf,vector " %}
14335 ins_encode(Java_To_Runtime(meth));
14336 ins_pipe(pipe_slow);
14337 %}
14338
14339 // Call runtime without safepoint
14340 instruct CallLeafNoFPDirect(method meth)
14341 %{
14342 match(CallLeafNoFP);
14343 effect(USE meth);
14344
14345 ins_cost(300);
14346 format %{ "call_leaf_nofp,runtime " %}
14347 ins_encode(clear_avx, Java_To_Runtime(meth));
14348 ins_pipe(pipe_slow);
14349 %}
14350
14351 // Return Instruction
14352 // Remove the return address & jump to it.
14353 // Notice: We always emit a nop after a ret to make sure there is room
14354 // for safepoint patching
14355 instruct Ret()
14356 %{
14357 match(Return);
14358
14359 format %{ "ret" %}
14360 ins_encode %{
14361 __ ret(0);
14362 %}
14363 ins_pipe(pipe_jmp);
14364 %}
14365
14366 // Tail Call; Jump from runtime stub to Java code.
14367 // Also known as an 'interprocedural jump'.
14368 // Target of jump will eventually return to caller.
14369 // TailJump below removes the return address.
14370 // Don't use rbp for 'jump_target' because a MachEpilogNode has already been
14371 // emitted just above the TailCall which has reset rbp to the caller state.
14372 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_ptr)
14373 %{
14374 match(TailCall jump_target method_ptr);
14375
14376 ins_cost(300);
14377 format %{ "jmp $jump_target\t# rbx holds method" %}
14378 ins_encode %{
14379 __ jmp($jump_target$$Register);
14380 %}
14381 ins_pipe(pipe_jmp);
14382 %}
14383
14384 // Tail Jump; remove the return address; jump to target.
14385 // TailCall above leaves the return address around.
14386 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
14387 %{
14388 match(TailJump jump_target ex_oop);
14389
14390 ins_cost(300);
14391 format %{ "popq rdx\t# pop return address\n\t"
14392 "jmp $jump_target" %}
14393 ins_encode %{
14394 __ popq(as_Register(RDX_enc));
14395 __ jmp($jump_target$$Register);
14396 %}
14397 ins_pipe(pipe_jmp);
14398 %}
14399
14400 // Forward exception.
14401 instruct ForwardExceptionjmp()
14402 %{
14403 match(ForwardException);
14404
14405 format %{ "jmp forward_exception_stub" %}
14406 ins_encode %{
14407 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()), noreg);
14408 %}
14409 ins_pipe(pipe_jmp);
14410 %}
14411
14412 // Create exception oop: created by stack-crawling runtime code.
14413 // Created exception is now available to this handler, and is setup
14414 // just prior to jumping to this handler. No code emitted.
14415 instruct CreateException(rax_RegP ex_oop)
14416 %{
14417 match(Set ex_oop (CreateEx));
14418
14419 size(0);
14420 // use the following format syntax
14421 format %{ "# exception oop is in rax; no code emitted" %}
14422 ins_encode();
14423 ins_pipe(empty);
14424 %}
14425
14426 // Rethrow exception:
14427 // The exception oop will come in the first argument position.
14428 // Then JUMP (not call) to the rethrow stub code.
14429 instruct RethrowException()
14430 %{
14431 match(Rethrow);
14432
14433 // use the following format syntax
14434 format %{ "jmp rethrow_stub" %}
14435 ins_encode %{
14436 __ jump(RuntimeAddress(OptoRuntime::rethrow_stub()), noreg);
14437 %}
14438 ins_pipe(pipe_jmp);
14439 %}
14440
14441 // ============================================================================
14442 // This name is KNOWN by the ADLC and cannot be changed.
14443 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
14444 // for this guy.
14445 instruct tlsLoadP(r15_RegP dst) %{
14446 match(Set dst (ThreadLocal));
14447 effect(DEF dst);
14448
14449 size(0);
14450 format %{ "# TLS is in R15" %}
14451 ins_encode( /*empty encoding*/ );
14452 ins_pipe(ialu_reg_reg);
14453 %}
14454
14455
14456 //----------PEEPHOLE RULES-----------------------------------------------------
14457 // These must follow all instruction definitions as they use the names
14458 // defined in the instructions definitions.
14459 //
14460 // peeppredicate ( rule_predicate );
14461 // // the predicate unless which the peephole rule will be ignored
14462 //
14463 // peepmatch ( root_instr_name [preceding_instruction]* );
14464 //
14465 // peepprocedure ( procedure_name );
14466 // // provide a procedure name to perform the optimization, the procedure should
14467 // // reside in the architecture dependent peephole file, the method has the
14468 // // signature of MachNode* (Block*, int, PhaseRegAlloc*, (MachNode*)(*)(), int...)
14469 // // with the arguments being the basic block, the current node index inside the
14470 // // block, the register allocator, the functions upon invoked return a new node
14471 // // defined in peepreplace, and the rules of the nodes appearing in the
14472 // // corresponding peepmatch, the function return true if successful, else
14473 // // return false
14474 //
14475 // peepconstraint %{
14476 // (instruction_number.operand_name relational_op instruction_number.operand_name
14477 // [, ...] );
14478 // // instruction numbers are zero-based using left to right order in peepmatch
14479 //
14480 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
14481 // // provide an instruction_number.operand_name for each operand that appears
14482 // // in the replacement instruction's match rule
14483 //
14484 // ---------VM FLAGS---------------------------------------------------------
14485 //
14486 // All peephole optimizations can be turned off using -XX:-OptoPeephole
14487 //
14488 // Each peephole rule is given an identifying number starting with zero and
14489 // increasing by one in the order seen by the parser. An individual peephole
14490 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
14491 // on the command-line.
14492 //
14493 // ---------CURRENT LIMITATIONS----------------------------------------------
14494 //
14495 // Only transformations inside a basic block (do we need more for peephole)
14496 //
14497 // ---------EXAMPLE----------------------------------------------------------
14498 //
14499 // // pertinent parts of existing instructions in architecture description
14500 // instruct movI(rRegI dst, rRegI src)
14501 // %{
14502 // match(Set dst (CopyI src));
14503 // %}
14504 //
14505 // instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
14506 // %{
14507 // match(Set dst (AddI dst src));
14508 // effect(KILL cr);
14509 // %}
14510 //
14511 // instruct leaI_rReg_immI(rRegI dst, immI_1 src)
14512 // %{
14513 // match(Set dst (AddI dst src));
14514 // %}
14515 //
14516 // 1. Simple replacement
14517 // - Only match adjacent instructions in same basic block
14518 // - Only equality constraints
14519 // - Only constraints between operands, not (0.dest_reg == RAX_enc)
14520 // - Only one replacement instruction
14521 //
14522 // // Change (inc mov) to lea
14523 // peephole %{
14524 // // lea should only be emitted when beneficial
14525 // peeppredicate( VM_Version::supports_fast_2op_lea() );
14526 // // increment preceded by register-register move
14527 // peepmatch ( incI_rReg movI );
14528 // // require that the destination register of the increment
14529 // // match the destination register of the move
14530 // peepconstraint ( 0.dst == 1.dst );
14531 // // construct a replacement instruction that sets
14532 // // the destination to ( move's source register + one )
14533 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
14534 // %}
14535 //
14536 // 2. Procedural replacement
14537 // - More flexible finding relevent nodes
14538 // - More flexible constraints
14539 // - More flexible transformations
14540 // - May utilise architecture-dependent API more effectively
14541 // - Currently only one replacement instruction due to adlc parsing capabilities
14542 //
14543 // // Change (inc mov) to lea
14544 // peephole %{
14545 // // lea should only be emitted when beneficial
14546 // peeppredicate( VM_Version::supports_fast_2op_lea() );
14547 // // the rule numbers of these nodes inside are passed into the function below
14548 // peepmatch ( incI_rReg movI );
14549 // // the method that takes the responsibility of transformation
14550 // peepprocedure ( inc_mov_to_lea );
14551 // // the replacement is a leaI_rReg_immI, a lambda upon invoked creating this
14552 // // node is passed into the function above
14553 // peepreplace ( leaI_rReg_immI() );
14554 // %}
14555
14556 // These instructions is not matched by the matcher but used by the peephole
14557 instruct leaI_rReg_rReg_peep(rRegI dst, rRegI src1, rRegI src2)
14558 %{
14559 predicate(false);
14560 match(Set dst (AddI src1 src2));
14561 format %{ "leal $dst, [$src1 + $src2]" %}
14562 ins_encode %{
14563 Register dst = $dst$$Register;
14564 Register src1 = $src1$$Register;
14565 Register src2 = $src2$$Register;
14566 if (src1 != rbp && src1 != r13) {
14567 __ leal(dst, Address(src1, src2, Address::times_1));
14568 } else {
14569 assert(src2 != rbp && src2 != r13, "");
14570 __ leal(dst, Address(src2, src1, Address::times_1));
14571 }
14572 %}
14573 ins_pipe(ialu_reg_reg);
14574 %}
14575
14576 instruct leaI_rReg_immI_peep(rRegI dst, rRegI src1, immI src2)
14577 %{
14578 predicate(false);
14579 match(Set dst (AddI src1 src2));
14580 format %{ "leal $dst, [$src1 + $src2]" %}
14581 ins_encode %{
14582 __ leal($dst$$Register, Address($src1$$Register, $src2$$constant));
14583 %}
14584 ins_pipe(ialu_reg_reg);
14585 %}
14586
14587 instruct leaI_rReg_immI2_peep(rRegI dst, rRegI src, immI2 shift)
14588 %{
14589 predicate(false);
14590 match(Set dst (LShiftI src shift));
14591 format %{ "leal $dst, [$src << $shift]" %}
14592 ins_encode %{
14593 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($shift$$constant);
14594 Register src = $src$$Register;
14595 if (scale == Address::times_2 && src != rbp && src != r13) {
14596 __ leal($dst$$Register, Address(src, src, Address::times_1));
14597 } else {
14598 __ leal($dst$$Register, Address(noreg, src, scale));
14599 }
14600 %}
14601 ins_pipe(ialu_reg_reg);
14602 %}
14603
14604 instruct leaL_rReg_rReg_peep(rRegL dst, rRegL src1, rRegL src2)
14605 %{
14606 predicate(false);
14607 match(Set dst (AddL src1 src2));
14608 format %{ "leaq $dst, [$src1 + $src2]" %}
14609 ins_encode %{
14610 Register dst = $dst$$Register;
14611 Register src1 = $src1$$Register;
14612 Register src2 = $src2$$Register;
14613 if (src1 != rbp && src1 != r13) {
14614 __ leaq(dst, Address(src1, src2, Address::times_1));
14615 } else {
14616 assert(src2 != rbp && src2 != r13, "");
14617 __ leaq(dst, Address(src2, src1, Address::times_1));
14618 }
14619 %}
14620 ins_pipe(ialu_reg_reg);
14621 %}
14622
14623 instruct leaL_rReg_immL32_peep(rRegL dst, rRegL src1, immL32 src2)
14624 %{
14625 predicate(false);
14626 match(Set dst (AddL src1 src2));
14627 format %{ "leaq $dst, [$src1 + $src2]" %}
14628 ins_encode %{
14629 __ leaq($dst$$Register, Address($src1$$Register, $src2$$constant));
14630 %}
14631 ins_pipe(ialu_reg_reg);
14632 %}
14633
14634 instruct leaL_rReg_immI2_peep(rRegL dst, rRegL src, immI2 shift)
14635 %{
14636 predicate(false);
14637 match(Set dst (LShiftL src shift));
14638 format %{ "leaq $dst, [$src << $shift]" %}
14639 ins_encode %{
14640 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($shift$$constant);
14641 Register src = $src$$Register;
14642 if (scale == Address::times_2 && src != rbp && src != r13) {
14643 __ leaq($dst$$Register, Address(src, src, Address::times_1));
14644 } else {
14645 __ leaq($dst$$Register, Address(noreg, src, scale));
14646 }
14647 %}
14648 ins_pipe(ialu_reg_reg);
14649 %}
14650
14651 // These peephole rules replace mov + I pairs (where I is one of {add, inc, dec,
14652 // sal}) with lea instructions. The {add, sal} rules are beneficial in
14653 // processors with at least partial ALU support for lea
14654 // (supports_fast_2op_lea()), whereas the {inc, dec} rules are only generally
14655 // beneficial for processors with full ALU support
14656 // (VM_Version::supports_fast_3op_lea()) and Intel Cascade Lake.
14657
14658 peephole
14659 %{
14660 peeppredicate(VM_Version::supports_fast_2op_lea());
14661 peepmatch (addI_rReg);
14662 peepprocedure (lea_coalesce_reg);
14663 peepreplace (leaI_rReg_rReg_peep());
14664 %}
14665
14666 peephole
14667 %{
14668 peeppredicate(VM_Version::supports_fast_2op_lea());
14669 peepmatch (addI_rReg_imm);
14670 peepprocedure (lea_coalesce_imm);
14671 peepreplace (leaI_rReg_immI_peep());
14672 %}
14673
14674 peephole
14675 %{
14676 peeppredicate(VM_Version::supports_fast_3op_lea() ||
14677 VM_Version::is_intel_cascade_lake());
14678 peepmatch (incI_rReg);
14679 peepprocedure (lea_coalesce_imm);
14680 peepreplace (leaI_rReg_immI_peep());
14681 %}
14682
14683 peephole
14684 %{
14685 peeppredicate(VM_Version::supports_fast_3op_lea() ||
14686 VM_Version::is_intel_cascade_lake());
14687 peepmatch (decI_rReg);
14688 peepprocedure (lea_coalesce_imm);
14689 peepreplace (leaI_rReg_immI_peep());
14690 %}
14691
14692 peephole
14693 %{
14694 peeppredicate(VM_Version::supports_fast_2op_lea());
14695 peepmatch (salI_rReg_immI2);
14696 peepprocedure (lea_coalesce_imm);
14697 peepreplace (leaI_rReg_immI2_peep());
14698 %}
14699
14700 peephole
14701 %{
14702 peeppredicate(VM_Version::supports_fast_2op_lea());
14703 peepmatch (addL_rReg);
14704 peepprocedure (lea_coalesce_reg);
14705 peepreplace (leaL_rReg_rReg_peep());
14706 %}
14707
14708 peephole
14709 %{
14710 peeppredicate(VM_Version::supports_fast_2op_lea());
14711 peepmatch (addL_rReg_imm);
14712 peepprocedure (lea_coalesce_imm);
14713 peepreplace (leaL_rReg_immL32_peep());
14714 %}
14715
14716 peephole
14717 %{
14718 peeppredicate(VM_Version::supports_fast_3op_lea() ||
14719 VM_Version::is_intel_cascade_lake());
14720 peepmatch (incL_rReg);
14721 peepprocedure (lea_coalesce_imm);
14722 peepreplace (leaL_rReg_immL32_peep());
14723 %}
14724
14725 peephole
14726 %{
14727 peeppredicate(VM_Version::supports_fast_3op_lea() ||
14728 VM_Version::is_intel_cascade_lake());
14729 peepmatch (decL_rReg);
14730 peepprocedure (lea_coalesce_imm);
14731 peepreplace (leaL_rReg_immL32_peep());
14732 %}
14733
14734 peephole
14735 %{
14736 peeppredicate(VM_Version::supports_fast_2op_lea());
14737 peepmatch (salL_rReg_immI2);
14738 peepprocedure (lea_coalesce_imm);
14739 peepreplace (leaL_rReg_immI2_peep());
14740 %}
14741
14742 // These peephole rules matches instructions which set flags and are followed by a testI/L_reg
14743 // The test instruction is redudanent in case the downstream instuctions (like JCC or CMOV) only use flags that are already set by the previous instruction
14744
14745 //int variant
14746 peephole
14747 %{
14748 peepmatch (testI_reg);
14749 peepprocedure (test_may_remove);
14750 %}
14751
14752 //long variant
14753 peephole
14754 %{
14755 peepmatch (testL_reg);
14756 peepprocedure (test_may_remove);
14757 %}
14758
14759
14760 //----------SMARTSPILL RULES---------------------------------------------------
14761 // These must follow all instruction definitions as they use the names
14762 // defined in the instructions definitions.