1 /*
2 * Copyright (c) 2018, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #include "c1/c1_LIRGenerator.hpp"
26 #include "c1/c1_CodeStubs.hpp"
27 #if INCLUDE_CDS
28 #include "code/SCCache.hpp"
29 #endif
30 #include "gc/g1/c1/g1BarrierSetC1.hpp"
31 #include "gc/g1/g1BarrierSet.hpp"
32 #include "gc/g1/g1BarrierSetAssembler.hpp"
33 #include "gc/g1/g1HeapRegion.hpp"
34 #include "gc/g1/g1ThreadLocalData.hpp"
35 #include "utilities/macros.hpp"
36
37 #ifdef ASSERT
38 #define __ gen->lir(__FILE__, __LINE__)->
39 #else
40 #define __ gen->lir()->
41 #endif
42
43 void G1PreBarrierStub::emit_code(LIR_Assembler* ce) {
44 G1BarrierSetAssembler* bs = (G1BarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
45 bs->gen_pre_barrier_stub(ce, this);
46 }
47
48 void G1PostBarrierStub::emit_code(LIR_Assembler* ce) {
49 G1BarrierSetAssembler* bs = (G1BarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
50 bs->gen_post_barrier_stub(ce, this);
51 }
52
53 void G1BarrierSetC1::pre_barrier(LIRAccess& access, LIR_Opr addr_opr,
54 LIR_Opr pre_val, CodeEmitInfo* info) {
55 LIRGenerator* gen = access.gen();
56 DecoratorSet decorators = access.decorators();
57
58 // First we test whether marking is in progress.
59 BasicType flag_type;
60 bool patch = (decorators & C1_NEEDS_PATCHING) != 0;
61 bool do_load = pre_val == LIR_OprFact::illegalOpr;
62 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
63 flag_type = T_INT;
64 } else {
65 guarantee(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1,
66 "Assumption");
67 // Use unsigned type T_BOOLEAN here rather than signed T_BYTE since some platforms, eg. ARM,
68 // need to use unsigned instructions to use the large offset to load the satb_mark_queue.
69 flag_type = T_BOOLEAN;
70 }
71 LIR_Opr thrd = gen->getThreadPointer();
72 LIR_Address* mark_active_flag_addr =
73 new LIR_Address(thrd,
74 in_bytes(G1ThreadLocalData::satb_mark_queue_active_offset()),
75 flag_type);
76 // Read the marking-in-progress flag.
77 // Note: When loading pre_val requires patching, i.e. do_load == true &&
78 // patch == true, a safepoint can occur while patching. This makes the
79 // pre-barrier non-atomic and invalidates the marking-in-progress check.
80 // Therefore, in the presence of patching, we must repeat the same
81 // marking-in-progress checking before calling into the Runtime. For
82 // simplicity, we do this check unconditionally (regardless of the presence
83 // of patching) in the runtime stub
84 // (G1BarrierSetAssembler::generate_c1_pre_barrier_runtime_stub).
85 LIR_Opr flag_val = gen->new_register(T_INT);
86 __ load(mark_active_flag_addr, flag_val);
87 __ cmp(lir_cond_notEqual, flag_val, LIR_OprFact::intConst(0));
88
89 LIR_PatchCode pre_val_patch_code = lir_patch_none;
90
91 CodeStub* slow;
92
93 if (do_load) {
94 assert(pre_val == LIR_OprFact::illegalOpr, "sanity");
95 assert(addr_opr != LIR_OprFact::illegalOpr, "sanity");
96
97 if (patch)
98 pre_val_patch_code = lir_patch_normal;
99
100 pre_val = gen->new_register(T_OBJECT);
101
102 if (!addr_opr->is_address()) {
103 assert(addr_opr->is_register(), "must be");
104 addr_opr = LIR_OprFact::address(new LIR_Address(addr_opr, T_OBJECT));
105 }
106 slow = new G1PreBarrierStub(addr_opr, pre_val, pre_val_patch_code, info);
107 } else {
108 assert(addr_opr == LIR_OprFact::illegalOpr, "sanity");
109 assert(pre_val->is_register(), "must be");
110 assert(pre_val->type() == T_OBJECT, "must be an object");
111 assert(info == nullptr, "sanity");
112
113 slow = new G1PreBarrierStub(pre_val);
114 }
115
116 __ branch(lir_cond_notEqual, slow);
117 __ branch_destination(slow->continuation());
118 }
119
120 void G1BarrierSetC1::post_barrier(LIRAccess& access, LIR_Opr addr, LIR_Opr new_val) {
121 LIRGenerator* gen = access.gen();
122 DecoratorSet decorators = access.decorators();
123 bool in_heap = (decorators & IN_HEAP) != 0;
124 if (!in_heap) {
125 return;
126 }
127
128 // If the "new_val" is a constant null, no barrier is necessary.
129 if (new_val->is_constant() &&
130 new_val->as_constant_ptr()->as_jobject() == nullptr) return;
131
132 if (!new_val->is_register()) {
133 LIR_Opr new_val_reg = gen->new_register(T_OBJECT);
134 if (new_val->is_constant()) {
135 __ move(new_val, new_val_reg);
136 } else {
137 __ leal(new_val, new_val_reg);
138 }
139 new_val = new_val_reg;
140 }
141 assert(new_val->is_register(), "must be a register at this point");
142
143 if (addr->is_address()) {
144 LIR_Address* address = addr->as_address_ptr();
145 LIR_Opr ptr = gen->new_pointer_register();
146 if (!address->index()->is_valid() && address->disp() == 0) {
147 __ move(address->base(), ptr);
148 } else {
149 assert(address->disp() != max_jint, "lea doesn't support patched addresses!");
150 __ leal(addr, ptr);
151 }
152 addr = ptr;
153 }
154 assert(addr->is_register(), "must be a register at this point");
155
156 LIR_Opr xor_res = gen->new_pointer_register();
157 LIR_Opr xor_shift_res = gen->new_pointer_register();
158 #if INCLUDE_CDS
159 // we need to load the grain shift from the AOT Runtime
160 // Constants Area
161 LIR_Opr grain_shift_addr = LIR_OprFact::intptrConst(AOTRuntimeConstants::grain_shift_address());
162 LIR_Opr grain_shift_reg = gen->new_pointer_register();
163 LIR_Address* grain_shift_indirect = new LIR_Address(grain_shift_reg, 0, T_INT);
164 #ifdef X86
165 LIR_Opr grain_shift = gen->shiftCountOpr();
166 #else // X86
167 LIR_Opr grain_shift = gen->new_register(T_INT);
168 #endif // X86
169 #endif
170 if (two_operand_lir_form) {
171 __ move(addr, xor_res);
172 __ logical_xor(xor_res, new_val, xor_res);
173 #if INCLUDE_CDS
174 if (SCCache::is_on_for_write()) {
175 __ move(grain_shift_addr, grain_shift_reg);
176 __ move(xor_res, xor_shift_res);
177 __ move(grain_shift_indirect, grain_shift);
178 __ unsigned_shift_right(xor_shift_res,
179 grain_shift,
180 xor_shift_res,
181 LIR_Opr::illegalOpr());
182 } else
183 #endif
184 {
185 __ move(xor_res, xor_shift_res);
186 __ unsigned_shift_right(xor_shift_res,
187 LIR_OprFact::intConst(checked_cast<jint>(G1HeapRegion::LogOfHRGrainBytes)),
188 xor_shift_res,
189 LIR_Opr::illegalOpr());
190 }
191 } else {
192 __ logical_xor(addr, new_val, xor_res);
193 #if INCLUDE_CDS
194 if (SCCache::is_on_for_write()) {
195 __ move(grain_shift_addr, grain_shift_reg);
196 __ move(grain_shift_indirect, grain_shift);
197 __ unsigned_shift_right(xor_res,
198 grain_shift,
199 xor_shift_res,
200 LIR_Opr::illegalOpr());
201 } else
202 #endif
203 {
204 __ unsigned_shift_right(xor_res,
205 LIR_OprFact::intConst(checked_cast<jint>(G1HeapRegion::LogOfHRGrainBytes)),
206 xor_shift_res,
207 LIR_Opr::illegalOpr());
208 }
209 }
210
211 __ cmp(lir_cond_notEqual, xor_shift_res, LIR_OprFact::intptrConst(NULL_WORD));
212
213 CodeStub* slow = new G1PostBarrierStub(addr, new_val);
214 __ branch(lir_cond_notEqual, slow);
215 __ branch_destination(slow->continuation());
216 }
217
218 void G1BarrierSetC1::load_at_resolved(LIRAccess& access, LIR_Opr result) {
219 DecoratorSet decorators = access.decorators();
220 bool is_weak = (decorators & ON_WEAK_OOP_REF) != 0;
221 bool is_phantom = (decorators & ON_PHANTOM_OOP_REF) != 0;
222 bool is_anonymous = (decorators & ON_UNKNOWN_OOP_REF) != 0;
223 LIRGenerator *gen = access.gen();
224
225 BarrierSetC1::load_at_resolved(access, result);
226
227 if (access.is_oop() && (is_weak || is_phantom || is_anonymous)) {
228 // Register the value in the referent field with the pre-barrier
229 LabelObj *Lcont_anonymous;
230 if (is_anonymous) {
231 Lcont_anonymous = new LabelObj();
232 generate_referent_check(access, Lcont_anonymous);
233 }
234 pre_barrier(access, LIR_OprFact::illegalOpr /* addr_opr */,
235 result /* pre_val */, access.patch_emit_info() /* info */);
236 if (is_anonymous) {
237 __ branch_destination(Lcont_anonymous->label());
238 }
239 }
240 }
241
242 class C1G1PreBarrierCodeGenClosure : public StubAssemblerCodeGenClosure {
243 virtual OopMapSet* generate_code(StubAssembler* sasm) {
244 G1BarrierSetAssembler* bs = (G1BarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
245 bs->generate_c1_pre_barrier_runtime_stub(sasm);
246 return nullptr;
247 }
248 };
249
250 class C1G1PostBarrierCodeGenClosure : public StubAssemblerCodeGenClosure {
251 virtual OopMapSet* generate_code(StubAssembler* sasm) {
252 G1BarrierSetAssembler* bs = (G1BarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
253 bs->generate_c1_post_barrier_runtime_stub(sasm);
254 return nullptr;
255 }
256 };
257
258 void G1BarrierSetC1::generate_c1_runtime_stubs(BufferBlob* buffer_blob) {
259 C1G1PreBarrierCodeGenClosure pre_code_gen_cl;
260 C1G1PostBarrierCodeGenClosure post_code_gen_cl;
261 _pre_barrier_c1_runtime_code_blob = Runtime1::generate_blob(buffer_blob, C1StubId::NO_STUBID, "g1_pre_barrier_slow",
262 false, &pre_code_gen_cl);
263 _post_barrier_c1_runtime_code_blob = Runtime1::generate_blob(buffer_blob, C1StubId::NO_STUBID, "g1_post_barrier_slow",
264 false, &post_code_gen_cl);
265 }