1 /* 2 * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "asm/assembler.hpp" 29 #include "c1/c1_CodeStubs.hpp" 30 #include "c1/c1_Compilation.hpp" 31 #include "c1/c1_LIRAssembler.hpp" 32 #include "c1/c1_MacroAssembler.hpp" 33 #include "c1/c1_Runtime1.hpp" 34 #include "c1/c1_ValueStack.hpp" 35 #include "ci/ciArrayKlass.hpp" 36 #include "ci/ciInstance.hpp" 37 #include "code/compiledIC.hpp" 38 #include "gc/shared/collectedHeap.hpp" 39 #include "gc/shared/gc_globals.hpp" 40 #include "nativeInst_aarch64.hpp" 41 #include "oops/objArrayKlass.hpp" 42 #include "runtime/frame.inline.hpp" 43 #include "runtime/sharedRuntime.hpp" 44 #include "runtime/stubRoutines.hpp" 45 #include "utilities/powerOfTwo.hpp" 46 #include "vmreg_aarch64.inline.hpp" 47 48 49 #ifndef PRODUCT 50 #define COMMENT(x) do { __ block_comment(x); } while (0) 51 #else 52 #define COMMENT(x) 53 #endif 54 55 NEEDS_CLEANUP // remove this definitions ? 56 const Register IC_Klass = rscratch2; // where the IC klass is cached 57 const Register SYNC_header = r0; // synchronization header 58 const Register SHIFT_count = r0; // where count for shift operations must be 59 60 #define __ _masm-> 61 62 63 static void select_different_registers(Register preserve, 64 Register extra, 65 Register &tmp1, 66 Register &tmp2) { 67 if (tmp1 == preserve) { 68 assert_different_registers(tmp1, tmp2, extra); 69 tmp1 = extra; 70 } else if (tmp2 == preserve) { 71 assert_different_registers(tmp1, tmp2, extra); 72 tmp2 = extra; 73 } 74 assert_different_registers(preserve, tmp1, tmp2); 75 } 76 77 78 79 static void select_different_registers(Register preserve, 80 Register extra, 81 Register &tmp1, 82 Register &tmp2, 83 Register &tmp3) { 84 if (tmp1 == preserve) { 85 assert_different_registers(tmp1, tmp2, tmp3, extra); 86 tmp1 = extra; 87 } else if (tmp2 == preserve) { 88 assert_different_registers(tmp1, tmp2, tmp3, extra); 89 tmp2 = extra; 90 } else if (tmp3 == preserve) { 91 assert_different_registers(tmp1, tmp2, tmp3, extra); 92 tmp3 = extra; 93 } 94 assert_different_registers(preserve, tmp1, tmp2, tmp3); 95 } 96 97 98 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; } 99 100 101 LIR_Opr LIR_Assembler::receiverOpr() { 102 return FrameMap::receiver_opr; 103 } 104 105 LIR_Opr LIR_Assembler::osrBufferPointer() { 106 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 107 } 108 109 //--------------fpu register translations----------------------- 110 111 112 address LIR_Assembler::float_constant(float f) { 113 address const_addr = __ float_constant(f); 114 if (const_addr == NULL) { 115 bailout("const section overflow"); 116 return __ code()->consts()->start(); 117 } else { 118 return const_addr; 119 } 120 } 121 122 123 address LIR_Assembler::double_constant(double d) { 124 address const_addr = __ double_constant(d); 125 if (const_addr == NULL) { 126 bailout("const section overflow"); 127 return __ code()->consts()->start(); 128 } else { 129 return const_addr; 130 } 131 } 132 133 address LIR_Assembler::int_constant(jlong n) { 134 address const_addr = __ long_constant(n); 135 if (const_addr == NULL) { 136 bailout("const section overflow"); 137 return __ code()->consts()->start(); 138 } else { 139 return const_addr; 140 } 141 } 142 143 void LIR_Assembler::breakpoint() { Unimplemented(); } 144 145 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); } 146 147 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); } 148 149 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; } 150 //------------------------------------------- 151 152 static Register as_reg(LIR_Opr op) { 153 return op->is_double_cpu() ? op->as_register_lo() : op->as_register(); 154 } 155 156 static jlong as_long(LIR_Opr data) { 157 jlong result; 158 switch (data->type()) { 159 case T_INT: 160 result = (data->as_jint()); 161 break; 162 case T_LONG: 163 result = (data->as_jlong()); 164 break; 165 default: 166 ShouldNotReachHere(); 167 result = 0; // unreachable 168 } 169 return result; 170 } 171 172 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 173 Register base = addr->base()->as_pointer_register(); 174 LIR_Opr opr = addr->index(); 175 if (opr->is_cpu_register()) { 176 Register index; 177 if (opr->is_single_cpu()) 178 index = opr->as_register(); 179 else 180 index = opr->as_register_lo(); 181 assert(addr->disp() == 0, "must be"); 182 switch(opr->type()) { 183 case T_INT: 184 return Address(base, index, Address::sxtw(addr->scale())); 185 case T_LONG: 186 return Address(base, index, Address::lsl(addr->scale())); 187 default: 188 ShouldNotReachHere(); 189 } 190 } else { 191 assert(addr->scale() == 0, 192 "expected for immediate operand, was: %d", addr->scale()); 193 ptrdiff_t offset = ptrdiff_t(addr->disp()); 194 // NOTE: Does not handle any 16 byte vector access. 195 const uint type_size = type2aelembytes(addr->type(), true); 196 return __ legitimize_address(Address(base, offset), type_size, tmp); 197 } 198 return Address(); 199 } 200 201 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 202 ShouldNotReachHere(); 203 return Address(); 204 } 205 206 Address LIR_Assembler::as_Address(LIR_Address* addr) { 207 return as_Address(addr, rscratch1); 208 } 209 210 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 211 return as_Address(addr, rscratch1); // Ouch 212 // FIXME: This needs to be much more clever. See x86. 213 } 214 215 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is 216 // not encodable as a base + (immediate) offset, generate an explicit address 217 // calculation to hold the address in a temporary register. 218 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) { 219 precond(size == 4 || size == 8); 220 Address addr = frame_map()->address_for_slot(index, adjust); 221 precond(addr.getMode() == Address::base_plus_offset); 222 precond(addr.base() == sp); 223 precond(addr.offset() > 0); 224 uint mask = size - 1; 225 assert((addr.offset() & mask) == 0, "scaled offsets only"); 226 return __ legitimize_address(addr, size, tmp); 227 } 228 229 void LIR_Assembler::osr_entry() { 230 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 231 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 232 ValueStack* entry_state = osr_entry->state(); 233 int number_of_locks = entry_state->locks_size(); 234 235 // we jump here if osr happens with the interpreter 236 // state set up to continue at the beginning of the 237 // loop that triggered osr - in particular, we have 238 // the following registers setup: 239 // 240 // r2: osr buffer 241 // 242 243 // build frame 244 ciMethod* m = compilation()->method(); 245 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 246 247 // OSR buffer is 248 // 249 // locals[nlocals-1..0] 250 // monitors[0..number_of_locks] 251 // 252 // locals is a direct copy of the interpreter frame so in the osr buffer 253 // so first slot in the local array is the last local from the interpreter 254 // and last slot is local[0] (receiver) from the interpreter 255 // 256 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 257 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 258 // in the interpreter frame (the method lock if a sync method) 259 260 // Initialize monitors in the compiled activation. 261 // r2: pointer to osr buffer 262 // 263 // All other registers are dead at this point and the locals will be 264 // copied into place by code emitted in the IR. 265 266 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 267 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 268 int monitor_offset = BytesPerWord * method()->max_locals() + 269 (2 * BytesPerWord) * (number_of_locks - 1); 270 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 271 // the OSR buffer using 2 word entries: first the lock and then 272 // the oop. 273 for (int i = 0; i < number_of_locks; i++) { 274 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 275 #ifdef ASSERT 276 // verify the interpreter's monitor has a non-null object 277 { 278 Label L; 279 __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 280 __ cbnz(rscratch1, L); 281 __ stop("locked object is NULL"); 282 __ bind(L); 283 } 284 #endif 285 __ ldp(r19, r20, Address(OSR_buf, slot_offset)); 286 __ str(r19, frame_map()->address_for_monitor_lock(i)); 287 __ str(r20, frame_map()->address_for_monitor_object(i)); 288 } 289 } 290 } 291 292 293 // inline cache check; done before the frame is built. 294 int LIR_Assembler::check_icache() { 295 Register receiver = FrameMap::receiver_opr->as_register(); 296 Register ic_klass = IC_Klass; 297 int start_offset = __ offset(); 298 __ inline_cache_check(receiver, ic_klass); 299 300 // if icache check fails, then jump to runtime routine 301 // Note: RECEIVER must still contain the receiver! 302 Label dont; 303 __ br(Assembler::EQ, dont); 304 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 305 306 // We align the verified entry point unless the method body 307 // (including its inline cache check) will fit in a single 64-byte 308 // icache line. 309 if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) { 310 // force alignment after the cache check. 311 __ align(CodeEntryAlignment); 312 } 313 314 __ bind(dont); 315 return start_offset; 316 } 317 318 void LIR_Assembler::clinit_barrier(ciMethod* method) { 319 assert(VM_Version::supports_fast_class_init_checks(), "sanity"); 320 assert(!method->holder()->is_not_initialized(), "initialization should have been started"); 321 322 Label L_skip_barrier; 323 324 __ mov_metadata(rscratch2, method->holder()->constant_encoding()); 325 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/); 326 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); 327 __ bind(L_skip_barrier); 328 } 329 330 void LIR_Assembler::jobject2reg(jobject o, Register reg) { 331 if (o == NULL) { 332 __ mov(reg, zr); 333 } else { 334 __ movoop(reg, o, /*immediate*/true); 335 } 336 } 337 338 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) { 339 address target = NULL; 340 relocInfo::relocType reloc_type = relocInfo::none; 341 342 switch (patching_id(info)) { 343 case PatchingStub::access_field_id: 344 target = Runtime1::entry_for(Runtime1::access_field_patching_id); 345 reloc_type = relocInfo::section_word_type; 346 break; 347 case PatchingStub::load_klass_id: 348 target = Runtime1::entry_for(Runtime1::load_klass_patching_id); 349 reloc_type = relocInfo::metadata_type; 350 break; 351 case PatchingStub::load_mirror_id: 352 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id); 353 reloc_type = relocInfo::oop_type; 354 break; 355 case PatchingStub::load_appendix_id: 356 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id); 357 reloc_type = relocInfo::oop_type; 358 break; 359 default: ShouldNotReachHere(); 360 } 361 362 __ far_call(RuntimeAddress(target)); 363 add_call_info_here(info); 364 } 365 366 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { 367 deoptimize_trap(info); 368 } 369 370 371 // This specifies the rsp decrement needed to build the frame 372 int LIR_Assembler::initial_frame_size_in_bytes() const { 373 // if rounding, must let FrameMap know! 374 375 return in_bytes(frame_map()->framesize_in_bytes()); 376 } 377 378 379 int LIR_Assembler::emit_exception_handler() { 380 // if the last instruction is a call (typically to do a throw which 381 // is coming at the end after block reordering) the return address 382 // must still point into the code area in order to avoid assertion 383 // failures when searching for the corresponding bci => add a nop 384 // (was bug 5/14/1999 - gri) 385 __ nop(); 386 387 // generate code for exception handler 388 address handler_base = __ start_a_stub(exception_handler_size()); 389 if (handler_base == NULL) { 390 // not enough space left for the handler 391 bailout("exception handler overflow"); 392 return -1; 393 } 394 395 int offset = code_offset(); 396 397 // the exception oop and pc are in r0, and r3 398 // no other registers need to be preserved, so invalidate them 399 __ invalidate_registers(false, true, true, false, true, true); 400 401 // check that there is really an exception 402 __ verify_not_null_oop(r0); 403 404 // search an exception handler (r0: exception oop, r3: throwing pc) 405 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); __ should_not_reach_here(); 406 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 407 __ end_a_stub(); 408 409 return offset; 410 } 411 412 413 // Emit the code to remove the frame from the stack in the exception 414 // unwind path. 415 int LIR_Assembler::emit_unwind_handler() { 416 #ifndef PRODUCT 417 if (CommentedAssembly) { 418 _masm->block_comment("Unwind handler"); 419 } 420 #endif 421 422 int offset = code_offset(); 423 424 // Fetch the exception from TLS and clear out exception related thread state 425 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset())); 426 __ str(zr, Address(rthread, JavaThread::exception_oop_offset())); 427 __ str(zr, Address(rthread, JavaThread::exception_pc_offset())); 428 429 __ bind(_unwind_handler_entry); 430 __ verify_not_null_oop(r0); 431 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 432 __ mov(r19, r0); // Preserve the exception 433 } 434 435 // Preform needed unlocking 436 MonitorExitStub* stub = NULL; 437 if (method()->is_synchronized()) { 438 monitor_address(0, FrameMap::r0_opr); 439 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0); 440 __ unlock_object(r5, r4, r0, *stub->entry()); 441 __ bind(*stub->continuation()); 442 } 443 444 if (compilation()->env()->dtrace_method_probes()) { 445 __ mov(c_rarg0, rthread); 446 __ mov_metadata(c_rarg1, method()->constant_encoding()); 447 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1); 448 } 449 450 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 451 __ mov(r0, r19); // Restore the exception 452 } 453 454 // remove the activation and dispatch to the unwind handler 455 __ block_comment("remove_frame and dispatch to the unwind handler"); 456 __ remove_frame(initial_frame_size_in_bytes()); 457 __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 458 459 // Emit the slow path assembly 460 if (stub != NULL) { 461 stub->emit_code(this); 462 } 463 464 return offset; 465 } 466 467 468 int LIR_Assembler::emit_deopt_handler() { 469 // if the last instruction is a call (typically to do a throw which 470 // is coming at the end after block reordering) the return address 471 // must still point into the code area in order to avoid assertion 472 // failures when searching for the corresponding bci => add a nop 473 // (was bug 5/14/1999 - gri) 474 __ nop(); 475 476 // generate code for exception handler 477 address handler_base = __ start_a_stub(deopt_handler_size()); 478 if (handler_base == NULL) { 479 // not enough space left for the handler 480 bailout("deopt handler overflow"); 481 return -1; 482 } 483 484 int offset = code_offset(); 485 486 __ adr(lr, pc()); 487 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 488 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 489 __ end_a_stub(); 490 491 return offset; 492 } 493 494 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) { 495 _masm->code_section()->relocate(adr, relocInfo::poll_type); 496 int pc_offset = code_offset(); 497 flush_debug_info(pc_offset); 498 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset); 499 if (info->exception_handlers() != NULL) { 500 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers()); 501 } 502 } 503 504 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) { 505 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,"); 506 507 // Pop the stack before the safepoint code 508 __ remove_frame(initial_frame_size_in_bytes()); 509 510 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 511 __ reserved_stack_check(); 512 } 513 514 code_stub->set_safepoint_offset(__ offset()); 515 __ relocate(relocInfo::poll_return_type); 516 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */); 517 __ ret(lr); 518 } 519 520 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 521 guarantee(info != NULL, "Shouldn't be NULL"); 522 __ get_polling_page(rscratch1, relocInfo::poll_type); 523 add_debug_info_for_branch(info); // This isn't just debug info: 524 // it's the oop map 525 __ read_polling_page(rscratch1, relocInfo::poll_type); 526 return __ offset(); 527 } 528 529 530 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 531 if (from_reg == r31_sp) 532 from_reg = sp; 533 if (to_reg == r31_sp) 534 to_reg = sp; 535 __ mov(to_reg, from_reg); 536 } 537 538 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); } 539 540 541 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 542 assert(src->is_constant(), "should not call otherwise"); 543 assert(dest->is_register(), "should not call otherwise"); 544 LIR_Const* c = src->as_constant_ptr(); 545 546 switch (c->type()) { 547 case T_INT: { 548 assert(patch_code == lir_patch_none, "no patching handled here"); 549 __ movw(dest->as_register(), c->as_jint()); 550 break; 551 } 552 553 case T_ADDRESS: { 554 assert(patch_code == lir_patch_none, "no patching handled here"); 555 __ mov(dest->as_register(), c->as_jint()); 556 break; 557 } 558 559 case T_LONG: { 560 assert(patch_code == lir_patch_none, "no patching handled here"); 561 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong()); 562 break; 563 } 564 565 case T_OBJECT: { 566 if (patch_code == lir_patch_none) { 567 jobject2reg(c->as_jobject(), dest->as_register()); 568 } else { 569 jobject2reg_with_patching(dest->as_register(), info); 570 } 571 break; 572 } 573 574 case T_METADATA: { 575 if (patch_code != lir_patch_none) { 576 klass2reg_with_patching(dest->as_register(), info); 577 } else { 578 __ mov_metadata(dest->as_register(), c->as_metadata()); 579 } 580 break; 581 } 582 583 case T_FLOAT: { 584 if (__ operand_valid_for_float_immediate(c->as_jfloat())) { 585 __ fmovs(dest->as_float_reg(), (c->as_jfloat())); 586 } else { 587 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat()))); 588 __ ldrs(dest->as_float_reg(), Address(rscratch1)); 589 } 590 break; 591 } 592 593 case T_DOUBLE: { 594 if (__ operand_valid_for_float_immediate(c->as_jdouble())) { 595 __ fmovd(dest->as_double_reg(), (c->as_jdouble())); 596 } else { 597 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble()))); 598 __ ldrd(dest->as_double_reg(), Address(rscratch1)); 599 } 600 break; 601 } 602 603 default: 604 ShouldNotReachHere(); 605 } 606 } 607 608 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 609 LIR_Const* c = src->as_constant_ptr(); 610 switch (c->type()) { 611 case T_OBJECT: 612 { 613 if (! c->as_jobject()) 614 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix())); 615 else { 616 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL); 617 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false); 618 } 619 } 620 break; 621 case T_ADDRESS: 622 { 623 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL); 624 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false); 625 } 626 case T_INT: 627 case T_FLOAT: 628 { 629 Register reg = zr; 630 if (c->as_jint_bits() == 0) 631 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix())); 632 else { 633 __ movw(rscratch1, c->as_jint_bits()); 634 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix())); 635 } 636 } 637 break; 638 case T_LONG: 639 case T_DOUBLE: 640 { 641 Register reg = zr; 642 if (c->as_jlong_bits() == 0) 643 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(), 644 lo_word_offset_in_bytes)); 645 else { 646 __ mov(rscratch1, (intptr_t)c->as_jlong_bits()); 647 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(), 648 lo_word_offset_in_bytes)); 649 } 650 } 651 break; 652 default: 653 ShouldNotReachHere(); 654 } 655 } 656 657 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 658 assert(src->is_constant(), "should not call otherwise"); 659 LIR_Const* c = src->as_constant_ptr(); 660 LIR_Address* to_addr = dest->as_address_ptr(); 661 662 void (Assembler::* insn)(Register Rt, const Address &adr); 663 664 switch (type) { 665 case T_ADDRESS: 666 assert(c->as_jint() == 0, "should be"); 667 insn = &Assembler::str; 668 break; 669 case T_LONG: 670 assert(c->as_jlong() == 0, "should be"); 671 insn = &Assembler::str; 672 break; 673 case T_INT: 674 assert(c->as_jint() == 0, "should be"); 675 insn = &Assembler::strw; 676 break; 677 case T_OBJECT: 678 case T_ARRAY: 679 assert(c->as_jobject() == 0, "should be"); 680 if (UseCompressedOops && !wide) { 681 insn = &Assembler::strw; 682 } else { 683 insn = &Assembler::str; 684 } 685 break; 686 case T_CHAR: 687 case T_SHORT: 688 assert(c->as_jint() == 0, "should be"); 689 insn = &Assembler::strh; 690 break; 691 case T_BOOLEAN: 692 case T_BYTE: 693 assert(c->as_jint() == 0, "should be"); 694 insn = &Assembler::strb; 695 break; 696 default: 697 ShouldNotReachHere(); 698 insn = &Assembler::str; // unreachable 699 } 700 701 if (info) add_debug_info_for_null_check_here(info); 702 (_masm->*insn)(zr, as_Address(to_addr, rscratch1)); 703 } 704 705 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 706 assert(src->is_register(), "should not call otherwise"); 707 assert(dest->is_register(), "should not call otherwise"); 708 709 // move between cpu-registers 710 if (dest->is_single_cpu()) { 711 if (src->type() == T_LONG) { 712 // Can do LONG -> OBJECT 713 move_regs(src->as_register_lo(), dest->as_register()); 714 return; 715 } 716 assert(src->is_single_cpu(), "must match"); 717 if (src->type() == T_OBJECT) { 718 __ verify_oop(src->as_register()); 719 } 720 move_regs(src->as_register(), dest->as_register()); 721 722 } else if (dest->is_double_cpu()) { 723 if (is_reference_type(src->type())) { 724 // Surprising to me but we can see move of a long to t_object 725 __ verify_oop(src->as_register()); 726 move_regs(src->as_register(), dest->as_register_lo()); 727 return; 728 } 729 assert(src->is_double_cpu(), "must match"); 730 Register f_lo = src->as_register_lo(); 731 Register f_hi = src->as_register_hi(); 732 Register t_lo = dest->as_register_lo(); 733 Register t_hi = dest->as_register_hi(); 734 assert(f_hi == f_lo, "must be same"); 735 assert(t_hi == t_lo, "must be same"); 736 move_regs(f_lo, t_lo); 737 738 } else if (dest->is_single_fpu()) { 739 __ fmovs(dest->as_float_reg(), src->as_float_reg()); 740 741 } else if (dest->is_double_fpu()) { 742 __ fmovd(dest->as_double_reg(), src->as_double_reg()); 743 744 } else { 745 ShouldNotReachHere(); 746 } 747 } 748 749 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 750 precond(src->is_register() && dest->is_stack()); 751 752 uint const c_sz32 = sizeof(uint32_t); 753 uint const c_sz64 = sizeof(uint64_t); 754 755 if (src->is_single_cpu()) { 756 int index = dest->single_stack_ix(); 757 if (is_reference_type(type)) { 758 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1)); 759 __ verify_oop(src->as_register()); 760 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) { 761 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1)); 762 } else { 763 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1)); 764 } 765 766 } else if (src->is_double_cpu()) { 767 int index = dest->double_stack_ix(); 768 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes); 769 __ str(src->as_register_lo(), dest_addr_LO); 770 771 } else if (src->is_single_fpu()) { 772 int index = dest->single_stack_ix(); 773 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1)); 774 775 } else if (src->is_double_fpu()) { 776 int index = dest->double_stack_ix(); 777 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1)); 778 779 } else { 780 ShouldNotReachHere(); 781 } 782 } 783 784 785 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { 786 LIR_Address* to_addr = dest->as_address_ptr(); 787 PatchingStub* patch = NULL; 788 Register compressed_src = rscratch1; 789 790 if (patch_code != lir_patch_none) { 791 deoptimize_trap(info); 792 return; 793 } 794 795 if (is_reference_type(type)) { 796 __ verify_oop(src->as_register()); 797 798 if (UseCompressedOops && !wide) { 799 __ encode_heap_oop(compressed_src, src->as_register()); 800 } else { 801 compressed_src = src->as_register(); 802 } 803 } 804 805 int null_check_here = code_offset(); 806 switch (type) { 807 case T_FLOAT: { 808 __ strs(src->as_float_reg(), as_Address(to_addr)); 809 break; 810 } 811 812 case T_DOUBLE: { 813 __ strd(src->as_double_reg(), as_Address(to_addr)); 814 break; 815 } 816 817 case T_ARRAY: // fall through 818 case T_OBJECT: // fall through 819 if (UseCompressedOops && !wide) { 820 __ strw(compressed_src, as_Address(to_addr, rscratch2)); 821 } else { 822 __ str(compressed_src, as_Address(to_addr)); 823 } 824 break; 825 case T_METADATA: 826 // We get here to store a method pointer to the stack to pass to 827 // a dtrace runtime call. This can't work on 64 bit with 828 // compressed klass ptrs: T_METADATA can be a compressed klass 829 // ptr or a 64 bit method pointer. 830 ShouldNotReachHere(); 831 __ str(src->as_register(), as_Address(to_addr)); 832 break; 833 case T_ADDRESS: 834 __ str(src->as_register(), as_Address(to_addr)); 835 break; 836 case T_INT: 837 __ strw(src->as_register(), as_Address(to_addr)); 838 break; 839 840 case T_LONG: { 841 __ str(src->as_register_lo(), as_Address_lo(to_addr)); 842 break; 843 } 844 845 case T_BYTE: // fall through 846 case T_BOOLEAN: { 847 __ strb(src->as_register(), as_Address(to_addr)); 848 break; 849 } 850 851 case T_CHAR: // fall through 852 case T_SHORT: 853 __ strh(src->as_register(), as_Address(to_addr)); 854 break; 855 856 default: 857 ShouldNotReachHere(); 858 } 859 if (info != NULL) { 860 add_debug_info_for_null_check(null_check_here, info); 861 } 862 } 863 864 865 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 866 precond(src->is_stack() && dest->is_register()); 867 868 uint const c_sz32 = sizeof(uint32_t); 869 uint const c_sz64 = sizeof(uint64_t); 870 871 if (dest->is_single_cpu()) { 872 int index = src->single_stack_ix(); 873 if (is_reference_type(type)) { 874 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1)); 875 __ verify_oop(dest->as_register()); 876 } else if (type == T_METADATA || type == T_ADDRESS) { 877 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1)); 878 } else { 879 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1)); 880 } 881 882 } else if (dest->is_double_cpu()) { 883 int index = src->double_stack_ix(); 884 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes); 885 __ ldr(dest->as_register_lo(), src_addr_LO); 886 887 } else if (dest->is_single_fpu()) { 888 int index = src->single_stack_ix(); 889 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1)); 890 891 } else if (dest->is_double_fpu()) { 892 int index = src->double_stack_ix(); 893 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1)); 894 895 } else { 896 ShouldNotReachHere(); 897 } 898 } 899 900 901 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { 902 address target = NULL; 903 relocInfo::relocType reloc_type = relocInfo::none; 904 905 switch (patching_id(info)) { 906 case PatchingStub::access_field_id: 907 target = Runtime1::entry_for(Runtime1::access_field_patching_id); 908 reloc_type = relocInfo::section_word_type; 909 break; 910 case PatchingStub::load_klass_id: 911 target = Runtime1::entry_for(Runtime1::load_klass_patching_id); 912 reloc_type = relocInfo::metadata_type; 913 break; 914 case PatchingStub::load_mirror_id: 915 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id); 916 reloc_type = relocInfo::oop_type; 917 break; 918 case PatchingStub::load_appendix_id: 919 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id); 920 reloc_type = relocInfo::oop_type; 921 break; 922 default: ShouldNotReachHere(); 923 } 924 925 __ far_call(RuntimeAddress(target)); 926 add_call_info_here(info); 927 } 928 929 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 930 931 LIR_Opr temp; 932 if (type == T_LONG || type == T_DOUBLE) 933 temp = FrameMap::rscratch1_long_opr; 934 else 935 temp = FrameMap::rscratch1_opr; 936 937 stack2reg(src, temp, src->type()); 938 reg2stack(temp, dest, dest->type(), false); 939 } 940 941 942 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { 943 LIR_Address* addr = src->as_address_ptr(); 944 LIR_Address* from_addr = src->as_address_ptr(); 945 946 if (addr->base()->type() == T_OBJECT) { 947 __ verify_oop(addr->base()->as_pointer_register()); 948 } 949 950 if (patch_code != lir_patch_none) { 951 deoptimize_trap(info); 952 return; 953 } 954 955 if (info != NULL) { 956 add_debug_info_for_null_check_here(info); 957 } 958 int null_check_here = code_offset(); 959 switch (type) { 960 case T_FLOAT: { 961 __ ldrs(dest->as_float_reg(), as_Address(from_addr)); 962 break; 963 } 964 965 case T_DOUBLE: { 966 __ ldrd(dest->as_double_reg(), as_Address(from_addr)); 967 break; 968 } 969 970 case T_ARRAY: // fall through 971 case T_OBJECT: // fall through 972 if (UseCompressedOops && !wide) { 973 __ ldrw(dest->as_register(), as_Address(from_addr)); 974 } else { 975 __ ldr(dest->as_register(), as_Address(from_addr)); 976 } 977 break; 978 case T_METADATA: 979 // We get here to store a method pointer to the stack to pass to 980 // a dtrace runtime call. This can't work on 64 bit with 981 // compressed klass ptrs: T_METADATA can be a compressed klass 982 // ptr or a 64 bit method pointer. 983 ShouldNotReachHere(); 984 __ ldr(dest->as_register(), as_Address(from_addr)); 985 break; 986 case T_ADDRESS: 987 // FIXME: OMG this is a horrible kludge. Any offset from an 988 // address that matches klass_offset_in_bytes() will be loaded 989 // as a word, not a long. 990 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) { 991 __ ldrw(dest->as_register(), as_Address(from_addr)); 992 } else { 993 __ ldr(dest->as_register(), as_Address(from_addr)); 994 } 995 break; 996 case T_INT: 997 __ ldrw(dest->as_register(), as_Address(from_addr)); 998 break; 999 1000 case T_LONG: { 1001 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr)); 1002 break; 1003 } 1004 1005 case T_BYTE: 1006 __ ldrsb(dest->as_register(), as_Address(from_addr)); 1007 break; 1008 case T_BOOLEAN: { 1009 __ ldrb(dest->as_register(), as_Address(from_addr)); 1010 break; 1011 } 1012 1013 case T_CHAR: 1014 __ ldrh(dest->as_register(), as_Address(from_addr)); 1015 break; 1016 case T_SHORT: 1017 __ ldrsh(dest->as_register(), as_Address(from_addr)); 1018 break; 1019 1020 default: 1021 ShouldNotReachHere(); 1022 } 1023 1024 if (is_reference_type(type)) { 1025 if (UseCompressedOops && !wide) { 1026 __ decode_heap_oop(dest->as_register()); 1027 } 1028 1029 if (!UseZGC) { 1030 // Load barrier has not yet been applied, so ZGC can't verify the oop here 1031 __ verify_oop(dest->as_register()); 1032 } 1033 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1034 if (UseCompressedClassPointers) { 1035 __ decode_klass_not_null(dest->as_register()); 1036 } 1037 } 1038 } 1039 1040 1041 int LIR_Assembler::array_element_size(BasicType type) const { 1042 int elem_size = type2aelembytes(type); 1043 return exact_log2(elem_size); 1044 } 1045 1046 1047 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1048 switch (op->code()) { 1049 case lir_idiv: 1050 case lir_irem: 1051 arithmetic_idiv(op->code(), 1052 op->in_opr1(), 1053 op->in_opr2(), 1054 op->in_opr3(), 1055 op->result_opr(), 1056 op->info()); 1057 break; 1058 case lir_fmad: 1059 __ fmaddd(op->result_opr()->as_double_reg(), 1060 op->in_opr1()->as_double_reg(), 1061 op->in_opr2()->as_double_reg(), 1062 op->in_opr3()->as_double_reg()); 1063 break; 1064 case lir_fmaf: 1065 __ fmadds(op->result_opr()->as_float_reg(), 1066 op->in_opr1()->as_float_reg(), 1067 op->in_opr2()->as_float_reg(), 1068 op->in_opr3()->as_float_reg()); 1069 break; 1070 default: ShouldNotReachHere(); break; 1071 } 1072 } 1073 1074 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1075 #ifdef ASSERT 1076 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1077 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1078 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1079 #endif 1080 1081 if (op->cond() == lir_cond_always) { 1082 if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1083 __ b(*(op->label())); 1084 } else { 1085 Assembler::Condition acond; 1086 if (op->code() == lir_cond_float_branch) { 1087 bool is_unordered = (op->ublock() == op->block()); 1088 // Assembler::EQ does not permit unordered branches, so we add 1089 // another branch here. Likewise, Assembler::NE does not permit 1090 // ordered branches. 1091 if ((is_unordered && op->cond() == lir_cond_equal) 1092 || (!is_unordered && op->cond() == lir_cond_notEqual)) 1093 __ br(Assembler::VS, *(op->ublock()->label())); 1094 switch(op->cond()) { 1095 case lir_cond_equal: acond = Assembler::EQ; break; 1096 case lir_cond_notEqual: acond = Assembler::NE; break; 1097 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break; 1098 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break; 1099 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break; 1100 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break; 1101 default: ShouldNotReachHere(); 1102 acond = Assembler::EQ; // unreachable 1103 } 1104 } else { 1105 switch (op->cond()) { 1106 case lir_cond_equal: acond = Assembler::EQ; break; 1107 case lir_cond_notEqual: acond = Assembler::NE; break; 1108 case lir_cond_less: acond = Assembler::LT; break; 1109 case lir_cond_lessEqual: acond = Assembler::LE; break; 1110 case lir_cond_greaterEqual: acond = Assembler::GE; break; 1111 case lir_cond_greater: acond = Assembler::GT; break; 1112 case lir_cond_belowEqual: acond = Assembler::LS; break; 1113 case lir_cond_aboveEqual: acond = Assembler::HS; break; 1114 default: ShouldNotReachHere(); 1115 acond = Assembler::EQ; // unreachable 1116 } 1117 } 1118 __ br(acond,*(op->label())); 1119 } 1120 } 1121 1122 1123 1124 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1125 LIR_Opr src = op->in_opr(); 1126 LIR_Opr dest = op->result_opr(); 1127 1128 switch (op->bytecode()) { 1129 case Bytecodes::_i2f: 1130 { 1131 __ scvtfws(dest->as_float_reg(), src->as_register()); 1132 break; 1133 } 1134 case Bytecodes::_i2d: 1135 { 1136 __ scvtfwd(dest->as_double_reg(), src->as_register()); 1137 break; 1138 } 1139 case Bytecodes::_l2d: 1140 { 1141 __ scvtfd(dest->as_double_reg(), src->as_register_lo()); 1142 break; 1143 } 1144 case Bytecodes::_l2f: 1145 { 1146 __ scvtfs(dest->as_float_reg(), src->as_register_lo()); 1147 break; 1148 } 1149 case Bytecodes::_f2d: 1150 { 1151 __ fcvts(dest->as_double_reg(), src->as_float_reg()); 1152 break; 1153 } 1154 case Bytecodes::_d2f: 1155 { 1156 __ fcvtd(dest->as_float_reg(), src->as_double_reg()); 1157 break; 1158 } 1159 case Bytecodes::_i2c: 1160 { 1161 __ ubfx(dest->as_register(), src->as_register(), 0, 16); 1162 break; 1163 } 1164 case Bytecodes::_i2l: 1165 { 1166 __ sxtw(dest->as_register_lo(), src->as_register()); 1167 break; 1168 } 1169 case Bytecodes::_i2s: 1170 { 1171 __ sxth(dest->as_register(), src->as_register()); 1172 break; 1173 } 1174 case Bytecodes::_i2b: 1175 { 1176 __ sxtb(dest->as_register(), src->as_register()); 1177 break; 1178 } 1179 case Bytecodes::_l2i: 1180 { 1181 _masm->block_comment("FIXME: This could be a no-op"); 1182 __ uxtw(dest->as_register(), src->as_register_lo()); 1183 break; 1184 } 1185 case Bytecodes::_d2l: 1186 { 1187 __ fcvtzd(dest->as_register_lo(), src->as_double_reg()); 1188 break; 1189 } 1190 case Bytecodes::_f2i: 1191 { 1192 __ fcvtzsw(dest->as_register(), src->as_float_reg()); 1193 break; 1194 } 1195 case Bytecodes::_f2l: 1196 { 1197 __ fcvtzs(dest->as_register_lo(), src->as_float_reg()); 1198 break; 1199 } 1200 case Bytecodes::_d2i: 1201 { 1202 __ fcvtzdw(dest->as_register(), src->as_double_reg()); 1203 break; 1204 } 1205 default: ShouldNotReachHere(); 1206 } 1207 } 1208 1209 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1210 if (op->init_check()) { 1211 __ ldrb(rscratch1, Address(op->klass()->as_register(), 1212 InstanceKlass::init_state_offset())); 1213 __ cmpw(rscratch1, InstanceKlass::fully_initialized); 1214 add_debug_info_for_null_check_here(op->stub()->info()); 1215 __ br(Assembler::NE, *op->stub()->entry()); 1216 } 1217 __ allocate_object(op->obj()->as_register(), 1218 op->tmp1()->as_register(), 1219 op->tmp2()->as_register(), 1220 op->header_size(), 1221 op->object_size(), 1222 op->klass()->as_register(), 1223 *op->stub()->entry()); 1224 __ bind(*op->stub()->continuation()); 1225 } 1226 1227 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1228 Register len = op->len()->as_register(); 1229 __ uxtw(len, len); 1230 1231 if (UseSlowPath || 1232 (!UseFastNewObjectArray && is_reference_type(op->type())) || 1233 (!UseFastNewTypeArray && !is_reference_type(op->type()))) { 1234 __ b(*op->stub()->entry()); 1235 } else { 1236 Register tmp1 = op->tmp1()->as_register(); 1237 Register tmp2 = op->tmp2()->as_register(); 1238 Register tmp3 = op->tmp3()->as_register(); 1239 if (len == tmp1) { 1240 tmp1 = tmp3; 1241 } else if (len == tmp2) { 1242 tmp2 = tmp3; 1243 } else if (len == tmp3) { 1244 // everything is ok 1245 } else { 1246 __ mov(tmp3, len); 1247 } 1248 __ allocate_array(op->obj()->as_register(), 1249 len, 1250 tmp1, 1251 tmp2, 1252 arrayOopDesc::header_size(op->type()), 1253 array_element_size(op->type()), 1254 op->klass()->as_register(), 1255 *op->stub()->entry()); 1256 } 1257 __ bind(*op->stub()->continuation()); 1258 } 1259 1260 void LIR_Assembler::type_profile_helper(Register mdo, 1261 ciMethodData *md, ciProfileData *data, 1262 Register recv, Label* update_done) { 1263 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1264 Label next_test; 1265 // See if the receiver is receiver[n]. 1266 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1267 __ ldr(rscratch1, Address(rscratch2)); 1268 __ cmp(recv, rscratch1); 1269 __ br(Assembler::NE, next_test); 1270 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1271 __ addptr(data_addr, DataLayout::counter_increment); 1272 __ b(*update_done); 1273 __ bind(next_test); 1274 } 1275 1276 // Didn't find receiver; find next empty slot and fill it in 1277 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1278 Label next_test; 1279 __ lea(rscratch2, 1280 Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1281 Address recv_addr(rscratch2); 1282 __ ldr(rscratch1, recv_addr); 1283 __ cbnz(rscratch1, next_test); 1284 __ str(recv, recv_addr); 1285 __ mov(rscratch1, DataLayout::counter_increment); 1286 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)))); 1287 __ str(rscratch1, Address(rscratch2)); 1288 __ b(*update_done); 1289 __ bind(next_test); 1290 } 1291 } 1292 1293 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1294 // we always need a stub for the failure case. 1295 CodeStub* stub = op->stub(); 1296 Register obj = op->object()->as_register(); 1297 Register k_RInfo = op->tmp1()->as_register(); 1298 Register klass_RInfo = op->tmp2()->as_register(); 1299 Register dst = op->result_opr()->as_register(); 1300 ciKlass* k = op->klass(); 1301 Register Rtmp1 = noreg; 1302 1303 // check if it needs to be profiled 1304 ciMethodData* md; 1305 ciProfileData* data; 1306 1307 const bool should_profile = op->should_profile(); 1308 1309 if (should_profile) { 1310 ciMethod* method = op->profiled_method(); 1311 assert(method != NULL, "Should have method"); 1312 int bci = op->profiled_bci(); 1313 md = method->method_data_or_null(); 1314 assert(md != NULL, "Sanity"); 1315 data = md->bci_to_data(bci); 1316 assert(data != NULL, "need data for type check"); 1317 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1318 } 1319 Label profile_cast_success, profile_cast_failure; 1320 Label *success_target = should_profile ? &profile_cast_success : success; 1321 Label *failure_target = should_profile ? &profile_cast_failure : failure; 1322 1323 if (obj == k_RInfo) { 1324 k_RInfo = dst; 1325 } else if (obj == klass_RInfo) { 1326 klass_RInfo = dst; 1327 } 1328 if (k->is_loaded() && !UseCompressedClassPointers) { 1329 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1330 } else { 1331 Rtmp1 = op->tmp3()->as_register(); 1332 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1333 } 1334 1335 assert_different_registers(obj, k_RInfo, klass_RInfo); 1336 1337 if (should_profile) { 1338 Label not_null; 1339 __ cbnz(obj, not_null); 1340 // Object is null; update MDO and exit 1341 Register mdo = klass_RInfo; 1342 __ mov_metadata(mdo, md->constant_encoding()); 1343 Address data_addr 1344 = __ form_address(rscratch2, mdo, 1345 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 1346 0); 1347 __ ldrb(rscratch1, data_addr); 1348 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant()); 1349 __ strb(rscratch1, data_addr); 1350 __ b(*obj_is_null); 1351 __ bind(not_null); 1352 } else { 1353 __ cbz(obj, *obj_is_null); 1354 } 1355 1356 if (!k->is_loaded()) { 1357 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 1358 } else { 1359 __ mov_metadata(k_RInfo, k->constant_encoding()); 1360 } 1361 __ verify_oop(obj); 1362 1363 if (op->fast_check()) { 1364 // get object class 1365 // not a safepoint as obj null check happens earlier 1366 __ load_klass(rscratch1, obj); 1367 __ cmp( rscratch1, k_RInfo); 1368 1369 __ br(Assembler::NE, *failure_target); 1370 // successful cast, fall through to profile or jump 1371 } else { 1372 // get object class 1373 // not a safepoint as obj null check happens earlier 1374 __ load_klass(klass_RInfo, obj); 1375 if (k->is_loaded()) { 1376 // See if we get an immediate positive hit 1377 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset()))); 1378 __ cmp(k_RInfo, rscratch1); 1379 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1380 __ br(Assembler::NE, *failure_target); 1381 // successful cast, fall through to profile or jump 1382 } else { 1383 // See if we get an immediate positive hit 1384 __ br(Assembler::EQ, *success_target); 1385 // check for self 1386 __ cmp(klass_RInfo, k_RInfo); 1387 __ br(Assembler::EQ, *success_target); 1388 1389 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize))); 1390 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1391 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize))); 1392 // result is a boolean 1393 __ cbzw(klass_RInfo, *failure_target); 1394 // successful cast, fall through to profile or jump 1395 } 1396 } else { 1397 // perform the fast part of the checking logic 1398 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1399 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1400 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize))); 1401 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1402 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize))); 1403 // result is a boolean 1404 __ cbz(k_RInfo, *failure_target); 1405 // successful cast, fall through to profile or jump 1406 } 1407 } 1408 if (should_profile) { 1409 Register mdo = klass_RInfo, recv = k_RInfo; 1410 __ bind(profile_cast_success); 1411 __ mov_metadata(mdo, md->constant_encoding()); 1412 __ load_klass(recv, obj); 1413 Label update_done; 1414 type_profile_helper(mdo, md, data, recv, success); 1415 __ b(*success); 1416 1417 __ bind(profile_cast_failure); 1418 __ mov_metadata(mdo, md->constant_encoding()); 1419 Address counter_addr 1420 = __ form_address(rscratch2, mdo, 1421 md->byte_offset_of_slot(data, CounterData::count_offset()), 1422 0); 1423 __ ldr(rscratch1, counter_addr); 1424 __ sub(rscratch1, rscratch1, DataLayout::counter_increment); 1425 __ str(rscratch1, counter_addr); 1426 __ b(*failure); 1427 } 1428 __ b(*success); 1429 } 1430 1431 1432 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1433 const bool should_profile = op->should_profile(); 1434 1435 LIR_Code code = op->code(); 1436 if (code == lir_store_check) { 1437 Register value = op->object()->as_register(); 1438 Register array = op->array()->as_register(); 1439 Register k_RInfo = op->tmp1()->as_register(); 1440 Register klass_RInfo = op->tmp2()->as_register(); 1441 Register Rtmp1 = op->tmp3()->as_register(); 1442 1443 CodeStub* stub = op->stub(); 1444 1445 // check if it needs to be profiled 1446 ciMethodData* md; 1447 ciProfileData* data; 1448 1449 if (should_profile) { 1450 ciMethod* method = op->profiled_method(); 1451 assert(method != NULL, "Should have method"); 1452 int bci = op->profiled_bci(); 1453 md = method->method_data_or_null(); 1454 assert(md != NULL, "Sanity"); 1455 data = md->bci_to_data(bci); 1456 assert(data != NULL, "need data for type check"); 1457 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1458 } 1459 Label profile_cast_success, profile_cast_failure, done; 1460 Label *success_target = should_profile ? &profile_cast_success : &done; 1461 Label *failure_target = should_profile ? &profile_cast_failure : stub->entry(); 1462 1463 if (should_profile) { 1464 Label not_null; 1465 __ cbnz(value, not_null); 1466 // Object is null; update MDO and exit 1467 Register mdo = klass_RInfo; 1468 __ mov_metadata(mdo, md->constant_encoding()); 1469 Address data_addr 1470 = __ form_address(rscratch2, mdo, 1471 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 1472 0); 1473 __ ldrb(rscratch1, data_addr); 1474 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant()); 1475 __ strb(rscratch1, data_addr); 1476 __ b(done); 1477 __ bind(not_null); 1478 } else { 1479 __ cbz(value, done); 1480 } 1481 1482 add_debug_info_for_null_check_here(op->info_for_exception()); 1483 __ load_klass(k_RInfo, array); 1484 __ load_klass(klass_RInfo, value); 1485 1486 // get instance klass (it's already uncompressed) 1487 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 1488 // perform the fast part of the checking logic 1489 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1490 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1491 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize))); 1492 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1493 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize))); 1494 // result is a boolean 1495 __ cbzw(k_RInfo, *failure_target); 1496 // fall through to the success case 1497 1498 if (should_profile) { 1499 Register mdo = klass_RInfo, recv = k_RInfo; 1500 __ bind(profile_cast_success); 1501 __ mov_metadata(mdo, md->constant_encoding()); 1502 __ load_klass(recv, value); 1503 Label update_done; 1504 type_profile_helper(mdo, md, data, recv, &done); 1505 __ b(done); 1506 1507 __ bind(profile_cast_failure); 1508 __ mov_metadata(mdo, md->constant_encoding()); 1509 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1510 __ lea(rscratch2, counter_addr); 1511 __ ldr(rscratch1, Address(rscratch2)); 1512 __ sub(rscratch1, rscratch1, DataLayout::counter_increment); 1513 __ str(rscratch1, Address(rscratch2)); 1514 __ b(*stub->entry()); 1515 } 1516 1517 __ bind(done); 1518 } else if (code == lir_checkcast) { 1519 Register obj = op->object()->as_register(); 1520 Register dst = op->result_opr()->as_register(); 1521 Label success; 1522 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1523 __ bind(success); 1524 if (dst != obj) { 1525 __ mov(dst, obj); 1526 } 1527 } else if (code == lir_instanceof) { 1528 Register obj = op->object()->as_register(); 1529 Register dst = op->result_opr()->as_register(); 1530 Label success, failure, done; 1531 emit_typecheck_helper(op, &success, &failure, &failure); 1532 __ bind(failure); 1533 __ mov(dst, zr); 1534 __ b(done); 1535 __ bind(success); 1536 __ mov(dst, 1); 1537 __ bind(done); 1538 } else { 1539 ShouldNotReachHere(); 1540 } 1541 } 1542 1543 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) { 1544 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1); 1545 __ cset(rscratch1, Assembler::NE); 1546 __ membar(__ AnyAny); 1547 } 1548 1549 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) { 1550 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1); 1551 __ cset(rscratch1, Assembler::NE); 1552 __ membar(__ AnyAny); 1553 } 1554 1555 1556 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1557 assert(VM_Version::supports_cx8(), "wrong machine"); 1558 Register addr; 1559 if (op->addr()->is_register()) { 1560 addr = as_reg(op->addr()); 1561 } else { 1562 assert(op->addr()->is_address(), "what else?"); 1563 LIR_Address* addr_ptr = op->addr()->as_address_ptr(); 1564 assert(addr_ptr->disp() == 0, "need 0 disp"); 1565 assert(addr_ptr->index() == LIR_OprDesc::illegalOpr(), "need 0 index"); 1566 addr = as_reg(addr_ptr->base()); 1567 } 1568 Register newval = as_reg(op->new_value()); 1569 Register cmpval = as_reg(op->cmp_value()); 1570 1571 if (op->code() == lir_cas_obj) { 1572 if (UseCompressedOops) { 1573 Register t1 = op->tmp1()->as_register(); 1574 assert(op->tmp1()->is_valid(), "must be"); 1575 __ encode_heap_oop(t1, cmpval); 1576 cmpval = t1; 1577 __ encode_heap_oop(rscratch2, newval); 1578 newval = rscratch2; 1579 casw(addr, newval, cmpval); 1580 } else { 1581 casl(addr, newval, cmpval); 1582 } 1583 } else if (op->code() == lir_cas_int) { 1584 casw(addr, newval, cmpval); 1585 } else { 1586 casl(addr, newval, cmpval); 1587 } 1588 } 1589 1590 1591 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1592 1593 Assembler::Condition acond, ncond; 1594 switch (condition) { 1595 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break; 1596 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break; 1597 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break; 1598 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break; 1599 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break; 1600 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break; 1601 case lir_cond_belowEqual: 1602 case lir_cond_aboveEqual: 1603 default: ShouldNotReachHere(); 1604 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable 1605 } 1606 1607 assert(result->is_single_cpu() || result->is_double_cpu(), 1608 "expect single register for result"); 1609 if (opr1->is_constant() && opr2->is_constant() 1610 && opr1->type() == T_INT && opr2->type() == T_INT) { 1611 jint val1 = opr1->as_jint(); 1612 jint val2 = opr2->as_jint(); 1613 if (val1 == 0 && val2 == 1) { 1614 __ cset(result->as_register(), ncond); 1615 return; 1616 } else if (val1 == 1 && val2 == 0) { 1617 __ cset(result->as_register(), acond); 1618 return; 1619 } 1620 } 1621 1622 if (opr1->is_constant() && opr2->is_constant() 1623 && opr1->type() == T_LONG && opr2->type() == T_LONG) { 1624 jlong val1 = opr1->as_jlong(); 1625 jlong val2 = opr2->as_jlong(); 1626 if (val1 == 0 && val2 == 1) { 1627 __ cset(result->as_register_lo(), ncond); 1628 return; 1629 } else if (val1 == 1 && val2 == 0) { 1630 __ cset(result->as_register_lo(), acond); 1631 return; 1632 } 1633 } 1634 1635 if (opr1->is_stack()) { 1636 stack2reg(opr1, FrameMap::rscratch1_opr, result->type()); 1637 opr1 = FrameMap::rscratch1_opr; 1638 } else if (opr1->is_constant()) { 1639 LIR_Opr tmp 1640 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr; 1641 const2reg(opr1, tmp, lir_patch_none, NULL); 1642 opr1 = tmp; 1643 } 1644 1645 if (opr2->is_stack()) { 1646 stack2reg(opr2, FrameMap::rscratch2_opr, result->type()); 1647 opr2 = FrameMap::rscratch2_opr; 1648 } else if (opr2->is_constant()) { 1649 LIR_Opr tmp 1650 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr; 1651 const2reg(opr2, tmp, lir_patch_none, NULL); 1652 opr2 = tmp; 1653 } 1654 1655 if (result->type() == T_LONG) 1656 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond); 1657 else 1658 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond); 1659 } 1660 1661 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 1662 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 1663 1664 if (left->is_single_cpu()) { 1665 Register lreg = left->as_register(); 1666 Register dreg = as_reg(dest); 1667 1668 if (right->is_single_cpu()) { 1669 // cpu register - cpu register 1670 1671 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT, 1672 "should be"); 1673 Register rreg = right->as_register(); 1674 switch (code) { 1675 case lir_add: __ addw (dest->as_register(), lreg, rreg); break; 1676 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break; 1677 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break; 1678 default: ShouldNotReachHere(); 1679 } 1680 1681 } else if (right->is_double_cpu()) { 1682 Register rreg = right->as_register_lo(); 1683 // single_cpu + double_cpu: can happen with obj+long 1684 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op"); 1685 switch (code) { 1686 case lir_add: __ add(dreg, lreg, rreg); break; 1687 case lir_sub: __ sub(dreg, lreg, rreg); break; 1688 default: ShouldNotReachHere(); 1689 } 1690 } else if (right->is_constant()) { 1691 // cpu register - constant 1692 jlong c; 1693 1694 // FIXME. This is fugly: we really need to factor all this logic. 1695 switch(right->type()) { 1696 case T_LONG: 1697 c = right->as_constant_ptr()->as_jlong(); 1698 break; 1699 case T_INT: 1700 case T_ADDRESS: 1701 c = right->as_constant_ptr()->as_jint(); 1702 break; 1703 default: 1704 ShouldNotReachHere(); 1705 c = 0; // unreachable 1706 break; 1707 } 1708 1709 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op"); 1710 if (c == 0 && dreg == lreg) { 1711 COMMENT("effective nop elided"); 1712 return; 1713 } 1714 switch(left->type()) { 1715 case T_INT: 1716 switch (code) { 1717 case lir_add: __ addw(dreg, lreg, c); break; 1718 case lir_sub: __ subw(dreg, lreg, c); break; 1719 default: ShouldNotReachHere(); 1720 } 1721 break; 1722 case T_OBJECT: 1723 case T_ADDRESS: 1724 switch (code) { 1725 case lir_add: __ add(dreg, lreg, c); break; 1726 case lir_sub: __ sub(dreg, lreg, c); break; 1727 default: ShouldNotReachHere(); 1728 } 1729 break; 1730 default: 1731 ShouldNotReachHere(); 1732 } 1733 } else { 1734 ShouldNotReachHere(); 1735 } 1736 1737 } else if (left->is_double_cpu()) { 1738 Register lreg_lo = left->as_register_lo(); 1739 1740 if (right->is_double_cpu()) { 1741 // cpu register - cpu register 1742 Register rreg_lo = right->as_register_lo(); 1743 switch (code) { 1744 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break; 1745 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break; 1746 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break; 1747 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break; 1748 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break; 1749 default: 1750 ShouldNotReachHere(); 1751 } 1752 1753 } else if (right->is_constant()) { 1754 jlong c = right->as_constant_ptr()->as_jlong(); 1755 Register dreg = as_reg(dest); 1756 switch (code) { 1757 case lir_add: 1758 case lir_sub: 1759 if (c == 0 && dreg == lreg_lo) { 1760 COMMENT("effective nop elided"); 1761 return; 1762 } 1763 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c); 1764 break; 1765 case lir_div: 1766 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant"); 1767 if (c == 1) { 1768 // move lreg_lo to dreg if divisor is 1 1769 __ mov(dreg, lreg_lo); 1770 } else { 1771 unsigned int shift = log2i_exact(c); 1772 // use rscratch1 as intermediate result register 1773 __ asr(rscratch1, lreg_lo, 63); 1774 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift); 1775 __ asr(dreg, rscratch1, shift); 1776 } 1777 break; 1778 case lir_rem: 1779 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant"); 1780 if (c == 1) { 1781 // move 0 to dreg if divisor is 1 1782 __ mov(dreg, zr); 1783 } else { 1784 // use rscratch1 as intermediate result register 1785 __ negs(rscratch1, lreg_lo); 1786 __ andr(dreg, lreg_lo, c - 1); 1787 __ andr(rscratch1, rscratch1, c - 1); 1788 __ csneg(dreg, dreg, rscratch1, Assembler::MI); 1789 } 1790 break; 1791 default: 1792 ShouldNotReachHere(); 1793 } 1794 } else { 1795 ShouldNotReachHere(); 1796 } 1797 } else if (left->is_single_fpu()) { 1798 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register"); 1799 switch (code) { 1800 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; 1801 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; 1802 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; 1803 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break; 1804 default: 1805 ShouldNotReachHere(); 1806 } 1807 } else if (left->is_double_fpu()) { 1808 if (right->is_double_fpu()) { 1809 // fpu register - fpu register 1810 switch (code) { 1811 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; 1812 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; 1813 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; 1814 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break; 1815 default: 1816 ShouldNotReachHere(); 1817 } 1818 } else { 1819 if (right->is_constant()) { 1820 ShouldNotReachHere(); 1821 } 1822 ShouldNotReachHere(); 1823 } 1824 } else if (left->is_single_stack() || left->is_address()) { 1825 assert(left == dest, "left and dest must be equal"); 1826 ShouldNotReachHere(); 1827 } else { 1828 ShouldNotReachHere(); 1829 } 1830 } 1831 1832 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); } 1833 1834 1835 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { 1836 switch(code) { 1837 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break; 1838 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break; 1839 default : ShouldNotReachHere(); 1840 } 1841 } 1842 1843 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 1844 1845 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register"); 1846 Register Rleft = left->is_single_cpu() ? left->as_register() : 1847 left->as_register_lo(); 1848 if (dst->is_single_cpu()) { 1849 Register Rdst = dst->as_register(); 1850 if (right->is_constant()) { 1851 switch (code) { 1852 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break; 1853 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break; 1854 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break; 1855 default: ShouldNotReachHere(); break; 1856 } 1857 } else { 1858 Register Rright = right->is_single_cpu() ? right->as_register() : 1859 right->as_register_lo(); 1860 switch (code) { 1861 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break; 1862 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break; 1863 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break; 1864 default: ShouldNotReachHere(); break; 1865 } 1866 } 1867 } else { 1868 Register Rdst = dst->as_register_lo(); 1869 if (right->is_constant()) { 1870 switch (code) { 1871 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break; 1872 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break; 1873 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break; 1874 default: ShouldNotReachHere(); break; 1875 } 1876 } else { 1877 Register Rright = right->is_single_cpu() ? right->as_register() : 1878 right->as_register_lo(); 1879 switch (code) { 1880 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break; 1881 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break; 1882 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break; 1883 default: ShouldNotReachHere(); break; 1884 } 1885 } 1886 } 1887 } 1888 1889 1890 1891 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) { 1892 1893 // opcode check 1894 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem"); 1895 bool is_irem = (code == lir_irem); 1896 1897 // operand check 1898 assert(left->is_single_cpu(), "left must be register"); 1899 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 1900 assert(result->is_single_cpu(), "result must be register"); 1901 Register lreg = left->as_register(); 1902 Register dreg = result->as_register(); 1903 1904 // power-of-2 constant check and codegen 1905 if (right->is_constant()) { 1906 int c = right->as_constant_ptr()->as_jint(); 1907 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant"); 1908 if (is_irem) { 1909 if (c == 1) { 1910 // move 0 to dreg if divisor is 1 1911 __ movw(dreg, zr); 1912 } else { 1913 // use rscratch1 as intermediate result register 1914 __ negsw(rscratch1, lreg); 1915 __ andw(dreg, lreg, c - 1); 1916 __ andw(rscratch1, rscratch1, c - 1); 1917 __ csnegw(dreg, dreg, rscratch1, Assembler::MI); 1918 } 1919 } else { 1920 if (c == 1) { 1921 // move lreg to dreg if divisor is 1 1922 __ movw(dreg, lreg); 1923 } else { 1924 unsigned int shift = exact_log2(c); 1925 // use rscratch1 as intermediate result register 1926 __ asrw(rscratch1, lreg, 31); 1927 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift); 1928 __ asrw(dreg, rscratch1, shift); 1929 } 1930 } 1931 } else { 1932 Register rreg = right->as_register(); 1933 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1); 1934 } 1935 } 1936 1937 1938 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 1939 if (opr1->is_constant() && opr2->is_single_cpu()) { 1940 // tableswitch 1941 Register reg = as_reg(opr2); 1942 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()]; 1943 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after); 1944 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) { 1945 Register reg1 = as_reg(opr1); 1946 if (opr2->is_single_cpu()) { 1947 // cpu register - cpu register 1948 Register reg2 = opr2->as_register(); 1949 if (is_reference_type(opr1->type())) { 1950 __ cmpoop(reg1, reg2); 1951 } else { 1952 assert(!is_reference_type(opr2->type()), "cmp int, oop?"); 1953 __ cmpw(reg1, reg2); 1954 } 1955 return; 1956 } 1957 if (opr2->is_double_cpu()) { 1958 // cpu register - cpu register 1959 Register reg2 = opr2->as_register_lo(); 1960 __ cmp(reg1, reg2); 1961 return; 1962 } 1963 1964 if (opr2->is_constant()) { 1965 bool is_32bit = false; // width of register operand 1966 jlong imm; 1967 1968 switch(opr2->type()) { 1969 case T_INT: 1970 imm = opr2->as_constant_ptr()->as_jint(); 1971 is_32bit = true; 1972 break; 1973 case T_LONG: 1974 imm = opr2->as_constant_ptr()->as_jlong(); 1975 break; 1976 case T_ADDRESS: 1977 imm = opr2->as_constant_ptr()->as_jint(); 1978 break; 1979 case T_METADATA: 1980 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata()); 1981 break; 1982 case T_OBJECT: 1983 case T_ARRAY: 1984 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1); 1985 __ cmpoop(reg1, rscratch1); 1986 return; 1987 default: 1988 ShouldNotReachHere(); 1989 imm = 0; // unreachable 1990 break; 1991 } 1992 1993 if (Assembler::operand_valid_for_add_sub_immediate(imm)) { 1994 if (is_32bit) 1995 __ cmpw(reg1, imm); 1996 else 1997 __ subs(zr, reg1, imm); 1998 return; 1999 } else { 2000 __ mov(rscratch1, imm); 2001 if (is_32bit) 2002 __ cmpw(reg1, rscratch1); 2003 else 2004 __ cmp(reg1, rscratch1); 2005 return; 2006 } 2007 } else 2008 ShouldNotReachHere(); 2009 } else if (opr1->is_single_fpu()) { 2010 FloatRegister reg1 = opr1->as_float_reg(); 2011 assert(opr2->is_single_fpu(), "expect single float register"); 2012 FloatRegister reg2 = opr2->as_float_reg(); 2013 __ fcmps(reg1, reg2); 2014 } else if (opr1->is_double_fpu()) { 2015 FloatRegister reg1 = opr1->as_double_reg(); 2016 assert(opr2->is_double_fpu(), "expect double float register"); 2017 FloatRegister reg2 = opr2->as_double_reg(); 2018 __ fcmpd(reg1, reg2); 2019 } else { 2020 ShouldNotReachHere(); 2021 } 2022 } 2023 2024 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ 2025 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2026 bool is_unordered_less = (code == lir_ucmp_fd2i); 2027 if (left->is_single_fpu()) { 2028 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register()); 2029 } else if (left->is_double_fpu()) { 2030 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register()); 2031 } else { 2032 ShouldNotReachHere(); 2033 } 2034 } else if (code == lir_cmp_l2i) { 2035 Label done; 2036 __ cmp(left->as_register_lo(), right->as_register_lo()); 2037 __ mov(dst->as_register(), (uint64_t)-1L); 2038 __ br(Assembler::LT, done); 2039 __ csinc(dst->as_register(), zr, zr, Assembler::EQ); 2040 __ bind(done); 2041 } else { 2042 ShouldNotReachHere(); 2043 } 2044 } 2045 2046 2047 void LIR_Assembler::align_call(LIR_Code code) { } 2048 2049 2050 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2051 address call = __ trampoline_call(Address(op->addr(), rtype)); 2052 if (call == NULL) { 2053 bailout("trampoline stub overflow"); 2054 return; 2055 } 2056 add_call_info(code_offset(), op->info()); 2057 } 2058 2059 2060 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2061 address call = __ ic_call(op->addr()); 2062 if (call == NULL) { 2063 bailout("trampoline stub overflow"); 2064 return; 2065 } 2066 add_call_info(code_offset(), op->info()); 2067 } 2068 2069 void LIR_Assembler::emit_static_call_stub() { 2070 address call_pc = __ pc(); 2071 address stub = __ start_a_stub(call_stub_size()); 2072 if (stub == NULL) { 2073 bailout("static call stub overflow"); 2074 return; 2075 } 2076 2077 int start = __ offset(); 2078 2079 __ relocate(static_stub_Relocation::spec(call_pc)); 2080 __ emit_static_call_stub(); 2081 2082 assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size() 2083 <= call_stub_size(), "stub too big"); 2084 __ end_a_stub(); 2085 } 2086 2087 2088 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2089 assert(exceptionOop->as_register() == r0, "must match"); 2090 assert(exceptionPC->as_register() == r3, "must match"); 2091 2092 // exception object is not added to oop map by LinearScan 2093 // (LinearScan assumes that no oops are in fixed registers) 2094 info->add_register_oop(exceptionOop); 2095 Runtime1::StubID unwind_id; 2096 2097 // get current pc information 2098 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2099 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) { 2100 // As no instructions have been generated yet for this LIR node it's 2101 // possible that an oop map already exists for the current offset. 2102 // In that case insert an dummy NOP here to ensure all oop map PCs 2103 // are unique. See JDK-8237483. 2104 __ nop(); 2105 } 2106 int pc_for_athrow_offset = __ offset(); 2107 InternalAddress pc_for_athrow(__ pc()); 2108 __ adr(exceptionPC->as_register(), pc_for_athrow); 2109 add_call_info(pc_for_athrow_offset, info); // for exception handler 2110 2111 __ verify_not_null_oop(r0); 2112 // search an exception handler (r0: exception oop, r3: throwing pc) 2113 if (compilation()->has_fpu_code()) { 2114 unwind_id = Runtime1::handle_exception_id; 2115 } else { 2116 unwind_id = Runtime1::handle_exception_nofpu_id; 2117 } 2118 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2119 2120 // FIXME: enough room for two byte trap ???? 2121 __ nop(); 2122 } 2123 2124 2125 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2126 assert(exceptionOop->as_register() == r0, "must match"); 2127 2128 __ b(_unwind_handler_entry); 2129 } 2130 2131 2132 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2133 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo(); 2134 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo(); 2135 2136 switch (left->type()) { 2137 case T_INT: { 2138 switch (code) { 2139 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break; 2140 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break; 2141 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break; 2142 default: 2143 ShouldNotReachHere(); 2144 break; 2145 } 2146 break; 2147 case T_LONG: 2148 case T_ADDRESS: 2149 case T_OBJECT: 2150 switch (code) { 2151 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break; 2152 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break; 2153 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break; 2154 default: 2155 ShouldNotReachHere(); 2156 break; 2157 } 2158 break; 2159 default: 2160 ShouldNotReachHere(); 2161 break; 2162 } 2163 } 2164 } 2165 2166 2167 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2168 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo(); 2169 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo(); 2170 2171 switch (left->type()) { 2172 case T_INT: { 2173 switch (code) { 2174 case lir_shl: __ lslw (dreg, lreg, count); break; 2175 case lir_shr: __ asrw (dreg, lreg, count); break; 2176 case lir_ushr: __ lsrw (dreg, lreg, count); break; 2177 default: 2178 ShouldNotReachHere(); 2179 break; 2180 } 2181 break; 2182 case T_LONG: 2183 case T_ADDRESS: 2184 case T_OBJECT: 2185 switch (code) { 2186 case lir_shl: __ lsl (dreg, lreg, count); break; 2187 case lir_shr: __ asr (dreg, lreg, count); break; 2188 case lir_ushr: __ lsr (dreg, lreg, count); break; 2189 default: 2190 ShouldNotReachHere(); 2191 break; 2192 } 2193 break; 2194 default: 2195 ShouldNotReachHere(); 2196 break; 2197 } 2198 } 2199 } 2200 2201 2202 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 2203 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2204 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2205 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2206 __ str (r, Address(sp, offset_from_rsp_in_bytes)); 2207 } 2208 2209 2210 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 2211 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2212 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2213 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2214 __ mov (rscratch1, c); 2215 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes)); 2216 } 2217 2218 2219 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 2220 ShouldNotReachHere(); 2221 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2222 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2223 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2224 __ lea(rscratch1, __ constant_oop_address(o)); 2225 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes)); 2226 } 2227 2228 2229 // This code replaces a call to arraycopy; no exception may 2230 // be thrown in this code, they must be thrown in the System.arraycopy 2231 // activation frame; we could save some checks if this would not be the case 2232 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 2233 ciArrayKlass* default_type = op->expected_type(); 2234 Register src = op->src()->as_register(); 2235 Register dst = op->dst()->as_register(); 2236 Register src_pos = op->src_pos()->as_register(); 2237 Register dst_pos = op->dst_pos()->as_register(); 2238 Register length = op->length()->as_register(); 2239 Register tmp = op->tmp()->as_register(); 2240 2241 CodeStub* stub = op->stub(); 2242 int flags = op->flags(); 2243 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 2244 if (is_reference_type(basic_type)) basic_type = T_OBJECT; 2245 2246 // if we don't know anything, just go through the generic arraycopy 2247 if (default_type == NULL // || basic_type == T_OBJECT 2248 ) { 2249 Label done; 2250 assert(src == r1 && src_pos == r2, "mismatch in calling convention"); 2251 2252 // Save the arguments in case the generic arraycopy fails and we 2253 // have to fall back to the JNI stub 2254 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord)); 2255 __ stp(length, src_pos, Address(sp, 2*BytesPerWord)); 2256 __ str(src, Address(sp, 4*BytesPerWord)); 2257 2258 address copyfunc_addr = StubRoutines::generic_arraycopy(); 2259 assert(copyfunc_addr != NULL, "generic arraycopy stub required"); 2260 2261 // The arguments are in java calling convention so we shift them 2262 // to C convention 2263 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 2264 __ mov(c_rarg0, j_rarg0); 2265 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 2266 __ mov(c_rarg1, j_rarg1); 2267 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 2268 __ mov(c_rarg2, j_rarg2); 2269 assert_different_registers(c_rarg3, j_rarg4); 2270 __ mov(c_rarg3, j_rarg3); 2271 __ mov(c_rarg4, j_rarg4); 2272 #ifndef PRODUCT 2273 if (PrintC1Statistics) { 2274 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 2275 } 2276 #endif 2277 __ far_call(RuntimeAddress(copyfunc_addr)); 2278 2279 __ cbz(r0, *stub->continuation()); 2280 2281 // Reload values from the stack so they are where the stub 2282 // expects them. 2283 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord)); 2284 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord)); 2285 __ ldr(src, Address(sp, 4*BytesPerWord)); 2286 2287 // r0 is -1^K where K == partial copied count 2288 __ eonw(rscratch1, r0, zr); 2289 // adjust length down and src/end pos up by partial copied count 2290 __ subw(length, length, rscratch1); 2291 __ addw(src_pos, src_pos, rscratch1); 2292 __ addw(dst_pos, dst_pos, rscratch1); 2293 __ b(*stub->entry()); 2294 2295 __ bind(*stub->continuation()); 2296 return; 2297 } 2298 2299 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 2300 2301 int elem_size = type2aelembytes(basic_type); 2302 int scale = exact_log2(elem_size); 2303 2304 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 2305 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 2306 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 2307 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 2308 2309 // test for NULL 2310 if (flags & LIR_OpArrayCopy::src_null_check) { 2311 __ cbz(src, *stub->entry()); 2312 } 2313 if (flags & LIR_OpArrayCopy::dst_null_check) { 2314 __ cbz(dst, *stub->entry()); 2315 } 2316 2317 // If the compiler was not able to prove that exact type of the source or the destination 2318 // of the arraycopy is an array type, check at runtime if the source or the destination is 2319 // an instance type. 2320 if (flags & LIR_OpArrayCopy::type_check) { 2321 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) { 2322 __ load_klass(tmp, dst); 2323 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset()))); 2324 __ cmpw(rscratch1, Klass::_lh_neutral_value); 2325 __ br(Assembler::GE, *stub->entry()); 2326 } 2327 2328 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) { 2329 __ load_klass(tmp, src); 2330 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset()))); 2331 __ cmpw(rscratch1, Klass::_lh_neutral_value); 2332 __ br(Assembler::GE, *stub->entry()); 2333 } 2334 } 2335 2336 // check if negative 2337 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 2338 __ cmpw(src_pos, 0); 2339 __ br(Assembler::LT, *stub->entry()); 2340 } 2341 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 2342 __ cmpw(dst_pos, 0); 2343 __ br(Assembler::LT, *stub->entry()); 2344 } 2345 2346 if (flags & LIR_OpArrayCopy::length_positive_check) { 2347 __ cmpw(length, 0); 2348 __ br(Assembler::LT, *stub->entry()); 2349 } 2350 2351 if (flags & LIR_OpArrayCopy::src_range_check) { 2352 __ addw(tmp, src_pos, length); 2353 __ ldrw(rscratch1, src_length_addr); 2354 __ cmpw(tmp, rscratch1); 2355 __ br(Assembler::HI, *stub->entry()); 2356 } 2357 if (flags & LIR_OpArrayCopy::dst_range_check) { 2358 __ addw(tmp, dst_pos, length); 2359 __ ldrw(rscratch1, dst_length_addr); 2360 __ cmpw(tmp, rscratch1); 2361 __ br(Assembler::HI, *stub->entry()); 2362 } 2363 2364 if (flags & LIR_OpArrayCopy::type_check) { 2365 // We don't know the array types are compatible 2366 if (basic_type != T_OBJECT) { 2367 // Simple test for basic type arrays 2368 if (UseCompressedClassPointers) { 2369 __ ldrw(tmp, src_klass_addr); 2370 __ ldrw(rscratch1, dst_klass_addr); 2371 __ cmpw(tmp, rscratch1); 2372 } else { 2373 __ ldr(tmp, src_klass_addr); 2374 __ ldr(rscratch1, dst_klass_addr); 2375 __ cmp(tmp, rscratch1); 2376 } 2377 __ br(Assembler::NE, *stub->entry()); 2378 } else { 2379 // For object arrays, if src is a sub class of dst then we can 2380 // safely do the copy. 2381 Label cont, slow; 2382 2383 #define PUSH(r1, r2) \ 2384 stp(r1, r2, __ pre(sp, -2 * wordSize)); 2385 2386 #define POP(r1, r2) \ 2387 ldp(r1, r2, __ post(sp, 2 * wordSize)); 2388 2389 __ PUSH(src, dst); 2390 2391 __ load_klass(src, src); 2392 __ load_klass(dst, dst); 2393 2394 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); 2395 2396 __ PUSH(src, dst); 2397 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 2398 __ POP(src, dst); 2399 2400 __ cbnz(src, cont); 2401 2402 __ bind(slow); 2403 __ POP(src, dst); 2404 2405 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 2406 if (copyfunc_addr != NULL) { // use stub if available 2407 // src is not a sub class of dst so we have to do a 2408 // per-element check. 2409 2410 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 2411 if ((flags & mask) != mask) { 2412 // Check that at least both of them object arrays. 2413 assert(flags & mask, "one of the two should be known to be an object array"); 2414 2415 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 2416 __ load_klass(tmp, src); 2417 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 2418 __ load_klass(tmp, dst); 2419 } 2420 int lh_offset = in_bytes(Klass::layout_helper_offset()); 2421 Address klass_lh_addr(tmp, lh_offset); 2422 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 2423 __ ldrw(rscratch1, klass_lh_addr); 2424 __ mov(rscratch2, objArray_lh); 2425 __ eorw(rscratch1, rscratch1, rscratch2); 2426 __ cbnzw(rscratch1, *stub->entry()); 2427 } 2428 2429 // Spill because stubs can use any register they like and it's 2430 // easier to restore just those that we care about. 2431 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord)); 2432 __ stp(length, src_pos, Address(sp, 2*BytesPerWord)); 2433 __ str(src, Address(sp, 4*BytesPerWord)); 2434 2435 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale))); 2436 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type)); 2437 assert_different_registers(c_rarg0, dst, dst_pos, length); 2438 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale))); 2439 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type)); 2440 assert_different_registers(c_rarg1, dst, length); 2441 __ uxtw(c_rarg2, length); 2442 assert_different_registers(c_rarg2, dst); 2443 2444 __ load_klass(c_rarg4, dst); 2445 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); 2446 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 2447 __ far_call(RuntimeAddress(copyfunc_addr)); 2448 2449 #ifndef PRODUCT 2450 if (PrintC1Statistics) { 2451 Label failed; 2452 __ cbnz(r0, failed); 2453 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); 2454 __ bind(failed); 2455 } 2456 #endif 2457 2458 __ cbz(r0, *stub->continuation()); 2459 2460 #ifndef PRODUCT 2461 if (PrintC1Statistics) { 2462 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); 2463 } 2464 #endif 2465 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1); 2466 2467 // Restore previously spilled arguments 2468 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord)); 2469 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord)); 2470 __ ldr(src, Address(sp, 4*BytesPerWord)); 2471 2472 // return value is -1^K where K is partial copied count 2473 __ eonw(rscratch1, r0, zr); 2474 // adjust length down and src/end pos up by partial copied count 2475 __ subw(length, length, rscratch1); 2476 __ addw(src_pos, src_pos, rscratch1); 2477 __ addw(dst_pos, dst_pos, rscratch1); 2478 } 2479 2480 __ b(*stub->entry()); 2481 2482 __ bind(cont); 2483 __ POP(src, dst); 2484 } 2485 } 2486 2487 #ifdef ASSERT 2488 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 2489 // Sanity check the known type with the incoming class. For the 2490 // primitive case the types must match exactly with src.klass and 2491 // dst.klass each exactly matching the default type. For the 2492 // object array case, if no type check is needed then either the 2493 // dst type is exactly the expected type and the src type is a 2494 // subtype which we can't check or src is the same array as dst 2495 // but not necessarily exactly of type default_type. 2496 Label known_ok, halt; 2497 __ mov_metadata(tmp, default_type->constant_encoding()); 2498 if (UseCompressedClassPointers) { 2499 __ encode_klass_not_null(tmp); 2500 } 2501 2502 if (basic_type != T_OBJECT) { 2503 2504 if (UseCompressedClassPointers) { 2505 __ ldrw(rscratch1, dst_klass_addr); 2506 __ cmpw(tmp, rscratch1); 2507 } else { 2508 __ ldr(rscratch1, dst_klass_addr); 2509 __ cmp(tmp, rscratch1); 2510 } 2511 __ br(Assembler::NE, halt); 2512 if (UseCompressedClassPointers) { 2513 __ ldrw(rscratch1, src_klass_addr); 2514 __ cmpw(tmp, rscratch1); 2515 } else { 2516 __ ldr(rscratch1, src_klass_addr); 2517 __ cmp(tmp, rscratch1); 2518 } 2519 __ br(Assembler::EQ, known_ok); 2520 } else { 2521 if (UseCompressedClassPointers) { 2522 __ ldrw(rscratch1, dst_klass_addr); 2523 __ cmpw(tmp, rscratch1); 2524 } else { 2525 __ ldr(rscratch1, dst_klass_addr); 2526 __ cmp(tmp, rscratch1); 2527 } 2528 __ br(Assembler::EQ, known_ok); 2529 __ cmp(src, dst); 2530 __ br(Assembler::EQ, known_ok); 2531 } 2532 __ bind(halt); 2533 __ stop("incorrect type information in arraycopy"); 2534 __ bind(known_ok); 2535 } 2536 #endif 2537 2538 #ifndef PRODUCT 2539 if (PrintC1Statistics) { 2540 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); 2541 } 2542 #endif 2543 2544 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale))); 2545 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type)); 2546 assert_different_registers(c_rarg0, dst, dst_pos, length); 2547 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale))); 2548 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type)); 2549 assert_different_registers(c_rarg1, dst, length); 2550 __ uxtw(c_rarg2, length); 2551 assert_different_registers(c_rarg2, dst); 2552 2553 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 2554 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 2555 const char *name; 2556 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 2557 2558 CodeBlob *cb = CodeCache::find_blob(entry); 2559 if (cb) { 2560 __ far_call(RuntimeAddress(entry)); 2561 } else { 2562 __ call_VM_leaf(entry, 3); 2563 } 2564 2565 __ bind(*stub->continuation()); 2566 } 2567 2568 2569 2570 2571 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 2572 Register obj = op->obj_opr()->as_register(); // may not be an oop 2573 Register hdr = op->hdr_opr()->as_register(); 2574 Register lock = op->lock_opr()->as_register(); 2575 if (!UseFastLocking) { 2576 __ b(*op->stub()->entry()); 2577 } else if (op->code() == lir_lock) { 2578 Register scratch = noreg; 2579 if (UseBiasedLocking) { 2580 scratch = op->scratch_opr()->as_register(); 2581 } 2582 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2583 // add debug info for NullPointerException only if one is possible 2584 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); 2585 if (op->info() != NULL) { 2586 add_debug_info_for_null_check(null_check_offset, op->info()); 2587 } 2588 // done 2589 } else if (op->code() == lir_unlock) { 2590 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2591 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 2592 } else { 2593 Unimplemented(); 2594 } 2595 __ bind(*op->stub()->continuation()); 2596 } 2597 2598 2599 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 2600 ciMethod* method = op->profiled_method(); 2601 int bci = op->profiled_bci(); 2602 ciMethod* callee = op->profiled_callee(); 2603 2604 // Update counter for all call types 2605 ciMethodData* md = method->method_data_or_null(); 2606 assert(md != NULL, "Sanity"); 2607 ciProfileData* data = md->bci_to_data(bci); 2608 assert(data != NULL && data->is_CounterData(), "need CounterData for calls"); 2609 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 2610 Register mdo = op->mdo()->as_register(); 2611 __ mov_metadata(mdo, md->constant_encoding()); 2612 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 2613 // Perform additional virtual call profiling for invokevirtual and 2614 // invokeinterface bytecodes 2615 if (op->should_profile_receiver_type()) { 2616 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 2617 Register recv = op->recv()->as_register(); 2618 assert_different_registers(mdo, recv); 2619 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 2620 ciKlass* known_klass = op->known_holder(); 2621 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 2622 // We know the type that will be seen at this call site; we can 2623 // statically update the MethodData* rather than needing to do 2624 // dynamic tests on the receiver type 2625 2626 // NOTE: we should probably put a lock around this search to 2627 // avoid collisions by concurrent compilations 2628 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 2629 uint i; 2630 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2631 ciKlass* receiver = vc_data->receiver(i); 2632 if (known_klass->equals(receiver)) { 2633 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 2634 __ addptr(data_addr, DataLayout::counter_increment); 2635 return; 2636 } 2637 } 2638 2639 // Receiver type not found in profile data; select an empty slot 2640 2641 // Note that this is less efficient than it should be because it 2642 // always does a write to the receiver part of the 2643 // VirtualCallData rather than just the first time 2644 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2645 ciKlass* receiver = vc_data->receiver(i); 2646 if (receiver == NULL) { 2647 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 2648 __ mov_metadata(rscratch1, known_klass->constant_encoding()); 2649 __ lea(rscratch2, recv_addr); 2650 __ str(rscratch1, Address(rscratch2)); 2651 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 2652 __ addptr(data_addr, DataLayout::counter_increment); 2653 return; 2654 } 2655 } 2656 } else { 2657 __ load_klass(recv, recv); 2658 Label update_done; 2659 type_profile_helper(mdo, md, data, recv, &update_done); 2660 // Receiver did not match any saved receiver and there is no empty row for it. 2661 // Increment total counter to indicate polymorphic case. 2662 __ addptr(counter_addr, DataLayout::counter_increment); 2663 2664 __ bind(update_done); 2665 } 2666 } else { 2667 // Static call 2668 __ addptr(counter_addr, DataLayout::counter_increment); 2669 } 2670 } 2671 2672 2673 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 2674 Unimplemented(); 2675 } 2676 2677 2678 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 2679 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 2680 } 2681 2682 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 2683 assert(op->crc()->is_single_cpu(), "crc must be register"); 2684 assert(op->val()->is_single_cpu(), "byte value must be register"); 2685 assert(op->result_opr()->is_single_cpu(), "result must be register"); 2686 Register crc = op->crc()->as_register(); 2687 Register val = op->val()->as_register(); 2688 Register res = op->result_opr()->as_register(); 2689 2690 assert_different_registers(val, crc, res); 2691 uint64_t offset; 2692 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset); 2693 if (offset) __ add(res, res, offset); 2694 2695 __ mvnw(crc, crc); // ~crc 2696 __ update_byte_crc32(crc, val, res); 2697 __ mvnw(res, crc); // ~crc 2698 } 2699 2700 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 2701 COMMENT("emit_profile_type {"); 2702 Register obj = op->obj()->as_register(); 2703 Register tmp = op->tmp()->as_pointer_register(); 2704 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 2705 ciKlass* exact_klass = op->exact_klass(); 2706 intptr_t current_klass = op->current_klass(); 2707 bool not_null = op->not_null(); 2708 bool no_conflict = op->no_conflict(); 2709 2710 Label update, next, none; 2711 2712 bool do_null = !not_null; 2713 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 2714 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 2715 2716 assert(do_null || do_update, "why are we here?"); 2717 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 2718 assert(mdo_addr.base() != rscratch1, "wrong register"); 2719 2720 __ verify_oop(obj); 2721 2722 if (tmp != obj) { 2723 __ mov(tmp, obj); 2724 } 2725 if (do_null) { 2726 __ cbnz(tmp, update); 2727 if (!TypeEntries::was_null_seen(current_klass)) { 2728 __ ldr(rscratch2, mdo_addr); 2729 __ orr(rscratch2, rscratch2, TypeEntries::null_seen); 2730 __ str(rscratch2, mdo_addr); 2731 } 2732 if (do_update) { 2733 #ifndef ASSERT 2734 __ b(next); 2735 } 2736 #else 2737 __ b(next); 2738 } 2739 } else { 2740 __ cbnz(tmp, update); 2741 __ stop("unexpected null obj"); 2742 #endif 2743 } 2744 2745 __ bind(update); 2746 2747 if (do_update) { 2748 #ifdef ASSERT 2749 if (exact_klass != NULL) { 2750 Label ok; 2751 __ load_klass(tmp, tmp); 2752 __ mov_metadata(rscratch1, exact_klass->constant_encoding()); 2753 __ eor(rscratch1, tmp, rscratch1); 2754 __ cbz(rscratch1, ok); 2755 __ stop("exact klass and actual klass differ"); 2756 __ bind(ok); 2757 } 2758 #endif 2759 if (!no_conflict) { 2760 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 2761 if (exact_klass != NULL) { 2762 __ mov_metadata(tmp, exact_klass->constant_encoding()); 2763 } else { 2764 __ load_klass(tmp, tmp); 2765 } 2766 2767 __ ldr(rscratch2, mdo_addr); 2768 __ eor(tmp, tmp, rscratch2); 2769 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask); 2770 // klass seen before, nothing to do. The unknown bit may have been 2771 // set already but no need to check. 2772 __ cbz(rscratch1, next); 2773 2774 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore. 2775 2776 if (TypeEntries::is_type_none(current_klass)) { 2777 __ cbz(rscratch2, none); 2778 __ cmp(rscratch2, (u1)TypeEntries::null_seen); 2779 __ br(Assembler::EQ, none); 2780 // There is a chance that the checks above (re-reading profiling 2781 // data from memory) fail if another thread has just set the 2782 // profiling to this obj's klass 2783 __ dmb(Assembler::ISHLD); 2784 __ ldr(rscratch2, mdo_addr); 2785 __ eor(tmp, tmp, rscratch2); 2786 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask); 2787 __ cbz(rscratch1, next); 2788 } 2789 } else { 2790 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 2791 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 2792 2793 __ ldr(tmp, mdo_addr); 2794 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore. 2795 } 2796 2797 // different than before. Cannot keep accurate profile. 2798 __ ldr(rscratch2, mdo_addr); 2799 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown); 2800 __ str(rscratch2, mdo_addr); 2801 2802 if (TypeEntries::is_type_none(current_klass)) { 2803 __ b(next); 2804 2805 __ bind(none); 2806 // first time here. Set profile type. 2807 __ str(tmp, mdo_addr); 2808 } 2809 } else { 2810 // There's a single possible klass at this profile point 2811 assert(exact_klass != NULL, "should be"); 2812 if (TypeEntries::is_type_none(current_klass)) { 2813 __ mov_metadata(tmp, exact_klass->constant_encoding()); 2814 __ ldr(rscratch2, mdo_addr); 2815 __ eor(tmp, tmp, rscratch2); 2816 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask); 2817 __ cbz(rscratch1, next); 2818 #ifdef ASSERT 2819 { 2820 Label ok; 2821 __ ldr(rscratch1, mdo_addr); 2822 __ cbz(rscratch1, ok); 2823 __ cmp(rscratch1, (u1)TypeEntries::null_seen); 2824 __ br(Assembler::EQ, ok); 2825 // may have been set by another thread 2826 __ dmb(Assembler::ISHLD); 2827 __ mov_metadata(rscratch1, exact_klass->constant_encoding()); 2828 __ ldr(rscratch2, mdo_addr); 2829 __ eor(rscratch2, rscratch1, rscratch2); 2830 __ andr(rscratch2, rscratch2, TypeEntries::type_mask); 2831 __ cbz(rscratch2, ok); 2832 2833 __ stop("unexpected profiling mismatch"); 2834 __ bind(ok); 2835 } 2836 #endif 2837 // first time here. Set profile type. 2838 __ str(tmp, mdo_addr); 2839 } else { 2840 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 2841 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 2842 2843 __ ldr(tmp, mdo_addr); 2844 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore. 2845 2846 __ orr(tmp, tmp, TypeEntries::type_unknown); 2847 __ str(tmp, mdo_addr); 2848 // FIXME: Write barrier needed here? 2849 } 2850 } 2851 2852 __ bind(next); 2853 } 2854 COMMENT("} emit_profile_type"); 2855 } 2856 2857 2858 void LIR_Assembler::align_backward_branch_target() { 2859 } 2860 2861 2862 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) { 2863 // tmp must be unused 2864 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2865 2866 if (left->is_single_cpu()) { 2867 assert(dest->is_single_cpu(), "expect single result reg"); 2868 __ negw(dest->as_register(), left->as_register()); 2869 } else if (left->is_double_cpu()) { 2870 assert(dest->is_double_cpu(), "expect double result reg"); 2871 __ neg(dest->as_register_lo(), left->as_register_lo()); 2872 } else if (left->is_single_fpu()) { 2873 assert(dest->is_single_fpu(), "expect single float result reg"); 2874 __ fnegs(dest->as_float_reg(), left->as_float_reg()); 2875 } else { 2876 assert(left->is_double_fpu(), "expect double float operand reg"); 2877 assert(dest->is_double_fpu(), "expect double float result reg"); 2878 __ fnegd(dest->as_double_reg(), left->as_double_reg()); 2879 } 2880 } 2881 2882 2883 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 2884 if (patch_code != lir_patch_none) { 2885 deoptimize_trap(info); 2886 return; 2887 } 2888 2889 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr())); 2890 } 2891 2892 2893 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 2894 assert(!tmp->is_valid(), "don't need temporary"); 2895 2896 CodeBlob *cb = CodeCache::find_blob(dest); 2897 if (cb) { 2898 __ far_call(RuntimeAddress(dest)); 2899 } else { 2900 __ mov(rscratch1, RuntimeAddress(dest)); 2901 __ blr(rscratch1); 2902 } 2903 2904 if (info != NULL) { 2905 add_call_info_here(info); 2906 } 2907 } 2908 2909 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 2910 if (dest->is_address() || src->is_address()) { 2911 move_op(src, dest, type, lir_patch_none, info, 2912 /*pop_fpu_stack*/false, /*unaligned*/false, /*wide*/false); 2913 } else { 2914 ShouldNotReachHere(); 2915 } 2916 } 2917 2918 #ifdef ASSERT 2919 // emit run-time assertion 2920 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 2921 assert(op->code() == lir_assert, "must be"); 2922 2923 if (op->in_opr1()->is_valid()) { 2924 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 2925 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 2926 } else { 2927 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 2928 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 2929 } 2930 2931 Label ok; 2932 if (op->condition() != lir_cond_always) { 2933 Assembler::Condition acond = Assembler::AL; 2934 switch (op->condition()) { 2935 case lir_cond_equal: acond = Assembler::EQ; break; 2936 case lir_cond_notEqual: acond = Assembler::NE; break; 2937 case lir_cond_less: acond = Assembler::LT; break; 2938 case lir_cond_lessEqual: acond = Assembler::LE; break; 2939 case lir_cond_greaterEqual: acond = Assembler::GE; break; 2940 case lir_cond_greater: acond = Assembler::GT; break; 2941 case lir_cond_belowEqual: acond = Assembler::LS; break; 2942 case lir_cond_aboveEqual: acond = Assembler::HS; break; 2943 default: ShouldNotReachHere(); 2944 } 2945 __ br(acond, ok); 2946 } 2947 if (op->halt()) { 2948 const char* str = __ code_string(op->msg()); 2949 __ stop(str); 2950 } else { 2951 breakpoint(); 2952 } 2953 __ bind(ok); 2954 } 2955 #endif 2956 2957 #ifndef PRODUCT 2958 #define COMMENT(x) do { __ block_comment(x); } while (0) 2959 #else 2960 #define COMMENT(x) 2961 #endif 2962 2963 void LIR_Assembler::membar() { 2964 COMMENT("membar"); 2965 __ membar(MacroAssembler::AnyAny); 2966 } 2967 2968 void LIR_Assembler::membar_acquire() { 2969 __ membar(Assembler::LoadLoad|Assembler::LoadStore); 2970 } 2971 2972 void LIR_Assembler::membar_release() { 2973 __ membar(Assembler::LoadStore|Assembler::StoreStore); 2974 } 2975 2976 void LIR_Assembler::membar_loadload() { 2977 __ membar(Assembler::LoadLoad); 2978 } 2979 2980 void LIR_Assembler::membar_storestore() { 2981 __ membar(MacroAssembler::StoreStore); 2982 } 2983 2984 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); } 2985 2986 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); } 2987 2988 void LIR_Assembler::on_spin_wait() { 2989 __ spin_wait(); 2990 } 2991 2992 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 2993 __ mov(result_reg->as_register(), rthread); 2994 } 2995 2996 2997 void LIR_Assembler::peephole(LIR_List *lir) { 2998 #if 0 2999 if (tableswitch_count >= max_tableswitches) 3000 return; 3001 3002 /* 3003 This finite-state automaton recognizes sequences of compare-and- 3004 branch instructions. We will turn them into a tableswitch. You 3005 could argue that C1 really shouldn't be doing this sort of 3006 optimization, but without it the code is really horrible. 3007 */ 3008 3009 enum { start_s, cmp1_s, beq_s, cmp_s } state; 3010 int first_key, last_key = -2147483648; 3011 int next_key = 0; 3012 int start_insn = -1; 3013 int last_insn = -1; 3014 Register reg = noreg; 3015 LIR_Opr reg_opr; 3016 state = start_s; 3017 3018 LIR_OpList* inst = lir->instructions_list(); 3019 for (int i = 0; i < inst->length(); i++) { 3020 LIR_Op* op = inst->at(i); 3021 switch (state) { 3022 case start_s: 3023 first_key = -1; 3024 start_insn = i; 3025 switch (op->code()) { 3026 case lir_cmp: 3027 LIR_Opr opr1 = op->as_Op2()->in_opr1(); 3028 LIR_Opr opr2 = op->as_Op2()->in_opr2(); 3029 if (opr1->is_cpu_register() && opr1->is_single_cpu() 3030 && opr2->is_constant() 3031 && opr2->type() == T_INT) { 3032 reg_opr = opr1; 3033 reg = opr1->as_register(); 3034 first_key = opr2->as_constant_ptr()->as_jint(); 3035 next_key = first_key + 1; 3036 state = cmp_s; 3037 goto next_state; 3038 } 3039 break; 3040 } 3041 break; 3042 case cmp_s: 3043 switch (op->code()) { 3044 case lir_branch: 3045 if (op->as_OpBranch()->cond() == lir_cond_equal) { 3046 state = beq_s; 3047 last_insn = i; 3048 goto next_state; 3049 } 3050 } 3051 state = start_s; 3052 break; 3053 case beq_s: 3054 switch (op->code()) { 3055 case lir_cmp: { 3056 LIR_Opr opr1 = op->as_Op2()->in_opr1(); 3057 LIR_Opr opr2 = op->as_Op2()->in_opr2(); 3058 if (opr1->is_cpu_register() && opr1->is_single_cpu() 3059 && opr1->as_register() == reg 3060 && opr2->is_constant() 3061 && opr2->type() == T_INT 3062 && opr2->as_constant_ptr()->as_jint() == next_key) { 3063 last_key = next_key; 3064 next_key++; 3065 state = cmp_s; 3066 goto next_state; 3067 } 3068 } 3069 } 3070 last_key = next_key; 3071 state = start_s; 3072 break; 3073 default: 3074 assert(false, "impossible state"); 3075 } 3076 if (state == start_s) { 3077 if (first_key < last_key - 5L && reg != noreg) { 3078 { 3079 // printf("found run register %d starting at insn %d low value %d high value %d\n", 3080 // reg->encoding(), 3081 // start_insn, first_key, last_key); 3082 // for (int i = 0; i < inst->length(); i++) { 3083 // inst->at(i)->print(); 3084 // tty->print("\n"); 3085 // } 3086 // tty->print("\n"); 3087 } 3088 3089 struct tableswitch *sw = &switches[tableswitch_count]; 3090 sw->_insn_index = start_insn, sw->_first_key = first_key, 3091 sw->_last_key = last_key, sw->_reg = reg; 3092 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after)); 3093 { 3094 // Insert the new table of branches 3095 int offset = last_insn; 3096 for (int n = first_key; n < last_key; n++) { 3097 inst->insert_before 3098 (last_insn + 1, 3099 new LIR_OpBranch(lir_cond_always, T_ILLEGAL, 3100 inst->at(offset)->as_OpBranch()->label())); 3101 offset -= 2, i++; 3102 } 3103 } 3104 // Delete all the old compare-and-branch instructions 3105 for (int n = first_key; n < last_key; n++) { 3106 inst->remove_at(start_insn); 3107 inst->remove_at(start_insn); 3108 } 3109 // Insert the tableswitch instruction 3110 inst->insert_before(start_insn, 3111 new LIR_Op2(lir_cmp, lir_cond_always, 3112 LIR_OprFact::intConst(tableswitch_count), 3113 reg_opr)); 3114 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches)); 3115 tableswitch_count++; 3116 } 3117 reg = noreg; 3118 last_key = -2147483648; 3119 } 3120 next_state: 3121 ; 3122 } 3123 #endif 3124 } 3125 3126 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) { 3127 Address addr = as_Address(src->as_address_ptr()); 3128 BasicType type = src->type(); 3129 bool is_oop = is_reference_type(type); 3130 3131 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr); 3132 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr); 3133 3134 switch(type) { 3135 case T_INT: 3136 xchg = &MacroAssembler::atomic_xchgalw; 3137 add = &MacroAssembler::atomic_addalw; 3138 break; 3139 case T_LONG: 3140 xchg = &MacroAssembler::atomic_xchgal; 3141 add = &MacroAssembler::atomic_addal; 3142 break; 3143 case T_OBJECT: 3144 case T_ARRAY: 3145 if (UseCompressedOops) { 3146 xchg = &MacroAssembler::atomic_xchgalw; 3147 add = &MacroAssembler::atomic_addalw; 3148 } else { 3149 xchg = &MacroAssembler::atomic_xchgal; 3150 add = &MacroAssembler::atomic_addal; 3151 } 3152 break; 3153 default: 3154 ShouldNotReachHere(); 3155 xchg = &MacroAssembler::atomic_xchgal; 3156 add = &MacroAssembler::atomic_addal; // unreachable 3157 } 3158 3159 switch (code) { 3160 case lir_xadd: 3161 { 3162 RegisterOrConstant inc; 3163 Register tmp = as_reg(tmp_op); 3164 Register dst = as_reg(dest); 3165 if (data->is_constant()) { 3166 inc = RegisterOrConstant(as_long(data)); 3167 assert_different_registers(dst, addr.base(), tmp, 3168 rscratch1, rscratch2); 3169 } else { 3170 inc = RegisterOrConstant(as_reg(data)); 3171 assert_different_registers(inc.as_register(), dst, addr.base(), tmp, 3172 rscratch1, rscratch2); 3173 } 3174 __ lea(tmp, addr); 3175 (_masm->*add)(dst, inc, tmp); 3176 break; 3177 } 3178 case lir_xchg: 3179 { 3180 Register tmp = tmp_op->as_register(); 3181 Register obj = as_reg(data); 3182 Register dst = as_reg(dest); 3183 if (is_oop && UseCompressedOops) { 3184 __ encode_heap_oop(rscratch2, obj); 3185 obj = rscratch2; 3186 } 3187 assert_different_registers(obj, addr.base(), tmp, rscratch1, dst); 3188 __ lea(tmp, addr); 3189 (_masm->*xchg)(dst, obj, tmp); 3190 if (is_oop && UseCompressedOops) { 3191 __ decode_heap_oop(dst); 3192 } 3193 } 3194 break; 3195 default: 3196 ShouldNotReachHere(); 3197 } 3198 __ membar(__ AnyAny); 3199 } 3200 3201 #undef __