1 /*
2 * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "code/compiledIC.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/gc_globals.hpp"
40 #include "nativeInst_aarch64.hpp"
41 #include "oops/objArrayKlass.hpp"
42 #include "runtime/frame.inline.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "utilities/powerOfTwo.hpp"
46 #include "vmreg_aarch64.inline.hpp"
47
48
49 #ifndef PRODUCT
50 #define COMMENT(x) do { __ block_comment(x); } while (0)
51 #else
52 #define COMMENT(x)
53 #endif
54
55 NEEDS_CLEANUP // remove this definitions ?
56 const Register IC_Klass = rscratch2; // where the IC klass is cached
57 const Register SYNC_header = r0; // synchronization header
58 const Register SHIFT_count = r0; // where count for shift operations must be
59
60 #define __ _masm->
61
62
63 static void select_different_registers(Register preserve,
64 Register extra,
65 Register &tmp1,
66 Register &tmp2) {
67 if (tmp1 == preserve) {
68 assert_different_registers(tmp1, tmp2, extra);
69 tmp1 = extra;
70 } else if (tmp2 == preserve) {
71 assert_different_registers(tmp1, tmp2, extra);
72 tmp2 = extra;
73 }
74 assert_different_registers(preserve, tmp1, tmp2);
75 }
76
77
78
79 static void select_different_registers(Register preserve,
80 Register extra,
81 Register &tmp1,
82 Register &tmp2,
83 Register &tmp3) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, tmp3, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, tmp3, extra);
89 tmp2 = extra;
90 } else if (tmp3 == preserve) {
91 assert_different_registers(tmp1, tmp2, tmp3, extra);
92 tmp3 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2, tmp3);
95 }
96
97
98 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
99
100
101 LIR_Opr LIR_Assembler::receiverOpr() {
102 return FrameMap::receiver_opr;
103 }
104
105 LIR_Opr LIR_Assembler::osrBufferPointer() {
106 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
107 }
108
109 //--------------fpu register translations-----------------------
110
111
112 address LIR_Assembler::float_constant(float f) {
113 address const_addr = __ float_constant(f);
114 if (const_addr == NULL) {
115 bailout("const section overflow");
116 return __ code()->consts()->start();
117 } else {
118 return const_addr;
119 }
120 }
121
122
123 address LIR_Assembler::double_constant(double d) {
124 address const_addr = __ double_constant(d);
125 if (const_addr == NULL) {
126 bailout("const section overflow");
127 return __ code()->consts()->start();
128 } else {
129 return const_addr;
130 }
131 }
132
133 address LIR_Assembler::int_constant(jlong n) {
134 address const_addr = __ long_constant(n);
135 if (const_addr == NULL) {
136 bailout("const section overflow");
137 return __ code()->consts()->start();
138 } else {
139 return const_addr;
140 }
141 }
142
143 void LIR_Assembler::breakpoint() { Unimplemented(); }
144
145 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
146
147 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
148
149 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
150 //-------------------------------------------
151
152 static Register as_reg(LIR_Opr op) {
153 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
154 }
155
156 static jlong as_long(LIR_Opr data) {
157 jlong result;
158 switch (data->type()) {
159 case T_INT:
160 result = (data->as_jint());
161 break;
162 case T_LONG:
163 result = (data->as_jlong());
164 break;
165 default:
166 ShouldNotReachHere();
167 result = 0; // unreachable
168 }
169 return result;
170 }
171
172 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
173 Register base = addr->base()->as_pointer_register();
174 LIR_Opr opr = addr->index();
175 if (opr->is_cpu_register()) {
176 Register index;
177 if (opr->is_single_cpu())
178 index = opr->as_register();
179 else
180 index = opr->as_register_lo();
181 assert(addr->disp() == 0, "must be");
182 switch(opr->type()) {
183 case T_INT:
184 return Address(base, index, Address::sxtw(addr->scale()));
185 case T_LONG:
186 return Address(base, index, Address::lsl(addr->scale()));
187 default:
188 ShouldNotReachHere();
189 }
190 } else {
191 assert(addr->scale() == 0,
192 "expected for immediate operand, was: %d", addr->scale());
193 ptrdiff_t offset = ptrdiff_t(addr->disp());
194 // NOTE: Does not handle any 16 byte vector access.
195 const uint type_size = type2aelembytes(addr->type(), true);
196 return __ legitimize_address(Address(base, offset), type_size, tmp);
197 }
198 return Address();
199 }
200
201 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
202 ShouldNotReachHere();
203 return Address();
204 }
205
206 Address LIR_Assembler::as_Address(LIR_Address* addr) {
207 return as_Address(addr, rscratch1);
208 }
209
210 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
211 return as_Address(addr, rscratch1); // Ouch
212 // FIXME: This needs to be much more clever. See x86.
213 }
214
215 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
216 // not encodable as a base + (immediate) offset, generate an explicit address
217 // calculation to hold the address in a temporary register.
218 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
219 precond(size == 4 || size == 8);
220 Address addr = frame_map()->address_for_slot(index, adjust);
221 precond(addr.getMode() == Address::base_plus_offset);
222 precond(addr.base() == sp);
223 precond(addr.offset() > 0);
224 uint mask = size - 1;
225 assert((addr.offset() & mask) == 0, "scaled offsets only");
226 return __ legitimize_address(addr, size, tmp);
227 }
228
229 void LIR_Assembler::osr_entry() {
230 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
231 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
232 ValueStack* entry_state = osr_entry->state();
233 int number_of_locks = entry_state->locks_size();
234
235 // we jump here if osr happens with the interpreter
236 // state set up to continue at the beginning of the
237 // loop that triggered osr - in particular, we have
238 // the following registers setup:
239 //
240 // r2: osr buffer
241 //
242
243 // build frame
244 ciMethod* m = compilation()->method();
245 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
246
247 // OSR buffer is
248 //
249 // locals[nlocals-1..0]
250 // monitors[0..number_of_locks]
251 //
252 // locals is a direct copy of the interpreter frame so in the osr buffer
253 // so first slot in the local array is the last local from the interpreter
254 // and last slot is local[0] (receiver) from the interpreter
255 //
256 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
257 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
258 // in the interpreter frame (the method lock if a sync method)
259
260 // Initialize monitors in the compiled activation.
261 // r2: pointer to osr buffer
262 //
263 // All other registers are dead at this point and the locals will be
264 // copied into place by code emitted in the IR.
265
266 Register OSR_buf = osrBufferPointer()->as_pointer_register();
267 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
268 int monitor_offset = BytesPerWord * method()->max_locals() +
269 (2 * BytesPerWord) * (number_of_locks - 1);
270 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
271 // the OSR buffer using 2 word entries: first the lock and then
272 // the oop.
273 for (int i = 0; i < number_of_locks; i++) {
274 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
275 #ifdef ASSERT
276 // verify the interpreter's monitor has a non-null object
277 {
278 Label L;
279 __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
280 __ cbnz(rscratch1, L);
281 __ stop("locked object is NULL");
282 __ bind(L);
283 }
284 #endif
285 __ ldr(r19, Address(OSR_buf, slot_offset));
286 __ ldr(r20, Address(OSR_buf, slot_offset + BytesPerWord));
287 __ str(r19, frame_map()->address_for_monitor_lock(i));
288 __ str(r20, frame_map()->address_for_monitor_object(i));
289 }
290 }
291 }
292
293
294 // inline cache check; done before the frame is built.
295 int LIR_Assembler::check_icache() {
296 Register receiver = FrameMap::receiver_opr->as_register();
297 Register ic_klass = IC_Klass;
298 int start_offset = __ offset();
299 __ inline_cache_check(receiver, ic_klass);
300
301 // if icache check fails, then jump to runtime routine
302 // Note: RECEIVER must still contain the receiver!
303 Label dont;
304 __ br(Assembler::EQ, dont);
305 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
306
307 // We align the verified entry point unless the method body
308 // (including its inline cache check) will fit in a single 64-byte
309 // icache line.
310 if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) {
311 // force alignment after the cache check.
312 __ align(CodeEntryAlignment);
313 }
314
315 __ bind(dont);
316 return start_offset;
317 }
318
319 void LIR_Assembler::clinit_barrier(ciMethod* method) {
320 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
321 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
322
323 Label L_skip_barrier;
324
325 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
326 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
327 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
328 __ bind(L_skip_barrier);
329 }
330
331 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
332 if (o == NULL) {
333 __ mov(reg, zr);
334 } else {
335 __ movoop(reg, o, /*immediate*/true);
336 }
337 }
338
339 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
340 address target = NULL;
341 relocInfo::relocType reloc_type = relocInfo::none;
342
343 switch (patching_id(info)) {
344 case PatchingStub::access_field_id:
345 target = Runtime1::entry_for(Runtime1::access_field_patching_id);
346 reloc_type = relocInfo::section_word_type;
347 break;
348 case PatchingStub::load_klass_id:
349 target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
350 reloc_type = relocInfo::metadata_type;
351 break;
352 case PatchingStub::load_mirror_id:
353 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
354 reloc_type = relocInfo::oop_type;
355 break;
356 case PatchingStub::load_appendix_id:
357 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
358 reloc_type = relocInfo::oop_type;
359 break;
360 default: ShouldNotReachHere();
361 }
362
363 __ far_call(RuntimeAddress(target));
364 add_call_info_here(info);
365 }
366
367 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
368 deoptimize_trap(info);
369 }
370
371
372 // This specifies the rsp decrement needed to build the frame
373 int LIR_Assembler::initial_frame_size_in_bytes() const {
374 // if rounding, must let FrameMap know!
375
376 return in_bytes(frame_map()->framesize_in_bytes());
377 }
378
379
380 int LIR_Assembler::emit_exception_handler() {
381 // if the last instruction is a call (typically to do a throw which
382 // is coming at the end after block reordering) the return address
383 // must still point into the code area in order to avoid assertion
384 // failures when searching for the corresponding bci => add a nop
385 // (was bug 5/14/1999 - gri)
386 __ nop();
387
388 // generate code for exception handler
389 address handler_base = __ start_a_stub(exception_handler_size());
390 if (handler_base == NULL) {
391 // not enough space left for the handler
392 bailout("exception handler overflow");
393 return -1;
394 }
395
396 int offset = code_offset();
397
398 // the exception oop and pc are in r0, and r3
399 // no other registers need to be preserved, so invalidate them
400 __ invalidate_registers(false, true, true, false, true, true);
401
402 // check that there is really an exception
403 __ verify_not_null_oop(r0);
404
405 // search an exception handler (r0: exception oop, r3: throwing pc)
406 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); __ should_not_reach_here();
407 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
408 __ end_a_stub();
409
410 return offset;
411 }
412
413
414 // Emit the code to remove the frame from the stack in the exception
415 // unwind path.
416 int LIR_Assembler::emit_unwind_handler() {
417 #ifndef PRODUCT
418 if (CommentedAssembly) {
419 _masm->block_comment("Unwind handler");
420 }
421 #endif
422
423 int offset = code_offset();
424
425 // Fetch the exception from TLS and clear out exception related thread state
426 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
427 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
428 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
429
430 __ bind(_unwind_handler_entry);
431 __ verify_not_null_oop(r0);
432 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
433 __ mov(r19, r0); // Preserve the exception
434 }
435
436 // Preform needed unlocking
437 MonitorExitStub* stub = NULL;
438 if (method()->is_synchronized()) {
439 monitor_address(0, FrameMap::r0_opr);
440 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
441 __ unlock_object(r5, r4, r0, *stub->entry());
442 __ bind(*stub->continuation());
443 }
444
445 if (compilation()->env()->dtrace_method_probes()) {
446 __ mov(c_rarg0, rthread);
447 __ mov_metadata(c_rarg1, method()->constant_encoding());
448 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
449 }
450
451 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
452 __ mov(r0, r19); // Restore the exception
453 }
454
455 // remove the activation and dispatch to the unwind handler
456 __ block_comment("remove_frame and dispatch to the unwind handler");
457 __ remove_frame(initial_frame_size_in_bytes());
458 __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
459
460 // Emit the slow path assembly
461 if (stub != NULL) {
462 stub->emit_code(this);
463 }
464
465 return offset;
466 }
467
468
469 int LIR_Assembler::emit_deopt_handler() {
470 // if the last instruction is a call (typically to do a throw which
471 // is coming at the end after block reordering) the return address
472 // must still point into the code area in order to avoid assertion
473 // failures when searching for the corresponding bci => add a nop
474 // (was bug 5/14/1999 - gri)
475 __ nop();
476
477 // generate code for exception handler
478 address handler_base = __ start_a_stub(deopt_handler_size());
479 if (handler_base == NULL) {
480 // not enough space left for the handler
481 bailout("deopt handler overflow");
482 return -1;
483 }
484
485 int offset = code_offset();
486
487 __ adr(lr, pc());
488 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
489 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
490 __ end_a_stub();
491
492 return offset;
493 }
494
495 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
496 _masm->code_section()->relocate(adr, relocInfo::poll_type);
497 int pc_offset = code_offset();
498 flush_debug_info(pc_offset);
499 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
500 if (info->exception_handlers() != NULL) {
501 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
502 }
503 }
504
505 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
506 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
507
508 // Pop the stack before the safepoint code
509 __ remove_frame(initial_frame_size_in_bytes());
510
511 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
512 __ reserved_stack_check();
513 }
514
515 code_stub->set_safepoint_offset(__ offset());
516 __ relocate(relocInfo::poll_return_type);
517 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
518 __ ret(lr);
519 }
520
521 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
522 guarantee(info != NULL, "Shouldn't be NULL");
523 __ get_polling_page(rscratch1, relocInfo::poll_type);
524 add_debug_info_for_branch(info); // This isn't just debug info:
525 // it's the oop map
526 __ read_polling_page(rscratch1, relocInfo::poll_type);
527 return __ offset();
528 }
529
530
531 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
532 if (from_reg == r31_sp)
533 from_reg = sp;
534 if (to_reg == r31_sp)
535 to_reg = sp;
536 __ mov(to_reg, from_reg);
537 }
538
539 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
540
541
542 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
543 assert(src->is_constant(), "should not call otherwise");
544 assert(dest->is_register(), "should not call otherwise");
545 LIR_Const* c = src->as_constant_ptr();
546
547 switch (c->type()) {
548 case T_INT: {
549 assert(patch_code == lir_patch_none, "no patching handled here");
550 __ movw(dest->as_register(), c->as_jint());
551 break;
552 }
553
554 case T_ADDRESS: {
555 assert(patch_code == lir_patch_none, "no patching handled here");
556 __ mov(dest->as_register(), c->as_jint());
557 break;
558 }
559
560 case T_LONG: {
561 assert(patch_code == lir_patch_none, "no patching handled here");
562 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
563 break;
564 }
565
566 case T_OBJECT: {
567 if (patch_code == lir_patch_none) {
568 jobject2reg(c->as_jobject(), dest->as_register());
569 } else {
570 jobject2reg_with_patching(dest->as_register(), info);
571 }
572 break;
573 }
574
575 case T_METADATA: {
576 if (patch_code != lir_patch_none) {
577 klass2reg_with_patching(dest->as_register(), info);
578 } else {
579 __ mov_metadata(dest->as_register(), c->as_metadata());
580 }
581 break;
582 }
583
584 case T_FLOAT: {
585 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
586 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
587 } else {
588 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
589 __ ldrs(dest->as_float_reg(), Address(rscratch1));
590 }
591 break;
592 }
593
594 case T_DOUBLE: {
595 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
596 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
597 } else {
598 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
599 __ ldrd(dest->as_double_reg(), Address(rscratch1));
600 }
601 break;
602 }
603
604 default:
605 ShouldNotReachHere();
606 }
607 }
608
609 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
610 LIR_Const* c = src->as_constant_ptr();
611 switch (c->type()) {
612 case T_OBJECT:
613 {
614 if (! c->as_jobject())
615 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
616 else {
617 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
618 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
619 }
620 }
621 break;
622 case T_ADDRESS:
623 {
624 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
625 reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
626 }
627 case T_INT:
628 case T_FLOAT:
629 {
630 Register reg = zr;
631 if (c->as_jint_bits() == 0)
632 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
633 else {
634 __ movw(rscratch1, c->as_jint_bits());
635 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
636 }
637 }
638 break;
639 case T_LONG:
640 case T_DOUBLE:
641 {
642 Register reg = zr;
643 if (c->as_jlong_bits() == 0)
644 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
645 lo_word_offset_in_bytes));
646 else {
647 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
648 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
649 lo_word_offset_in_bytes));
650 }
651 }
652 break;
653 default:
654 ShouldNotReachHere();
655 }
656 }
657
658 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
659 assert(src->is_constant(), "should not call otherwise");
660 LIR_Const* c = src->as_constant_ptr();
661 LIR_Address* to_addr = dest->as_address_ptr();
662
663 void (Assembler::* insn)(Register Rt, const Address &adr);
664
665 switch (type) {
666 case T_ADDRESS:
667 assert(c->as_jint() == 0, "should be");
668 insn = &Assembler::str;
669 break;
670 case T_LONG:
671 assert(c->as_jlong() == 0, "should be");
672 insn = &Assembler::str;
673 break;
674 case T_INT:
675 assert(c->as_jint() == 0, "should be");
676 insn = &Assembler::strw;
677 break;
678 case T_OBJECT:
679 case T_ARRAY:
680 assert(c->as_jobject() == 0, "should be");
681 if (UseCompressedOops && !wide) {
682 insn = &Assembler::strw;
683 } else {
684 insn = &Assembler::str;
685 }
686 break;
687 case T_CHAR:
688 case T_SHORT:
689 assert(c->as_jint() == 0, "should be");
690 insn = &Assembler::strh;
691 break;
692 case T_BOOLEAN:
693 case T_BYTE:
694 assert(c->as_jint() == 0, "should be");
695 insn = &Assembler::strb;
696 break;
697 default:
698 ShouldNotReachHere();
699 insn = &Assembler::str; // unreachable
700 }
701
702 if (info) add_debug_info_for_null_check_here(info);
703 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
704 }
705
706 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
707 assert(src->is_register(), "should not call otherwise");
708 assert(dest->is_register(), "should not call otherwise");
709
710 // move between cpu-registers
711 if (dest->is_single_cpu()) {
712 if (src->type() == T_LONG) {
713 // Can do LONG -> OBJECT
714 move_regs(src->as_register_lo(), dest->as_register());
715 return;
716 }
717 assert(src->is_single_cpu(), "must match");
718 if (src->type() == T_OBJECT) {
719 __ verify_oop(src->as_register());
720 }
721 move_regs(src->as_register(), dest->as_register());
722
723 } else if (dest->is_double_cpu()) {
724 if (is_reference_type(src->type())) {
725 // Surprising to me but we can see move of a long to t_object
726 __ verify_oop(src->as_register());
727 move_regs(src->as_register(), dest->as_register_lo());
728 return;
729 }
730 assert(src->is_double_cpu(), "must match");
731 Register f_lo = src->as_register_lo();
732 Register f_hi = src->as_register_hi();
733 Register t_lo = dest->as_register_lo();
734 Register t_hi = dest->as_register_hi();
735 assert(f_hi == f_lo, "must be same");
736 assert(t_hi == t_lo, "must be same");
737 move_regs(f_lo, t_lo);
738
739 } else if (dest->is_single_fpu()) {
740 __ fmovs(dest->as_float_reg(), src->as_float_reg());
741
742 } else if (dest->is_double_fpu()) {
743 __ fmovd(dest->as_double_reg(), src->as_double_reg());
744
745 } else {
746 ShouldNotReachHere();
747 }
748 }
749
750 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
751 precond(src->is_register() && dest->is_stack());
752
753 uint const c_sz32 = sizeof(uint32_t);
754 uint const c_sz64 = sizeof(uint64_t);
755
756 if (src->is_single_cpu()) {
757 int index = dest->single_stack_ix();
758 if (is_reference_type(type)) {
759 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
760 __ verify_oop(src->as_register());
761 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
762 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
763 } else {
764 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
765 }
766
767 } else if (src->is_double_cpu()) {
768 int index = dest->double_stack_ix();
769 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
770 __ str(src->as_register_lo(), dest_addr_LO);
771
772 } else if (src->is_single_fpu()) {
773 int index = dest->single_stack_ix();
774 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
775
776 } else if (src->is_double_fpu()) {
777 int index = dest->double_stack_ix();
778 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
779
780 } else {
781 ShouldNotReachHere();
782 }
783 }
784
785
786 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
787 LIR_Address* to_addr = dest->as_address_ptr();
788 PatchingStub* patch = NULL;
789 Register compressed_src = rscratch1;
790
791 if (patch_code != lir_patch_none) {
792 deoptimize_trap(info);
793 return;
794 }
795
796 if (is_reference_type(type)) {
797 __ verify_oop(src->as_register());
798
799 if (UseCompressedOops && !wide) {
800 __ encode_heap_oop(compressed_src, src->as_register());
801 } else {
802 compressed_src = src->as_register();
803 }
804 }
805
806 int null_check_here = code_offset();
807 switch (type) {
808 case T_FLOAT: {
809 __ strs(src->as_float_reg(), as_Address(to_addr));
810 break;
811 }
812
813 case T_DOUBLE: {
814 __ strd(src->as_double_reg(), as_Address(to_addr));
815 break;
816 }
817
818 case T_ARRAY: // fall through
819 case T_OBJECT: // fall through
820 if (UseCompressedOops && !wide) {
821 __ strw(compressed_src, as_Address(to_addr, rscratch2));
822 } else {
823 __ str(compressed_src, as_Address(to_addr));
824 }
825 break;
826 case T_METADATA:
827 // We get here to store a method pointer to the stack to pass to
828 // a dtrace runtime call. This can't work on 64 bit with
829 // compressed klass ptrs: T_METADATA can be a compressed klass
830 // ptr or a 64 bit method pointer.
831 ShouldNotReachHere();
832 __ str(src->as_register(), as_Address(to_addr));
833 break;
834 case T_ADDRESS:
835 __ str(src->as_register(), as_Address(to_addr));
836 break;
837 case T_INT:
838 __ strw(src->as_register(), as_Address(to_addr));
839 break;
840
841 case T_LONG: {
842 __ str(src->as_register_lo(), as_Address_lo(to_addr));
843 break;
844 }
845
846 case T_BYTE: // fall through
847 case T_BOOLEAN: {
848 __ strb(src->as_register(), as_Address(to_addr));
849 break;
850 }
851
852 case T_CHAR: // fall through
853 case T_SHORT:
854 __ strh(src->as_register(), as_Address(to_addr));
855 break;
856
857 default:
858 ShouldNotReachHere();
859 }
860 if (info != NULL) {
861 add_debug_info_for_null_check(null_check_here, info);
862 }
863 }
864
865
866 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
867 precond(src->is_stack() && dest->is_register());
868
869 uint const c_sz32 = sizeof(uint32_t);
870 uint const c_sz64 = sizeof(uint64_t);
871
872 if (dest->is_single_cpu()) {
873 int index = src->single_stack_ix();
874 if (is_reference_type(type)) {
875 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
876 __ verify_oop(dest->as_register());
877 } else if (type == T_METADATA || type == T_ADDRESS) {
878 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
879 } else {
880 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
881 }
882
883 } else if (dest->is_double_cpu()) {
884 int index = src->double_stack_ix();
885 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
886 __ ldr(dest->as_register_lo(), src_addr_LO);
887
888 } else if (dest->is_single_fpu()) {
889 int index = src->single_stack_ix();
890 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
891
892 } else if (dest->is_double_fpu()) {
893 int index = src->double_stack_ix();
894 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
895
896 } else {
897 ShouldNotReachHere();
898 }
899 }
900
901
902 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
903 address target = NULL;
904 relocInfo::relocType reloc_type = relocInfo::none;
905
906 switch (patching_id(info)) {
907 case PatchingStub::access_field_id:
908 target = Runtime1::entry_for(Runtime1::access_field_patching_id);
909 reloc_type = relocInfo::section_word_type;
910 break;
911 case PatchingStub::load_klass_id:
912 target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
913 reloc_type = relocInfo::metadata_type;
914 break;
915 case PatchingStub::load_mirror_id:
916 target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
917 reloc_type = relocInfo::oop_type;
918 break;
919 case PatchingStub::load_appendix_id:
920 target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
921 reloc_type = relocInfo::oop_type;
922 break;
923 default: ShouldNotReachHere();
924 }
925
926 __ far_call(RuntimeAddress(target));
927 add_call_info_here(info);
928 }
929
930 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
931
932 LIR_Opr temp;
933 if (type == T_LONG || type == T_DOUBLE)
934 temp = FrameMap::rscratch1_long_opr;
935 else
936 temp = FrameMap::rscratch1_opr;
937
938 stack2reg(src, temp, src->type());
939 reg2stack(temp, dest, dest->type(), false);
940 }
941
942
943 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
944 LIR_Address* addr = src->as_address_ptr();
945 LIR_Address* from_addr = src->as_address_ptr();
946
947 if (addr->base()->type() == T_OBJECT) {
948 __ verify_oop(addr->base()->as_pointer_register());
949 }
950
951 if (patch_code != lir_patch_none) {
952 deoptimize_trap(info);
953 return;
954 }
955
956 if (info != NULL) {
957 add_debug_info_for_null_check_here(info);
958 }
959 int null_check_here = code_offset();
960 switch (type) {
961 case T_FLOAT: {
962 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
963 break;
964 }
965
966 case T_DOUBLE: {
967 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
968 break;
969 }
970
971 case T_ARRAY: // fall through
972 case T_OBJECT: // fall through
973 if (UseCompressedOops && !wide) {
974 __ ldrw(dest->as_register(), as_Address(from_addr));
975 } else {
976 __ ldr(dest->as_register(), as_Address(from_addr));
977 }
978 break;
979 case T_METADATA:
980 // We get here to store a method pointer to the stack to pass to
981 // a dtrace runtime call. This can't work on 64 bit with
982 // compressed klass ptrs: T_METADATA can be a compressed klass
983 // ptr or a 64 bit method pointer.
984 ShouldNotReachHere();
985 __ ldr(dest->as_register(), as_Address(from_addr));
986 break;
987 case T_ADDRESS:
988 __ ldr(dest->as_register(), as_Address(from_addr));
989 break;
990 case T_INT:
991 __ ldrw(dest->as_register(), as_Address(from_addr));
992 break;
993
994 case T_LONG: {
995 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
996 break;
997 }
998
999 case T_BYTE:
1000 __ ldrsb(dest->as_register(), as_Address(from_addr));
1001 break;
1002 case T_BOOLEAN: {
1003 __ ldrb(dest->as_register(), as_Address(from_addr));
1004 break;
1005 }
1006
1007 case T_CHAR:
1008 __ ldrh(dest->as_register(), as_Address(from_addr));
1009 break;
1010 case T_SHORT:
1011 __ ldrsh(dest->as_register(), as_Address(from_addr));
1012 break;
1013
1014 default:
1015 ShouldNotReachHere();
1016 }
1017
1018 if (is_reference_type(type)) {
1019 if (UseCompressedOops && !wide) {
1020 __ decode_heap_oop(dest->as_register());
1021 }
1022
1023 if (!UseZGC) {
1024 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1025 __ verify_oop(dest->as_register());
1026 }
1027 }
1028 }
1029
1030
1031 int LIR_Assembler::array_element_size(BasicType type) const {
1032 int elem_size = type2aelembytes(type);
1033 return exact_log2(elem_size);
1034 }
1035
1036
1037 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1038 switch (op->code()) {
1039 case lir_idiv:
1040 case lir_irem:
1041 arithmetic_idiv(op->code(),
1042 op->in_opr1(),
1043 op->in_opr2(),
1044 op->in_opr3(),
1045 op->result_opr(),
1046 op->info());
1047 break;
1048 case lir_fmad:
1049 __ fmaddd(op->result_opr()->as_double_reg(),
1050 op->in_opr1()->as_double_reg(),
1051 op->in_opr2()->as_double_reg(),
1052 op->in_opr3()->as_double_reg());
1053 break;
1054 case lir_fmaf:
1055 __ fmadds(op->result_opr()->as_float_reg(),
1056 op->in_opr1()->as_float_reg(),
1057 op->in_opr2()->as_float_reg(),
1058 op->in_opr3()->as_float_reg());
1059 break;
1060 default: ShouldNotReachHere(); break;
1061 }
1062 }
1063
1064 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1065 #ifdef ASSERT
1066 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1067 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1068 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1069 #endif
1070
1071 if (op->cond() == lir_cond_always) {
1072 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1073 __ b(*(op->label()));
1074 } else {
1075 Assembler::Condition acond;
1076 if (op->code() == lir_cond_float_branch) {
1077 bool is_unordered = (op->ublock() == op->block());
1078 // Assembler::EQ does not permit unordered branches, so we add
1079 // another branch here. Likewise, Assembler::NE does not permit
1080 // ordered branches.
1081 if ((is_unordered && op->cond() == lir_cond_equal)
1082 || (!is_unordered && op->cond() == lir_cond_notEqual))
1083 __ br(Assembler::VS, *(op->ublock()->label()));
1084 switch(op->cond()) {
1085 case lir_cond_equal: acond = Assembler::EQ; break;
1086 case lir_cond_notEqual: acond = Assembler::NE; break;
1087 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1088 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1089 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1090 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1091 default: ShouldNotReachHere();
1092 acond = Assembler::EQ; // unreachable
1093 }
1094 } else {
1095 switch (op->cond()) {
1096 case lir_cond_equal: acond = Assembler::EQ; break;
1097 case lir_cond_notEqual: acond = Assembler::NE; break;
1098 case lir_cond_less: acond = Assembler::LT; break;
1099 case lir_cond_lessEqual: acond = Assembler::LE; break;
1100 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1101 case lir_cond_greater: acond = Assembler::GT; break;
1102 case lir_cond_belowEqual: acond = Assembler::LS; break;
1103 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1104 default: ShouldNotReachHere();
1105 acond = Assembler::EQ; // unreachable
1106 }
1107 }
1108 __ br(acond,*(op->label()));
1109 }
1110 }
1111
1112
1113
1114 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1115 LIR_Opr src = op->in_opr();
1116 LIR_Opr dest = op->result_opr();
1117
1118 switch (op->bytecode()) {
1119 case Bytecodes::_i2f:
1120 {
1121 __ scvtfws(dest->as_float_reg(), src->as_register());
1122 break;
1123 }
1124 case Bytecodes::_i2d:
1125 {
1126 __ scvtfwd(dest->as_double_reg(), src->as_register());
1127 break;
1128 }
1129 case Bytecodes::_l2d:
1130 {
1131 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1132 break;
1133 }
1134 case Bytecodes::_l2f:
1135 {
1136 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1137 break;
1138 }
1139 case Bytecodes::_f2d:
1140 {
1141 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1142 break;
1143 }
1144 case Bytecodes::_d2f:
1145 {
1146 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1147 break;
1148 }
1149 case Bytecodes::_i2c:
1150 {
1151 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1152 break;
1153 }
1154 case Bytecodes::_i2l:
1155 {
1156 __ sxtw(dest->as_register_lo(), src->as_register());
1157 break;
1158 }
1159 case Bytecodes::_i2s:
1160 {
1161 __ sxth(dest->as_register(), src->as_register());
1162 break;
1163 }
1164 case Bytecodes::_i2b:
1165 {
1166 __ sxtb(dest->as_register(), src->as_register());
1167 break;
1168 }
1169 case Bytecodes::_l2i:
1170 {
1171 _masm->block_comment("FIXME: This could be a no-op");
1172 __ uxtw(dest->as_register(), src->as_register_lo());
1173 break;
1174 }
1175 case Bytecodes::_d2l:
1176 {
1177 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1178 break;
1179 }
1180 case Bytecodes::_f2i:
1181 {
1182 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1183 break;
1184 }
1185 case Bytecodes::_f2l:
1186 {
1187 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1188 break;
1189 }
1190 case Bytecodes::_d2i:
1191 {
1192 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1193 break;
1194 }
1195 default: ShouldNotReachHere();
1196 }
1197 }
1198
1199 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1200 if (op->init_check()) {
1201 __ ldrb(rscratch1, Address(op->klass()->as_register(),
1202 InstanceKlass::init_state_offset()));
1203 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1204 add_debug_info_for_null_check_here(op->stub()->info());
1205 __ br(Assembler::NE, *op->stub()->entry());
1206 }
1207 __ allocate_object(op->obj()->as_register(),
1208 op->tmp1()->as_register(),
1209 op->tmp2()->as_register(),
1210 op->header_size(),
1211 op->object_size(),
1212 op->klass()->as_register(),
1213 *op->stub()->entry());
1214 __ bind(*op->stub()->continuation());
1215 }
1216
1217 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1218 Register len = op->len()->as_register();
1219 __ uxtw(len, len);
1220
1221 if (UseSlowPath ||
1222 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1223 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1224 __ b(*op->stub()->entry());
1225 } else {
1226 Register tmp1 = op->tmp1()->as_register();
1227 Register tmp2 = op->tmp2()->as_register();
1228 Register tmp3 = op->tmp3()->as_register();
1229 if (len == tmp1) {
1230 tmp1 = tmp3;
1231 } else if (len == tmp2) {
1232 tmp2 = tmp3;
1233 } else if (len == tmp3) {
1234 // everything is ok
1235 } else {
1236 __ mov(tmp3, len);
1237 }
1238 __ allocate_array(op->obj()->as_register(),
1239 len,
1240 tmp1,
1241 tmp2,
1242 arrayOopDesc::header_size(op->type()),
1243 array_element_size(op->type()),
1244 op->klass()->as_register(),
1245 *op->stub()->entry());
1246 }
1247 __ bind(*op->stub()->continuation());
1248 }
1249
1250 void LIR_Assembler::type_profile_helper(Register mdo,
1251 ciMethodData *md, ciProfileData *data,
1252 Register recv, Label* update_done) {
1253 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1254 Label next_test;
1255 // See if the receiver is receiver[n].
1256 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1257 __ ldr(rscratch1, Address(rscratch2));
1258 __ cmp(recv, rscratch1);
1259 __ br(Assembler::NE, next_test);
1260 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1261 __ addptr(data_addr, DataLayout::counter_increment);
1262 __ b(*update_done);
1263 __ bind(next_test);
1264 }
1265
1266 // Didn't find receiver; find next empty slot and fill it in
1267 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1268 Label next_test;
1269 __ lea(rscratch2,
1270 Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1271 Address recv_addr(rscratch2);
1272 __ ldr(rscratch1, recv_addr);
1273 __ cbnz(rscratch1, next_test);
1274 __ str(recv, recv_addr);
1275 __ mov(rscratch1, DataLayout::counter_increment);
1276 __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1277 __ str(rscratch1, Address(rscratch2));
1278 __ b(*update_done);
1279 __ bind(next_test);
1280 }
1281 }
1282
1283 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1284 // we always need a stub for the failure case.
1285 CodeStub* stub = op->stub();
1286 Register obj = op->object()->as_register();
1287 Register k_RInfo = op->tmp1()->as_register();
1288 Register klass_RInfo = op->tmp2()->as_register();
1289 Register dst = op->result_opr()->as_register();
1290 ciKlass* k = op->klass();
1291 Register Rtmp1 = noreg;
1292
1293 // check if it needs to be profiled
1294 ciMethodData* md;
1295 ciProfileData* data;
1296
1297 const bool should_profile = op->should_profile();
1298
1299 if (should_profile) {
1300 ciMethod* method = op->profiled_method();
1301 assert(method != NULL, "Should have method");
1302 int bci = op->profiled_bci();
1303 md = method->method_data_or_null();
1304 assert(md != NULL, "Sanity");
1305 data = md->bci_to_data(bci);
1306 assert(data != NULL, "need data for type check");
1307 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1308 }
1309 Label profile_cast_success, profile_cast_failure;
1310 Label *success_target = should_profile ? &profile_cast_success : success;
1311 Label *failure_target = should_profile ? &profile_cast_failure : failure;
1312
1313 if (obj == k_RInfo) {
1314 k_RInfo = dst;
1315 } else if (obj == klass_RInfo) {
1316 klass_RInfo = dst;
1317 }
1318 if (k->is_loaded() && !UseCompressedClassPointers) {
1319 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1320 } else {
1321 Rtmp1 = op->tmp3()->as_register();
1322 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1323 }
1324
1325 assert_different_registers(obj, k_RInfo, klass_RInfo);
1326
1327 if (should_profile) {
1328 Label not_null;
1329 __ cbnz(obj, not_null);
1330 // Object is null; update MDO and exit
1331 Register mdo = klass_RInfo;
1332 __ mov_metadata(mdo, md->constant_encoding());
1333 Address data_addr
1334 = __ form_address(rscratch2, mdo,
1335 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1336 0);
1337 __ ldrb(rscratch1, data_addr);
1338 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1339 __ strb(rscratch1, data_addr);
1340 __ b(*obj_is_null);
1341 __ bind(not_null);
1342 } else {
1343 __ cbz(obj, *obj_is_null);
1344 }
1345
1346 if (!k->is_loaded()) {
1347 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1348 } else {
1349 __ mov_metadata(k_RInfo, k->constant_encoding());
1350 }
1351 __ verify_oop(obj);
1352
1353 if (op->fast_check()) {
1354 // get object class
1355 // not a safepoint as obj null check happens earlier
1356 __ load_klass(rscratch1, obj);
1357 __ cmp( rscratch1, k_RInfo);
1358
1359 __ br(Assembler::NE, *failure_target);
1360 // successful cast, fall through to profile or jump
1361 } else {
1362 // get object class
1363 // not a safepoint as obj null check happens earlier
1364 __ load_klass(klass_RInfo, obj);
1365 if (k->is_loaded()) {
1366 // See if we get an immediate positive hit
1367 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1368 __ cmp(k_RInfo, rscratch1);
1369 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1370 __ br(Assembler::NE, *failure_target);
1371 // successful cast, fall through to profile or jump
1372 } else {
1373 // See if we get an immediate positive hit
1374 __ br(Assembler::EQ, *success_target);
1375 // check for self
1376 __ cmp(klass_RInfo, k_RInfo);
1377 __ br(Assembler::EQ, *success_target);
1378
1379 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1380 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1381 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1382 // result is a boolean
1383 __ cbzw(klass_RInfo, *failure_target);
1384 // successful cast, fall through to profile or jump
1385 }
1386 } else {
1387 // perform the fast part of the checking logic
1388 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1389 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1390 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1391 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1392 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1393 // result is a boolean
1394 __ cbz(k_RInfo, *failure_target);
1395 // successful cast, fall through to profile or jump
1396 }
1397 }
1398 if (should_profile) {
1399 Register mdo = klass_RInfo, recv = k_RInfo;
1400 __ bind(profile_cast_success);
1401 __ mov_metadata(mdo, md->constant_encoding());
1402 __ load_klass(recv, obj);
1403 Label update_done;
1404 type_profile_helper(mdo, md, data, recv, success);
1405 __ b(*success);
1406
1407 __ bind(profile_cast_failure);
1408 __ mov_metadata(mdo, md->constant_encoding());
1409 Address counter_addr
1410 = __ form_address(rscratch2, mdo,
1411 md->byte_offset_of_slot(data, CounterData::count_offset()),
1412 0);
1413 __ ldr(rscratch1, counter_addr);
1414 __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1415 __ str(rscratch1, counter_addr);
1416 __ b(*failure);
1417 }
1418 __ b(*success);
1419 }
1420
1421
1422 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1423 const bool should_profile = op->should_profile();
1424
1425 LIR_Code code = op->code();
1426 if (code == lir_store_check) {
1427 Register value = op->object()->as_register();
1428 Register array = op->array()->as_register();
1429 Register k_RInfo = op->tmp1()->as_register();
1430 Register klass_RInfo = op->tmp2()->as_register();
1431 Register Rtmp1 = op->tmp3()->as_register();
1432
1433 CodeStub* stub = op->stub();
1434
1435 // check if it needs to be profiled
1436 ciMethodData* md;
1437 ciProfileData* data;
1438
1439 if (should_profile) {
1440 ciMethod* method = op->profiled_method();
1441 assert(method != NULL, "Should have method");
1442 int bci = op->profiled_bci();
1443 md = method->method_data_or_null();
1444 assert(md != NULL, "Sanity");
1445 data = md->bci_to_data(bci);
1446 assert(data != NULL, "need data for type check");
1447 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1448 }
1449 Label profile_cast_success, profile_cast_failure, done;
1450 Label *success_target = should_profile ? &profile_cast_success : &done;
1451 Label *failure_target = should_profile ? &profile_cast_failure : stub->entry();
1452
1453 if (should_profile) {
1454 Label not_null;
1455 __ cbnz(value, not_null);
1456 // Object is null; update MDO and exit
1457 Register mdo = klass_RInfo;
1458 __ mov_metadata(mdo, md->constant_encoding());
1459 Address data_addr
1460 = __ form_address(rscratch2, mdo,
1461 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1462 0);
1463 __ ldrb(rscratch1, data_addr);
1464 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1465 __ strb(rscratch1, data_addr);
1466 __ b(done);
1467 __ bind(not_null);
1468 } else {
1469 __ cbz(value, done);
1470 }
1471
1472 add_debug_info_for_null_check_here(op->info_for_exception());
1473 __ load_klass(k_RInfo, array);
1474 __ load_klass(klass_RInfo, value);
1475
1476 // get instance klass (it's already uncompressed)
1477 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1478 // perform the fast part of the checking logic
1479 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1480 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1481 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1482 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1483 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1484 // result is a boolean
1485 __ cbzw(k_RInfo, *failure_target);
1486 // fall through to the success case
1487
1488 if (should_profile) {
1489 Register mdo = klass_RInfo, recv = k_RInfo;
1490 __ bind(profile_cast_success);
1491 __ mov_metadata(mdo, md->constant_encoding());
1492 __ load_klass(recv, value);
1493 Label update_done;
1494 type_profile_helper(mdo, md, data, recv, &done);
1495 __ b(done);
1496
1497 __ bind(profile_cast_failure);
1498 __ mov_metadata(mdo, md->constant_encoding());
1499 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1500 __ lea(rscratch2, counter_addr);
1501 __ ldr(rscratch1, Address(rscratch2));
1502 __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1503 __ str(rscratch1, Address(rscratch2));
1504 __ b(*stub->entry());
1505 }
1506
1507 __ bind(done);
1508 } else if (code == lir_checkcast) {
1509 Register obj = op->object()->as_register();
1510 Register dst = op->result_opr()->as_register();
1511 Label success;
1512 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1513 __ bind(success);
1514 if (dst != obj) {
1515 __ mov(dst, obj);
1516 }
1517 } else if (code == lir_instanceof) {
1518 Register obj = op->object()->as_register();
1519 Register dst = op->result_opr()->as_register();
1520 Label success, failure, done;
1521 emit_typecheck_helper(op, &success, &failure, &failure);
1522 __ bind(failure);
1523 __ mov(dst, zr);
1524 __ b(done);
1525 __ bind(success);
1526 __ mov(dst, 1);
1527 __ bind(done);
1528 } else {
1529 ShouldNotReachHere();
1530 }
1531 }
1532
1533 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1534 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1535 __ cset(rscratch1, Assembler::NE);
1536 __ membar(__ AnyAny);
1537 }
1538
1539 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1540 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1541 __ cset(rscratch1, Assembler::NE);
1542 __ membar(__ AnyAny);
1543 }
1544
1545
1546 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1547 assert(VM_Version::supports_cx8(), "wrong machine");
1548 Register addr;
1549 if (op->addr()->is_register()) {
1550 addr = as_reg(op->addr());
1551 } else {
1552 assert(op->addr()->is_address(), "what else?");
1553 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1554 assert(addr_ptr->disp() == 0, "need 0 disp");
1555 assert(addr_ptr->index() == LIR_OprDesc::illegalOpr(), "need 0 index");
1556 addr = as_reg(addr_ptr->base());
1557 }
1558 Register newval = as_reg(op->new_value());
1559 Register cmpval = as_reg(op->cmp_value());
1560
1561 if (op->code() == lir_cas_obj) {
1562 if (UseCompressedOops) {
1563 Register t1 = op->tmp1()->as_register();
1564 assert(op->tmp1()->is_valid(), "must be");
1565 __ encode_heap_oop(t1, cmpval);
1566 cmpval = t1;
1567 __ encode_heap_oop(rscratch2, newval);
1568 newval = rscratch2;
1569 casw(addr, newval, cmpval);
1570 } else {
1571 casl(addr, newval, cmpval);
1572 }
1573 } else if (op->code() == lir_cas_int) {
1574 casw(addr, newval, cmpval);
1575 } else {
1576 casl(addr, newval, cmpval);
1577 }
1578 }
1579
1580
1581 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1582
1583 Assembler::Condition acond, ncond;
1584 switch (condition) {
1585 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1586 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1587 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1588 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1589 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1590 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1591 case lir_cond_belowEqual:
1592 case lir_cond_aboveEqual:
1593 default: ShouldNotReachHere();
1594 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1595 }
1596
1597 assert(result->is_single_cpu() || result->is_double_cpu(),
1598 "expect single register for result");
1599 if (opr1->is_constant() && opr2->is_constant()
1600 && opr1->type() == T_INT && opr2->type() == T_INT) {
1601 jint val1 = opr1->as_jint();
1602 jint val2 = opr2->as_jint();
1603 if (val1 == 0 && val2 == 1) {
1604 __ cset(result->as_register(), ncond);
1605 return;
1606 } else if (val1 == 1 && val2 == 0) {
1607 __ cset(result->as_register(), acond);
1608 return;
1609 }
1610 }
1611
1612 if (opr1->is_constant() && opr2->is_constant()
1613 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1614 jlong val1 = opr1->as_jlong();
1615 jlong val2 = opr2->as_jlong();
1616 if (val1 == 0 && val2 == 1) {
1617 __ cset(result->as_register_lo(), ncond);
1618 return;
1619 } else if (val1 == 1 && val2 == 0) {
1620 __ cset(result->as_register_lo(), acond);
1621 return;
1622 }
1623 }
1624
1625 if (opr1->is_stack()) {
1626 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1627 opr1 = FrameMap::rscratch1_opr;
1628 } else if (opr1->is_constant()) {
1629 LIR_Opr tmp
1630 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1631 const2reg(opr1, tmp, lir_patch_none, NULL);
1632 opr1 = tmp;
1633 }
1634
1635 if (opr2->is_stack()) {
1636 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1637 opr2 = FrameMap::rscratch2_opr;
1638 } else if (opr2->is_constant()) {
1639 LIR_Opr tmp
1640 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1641 const2reg(opr2, tmp, lir_patch_none, NULL);
1642 opr2 = tmp;
1643 }
1644
1645 if (result->type() == T_LONG)
1646 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1647 else
1648 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1649 }
1650
1651 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1652 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1653
1654 if (left->is_single_cpu()) {
1655 Register lreg = left->as_register();
1656 Register dreg = as_reg(dest);
1657
1658 if (right->is_single_cpu()) {
1659 // cpu register - cpu register
1660
1661 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1662 "should be");
1663 Register rreg = right->as_register();
1664 switch (code) {
1665 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1666 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1667 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1668 default: ShouldNotReachHere();
1669 }
1670
1671 } else if (right->is_double_cpu()) {
1672 Register rreg = right->as_register_lo();
1673 // single_cpu + double_cpu: can happen with obj+long
1674 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1675 switch (code) {
1676 case lir_add: __ add(dreg, lreg, rreg); break;
1677 case lir_sub: __ sub(dreg, lreg, rreg); break;
1678 default: ShouldNotReachHere();
1679 }
1680 } else if (right->is_constant()) {
1681 // cpu register - constant
1682 jlong c;
1683
1684 // FIXME. This is fugly: we really need to factor all this logic.
1685 switch(right->type()) {
1686 case T_LONG:
1687 c = right->as_constant_ptr()->as_jlong();
1688 break;
1689 case T_INT:
1690 case T_ADDRESS:
1691 c = right->as_constant_ptr()->as_jint();
1692 break;
1693 default:
1694 ShouldNotReachHere();
1695 c = 0; // unreachable
1696 break;
1697 }
1698
1699 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1700 if (c == 0 && dreg == lreg) {
1701 COMMENT("effective nop elided");
1702 return;
1703 }
1704 switch(left->type()) {
1705 case T_INT:
1706 switch (code) {
1707 case lir_add: __ addw(dreg, lreg, c); break;
1708 case lir_sub: __ subw(dreg, lreg, c); break;
1709 default: ShouldNotReachHere();
1710 }
1711 break;
1712 case T_OBJECT:
1713 case T_ADDRESS:
1714 switch (code) {
1715 case lir_add: __ add(dreg, lreg, c); break;
1716 case lir_sub: __ sub(dreg, lreg, c); break;
1717 default: ShouldNotReachHere();
1718 }
1719 break;
1720 default:
1721 ShouldNotReachHere();
1722 }
1723 } else {
1724 ShouldNotReachHere();
1725 }
1726
1727 } else if (left->is_double_cpu()) {
1728 Register lreg_lo = left->as_register_lo();
1729
1730 if (right->is_double_cpu()) {
1731 // cpu register - cpu register
1732 Register rreg_lo = right->as_register_lo();
1733 switch (code) {
1734 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1735 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1736 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1737 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1738 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1739 default:
1740 ShouldNotReachHere();
1741 }
1742
1743 } else if (right->is_constant()) {
1744 jlong c = right->as_constant_ptr()->as_jlong();
1745 Register dreg = as_reg(dest);
1746 switch (code) {
1747 case lir_add:
1748 case lir_sub:
1749 if (c == 0 && dreg == lreg_lo) {
1750 COMMENT("effective nop elided");
1751 return;
1752 }
1753 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1754 break;
1755 case lir_div:
1756 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1757 if (c == 1) {
1758 // move lreg_lo to dreg if divisor is 1
1759 __ mov(dreg, lreg_lo);
1760 } else {
1761 unsigned int shift = log2i_exact(c);
1762 // use rscratch1 as intermediate result register
1763 __ asr(rscratch1, lreg_lo, 63);
1764 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1765 __ asr(dreg, rscratch1, shift);
1766 }
1767 break;
1768 case lir_rem:
1769 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1770 if (c == 1) {
1771 // move 0 to dreg if divisor is 1
1772 __ mov(dreg, zr);
1773 } else {
1774 // use rscratch1 as intermediate result register
1775 __ negs(rscratch1, lreg_lo);
1776 __ andr(dreg, lreg_lo, c - 1);
1777 __ andr(rscratch1, rscratch1, c - 1);
1778 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1779 }
1780 break;
1781 default:
1782 ShouldNotReachHere();
1783 }
1784 } else {
1785 ShouldNotReachHere();
1786 }
1787 } else if (left->is_single_fpu()) {
1788 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1789 switch (code) {
1790 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1791 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1792 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1793 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1794 default:
1795 ShouldNotReachHere();
1796 }
1797 } else if (left->is_double_fpu()) {
1798 if (right->is_double_fpu()) {
1799 // fpu register - fpu register
1800 switch (code) {
1801 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1802 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1803 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1804 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1805 default:
1806 ShouldNotReachHere();
1807 }
1808 } else {
1809 if (right->is_constant()) {
1810 ShouldNotReachHere();
1811 }
1812 ShouldNotReachHere();
1813 }
1814 } else if (left->is_single_stack() || left->is_address()) {
1815 assert(left == dest, "left and dest must be equal");
1816 ShouldNotReachHere();
1817 } else {
1818 ShouldNotReachHere();
1819 }
1820 }
1821
1822 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1823
1824
1825 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1826 switch(code) {
1827 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1828 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1829 default : ShouldNotReachHere();
1830 }
1831 }
1832
1833 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1834
1835 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1836 Register Rleft = left->is_single_cpu() ? left->as_register() :
1837 left->as_register_lo();
1838 if (dst->is_single_cpu()) {
1839 Register Rdst = dst->as_register();
1840 if (right->is_constant()) {
1841 switch (code) {
1842 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1843 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1844 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1845 default: ShouldNotReachHere(); break;
1846 }
1847 } else {
1848 Register Rright = right->is_single_cpu() ? right->as_register() :
1849 right->as_register_lo();
1850 switch (code) {
1851 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1852 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1853 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1854 default: ShouldNotReachHere(); break;
1855 }
1856 }
1857 } else {
1858 Register Rdst = dst->as_register_lo();
1859 if (right->is_constant()) {
1860 switch (code) {
1861 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1862 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1863 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1864 default: ShouldNotReachHere(); break;
1865 }
1866 } else {
1867 Register Rright = right->is_single_cpu() ? right->as_register() :
1868 right->as_register_lo();
1869 switch (code) {
1870 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1871 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1872 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1873 default: ShouldNotReachHere(); break;
1874 }
1875 }
1876 }
1877 }
1878
1879
1880
1881 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1882
1883 // opcode check
1884 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1885 bool is_irem = (code == lir_irem);
1886
1887 // operand check
1888 assert(left->is_single_cpu(), "left must be register");
1889 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1890 assert(result->is_single_cpu(), "result must be register");
1891 Register lreg = left->as_register();
1892 Register dreg = result->as_register();
1893
1894 // power-of-2 constant check and codegen
1895 if (right->is_constant()) {
1896 int c = right->as_constant_ptr()->as_jint();
1897 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1898 if (is_irem) {
1899 if (c == 1) {
1900 // move 0 to dreg if divisor is 1
1901 __ movw(dreg, zr);
1902 } else {
1903 // use rscratch1 as intermediate result register
1904 __ negsw(rscratch1, lreg);
1905 __ andw(dreg, lreg, c - 1);
1906 __ andw(rscratch1, rscratch1, c - 1);
1907 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1908 }
1909 } else {
1910 if (c == 1) {
1911 // move lreg to dreg if divisor is 1
1912 __ movw(dreg, lreg);
1913 } else {
1914 unsigned int shift = exact_log2(c);
1915 // use rscratch1 as intermediate result register
1916 __ asrw(rscratch1, lreg, 31);
1917 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1918 __ asrw(dreg, rscratch1, shift);
1919 }
1920 }
1921 } else {
1922 Register rreg = right->as_register();
1923 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1924 }
1925 }
1926
1927
1928 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1929 if (opr1->is_constant() && opr2->is_single_cpu()) {
1930 // tableswitch
1931 Register reg = as_reg(opr2);
1932 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1933 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1934 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1935 Register reg1 = as_reg(opr1);
1936 if (opr2->is_single_cpu()) {
1937 // cpu register - cpu register
1938 Register reg2 = opr2->as_register();
1939 if (is_reference_type(opr1->type())) {
1940 __ cmpoop(reg1, reg2);
1941 } else {
1942 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1943 __ cmpw(reg1, reg2);
1944 }
1945 return;
1946 }
1947 if (opr2->is_double_cpu()) {
1948 // cpu register - cpu register
1949 Register reg2 = opr2->as_register_lo();
1950 __ cmp(reg1, reg2);
1951 return;
1952 }
1953
1954 if (opr2->is_constant()) {
1955 bool is_32bit = false; // width of register operand
1956 jlong imm;
1957
1958 switch(opr2->type()) {
1959 case T_INT:
1960 imm = opr2->as_constant_ptr()->as_jint();
1961 is_32bit = true;
1962 break;
1963 case T_LONG:
1964 imm = opr2->as_constant_ptr()->as_jlong();
1965 break;
1966 case T_ADDRESS:
1967 imm = opr2->as_constant_ptr()->as_jint();
1968 break;
1969 case T_METADATA:
1970 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1971 break;
1972 case T_OBJECT:
1973 case T_ARRAY:
1974 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1975 __ cmpoop(reg1, rscratch1);
1976 return;
1977 default:
1978 ShouldNotReachHere();
1979 imm = 0; // unreachable
1980 break;
1981 }
1982
1983 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1984 if (is_32bit)
1985 __ cmpw(reg1, imm);
1986 else
1987 __ subs(zr, reg1, imm);
1988 return;
1989 } else {
1990 __ mov(rscratch1, imm);
1991 if (is_32bit)
1992 __ cmpw(reg1, rscratch1);
1993 else
1994 __ cmp(reg1, rscratch1);
1995 return;
1996 }
1997 } else
1998 ShouldNotReachHere();
1999 } else if (opr1->is_single_fpu()) {
2000 FloatRegister reg1 = opr1->as_float_reg();
2001 assert(opr2->is_single_fpu(), "expect single float register");
2002 FloatRegister reg2 = opr2->as_float_reg();
2003 __ fcmps(reg1, reg2);
2004 } else if (opr1->is_double_fpu()) {
2005 FloatRegister reg1 = opr1->as_double_reg();
2006 assert(opr2->is_double_fpu(), "expect double float register");
2007 FloatRegister reg2 = opr2->as_double_reg();
2008 __ fcmpd(reg1, reg2);
2009 } else {
2010 ShouldNotReachHere();
2011 }
2012 }
2013
2014 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2015 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2016 bool is_unordered_less = (code == lir_ucmp_fd2i);
2017 if (left->is_single_fpu()) {
2018 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2019 } else if (left->is_double_fpu()) {
2020 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2021 } else {
2022 ShouldNotReachHere();
2023 }
2024 } else if (code == lir_cmp_l2i) {
2025 Label done;
2026 __ cmp(left->as_register_lo(), right->as_register_lo());
2027 __ mov(dst->as_register(), (uint64_t)-1L);
2028 __ br(Assembler::LT, done);
2029 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2030 __ bind(done);
2031 } else {
2032 ShouldNotReachHere();
2033 }
2034 }
2035
2036
2037 void LIR_Assembler::align_call(LIR_Code code) { }
2038
2039
2040 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2041 address call = __ trampoline_call(Address(op->addr(), rtype));
2042 if (call == NULL) {
2043 bailout("trampoline stub overflow");
2044 return;
2045 }
2046 add_call_info(code_offset(), op->info());
2047 }
2048
2049
2050 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2051 address call = __ ic_call(op->addr());
2052 if (call == NULL) {
2053 bailout("trampoline stub overflow");
2054 return;
2055 }
2056 add_call_info(code_offset(), op->info());
2057 }
2058
2059 void LIR_Assembler::emit_static_call_stub() {
2060 address call_pc = __ pc();
2061 address stub = __ start_a_stub(call_stub_size());
2062 if (stub == NULL) {
2063 bailout("static call stub overflow");
2064 return;
2065 }
2066
2067 int start = __ offset();
2068
2069 __ relocate(static_stub_Relocation::spec(call_pc));
2070 __ emit_static_call_stub();
2071
2072 assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size()
2073 <= call_stub_size(), "stub too big");
2074 __ end_a_stub();
2075 }
2076
2077
2078 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2079 assert(exceptionOop->as_register() == r0, "must match");
2080 assert(exceptionPC->as_register() == r3, "must match");
2081
2082 // exception object is not added to oop map by LinearScan
2083 // (LinearScan assumes that no oops are in fixed registers)
2084 info->add_register_oop(exceptionOop);
2085 Runtime1::StubID unwind_id;
2086
2087 // get current pc information
2088 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2089 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2090 // As no instructions have been generated yet for this LIR node it's
2091 // possible that an oop map already exists for the current offset.
2092 // In that case insert an dummy NOP here to ensure all oop map PCs
2093 // are unique. See JDK-8237483.
2094 __ nop();
2095 }
2096 int pc_for_athrow_offset = __ offset();
2097 InternalAddress pc_for_athrow(__ pc());
2098 __ adr(exceptionPC->as_register(), pc_for_athrow);
2099 add_call_info(pc_for_athrow_offset, info); // for exception handler
2100
2101 __ verify_not_null_oop(r0);
2102 // search an exception handler (r0: exception oop, r3: throwing pc)
2103 if (compilation()->has_fpu_code()) {
2104 unwind_id = Runtime1::handle_exception_id;
2105 } else {
2106 unwind_id = Runtime1::handle_exception_nofpu_id;
2107 }
2108 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2109
2110 // FIXME: enough room for two byte trap ????
2111 __ nop();
2112 }
2113
2114
2115 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2116 assert(exceptionOop->as_register() == r0, "must match");
2117
2118 __ b(_unwind_handler_entry);
2119 }
2120
2121
2122 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2123 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2124 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2125
2126 switch (left->type()) {
2127 case T_INT: {
2128 switch (code) {
2129 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2130 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2131 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2132 default:
2133 ShouldNotReachHere();
2134 break;
2135 }
2136 break;
2137 case T_LONG:
2138 case T_ADDRESS:
2139 case T_OBJECT:
2140 switch (code) {
2141 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2142 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2143 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2144 default:
2145 ShouldNotReachHere();
2146 break;
2147 }
2148 break;
2149 default:
2150 ShouldNotReachHere();
2151 break;
2152 }
2153 }
2154 }
2155
2156
2157 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2158 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2159 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2160
2161 switch (left->type()) {
2162 case T_INT: {
2163 switch (code) {
2164 case lir_shl: __ lslw (dreg, lreg, count); break;
2165 case lir_shr: __ asrw (dreg, lreg, count); break;
2166 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2167 default:
2168 ShouldNotReachHere();
2169 break;
2170 }
2171 break;
2172 case T_LONG:
2173 case T_ADDRESS:
2174 case T_OBJECT:
2175 switch (code) {
2176 case lir_shl: __ lsl (dreg, lreg, count); break;
2177 case lir_shr: __ asr (dreg, lreg, count); break;
2178 case lir_ushr: __ lsr (dreg, lreg, count); break;
2179 default:
2180 ShouldNotReachHere();
2181 break;
2182 }
2183 break;
2184 default:
2185 ShouldNotReachHere();
2186 break;
2187 }
2188 }
2189 }
2190
2191
2192 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2193 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2194 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2195 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2196 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2197 }
2198
2199
2200 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2201 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2202 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2203 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2204 __ mov (rscratch1, c);
2205 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2206 }
2207
2208
2209 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2210 ShouldNotReachHere();
2211 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2212 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2213 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2214 __ lea(rscratch1, __ constant_oop_address(o));
2215 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2216 }
2217
2218
2219 // This code replaces a call to arraycopy; no exception may
2220 // be thrown in this code, they must be thrown in the System.arraycopy
2221 // activation frame; we could save some checks if this would not be the case
2222 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2223 ciArrayKlass* default_type = op->expected_type();
2224 Register src = op->src()->as_register();
2225 Register dst = op->dst()->as_register();
2226 Register src_pos = op->src_pos()->as_register();
2227 Register dst_pos = op->dst_pos()->as_register();
2228 Register length = op->length()->as_register();
2229 Register tmp = op->tmp()->as_register();
2230
2231 CodeStub* stub = op->stub();
2232 int flags = op->flags();
2233 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2234 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2235
2236 // if we don't know anything, just go through the generic arraycopy
2237 if (default_type == NULL // || basic_type == T_OBJECT
2238 ) {
2239 Label done;
2240 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2241
2242 // Save the arguments in case the generic arraycopy fails and we
2243 // have to fall back to the JNI stub
2244 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2245 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2246 __ str(src, Address(sp, 4*BytesPerWord));
2247
2248 address copyfunc_addr = StubRoutines::generic_arraycopy();
2249 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2250
2251 // The arguments are in java calling convention so we shift them
2252 // to C convention
2253 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2254 __ mov(c_rarg0, j_rarg0);
2255 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2256 __ mov(c_rarg1, j_rarg1);
2257 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2258 __ mov(c_rarg2, j_rarg2);
2259 assert_different_registers(c_rarg3, j_rarg4);
2260 __ mov(c_rarg3, j_rarg3);
2261 __ mov(c_rarg4, j_rarg4);
2262 #ifndef PRODUCT
2263 if (PrintC1Statistics) {
2264 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2265 }
2266 #endif
2267 __ far_call(RuntimeAddress(copyfunc_addr));
2268
2269 __ cbz(r0, *stub->continuation());
2270
2271 // Reload values from the stack so they are where the stub
2272 // expects them.
2273 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2274 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2275 __ ldr(src, Address(sp, 4*BytesPerWord));
2276
2277 // r0 is -1^K where K == partial copied count
2278 __ eonw(rscratch1, r0, zr);
2279 // adjust length down and src/end pos up by partial copied count
2280 __ subw(length, length, rscratch1);
2281 __ addw(src_pos, src_pos, rscratch1);
2282 __ addw(dst_pos, dst_pos, rscratch1);
2283 __ b(*stub->entry());
2284
2285 __ bind(*stub->continuation());
2286 return;
2287 }
2288
2289 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2290
2291 int elem_size = type2aelembytes(basic_type);
2292 int scale = exact_log2(elem_size);
2293
2294 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2295 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2296 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2297 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2298
2299 // test for NULL
2300 if (flags & LIR_OpArrayCopy::src_null_check) {
2301 __ cbz(src, *stub->entry());
2302 }
2303 if (flags & LIR_OpArrayCopy::dst_null_check) {
2304 __ cbz(dst, *stub->entry());
2305 }
2306
2307 // If the compiler was not able to prove that exact type of the source or the destination
2308 // of the arraycopy is an array type, check at runtime if the source or the destination is
2309 // an instance type.
2310 if (flags & LIR_OpArrayCopy::type_check) {
2311 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2312 __ load_klass(tmp, dst);
2313 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2314 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2315 __ br(Assembler::GE, *stub->entry());
2316 }
2317
2318 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2319 __ load_klass(tmp, src);
2320 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2321 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2322 __ br(Assembler::GE, *stub->entry());
2323 }
2324 }
2325
2326 // check if negative
2327 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2328 __ cmpw(src_pos, 0);
2329 __ br(Assembler::LT, *stub->entry());
2330 }
2331 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2332 __ cmpw(dst_pos, 0);
2333 __ br(Assembler::LT, *stub->entry());
2334 }
2335
2336 if (flags & LIR_OpArrayCopy::length_positive_check) {
2337 __ cmpw(length, 0);
2338 __ br(Assembler::LT, *stub->entry());
2339 }
2340
2341 if (flags & LIR_OpArrayCopy::src_range_check) {
2342 __ addw(tmp, src_pos, length);
2343 __ ldrw(rscratch1, src_length_addr);
2344 __ cmpw(tmp, rscratch1);
2345 __ br(Assembler::HI, *stub->entry());
2346 }
2347 if (flags & LIR_OpArrayCopy::dst_range_check) {
2348 __ addw(tmp, dst_pos, length);
2349 __ ldrw(rscratch1, dst_length_addr);
2350 __ cmpw(tmp, rscratch1);
2351 __ br(Assembler::HI, *stub->entry());
2352 }
2353
2354 if (flags & LIR_OpArrayCopy::type_check) {
2355 // We don't know the array types are compatible
2356 if (basic_type != T_OBJECT) {
2357 // Simple test for basic type arrays
2358 if (UseCompressedClassPointers) {
2359 __ ldrw(tmp, src_klass_addr);
2360 __ ldrw(rscratch1, dst_klass_addr);
2361 __ cmpw(tmp, rscratch1);
2362 } else {
2363 __ ldr(tmp, src_klass_addr);
2364 __ ldr(rscratch1, dst_klass_addr);
2365 __ cmp(tmp, rscratch1);
2366 }
2367 __ br(Assembler::NE, *stub->entry());
2368 } else {
2369 // For object arrays, if src is a sub class of dst then we can
2370 // safely do the copy.
2371 Label cont, slow;
2372
2373 #define PUSH(r1, r2) \
2374 stp(r1, r2, __ pre(sp, -2 * wordSize));
2375
2376 #define POP(r1, r2) \
2377 ldp(r1, r2, __ post(sp, 2 * wordSize));
2378
2379 __ PUSH(src, dst);
2380
2381 __ load_klass(src, src);
2382 __ load_klass(dst, dst);
2383
2384 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
2385
2386 __ PUSH(src, dst);
2387 __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
2388 __ POP(src, dst);
2389
2390 __ cbnz(src, cont);
2391
2392 __ bind(slow);
2393 __ POP(src, dst);
2394
2395 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2396 if (copyfunc_addr != NULL) { // use stub if available
2397 // src is not a sub class of dst so we have to do a
2398 // per-element check.
2399
2400 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2401 if ((flags & mask) != mask) {
2402 // Check that at least both of them object arrays.
2403 assert(flags & mask, "one of the two should be known to be an object array");
2404
2405 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2406 __ load_klass(tmp, src);
2407 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2408 __ load_klass(tmp, dst);
2409 }
2410 int lh_offset = in_bytes(Klass::layout_helper_offset());
2411 Address klass_lh_addr(tmp, lh_offset);
2412 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2413 __ ldrw(rscratch1, klass_lh_addr);
2414 __ mov(rscratch2, objArray_lh);
2415 __ eorw(rscratch1, rscratch1, rscratch2);
2416 __ cbnzw(rscratch1, *stub->entry());
2417 }
2418
2419 // Spill because stubs can use any register they like and it's
2420 // easier to restore just those that we care about.
2421 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2422 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2423 __ str(src, Address(sp, 4*BytesPerWord));
2424
2425 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2426 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2427 assert_different_registers(c_rarg0, dst, dst_pos, length);
2428 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2429 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2430 assert_different_registers(c_rarg1, dst, length);
2431 __ uxtw(c_rarg2, length);
2432 assert_different_registers(c_rarg2, dst);
2433
2434 __ load_klass(c_rarg4, dst);
2435 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2436 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2437 __ far_call(RuntimeAddress(copyfunc_addr));
2438
2439 #ifndef PRODUCT
2440 if (PrintC1Statistics) {
2441 Label failed;
2442 __ cbnz(r0, failed);
2443 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2444 __ bind(failed);
2445 }
2446 #endif
2447
2448 __ cbz(r0, *stub->continuation());
2449
2450 #ifndef PRODUCT
2451 if (PrintC1Statistics) {
2452 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2453 }
2454 #endif
2455 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2456
2457 // Restore previously spilled arguments
2458 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2459 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2460 __ ldr(src, Address(sp, 4*BytesPerWord));
2461
2462 // return value is -1^K where K is partial copied count
2463 __ eonw(rscratch1, r0, zr);
2464 // adjust length down and src/end pos up by partial copied count
2465 __ subw(length, length, rscratch1);
2466 __ addw(src_pos, src_pos, rscratch1);
2467 __ addw(dst_pos, dst_pos, rscratch1);
2468 }
2469
2470 __ b(*stub->entry());
2471
2472 __ bind(cont);
2473 __ POP(src, dst);
2474 }
2475 }
2476
2477 #ifdef ASSERT
2478 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2479 // Sanity check the known type with the incoming class. For the
2480 // primitive case the types must match exactly with src.klass and
2481 // dst.klass each exactly matching the default type. For the
2482 // object array case, if no type check is needed then either the
2483 // dst type is exactly the expected type and the src type is a
2484 // subtype which we can't check or src is the same array as dst
2485 // but not necessarily exactly of type default_type.
2486 Label known_ok, halt;
2487 __ mov_metadata(tmp, default_type->constant_encoding());
2488 if (UseCompressedClassPointers) {
2489 __ encode_klass_not_null(tmp);
2490 }
2491
2492 if (basic_type != T_OBJECT) {
2493
2494 if (UseCompressedClassPointers) {
2495 __ ldrw(rscratch1, dst_klass_addr);
2496 __ cmpw(tmp, rscratch1);
2497 } else {
2498 __ ldr(rscratch1, dst_klass_addr);
2499 __ cmp(tmp, rscratch1);
2500 }
2501 __ br(Assembler::NE, halt);
2502 if (UseCompressedClassPointers) {
2503 __ ldrw(rscratch1, src_klass_addr);
2504 __ cmpw(tmp, rscratch1);
2505 } else {
2506 __ ldr(rscratch1, src_klass_addr);
2507 __ cmp(tmp, rscratch1);
2508 }
2509 __ br(Assembler::EQ, known_ok);
2510 } else {
2511 if (UseCompressedClassPointers) {
2512 __ ldrw(rscratch1, dst_klass_addr);
2513 __ cmpw(tmp, rscratch1);
2514 } else {
2515 __ ldr(rscratch1, dst_klass_addr);
2516 __ cmp(tmp, rscratch1);
2517 }
2518 __ br(Assembler::EQ, known_ok);
2519 __ cmp(src, dst);
2520 __ br(Assembler::EQ, known_ok);
2521 }
2522 __ bind(halt);
2523 __ stop("incorrect type information in arraycopy");
2524 __ bind(known_ok);
2525 }
2526 #endif
2527
2528 #ifndef PRODUCT
2529 if (PrintC1Statistics) {
2530 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2531 }
2532 #endif
2533
2534 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2535 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2536 assert_different_registers(c_rarg0, dst, dst_pos, length);
2537 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2538 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2539 assert_different_registers(c_rarg1, dst, length);
2540 __ uxtw(c_rarg2, length);
2541 assert_different_registers(c_rarg2, dst);
2542
2543 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2544 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2545 const char *name;
2546 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2547
2548 CodeBlob *cb = CodeCache::find_blob(entry);
2549 if (cb) {
2550 __ far_call(RuntimeAddress(entry));
2551 } else {
2552 __ call_VM_leaf(entry, 3);
2553 }
2554
2555 __ bind(*stub->continuation());
2556 }
2557
2558
2559
2560
2561 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2562 Register obj = op->obj_opr()->as_register(); // may not be an oop
2563 Register hdr = op->hdr_opr()->as_register();
2564 Register lock = op->lock_opr()->as_register();
2565 if (!UseFastLocking) {
2566 __ b(*op->stub()->entry());
2567 } else if (op->code() == lir_lock) {
2568 Register scratch = noreg;
2569 if (UseBiasedLocking) {
2570 scratch = op->scratch_opr()->as_register();
2571 }
2572 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2573 // add debug info for NullPointerException only if one is possible
2574 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
2575 if (op->info() != NULL) {
2576 add_debug_info_for_null_check(null_check_offset, op->info());
2577 }
2578 // done
2579 } else if (op->code() == lir_unlock) {
2580 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2581 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2582 } else {
2583 Unimplemented();
2584 }
2585 __ bind(*op->stub()->continuation());
2586 }
2587
2588 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2589 Register obj = op->obj()->as_pointer_register();
2590 Register result = op->result_opr()->as_pointer_register();
2591
2592 CodeEmitInfo* info = op->info();
2593 if (info != NULL) {
2594 add_debug_info_for_null_check_here(info);
2595 }
2596
2597 if (UseCompressedClassPointers) {
2598 __ ldrw(result, Address (obj, oopDesc::klass_offset_in_bytes()));
2599 __ decode_klass_not_null(result);
2600 } else {
2601 __ ldr(result, Address (obj, oopDesc::klass_offset_in_bytes()));
2602 }
2603 }
2604
2605 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2606 ciMethod* method = op->profiled_method();
2607 int bci = op->profiled_bci();
2608 ciMethod* callee = op->profiled_callee();
2609
2610 // Update counter for all call types
2611 ciMethodData* md = method->method_data_or_null();
2612 assert(md != NULL, "Sanity");
2613 ciProfileData* data = md->bci_to_data(bci);
2614 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2615 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2616 Register mdo = op->mdo()->as_register();
2617 __ mov_metadata(mdo, md->constant_encoding());
2618 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2619 // Perform additional virtual call profiling for invokevirtual and
2620 // invokeinterface bytecodes
2621 if (op->should_profile_receiver_type()) {
2622 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2623 Register recv = op->recv()->as_register();
2624 assert_different_registers(mdo, recv);
2625 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2626 ciKlass* known_klass = op->known_holder();
2627 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2628 // We know the type that will be seen at this call site; we can
2629 // statically update the MethodData* rather than needing to do
2630 // dynamic tests on the receiver type
2631
2632 // NOTE: we should probably put a lock around this search to
2633 // avoid collisions by concurrent compilations
2634 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2635 uint i;
2636 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2637 ciKlass* receiver = vc_data->receiver(i);
2638 if (known_klass->equals(receiver)) {
2639 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2640 __ addptr(data_addr, DataLayout::counter_increment);
2641 return;
2642 }
2643 }
2644
2645 // Receiver type not found in profile data; select an empty slot
2646
2647 // Note that this is less efficient than it should be because it
2648 // always does a write to the receiver part of the
2649 // VirtualCallData rather than just the first time
2650 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2651 ciKlass* receiver = vc_data->receiver(i);
2652 if (receiver == NULL) {
2653 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2654 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2655 __ lea(rscratch2, recv_addr);
2656 __ str(rscratch1, Address(rscratch2));
2657 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2658 __ addptr(data_addr, DataLayout::counter_increment);
2659 return;
2660 }
2661 }
2662 } else {
2663 __ load_klass(recv, recv);
2664 Label update_done;
2665 type_profile_helper(mdo, md, data, recv, &update_done);
2666 // Receiver did not match any saved receiver and there is no empty row for it.
2667 // Increment total counter to indicate polymorphic case.
2668 __ addptr(counter_addr, DataLayout::counter_increment);
2669
2670 __ bind(update_done);
2671 }
2672 } else {
2673 // Static call
2674 __ addptr(counter_addr, DataLayout::counter_increment);
2675 }
2676 }
2677
2678
2679 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2680 Unimplemented();
2681 }
2682
2683
2684 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2685 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2686 }
2687
2688 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2689 assert(op->crc()->is_single_cpu(), "crc must be register");
2690 assert(op->val()->is_single_cpu(), "byte value must be register");
2691 assert(op->result_opr()->is_single_cpu(), "result must be register");
2692 Register crc = op->crc()->as_register();
2693 Register val = op->val()->as_register();
2694 Register res = op->result_opr()->as_register();
2695
2696 assert_different_registers(val, crc, res);
2697 uint64_t offset;
2698 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2699 if (offset) __ add(res, res, offset);
2700
2701 __ mvnw(crc, crc); // ~crc
2702 __ update_byte_crc32(crc, val, res);
2703 __ mvnw(res, crc); // ~crc
2704 }
2705
2706 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2707 COMMENT("emit_profile_type {");
2708 Register obj = op->obj()->as_register();
2709 Register tmp = op->tmp()->as_pointer_register();
2710 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2711 ciKlass* exact_klass = op->exact_klass();
2712 intptr_t current_klass = op->current_klass();
2713 bool not_null = op->not_null();
2714 bool no_conflict = op->no_conflict();
2715
2716 Label update, next, none;
2717
2718 bool do_null = !not_null;
2719 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2720 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2721
2722 assert(do_null || do_update, "why are we here?");
2723 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2724 assert(mdo_addr.base() != rscratch1, "wrong register");
2725
2726 __ verify_oop(obj);
2727
2728 if (tmp != obj) {
2729 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2730 __ mov(tmp, obj);
2731 } else {
2732 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2733 }
2734 if (do_null) {
2735 __ cbnz(tmp, update);
2736 if (!TypeEntries::was_null_seen(current_klass)) {
2737 __ ldr(rscratch2, mdo_addr);
2738 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2739 __ str(rscratch2, mdo_addr);
2740 }
2741 if (do_update) {
2742 #ifndef ASSERT
2743 __ b(next);
2744 }
2745 #else
2746 __ b(next);
2747 }
2748 } else {
2749 __ cbnz(tmp, update);
2750 __ stop("unexpected null obj");
2751 #endif
2752 }
2753
2754 __ bind(update);
2755
2756 if (do_update) {
2757 #ifdef ASSERT
2758 if (exact_klass != NULL) {
2759 Label ok;
2760 __ load_klass(tmp, tmp);
2761 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2762 __ eor(rscratch1, tmp, rscratch1);
2763 __ cbz(rscratch1, ok);
2764 __ stop("exact klass and actual klass differ");
2765 __ bind(ok);
2766 }
2767 #endif
2768 if (!no_conflict) {
2769 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2770 if (exact_klass != NULL) {
2771 __ mov_metadata(tmp, exact_klass->constant_encoding());
2772 } else {
2773 __ load_klass(tmp, tmp);
2774 }
2775
2776 __ ldr(rscratch2, mdo_addr);
2777 __ eor(tmp, tmp, rscratch2);
2778 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2779 // klass seen before, nothing to do. The unknown bit may have been
2780 // set already but no need to check.
2781 __ cbz(rscratch1, next);
2782
2783 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2784
2785 if (TypeEntries::is_type_none(current_klass)) {
2786 __ cbz(rscratch2, none);
2787 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2788 __ br(Assembler::EQ, none);
2789 // There is a chance that the checks above
2790 // fail if another thread has just set the
2791 // profiling to this obj's klass
2792 __ dmb(Assembler::ISHLD);
2793 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2794 __ ldr(rscratch2, mdo_addr);
2795 __ eor(tmp, tmp, rscratch2);
2796 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2797 __ cbz(rscratch1, next);
2798 }
2799 } else {
2800 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2801 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2802
2803 __ ldr(tmp, mdo_addr);
2804 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2805 }
2806
2807 // different than before. Cannot keep accurate profile.
2808 __ ldr(rscratch2, mdo_addr);
2809 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2810 __ str(rscratch2, mdo_addr);
2811
2812 if (TypeEntries::is_type_none(current_klass)) {
2813 __ b(next);
2814
2815 __ bind(none);
2816 // first time here. Set profile type.
2817 __ str(tmp, mdo_addr);
2818 #ifdef ASSERT
2819 __ andr(tmp, tmp, TypeEntries::type_mask);
2820 __ verify_klass_ptr(tmp);
2821 #endif
2822 }
2823 } else {
2824 // There's a single possible klass at this profile point
2825 assert(exact_klass != NULL, "should be");
2826 if (TypeEntries::is_type_none(current_klass)) {
2827 __ mov_metadata(tmp, exact_klass->constant_encoding());
2828 __ ldr(rscratch2, mdo_addr);
2829 __ eor(tmp, tmp, rscratch2);
2830 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2831 __ cbz(rscratch1, next);
2832 #ifdef ASSERT
2833 {
2834 Label ok;
2835 __ ldr(rscratch1, mdo_addr);
2836 __ cbz(rscratch1, ok);
2837 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2838 __ br(Assembler::EQ, ok);
2839 // may have been set by another thread
2840 __ dmb(Assembler::ISHLD);
2841 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2842 __ ldr(rscratch2, mdo_addr);
2843 __ eor(rscratch2, rscratch1, rscratch2);
2844 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2845 __ cbz(rscratch2, ok);
2846
2847 __ stop("unexpected profiling mismatch");
2848 __ bind(ok);
2849 }
2850 #endif
2851 // first time here. Set profile type.
2852 __ str(tmp, mdo_addr);
2853 #ifdef ASSERT
2854 __ andr(tmp, tmp, TypeEntries::type_mask);
2855 __ verify_klass_ptr(tmp);
2856 #endif
2857 } else {
2858 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2859 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2860
2861 __ ldr(tmp, mdo_addr);
2862 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2863
2864 __ orr(tmp, tmp, TypeEntries::type_unknown);
2865 __ str(tmp, mdo_addr);
2866 // FIXME: Write barrier needed here?
2867 }
2868 }
2869
2870 __ bind(next);
2871 }
2872 COMMENT("} emit_profile_type");
2873 }
2874
2875
2876 void LIR_Assembler::align_backward_branch_target() {
2877 }
2878
2879
2880 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2881 // tmp must be unused
2882 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2883
2884 if (left->is_single_cpu()) {
2885 assert(dest->is_single_cpu(), "expect single result reg");
2886 __ negw(dest->as_register(), left->as_register());
2887 } else if (left->is_double_cpu()) {
2888 assert(dest->is_double_cpu(), "expect double result reg");
2889 __ neg(dest->as_register_lo(), left->as_register_lo());
2890 } else if (left->is_single_fpu()) {
2891 assert(dest->is_single_fpu(), "expect single float result reg");
2892 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2893 } else {
2894 assert(left->is_double_fpu(), "expect double float operand reg");
2895 assert(dest->is_double_fpu(), "expect double float result reg");
2896 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2897 }
2898 }
2899
2900
2901 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2902 if (patch_code != lir_patch_none) {
2903 deoptimize_trap(info);
2904 return;
2905 }
2906
2907 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2908 }
2909
2910
2911 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2912 assert(!tmp->is_valid(), "don't need temporary");
2913
2914 CodeBlob *cb = CodeCache::find_blob(dest);
2915 if (cb) {
2916 __ far_call(RuntimeAddress(dest));
2917 } else {
2918 __ mov(rscratch1, RuntimeAddress(dest));
2919 __ blr(rscratch1);
2920 }
2921
2922 if (info != NULL) {
2923 add_call_info_here(info);
2924 }
2925 }
2926
2927 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2928 if (dest->is_address() || src->is_address()) {
2929 move_op(src, dest, type, lir_patch_none, info,
2930 /*pop_fpu_stack*/false, /*unaligned*/false, /*wide*/false);
2931 } else {
2932 ShouldNotReachHere();
2933 }
2934 }
2935
2936 #ifdef ASSERT
2937 // emit run-time assertion
2938 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2939 assert(op->code() == lir_assert, "must be");
2940
2941 if (op->in_opr1()->is_valid()) {
2942 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2943 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2944 } else {
2945 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2946 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2947 }
2948
2949 Label ok;
2950 if (op->condition() != lir_cond_always) {
2951 Assembler::Condition acond = Assembler::AL;
2952 switch (op->condition()) {
2953 case lir_cond_equal: acond = Assembler::EQ; break;
2954 case lir_cond_notEqual: acond = Assembler::NE; break;
2955 case lir_cond_less: acond = Assembler::LT; break;
2956 case lir_cond_lessEqual: acond = Assembler::LE; break;
2957 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2958 case lir_cond_greater: acond = Assembler::GT; break;
2959 case lir_cond_belowEqual: acond = Assembler::LS; break;
2960 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2961 default: ShouldNotReachHere();
2962 }
2963 __ br(acond, ok);
2964 }
2965 if (op->halt()) {
2966 const char* str = __ code_string(op->msg());
2967 __ stop(str);
2968 } else {
2969 breakpoint();
2970 }
2971 __ bind(ok);
2972 }
2973 #endif
2974
2975 #ifndef PRODUCT
2976 #define COMMENT(x) do { __ block_comment(x); } while (0)
2977 #else
2978 #define COMMENT(x)
2979 #endif
2980
2981 void LIR_Assembler::membar() {
2982 COMMENT("membar");
2983 __ membar(MacroAssembler::AnyAny);
2984 }
2985
2986 void LIR_Assembler::membar_acquire() {
2987 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2988 }
2989
2990 void LIR_Assembler::membar_release() {
2991 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2992 }
2993
2994 void LIR_Assembler::membar_loadload() {
2995 __ membar(Assembler::LoadLoad);
2996 }
2997
2998 void LIR_Assembler::membar_storestore() {
2999 __ membar(MacroAssembler::StoreStore);
3000 }
3001
3002 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3003
3004 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3005
3006 void LIR_Assembler::on_spin_wait() {
3007 __ spin_wait();
3008 }
3009
3010 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3011 __ mov(result_reg->as_register(), rthread);
3012 }
3013
3014
3015 void LIR_Assembler::peephole(LIR_List *lir) {
3016 #if 0
3017 if (tableswitch_count >= max_tableswitches)
3018 return;
3019
3020 /*
3021 This finite-state automaton recognizes sequences of compare-and-
3022 branch instructions. We will turn them into a tableswitch. You
3023 could argue that C1 really shouldn't be doing this sort of
3024 optimization, but without it the code is really horrible.
3025 */
3026
3027 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3028 int first_key, last_key = -2147483648;
3029 int next_key = 0;
3030 int start_insn = -1;
3031 int last_insn = -1;
3032 Register reg = noreg;
3033 LIR_Opr reg_opr;
3034 state = start_s;
3035
3036 LIR_OpList* inst = lir->instructions_list();
3037 for (int i = 0; i < inst->length(); i++) {
3038 LIR_Op* op = inst->at(i);
3039 switch (state) {
3040 case start_s:
3041 first_key = -1;
3042 start_insn = i;
3043 switch (op->code()) {
3044 case lir_cmp:
3045 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3046 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3047 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3048 && opr2->is_constant()
3049 && opr2->type() == T_INT) {
3050 reg_opr = opr1;
3051 reg = opr1->as_register();
3052 first_key = opr2->as_constant_ptr()->as_jint();
3053 next_key = first_key + 1;
3054 state = cmp_s;
3055 goto next_state;
3056 }
3057 break;
3058 }
3059 break;
3060 case cmp_s:
3061 switch (op->code()) {
3062 case lir_branch:
3063 if (op->as_OpBranch()->cond() == lir_cond_equal) {
3064 state = beq_s;
3065 last_insn = i;
3066 goto next_state;
3067 }
3068 }
3069 state = start_s;
3070 break;
3071 case beq_s:
3072 switch (op->code()) {
3073 case lir_cmp: {
3074 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3075 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3076 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3077 && opr1->as_register() == reg
3078 && opr2->is_constant()
3079 && opr2->type() == T_INT
3080 && opr2->as_constant_ptr()->as_jint() == next_key) {
3081 last_key = next_key;
3082 next_key++;
3083 state = cmp_s;
3084 goto next_state;
3085 }
3086 }
3087 }
3088 last_key = next_key;
3089 state = start_s;
3090 break;
3091 default:
3092 assert(false, "impossible state");
3093 }
3094 if (state == start_s) {
3095 if (first_key < last_key - 5L && reg != noreg) {
3096 {
3097 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3098 // reg->encoding(),
3099 // start_insn, first_key, last_key);
3100 // for (int i = 0; i < inst->length(); i++) {
3101 // inst->at(i)->print();
3102 // tty->print("\n");
3103 // }
3104 // tty->print("\n");
3105 }
3106
3107 struct tableswitch *sw = &switches[tableswitch_count];
3108 sw->_insn_index = start_insn, sw->_first_key = first_key,
3109 sw->_last_key = last_key, sw->_reg = reg;
3110 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3111 {
3112 // Insert the new table of branches
3113 int offset = last_insn;
3114 for (int n = first_key; n < last_key; n++) {
3115 inst->insert_before
3116 (last_insn + 1,
3117 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3118 inst->at(offset)->as_OpBranch()->label()));
3119 offset -= 2, i++;
3120 }
3121 }
3122 // Delete all the old compare-and-branch instructions
3123 for (int n = first_key; n < last_key; n++) {
3124 inst->remove_at(start_insn);
3125 inst->remove_at(start_insn);
3126 }
3127 // Insert the tableswitch instruction
3128 inst->insert_before(start_insn,
3129 new LIR_Op2(lir_cmp, lir_cond_always,
3130 LIR_OprFact::intConst(tableswitch_count),
3131 reg_opr));
3132 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3133 tableswitch_count++;
3134 }
3135 reg = noreg;
3136 last_key = -2147483648;
3137 }
3138 next_state:
3139 ;
3140 }
3141 #endif
3142 }
3143
3144 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3145 Address addr = as_Address(src->as_address_ptr());
3146 BasicType type = src->type();
3147 bool is_oop = is_reference_type(type);
3148
3149 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3150 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3151
3152 switch(type) {
3153 case T_INT:
3154 xchg = &MacroAssembler::atomic_xchgalw;
3155 add = &MacroAssembler::atomic_addalw;
3156 break;
3157 case T_LONG:
3158 xchg = &MacroAssembler::atomic_xchgal;
3159 add = &MacroAssembler::atomic_addal;
3160 break;
3161 case T_OBJECT:
3162 case T_ARRAY:
3163 if (UseCompressedOops) {
3164 xchg = &MacroAssembler::atomic_xchgalw;
3165 add = &MacroAssembler::atomic_addalw;
3166 } else {
3167 xchg = &MacroAssembler::atomic_xchgal;
3168 add = &MacroAssembler::atomic_addal;
3169 }
3170 break;
3171 default:
3172 ShouldNotReachHere();
3173 xchg = &MacroAssembler::atomic_xchgal;
3174 add = &MacroAssembler::atomic_addal; // unreachable
3175 }
3176
3177 switch (code) {
3178 case lir_xadd:
3179 {
3180 RegisterOrConstant inc;
3181 Register tmp = as_reg(tmp_op);
3182 Register dst = as_reg(dest);
3183 if (data->is_constant()) {
3184 inc = RegisterOrConstant(as_long(data));
3185 assert_different_registers(dst, addr.base(), tmp,
3186 rscratch1, rscratch2);
3187 } else {
3188 inc = RegisterOrConstant(as_reg(data));
3189 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3190 rscratch1, rscratch2);
3191 }
3192 __ lea(tmp, addr);
3193 (_masm->*add)(dst, inc, tmp);
3194 break;
3195 }
3196 case lir_xchg:
3197 {
3198 Register tmp = tmp_op->as_register();
3199 Register obj = as_reg(data);
3200 Register dst = as_reg(dest);
3201 if (is_oop && UseCompressedOops) {
3202 __ encode_heap_oop(rscratch2, obj);
3203 obj = rscratch2;
3204 }
3205 assert_different_registers(obj, addr.base(), tmp, rscratch1, dst);
3206 __ lea(tmp, addr);
3207 (_masm->*xchg)(dst, obj, tmp);
3208 if (is_oop && UseCompressedOops) {
3209 __ decode_heap_oop(dst);
3210 }
3211 }
3212 break;
3213 default:
3214 ShouldNotReachHere();
3215 }
3216 __ membar(__ AnyAny);
3217 }
3218
3219 #undef __