1 /*
2 * Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc/shared/collectedHeap.hpp"
35 #include "memory/universe.hpp"
36 #include "nativeInst_arm.hpp"
37 #include "oops/objArrayKlass.hpp"
38 #include "runtime/frame.inline.hpp"
39 #include "runtime/sharedRuntime.hpp"
40 #include "runtime/stubRoutines.hpp"
41 #include "utilities/powerOfTwo.hpp"
42 #include "vmreg_arm.inline.hpp"
43
44 #define __ _masm->
45
46 // Note: Rtemp usage is this file should not impact C2 and should be
47 // correct as long as it is not implicitly used in lower layers (the
48 // arm [macro]assembler) and used with care in the other C1 specific
49 // files.
50
51 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
52 ShouldNotCallThis(); // Not used on ARM
53 return false;
54 }
55
56
57 LIR_Opr LIR_Assembler::receiverOpr() {
58 // The first register in Java calling conventions
59 return FrameMap::R0_oop_opr;
60 }
61
62 LIR_Opr LIR_Assembler::osrBufferPointer() {
63 return FrameMap::as_pointer_opr(R0);
64 }
65
66 #ifndef PRODUCT
67 void LIR_Assembler::verify_reserved_argument_area_size(int args_count) {
68 assert(args_count * wordSize <= frame_map()->reserved_argument_area_size(), "not enough space for arguments");
69 }
70 #endif // !PRODUCT
71
72 void LIR_Assembler::store_parameter(jint c, int offset_from_sp_in_words) {
73 assert(offset_from_sp_in_words >= 0, "invalid offset from sp");
74 int offset_from_sp_in_bytes = offset_from_sp_in_words * BytesPerWord;
75 assert(offset_from_sp_in_bytes < frame_map()->reserved_argument_area_size(), "not enough space");
76 __ mov_slow(Rtemp, c);
77 __ str(Rtemp, Address(SP, offset_from_sp_in_bytes));
78 }
79
80 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_sp_in_words) {
81 assert(offset_from_sp_in_words >= 0, "invalid offset from sp");
82 int offset_from_sp_in_bytes = offset_from_sp_in_words * BytesPerWord;
83 assert(offset_from_sp_in_bytes < frame_map()->reserved_argument_area_size(), "not enough space");
84 __ mov_metadata(Rtemp, m);
85 __ str(Rtemp, Address(SP, offset_from_sp_in_bytes));
86 }
87
88 //--------------fpu register translations-----------------------
89
90
91 void LIR_Assembler::breakpoint() {
92 __ breakpoint();
93 }
94
95 void LIR_Assembler::push(LIR_Opr opr) {
96 Unimplemented();
97 }
98
99 void LIR_Assembler::pop(LIR_Opr opr) {
100 Unimplemented();
101 }
102
103 //-------------------------------------------
104 Address LIR_Assembler::as_Address(LIR_Address* addr) {
105 Register base = addr->base()->as_pointer_register();
106
107
108 if (addr->index()->is_illegal() || addr->index()->is_constant()) {
109 int offset = addr->disp();
110 if (addr->index()->is_constant()) {
111 offset += addr->index()->as_constant_ptr()->as_jint() << addr->scale();
112 }
113
114 if ((offset <= -4096) || (offset >= 4096)) {
115 BAILOUT_("offset not in range", Address(base));
116 }
117
118 return Address(base, offset);
119
120 } else {
121 assert(addr->disp() == 0, "can't have both");
122 int scale = addr->scale();
123
124 assert(addr->index()->is_single_cpu(), "should be");
125 return scale >= 0 ? Address(base, addr->index()->as_register(), lsl, scale) :
126 Address(base, addr->index()->as_register(), lsr, -scale);
127 }
128 }
129
130 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
131 Address base = as_Address(addr);
132 assert(base.index() == noreg, "must be");
133 if (base.disp() + BytesPerWord >= 4096) { BAILOUT_("offset not in range", Address(base.base(),0)); }
134 return Address(base.base(), base.disp() + BytesPerWord);
135 }
136
137 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
138 return as_Address(addr);
139 }
140
141
142 void LIR_Assembler::osr_entry() {
143 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
144 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
145 ValueStack* entry_state = osr_entry->end()->state();
146 int number_of_locks = entry_state->locks_size();
147
148 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
149 Register OSR_buf = osrBufferPointer()->as_pointer_register();
150
151 assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
152 int monitor_offset = (method()->max_locals() + 2 * (number_of_locks - 1)) * BytesPerWord;
153 for (int i = 0; i < number_of_locks; i++) {
154 int slot_offset = monitor_offset - (i * 2 * BytesPerWord);
155 __ ldr(R1, Address(OSR_buf, slot_offset + 0*BytesPerWord));
156 __ ldr(R2, Address(OSR_buf, slot_offset + 1*BytesPerWord));
157 __ str(R1, frame_map()->address_for_monitor_lock(i));
158 __ str(R2, frame_map()->address_for_monitor_object(i));
159 }
160 }
161
162
163 int LIR_Assembler::check_icache() {
164 Register receiver = LIR_Assembler::receiverOpr()->as_register();
165 int offset = __ offset();
166 __ inline_cache_check(receiver, Ricklass);
167 return offset;
168 }
169
170 void LIR_Assembler::clinit_barrier(ciMethod* method) {
171 ShouldNotReachHere(); // not implemented
172 }
173
174 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
175 jobject o = (jobject)Universe::non_oop_word();
176 int index = __ oop_recorder()->allocate_oop_index(o);
177
178 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), index);
179
180 __ patchable_mov_oop(reg, o, index);
181 patching_epilog(patch, lir_patch_normal, reg, info);
182 }
183
184
185 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
186 Metadata* o = (Metadata*)Universe::non_oop_word();
187 int index = __ oop_recorder()->allocate_metadata_index(o);
188 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
189
190 __ patchable_mov_metadata(reg, o, index);
191 patching_epilog(patch, lir_patch_normal, reg, info);
192 }
193
194
195 int LIR_Assembler::initial_frame_size_in_bytes() const {
196 // Subtracts two words to account for return address and link
197 return frame_map()->framesize()*VMRegImpl::stack_slot_size - 2*wordSize;
198 }
199
200
201 int LIR_Assembler::emit_exception_handler() {
202 // TODO: ARM
203 __ nop(); // See comments in other ports
204
205 address handler_base = __ start_a_stub(exception_handler_size());
206 if (handler_base == NULL) {
207 bailout("exception handler overflow");
208 return -1;
209 }
210
211 int offset = code_offset();
212
213 // check that there is really an exception
214 __ verify_not_null_oop(Rexception_obj);
215
216 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
217 __ should_not_reach_here();
218
219 assert(code_offset() - offset <= exception_handler_size(), "overflow");
220 __ end_a_stub();
221
222 return offset;
223 }
224
225 // Emit the code to remove the frame from the stack in the exception
226 // unwind path.
227 int LIR_Assembler::emit_unwind_handler() {
228 #ifndef PRODUCT
229 if (CommentedAssembly) {
230 _masm->block_comment("Unwind handler");
231 }
232 #endif
233
234 int offset = code_offset();
235
236 // Fetch the exception from TLS and clear out exception related thread state
237 Register zero = __ zero_register(Rtemp);
238 __ ldr(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
239 __ str(zero, Address(Rthread, JavaThread::exception_oop_offset()));
240 __ str(zero, Address(Rthread, JavaThread::exception_pc_offset()));
241
242 __ bind(_unwind_handler_entry);
243 __ verify_not_null_oop(Rexception_obj);
244
245 // Preform needed unlocking
246 MonitorExitStub* stub = NULL;
247 if (method()->is_synchronized()) {
248 monitor_address(0, FrameMap::R0_opr);
249 stub = new MonitorExitStub(FrameMap::R0_opr, true, 0);
250 __ unlock_object(R2, R1, R0, Rtemp, *stub->entry());
251 __ bind(*stub->continuation());
252 }
253
254 // remove the activation and dispatch to the unwind handler
255 __ remove_frame(initial_frame_size_in_bytes()); // restores FP and LR
256 __ jump(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type, Rtemp);
257
258 // Emit the slow path assembly
259 if (stub != NULL) {
260 stub->emit_code(this);
261 }
262
263 return offset;
264 }
265
266
267 int LIR_Assembler::emit_deopt_handler() {
268 address handler_base = __ start_a_stub(deopt_handler_size());
269 if (handler_base == NULL) {
270 bailout("deopt handler overflow");
271 return -1;
272 }
273
274 int offset = code_offset();
275
276 __ mov_relative_address(LR, __ pc());
277 __ push(LR); // stub expects LR to be saved
278 __ jump(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type, noreg);
279
280 assert(code_offset() - offset <= deopt_handler_size(), "overflow");
281 __ end_a_stub();
282
283 return offset;
284 }
285
286
287 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
288 // Pop the frame before safepoint polling
289 __ remove_frame(initial_frame_size_in_bytes());
290 __ read_polling_page(Rtemp, relocInfo::poll_return_type);
291 __ ret();
292 }
293
294 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
295
296 int offset = __ offset();
297 __ get_polling_page(Rtemp);
298 __ relocate(relocInfo::poll_type);
299 add_debug_info_for_branch(info); // help pc_desc_at to find correct scope for current PC
300 __ ldr(Rtemp, Address(Rtemp));
301
302 return offset;
303 }
304
305
306 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
307 if (from_reg != to_reg) {
308 __ mov(to_reg, from_reg);
309 }
310 }
311
312 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
313 assert(src->is_constant() && dest->is_register(), "must be");
314 LIR_Const* c = src->as_constant_ptr();
315
316 switch (c->type()) {
317 case T_ADDRESS:
318 case T_INT:
319 assert(patch_code == lir_patch_none, "no patching handled here");
320 __ mov_slow(dest->as_register(), c->as_jint());
321 break;
322
323 case T_LONG:
324 assert(patch_code == lir_patch_none, "no patching handled here");
325 __ mov_slow(dest->as_register_lo(), c->as_jint_lo());
326 __ mov_slow(dest->as_register_hi(), c->as_jint_hi());
327 break;
328
329 case T_OBJECT:
330 if (patch_code == lir_patch_none) {
331 __ mov_oop(dest->as_register(), c->as_jobject());
332 } else {
333 jobject2reg_with_patching(dest->as_register(), info);
334 }
335 break;
336
337 case T_METADATA:
338 if (patch_code == lir_patch_none) {
339 __ mov_metadata(dest->as_register(), c->as_metadata());
340 } else {
341 klass2reg_with_patching(dest->as_register(), info);
342 }
343 break;
344
345 case T_FLOAT:
346 if (dest->is_single_fpu()) {
347 __ mov_float(dest->as_float_reg(), c->as_jfloat());
348 } else {
349 // Simple getters can return float constant directly into r0
350 __ mov_slow(dest->as_register(), c->as_jint_bits());
351 }
352 break;
353
354 case T_DOUBLE:
355 if (dest->is_double_fpu()) {
356 __ mov_double(dest->as_double_reg(), c->as_jdouble());
357 } else {
358 // Simple getters can return double constant directly into r1r0
359 __ mov_slow(dest->as_register_lo(), c->as_jint_lo_bits());
360 __ mov_slow(dest->as_register_hi(), c->as_jint_hi_bits());
361 }
362 break;
363
364 default:
365 ShouldNotReachHere();
366 }
367 }
368
369 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
370 assert(src->is_constant(), "must be");
371 assert(dest->is_stack(), "must be");
372 LIR_Const* c = src->as_constant_ptr();
373
374 switch (c->type()) {
375 case T_INT: // fall through
376 case T_FLOAT:
377 __ mov_slow(Rtemp, c->as_jint_bits());
378 __ str_32(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
379 break;
380
381 case T_ADDRESS:
382 __ mov_slow(Rtemp, c->as_jint());
383 __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
384 break;
385
386 case T_OBJECT:
387 __ mov_oop(Rtemp, c->as_jobject());
388 __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
389 break;
390
391 case T_LONG: // fall through
392 case T_DOUBLE:
393 __ mov_slow(Rtemp, c->as_jint_lo_bits());
394 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
395 if (c->as_jint_hi_bits() != c->as_jint_lo_bits()) {
396 __ mov_slow(Rtemp, c->as_jint_hi_bits());
397 }
398 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
399 break;
400
401 default:
402 ShouldNotReachHere();
403 }
404 }
405
406 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
407 CodeEmitInfo* info, bool wide) {
408 assert((src->as_constant_ptr()->type() == T_OBJECT && src->as_constant_ptr()->as_jobject() == NULL),"cannot handle otherwise");
409 __ mov(Rtemp, 0);
410
411 int null_check_offset = code_offset();
412 __ str(Rtemp, as_Address(dest->as_address_ptr()));
413
414 if (info != NULL) {
415 assert(false, "arm32 didn't support this before, investigate if bug");
416 add_debug_info_for_null_check(null_check_offset, info);
417 }
418 }
419
420 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
421 assert(src->is_register() && dest->is_register(), "must be");
422
423 if (src->is_single_cpu()) {
424 if (dest->is_single_cpu()) {
425 move_regs(src->as_register(), dest->as_register());
426 } else if (dest->is_single_fpu()) {
427 __ fmsr(dest->as_float_reg(), src->as_register());
428 } else {
429 ShouldNotReachHere();
430 }
431 } else if (src->is_double_cpu()) {
432 if (dest->is_double_cpu()) {
433 __ long_move(dest->as_register_lo(), dest->as_register_hi(), src->as_register_lo(), src->as_register_hi());
434 } else {
435 __ fmdrr(dest->as_double_reg(), src->as_register_lo(), src->as_register_hi());
436 }
437 } else if (src->is_single_fpu()) {
438 if (dest->is_single_fpu()) {
439 __ mov_float(dest->as_float_reg(), src->as_float_reg());
440 } else if (dest->is_single_cpu()) {
441 __ mov_fpr2gpr_float(dest->as_register(), src->as_float_reg());
442 } else {
443 ShouldNotReachHere();
444 }
445 } else if (src->is_double_fpu()) {
446 if (dest->is_double_fpu()) {
447 __ mov_double(dest->as_double_reg(), src->as_double_reg());
448 } else if (dest->is_double_cpu()) {
449 __ fmrrd(dest->as_register_lo(), dest->as_register_hi(), src->as_double_reg());
450 } else {
451 ShouldNotReachHere();
452 }
453 } else {
454 ShouldNotReachHere();
455 }
456 }
457
458 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
459 assert(src->is_register(), "should not call otherwise");
460 assert(dest->is_stack(), "should not call otherwise");
461
462 Address addr = dest->is_single_word() ?
463 frame_map()->address_for_slot(dest->single_stack_ix()) :
464 frame_map()->address_for_slot(dest->double_stack_ix());
465
466 assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
467 if (src->is_single_fpu() || src->is_double_fpu()) {
468 if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
469 }
470
471 if (src->is_single_cpu()) {
472 switch (type) {
473 case T_OBJECT:
474 case T_ARRAY: __ verify_oop(src->as_register()); // fall through
475 case T_ADDRESS:
476 case T_METADATA: __ str(src->as_register(), addr); break;
477 case T_FLOAT: // used in intBitsToFloat intrinsic implementation, fall through
478 case T_INT: __ str_32(src->as_register(), addr); break;
479 default:
480 ShouldNotReachHere();
481 }
482 } else if (src->is_double_cpu()) {
483 __ str(src->as_register_lo(), addr);
484 __ str(src->as_register_hi(), frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
485 } else if (src->is_single_fpu()) {
486 __ str_float(src->as_float_reg(), addr);
487 } else if (src->is_double_fpu()) {
488 __ str_double(src->as_double_reg(), addr);
489 } else {
490 ShouldNotReachHere();
491 }
492 }
493
494
495 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
496 LIR_PatchCode patch_code, CodeEmitInfo* info,
497 bool pop_fpu_stack, bool wide,
498 bool unaligned) {
499 LIR_Address* to_addr = dest->as_address_ptr();
500 Register base_reg = to_addr->base()->as_pointer_register();
501 const bool needs_patching = (patch_code != lir_patch_none);
502
503 PatchingStub* patch = NULL;
504 if (needs_patching) {
505 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
506 }
507
508 int null_check_offset = code_offset();
509
510 switch (type) {
511 case T_ARRAY:
512 case T_OBJECT:
513 if (UseCompressedOops && !wide) {
514 ShouldNotReachHere();
515 } else {
516 __ str(src->as_register(), as_Address(to_addr));
517 }
518 break;
519
520 case T_ADDRESS:
521 __ str(src->as_pointer_register(), as_Address(to_addr));
522 break;
523
524 case T_BYTE:
525 case T_BOOLEAN:
526 __ strb(src->as_register(), as_Address(to_addr));
527 break;
528
529 case T_CHAR:
530 case T_SHORT:
531 __ strh(src->as_register(), as_Address(to_addr));
532 break;
533
534 case T_INT:
535 #ifdef __SOFTFP__
536 case T_FLOAT:
537 #endif // __SOFTFP__
538 __ str_32(src->as_register(), as_Address(to_addr));
539 break;
540
541
542 #ifdef __SOFTFP__
543 case T_DOUBLE:
544 #endif // __SOFTFP__
545 case T_LONG: {
546 Register from_lo = src->as_register_lo();
547 Register from_hi = src->as_register_hi();
548 if (to_addr->index()->is_register()) {
549 assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
550 assert(to_addr->disp() == 0, "Not yet supporting both");
551 __ add(Rtemp, base_reg, to_addr->index()->as_register());
552 base_reg = Rtemp;
553 __ str(from_lo, Address(Rtemp));
554 if (patch != NULL) {
555 __ nop(); // see comment before patching_epilog for 2nd str
556 patching_epilog(patch, lir_patch_low, base_reg, info);
557 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
558 patch_code = lir_patch_high;
559 }
560 __ str(from_hi, Address(Rtemp, BytesPerWord));
561 } else if (base_reg == from_lo) {
562 __ str(from_hi, as_Address_hi(to_addr));
563 if (patch != NULL) {
564 __ nop(); // see comment before patching_epilog for 2nd str
565 patching_epilog(patch, lir_patch_high, base_reg, info);
566 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
567 patch_code = lir_patch_low;
568 }
569 __ str(from_lo, as_Address_lo(to_addr));
570 } else {
571 __ str(from_lo, as_Address_lo(to_addr));
572 if (patch != NULL) {
573 __ nop(); // see comment before patching_epilog for 2nd str
574 patching_epilog(patch, lir_patch_low, base_reg, info);
575 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
576 patch_code = lir_patch_high;
577 }
578 __ str(from_hi, as_Address_hi(to_addr));
579 }
580 break;
581 }
582
583 #ifndef __SOFTFP__
584 case T_FLOAT:
585 if (to_addr->index()->is_register()) {
586 assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
587 __ add(Rtemp, base_reg, to_addr->index()->as_register());
588 if ((to_addr->disp() <= -4096) || (to_addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
589 __ fsts(src->as_float_reg(), Address(Rtemp, to_addr->disp()));
590 } else {
591 __ fsts(src->as_float_reg(), as_Address(to_addr));
592 }
593 break;
594
595 case T_DOUBLE:
596 if (to_addr->index()->is_register()) {
597 assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
598 __ add(Rtemp, base_reg, to_addr->index()->as_register());
599 if ((to_addr->disp() <= -4096) || (to_addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
600 __ fstd(src->as_double_reg(), Address(Rtemp, to_addr->disp()));
601 } else {
602 __ fstd(src->as_double_reg(), as_Address(to_addr));
603 }
604 break;
605 #endif // __SOFTFP__
606
607
608 default:
609 ShouldNotReachHere();
610 }
611
612 if (info != NULL) {
613 add_debug_info_for_null_check(null_check_offset, info);
614 }
615
616 if (patch != NULL) {
617 // Offset embedded into LDR/STR instruction may appear not enough
618 // to address a field. So, provide a space for one more instruction
619 // that will deal with larger offsets.
620 __ nop();
621 patching_epilog(patch, patch_code, base_reg, info);
622 }
623 }
624
625
626 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
627 assert(src->is_stack(), "should not call otherwise");
628 assert(dest->is_register(), "should not call otherwise");
629
630 Address addr = src->is_single_word() ?
631 frame_map()->address_for_slot(src->single_stack_ix()) :
632 frame_map()->address_for_slot(src->double_stack_ix());
633
634 assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
635 if (dest->is_single_fpu() || dest->is_double_fpu()) {
636 if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
637 }
638
639 if (dest->is_single_cpu()) {
640 switch (type) {
641 case T_OBJECT:
642 case T_ARRAY:
643 case T_ADDRESS:
644 case T_METADATA: __ ldr(dest->as_register(), addr); break;
645 case T_FLOAT: // used in floatToRawIntBits intrinsic implemenation
646 case T_INT: __ ldr_u32(dest->as_register(), addr); break;
647 default:
648 ShouldNotReachHere();
649 }
650 if ((type == T_OBJECT) || (type == T_ARRAY)) {
651 __ verify_oop(dest->as_register());
652 }
653 } else if (dest->is_double_cpu()) {
654 __ ldr(dest->as_register_lo(), addr);
655 __ ldr(dest->as_register_hi(), frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
656 } else if (dest->is_single_fpu()) {
657 __ ldr_float(dest->as_float_reg(), addr);
658 } else if (dest->is_double_fpu()) {
659 __ ldr_double(dest->as_double_reg(), addr);
660 } else {
661 ShouldNotReachHere();
662 }
663 }
664
665
666 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
667 if (src->is_single_stack()) {
668 switch (src->type()) {
669 case T_OBJECT:
670 case T_ARRAY:
671 case T_ADDRESS:
672 case T_METADATA:
673 __ ldr(Rtemp, frame_map()->address_for_slot(src->single_stack_ix()));
674 __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
675 break;
676
677 case T_INT:
678 case T_FLOAT:
679 __ ldr_u32(Rtemp, frame_map()->address_for_slot(src->single_stack_ix()));
680 __ str_32(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
681 break;
682
683 default:
684 ShouldNotReachHere();
685 }
686 } else {
687 assert(src->is_double_stack(), "must be");
688 __ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes));
689 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
690 __ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
691 __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
692 }
693 }
694
695
696 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type,
697 LIR_PatchCode patch_code, CodeEmitInfo* info,
698 bool wide, bool unaligned) {
699 assert(src->is_address(), "should not call otherwise");
700 assert(dest->is_register(), "should not call otherwise");
701 LIR_Address* addr = src->as_address_ptr();
702
703 Register base_reg = addr->base()->as_pointer_register();
704
705 PatchingStub* patch = NULL;
706 if (patch_code != lir_patch_none) {
707 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
708 }
709 if (info != NULL) {
710 add_debug_info_for_null_check_here(info);
711 }
712
713 switch (type) {
714 case T_OBJECT: // fall through
715 case T_ARRAY:
716 if (UseCompressedOops && !wide) {
717 __ ldr_u32(dest->as_register(), as_Address(addr));
718 } else {
719 __ ldr(dest->as_register(), as_Address(addr));
720 }
721 break;
722
723 case T_ADDRESS:
724 __ ldr(dest->as_pointer_register(), as_Address(addr));
725 break;
726
727 case T_INT:
728 #ifdef __SOFTFP__
729 case T_FLOAT:
730 #endif // __SOFTFP__
731 __ ldr(dest->as_pointer_register(), as_Address(addr));
732 break;
733
734 case T_BOOLEAN:
735 __ ldrb(dest->as_register(), as_Address(addr));
736 break;
737
738 case T_BYTE:
739 __ ldrsb(dest->as_register(), as_Address(addr));
740 break;
741
742 case T_CHAR:
743 __ ldrh(dest->as_register(), as_Address(addr));
744 break;
745
746 case T_SHORT:
747 __ ldrsh(dest->as_register(), as_Address(addr));
748 break;
749
750
751 #ifdef __SOFTFP__
752 case T_DOUBLE:
753 #endif // __SOFTFP__
754 case T_LONG: {
755 Register to_lo = dest->as_register_lo();
756 Register to_hi = dest->as_register_hi();
757 if (addr->index()->is_register()) {
758 assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
759 assert(addr->disp() == 0, "Not yet supporting both");
760 __ add(Rtemp, base_reg, addr->index()->as_register());
761 base_reg = Rtemp;
762 __ ldr(to_lo, Address(Rtemp));
763 if (patch != NULL) {
764 __ nop(); // see comment before patching_epilog for 2nd ldr
765 patching_epilog(patch, lir_patch_low, base_reg, info);
766 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
767 patch_code = lir_patch_high;
768 }
769 __ ldr(to_hi, Address(Rtemp, BytesPerWord));
770 } else if (base_reg == to_lo) {
771 __ ldr(to_hi, as_Address_hi(addr));
772 if (patch != NULL) {
773 __ nop(); // see comment before patching_epilog for 2nd ldr
774 patching_epilog(patch, lir_patch_high, base_reg, info);
775 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
776 patch_code = lir_patch_low;
777 }
778 __ ldr(to_lo, as_Address_lo(addr));
779 } else {
780 __ ldr(to_lo, as_Address_lo(addr));
781 if (patch != NULL) {
782 __ nop(); // see comment before patching_epilog for 2nd ldr
783 patching_epilog(patch, lir_patch_low, base_reg, info);
784 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
785 patch_code = lir_patch_high;
786 }
787 __ ldr(to_hi, as_Address_hi(addr));
788 }
789 break;
790 }
791
792 #ifndef __SOFTFP__
793 case T_FLOAT:
794 if (addr->index()->is_register()) {
795 assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
796 __ add(Rtemp, base_reg, addr->index()->as_register());
797 if ((addr->disp() <= -4096) || (addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
798 __ flds(dest->as_float_reg(), Address(Rtemp, addr->disp()));
799 } else {
800 __ flds(dest->as_float_reg(), as_Address(addr));
801 }
802 break;
803
804 case T_DOUBLE:
805 if (addr->index()->is_register()) {
806 assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
807 __ add(Rtemp, base_reg, addr->index()->as_register());
808 if ((addr->disp() <= -4096) || (addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
809 __ fldd(dest->as_double_reg(), Address(Rtemp, addr->disp()));
810 } else {
811 __ fldd(dest->as_double_reg(), as_Address(addr));
812 }
813 break;
814 #endif // __SOFTFP__
815
816
817 default:
818 ShouldNotReachHere();
819 }
820
821 if (patch != NULL) {
822 // Offset embedded into LDR/STR instruction may appear not enough
823 // to address a field. So, provide a space for one more instruction
824 // that will deal with larger offsets.
825 __ nop();
826 patching_epilog(patch, patch_code, base_reg, info);
827 }
828
829 }
830
831
832 void LIR_Assembler::emit_op3(LIR_Op3* op) {
833 bool is_32 = op->result_opr()->is_single_cpu();
834
835 if (op->code() == lir_idiv && op->in_opr2()->is_constant() && is_32) {
836 int c = op->in_opr2()->as_constant_ptr()->as_jint();
837 assert(is_power_of_2(c), "non power-of-2 constant should be put in a register");
838
839 Register left = op->in_opr1()->as_register();
840 Register dest = op->result_opr()->as_register();
841 if (c == 1) {
842 __ mov(dest, left);
843 } else if (c == 2) {
844 __ add_32(dest, left, AsmOperand(left, lsr, 31));
845 __ asr_32(dest, dest, 1);
846 } else if (c != (int) 0x80000000) {
847 int power = log2i_exact(c);
848 __ asr_32(Rtemp, left, 31);
849 __ add_32(dest, left, AsmOperand(Rtemp, lsr, 32-power)); // dest = left + (left < 0 ? 2^power - 1 : 0);
850 __ asr_32(dest, dest, power); // dest = dest >>> power;
851 } else {
852 // x/0x80000000 is a special case, since dividend is a power of two, but is negative.
853 // The only possible result values are 0 and 1, with 1 only for dividend == divisor == 0x80000000.
854 __ cmp_32(left, c);
855 __ mov(dest, 0, ne);
856 __ mov(dest, 1, eq);
857 }
858 } else {
859 assert(op->code() == lir_idiv || op->code() == lir_irem, "unexpected op3");
860 __ call(StubRoutines::Arm::idiv_irem_entry(), relocInfo::runtime_call_type);
861 add_debug_info_for_div0_here(op->info());
862 }
863 }
864
865
866 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
867 #ifdef ASSERT
868 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
869 if (op->block() != NULL) _branch_target_blocks.append(op->block());
870 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
871 assert(op->info() == NULL, "CodeEmitInfo?");
872 #endif // ASSERT
873
874 #ifdef __SOFTFP__
875 assert (op->code() != lir_cond_float_branch, "this should be impossible");
876 #else
877 if (op->code() == lir_cond_float_branch) {
878 __ fmstat();
879 __ b(*(op->ublock()->label()), vs);
880 }
881 #endif // __SOFTFP__
882
883 AsmCondition acond = al;
884 switch (op->cond()) {
885 case lir_cond_equal: acond = eq; break;
886 case lir_cond_notEqual: acond = ne; break;
887 case lir_cond_less: acond = lt; break;
888 case lir_cond_lessEqual: acond = le; break;
889 case lir_cond_greaterEqual: acond = ge; break;
890 case lir_cond_greater: acond = gt; break;
891 case lir_cond_aboveEqual: acond = hs; break;
892 case lir_cond_belowEqual: acond = ls; break;
893 default: assert(op->cond() == lir_cond_always, "must be");
894 }
895 __ b(*(op->label()), acond);
896 }
897
898
899 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
900 LIR_Opr src = op->in_opr();
901 LIR_Opr dest = op->result_opr();
902
903 switch (op->bytecode()) {
904 case Bytecodes::_i2l:
905 move_regs(src->as_register(), dest->as_register_lo());
906 __ mov(dest->as_register_hi(), AsmOperand(src->as_register(), asr, 31));
907 break;
908 case Bytecodes::_l2i:
909 move_regs(src->as_register_lo(), dest->as_register());
910 break;
911 case Bytecodes::_i2b:
912 __ sign_extend(dest->as_register(), src->as_register(), 8);
913 break;
914 case Bytecodes::_i2s:
915 __ sign_extend(dest->as_register(), src->as_register(), 16);
916 break;
917 case Bytecodes::_i2c:
918 __ zero_extend(dest->as_register(), src->as_register(), 16);
919 break;
920 case Bytecodes::_f2d:
921 __ convert_f2d(dest->as_double_reg(), src->as_float_reg());
922 break;
923 case Bytecodes::_d2f:
924 __ convert_d2f(dest->as_float_reg(), src->as_double_reg());
925 break;
926 case Bytecodes::_i2f:
927 __ fmsr(Stemp, src->as_register());
928 __ fsitos(dest->as_float_reg(), Stemp);
929 break;
930 case Bytecodes::_i2d:
931 __ fmsr(Stemp, src->as_register());
932 __ fsitod(dest->as_double_reg(), Stemp);
933 break;
934 case Bytecodes::_f2i:
935 __ ftosizs(Stemp, src->as_float_reg());
936 __ fmrs(dest->as_register(), Stemp);
937 break;
938 case Bytecodes::_d2i:
939 __ ftosizd(Stemp, src->as_double_reg());
940 __ fmrs(dest->as_register(), Stemp);
941 break;
942 default:
943 ShouldNotReachHere();
944 }
945 }
946
947
948 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
949 if (op->init_check()) {
950 Register tmp = op->tmp1()->as_register();
951 __ ldrb(tmp, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
952 add_debug_info_for_null_check_here(op->stub()->info());
953 __ cmp(tmp, InstanceKlass::fully_initialized);
954 __ b(*op->stub()->entry(), ne);
955 }
956 __ allocate_object(op->obj()->as_register(),
957 op->tmp1()->as_register(),
958 op->tmp2()->as_register(),
959 op->tmp3()->as_register(),
960 op->header_size(),
961 op->object_size(),
962 op->klass()->as_register(),
963 *op->stub()->entry());
964 __ bind(*op->stub()->continuation());
965 }
966
967 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
968 if (UseSlowPath ||
969 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
970 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
971 __ b(*op->stub()->entry());
972 } else {
973 __ allocate_array(op->obj()->as_register(),
974 op->len()->as_register(),
975 op->tmp1()->as_register(),
976 op->tmp2()->as_register(),
977 op->tmp3()->as_register(),
978 arrayOopDesc::header_size(op->type()),
979 type2aelembytes(op->type()),
980 op->klass()->as_register(),
981 *op->stub()->entry());
982 }
983 __ bind(*op->stub()->continuation());
984 }
985
986 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
987 ciMethodData *md, ciProfileData *data,
988 Register recv, Register tmp1, Label* update_done) {
989 assert_different_registers(mdo, recv, tmp1);
990 uint i;
991 for (i = 0; i < VirtualCallData::row_limit(); i++) {
992 Label next_test;
993 // See if the receiver is receiver[n].
994 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
995 mdo_offset_bias);
996 __ ldr(tmp1, receiver_addr);
997 __ verify_klass_ptr(tmp1);
998 __ cmp(recv, tmp1);
999 __ b(next_test, ne);
1000 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
1001 mdo_offset_bias);
1002 __ ldr(tmp1, data_addr);
1003 __ add(tmp1, tmp1, DataLayout::counter_increment);
1004 __ str(tmp1, data_addr);
1005 __ b(*update_done);
1006 __ bind(next_test);
1007 }
1008
1009 // Didn't find receiver; find next empty slot and fill it in
1010 for (i = 0; i < VirtualCallData::row_limit(); i++) {
1011 Label next_test;
1012 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
1013 mdo_offset_bias);
1014 __ ldr(tmp1, recv_addr);
1015 __ cbnz(tmp1, next_test);
1016 __ str(recv, recv_addr);
1017 __ mov(tmp1, DataLayout::counter_increment);
1018 __ str(tmp1, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
1019 mdo_offset_bias));
1020 __ b(*update_done);
1021 __ bind(next_test);
1022 }
1023 }
1024
1025 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
1026 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
1027 md = method->method_data_or_null();
1028 assert(md != NULL, "Sanity");
1029 data = md->bci_to_data(bci);
1030 assert(data != NULL, "need data for checkcast");
1031 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1032 if (md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes() >= 4096) {
1033 // The offset is large so bias the mdo by the base of the slot so
1034 // that the ldr can use an immediate offset to reference the slots of the data
1035 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
1036 }
1037 }
1038
1039 // On 32-bit ARM, code before this helper should test obj for null (ZF should be set if obj is null).
1040 void LIR_Assembler::typecheck_profile_helper1(ciMethod* method, int bci,
1041 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias,
1042 Register obj, Register mdo, Register data_val, Label* obj_is_null) {
1043 assert(method != NULL, "Should have method");
1044 assert_different_registers(obj, mdo, data_val);
1045 setup_md_access(method, bci, md, data, mdo_offset_bias);
1046 Label not_null;
1047 __ b(not_null, ne);
1048 __ mov_metadata(mdo, md->constant_encoding());
1049 if (mdo_offset_bias > 0) {
1050 __ mov_slow(data_val, mdo_offset_bias);
1051 __ add(mdo, mdo, data_val);
1052 }
1053 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
1054 __ ldrb(data_val, flags_addr);
1055 __ orr(data_val, data_val, (uint)BitData::null_seen_byte_constant());
1056 __ strb(data_val, flags_addr);
1057 __ b(*obj_is_null);
1058 __ bind(not_null);
1059 }
1060
1061 void LIR_Assembler::typecheck_profile_helper2(ciMethodData* md, ciProfileData* data, int mdo_offset_bias,
1062 Register mdo, Register recv, Register value, Register tmp1,
1063 Label* profile_cast_success, Label* profile_cast_failure,
1064 Label* success, Label* failure) {
1065 assert_different_registers(mdo, value, tmp1);
1066 __ bind(*profile_cast_success);
1067 __ mov_metadata(mdo, md->constant_encoding());
1068 if (mdo_offset_bias > 0) {
1069 __ mov_slow(tmp1, mdo_offset_bias);
1070 __ add(mdo, mdo, tmp1);
1071 }
1072 __ load_klass(recv, value);
1073 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
1074 __ b(*success);
1075 // Cast failure case
1076 __ bind(*profile_cast_failure);
1077 __ mov_metadata(mdo, md->constant_encoding());
1078 if (mdo_offset_bias > 0) {
1079 __ mov_slow(tmp1, mdo_offset_bias);
1080 __ add(mdo, mdo, tmp1);
1081 }
1082 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
1083 __ ldr(tmp1, data_addr);
1084 __ sub(tmp1, tmp1, DataLayout::counter_increment);
1085 __ str(tmp1, data_addr);
1086 __ b(*failure);
1087 }
1088
1089 // Sets `res` to true, if `cond` holds.
1090 static void set_instanceof_result(MacroAssembler* _masm, Register res, AsmCondition cond) {
1091 __ mov(res, 1, cond);
1092 }
1093
1094
1095 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1096 // TODO: ARM - can be more effective with one more register
1097 switch (op->code()) {
1098 case lir_store_check: {
1099 CodeStub* stub = op->stub();
1100 Register value = op->object()->as_register();
1101 Register array = op->array()->as_register();
1102 Register klass_RInfo = op->tmp1()->as_register();
1103 Register k_RInfo = op->tmp2()->as_register();
1104 assert_different_registers(klass_RInfo, k_RInfo, Rtemp);
1105 if (op->should_profile()) {
1106 assert_different_registers(value, klass_RInfo, k_RInfo, Rtemp);
1107 }
1108
1109 // check if it needs to be profiled
1110 ciMethodData* md;
1111 ciProfileData* data;
1112 int mdo_offset_bias = 0;
1113 Label profile_cast_success, profile_cast_failure, done;
1114 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1115 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1116
1117 if (op->should_profile()) {
1118 __ cmp(value, 0);
1119 typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, value, k_RInfo, Rtemp, &done);
1120 } else {
1121 __ cbz(value, done);
1122 }
1123 assert_different_registers(k_RInfo, value);
1124 add_debug_info_for_null_check_here(op->info_for_exception());
1125 __ load_klass(k_RInfo, array);
1126 __ load_klass(klass_RInfo, value);
1127 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1128 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1129 // check for immediate positive hit
1130 __ ldr(Rtemp, Address(klass_RInfo, Rtemp));
1131 __ cmp(klass_RInfo, k_RInfo);
1132 __ cond_cmp(Rtemp, k_RInfo, ne);
1133 __ b(*success_target, eq);
1134 // check for immediate negative hit
1135 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1136 __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1137 __ b(*failure_target, ne);
1138 // slow case
1139 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1140 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1141 __ cbz(R0, *failure_target);
1142 if (op->should_profile()) {
1143 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1144 if (mdo == value) {
1145 mdo = k_RInfo;
1146 recv = klass_RInfo;
1147 }
1148 typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, value, tmp1,
1149 &profile_cast_success, &profile_cast_failure,
1150 &done, stub->entry());
1151 }
1152 __ bind(done);
1153 break;
1154 }
1155
1156 case lir_checkcast: {
1157 CodeStub* stub = op->stub();
1158 Register obj = op->object()->as_register();
1159 Register res = op->result_opr()->as_register();
1160 Register klass_RInfo = op->tmp1()->as_register();
1161 Register k_RInfo = op->tmp2()->as_register();
1162 ciKlass* k = op->klass();
1163 assert_different_registers(res, k_RInfo, klass_RInfo, Rtemp);
1164
1165 if (stub->is_simple_exception_stub()) {
1166 // TODO: ARM - Late binding is used to prevent confusion of register allocator
1167 assert(stub->is_exception_throw_stub(), "must be");
1168 ((SimpleExceptionStub*)stub)->set_obj(op->result_opr());
1169 }
1170 ciMethodData* md;
1171 ciProfileData* data;
1172 int mdo_offset_bias = 0;
1173
1174 Label done;
1175
1176 Label profile_cast_failure, profile_cast_success;
1177 Label *failure_target = op->should_profile() ? &profile_cast_failure : op->stub()->entry();
1178 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1179
1180
1181 __ movs(res, obj);
1182 if (op->should_profile()) {
1183 typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, res, klass_RInfo, Rtemp, &done);
1184 } else {
1185 __ b(done, eq);
1186 }
1187 if (k->is_loaded()) {
1188 __ mov_metadata(k_RInfo, k->constant_encoding());
1189 } else if (k_RInfo != obj) {
1190 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1191 __ movs(res, obj);
1192 } else {
1193 // Patching doesn't update "res" register after GC, so do patching first
1194 klass2reg_with_patching(Rtemp, op->info_for_patch());
1195 __ movs(res, obj);
1196 __ mov(k_RInfo, Rtemp);
1197 }
1198 __ load_klass(klass_RInfo, res, ne);
1199
1200 if (op->fast_check()) {
1201 __ cmp(klass_RInfo, k_RInfo, ne);
1202 __ b(*failure_target, ne);
1203 } else if (k->is_loaded()) {
1204 __ b(*success_target, eq);
1205 __ ldr(Rtemp, Address(klass_RInfo, k->super_check_offset()));
1206 if (in_bytes(Klass::secondary_super_cache_offset()) != (int) k->super_check_offset()) {
1207 __ cmp(Rtemp, k_RInfo);
1208 __ b(*failure_target, ne);
1209 } else {
1210 __ cmp(klass_RInfo, k_RInfo);
1211 __ cmp(Rtemp, k_RInfo, ne);
1212 __ b(*success_target, eq);
1213 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1214 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1215 __ cbz(R0, *failure_target);
1216 }
1217 } else {
1218 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1219 __ b(*success_target, eq);
1220 // check for immediate positive hit
1221 __ ldr(Rtemp, Address(klass_RInfo, Rtemp));
1222 __ cmp(klass_RInfo, k_RInfo);
1223 __ cmp(Rtemp, k_RInfo, ne);
1224 __ b(*success_target, eq);
1225 // check for immediate negative hit
1226 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1227 __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1228 __ b(*failure_target, ne);
1229 // slow case
1230 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1231 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1232 __ cbz(R0, *failure_target);
1233 }
1234
1235 if (op->should_profile()) {
1236 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1237 typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, res, tmp1,
1238 &profile_cast_success, &profile_cast_failure,
1239 &done, stub->entry());
1240 }
1241 __ bind(done);
1242 break;
1243 }
1244
1245 case lir_instanceof: {
1246 Register obj = op->object()->as_register();
1247 Register res = op->result_opr()->as_register();
1248 Register klass_RInfo = op->tmp1()->as_register();
1249 Register k_RInfo = op->tmp2()->as_register();
1250 ciKlass* k = op->klass();
1251 assert_different_registers(res, klass_RInfo, k_RInfo, Rtemp);
1252
1253 ciMethodData* md;
1254 ciProfileData* data;
1255 int mdo_offset_bias = 0;
1256
1257 Label done;
1258
1259 Label profile_cast_failure, profile_cast_success;
1260 Label *failure_target = op->should_profile() ? &profile_cast_failure : &done;
1261 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1262
1263 __ movs(res, obj);
1264
1265 if (op->should_profile()) {
1266 typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, res, klass_RInfo, Rtemp, &done);
1267 } else {
1268 __ b(done, eq);
1269 }
1270
1271 if (k->is_loaded()) {
1272 __ mov_metadata(k_RInfo, k->constant_encoding());
1273 } else {
1274 op->info_for_patch()->add_register_oop(FrameMap::as_oop_opr(res));
1275 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1276 }
1277 __ load_klass(klass_RInfo, res);
1278
1279 if (!op->should_profile()) {
1280 __ mov(res, 0);
1281 }
1282
1283 if (op->fast_check()) {
1284 __ cmp(klass_RInfo, k_RInfo);
1285 if (!op->should_profile()) {
1286 set_instanceof_result(_masm, res, eq);
1287 } else {
1288 __ b(profile_cast_failure, ne);
1289 }
1290 } else if (k->is_loaded()) {
1291 __ ldr(Rtemp, Address(klass_RInfo, k->super_check_offset()));
1292 if (in_bytes(Klass::secondary_super_cache_offset()) != (int) k->super_check_offset()) {
1293 __ cmp(Rtemp, k_RInfo);
1294 if (!op->should_profile()) {
1295 set_instanceof_result(_masm, res, eq);
1296 } else {
1297 __ b(profile_cast_failure, ne);
1298 }
1299 } else {
1300 __ cmp(klass_RInfo, k_RInfo);
1301 __ cond_cmp(Rtemp, k_RInfo, ne);
1302 if (!op->should_profile()) {
1303 set_instanceof_result(_masm, res, eq);
1304 }
1305 __ b(*success_target, eq);
1306 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1307 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1308 if (!op->should_profile()) {
1309 move_regs(R0, res);
1310 } else {
1311 __ cbz(R0, *failure_target);
1312 }
1313 }
1314 } else {
1315 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1316 // check for immediate positive hit
1317 __ cmp(klass_RInfo, k_RInfo);
1318 if (!op->should_profile()) {
1319 __ ldr(res, Address(klass_RInfo, Rtemp), ne);
1320 __ cond_cmp(res, k_RInfo, ne);
1321 set_instanceof_result(_masm, res, eq);
1322 } else {
1323 __ ldr(Rtemp, Address(klass_RInfo, Rtemp), ne);
1324 __ cond_cmp(Rtemp, k_RInfo, ne);
1325 }
1326 __ b(*success_target, eq);
1327 // check for immediate negative hit
1328 if (op->should_profile()) {
1329 __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1330 }
1331 __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1332 if (!op->should_profile()) {
1333 __ mov(res, 0, ne);
1334 }
1335 __ b(*failure_target, ne);
1336 // slow case
1337 assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1338 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1339 if (!op->should_profile()) {
1340 move_regs(R0, res);
1341 }
1342 if (op->should_profile()) {
1343 __ cbz(R0, *failure_target);
1344 }
1345 }
1346
1347 if (op->should_profile()) {
1348 Label done_ok, done_failure;
1349 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1350 typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, res, tmp1,
1351 &profile_cast_success, &profile_cast_failure,
1352 &done_ok, &done_failure);
1353 __ bind(done_failure);
1354 __ mov(res, 0);
1355 __ b(done);
1356 __ bind(done_ok);
1357 __ mov(res, 1);
1358 }
1359 __ bind(done);
1360 break;
1361 }
1362 default:
1363 ShouldNotReachHere();
1364 }
1365 }
1366
1367
1368 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1369 // if (*addr == cmpval) {
1370 // *addr = newval;
1371 // dest = 1;
1372 // } else {
1373 // dest = 0;
1374 // }
1375 // FIXME: membar_release
1376 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
1377 Register addr = op->addr()->is_register() ?
1378 op->addr()->as_pointer_register() :
1379 op->addr()->as_address_ptr()->base()->as_pointer_register();
1380 assert(op->addr()->is_register() || op->addr()->as_address_ptr()->disp() == 0, "unexpected disp");
1381 assert(op->addr()->is_register() || op->addr()->as_address_ptr()->index() == LIR_OprDesc::illegalOpr(), "unexpected index");
1382 if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
1383 Register cmpval = op->cmp_value()->as_register();
1384 Register newval = op->new_value()->as_register();
1385 Register dest = op->result_opr()->as_register();
1386 assert_different_registers(dest, addr, cmpval, newval, Rtemp);
1387
1388 __ atomic_cas_bool(cmpval, newval, addr, 0, Rtemp); // Rtemp free by default at C1 LIR layer
1389 __ mov(dest, 1, eq);
1390 __ mov(dest, 0, ne);
1391 } else if (op->code() == lir_cas_long) {
1392 assert(VM_Version::supports_cx8(), "wrong machine");
1393 Register cmp_value_lo = op->cmp_value()->as_register_lo();
1394 Register cmp_value_hi = op->cmp_value()->as_register_hi();
1395 Register new_value_lo = op->new_value()->as_register_lo();
1396 Register new_value_hi = op->new_value()->as_register_hi();
1397 Register dest = op->result_opr()->as_register();
1398 Register tmp_lo = op->tmp1()->as_register_lo();
1399 Register tmp_hi = op->tmp1()->as_register_hi();
1400
1401 assert_different_registers(tmp_lo, tmp_hi, cmp_value_lo, cmp_value_hi, dest, new_value_lo, new_value_hi, addr);
1402 assert(tmp_hi->encoding() == tmp_lo->encoding() + 1, "non aligned register pair");
1403 assert(new_value_hi->encoding() == new_value_lo->encoding() + 1, "non aligned register pair");
1404 assert((tmp_lo->encoding() & 0x1) == 0, "misaligned register pair");
1405 assert((new_value_lo->encoding() & 0x1) == 0, "misaligned register pair");
1406 __ atomic_cas64(tmp_lo, tmp_hi, dest, cmp_value_lo, cmp_value_hi,
1407 new_value_lo, new_value_hi, addr, 0);
1408 } else {
1409 Unimplemented();
1410 }
1411 // FIXME: is full membar really needed instead of just membar_acquire?
1412 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp);
1413 }
1414
1415
1416 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1417 AsmCondition acond = al;
1418 AsmCondition ncond = nv;
1419 if (opr1 != opr2) {
1420 switch (condition) {
1421 case lir_cond_equal: acond = eq; ncond = ne; break;
1422 case lir_cond_notEqual: acond = ne; ncond = eq; break;
1423 case lir_cond_less: acond = lt; ncond = ge; break;
1424 case lir_cond_lessEqual: acond = le; ncond = gt; break;
1425 case lir_cond_greaterEqual: acond = ge; ncond = lt; break;
1426 case lir_cond_greater: acond = gt; ncond = le; break;
1427 case lir_cond_aboveEqual: acond = hs; ncond = lo; break;
1428 case lir_cond_belowEqual: acond = ls; ncond = hi; break;
1429 default: ShouldNotReachHere();
1430 }
1431 }
1432
1433 for (;;) { // two iterations only
1434 if (opr1 == result) {
1435 // do nothing
1436 } else if (opr1->is_single_cpu()) {
1437 __ mov(result->as_register(), opr1->as_register(), acond);
1438 } else if (opr1->is_double_cpu()) {
1439 __ long_move(result->as_register_lo(), result->as_register_hi(),
1440 opr1->as_register_lo(), opr1->as_register_hi(), acond);
1441 } else if (opr1->is_single_stack()) {
1442 __ ldr(result->as_register(), frame_map()->address_for_slot(opr1->single_stack_ix()), acond);
1443 } else if (opr1->is_double_stack()) {
1444 __ ldr(result->as_register_lo(),
1445 frame_map()->address_for_slot(opr1->double_stack_ix(), lo_word_offset_in_bytes), acond);
1446 __ ldr(result->as_register_hi(),
1447 frame_map()->address_for_slot(opr1->double_stack_ix(), hi_word_offset_in_bytes), acond);
1448 } else if (opr1->is_illegal()) {
1449 // do nothing: this part of the cmove has been optimized away in the peephole optimizer
1450 } else {
1451 assert(opr1->is_constant(), "must be");
1452 LIR_Const* c = opr1->as_constant_ptr();
1453
1454 switch (c->type()) {
1455 case T_INT:
1456 __ mov_slow(result->as_register(), c->as_jint(), acond);
1457 break;
1458 case T_LONG:
1459 __ mov_slow(result->as_register_lo(), c->as_jint_lo(), acond);
1460 __ mov_slow(result->as_register_hi(), c->as_jint_hi(), acond);
1461 break;
1462 case T_OBJECT:
1463 __ mov_oop(result->as_register(), c->as_jobject(), 0, acond);
1464 break;
1465 case T_FLOAT:
1466 #ifdef __SOFTFP__
1467 // not generated now.
1468 __ mov_slow(result->as_register(), c->as_jint(), acond);
1469 #else
1470 __ mov_float(result->as_float_reg(), c->as_jfloat(), acond);
1471 #endif // __SOFTFP__
1472 break;
1473 case T_DOUBLE:
1474 #ifdef __SOFTFP__
1475 // not generated now.
1476 __ mov_slow(result->as_register_lo(), c->as_jint_lo(), acond);
1477 __ mov_slow(result->as_register_hi(), c->as_jint_hi(), acond);
1478 #else
1479 __ mov_double(result->as_double_reg(), c->as_jdouble(), acond);
1480 #endif // __SOFTFP__
1481 break;
1482 case T_METADATA:
1483 __ mov_metadata(result->as_register(), c->as_metadata(), acond);
1484 break;
1485 default:
1486 ShouldNotReachHere();
1487 }
1488 }
1489
1490 // Negate the condition and repeat the algorithm with the second operand
1491 if (opr1 == opr2) { break; }
1492 opr1 = opr2;
1493 acond = ncond;
1494 }
1495 }
1496
1497 #ifdef ASSERT
1498 static int reg_size(LIR_Opr op) {
1499 switch (op->type()) {
1500 case T_FLOAT:
1501 case T_INT: return BytesPerInt;
1502 case T_LONG:
1503 case T_DOUBLE: return BytesPerLong;
1504 case T_OBJECT:
1505 case T_ARRAY:
1506 case T_METADATA: return BytesPerWord;
1507 case T_ADDRESS:
1508 case T_ILLEGAL: // fall through
1509 default: ShouldNotReachHere(); return -1;
1510 }
1511 }
1512 #endif
1513
1514 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1515 assert(info == NULL, "unused on this code path");
1516 assert(dest->is_register(), "wrong items state");
1517
1518 if (right->is_address()) {
1519 // special case for adding shifted/extended register
1520 const Register res = dest->as_pointer_register();
1521 const Register lreg = left->as_pointer_register();
1522 const LIR_Address* addr = right->as_address_ptr();
1523
1524 assert(addr->base()->as_pointer_register() == lreg && addr->index()->is_register() && addr->disp() == 0, "must be");
1525
1526 int scale = addr->scale();
1527 AsmShift shift = lsl;
1528
1529
1530 assert(reg_size(addr->base()) == reg_size(addr->index()), "should be");
1531 assert(reg_size(addr->base()) == reg_size(dest), "should be");
1532 assert(reg_size(dest) == wordSize, "should be");
1533
1534 AsmOperand operand(addr->index()->as_pointer_register(), shift, scale);
1535 switch (code) {
1536 case lir_add: __ add(res, lreg, operand); break;
1537 case lir_sub: __ sub(res, lreg, operand); break;
1538 default: ShouldNotReachHere();
1539 }
1540
1541 } else if (left->is_address()) {
1542 assert(code == lir_sub && right->is_single_cpu(), "special case used by strength_reduce_multiply()");
1543 const LIR_Address* addr = left->as_address_ptr();
1544 const Register res = dest->as_register();
1545 const Register rreg = right->as_register();
1546 assert(addr->base()->as_register() == rreg && addr->index()->is_register() && addr->disp() == 0, "must be");
1547 __ rsb(res, rreg, AsmOperand(addr->index()->as_register(), lsl, addr->scale()));
1548
1549 } else if (dest->is_single_cpu()) {
1550 assert(left->is_single_cpu(), "unexpected left operand");
1551
1552 const Register res = dest->as_register();
1553 const Register lreg = left->as_register();
1554
1555 if (right->is_single_cpu()) {
1556 const Register rreg = right->as_register();
1557 switch (code) {
1558 case lir_add: __ add_32(res, lreg, rreg); break;
1559 case lir_sub: __ sub_32(res, lreg, rreg); break;
1560 case lir_mul: __ mul_32(res, lreg, rreg); break;
1561 default: ShouldNotReachHere();
1562 }
1563 } else {
1564 assert(right->is_constant(), "must be");
1565 const jint c = right->as_constant_ptr()->as_jint();
1566 if (!Assembler::is_arith_imm_in_range(c)) {
1567 BAILOUT("illegal arithmetic operand");
1568 }
1569 switch (code) {
1570 case lir_add: __ add_32(res, lreg, c); break;
1571 case lir_sub: __ sub_32(res, lreg, c); break;
1572 default: ShouldNotReachHere();
1573 }
1574 }
1575
1576 } else if (dest->is_double_cpu()) {
1577 Register res_lo = dest->as_register_lo();
1578 Register res_hi = dest->as_register_hi();
1579 Register lreg_lo = left->as_register_lo();
1580 Register lreg_hi = left->as_register_hi();
1581 if (right->is_double_cpu()) {
1582 Register rreg_lo = right->as_register_lo();
1583 Register rreg_hi = right->as_register_hi();
1584 if (res_lo == lreg_hi || res_lo == rreg_hi) {
1585 res_lo = Rtemp;
1586 }
1587 switch (code) {
1588 case lir_add:
1589 __ adds(res_lo, lreg_lo, rreg_lo);
1590 __ adc(res_hi, lreg_hi, rreg_hi);
1591 break;
1592 case lir_sub:
1593 __ subs(res_lo, lreg_lo, rreg_lo);
1594 __ sbc(res_hi, lreg_hi, rreg_hi);
1595 break;
1596 default:
1597 ShouldNotReachHere();
1598 }
1599 } else {
1600 assert(right->is_constant(), "must be");
1601 assert((right->as_constant_ptr()->as_jlong() >> 32) == 0, "out of range");
1602 const jint c = (jint) right->as_constant_ptr()->as_jlong();
1603 if (res_lo == lreg_hi) {
1604 res_lo = Rtemp;
1605 }
1606 switch (code) {
1607 case lir_add:
1608 __ adds(res_lo, lreg_lo, c);
1609 __ adc(res_hi, lreg_hi, 0);
1610 break;
1611 case lir_sub:
1612 __ subs(res_lo, lreg_lo, c);
1613 __ sbc(res_hi, lreg_hi, 0);
1614 break;
1615 default:
1616 ShouldNotReachHere();
1617 }
1618 }
1619 move_regs(res_lo, dest->as_register_lo());
1620
1621 } else if (dest->is_single_fpu()) {
1622 assert(left->is_single_fpu(), "must be");
1623 assert(right->is_single_fpu(), "must be");
1624 const FloatRegister res = dest->as_float_reg();
1625 const FloatRegister lreg = left->as_float_reg();
1626 const FloatRegister rreg = right->as_float_reg();
1627 switch (code) {
1628 case lir_add: __ add_float(res, lreg, rreg); break;
1629 case lir_sub: __ sub_float(res, lreg, rreg); break;
1630 case lir_mul: __ mul_float(res, lreg, rreg); break;
1631 case lir_div: __ div_float(res, lreg, rreg); break;
1632 default: ShouldNotReachHere();
1633 }
1634 } else if (dest->is_double_fpu()) {
1635 assert(left->is_double_fpu(), "must be");
1636 assert(right->is_double_fpu(), "must be");
1637 const FloatRegister res = dest->as_double_reg();
1638 const FloatRegister lreg = left->as_double_reg();
1639 const FloatRegister rreg = right->as_double_reg();
1640 switch (code) {
1641 case lir_add: __ add_double(res, lreg, rreg); break;
1642 case lir_sub: __ sub_double(res, lreg, rreg); break;
1643 case lir_mul: __ mul_double(res, lreg, rreg); break;
1644 case lir_div: __ div_double(res, lreg, rreg); break;
1645 default: ShouldNotReachHere();
1646 }
1647 } else {
1648 ShouldNotReachHere();
1649 }
1650 }
1651
1652
1653 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1654 switch (code) {
1655 case lir_abs:
1656 __ abs_double(dest->as_double_reg(), value->as_double_reg());
1657 break;
1658 case lir_sqrt:
1659 __ sqrt_double(dest->as_double_reg(), value->as_double_reg());
1660 break;
1661 default:
1662 ShouldNotReachHere();
1663 }
1664 }
1665
1666
1667 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1668 assert(dest->is_register(), "wrong items state");
1669 assert(left->is_register(), "wrong items state");
1670
1671 if (dest->is_single_cpu()) {
1672
1673 const Register res = dest->as_register();
1674 const Register lreg = left->as_register();
1675
1676 if (right->is_single_cpu()) {
1677 const Register rreg = right->as_register();
1678 switch (code) {
1679 case lir_logic_and: __ and_32(res, lreg, rreg); break;
1680 case lir_logic_or: __ orr_32(res, lreg, rreg); break;
1681 case lir_logic_xor: __ eor_32(res, lreg, rreg); break;
1682 default: ShouldNotReachHere();
1683 }
1684 } else {
1685 assert(right->is_constant(), "must be");
1686 const uint c = (uint)right->as_constant_ptr()->as_jint();
1687 if (!Assembler::is_arith_imm_in_range(c)) {
1688 BAILOUT("illegal arithmetic operand");
1689 }
1690 switch (code) {
1691 case lir_logic_and: __ and_32(res, lreg, c); break;
1692 case lir_logic_or: __ orr_32(res, lreg, c); break;
1693 case lir_logic_xor: __ eor_32(res, lreg, c); break;
1694 default: ShouldNotReachHere();
1695 }
1696 }
1697 } else {
1698 assert(dest->is_double_cpu(), "should be");
1699 Register res_lo = dest->as_register_lo();
1700
1701 assert (dest->type() == T_LONG, "unexpected result type");
1702 assert (left->type() == T_LONG, "unexpected left type");
1703 assert (right->type() == T_LONG, "unexpected right type");
1704
1705 const Register res_hi = dest->as_register_hi();
1706 const Register lreg_lo = left->as_register_lo();
1707 const Register lreg_hi = left->as_register_hi();
1708
1709 if (right->is_register()) {
1710 const Register rreg_lo = right->as_register_lo();
1711 const Register rreg_hi = right->as_register_hi();
1712 if (res_lo == lreg_hi || res_lo == rreg_hi) {
1713 res_lo = Rtemp; // Temp register helps to avoid overlap between result and input
1714 }
1715 switch (code) {
1716 case lir_logic_and:
1717 __ andr(res_lo, lreg_lo, rreg_lo);
1718 __ andr(res_hi, lreg_hi, rreg_hi);
1719 break;
1720 case lir_logic_or:
1721 __ orr(res_lo, lreg_lo, rreg_lo);
1722 __ orr(res_hi, lreg_hi, rreg_hi);
1723 break;
1724 case lir_logic_xor:
1725 __ eor(res_lo, lreg_lo, rreg_lo);
1726 __ eor(res_hi, lreg_hi, rreg_hi);
1727 break;
1728 default:
1729 ShouldNotReachHere();
1730 }
1731 move_regs(res_lo, dest->as_register_lo());
1732 } else {
1733 assert(right->is_constant(), "must be");
1734 const jint c_lo = (jint) right->as_constant_ptr()->as_jlong();
1735 const jint c_hi = (jint) (right->as_constant_ptr()->as_jlong() >> 32);
1736 // Case for logic_or from do_ClassIDIntrinsic()
1737 if (c_hi == 0 && AsmOperand::is_rotated_imm(c_lo)) {
1738 switch (code) {
1739 case lir_logic_and:
1740 __ andr(res_lo, lreg_lo, c_lo);
1741 __ mov(res_hi, 0);
1742 break;
1743 case lir_logic_or:
1744 __ orr(res_lo, lreg_lo, c_lo);
1745 break;
1746 case lir_logic_xor:
1747 __ eor(res_lo, lreg_lo, c_lo);
1748 break;
1749 default:
1750 ShouldNotReachHere();
1751 }
1752 } else if (code == lir_logic_and &&
1753 c_hi == -1 &&
1754 (AsmOperand::is_rotated_imm(c_lo) ||
1755 AsmOperand::is_rotated_imm(~c_lo))) {
1756 // Another case which handles logic_and from do_ClassIDIntrinsic()
1757 if (AsmOperand::is_rotated_imm(c_lo)) {
1758 __ andr(res_lo, lreg_lo, c_lo);
1759 } else {
1760 __ bic(res_lo, lreg_lo, ~c_lo);
1761 }
1762 if (res_hi != lreg_hi) {
1763 __ mov(res_hi, lreg_hi);
1764 }
1765 } else {
1766 BAILOUT("64 bit constant cannot be inlined");
1767 }
1768 }
1769 }
1770 }
1771
1772
1773
1774 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1775 if (opr1->is_single_cpu()) {
1776 if (opr2->is_constant()) {
1777 switch (opr2->as_constant_ptr()->type()) {
1778 case T_INT: {
1779 const jint c = opr2->as_constant_ptr()->as_jint();
1780 if (Assembler::is_arith_imm_in_range(c)) {
1781 __ cmp_32(opr1->as_register(), c);
1782 } else if (Assembler::is_arith_imm_in_range(-c)) {
1783 __ cmn_32(opr1->as_register(), -c);
1784 } else {
1785 // This can happen when compiling lookupswitch
1786 __ mov_slow(Rtemp, c);
1787 __ cmp_32(opr1->as_register(), Rtemp);
1788 }
1789 break;
1790 }
1791 case T_OBJECT:
1792 assert(opr2->as_constant_ptr()->as_jobject() == NULL, "cannot handle otherwise");
1793 __ cmp(opr1->as_register(), 0);
1794 break;
1795 case T_METADATA:
1796 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "Only equality tests");
1797 assert(opr2->as_constant_ptr()->as_metadata() == NULL, "cannot handle otherwise");
1798 __ cmp(opr1->as_register(), 0);
1799 break;
1800 default:
1801 ShouldNotReachHere();
1802 }
1803 } else if (opr2->is_single_cpu()) {
1804 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1805 assert(opr2->type() == T_OBJECT || opr2->type() == T_ARRAY, "incompatibe type");
1806 __ cmpoop(opr1->as_register(), opr2->as_register());
1807 } else if (opr1->type() == T_METADATA || opr1->type() == T_ADDRESS) {
1808 assert(opr2->type() == T_METADATA || opr2->type() == T_ADDRESS, "incompatibe type");
1809 __ cmp(opr1->as_register(), opr2->as_register());
1810 } else {
1811 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY && opr2->type() != T_METADATA && opr2->type() != T_ADDRESS, "incompatibe type");
1812 __ cmp_32(opr1->as_register(), opr2->as_register());
1813 }
1814 } else {
1815 ShouldNotReachHere();
1816 }
1817 } else if (opr1->is_double_cpu()) {
1818 Register xlo = opr1->as_register_lo();
1819 Register xhi = opr1->as_register_hi();
1820 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1821 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "cannot handle otherwise");
1822 __ orrs(Rtemp, xlo, xhi);
1823 } else if (opr2->is_register()) {
1824 Register ylo = opr2->as_register_lo();
1825 Register yhi = opr2->as_register_hi();
1826 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1827 __ teq(xhi, yhi);
1828 __ teq(xlo, ylo, eq);
1829 } else {
1830 __ subs(Rtemp, xlo, ylo);
1831 __ sbcs(Rtemp, xhi, yhi);
1832 }
1833 } else {
1834 ShouldNotReachHere();
1835 }
1836 } else if (opr1->is_single_fpu()) {
1837 if (opr2->is_constant()) {
1838 assert(opr2->as_jfloat() == 0.0f, "cannot handle otherwise");
1839 __ cmp_zero_float(opr1->as_float_reg());
1840 } else {
1841 __ cmp_float(opr1->as_float_reg(), opr2->as_float_reg());
1842 }
1843 } else if (opr1->is_double_fpu()) {
1844 if (opr2->is_constant()) {
1845 assert(opr2->as_jdouble() == 0.0, "cannot handle otherwise");
1846 __ cmp_zero_double(opr1->as_double_reg());
1847 } else {
1848 __ cmp_double(opr1->as_double_reg(), opr2->as_double_reg());
1849 }
1850 } else {
1851 ShouldNotReachHere();
1852 }
1853 }
1854
1855 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
1856 const Register res = dst->as_register();
1857 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1858 comp_op(lir_cond_unknown, left, right, op);
1859 __ fmstat();
1860 if (code == lir_ucmp_fd2i) { // unordered is less
1861 __ mvn(res, 0, lt);
1862 __ mov(res, 1, ge);
1863 } else { // unordered is greater
1864 __ mov(res, 1, cs);
1865 __ mvn(res, 0, cc);
1866 }
1867 __ mov(res, 0, eq);
1868
1869 } else {
1870 assert(code == lir_cmp_l2i, "must be");
1871
1872 Label done;
1873 const Register xlo = left->as_register_lo();
1874 const Register xhi = left->as_register_hi();
1875 const Register ylo = right->as_register_lo();
1876 const Register yhi = right->as_register_hi();
1877 __ cmp(xhi, yhi);
1878 __ mov(res, 1, gt);
1879 __ mvn(res, 0, lt);
1880 __ b(done, ne);
1881 __ subs(res, xlo, ylo);
1882 __ mov(res, 1, hi);
1883 __ mvn(res, 0, lo);
1884 __ bind(done);
1885 }
1886 }
1887
1888
1889 void LIR_Assembler::align_call(LIR_Code code) {
1890 // Not needed
1891 }
1892
1893
1894 void LIR_Assembler::call(LIR_OpJavaCall *op, relocInfo::relocType rtype) {
1895 int ret_addr_offset = __ patchable_call(op->addr(), rtype);
1896 assert(ret_addr_offset == __ offset(), "embedded return address not allowed");
1897 add_call_info_here(op->info());
1898 }
1899
1900
1901 void LIR_Assembler::ic_call(LIR_OpJavaCall *op) {
1902 bool near_range = __ cache_fully_reachable();
1903 address oop_address = pc();
1904
1905 bool use_movw = VM_Version::supports_movw();
1906
1907 // Ricklass may contain something that is not a metadata pointer so
1908 // mov_metadata can't be used
1909 InlinedAddress value((address)Universe::non_oop_word());
1910 InlinedAddress addr(op->addr());
1911 if (use_movw) {
1912 __ movw(Ricklass, ((unsigned int)Universe::non_oop_word()) & 0xffff);
1913 __ movt(Ricklass, ((unsigned int)Universe::non_oop_word()) >> 16);
1914 } else {
1915 // No movw/movt, must be load a pc relative value but no
1916 // relocation so no metadata table to load from.
1917 // Use a b instruction rather than a bl, inline constant after the
1918 // branch, use a PC relative ldr to load the constant, arrange for
1919 // the call to return after the constant(s).
1920 __ ldr_literal(Ricklass, value);
1921 }
1922 __ relocate(virtual_call_Relocation::spec(oop_address));
1923 if (near_range && use_movw) {
1924 __ bl(op->addr());
1925 } else {
1926 Label call_return;
1927 __ adr(LR, call_return);
1928 if (near_range) {
1929 __ b(op->addr());
1930 } else {
1931 __ indirect_jump(addr, Rtemp);
1932 __ bind_literal(addr);
1933 }
1934 if (!use_movw) {
1935 __ bind_literal(value);
1936 }
1937 __ bind(call_return);
1938 }
1939 add_call_info(code_offset(), op->info());
1940 }
1941
1942 void LIR_Assembler::emit_static_call_stub() {
1943 address call_pc = __ pc();
1944 address stub = __ start_a_stub(call_stub_size());
1945 if (stub == NULL) {
1946 BAILOUT("static call stub overflow");
1947 }
1948
1949 DEBUG_ONLY(int offset = code_offset();)
1950
1951 InlinedMetadata metadata_literal(NULL);
1952 __ relocate(static_stub_Relocation::spec(call_pc));
1953 // If not a single instruction, NativeMovConstReg::next_instruction_address()
1954 // must jump over the whole following ldr_literal.
1955 // (See CompiledStaticCall::set_to_interpreted())
1956 #ifdef ASSERT
1957 address ldr_site = __ pc();
1958 #endif
1959 __ ldr_literal(Rmethod, metadata_literal);
1960 assert(nativeMovConstReg_at(ldr_site)->next_instruction_address() == __ pc(), "Fix ldr_literal or its parsing");
1961 bool near_range = __ cache_fully_reachable();
1962 InlinedAddress dest((address)-1);
1963 if (near_range) {
1964 address branch_site = __ pc();
1965 __ b(branch_site); // b to self maps to special NativeJump -1 destination
1966 } else {
1967 __ indirect_jump(dest, Rtemp);
1968 }
1969 __ bind_literal(metadata_literal); // includes spec_for_immediate reloc
1970 if (!near_range) {
1971 __ bind_literal(dest); // special NativeJump -1 destination
1972 }
1973
1974 assert(code_offset() - offset <= call_stub_size(), "overflow");
1975 __ end_a_stub();
1976 }
1977
1978 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1979 assert(exceptionOop->as_register() == Rexception_obj, "must match");
1980 assert(exceptionPC->as_register() == Rexception_pc, "must match");
1981 info->add_register_oop(exceptionOop);
1982
1983 Runtime1::StubID handle_id = compilation()->has_fpu_code() ?
1984 Runtime1::handle_exception_id :
1985 Runtime1::handle_exception_nofpu_id;
1986 Label return_address;
1987 __ adr(Rexception_pc, return_address);
1988 __ call(Runtime1::entry_for(handle_id), relocInfo::runtime_call_type);
1989 __ bind(return_address);
1990 add_call_info_here(info); // for exception handler
1991 }
1992
1993 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1994 assert(exceptionOop->as_register() == Rexception_obj, "must match");
1995 __ b(_unwind_handler_entry);
1996 }
1997
1998 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
1999 AsmShift shift = lsl;
2000 switch (code) {
2001 case lir_shl: shift = lsl; break;
2002 case lir_shr: shift = asr; break;
2003 case lir_ushr: shift = lsr; break;
2004 default: ShouldNotReachHere();
2005 }
2006
2007 if (dest->is_single_cpu()) {
2008 __ andr(Rtemp, count->as_register(), 31);
2009 __ mov(dest->as_register(), AsmOperand(left->as_register(), shift, Rtemp));
2010 } else if (dest->is_double_cpu()) {
2011 Register dest_lo = dest->as_register_lo();
2012 Register dest_hi = dest->as_register_hi();
2013 Register src_lo = left->as_register_lo();
2014 Register src_hi = left->as_register_hi();
2015 Register Rcount = count->as_register();
2016 // Resolve possible register conflicts
2017 if (shift == lsl && dest_hi == src_lo) {
2018 dest_hi = Rtemp;
2019 } else if (shift != lsl && dest_lo == src_hi) {
2020 dest_lo = Rtemp;
2021 } else if (dest_lo == src_lo && dest_hi == src_hi) {
2022 dest_lo = Rtemp;
2023 } else if (dest_lo == Rcount || dest_hi == Rcount) {
2024 Rcount = Rtemp;
2025 }
2026 __ andr(Rcount, count->as_register(), 63);
2027 __ long_shift(dest_lo, dest_hi, src_lo, src_hi, shift, Rcount);
2028 move_regs(dest_lo, dest->as_register_lo());
2029 move_regs(dest_hi, dest->as_register_hi());
2030 } else {
2031 ShouldNotReachHere();
2032 }
2033 }
2034
2035
2036 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2037 AsmShift shift = lsl;
2038 switch (code) {
2039 case lir_shl: shift = lsl; break;
2040 case lir_shr: shift = asr; break;
2041 case lir_ushr: shift = lsr; break;
2042 default: ShouldNotReachHere();
2043 }
2044
2045 if (dest->is_single_cpu()) {
2046 count &= 31;
2047 if (count != 0) {
2048 __ mov(dest->as_register(), AsmOperand(left->as_register(), shift, count));
2049 } else {
2050 move_regs(left->as_register(), dest->as_register());
2051 }
2052 } else if (dest->is_double_cpu()) {
2053 count &= 63;
2054 if (count != 0) {
2055 Register dest_lo = dest->as_register_lo();
2056 Register dest_hi = dest->as_register_hi();
2057 Register src_lo = left->as_register_lo();
2058 Register src_hi = left->as_register_hi();
2059 // Resolve possible register conflicts
2060 if (shift == lsl && dest_hi == src_lo) {
2061 dest_hi = Rtemp;
2062 } else if (shift != lsl && dest_lo == src_hi) {
2063 dest_lo = Rtemp;
2064 }
2065 __ long_shift(dest_lo, dest_hi, src_lo, src_hi, shift, count);
2066 move_regs(dest_lo, dest->as_register_lo());
2067 move_regs(dest_hi, dest->as_register_hi());
2068 } else {
2069 __ long_move(dest->as_register_lo(), dest->as_register_hi(),
2070 left->as_register_lo(), left->as_register_hi());
2071 }
2072 } else {
2073 ShouldNotReachHere();
2074 }
2075 }
2076
2077
2078 // Saves 4 given registers in reserved argument area.
2079 void LIR_Assembler::save_in_reserved_area(Register r1, Register r2, Register r3, Register r4) {
2080 verify_reserved_argument_area_size(4);
2081 __ stmia(SP, RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3) | RegisterSet(r4));
2082 }
2083
2084 // Restores 4 given registers from reserved argument area.
2085 void LIR_Assembler::restore_from_reserved_area(Register r1, Register r2, Register r3, Register r4) {
2086 __ ldmia(SP, RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3) | RegisterSet(r4), no_writeback);
2087 }
2088
2089
2090 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2091 ciArrayKlass* default_type = op->expected_type();
2092 Register src = op->src()->as_register();
2093 Register src_pos = op->src_pos()->as_register();
2094 Register dst = op->dst()->as_register();
2095 Register dst_pos = op->dst_pos()->as_register();
2096 Register length = op->length()->as_register();
2097 Register tmp = op->tmp()->as_register();
2098 Register tmp2 = Rtemp;
2099
2100 assert(src == R0 && src_pos == R1 && dst == R2 && dst_pos == R3, "code assumption");
2101
2102 CodeStub* stub = op->stub();
2103
2104 int flags = op->flags();
2105 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2106 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2107
2108 // If we don't know anything or it's an object array, just go through the generic arraycopy
2109 if (default_type == NULL) {
2110
2111 // save arguments, because they will be killed by a runtime call
2112 save_in_reserved_area(R0, R1, R2, R3);
2113
2114 // pass length argument on SP[0]
2115 __ str(length, Address(SP, -2*wordSize, pre_indexed)); // 2 words for a proper stack alignment
2116
2117 address copyfunc_addr = StubRoutines::generic_arraycopy();
2118 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2119 #ifndef PRODUCT
2120 if (PrintC1Statistics) {
2121 __ inc_counter((address)&Runtime1::_generic_arraycopystub_cnt, tmp, tmp2);
2122 }
2123 #endif // !PRODUCT
2124 // the stub is in the code cache so close enough
2125 __ call(copyfunc_addr, relocInfo::runtime_call_type);
2126
2127 __ add(SP, SP, 2*wordSize);
2128
2129 __ cbz_32(R0, *stub->continuation());
2130
2131 __ mvn_32(tmp, R0);
2132 restore_from_reserved_area(R0, R1, R2, R3); // load saved arguments in slow case only
2133 __ sub_32(length, length, tmp);
2134 __ add_32(src_pos, src_pos, tmp);
2135 __ add_32(dst_pos, dst_pos, tmp);
2136
2137 __ b(*stub->entry());
2138
2139 __ bind(*stub->continuation());
2140 return;
2141 }
2142
2143 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(),
2144 "must be true at this point");
2145 int elem_size = type2aelembytes(basic_type);
2146 int shift = exact_log2(elem_size);
2147
2148 // Check for NULL
2149 if (flags & LIR_OpArrayCopy::src_null_check) {
2150 if (flags & LIR_OpArrayCopy::dst_null_check) {
2151 __ cmp(src, 0);
2152 __ cond_cmp(dst, 0, ne); // make one instruction shorter if both checks are needed
2153 __ b(*stub->entry(), eq);
2154 } else {
2155 __ cbz(src, *stub->entry());
2156 }
2157 } else if (flags & LIR_OpArrayCopy::dst_null_check) {
2158 __ cbz(dst, *stub->entry());
2159 }
2160
2161 // If the compiler was not able to prove that exact type of the source or the destination
2162 // of the arraycopy is an array type, check at runtime if the source or the destination is
2163 // an instance type.
2164 if (flags & LIR_OpArrayCopy::type_check) {
2165 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2166 __ load_klass(tmp, dst);
2167 __ ldr_u32(tmp2, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2168 __ mov_slow(tmp, Klass::_lh_neutral_value);
2169 __ cmp_32(tmp2, tmp);
2170 __ b(*stub->entry(), ge);
2171 }
2172
2173 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2174 __ load_klass(tmp, src);
2175 __ ldr_u32(tmp2, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2176 __ mov_slow(tmp, Klass::_lh_neutral_value);
2177 __ cmp_32(tmp2, tmp);
2178 __ b(*stub->entry(), ge);
2179 }
2180 }
2181
2182 // Check if negative
2183 const int all_positive_checks = LIR_OpArrayCopy::src_pos_positive_check |
2184 LIR_OpArrayCopy::dst_pos_positive_check |
2185 LIR_OpArrayCopy::length_positive_check;
2186 switch (flags & all_positive_checks) {
2187 case LIR_OpArrayCopy::src_pos_positive_check:
2188 __ branch_if_negative_32(src_pos, *stub->entry());
2189 break;
2190 case LIR_OpArrayCopy::dst_pos_positive_check:
2191 __ branch_if_negative_32(dst_pos, *stub->entry());
2192 break;
2193 case LIR_OpArrayCopy::length_positive_check:
2194 __ branch_if_negative_32(length, *stub->entry());
2195 break;
2196 case LIR_OpArrayCopy::src_pos_positive_check | LIR_OpArrayCopy::dst_pos_positive_check:
2197 __ branch_if_any_negative_32(src_pos, dst_pos, tmp, *stub->entry());
2198 break;
2199 case LIR_OpArrayCopy::src_pos_positive_check | LIR_OpArrayCopy::length_positive_check:
2200 __ branch_if_any_negative_32(src_pos, length, tmp, *stub->entry());
2201 break;
2202 case LIR_OpArrayCopy::dst_pos_positive_check | LIR_OpArrayCopy::length_positive_check:
2203 __ branch_if_any_negative_32(dst_pos, length, tmp, *stub->entry());
2204 break;
2205 case all_positive_checks:
2206 __ branch_if_any_negative_32(src_pos, dst_pos, length, tmp, *stub->entry());
2207 break;
2208 default:
2209 assert((flags & all_positive_checks) == 0, "the last option");
2210 }
2211
2212 // Range checks
2213 if (flags & LIR_OpArrayCopy::src_range_check) {
2214 __ ldr_s32(tmp2, Address(src, arrayOopDesc::length_offset_in_bytes()));
2215 __ add_32(tmp, src_pos, length);
2216 __ cmp_32(tmp, tmp2);
2217 __ b(*stub->entry(), hi);
2218 }
2219 if (flags & LIR_OpArrayCopy::dst_range_check) {
2220 __ ldr_s32(tmp2, Address(dst, arrayOopDesc::length_offset_in_bytes()));
2221 __ add_32(tmp, dst_pos, length);
2222 __ cmp_32(tmp, tmp2);
2223 __ b(*stub->entry(), hi);
2224 }
2225
2226 // Check if src and dst are of the same type
2227 if (flags & LIR_OpArrayCopy::type_check) {
2228 // We don't know the array types are compatible
2229 if (basic_type != T_OBJECT) {
2230 // Simple test for basic type arrays
2231 if (UseCompressedClassPointers) {
2232 // We don't need decode because we just need to compare
2233 __ ldr_u32(tmp, Address(src, oopDesc::klass_offset_in_bytes()));
2234 __ ldr_u32(tmp2, Address(dst, oopDesc::klass_offset_in_bytes()));
2235 __ cmp_32(tmp, tmp2);
2236 } else {
2237 __ load_klass(tmp, src);
2238 __ load_klass(tmp2, dst);
2239 __ cmp(tmp, tmp2);
2240 }
2241 __ b(*stub->entry(), ne);
2242 } else {
2243 // For object arrays, if src is a sub class of dst then we can
2244 // safely do the copy.
2245 Label cont, slow;
2246
2247 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2248
2249 __ load_klass(tmp, src);
2250 __ load_klass(tmp2, dst);
2251
2252 // We are at a call so all live registers are saved before we
2253 // get here
2254 assert_different_registers(tmp, tmp2, R6, altFP_7_11);
2255
2256 __ check_klass_subtype_fast_path(tmp, tmp2, R6, altFP_7_11, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
2257
2258 __ mov(R6, R0);
2259 __ mov(altFP_7_11, R1);
2260 __ mov(R0, tmp);
2261 __ mov(R1, tmp2);
2262 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); // does not blow any registers except R0, LR and Rtemp
2263 __ cmp_32(R0, 0);
2264 __ mov(R0, R6);
2265 __ mov(R1, altFP_7_11);
2266
2267 if (copyfunc_addr != NULL) { // use stub if available
2268 // src is not a sub class of dst so we have to do a
2269 // per-element check.
2270
2271 __ b(cont, ne);
2272
2273 __ bind(slow);
2274
2275 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2276 if ((flags & mask) != mask) {
2277 // Check that at least both of them object arrays.
2278 assert(flags & mask, "one of the two should be known to be an object array");
2279
2280 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2281 __ load_klass(tmp, src);
2282 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2283 __ load_klass(tmp, dst);
2284 }
2285 int lh_offset = in_bytes(Klass::layout_helper_offset());
2286
2287 __ ldr_u32(tmp2, Address(tmp, lh_offset));
2288
2289 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2290 __ mov_slow(tmp, objArray_lh);
2291 __ cmp_32(tmp, tmp2);
2292 __ b(*stub->entry(), ne);
2293 }
2294
2295 save_in_reserved_area(R0, R1, R2, R3);
2296
2297 Register src_ptr = R0;
2298 Register dst_ptr = R1;
2299 Register len = R2;
2300 Register chk_off = R3;
2301 Register super_k = tmp;
2302
2303 __ add(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2304 __ add_ptr_scaled_int32(src_ptr, src_ptr, src_pos, shift);
2305
2306 __ add(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2307 __ add_ptr_scaled_int32(dst_ptr, dst_ptr, dst_pos, shift);
2308 __ load_klass(tmp, dst);
2309
2310 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2311 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2312
2313 __ ldr(super_k, Address(tmp, ek_offset));
2314
2315 __ mov(len, length);
2316 __ ldr_u32(chk_off, Address(super_k, sco_offset));
2317 __ push(super_k);
2318
2319 __ call(copyfunc_addr, relocInfo::runtime_call_type);
2320
2321 #ifndef PRODUCT
2322 if (PrintC1Statistics) {
2323 Label failed;
2324 __ cbnz_32(R0, failed);
2325 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, tmp, tmp2);
2326 __ bind(failed);
2327 }
2328 #endif // PRODUCT
2329
2330 __ add(SP, SP, wordSize); // Drop super_k argument
2331
2332 __ cbz_32(R0, *stub->continuation());
2333 __ mvn_32(tmp, R0);
2334
2335 // load saved arguments in slow case only
2336 restore_from_reserved_area(R0, R1, R2, R3);
2337
2338 __ sub_32(length, length, tmp);
2339 __ add_32(src_pos, src_pos, tmp);
2340 __ add_32(dst_pos, dst_pos, tmp);
2341
2342 #ifndef PRODUCT
2343 if (PrintC1Statistics) {
2344 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, tmp, tmp2);
2345 }
2346 #endif
2347
2348 __ b(*stub->entry());
2349
2350 __ bind(cont);
2351 } else {
2352 __ b(*stub->entry(), eq);
2353 __ bind(cont);
2354 }
2355 }
2356 }
2357
2358 #ifndef PRODUCT
2359 if (PrintC1Statistics) {
2360 address counter = Runtime1::arraycopy_count_address(basic_type);
2361 __ inc_counter(counter, tmp, tmp2);
2362 }
2363 #endif // !PRODUCT
2364
2365 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2366 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2367 const char *name;
2368 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2369
2370 Register src_ptr = R0;
2371 Register dst_ptr = R1;
2372 Register len = R2;
2373
2374 __ add(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2375 __ add_ptr_scaled_int32(src_ptr, src_ptr, src_pos, shift);
2376
2377 __ add(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2378 __ add_ptr_scaled_int32(dst_ptr, dst_ptr, dst_pos, shift);
2379
2380 __ mov(len, length);
2381
2382 __ call(entry, relocInfo::runtime_call_type);
2383
2384 __ bind(*stub->continuation());
2385 }
2386
2387 #ifdef ASSERT
2388 // emit run-time assertion
2389 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2390 assert(op->code() == lir_assert, "must be");
2391
2392 if (op->in_opr1()->is_valid()) {
2393 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2394 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2395 } else {
2396 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2397 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2398 }
2399
2400 Label ok;
2401 if (op->condition() != lir_cond_always) {
2402 AsmCondition acond = al;
2403 switch (op->condition()) {
2404 case lir_cond_equal: acond = eq; break;
2405 case lir_cond_notEqual: acond = ne; break;
2406 case lir_cond_less: acond = lt; break;
2407 case lir_cond_lessEqual: acond = le; break;
2408 case lir_cond_greaterEqual: acond = ge; break;
2409 case lir_cond_greater: acond = gt; break;
2410 case lir_cond_aboveEqual: acond = hs; break;
2411 case lir_cond_belowEqual: acond = ls; break;
2412 default: ShouldNotReachHere();
2413 }
2414 __ b(ok, acond);
2415 }
2416 if (op->halt()) {
2417 const char* str = __ code_string(op->msg());
2418 __ stop(str);
2419 } else {
2420 breakpoint();
2421 }
2422 __ bind(ok);
2423 }
2424 #endif // ASSERT
2425
2426 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2427 fatal("CRC32 intrinsic is not implemented on this platform");
2428 }
2429
2430 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2431 Register obj = op->obj_opr()->as_pointer_register();
2432 Register hdr = op->hdr_opr()->as_pointer_register();
2433 Register lock = op->lock_opr()->as_pointer_register();
2434 Register tmp = op->scratch_opr()->is_illegal() ? noreg :
2435 op->scratch_opr()->as_pointer_register();
2436
2437 if (!UseFastLocking) {
2438 __ b(*op->stub()->entry());
2439 } else if (op->code() == lir_lock) {
2440 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2441 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
2442 if (op->info() != NULL) {
2443 add_debug_info_for_null_check(null_check_offset, op->info());
2444 }
2445 } else if (op->code() == lir_unlock) {
2446 __ unlock_object(hdr, obj, lock, tmp, *op->stub()->entry());
2447 } else {
2448 ShouldNotReachHere();
2449 }
2450 __ bind(*op->stub()->continuation());
2451 }
2452
2453 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2454 Register obj = op->obj()->as_pointer_register();
2455 Register result = op->result_opr()->as_pointer_register();
2456
2457 CodeEmitInfo* info = op->info();
2458 if (info != NULL) {
2459 add_debug_info_for_null_check_here(info);
2460 }
2461
2462 if (UseCompressedClassPointers) { // On 32 bit arm??
2463 __ ldr_u32(result, Address(obj, oopDesc::klass_offset_in_bytes()));
2464 } else {
2465 __ ldr(result, Address(obj, oopDesc::klass_offset_in_bytes()));
2466 }
2467 }
2468
2469 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2470 ciMethod* method = op->profiled_method();
2471 int bci = op->profiled_bci();
2472 ciMethod* callee = op->profiled_callee();
2473
2474 // Update counter for all call types
2475 ciMethodData* md = method->method_data_or_null();
2476 assert(md != NULL, "Sanity");
2477 ciProfileData* data = md->bci_to_data(bci);
2478 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2479 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2480 Register mdo = op->mdo()->as_register();
2481 assert(op->tmp1()->is_register(), "tmp1 must be allocated");
2482 Register tmp1 = op->tmp1()->as_pointer_register();
2483 assert_different_registers(mdo, tmp1);
2484 __ mov_metadata(mdo, md->constant_encoding());
2485 int mdo_offset_bias = 0;
2486 int max_offset = 4096;
2487 if (md->byte_offset_of_slot(data, CounterData::count_offset()) + data->size_in_bytes() >= max_offset) {
2488 // The offset is large so bias the mdo by the base of the slot so
2489 // that the ldr can use an immediate offset to reference the slots of the data
2490 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2491 __ mov_slow(tmp1, mdo_offset_bias);
2492 __ add(mdo, mdo, tmp1);
2493 }
2494
2495 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2496 // Perform additional virtual call profiling for invokevirtual and
2497 // invokeinterface bytecodes
2498 if (op->should_profile_receiver_type()) {
2499 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2500 Register recv = op->recv()->as_register();
2501 assert_different_registers(mdo, tmp1, recv);
2502 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2503 ciKlass* known_klass = op->known_holder();
2504 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2505 // We know the type that will be seen at this call site; we can
2506 // statically update the MethodData* rather than needing to do
2507 // dynamic tests on the receiver type
2508
2509 // NOTE: we should probably put a lock around this search to
2510 // avoid collisions by concurrent compilations
2511 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2512 uint i;
2513 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2514 ciKlass* receiver = vc_data->receiver(i);
2515 if (known_klass->equals(receiver)) {
2516 Address data_addr(mdo, md->byte_offset_of_slot(data,
2517 VirtualCallData::receiver_count_offset(i)) -
2518 mdo_offset_bias);
2519 __ ldr(tmp1, data_addr);
2520 __ add(tmp1, tmp1, DataLayout::counter_increment);
2521 __ str(tmp1, data_addr);
2522 return;
2523 }
2524 }
2525
2526 // Receiver type not found in profile data; select an empty slot
2527
2528 // Note that this is less efficient than it should be because it
2529 // always does a write to the receiver part of the
2530 // VirtualCallData rather than just the first time
2531 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2532 ciKlass* receiver = vc_data->receiver(i);
2533 if (receiver == NULL) {
2534 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2535 mdo_offset_bias);
2536 __ mov_metadata(tmp1, known_klass->constant_encoding());
2537 __ str(tmp1, recv_addr);
2538 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2539 mdo_offset_bias);
2540 __ ldr(tmp1, data_addr);
2541 __ add(tmp1, tmp1, DataLayout::counter_increment);
2542 __ str(tmp1, data_addr);
2543 return;
2544 }
2545 }
2546 } else {
2547 __ load_klass(recv, recv);
2548 Label update_done;
2549 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2550 // Receiver did not match any saved receiver and there is no empty row for it.
2551 // Increment total counter to indicate polymorphic case.
2552 __ ldr(tmp1, counter_addr);
2553 __ add(tmp1, tmp1, DataLayout::counter_increment);
2554 __ str(tmp1, counter_addr);
2555
2556 __ bind(update_done);
2557 }
2558 } else {
2559 // Static call
2560 __ ldr(tmp1, counter_addr);
2561 __ add(tmp1, tmp1, DataLayout::counter_increment);
2562 __ str(tmp1, counter_addr);
2563 }
2564 }
2565
2566 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2567 fatal("Type profiling not implemented on this platform");
2568 }
2569
2570 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2571 Unimplemented();
2572 }
2573
2574
2575 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2576 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2577 __ add_slow(dst->as_pointer_register(), mon_addr.base(), mon_addr.disp());
2578 }
2579
2580
2581 void LIR_Assembler::align_backward_branch_target() {
2582 // Some ARM processors do better with 8-byte branch target alignment
2583 __ align(8);
2584 }
2585
2586
2587 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2588 // tmp must be unused
2589 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2590
2591 if (left->is_single_cpu()) {
2592 assert (dest->type() == T_INT, "unexpected result type");
2593 assert (left->type() == T_INT, "unexpected left type");
2594 __ neg_32(dest->as_register(), left->as_register());
2595 } else if (left->is_double_cpu()) {
2596 Register dest_lo = dest->as_register_lo();
2597 Register dest_hi = dest->as_register_hi();
2598 Register src_lo = left->as_register_lo();
2599 Register src_hi = left->as_register_hi();
2600 if (dest_lo == src_hi) {
2601 dest_lo = Rtemp;
2602 }
2603 __ rsbs(dest_lo, src_lo, 0);
2604 __ rsc(dest_hi, src_hi, 0);
2605 move_regs(dest_lo, dest->as_register_lo());
2606 } else if (left->is_single_fpu()) {
2607 __ neg_float(dest->as_float_reg(), left->as_float_reg());
2608 } else if (left->is_double_fpu()) {
2609 __ neg_double(dest->as_double_reg(), left->as_double_reg());
2610 } else {
2611 ShouldNotReachHere();
2612 }
2613 }
2614
2615
2616 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2617 assert(patch_code == lir_patch_none, "Patch code not supported");
2618 LIR_Address* addr = addr_opr->as_address_ptr();
2619 if (addr->index()->is_illegal()) {
2620 jint c = addr->disp();
2621 if (!Assembler::is_arith_imm_in_range(c)) {
2622 BAILOUT("illegal arithmetic operand");
2623 }
2624 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), c);
2625 } else {
2626 assert(addr->disp() == 0, "cannot handle otherwise");
2627 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(),
2628 AsmOperand(addr->index()->as_pointer_register(), lsl, addr->scale()));
2629 }
2630 }
2631
2632
2633 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2634 assert(!tmp->is_valid(), "don't need temporary");
2635 __ call(dest);
2636 if (info != NULL) {
2637 add_call_info_here(info);
2638 }
2639 }
2640
2641
2642 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2643 assert(src->is_double_cpu() && dest->is_address() ||
2644 src->is_address() && dest->is_double_cpu(),
2645 "Simple move_op is called for all other cases");
2646
2647 int null_check_offset;
2648 if (dest->is_address()) {
2649 // Store
2650 const LIR_Address* addr = dest->as_address_ptr();
2651 const Register src_lo = src->as_register_lo();
2652 const Register src_hi = src->as_register_hi();
2653 assert(addr->index()->is_illegal() && addr->disp() == 0, "The address is simple already");
2654
2655 if (src_lo < src_hi) {
2656 null_check_offset = __ offset();
2657 __ stmia(addr->base()->as_register(), RegisterSet(src_lo) | RegisterSet(src_hi));
2658 } else {
2659 assert(src_lo < Rtemp, "Rtemp is higher than any allocatable register");
2660 __ mov(Rtemp, src_hi);
2661 null_check_offset = __ offset();
2662 __ stmia(addr->base()->as_register(), RegisterSet(src_lo) | RegisterSet(Rtemp));
2663 }
2664 } else {
2665 // Load
2666 const LIR_Address* addr = src->as_address_ptr();
2667 const Register dest_lo = dest->as_register_lo();
2668 const Register dest_hi = dest->as_register_hi();
2669 assert(addr->index()->is_illegal() && addr->disp() == 0, "The address is simple already");
2670
2671 null_check_offset = __ offset();
2672 if (dest_lo < dest_hi) {
2673 __ ldmia(addr->base()->as_register(), RegisterSet(dest_lo) | RegisterSet(dest_hi));
2674 } else {
2675 assert(dest_lo < Rtemp, "Rtemp is higher than any allocatable register");
2676 __ ldmia(addr->base()->as_register(), RegisterSet(dest_lo) | RegisterSet(Rtemp));
2677 __ mov(dest_hi, Rtemp);
2678 }
2679 }
2680
2681 if (info != NULL) {
2682 add_debug_info_for_null_check(null_check_offset, info);
2683 }
2684 }
2685
2686
2687 void LIR_Assembler::membar() {
2688 __ membar(MacroAssembler::StoreLoad, Rtemp);
2689 }
2690
2691 void LIR_Assembler::membar_acquire() {
2692 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::LoadLoad | MacroAssembler::LoadStore), Rtemp);
2693 }
2694
2695 void LIR_Assembler::membar_release() {
2696 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
2697 }
2698
2699 void LIR_Assembler::membar_loadload() {
2700 __ membar(MacroAssembler::LoadLoad, Rtemp);
2701 }
2702
2703 void LIR_Assembler::membar_storestore() {
2704 __ membar(MacroAssembler::StoreStore, Rtemp);
2705 }
2706
2707 void LIR_Assembler::membar_loadstore() {
2708 __ membar(MacroAssembler::LoadStore, Rtemp);
2709 }
2710
2711 void LIR_Assembler::membar_storeload() {
2712 __ membar(MacroAssembler::StoreLoad, Rtemp);
2713 }
2714
2715 void LIR_Assembler::on_spin_wait() {
2716 Unimplemented();
2717 }
2718
2719 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2720 // Not used on ARM
2721 Unimplemented();
2722 }
2723
2724 void LIR_Assembler::peephole(LIR_List* lir) {
2725 LIR_OpList* inst = lir->instructions_list();
2726 const int inst_length = inst->length();
2727 for (int i = 0; i < inst_length; i++) {
2728 LIR_Op* op = inst->at(i);
2729 switch (op->code()) {
2730 case lir_cmp: {
2731 // Replace:
2732 // cmp rX, y
2733 // cmove [EQ] y, z, rX
2734 // with
2735 // cmp rX, y
2736 // cmove [EQ] illegalOpr, z, rX
2737 //
2738 // or
2739 // cmp rX, y
2740 // cmove [NE] z, y, rX
2741 // with
2742 // cmp rX, y
2743 // cmove [NE] z, illegalOpr, rX
2744 //
2745 // moves from illegalOpr should be removed when converting LIR to native assembly
2746
2747 LIR_Op2* cmp = op->as_Op2();
2748 assert(cmp != NULL, "cmp LIR instruction is not an op2");
2749
2750 if (i + 1 < inst_length) {
2751 LIR_Op2* cmove = inst->at(i + 1)->as_Op2();
2752 if (cmove != NULL && cmove->code() == lir_cmove) {
2753 LIR_Opr cmove_res = cmove->result_opr();
2754 bool res_is_op1 = cmove_res == cmp->in_opr1();
2755 bool res_is_op2 = cmove_res == cmp->in_opr2();
2756 LIR_Opr cmp_res, cmp_arg;
2757 if (res_is_op1) {
2758 cmp_res = cmp->in_opr1();
2759 cmp_arg = cmp->in_opr2();
2760 } else if (res_is_op2) {
2761 cmp_res = cmp->in_opr2();
2762 cmp_arg = cmp->in_opr1();
2763 } else {
2764 cmp_res = LIR_OprFact::illegalOpr;
2765 cmp_arg = LIR_OprFact::illegalOpr;
2766 }
2767
2768 if (cmp_res != LIR_OprFact::illegalOpr) {
2769 LIR_Condition cond = cmove->condition();
2770 if (cond == lir_cond_equal && cmove->in_opr1() == cmp_arg) {
2771 cmove->set_in_opr1(LIR_OprFact::illegalOpr);
2772 } else if (cond == lir_cond_notEqual && cmove->in_opr2() == cmp_arg) {
2773 cmove->set_in_opr2(LIR_OprFact::illegalOpr);
2774 }
2775 }
2776 }
2777 }
2778 break;
2779 }
2780
2781 default:
2782 break;
2783 }
2784 }
2785 }
2786
2787 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2788 assert(src->is_address(), "sanity");
2789 Address addr = as_Address(src->as_address_ptr());
2790
2791 if (code == lir_xchg) {
2792 } else {
2793 assert (!data->is_oop(), "xadd for oops");
2794 }
2795
2796 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
2797
2798 Label retry;
2799 __ bind(retry);
2800
2801 if (data->type() == T_INT || data->is_oop()) {
2802 Register dst = dest->as_register();
2803 Register new_val = noreg;
2804 __ ldrex(dst, addr);
2805 if (code == lir_xadd) {
2806 Register tmp_reg = tmp->as_register();
2807 if (data->is_constant()) {
2808 assert_different_registers(dst, tmp_reg);
2809 __ add_32(tmp_reg, dst, data->as_constant_ptr()->as_jint());
2810 } else {
2811 assert_different_registers(dst, tmp_reg, data->as_register());
2812 __ add_32(tmp_reg, dst, data->as_register());
2813 }
2814 new_val = tmp_reg;
2815 } else {
2816 if (UseCompressedOops && data->is_oop()) {
2817 new_val = tmp->as_pointer_register();
2818 } else {
2819 new_val = data->as_register();
2820 }
2821 assert_different_registers(dst, new_val);
2822 }
2823 __ strex(Rtemp, new_val, addr);
2824
2825 } else if (data->type() == T_LONG) {
2826 Register dst_lo = dest->as_register_lo();
2827 Register new_val_lo = noreg;
2828 Register dst_hi = dest->as_register_hi();
2829
2830 assert(dst_hi->encoding() == dst_lo->encoding() + 1, "non aligned register pair");
2831 assert((dst_lo->encoding() & 0x1) == 0, "misaligned register pair");
2832
2833 __ bind(retry);
2834 __ ldrexd(dst_lo, addr);
2835 if (code == lir_xadd) {
2836 Register tmp_lo = tmp->as_register_lo();
2837 Register tmp_hi = tmp->as_register_hi();
2838
2839 assert(tmp_hi->encoding() == tmp_lo->encoding() + 1, "non aligned register pair");
2840 assert((tmp_lo->encoding() & 0x1) == 0, "misaligned register pair");
2841
2842 if (data->is_constant()) {
2843 jlong c = data->as_constant_ptr()->as_jlong();
2844 assert((jlong)((jint)c) == c, "overflow");
2845 assert_different_registers(dst_lo, dst_hi, tmp_lo, tmp_hi);
2846 __ adds(tmp_lo, dst_lo, (jint)c);
2847 __ adc(tmp_hi, dst_hi, 0);
2848 } else {
2849 Register new_val_lo = data->as_register_lo();
2850 Register new_val_hi = data->as_register_hi();
2851 __ adds(tmp_lo, dst_lo, new_val_lo);
2852 __ adc(tmp_hi, dst_hi, new_val_hi);
2853 assert_different_registers(dst_lo, dst_hi, tmp_lo, tmp_hi, new_val_lo, new_val_hi);
2854 }
2855 new_val_lo = tmp_lo;
2856 } else {
2857 new_val_lo = data->as_register_lo();
2858 Register new_val_hi = data->as_register_hi();
2859
2860 assert_different_registers(dst_lo, dst_hi, new_val_lo, new_val_hi);
2861 assert(new_val_hi->encoding() == new_val_lo->encoding() + 1, "non aligned register pair");
2862 assert((new_val_lo->encoding() & 0x1) == 0, "misaligned register pair");
2863 }
2864 __ strexd(Rtemp, new_val_lo, addr);
2865 } else {
2866 ShouldNotReachHere();
2867 }
2868
2869 __ cbnz_32(Rtemp, retry);
2870 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp);
2871
2872 }
2873
2874 #undef __