1 /*
2 * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2021 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "memory/universe.hpp"
37 #include "nativeInst_ppc.hpp"
38 #include "oops/compressedOops.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/frame.inline.hpp"
41 #include "runtime/safepointMechanism.inline.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "runtime/stubRoutines.hpp"
44 #include "runtime/vm_version.hpp"
45 #include "utilities/powerOfTwo.hpp"
46
47 #define __ _masm->
48
49
50 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5;
51
52
53 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
54 Unimplemented(); return false; // Currently not used on this platform.
55 }
56
57
58 LIR_Opr LIR_Assembler::receiverOpr() {
59 return FrameMap::R3_oop_opr;
60 }
61
62
63 LIR_Opr LIR_Assembler::osrBufferPointer() {
64 return FrameMap::R3_opr;
65 }
66
67
68 // This specifies the stack pointer decrement needed to build the frame.
69 int LIR_Assembler::initial_frame_size_in_bytes() const {
70 return in_bytes(frame_map()->framesize_in_bytes());
71 }
72
73
74 // Inline cache check: the inline cached class is in inline_cache_reg;
75 // we fetch the class of the receiver and compare it with the cached class.
76 // If they do not match we jump to slow case.
77 int LIR_Assembler::check_icache() {
78 int offset = __ offset();
79 __ inline_cache_check(R3_ARG1, R19_inline_cache_reg);
80 return offset;
81 }
82
83 void LIR_Assembler::clinit_barrier(ciMethod* method) {
84 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
85
86 Label L_skip_barrier;
87 Register klass = R20;
88
89 metadata2reg(method->holder()->constant_encoding(), klass);
90 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
91
92 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
93 __ mtctr(klass);
94 __ bctr();
95
96 __ bind(L_skip_barrier);
97 }
98
99 void LIR_Assembler::osr_entry() {
100 // On-stack-replacement entry sequence:
101 //
102 // 1. Create a new compiled activation.
103 // 2. Initialize local variables in the compiled activation. The expression
104 // stack must be empty at the osr_bci; it is not initialized.
105 // 3. Jump to the continuation address in compiled code to resume execution.
106
107 // OSR entry point
108 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
109 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
110 ValueStack* entry_state = osr_entry->end()->state();
111 int number_of_locks = entry_state->locks_size();
112
113 // Create a frame for the compiled activation.
114 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
115
116 // OSR buffer is
117 //
118 // locals[nlocals-1..0]
119 // monitors[number_of_locks-1..0]
120 //
121 // Locals is a direct copy of the interpreter frame so in the osr buffer
122 // the first slot in the local array is the last local from the interpreter
123 // and the last slot is local[0] (receiver) from the interpreter.
124 //
125 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
126 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
127 // in the interpreter frame (the method lock if a sync method).
128
129 // Initialize monitors in the compiled activation.
130 // R3: pointer to osr buffer
131 //
132 // All other registers are dead at this point and the locals will be
133 // copied into place by code emitted in the IR.
134
135 Register OSR_buf = osrBufferPointer()->as_register();
136 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
137 int monitor_offset = BytesPerWord * method()->max_locals() +
138 (2 * BytesPerWord) * (number_of_locks - 1);
139 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
140 // the OSR buffer using 2 word entries: first the lock and then
141 // the oop.
142 for (int i = 0; i < number_of_locks; i++) {
143 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
144 #ifdef ASSERT
145 // Verify the interpreter's monitor has a non-null object.
146 {
147 Label L;
148 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
149 __ cmpdi(CCR0, R0, 0);
150 __ bne(CCR0, L);
151 __ stop("locked object is NULL");
152 __ bind(L);
153 }
154 #endif // ASSERT
155 // Copy the lock field into the compiled activation.
156 Address ml = frame_map()->address_for_monitor_lock(i),
157 mo = frame_map()->address_for_monitor_object(i);
158 assert(ml.index() == noreg && mo.index() == noreg, "sanity");
159 __ ld(R0, slot_offset + 0, OSR_buf);
160 __ std(R0, ml.disp(), ml.base());
161 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
162 __ std(R0, mo.disp(), mo.base());
163 }
164 }
165 }
166
167
168 int LIR_Assembler::emit_exception_handler() {
169 // If the last instruction is a call (typically to do a throw which
170 // is coming at the end after block reordering) the return address
171 // must still point into the code area in order to avoid assertion
172 // failures when searching for the corresponding bci => add a nop
173 // (was bug 5/14/1999 - gri).
174 __ nop();
175
176 // Generate code for the exception handler.
177 address handler_base = __ start_a_stub(exception_handler_size());
178
179 if (handler_base == NULL) {
180 // Not enough space left for the handler.
181 bailout("exception handler overflow");
182 return -1;
183 }
184
185 int offset = code_offset();
186 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id));
187 //__ load_const_optimized(R0, entry_point);
188 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
189 __ mtctr(R0);
190 __ bctr();
191
192 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
193 __ end_a_stub();
194
195 return offset;
196 }
197
198
199 // Emit the code to remove the frame from the stack in the exception
200 // unwind path.
201 int LIR_Assembler::emit_unwind_handler() {
202 _masm->block_comment("Unwind handler");
203
204 int offset = code_offset();
205 bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
206 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
207
208 // Fetch the exception from TLS and clear out exception related thread state.
209 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
210 __ li(R0, 0);
211 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
212 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
213
214 __ bind(_unwind_handler_entry);
215 __ verify_not_null_oop(Rexception);
216 if (preserve_exception) { __ mr(Rexception_save, Rexception); }
217
218 // Perform needed unlocking
219 MonitorExitStub* stub = NULL;
220 if (method()->is_synchronized()) {
221 monitor_address(0, FrameMap::R4_opr);
222 stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
223 __ unlock_object(R5, R6, R4, *stub->entry());
224 __ bind(*stub->continuation());
225 }
226
227 if (compilation()->env()->dtrace_method_probes()) {
228 Unimplemented();
229 }
230
231 // Dispatch to the unwind logic.
232 address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id);
233 //__ load_const_optimized(R0, unwind_stub);
234 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
235 if (preserve_exception) { __ mr(Rexception, Rexception_save); }
236 __ mtctr(R0);
237 __ bctr();
238
239 // Emit the slow path assembly.
240 if (stub != NULL) {
241 stub->emit_code(this);
242 }
243
244 return offset;
245 }
246
247
248 int LIR_Assembler::emit_deopt_handler() {
249 // If the last instruction is a call (typically to do a throw which
250 // is coming at the end after block reordering) the return address
251 // must still point into the code area in order to avoid assertion
252 // failures when searching for the corresponding bci => add a nop
253 // (was bug 5/14/1999 - gri).
254 __ nop();
255
256 // Generate code for deopt handler.
257 address handler_base = __ start_a_stub(deopt_handler_size());
258
259 if (handler_base == NULL) {
260 // Not enough space left for the handler.
261 bailout("deopt handler overflow");
262 return -1;
263 }
264
265 int offset = code_offset();
266 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
267
268 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
269 __ end_a_stub();
270
271 return offset;
272 }
273
274
275 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
276 if (o == NULL) {
277 __ li(reg, 0);
278 } else {
279 AddressLiteral addrlit = __ constant_oop_address(o);
280 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
281 }
282 }
283
284
285 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
286 // Allocate a new index in table to hold the object once it's been patched.
287 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
288 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
289
290 AddressLiteral addrlit((address)NULL, oop_Relocation::spec(oop_index));
291 __ load_const(reg, addrlit, R0);
292
293 patching_epilog(patch, lir_patch_normal, reg, info);
294 }
295
296
297 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
298 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
299 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
300 }
301
302
303 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
304 // Allocate a new index in table to hold the klass once it's been patched.
305 int index = __ oop_recorder()->allocate_metadata_index(NULL);
306 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
307
308 AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index));
309 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
310 __ load_const(reg, addrlit, R0);
311
312 patching_epilog(patch, lir_patch_normal, reg, info);
313 }
314
315
316 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
317 const bool is_int = result->is_single_cpu();
318 Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
319 Register Rdivisor = noreg;
320 Register Rscratch = temp->as_register();
321 Register Rresult = is_int ? result->as_register() : result->as_register_lo();
322 long divisor = -1;
323
324 if (right->is_register()) {
325 Rdivisor = is_int ? right->as_register() : right->as_register_lo();
326 } else {
327 divisor = is_int ? right->as_constant_ptr()->as_jint()
328 : right->as_constant_ptr()->as_jlong();
329 }
330
331 assert(Rdividend != Rscratch, "");
332 assert(Rdivisor != Rscratch, "");
333 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
334
335 if (Rdivisor == noreg) {
336 if (divisor == 1) { // stupid, but can happen
337 if (code == lir_idiv) {
338 __ mr_if_needed(Rresult, Rdividend);
339 } else {
340 __ li(Rresult, 0);
341 }
342
343 } else if (is_power_of_2(divisor)) {
344 // Convert division by a power of two into some shifts and logical operations.
345 int log2 = log2i_exact(divisor);
346
347 // Round towards 0.
348 if (divisor == 2) {
349 if (is_int) {
350 __ srwi(Rscratch, Rdividend, 31);
351 } else {
352 __ srdi(Rscratch, Rdividend, 63);
353 }
354 } else {
355 if (is_int) {
356 __ srawi(Rscratch, Rdividend, 31);
357 } else {
358 __ sradi(Rscratch, Rdividend, 63);
359 }
360 __ clrldi(Rscratch, Rscratch, 64-log2);
361 }
362 __ add(Rscratch, Rdividend, Rscratch);
363
364 if (code == lir_idiv) {
365 if (is_int) {
366 __ srawi(Rresult, Rscratch, log2);
367 } else {
368 __ sradi(Rresult, Rscratch, log2);
369 }
370 } else { // lir_irem
371 __ clrrdi(Rscratch, Rscratch, log2);
372 __ sub(Rresult, Rdividend, Rscratch);
373 }
374
375 } else if (divisor == -1) {
376 if (code == lir_idiv) {
377 __ neg(Rresult, Rdividend);
378 } else {
379 __ li(Rresult, 0);
380 }
381
382 } else {
383 __ load_const_optimized(Rscratch, divisor);
384 if (code == lir_idiv) {
385 if (is_int) {
386 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
387 } else {
388 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
389 }
390 } else {
391 assert(Rscratch != R0, "need both");
392 if (is_int) {
393 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
394 __ mullw(Rscratch, R0, Rscratch);
395 } else {
396 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
397 __ mulld(Rscratch, R0, Rscratch);
398 }
399 __ sub(Rresult, Rdividend, Rscratch);
400 }
401
402 }
403 return;
404 }
405
406 Label regular, done;
407 if (is_int) {
408 __ cmpwi(CCR0, Rdivisor, -1);
409 } else {
410 __ cmpdi(CCR0, Rdivisor, -1);
411 }
412 __ bne(CCR0, regular);
413 if (code == lir_idiv) {
414 __ neg(Rresult, Rdividend);
415 __ b(done);
416 __ bind(regular);
417 if (is_int) {
418 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
419 } else {
420 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
421 }
422 } else { // lir_irem
423 __ li(Rresult, 0);
424 __ b(done);
425 __ bind(regular);
426 if (is_int) {
427 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
428 __ mullw(Rscratch, Rscratch, Rdivisor);
429 } else {
430 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
431 __ mulld(Rscratch, Rscratch, Rdivisor);
432 }
433 __ sub(Rresult, Rdividend, Rscratch);
434 }
435 __ bind(done);
436 }
437
438
439 void LIR_Assembler::emit_op3(LIR_Op3* op) {
440 switch (op->code()) {
441 case lir_idiv:
442 case lir_irem:
443 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
444 op->result_opr(), op->info());
445 break;
446 case lir_fmad:
447 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
448 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
449 break;
450 case lir_fmaf:
451 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
452 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
453 break;
454 default: ShouldNotReachHere(); break;
455 }
456 }
457
458
459 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
460 #ifdef ASSERT
461 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
462 if (op->block() != NULL) _branch_target_blocks.append(op->block());
463 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
464 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
465 #endif
466
467 Label *L = op->label();
468 if (op->cond() == lir_cond_always) {
469 __ b(*L);
470 } else {
471 Label done;
472 bool is_unordered = false;
473 if (op->code() == lir_cond_float_branch) {
474 assert(op->ublock() != NULL, "must have unordered successor");
475 is_unordered = true;
476 } else {
477 assert(op->code() == lir_branch, "just checking");
478 }
479
480 bool positive = false;
481 Assembler::Condition cond = Assembler::equal;
482 switch (op->cond()) {
483 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break;
484 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break;
485 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
486 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
487 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
488 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
489 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
490 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
491 default: ShouldNotReachHere();
492 }
493 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
494 int bi = Assembler::bi0(BOOL_RESULT, cond);
495 if (is_unordered) {
496 if (positive) {
497 if (op->ublock() == op->block()) {
498 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
499 }
500 } else {
501 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
502 }
503 }
504 __ bc_far_optimized(bo, bi, *L);
505 __ bind(done);
506 }
507 }
508
509
510 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
511 Bytecodes::Code code = op->bytecode();
512 LIR_Opr src = op->in_opr(),
513 dst = op->result_opr();
514
515 switch(code) {
516 case Bytecodes::_i2l: {
517 __ extsw(dst->as_register_lo(), src->as_register());
518 break;
519 }
520 case Bytecodes::_l2i: {
521 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
522 break;
523 }
524 case Bytecodes::_i2b: {
525 __ extsb(dst->as_register(), src->as_register());
526 break;
527 }
528 case Bytecodes::_i2c: {
529 __ clrldi(dst->as_register(), src->as_register(), 64-16);
530 break;
531 }
532 case Bytecodes::_i2s: {
533 __ extsh(dst->as_register(), src->as_register());
534 break;
535 }
536 case Bytecodes::_i2d:
537 case Bytecodes::_l2d: {
538 bool src_in_memory = !VM_Version::has_mtfprd();
539 FloatRegister rdst = dst->as_double_reg();
540 FloatRegister rsrc;
541 if (src_in_memory) {
542 rsrc = src->as_double_reg(); // via mem
543 } else {
544 // move src to dst register
545 if (code == Bytecodes::_i2d) {
546 __ mtfprwa(rdst, src->as_register());
547 } else {
548 __ mtfprd(rdst, src->as_register_lo());
549 }
550 rsrc = rdst;
551 }
552 __ fcfid(rdst, rsrc);
553 break;
554 }
555 case Bytecodes::_i2f:
556 case Bytecodes::_l2f: {
557 bool src_in_memory = !VM_Version::has_mtfprd();
558 FloatRegister rdst = dst->as_float_reg();
559 FloatRegister rsrc;
560 if (src_in_memory) {
561 rsrc = src->as_double_reg(); // via mem
562 } else {
563 // move src to dst register
564 if (code == Bytecodes::_i2f) {
565 __ mtfprwa(rdst, src->as_register());
566 } else {
567 __ mtfprd(rdst, src->as_register_lo());
568 }
569 rsrc = rdst;
570 }
571 if (VM_Version::has_fcfids()) {
572 __ fcfids(rdst, rsrc);
573 } else {
574 assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
575 __ fcfid(rdst, rsrc);
576 __ frsp(rdst, rdst);
577 }
578 break;
579 }
580 case Bytecodes::_f2d: {
581 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
582 break;
583 }
584 case Bytecodes::_d2f: {
585 __ frsp(dst->as_float_reg(), src->as_double_reg());
586 break;
587 }
588 case Bytecodes::_d2i:
589 case Bytecodes::_f2i: {
590 bool dst_in_memory = !VM_Version::has_mtfprd();
591 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
592 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
593 Label L;
594 // Result must be 0 if value is NaN; test by comparing value to itself.
595 __ fcmpu(CCR0, rsrc, rsrc);
596 if (dst_in_memory) {
597 __ li(R0, 0); // 0 in case of NAN
598 __ std(R0, addr.disp(), addr.base());
599 } else {
600 __ li(dst->as_register(), 0);
601 }
602 __ bso(CCR0, L);
603 __ fctiwz(rsrc, rsrc); // USE_KILL
604 if (dst_in_memory) {
605 __ stfd(rsrc, addr.disp(), addr.base());
606 } else {
607 __ mffprd(dst->as_register(), rsrc);
608 }
609 __ bind(L);
610 break;
611 }
612 case Bytecodes::_d2l:
613 case Bytecodes::_f2l: {
614 bool dst_in_memory = !VM_Version::has_mtfprd();
615 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
616 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
617 Label L;
618 // Result must be 0 if value is NaN; test by comparing value to itself.
619 __ fcmpu(CCR0, rsrc, rsrc);
620 if (dst_in_memory) {
621 __ li(R0, 0); // 0 in case of NAN
622 __ std(R0, addr.disp(), addr.base());
623 } else {
624 __ li(dst->as_register_lo(), 0);
625 }
626 __ bso(CCR0, L);
627 __ fctidz(rsrc, rsrc); // USE_KILL
628 if (dst_in_memory) {
629 __ stfd(rsrc, addr.disp(), addr.base());
630 } else {
631 __ mffprd(dst->as_register_lo(), rsrc);
632 }
633 __ bind(L);
634 break;
635 }
636
637 default: ShouldNotReachHere();
638 }
639 }
640
641
642 void LIR_Assembler::align_call(LIR_Code) {
643 // do nothing since all instructions are word aligned on ppc
644 }
645
646
647 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
648 int start_offset = __ offset();
649 // Put the entry point as a constant into the constant pool.
650 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none);
651 if (entry_point_toc_addr == NULL) {
652 bailout("const section overflow");
653 return false;
654 }
655 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
656
657 // Emit the trampoline stub which will be related to the branch-and-link below.
658 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
659 if (!stub) {
660 bailout("no space for trampoline stub");
661 return false;
662 }
663 return true;
664 }
665
666
667 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
668 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
669
670 bool success = emit_trampoline_stub_for_call(op->addr());
671 if (!success) { return; }
672
673 __ relocate(rtype);
674 // Note: At this point we do not have the address of the trampoline
675 // stub, and the entry point might be too far away for bl, so __ pc()
676 // serves as dummy and the bl will be patched later.
677 __ code()->set_insts_mark();
678 __ bl(__ pc());
679 add_call_info(code_offset(), op->info());
680 }
681
682
683 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
684 __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
685
686 // Virtual call relocation will point to ic load.
687 address virtual_call_meta_addr = __ pc();
688 // Load a clear inline cache.
689 AddressLiteral empty_ic((address) Universe::non_oop_word());
690 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
691 if (!success) {
692 bailout("const section overflow");
693 return;
694 }
695 // Call to fixup routine. Fixup routine uses ScopeDesc info
696 // to determine who we intended to call.
697 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
698
699 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
700 if (!success) { return; }
701
702 // Note: At this point we do not have the address of the trampoline
703 // stub, and the entry point might be too far away for bl, so __ pc()
704 // serves as dummy and the bl will be patched later.
705 __ bl(__ pc());
706 add_call_info(code_offset(), op->info());
707 }
708
709 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
710 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
711 __ null_check(addr, stub->entry());
712 append_code_stub(stub);
713 }
714
715
716 // Attention: caller must encode oop if needed
717 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
718 int store_offset;
719 if (!Assembler::is_simm16(offset)) {
720 // For offsets larger than a simm16 we setup the offset.
721 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
722 __ load_const_optimized(R0, offset);
723 store_offset = store(from_reg, base, R0, type, wide);
724 } else {
725 store_offset = code_offset();
726 switch (type) {
727 case T_BOOLEAN: // fall through
728 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break;
729 case T_CHAR :
730 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
731 case T_INT : __ stw(from_reg->as_register(), offset, base); break;
732 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break;
733 case T_ADDRESS:
734 case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
735 case T_ARRAY : // fall through
736 case T_OBJECT:
737 {
738 if (UseCompressedOops && !wide) {
739 // Encoding done in caller
740 __ stw(from_reg->as_register(), offset, base);
741 __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
742 } else {
743 __ std(from_reg->as_register(), offset, base);
744 __ verify_oop(from_reg->as_register(), FILE_AND_LINE);
745 }
746 break;
747 }
748 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
749 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
750 default : ShouldNotReachHere();
751 }
752 }
753 return store_offset;
754 }
755
756
757 // Attention: caller must encode oop if needed
758 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
759 int store_offset = code_offset();
760 switch (type) {
761 case T_BOOLEAN: // fall through
762 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break;
763 case T_CHAR :
764 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
765 case T_INT : __ stwx(from_reg->as_register(), base, disp); break;
766 case T_LONG :
767 #ifdef _LP64
768 __ stdx(from_reg->as_register_lo(), base, disp);
769 #else
770 Unimplemented();
771 #endif
772 break;
773 case T_ADDRESS:
774 __ stdx(from_reg->as_register(), base, disp);
775 break;
776 case T_ARRAY : // fall through
777 case T_OBJECT:
778 {
779 if (UseCompressedOops && !wide) {
780 // Encoding done in caller.
781 __ stwx(from_reg->as_register(), base, disp);
782 __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
783 } else {
784 __ stdx(from_reg->as_register(), base, disp);
785 __ verify_oop(from_reg->as_register(), FILE_AND_LINE); // kills R0
786 }
787 break;
788 }
789 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
790 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
791 default : ShouldNotReachHere();
792 }
793 return store_offset;
794 }
795
796
797 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
798 int load_offset;
799 if (!Assembler::is_simm16(offset)) {
800 // For offsets larger than a simm16 we setup the offset.
801 __ load_const_optimized(R0, offset);
802 load_offset = load(base, R0, to_reg, type, wide);
803 } else {
804 load_offset = code_offset();
805 switch(type) {
806 case T_BOOLEAN: // fall through
807 case T_BYTE : __ lbz(to_reg->as_register(), offset, base);
808 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
809 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break;
810 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break;
811 case T_INT : __ lwa(to_reg->as_register(), offset, base); break;
812 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break;
813 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
814 case T_ADDRESS:
815 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
816 __ lwz(to_reg->as_register(), offset, base);
817 __ decode_klass_not_null(to_reg->as_register());
818 } else {
819 __ ld(to_reg->as_register(), offset, base);
820 }
821 break;
822 case T_ARRAY : // fall through
823 case T_OBJECT:
824 {
825 if (UseCompressedOops && !wide) {
826 __ lwz(to_reg->as_register(), offset, base);
827 __ decode_heap_oop(to_reg->as_register());
828 } else {
829 __ ld(to_reg->as_register(), offset, base);
830 }
831 break;
832 }
833 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break;
834 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
835 default : ShouldNotReachHere();
836 }
837 }
838 return load_offset;
839 }
840
841
842 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
843 int load_offset = code_offset();
844 switch(type) {
845 case T_BOOLEAN: // fall through
846 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp);
847 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
848 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break;
849 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break;
850 case T_INT : __ lwax(to_reg->as_register(), base, disp); break;
851 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
852 case T_ARRAY : // fall through
853 case T_OBJECT:
854 {
855 if (UseCompressedOops && !wide) {
856 __ lwzx(to_reg->as_register(), base, disp);
857 __ decode_heap_oop(to_reg->as_register());
858 } else {
859 __ ldx(to_reg->as_register(), base, disp);
860 }
861 break;
862 }
863 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break;
864 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
865 case T_LONG :
866 #ifdef _LP64
867 __ ldx(to_reg->as_register_lo(), base, disp);
868 #else
869 Unimplemented();
870 #endif
871 break;
872 default : ShouldNotReachHere();
873 }
874 return load_offset;
875 }
876
877
878 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
879 LIR_Const* c = src->as_constant_ptr();
880 Register src_reg = R0;
881 switch (c->type()) {
882 case T_INT:
883 case T_FLOAT: {
884 int value = c->as_jint_bits();
885 __ load_const_optimized(src_reg, value);
886 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
887 __ stw(src_reg, addr.disp(), addr.base());
888 break;
889 }
890 case T_ADDRESS: {
891 int value = c->as_jint_bits();
892 __ load_const_optimized(src_reg, value);
893 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
894 __ std(src_reg, addr.disp(), addr.base());
895 break;
896 }
897 case T_OBJECT: {
898 jobject2reg(c->as_jobject(), src_reg);
899 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
900 __ std(src_reg, addr.disp(), addr.base());
901 break;
902 }
903 case T_LONG:
904 case T_DOUBLE: {
905 int value = c->as_jlong_bits();
906 __ load_const_optimized(src_reg, value);
907 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
908 __ std(src_reg, addr.disp(), addr.base());
909 break;
910 }
911 default:
912 Unimplemented();
913 }
914 }
915
916
917 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
918 LIR_Const* c = src->as_constant_ptr();
919 LIR_Address* addr = dest->as_address_ptr();
920 Register base = addr->base()->as_pointer_register();
921 LIR_Opr tmp = LIR_OprFact::illegalOpr;
922 int offset = -1;
923 // Null check for large offsets in LIRGenerator::do_StoreField.
924 bool needs_explicit_null_check = !ImplicitNullChecks;
925
926 if (info != NULL && needs_explicit_null_check) {
927 explicit_null_check(base, info);
928 }
929
930 switch (c->type()) {
931 case T_FLOAT: type = T_INT;
932 case T_INT:
933 case T_ADDRESS: {
934 tmp = FrameMap::R0_opr;
935 __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
936 break;
937 }
938 case T_DOUBLE: type = T_LONG;
939 case T_LONG: {
940 tmp = FrameMap::R0_long_opr;
941 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
942 break;
943 }
944 case T_OBJECT: {
945 tmp = FrameMap::R0_opr;
946 if (UseCompressedOops && !wide && c->as_jobject() != NULL) {
947 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
948 __ lis(R0, oop_addr.value() >> 16); // Don't care about sign extend (will use stw).
949 __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
950 __ ori(R0, R0, oop_addr.value() & 0xffff);
951 } else {
952 jobject2reg(c->as_jobject(), R0);
953 }
954 break;
955 }
956 default:
957 Unimplemented();
958 }
959
960 // Handle either reg+reg or reg+disp address.
961 if (addr->index()->is_valid()) {
962 assert(addr->disp() == 0, "must be zero");
963 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
964 } else {
965 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
966 offset = store(tmp, base, addr->disp(), type, wide, false);
967 }
968
969 if (info != NULL) {
970 assert(offset != -1, "offset should've been set");
971 if (!needs_explicit_null_check) {
972 add_debug_info_for_null_check(offset, info);
973 }
974 }
975 }
976
977
978 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
979 LIR_Const* c = src->as_constant_ptr();
980 LIR_Opr to_reg = dest;
981
982 switch (c->type()) {
983 case T_INT: {
984 assert(patch_code == lir_patch_none, "no patching handled here");
985 __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
986 break;
987 }
988 case T_ADDRESS: {
989 assert(patch_code == lir_patch_none, "no patching handled here");
990 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ...
991 break;
992 }
993 case T_LONG: {
994 assert(patch_code == lir_patch_none, "no patching handled here");
995 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
996 break;
997 }
998
999 case T_OBJECT: {
1000 if (patch_code == lir_patch_none) {
1001 jobject2reg(c->as_jobject(), to_reg->as_register());
1002 } else {
1003 jobject2reg_with_patching(to_reg->as_register(), info);
1004 }
1005 break;
1006 }
1007
1008 case T_METADATA:
1009 {
1010 if (patch_code == lir_patch_none) {
1011 metadata2reg(c->as_metadata(), to_reg->as_register());
1012 } else {
1013 klass2reg_with_patching(to_reg->as_register(), info);
1014 }
1015 }
1016 break;
1017
1018 case T_FLOAT:
1019 {
1020 if (to_reg->is_single_fpu()) {
1021 address const_addr = __ float_constant(c->as_jfloat());
1022 if (const_addr == NULL) {
1023 bailout("const section overflow");
1024 break;
1025 }
1026 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1027 __ relocate(rspec);
1028 __ load_const(R0, const_addr);
1029 __ lfsx(to_reg->as_float_reg(), R0);
1030 } else {
1031 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1032 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1033 }
1034 }
1035 break;
1036
1037 case T_DOUBLE:
1038 {
1039 if (to_reg->is_double_fpu()) {
1040 address const_addr = __ double_constant(c->as_jdouble());
1041 if (const_addr == NULL) {
1042 bailout("const section overflow");
1043 break;
1044 }
1045 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1046 __ relocate(rspec);
1047 __ load_const(R0, const_addr);
1048 __ lfdx(to_reg->as_double_reg(), R0);
1049 } else {
1050 assert(to_reg->is_double_cpu(), "Must be a long register.");
1051 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1052 }
1053 }
1054 break;
1055
1056 default:
1057 ShouldNotReachHere();
1058 }
1059 }
1060
1061
1062 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1063 Unimplemented(); return Address();
1064 }
1065
1066
1067 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1068 if (addr->index()->is_illegal()) {
1069 return (RegisterOrConstant)(addr->disp());
1070 } else {
1071 return (RegisterOrConstant)(addr->index()->as_pointer_register());
1072 }
1073 }
1074
1075
1076 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1077 const Register tmp = R0;
1078 switch (type) {
1079 case T_INT:
1080 case T_FLOAT: {
1081 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1082 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1083 __ lwz(tmp, from.disp(), from.base());
1084 __ stw(tmp, to.disp(), to.base());
1085 break;
1086 }
1087 case T_ADDRESS:
1088 case T_OBJECT: {
1089 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1090 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1091 __ ld(tmp, from.disp(), from.base());
1092 __ std(tmp, to.disp(), to.base());
1093 break;
1094 }
1095 case T_LONG:
1096 case T_DOUBLE: {
1097 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1098 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1099 __ ld(tmp, from.disp(), from.base());
1100 __ std(tmp, to.disp(), to.base());
1101 break;
1102 }
1103
1104 default:
1105 ShouldNotReachHere();
1106 }
1107 }
1108
1109
1110 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1111 Unimplemented(); return Address();
1112 }
1113
1114
1115 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1116 Unimplemented(); return Address();
1117 }
1118
1119
1120 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1121 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1122
1123 assert(type != T_METADATA, "load of metadata ptr not supported");
1124 LIR_Address* addr = src_opr->as_address_ptr();
1125 LIR_Opr to_reg = dest;
1126
1127 Register src = addr->base()->as_pointer_register();
1128 Register disp_reg = noreg;
1129 int disp_value = addr->disp();
1130 bool needs_patching = (patch_code != lir_patch_none);
1131 // null check for large offsets in LIRGenerator::do_LoadField
1132 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1133
1134 if (info != NULL && needs_explicit_null_check) {
1135 explicit_null_check(src, info);
1136 }
1137
1138 if (addr->base()->type() == T_OBJECT) {
1139 __ verify_oop(src, FILE_AND_LINE);
1140 }
1141
1142 PatchingStub* patch = NULL;
1143 if (needs_patching) {
1144 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1145 assert(!to_reg->is_double_cpu() ||
1146 patch_code == lir_patch_none ||
1147 patch_code == lir_patch_normal, "patching doesn't match register");
1148 }
1149
1150 if (addr->index()->is_illegal()) {
1151 if (!Assembler::is_simm16(disp_value)) {
1152 if (needs_patching) {
1153 __ load_const32(R0, 0); // patchable int
1154 } else {
1155 __ load_const_optimized(R0, disp_value);
1156 }
1157 disp_reg = R0;
1158 }
1159 } else {
1160 disp_reg = addr->index()->as_pointer_register();
1161 assert(disp_value == 0, "can't handle 3 operand addresses");
1162 }
1163
1164 // Remember the offset of the load. The patching_epilog must be done
1165 // before the call to add_debug_info, otherwise the PcDescs don't get
1166 // entered in increasing order.
1167 int offset;
1168
1169 if (disp_reg == noreg) {
1170 assert(Assembler::is_simm16(disp_value), "should have set this up");
1171 offset = load(src, disp_value, to_reg, type, wide, unaligned);
1172 } else {
1173 assert(!unaligned, "unexpected");
1174 offset = load(src, disp_reg, to_reg, type, wide);
1175 }
1176
1177 if (patch != NULL) {
1178 patching_epilog(patch, patch_code, src, info);
1179 }
1180 if (info != NULL && !needs_explicit_null_check) {
1181 add_debug_info_for_null_check(offset, info);
1182 }
1183 }
1184
1185
1186 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1187 Address addr;
1188 if (src->is_single_word()) {
1189 addr = frame_map()->address_for_slot(src->single_stack_ix());
1190 } else if (src->is_double_word()) {
1191 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1192 }
1193
1194 bool unaligned = addr.disp() % 8 != 0;
1195 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1196 }
1197
1198
1199 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1200 Address addr;
1201 if (dest->is_single_word()) {
1202 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1203 } else if (dest->is_double_word()) {
1204 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1205 }
1206 bool unaligned = addr.disp() % 8 != 0;
1207 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1208 }
1209
1210
1211 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1212 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1213 if (from_reg->is_double_fpu()) {
1214 // double to double moves
1215 assert(to_reg->is_double_fpu(), "should match");
1216 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1217 } else {
1218 // float to float moves
1219 assert(to_reg->is_single_fpu(), "should match");
1220 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1221 }
1222 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1223 if (from_reg->is_double_cpu()) {
1224 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1225 } else if (to_reg->is_double_cpu()) {
1226 // int to int moves
1227 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1228 } else {
1229 // int to int moves
1230 __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1231 }
1232 } else {
1233 ShouldNotReachHere();
1234 }
1235 if (is_reference_type(to_reg->type())) {
1236 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1237 }
1238 }
1239
1240
1241 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1242 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1243 bool wide, bool unaligned) {
1244 assert(type != T_METADATA, "store of metadata ptr not supported");
1245 LIR_Address* addr = dest->as_address_ptr();
1246
1247 Register src = addr->base()->as_pointer_register();
1248 Register disp_reg = noreg;
1249 int disp_value = addr->disp();
1250 bool needs_patching = (patch_code != lir_patch_none);
1251 bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1252 CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1253 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1254 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1255 // Null check for large offsets in LIRGenerator::do_StoreField.
1256 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1257
1258 if (info != NULL && needs_explicit_null_check) {
1259 explicit_null_check(src, info);
1260 }
1261
1262 if (addr->base()->is_oop_register()) {
1263 __ verify_oop(src, FILE_AND_LINE);
1264 }
1265
1266 PatchingStub* patch = NULL;
1267 if (needs_patching) {
1268 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1269 assert(!from_reg->is_double_cpu() ||
1270 patch_code == lir_patch_none ||
1271 patch_code == lir_patch_normal, "patching doesn't match register");
1272 }
1273
1274 if (addr->index()->is_illegal()) {
1275 if (load_disp) {
1276 disp_reg = use_R29 ? R29_TOC : R0;
1277 if (needs_patching) {
1278 __ load_const32(disp_reg, 0); // patchable int
1279 } else {
1280 __ load_const_optimized(disp_reg, disp_value);
1281 }
1282 }
1283 } else {
1284 disp_reg = addr->index()->as_pointer_register();
1285 assert(disp_value == 0, "can't handle 3 operand addresses");
1286 }
1287
1288 // remember the offset of the store. The patching_epilog must be done
1289 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1290 // entered in increasing order.
1291 int offset;
1292
1293 if (compress_oop) {
1294 Register co = __ encode_heap_oop(R0, from_reg->as_register());
1295 from_reg = FrameMap::as_opr(co);
1296 }
1297
1298 if (disp_reg == noreg) {
1299 assert(Assembler::is_simm16(disp_value), "should have set this up");
1300 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1301 } else {
1302 assert(!unaligned, "unexpected");
1303 offset = store(from_reg, src, disp_reg, type, wide);
1304 }
1305
1306 if (use_R29) {
1307 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1308 }
1309
1310 if (patch != NULL) {
1311 patching_epilog(patch, patch_code, src, info);
1312 }
1313
1314 if (info != NULL && !needs_explicit_null_check) {
1315 add_debug_info_for_null_check(offset, info);
1316 }
1317 }
1318
1319
1320 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1321 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone().
1322 const Register temp = R12;
1323
1324 // Pop the stack before the safepoint code.
1325 int frame_size = initial_frame_size_in_bytes();
1326 if (Assembler::is_simm(frame_size, 16)) {
1327 __ addi(R1_SP, R1_SP, frame_size);
1328 } else {
1329 __ pop_frame();
1330 }
1331
1332 // Restore return pc relative to callers' sp.
1333 __ ld(return_pc, _abi0(lr), R1_SP);
1334 // Move return pc to LR.
1335 __ mtlr(return_pc);
1336
1337 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1338 __ reserved_stack_check(return_pc);
1339 }
1340
1341 // We need to mark the code position where the load from the safepoint
1342 // polling page was emitted as relocInfo::poll_return_type here.
1343 if (!UseSIGTRAP) {
1344 code_stub->set_safepoint_offset(__ offset());
1345 __ relocate(relocInfo::poll_return_type);
1346 }
1347 __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */);
1348
1349 // Return.
1350 __ blr();
1351 }
1352
1353
1354 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1355 const Register poll_addr = tmp->as_register();
1356 __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1357 if (info != NULL) {
1358 add_debug_info_for_branch(info);
1359 }
1360 int offset = __ offset();
1361 __ relocate(relocInfo::poll_type);
1362 __ load_from_polling_page(poll_addr);
1363
1364 return offset;
1365 }
1366
1367
1368 void LIR_Assembler::emit_static_call_stub() {
1369 address call_pc = __ pc();
1370 address stub = __ start_a_stub(static_call_stub_size());
1371 if (stub == NULL) {
1372 bailout("static call stub overflow");
1373 return;
1374 }
1375
1376 // For java_to_interp stubs we use R11_scratch1 as scratch register
1377 // and in call trampoline stubs we use R12_scratch2. This way we
1378 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1379 const Register reg_scratch = R11_scratch1;
1380
1381 // Create a static stub relocation which relates this stub
1382 // with the call instruction at insts_call_instruction_offset in the
1383 // instructions code-section.
1384 int start = __ offset();
1385 __ relocate(static_stub_Relocation::spec(call_pc));
1386
1387 // Now, create the stub's code:
1388 // - load the TOC
1389 // - load the inline cache oop from the constant pool
1390 // - load the call target from the constant pool
1391 // - call
1392 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1393 AddressLiteral ic = __ allocate_metadata_address((Metadata *)NULL);
1394 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1395
1396 if (ReoptimizeCallSequences) {
1397 __ b64_patchable((address)-1, relocInfo::none);
1398 } else {
1399 AddressLiteral a((address)-1);
1400 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1401 __ mtctr(reg_scratch);
1402 __ bctr();
1403 }
1404 if (!success) {
1405 bailout("const section overflow");
1406 return;
1407 }
1408
1409 assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1410 __ end_a_stub();
1411 }
1412
1413
1414 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1415 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1416 if (opr1->is_single_fpu()) {
1417 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1418 } else if (opr1->is_double_fpu()) {
1419 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1420 } else if (opr1->is_single_cpu()) {
1421 if (opr2->is_constant()) {
1422 switch (opr2->as_constant_ptr()->type()) {
1423 case T_INT:
1424 {
1425 jint con = opr2->as_constant_ptr()->as_jint();
1426 if (unsigned_comp) {
1427 if (Assembler::is_uimm(con, 16)) {
1428 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1429 } else {
1430 __ load_const_optimized(R0, con);
1431 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1432 }
1433 } else {
1434 if (Assembler::is_simm(con, 16)) {
1435 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1436 } else {
1437 __ load_const_optimized(R0, con);
1438 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1439 }
1440 }
1441 }
1442 break;
1443
1444 case T_OBJECT:
1445 // There are only equal/notequal comparisons on objects.
1446 {
1447 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1448 jobject con = opr2->as_constant_ptr()->as_jobject();
1449 if (con == NULL) {
1450 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1451 } else {
1452 jobject2reg(con, R0);
1453 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1454 }
1455 }
1456 break;
1457
1458 case T_METADATA:
1459 // We only need, for now, comparison with NULL for metadata.
1460 {
1461 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1462 Metadata* p = opr2->as_constant_ptr()->as_metadata();
1463 if (p == NULL) {
1464 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1465 } else {
1466 ShouldNotReachHere();
1467 }
1468 }
1469 break;
1470
1471 default:
1472 ShouldNotReachHere();
1473 break;
1474 }
1475 } else {
1476 assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1477 if (is_reference_type(opr1->type())) {
1478 // There are only equal/notequal comparisons on objects.
1479 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1480 __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1481 } else {
1482 if (unsigned_comp) {
1483 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1484 } else {
1485 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1486 }
1487 }
1488 }
1489 } else if (opr1->is_double_cpu()) {
1490 if (opr2->is_constant()) {
1491 jlong con = opr2->as_constant_ptr()->as_jlong();
1492 if (unsigned_comp) {
1493 if (Assembler::is_uimm(con, 16)) {
1494 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1495 } else {
1496 __ load_const_optimized(R0, con);
1497 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1498 }
1499 } else {
1500 if (Assembler::is_simm(con, 16)) {
1501 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1502 } else {
1503 __ load_const_optimized(R0, con);
1504 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1505 }
1506 }
1507 } else if (opr2->is_register()) {
1508 if (unsigned_comp) {
1509 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1510 } else {
1511 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1512 }
1513 } else {
1514 ShouldNotReachHere();
1515 }
1516 } else {
1517 ShouldNotReachHere();
1518 }
1519 }
1520
1521
1522 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1523 const Register Rdst = dst->as_register();
1524 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1525 bool is_unordered_less = (code == lir_ucmp_fd2i);
1526 if (left->is_single_fpu()) {
1527 __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg());
1528 } else if (left->is_double_fpu()) {
1529 __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg());
1530 } else {
1531 ShouldNotReachHere();
1532 }
1533 __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1
1534 } else if (code == lir_cmp_l2i) {
1535 __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo());
1536 __ set_cmp3(Rdst); // set result as follows: <: -1, =: 0, >: 1
1537 } else {
1538 ShouldNotReachHere();
1539 }
1540 }
1541
1542
1543 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1544 if (src->is_constant()) {
1545 lasm->const2reg(src, dst, lir_patch_none, NULL);
1546 } else if (src->is_register()) {
1547 lasm->reg2reg(src, dst);
1548 } else if (src->is_stack()) {
1549 lasm->stack2reg(src, dst, dst->type());
1550 } else {
1551 ShouldNotReachHere();
1552 }
1553 }
1554
1555
1556 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1557 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1558 load_to_reg(this, opr1, result); // Condition doesn't matter.
1559 return;
1560 }
1561
1562 bool positive = false;
1563 Assembler::Condition cond = Assembler::equal;
1564 switch (condition) {
1565 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break;
1566 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break;
1567 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
1568 case lir_cond_belowEqual:
1569 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
1570 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
1571 case lir_cond_aboveEqual:
1572 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
1573 default: ShouldNotReachHere();
1574 }
1575
1576 // Try to use isel on >=Power7.
1577 if (VM_Version::has_isel() && result->is_cpu_register()) {
1578 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1579 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1580
1581 // We can use result_reg to load one operand if not already in register.
1582 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1583 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1584
1585 if (first != second) {
1586 if (!o1_is_reg) {
1587 load_to_reg(this, opr1, result);
1588 }
1589
1590 if (!o2_is_reg) {
1591 load_to_reg(this, opr2, result);
1592 }
1593
1594 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1595 return;
1596 }
1597 } // isel
1598
1599 load_to_reg(this, opr1, result);
1600
1601 Label skip;
1602 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1603 int bi = Assembler::bi0(BOOL_RESULT, cond);
1604 __ bc(bo, bi, skip);
1605
1606 load_to_reg(this, opr2, result);
1607 __ bind(skip);
1608 }
1609
1610
1611 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1612 CodeEmitInfo* info, bool pop_fpu_stack) {
1613 assert(info == NULL, "unused on this code path");
1614 assert(left->is_register(), "wrong items state");
1615 assert(dest->is_register(), "wrong items state");
1616
1617 if (right->is_register()) {
1618 if (dest->is_float_kind()) {
1619
1620 FloatRegister lreg, rreg, res;
1621 if (right->is_single_fpu()) {
1622 lreg = left->as_float_reg();
1623 rreg = right->as_float_reg();
1624 res = dest->as_float_reg();
1625 switch (code) {
1626 case lir_add: __ fadds(res, lreg, rreg); break;
1627 case lir_sub: __ fsubs(res, lreg, rreg); break;
1628 case lir_mul: __ fmuls(res, lreg, rreg); break;
1629 case lir_div: __ fdivs(res, lreg, rreg); break;
1630 default: ShouldNotReachHere();
1631 }
1632 } else {
1633 lreg = left->as_double_reg();
1634 rreg = right->as_double_reg();
1635 res = dest->as_double_reg();
1636 switch (code) {
1637 case lir_add: __ fadd(res, lreg, rreg); break;
1638 case lir_sub: __ fsub(res, lreg, rreg); break;
1639 case lir_mul: __ fmul(res, lreg, rreg); break;
1640 case lir_div: __ fdiv(res, lreg, rreg); break;
1641 default: ShouldNotReachHere();
1642 }
1643 }
1644
1645 } else if (dest->is_double_cpu()) {
1646
1647 Register dst_lo = dest->as_register_lo();
1648 Register op1_lo = left->as_pointer_register();
1649 Register op2_lo = right->as_pointer_register();
1650
1651 switch (code) {
1652 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1653 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1654 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1655 default: ShouldNotReachHere();
1656 }
1657 } else {
1658 assert (right->is_single_cpu(), "Just Checking");
1659
1660 Register lreg = left->as_register();
1661 Register res = dest->as_register();
1662 Register rreg = right->as_register();
1663 switch (code) {
1664 case lir_add: __ add (res, lreg, rreg); break;
1665 case lir_sub: __ sub (res, lreg, rreg); break;
1666 case lir_mul: __ mullw(res, lreg, rreg); break;
1667 default: ShouldNotReachHere();
1668 }
1669 }
1670 } else {
1671 assert (right->is_constant(), "must be constant");
1672
1673 if (dest->is_single_cpu()) {
1674 Register lreg = left->as_register();
1675 Register res = dest->as_register();
1676 int simm16 = right->as_constant_ptr()->as_jint();
1677
1678 switch (code) {
1679 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1680 simm16 = -simm16;
1681 case lir_add: if (res == lreg && simm16 == 0) break;
1682 __ addi(res, lreg, simm16); break;
1683 case lir_mul: if (res == lreg && simm16 == 1) break;
1684 __ mulli(res, lreg, simm16); break;
1685 default: ShouldNotReachHere();
1686 }
1687 } else {
1688 Register lreg = left->as_pointer_register();
1689 Register res = dest->as_register_lo();
1690 long con = right->as_constant_ptr()->as_jlong();
1691 assert(Assembler::is_simm16(con), "must be simm16");
1692
1693 switch (code) {
1694 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long
1695 con = -con;
1696 case lir_add: if (res == lreg && con == 0) break;
1697 __ addi(res, lreg, (int)con); break;
1698 case lir_mul: if (res == lreg && con == 1) break;
1699 __ mulli(res, lreg, (int)con); break;
1700 default: ShouldNotReachHere();
1701 }
1702 }
1703 }
1704 }
1705
1706
1707 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1708 switch (code) {
1709 case lir_sqrt: {
1710 __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1711 break;
1712 }
1713 case lir_abs: {
1714 __ fabs(dest->as_double_reg(), value->as_double_reg());
1715 break;
1716 }
1717 default: {
1718 ShouldNotReachHere();
1719 break;
1720 }
1721 }
1722 }
1723
1724
1725 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1726 if (right->is_constant()) { // see do_LogicOp
1727 long uimm;
1728 Register d, l;
1729 if (dest->is_single_cpu()) {
1730 uimm = right->as_constant_ptr()->as_jint();
1731 d = dest->as_register();
1732 l = left->as_register();
1733 } else {
1734 uimm = right->as_constant_ptr()->as_jlong();
1735 d = dest->as_register_lo();
1736 l = left->as_register_lo();
1737 }
1738 long uimms = (unsigned long)uimm >> 16,
1739 uimmss = (unsigned long)uimm >> 32;
1740
1741 switch (code) {
1742 case lir_logic_and:
1743 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2(uimm)) {
1744 __ andi(d, l, uimm); // special cases
1745 } else if (uimms != 0) { __ andis_(d, l, uimms); }
1746 else { __ andi_(d, l, uimm); }
1747 break;
1748
1749 case lir_logic_or:
1750 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1751 else { __ ori(d, l, uimm); }
1752 break;
1753
1754 case lir_logic_xor:
1755 if (uimm == -1) { __ nand(d, l, l); } // special case
1756 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1757 else { __ xori(d, l, uimm); }
1758 break;
1759
1760 default: ShouldNotReachHere();
1761 }
1762 } else {
1763 assert(right->is_register(), "right should be in register");
1764
1765 if (dest->is_single_cpu()) {
1766 switch (code) {
1767 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1768 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1769 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1770 default: ShouldNotReachHere();
1771 }
1772 } else {
1773 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1774 left->as_register_lo();
1775 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1776 right->as_register_lo();
1777
1778 switch (code) {
1779 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1780 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break;
1781 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1782 default: ShouldNotReachHere();
1783 }
1784 }
1785 }
1786 }
1787
1788
1789 int LIR_Assembler::shift_amount(BasicType t) {
1790 int elem_size = type2aelembytes(t);
1791 switch (elem_size) {
1792 case 1 : return 0;
1793 case 2 : return 1;
1794 case 4 : return 2;
1795 case 8 : return 3;
1796 }
1797 ShouldNotReachHere();
1798 return -1;
1799 }
1800
1801
1802 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1803 info->add_register_oop(exceptionOop);
1804
1805 // Reuse the debug info from the safepoint poll for the throw op itself.
1806 address pc_for_athrow = __ pc();
1807 int pc_for_athrow_offset = __ offset();
1808 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1809 //__ relocate(rspec);
1810 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1811 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1812 add_call_info(pc_for_athrow_offset, info); // for exception handler
1813
1814 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1815 : Runtime1::handle_exception_nofpu_id);
1816 //__ load_const_optimized(R0, stub);
1817 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1818 __ mtctr(R0);
1819 __ bctr();
1820 }
1821
1822
1823 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1824 // Note: Not used with EnableDebuggingOnDemand.
1825 assert(exceptionOop->as_register() == R3, "should match");
1826 __ b(_unwind_handler_entry);
1827 }
1828
1829
1830 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1831 Register src = op->src()->as_register();
1832 Register dst = op->dst()->as_register();
1833 Register src_pos = op->src_pos()->as_register();
1834 Register dst_pos = op->dst_pos()->as_register();
1835 Register length = op->length()->as_register();
1836 Register tmp = op->tmp()->as_register();
1837 Register tmp2 = R0;
1838
1839 int flags = op->flags();
1840 ciArrayKlass* default_type = op->expected_type();
1841 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1842 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1843
1844 // Set up the arraycopy stub information.
1845 ArrayCopyStub* stub = op->stub();
1846 const int frame_resize = frame::abi_reg_args_size - sizeof(frame::jit_abi); // C calls need larger frame.
1847
1848 // Always do stub if no type information is available. It's ok if
1849 // the known type isn't loaded since the code sanity checks
1850 // in debug mode and the type isn't required when we know the exact type
1851 // also check that the type is an array type.
1852 if (op->expected_type() == NULL) {
1853 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1854 length->is_nonvolatile(), "must preserve");
1855 address copyfunc_addr = StubRoutines::generic_arraycopy();
1856 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
1857
1858 // 3 parms are int. Convert to long.
1859 __ mr(R3_ARG1, src);
1860 __ extsw(R4_ARG2, src_pos);
1861 __ mr(R5_ARG3, dst);
1862 __ extsw(R6_ARG4, dst_pos);
1863 __ extsw(R7_ARG5, length);
1864
1865 #ifndef PRODUCT
1866 if (PrintC1Statistics) {
1867 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1868 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1869 __ lwz(R11_scratch1, simm16_offs, tmp);
1870 __ addi(R11_scratch1, R11_scratch1, 1);
1871 __ stw(R11_scratch1, simm16_offs, tmp);
1872 }
1873 #endif
1874 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
1875
1876 __ nand(tmp, R3_RET, R3_RET);
1877 __ subf(length, tmp, length);
1878 __ add(src_pos, tmp, src_pos);
1879 __ add(dst_pos, tmp, dst_pos);
1880
1881 __ cmpwi(CCR0, R3_RET, 0);
1882 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry());
1883 __ bind(*stub->continuation());
1884 return;
1885 }
1886
1887 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1888 Label cont, slow, copyfunc;
1889
1890 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1891 LIR_OpArrayCopy::dst_null_check |
1892 LIR_OpArrayCopy::src_pos_positive_check |
1893 LIR_OpArrayCopy::dst_pos_positive_check |
1894 LIR_OpArrayCopy::length_positive_check);
1895
1896 // Use only one conditional branch for simple checks.
1897 if (simple_check_flag_set) {
1898 ConditionRegister combined_check = CCR1, tmp_check = CCR1;
1899
1900 // Make sure src and dst are non-null.
1901 if (flags & LIR_OpArrayCopy::src_null_check) {
1902 __ cmpdi(combined_check, src, 0);
1903 tmp_check = CCR0;
1904 }
1905
1906 if (flags & LIR_OpArrayCopy::dst_null_check) {
1907 __ cmpdi(tmp_check, dst, 0);
1908 if (tmp_check != combined_check) {
1909 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1910 }
1911 tmp_check = CCR0;
1912 }
1913
1914 // Clear combined_check.eq if not already used.
1915 if (tmp_check == combined_check) {
1916 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1917 tmp_check = CCR0;
1918 }
1919
1920 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1921 // Test src_pos register.
1922 __ cmpwi(tmp_check, src_pos, 0);
1923 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1924 }
1925
1926 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1927 // Test dst_pos register.
1928 __ cmpwi(tmp_check, dst_pos, 0);
1929 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1930 }
1931
1932 if (flags & LIR_OpArrayCopy::length_positive_check) {
1933 // Make sure length isn't negative.
1934 __ cmpwi(tmp_check, length, 0);
1935 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1936 }
1937
1938 __ beq(combined_check, slow);
1939 }
1940
1941 // If the compiler was not able to prove that exact type of the source or the destination
1942 // of the arraycopy is an array type, check at runtime if the source or the destination is
1943 // an instance type.
1944 if (flags & LIR_OpArrayCopy::type_check) {
1945 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1946 __ load_klass(tmp, dst);
1947 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1948 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1949 __ bge(CCR0, slow);
1950 }
1951
1952 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1953 __ load_klass(tmp, src);
1954 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1955 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1956 __ bge(CCR0, slow);
1957 }
1958 }
1959
1960 // Higher 32bits must be null.
1961 __ extsw(length, length);
1962
1963 __ extsw(src_pos, src_pos);
1964 if (flags & LIR_OpArrayCopy::src_range_check) {
1965 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1966 __ add(tmp, length, src_pos);
1967 __ cmpld(CCR0, tmp2, tmp);
1968 __ ble(CCR0, slow);
1969 }
1970
1971 __ extsw(dst_pos, dst_pos);
1972 if (flags & LIR_OpArrayCopy::dst_range_check) {
1973 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1974 __ add(tmp, length, dst_pos);
1975 __ cmpld(CCR0, tmp2, tmp);
1976 __ ble(CCR0, slow);
1977 }
1978
1979 int shift = shift_amount(basic_type);
1980
1981 if (!(flags & LIR_OpArrayCopy::type_check)) {
1982 __ b(cont);
1983 } else {
1984 // We don't know the array types are compatible.
1985 if (basic_type != T_OBJECT) {
1986 // Simple test for basic type arrays.
1987 if (UseCompressedClassPointers) {
1988 // We don't need decode because we just need to compare.
1989 __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src);
1990 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1991 __ cmpw(CCR0, tmp, tmp2);
1992 } else {
1993 __ ld(tmp, oopDesc::klass_offset_in_bytes(), src);
1994 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1995 __ cmpd(CCR0, tmp, tmp2);
1996 }
1997 __ beq(CCR0, cont);
1998 } else {
1999 // For object arrays, if src is a sub class of dst then we can
2000 // safely do the copy.
2001 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2002
2003 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
2004 assert_different_registers(tmp, tmp2, sub_klass, super_klass);
2005
2006 __ load_klass(sub_klass, src);
2007 __ load_klass(super_klass, dst);
2008
2009 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
2010 &cont, copyfunc_addr != NULL ? ©func : &slow, NULL);
2011
2012 address slow_stc = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2013 //__ load_const_optimized(tmp, slow_stc, tmp2);
2014 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
2015 __ mtctr(tmp);
2016 __ bctrl(); // sets CR0
2017 __ beq(CCR0, cont);
2018
2019 if (copyfunc_addr != NULL) { // Use stub if available.
2020 __ bind(copyfunc);
2021 // Src is not a sub class of dst so we have to do a
2022 // per-element check.
2023 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2024 if ((flags & mask) != mask) {
2025 assert(flags & mask, "one of the two should be known to be an object array");
2026
2027 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2028 __ load_klass(tmp, src);
2029 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2030 __ load_klass(tmp, dst);
2031 }
2032
2033 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2034
2035 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2036 __ load_const_optimized(tmp, objArray_lh);
2037 __ cmpw(CCR0, tmp, tmp2);
2038 __ bne(CCR0, slow);
2039 }
2040
2041 Register src_ptr = R3_ARG1;
2042 Register dst_ptr = R4_ARG2;
2043 Register len = R5_ARG3;
2044 Register chk_off = R6_ARG4;
2045 Register super_k = R7_ARG5;
2046
2047 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2048 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2049 if (shift == 0) {
2050 __ add(src_ptr, src_pos, src_ptr);
2051 __ add(dst_ptr, dst_pos, dst_ptr);
2052 } else {
2053 __ sldi(tmp, src_pos, shift);
2054 __ sldi(tmp2, dst_pos, shift);
2055 __ add(src_ptr, tmp, src_ptr);
2056 __ add(dst_ptr, tmp2, dst_ptr);
2057 }
2058
2059 __ load_klass(tmp, dst);
2060 __ mr(len, length);
2061
2062 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2063 __ ld(super_k, ek_offset, tmp);
2064
2065 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2066 __ lwz(chk_off, sco_offset, super_k);
2067
2068 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
2069
2070 #ifndef PRODUCT
2071 if (PrintC1Statistics) {
2072 Label failed;
2073 __ cmpwi(CCR0, R3_RET, 0);
2074 __ bne(CCR0, failed);
2075 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2076 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2077 __ lwz(R11_scratch1, simm16_offs, tmp);
2078 __ addi(R11_scratch1, R11_scratch1, 1);
2079 __ stw(R11_scratch1, simm16_offs, tmp);
2080 __ bind(failed);
2081 }
2082 #endif
2083
2084 __ nand(tmp, R3_RET, R3_RET);
2085 __ cmpwi(CCR0, R3_RET, 0);
2086 __ beq(CCR0, *stub->continuation());
2087
2088 #ifndef PRODUCT
2089 if (PrintC1Statistics) {
2090 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2091 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2092 __ lwz(R11_scratch1, simm16_offs, tmp);
2093 __ addi(R11_scratch1, R11_scratch1, 1);
2094 __ stw(R11_scratch1, simm16_offs, tmp);
2095 }
2096 #endif
2097
2098 __ subf(length, tmp, length);
2099 __ add(src_pos, tmp, src_pos);
2100 __ add(dst_pos, tmp, dst_pos);
2101 }
2102 }
2103 }
2104 __ bind(slow);
2105 __ b(*stub->entry());
2106 __ bind(cont);
2107
2108 #ifdef ASSERT
2109 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2110 // Sanity check the known type with the incoming class. For the
2111 // primitive case the types must match exactly with src.klass and
2112 // dst.klass each exactly matching the default type. For the
2113 // object array case, if no type check is needed then either the
2114 // dst type is exactly the expected type and the src type is a
2115 // subtype which we can't check or src is the same array as dst
2116 // but not necessarily exactly of type default_type.
2117 Label known_ok, halt;
2118 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2119 if (UseCompressedClassPointers) {
2120 // Tmp holds the default type. It currently comes uncompressed after the
2121 // load of a constant, so encode it.
2122 __ encode_klass_not_null(tmp);
2123 // Load the raw value of the dst klass, since we will be comparing
2124 // uncompressed values directly.
2125 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2126 __ cmpw(CCR0, tmp, tmp2);
2127 if (basic_type != T_OBJECT) {
2128 __ bne(CCR0, halt);
2129 // Load the raw value of the src klass.
2130 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src);
2131 __ cmpw(CCR0, tmp, tmp2);
2132 __ beq(CCR0, known_ok);
2133 } else {
2134 __ beq(CCR0, known_ok);
2135 __ cmpw(CCR0, src, dst);
2136 __ beq(CCR0, known_ok);
2137 }
2138 } else {
2139 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2140 __ cmpd(CCR0, tmp, tmp2);
2141 if (basic_type != T_OBJECT) {
2142 __ bne(CCR0, halt);
2143 // Load the raw value of the src klass.
2144 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src);
2145 __ cmpd(CCR0, tmp, tmp2);
2146 __ beq(CCR0, known_ok);
2147 } else {
2148 __ beq(CCR0, known_ok);
2149 __ cmpd(CCR0, src, dst);
2150 __ beq(CCR0, known_ok);
2151 }
2152 }
2153 __ bind(halt);
2154 __ stop("incorrect type information in arraycopy");
2155 __ bind(known_ok);
2156 }
2157 #endif
2158
2159 #ifndef PRODUCT
2160 if (PrintC1Statistics) {
2161 address counter = Runtime1::arraycopy_count_address(basic_type);
2162 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2163 __ lwz(R11_scratch1, simm16_offs, tmp);
2164 __ addi(R11_scratch1, R11_scratch1, 1);
2165 __ stw(R11_scratch1, simm16_offs, tmp);
2166 }
2167 #endif
2168
2169 Register src_ptr = R3_ARG1;
2170 Register dst_ptr = R4_ARG2;
2171 Register len = R5_ARG3;
2172
2173 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2174 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2175 if (shift == 0) {
2176 __ add(src_ptr, src_pos, src_ptr);
2177 __ add(dst_ptr, dst_pos, dst_ptr);
2178 } else {
2179 __ sldi(tmp, src_pos, shift);
2180 __ sldi(tmp2, dst_pos, shift);
2181 __ add(src_ptr, tmp, src_ptr);
2182 __ add(dst_ptr, tmp2, dst_ptr);
2183 }
2184
2185 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2186 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2187 const char *name;
2188 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2189
2190 // Arraycopy stubs takes a length in number of elements, so don't scale it.
2191 __ mr(len, length);
2192 __ call_c_with_frame_resize(entry, /*stub does not need resized frame*/ 0);
2193
2194 __ bind(*stub->continuation());
2195 }
2196
2197
2198 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2199 if (dest->is_single_cpu()) {
2200 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2201 #ifdef _LP64
2202 if (left->type() == T_OBJECT) {
2203 switch (code) {
2204 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2205 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2206 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2207 default: ShouldNotReachHere();
2208 }
2209 } else
2210 #endif
2211 switch (code) {
2212 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2213 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2214 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2215 default: ShouldNotReachHere();
2216 }
2217 } else {
2218 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2219 switch (code) {
2220 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2221 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2222 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2223 default: ShouldNotReachHere();
2224 }
2225 }
2226 }
2227
2228
2229 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2230 #ifdef _LP64
2231 if (left->type() == T_OBJECT) {
2232 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2233 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2234 else {
2235 switch (code) {
2236 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2237 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2238 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2239 default: ShouldNotReachHere();
2240 }
2241 }
2242 return;
2243 }
2244 #endif
2245
2246 if (dest->is_single_cpu()) {
2247 count = count & 0x1F; // Java spec
2248 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2249 else {
2250 switch (code) {
2251 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2252 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break;
2253 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2254 default: ShouldNotReachHere();
2255 }
2256 }
2257 } else if (dest->is_double_cpu()) {
2258 count = count & 63; // Java spec
2259 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2260 else {
2261 switch (code) {
2262 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2263 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2264 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2265 default: ShouldNotReachHere();
2266 }
2267 }
2268 } else {
2269 ShouldNotReachHere();
2270 }
2271 }
2272
2273
2274 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2275 if (op->init_check()) {
2276 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2277 explicit_null_check(op->klass()->as_register(), op->stub()->info());
2278 } else {
2279 add_debug_info_for_null_check_here(op->stub()->info());
2280 }
2281 __ lbz(op->tmp1()->as_register(),
2282 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2283 __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2284 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry());
2285 }
2286 __ allocate_object(op->obj()->as_register(),
2287 op->tmp1()->as_register(),
2288 op->tmp2()->as_register(),
2289 op->tmp3()->as_register(),
2290 op->header_size(),
2291 op->object_size(),
2292 op->klass()->as_register(),
2293 *op->stub()->entry());
2294
2295 __ bind(*op->stub()->continuation());
2296 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2297 }
2298
2299
2300 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2301 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2302 if (UseSlowPath ||
2303 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2304 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2305 __ b(*op->stub()->entry());
2306 } else {
2307 __ allocate_array(op->obj()->as_register(),
2308 op->len()->as_register(),
2309 op->tmp1()->as_register(),
2310 op->tmp2()->as_register(),
2311 op->tmp3()->as_register(),
2312 arrayOopDesc::header_size(op->type()),
2313 type2aelembytes(op->type()),
2314 op->klass()->as_register(),
2315 *op->stub()->entry());
2316 }
2317 __ bind(*op->stub()->continuation());
2318 }
2319
2320
2321 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2322 ciMethodData *md, ciProfileData *data,
2323 Register recv, Register tmp1, Label* update_done) {
2324 uint i;
2325 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2326 Label next_test;
2327 // See if the receiver is receiver[n].
2328 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2329 __ verify_klass_ptr(tmp1);
2330 __ cmpd(CCR0, recv, tmp1);
2331 __ bne(CCR0, next_test);
2332
2333 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2334 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2335 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2336 __ b(*update_done);
2337
2338 __ bind(next_test);
2339 }
2340
2341 // Didn't find receiver; find next empty slot and fill it in.
2342 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2343 Label next_test;
2344 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2345 __ cmpdi(CCR0, tmp1, 0);
2346 __ bne(CCR0, next_test);
2347 __ li(tmp1, DataLayout::counter_increment);
2348 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2349 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2350 __ b(*update_done);
2351
2352 __ bind(next_test);
2353 }
2354 }
2355
2356
2357 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2358 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2359 md = method->method_data_or_null();
2360 assert(md != NULL, "Sanity");
2361 data = md->bci_to_data(bci);
2362 assert(data != NULL, "need data for checkcast");
2363 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2364 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2365 // The offset is large so bias the mdo by the base of the slot so
2366 // that the ld can use simm16s to reference the slots of the data.
2367 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2368 }
2369 }
2370
2371
2372 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2373 const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2374 Register k_RInfo = op->tmp1()->as_register();
2375 Register klass_RInfo = op->tmp2()->as_register();
2376 Register Rtmp1 = op->tmp3()->as_register();
2377 Register dst = op->result_opr()->as_register();
2378 ciKlass* k = op->klass();
2379 bool should_profile = op->should_profile();
2380 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2381 bool reg_conflict = false;
2382 if (obj == k_RInfo) {
2383 k_RInfo = dst;
2384 reg_conflict = true;
2385 } else if (obj == klass_RInfo) {
2386 klass_RInfo = dst;
2387 reg_conflict = true;
2388 } else if (obj == Rtmp1) {
2389 Rtmp1 = dst;
2390 reg_conflict = true;
2391 }
2392 assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2393
2394 __ cmpdi(CCR0, obj, 0);
2395
2396 ciMethodData* md = NULL;
2397 ciProfileData* data = NULL;
2398 int mdo_offset_bias = 0;
2399 if (should_profile) {
2400 ciMethod* method = op->profiled_method();
2401 assert(method != NULL, "Should have method");
2402 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2403
2404 Register mdo = k_RInfo;
2405 Register data_val = Rtmp1;
2406 Label not_null;
2407 __ bne(CCR0, not_null);
2408 metadata2reg(md->constant_encoding(), mdo);
2409 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2410 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2411 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2412 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2413 __ b(*obj_is_null);
2414 __ bind(not_null);
2415 } else {
2416 __ beq(CCR0, *obj_is_null);
2417 }
2418
2419 // get object class
2420 __ load_klass(klass_RInfo, obj);
2421
2422 if (k->is_loaded()) {
2423 metadata2reg(k->constant_encoding(), k_RInfo);
2424 } else {
2425 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2426 }
2427
2428 Label profile_cast_failure, failure_restore_obj, profile_cast_success;
2429 Label *failure_target = should_profile ? &profile_cast_failure : failure;
2430 Label *success_target = should_profile ? &profile_cast_success : success;
2431
2432 if (op->fast_check()) {
2433 assert_different_registers(klass_RInfo, k_RInfo);
2434 __ cmpd(CCR0, k_RInfo, klass_RInfo);
2435 if (should_profile) {
2436 __ bne(CCR0, *failure_target);
2437 // Fall through to success case.
2438 } else {
2439 __ beq(CCR0, *success);
2440 // Fall through to failure case.
2441 }
2442 } else {
2443 bool need_slow_path = true;
2444 if (k->is_loaded()) {
2445 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2446 need_slow_path = false;
2447 }
2448 // Perform the fast part of the checking logic.
2449 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success_target : NULL),
2450 failure_target, NULL, RegisterOrConstant(k->super_check_offset()));
2451 } else {
2452 // Perform the fast part of the checking logic.
2453 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, failure_target);
2454 }
2455 if (!need_slow_path) {
2456 if (!should_profile) { __ b(*success); }
2457 } else {
2458 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2459 address entry = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2460 // Stub needs fixed registers (tmp1-3).
2461 Register original_k_RInfo = op->tmp1()->as_register();
2462 Register original_klass_RInfo = op->tmp2()->as_register();
2463 Register original_Rtmp1 = op->tmp3()->as_register();
2464 bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2465 bool keep_klass_RInfo_alive = (obj == original_klass_RInfo) && should_profile;
2466 if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2467 __ mr_if_needed(original_k_RInfo, k_RInfo);
2468 __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2469 if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2470 //__ load_const_optimized(original_Rtmp1, entry, R0);
2471 __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2472 __ mtctr(original_Rtmp1);
2473 __ bctrl(); // sets CR0
2474 if (keep_obj_alive) {
2475 if (keep_klass_RInfo_alive) { __ mr(R0, obj); }
2476 __ mr(obj, dst);
2477 }
2478 if (should_profile) {
2479 __ bne(CCR0, *failure_target);
2480 if (keep_klass_RInfo_alive) { __ mr(klass_RInfo, keep_obj_alive ? R0 : obj); }
2481 // Fall through to success case.
2482 } else {
2483 __ beq(CCR0, *success);
2484 // Fall through to failure case.
2485 }
2486 }
2487 }
2488
2489 if (should_profile) {
2490 Register mdo = k_RInfo, recv = klass_RInfo;
2491 assert_different_registers(mdo, recv, Rtmp1);
2492 __ bind(profile_cast_success);
2493 metadata2reg(md->constant_encoding(), mdo);
2494 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2495 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, success);
2496 __ b(*success);
2497
2498 // Cast failure case.
2499 __ bind(profile_cast_failure);
2500 metadata2reg(md->constant_encoding(), mdo);
2501 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2502 __ ld(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2503 __ addi(Rtmp1, Rtmp1, -DataLayout::counter_increment);
2504 __ std(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2505 }
2506
2507 __ bind(*failure);
2508 }
2509
2510
2511 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2512 LIR_Code code = op->code();
2513 if (code == lir_store_check) {
2514 Register value = op->object()->as_register();
2515 Register array = op->array()->as_register();
2516 Register k_RInfo = op->tmp1()->as_register();
2517 Register klass_RInfo = op->tmp2()->as_register();
2518 Register Rtmp1 = op->tmp3()->as_register();
2519 bool should_profile = op->should_profile();
2520
2521 __ verify_oop(value, FILE_AND_LINE);
2522 CodeStub* stub = op->stub();
2523 // Check if it needs to be profiled.
2524 ciMethodData* md = NULL;
2525 ciProfileData* data = NULL;
2526 int mdo_offset_bias = 0;
2527 if (should_profile) {
2528 ciMethod* method = op->profiled_method();
2529 assert(method != NULL, "Should have method");
2530 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2531 }
2532 Label profile_cast_success, failure, done;
2533 Label *success_target = should_profile ? &profile_cast_success : &done;
2534
2535 __ cmpdi(CCR0, value, 0);
2536 if (should_profile) {
2537 Label not_null;
2538 __ bne(CCR0, not_null);
2539 Register mdo = k_RInfo;
2540 Register data_val = Rtmp1;
2541 metadata2reg(md->constant_encoding(), mdo);
2542 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2543 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2544 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2545 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2546 __ b(done);
2547 __ bind(not_null);
2548 } else {
2549 __ beq(CCR0, done);
2550 }
2551 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2552 explicit_null_check(array, op->info_for_exception());
2553 } else {
2554 add_debug_info_for_null_check_here(op->info_for_exception());
2555 }
2556 __ load_klass(k_RInfo, array);
2557 __ load_klass(klass_RInfo, value);
2558
2559 // Get instance klass.
2560 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2561 // Perform the fast part of the checking logic.
2562 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, &failure, NULL);
2563
2564 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2565 const address slow_path = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2566 //__ load_const_optimized(R0, slow_path);
2567 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2568 __ mtctr(R0);
2569 __ bctrl(); // sets CR0
2570 if (!should_profile) {
2571 __ beq(CCR0, done);
2572 __ bind(failure);
2573 } else {
2574 __ bne(CCR0, failure);
2575 // Fall through to the success case.
2576
2577 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2578 assert_different_registers(value, mdo, recv, tmp1);
2579 __ bind(profile_cast_success);
2580 metadata2reg(md->constant_encoding(), mdo);
2581 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2582 __ load_klass(recv, value);
2583 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2584 __ b(done);
2585
2586 // Cast failure case.
2587 __ bind(failure);
2588 metadata2reg(md->constant_encoding(), mdo);
2589 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2590 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2591 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2592 __ addi(tmp1, tmp1, -DataLayout::counter_increment);
2593 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2594 }
2595 __ b(*stub->entry());
2596 __ bind(done);
2597
2598 } else if (code == lir_checkcast) {
2599 Label success, failure;
2600 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2601 __ b(*op->stub()->entry());
2602 __ align(32, 12);
2603 __ bind(success);
2604 __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2605 } else if (code == lir_instanceof) {
2606 Register dst = op->result_opr()->as_register();
2607 Label success, failure, done;
2608 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2609 __ li(dst, 0);
2610 __ b(done);
2611 __ align(32, 12);
2612 __ bind(success);
2613 __ li(dst, 1);
2614 __ bind(done);
2615 } else {
2616 ShouldNotReachHere();
2617 }
2618 }
2619
2620
2621 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2622 Register addr = op->addr()->as_pointer_register();
2623 Register cmp_value = noreg, new_value = noreg;
2624 bool is_64bit = false;
2625
2626 if (op->code() == lir_cas_long) {
2627 cmp_value = op->cmp_value()->as_register_lo();
2628 new_value = op->new_value()->as_register_lo();
2629 is_64bit = true;
2630 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2631 cmp_value = op->cmp_value()->as_register();
2632 new_value = op->new_value()->as_register();
2633 if (op->code() == lir_cas_obj) {
2634 if (UseCompressedOops) {
2635 Register t1 = op->tmp1()->as_register();
2636 Register t2 = op->tmp2()->as_register();
2637 cmp_value = __ encode_heap_oop(t1, cmp_value);
2638 new_value = __ encode_heap_oop(t2, new_value);
2639 } else {
2640 is_64bit = true;
2641 }
2642 }
2643 } else {
2644 Unimplemented();
2645 }
2646
2647 if (is_64bit) {
2648 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2649 MacroAssembler::MemBarNone,
2650 MacroAssembler::cmpxchgx_hint_atomic_update(),
2651 noreg, NULL, /*check without ldarx first*/true);
2652 } else {
2653 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2654 MacroAssembler::MemBarNone,
2655 MacroAssembler::cmpxchgx_hint_atomic_update(),
2656 noreg, /*check without ldarx first*/true);
2657 }
2658
2659 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2660 __ isync();
2661 } else {
2662 __ sync();
2663 }
2664 }
2665
2666 void LIR_Assembler::breakpoint() {
2667 __ illtrap();
2668 }
2669
2670
2671 void LIR_Assembler::push(LIR_Opr opr) {
2672 Unimplemented();
2673 }
2674
2675 void LIR_Assembler::pop(LIR_Opr opr) {
2676 Unimplemented();
2677 }
2678
2679
2680 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2681 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2682 Register dst = dst_opr->as_register();
2683 Register reg = mon_addr.base();
2684 int offset = mon_addr.disp();
2685 // Compute pointer to BasicLock.
2686 __ add_const_optimized(dst, reg, offset);
2687 }
2688
2689
2690 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2691 Register obj = op->obj_opr()->as_register();
2692 Register hdr = op->hdr_opr()->as_register();
2693 Register lock = op->lock_opr()->as_register();
2694
2695 // Obj may not be an oop.
2696 if (op->code() == lir_lock) {
2697 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2698 if (UseFastLocking) {
2699 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2700 // Add debug info for NullPointerException only if one is possible.
2701 if (op->info() != NULL) {
2702 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2703 explicit_null_check(obj, op->info());
2704 } else {
2705 add_debug_info_for_null_check_here(op->info());
2706 }
2707 }
2708 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2709 } else {
2710 // always do slow locking
2711 // note: The slow locking code could be inlined here, however if we use
2712 // slow locking, speed doesn't matter anyway and this solution is
2713 // simpler and requires less duplicated code - additionally, the
2714 // slow locking code is the same in either case which simplifies
2715 // debugging.
2716 __ b(*op->stub()->entry());
2717 }
2718 } else {
2719 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2720 if (UseFastLocking) {
2721 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2722 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2723 } else {
2724 // always do slow unlocking
2725 // note: The slow unlocking code could be inlined here, however if we use
2726 // slow unlocking, speed doesn't matter anyway and this solution is
2727 // simpler and requires less duplicated code - additionally, the
2728 // slow unlocking code is the same in either case which simplifies
2729 // debugging.
2730 __ b(*op->stub()->entry());
2731 }
2732 }
2733 __ bind(*op->stub()->continuation());
2734 }
2735
2736
2737 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2738 ciMethod* method = op->profiled_method();
2739 int bci = op->profiled_bci();
2740 ciMethod* callee = op->profiled_callee();
2741
2742 // Update counter for all call types.
2743 ciMethodData* md = method->method_data_or_null();
2744 assert(md != NULL, "Sanity");
2745 ciProfileData* data = md->bci_to_data(bci);
2746 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2747 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2748 Register mdo = op->mdo()->as_register();
2749 #ifdef _LP64
2750 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2751 Register tmp1 = op->tmp1()->as_register_lo();
2752 #else
2753 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2754 Register tmp1 = op->tmp1()->as_register();
2755 #endif
2756 metadata2reg(md->constant_encoding(), mdo);
2757 int mdo_offset_bias = 0;
2758 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2759 data->size_in_bytes())) {
2760 // The offset is large so bias the mdo by the base of the slot so
2761 // that the ld can use simm16s to reference the slots of the data.
2762 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2763 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2764 }
2765
2766 // Perform additional virtual call profiling for invokevirtual and
2767 // invokeinterface bytecodes
2768 if (op->should_profile_receiver_type()) {
2769 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2770 Register recv = op->recv()->as_register();
2771 assert_different_registers(mdo, tmp1, recv);
2772 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2773 ciKlass* known_klass = op->known_holder();
2774 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2775 // We know the type that will be seen at this call site; we can
2776 // statically update the MethodData* rather than needing to do
2777 // dynamic tests on the receiver type.
2778
2779 // NOTE: we should probably put a lock around this search to
2780 // avoid collisions by concurrent compilations.
2781 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2782 uint i;
2783 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2784 ciKlass* receiver = vc_data->receiver(i);
2785 if (known_klass->equals(receiver)) {
2786 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2787 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2788 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2789 return;
2790 }
2791 }
2792
2793 // Receiver type not found in profile data; select an empty slot.
2794
2795 // Note that this is less efficient than it should be because it
2796 // always does a write to the receiver part of the
2797 // VirtualCallData rather than just the first time.
2798 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2799 ciKlass* receiver = vc_data->receiver(i);
2800 if (receiver == NULL) {
2801 metadata2reg(known_klass->constant_encoding(), tmp1);
2802 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2803
2804 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2805 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2806 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2807 return;
2808 }
2809 }
2810 } else {
2811 __ load_klass(recv, recv);
2812 Label update_done;
2813 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2814 // Receiver did not match any saved receiver and there is no empty row for it.
2815 // Increment total counter to indicate polymorphic case.
2816 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2817 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2818 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2819
2820 __ bind(update_done);
2821 }
2822 } else {
2823 // Static call
2824 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2825 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2826 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2827 }
2828 }
2829
2830
2831 void LIR_Assembler::align_backward_branch_target() {
2832 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2833 }
2834
2835
2836 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2837 Unimplemented();
2838 }
2839
2840
2841 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2842 // tmp must be unused
2843 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2844 assert(left->is_register(), "can only handle registers");
2845
2846 if (left->is_single_cpu()) {
2847 __ neg(dest->as_register(), left->as_register());
2848 } else if (left->is_single_fpu()) {
2849 __ fneg(dest->as_float_reg(), left->as_float_reg());
2850 } else if (left->is_double_fpu()) {
2851 __ fneg(dest->as_double_reg(), left->as_double_reg());
2852 } else {
2853 assert (left->is_double_cpu(), "Must be a long");
2854 __ neg(dest->as_register_lo(), left->as_register_lo());
2855 }
2856 }
2857
2858
2859 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2860 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2861 // Stubs: Called via rt_call, but dest is a stub address (no function descriptor).
2862 if (dest == Runtime1::entry_for(Runtime1::register_finalizer_id) ||
2863 dest == Runtime1::entry_for(Runtime1::new_multi_array_id )) {
2864 //__ load_const_optimized(R0, dest);
2865 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2866 __ mtctr(R0);
2867 __ bctrl();
2868 assert(info != NULL, "sanity");
2869 add_call_info_here(info);
2870 return;
2871 }
2872
2873 __ call_c_with_frame_resize(dest, /*no resizing*/ 0);
2874 if (info != NULL) {
2875 add_call_info_here(info);
2876 }
2877 }
2878
2879
2880 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2881 ShouldNotReachHere(); // Not needed on _LP64.
2882 }
2883
2884 void LIR_Assembler::membar() {
2885 __ fence();
2886 }
2887
2888 void LIR_Assembler::membar_acquire() {
2889 __ acquire();
2890 }
2891
2892 void LIR_Assembler::membar_release() {
2893 __ release();
2894 }
2895
2896 void LIR_Assembler::membar_loadload() {
2897 __ membar(Assembler::LoadLoad);
2898 }
2899
2900 void LIR_Assembler::membar_storestore() {
2901 __ membar(Assembler::StoreStore);
2902 }
2903
2904 void LIR_Assembler::membar_loadstore() {
2905 __ membar(Assembler::LoadStore);
2906 }
2907
2908 void LIR_Assembler::membar_storeload() {
2909 __ membar(Assembler::StoreLoad);
2910 }
2911
2912 void LIR_Assembler::on_spin_wait() {
2913 Unimplemented();
2914 }
2915
2916 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2917 LIR_Address* addr = addr_opr->as_address_ptr();
2918 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2919
2920 if (addr->index()->is_illegal()) {
2921 if (patch_code != lir_patch_none) {
2922 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2923 __ load_const32(R0, 0); // patchable int
2924 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0);
2925 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2926 } else {
2927 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2928 }
2929 } else {
2930 assert(patch_code == lir_patch_none, "Patch code not supported");
2931 assert(addr->disp() == 0, "can't have both: index and disp");
2932 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2933 }
2934 }
2935
2936
2937 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2938 ShouldNotReachHere();
2939 }
2940
2941
2942 #ifdef ASSERT
2943 // Emit run-time assertion.
2944 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2945 Unimplemented();
2946 }
2947 #endif
2948
2949
2950 void LIR_Assembler::peephole(LIR_List* lir) {
2951 // Optimize instruction pairs before emitting.
2952 LIR_OpList* inst = lir->instructions_list();
2953 for (int i = 1; i < inst->length(); i++) {
2954 LIR_Op* op = inst->at(i);
2955
2956 // 2 register-register-moves
2957 if (op->code() == lir_move) {
2958 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(),
2959 res2 = ((LIR_Op1*)op)->result_opr();
2960 if (in2->is_register() && res2->is_register()) {
2961 LIR_Op* prev = inst->at(i - 1);
2962 if (prev && prev->code() == lir_move) {
2963 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(),
2964 res1 = ((LIR_Op1*)prev)->result_opr();
2965 if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2966 inst->remove_at(i);
2967 }
2968 }
2969 }
2970 }
2971
2972 }
2973 return;
2974 }
2975
2976
2977 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2978 const LIR_Address *addr = src->as_address_ptr();
2979 assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
2980 const Register Rptr = addr->base()->as_pointer_register(),
2981 Rtmp = tmp->as_register();
2982 Register Rco = noreg;
2983 if (UseCompressedOops && data->is_oop()) {
2984 Rco = __ encode_heap_oop(Rtmp, data->as_register());
2985 }
2986
2987 Label Lretry;
2988 __ bind(Lretry);
2989
2990 if (data->type() == T_INT) {
2991 const Register Rold = dest->as_register(),
2992 Rsrc = data->as_register();
2993 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2994 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2995 if (code == lir_xadd) {
2996 __ add(Rtmp, Rsrc, Rold);
2997 __ stwcx_(Rtmp, Rptr);
2998 } else {
2999 __ stwcx_(Rsrc, Rptr);
3000 }
3001 } else if (data->is_oop()) {
3002 assert(code == lir_xchg, "xadd for oops");
3003 const Register Rold = dest->as_register();
3004 if (UseCompressedOops) {
3005 assert_different_registers(Rptr, Rold, Rco);
3006 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3007 __ stwcx_(Rco, Rptr);
3008 } else {
3009 const Register Robj = data->as_register();
3010 assert_different_registers(Rptr, Rold, Robj);
3011 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3012 __ stdcx_(Robj, Rptr);
3013 }
3014 } else if (data->type() == T_LONG) {
3015 const Register Rold = dest->as_register_lo(),
3016 Rsrc = data->as_register_lo();
3017 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3018 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3019 if (code == lir_xadd) {
3020 __ add(Rtmp, Rsrc, Rold);
3021 __ stdcx_(Rtmp, Rptr);
3022 } else {
3023 __ stdcx_(Rsrc, Rptr);
3024 }
3025 } else {
3026 ShouldNotReachHere();
3027 }
3028
3029 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3030 __ bne_predict_not_taken(CCR0, Lretry);
3031 } else {
3032 __ bne( CCR0, Lretry);
3033 }
3034
3035 if (UseCompressedOops && data->is_oop()) {
3036 __ decode_heap_oop(dest->as_register());
3037 }
3038 }
3039
3040
3041 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3042 Register obj = op->obj()->as_register();
3043 Register tmp = op->tmp()->as_pointer_register();
3044 LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
3045 ciKlass* exact_klass = op->exact_klass();
3046 intptr_t current_klass = op->current_klass();
3047 bool not_null = op->not_null();
3048 bool no_conflict = op->no_conflict();
3049
3050 Label Lupdate, Ldo_update, Ldone;
3051
3052 bool do_null = !not_null;
3053 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3054 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3055
3056 assert(do_null || do_update, "why are we here?");
3057 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3058
3059 __ verify_oop(obj, FILE_AND_LINE);
3060
3061 if (do_null) {
3062 if (!TypeEntries::was_null_seen(current_klass)) {
3063 __ cmpdi(CCR0, obj, 0);
3064 __ bne(CCR0, Lupdate);
3065 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3066 __ ori(R0, R0, TypeEntries::null_seen);
3067 if (do_update) {
3068 __ b(Ldo_update);
3069 } else {
3070 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3071 }
3072 } else {
3073 if (do_update) {
3074 __ cmpdi(CCR0, obj, 0);
3075 __ beq(CCR0, Ldone);
3076 }
3077 }
3078 #ifdef ASSERT
3079 } else {
3080 __ cmpdi(CCR0, obj, 0);
3081 __ bne(CCR0, Lupdate);
3082 __ stop("unexpect null obj");
3083 #endif
3084 }
3085
3086 __ bind(Lupdate);
3087 if (do_update) {
3088 Label Lnext;
3089 const Register klass = R29_TOC; // kill and reload
3090 bool klass_reg_used = false;
3091 #ifdef ASSERT
3092 if (exact_klass != NULL) {
3093 Label ok;
3094 klass_reg_used = true;
3095 __ load_klass(klass, obj);
3096 metadata2reg(exact_klass->constant_encoding(), R0);
3097 __ cmpd(CCR0, klass, R0);
3098 __ beq(CCR0, ok);
3099 __ stop("exact klass and actual klass differ");
3100 __ bind(ok);
3101 }
3102 #endif
3103
3104 if (!no_conflict) {
3105 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3106 klass_reg_used = true;
3107 if (exact_klass != NULL) {
3108 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3109 metadata2reg(exact_klass->constant_encoding(), klass);
3110 } else {
3111 __ load_klass(klass, obj);
3112 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3113 }
3114
3115 // Like InterpreterMacroAssembler::profile_obj_type
3116 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3117 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3118 __ cmpd(CCR1, R0, klass);
3119 // Klass seen before, nothing to do (regardless of unknown bit).
3120 //beq(CCR1, do_nothing);
3121
3122 __ andi_(R0, klass, TypeEntries::type_unknown);
3123 // Already unknown. Nothing to do anymore.
3124 //bne(CCR0, do_nothing);
3125 __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3126 __ beq(CCR0, Lnext);
3127
3128 if (TypeEntries::is_type_none(current_klass)) {
3129 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3130 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3131 __ beq(CCR0, Ldo_update); // First time here. Set profile type.
3132 }
3133
3134 } else {
3135 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3136 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3137
3138 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3139 __ andi_(R0, tmp, TypeEntries::type_unknown);
3140 // Already unknown. Nothing to do anymore.
3141 __ bne(CCR0, Lnext);
3142 }
3143
3144 // Different than before. Cannot keep accurate profile.
3145 __ ori(R0, tmp, TypeEntries::type_unknown);
3146 } else {
3147 // There's a single possible klass at this profile point
3148 assert(exact_klass != NULL, "should be");
3149 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3150
3151 if (TypeEntries::is_type_none(current_klass)) {
3152 klass_reg_used = true;
3153 metadata2reg(exact_klass->constant_encoding(), klass);
3154
3155 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3156 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3157 __ cmpd(CCR1, R0, klass);
3158 // Klass seen before, nothing to do (regardless of unknown bit).
3159 __ beq(CCR1, Lnext);
3160 #ifdef ASSERT
3161 {
3162 Label ok;
3163 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3164 __ beq(CCR0, ok); // First time here.
3165
3166 __ stop("unexpected profiling mismatch");
3167 __ bind(ok);
3168 }
3169 #endif
3170 // First time here. Set profile type.
3171 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3172 } else {
3173 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3174 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3175
3176 // Already unknown. Nothing to do anymore.
3177 __ andi_(R0, tmp, TypeEntries::type_unknown);
3178 __ bne(CCR0, Lnext);
3179
3180 // Different than before. Cannot keep accurate profile.
3181 __ ori(R0, tmp, TypeEntries::type_unknown);
3182 }
3183 }
3184
3185 __ bind(Ldo_update);
3186 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3187
3188 __ bind(Lnext);
3189 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3190 }
3191 __ bind(Ldone);
3192 }
3193
3194
3195 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3196 assert(op->crc()->is_single_cpu(), "crc must be register");
3197 assert(op->val()->is_single_cpu(), "byte value must be register");
3198 assert(op->result_opr()->is_single_cpu(), "result must be register");
3199 Register crc = op->crc()->as_register();
3200 Register val = op->val()->as_register();
3201 Register res = op->result_opr()->as_register();
3202
3203 assert_different_registers(val, crc, res);
3204
3205 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3206 __ kernel_crc32_singleByteReg(crc, val, res, true);
3207 __ mr(res, crc);
3208 }
3209
3210 #undef __